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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/MIMX8MD7_cm4.h47688
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/MIMX8MD7_cm4_features.h388
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/drivers/driver_reset.cmake14
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/drivers/fsl_clock.c967
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/drivers/fsl_clock.h1349
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/drivers/fsl_iomuxc.h606
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/fsl_device_registers.h38
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/MIMX8MD7xxxHZ_cm4_ddr_ram.ld226
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/MIMX8MD7xxxHZ_cm4_ram.ld225
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/MIMX8MD7xxxJZ_cm4_ddr_ram.ld226
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/MIMX8MD7xxxJZ_cm4_ram.ld225
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/startup_MIMX8MD7_cm4.S754
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/mcuxpresso/startup_MIMX8MD7_cm4.c822
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/mcuxpresso/startup_MIMX8MD7_cm4.cpp821
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/board.c179
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/board.h46
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/clock_config.c145
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/clock_config.h27
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/peripherals.c23
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/peripherals.h23
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/pin_mux.c57
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/pin_mux.h54
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/system_MIMX8MD7_cm4.c269
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/system_MIMX8MD7_cm4.h119
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/template/RTE_Device.h48
25 files changed, 55339 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/MIMX8MD7_cm4.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/MIMX8MD7_cm4.h
new file mode 100644
index 000000000..82976abeb
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/MIMX8MD7_cm4.h
@@ -0,0 +1,47688 @@
1/*
2** ###################################################################
3** Processors: MIMX8MD7CVAHZ
4** MIMX8MD7DVAJZ
5**
6** Compilers: Keil ARM C/C++ Compiler
7** GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9**
10** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018
11** Version: rev. 4.0, 2018-01-26
12** Build: b180903
13**
14** Abstract:
15** CMSIS Peripheral Access Layer for MIMX8MD7_cm4
16**
17** Copyright 1997-2016 Freescale Semiconductor, Inc.
18** Copyright 2016-2018 NXP
19** All rights reserved.
20**
21** SPDX-License-Identifier: BSD-3-Clause
22**
23** http: www.nxp.com
24** mail: [email protected]
25**
26** Revisions:
27** - rev. 1.0 (2017-01-10)
28** Initial version.
29** - rev. 2.0 (2017-04-27)
30** Rev.B Header EAR1
31** - rev. 3.0 (2017-07-19)
32** Rev.C Header EAR2
33** - rev. 4.0 (2018-01-26)
34** Rev.D Header RFP
35**
36** ###################################################################
37*/
38
39/*!
40 * @file MIMX8MD7_cm4.h
41 * @version 4.0
42 * @date 2018-01-26
43 * @brief CMSIS Peripheral Access Layer for MIMX8MD7_cm4
44 *
45 * CMSIS Peripheral Access Layer for MIMX8MD7_cm4
46 */
47
48#ifndef _MIMX8MD7_CM4_H_
49#define _MIMX8MD7_CM4_H_ /**< Symbol preventing repeated inclusion */
50
51/** Memory map major version (memory maps with equal major version number are
52 * compatible) */
53#define MCU_MEM_MAP_VERSION 0x0400U
54/** Memory map minor version */
55#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
56
57
58/* ----------------------------------------------------------------------------
59 -- Interrupt vector numbers
60 ---------------------------------------------------------------------------- */
61
62/*!
63 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
64 * @{
65 */
66
67/** Interrupt Number Definitions */
68#define NUMBER_OF_INT_VECTORS 144 /**< Number of interrupts in the Vector table */
69
70typedef enum IRQn {
71 /* Auxiliary constants */
72 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
73
74 /* Core interrupts */
75 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
76 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
77 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
78 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
79 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
80 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
81 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
82 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
83 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
84
85 /* Device specific interrupts */
86 GPR_IRQ_IRQn = 0, /**< GPR Interrupt. Used to notify cores on exception condition while boot. */
87 DAP_IRQn = 1, /**< DAP Interrupt */
88 SDMA1_IRQn = 2, /**< AND of all 48 SDMA interrupts (events) from all the channels */
89 GPU_IRQn = 3, /**< GPU Interrupt */
90 SNVS_IRQn = 4, /**< ON-OFF button press shorter than 5 seconds (pulse event) */
91 LCDIF_IRQn = 5, /**< LCDIF Sync Interrupt */
92 SPDIF1_IRQn = 6, /**< SPDIF1 Interrupt */
93 H264_IRQn = 7, /**< h264 Decoder Interrupt */
94 VPUDMA_IRQn = 8, /**< VPU DMA Interrupt */
95 QOS_IRQn = 9, /**< QOS interrupt */
96 WDOG3_IRQn = 10, /**< Watchdog Timer reset */
97 HS_CP1_IRQn = 11, /**< HS Interrupt Request */
98 APBHDMA_IRQn = 12, /**< GPMI operation channel 0-3 description complete interrupt */
99 SPDIF2_IRQn = 13, /**< SPDIF2 Interrupt */
100 BCH_IRQn = 14, /**< BCH operation complete interrupt */
101 GPMI_IRQn = 15, /**< GPMI operation TIMEOUT ERROR interrupt */
102 HDMI_IRQ0_IRQn = 16, /**< HDMI Interrupt 0 */
103 HDMI_IRQ1_IRQn = 17, /**< HDMI Interrupt 1 */
104 HDMI_IRQ2_IRQn = 18, /**< HDMI Interrupt 2 */
105 SNVS_Consolidated_IRQn = 19, /**< SRTC Consolidated Interrupt. Non TZ. */
106 SNVS_Security_IRQn = 20, /**< SRTC Security Interrupt. TZ. */
107 CSU_IRQn = 21, /**< CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted. */
108 USDHC1_IRQn = 22, /**< uSDHC1 Enhanced SDHC Interrupt Request */
109 USDHC2_IRQn = 23, /**< uSDHC2 Enhanced SDHC Interrupt Request */
110 DDC_IRQn = 24, /**< DC8000 Display Controller IRQ */
111 DTRC_IRQn = 25, /**< DTRC interrupt */
112 UART1_IRQn = 26, /**< UART-1 ORed interrupt */
113 UART2_IRQn = 27, /**< UART-2 ORed interrupt */
114 UART3_IRQn = 28, /**< UART-3 ORed interrupt */
115 UART4_IRQn = 29, /**< UART-4 ORed interrupt */
116 VP9_IRQn = 30, /**< VP9 Decoder interrupt */
117 ECSPI1_IRQn = 31, /**< ECSPI1 interrupt request line to the core. */
118 ECSPI2_IRQn = 32, /**< ECSPI2 interrupt request line to the core. */
119 ECSPI3_IRQn = 33, /**< ECSPI3 interrupt request line to the core. */
120 MIPI_DSI_IRQn = 34, /**< DSI Interrupt */
121 I2C1_IRQn = 35, /**< I2C-1 Interrupt */
122 I2C2_IRQn = 36, /**< I2C-2 Interrupt */
123 I2C3_IRQn = 37, /**< I2C-3 Interrupt */
124 I2C4_IRQn = 38, /**< I2C-4 Interrupt */
125 RDC_IRQn = 39, /**< RDC interrupt */
126 USB1_IRQn = 40, /**< USB1 Interrupt */
127 USB2_IRQn = 41, /**< USB1 Interrupt */
128 CSI1_IRQn = 42, /**< CSI1 interrupt */
129 CSI2_IRQn = 43, /**< CSI2 interrupt */
130 MIPI_CSI1_IRQn = 44, /**< MIPI-CSI-1 Interrupt */
131 MIPI_CSI2_IRQn = 45, /**< MIPI-CSI-2 Interrupt */
132 GPT6_IRQn = 46, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
133 SCTR_IRQ0_IRQn = 47, /**< ISO7816IP Interrupt 0 */
134 SCTR_IRQ1_IRQn = 48, /**< ISO7816IP Interrupt 1 */
135 TEMPMON_IRQn = 49, /**< TempSensor (Temperature alarm). */
136 I2S3_IRQn = 50, /**< SAI3 Receive / Transmit Interrupt */
137 GPT5_IRQn = 51, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
138 GPT4_IRQn = 52, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
139 GPT3_IRQn = 53, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
140 GPT2_IRQn = 54, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
141 GPT1_IRQn = 55, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
142 GPIO1_INT7_IRQn = 56, /**< Active HIGH Interrupt from INT7 from GPIO */
143 GPIO1_INT6_IRQn = 57, /**< Active HIGH Interrupt from INT6 from GPIO */
144 GPIO1_INT5_IRQn = 58, /**< Active HIGH Interrupt from INT5 from GPIO */
145 GPIO1_INT4_IRQn = 59, /**< Active HIGH Interrupt from INT4 from GPIO */
146 GPIO1_INT3_IRQn = 60, /**< Active HIGH Interrupt from INT3 from GPIO */
147 GPIO1_INT2_IRQn = 61, /**< Active HIGH Interrupt from INT2 from GPIO */
148 GPIO1_INT1_IRQn = 62, /**< Active HIGH Interrupt from INT1 from GPIO */
149 GPIO1_INT0_IRQn = 63, /**< Active HIGH Interrupt from INT0 from GPIO */
150 GPIO1_Combined_0_15_IRQn = 64, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
151 GPIO1_Combined_16_31_IRQn = 65, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
152 GPIO2_Combined_0_15_IRQn = 66, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
153 GPIO2_Combined_16_31_IRQn = 67, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
154 GPIO3_Combined_0_15_IRQn = 68, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
155 GPIO3_Combined_16_31_IRQn = 69, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
156 GPIO4_Combined_0_15_IRQn = 70, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */
157 GPIO4_Combined_16_31_IRQn = 71, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */
158 GPIO5_Combined_0_15_IRQn = 72, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
159 GPIO5_Combined_16_31_IRQn = 73, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
160 PCIE_CTRL2_IRQ0_IRQn = 74, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
161 PCIE_CTRL2_IRQ1_IRQn = 75, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
162 PCIE_CTRL2_IRQ2_IRQn = 76, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
163 PCIE_CTRL2_IRQ3_IRQn = 77, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
164 WDOG1_IRQn = 78, /**< Watchdog Timer reset */
165 WDOG2_IRQn = 79, /**< Watchdog Timer reset */
166 PCIE_CTRL2_IRQn = 80, /**< Channels [63:32] interrupts requests */
167 PWM1_IRQn = 81, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
168 PWM2_IRQn = 82, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
169 PWM3_IRQn = 83, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
170 PWM4_IRQn = 84, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
171 CCM_IRQ1_IRQn = 85, /**< CCM, Interrupt Request 1 */
172 CCM_IRQ2_IRQn = 86, /**< CCM, Interrupt Request 2 */
173 GPC_IRQn = 87, /**< GPC Interrupt Request 1 */
174 MU_A53_IRQn = 88, /**< Interrupt to A53 */
175 SRC_IRQn = 89, /**< SRC interrupt request */
176 I2S56_IRQn = 90, /**< SAI5/6 Receive / Transmit Interrupt */
177 RTIC_IRQn = 91, /**< RTIC Interrupt */
178 CPU_PerformanceUnit_IRQn = 92, /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n] */
179 CPU_CTI_Trigger_IRQn = 93, /**< CTI trigger outputs (internal: nCTIIRQ[n] */
180 SRC_Combined_IRQn = 94, /**< Combined CPU wdog interrupts (4x) out of SRC. */
181 I2S1_IRQn = 95, /**< SAI1 Receive / Transmit Interrupt */
182 I2S2_IRQn = 96, /**< SAI2 Receive / Transmit Interrupt */
183 MU_M4_IRQn = 97, /**< Interrupt to M4 */
184 DDR_PerformanceMonitor_IRQn = 98, /**< ddr Interrupt for performance monitor */
185 DDR_IRQn = 99, /**< ddr Interrupt */
186 I2S4_IRQn = 100, /**< SAI4 Receive / Transmit Interrupt */
187 CPU_Error_AXI_IRQn = 101, /**< CPU Error indicator for AXI transaction with a write response error condition */
188 CPU_Error_L2RAM_IRQn = 102, /**< CPU Error indicator for L2 RAM double-bit ECC error */
189 SDMA2_IRQn = 103, /**< AND of all 48 SDMA interrupts (events) from all the channels */
190 Reserved120_IRQn = 104, /**< Reserved */
191 CAAM_IRQ0_IRQn = 105, /**< CAAM interrupt queue for JQ */
192 CAAM_IRQ1_IRQn = 106, /**< CAAM interrupt queue for JQ */
193 QSPI_IRQn = 107, /**< QSPI Interrupt */
194 TZASC_IRQn = 108, /**< TZASC (PL380) interrupt */
195 Reserved125_IRQn = 109, /**< Reserved */
196 Reserved126_IRQn = 110, /**< Reserved */
197 Reserved127_IRQn = 111, /**< Reserved */
198 PERFMON1_IRQn = 112, /**< General Interrupt */
199 PERFMON2_IRQn = 113, /**< General Interrupt */
200 CAAM_IRQ2_IRQn = 114, /**< CAAM interrupt queue for JQ */
201 CAAM_ERROR_IRQn = 115, /**< Recoverable error interrupt */
202 HS_CP0_IRQn = 116, /**< HS Interrupt Request */
203 HEVC_IRQn = 117, /**< HEVC interrupt */
204 ENET_MAC0_Rx_Tx_Done1_IRQn = 118, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */
205 ENET_MAC0_Rx_Tx_Done2_IRQn = 119, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */
206 ENET_IRQn = 120, /**< MAC 0 IRQ */
207 ENET_1588_IRQn = 121, /**< MAC 0 1588 Timer Interrupt - synchronous */
208 PCIE_CTRL1_IRQ0_IRQn = 122, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
209 PCIE_CTRL1_IRQ1_IRQn = 123, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
210 PCIE_CTRL1_IRQ2_IRQn = 124, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
211 PCIE_CTRL1_IRQ3_IRQn = 125, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
212 Reserved142_IRQn = 126, /**< Reserved */
213 PCIE_CTRL1_IRQn = 127 /**< Channels [63:32] interrupts requests */
214} IRQn_Type;
215
216/*!
217 * @}
218 */ /* end of group Interrupt_vector_numbers */
219
220
221/* ----------------------------------------------------------------------------
222 -- Cortex M4 Core Configuration
223 ---------------------------------------------------------------------------- */
224
225/*!
226 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
227 * @{
228 */
229
230#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
231#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
232#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
233#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
234
235#include "core_cm4.h" /* Core Peripheral Access Layer */
236#include "system_MIMX8MD7_cm4.h" /* Device specific configuration file */
237
238/*!
239 * @}
240 */ /* end of group Cortex_Core_Configuration */
241
242
243/* ----------------------------------------------------------------------------
244 -- Mapping Information
245 ---------------------------------------------------------------------------- */
246
247/*!
248 * @addtogroup Mapping_Information Mapping Information
249 * @{
250 */
251
252/** Mapping Information */
253/*!
254 * @addtogroup iomuxc_pads
255 * @{ */
256
257/*******************************************************************************
258 * Definitions
259*******************************************************************************/
260
261/*!
262 * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
263 *
264 * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
265 */
266typedef enum _iomuxc_sw_mux_ctl_pad
267{
268 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
269 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
270 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
271 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
272 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
273 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
274 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
275 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
276 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
277 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
278 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
279 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
280 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
281 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
282 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
283 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
284 kIOMUXC_SW_MUX_CTL_PAD_ENET_MDC = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */
285 kIOMUXC_SW_MUX_CTL_PAD_ENET_MDIO = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */
286 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD3 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */
287 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD2 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */
288 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD1 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */
289 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD0 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */
290 kIOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */
291 kIOMUXC_SW_MUX_CTL_PAD_ENET_TXC = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */
292 kIOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */
293 kIOMUXC_SW_MUX_CTL_PAD_ENET_RXC = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */
294 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD0 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */
295 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD1 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */
296 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD2 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */
297 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD3 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */
298 kIOMUXC_SW_MUX_CTL_PAD_SD1_CLK = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */
299 kIOMUXC_SW_MUX_CTL_PAD_SD1_CMD = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */
300 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */
301 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */
302 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */
303 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */
304 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA4 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */
305 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA5 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */
306 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA6 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */
307 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA7 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */
308 kIOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */
309 kIOMUXC_SW_MUX_CTL_PAD_SD1_STROBE = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */
310 kIOMUXC_SW_MUX_CTL_PAD_SD2_CD_B = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */
311 kIOMUXC_SW_MUX_CTL_PAD_SD2_CLK = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */
312 kIOMUXC_SW_MUX_CTL_PAD_SD2_CMD = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */
313 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */
314 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */
315 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */
316 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */
317 kIOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */
318 kIOMUXC_SW_MUX_CTL_PAD_SD2_WP = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */
319 kIOMUXC_SW_MUX_CTL_PAD_NAND_ALE = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */
320 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */
321 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */
322 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */
323 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */
324 kIOMUXC_SW_MUX_CTL_PAD_NAND_CLE = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */
325 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */
326 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */
327 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */
328 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */
329 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */
330 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */
331 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */
332 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */
333 kIOMUXC_SW_MUX_CTL_PAD_NAND_DQS = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */
334 kIOMUXC_SW_MUX_CTL_PAD_NAND_RE_B = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */
335 kIOMUXC_SW_MUX_CTL_PAD_NAND_READY_B = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */
336 kIOMUXC_SW_MUX_CTL_PAD_NAND_WE_B = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */
337 kIOMUXC_SW_MUX_CTL_PAD_NAND_WP_B = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */
338 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */
339 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXC = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */
340 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */
341 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */
342 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */
343 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */
344 kIOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */
345 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXFS = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */
346 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXC = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */
347 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD0 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */
348 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD1 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */
349 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD2 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */
350 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD3 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */
351 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD4 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */
352 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD5 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */
353 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD6 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */
354 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD7 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */
355 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXFS = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */
356 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXC = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */
357 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD0 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */
358 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD1 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */
359 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD2 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */
360 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD3 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */
361 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD4 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */
362 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD5 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */
363 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD6 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */
364 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD7 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */
365 kIOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */
366 kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */
367 kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXC = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */
368 kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */
369 kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */
370 kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXC = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */
371 kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */
372 kIOMUXC_SW_MUX_CTL_PAD_SAI2_MCLK = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */
373 kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */
374 kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXC = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */
375 kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXD = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */
376 kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */
377 kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXC = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */
378 kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXD = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */
379 kIOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */
380 kIOMUXC_SW_MUX_CTL_PAD_SPDIF_TX = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */
381 kIOMUXC_SW_MUX_CTL_PAD_SPDIF_RX = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */
382 kIOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */
383 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */
384 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */
385 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */
386 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */
387 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */
388 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */
389 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */
390 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */
391 kIOMUXC_SW_MUX_CTL_PAD_I2C1_SCL = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */
392 kIOMUXC_SW_MUX_CTL_PAD_I2C1_SDA = 124U, /**< IOMUXC SW_MUX_CTL_PAD index */
393 kIOMUXC_SW_MUX_CTL_PAD_I2C2_SCL = 125U, /**< IOMUXC SW_MUX_CTL_PAD index */
394 kIOMUXC_SW_MUX_CTL_PAD_I2C2_SDA = 126U, /**< IOMUXC SW_MUX_CTL_PAD index */
395 kIOMUXC_SW_MUX_CTL_PAD_I2C3_SCL = 127U, /**< IOMUXC SW_MUX_CTL_PAD index */
396 kIOMUXC_SW_MUX_CTL_PAD_I2C3_SDA = 128U, /**< IOMUXC SW_MUX_CTL_PAD index */
397 kIOMUXC_SW_MUX_CTL_PAD_I2C4_SCL = 129U, /**< IOMUXC SW_MUX_CTL_PAD index */
398 kIOMUXC_SW_MUX_CTL_PAD_I2C4_SDA = 130U, /**< IOMUXC SW_MUX_CTL_PAD index */
399 kIOMUXC_SW_MUX_CTL_PAD_UART1_RXD = 131U, /**< IOMUXC SW_MUX_CTL_PAD index */
400 kIOMUXC_SW_MUX_CTL_PAD_UART1_TXD = 132U, /**< IOMUXC SW_MUX_CTL_PAD index */
401 kIOMUXC_SW_MUX_CTL_PAD_UART2_RXD = 133U, /**< IOMUXC SW_MUX_CTL_PAD index */
402 kIOMUXC_SW_MUX_CTL_PAD_UART2_TXD = 134U, /**< IOMUXC SW_MUX_CTL_PAD index */
403 kIOMUXC_SW_MUX_CTL_PAD_UART3_RXD = 135U, /**< IOMUXC SW_MUX_CTL_PAD index */
404 kIOMUXC_SW_MUX_CTL_PAD_UART3_TXD = 136U, /**< IOMUXC SW_MUX_CTL_PAD index */
405 kIOMUXC_SW_MUX_CTL_PAD_UART4_RXD = 137U, /**< IOMUXC SW_MUX_CTL_PAD index */
406 kIOMUXC_SW_MUX_CTL_PAD_UART4_TXD = 138U, /**< IOMUXC SW_MUX_CTL_PAD index */
407} iomuxc_sw_mux_ctl_pad_t;
408
409/*!
410 * @addtogroup iomuxc_pads
411 * @{ */
412
413/*******************************************************************************
414 * Definitions
415*******************************************************************************/
416
417/*!
418 * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
419 *
420 * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
421 */
422typedef enum _iomuxc_sw_pad_ctl_pad
423{
424 kIOMUXC_SW_PAD_CTL_PAD_TEST_MODE = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
425 kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
426 kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
427 kIOMUXC_SW_PAD_CTL_PAD_JTAG_MOD = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
428 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
429 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDI = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
430 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TMS = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */
431 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TCK = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */
432 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDO = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */
433 kIOMUXC_SW_PAD_CTL_PAD_RTC = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */
434 kIOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */
435 kIOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */
436 kIOMUXC_SW_PAD_CTL_PAD_ONOFF = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */
437 kIOMUXC_SW_PAD_CTL_PAD_POR_B = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */
438 kIOMUXC_SW_PAD_CTL_PAD_RTC_RESET_B = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */
439 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
440 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */
441 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */
442 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */
443 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */
444 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */
445 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */
446 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */
447 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */
448 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */
449 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */
450 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */
451 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */
452 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */
453 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */
454 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */
455 kIOMUXC_SW_PAD_CTL_PAD_ENET_MDC = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */
456 kIOMUXC_SW_PAD_CTL_PAD_ENET_MDIO = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */
457 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD3 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */
458 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD2 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */
459 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD1 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */
460 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD0 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */
461 kIOMUXC_SW_PAD_CTL_PAD_ENET_TX_CTL = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */
462 kIOMUXC_SW_PAD_CTL_PAD_ENET_TXC = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */
463 kIOMUXC_SW_PAD_CTL_PAD_ENET_RX_CTL = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */
464 kIOMUXC_SW_PAD_CTL_PAD_ENET_RXC = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */
465 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD0 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */
466 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD1 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */
467 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD2 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */
468 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD3 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */
469 kIOMUXC_SW_PAD_CTL_PAD_SD1_CLK = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */
470 kIOMUXC_SW_PAD_CTL_PAD_SD1_CMD = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */
471 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */
472 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */
473 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */
474 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */
475 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA4 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */
476 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA5 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */
477 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA6 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */
478 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA7 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */
479 kIOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */
480 kIOMUXC_SW_PAD_CTL_PAD_SD1_STROBE = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */
481 kIOMUXC_SW_PAD_CTL_PAD_SD2_CD_B = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */
482 kIOMUXC_SW_PAD_CTL_PAD_SD2_CLK = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */
483 kIOMUXC_SW_PAD_CTL_PAD_SD2_CMD = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */
484 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */
485 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */
486 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */
487 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */
488 kIOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */
489 kIOMUXC_SW_PAD_CTL_PAD_SD2_WP = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */
490 kIOMUXC_SW_PAD_CTL_PAD_NAND_ALE = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */
491 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */
492 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */
493 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE2_B = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */
494 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE3_B = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */
495 kIOMUXC_SW_PAD_CTL_PAD_NAND_CLE = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */
496 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */
497 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */
498 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */
499 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */
500 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */
501 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */
502 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */
503 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */
504 kIOMUXC_SW_PAD_CTL_PAD_NAND_DQS = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */
505 kIOMUXC_SW_PAD_CTL_PAD_NAND_RE_B = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */
506 kIOMUXC_SW_PAD_CTL_PAD_NAND_READY_B = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */
507 kIOMUXC_SW_PAD_CTL_PAD_NAND_WE_B = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */
508 kIOMUXC_SW_PAD_CTL_PAD_NAND_WP_B = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */
509 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXFS = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */
510 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXC = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */
511 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD0 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */
512 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD1 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */
513 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD2 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */
514 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD3 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */
515 kIOMUXC_SW_PAD_CTL_PAD_SAI5_MCLK = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */
516 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXFS = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */
517 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXC = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */
518 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD0 = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */
519 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD1 = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */
520 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD2 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */
521 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD3 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */
522 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD4 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */
523 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD5 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */
524 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD6 = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */
525 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD7 = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */
526 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXFS = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */
527 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXC = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */
528 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD0 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */
529 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD1 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */
530 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD2 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */
531 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD3 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */
532 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD4 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */
533 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD5 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */
534 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD6 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */
535 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD7 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */
536 kIOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK = 112U, /**< IOMUXC SW_PAD_CTL_PAD index */
537 kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXFS = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */
538 kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXC = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */
539 kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXD0 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */
540 kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXFS = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */
541 kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXC = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */
542 kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXD0 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */
543 kIOMUXC_SW_PAD_CTL_PAD_SAI2_MCLK = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */
544 kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXFS = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */
545 kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXC = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */
546 kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXD = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */
547 kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXFS = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */
548 kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXC = 124U, /**< IOMUXC SW_PAD_CTL_PAD index */
549 kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXD = 125U, /**< IOMUXC SW_PAD_CTL_PAD index */
550 kIOMUXC_SW_PAD_CTL_PAD_SAI3_MCLK = 126U, /**< IOMUXC SW_PAD_CTL_PAD index */
551 kIOMUXC_SW_PAD_CTL_PAD_SPDIF_TX = 127U, /**< IOMUXC SW_PAD_CTL_PAD index */
552 kIOMUXC_SW_PAD_CTL_PAD_SPDIF_RX = 128U, /**< IOMUXC SW_PAD_CTL_PAD index */
553 kIOMUXC_SW_PAD_CTL_PAD_SPDIF_EXT_CLK = 129U, /**< IOMUXC SW_PAD_CTL_PAD index */
554 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK = 130U, /**< IOMUXC SW_PAD_CTL_PAD index */
555 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI = 131U, /**< IOMUXC SW_PAD_CTL_PAD index */
556 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO = 132U, /**< IOMUXC SW_PAD_CTL_PAD index */
557 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0 = 133U, /**< IOMUXC SW_PAD_CTL_PAD index */
558 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK = 134U, /**< IOMUXC SW_PAD_CTL_PAD index */
559 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI = 135U, /**< IOMUXC SW_PAD_CTL_PAD index */
560 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO = 136U, /**< IOMUXC SW_PAD_CTL_PAD index */
561 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0 = 137U, /**< IOMUXC SW_PAD_CTL_PAD index */
562 kIOMUXC_SW_PAD_CTL_PAD_I2C1_SCL = 138U, /**< IOMUXC SW_PAD_CTL_PAD index */
563 kIOMUXC_SW_PAD_CTL_PAD_I2C1_SDA = 139U, /**< IOMUXC SW_PAD_CTL_PAD index */
564 kIOMUXC_SW_PAD_CTL_PAD_I2C2_SCL = 140U, /**< IOMUXC SW_PAD_CTL_PAD index */
565 kIOMUXC_SW_PAD_CTL_PAD_I2C2_SDA = 141U, /**< IOMUXC SW_PAD_CTL_PAD index */
566 kIOMUXC_SW_PAD_CTL_PAD_I2C3_SCL = 142U, /**< IOMUXC SW_PAD_CTL_PAD index */
567 kIOMUXC_SW_PAD_CTL_PAD_I2C3_SDA = 143U, /**< IOMUXC SW_PAD_CTL_PAD index */
568 kIOMUXC_SW_PAD_CTL_PAD_I2C4_SCL = 144U, /**< IOMUXC SW_PAD_CTL_PAD index */
569 kIOMUXC_SW_PAD_CTL_PAD_I2C4_SDA = 145U, /**< IOMUXC SW_PAD_CTL_PAD index */
570 kIOMUXC_SW_PAD_CTL_PAD_UART1_RXD = 146U, /**< IOMUXC SW_PAD_CTL_PAD index */
571 kIOMUXC_SW_PAD_CTL_PAD_UART1_TXD = 147U, /**< IOMUXC SW_PAD_CTL_PAD index */
572 kIOMUXC_SW_PAD_CTL_PAD_UART2_RXD = 148U, /**< IOMUXC SW_PAD_CTL_PAD index */
573 kIOMUXC_SW_PAD_CTL_PAD_UART2_TXD = 149U, /**< IOMUXC SW_PAD_CTL_PAD index */
574 kIOMUXC_SW_PAD_CTL_PAD_UART3_RXD = 150U, /**< IOMUXC SW_PAD_CTL_PAD index */
575 kIOMUXC_SW_PAD_CTL_PAD_UART3_TXD = 151U, /**< IOMUXC SW_PAD_CTL_PAD index */
576 kIOMUXC_SW_PAD_CTL_PAD_UART4_RXD = 152U, /**< IOMUXC SW_PAD_CTL_PAD index */
577 kIOMUXC_SW_PAD_CTL_PAD_UART4_TXD = 153U, /**< IOMUXC SW_PAD_CTL_PAD index */
578} iomuxc_sw_pad_ctl_pad_t;
579
580/* @} */
581
582/*!
583 * @brief Enumeration for the IOMUXC select input
584 *
585 * Defines the enumeration for the IOMUXC select input collections.
586 */
587typedef enum _iomuxc_select_input
588{
589 kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 0U, /**< IOMUXC select input index */
590 kIOMUXC_ENET1_MDIO_SELECT_INPUT = 1U, /**< IOMUXC select input index */
591 kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 2U, /**< IOMUXC select input index */
592 kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 3U, /**< IOMUXC select input index */
593 kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 4U, /**< IOMUXC select input index */
594 kIOMUXC_SAI5_RX_BCLK_SELECT_INPUT = 5U, /**< IOMUXC select input index */
595 kIOMUXC_SAI5_RXD0_SELECT_INPUT = 6U, /**< IOMUXC select input index */
596 kIOMUXC_SAI5_RXD1_SELECT_INPUT = 7U, /**< IOMUXC select input index */
597 kIOMUXC_SAI5_RXD2_SELECT_INPUT = 8U, /**< IOMUXC select input index */
598 kIOMUXC_SAI5_RXD3_SELECT_INPUT = 9U, /**< IOMUXC select input index */
599 kIOMUXC_SAI5_RX_SYNC_SELECT_INPUT = 10U, /**< IOMUXC select input index */
600 kIOMUXC_SAI5_TX_BCLK_SELECT_INPUT = 11U, /**< IOMUXC select input index */
601 kIOMUXC_SAI5_TX_SYNC_SELECT_INPUT = 12U, /**< IOMUXC select input index */
602 kIOMUXC_UART1_RTS_B_SELECT_INPUT = 13U, /**< IOMUXC select input index */
603 kIOMUXC_UART1_RXD_SELECT_INPUT = 14U, /**< IOMUXC select input index */
604 kIOMUXC_UART2_RTS_B_SELECT_INPUT = 15U, /**< IOMUXC select input index */
605 kIOMUXC_UART2_RXD_SELECT_INPUT = 16U, /**< IOMUXC select input index */
606 kIOMUXC_UART3_RTS_B_SELECT_INPUT = 17U, /**< IOMUXC select input index */
607 kIOMUXC_UART3_RXD_SELECT_INPUT = 18U, /**< IOMUXC select input index */
608 kIOMUXC_UART4_RTS_B_SELECT_INPUT = 19U, /**< IOMUXC select input index */
609 kIOMUXC_UART4_RXD_SELECT_INPUT = 20U, /**< IOMUXC select input index */
610 kIOMUXC_SAI6_RX_BCLK_SELECT_INPUT = 21U, /**< IOMUXC select input index */
611 kIOMUXC_SAI6_RXD0_SELECT_INPUT = 22U, /**< IOMUXC select input index */
612 kIOMUXC_SAI6_RX_SYNC_SELECT_INPUT = 23U, /**< IOMUXC select input index */
613 kIOMUXC_SAI6_TX_BCLK_SELECT_INPUT = 24U, /**< IOMUXC select input index */
614 kIOMUXC_SAI6_TX_SYNC_SELECT_INPUT = 25U, /**< IOMUXC select input index */
615 kIOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT = 26U, /**< IOMUXC select input index */
616 kIOMUXC_PCIE2_CLKREQ_B_SELECT_INPUT = 27U, /**< IOMUXC select input index */
617 kIOMUXC_SAI5_MCLK_SELECT_INPUT = 28U, /**< IOMUXC select input index */
618 kIOMUXC_SAI6_MCLK_SELECT_INPUT = 29U, /**< IOMUXC select input index */
619} iomuxc_select_input_t;
620
621/*!
622 * @addtogroup rdc_mapping
623 * @{
624 */
625
626/*******************************************************************************
627 * Definitions
628 ******************************************************************************/
629
630/*!
631 * @brief Structure for the RDC mapping
632 *
633 * Defines the structure for the RDC resource collections.
634 */
635
636typedef enum _rdc_master
637{
638 kRDC_Master_A53 = 0U, /**< ARM Cortex-A53 RDC Master */
639 kRDC_Master_M4 = 1U, /**< ARM Cortex-M4 RDC Master */
640 kRDC_Master_PCIE1 = 2U, /**< PCIE1 RDC Master */
641 kRDC_Master_PCIE2 = 3U, /**< PCIE2 RDC Master */
642 kRDC_Master_VPU = 4U, /**< VPU RDC Master */
643 kRDC_Master_LCDIF = 5U, /**< LCDIF RDC Master */
644 kRDC_Master_CSI1 = 6U, /**< CSI1 PORT RDC Master */
645 kRDC_Master_CSI2 = 7U, /**< CSI2 RDC Master */
646 kRDC_Master_Coresight = 8U, /**< CORESIGHT RDC Master */
647 kRDC_Master_DAP = 9U, /**< DAP RDC Master */
648 kRDC_Master_CAAM = 10U, /**< CAAM RDC Master */
649 kRDC_Master_SDMA1_PERIPH = 11U, /**< SDMA1 PERIPHERAL RDC Master */
650 kRDC_Master_SDMA1_BURST = 12U, /**< SDMA1 BURST RDC Master */
651 kRDC_Master_APBHDMA = 13U, /**< APBH DMA RDC Master */
652 kRDC_Master_RAWNAND = 14U, /**< RAW NAND RDC Master */
653 kRDC_Master_USDHC1 = 15U, /**< USDHC1 RDC Master */
654 kRDC_Master_USDHC2 = 16U, /**< USDHC2 RDC Master */
655 kRDC_Master_DP = 17U, /**< DP RDC Master */
656 kRDC_Master_GPU = 18U, /**< GPU RDC Master */
657 kRDC_Master_USB1 = 19U, /**< USB1 RDC Master */
658 kRDC_Master_USB2 = 20U, /**< USB2 RDC Master */
659 kRDC_Master_TESTPORT = 21U, /**< TESTPORT RDC Master */
660 kRDC_Master_ENET1TX = 22U, /**< ENET1 TX RDC Master */
661 kRDC_Master_ENET1RX = 23U, /**< ENET1 RX RDC Master */
662 kRDC_Master_SDMA2_PERIPH = 24U, /**< SDMA2 PERIPH RDC Master */
663 kRDC_Master_SDMA2_BURST = 24U, /**< SDMA2 BURST RDC Master */
664 kRDC_Master_SDMA2_SPDA2 = 24U, /**< SDMA2 to SPDA2 RDC Master */
665 kRDC_Master_SDMA1_SPBA1 = 26U, /**< SDMA1 to SPBA1 RDC Master */
666} rdc_master_t;
667
668typedef enum _rdc_mem
669{
670 kRDC_Mem_MRC0_0 = 0U, /**< MMDC/DRAM. Region resolution 4KB. */
671 kRDC_Mem_MRC0_1 = 1U,
672 kRDC_Mem_MRC0_2 = 2U,
673 kRDC_Mem_MRC0_3 = 3U,
674 kRDC_Mem_MRC0_4 = 4U,
675 kRDC_Mem_MRC0_5 = 5U,
676 kRDC_Mem_MRC0_6 = 6U,
677 kRDC_Mem_MRC0_7 = 7U,
678 kRDC_Mem_MRC1_0 = 8U, /**< PCIE2. Region resolution 4KB. */
679 kRDC_Mem_MRC1_1 = 9U,
680 kRDC_Mem_MRC1_2 = 10U,
681 kRDC_Mem_MRC1_3 = 11U,
682 kRDC_Mem_MRC2_0 = 12U, /**< QSPI. Region resolution 4KB. */
683 kRDC_Mem_MRC2_1 = 13U,
684 kRDC_Mem_MRC2_2 = 14U,
685 kRDC_Mem_MRC2_3 = 15U,
686 kRDC_Mem_MRC2_4 = 16U,
687 kRDC_Mem_MRC2_5 = 17U,
688 kRDC_Mem_MRC2_6 = 18U,
689 kRDC_Mem_MRC2_7 = 19U,
690 kRDC_Mem_MRC3_0 = 20U, /**< PCIE1. Region resolution 4KB. */
691 kRDC_Mem_MRC3_1 = 21U,
692 kRDC_Mem_MRC3_2 = 22U,
693 kRDC_Mem_MRC3_3 = 23U,
694 kRDC_Mem_MRC4_0 = 24U, /**< OCRAM. Region resolution 128B. */
695 kRDC_Mem_MRC4_1 = 25U,
696 kRDC_Mem_MRC4_2 = 26U,
697 kRDC_Mem_MRC4_3 = 27U,
698 kRDC_Mem_MRC4_4 = 28U,
699 kRDC_Mem_MRC5_0 = 29U, /**< OCRAM_S. Region resolution 128B. */
700 kRDC_Mem_MRC5_1 = 30U,
701 kRDC_Mem_MRC5_2 = 31U,
702 kRDC_Mem_MRC5_3 = 32U,
703 kRDC_Mem_MRC5_4 = 33U,
704 kRDC_Mem_MRC6_0 = 34U, /**< TCM. Region resolution 128B. */
705 kRDC_Mem_MRC6_1 = 35U,
706 kRDC_Mem_MRC6_2 = 36U,
707 kRDC_Mem_MRC6_3 = 37U,
708 kRDC_Mem_MRC6_4 = 38U,
709 kRDC_Mem_MRC7_0 = 39U, /**< GIC. Region resolution 4KB. */
710 kRDC_Mem_MRC7_1 = 40U,
711 kRDC_Mem_MRC7_2 = 41U,
712 kRDC_Mem_MRC7_3 = 42U,
713 kRDC_Mem_MRC8_0 = 43U, /**< USBMIX. Region resolution 4KB. */
714 kRDC_Mem_MRC8_1 = 44U,
715 kRDC_Mem_MRC8_2 = 45U,
716 kRDC_Mem_MRC8_3 = 46U,
717 kRDC_Mem_MRC9_0 = 47U, /**< GPU. Region resolution 4KB. */
718 kRDC_Mem_MRC9_1 = 48U,
719 kRDC_Mem_MRC9_2 = 49U,
720 kRDC_Mem_MRC9_3 = 50U,
721 kRDC_Mem_MRC10_0 = 51U, /**< VPU(Decoder). Region resolution 4KB. */
722 kRDC_Mem_MRC10_1 = 52U,
723 kRDC_Mem_MRC10_2 = 53U,
724 kRDC_Mem_MRC10_3 = 54U,
725 kRDC_Mem_MRC11_0 = 55U, /**< DEBUG(DAP). Region resolution 4KB. */
726 kRDC_Mem_MRC11_1 = 56U,
727 kRDC_Mem_MRC11_2 = 57U,
728 kRDC_Mem_MRC11_3 = 58U,
729 kRDC_Mem_MRC12_0 = 59U, /**< DDRC(REG). Region resolution 4KB. */
730 kRDC_Mem_MRC12_1 = 60U,
731 kRDC_Mem_MRC12_2 = 61U,
732 kRDC_Mem_MRC12_3 = 62U,
733 kRDC_Mem_MRC12_4 = 63U,
734} rdc_mem_t;
735
736typedef enum _rdc_periph
737{
738 kRDC_Periph_GPIO1 = 0U, /**< GPIO1 RDC Peripheral */
739 kRDC_Periph_GPIO2 = 1U, /**< GPIO2 RDC Peripheral */
740 kRDC_Periph_GPIO3 = 2U, /**< GPIO3 RDC Peripheral */
741 kRDC_Periph_GPIO4 = 3U, /**< GPIO4 RDC Peripheral */
742 kRDC_Periph_GPIO5 = 4U, /**< GPIO5 RDC Peripheral */
743 kRDC_Periph_ANA_TSENSOR = 6U, /**< ANA_TSENSOR RDC Peripheral */
744 kRDC_Periph_ANA_OSC = 7U, /**< ANA_OSC RDC Peripheral */
745 kRDC_Periph_WDOG1 = 8U, /**< WDOG1 RDC Peripheral */
746 kRDC_Periph_WDOG2 = 9U, /**< WDOG2 RDC Peripheral */
747 kRDC_Periph_WDOG3 = 10U, /**< WDOG3 RDC Peripheral */
748 kRDC_Periph_SDMA2 = 12U, /**< SDMA2 RDC Peripheral */
749 kRDC_Periph_GPT1 = 13U, /**< GPT1 RDC Peripheral */
750 kRDC_Periph_GPT2 = 14U, /**< GPT2 RDC Peripheral */
751 kRDC_Periph_GPT3 = 15U, /**< GPT3 RDC Peripheral */
752 kRDC_Periph_ROMCP = 17U, /**< ROMCP RDC Peripheral */
753 kRDC_Periph_LCDIF = 18U, /**< LCDIF RDC Peripheral */
754 kRDC_Periph_IOMUXC = 19U, /**< IOMUXC RDC Peripheral */
755 kRDC_Periph_IOMUXC_GPR = 20U, /**< IOMUXC_GPR RDC Peripheral */
756 kRDC_Periph_OCOTP_CTRL = 21U, /**< OCOTP_CTRL RDC Peripheral */
757 kRDC_Periph_ANA_PLL = 22U, /**< ANA_PLL RDC Peripheral */
758 kRDC_Periph_SNVS_HP = 23U, /**< SNVS_HP GPR RDC Peripheral */
759 kRDC_Periph_CCM = 24U, /**< CCM RDC Peripheral */
760 kRDC_Periph_SRC = 25U, /**< SRC RDC Peripheral */
761 kRDC_Periph_GPC = 26U, /**< GPC RDC Peripheral */
762 kRDC_Periph_SEMAPHORE1 = 27U, /**< SEMAPHORE1 RDC Peripheral */
763 kRDC_Periph_SEMAPHORE2 = 28U, /**< SEMAPHORE2 RDC Peripheral */
764 kRDC_Periph_RDC = 29U, /**< RDC RDC Peripheral */
765 kRDC_Periph_CSU = 30U, /**< CSU RDC Peripheral */
766 kRDC_Periph_DC_MST0 = 32U, /**< DC_MST0 RDC Peripheral */
767 kRDC_Periph_DC_MST1 = 33U, /**< DC_MST1 RDC Peripheral */
768 kRDC_Periph_DC_MST2 = 34U, /**< DC_MST2 RDC Peripheral */
769 kRDC_Periph_DC_MST3 = 35U, /**< DC_MST3 RDC Peripheral */
770 kRDC_Periph_HDMI_SEC = 36U, /**< HDMI_SEC RDC Peripheral */
771 kRDC_Periph_PWM1 = 38U, /**< PWM1 RDC Peripheral */
772 kRDC_Periph_PWM2 = 39U, /**< PWM2 RDC Peripheral */
773 kRDC_Periph_PWM3 = 40U, /**< PWM3 RDC Peripheral */
774 kRDC_Periph_PWM4 = 41U, /**< PWM4 RDC Peripheral */
775 kRDC_Periph_SYS_COUNTER_RD = 42U, /**< System counter read RDC Peripheral */
776 kRDC_Periph_SYS_COUNTER_CMP = 43U, /**< System counter compare RDC Peripheral */
777 kRDC_Periph_SYS_COUNTER_CTRL = 44U, /**< System counter control RDC Peripheral */
778 kRDC_Periph_HDMI_CTRL = 45U, /**< HDMI_CTRL RDC Peripheral */
779 kRDC_Periph_GPT6 = 46U, /**< GPT6 RDC Peripheral */
780 kRDC_Periph_GPT5 = 47U, /**< GPT5 RDC Peripheral */
781 kRDC_Periph_GPT4 = 48U, /**< GPT4 RDC Peripheral */
782 kRDC_Periph_TZASC = 56U, /**< TZASC RDC Peripheral */
783 kRDC_Periph_MTR = 59U, /**< MTR RDC Peripheral */
784 kRDC_Periph_PERFMON1 = 60U, /**< PERFMON1 RDC Peripheral */
785 kRDC_Periph_PERFMON2 = 61U, /**< PERFMON2 RDC Peripheral */
786 kRDC_Periph_PLATFORM_CTRL = 62U, /**< PLATFORM_CTRL RDC Peripheral */
787 kRDC_Periph_QOSC = 63U, /**< QOSC RDC Peripheral */
788 kRDC_Periph_MIPI_PHY = 64U, /**< MIPI_PHY RDC Peripheral */
789 kRDC_Periph_MIPI_DSI = 65U, /**< MIPI_DSI RDC Peripheral */
790 kRDC_Periph_I2C1 = 66U, /**< I2C1 RDC Peripheral */
791 kRDC_Periph_I2C2 = 67U, /**< I2C2 RDC Peripheral */
792 kRDC_Periph_I2C3 = 68U, /**< I2C3 RDC Peripheral */
793 kRDC_Periph_I2C4 = 69U, /**< I2C4 RDC Peripheral */
794 kRDC_Periph_UART4 = 70U, /**< UART4 RDC Peripheral */
795 kRDC_Periph_MIPI_CSI1 = 71U, /**< MIPI_CSI1 RDC Peripheral */
796 kRDC_Periph_MIPI_CSI_PHY1 = 72U, /**< MIPI_CSI_PHY1 RDC Peripheral */
797 kRDC_Periph_CSI1 = 73U, /**< CSI1 RDC Peripheral */
798 kRDC_Periph_MU_A = 74U, /**< MU_A RDC Peripheral */
799 kRDC_Periph_MU_B = 75U, /**< MU_B RDC Peripheral */
800 kRDC_Periph_SEMAPHORE_HS = 76U, /**< SEMAPHORE_HS RDC Peripheral */
801 kRDC_Periph_SAI1 = 78U, /**< SAI1 RDC Peripheral */
802 kRDC_Periph_SAI6 = 80U, /**< SAI6 RDC Peripheral */
803 kRDC_Periph_SAI5 = 81U, /**< SAI5 RDC Peripheral */
804 kRDC_Periph_SAI4 = 82U, /**< SAI4 RDC Peripheral */
805 kRDC_Periph_USDHC1 = 84U, /**< USDHC1 RDC Peripheral */
806 kRDC_Periph_USDHC2 = 85U, /**< USDHC2 RDC Peripheral */
807 kRDC_Periph_MIPI_CSI2 = 86U, /**< MIPI_CSI2 RDC Peripheral */
808 kRDC_Periph_MIPI_CSI_PHY2 = 87U, /**< MIPI_CSI_PHY2 RDC Peripheral */
809 kRDC_Periph_CSI2 = 88U, /**< CSI2 RDC Peripheral */
810 kRDC_Periph_SPBA2 = 90U, /**< SPBA2 RDC Peripheral */
811 kRDC_Periph_QSPI = 91U, /**< QSPI RDC Peripheral */
812 kRDC_Periph_SDMA1 = 93U, /**< SDMA1 RDC Peripheral */
813 kRDC_Periph_ENET1 = 94U, /**< ENET1 RDC Peripheral */
814 kRDC_Periph_SPDIF1 = 97U, /**< SPDIF1 RDC Peripheral */
815 kRDC_Periph_ECSPI1 = 98U, /**< ECSPI1 RDC Peripheral */
816 kRDC_Periph_ECSPI2 = 99U, /**< ECSPI2 RDC Peripheral */
817 kRDC_Periph_ECSPI3 = 100U, /**< ECSPI3 RDC Peripheral */
818 kRDC_Periph_UART1 = 102U, /**< UART1 RDC Peripheral */
819 kRDC_Periph_UART3 = 104U, /**< UART3 RDC Peripheral */
820 kRDC_Periph_UART2 = 105U, /**< UART2 RDC Peripheral */
821 kRDC_Periph_SPDIF2 = 106U, /**< SPDIF2 RDC Peripheral */
822 kRDC_Periph_SAI2 = 107U, /**< SAI2 RDC Peripheral */
823 kRDC_Periph_SAI3 = 108U, /**< SAI3 RDC Peripheral */
824 kRDC_Periph_SPBA1 = 111U, /**< SPBA1 RDC Peripheral */
825 kRDC_Periph_CAAM = 114U, /**< CAAM RDC Peripheral */
826} rdc_periph_t;
827
828/* @} */
829
830
831/*!
832 * @}
833 */ /* end of group Mapping_Information */
834
835
836/* ----------------------------------------------------------------------------
837 -- Device Peripheral Access Layer
838 ---------------------------------------------------------------------------- */
839
840/*!
841 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
842 * @{
843 */
844
845
846/*
847** Start of section using anonymous unions
848*/
849
850#if defined(__ARMCC_VERSION)
851 #if (__ARMCC_VERSION >= 6010050)
852 #pragma clang diagnostic push
853 #else
854 #pragma push
855 #pragma anon_unions
856 #endif
857#elif defined(__GNUC__)
858 /* anonymous unions are enabled by default */
859#elif defined(__IAR_SYSTEMS_ICC__)
860 #pragma language=extended
861#else
862 #error Not supported compiler type
863#endif
864
865/* ----------------------------------------------------------------------------
866 -- AIPSTZ Peripheral Access Layer
867 ---------------------------------------------------------------------------- */
868
869/*!
870 * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
871 * @{
872 */
873
874/** AIPSTZ - Register Layout Typedef */
875typedef struct {
876 __IO uint32_t MPR; /**< MPR, offset: 0x0 */
877 uint8_t RESERVED_0[60];
878 __IO uint32_t OPACR; /**< OPACR, offset: 0x40 */
879 __IO uint32_t OPACR1; /**< OPACR1, offset: 0x44 */
880 __IO uint32_t OPACR2; /**< OPACR2, offset: 0x48 */
881 __IO uint32_t OPACR3; /**< OPACR3, offset: 0x4C */
882 __IO uint32_t OPACR4; /**< OPACR4, offset: 0x50 */
883} AIPSTZ_Type;
884
885/* ----------------------------------------------------------------------------
886 -- AIPSTZ Register Masks
887 ---------------------------------------------------------------------------- */
888
889/*!
890 * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
891 * @{
892 */
893
894/*! @name MPR - MPR */
895/*! @{ */
896#define AIPSTZ_MPR_MPROT5_MASK (0xF00U)
897#define AIPSTZ_MPR_MPROT5_SHIFT (8U)
898#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
899#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
900#define AIPSTZ_MPR_MPROT3_SHIFT (16U)
901#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
902#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
903#define AIPSTZ_MPR_MPROT2_SHIFT (20U)
904#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
905#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
906#define AIPSTZ_MPR_MPROT1_SHIFT (24U)
907#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
908#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
909#define AIPSTZ_MPR_MPROT0_SHIFT (28U)
910#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
911/*! @} */
912
913/*! @name OPACR - OPACR */
914/*! @{ */
915#define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
916#define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
917#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
918#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
919#define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
920#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
921#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
922#define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
923#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
924#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
925#define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
926#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
927#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
928#define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
929#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
930#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
931#define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
932#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
933#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
934#define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
935#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
936#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
937#define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
938#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
939/*! @} */
940
941/*! @name OPACR1 - OPACR1 */
942/*! @{ */
943#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
944#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
945#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
946#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
947#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
948#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
949#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
950#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
951#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
952#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
953#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
954#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
955#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
956#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
957#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
958#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
959#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
960#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
961#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
962#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
963#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
964#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
965#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
966#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
967/*! @} */
968
969/*! @name OPACR2 - OPACR2 */
970/*! @{ */
971#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
972#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
973#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
974#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
975#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
976#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
977#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
978#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
979#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
980#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
981#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
982#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
983#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
984#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
985#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
986#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
987#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
988#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
989#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
990#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
991#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
992#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
993#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
994#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
995/*! @} */
996
997/*! @name OPACR3 - OPACR3 */
998/*! @{ */
999#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
1000#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
1001#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
1002#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
1003#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
1004#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
1005#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
1006#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
1007#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
1008#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
1009#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
1010#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
1011#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
1012#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
1013#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
1014#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
1015#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
1016#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
1017#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
1018#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
1019#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
1020#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
1021#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
1022#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
1023/*! @} */
1024
1025/*! @name OPACR4 - OPACR4 */
1026/*! @{ */
1027#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
1028#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
1029#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
1030#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
1031#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
1032#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
1033/*! @} */
1034
1035
1036/*!
1037 * @}
1038 */ /* end of group AIPSTZ_Register_Masks */
1039
1040
1041/* AIPSTZ - Peripheral instance base addresses */
1042/** Peripheral AIPSTZ1 base address */
1043#define AIPSTZ1_BASE (0x301F0000u)
1044/** Peripheral AIPSTZ1 base pointer */
1045#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)
1046/** Peripheral AIPSTZ2 base address */
1047#define AIPSTZ2_BASE (0x305F0000u)
1048/** Peripheral AIPSTZ2 base pointer */
1049#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)
1050/** Peripheral AIPSTZ3 base address */
1051#define AIPSTZ3_BASE (0x309F0000u)
1052/** Peripheral AIPSTZ3 base pointer */
1053#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)
1054/** Peripheral AIPSTZ4 base address */
1055#define AIPSTZ4_BASE (0x32DF0000u)
1056/** Peripheral AIPSTZ4 base pointer */
1057#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)
1058/** Array initializer of AIPSTZ peripheral base addresses */
1059#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }
1060/** Array initializer of AIPSTZ peripheral base pointers */
1061#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }
1062
1063/*!
1064 * @}
1065 */ /* end of group AIPSTZ_Peripheral_Access_Layer */
1066
1067
1068/* ----------------------------------------------------------------------------
1069 -- APBH Peripheral Access Layer
1070 ---------------------------------------------------------------------------- */
1071
1072/*!
1073 * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer
1074 * @{
1075 */
1076
1077/** APBH - Register Layout Typedef */
1078typedef struct {
1079 __IO uint32_t CTRL0; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */
1080 __IO uint32_t CTRL0_SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */
1081 __IO uint32_t CTRL0_CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */
1082 __IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */
1083 __IO uint32_t CTRL1; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */
1084 __IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */
1085 __IO uint32_t CTRL1_CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */
1086 __IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */
1087 __IO uint32_t CTRL2; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */
1088 __IO uint32_t CTRL2_SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */
1089 __IO uint32_t CTRL2_CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */
1090 __IO uint32_t CTRL2_TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */
1091 __IO uint32_t CHANNEL_CTRL; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */
1092 __IO uint32_t CHANNEL_CTRL_SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */
1093 __IO uint32_t CHANNEL_CTRL_CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */
1094 __IO uint32_t CHANNEL_CTRL_TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */
1095 __I uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */
1096 uint8_t RESERVED_0[12];
1097 __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */
1098 uint8_t RESERVED_1[12];
1099 __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */
1100 uint8_t RESERVED_2[156];
1101 __I uint32_t CH0_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x100 */
1102 uint8_t RESERVED_3[12];
1103 __IO uint32_t CH0_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x110 */
1104 uint8_t RESERVED_4[12];
1105 __I uint32_t CH0_CMD; /**< APBH DMA Channel n Command Register, offset: 0x120 */
1106 uint8_t RESERVED_5[12];
1107 __I uint32_t CH0_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x130 */
1108 uint8_t RESERVED_6[12];
1109 __IO uint32_t CH0_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x140 */
1110 uint8_t RESERVED_7[12];
1111 __I uint32_t CH0_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x150 */
1112 uint8_t RESERVED_8[12];
1113 __I uint32_t CH0_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x160 */
1114 uint8_t RESERVED_9[12];
1115 __I uint32_t CH1_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x170 */
1116 uint8_t RESERVED_10[12];
1117 __IO uint32_t CH1_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x180 */
1118 uint8_t RESERVED_11[12];
1119 __I uint32_t CH1_CMD; /**< APBH DMA Channel n Command Register, offset: 0x190 */
1120 uint8_t RESERVED_12[12];
1121 __I uint32_t CH1_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x1A0 */
1122 uint8_t RESERVED_13[12];
1123 __IO uint32_t CH1_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x1B0 */
1124 uint8_t RESERVED_14[12];
1125 __I uint32_t CH1_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1C0 */
1126 uint8_t RESERVED_15[12];
1127 __I uint32_t CH1_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1D0 */
1128 uint8_t RESERVED_16[12];
1129 __I uint32_t CH2_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x1E0 */
1130 uint8_t RESERVED_17[12];
1131 __IO uint32_t CH2_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x1F0 */
1132 uint8_t RESERVED_18[12];
1133 __I uint32_t CH2_CMD; /**< APBH DMA Channel n Command Register, offset: 0x200 */
1134 uint8_t RESERVED_19[12];
1135 __I uint32_t CH2_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x210 */
1136 uint8_t RESERVED_20[12];
1137 __IO uint32_t CH2_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x220 */
1138 uint8_t RESERVED_21[12];
1139 __I uint32_t CH2_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x230 */
1140 uint8_t RESERVED_22[12];
1141 __I uint32_t CH2_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x240 */
1142 uint8_t RESERVED_23[12];
1143 __I uint32_t CH3_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x250 */
1144 uint8_t RESERVED_24[12];
1145 __IO uint32_t CH3_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x260 */
1146 uint8_t RESERVED_25[12];
1147 __I uint32_t CH3_CMD; /**< APBH DMA Channel n Command Register, offset: 0x270 */
1148 uint8_t RESERVED_26[12];
1149 __I uint32_t CH3_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x280 */
1150 uint8_t RESERVED_27[12];
1151 __IO uint32_t CH3_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x290 */
1152 uint8_t RESERVED_28[12];
1153 __I uint32_t CH3_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2A0 */
1154 uint8_t RESERVED_29[12];
1155 __I uint32_t CH3_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2B0 */
1156 uint8_t RESERVED_30[12];
1157 __I uint32_t CH4_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x2C0 */
1158 uint8_t RESERVED_31[12];
1159 __IO uint32_t CH4_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x2D0 */
1160 uint8_t RESERVED_32[12];
1161 __I uint32_t CH4_CMD; /**< APBH DMA Channel n Command Register, offset: 0x2E0 */
1162 uint8_t RESERVED_33[12];
1163 __I uint32_t CH4_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x2F0 */
1164 uint8_t RESERVED_34[12];
1165 __IO uint32_t CH4_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x300 */
1166 uint8_t RESERVED_35[12];
1167 __I uint32_t CH4_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x310 */
1168 uint8_t RESERVED_36[12];
1169 __I uint32_t CH4_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x320 */
1170 uint8_t RESERVED_37[12];
1171 __I uint32_t CH5_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x330 */
1172 uint8_t RESERVED_38[12];
1173 __IO uint32_t CH5_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x340 */
1174 uint8_t RESERVED_39[12];
1175 __I uint32_t CH5_CMD; /**< APBH DMA Channel n Command Register, offset: 0x350 */
1176 uint8_t RESERVED_40[12];
1177 __I uint32_t CH5_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x360 */
1178 uint8_t RESERVED_41[12];
1179 __IO uint32_t CH5_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x370 */
1180 uint8_t RESERVED_42[12];
1181 __I uint32_t CH5_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x380 */
1182 uint8_t RESERVED_43[12];
1183 __I uint32_t CH5_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x390 */
1184 uint8_t RESERVED_44[12];
1185 __I uint32_t CH6_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x3A0 */
1186 uint8_t RESERVED_45[12];
1187 __IO uint32_t CH6_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x3B0 */
1188 uint8_t RESERVED_46[12];
1189 __I uint32_t CH6_CMD; /**< APBH DMA Channel n Command Register, offset: 0x3C0 */
1190 uint8_t RESERVED_47[12];
1191 __I uint32_t CH6_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x3D0 */
1192 uint8_t RESERVED_48[12];
1193 __IO uint32_t CH6_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x3E0 */
1194 uint8_t RESERVED_49[12];
1195 __I uint32_t CH6_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x3F0 */
1196 uint8_t RESERVED_50[12];
1197 __I uint32_t CH6_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x400 */
1198 uint8_t RESERVED_51[12];
1199 __I uint32_t CH7_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x410 */
1200 uint8_t RESERVED_52[12];
1201 __IO uint32_t CH7_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x420 */
1202 uint8_t RESERVED_53[12];
1203 __I uint32_t CH7_CMD; /**< APBH DMA Channel n Command Register, offset: 0x430 */
1204 uint8_t RESERVED_54[12];
1205 __I uint32_t CH7_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x440 */
1206 uint8_t RESERVED_55[12];
1207 __IO uint32_t CH7_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x450 */
1208 uint8_t RESERVED_56[12];
1209 __I uint32_t CH7_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x460 */
1210 uint8_t RESERVED_57[12];
1211 __I uint32_t CH7_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x470 */
1212 uint8_t RESERVED_58[12];
1213 __I uint32_t CH8_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x480 */
1214 uint8_t RESERVED_59[12];
1215 __IO uint32_t CH8_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x490 */
1216 uint8_t RESERVED_60[12];
1217 __I uint32_t CH8_CMD; /**< APBH DMA Channel n Command Register, offset: 0x4A0 */
1218 uint8_t RESERVED_61[12];
1219 __I uint32_t CH8_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x4B0 */
1220 uint8_t RESERVED_62[12];
1221 __IO uint32_t CH8_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x4C0 */
1222 uint8_t RESERVED_63[12];
1223 __I uint32_t CH8_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4D0 */
1224 uint8_t RESERVED_64[12];
1225 __I uint32_t CH8_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4E0 */
1226 uint8_t RESERVED_65[12];
1227 __I uint32_t CH9_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x4F0 */
1228 uint8_t RESERVED_66[12];
1229 __IO uint32_t CH9_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x500 */
1230 uint8_t RESERVED_67[12];
1231 __I uint32_t CH9_CMD; /**< APBH DMA Channel n Command Register, offset: 0x510 */
1232 uint8_t RESERVED_68[12];
1233 __I uint32_t CH9_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x520 */
1234 uint8_t RESERVED_69[12];
1235 __IO uint32_t CH9_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x530 */
1236 uint8_t RESERVED_70[12];
1237 __I uint32_t CH9_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x540 */
1238 uint8_t RESERVED_71[12];
1239 __I uint32_t CH9_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x550 */
1240 uint8_t RESERVED_72[12];
1241 __I uint32_t CH10_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x560 */
1242 uint8_t RESERVED_73[12];
1243 __IO uint32_t CH10_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x570 */
1244 uint8_t RESERVED_74[12];
1245 __I uint32_t CH10_CMD; /**< APBH DMA Channel n Command Register, offset: 0x580 */
1246 uint8_t RESERVED_75[12];
1247 __I uint32_t CH10_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x590 */
1248 uint8_t RESERVED_76[12];
1249 __IO uint32_t CH10_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x5A0 */
1250 uint8_t RESERVED_77[12];
1251 __I uint32_t CH10_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5B0 */
1252 uint8_t RESERVED_78[12];
1253 __I uint32_t CH10_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5C0 */
1254 uint8_t RESERVED_79[12];
1255 __I uint32_t CH11_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x5D0 */
1256 uint8_t RESERVED_80[12];
1257 __IO uint32_t CH11_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x5E0 */
1258 uint8_t RESERVED_81[12];
1259 __I uint32_t CH11_CMD; /**< APBH DMA Channel n Command Register, offset: 0x5F0 */
1260 uint8_t RESERVED_82[12];
1261 __I uint32_t CH11_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x600 */
1262 uint8_t RESERVED_83[12];
1263 __IO uint32_t CH11_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x610 */
1264 uint8_t RESERVED_84[12];
1265 __I uint32_t CH11_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x620 */
1266 uint8_t RESERVED_85[12];
1267 __I uint32_t CH11_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x630 */
1268 uint8_t RESERVED_86[12];
1269 __I uint32_t CH12_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x640 */
1270 uint8_t RESERVED_87[12];
1271 __IO uint32_t CH12_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x650 */
1272 uint8_t RESERVED_88[12];
1273 __I uint32_t CH12_CMD; /**< APBH DMA Channel n Command Register, offset: 0x660 */
1274 uint8_t RESERVED_89[12];
1275 __I uint32_t CH12_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x670 */
1276 uint8_t RESERVED_90[12];
1277 __IO uint32_t CH12_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x680 */
1278 uint8_t RESERVED_91[12];
1279 __I uint32_t CH12_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x690 */
1280 uint8_t RESERVED_92[12];
1281 __I uint32_t CH12_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x6A0 */
1282 uint8_t RESERVED_93[12];
1283 __I uint32_t CH13_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x6B0 */
1284 uint8_t RESERVED_94[12];
1285 __IO uint32_t CH13_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x6C0 */
1286 uint8_t RESERVED_95[12];
1287 __I uint32_t CH13_CMD; /**< APBH DMA Channel n Command Register, offset: 0x6D0 */
1288 uint8_t RESERVED_96[12];
1289 __I uint32_t CH13_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x6E0 */
1290 uint8_t RESERVED_97[12];
1291 __IO uint32_t CH13_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x6F0 */
1292 uint8_t RESERVED_98[12];
1293 __I uint32_t CH13_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x700 */
1294 uint8_t RESERVED_99[12];
1295 __I uint32_t CH13_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x710 */
1296 uint8_t RESERVED_100[12];
1297 __I uint32_t CH14_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x720 */
1298 uint8_t RESERVED_101[12];
1299 __IO uint32_t CH14_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x730 */
1300 uint8_t RESERVED_102[12];
1301 __I uint32_t CH14_CMD; /**< APBH DMA Channel n Command Register, offset: 0x740 */
1302 uint8_t RESERVED_103[12];
1303 __I uint32_t CH14_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x750 */
1304 uint8_t RESERVED_104[12];
1305 __IO uint32_t CH14_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x760 */
1306 uint8_t RESERVED_105[12];
1307 __I uint32_t CH14_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x770 */
1308 uint8_t RESERVED_106[12];
1309 __I uint32_t CH14_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x780 */
1310 uint8_t RESERVED_107[12];
1311 __I uint32_t CH15_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x790 */
1312 uint8_t RESERVED_108[12];
1313 __IO uint32_t CH15_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x7A0 */
1314 uint8_t RESERVED_109[12];
1315 __I uint32_t CH15_CMD; /**< APBH DMA Channel n Command Register, offset: 0x7B0 */
1316 uint8_t RESERVED_110[12];
1317 __I uint32_t CH15_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x7C0 */
1318 uint8_t RESERVED_111[12];
1319 __IO uint32_t CH15_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x7D0 */
1320 uint8_t RESERVED_112[12];
1321 __I uint32_t CH15_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7E0 */
1322 uint8_t RESERVED_113[12];
1323 __I uint32_t CH15_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7F0 */
1324 uint8_t RESERVED_114[12];
1325 __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */
1326} APBH_Type;
1327
1328/* ----------------------------------------------------------------------------
1329 -- APBH Register Masks
1330 ---------------------------------------------------------------------------- */
1331
1332/*!
1333 * @addtogroup APBH_Register_Masks APBH Register Masks
1334 * @{
1335 */
1336
1337/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */
1338/*! @{ */
1339#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU)
1340#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U)
1341/*! CLKGATE_CHANNEL
1342 * 0b0000000000000001..NAND0
1343 * 0b0000000000000010..NAND1
1344 * 0b0000000000000100..NAND2
1345 * 0b0000000000001000..NAND3
1346 * 0b0000000000010000..NAND4
1347 * 0b0000000000100000..NAND5
1348 * 0b0000000001000000..NAND6
1349 * 0b0000000010000000..NAND7
1350 * 0b0000000100000000..SSP
1351 */
1352#define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK)
1353#define APBH_CTRL0_RSVD0_MASK (0xFFF0000U)
1354#define APBH_CTRL0_RSVD0_SHIFT (16U)
1355#define APBH_CTRL0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_RSVD0_SHIFT)) & APBH_CTRL0_RSVD0_MASK)
1356#define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U)
1357#define APBH_CTRL0_APB_BURST_EN_SHIFT (28U)
1358#define APBH_CTRL0_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK)
1359#define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U)
1360#define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U)
1361#define APBH_CTRL0_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK)
1362#define APBH_CTRL0_CLKGATE_MASK (0x40000000U)
1363#define APBH_CTRL0_CLKGATE_SHIFT (30U)
1364#define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK)
1365#define APBH_CTRL0_SFTRST_MASK (0x80000000U)
1366#define APBH_CTRL0_SFTRST_SHIFT (31U)
1367#define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK)
1368/*! @} */
1369
1370/*! @name CTRL0_SET - AHB to APBH Bridge Control and Status Register 0 */
1371/*! @{ */
1372#define APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK (0xFFFFU)
1373#define APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT (0U)
1374/*! CLKGATE_CHANNEL
1375 * 0b0000000000000001..NAND0
1376 * 0b0000000000000010..NAND1
1377 * 0b0000000000000100..NAND2
1378 * 0b0000000000001000..NAND3
1379 * 0b0000000000010000..NAND4
1380 * 0b0000000000100000..NAND5
1381 * 0b0000000001000000..NAND6
1382 * 0b0000000010000000..NAND7
1383 * 0b0000000100000000..SSP
1384 */
1385#define APBH_CTRL0_SET_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK)
1386#define APBH_CTRL0_SET_RSVD0_MASK (0xFFF0000U)
1387#define APBH_CTRL0_SET_RSVD0_SHIFT (16U)
1388#define APBH_CTRL0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_RSVD0_SHIFT)) & APBH_CTRL0_SET_RSVD0_MASK)
1389#define APBH_CTRL0_SET_APB_BURST_EN_MASK (0x10000000U)
1390#define APBH_CTRL0_SET_APB_BURST_EN_SHIFT (28U)
1391#define APBH_CTRL0_SET_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_APB_BURST_EN_SHIFT)) & APBH_CTRL0_SET_APB_BURST_EN_MASK)
1392#define APBH_CTRL0_SET_AHB_BURST8_EN_MASK (0x20000000U)
1393#define APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT (29U)
1394#define APBH_CTRL0_SET_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_SET_AHB_BURST8_EN_MASK)
1395#define APBH_CTRL0_SET_CLKGATE_MASK (0x40000000U)
1396#define APBH_CTRL0_SET_CLKGATE_SHIFT (30U)
1397#define APBH_CTRL0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_SHIFT)) & APBH_CTRL0_SET_CLKGATE_MASK)
1398#define APBH_CTRL0_SET_SFTRST_MASK (0x80000000U)
1399#define APBH_CTRL0_SET_SFTRST_SHIFT (31U)
1400#define APBH_CTRL0_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_SFTRST_SHIFT)) & APBH_CTRL0_SET_SFTRST_MASK)
1401/*! @} */
1402
1403/*! @name CTRL0_CLR - AHB to APBH Bridge Control and Status Register 0 */
1404/*! @{ */
1405#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK (0xFFFFU)
1406#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT (0U)
1407/*! CLKGATE_CHANNEL
1408 * 0b0000000000000001..NAND0
1409 * 0b0000000000000010..NAND1
1410 * 0b0000000000000100..NAND2
1411 * 0b0000000000001000..NAND3
1412 * 0b0000000000010000..NAND4
1413 * 0b0000000000100000..NAND5
1414 * 0b0000000001000000..NAND6
1415 * 0b0000000010000000..NAND7
1416 * 0b0000000100000000..SSP
1417 */
1418#define APBH_CTRL0_CLR_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK)
1419#define APBH_CTRL0_CLR_RSVD0_MASK (0xFFF0000U)
1420#define APBH_CTRL0_CLR_RSVD0_SHIFT (16U)
1421#define APBH_CTRL0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_RSVD0_SHIFT)) & APBH_CTRL0_CLR_RSVD0_MASK)
1422#define APBH_CTRL0_CLR_APB_BURST_EN_MASK (0x10000000U)
1423#define APBH_CTRL0_CLR_APB_BURST_EN_SHIFT (28U)
1424#define APBH_CTRL0_CLR_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_APB_BURST_EN_SHIFT)) & APBH_CTRL0_CLR_APB_BURST_EN_MASK)
1425#define APBH_CTRL0_CLR_AHB_BURST8_EN_MASK (0x20000000U)
1426#define APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT (29U)
1427#define APBH_CTRL0_CLR_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_CLR_AHB_BURST8_EN_MASK)
1428#define APBH_CTRL0_CLR_CLKGATE_MASK (0x40000000U)
1429#define APBH_CTRL0_CLR_CLKGATE_SHIFT (30U)
1430#define APBH_CTRL0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_MASK)
1431#define APBH_CTRL0_CLR_SFTRST_MASK (0x80000000U)
1432#define APBH_CTRL0_CLR_SFTRST_SHIFT (31U)
1433#define APBH_CTRL0_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_SFTRST_SHIFT)) & APBH_CTRL0_CLR_SFTRST_MASK)
1434/*! @} */
1435
1436/*! @name CTRL0_TOG - AHB to APBH Bridge Control and Status Register 0 */
1437/*! @{ */
1438#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK (0xFFFFU)
1439#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT (0U)
1440/*! CLKGATE_CHANNEL
1441 * 0b0000000000000001..NAND0
1442 * 0b0000000000000010..NAND1
1443 * 0b0000000000000100..NAND2
1444 * 0b0000000000001000..NAND3
1445 * 0b0000000000010000..NAND4
1446 * 0b0000000000100000..NAND5
1447 * 0b0000000001000000..NAND6
1448 * 0b0000000010000000..NAND7
1449 * 0b0000000100000000..SSP
1450 */
1451#define APBH_CTRL0_TOG_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK)
1452#define APBH_CTRL0_TOG_RSVD0_MASK (0xFFF0000U)
1453#define APBH_CTRL0_TOG_RSVD0_SHIFT (16U)
1454#define APBH_CTRL0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_RSVD0_SHIFT)) & APBH_CTRL0_TOG_RSVD0_MASK)
1455#define APBH_CTRL0_TOG_APB_BURST_EN_MASK (0x10000000U)
1456#define APBH_CTRL0_TOG_APB_BURST_EN_SHIFT (28U)
1457#define APBH_CTRL0_TOG_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_APB_BURST_EN_SHIFT)) & APBH_CTRL0_TOG_APB_BURST_EN_MASK)
1458#define APBH_CTRL0_TOG_AHB_BURST8_EN_MASK (0x20000000U)
1459#define APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT (29U)
1460#define APBH_CTRL0_TOG_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_TOG_AHB_BURST8_EN_MASK)
1461#define APBH_CTRL0_TOG_CLKGATE_MASK (0x40000000U)
1462#define APBH_CTRL0_TOG_CLKGATE_SHIFT (30U)
1463#define APBH_CTRL0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_MASK)
1464#define APBH_CTRL0_TOG_SFTRST_MASK (0x80000000U)
1465#define APBH_CTRL0_TOG_SFTRST_SHIFT (31U)
1466#define APBH_CTRL0_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_SFTRST_SHIFT)) & APBH_CTRL0_TOG_SFTRST_MASK)
1467/*! @} */
1468
1469/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */
1470/*! @{ */
1471#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1472#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1473#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK)
1474#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1475#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1476#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK)
1477#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1478#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1479#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK)
1480#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1481#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1482#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK)
1483#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1484#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1485#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK)
1486#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1487#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1488#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK)
1489#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1490#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1491#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK)
1492#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1493#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1494#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK)
1495#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1496#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1497#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK)
1498#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1499#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1500#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK)
1501#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1502#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1503#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK)
1504#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1505#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1506#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK)
1507#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1508#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1509#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK)
1510#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1511#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1512#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK)
1513#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1514#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1515#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK)
1516#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1517#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1518#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK)
1519#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1520#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
1521#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK)
1522#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
1523#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
1524#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK)
1525#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
1526#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
1527#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK)
1528#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
1529#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
1530#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK)
1531#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
1532#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
1533#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK)
1534#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
1535#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
1536#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK)
1537#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
1538#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
1539#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK)
1540#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
1541#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
1542#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK)
1543#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
1544#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
1545#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK)
1546#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
1547#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
1548#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK)
1549#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
1550#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
1551#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
1552#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
1553#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
1554#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK)
1555#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
1556#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
1557#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK)
1558#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
1559#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
1560#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK)
1561#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
1562#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
1563#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK)
1564#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
1565#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
1566#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK)
1567/*! @} */
1568
1569/*! @name CTRL1_SET - AHB to APBH Bridge Control and Status Register 1 */
1570/*! @{ */
1571#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1572#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1573#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK)
1574#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1575#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1576#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK)
1577#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1578#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1579#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK)
1580#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1581#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1582#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK)
1583#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1584#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1585#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK)
1586#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1587#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1588#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK)
1589#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1590#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1591#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK)
1592#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1593#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1594#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK)
1595#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1596#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1597#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK)
1598#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1599#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1600#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK)
1601#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1602#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1603#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK)
1604#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1605#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1606#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK)
1607#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1608#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1609#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK)
1610#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1611#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1612#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK)
1613#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1614#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1615#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK)
1616#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1617#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1618#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK)
1619#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1620#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
1621#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK)
1622#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
1623#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
1624#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK)
1625#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
1626#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
1627#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK)
1628#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
1629#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
1630#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK)
1631#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
1632#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
1633#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK)
1634#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
1635#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
1636#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK)
1637#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
1638#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
1639#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK)
1640#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
1641#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
1642#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK)
1643#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
1644#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
1645#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK)
1646#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
1647#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
1648#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK)
1649#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
1650#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
1651#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK)
1652#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
1653#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
1654#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK)
1655#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
1656#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
1657#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK)
1658#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
1659#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
1660#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK)
1661#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
1662#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
1663#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK)
1664#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
1665#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
1666#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK)
1667/*! @} */
1668
1669/*! @name CTRL1_CLR - AHB to APBH Bridge Control and Status Register 1 */
1670/*! @{ */
1671#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1672#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1673#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK)
1674#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1675#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1676#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK)
1677#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1678#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1679#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK)
1680#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1681#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1682#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK)
1683#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1684#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1685#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK)
1686#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1687#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1688#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK)
1689#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1690#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1691#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK)
1692#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1693#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1694#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK)
1695#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1696#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1697#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK)
1698#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1699#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1700#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK)
1701#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1702#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1703#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK)
1704#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1705#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1706#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK)
1707#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1708#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1709#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK)
1710#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1711#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1712#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK)
1713#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1714#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1715#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK)
1716#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1717#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1718#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK)
1719#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1720#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
1721#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK)
1722#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
1723#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
1724#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK)
1725#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
1726#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
1727#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK)
1728#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
1729#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
1730#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK)
1731#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
1732#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
1733#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK)
1734#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
1735#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
1736#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK)
1737#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
1738#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
1739#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK)
1740#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
1741#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
1742#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK)
1743#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
1744#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
1745#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK)
1746#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
1747#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
1748#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK)
1749#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
1750#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
1751#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK)
1752#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
1753#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
1754#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK)
1755#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
1756#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
1757#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK)
1758#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
1759#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
1760#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK)
1761#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
1762#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
1763#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK)
1764#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
1765#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
1766#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK)
1767/*! @} */
1768
1769/*! @name CTRL1_TOG - AHB to APBH Bridge Control and Status Register 1 */
1770/*! @{ */
1771#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1772#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1773#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK)
1774#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1775#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1776#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK)
1777#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1778#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1779#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK)
1780#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1781#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1782#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK)
1783#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1784#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1785#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK)
1786#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1787#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1788#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK)
1789#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1790#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1791#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK)
1792#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1793#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1794#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK)
1795#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1796#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1797#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK)
1798#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1799#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1800#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK)
1801#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1802#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1803#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK)
1804#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1805#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1806#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK)
1807#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1808#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1809#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK)
1810#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1811#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1812#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK)
1813#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1814#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1815#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK)
1816#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1817#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1818#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK)
1819#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1820#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
1821#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK)
1822#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
1823#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
1824#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK)
1825#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
1826#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
1827#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK)
1828#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
1829#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
1830#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK)
1831#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
1832#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
1833#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK)
1834#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
1835#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
1836#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK)
1837#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
1838#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
1839#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK)
1840#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
1841#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
1842#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK)
1843#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
1844#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
1845#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK)
1846#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
1847#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
1848#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK)
1849#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
1850#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
1851#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK)
1852#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
1853#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
1854#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK)
1855#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
1856#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
1857#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK)
1858#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
1859#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
1860#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK)
1861#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
1862#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
1863#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK)
1864#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
1865#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
1866#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK)
1867/*! @} */
1868
1869/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */
1870/*! @{ */
1871#define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U)
1872#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U)
1873#define APBH_CTRL2_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK)
1874#define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U)
1875#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U)
1876#define APBH_CTRL2_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK)
1877#define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U)
1878#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U)
1879#define APBH_CTRL2_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK)
1880#define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U)
1881#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U)
1882#define APBH_CTRL2_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK)
1883#define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U)
1884#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U)
1885#define APBH_CTRL2_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK)
1886#define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U)
1887#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U)
1888#define APBH_CTRL2_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK)
1889#define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U)
1890#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U)
1891#define APBH_CTRL2_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK)
1892#define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U)
1893#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U)
1894#define APBH_CTRL2_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK)
1895#define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U)
1896#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U)
1897#define APBH_CTRL2_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK)
1898#define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U)
1899#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U)
1900#define APBH_CTRL2_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK)
1901#define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U)
1902#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U)
1903#define APBH_CTRL2_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK)
1904#define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U)
1905#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U)
1906#define APBH_CTRL2_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK)
1907#define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U)
1908#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U)
1909#define APBH_CTRL2_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK)
1910#define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U)
1911#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U)
1912#define APBH_CTRL2_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK)
1913#define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U)
1914#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U)
1915#define APBH_CTRL2_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK)
1916#define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U)
1917#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U)
1918#define APBH_CTRL2_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK)
1919#define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U)
1920#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U)
1921/*! CH0_ERROR_STATUS
1922 * 0b0..An early termination from the device causes error IRQ.
1923 * 0b1..An AHB bus error causes error IRQ.
1924 */
1925#define APBH_CTRL2_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK)
1926#define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U)
1927#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U)
1928/*! CH1_ERROR_STATUS
1929 * 0b0..An early termination from the device causes error IRQ.
1930 * 0b1..An AHB bus error causes error IRQ.
1931 */
1932#define APBH_CTRL2_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK)
1933#define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U)
1934#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U)
1935/*! CH2_ERROR_STATUS
1936 * 0b0..An early termination from the device causes error IRQ.
1937 * 0b1..An AHB bus error causes error IRQ.
1938 */
1939#define APBH_CTRL2_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK)
1940#define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U)
1941#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U)
1942/*! CH3_ERROR_STATUS
1943 * 0b0..An early termination from the device causes error IRQ.
1944 * 0b1..An AHB bus error causes error IRQ.
1945 */
1946#define APBH_CTRL2_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK)
1947#define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U)
1948#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U)
1949/*! CH4_ERROR_STATUS
1950 * 0b0..An early termination from the device causes error IRQ.
1951 * 0b1..An AHB bus error causes error IRQ.
1952 */
1953#define APBH_CTRL2_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK)
1954#define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U)
1955#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U)
1956/*! CH5_ERROR_STATUS
1957 * 0b0..An early termination from the device causes error IRQ.
1958 * 0b1..An AHB bus error causes error IRQ.
1959 */
1960#define APBH_CTRL2_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK)
1961#define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U)
1962#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U)
1963/*! CH6_ERROR_STATUS
1964 * 0b0..An early termination from the device causes error IRQ.
1965 * 0b1..An AHB bus error causes error IRQ.
1966 */
1967#define APBH_CTRL2_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK)
1968#define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U)
1969#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U)
1970/*! CH7_ERROR_STATUS
1971 * 0b0..An early termination from the device causes error IRQ.
1972 * 0b1..An AHB bus error causes error IRQ.
1973 */
1974#define APBH_CTRL2_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK)
1975#define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U)
1976#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U)
1977/*! CH8_ERROR_STATUS
1978 * 0b0..An early termination from the device causes error IRQ.
1979 * 0b1..An AHB bus error causes error IRQ.
1980 */
1981#define APBH_CTRL2_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK)
1982#define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U)
1983#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U)
1984/*! CH9_ERROR_STATUS
1985 * 0b0..An early termination from the device causes error IRQ.
1986 * 0b1..An AHB bus error causes error IRQ.
1987 */
1988#define APBH_CTRL2_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK)
1989#define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U)
1990#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U)
1991/*! CH10_ERROR_STATUS
1992 * 0b0..An early termination from the device causes error IRQ.
1993 * 0b1..An AHB bus error causes error IRQ.
1994 */
1995#define APBH_CTRL2_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK)
1996#define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U)
1997#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U)
1998/*! CH11_ERROR_STATUS
1999 * 0b0..An early termination from the device causes error IRQ.
2000 * 0b1..An AHB bus error causes error IRQ.
2001 */
2002#define APBH_CTRL2_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK)
2003#define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U)
2004#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U)
2005/*! CH12_ERROR_STATUS
2006 * 0b0..An early termination from the device causes error IRQ.
2007 * 0b1..An AHB bus error causes error IRQ.
2008 */
2009#define APBH_CTRL2_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK)
2010#define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U)
2011#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U)
2012/*! CH13_ERROR_STATUS
2013 * 0b0..An early termination from the device causes error IRQ.
2014 * 0b1..An AHB bus error causes error IRQ.
2015 */
2016#define APBH_CTRL2_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK)
2017#define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U)
2018#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U)
2019/*! CH14_ERROR_STATUS
2020 * 0b0..An early termination from the device causes error IRQ.
2021 * 0b1..An AHB bus error causes error IRQ.
2022 */
2023#define APBH_CTRL2_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK)
2024#define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U)
2025#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U)
2026/*! CH15_ERROR_STATUS
2027 * 0b0..An early termination from the device causes error IRQ.
2028 * 0b1..An AHB bus error causes error IRQ.
2029 */
2030#define APBH_CTRL2_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK)
2031/*! @} */
2032
2033/*! @name CTRL2_SET - AHB to APBH Bridge Control and Status Register 2 */
2034/*! @{ */
2035#define APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK (0x1U)
2036#define APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT (0U)
2037#define APBH_CTRL2_SET_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK)
2038#define APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK (0x2U)
2039#define APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT (1U)
2040#define APBH_CTRL2_SET_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK)
2041#define APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK (0x4U)
2042#define APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT (2U)
2043#define APBH_CTRL2_SET_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK)
2044#define APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK (0x8U)
2045#define APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT (3U)
2046#define APBH_CTRL2_SET_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK)
2047#define APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK (0x10U)
2048#define APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT (4U)
2049#define APBH_CTRL2_SET_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK)
2050#define APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK (0x20U)
2051#define APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT (5U)
2052#define APBH_CTRL2_SET_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK)
2053#define APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK (0x40U)
2054#define APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT (6U)
2055#define APBH_CTRL2_SET_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK)
2056#define APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK (0x80U)
2057#define APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT (7U)
2058#define APBH_CTRL2_SET_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK)
2059#define APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK (0x100U)
2060#define APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT (8U)
2061#define APBH_CTRL2_SET_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK)
2062#define APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK (0x200U)
2063#define APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT (9U)
2064#define APBH_CTRL2_SET_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK)
2065#define APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK (0x400U)
2066#define APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT (10U)
2067#define APBH_CTRL2_SET_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK)
2068#define APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK (0x800U)
2069#define APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT (11U)
2070#define APBH_CTRL2_SET_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK)
2071#define APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK (0x1000U)
2072#define APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT (12U)
2073#define APBH_CTRL2_SET_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK)
2074#define APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK (0x2000U)
2075#define APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT (13U)
2076#define APBH_CTRL2_SET_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK)
2077#define APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK (0x4000U)
2078#define APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT (14U)
2079#define APBH_CTRL2_SET_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK)
2080#define APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK (0x8000U)
2081#define APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT (15U)
2082#define APBH_CTRL2_SET_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK)
2083#define APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK (0x10000U)
2084#define APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT (16U)
2085/*! CH0_ERROR_STATUS
2086 * 0b0..An early termination from the device causes error IRQ.
2087 * 0b1..An AHB bus error causes error IRQ.
2088 */
2089#define APBH_CTRL2_SET_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK)
2090#define APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK (0x20000U)
2091#define APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT (17U)
2092/*! CH1_ERROR_STATUS
2093 * 0b0..An early termination from the device causes error IRQ.
2094 * 0b1..An AHB bus error causes error IRQ.
2095 */
2096#define APBH_CTRL2_SET_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK)
2097#define APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK (0x40000U)
2098#define APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT (18U)
2099/*! CH2_ERROR_STATUS
2100 * 0b0..An early termination from the device causes error IRQ.
2101 * 0b1..An AHB bus error causes error IRQ.
2102 */
2103#define APBH_CTRL2_SET_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK)
2104#define APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK (0x80000U)
2105#define APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT (19U)
2106/*! CH3_ERROR_STATUS
2107 * 0b0..An early termination from the device causes error IRQ.
2108 * 0b1..An AHB bus error causes error IRQ.
2109 */
2110#define APBH_CTRL2_SET_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK)
2111#define APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK (0x100000U)
2112#define APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT (20U)
2113/*! CH4_ERROR_STATUS
2114 * 0b0..An early termination from the device causes error IRQ.
2115 * 0b1..An AHB bus error causes error IRQ.
2116 */
2117#define APBH_CTRL2_SET_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK)
2118#define APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK (0x200000U)
2119#define APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT (21U)
2120/*! CH5_ERROR_STATUS
2121 * 0b0..An early termination from the device causes error IRQ.
2122 * 0b1..An AHB bus error causes error IRQ.
2123 */
2124#define APBH_CTRL2_SET_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK)
2125#define APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK (0x400000U)
2126#define APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT (22U)
2127/*! CH6_ERROR_STATUS
2128 * 0b0..An early termination from the device causes error IRQ.
2129 * 0b1..An AHB bus error causes error IRQ.
2130 */
2131#define APBH_CTRL2_SET_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK)
2132#define APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK (0x800000U)
2133#define APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT (23U)
2134/*! CH7_ERROR_STATUS
2135 * 0b0..An early termination from the device causes error IRQ.
2136 * 0b1..An AHB bus error causes error IRQ.
2137 */
2138#define APBH_CTRL2_SET_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK)
2139#define APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK (0x1000000U)
2140#define APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT (24U)
2141/*! CH8_ERROR_STATUS
2142 * 0b0..An early termination from the device causes error IRQ.
2143 * 0b1..An AHB bus error causes error IRQ.
2144 */
2145#define APBH_CTRL2_SET_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK)
2146#define APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK (0x2000000U)
2147#define APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT (25U)
2148/*! CH9_ERROR_STATUS
2149 * 0b0..An early termination from the device causes error IRQ.
2150 * 0b1..An AHB bus error causes error IRQ.
2151 */
2152#define APBH_CTRL2_SET_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK)
2153#define APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK (0x4000000U)
2154#define APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT (26U)
2155/*! CH10_ERROR_STATUS
2156 * 0b0..An early termination from the device causes error IRQ.
2157 * 0b1..An AHB bus error causes error IRQ.
2158 */
2159#define APBH_CTRL2_SET_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK)
2160#define APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK (0x8000000U)
2161#define APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT (27U)
2162/*! CH11_ERROR_STATUS
2163 * 0b0..An early termination from the device causes error IRQ.
2164 * 0b1..An AHB bus error causes error IRQ.
2165 */
2166#define APBH_CTRL2_SET_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK)
2167#define APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK (0x10000000U)
2168#define APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT (28U)
2169/*! CH12_ERROR_STATUS
2170 * 0b0..An early termination from the device causes error IRQ.
2171 * 0b1..An AHB bus error causes error IRQ.
2172 */
2173#define APBH_CTRL2_SET_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK)
2174#define APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK (0x20000000U)
2175#define APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT (29U)
2176/*! CH13_ERROR_STATUS
2177 * 0b0..An early termination from the device causes error IRQ.
2178 * 0b1..An AHB bus error causes error IRQ.
2179 */
2180#define APBH_CTRL2_SET_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK)
2181#define APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK (0x40000000U)
2182#define APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT (30U)
2183/*! CH14_ERROR_STATUS
2184 * 0b0..An early termination from the device causes error IRQ.
2185 * 0b1..An AHB bus error causes error IRQ.
2186 */
2187#define APBH_CTRL2_SET_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK)
2188#define APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK (0x80000000U)
2189#define APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT (31U)
2190/*! CH15_ERROR_STATUS
2191 * 0b0..An early termination from the device causes error IRQ.
2192 * 0b1..An AHB bus error causes error IRQ.
2193 */
2194#define APBH_CTRL2_SET_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK)
2195/*! @} */
2196
2197/*! @name CTRL2_CLR - AHB to APBH Bridge Control and Status Register 2 */
2198/*! @{ */
2199#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK (0x1U)
2200#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT (0U)
2201#define APBH_CTRL2_CLR_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK)
2202#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK (0x2U)
2203#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT (1U)
2204#define APBH_CTRL2_CLR_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK)
2205#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK (0x4U)
2206#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT (2U)
2207#define APBH_CTRL2_CLR_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK)
2208#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK (0x8U)
2209#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT (3U)
2210#define APBH_CTRL2_CLR_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK)
2211#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK (0x10U)
2212#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT (4U)
2213#define APBH_CTRL2_CLR_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK)
2214#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK (0x20U)
2215#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT (5U)
2216#define APBH_CTRL2_CLR_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK)
2217#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK (0x40U)
2218#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT (6U)
2219#define APBH_CTRL2_CLR_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK)
2220#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK (0x80U)
2221#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT (7U)
2222#define APBH_CTRL2_CLR_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK)
2223#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK (0x100U)
2224#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT (8U)
2225#define APBH_CTRL2_CLR_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK)
2226#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK (0x200U)
2227#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT (9U)
2228#define APBH_CTRL2_CLR_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK)
2229#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK (0x400U)
2230#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT (10U)
2231#define APBH_CTRL2_CLR_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK)
2232#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK (0x800U)
2233#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT (11U)
2234#define APBH_CTRL2_CLR_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK)
2235#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK (0x1000U)
2236#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT (12U)
2237#define APBH_CTRL2_CLR_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK)
2238#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK (0x2000U)
2239#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT (13U)
2240#define APBH_CTRL2_CLR_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK)
2241#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK (0x4000U)
2242#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT (14U)
2243#define APBH_CTRL2_CLR_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK)
2244#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK (0x8000U)
2245#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT (15U)
2246#define APBH_CTRL2_CLR_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK)
2247#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK (0x10000U)
2248#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT (16U)
2249/*! CH0_ERROR_STATUS
2250 * 0b0..An early termination from the device causes error IRQ.
2251 * 0b1..An AHB bus error causes error IRQ.
2252 */
2253#define APBH_CTRL2_CLR_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK)
2254#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK (0x20000U)
2255#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT (17U)
2256/*! CH1_ERROR_STATUS
2257 * 0b0..An early termination from the device causes error IRQ.
2258 * 0b1..An AHB bus error causes error IRQ.
2259 */
2260#define APBH_CTRL2_CLR_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK)
2261#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK (0x40000U)
2262#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT (18U)
2263/*! CH2_ERROR_STATUS
2264 * 0b0..An early termination from the device causes error IRQ.
2265 * 0b1..An AHB bus error causes error IRQ.
2266 */
2267#define APBH_CTRL2_CLR_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK)
2268#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK (0x80000U)
2269#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT (19U)
2270/*! CH3_ERROR_STATUS
2271 * 0b0..An early termination from the device causes error IRQ.
2272 * 0b1..An AHB bus error causes error IRQ.
2273 */
2274#define APBH_CTRL2_CLR_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK)
2275#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK (0x100000U)
2276#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT (20U)
2277/*! CH4_ERROR_STATUS
2278 * 0b0..An early termination from the device causes error IRQ.
2279 * 0b1..An AHB bus error causes error IRQ.
2280 */
2281#define APBH_CTRL2_CLR_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK)
2282#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK (0x200000U)
2283#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT (21U)
2284/*! CH5_ERROR_STATUS
2285 * 0b0..An early termination from the device causes error IRQ.
2286 * 0b1..An AHB bus error causes error IRQ.
2287 */
2288#define APBH_CTRL2_CLR_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK)
2289#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK (0x400000U)
2290#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT (22U)
2291/*! CH6_ERROR_STATUS
2292 * 0b0..An early termination from the device causes error IRQ.
2293 * 0b1..An AHB bus error causes error IRQ.
2294 */
2295#define APBH_CTRL2_CLR_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK)
2296#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK (0x800000U)
2297#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT (23U)
2298/*! CH7_ERROR_STATUS
2299 * 0b0..An early termination from the device causes error IRQ.
2300 * 0b1..An AHB bus error causes error IRQ.
2301 */
2302#define APBH_CTRL2_CLR_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK)
2303#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK (0x1000000U)
2304#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT (24U)
2305/*! CH8_ERROR_STATUS
2306 * 0b0..An early termination from the device causes error IRQ.
2307 * 0b1..An AHB bus error causes error IRQ.
2308 */
2309#define APBH_CTRL2_CLR_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK)
2310#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK (0x2000000U)
2311#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT (25U)
2312/*! CH9_ERROR_STATUS
2313 * 0b0..An early termination from the device causes error IRQ.
2314 * 0b1..An AHB bus error causes error IRQ.
2315 */
2316#define APBH_CTRL2_CLR_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK)
2317#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK (0x4000000U)
2318#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT (26U)
2319/*! CH10_ERROR_STATUS
2320 * 0b0..An early termination from the device causes error IRQ.
2321 * 0b1..An AHB bus error causes error IRQ.
2322 */
2323#define APBH_CTRL2_CLR_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK)
2324#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK (0x8000000U)
2325#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT (27U)
2326/*! CH11_ERROR_STATUS
2327 * 0b0..An early termination from the device causes error IRQ.
2328 * 0b1..An AHB bus error causes error IRQ.
2329 */
2330#define APBH_CTRL2_CLR_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK)
2331#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK (0x10000000U)
2332#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT (28U)
2333/*! CH12_ERROR_STATUS
2334 * 0b0..An early termination from the device causes error IRQ.
2335 * 0b1..An AHB bus error causes error IRQ.
2336 */
2337#define APBH_CTRL2_CLR_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK)
2338#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK (0x20000000U)
2339#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT (29U)
2340/*! CH13_ERROR_STATUS
2341 * 0b0..An early termination from the device causes error IRQ.
2342 * 0b1..An AHB bus error causes error IRQ.
2343 */
2344#define APBH_CTRL2_CLR_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK)
2345#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK (0x40000000U)
2346#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT (30U)
2347/*! CH14_ERROR_STATUS
2348 * 0b0..An early termination from the device causes error IRQ.
2349 * 0b1..An AHB bus error causes error IRQ.
2350 */
2351#define APBH_CTRL2_CLR_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK)
2352#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK (0x80000000U)
2353#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT (31U)
2354/*! CH15_ERROR_STATUS
2355 * 0b0..An early termination from the device causes error IRQ.
2356 * 0b1..An AHB bus error causes error IRQ.
2357 */
2358#define APBH_CTRL2_CLR_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK)
2359/*! @} */
2360
2361/*! @name CTRL2_TOG - AHB to APBH Bridge Control and Status Register 2 */
2362/*! @{ */
2363#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK (0x1U)
2364#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT (0U)
2365#define APBH_CTRL2_TOG_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK)
2366#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK (0x2U)
2367#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT (1U)
2368#define APBH_CTRL2_TOG_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK)
2369#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK (0x4U)
2370#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT (2U)
2371#define APBH_CTRL2_TOG_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK)
2372#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK (0x8U)
2373#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT (3U)
2374#define APBH_CTRL2_TOG_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK)
2375#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK (0x10U)
2376#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT (4U)
2377#define APBH_CTRL2_TOG_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK)
2378#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK (0x20U)
2379#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT (5U)
2380#define APBH_CTRL2_TOG_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK)
2381#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK (0x40U)
2382#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT (6U)
2383#define APBH_CTRL2_TOG_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK)
2384#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK (0x80U)
2385#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT (7U)
2386#define APBH_CTRL2_TOG_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK)
2387#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK (0x100U)
2388#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT (8U)
2389#define APBH_CTRL2_TOG_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK)
2390#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK (0x200U)
2391#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT (9U)
2392#define APBH_CTRL2_TOG_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK)
2393#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK (0x400U)
2394#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT (10U)
2395#define APBH_CTRL2_TOG_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK)
2396#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK (0x800U)
2397#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT (11U)
2398#define APBH_CTRL2_TOG_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK)
2399#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK (0x1000U)
2400#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT (12U)
2401#define APBH_CTRL2_TOG_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK)
2402#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK (0x2000U)
2403#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT (13U)
2404#define APBH_CTRL2_TOG_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK)
2405#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK (0x4000U)
2406#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT (14U)
2407#define APBH_CTRL2_TOG_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK)
2408#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK (0x8000U)
2409#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT (15U)
2410#define APBH_CTRL2_TOG_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK)
2411#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK (0x10000U)
2412#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT (16U)
2413/*! CH0_ERROR_STATUS
2414 * 0b0..An early termination from the device causes error IRQ.
2415 * 0b1..An AHB bus error causes error IRQ.
2416 */
2417#define APBH_CTRL2_TOG_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK)
2418#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK (0x20000U)
2419#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT (17U)
2420/*! CH1_ERROR_STATUS
2421 * 0b0..An early termination from the device causes error IRQ.
2422 * 0b1..An AHB bus error causes error IRQ.
2423 */
2424#define APBH_CTRL2_TOG_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK)
2425#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK (0x40000U)
2426#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT (18U)
2427/*! CH2_ERROR_STATUS
2428 * 0b0..An early termination from the device causes error IRQ.
2429 * 0b1..An AHB bus error causes error IRQ.
2430 */
2431#define APBH_CTRL2_TOG_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK)
2432#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK (0x80000U)
2433#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT (19U)
2434/*! CH3_ERROR_STATUS
2435 * 0b0..An early termination from the device causes error IRQ.
2436 * 0b1..An AHB bus error causes error IRQ.
2437 */
2438#define APBH_CTRL2_TOG_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK)
2439#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK (0x100000U)
2440#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT (20U)
2441/*! CH4_ERROR_STATUS
2442 * 0b0..An early termination from the device causes error IRQ.
2443 * 0b1..An AHB bus error causes error IRQ.
2444 */
2445#define APBH_CTRL2_TOG_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK)
2446#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK (0x200000U)
2447#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT (21U)
2448/*! CH5_ERROR_STATUS
2449 * 0b0..An early termination from the device causes error IRQ.
2450 * 0b1..An AHB bus error causes error IRQ.
2451 */
2452#define APBH_CTRL2_TOG_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK)
2453#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK (0x400000U)
2454#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT (22U)
2455/*! CH6_ERROR_STATUS
2456 * 0b0..An early termination from the device causes error IRQ.
2457 * 0b1..An AHB bus error causes error IRQ.
2458 */
2459#define APBH_CTRL2_TOG_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK)
2460#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK (0x800000U)
2461#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT (23U)
2462/*! CH7_ERROR_STATUS
2463 * 0b0..An early termination from the device causes error IRQ.
2464 * 0b1..An AHB bus error causes error IRQ.
2465 */
2466#define APBH_CTRL2_TOG_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK)
2467#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK (0x1000000U)
2468#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT (24U)
2469/*! CH8_ERROR_STATUS
2470 * 0b0..An early termination from the device causes error IRQ.
2471 * 0b1..An AHB bus error causes error IRQ.
2472 */
2473#define APBH_CTRL2_TOG_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK)
2474#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK (0x2000000U)
2475#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT (25U)
2476/*! CH9_ERROR_STATUS
2477 * 0b0..An early termination from the device causes error IRQ.
2478 * 0b1..An AHB bus error causes error IRQ.
2479 */
2480#define APBH_CTRL2_TOG_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK)
2481#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK (0x4000000U)
2482#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT (26U)
2483/*! CH10_ERROR_STATUS
2484 * 0b0..An early termination from the device causes error IRQ.
2485 * 0b1..An AHB bus error causes error IRQ.
2486 */
2487#define APBH_CTRL2_TOG_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK)
2488#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK (0x8000000U)
2489#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT (27U)
2490/*! CH11_ERROR_STATUS
2491 * 0b0..An early termination from the device causes error IRQ.
2492 * 0b1..An AHB bus error causes error IRQ.
2493 */
2494#define APBH_CTRL2_TOG_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK)
2495#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK (0x10000000U)
2496#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT (28U)
2497/*! CH12_ERROR_STATUS
2498 * 0b0..An early termination from the device causes error IRQ.
2499 * 0b1..An AHB bus error causes error IRQ.
2500 */
2501#define APBH_CTRL2_TOG_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK)
2502#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK (0x20000000U)
2503#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT (29U)
2504/*! CH13_ERROR_STATUS
2505 * 0b0..An early termination from the device causes error IRQ.
2506 * 0b1..An AHB bus error causes error IRQ.
2507 */
2508#define APBH_CTRL2_TOG_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK)
2509#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK (0x40000000U)
2510#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT (30U)
2511/*! CH14_ERROR_STATUS
2512 * 0b0..An early termination from the device causes error IRQ.
2513 * 0b1..An AHB bus error causes error IRQ.
2514 */
2515#define APBH_CTRL2_TOG_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK)
2516#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK (0x80000000U)
2517#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT (31U)
2518/*! CH15_ERROR_STATUS
2519 * 0b0..An early termination from the device causes error IRQ.
2520 * 0b1..An AHB bus error causes error IRQ.
2521 */
2522#define APBH_CTRL2_TOG_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK)
2523/*! @} */
2524
2525/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */
2526/*! @{ */
2527#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU)
2528#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U)
2529/*! FREEZE_CHANNEL
2530 * 0b0000000000000001..NAND0
2531 * 0b0000000000000010..NAND1
2532 * 0b0000000000000100..NAND2
2533 * 0b0000000000001000..NAND3
2534 * 0b0000000000010000..NAND4
2535 * 0b0000000000100000..NAND5
2536 * 0b0000000001000000..NAND6
2537 * 0b0000000010000000..NAND7
2538 * 0b0000000100000000..SSP
2539 */
2540#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK)
2541#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U)
2542#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U)
2543/*! RESET_CHANNEL
2544 * 0b0000000000000001..NAND0
2545 * 0b0000000000000010..NAND1
2546 * 0b0000000000000100..NAND2
2547 * 0b0000000000001000..NAND3
2548 * 0b0000000000010000..NAND4
2549 * 0b0000000000100000..NAND5
2550 * 0b0000000001000000..NAND6
2551 * 0b0000000010000000..NAND7
2552 * 0b0000000100000000..SSP
2553 */
2554#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK)
2555/*! @} */
2556
2557/*! @name CHANNEL_CTRL_SET - AHB to APBH Bridge Channel Register */
2558/*! @{ */
2559#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK (0xFFFFU)
2560#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT (0U)
2561/*! FREEZE_CHANNEL
2562 * 0b0000000000000001..NAND0
2563 * 0b0000000000000010..NAND1
2564 * 0b0000000000000100..NAND2
2565 * 0b0000000000001000..NAND3
2566 * 0b0000000000010000..NAND4
2567 * 0b0000000000100000..NAND5
2568 * 0b0000000001000000..NAND6
2569 * 0b0000000010000000..NAND7
2570 * 0b0000000100000000..SSP
2571 */
2572#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK)
2573#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK (0xFFFF0000U)
2574#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT (16U)
2575/*! RESET_CHANNEL
2576 * 0b0000000000000001..NAND0
2577 * 0b0000000000000010..NAND1
2578 * 0b0000000000000100..NAND2
2579 * 0b0000000000001000..NAND3
2580 * 0b0000000000010000..NAND4
2581 * 0b0000000000100000..NAND5
2582 * 0b0000000001000000..NAND6
2583 * 0b0000000010000000..NAND7
2584 * 0b0000000100000000..SSP
2585 */
2586#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK)
2587/*! @} */
2588
2589/*! @name CHANNEL_CTRL_CLR - AHB to APBH Bridge Channel Register */
2590/*! @{ */
2591#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK (0xFFFFU)
2592#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT (0U)
2593/*! FREEZE_CHANNEL
2594 * 0b0000000000000001..NAND0
2595 * 0b0000000000000010..NAND1
2596 * 0b0000000000000100..NAND2
2597 * 0b0000000000001000..NAND3
2598 * 0b0000000000010000..NAND4
2599 * 0b0000000000100000..NAND5
2600 * 0b0000000001000000..NAND6
2601 * 0b0000000010000000..NAND7
2602 * 0b0000000100000000..SSP
2603 */
2604#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK)
2605#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK (0xFFFF0000U)
2606#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT (16U)
2607/*! RESET_CHANNEL
2608 * 0b0000000000000001..NAND0
2609 * 0b0000000000000010..NAND1
2610 * 0b0000000000000100..NAND2
2611 * 0b0000000000001000..NAND3
2612 * 0b0000000000010000..NAND4
2613 * 0b0000000000100000..NAND5
2614 * 0b0000000001000000..NAND6
2615 * 0b0000000010000000..NAND7
2616 * 0b0000000100000000..SSP
2617 */
2618#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK)
2619/*! @} */
2620
2621/*! @name CHANNEL_CTRL_TOG - AHB to APBH Bridge Channel Register */
2622/*! @{ */
2623#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK (0xFFFFU)
2624#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT (0U)
2625/*! FREEZE_CHANNEL
2626 * 0b0000000000000001..NAND0
2627 * 0b0000000000000010..NAND1
2628 * 0b0000000000000100..NAND2
2629 * 0b0000000000001000..NAND3
2630 * 0b0000000000010000..NAND4
2631 * 0b0000000000100000..NAND5
2632 * 0b0000000001000000..NAND6
2633 * 0b0000000010000000..NAND7
2634 * 0b0000000100000000..SSP
2635 */
2636#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK)
2637#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK (0xFFFF0000U)
2638#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT (16U)
2639/*! RESET_CHANNEL
2640 * 0b0000000000000001..NAND0
2641 * 0b0000000000000010..NAND1
2642 * 0b0000000000000100..NAND2
2643 * 0b0000000000001000..NAND3
2644 * 0b0000000000010000..NAND4
2645 * 0b0000000000100000..NAND5
2646 * 0b0000000001000000..NAND6
2647 * 0b0000000010000000..NAND7
2648 * 0b0000000100000000..SSP
2649 */
2650#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK)
2651/*! @} */
2652
2653/*! @name DEVSEL - AHB to APBH DMA Device Assignment Register */
2654/*! @{ */
2655#define APBH_DEVSEL_CH0_MASK (0x3U)
2656#define APBH_DEVSEL_CH0_SHIFT (0U)
2657#define APBH_DEVSEL_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH0_SHIFT)) & APBH_DEVSEL_CH0_MASK)
2658#define APBH_DEVSEL_CH1_MASK (0xCU)
2659#define APBH_DEVSEL_CH1_SHIFT (2U)
2660#define APBH_DEVSEL_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH1_SHIFT)) & APBH_DEVSEL_CH1_MASK)
2661#define APBH_DEVSEL_CH2_MASK (0x30U)
2662#define APBH_DEVSEL_CH2_SHIFT (4U)
2663#define APBH_DEVSEL_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH2_SHIFT)) & APBH_DEVSEL_CH2_MASK)
2664#define APBH_DEVSEL_CH3_MASK (0xC0U)
2665#define APBH_DEVSEL_CH3_SHIFT (6U)
2666#define APBH_DEVSEL_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH3_SHIFT)) & APBH_DEVSEL_CH3_MASK)
2667#define APBH_DEVSEL_CH4_MASK (0x300U)
2668#define APBH_DEVSEL_CH4_SHIFT (8U)
2669#define APBH_DEVSEL_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH4_SHIFT)) & APBH_DEVSEL_CH4_MASK)
2670#define APBH_DEVSEL_CH5_MASK (0xC00U)
2671#define APBH_DEVSEL_CH5_SHIFT (10U)
2672#define APBH_DEVSEL_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH5_SHIFT)) & APBH_DEVSEL_CH5_MASK)
2673#define APBH_DEVSEL_CH6_MASK (0x3000U)
2674#define APBH_DEVSEL_CH6_SHIFT (12U)
2675#define APBH_DEVSEL_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH6_SHIFT)) & APBH_DEVSEL_CH6_MASK)
2676#define APBH_DEVSEL_CH7_MASK (0xC000U)
2677#define APBH_DEVSEL_CH7_SHIFT (14U)
2678#define APBH_DEVSEL_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH7_SHIFT)) & APBH_DEVSEL_CH7_MASK)
2679#define APBH_DEVSEL_CH8_MASK (0x30000U)
2680#define APBH_DEVSEL_CH8_SHIFT (16U)
2681#define APBH_DEVSEL_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH8_SHIFT)) & APBH_DEVSEL_CH8_MASK)
2682#define APBH_DEVSEL_CH9_MASK (0xC0000U)
2683#define APBH_DEVSEL_CH9_SHIFT (18U)
2684#define APBH_DEVSEL_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH9_SHIFT)) & APBH_DEVSEL_CH9_MASK)
2685#define APBH_DEVSEL_CH10_MASK (0x300000U)
2686#define APBH_DEVSEL_CH10_SHIFT (20U)
2687#define APBH_DEVSEL_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH10_SHIFT)) & APBH_DEVSEL_CH10_MASK)
2688#define APBH_DEVSEL_CH11_MASK (0xC00000U)
2689#define APBH_DEVSEL_CH11_SHIFT (22U)
2690#define APBH_DEVSEL_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH11_SHIFT)) & APBH_DEVSEL_CH11_MASK)
2691#define APBH_DEVSEL_CH12_MASK (0x3000000U)
2692#define APBH_DEVSEL_CH12_SHIFT (24U)
2693#define APBH_DEVSEL_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH12_SHIFT)) & APBH_DEVSEL_CH12_MASK)
2694#define APBH_DEVSEL_CH13_MASK (0xC000000U)
2695#define APBH_DEVSEL_CH13_SHIFT (26U)
2696#define APBH_DEVSEL_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH13_SHIFT)) & APBH_DEVSEL_CH13_MASK)
2697#define APBH_DEVSEL_CH14_MASK (0x30000000U)
2698#define APBH_DEVSEL_CH14_SHIFT (28U)
2699#define APBH_DEVSEL_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH14_SHIFT)) & APBH_DEVSEL_CH14_MASK)
2700#define APBH_DEVSEL_CH15_MASK (0xC0000000U)
2701#define APBH_DEVSEL_CH15_SHIFT (30U)
2702#define APBH_DEVSEL_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH15_SHIFT)) & APBH_DEVSEL_CH15_MASK)
2703/*! @} */
2704
2705/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */
2706/*! @{ */
2707#define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U)
2708#define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U)
2709#define APBH_DMA_BURST_SIZE_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK)
2710#define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU)
2711#define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U)
2712#define APBH_DMA_BURST_SIZE_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK)
2713#define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U)
2714#define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U)
2715#define APBH_DMA_BURST_SIZE_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK)
2716#define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U)
2717#define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U)
2718#define APBH_DMA_BURST_SIZE_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK)
2719#define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U)
2720#define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U)
2721#define APBH_DMA_BURST_SIZE_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK)
2722#define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U)
2723#define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U)
2724#define APBH_DMA_BURST_SIZE_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK)
2725#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U)
2726#define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U)
2727#define APBH_DMA_BURST_SIZE_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK)
2728#define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U)
2729#define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U)
2730#define APBH_DMA_BURST_SIZE_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK)
2731#define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U)
2732#define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U)
2733/*! CH8
2734 * 0b00..BURST0
2735 * 0b01..BURST4
2736 * 0b10..BURST8
2737 */
2738#define APBH_DMA_BURST_SIZE_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK)
2739#define APBH_DMA_BURST_SIZE_CH9_MASK (0xC0000U)
2740#define APBH_DMA_BURST_SIZE_CH9_SHIFT (18U)
2741#define APBH_DMA_BURST_SIZE_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH9_SHIFT)) & APBH_DMA_BURST_SIZE_CH9_MASK)
2742#define APBH_DMA_BURST_SIZE_CH10_MASK (0x300000U)
2743#define APBH_DMA_BURST_SIZE_CH10_SHIFT (20U)
2744#define APBH_DMA_BURST_SIZE_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH10_SHIFT)) & APBH_DMA_BURST_SIZE_CH10_MASK)
2745#define APBH_DMA_BURST_SIZE_CH11_MASK (0xC00000U)
2746#define APBH_DMA_BURST_SIZE_CH11_SHIFT (22U)
2747#define APBH_DMA_BURST_SIZE_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH11_SHIFT)) & APBH_DMA_BURST_SIZE_CH11_MASK)
2748#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3000000U)
2749#define APBH_DMA_BURST_SIZE_CH12_SHIFT (24U)
2750#define APBH_DMA_BURST_SIZE_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH12_SHIFT)) & APBH_DMA_BURST_SIZE_CH12_MASK)
2751#define APBH_DMA_BURST_SIZE_CH13_MASK (0xC000000U)
2752#define APBH_DMA_BURST_SIZE_CH13_SHIFT (26U)
2753#define APBH_DMA_BURST_SIZE_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH13_SHIFT)) & APBH_DMA_BURST_SIZE_CH13_MASK)
2754#define APBH_DMA_BURST_SIZE_CH14_MASK (0x30000000U)
2755#define APBH_DMA_BURST_SIZE_CH14_SHIFT (28U)
2756#define APBH_DMA_BURST_SIZE_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH14_SHIFT)) & APBH_DMA_BURST_SIZE_CH14_MASK)
2757#define APBH_DMA_BURST_SIZE_CH15_MASK (0xC0000000U)
2758#define APBH_DMA_BURST_SIZE_CH15_SHIFT (30U)
2759#define APBH_DMA_BURST_SIZE_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH15_SHIFT)) & APBH_DMA_BURST_SIZE_CH15_MASK)
2760/*! @} */
2761
2762/*! @name DEBUG - AHB to APBH DMA Debug Register */
2763/*! @{ */
2764#define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U)
2765#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U)
2766#define APBH_DEBUG_GPMI_ONE_FIFO(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK)
2767/*! @} */
2768
2769/*! @name CH0_CURCMDAR - APBH DMA Channel n Current Command Address Register */
2770/*! @{ */
2771#define APBH_CH0_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
2772#define APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT (0U)
2773#define APBH_CH0_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_CURCMDAR_CMD_ADDR_MASK)
2774/*! @} */
2775
2776/*! @name CH0_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
2777/*! @{ */
2778#define APBH_CH0_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
2779#define APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT (0U)
2780#define APBH_CH0_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_NXTCMDAR_CMD_ADDR_MASK)
2781/*! @} */
2782
2783/*! @name CH0_CMD - APBH DMA Channel n Command Register */
2784/*! @{ */
2785#define APBH_CH0_CMD_COMMAND_MASK (0x3U)
2786#define APBH_CH0_CMD_COMMAND_SHIFT (0U)
2787/*! COMMAND
2788 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
2789 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
2790 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
2791 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
2792 */
2793#define APBH_CH0_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_COMMAND_SHIFT)) & APBH_CH0_CMD_COMMAND_MASK)
2794#define APBH_CH0_CMD_CHAIN_MASK (0x4U)
2795#define APBH_CH0_CMD_CHAIN_SHIFT (2U)
2796#define APBH_CH0_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CHAIN_SHIFT)) & APBH_CH0_CMD_CHAIN_MASK)
2797#define APBH_CH0_CMD_IRQONCMPLT_MASK (0x8U)
2798#define APBH_CH0_CMD_IRQONCMPLT_SHIFT (3U)
2799#define APBH_CH0_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_IRQONCMPLT_SHIFT)) & APBH_CH0_CMD_IRQONCMPLT_MASK)
2800#define APBH_CH0_CMD_NANDLOCK_MASK (0x10U)
2801#define APBH_CH0_CMD_NANDLOCK_SHIFT (4U)
2802#define APBH_CH0_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDLOCK_SHIFT)) & APBH_CH0_CMD_NANDLOCK_MASK)
2803#define APBH_CH0_CMD_NANDWAIT4READY_MASK (0x20U)
2804#define APBH_CH0_CMD_NANDWAIT4READY_SHIFT (5U)
2805#define APBH_CH0_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH0_CMD_NANDWAIT4READY_MASK)
2806#define APBH_CH0_CMD_SEMAPHORE_MASK (0x40U)
2807#define APBH_CH0_CMD_SEMAPHORE_SHIFT (6U)
2808#define APBH_CH0_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_SEMAPHORE_SHIFT)) & APBH_CH0_CMD_SEMAPHORE_MASK)
2809#define APBH_CH0_CMD_WAIT4ENDCMD_MASK (0x80U)
2810#define APBH_CH0_CMD_WAIT4ENDCMD_SHIFT (7U)
2811#define APBH_CH0_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH0_CMD_WAIT4ENDCMD_MASK)
2812#define APBH_CH0_CMD_HALTONTERMINATE_MASK (0x100U)
2813#define APBH_CH0_CMD_HALTONTERMINATE_SHIFT (8U)
2814#define APBH_CH0_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH0_CMD_HALTONTERMINATE_MASK)
2815#define APBH_CH0_CMD_CMDWORDS_MASK (0xF000U)
2816#define APBH_CH0_CMD_CMDWORDS_SHIFT (12U)
2817#define APBH_CH0_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CMDWORDS_SHIFT)) & APBH_CH0_CMD_CMDWORDS_MASK)
2818#define APBH_CH0_CMD_XFER_COUNT_MASK (0xFFFF0000U)
2819#define APBH_CH0_CMD_XFER_COUNT_SHIFT (16U)
2820#define APBH_CH0_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_XFER_COUNT_SHIFT)) & APBH_CH0_CMD_XFER_COUNT_MASK)
2821/*! @} */
2822
2823/*! @name CH0_BAR - APBH DMA Channel n Buffer Address Register */
2824/*! @{ */
2825#define APBH_CH0_BAR_ADDRESS_MASK (0xFFFFFFFFU)
2826#define APBH_CH0_BAR_ADDRESS_SHIFT (0U)
2827#define APBH_CH0_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_BAR_ADDRESS_SHIFT)) & APBH_CH0_BAR_ADDRESS_MASK)
2828/*! @} */
2829
2830/*! @name CH0_SEMA - APBH DMA Channel n Semaphore Register */
2831/*! @{ */
2832#define APBH_CH0_SEMA_INCREMENT_SEMA_MASK (0xFFU)
2833#define APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT (0U)
2834#define APBH_CH0_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH0_SEMA_INCREMENT_SEMA_MASK)
2835#define APBH_CH0_SEMA_PHORE_MASK (0xFF0000U)
2836#define APBH_CH0_SEMA_PHORE_SHIFT (16U)
2837#define APBH_CH0_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_PHORE_SHIFT)) & APBH_CH0_SEMA_PHORE_MASK)
2838/*! @} */
2839
2840/*! @name CH0_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
2841/*! @{ */
2842#define APBH_CH0_DEBUG1_STATEMACHINE_MASK (0x1FU)
2843#define APBH_CH0_DEBUG1_STATEMACHINE_SHIFT (0U)
2844/*! STATEMACHINE
2845 * 0b00000..This is the idle state of the DMA state machine.
2846 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
2847 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
2848 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
2849 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
2850 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
2851 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
2852 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
2853 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
2854 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
2855 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
2856 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
2857 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
2858 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
2859 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
2860 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
2861 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
2862 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
2863 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
2864 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
2865 */
2866#define APBH_CH0_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH0_DEBUG1_STATEMACHINE_MASK)
2867#define APBH_CH0_DEBUG1_RSVD1_MASK (0xFFFE0U)
2868#define APBH_CH0_DEBUG1_RSVD1_SHIFT (5U)
2869#define APBH_CH0_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RSVD1_SHIFT)) & APBH_CH0_DEBUG1_RSVD1_MASK)
2870#define APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
2871#define APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
2872#define APBH_CH0_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK)
2873#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
2874#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
2875#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK)
2876#define APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
2877#define APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
2878#define APBH_CH0_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK)
2879#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
2880#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
2881#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK)
2882#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
2883#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
2884#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK)
2885#define APBH_CH0_DEBUG1_LOCK_MASK (0x2000000U)
2886#define APBH_CH0_DEBUG1_LOCK_SHIFT (25U)
2887#define APBH_CH0_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_LOCK_SHIFT)) & APBH_CH0_DEBUG1_LOCK_MASK)
2888#define APBH_CH0_DEBUG1_READY_MASK (0x4000000U)
2889#define APBH_CH0_DEBUG1_READY_SHIFT (26U)
2890#define APBH_CH0_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_READY_SHIFT)) & APBH_CH0_DEBUG1_READY_MASK)
2891#define APBH_CH0_DEBUG1_SENSE_MASK (0x8000000U)
2892#define APBH_CH0_DEBUG1_SENSE_SHIFT (27U)
2893#define APBH_CH0_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_SENSE_SHIFT)) & APBH_CH0_DEBUG1_SENSE_MASK)
2894#define APBH_CH0_DEBUG1_END_MASK (0x10000000U)
2895#define APBH_CH0_DEBUG1_END_SHIFT (28U)
2896#define APBH_CH0_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_END_SHIFT)) & APBH_CH0_DEBUG1_END_MASK)
2897#define APBH_CH0_DEBUG1_KICK_MASK (0x20000000U)
2898#define APBH_CH0_DEBUG1_KICK_SHIFT (29U)
2899#define APBH_CH0_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_KICK_SHIFT)) & APBH_CH0_DEBUG1_KICK_MASK)
2900#define APBH_CH0_DEBUG1_BURST_MASK (0x40000000U)
2901#define APBH_CH0_DEBUG1_BURST_SHIFT (30U)
2902#define APBH_CH0_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_BURST_SHIFT)) & APBH_CH0_DEBUG1_BURST_MASK)
2903#define APBH_CH0_DEBUG1_REQ_MASK (0x80000000U)
2904#define APBH_CH0_DEBUG1_REQ_SHIFT (31U)
2905#define APBH_CH0_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_REQ_SHIFT)) & APBH_CH0_DEBUG1_REQ_MASK)
2906/*! @} */
2907
2908/*! @name CH0_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
2909/*! @{ */
2910#define APBH_CH0_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
2911#define APBH_CH0_DEBUG2_AHB_BYTES_SHIFT (0U)
2912#define APBH_CH0_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_AHB_BYTES_MASK)
2913#define APBH_CH0_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
2914#define APBH_CH0_DEBUG2_APB_BYTES_SHIFT (16U)
2915#define APBH_CH0_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_APB_BYTES_MASK)
2916/*! @} */
2917
2918/*! @name CH1_CURCMDAR - APBH DMA Channel n Current Command Address Register */
2919/*! @{ */
2920#define APBH_CH1_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
2921#define APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT (0U)
2922#define APBH_CH1_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_CURCMDAR_CMD_ADDR_MASK)
2923/*! @} */
2924
2925/*! @name CH1_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
2926/*! @{ */
2927#define APBH_CH1_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
2928#define APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT (0U)
2929#define APBH_CH1_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_NXTCMDAR_CMD_ADDR_MASK)
2930/*! @} */
2931
2932/*! @name CH1_CMD - APBH DMA Channel n Command Register */
2933/*! @{ */
2934#define APBH_CH1_CMD_COMMAND_MASK (0x3U)
2935#define APBH_CH1_CMD_COMMAND_SHIFT (0U)
2936/*! COMMAND
2937 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
2938 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
2939 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
2940 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
2941 */
2942#define APBH_CH1_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_COMMAND_SHIFT)) & APBH_CH1_CMD_COMMAND_MASK)
2943#define APBH_CH1_CMD_CHAIN_MASK (0x4U)
2944#define APBH_CH1_CMD_CHAIN_SHIFT (2U)
2945#define APBH_CH1_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CHAIN_SHIFT)) & APBH_CH1_CMD_CHAIN_MASK)
2946#define APBH_CH1_CMD_IRQONCMPLT_MASK (0x8U)
2947#define APBH_CH1_CMD_IRQONCMPLT_SHIFT (3U)
2948#define APBH_CH1_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_IRQONCMPLT_SHIFT)) & APBH_CH1_CMD_IRQONCMPLT_MASK)
2949#define APBH_CH1_CMD_NANDLOCK_MASK (0x10U)
2950#define APBH_CH1_CMD_NANDLOCK_SHIFT (4U)
2951#define APBH_CH1_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDLOCK_SHIFT)) & APBH_CH1_CMD_NANDLOCK_MASK)
2952#define APBH_CH1_CMD_NANDWAIT4READY_MASK (0x20U)
2953#define APBH_CH1_CMD_NANDWAIT4READY_SHIFT (5U)
2954#define APBH_CH1_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH1_CMD_NANDWAIT4READY_MASK)
2955#define APBH_CH1_CMD_SEMAPHORE_MASK (0x40U)
2956#define APBH_CH1_CMD_SEMAPHORE_SHIFT (6U)
2957#define APBH_CH1_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_SEMAPHORE_SHIFT)) & APBH_CH1_CMD_SEMAPHORE_MASK)
2958#define APBH_CH1_CMD_WAIT4ENDCMD_MASK (0x80U)
2959#define APBH_CH1_CMD_WAIT4ENDCMD_SHIFT (7U)
2960#define APBH_CH1_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH1_CMD_WAIT4ENDCMD_MASK)
2961#define APBH_CH1_CMD_HALTONTERMINATE_MASK (0x100U)
2962#define APBH_CH1_CMD_HALTONTERMINATE_SHIFT (8U)
2963#define APBH_CH1_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH1_CMD_HALTONTERMINATE_MASK)
2964#define APBH_CH1_CMD_CMDWORDS_MASK (0xF000U)
2965#define APBH_CH1_CMD_CMDWORDS_SHIFT (12U)
2966#define APBH_CH1_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CMDWORDS_SHIFT)) & APBH_CH1_CMD_CMDWORDS_MASK)
2967#define APBH_CH1_CMD_XFER_COUNT_MASK (0xFFFF0000U)
2968#define APBH_CH1_CMD_XFER_COUNT_SHIFT (16U)
2969#define APBH_CH1_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_XFER_COUNT_SHIFT)) & APBH_CH1_CMD_XFER_COUNT_MASK)
2970/*! @} */
2971
2972/*! @name CH1_BAR - APBH DMA Channel n Buffer Address Register */
2973/*! @{ */
2974#define APBH_CH1_BAR_ADDRESS_MASK (0xFFFFFFFFU)
2975#define APBH_CH1_BAR_ADDRESS_SHIFT (0U)
2976#define APBH_CH1_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_BAR_ADDRESS_SHIFT)) & APBH_CH1_BAR_ADDRESS_MASK)
2977/*! @} */
2978
2979/*! @name CH1_SEMA - APBH DMA Channel n Semaphore Register */
2980/*! @{ */
2981#define APBH_CH1_SEMA_INCREMENT_SEMA_MASK (0xFFU)
2982#define APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT (0U)
2983#define APBH_CH1_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH1_SEMA_INCREMENT_SEMA_MASK)
2984#define APBH_CH1_SEMA_PHORE_MASK (0xFF0000U)
2985#define APBH_CH1_SEMA_PHORE_SHIFT (16U)
2986#define APBH_CH1_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_PHORE_SHIFT)) & APBH_CH1_SEMA_PHORE_MASK)
2987/*! @} */
2988
2989/*! @name CH1_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
2990/*! @{ */
2991#define APBH_CH1_DEBUG1_STATEMACHINE_MASK (0x1FU)
2992#define APBH_CH1_DEBUG1_STATEMACHINE_SHIFT (0U)
2993/*! STATEMACHINE
2994 * 0b00000..This is the idle state of the DMA state machine.
2995 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
2996 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
2997 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
2998 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
2999 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
3000 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
3001 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
3002 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
3003 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
3004 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3005 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3006 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
3007 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
3008 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
3009 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
3010 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
3011 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
3012 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
3013 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
3014 */
3015#define APBH_CH1_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH1_DEBUG1_STATEMACHINE_MASK)
3016#define APBH_CH1_DEBUG1_RSVD1_MASK (0xFFFE0U)
3017#define APBH_CH1_DEBUG1_RSVD1_SHIFT (5U)
3018#define APBH_CH1_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RSVD1_SHIFT)) & APBH_CH1_DEBUG1_RSVD1_MASK)
3019#define APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
3020#define APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
3021#define APBH_CH1_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK)
3022#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
3023#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
3024#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK)
3025#define APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
3026#define APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
3027#define APBH_CH1_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK)
3028#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
3029#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
3030#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK)
3031#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
3032#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
3033#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK)
3034#define APBH_CH1_DEBUG1_LOCK_MASK (0x2000000U)
3035#define APBH_CH1_DEBUG1_LOCK_SHIFT (25U)
3036#define APBH_CH1_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_LOCK_SHIFT)) & APBH_CH1_DEBUG1_LOCK_MASK)
3037#define APBH_CH1_DEBUG1_READY_MASK (0x4000000U)
3038#define APBH_CH1_DEBUG1_READY_SHIFT (26U)
3039#define APBH_CH1_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_READY_SHIFT)) & APBH_CH1_DEBUG1_READY_MASK)
3040#define APBH_CH1_DEBUG1_SENSE_MASK (0x8000000U)
3041#define APBH_CH1_DEBUG1_SENSE_SHIFT (27U)
3042#define APBH_CH1_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_SENSE_SHIFT)) & APBH_CH1_DEBUG1_SENSE_MASK)
3043#define APBH_CH1_DEBUG1_END_MASK (0x10000000U)
3044#define APBH_CH1_DEBUG1_END_SHIFT (28U)
3045#define APBH_CH1_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_END_SHIFT)) & APBH_CH1_DEBUG1_END_MASK)
3046#define APBH_CH1_DEBUG1_KICK_MASK (0x20000000U)
3047#define APBH_CH1_DEBUG1_KICK_SHIFT (29U)
3048#define APBH_CH1_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_KICK_SHIFT)) & APBH_CH1_DEBUG1_KICK_MASK)
3049#define APBH_CH1_DEBUG1_BURST_MASK (0x40000000U)
3050#define APBH_CH1_DEBUG1_BURST_SHIFT (30U)
3051#define APBH_CH1_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_BURST_SHIFT)) & APBH_CH1_DEBUG1_BURST_MASK)
3052#define APBH_CH1_DEBUG1_REQ_MASK (0x80000000U)
3053#define APBH_CH1_DEBUG1_REQ_SHIFT (31U)
3054#define APBH_CH1_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_REQ_SHIFT)) & APBH_CH1_DEBUG1_REQ_MASK)
3055/*! @} */
3056
3057/*! @name CH1_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
3058/*! @{ */
3059#define APBH_CH1_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
3060#define APBH_CH1_DEBUG2_AHB_BYTES_SHIFT (0U)
3061#define APBH_CH1_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_AHB_BYTES_MASK)
3062#define APBH_CH1_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
3063#define APBH_CH1_DEBUG2_APB_BYTES_SHIFT (16U)
3064#define APBH_CH1_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_APB_BYTES_MASK)
3065/*! @} */
3066
3067/*! @name CH2_CURCMDAR - APBH DMA Channel n Current Command Address Register */
3068/*! @{ */
3069#define APBH_CH2_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3070#define APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT (0U)
3071#define APBH_CH2_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_CURCMDAR_CMD_ADDR_MASK)
3072/*! @} */
3073
3074/*! @name CH2_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
3075/*! @{ */
3076#define APBH_CH2_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3077#define APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT (0U)
3078#define APBH_CH2_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_NXTCMDAR_CMD_ADDR_MASK)
3079/*! @} */
3080
3081/*! @name CH2_CMD - APBH DMA Channel n Command Register */
3082/*! @{ */
3083#define APBH_CH2_CMD_COMMAND_MASK (0x3U)
3084#define APBH_CH2_CMD_COMMAND_SHIFT (0U)
3085/*! COMMAND
3086 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
3087 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
3088 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
3089 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
3090 */
3091#define APBH_CH2_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_COMMAND_SHIFT)) & APBH_CH2_CMD_COMMAND_MASK)
3092#define APBH_CH2_CMD_CHAIN_MASK (0x4U)
3093#define APBH_CH2_CMD_CHAIN_SHIFT (2U)
3094#define APBH_CH2_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CHAIN_SHIFT)) & APBH_CH2_CMD_CHAIN_MASK)
3095#define APBH_CH2_CMD_IRQONCMPLT_MASK (0x8U)
3096#define APBH_CH2_CMD_IRQONCMPLT_SHIFT (3U)
3097#define APBH_CH2_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_IRQONCMPLT_SHIFT)) & APBH_CH2_CMD_IRQONCMPLT_MASK)
3098#define APBH_CH2_CMD_NANDLOCK_MASK (0x10U)
3099#define APBH_CH2_CMD_NANDLOCK_SHIFT (4U)
3100#define APBH_CH2_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDLOCK_SHIFT)) & APBH_CH2_CMD_NANDLOCK_MASK)
3101#define APBH_CH2_CMD_NANDWAIT4READY_MASK (0x20U)
3102#define APBH_CH2_CMD_NANDWAIT4READY_SHIFT (5U)
3103#define APBH_CH2_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH2_CMD_NANDWAIT4READY_MASK)
3104#define APBH_CH2_CMD_SEMAPHORE_MASK (0x40U)
3105#define APBH_CH2_CMD_SEMAPHORE_SHIFT (6U)
3106#define APBH_CH2_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_SEMAPHORE_SHIFT)) & APBH_CH2_CMD_SEMAPHORE_MASK)
3107#define APBH_CH2_CMD_WAIT4ENDCMD_MASK (0x80U)
3108#define APBH_CH2_CMD_WAIT4ENDCMD_SHIFT (7U)
3109#define APBH_CH2_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH2_CMD_WAIT4ENDCMD_MASK)
3110#define APBH_CH2_CMD_HALTONTERMINATE_MASK (0x100U)
3111#define APBH_CH2_CMD_HALTONTERMINATE_SHIFT (8U)
3112#define APBH_CH2_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH2_CMD_HALTONTERMINATE_MASK)
3113#define APBH_CH2_CMD_CMDWORDS_MASK (0xF000U)
3114#define APBH_CH2_CMD_CMDWORDS_SHIFT (12U)
3115#define APBH_CH2_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CMDWORDS_SHIFT)) & APBH_CH2_CMD_CMDWORDS_MASK)
3116#define APBH_CH2_CMD_XFER_COUNT_MASK (0xFFFF0000U)
3117#define APBH_CH2_CMD_XFER_COUNT_SHIFT (16U)
3118#define APBH_CH2_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_XFER_COUNT_SHIFT)) & APBH_CH2_CMD_XFER_COUNT_MASK)
3119/*! @} */
3120
3121/*! @name CH2_BAR - APBH DMA Channel n Buffer Address Register */
3122/*! @{ */
3123#define APBH_CH2_BAR_ADDRESS_MASK (0xFFFFFFFFU)
3124#define APBH_CH2_BAR_ADDRESS_SHIFT (0U)
3125#define APBH_CH2_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_BAR_ADDRESS_SHIFT)) & APBH_CH2_BAR_ADDRESS_MASK)
3126/*! @} */
3127
3128/*! @name CH2_SEMA - APBH DMA Channel n Semaphore Register */
3129/*! @{ */
3130#define APBH_CH2_SEMA_INCREMENT_SEMA_MASK (0xFFU)
3131#define APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT (0U)
3132#define APBH_CH2_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH2_SEMA_INCREMENT_SEMA_MASK)
3133#define APBH_CH2_SEMA_PHORE_MASK (0xFF0000U)
3134#define APBH_CH2_SEMA_PHORE_SHIFT (16U)
3135#define APBH_CH2_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_PHORE_SHIFT)) & APBH_CH2_SEMA_PHORE_MASK)
3136/*! @} */
3137
3138/*! @name CH2_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
3139/*! @{ */
3140#define APBH_CH2_DEBUG1_STATEMACHINE_MASK (0x1FU)
3141#define APBH_CH2_DEBUG1_STATEMACHINE_SHIFT (0U)
3142/*! STATEMACHINE
3143 * 0b00000..This is the idle state of the DMA state machine.
3144 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
3145 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
3146 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
3147 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
3148 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
3149 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
3150 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
3151 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
3152 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
3153 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3154 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3155 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
3156 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
3157 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
3158 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
3159 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
3160 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
3161 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
3162 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
3163 */
3164#define APBH_CH2_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH2_DEBUG1_STATEMACHINE_MASK)
3165#define APBH_CH2_DEBUG1_RSVD1_MASK (0xFFFE0U)
3166#define APBH_CH2_DEBUG1_RSVD1_SHIFT (5U)
3167#define APBH_CH2_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RSVD1_SHIFT)) & APBH_CH2_DEBUG1_RSVD1_MASK)
3168#define APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
3169#define APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
3170#define APBH_CH2_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK)
3171#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
3172#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
3173#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK)
3174#define APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
3175#define APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
3176#define APBH_CH2_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK)
3177#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
3178#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
3179#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK)
3180#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
3181#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
3182#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK)
3183#define APBH_CH2_DEBUG1_LOCK_MASK (0x2000000U)
3184#define APBH_CH2_DEBUG1_LOCK_SHIFT (25U)
3185#define APBH_CH2_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_LOCK_SHIFT)) & APBH_CH2_DEBUG1_LOCK_MASK)
3186#define APBH_CH2_DEBUG1_READY_MASK (0x4000000U)
3187#define APBH_CH2_DEBUG1_READY_SHIFT (26U)
3188#define APBH_CH2_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_READY_SHIFT)) & APBH_CH2_DEBUG1_READY_MASK)
3189#define APBH_CH2_DEBUG1_SENSE_MASK (0x8000000U)
3190#define APBH_CH2_DEBUG1_SENSE_SHIFT (27U)
3191#define APBH_CH2_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_SENSE_SHIFT)) & APBH_CH2_DEBUG1_SENSE_MASK)
3192#define APBH_CH2_DEBUG1_END_MASK (0x10000000U)
3193#define APBH_CH2_DEBUG1_END_SHIFT (28U)
3194#define APBH_CH2_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_END_SHIFT)) & APBH_CH2_DEBUG1_END_MASK)
3195#define APBH_CH2_DEBUG1_KICK_MASK (0x20000000U)
3196#define APBH_CH2_DEBUG1_KICK_SHIFT (29U)
3197#define APBH_CH2_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_KICK_SHIFT)) & APBH_CH2_DEBUG1_KICK_MASK)
3198#define APBH_CH2_DEBUG1_BURST_MASK (0x40000000U)
3199#define APBH_CH2_DEBUG1_BURST_SHIFT (30U)
3200#define APBH_CH2_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_BURST_SHIFT)) & APBH_CH2_DEBUG1_BURST_MASK)
3201#define APBH_CH2_DEBUG1_REQ_MASK (0x80000000U)
3202#define APBH_CH2_DEBUG1_REQ_SHIFT (31U)
3203#define APBH_CH2_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_REQ_SHIFT)) & APBH_CH2_DEBUG1_REQ_MASK)
3204/*! @} */
3205
3206/*! @name CH2_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
3207/*! @{ */
3208#define APBH_CH2_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
3209#define APBH_CH2_DEBUG2_AHB_BYTES_SHIFT (0U)
3210#define APBH_CH2_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_AHB_BYTES_MASK)
3211#define APBH_CH2_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
3212#define APBH_CH2_DEBUG2_APB_BYTES_SHIFT (16U)
3213#define APBH_CH2_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_APB_BYTES_MASK)
3214/*! @} */
3215
3216/*! @name CH3_CURCMDAR - APBH DMA Channel n Current Command Address Register */
3217/*! @{ */
3218#define APBH_CH3_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3219#define APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT (0U)
3220#define APBH_CH3_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_CURCMDAR_CMD_ADDR_MASK)
3221/*! @} */
3222
3223/*! @name CH3_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
3224/*! @{ */
3225#define APBH_CH3_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3226#define APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT (0U)
3227#define APBH_CH3_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_NXTCMDAR_CMD_ADDR_MASK)
3228/*! @} */
3229
3230/*! @name CH3_CMD - APBH DMA Channel n Command Register */
3231/*! @{ */
3232#define APBH_CH3_CMD_COMMAND_MASK (0x3U)
3233#define APBH_CH3_CMD_COMMAND_SHIFT (0U)
3234/*! COMMAND
3235 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
3236 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
3237 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
3238 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
3239 */
3240#define APBH_CH3_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_COMMAND_SHIFT)) & APBH_CH3_CMD_COMMAND_MASK)
3241#define APBH_CH3_CMD_CHAIN_MASK (0x4U)
3242#define APBH_CH3_CMD_CHAIN_SHIFT (2U)
3243#define APBH_CH3_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CHAIN_SHIFT)) & APBH_CH3_CMD_CHAIN_MASK)
3244#define APBH_CH3_CMD_IRQONCMPLT_MASK (0x8U)
3245#define APBH_CH3_CMD_IRQONCMPLT_SHIFT (3U)
3246#define APBH_CH3_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_IRQONCMPLT_SHIFT)) & APBH_CH3_CMD_IRQONCMPLT_MASK)
3247#define APBH_CH3_CMD_NANDLOCK_MASK (0x10U)
3248#define APBH_CH3_CMD_NANDLOCK_SHIFT (4U)
3249#define APBH_CH3_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDLOCK_SHIFT)) & APBH_CH3_CMD_NANDLOCK_MASK)
3250#define APBH_CH3_CMD_NANDWAIT4READY_MASK (0x20U)
3251#define APBH_CH3_CMD_NANDWAIT4READY_SHIFT (5U)
3252#define APBH_CH3_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH3_CMD_NANDWAIT4READY_MASK)
3253#define APBH_CH3_CMD_SEMAPHORE_MASK (0x40U)
3254#define APBH_CH3_CMD_SEMAPHORE_SHIFT (6U)
3255#define APBH_CH3_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_SEMAPHORE_SHIFT)) & APBH_CH3_CMD_SEMAPHORE_MASK)
3256#define APBH_CH3_CMD_WAIT4ENDCMD_MASK (0x80U)
3257#define APBH_CH3_CMD_WAIT4ENDCMD_SHIFT (7U)
3258#define APBH_CH3_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH3_CMD_WAIT4ENDCMD_MASK)
3259#define APBH_CH3_CMD_HALTONTERMINATE_MASK (0x100U)
3260#define APBH_CH3_CMD_HALTONTERMINATE_SHIFT (8U)
3261#define APBH_CH3_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH3_CMD_HALTONTERMINATE_MASK)
3262#define APBH_CH3_CMD_CMDWORDS_MASK (0xF000U)
3263#define APBH_CH3_CMD_CMDWORDS_SHIFT (12U)
3264#define APBH_CH3_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CMDWORDS_SHIFT)) & APBH_CH3_CMD_CMDWORDS_MASK)
3265#define APBH_CH3_CMD_XFER_COUNT_MASK (0xFFFF0000U)
3266#define APBH_CH3_CMD_XFER_COUNT_SHIFT (16U)
3267#define APBH_CH3_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_XFER_COUNT_SHIFT)) & APBH_CH3_CMD_XFER_COUNT_MASK)
3268/*! @} */
3269
3270/*! @name CH3_BAR - APBH DMA Channel n Buffer Address Register */
3271/*! @{ */
3272#define APBH_CH3_BAR_ADDRESS_MASK (0xFFFFFFFFU)
3273#define APBH_CH3_BAR_ADDRESS_SHIFT (0U)
3274#define APBH_CH3_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_BAR_ADDRESS_SHIFT)) & APBH_CH3_BAR_ADDRESS_MASK)
3275/*! @} */
3276
3277/*! @name CH3_SEMA - APBH DMA Channel n Semaphore Register */
3278/*! @{ */
3279#define APBH_CH3_SEMA_INCREMENT_SEMA_MASK (0xFFU)
3280#define APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT (0U)
3281#define APBH_CH3_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH3_SEMA_INCREMENT_SEMA_MASK)
3282#define APBH_CH3_SEMA_PHORE_MASK (0xFF0000U)
3283#define APBH_CH3_SEMA_PHORE_SHIFT (16U)
3284#define APBH_CH3_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_PHORE_SHIFT)) & APBH_CH3_SEMA_PHORE_MASK)
3285/*! @} */
3286
3287/*! @name CH3_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
3288/*! @{ */
3289#define APBH_CH3_DEBUG1_STATEMACHINE_MASK (0x1FU)
3290#define APBH_CH3_DEBUG1_STATEMACHINE_SHIFT (0U)
3291/*! STATEMACHINE
3292 * 0b00000..This is the idle state of the DMA state machine.
3293 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
3294 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
3295 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
3296 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
3297 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
3298 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
3299 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
3300 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
3301 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
3302 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3303 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3304 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
3305 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
3306 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
3307 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
3308 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
3309 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
3310 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
3311 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
3312 */
3313#define APBH_CH3_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH3_DEBUG1_STATEMACHINE_MASK)
3314#define APBH_CH3_DEBUG1_RSVD1_MASK (0xFFFE0U)
3315#define APBH_CH3_DEBUG1_RSVD1_SHIFT (5U)
3316#define APBH_CH3_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RSVD1_SHIFT)) & APBH_CH3_DEBUG1_RSVD1_MASK)
3317#define APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
3318#define APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
3319#define APBH_CH3_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK)
3320#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
3321#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
3322#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK)
3323#define APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
3324#define APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
3325#define APBH_CH3_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK)
3326#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
3327#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
3328#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK)
3329#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
3330#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
3331#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK)
3332#define APBH_CH3_DEBUG1_LOCK_MASK (0x2000000U)
3333#define APBH_CH3_DEBUG1_LOCK_SHIFT (25U)
3334#define APBH_CH3_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_LOCK_SHIFT)) & APBH_CH3_DEBUG1_LOCK_MASK)
3335#define APBH_CH3_DEBUG1_READY_MASK (0x4000000U)
3336#define APBH_CH3_DEBUG1_READY_SHIFT (26U)
3337#define APBH_CH3_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_READY_SHIFT)) & APBH_CH3_DEBUG1_READY_MASK)
3338#define APBH_CH3_DEBUG1_SENSE_MASK (0x8000000U)
3339#define APBH_CH3_DEBUG1_SENSE_SHIFT (27U)
3340#define APBH_CH3_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_SENSE_SHIFT)) & APBH_CH3_DEBUG1_SENSE_MASK)
3341#define APBH_CH3_DEBUG1_END_MASK (0x10000000U)
3342#define APBH_CH3_DEBUG1_END_SHIFT (28U)
3343#define APBH_CH3_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_END_SHIFT)) & APBH_CH3_DEBUG1_END_MASK)
3344#define APBH_CH3_DEBUG1_KICK_MASK (0x20000000U)
3345#define APBH_CH3_DEBUG1_KICK_SHIFT (29U)
3346#define APBH_CH3_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_KICK_SHIFT)) & APBH_CH3_DEBUG1_KICK_MASK)
3347#define APBH_CH3_DEBUG1_BURST_MASK (0x40000000U)
3348#define APBH_CH3_DEBUG1_BURST_SHIFT (30U)
3349#define APBH_CH3_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_BURST_SHIFT)) & APBH_CH3_DEBUG1_BURST_MASK)
3350#define APBH_CH3_DEBUG1_REQ_MASK (0x80000000U)
3351#define APBH_CH3_DEBUG1_REQ_SHIFT (31U)
3352#define APBH_CH3_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_REQ_SHIFT)) & APBH_CH3_DEBUG1_REQ_MASK)
3353/*! @} */
3354
3355/*! @name CH3_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
3356/*! @{ */
3357#define APBH_CH3_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
3358#define APBH_CH3_DEBUG2_AHB_BYTES_SHIFT (0U)
3359#define APBH_CH3_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_AHB_BYTES_MASK)
3360#define APBH_CH3_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
3361#define APBH_CH3_DEBUG2_APB_BYTES_SHIFT (16U)
3362#define APBH_CH3_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_APB_BYTES_MASK)
3363/*! @} */
3364
3365/*! @name CH4_CURCMDAR - APBH DMA Channel n Current Command Address Register */
3366/*! @{ */
3367#define APBH_CH4_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3368#define APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT (0U)
3369#define APBH_CH4_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_CURCMDAR_CMD_ADDR_MASK)
3370/*! @} */
3371
3372/*! @name CH4_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
3373/*! @{ */
3374#define APBH_CH4_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3375#define APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT (0U)
3376#define APBH_CH4_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_NXTCMDAR_CMD_ADDR_MASK)
3377/*! @} */
3378
3379/*! @name CH4_CMD - APBH DMA Channel n Command Register */
3380/*! @{ */
3381#define APBH_CH4_CMD_COMMAND_MASK (0x3U)
3382#define APBH_CH4_CMD_COMMAND_SHIFT (0U)
3383/*! COMMAND
3384 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
3385 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
3386 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
3387 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
3388 */
3389#define APBH_CH4_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_COMMAND_SHIFT)) & APBH_CH4_CMD_COMMAND_MASK)
3390#define APBH_CH4_CMD_CHAIN_MASK (0x4U)
3391#define APBH_CH4_CMD_CHAIN_SHIFT (2U)
3392#define APBH_CH4_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CHAIN_SHIFT)) & APBH_CH4_CMD_CHAIN_MASK)
3393#define APBH_CH4_CMD_IRQONCMPLT_MASK (0x8U)
3394#define APBH_CH4_CMD_IRQONCMPLT_SHIFT (3U)
3395#define APBH_CH4_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_IRQONCMPLT_SHIFT)) & APBH_CH4_CMD_IRQONCMPLT_MASK)
3396#define APBH_CH4_CMD_NANDLOCK_MASK (0x10U)
3397#define APBH_CH4_CMD_NANDLOCK_SHIFT (4U)
3398#define APBH_CH4_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDLOCK_SHIFT)) & APBH_CH4_CMD_NANDLOCK_MASK)
3399#define APBH_CH4_CMD_NANDWAIT4READY_MASK (0x20U)
3400#define APBH_CH4_CMD_NANDWAIT4READY_SHIFT (5U)
3401#define APBH_CH4_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH4_CMD_NANDWAIT4READY_MASK)
3402#define APBH_CH4_CMD_SEMAPHORE_MASK (0x40U)
3403#define APBH_CH4_CMD_SEMAPHORE_SHIFT (6U)
3404#define APBH_CH4_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_SEMAPHORE_SHIFT)) & APBH_CH4_CMD_SEMAPHORE_MASK)
3405#define APBH_CH4_CMD_WAIT4ENDCMD_MASK (0x80U)
3406#define APBH_CH4_CMD_WAIT4ENDCMD_SHIFT (7U)
3407#define APBH_CH4_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH4_CMD_WAIT4ENDCMD_MASK)
3408#define APBH_CH4_CMD_HALTONTERMINATE_MASK (0x100U)
3409#define APBH_CH4_CMD_HALTONTERMINATE_SHIFT (8U)
3410#define APBH_CH4_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH4_CMD_HALTONTERMINATE_MASK)
3411#define APBH_CH4_CMD_CMDWORDS_MASK (0xF000U)
3412#define APBH_CH4_CMD_CMDWORDS_SHIFT (12U)
3413#define APBH_CH4_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CMDWORDS_SHIFT)) & APBH_CH4_CMD_CMDWORDS_MASK)
3414#define APBH_CH4_CMD_XFER_COUNT_MASK (0xFFFF0000U)
3415#define APBH_CH4_CMD_XFER_COUNT_SHIFT (16U)
3416#define APBH_CH4_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_XFER_COUNT_SHIFT)) & APBH_CH4_CMD_XFER_COUNT_MASK)
3417/*! @} */
3418
3419/*! @name CH4_BAR - APBH DMA Channel n Buffer Address Register */
3420/*! @{ */
3421#define APBH_CH4_BAR_ADDRESS_MASK (0xFFFFFFFFU)
3422#define APBH_CH4_BAR_ADDRESS_SHIFT (0U)
3423#define APBH_CH4_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_BAR_ADDRESS_SHIFT)) & APBH_CH4_BAR_ADDRESS_MASK)
3424/*! @} */
3425
3426/*! @name CH4_SEMA - APBH DMA Channel n Semaphore Register */
3427/*! @{ */
3428#define APBH_CH4_SEMA_INCREMENT_SEMA_MASK (0xFFU)
3429#define APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT (0U)
3430#define APBH_CH4_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH4_SEMA_INCREMENT_SEMA_MASK)
3431#define APBH_CH4_SEMA_PHORE_MASK (0xFF0000U)
3432#define APBH_CH4_SEMA_PHORE_SHIFT (16U)
3433#define APBH_CH4_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_PHORE_SHIFT)) & APBH_CH4_SEMA_PHORE_MASK)
3434/*! @} */
3435
3436/*! @name CH4_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
3437/*! @{ */
3438#define APBH_CH4_DEBUG1_STATEMACHINE_MASK (0x1FU)
3439#define APBH_CH4_DEBUG1_STATEMACHINE_SHIFT (0U)
3440/*! STATEMACHINE
3441 * 0b00000..This is the idle state of the DMA state machine.
3442 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
3443 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
3444 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
3445 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
3446 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
3447 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
3448 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
3449 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
3450 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
3451 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3452 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3453 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
3454 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
3455 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
3456 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
3457 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
3458 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
3459 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
3460 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
3461 */
3462#define APBH_CH4_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH4_DEBUG1_STATEMACHINE_MASK)
3463#define APBH_CH4_DEBUG1_RSVD1_MASK (0xFFFE0U)
3464#define APBH_CH4_DEBUG1_RSVD1_SHIFT (5U)
3465#define APBH_CH4_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RSVD1_SHIFT)) & APBH_CH4_DEBUG1_RSVD1_MASK)
3466#define APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
3467#define APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
3468#define APBH_CH4_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK)
3469#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
3470#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
3471#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK)
3472#define APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
3473#define APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
3474#define APBH_CH4_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK)
3475#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
3476#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
3477#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK)
3478#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
3479#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
3480#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK)
3481#define APBH_CH4_DEBUG1_LOCK_MASK (0x2000000U)
3482#define APBH_CH4_DEBUG1_LOCK_SHIFT (25U)
3483#define APBH_CH4_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_LOCK_SHIFT)) & APBH_CH4_DEBUG1_LOCK_MASK)
3484#define APBH_CH4_DEBUG1_READY_MASK (0x4000000U)
3485#define APBH_CH4_DEBUG1_READY_SHIFT (26U)
3486#define APBH_CH4_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_READY_SHIFT)) & APBH_CH4_DEBUG1_READY_MASK)
3487#define APBH_CH4_DEBUG1_SENSE_MASK (0x8000000U)
3488#define APBH_CH4_DEBUG1_SENSE_SHIFT (27U)
3489#define APBH_CH4_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_SENSE_SHIFT)) & APBH_CH4_DEBUG1_SENSE_MASK)
3490#define APBH_CH4_DEBUG1_END_MASK (0x10000000U)
3491#define APBH_CH4_DEBUG1_END_SHIFT (28U)
3492#define APBH_CH4_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_END_SHIFT)) & APBH_CH4_DEBUG1_END_MASK)
3493#define APBH_CH4_DEBUG1_KICK_MASK (0x20000000U)
3494#define APBH_CH4_DEBUG1_KICK_SHIFT (29U)
3495#define APBH_CH4_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_KICK_SHIFT)) & APBH_CH4_DEBUG1_KICK_MASK)
3496#define APBH_CH4_DEBUG1_BURST_MASK (0x40000000U)
3497#define APBH_CH4_DEBUG1_BURST_SHIFT (30U)
3498#define APBH_CH4_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_BURST_SHIFT)) & APBH_CH4_DEBUG1_BURST_MASK)
3499#define APBH_CH4_DEBUG1_REQ_MASK (0x80000000U)
3500#define APBH_CH4_DEBUG1_REQ_SHIFT (31U)
3501#define APBH_CH4_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_REQ_SHIFT)) & APBH_CH4_DEBUG1_REQ_MASK)
3502/*! @} */
3503
3504/*! @name CH4_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
3505/*! @{ */
3506#define APBH_CH4_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
3507#define APBH_CH4_DEBUG2_AHB_BYTES_SHIFT (0U)
3508#define APBH_CH4_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_AHB_BYTES_MASK)
3509#define APBH_CH4_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
3510#define APBH_CH4_DEBUG2_APB_BYTES_SHIFT (16U)
3511#define APBH_CH4_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_APB_BYTES_MASK)
3512/*! @} */
3513
3514/*! @name CH5_CURCMDAR - APBH DMA Channel n Current Command Address Register */
3515/*! @{ */
3516#define APBH_CH5_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3517#define APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT (0U)
3518#define APBH_CH5_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_CURCMDAR_CMD_ADDR_MASK)
3519/*! @} */
3520
3521/*! @name CH5_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
3522/*! @{ */
3523#define APBH_CH5_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3524#define APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT (0U)
3525#define APBH_CH5_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_NXTCMDAR_CMD_ADDR_MASK)
3526/*! @} */
3527
3528/*! @name CH5_CMD - APBH DMA Channel n Command Register */
3529/*! @{ */
3530#define APBH_CH5_CMD_COMMAND_MASK (0x3U)
3531#define APBH_CH5_CMD_COMMAND_SHIFT (0U)
3532/*! COMMAND
3533 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
3534 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
3535 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
3536 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
3537 */
3538#define APBH_CH5_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_COMMAND_SHIFT)) & APBH_CH5_CMD_COMMAND_MASK)
3539#define APBH_CH5_CMD_CHAIN_MASK (0x4U)
3540#define APBH_CH5_CMD_CHAIN_SHIFT (2U)
3541#define APBH_CH5_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CHAIN_SHIFT)) & APBH_CH5_CMD_CHAIN_MASK)
3542#define APBH_CH5_CMD_IRQONCMPLT_MASK (0x8U)
3543#define APBH_CH5_CMD_IRQONCMPLT_SHIFT (3U)
3544#define APBH_CH5_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_IRQONCMPLT_SHIFT)) & APBH_CH5_CMD_IRQONCMPLT_MASK)
3545#define APBH_CH5_CMD_NANDLOCK_MASK (0x10U)
3546#define APBH_CH5_CMD_NANDLOCK_SHIFT (4U)
3547#define APBH_CH5_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK)
3548#define APBH_CH5_CMD_NANDWAIT4READY_MASK (0x20U)
3549#define APBH_CH5_CMD_NANDWAIT4READY_SHIFT (5U)
3550#define APBH_CH5_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH5_CMD_NANDWAIT4READY_MASK)
3551#define APBH_CH5_CMD_SEMAPHORE_MASK (0x40U)
3552#define APBH_CH5_CMD_SEMAPHORE_SHIFT (6U)
3553#define APBH_CH5_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_SEMAPHORE_SHIFT)) & APBH_CH5_CMD_SEMAPHORE_MASK)
3554#define APBH_CH5_CMD_WAIT4ENDCMD_MASK (0x80U)
3555#define APBH_CH5_CMD_WAIT4ENDCMD_SHIFT (7U)
3556#define APBH_CH5_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH5_CMD_WAIT4ENDCMD_MASK)
3557#define APBH_CH5_CMD_HALTONTERMINATE_MASK (0x100U)
3558#define APBH_CH5_CMD_HALTONTERMINATE_SHIFT (8U)
3559#define APBH_CH5_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH5_CMD_HALTONTERMINATE_MASK)
3560#define APBH_CH5_CMD_CMDWORDS_MASK (0xF000U)
3561#define APBH_CH5_CMD_CMDWORDS_SHIFT (12U)
3562#define APBH_CH5_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CMDWORDS_SHIFT)) & APBH_CH5_CMD_CMDWORDS_MASK)
3563#define APBH_CH5_CMD_XFER_COUNT_MASK (0xFFFF0000U)
3564#define APBH_CH5_CMD_XFER_COUNT_SHIFT (16U)
3565#define APBH_CH5_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_XFER_COUNT_SHIFT)) & APBH_CH5_CMD_XFER_COUNT_MASK)
3566/*! @} */
3567
3568/*! @name CH5_BAR - APBH DMA Channel n Buffer Address Register */
3569/*! @{ */
3570#define APBH_CH5_BAR_ADDRESS_MASK (0xFFFFFFFFU)
3571#define APBH_CH5_BAR_ADDRESS_SHIFT (0U)
3572#define APBH_CH5_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_BAR_ADDRESS_SHIFT)) & APBH_CH5_BAR_ADDRESS_MASK)
3573/*! @} */
3574
3575/*! @name CH5_SEMA - APBH DMA Channel n Semaphore Register */
3576/*! @{ */
3577#define APBH_CH5_SEMA_INCREMENT_SEMA_MASK (0xFFU)
3578#define APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT (0U)
3579#define APBH_CH5_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH5_SEMA_INCREMENT_SEMA_MASK)
3580#define APBH_CH5_SEMA_PHORE_MASK (0xFF0000U)
3581#define APBH_CH5_SEMA_PHORE_SHIFT (16U)
3582#define APBH_CH5_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_PHORE_SHIFT)) & APBH_CH5_SEMA_PHORE_MASK)
3583/*! @} */
3584
3585/*! @name CH5_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
3586/*! @{ */
3587#define APBH_CH5_DEBUG1_STATEMACHINE_MASK (0x1FU)
3588#define APBH_CH5_DEBUG1_STATEMACHINE_SHIFT (0U)
3589/*! STATEMACHINE
3590 * 0b00000..This is the idle state of the DMA state machine.
3591 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
3592 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
3593 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
3594 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
3595 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
3596 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
3597 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
3598 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
3599 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
3600 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3601 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3602 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
3603 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
3604 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
3605 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
3606 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
3607 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
3608 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
3609 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
3610 */
3611#define APBH_CH5_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH5_DEBUG1_STATEMACHINE_MASK)
3612#define APBH_CH5_DEBUG1_RSVD1_MASK (0xFFFE0U)
3613#define APBH_CH5_DEBUG1_RSVD1_SHIFT (5U)
3614#define APBH_CH5_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RSVD1_SHIFT)) & APBH_CH5_DEBUG1_RSVD1_MASK)
3615#define APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
3616#define APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
3617#define APBH_CH5_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK)
3618#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
3619#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
3620#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK)
3621#define APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
3622#define APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
3623#define APBH_CH5_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK)
3624#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
3625#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
3626#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK)
3627#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
3628#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
3629#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK)
3630#define APBH_CH5_DEBUG1_LOCK_MASK (0x2000000U)
3631#define APBH_CH5_DEBUG1_LOCK_SHIFT (25U)
3632#define APBH_CH5_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_LOCK_SHIFT)) & APBH_CH5_DEBUG1_LOCK_MASK)
3633#define APBH_CH5_DEBUG1_READY_MASK (0x4000000U)
3634#define APBH_CH5_DEBUG1_READY_SHIFT (26U)
3635#define APBH_CH5_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_READY_SHIFT)) & APBH_CH5_DEBUG1_READY_MASK)
3636#define APBH_CH5_DEBUG1_SENSE_MASK (0x8000000U)
3637#define APBH_CH5_DEBUG1_SENSE_SHIFT (27U)
3638#define APBH_CH5_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_SENSE_SHIFT)) & APBH_CH5_DEBUG1_SENSE_MASK)
3639#define APBH_CH5_DEBUG1_END_MASK (0x10000000U)
3640#define APBH_CH5_DEBUG1_END_SHIFT (28U)
3641#define APBH_CH5_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_END_SHIFT)) & APBH_CH5_DEBUG1_END_MASK)
3642#define APBH_CH5_DEBUG1_KICK_MASK (0x20000000U)
3643#define APBH_CH5_DEBUG1_KICK_SHIFT (29U)
3644#define APBH_CH5_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_KICK_SHIFT)) & APBH_CH5_DEBUG1_KICK_MASK)
3645#define APBH_CH5_DEBUG1_BURST_MASK (0x40000000U)
3646#define APBH_CH5_DEBUG1_BURST_SHIFT (30U)
3647#define APBH_CH5_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_BURST_SHIFT)) & APBH_CH5_DEBUG1_BURST_MASK)
3648#define APBH_CH5_DEBUG1_REQ_MASK (0x80000000U)
3649#define APBH_CH5_DEBUG1_REQ_SHIFT (31U)
3650#define APBH_CH5_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_REQ_SHIFT)) & APBH_CH5_DEBUG1_REQ_MASK)
3651/*! @} */
3652
3653/*! @name CH5_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
3654/*! @{ */
3655#define APBH_CH5_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
3656#define APBH_CH5_DEBUG2_AHB_BYTES_SHIFT (0U)
3657#define APBH_CH5_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_AHB_BYTES_MASK)
3658#define APBH_CH5_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
3659#define APBH_CH5_DEBUG2_APB_BYTES_SHIFT (16U)
3660#define APBH_CH5_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_APB_BYTES_MASK)
3661/*! @} */
3662
3663/*! @name CH6_CURCMDAR - APBH DMA Channel n Current Command Address Register */
3664/*! @{ */
3665#define APBH_CH6_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3666#define APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT (0U)
3667#define APBH_CH6_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_CURCMDAR_CMD_ADDR_MASK)
3668/*! @} */
3669
3670/*! @name CH6_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
3671/*! @{ */
3672#define APBH_CH6_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3673#define APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT (0U)
3674#define APBH_CH6_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_NXTCMDAR_CMD_ADDR_MASK)
3675/*! @} */
3676
3677/*! @name CH6_CMD - APBH DMA Channel n Command Register */
3678/*! @{ */
3679#define APBH_CH6_CMD_COMMAND_MASK (0x3U)
3680#define APBH_CH6_CMD_COMMAND_SHIFT (0U)
3681/*! COMMAND
3682 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
3683 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
3684 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
3685 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
3686 */
3687#define APBH_CH6_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_COMMAND_SHIFT)) & APBH_CH6_CMD_COMMAND_MASK)
3688#define APBH_CH6_CMD_CHAIN_MASK (0x4U)
3689#define APBH_CH6_CMD_CHAIN_SHIFT (2U)
3690#define APBH_CH6_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CHAIN_SHIFT)) & APBH_CH6_CMD_CHAIN_MASK)
3691#define APBH_CH6_CMD_IRQONCMPLT_MASK (0x8U)
3692#define APBH_CH6_CMD_IRQONCMPLT_SHIFT (3U)
3693#define APBH_CH6_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_IRQONCMPLT_SHIFT)) & APBH_CH6_CMD_IRQONCMPLT_MASK)
3694#define APBH_CH6_CMD_NANDLOCK_MASK (0x10U)
3695#define APBH_CH6_CMD_NANDLOCK_SHIFT (4U)
3696#define APBH_CH6_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDLOCK_SHIFT)) & APBH_CH6_CMD_NANDLOCK_MASK)
3697#define APBH_CH6_CMD_NANDWAIT4READY_MASK (0x20U)
3698#define APBH_CH6_CMD_NANDWAIT4READY_SHIFT (5U)
3699#define APBH_CH6_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH6_CMD_NANDWAIT4READY_MASK)
3700#define APBH_CH6_CMD_SEMAPHORE_MASK (0x40U)
3701#define APBH_CH6_CMD_SEMAPHORE_SHIFT (6U)
3702#define APBH_CH6_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_SEMAPHORE_SHIFT)) & APBH_CH6_CMD_SEMAPHORE_MASK)
3703#define APBH_CH6_CMD_WAIT4ENDCMD_MASK (0x80U)
3704#define APBH_CH6_CMD_WAIT4ENDCMD_SHIFT (7U)
3705#define APBH_CH6_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH6_CMD_WAIT4ENDCMD_MASK)
3706#define APBH_CH6_CMD_HALTONTERMINATE_MASK (0x100U)
3707#define APBH_CH6_CMD_HALTONTERMINATE_SHIFT (8U)
3708#define APBH_CH6_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH6_CMD_HALTONTERMINATE_MASK)
3709#define APBH_CH6_CMD_CMDWORDS_MASK (0xF000U)
3710#define APBH_CH6_CMD_CMDWORDS_SHIFT (12U)
3711#define APBH_CH6_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CMDWORDS_SHIFT)) & APBH_CH6_CMD_CMDWORDS_MASK)
3712#define APBH_CH6_CMD_XFER_COUNT_MASK (0xFFFF0000U)
3713#define APBH_CH6_CMD_XFER_COUNT_SHIFT (16U)
3714#define APBH_CH6_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_XFER_COUNT_SHIFT)) & APBH_CH6_CMD_XFER_COUNT_MASK)
3715/*! @} */
3716
3717/*! @name CH6_BAR - APBH DMA Channel n Buffer Address Register */
3718/*! @{ */
3719#define APBH_CH6_BAR_ADDRESS_MASK (0xFFFFFFFFU)
3720#define APBH_CH6_BAR_ADDRESS_SHIFT (0U)
3721#define APBH_CH6_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_BAR_ADDRESS_SHIFT)) & APBH_CH6_BAR_ADDRESS_MASK)
3722/*! @} */
3723
3724/*! @name CH6_SEMA - APBH DMA Channel n Semaphore Register */
3725/*! @{ */
3726#define APBH_CH6_SEMA_INCREMENT_SEMA_MASK (0xFFU)
3727#define APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT (0U)
3728#define APBH_CH6_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH6_SEMA_INCREMENT_SEMA_MASK)
3729#define APBH_CH6_SEMA_PHORE_MASK (0xFF0000U)
3730#define APBH_CH6_SEMA_PHORE_SHIFT (16U)
3731#define APBH_CH6_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_PHORE_SHIFT)) & APBH_CH6_SEMA_PHORE_MASK)
3732/*! @} */
3733
3734/*! @name CH6_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
3735/*! @{ */
3736#define APBH_CH6_DEBUG1_STATEMACHINE_MASK (0x1FU)
3737#define APBH_CH6_DEBUG1_STATEMACHINE_SHIFT (0U)
3738/*! STATEMACHINE
3739 * 0b00000..This is the idle state of the DMA state machine.
3740 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
3741 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
3742 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
3743 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
3744 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
3745 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
3746 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
3747 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
3748 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
3749 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3750 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3751 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
3752 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
3753 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
3754 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
3755 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
3756 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
3757 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
3758 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
3759 */
3760#define APBH_CH6_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH6_DEBUG1_STATEMACHINE_MASK)
3761#define APBH_CH6_DEBUG1_RSVD1_MASK (0xFFFE0U)
3762#define APBH_CH6_DEBUG1_RSVD1_SHIFT (5U)
3763#define APBH_CH6_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RSVD1_SHIFT)) & APBH_CH6_DEBUG1_RSVD1_MASK)
3764#define APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
3765#define APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
3766#define APBH_CH6_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK)
3767#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
3768#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
3769#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK)
3770#define APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
3771#define APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
3772#define APBH_CH6_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK)
3773#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
3774#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
3775#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK)
3776#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
3777#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
3778#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK)
3779#define APBH_CH6_DEBUG1_LOCK_MASK (0x2000000U)
3780#define APBH_CH6_DEBUG1_LOCK_SHIFT (25U)
3781#define APBH_CH6_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_LOCK_SHIFT)) & APBH_CH6_DEBUG1_LOCK_MASK)
3782#define APBH_CH6_DEBUG1_READY_MASK (0x4000000U)
3783#define APBH_CH6_DEBUG1_READY_SHIFT (26U)
3784#define APBH_CH6_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_READY_SHIFT)) & APBH_CH6_DEBUG1_READY_MASK)
3785#define APBH_CH6_DEBUG1_SENSE_MASK (0x8000000U)
3786#define APBH_CH6_DEBUG1_SENSE_SHIFT (27U)
3787#define APBH_CH6_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_SENSE_SHIFT)) & APBH_CH6_DEBUG1_SENSE_MASK)
3788#define APBH_CH6_DEBUG1_END_MASK (0x10000000U)
3789#define APBH_CH6_DEBUG1_END_SHIFT (28U)
3790#define APBH_CH6_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_END_SHIFT)) & APBH_CH6_DEBUG1_END_MASK)
3791#define APBH_CH6_DEBUG1_KICK_MASK (0x20000000U)
3792#define APBH_CH6_DEBUG1_KICK_SHIFT (29U)
3793#define APBH_CH6_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_KICK_SHIFT)) & APBH_CH6_DEBUG1_KICK_MASK)
3794#define APBH_CH6_DEBUG1_BURST_MASK (0x40000000U)
3795#define APBH_CH6_DEBUG1_BURST_SHIFT (30U)
3796#define APBH_CH6_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_BURST_SHIFT)) & APBH_CH6_DEBUG1_BURST_MASK)
3797#define APBH_CH6_DEBUG1_REQ_MASK (0x80000000U)
3798#define APBH_CH6_DEBUG1_REQ_SHIFT (31U)
3799#define APBH_CH6_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_REQ_SHIFT)) & APBH_CH6_DEBUG1_REQ_MASK)
3800/*! @} */
3801
3802/*! @name CH6_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
3803/*! @{ */
3804#define APBH_CH6_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
3805#define APBH_CH6_DEBUG2_AHB_BYTES_SHIFT (0U)
3806#define APBH_CH6_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_AHB_BYTES_MASK)
3807#define APBH_CH6_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
3808#define APBH_CH6_DEBUG2_APB_BYTES_SHIFT (16U)
3809#define APBH_CH6_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_APB_BYTES_MASK)
3810/*! @} */
3811
3812/*! @name CH7_CURCMDAR - APBH DMA Channel n Current Command Address Register */
3813/*! @{ */
3814#define APBH_CH7_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3815#define APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT (0U)
3816#define APBH_CH7_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_CURCMDAR_CMD_ADDR_MASK)
3817/*! @} */
3818
3819/*! @name CH7_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
3820/*! @{ */
3821#define APBH_CH7_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3822#define APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT (0U)
3823#define APBH_CH7_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_NXTCMDAR_CMD_ADDR_MASK)
3824/*! @} */
3825
3826/*! @name CH7_CMD - APBH DMA Channel n Command Register */
3827/*! @{ */
3828#define APBH_CH7_CMD_COMMAND_MASK (0x3U)
3829#define APBH_CH7_CMD_COMMAND_SHIFT (0U)
3830/*! COMMAND
3831 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
3832 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
3833 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
3834 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
3835 */
3836#define APBH_CH7_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_COMMAND_SHIFT)) & APBH_CH7_CMD_COMMAND_MASK)
3837#define APBH_CH7_CMD_CHAIN_MASK (0x4U)
3838#define APBH_CH7_CMD_CHAIN_SHIFT (2U)
3839#define APBH_CH7_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CHAIN_SHIFT)) & APBH_CH7_CMD_CHAIN_MASK)
3840#define APBH_CH7_CMD_IRQONCMPLT_MASK (0x8U)
3841#define APBH_CH7_CMD_IRQONCMPLT_SHIFT (3U)
3842#define APBH_CH7_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_IRQONCMPLT_SHIFT)) & APBH_CH7_CMD_IRQONCMPLT_MASK)
3843#define APBH_CH7_CMD_NANDLOCK_MASK (0x10U)
3844#define APBH_CH7_CMD_NANDLOCK_SHIFT (4U)
3845#define APBH_CH7_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_NANDLOCK_SHIFT)) & APBH_CH7_CMD_NANDLOCK_MASK)
3846#define APBH_CH7_CMD_NANDWAIT4READY_MASK (0x20U)
3847#define APBH_CH7_CMD_NANDWAIT4READY_SHIFT (5U)
3848#define APBH_CH7_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH7_CMD_NANDWAIT4READY_MASK)
3849#define APBH_CH7_CMD_SEMAPHORE_MASK (0x40U)
3850#define APBH_CH7_CMD_SEMAPHORE_SHIFT (6U)
3851#define APBH_CH7_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_SEMAPHORE_SHIFT)) & APBH_CH7_CMD_SEMAPHORE_MASK)
3852#define APBH_CH7_CMD_WAIT4ENDCMD_MASK (0x80U)
3853#define APBH_CH7_CMD_WAIT4ENDCMD_SHIFT (7U)
3854#define APBH_CH7_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH7_CMD_WAIT4ENDCMD_MASK)
3855#define APBH_CH7_CMD_HALTONTERMINATE_MASK (0x100U)
3856#define APBH_CH7_CMD_HALTONTERMINATE_SHIFT (8U)
3857#define APBH_CH7_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH7_CMD_HALTONTERMINATE_MASK)
3858#define APBH_CH7_CMD_CMDWORDS_MASK (0xF000U)
3859#define APBH_CH7_CMD_CMDWORDS_SHIFT (12U)
3860#define APBH_CH7_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CMDWORDS_SHIFT)) & APBH_CH7_CMD_CMDWORDS_MASK)
3861#define APBH_CH7_CMD_XFER_COUNT_MASK (0xFFFF0000U)
3862#define APBH_CH7_CMD_XFER_COUNT_SHIFT (16U)
3863#define APBH_CH7_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_XFER_COUNT_SHIFT)) & APBH_CH7_CMD_XFER_COUNT_MASK)
3864/*! @} */
3865
3866/*! @name CH7_BAR - APBH DMA Channel n Buffer Address Register */
3867/*! @{ */
3868#define APBH_CH7_BAR_ADDRESS_MASK (0xFFFFFFFFU)
3869#define APBH_CH7_BAR_ADDRESS_SHIFT (0U)
3870#define APBH_CH7_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_BAR_ADDRESS_SHIFT)) & APBH_CH7_BAR_ADDRESS_MASK)
3871/*! @} */
3872
3873/*! @name CH7_SEMA - APBH DMA Channel n Semaphore Register */
3874/*! @{ */
3875#define APBH_CH7_SEMA_INCREMENT_SEMA_MASK (0xFFU)
3876#define APBH_CH7_SEMA_INCREMENT_SEMA_SHIFT (0U)
3877#define APBH_CH7_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH7_SEMA_INCREMENT_SEMA_MASK)
3878#define APBH_CH7_SEMA_PHORE_MASK (0xFF0000U)
3879#define APBH_CH7_SEMA_PHORE_SHIFT (16U)
3880#define APBH_CH7_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_SEMA_PHORE_SHIFT)) & APBH_CH7_SEMA_PHORE_MASK)
3881/*! @} */
3882
3883/*! @name CH7_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
3884/*! @{ */
3885#define APBH_CH7_DEBUG1_STATEMACHINE_MASK (0x1FU)
3886#define APBH_CH7_DEBUG1_STATEMACHINE_SHIFT (0U)
3887/*! STATEMACHINE
3888 * 0b00000..This is the idle state of the DMA state machine.
3889 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
3890 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
3891 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
3892 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
3893 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
3894 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
3895 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
3896 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
3897 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
3898 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3899 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3900 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
3901 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
3902 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
3903 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
3904 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
3905 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
3906 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
3907 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
3908 */
3909#define APBH_CH7_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH7_DEBUG1_STATEMACHINE_MASK)
3910#define APBH_CH7_DEBUG1_RSVD1_MASK (0xFFFE0U)
3911#define APBH_CH7_DEBUG1_RSVD1_SHIFT (5U)
3912#define APBH_CH7_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RSVD1_SHIFT)) & APBH_CH7_DEBUG1_RSVD1_MASK)
3913#define APBH_CH7_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
3914#define APBH_CH7_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
3915#define APBH_CH7_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH7_DEBUG1_WR_FIFO_FULL_MASK)
3916#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
3917#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
3918#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH7_DEBUG1_WR_FIFO_EMPTY_MASK)
3919#define APBH_CH7_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
3920#define APBH_CH7_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
3921#define APBH_CH7_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH7_DEBUG1_RD_FIFO_FULL_MASK)
3922#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
3923#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
3924#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH7_DEBUG1_RD_FIFO_EMPTY_MASK)
3925#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
3926#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
3927#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH7_DEBUG1_NEXTCMDADDRVALID_MASK)
3928#define APBH_CH7_DEBUG1_LOCK_MASK (0x2000000U)
3929#define APBH_CH7_DEBUG1_LOCK_SHIFT (25U)
3930#define APBH_CH7_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_LOCK_SHIFT)) & APBH_CH7_DEBUG1_LOCK_MASK)
3931#define APBH_CH7_DEBUG1_READY_MASK (0x4000000U)
3932#define APBH_CH7_DEBUG1_READY_SHIFT (26U)
3933#define APBH_CH7_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_READY_SHIFT)) & APBH_CH7_DEBUG1_READY_MASK)
3934#define APBH_CH7_DEBUG1_SENSE_MASK (0x8000000U)
3935#define APBH_CH7_DEBUG1_SENSE_SHIFT (27U)
3936#define APBH_CH7_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_SENSE_SHIFT)) & APBH_CH7_DEBUG1_SENSE_MASK)
3937#define APBH_CH7_DEBUG1_END_MASK (0x10000000U)
3938#define APBH_CH7_DEBUG1_END_SHIFT (28U)
3939#define APBH_CH7_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_END_SHIFT)) & APBH_CH7_DEBUG1_END_MASK)
3940#define APBH_CH7_DEBUG1_KICK_MASK (0x20000000U)
3941#define APBH_CH7_DEBUG1_KICK_SHIFT (29U)
3942#define APBH_CH7_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_KICK_SHIFT)) & APBH_CH7_DEBUG1_KICK_MASK)
3943#define APBH_CH7_DEBUG1_BURST_MASK (0x40000000U)
3944#define APBH_CH7_DEBUG1_BURST_SHIFT (30U)
3945#define APBH_CH7_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_BURST_SHIFT)) & APBH_CH7_DEBUG1_BURST_MASK)
3946#define APBH_CH7_DEBUG1_REQ_MASK (0x80000000U)
3947#define APBH_CH7_DEBUG1_REQ_SHIFT (31U)
3948#define APBH_CH7_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_REQ_SHIFT)) & APBH_CH7_DEBUG1_REQ_MASK)
3949/*! @} */
3950
3951/*! @name CH7_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
3952/*! @{ */
3953#define APBH_CH7_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
3954#define APBH_CH7_DEBUG2_AHB_BYTES_SHIFT (0U)
3955#define APBH_CH7_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH7_DEBUG2_AHB_BYTES_MASK)
3956#define APBH_CH7_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
3957#define APBH_CH7_DEBUG2_APB_BYTES_SHIFT (16U)
3958#define APBH_CH7_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH7_DEBUG2_APB_BYTES_MASK)
3959/*! @} */
3960
3961/*! @name CH8_CURCMDAR - APBH DMA Channel n Current Command Address Register */
3962/*! @{ */
3963#define APBH_CH8_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3964#define APBH_CH8_CURCMDAR_CMD_ADDR_SHIFT (0U)
3965#define APBH_CH8_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH8_CURCMDAR_CMD_ADDR_MASK)
3966/*! @} */
3967
3968/*! @name CH8_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
3969/*! @{ */
3970#define APBH_CH8_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3971#define APBH_CH8_NXTCMDAR_CMD_ADDR_SHIFT (0U)
3972#define APBH_CH8_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH8_NXTCMDAR_CMD_ADDR_MASK)
3973/*! @} */
3974
3975/*! @name CH8_CMD - APBH DMA Channel n Command Register */
3976/*! @{ */
3977#define APBH_CH8_CMD_COMMAND_MASK (0x3U)
3978#define APBH_CH8_CMD_COMMAND_SHIFT (0U)
3979/*! COMMAND
3980 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
3981 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
3982 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
3983 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
3984 */
3985#define APBH_CH8_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_COMMAND_SHIFT)) & APBH_CH8_CMD_COMMAND_MASK)
3986#define APBH_CH8_CMD_CHAIN_MASK (0x4U)
3987#define APBH_CH8_CMD_CHAIN_SHIFT (2U)
3988#define APBH_CH8_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_CHAIN_SHIFT)) & APBH_CH8_CMD_CHAIN_MASK)
3989#define APBH_CH8_CMD_IRQONCMPLT_MASK (0x8U)
3990#define APBH_CH8_CMD_IRQONCMPLT_SHIFT (3U)
3991#define APBH_CH8_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_IRQONCMPLT_SHIFT)) & APBH_CH8_CMD_IRQONCMPLT_MASK)
3992#define APBH_CH8_CMD_NANDLOCK_MASK (0x10U)
3993#define APBH_CH8_CMD_NANDLOCK_SHIFT (4U)
3994#define APBH_CH8_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_NANDLOCK_SHIFT)) & APBH_CH8_CMD_NANDLOCK_MASK)
3995#define APBH_CH8_CMD_NANDWAIT4READY_MASK (0x20U)
3996#define APBH_CH8_CMD_NANDWAIT4READY_SHIFT (5U)
3997#define APBH_CH8_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH8_CMD_NANDWAIT4READY_MASK)
3998#define APBH_CH8_CMD_SEMAPHORE_MASK (0x40U)
3999#define APBH_CH8_CMD_SEMAPHORE_SHIFT (6U)
4000#define APBH_CH8_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_SEMAPHORE_SHIFT)) & APBH_CH8_CMD_SEMAPHORE_MASK)
4001#define APBH_CH8_CMD_WAIT4ENDCMD_MASK (0x80U)
4002#define APBH_CH8_CMD_WAIT4ENDCMD_SHIFT (7U)
4003#define APBH_CH8_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH8_CMD_WAIT4ENDCMD_MASK)
4004#define APBH_CH8_CMD_HALTONTERMINATE_MASK (0x100U)
4005#define APBH_CH8_CMD_HALTONTERMINATE_SHIFT (8U)
4006#define APBH_CH8_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH8_CMD_HALTONTERMINATE_MASK)
4007#define APBH_CH8_CMD_CMDWORDS_MASK (0xF000U)
4008#define APBH_CH8_CMD_CMDWORDS_SHIFT (12U)
4009#define APBH_CH8_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_CMDWORDS_SHIFT)) & APBH_CH8_CMD_CMDWORDS_MASK)
4010#define APBH_CH8_CMD_XFER_COUNT_MASK (0xFFFF0000U)
4011#define APBH_CH8_CMD_XFER_COUNT_SHIFT (16U)
4012#define APBH_CH8_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_XFER_COUNT_SHIFT)) & APBH_CH8_CMD_XFER_COUNT_MASK)
4013/*! @} */
4014
4015/*! @name CH8_BAR - APBH DMA Channel n Buffer Address Register */
4016/*! @{ */
4017#define APBH_CH8_BAR_ADDRESS_MASK (0xFFFFFFFFU)
4018#define APBH_CH8_BAR_ADDRESS_SHIFT (0U)
4019#define APBH_CH8_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_BAR_ADDRESS_SHIFT)) & APBH_CH8_BAR_ADDRESS_MASK)
4020/*! @} */
4021
4022/*! @name CH8_SEMA - APBH DMA Channel n Semaphore Register */
4023/*! @{ */
4024#define APBH_CH8_SEMA_INCREMENT_SEMA_MASK (0xFFU)
4025#define APBH_CH8_SEMA_INCREMENT_SEMA_SHIFT (0U)
4026#define APBH_CH8_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH8_SEMA_INCREMENT_SEMA_MASK)
4027#define APBH_CH8_SEMA_PHORE_MASK (0xFF0000U)
4028#define APBH_CH8_SEMA_PHORE_SHIFT (16U)
4029#define APBH_CH8_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_SEMA_PHORE_SHIFT)) & APBH_CH8_SEMA_PHORE_MASK)
4030/*! @} */
4031
4032/*! @name CH8_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
4033/*! @{ */
4034#define APBH_CH8_DEBUG1_STATEMACHINE_MASK (0x1FU)
4035#define APBH_CH8_DEBUG1_STATEMACHINE_SHIFT (0U)
4036/*! STATEMACHINE
4037 * 0b00000..This is the idle state of the DMA state machine.
4038 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
4039 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
4040 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
4041 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
4042 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
4043 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
4044 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
4045 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
4046 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
4047 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
4048 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
4049 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
4050 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
4051 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
4052 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
4053 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
4054 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
4055 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
4056 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
4057 */
4058#define APBH_CH8_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH8_DEBUG1_STATEMACHINE_MASK)
4059#define APBH_CH8_DEBUG1_RSVD1_MASK (0xFFFE0U)
4060#define APBH_CH8_DEBUG1_RSVD1_SHIFT (5U)
4061#define APBH_CH8_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RSVD1_SHIFT)) & APBH_CH8_DEBUG1_RSVD1_MASK)
4062#define APBH_CH8_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
4063#define APBH_CH8_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
4064#define APBH_CH8_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH8_DEBUG1_WR_FIFO_FULL_MASK)
4065#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
4066#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
4067#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH8_DEBUG1_WR_FIFO_EMPTY_MASK)
4068#define APBH_CH8_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
4069#define APBH_CH8_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
4070#define APBH_CH8_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH8_DEBUG1_RD_FIFO_FULL_MASK)
4071#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
4072#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
4073#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH8_DEBUG1_RD_FIFO_EMPTY_MASK)
4074#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
4075#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
4076#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH8_DEBUG1_NEXTCMDADDRVALID_MASK)
4077#define APBH_CH8_DEBUG1_LOCK_MASK (0x2000000U)
4078#define APBH_CH8_DEBUG1_LOCK_SHIFT (25U)
4079#define APBH_CH8_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_LOCK_SHIFT)) & APBH_CH8_DEBUG1_LOCK_MASK)
4080#define APBH_CH8_DEBUG1_READY_MASK (0x4000000U)
4081#define APBH_CH8_DEBUG1_READY_SHIFT (26U)
4082#define APBH_CH8_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_READY_SHIFT)) & APBH_CH8_DEBUG1_READY_MASK)
4083#define APBH_CH8_DEBUG1_SENSE_MASK (0x8000000U)
4084#define APBH_CH8_DEBUG1_SENSE_SHIFT (27U)
4085#define APBH_CH8_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_SENSE_SHIFT)) & APBH_CH8_DEBUG1_SENSE_MASK)
4086#define APBH_CH8_DEBUG1_END_MASK (0x10000000U)
4087#define APBH_CH8_DEBUG1_END_SHIFT (28U)
4088#define APBH_CH8_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_END_SHIFT)) & APBH_CH8_DEBUG1_END_MASK)
4089#define APBH_CH8_DEBUG1_KICK_MASK (0x20000000U)
4090#define APBH_CH8_DEBUG1_KICK_SHIFT (29U)
4091#define APBH_CH8_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_KICK_SHIFT)) & APBH_CH8_DEBUG1_KICK_MASK)
4092#define APBH_CH8_DEBUG1_BURST_MASK (0x40000000U)
4093#define APBH_CH8_DEBUG1_BURST_SHIFT (30U)
4094#define APBH_CH8_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_BURST_SHIFT)) & APBH_CH8_DEBUG1_BURST_MASK)
4095#define APBH_CH8_DEBUG1_REQ_MASK (0x80000000U)
4096#define APBH_CH8_DEBUG1_REQ_SHIFT (31U)
4097#define APBH_CH8_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_REQ_SHIFT)) & APBH_CH8_DEBUG1_REQ_MASK)
4098/*! @} */
4099
4100/*! @name CH8_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
4101/*! @{ */
4102#define APBH_CH8_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
4103#define APBH_CH8_DEBUG2_AHB_BYTES_SHIFT (0U)
4104#define APBH_CH8_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH8_DEBUG2_AHB_BYTES_MASK)
4105#define APBH_CH8_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
4106#define APBH_CH8_DEBUG2_APB_BYTES_SHIFT (16U)
4107#define APBH_CH8_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH8_DEBUG2_APB_BYTES_MASK)
4108/*! @} */
4109
4110/*! @name CH9_CURCMDAR - APBH DMA Channel n Current Command Address Register */
4111/*! @{ */
4112#define APBH_CH9_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
4113#define APBH_CH9_CURCMDAR_CMD_ADDR_SHIFT (0U)
4114#define APBH_CH9_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH9_CURCMDAR_CMD_ADDR_MASK)
4115/*! @} */
4116
4117/*! @name CH9_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
4118/*! @{ */
4119#define APBH_CH9_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
4120#define APBH_CH9_NXTCMDAR_CMD_ADDR_SHIFT (0U)
4121#define APBH_CH9_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH9_NXTCMDAR_CMD_ADDR_MASK)
4122/*! @} */
4123
4124/*! @name CH9_CMD - APBH DMA Channel n Command Register */
4125/*! @{ */
4126#define APBH_CH9_CMD_COMMAND_MASK (0x3U)
4127#define APBH_CH9_CMD_COMMAND_SHIFT (0U)
4128/*! COMMAND
4129 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
4130 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
4131 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
4132 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
4133 */
4134#define APBH_CH9_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_COMMAND_SHIFT)) & APBH_CH9_CMD_COMMAND_MASK)
4135#define APBH_CH9_CMD_CHAIN_MASK (0x4U)
4136#define APBH_CH9_CMD_CHAIN_SHIFT (2U)
4137#define APBH_CH9_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_CHAIN_SHIFT)) & APBH_CH9_CMD_CHAIN_MASK)
4138#define APBH_CH9_CMD_IRQONCMPLT_MASK (0x8U)
4139#define APBH_CH9_CMD_IRQONCMPLT_SHIFT (3U)
4140#define APBH_CH9_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_IRQONCMPLT_SHIFT)) & APBH_CH9_CMD_IRQONCMPLT_MASK)
4141#define APBH_CH9_CMD_NANDLOCK_MASK (0x10U)
4142#define APBH_CH9_CMD_NANDLOCK_SHIFT (4U)
4143#define APBH_CH9_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_NANDLOCK_SHIFT)) & APBH_CH9_CMD_NANDLOCK_MASK)
4144#define APBH_CH9_CMD_NANDWAIT4READY_MASK (0x20U)
4145#define APBH_CH9_CMD_NANDWAIT4READY_SHIFT (5U)
4146#define APBH_CH9_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH9_CMD_NANDWAIT4READY_MASK)
4147#define APBH_CH9_CMD_SEMAPHORE_MASK (0x40U)
4148#define APBH_CH9_CMD_SEMAPHORE_SHIFT (6U)
4149#define APBH_CH9_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_SEMAPHORE_SHIFT)) & APBH_CH9_CMD_SEMAPHORE_MASK)
4150#define APBH_CH9_CMD_WAIT4ENDCMD_MASK (0x80U)
4151#define APBH_CH9_CMD_WAIT4ENDCMD_SHIFT (7U)
4152#define APBH_CH9_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH9_CMD_WAIT4ENDCMD_MASK)
4153#define APBH_CH9_CMD_HALTONTERMINATE_MASK (0x100U)
4154#define APBH_CH9_CMD_HALTONTERMINATE_SHIFT (8U)
4155#define APBH_CH9_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH9_CMD_HALTONTERMINATE_MASK)
4156#define APBH_CH9_CMD_CMDWORDS_MASK (0xF000U)
4157#define APBH_CH9_CMD_CMDWORDS_SHIFT (12U)
4158#define APBH_CH9_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_CMDWORDS_SHIFT)) & APBH_CH9_CMD_CMDWORDS_MASK)
4159#define APBH_CH9_CMD_XFER_COUNT_MASK (0xFFFF0000U)
4160#define APBH_CH9_CMD_XFER_COUNT_SHIFT (16U)
4161#define APBH_CH9_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_XFER_COUNT_SHIFT)) & APBH_CH9_CMD_XFER_COUNT_MASK)
4162/*! @} */
4163
4164/*! @name CH9_BAR - APBH DMA Channel n Buffer Address Register */
4165/*! @{ */
4166#define APBH_CH9_BAR_ADDRESS_MASK (0xFFFFFFFFU)
4167#define APBH_CH9_BAR_ADDRESS_SHIFT (0U)
4168#define APBH_CH9_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_BAR_ADDRESS_SHIFT)) & APBH_CH9_BAR_ADDRESS_MASK)
4169/*! @} */
4170
4171/*! @name CH9_SEMA - APBH DMA Channel n Semaphore Register */
4172/*! @{ */
4173#define APBH_CH9_SEMA_INCREMENT_SEMA_MASK (0xFFU)
4174#define APBH_CH9_SEMA_INCREMENT_SEMA_SHIFT (0U)
4175#define APBH_CH9_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH9_SEMA_INCREMENT_SEMA_MASK)
4176#define APBH_CH9_SEMA_PHORE_MASK (0xFF0000U)
4177#define APBH_CH9_SEMA_PHORE_SHIFT (16U)
4178#define APBH_CH9_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_SEMA_PHORE_SHIFT)) & APBH_CH9_SEMA_PHORE_MASK)
4179/*! @} */
4180
4181/*! @name CH9_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
4182/*! @{ */
4183#define APBH_CH9_DEBUG1_STATEMACHINE_MASK (0x1FU)
4184#define APBH_CH9_DEBUG1_STATEMACHINE_SHIFT (0U)
4185/*! STATEMACHINE
4186 * 0b00000..This is the idle state of the DMA state machine.
4187 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
4188 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
4189 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
4190 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
4191 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
4192 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
4193 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
4194 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
4195 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
4196 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
4197 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
4198 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
4199 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
4200 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
4201 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
4202 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
4203 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
4204 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
4205 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
4206 */
4207#define APBH_CH9_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH9_DEBUG1_STATEMACHINE_MASK)
4208#define APBH_CH9_DEBUG1_RSVD1_MASK (0xFFFE0U)
4209#define APBH_CH9_DEBUG1_RSVD1_SHIFT (5U)
4210#define APBH_CH9_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RSVD1_SHIFT)) & APBH_CH9_DEBUG1_RSVD1_MASK)
4211#define APBH_CH9_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
4212#define APBH_CH9_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
4213#define APBH_CH9_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH9_DEBUG1_WR_FIFO_FULL_MASK)
4214#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
4215#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
4216#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH9_DEBUG1_WR_FIFO_EMPTY_MASK)
4217#define APBH_CH9_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
4218#define APBH_CH9_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
4219#define APBH_CH9_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH9_DEBUG1_RD_FIFO_FULL_MASK)
4220#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
4221#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
4222#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH9_DEBUG1_RD_FIFO_EMPTY_MASK)
4223#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
4224#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
4225#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH9_DEBUG1_NEXTCMDADDRVALID_MASK)
4226#define APBH_CH9_DEBUG1_LOCK_MASK (0x2000000U)
4227#define APBH_CH9_DEBUG1_LOCK_SHIFT (25U)
4228#define APBH_CH9_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_LOCK_SHIFT)) & APBH_CH9_DEBUG1_LOCK_MASK)
4229#define APBH_CH9_DEBUG1_READY_MASK (0x4000000U)
4230#define APBH_CH9_DEBUG1_READY_SHIFT (26U)
4231#define APBH_CH9_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_READY_SHIFT)) & APBH_CH9_DEBUG1_READY_MASK)
4232#define APBH_CH9_DEBUG1_SENSE_MASK (0x8000000U)
4233#define APBH_CH9_DEBUG1_SENSE_SHIFT (27U)
4234#define APBH_CH9_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_SENSE_SHIFT)) & APBH_CH9_DEBUG1_SENSE_MASK)
4235#define APBH_CH9_DEBUG1_END_MASK (0x10000000U)
4236#define APBH_CH9_DEBUG1_END_SHIFT (28U)
4237#define APBH_CH9_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_END_SHIFT)) & APBH_CH9_DEBUG1_END_MASK)
4238#define APBH_CH9_DEBUG1_KICK_MASK (0x20000000U)
4239#define APBH_CH9_DEBUG1_KICK_SHIFT (29U)
4240#define APBH_CH9_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_KICK_SHIFT)) & APBH_CH9_DEBUG1_KICK_MASK)
4241#define APBH_CH9_DEBUG1_BURST_MASK (0x40000000U)
4242#define APBH_CH9_DEBUG1_BURST_SHIFT (30U)
4243#define APBH_CH9_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_BURST_SHIFT)) & APBH_CH9_DEBUG1_BURST_MASK)
4244#define APBH_CH9_DEBUG1_REQ_MASK (0x80000000U)
4245#define APBH_CH9_DEBUG1_REQ_SHIFT (31U)
4246#define APBH_CH9_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_REQ_SHIFT)) & APBH_CH9_DEBUG1_REQ_MASK)
4247/*! @} */
4248
4249/*! @name CH9_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
4250/*! @{ */
4251#define APBH_CH9_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
4252#define APBH_CH9_DEBUG2_AHB_BYTES_SHIFT (0U)
4253#define APBH_CH9_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH9_DEBUG2_AHB_BYTES_MASK)
4254#define APBH_CH9_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
4255#define APBH_CH9_DEBUG2_APB_BYTES_SHIFT (16U)
4256#define APBH_CH9_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH9_DEBUG2_APB_BYTES_MASK)
4257/*! @} */
4258
4259/*! @name CH10_CURCMDAR - APBH DMA Channel n Current Command Address Register */
4260/*! @{ */
4261#define APBH_CH10_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
4262#define APBH_CH10_CURCMDAR_CMD_ADDR_SHIFT (0U)
4263#define APBH_CH10_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH10_CURCMDAR_CMD_ADDR_MASK)
4264/*! @} */
4265
4266/*! @name CH10_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
4267/*! @{ */
4268#define APBH_CH10_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
4269#define APBH_CH10_NXTCMDAR_CMD_ADDR_SHIFT (0U)
4270#define APBH_CH10_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH10_NXTCMDAR_CMD_ADDR_MASK)
4271/*! @} */
4272
4273/*! @name CH10_CMD - APBH DMA Channel n Command Register */
4274/*! @{ */
4275#define APBH_CH10_CMD_COMMAND_MASK (0x3U)
4276#define APBH_CH10_CMD_COMMAND_SHIFT (0U)
4277/*! COMMAND
4278 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
4279 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
4280 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
4281 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
4282 */
4283#define APBH_CH10_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_COMMAND_SHIFT)) & APBH_CH10_CMD_COMMAND_MASK)
4284#define APBH_CH10_CMD_CHAIN_MASK (0x4U)
4285#define APBH_CH10_CMD_CHAIN_SHIFT (2U)
4286#define APBH_CH10_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_CHAIN_SHIFT)) & APBH_CH10_CMD_CHAIN_MASK)
4287#define APBH_CH10_CMD_IRQONCMPLT_MASK (0x8U)
4288#define APBH_CH10_CMD_IRQONCMPLT_SHIFT (3U)
4289#define APBH_CH10_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_IRQONCMPLT_SHIFT)) & APBH_CH10_CMD_IRQONCMPLT_MASK)
4290#define APBH_CH10_CMD_NANDLOCK_MASK (0x10U)
4291#define APBH_CH10_CMD_NANDLOCK_SHIFT (4U)
4292#define APBH_CH10_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_NANDLOCK_SHIFT)) & APBH_CH10_CMD_NANDLOCK_MASK)
4293#define APBH_CH10_CMD_NANDWAIT4READY_MASK (0x20U)
4294#define APBH_CH10_CMD_NANDWAIT4READY_SHIFT (5U)
4295#define APBH_CH10_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH10_CMD_NANDWAIT4READY_MASK)
4296#define APBH_CH10_CMD_SEMAPHORE_MASK (0x40U)
4297#define APBH_CH10_CMD_SEMAPHORE_SHIFT (6U)
4298#define APBH_CH10_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_SEMAPHORE_SHIFT)) & APBH_CH10_CMD_SEMAPHORE_MASK)
4299#define APBH_CH10_CMD_WAIT4ENDCMD_MASK (0x80U)
4300#define APBH_CH10_CMD_WAIT4ENDCMD_SHIFT (7U)
4301#define APBH_CH10_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH10_CMD_WAIT4ENDCMD_MASK)
4302#define APBH_CH10_CMD_HALTONTERMINATE_MASK (0x100U)
4303#define APBH_CH10_CMD_HALTONTERMINATE_SHIFT (8U)
4304#define APBH_CH10_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH10_CMD_HALTONTERMINATE_MASK)
4305#define APBH_CH10_CMD_CMDWORDS_MASK (0xF000U)
4306#define APBH_CH10_CMD_CMDWORDS_SHIFT (12U)
4307#define APBH_CH10_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_CMDWORDS_SHIFT)) & APBH_CH10_CMD_CMDWORDS_MASK)
4308#define APBH_CH10_CMD_XFER_COUNT_MASK (0xFFFF0000U)
4309#define APBH_CH10_CMD_XFER_COUNT_SHIFT (16U)
4310#define APBH_CH10_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_XFER_COUNT_SHIFT)) & APBH_CH10_CMD_XFER_COUNT_MASK)
4311/*! @} */
4312
4313/*! @name CH10_BAR - APBH DMA Channel n Buffer Address Register */
4314/*! @{ */
4315#define APBH_CH10_BAR_ADDRESS_MASK (0xFFFFFFFFU)
4316#define APBH_CH10_BAR_ADDRESS_SHIFT (0U)
4317#define APBH_CH10_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_BAR_ADDRESS_SHIFT)) & APBH_CH10_BAR_ADDRESS_MASK)
4318/*! @} */
4319
4320/*! @name CH10_SEMA - APBH DMA Channel n Semaphore Register */
4321/*! @{ */
4322#define APBH_CH10_SEMA_INCREMENT_SEMA_MASK (0xFFU)
4323#define APBH_CH10_SEMA_INCREMENT_SEMA_SHIFT (0U)
4324#define APBH_CH10_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH10_SEMA_INCREMENT_SEMA_MASK)
4325#define APBH_CH10_SEMA_PHORE_MASK (0xFF0000U)
4326#define APBH_CH10_SEMA_PHORE_SHIFT (16U)
4327#define APBH_CH10_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_SEMA_PHORE_SHIFT)) & APBH_CH10_SEMA_PHORE_MASK)
4328/*! @} */
4329
4330/*! @name CH10_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
4331/*! @{ */
4332#define APBH_CH10_DEBUG1_STATEMACHINE_MASK (0x1FU)
4333#define APBH_CH10_DEBUG1_STATEMACHINE_SHIFT (0U)
4334/*! STATEMACHINE
4335 * 0b00000..This is the idle state of the DMA state machine.
4336 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
4337 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
4338 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
4339 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
4340 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
4341 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
4342 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
4343 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
4344 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
4345 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
4346 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
4347 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
4348 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
4349 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
4350 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
4351 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
4352 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
4353 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
4354 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
4355 */
4356#define APBH_CH10_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH10_DEBUG1_STATEMACHINE_MASK)
4357#define APBH_CH10_DEBUG1_RSVD1_MASK (0xFFFE0U)
4358#define APBH_CH10_DEBUG1_RSVD1_SHIFT (5U)
4359#define APBH_CH10_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RSVD1_SHIFT)) & APBH_CH10_DEBUG1_RSVD1_MASK)
4360#define APBH_CH10_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
4361#define APBH_CH10_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
4362#define APBH_CH10_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH10_DEBUG1_WR_FIFO_FULL_MASK)
4363#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
4364#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
4365#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH10_DEBUG1_WR_FIFO_EMPTY_MASK)
4366#define APBH_CH10_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
4367#define APBH_CH10_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
4368#define APBH_CH10_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH10_DEBUG1_RD_FIFO_FULL_MASK)
4369#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
4370#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
4371#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH10_DEBUG1_RD_FIFO_EMPTY_MASK)
4372#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
4373#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
4374#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH10_DEBUG1_NEXTCMDADDRVALID_MASK)
4375#define APBH_CH10_DEBUG1_LOCK_MASK (0x2000000U)
4376#define APBH_CH10_DEBUG1_LOCK_SHIFT (25U)
4377#define APBH_CH10_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_LOCK_SHIFT)) & APBH_CH10_DEBUG1_LOCK_MASK)
4378#define APBH_CH10_DEBUG1_READY_MASK (0x4000000U)
4379#define APBH_CH10_DEBUG1_READY_SHIFT (26U)
4380#define APBH_CH10_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_READY_SHIFT)) & APBH_CH10_DEBUG1_READY_MASK)
4381#define APBH_CH10_DEBUG1_SENSE_MASK (0x8000000U)
4382#define APBH_CH10_DEBUG1_SENSE_SHIFT (27U)
4383#define APBH_CH10_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_SENSE_SHIFT)) & APBH_CH10_DEBUG1_SENSE_MASK)
4384#define APBH_CH10_DEBUG1_END_MASK (0x10000000U)
4385#define APBH_CH10_DEBUG1_END_SHIFT (28U)
4386#define APBH_CH10_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_END_SHIFT)) & APBH_CH10_DEBUG1_END_MASK)
4387#define APBH_CH10_DEBUG1_KICK_MASK (0x20000000U)
4388#define APBH_CH10_DEBUG1_KICK_SHIFT (29U)
4389#define APBH_CH10_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_KICK_SHIFT)) & APBH_CH10_DEBUG1_KICK_MASK)
4390#define APBH_CH10_DEBUG1_BURST_MASK (0x40000000U)
4391#define APBH_CH10_DEBUG1_BURST_SHIFT (30U)
4392#define APBH_CH10_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_BURST_SHIFT)) & APBH_CH10_DEBUG1_BURST_MASK)
4393#define APBH_CH10_DEBUG1_REQ_MASK (0x80000000U)
4394#define APBH_CH10_DEBUG1_REQ_SHIFT (31U)
4395#define APBH_CH10_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_REQ_SHIFT)) & APBH_CH10_DEBUG1_REQ_MASK)
4396/*! @} */
4397
4398/*! @name CH10_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
4399/*! @{ */
4400#define APBH_CH10_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
4401#define APBH_CH10_DEBUG2_AHB_BYTES_SHIFT (0U)
4402#define APBH_CH10_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH10_DEBUG2_AHB_BYTES_MASK)
4403#define APBH_CH10_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
4404#define APBH_CH10_DEBUG2_APB_BYTES_SHIFT (16U)
4405#define APBH_CH10_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH10_DEBUG2_APB_BYTES_MASK)
4406/*! @} */
4407
4408/*! @name CH11_CURCMDAR - APBH DMA Channel n Current Command Address Register */
4409/*! @{ */
4410#define APBH_CH11_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
4411#define APBH_CH11_CURCMDAR_CMD_ADDR_SHIFT (0U)
4412#define APBH_CH11_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH11_CURCMDAR_CMD_ADDR_MASK)
4413/*! @} */
4414
4415/*! @name CH11_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
4416/*! @{ */
4417#define APBH_CH11_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
4418#define APBH_CH11_NXTCMDAR_CMD_ADDR_SHIFT (0U)
4419#define APBH_CH11_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH11_NXTCMDAR_CMD_ADDR_MASK)
4420/*! @} */
4421
4422/*! @name CH11_CMD - APBH DMA Channel n Command Register */
4423/*! @{ */
4424#define APBH_CH11_CMD_COMMAND_MASK (0x3U)
4425#define APBH_CH11_CMD_COMMAND_SHIFT (0U)
4426/*! COMMAND
4427 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
4428 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
4429 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
4430 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
4431 */
4432#define APBH_CH11_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_COMMAND_SHIFT)) & APBH_CH11_CMD_COMMAND_MASK)
4433#define APBH_CH11_CMD_CHAIN_MASK (0x4U)
4434#define APBH_CH11_CMD_CHAIN_SHIFT (2U)
4435#define APBH_CH11_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_CHAIN_SHIFT)) & APBH_CH11_CMD_CHAIN_MASK)
4436#define APBH_CH11_CMD_IRQONCMPLT_MASK (0x8U)
4437#define APBH_CH11_CMD_IRQONCMPLT_SHIFT (3U)
4438#define APBH_CH11_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_IRQONCMPLT_SHIFT)) & APBH_CH11_CMD_IRQONCMPLT_MASK)
4439#define APBH_CH11_CMD_NANDLOCK_MASK (0x10U)
4440#define APBH_CH11_CMD_NANDLOCK_SHIFT (4U)
4441#define APBH_CH11_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_NANDLOCK_SHIFT)) & APBH_CH11_CMD_NANDLOCK_MASK)
4442#define APBH_CH11_CMD_NANDWAIT4READY_MASK (0x20U)
4443#define APBH_CH11_CMD_NANDWAIT4READY_SHIFT (5U)
4444#define APBH_CH11_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH11_CMD_NANDWAIT4READY_MASK)
4445#define APBH_CH11_CMD_SEMAPHORE_MASK (0x40U)
4446#define APBH_CH11_CMD_SEMAPHORE_SHIFT (6U)
4447#define APBH_CH11_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_SEMAPHORE_SHIFT)) & APBH_CH11_CMD_SEMAPHORE_MASK)
4448#define APBH_CH11_CMD_WAIT4ENDCMD_MASK (0x80U)
4449#define APBH_CH11_CMD_WAIT4ENDCMD_SHIFT (7U)
4450#define APBH_CH11_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH11_CMD_WAIT4ENDCMD_MASK)
4451#define APBH_CH11_CMD_HALTONTERMINATE_MASK (0x100U)
4452#define APBH_CH11_CMD_HALTONTERMINATE_SHIFT (8U)
4453#define APBH_CH11_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH11_CMD_HALTONTERMINATE_MASK)
4454#define APBH_CH11_CMD_CMDWORDS_MASK (0xF000U)
4455#define APBH_CH11_CMD_CMDWORDS_SHIFT (12U)
4456#define APBH_CH11_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_CMDWORDS_SHIFT)) & APBH_CH11_CMD_CMDWORDS_MASK)
4457#define APBH_CH11_CMD_XFER_COUNT_MASK (0xFFFF0000U)
4458#define APBH_CH11_CMD_XFER_COUNT_SHIFT (16U)
4459#define APBH_CH11_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_XFER_COUNT_SHIFT)) & APBH_CH11_CMD_XFER_COUNT_MASK)
4460/*! @} */
4461
4462/*! @name CH11_BAR - APBH DMA Channel n Buffer Address Register */
4463/*! @{ */
4464#define APBH_CH11_BAR_ADDRESS_MASK (0xFFFFFFFFU)
4465#define APBH_CH11_BAR_ADDRESS_SHIFT (0U)
4466#define APBH_CH11_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_BAR_ADDRESS_SHIFT)) & APBH_CH11_BAR_ADDRESS_MASK)
4467/*! @} */
4468
4469/*! @name CH11_SEMA - APBH DMA Channel n Semaphore Register */
4470/*! @{ */
4471#define APBH_CH11_SEMA_INCREMENT_SEMA_MASK (0xFFU)
4472#define APBH_CH11_SEMA_INCREMENT_SEMA_SHIFT (0U)
4473#define APBH_CH11_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH11_SEMA_INCREMENT_SEMA_MASK)
4474#define APBH_CH11_SEMA_PHORE_MASK (0xFF0000U)
4475#define APBH_CH11_SEMA_PHORE_SHIFT (16U)
4476#define APBH_CH11_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_SEMA_PHORE_SHIFT)) & APBH_CH11_SEMA_PHORE_MASK)
4477/*! @} */
4478
4479/*! @name CH11_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
4480/*! @{ */
4481#define APBH_CH11_DEBUG1_STATEMACHINE_MASK (0x1FU)
4482#define APBH_CH11_DEBUG1_STATEMACHINE_SHIFT (0U)
4483/*! STATEMACHINE
4484 * 0b00000..This is the idle state of the DMA state machine.
4485 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
4486 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
4487 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
4488 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
4489 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
4490 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
4491 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
4492 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
4493 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
4494 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
4495 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
4496 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
4497 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
4498 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
4499 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
4500 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
4501 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
4502 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
4503 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
4504 */
4505#define APBH_CH11_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH11_DEBUG1_STATEMACHINE_MASK)
4506#define APBH_CH11_DEBUG1_RSVD1_MASK (0xFFFE0U)
4507#define APBH_CH11_DEBUG1_RSVD1_SHIFT (5U)
4508#define APBH_CH11_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RSVD1_SHIFT)) & APBH_CH11_DEBUG1_RSVD1_MASK)
4509#define APBH_CH11_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
4510#define APBH_CH11_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
4511#define APBH_CH11_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH11_DEBUG1_WR_FIFO_FULL_MASK)
4512#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
4513#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
4514#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH11_DEBUG1_WR_FIFO_EMPTY_MASK)
4515#define APBH_CH11_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
4516#define APBH_CH11_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
4517#define APBH_CH11_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH11_DEBUG1_RD_FIFO_FULL_MASK)
4518#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
4519#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
4520#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH11_DEBUG1_RD_FIFO_EMPTY_MASK)
4521#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
4522#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
4523#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH11_DEBUG1_NEXTCMDADDRVALID_MASK)
4524#define APBH_CH11_DEBUG1_LOCK_MASK (0x2000000U)
4525#define APBH_CH11_DEBUG1_LOCK_SHIFT (25U)
4526#define APBH_CH11_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_LOCK_SHIFT)) & APBH_CH11_DEBUG1_LOCK_MASK)
4527#define APBH_CH11_DEBUG1_READY_MASK (0x4000000U)
4528#define APBH_CH11_DEBUG1_READY_SHIFT (26U)
4529#define APBH_CH11_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_READY_SHIFT)) & APBH_CH11_DEBUG1_READY_MASK)
4530#define APBH_CH11_DEBUG1_SENSE_MASK (0x8000000U)
4531#define APBH_CH11_DEBUG1_SENSE_SHIFT (27U)
4532#define APBH_CH11_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_SENSE_SHIFT)) & APBH_CH11_DEBUG1_SENSE_MASK)
4533#define APBH_CH11_DEBUG1_END_MASK (0x10000000U)
4534#define APBH_CH11_DEBUG1_END_SHIFT (28U)
4535#define APBH_CH11_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_END_SHIFT)) & APBH_CH11_DEBUG1_END_MASK)
4536#define APBH_CH11_DEBUG1_KICK_MASK (0x20000000U)
4537#define APBH_CH11_DEBUG1_KICK_SHIFT (29U)
4538#define APBH_CH11_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_KICK_SHIFT)) & APBH_CH11_DEBUG1_KICK_MASK)
4539#define APBH_CH11_DEBUG1_BURST_MASK (0x40000000U)
4540#define APBH_CH11_DEBUG1_BURST_SHIFT (30U)
4541#define APBH_CH11_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_BURST_SHIFT)) & APBH_CH11_DEBUG1_BURST_MASK)
4542#define APBH_CH11_DEBUG1_REQ_MASK (0x80000000U)
4543#define APBH_CH11_DEBUG1_REQ_SHIFT (31U)
4544#define APBH_CH11_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_REQ_SHIFT)) & APBH_CH11_DEBUG1_REQ_MASK)
4545/*! @} */
4546
4547/*! @name CH11_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
4548/*! @{ */
4549#define APBH_CH11_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
4550#define APBH_CH11_DEBUG2_AHB_BYTES_SHIFT (0U)
4551#define APBH_CH11_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH11_DEBUG2_AHB_BYTES_MASK)
4552#define APBH_CH11_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
4553#define APBH_CH11_DEBUG2_APB_BYTES_SHIFT (16U)
4554#define APBH_CH11_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH11_DEBUG2_APB_BYTES_MASK)
4555/*! @} */
4556
4557/*! @name CH12_CURCMDAR - APBH DMA Channel n Current Command Address Register */
4558/*! @{ */
4559#define APBH_CH12_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
4560#define APBH_CH12_CURCMDAR_CMD_ADDR_SHIFT (0U)
4561#define APBH_CH12_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH12_CURCMDAR_CMD_ADDR_MASK)
4562/*! @} */
4563
4564/*! @name CH12_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
4565/*! @{ */
4566#define APBH_CH12_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
4567#define APBH_CH12_NXTCMDAR_CMD_ADDR_SHIFT (0U)
4568#define APBH_CH12_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH12_NXTCMDAR_CMD_ADDR_MASK)
4569/*! @} */
4570
4571/*! @name CH12_CMD - APBH DMA Channel n Command Register */
4572/*! @{ */
4573#define APBH_CH12_CMD_COMMAND_MASK (0x3U)
4574#define APBH_CH12_CMD_COMMAND_SHIFT (0U)
4575/*! COMMAND
4576 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
4577 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
4578 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
4579 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
4580 */
4581#define APBH_CH12_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_COMMAND_SHIFT)) & APBH_CH12_CMD_COMMAND_MASK)
4582#define APBH_CH12_CMD_CHAIN_MASK (0x4U)
4583#define APBH_CH12_CMD_CHAIN_SHIFT (2U)
4584#define APBH_CH12_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_CHAIN_SHIFT)) & APBH_CH12_CMD_CHAIN_MASK)
4585#define APBH_CH12_CMD_IRQONCMPLT_MASK (0x8U)
4586#define APBH_CH12_CMD_IRQONCMPLT_SHIFT (3U)
4587#define APBH_CH12_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_IRQONCMPLT_SHIFT)) & APBH_CH12_CMD_IRQONCMPLT_MASK)
4588#define APBH_CH12_CMD_NANDLOCK_MASK (0x10U)
4589#define APBH_CH12_CMD_NANDLOCK_SHIFT (4U)
4590#define APBH_CH12_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_NANDLOCK_SHIFT)) & APBH_CH12_CMD_NANDLOCK_MASK)
4591#define APBH_CH12_CMD_NANDWAIT4READY_MASK (0x20U)
4592#define APBH_CH12_CMD_NANDWAIT4READY_SHIFT (5U)
4593#define APBH_CH12_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH12_CMD_NANDWAIT4READY_MASK)
4594#define APBH_CH12_CMD_SEMAPHORE_MASK (0x40U)
4595#define APBH_CH12_CMD_SEMAPHORE_SHIFT (6U)
4596#define APBH_CH12_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_SEMAPHORE_SHIFT)) & APBH_CH12_CMD_SEMAPHORE_MASK)
4597#define APBH_CH12_CMD_WAIT4ENDCMD_MASK (0x80U)
4598#define APBH_CH12_CMD_WAIT4ENDCMD_SHIFT (7U)
4599#define APBH_CH12_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH12_CMD_WAIT4ENDCMD_MASK)
4600#define APBH_CH12_CMD_HALTONTERMINATE_MASK (0x100U)
4601#define APBH_CH12_CMD_HALTONTERMINATE_SHIFT (8U)
4602#define APBH_CH12_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH12_CMD_HALTONTERMINATE_MASK)
4603#define APBH_CH12_CMD_CMDWORDS_MASK (0xF000U)
4604#define APBH_CH12_CMD_CMDWORDS_SHIFT (12U)
4605#define APBH_CH12_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_CMDWORDS_SHIFT)) & APBH_CH12_CMD_CMDWORDS_MASK)
4606#define APBH_CH12_CMD_XFER_COUNT_MASK (0xFFFF0000U)
4607#define APBH_CH12_CMD_XFER_COUNT_SHIFT (16U)
4608#define APBH_CH12_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_XFER_COUNT_SHIFT)) & APBH_CH12_CMD_XFER_COUNT_MASK)
4609/*! @} */
4610
4611/*! @name CH12_BAR - APBH DMA Channel n Buffer Address Register */
4612/*! @{ */
4613#define APBH_CH12_BAR_ADDRESS_MASK (0xFFFFFFFFU)
4614#define APBH_CH12_BAR_ADDRESS_SHIFT (0U)
4615#define APBH_CH12_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_BAR_ADDRESS_SHIFT)) & APBH_CH12_BAR_ADDRESS_MASK)
4616/*! @} */
4617
4618/*! @name CH12_SEMA - APBH DMA Channel n Semaphore Register */
4619/*! @{ */
4620#define APBH_CH12_SEMA_INCREMENT_SEMA_MASK (0xFFU)
4621#define APBH_CH12_SEMA_INCREMENT_SEMA_SHIFT (0U)
4622#define APBH_CH12_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH12_SEMA_INCREMENT_SEMA_MASK)
4623#define APBH_CH12_SEMA_PHORE_MASK (0xFF0000U)
4624#define APBH_CH12_SEMA_PHORE_SHIFT (16U)
4625#define APBH_CH12_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_SEMA_PHORE_SHIFT)) & APBH_CH12_SEMA_PHORE_MASK)
4626/*! @} */
4627
4628/*! @name CH12_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
4629/*! @{ */
4630#define APBH_CH12_DEBUG1_STATEMACHINE_MASK (0x1FU)
4631#define APBH_CH12_DEBUG1_STATEMACHINE_SHIFT (0U)
4632/*! STATEMACHINE
4633 * 0b00000..This is the idle state of the DMA state machine.
4634 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
4635 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
4636 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
4637 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
4638 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
4639 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
4640 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
4641 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
4642 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
4643 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
4644 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
4645 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
4646 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
4647 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
4648 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
4649 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
4650 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
4651 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
4652 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
4653 */
4654#define APBH_CH12_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH12_DEBUG1_STATEMACHINE_MASK)
4655#define APBH_CH12_DEBUG1_RSVD1_MASK (0xFFFE0U)
4656#define APBH_CH12_DEBUG1_RSVD1_SHIFT (5U)
4657#define APBH_CH12_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RSVD1_SHIFT)) & APBH_CH12_DEBUG1_RSVD1_MASK)
4658#define APBH_CH12_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
4659#define APBH_CH12_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
4660#define APBH_CH12_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH12_DEBUG1_WR_FIFO_FULL_MASK)
4661#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
4662#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
4663#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH12_DEBUG1_WR_FIFO_EMPTY_MASK)
4664#define APBH_CH12_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
4665#define APBH_CH12_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
4666#define APBH_CH12_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH12_DEBUG1_RD_FIFO_FULL_MASK)
4667#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
4668#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
4669#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH12_DEBUG1_RD_FIFO_EMPTY_MASK)
4670#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
4671#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
4672#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH12_DEBUG1_NEXTCMDADDRVALID_MASK)
4673#define APBH_CH12_DEBUG1_LOCK_MASK (0x2000000U)
4674#define APBH_CH12_DEBUG1_LOCK_SHIFT (25U)
4675#define APBH_CH12_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_LOCK_SHIFT)) & APBH_CH12_DEBUG1_LOCK_MASK)
4676#define APBH_CH12_DEBUG1_READY_MASK (0x4000000U)
4677#define APBH_CH12_DEBUG1_READY_SHIFT (26U)
4678#define APBH_CH12_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_READY_SHIFT)) & APBH_CH12_DEBUG1_READY_MASK)
4679#define APBH_CH12_DEBUG1_SENSE_MASK (0x8000000U)
4680#define APBH_CH12_DEBUG1_SENSE_SHIFT (27U)
4681#define APBH_CH12_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_SENSE_SHIFT)) & APBH_CH12_DEBUG1_SENSE_MASK)
4682#define APBH_CH12_DEBUG1_END_MASK (0x10000000U)
4683#define APBH_CH12_DEBUG1_END_SHIFT (28U)
4684#define APBH_CH12_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_END_SHIFT)) & APBH_CH12_DEBUG1_END_MASK)
4685#define APBH_CH12_DEBUG1_KICK_MASK (0x20000000U)
4686#define APBH_CH12_DEBUG1_KICK_SHIFT (29U)
4687#define APBH_CH12_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_KICK_SHIFT)) & APBH_CH12_DEBUG1_KICK_MASK)
4688#define APBH_CH12_DEBUG1_BURST_MASK (0x40000000U)
4689#define APBH_CH12_DEBUG1_BURST_SHIFT (30U)
4690#define APBH_CH12_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_BURST_SHIFT)) & APBH_CH12_DEBUG1_BURST_MASK)
4691#define APBH_CH12_DEBUG1_REQ_MASK (0x80000000U)
4692#define APBH_CH12_DEBUG1_REQ_SHIFT (31U)
4693#define APBH_CH12_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_REQ_SHIFT)) & APBH_CH12_DEBUG1_REQ_MASK)
4694/*! @} */
4695
4696/*! @name CH12_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
4697/*! @{ */
4698#define APBH_CH12_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
4699#define APBH_CH12_DEBUG2_AHB_BYTES_SHIFT (0U)
4700#define APBH_CH12_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH12_DEBUG2_AHB_BYTES_MASK)
4701#define APBH_CH12_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
4702#define APBH_CH12_DEBUG2_APB_BYTES_SHIFT (16U)
4703#define APBH_CH12_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH12_DEBUG2_APB_BYTES_MASK)
4704/*! @} */
4705
4706/*! @name CH13_CURCMDAR - APBH DMA Channel n Current Command Address Register */
4707/*! @{ */
4708#define APBH_CH13_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
4709#define APBH_CH13_CURCMDAR_CMD_ADDR_SHIFT (0U)
4710#define APBH_CH13_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH13_CURCMDAR_CMD_ADDR_MASK)
4711/*! @} */
4712
4713/*! @name CH13_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
4714/*! @{ */
4715#define APBH_CH13_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
4716#define APBH_CH13_NXTCMDAR_CMD_ADDR_SHIFT (0U)
4717#define APBH_CH13_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH13_NXTCMDAR_CMD_ADDR_MASK)
4718/*! @} */
4719
4720/*! @name CH13_CMD - APBH DMA Channel n Command Register */
4721/*! @{ */
4722#define APBH_CH13_CMD_COMMAND_MASK (0x3U)
4723#define APBH_CH13_CMD_COMMAND_SHIFT (0U)
4724/*! COMMAND
4725 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
4726 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
4727 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
4728 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
4729 */
4730#define APBH_CH13_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_COMMAND_SHIFT)) & APBH_CH13_CMD_COMMAND_MASK)
4731#define APBH_CH13_CMD_CHAIN_MASK (0x4U)
4732#define APBH_CH13_CMD_CHAIN_SHIFT (2U)
4733#define APBH_CH13_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_CHAIN_SHIFT)) & APBH_CH13_CMD_CHAIN_MASK)
4734#define APBH_CH13_CMD_IRQONCMPLT_MASK (0x8U)
4735#define APBH_CH13_CMD_IRQONCMPLT_SHIFT (3U)
4736#define APBH_CH13_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_IRQONCMPLT_SHIFT)) & APBH_CH13_CMD_IRQONCMPLT_MASK)
4737#define APBH_CH13_CMD_NANDLOCK_MASK (0x10U)
4738#define APBH_CH13_CMD_NANDLOCK_SHIFT (4U)
4739#define APBH_CH13_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_NANDLOCK_SHIFT)) & APBH_CH13_CMD_NANDLOCK_MASK)
4740#define APBH_CH13_CMD_NANDWAIT4READY_MASK (0x20U)
4741#define APBH_CH13_CMD_NANDWAIT4READY_SHIFT (5U)
4742#define APBH_CH13_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH13_CMD_NANDWAIT4READY_MASK)
4743#define APBH_CH13_CMD_SEMAPHORE_MASK (0x40U)
4744#define APBH_CH13_CMD_SEMAPHORE_SHIFT (6U)
4745#define APBH_CH13_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_SEMAPHORE_SHIFT)) & APBH_CH13_CMD_SEMAPHORE_MASK)
4746#define APBH_CH13_CMD_WAIT4ENDCMD_MASK (0x80U)
4747#define APBH_CH13_CMD_WAIT4ENDCMD_SHIFT (7U)
4748#define APBH_CH13_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH13_CMD_WAIT4ENDCMD_MASK)
4749#define APBH_CH13_CMD_HALTONTERMINATE_MASK (0x100U)
4750#define APBH_CH13_CMD_HALTONTERMINATE_SHIFT (8U)
4751#define APBH_CH13_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH13_CMD_HALTONTERMINATE_MASK)
4752#define APBH_CH13_CMD_CMDWORDS_MASK (0xF000U)
4753#define APBH_CH13_CMD_CMDWORDS_SHIFT (12U)
4754#define APBH_CH13_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_CMDWORDS_SHIFT)) & APBH_CH13_CMD_CMDWORDS_MASK)
4755#define APBH_CH13_CMD_XFER_COUNT_MASK (0xFFFF0000U)
4756#define APBH_CH13_CMD_XFER_COUNT_SHIFT (16U)
4757#define APBH_CH13_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_XFER_COUNT_SHIFT)) & APBH_CH13_CMD_XFER_COUNT_MASK)
4758/*! @} */
4759
4760/*! @name CH13_BAR - APBH DMA Channel n Buffer Address Register */
4761/*! @{ */
4762#define APBH_CH13_BAR_ADDRESS_MASK (0xFFFFFFFFU)
4763#define APBH_CH13_BAR_ADDRESS_SHIFT (0U)
4764#define APBH_CH13_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_BAR_ADDRESS_SHIFT)) & APBH_CH13_BAR_ADDRESS_MASK)
4765/*! @} */
4766
4767/*! @name CH13_SEMA - APBH DMA Channel n Semaphore Register */
4768/*! @{ */
4769#define APBH_CH13_SEMA_INCREMENT_SEMA_MASK (0xFFU)
4770#define APBH_CH13_SEMA_INCREMENT_SEMA_SHIFT (0U)
4771#define APBH_CH13_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH13_SEMA_INCREMENT_SEMA_MASK)
4772#define APBH_CH13_SEMA_PHORE_MASK (0xFF0000U)
4773#define APBH_CH13_SEMA_PHORE_SHIFT (16U)
4774#define APBH_CH13_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_SEMA_PHORE_SHIFT)) & APBH_CH13_SEMA_PHORE_MASK)
4775/*! @} */
4776
4777/*! @name CH13_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
4778/*! @{ */
4779#define APBH_CH13_DEBUG1_STATEMACHINE_MASK (0x1FU)
4780#define APBH_CH13_DEBUG1_STATEMACHINE_SHIFT (0U)
4781/*! STATEMACHINE
4782 * 0b00000..This is the idle state of the DMA state machine.
4783 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
4784 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
4785 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
4786 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
4787 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
4788 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
4789 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
4790 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
4791 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
4792 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
4793 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
4794 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
4795 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
4796 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
4797 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
4798 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
4799 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
4800 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
4801 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
4802 */
4803#define APBH_CH13_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH13_DEBUG1_STATEMACHINE_MASK)
4804#define APBH_CH13_DEBUG1_RSVD1_MASK (0xFFFE0U)
4805#define APBH_CH13_DEBUG1_RSVD1_SHIFT (5U)
4806#define APBH_CH13_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RSVD1_SHIFT)) & APBH_CH13_DEBUG1_RSVD1_MASK)
4807#define APBH_CH13_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
4808#define APBH_CH13_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
4809#define APBH_CH13_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH13_DEBUG1_WR_FIFO_FULL_MASK)
4810#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
4811#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
4812#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH13_DEBUG1_WR_FIFO_EMPTY_MASK)
4813#define APBH_CH13_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
4814#define APBH_CH13_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
4815#define APBH_CH13_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH13_DEBUG1_RD_FIFO_FULL_MASK)
4816#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
4817#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
4818#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH13_DEBUG1_RD_FIFO_EMPTY_MASK)
4819#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
4820#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
4821#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH13_DEBUG1_NEXTCMDADDRVALID_MASK)
4822#define APBH_CH13_DEBUG1_LOCK_MASK (0x2000000U)
4823#define APBH_CH13_DEBUG1_LOCK_SHIFT (25U)
4824#define APBH_CH13_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_LOCK_SHIFT)) & APBH_CH13_DEBUG1_LOCK_MASK)
4825#define APBH_CH13_DEBUG1_READY_MASK (0x4000000U)
4826#define APBH_CH13_DEBUG1_READY_SHIFT (26U)
4827#define APBH_CH13_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_READY_SHIFT)) & APBH_CH13_DEBUG1_READY_MASK)
4828#define APBH_CH13_DEBUG1_SENSE_MASK (0x8000000U)
4829#define APBH_CH13_DEBUG1_SENSE_SHIFT (27U)
4830#define APBH_CH13_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_SENSE_SHIFT)) & APBH_CH13_DEBUG1_SENSE_MASK)
4831#define APBH_CH13_DEBUG1_END_MASK (0x10000000U)
4832#define APBH_CH13_DEBUG1_END_SHIFT (28U)
4833#define APBH_CH13_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_END_SHIFT)) & APBH_CH13_DEBUG1_END_MASK)
4834#define APBH_CH13_DEBUG1_KICK_MASK (0x20000000U)
4835#define APBH_CH13_DEBUG1_KICK_SHIFT (29U)
4836#define APBH_CH13_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_KICK_SHIFT)) & APBH_CH13_DEBUG1_KICK_MASK)
4837#define APBH_CH13_DEBUG1_BURST_MASK (0x40000000U)
4838#define APBH_CH13_DEBUG1_BURST_SHIFT (30U)
4839#define APBH_CH13_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_BURST_SHIFT)) & APBH_CH13_DEBUG1_BURST_MASK)
4840#define APBH_CH13_DEBUG1_REQ_MASK (0x80000000U)
4841#define APBH_CH13_DEBUG1_REQ_SHIFT (31U)
4842#define APBH_CH13_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_REQ_SHIFT)) & APBH_CH13_DEBUG1_REQ_MASK)
4843/*! @} */
4844
4845/*! @name CH13_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
4846/*! @{ */
4847#define APBH_CH13_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
4848#define APBH_CH13_DEBUG2_AHB_BYTES_SHIFT (0U)
4849#define APBH_CH13_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH13_DEBUG2_AHB_BYTES_MASK)
4850#define APBH_CH13_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
4851#define APBH_CH13_DEBUG2_APB_BYTES_SHIFT (16U)
4852#define APBH_CH13_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH13_DEBUG2_APB_BYTES_MASK)
4853/*! @} */
4854
4855/*! @name CH14_CURCMDAR - APBH DMA Channel n Current Command Address Register */
4856/*! @{ */
4857#define APBH_CH14_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
4858#define APBH_CH14_CURCMDAR_CMD_ADDR_SHIFT (0U)
4859#define APBH_CH14_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH14_CURCMDAR_CMD_ADDR_MASK)
4860/*! @} */
4861
4862/*! @name CH14_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
4863/*! @{ */
4864#define APBH_CH14_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
4865#define APBH_CH14_NXTCMDAR_CMD_ADDR_SHIFT (0U)
4866#define APBH_CH14_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH14_NXTCMDAR_CMD_ADDR_MASK)
4867/*! @} */
4868
4869/*! @name CH14_CMD - APBH DMA Channel n Command Register */
4870/*! @{ */
4871#define APBH_CH14_CMD_COMMAND_MASK (0x3U)
4872#define APBH_CH14_CMD_COMMAND_SHIFT (0U)
4873/*! COMMAND
4874 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
4875 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
4876 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
4877 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
4878 */
4879#define APBH_CH14_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_COMMAND_SHIFT)) & APBH_CH14_CMD_COMMAND_MASK)
4880#define APBH_CH14_CMD_CHAIN_MASK (0x4U)
4881#define APBH_CH14_CMD_CHAIN_SHIFT (2U)
4882#define APBH_CH14_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_CHAIN_SHIFT)) & APBH_CH14_CMD_CHAIN_MASK)
4883#define APBH_CH14_CMD_IRQONCMPLT_MASK (0x8U)
4884#define APBH_CH14_CMD_IRQONCMPLT_SHIFT (3U)
4885#define APBH_CH14_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_IRQONCMPLT_SHIFT)) & APBH_CH14_CMD_IRQONCMPLT_MASK)
4886#define APBH_CH14_CMD_NANDLOCK_MASK (0x10U)
4887#define APBH_CH14_CMD_NANDLOCK_SHIFT (4U)
4888#define APBH_CH14_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_NANDLOCK_SHIFT)) & APBH_CH14_CMD_NANDLOCK_MASK)
4889#define APBH_CH14_CMD_NANDWAIT4READY_MASK (0x20U)
4890#define APBH_CH14_CMD_NANDWAIT4READY_SHIFT (5U)
4891#define APBH_CH14_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH14_CMD_NANDWAIT4READY_MASK)
4892#define APBH_CH14_CMD_SEMAPHORE_MASK (0x40U)
4893#define APBH_CH14_CMD_SEMAPHORE_SHIFT (6U)
4894#define APBH_CH14_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_SEMAPHORE_SHIFT)) & APBH_CH14_CMD_SEMAPHORE_MASK)
4895#define APBH_CH14_CMD_WAIT4ENDCMD_MASK (0x80U)
4896#define APBH_CH14_CMD_WAIT4ENDCMD_SHIFT (7U)
4897#define APBH_CH14_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH14_CMD_WAIT4ENDCMD_MASK)
4898#define APBH_CH14_CMD_HALTONTERMINATE_MASK (0x100U)
4899#define APBH_CH14_CMD_HALTONTERMINATE_SHIFT (8U)
4900#define APBH_CH14_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH14_CMD_HALTONTERMINATE_MASK)
4901#define APBH_CH14_CMD_CMDWORDS_MASK (0xF000U)
4902#define APBH_CH14_CMD_CMDWORDS_SHIFT (12U)
4903#define APBH_CH14_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_CMDWORDS_SHIFT)) & APBH_CH14_CMD_CMDWORDS_MASK)
4904#define APBH_CH14_CMD_XFER_COUNT_MASK (0xFFFF0000U)
4905#define APBH_CH14_CMD_XFER_COUNT_SHIFT (16U)
4906#define APBH_CH14_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_XFER_COUNT_SHIFT)) & APBH_CH14_CMD_XFER_COUNT_MASK)
4907/*! @} */
4908
4909/*! @name CH14_BAR - APBH DMA Channel n Buffer Address Register */
4910/*! @{ */
4911#define APBH_CH14_BAR_ADDRESS_MASK (0xFFFFFFFFU)
4912#define APBH_CH14_BAR_ADDRESS_SHIFT (0U)
4913#define APBH_CH14_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_BAR_ADDRESS_SHIFT)) & APBH_CH14_BAR_ADDRESS_MASK)
4914/*! @} */
4915
4916/*! @name CH14_SEMA - APBH DMA Channel n Semaphore Register */
4917/*! @{ */
4918#define APBH_CH14_SEMA_INCREMENT_SEMA_MASK (0xFFU)
4919#define APBH_CH14_SEMA_INCREMENT_SEMA_SHIFT (0U)
4920#define APBH_CH14_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH14_SEMA_INCREMENT_SEMA_MASK)
4921#define APBH_CH14_SEMA_PHORE_MASK (0xFF0000U)
4922#define APBH_CH14_SEMA_PHORE_SHIFT (16U)
4923#define APBH_CH14_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_SEMA_PHORE_SHIFT)) & APBH_CH14_SEMA_PHORE_MASK)
4924/*! @} */
4925
4926/*! @name CH14_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
4927/*! @{ */
4928#define APBH_CH14_DEBUG1_STATEMACHINE_MASK (0x1FU)
4929#define APBH_CH14_DEBUG1_STATEMACHINE_SHIFT (0U)
4930/*! STATEMACHINE
4931 * 0b00000..This is the idle state of the DMA state machine.
4932 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
4933 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
4934 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
4935 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
4936 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
4937 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
4938 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
4939 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
4940 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
4941 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
4942 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
4943 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
4944 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
4945 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
4946 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
4947 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
4948 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
4949 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
4950 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
4951 */
4952#define APBH_CH14_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH14_DEBUG1_STATEMACHINE_MASK)
4953#define APBH_CH14_DEBUG1_RSVD1_MASK (0xFFFE0U)
4954#define APBH_CH14_DEBUG1_RSVD1_SHIFT (5U)
4955#define APBH_CH14_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RSVD1_SHIFT)) & APBH_CH14_DEBUG1_RSVD1_MASK)
4956#define APBH_CH14_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
4957#define APBH_CH14_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
4958#define APBH_CH14_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH14_DEBUG1_WR_FIFO_FULL_MASK)
4959#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
4960#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
4961#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH14_DEBUG1_WR_FIFO_EMPTY_MASK)
4962#define APBH_CH14_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
4963#define APBH_CH14_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
4964#define APBH_CH14_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH14_DEBUG1_RD_FIFO_FULL_MASK)
4965#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
4966#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
4967#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH14_DEBUG1_RD_FIFO_EMPTY_MASK)
4968#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
4969#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
4970#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH14_DEBUG1_NEXTCMDADDRVALID_MASK)
4971#define APBH_CH14_DEBUG1_LOCK_MASK (0x2000000U)
4972#define APBH_CH14_DEBUG1_LOCK_SHIFT (25U)
4973#define APBH_CH14_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_LOCK_SHIFT)) & APBH_CH14_DEBUG1_LOCK_MASK)
4974#define APBH_CH14_DEBUG1_READY_MASK (0x4000000U)
4975#define APBH_CH14_DEBUG1_READY_SHIFT (26U)
4976#define APBH_CH14_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_READY_SHIFT)) & APBH_CH14_DEBUG1_READY_MASK)
4977#define APBH_CH14_DEBUG1_SENSE_MASK (0x8000000U)
4978#define APBH_CH14_DEBUG1_SENSE_SHIFT (27U)
4979#define APBH_CH14_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_SENSE_SHIFT)) & APBH_CH14_DEBUG1_SENSE_MASK)
4980#define APBH_CH14_DEBUG1_END_MASK (0x10000000U)
4981#define APBH_CH14_DEBUG1_END_SHIFT (28U)
4982#define APBH_CH14_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_END_SHIFT)) & APBH_CH14_DEBUG1_END_MASK)
4983#define APBH_CH14_DEBUG1_KICK_MASK (0x20000000U)
4984#define APBH_CH14_DEBUG1_KICK_SHIFT (29U)
4985#define APBH_CH14_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_KICK_SHIFT)) & APBH_CH14_DEBUG1_KICK_MASK)
4986#define APBH_CH14_DEBUG1_BURST_MASK (0x40000000U)
4987#define APBH_CH14_DEBUG1_BURST_SHIFT (30U)
4988#define APBH_CH14_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_BURST_SHIFT)) & APBH_CH14_DEBUG1_BURST_MASK)
4989#define APBH_CH14_DEBUG1_REQ_MASK (0x80000000U)
4990#define APBH_CH14_DEBUG1_REQ_SHIFT (31U)
4991#define APBH_CH14_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_REQ_SHIFT)) & APBH_CH14_DEBUG1_REQ_MASK)
4992/*! @} */
4993
4994/*! @name CH14_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
4995/*! @{ */
4996#define APBH_CH14_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
4997#define APBH_CH14_DEBUG2_AHB_BYTES_SHIFT (0U)
4998#define APBH_CH14_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH14_DEBUG2_AHB_BYTES_MASK)
4999#define APBH_CH14_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
5000#define APBH_CH14_DEBUG2_APB_BYTES_SHIFT (16U)
5001#define APBH_CH14_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH14_DEBUG2_APB_BYTES_MASK)
5002/*! @} */
5003
5004/*! @name CH15_CURCMDAR - APBH DMA Channel n Current Command Address Register */
5005/*! @{ */
5006#define APBH_CH15_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
5007#define APBH_CH15_CURCMDAR_CMD_ADDR_SHIFT (0U)
5008#define APBH_CH15_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH15_CURCMDAR_CMD_ADDR_MASK)
5009/*! @} */
5010
5011/*! @name CH15_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
5012/*! @{ */
5013#define APBH_CH15_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
5014#define APBH_CH15_NXTCMDAR_CMD_ADDR_SHIFT (0U)
5015#define APBH_CH15_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH15_NXTCMDAR_CMD_ADDR_MASK)
5016/*! @} */
5017
5018/*! @name CH15_CMD - APBH DMA Channel n Command Register */
5019/*! @{ */
5020#define APBH_CH15_CMD_COMMAND_MASK (0x3U)
5021#define APBH_CH15_CMD_COMMAND_SHIFT (0U)
5022/*! COMMAND
5023 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
5024 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
5025 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
5026 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
5027 */
5028#define APBH_CH15_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_COMMAND_SHIFT)) & APBH_CH15_CMD_COMMAND_MASK)
5029#define APBH_CH15_CMD_CHAIN_MASK (0x4U)
5030#define APBH_CH15_CMD_CHAIN_SHIFT (2U)
5031#define APBH_CH15_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_CHAIN_SHIFT)) & APBH_CH15_CMD_CHAIN_MASK)
5032#define APBH_CH15_CMD_IRQONCMPLT_MASK (0x8U)
5033#define APBH_CH15_CMD_IRQONCMPLT_SHIFT (3U)
5034#define APBH_CH15_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_IRQONCMPLT_SHIFT)) & APBH_CH15_CMD_IRQONCMPLT_MASK)
5035#define APBH_CH15_CMD_NANDLOCK_MASK (0x10U)
5036#define APBH_CH15_CMD_NANDLOCK_SHIFT (4U)
5037#define APBH_CH15_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_NANDLOCK_SHIFT)) & APBH_CH15_CMD_NANDLOCK_MASK)
5038#define APBH_CH15_CMD_NANDWAIT4READY_MASK (0x20U)
5039#define APBH_CH15_CMD_NANDWAIT4READY_SHIFT (5U)
5040#define APBH_CH15_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH15_CMD_NANDWAIT4READY_MASK)
5041#define APBH_CH15_CMD_SEMAPHORE_MASK (0x40U)
5042#define APBH_CH15_CMD_SEMAPHORE_SHIFT (6U)
5043#define APBH_CH15_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_SEMAPHORE_SHIFT)) & APBH_CH15_CMD_SEMAPHORE_MASK)
5044#define APBH_CH15_CMD_WAIT4ENDCMD_MASK (0x80U)
5045#define APBH_CH15_CMD_WAIT4ENDCMD_SHIFT (7U)
5046#define APBH_CH15_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH15_CMD_WAIT4ENDCMD_MASK)
5047#define APBH_CH15_CMD_HALTONTERMINATE_MASK (0x100U)
5048#define APBH_CH15_CMD_HALTONTERMINATE_SHIFT (8U)
5049#define APBH_CH15_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH15_CMD_HALTONTERMINATE_MASK)
5050#define APBH_CH15_CMD_CMDWORDS_MASK (0xF000U)
5051#define APBH_CH15_CMD_CMDWORDS_SHIFT (12U)
5052#define APBH_CH15_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_CMDWORDS_SHIFT)) & APBH_CH15_CMD_CMDWORDS_MASK)
5053#define APBH_CH15_CMD_XFER_COUNT_MASK (0xFFFF0000U)
5054#define APBH_CH15_CMD_XFER_COUNT_SHIFT (16U)
5055#define APBH_CH15_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_XFER_COUNT_SHIFT)) & APBH_CH15_CMD_XFER_COUNT_MASK)
5056/*! @} */
5057
5058/*! @name CH15_BAR - APBH DMA Channel n Buffer Address Register */
5059/*! @{ */
5060#define APBH_CH15_BAR_ADDRESS_MASK (0xFFFFFFFFU)
5061#define APBH_CH15_BAR_ADDRESS_SHIFT (0U)
5062#define APBH_CH15_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_BAR_ADDRESS_SHIFT)) & APBH_CH15_BAR_ADDRESS_MASK)
5063/*! @} */
5064
5065/*! @name CH15_SEMA - APBH DMA Channel n Semaphore Register */
5066/*! @{ */
5067#define APBH_CH15_SEMA_INCREMENT_SEMA_MASK (0xFFU)
5068#define APBH_CH15_SEMA_INCREMENT_SEMA_SHIFT (0U)
5069#define APBH_CH15_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH15_SEMA_INCREMENT_SEMA_MASK)
5070#define APBH_CH15_SEMA_PHORE_MASK (0xFF0000U)
5071#define APBH_CH15_SEMA_PHORE_SHIFT (16U)
5072#define APBH_CH15_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_SEMA_PHORE_SHIFT)) & APBH_CH15_SEMA_PHORE_MASK)
5073/*! @} */
5074
5075/*! @name CH15_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
5076/*! @{ */
5077#define APBH_CH15_DEBUG1_STATEMACHINE_MASK (0x1FU)
5078#define APBH_CH15_DEBUG1_STATEMACHINE_SHIFT (0U)
5079/*! STATEMACHINE
5080 * 0b00000..This is the idle state of the DMA state machine.
5081 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
5082 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
5083 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
5084 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
5085 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
5086 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
5087 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
5088 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
5089 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
5090 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
5091 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
5092 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
5093 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
5094 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
5095 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
5096 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
5097 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
5098 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
5099 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
5100 */
5101#define APBH_CH15_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH15_DEBUG1_STATEMACHINE_MASK)
5102#define APBH_CH15_DEBUG1_RSVD1_MASK (0xFFFE0U)
5103#define APBH_CH15_DEBUG1_RSVD1_SHIFT (5U)
5104#define APBH_CH15_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RSVD1_SHIFT)) & APBH_CH15_DEBUG1_RSVD1_MASK)
5105#define APBH_CH15_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
5106#define APBH_CH15_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
5107#define APBH_CH15_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH15_DEBUG1_WR_FIFO_FULL_MASK)
5108#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
5109#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
5110#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH15_DEBUG1_WR_FIFO_EMPTY_MASK)
5111#define APBH_CH15_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
5112#define APBH_CH15_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
5113#define APBH_CH15_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH15_DEBUG1_RD_FIFO_FULL_MASK)
5114#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
5115#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
5116#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH15_DEBUG1_RD_FIFO_EMPTY_MASK)
5117#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
5118#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
5119#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH15_DEBUG1_NEXTCMDADDRVALID_MASK)
5120#define APBH_CH15_DEBUG1_LOCK_MASK (0x2000000U)
5121#define APBH_CH15_DEBUG1_LOCK_SHIFT (25U)
5122#define APBH_CH15_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_LOCK_SHIFT)) & APBH_CH15_DEBUG1_LOCK_MASK)
5123#define APBH_CH15_DEBUG1_READY_MASK (0x4000000U)
5124#define APBH_CH15_DEBUG1_READY_SHIFT (26U)
5125#define APBH_CH15_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_READY_SHIFT)) & APBH_CH15_DEBUG1_READY_MASK)
5126#define APBH_CH15_DEBUG1_SENSE_MASK (0x8000000U)
5127#define APBH_CH15_DEBUG1_SENSE_SHIFT (27U)
5128#define APBH_CH15_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_SENSE_SHIFT)) & APBH_CH15_DEBUG1_SENSE_MASK)
5129#define APBH_CH15_DEBUG1_END_MASK (0x10000000U)
5130#define APBH_CH15_DEBUG1_END_SHIFT (28U)
5131#define APBH_CH15_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_END_SHIFT)) & APBH_CH15_DEBUG1_END_MASK)
5132#define APBH_CH15_DEBUG1_KICK_MASK (0x20000000U)
5133#define APBH_CH15_DEBUG1_KICK_SHIFT (29U)
5134#define APBH_CH15_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_KICK_SHIFT)) & APBH_CH15_DEBUG1_KICK_MASK)
5135#define APBH_CH15_DEBUG1_BURST_MASK (0x40000000U)
5136#define APBH_CH15_DEBUG1_BURST_SHIFT (30U)
5137#define APBH_CH15_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_BURST_SHIFT)) & APBH_CH15_DEBUG1_BURST_MASK)
5138#define APBH_CH15_DEBUG1_REQ_MASK (0x80000000U)
5139#define APBH_CH15_DEBUG1_REQ_SHIFT (31U)
5140#define APBH_CH15_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_REQ_SHIFT)) & APBH_CH15_DEBUG1_REQ_MASK)
5141/*! @} */
5142
5143/*! @name CH15_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
5144/*! @{ */
5145#define APBH_CH15_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
5146#define APBH_CH15_DEBUG2_AHB_BYTES_SHIFT (0U)
5147#define APBH_CH15_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH15_DEBUG2_AHB_BYTES_MASK)
5148#define APBH_CH15_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
5149#define APBH_CH15_DEBUG2_APB_BYTES_SHIFT (16U)
5150#define APBH_CH15_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH15_DEBUG2_APB_BYTES_MASK)
5151/*! @} */
5152
5153/*! @name VERSION - APBH Bridge Version Register */
5154/*! @{ */
5155#define APBH_VERSION_STEP_MASK (0xFFFFU)
5156#define APBH_VERSION_STEP_SHIFT (0U)
5157#define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK)
5158#define APBH_VERSION_MINOR_MASK (0xFF0000U)
5159#define APBH_VERSION_MINOR_SHIFT (16U)
5160#define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK)
5161#define APBH_VERSION_MAJOR_MASK (0xFF000000U)
5162#define APBH_VERSION_MAJOR_SHIFT (24U)
5163#define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK)
5164/*! @} */
5165
5166
5167/*!
5168 * @}
5169 */ /* end of group APBH_Register_Masks */
5170
5171
5172/* APBH - Peripheral instance base addresses */
5173/** Peripheral APBH base address */
5174#define APBH_BASE (0x33000000u)
5175/** Peripheral APBH base pointer */
5176#define APBH ((APBH_Type *)APBH_BASE)
5177/** Array initializer of APBH peripheral base addresses */
5178#define APBH_BASE_ADDRS { APBH_BASE }
5179/** Array initializer of APBH peripheral base pointers */
5180#define APBH_BASE_PTRS { APBH }
5181/** Interrupt vectors for the APBH peripheral type */
5182#define APBH_IRQS { APBHDMA_IRQn }
5183
5184/*!
5185 * @}
5186 */ /* end of group APBH_Peripheral_Access_Layer */
5187
5188
5189/* ----------------------------------------------------------------------------
5190 -- BCH Peripheral Access Layer
5191 ---------------------------------------------------------------------------- */
5192
5193/*!
5194 * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer
5195 * @{
5196 */
5197
5198/** BCH - Register Layout Typedef */
5199typedef struct {
5200 __IO uint32_t CTRL; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */
5201 __IO uint32_t CTRL_SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */
5202 __IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */
5203 __IO uint32_t CTRL_TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */
5204 __I uint32_t STATUS0; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */
5205 __I uint32_t STATUS0_SET; /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */
5206 __I uint32_t STATUS0_CLR; /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */
5207 __I uint32_t STATUS0_TOG; /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */
5208 __IO uint32_t MODE; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */
5209 __IO uint32_t MODE_SET; /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */
5210 __IO uint32_t MODE_CLR; /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */
5211 __IO uint32_t MODE_TOG; /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */
5212 __IO uint32_t ENCODEPTR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */
5213 __IO uint32_t ENCODEPTR_SET; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */
5214 __IO uint32_t ENCODEPTR_CLR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */
5215 __IO uint32_t ENCODEPTR_TOG; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */
5216 __IO uint32_t DATAPTR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */
5217 __IO uint32_t DATAPTR_SET; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */
5218 __IO uint32_t DATAPTR_CLR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */
5219 __IO uint32_t DATAPTR_TOG; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */
5220 __IO uint32_t METAPTR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */
5221 __IO uint32_t METAPTR_SET; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */
5222 __IO uint32_t METAPTR_CLR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */
5223 __IO uint32_t METAPTR_TOG; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */
5224 uint8_t RESERVED_0[16];
5225 __IO uint32_t LAYOUTSELECT; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */
5226 __IO uint32_t LAYOUTSELECT_SET; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */
5227 __IO uint32_t LAYOUTSELECT_CLR; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */
5228 __IO uint32_t LAYOUTSELECT_TOG; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */
5229 __IO uint32_t FLASH0LAYOUT0; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */
5230 __IO uint32_t FLASH0LAYOUT0_SET; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */
5231 __IO uint32_t FLASH0LAYOUT0_CLR; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */
5232 __IO uint32_t FLASH0LAYOUT0_TOG; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */
5233 __IO uint32_t FLASH0LAYOUT1; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */
5234 __IO uint32_t FLASH0LAYOUT1_SET; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */
5235 __IO uint32_t FLASH0LAYOUT1_CLR; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */
5236 __IO uint32_t FLASH0LAYOUT1_TOG; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */
5237 __IO uint32_t FLASH1LAYOUT0; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */
5238 __IO uint32_t FLASH1LAYOUT0_SET; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */
5239 __IO uint32_t FLASH1LAYOUT0_CLR; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */
5240 __IO uint32_t FLASH1LAYOUT0_TOG; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */
5241 __IO uint32_t FLASH1LAYOUT1; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */
5242 __IO uint32_t FLASH1LAYOUT1_SET; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */
5243 __IO uint32_t FLASH1LAYOUT1_CLR; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */
5244 __IO uint32_t FLASH1LAYOUT1_TOG; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */
5245 __IO uint32_t FLASH2LAYOUT0; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */
5246 __IO uint32_t FLASH2LAYOUT0_SET; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */
5247 __IO uint32_t FLASH2LAYOUT0_CLR; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */
5248 __IO uint32_t FLASH2LAYOUT0_TOG; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */
5249 __IO uint32_t FLASH2LAYOUT1; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */
5250 __IO uint32_t FLASH2LAYOUT1_SET; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */
5251 __IO uint32_t FLASH2LAYOUT1_CLR; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */
5252 __IO uint32_t FLASH2LAYOUT1_TOG; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */
5253 __IO uint32_t FLASH3LAYOUT0; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */
5254 __IO uint32_t FLASH3LAYOUT0_SET; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */
5255 __IO uint32_t FLASH3LAYOUT0_CLR; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */
5256 __IO uint32_t FLASH3LAYOUT0_TOG; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */
5257 __IO uint32_t FLASH3LAYOUT1; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */
5258 __IO uint32_t FLASH3LAYOUT1_SET; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */
5259 __IO uint32_t FLASH3LAYOUT1_CLR; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */
5260 __IO uint32_t FLASH3LAYOUT1_TOG; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */
5261 __IO uint32_t DEBUG0; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */
5262 __IO uint32_t DEBUG0_SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */
5263 __IO uint32_t DEBUG0_CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */
5264 __IO uint32_t DEBUG0_TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */
5265 __I uint32_t DBGKESREAD; /**< KES Debug Read Register, offset: 0x110 */
5266 __I uint32_t DBGKESREAD_SET; /**< KES Debug Read Register, offset: 0x114 */
5267 __I uint32_t DBGKESREAD_CLR; /**< KES Debug Read Register, offset: 0x118 */
5268 __I uint32_t DBGKESREAD_TOG; /**< KES Debug Read Register, offset: 0x11C */
5269 __I uint32_t DBGCSFEREAD; /**< Chien Search Debug Read Register, offset: 0x120 */
5270 __I uint32_t DBGCSFEREAD_SET; /**< Chien Search Debug Read Register, offset: 0x124 */
5271 __I uint32_t DBGCSFEREAD_CLR; /**< Chien Search Debug Read Register, offset: 0x128 */
5272 __I uint32_t DBGCSFEREAD_TOG; /**< Chien Search Debug Read Register, offset: 0x12C */
5273 __I uint32_t DBGSYNDGENREAD; /**< Syndrome Generator Debug Read Register, offset: 0x130 */
5274 __I uint32_t DBGSYNDGENREAD_SET; /**< Syndrome Generator Debug Read Register, offset: 0x134 */
5275 __I uint32_t DBGSYNDGENREAD_CLR; /**< Syndrome Generator Debug Read Register, offset: 0x138 */
5276 __I uint32_t DBGSYNDGENREAD_TOG; /**< Syndrome Generator Debug Read Register, offset: 0x13C */
5277 __I uint32_t DBGAHBMREAD; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */
5278 __I uint32_t DBGAHBMREAD_SET; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */
5279 __I uint32_t DBGAHBMREAD_CLR; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */
5280 __I uint32_t DBGAHBMREAD_TOG; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */
5281 __I uint32_t BLOCKNAME; /**< Block Name Register, offset: 0x150 */
5282 __I uint32_t BLOCKNAME_SET; /**< Block Name Register, offset: 0x154 */
5283 __I uint32_t BLOCKNAME_CLR; /**< Block Name Register, offset: 0x158 */
5284 __I uint32_t BLOCKNAME_TOG; /**< Block Name Register, offset: 0x15C */
5285 __I uint32_t VERSION; /**< BCH Version Register, offset: 0x160 */
5286 __I uint32_t VERSION_SET; /**< BCH Version Register, offset: 0x164 */
5287 __I uint32_t VERSION_CLR; /**< BCH Version Register, offset: 0x168 */
5288 __I uint32_t VERSION_TOG; /**< BCH Version Register, offset: 0x16C */
5289 __IO uint32_t DEBUG1; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */
5290 __IO uint32_t DEBUG1_SET; /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */
5291 __IO uint32_t DEBUG1_CLR; /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */
5292 __IO uint32_t DEBUG1_TOG; /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */
5293} BCH_Type;
5294
5295/* ----------------------------------------------------------------------------
5296 -- BCH Register Masks
5297 ---------------------------------------------------------------------------- */
5298
5299/*!
5300 * @addtogroup BCH_Register_Masks BCH Register Masks
5301 * @{
5302 */
5303
5304/*! @name CTRL - Hardware BCH ECC Accelerator Control Register */
5305/*! @{ */
5306#define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U)
5307#define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U)
5308#define BCH_CTRL_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK)
5309#define BCH_CTRL_RSVD0_MASK (0x2U)
5310#define BCH_CTRL_RSVD0_SHIFT (1U)
5311#define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK)
5312#define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U)
5313#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U)
5314#define BCH_CTRL_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK)
5315#define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U)
5316#define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U)
5317#define BCH_CTRL_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK)
5318#define BCH_CTRL_RSVD1_MASK (0xF0U)
5319#define BCH_CTRL_RSVD1_SHIFT (4U)
5320#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK)
5321#define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U)
5322#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U)
5323#define BCH_CTRL_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK)
5324#define BCH_CTRL_RSVD2_MASK (0x200U)
5325#define BCH_CTRL_RSVD2_SHIFT (9U)
5326#define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK)
5327#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U)
5328#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U)
5329#define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK)
5330#define BCH_CTRL_RSVD3_MASK (0xF800U)
5331#define BCH_CTRL_RSVD3_SHIFT (11U)
5332#define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK)
5333#define BCH_CTRL_M2M_ENABLE_MASK (0x10000U)
5334#define BCH_CTRL_M2M_ENABLE_SHIFT (16U)
5335#define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK)
5336#define BCH_CTRL_M2M_ENCODE_MASK (0x20000U)
5337#define BCH_CTRL_M2M_ENCODE_SHIFT (17U)
5338#define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK)
5339#define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U)
5340#define BCH_CTRL_M2M_LAYOUT_SHIFT (18U)
5341#define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK)
5342#define BCH_CTRL_RSVD4_MASK (0x300000U)
5343#define BCH_CTRL_RSVD4_SHIFT (20U)
5344#define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK)
5345#define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U)
5346#define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U)
5347#define BCH_CTRL_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK)
5348#define BCH_CTRL_RSVD5_MASK (0x3F800000U)
5349#define BCH_CTRL_RSVD5_SHIFT (23U)
5350#define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK)
5351#define BCH_CTRL_CLKGATE_MASK (0x40000000U)
5352#define BCH_CTRL_CLKGATE_SHIFT (30U)
5353/*! CLKGATE
5354 * 0b0..Allow BCH to operate normally.
5355 * 0b1..Do not clock BCH gates in order to minimize power consumption.
5356 */
5357#define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK)
5358#define BCH_CTRL_SFTRST_MASK (0x80000000U)
5359#define BCH_CTRL_SFTRST_SHIFT (31U)
5360/*! SFTRST
5361 * 0b0..Allow BCH to operate normally.
5362 * 0b1..Hold BCH in reset.
5363 */
5364#define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK)
5365/*! @} */
5366
5367/*! @name CTRL_SET - Hardware BCH ECC Accelerator Control Register */
5368/*! @{ */
5369#define BCH_CTRL_SET_COMPLETE_IRQ_MASK (0x1U)
5370#define BCH_CTRL_SET_COMPLETE_IRQ_SHIFT (0U)
5371#define BCH_CTRL_SET_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_MASK)
5372#define BCH_CTRL_SET_RSVD0_MASK (0x2U)
5373#define BCH_CTRL_SET_RSVD0_SHIFT (1U)
5374#define BCH_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD0_SHIFT)) & BCH_CTRL_SET_RSVD0_MASK)
5375#define BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK (0x4U)
5376#define BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT (2U)
5377#define BCH_CTRL_SET_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK)
5378#define BCH_CTRL_SET_BM_ERROR_IRQ_MASK (0x8U)
5379#define BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT (3U)
5380#define BCH_CTRL_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_SET_BM_ERROR_IRQ_MASK)
5381#define BCH_CTRL_SET_RSVD1_MASK (0xF0U)
5382#define BCH_CTRL_SET_RSVD1_SHIFT (4U)
5383#define BCH_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD1_SHIFT)) & BCH_CTRL_SET_RSVD1_MASK)
5384#define BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK (0x100U)
5385#define BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT (8U)
5386#define BCH_CTRL_SET_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK)
5387#define BCH_CTRL_SET_RSVD2_MASK (0x200U)
5388#define BCH_CTRL_SET_RSVD2_SHIFT (9U)
5389#define BCH_CTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD2_SHIFT)) & BCH_CTRL_SET_RSVD2_MASK)
5390#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK (0x400U)
5391#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT (10U)
5392#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK)
5393#define BCH_CTRL_SET_RSVD3_MASK (0xF800U)
5394#define BCH_CTRL_SET_RSVD3_SHIFT (11U)
5395#define BCH_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD3_SHIFT)) & BCH_CTRL_SET_RSVD3_MASK)
5396#define BCH_CTRL_SET_M2M_ENABLE_MASK (0x10000U)
5397#define BCH_CTRL_SET_M2M_ENABLE_SHIFT (16U)
5398#define BCH_CTRL_SET_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENABLE_SHIFT)) & BCH_CTRL_SET_M2M_ENABLE_MASK)
5399#define BCH_CTRL_SET_M2M_ENCODE_MASK (0x20000U)
5400#define BCH_CTRL_SET_M2M_ENCODE_SHIFT (17U)
5401#define BCH_CTRL_SET_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENCODE_SHIFT)) & BCH_CTRL_SET_M2M_ENCODE_MASK)
5402#define BCH_CTRL_SET_M2M_LAYOUT_MASK (0xC0000U)
5403#define BCH_CTRL_SET_M2M_LAYOUT_SHIFT (18U)
5404#define BCH_CTRL_SET_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_LAYOUT_SHIFT)) & BCH_CTRL_SET_M2M_LAYOUT_MASK)
5405#define BCH_CTRL_SET_RSVD4_MASK (0x300000U)
5406#define BCH_CTRL_SET_RSVD4_SHIFT (20U)
5407#define BCH_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD4_SHIFT)) & BCH_CTRL_SET_RSVD4_MASK)
5408#define BCH_CTRL_SET_DEBUGSYNDROME_MASK (0x400000U)
5409#define BCH_CTRL_SET_DEBUGSYNDROME_SHIFT (22U)
5410#define BCH_CTRL_SET_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_SET_DEBUGSYNDROME_MASK)
5411#define BCH_CTRL_SET_RSVD5_MASK (0x3F800000U)
5412#define BCH_CTRL_SET_RSVD5_SHIFT (23U)
5413#define BCH_CTRL_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD5_SHIFT)) & BCH_CTRL_SET_RSVD5_MASK)
5414#define BCH_CTRL_SET_CLKGATE_MASK (0x40000000U)
5415#define BCH_CTRL_SET_CLKGATE_SHIFT (30U)
5416/*! CLKGATE
5417 * 0b0..Allow BCH to operate normally.
5418 * 0b1..Do not clock BCH gates in order to minimize power consumption.
5419 */
5420#define BCH_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_CLKGATE_SHIFT)) & BCH_CTRL_SET_CLKGATE_MASK)
5421#define BCH_CTRL_SET_SFTRST_MASK (0x80000000U)
5422#define BCH_CTRL_SET_SFTRST_SHIFT (31U)
5423/*! SFTRST
5424 * 0b0..Allow BCH to operate normally.
5425 * 0b1..Hold BCH in reset.
5426 */
5427#define BCH_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_SFTRST_SHIFT)) & BCH_CTRL_SET_SFTRST_MASK)
5428/*! @} */
5429
5430/*! @name CTRL_CLR - Hardware BCH ECC Accelerator Control Register */
5431/*! @{ */
5432#define BCH_CTRL_CLR_COMPLETE_IRQ_MASK (0x1U)
5433#define BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT (0U)
5434#define BCH_CTRL_CLR_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_MASK)
5435#define BCH_CTRL_CLR_RSVD0_MASK (0x2U)
5436#define BCH_CTRL_CLR_RSVD0_SHIFT (1U)
5437#define BCH_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD0_SHIFT)) & BCH_CTRL_CLR_RSVD0_MASK)
5438#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK (0x4U)
5439#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT (2U)
5440#define BCH_CTRL_CLR_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK)
5441#define BCH_CTRL_CLR_BM_ERROR_IRQ_MASK (0x8U)
5442#define BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT (3U)
5443#define BCH_CTRL_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_CLR_BM_ERROR_IRQ_MASK)
5444#define BCH_CTRL_CLR_RSVD1_MASK (0xF0U)
5445#define BCH_CTRL_CLR_RSVD1_SHIFT (4U)
5446#define BCH_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD1_SHIFT)) & BCH_CTRL_CLR_RSVD1_MASK)
5447#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK (0x100U)
5448#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT (8U)
5449#define BCH_CTRL_CLR_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK)
5450#define BCH_CTRL_CLR_RSVD2_MASK (0x200U)
5451#define BCH_CTRL_CLR_RSVD2_SHIFT (9U)
5452#define BCH_CTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD2_SHIFT)) & BCH_CTRL_CLR_RSVD2_MASK)
5453#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK (0x400U)
5454#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT (10U)
5455#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK)
5456#define BCH_CTRL_CLR_RSVD3_MASK (0xF800U)
5457#define BCH_CTRL_CLR_RSVD3_SHIFT (11U)
5458#define BCH_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD3_SHIFT)) & BCH_CTRL_CLR_RSVD3_MASK)
5459#define BCH_CTRL_CLR_M2M_ENABLE_MASK (0x10000U)
5460#define BCH_CTRL_CLR_M2M_ENABLE_SHIFT (16U)
5461#define BCH_CTRL_CLR_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENABLE_SHIFT)) & BCH_CTRL_CLR_M2M_ENABLE_MASK)
5462#define BCH_CTRL_CLR_M2M_ENCODE_MASK (0x20000U)
5463#define BCH_CTRL_CLR_M2M_ENCODE_SHIFT (17U)
5464#define BCH_CTRL_CLR_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENCODE_SHIFT)) & BCH_CTRL_CLR_M2M_ENCODE_MASK)
5465#define BCH_CTRL_CLR_M2M_LAYOUT_MASK (0xC0000U)
5466#define BCH_CTRL_CLR_M2M_LAYOUT_SHIFT (18U)
5467#define BCH_CTRL_CLR_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_LAYOUT_SHIFT)) & BCH_CTRL_CLR_M2M_LAYOUT_MASK)
5468#define BCH_CTRL_CLR_RSVD4_MASK (0x300000U)
5469#define BCH_CTRL_CLR_RSVD4_SHIFT (20U)
5470#define BCH_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD4_SHIFT)) & BCH_CTRL_CLR_RSVD4_MASK)
5471#define BCH_CTRL_CLR_DEBUGSYNDROME_MASK (0x400000U)
5472#define BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT (22U)
5473#define BCH_CTRL_CLR_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_CLR_DEBUGSYNDROME_MASK)
5474#define BCH_CTRL_CLR_RSVD5_MASK (0x3F800000U)
5475#define BCH_CTRL_CLR_RSVD5_SHIFT (23U)
5476#define BCH_CTRL_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD5_SHIFT)) & BCH_CTRL_CLR_RSVD5_MASK)
5477#define BCH_CTRL_CLR_CLKGATE_MASK (0x40000000U)
5478#define BCH_CTRL_CLR_CLKGATE_SHIFT (30U)
5479/*! CLKGATE
5480 * 0b0..Allow BCH to operate normally.
5481 * 0b1..Do not clock BCH gates in order to minimize power consumption.
5482 */
5483#define BCH_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_CLKGATE_SHIFT)) & BCH_CTRL_CLR_CLKGATE_MASK)
5484#define BCH_CTRL_CLR_SFTRST_MASK (0x80000000U)
5485#define BCH_CTRL_CLR_SFTRST_SHIFT (31U)
5486/*! SFTRST
5487 * 0b0..Allow BCH to operate normally.
5488 * 0b1..Hold BCH in reset.
5489 */
5490#define BCH_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_SFTRST_SHIFT)) & BCH_CTRL_CLR_SFTRST_MASK)
5491/*! @} */
5492
5493/*! @name CTRL_TOG - Hardware BCH ECC Accelerator Control Register */
5494/*! @{ */
5495#define BCH_CTRL_TOG_COMPLETE_IRQ_MASK (0x1U)
5496#define BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT (0U)
5497#define BCH_CTRL_TOG_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_MASK)
5498#define BCH_CTRL_TOG_RSVD0_MASK (0x2U)
5499#define BCH_CTRL_TOG_RSVD0_SHIFT (1U)
5500#define BCH_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD0_SHIFT)) & BCH_CTRL_TOG_RSVD0_MASK)
5501#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK (0x4U)
5502#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT (2U)
5503#define BCH_CTRL_TOG_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK)
5504#define BCH_CTRL_TOG_BM_ERROR_IRQ_MASK (0x8U)
5505#define BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT (3U)
5506#define BCH_CTRL_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_TOG_BM_ERROR_IRQ_MASK)
5507#define BCH_CTRL_TOG_RSVD1_MASK (0xF0U)
5508#define BCH_CTRL_TOG_RSVD1_SHIFT (4U)
5509#define BCH_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD1_SHIFT)) & BCH_CTRL_TOG_RSVD1_MASK)
5510#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK (0x100U)
5511#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT (8U)
5512#define BCH_CTRL_TOG_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK)
5513#define BCH_CTRL_TOG_RSVD2_MASK (0x200U)
5514#define BCH_CTRL_TOG_RSVD2_SHIFT (9U)
5515#define BCH_CTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD2_SHIFT)) & BCH_CTRL_TOG_RSVD2_MASK)
5516#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK (0x400U)
5517#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT (10U)
5518#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK)
5519#define BCH_CTRL_TOG_RSVD3_MASK (0xF800U)
5520#define BCH_CTRL_TOG_RSVD3_SHIFT (11U)
5521#define BCH_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD3_SHIFT)) & BCH_CTRL_TOG_RSVD3_MASK)
5522#define BCH_CTRL_TOG_M2M_ENABLE_MASK (0x10000U)
5523#define BCH_CTRL_TOG_M2M_ENABLE_SHIFT (16U)
5524#define BCH_CTRL_TOG_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENABLE_SHIFT)) & BCH_CTRL_TOG_M2M_ENABLE_MASK)
5525#define BCH_CTRL_TOG_M2M_ENCODE_MASK (0x20000U)
5526#define BCH_CTRL_TOG_M2M_ENCODE_SHIFT (17U)
5527#define BCH_CTRL_TOG_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENCODE_SHIFT)) & BCH_CTRL_TOG_M2M_ENCODE_MASK)
5528#define BCH_CTRL_TOG_M2M_LAYOUT_MASK (0xC0000U)
5529#define BCH_CTRL_TOG_M2M_LAYOUT_SHIFT (18U)
5530#define BCH_CTRL_TOG_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_LAYOUT_SHIFT)) & BCH_CTRL_TOG_M2M_LAYOUT_MASK)
5531#define BCH_CTRL_TOG_RSVD4_MASK (0x300000U)
5532#define BCH_CTRL_TOG_RSVD4_SHIFT (20U)
5533#define BCH_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD4_SHIFT)) & BCH_CTRL_TOG_RSVD4_MASK)
5534#define BCH_CTRL_TOG_DEBUGSYNDROME_MASK (0x400000U)
5535#define BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT (22U)
5536#define BCH_CTRL_TOG_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_TOG_DEBUGSYNDROME_MASK)
5537#define BCH_CTRL_TOG_RSVD5_MASK (0x3F800000U)
5538#define BCH_CTRL_TOG_RSVD5_SHIFT (23U)
5539#define BCH_CTRL_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD5_SHIFT)) & BCH_CTRL_TOG_RSVD5_MASK)
5540#define BCH_CTRL_TOG_CLKGATE_MASK (0x40000000U)
5541#define BCH_CTRL_TOG_CLKGATE_SHIFT (30U)
5542/*! CLKGATE
5543 * 0b0..Allow BCH to operate normally.
5544 * 0b1..Do not clock BCH gates in order to minimize power consumption.
5545 */
5546#define BCH_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_CLKGATE_SHIFT)) & BCH_CTRL_TOG_CLKGATE_MASK)
5547#define BCH_CTRL_TOG_SFTRST_MASK (0x80000000U)
5548#define BCH_CTRL_TOG_SFTRST_SHIFT (31U)
5549/*! SFTRST
5550 * 0b0..Allow BCH to operate normally.
5551 * 0b1..Hold BCH in reset.
5552 */
5553#define BCH_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_SFTRST_SHIFT)) & BCH_CTRL_TOG_SFTRST_MASK)
5554/*! @} */
5555
5556/*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */
5557/*! @{ */
5558#define BCH_STATUS0_RSVD0_MASK (0x3U)
5559#define BCH_STATUS0_RSVD0_SHIFT (0U)
5560#define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK)
5561#define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U)
5562#define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U)
5563#define BCH_STATUS0_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK)
5564#define BCH_STATUS0_CORRECTED_MASK (0x8U)
5565#define BCH_STATUS0_CORRECTED_SHIFT (3U)
5566#define BCH_STATUS0_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK)
5567#define BCH_STATUS0_ALLONES_MASK (0x10U)
5568#define BCH_STATUS0_ALLONES_SHIFT (4U)
5569#define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK)
5570#define BCH_STATUS0_RSVD1_MASK (0xE0U)
5571#define BCH_STATUS0_RSVD1_SHIFT (5U)
5572#define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK)
5573#define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U)
5574#define BCH_STATUS0_STATUS_BLK0_SHIFT (8U)
5575/*! STATUS_BLK0
5576 * 0b00000000..No errors found on block.
5577 * 0b00000001..One error found on block.
5578 * 0b00000010..One errors found on block.
5579 * 0b00000011..One errors found on block.
5580 * 0b00000100..One errors found on block.
5581 * 0b11111110..Block exhibited uncorrectable errors.
5582 * 0b11111111..Page is erased.
5583 */
5584#define BCH_STATUS0_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK)
5585#define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U)
5586#define BCH_STATUS0_COMPLETED_CE_SHIFT (16U)
5587#define BCH_STATUS0_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK)
5588#define BCH_STATUS0_HANDLE_MASK (0xFFF00000U)
5589#define BCH_STATUS0_HANDLE_SHIFT (20U)
5590#define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK)
5591/*! @} */
5592
5593/*! @name STATUS0_SET - Hardware ECC Accelerator Status Register 0 */
5594/*! @{ */
5595#define BCH_STATUS0_SET_RSVD0_MASK (0x3U)
5596#define BCH_STATUS0_SET_RSVD0_SHIFT (0U)
5597#define BCH_STATUS0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_RSVD0_SHIFT)) & BCH_STATUS0_SET_RSVD0_MASK)
5598#define BCH_STATUS0_SET_UNCORRECTABLE_MASK (0x4U)
5599#define BCH_STATUS0_SET_UNCORRECTABLE_SHIFT (2U)
5600#define BCH_STATUS0_SET_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_SET_UNCORRECTABLE_MASK)
5601#define BCH_STATUS0_SET_CORRECTED_MASK (0x8U)
5602#define BCH_STATUS0_SET_CORRECTED_SHIFT (3U)
5603#define BCH_STATUS0_SET_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_CORRECTED_SHIFT)) & BCH_STATUS0_SET_CORRECTED_MASK)
5604#define BCH_STATUS0_SET_ALLONES_MASK (0x10U)
5605#define BCH_STATUS0_SET_ALLONES_SHIFT (4U)
5606#define BCH_STATUS0_SET_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_ALLONES_SHIFT)) & BCH_STATUS0_SET_ALLONES_MASK)
5607#define BCH_STATUS0_SET_RSVD1_MASK (0xE0U)
5608#define BCH_STATUS0_SET_RSVD1_SHIFT (5U)
5609#define BCH_STATUS0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_RSVD1_SHIFT)) & BCH_STATUS0_SET_RSVD1_MASK)
5610#define BCH_STATUS0_SET_STATUS_BLK0_MASK (0xFF00U)
5611#define BCH_STATUS0_SET_STATUS_BLK0_SHIFT (8U)
5612/*! STATUS_BLK0
5613 * 0b00000000..No errors found on block.
5614 * 0b00000001..One error found on block.
5615 * 0b00000010..One errors found on block.
5616 * 0b00000011..One errors found on block.
5617 * 0b00000100..One errors found on block.
5618 * 0b11111110..Block exhibited uncorrectable errors.
5619 * 0b11111111..Page is erased.
5620 */
5621#define BCH_STATUS0_SET_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_STATUS_BLK0_SHIFT)) & BCH_STATUS0_SET_STATUS_BLK0_MASK)
5622#define BCH_STATUS0_SET_COMPLETED_CE_MASK (0xF0000U)
5623#define BCH_STATUS0_SET_COMPLETED_CE_SHIFT (16U)
5624#define BCH_STATUS0_SET_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_COMPLETED_CE_SHIFT)) & BCH_STATUS0_SET_COMPLETED_CE_MASK)
5625#define BCH_STATUS0_SET_HANDLE_MASK (0xFFF00000U)
5626#define BCH_STATUS0_SET_HANDLE_SHIFT (20U)
5627#define BCH_STATUS0_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_HANDLE_SHIFT)) & BCH_STATUS0_SET_HANDLE_MASK)
5628/*! @} */
5629
5630/*! @name STATUS0_CLR - Hardware ECC Accelerator Status Register 0 */
5631/*! @{ */
5632#define BCH_STATUS0_CLR_RSVD0_MASK (0x3U)
5633#define BCH_STATUS0_CLR_RSVD0_SHIFT (0U)
5634#define BCH_STATUS0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD0_SHIFT)) & BCH_STATUS0_CLR_RSVD0_MASK)
5635#define BCH_STATUS0_CLR_UNCORRECTABLE_MASK (0x4U)
5636#define BCH_STATUS0_CLR_UNCORRECTABLE_SHIFT (2U)
5637#define BCH_STATUS0_CLR_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_CLR_UNCORRECTABLE_MASK)
5638#define BCH_STATUS0_CLR_CORRECTED_MASK (0x8U)
5639#define BCH_STATUS0_CLR_CORRECTED_SHIFT (3U)
5640#define BCH_STATUS0_CLR_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_CORRECTED_SHIFT)) & BCH_STATUS0_CLR_CORRECTED_MASK)
5641#define BCH_STATUS0_CLR_ALLONES_MASK (0x10U)
5642#define BCH_STATUS0_CLR_ALLONES_SHIFT (4U)
5643#define BCH_STATUS0_CLR_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_ALLONES_SHIFT)) & BCH_STATUS0_CLR_ALLONES_MASK)
5644#define BCH_STATUS0_CLR_RSVD1_MASK (0xE0U)
5645#define BCH_STATUS0_CLR_RSVD1_SHIFT (5U)
5646#define BCH_STATUS0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD1_SHIFT)) & BCH_STATUS0_CLR_RSVD1_MASK)
5647#define BCH_STATUS0_CLR_STATUS_BLK0_MASK (0xFF00U)
5648#define BCH_STATUS0_CLR_STATUS_BLK0_SHIFT (8U)
5649/*! STATUS_BLK0
5650 * 0b00000000..No errors found on block.
5651 * 0b00000001..One error found on block.
5652 * 0b00000010..One errors found on block.
5653 * 0b00000011..One errors found on block.
5654 * 0b00000100..One errors found on block.
5655 * 0b11111110..Block exhibited uncorrectable errors.
5656 * 0b11111111..Page is erased.
5657 */
5658#define BCH_STATUS0_CLR_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_STATUS_BLK0_SHIFT)) & BCH_STATUS0_CLR_STATUS_BLK0_MASK)
5659#define BCH_STATUS0_CLR_COMPLETED_CE_MASK (0xF0000U)
5660#define BCH_STATUS0_CLR_COMPLETED_CE_SHIFT (16U)
5661#define BCH_STATUS0_CLR_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_COMPLETED_CE_SHIFT)) & BCH_STATUS0_CLR_COMPLETED_CE_MASK)
5662#define BCH_STATUS0_CLR_HANDLE_MASK (0xFFF00000U)
5663#define BCH_STATUS0_CLR_HANDLE_SHIFT (20U)
5664#define BCH_STATUS0_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_HANDLE_SHIFT)) & BCH_STATUS0_CLR_HANDLE_MASK)
5665/*! @} */
5666
5667/*! @name STATUS0_TOG - Hardware ECC Accelerator Status Register 0 */
5668/*! @{ */
5669#define BCH_STATUS0_TOG_RSVD0_MASK (0x3U)
5670#define BCH_STATUS0_TOG_RSVD0_SHIFT (0U)
5671#define BCH_STATUS0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_RSVD0_SHIFT)) & BCH_STATUS0_TOG_RSVD0_MASK)
5672#define BCH_STATUS0_TOG_UNCORRECTABLE_MASK (0x4U)
5673#define BCH_STATUS0_TOG_UNCORRECTABLE_SHIFT (2U)
5674#define BCH_STATUS0_TOG_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_TOG_UNCORRECTABLE_MASK)
5675#define BCH_STATUS0_TOG_CORRECTED_MASK (0x8U)
5676#define BCH_STATUS0_TOG_CORRECTED_SHIFT (3U)
5677#define BCH_STATUS0_TOG_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_CORRECTED_SHIFT)) & BCH_STATUS0_TOG_CORRECTED_MASK)
5678#define BCH_STATUS0_TOG_ALLONES_MASK (0x10U)
5679#define BCH_STATUS0_TOG_ALLONES_SHIFT (4U)
5680#define BCH_STATUS0_TOG_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_ALLONES_SHIFT)) & BCH_STATUS0_TOG_ALLONES_MASK)
5681#define BCH_STATUS0_TOG_RSVD1_MASK (0xE0U)
5682#define BCH_STATUS0_TOG_RSVD1_SHIFT (5U)
5683#define BCH_STATUS0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_RSVD1_SHIFT)) & BCH_STATUS0_TOG_RSVD1_MASK)
5684#define BCH_STATUS0_TOG_STATUS_BLK0_MASK (0xFF00U)
5685#define BCH_STATUS0_TOG_STATUS_BLK0_SHIFT (8U)
5686/*! STATUS_BLK0
5687 * 0b00000000..No errors found on block.
5688 * 0b00000001..One error found on block.
5689 * 0b00000010..One errors found on block.
5690 * 0b00000011..One errors found on block.
5691 * 0b00000100..One errors found on block.
5692 * 0b11111110..Block exhibited uncorrectable errors.
5693 * 0b11111111..Page is erased.
5694 */
5695#define BCH_STATUS0_TOG_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_STATUS_BLK0_SHIFT)) & BCH_STATUS0_TOG_STATUS_BLK0_MASK)
5696#define BCH_STATUS0_TOG_COMPLETED_CE_MASK (0xF0000U)
5697#define BCH_STATUS0_TOG_COMPLETED_CE_SHIFT (16U)
5698#define BCH_STATUS0_TOG_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_COMPLETED_CE_SHIFT)) & BCH_STATUS0_TOG_COMPLETED_CE_MASK)
5699#define BCH_STATUS0_TOG_HANDLE_MASK (0xFFF00000U)
5700#define BCH_STATUS0_TOG_HANDLE_SHIFT (20U)
5701#define BCH_STATUS0_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_HANDLE_SHIFT)) & BCH_STATUS0_TOG_HANDLE_MASK)
5702/*! @} */
5703
5704/*! @name MODE - Hardware ECC Accelerator Mode Register */
5705/*! @{ */
5706#define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU)
5707#define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U)
5708#define BCH_MODE_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK)
5709#define BCH_MODE_RSVD_MASK (0xFFFFFF00U)
5710#define BCH_MODE_RSVD_SHIFT (8U)
5711#define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK)
5712/*! @} */
5713
5714/*! @name MODE_SET - Hardware ECC Accelerator Mode Register */
5715/*! @{ */
5716#define BCH_MODE_SET_ERASE_THRESHOLD_MASK (0xFFU)
5717#define BCH_MODE_SET_ERASE_THRESHOLD_SHIFT (0U)
5718#define BCH_MODE_SET_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_SET_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_SET_ERASE_THRESHOLD_MASK)
5719#define BCH_MODE_SET_RSVD_MASK (0xFFFFFF00U)
5720#define BCH_MODE_SET_RSVD_SHIFT (8U)
5721#define BCH_MODE_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_SET_RSVD_SHIFT)) & BCH_MODE_SET_RSVD_MASK)
5722/*! @} */
5723
5724/*! @name MODE_CLR - Hardware ECC Accelerator Mode Register */
5725/*! @{ */
5726#define BCH_MODE_CLR_ERASE_THRESHOLD_MASK (0xFFU)
5727#define BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT (0U)
5728#define BCH_MODE_CLR_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_CLR_ERASE_THRESHOLD_MASK)
5729#define BCH_MODE_CLR_RSVD_MASK (0xFFFFFF00U)
5730#define BCH_MODE_CLR_RSVD_SHIFT (8U)
5731#define BCH_MODE_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_CLR_RSVD_SHIFT)) & BCH_MODE_CLR_RSVD_MASK)
5732/*! @} */
5733
5734/*! @name MODE_TOG - Hardware ECC Accelerator Mode Register */
5735/*! @{ */
5736#define BCH_MODE_TOG_ERASE_THRESHOLD_MASK (0xFFU)
5737#define BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT (0U)
5738#define BCH_MODE_TOG_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_TOG_ERASE_THRESHOLD_MASK)
5739#define BCH_MODE_TOG_RSVD_MASK (0xFFFFFF00U)
5740#define BCH_MODE_TOG_RSVD_SHIFT (8U)
5741#define BCH_MODE_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_TOG_RSVD_SHIFT)) & BCH_MODE_TOG_RSVD_MASK)
5742/*! @} */
5743
5744/*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */
5745/*! @{ */
5746#define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU)
5747#define BCH_ENCODEPTR_ADDR_SHIFT (0U)
5748#define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK)
5749/*! @} */
5750
5751/*! @name ENCODEPTR_SET - Hardware BCH ECC Loopback Encode Buffer Register */
5752/*! @{ */
5753#define BCH_ENCODEPTR_SET_ADDR_MASK (0xFFFFFFFFU)
5754#define BCH_ENCODEPTR_SET_ADDR_SHIFT (0U)
5755#define BCH_ENCODEPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_SET_ADDR_SHIFT)) & BCH_ENCODEPTR_SET_ADDR_MASK)
5756/*! @} */
5757
5758/*! @name ENCODEPTR_CLR - Hardware BCH ECC Loopback Encode Buffer Register */
5759/*! @{ */
5760#define BCH_ENCODEPTR_CLR_ADDR_MASK (0xFFFFFFFFU)
5761#define BCH_ENCODEPTR_CLR_ADDR_SHIFT (0U)
5762#define BCH_ENCODEPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_CLR_ADDR_SHIFT)) & BCH_ENCODEPTR_CLR_ADDR_MASK)
5763/*! @} */
5764
5765/*! @name ENCODEPTR_TOG - Hardware BCH ECC Loopback Encode Buffer Register */
5766/*! @{ */
5767#define BCH_ENCODEPTR_TOG_ADDR_MASK (0xFFFFFFFFU)
5768#define BCH_ENCODEPTR_TOG_ADDR_SHIFT (0U)
5769#define BCH_ENCODEPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_TOG_ADDR_SHIFT)) & BCH_ENCODEPTR_TOG_ADDR_MASK)
5770/*! @} */
5771
5772/*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */
5773/*! @{ */
5774#define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU)
5775#define BCH_DATAPTR_ADDR_SHIFT (0U)
5776#define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK)
5777/*! @} */
5778
5779/*! @name DATAPTR_SET - Hardware BCH ECC Loopback Data Buffer Register */
5780/*! @{ */
5781#define BCH_DATAPTR_SET_ADDR_MASK (0xFFFFFFFFU)
5782#define BCH_DATAPTR_SET_ADDR_SHIFT (0U)
5783#define BCH_DATAPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_SET_ADDR_SHIFT)) & BCH_DATAPTR_SET_ADDR_MASK)
5784/*! @} */
5785
5786/*! @name DATAPTR_CLR - Hardware BCH ECC Loopback Data Buffer Register */
5787/*! @{ */
5788#define BCH_DATAPTR_CLR_ADDR_MASK (0xFFFFFFFFU)
5789#define BCH_DATAPTR_CLR_ADDR_SHIFT (0U)
5790#define BCH_DATAPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_CLR_ADDR_SHIFT)) & BCH_DATAPTR_CLR_ADDR_MASK)
5791/*! @} */
5792
5793/*! @name DATAPTR_TOG - Hardware BCH ECC Loopback Data Buffer Register */
5794/*! @{ */
5795#define BCH_DATAPTR_TOG_ADDR_MASK (0xFFFFFFFFU)
5796#define BCH_DATAPTR_TOG_ADDR_SHIFT (0U)
5797#define BCH_DATAPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_TOG_ADDR_SHIFT)) & BCH_DATAPTR_TOG_ADDR_MASK)
5798/*! @} */
5799
5800/*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */
5801/*! @{ */
5802#define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU)
5803#define BCH_METAPTR_ADDR_SHIFT (0U)
5804#define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK)
5805/*! @} */
5806
5807/*! @name METAPTR_SET - Hardware BCH ECC Loopback Metadata Buffer Register */
5808/*! @{ */
5809#define BCH_METAPTR_SET_ADDR_MASK (0xFFFFFFFFU)
5810#define BCH_METAPTR_SET_ADDR_SHIFT (0U)
5811#define BCH_METAPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_SET_ADDR_SHIFT)) & BCH_METAPTR_SET_ADDR_MASK)
5812/*! @} */
5813
5814/*! @name METAPTR_CLR - Hardware BCH ECC Loopback Metadata Buffer Register */
5815/*! @{ */
5816#define BCH_METAPTR_CLR_ADDR_MASK (0xFFFFFFFFU)
5817#define BCH_METAPTR_CLR_ADDR_SHIFT (0U)
5818#define BCH_METAPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_CLR_ADDR_SHIFT)) & BCH_METAPTR_CLR_ADDR_MASK)
5819/*! @} */
5820
5821/*! @name METAPTR_TOG - Hardware BCH ECC Loopback Metadata Buffer Register */
5822/*! @{ */
5823#define BCH_METAPTR_TOG_ADDR_MASK (0xFFFFFFFFU)
5824#define BCH_METAPTR_TOG_ADDR_SHIFT (0U)
5825#define BCH_METAPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_TOG_ADDR_SHIFT)) & BCH_METAPTR_TOG_ADDR_MASK)
5826/*! @} */
5827
5828/*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */
5829/*! @{ */
5830#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U)
5831#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U)
5832#define BCH_LAYOUTSELECT_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK)
5833#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU)
5834#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U)
5835#define BCH_LAYOUTSELECT_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK)
5836#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U)
5837#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U)
5838#define BCH_LAYOUTSELECT_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK)
5839#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U)
5840#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U)
5841#define BCH_LAYOUTSELECT_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK)
5842#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U)
5843#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U)
5844#define BCH_LAYOUTSELECT_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK)
5845#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U)
5846#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U)
5847#define BCH_LAYOUTSELECT_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK)
5848#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U)
5849#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U)
5850#define BCH_LAYOUTSELECT_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK)
5851#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U)
5852#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U)
5853#define BCH_LAYOUTSELECT_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK)
5854#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U)
5855#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U)
5856#define BCH_LAYOUTSELECT_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK)
5857#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U)
5858#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U)
5859#define BCH_LAYOUTSELECT_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK)
5860#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U)
5861#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U)
5862#define BCH_LAYOUTSELECT_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK)
5863#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U)
5864#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U)
5865#define BCH_LAYOUTSELECT_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK)
5866#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U)
5867#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U)
5868#define BCH_LAYOUTSELECT_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK)
5869#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U)
5870#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U)
5871#define BCH_LAYOUTSELECT_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK)
5872#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U)
5873#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U)
5874#define BCH_LAYOUTSELECT_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK)
5875#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U)
5876#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U)
5877#define BCH_LAYOUTSELECT_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK)
5878/*! @} */
5879
5880/*! @name LAYOUTSELECT_SET - Hardware ECC Accelerator Layout Select Register */
5881/*! @{ */
5882#define BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK (0x3U)
5883#define BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT (0U)
5884#define BCH_LAYOUTSELECT_SET_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK)
5885#define BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK (0xCU)
5886#define BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT (2U)
5887#define BCH_LAYOUTSELECT_SET_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK)
5888#define BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK (0x30U)
5889#define BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT (4U)
5890#define BCH_LAYOUTSELECT_SET_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK)
5891#define BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK (0xC0U)
5892#define BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT (6U)
5893#define BCH_LAYOUTSELECT_SET_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK)
5894#define BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK (0x300U)
5895#define BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT (8U)
5896#define BCH_LAYOUTSELECT_SET_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK)
5897#define BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK (0xC00U)
5898#define BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT (10U)
5899#define BCH_LAYOUTSELECT_SET_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK)
5900#define BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK (0x3000U)
5901#define BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT (12U)
5902#define BCH_LAYOUTSELECT_SET_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK)
5903#define BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK (0xC000U)
5904#define BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT (14U)
5905#define BCH_LAYOUTSELECT_SET_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK)
5906#define BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK (0x30000U)
5907#define BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT (16U)
5908#define BCH_LAYOUTSELECT_SET_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK)
5909#define BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK (0xC0000U)
5910#define BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT (18U)
5911#define BCH_LAYOUTSELECT_SET_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK)
5912#define BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK (0x300000U)
5913#define BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT (20U)
5914#define BCH_LAYOUTSELECT_SET_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK)
5915#define BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK (0xC00000U)
5916#define BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT (22U)
5917#define BCH_LAYOUTSELECT_SET_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK)
5918#define BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK (0x3000000U)
5919#define BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT (24U)
5920#define BCH_LAYOUTSELECT_SET_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK)
5921#define BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK (0xC000000U)
5922#define BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT (26U)
5923#define BCH_LAYOUTSELECT_SET_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK)
5924#define BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK (0x30000000U)
5925#define BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT (28U)
5926#define BCH_LAYOUTSELECT_SET_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK)
5927#define BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK (0xC0000000U)
5928#define BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT (30U)
5929#define BCH_LAYOUTSELECT_SET_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK)
5930/*! @} */
5931
5932/*! @name LAYOUTSELECT_CLR - Hardware ECC Accelerator Layout Select Register */
5933/*! @{ */
5934#define BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK (0x3U)
5935#define BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT (0U)
5936#define BCH_LAYOUTSELECT_CLR_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK)
5937#define BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK (0xCU)
5938#define BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT (2U)
5939#define BCH_LAYOUTSELECT_CLR_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK)
5940#define BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK (0x30U)
5941#define BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT (4U)
5942#define BCH_LAYOUTSELECT_CLR_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK)
5943#define BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK (0xC0U)
5944#define BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT (6U)
5945#define BCH_LAYOUTSELECT_CLR_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK)
5946#define BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK (0x300U)
5947#define BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT (8U)
5948#define BCH_LAYOUTSELECT_CLR_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK)
5949#define BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK (0xC00U)
5950#define BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT (10U)
5951#define BCH_LAYOUTSELECT_CLR_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK)
5952#define BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK (0x3000U)
5953#define BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT (12U)
5954#define BCH_LAYOUTSELECT_CLR_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK)
5955#define BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK (0xC000U)
5956#define BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT (14U)
5957#define BCH_LAYOUTSELECT_CLR_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK)
5958#define BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK (0x30000U)
5959#define BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT (16U)
5960#define BCH_LAYOUTSELECT_CLR_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK)
5961#define BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK (0xC0000U)
5962#define BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT (18U)
5963#define BCH_LAYOUTSELECT_CLR_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK)
5964#define BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK (0x300000U)
5965#define BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT (20U)
5966#define BCH_LAYOUTSELECT_CLR_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK)
5967#define BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK (0xC00000U)
5968#define BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT (22U)
5969#define BCH_LAYOUTSELECT_CLR_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK)
5970#define BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK (0x3000000U)
5971#define BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT (24U)
5972#define BCH_LAYOUTSELECT_CLR_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK)
5973#define BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK (0xC000000U)
5974#define BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT (26U)
5975#define BCH_LAYOUTSELECT_CLR_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK)
5976#define BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK (0x30000000U)
5977#define BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT (28U)
5978#define BCH_LAYOUTSELECT_CLR_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK)
5979#define BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK (0xC0000000U)
5980#define BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT (30U)
5981#define BCH_LAYOUTSELECT_CLR_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK)
5982/*! @} */
5983
5984/*! @name LAYOUTSELECT_TOG - Hardware ECC Accelerator Layout Select Register */
5985/*! @{ */
5986#define BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK (0x3U)
5987#define BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT (0U)
5988#define BCH_LAYOUTSELECT_TOG_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK)
5989#define BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK (0xCU)
5990#define BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT (2U)
5991#define BCH_LAYOUTSELECT_TOG_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK)
5992#define BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK (0x30U)
5993#define BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT (4U)
5994#define BCH_LAYOUTSELECT_TOG_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK)
5995#define BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK (0xC0U)
5996#define BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT (6U)
5997#define BCH_LAYOUTSELECT_TOG_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK)
5998#define BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK (0x300U)
5999#define BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT (8U)
6000#define BCH_LAYOUTSELECT_TOG_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK)
6001#define BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK (0xC00U)
6002#define BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT (10U)
6003#define BCH_LAYOUTSELECT_TOG_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK)
6004#define BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK (0x3000U)
6005#define BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT (12U)
6006#define BCH_LAYOUTSELECT_TOG_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK)
6007#define BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK (0xC000U)
6008#define BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT (14U)
6009#define BCH_LAYOUTSELECT_TOG_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK)
6010#define BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK (0x30000U)
6011#define BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT (16U)
6012#define BCH_LAYOUTSELECT_TOG_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK)
6013#define BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK (0xC0000U)
6014#define BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT (18U)
6015#define BCH_LAYOUTSELECT_TOG_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK)
6016#define BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK (0x300000U)
6017#define BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT (20U)
6018#define BCH_LAYOUTSELECT_TOG_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK)
6019#define BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK (0xC00000U)
6020#define BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT (22U)
6021#define BCH_LAYOUTSELECT_TOG_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK)
6022#define BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK (0x3000000U)
6023#define BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT (24U)
6024#define BCH_LAYOUTSELECT_TOG_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK)
6025#define BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK (0xC000000U)
6026#define BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT (26U)
6027#define BCH_LAYOUTSELECT_TOG_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK)
6028#define BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK (0x30000000U)
6029#define BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT (28U)
6030#define BCH_LAYOUTSELECT_TOG_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK)
6031#define BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK (0xC0000000U)
6032#define BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT (30U)
6033#define BCH_LAYOUTSELECT_TOG_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK)
6034/*! @} */
6035
6036/*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */
6037/*! @{ */
6038#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
6039#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U)
6040#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK)
6041#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
6042#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
6043#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK)
6044#define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF800U)
6045#define BCH_FLASH0LAYOUT0_ECC0_SHIFT (11U)
6046/*! ECC0
6047 * 0b00000..No ECC to be performed
6048 * 0b00001..ECC 2 to be performed
6049 * 0b00010..ECC 4 to be performed
6050 * 0b11110..ECC 60 to be performed
6051 * 0b11111..ECC 62 to be performed
6052 */
6053#define BCH_FLASH0LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK)
6054#define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U)
6055#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U)
6056#define BCH_FLASH0LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK)
6057#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U)
6058#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U)
6059#define BCH_FLASH0LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK)
6060/*! @} */
6061
6062/*! @name FLASH0LAYOUT0_SET - Hardware BCH ECC Flash 0 Layout 0 Register */
6063/*! @{ */
6064#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU)
6065#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT (0U)
6066#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK)
6067#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U)
6068#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U)
6069#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_MASK)
6070#define BCH_FLASH0LAYOUT0_SET_ECC0_MASK (0xF800U)
6071#define BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT (11U)
6072/*! ECC0
6073 * 0b00000..No ECC to be performed
6074 * 0b00001..ECC 2 to be performed
6075 * 0b00010..ECC 4 to be performed
6076 * 0b11110..ECC 60 to be performed
6077 * 0b11111..ECC 62 to be performed
6078 */
6079#define BCH_FLASH0LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_SET_ECC0_MASK)
6080#define BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK (0xFF0000U)
6081#define BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT (16U)
6082#define BCH_FLASH0LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK)
6083#define BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U)
6084#define BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT (24U)
6085#define BCH_FLASH0LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK)
6086/*! @} */
6087
6088/*! @name FLASH0LAYOUT0_CLR - Hardware BCH ECC Flash 0 Layout 0 Register */
6089/*! @{ */
6090#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU)
6091#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U)
6092#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK)
6093#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U)
6094#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U)
6095#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_MASK)
6096#define BCH_FLASH0LAYOUT0_CLR_ECC0_MASK (0xF800U)
6097#define BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT (11U)
6098/*! ECC0
6099 * 0b00000..No ECC to be performed
6100 * 0b00001..ECC 2 to be performed
6101 * 0b00010..ECC 4 to be performed
6102 * 0b11110..ECC 60 to be performed
6103 * 0b11111..ECC 62 to be performed
6104 */
6105#define BCH_FLASH0LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_ECC0_MASK)
6106#define BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U)
6107#define BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT (16U)
6108#define BCH_FLASH0LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK)
6109#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U)
6110#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT (24U)
6111#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK)
6112/*! @} */
6113
6114/*! @name FLASH0LAYOUT0_TOG - Hardware BCH ECC Flash 0 Layout 0 Register */
6115/*! @{ */
6116#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU)
6117#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U)
6118#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK)
6119#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U)
6120#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U)
6121#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_MASK)
6122#define BCH_FLASH0LAYOUT0_TOG_ECC0_MASK (0xF800U)
6123#define BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT (11U)
6124/*! ECC0
6125 * 0b00000..No ECC to be performed
6126 * 0b00001..ECC 2 to be performed
6127 * 0b00010..ECC 4 to be performed
6128 * 0b11110..ECC 60 to be performed
6129 * 0b11111..ECC 62 to be performed
6130 */
6131#define BCH_FLASH0LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_ECC0_MASK)
6132#define BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U)
6133#define BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT (16U)
6134#define BCH_FLASH0LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK)
6135#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U)
6136#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT (24U)
6137#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK)
6138/*! @} */
6139
6140/*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */
6141/*! @{ */
6142#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
6143#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U)
6144#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK)
6145#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
6146#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
6147#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK)
6148#define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF800U)
6149#define BCH_FLASH0LAYOUT1_ECCN_SHIFT (11U)
6150/*! ECCN
6151 * 0b00000..No ECC to be performed
6152 * 0b00001..ECC 2 to be performed
6153 * 0b00010..ECC 4 to be performed
6154 * 0b11110..ECC 60 to be performed
6155 * 0b11111..ECC 62 to be performed
6156 */
6157#define BCH_FLASH0LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK)
6158#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
6159#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U)
6160#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK)
6161/*! @} */
6162
6163/*! @name FLASH0LAYOUT1_SET - Hardware BCH ECC Flash 0 Layout 1 Register */
6164/*! @{ */
6165#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU)
6166#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT (0U)
6167#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK)
6168#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U)
6169#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U)
6170#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_MASK)
6171#define BCH_FLASH0LAYOUT1_SET_ECCN_MASK (0xF800U)
6172#define BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT (11U)
6173/*! ECCN
6174 * 0b00000..No ECC to be performed
6175 * 0b00001..ECC 2 to be performed
6176 * 0b00010..ECC 4 to be performed
6177 * 0b11110..ECC 60 to be performed
6178 * 0b11111..ECC 62 to be performed
6179 */
6180#define BCH_FLASH0LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_SET_ECCN_MASK)
6181#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U)
6182#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT (16U)
6183#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK)
6184/*! @} */
6185
6186/*! @name FLASH0LAYOUT1_CLR - Hardware BCH ECC Flash 0 Layout 1 Register */
6187/*! @{ */
6188#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU)
6189#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U)
6190#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK)
6191#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U)
6192#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U)
6193#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_MASK)
6194#define BCH_FLASH0LAYOUT1_CLR_ECCN_MASK (0xF800U)
6195#define BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT (11U)
6196/*! ECCN
6197 * 0b00000..No ECC to be performed
6198 * 0b00001..ECC 2 to be performed
6199 * 0b00010..ECC 4 to be performed
6200 * 0b11110..ECC 60 to be performed
6201 * 0b11111..ECC 62 to be performed
6202 */
6203#define BCH_FLASH0LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_ECCN_MASK)
6204#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U)
6205#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U)
6206#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK)
6207/*! @} */
6208
6209/*! @name FLASH0LAYOUT1_TOG - Hardware BCH ECC Flash 0 Layout 1 Register */
6210/*! @{ */
6211#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU)
6212#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U)
6213#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK)
6214#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U)
6215#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U)
6216#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_MASK)
6217#define BCH_FLASH0LAYOUT1_TOG_ECCN_MASK (0xF800U)
6218#define BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT (11U)
6219/*! ECCN
6220 * 0b00000..No ECC to be performed
6221 * 0b00001..ECC 2 to be performed
6222 * 0b00010..ECC 4 to be performed
6223 * 0b11110..ECC 60 to be performed
6224 * 0b11111..ECC 62 to be performed
6225 */
6226#define BCH_FLASH0LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_ECCN_MASK)
6227#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U)
6228#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U)
6229#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK)
6230/*! @} */
6231
6232/*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */
6233/*! @{ */
6234#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
6235#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U)
6236#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK)
6237#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
6238#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
6239#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK)
6240#define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF800U)
6241#define BCH_FLASH1LAYOUT0_ECC0_SHIFT (11U)
6242/*! ECC0
6243 * 0b00000..No ECC to be performed
6244 * 0b00001..ECC 2 to be performed
6245 * 0b00010..ECC 4 to be performed
6246 * 0b11110..ECC 60 to be performed
6247 * 0b11111..ECC 62 to be performed
6248 */
6249#define BCH_FLASH1LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK)
6250#define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U)
6251#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U)
6252#define BCH_FLASH1LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK)
6253#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U)
6254#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U)
6255#define BCH_FLASH1LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK)
6256/*! @} */
6257
6258/*! @name FLASH1LAYOUT0_SET - Hardware BCH ECC Flash 1 Layout 0 Register */
6259/*! @{ */
6260#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU)
6261#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT (0U)
6262#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK)
6263#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U)
6264#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U)
6265#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_MASK)
6266#define BCH_FLASH1LAYOUT0_SET_ECC0_MASK (0xF800U)
6267#define BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT (11U)
6268/*! ECC0
6269 * 0b00000..No ECC to be performed
6270 * 0b00001..ECC 2 to be performed
6271 * 0b00010..ECC 4 to be performed
6272 * 0b11110..ECC 60 to be performed
6273 * 0b11111..ECC 62 to be performed
6274 */
6275#define BCH_FLASH1LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_SET_ECC0_MASK)
6276#define BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK (0xFF0000U)
6277#define BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT (16U)
6278#define BCH_FLASH1LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK)
6279#define BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U)
6280#define BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT (24U)
6281#define BCH_FLASH1LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK)
6282/*! @} */
6283
6284/*! @name FLASH1LAYOUT0_CLR - Hardware BCH ECC Flash 1 Layout 0 Register */
6285/*! @{ */
6286#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU)
6287#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U)
6288#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK)
6289#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U)
6290#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U)
6291#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_MASK)
6292#define BCH_FLASH1LAYOUT0_CLR_ECC0_MASK (0xF800U)
6293#define BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT (11U)
6294/*! ECC0
6295 * 0b00000..No ECC to be performed
6296 * 0b00001..ECC 2 to be performed
6297 * 0b00010..ECC 4 to be performed
6298 * 0b11110..ECC 60 to be performed
6299 * 0b11111..ECC 62 to be performed
6300 */
6301#define BCH_FLASH1LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_ECC0_MASK)
6302#define BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U)
6303#define BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT (16U)
6304#define BCH_FLASH1LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK)
6305#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U)
6306#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT (24U)
6307#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK)
6308/*! @} */
6309
6310/*! @name FLASH1LAYOUT0_TOG - Hardware BCH ECC Flash 1 Layout 0 Register */
6311/*! @{ */
6312#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU)
6313#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U)
6314#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK)
6315#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U)
6316#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U)
6317#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_MASK)
6318#define BCH_FLASH1LAYOUT0_TOG_ECC0_MASK (0xF800U)
6319#define BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT (11U)
6320/*! ECC0
6321 * 0b00000..No ECC to be performed
6322 * 0b00001..ECC 2 to be performed
6323 * 0b00010..ECC 4 to be performed
6324 * 0b11110..ECC 60 to be performed
6325 * 0b11111..ECC 62 to be performed
6326 */
6327#define BCH_FLASH1LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_ECC0_MASK)
6328#define BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U)
6329#define BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT (16U)
6330#define BCH_FLASH1LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK)
6331#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U)
6332#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT (24U)
6333#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK)
6334/*! @} */
6335
6336/*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */
6337/*! @{ */
6338#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
6339#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U)
6340#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK)
6341#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
6342#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
6343#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK)
6344#define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF800U)
6345#define BCH_FLASH1LAYOUT1_ECCN_SHIFT (11U)
6346/*! ECCN
6347 * 0b00000..No ECC to be performed
6348 * 0b00001..ECC 2 to be performed
6349 * 0b00010..ECC 4 to be performed
6350 * 0b11110..ECC 60 to be performed
6351 * 0b11111..ECC 62 to be performed
6352 */
6353#define BCH_FLASH1LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK)
6354#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
6355#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U)
6356#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK)
6357/*! @} */
6358
6359/*! @name FLASH1LAYOUT1_SET - Hardware BCH ECC Flash 1 Layout 1 Register */
6360/*! @{ */
6361#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU)
6362#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT (0U)
6363#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK)
6364#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U)
6365#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U)
6366#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_MASK)
6367#define BCH_FLASH1LAYOUT1_SET_ECCN_MASK (0xF800U)
6368#define BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT (11U)
6369/*! ECCN
6370 * 0b00000..No ECC to be performed
6371 * 0b00001..ECC 2 to be performed
6372 * 0b00010..ECC 4 to be performed
6373 * 0b11110..ECC 60 to be performed
6374 * 0b11111..ECC 62 to be performed
6375 */
6376#define BCH_FLASH1LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_SET_ECCN_MASK)
6377#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U)
6378#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT (16U)
6379#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK)
6380/*! @} */
6381
6382/*! @name FLASH1LAYOUT1_CLR - Hardware BCH ECC Flash 1 Layout 1 Register */
6383/*! @{ */
6384#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU)
6385#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U)
6386#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK)
6387#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U)
6388#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U)
6389#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_MASK)
6390#define BCH_FLASH1LAYOUT1_CLR_ECCN_MASK (0xF800U)
6391#define BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT (11U)
6392/*! ECCN
6393 * 0b00000..No ECC to be performed
6394 * 0b00001..ECC 2 to be performed
6395 * 0b00010..ECC 4 to be performed
6396 * 0b11110..ECC 60 to be performed
6397 * 0b11111..ECC 62 to be performed
6398 */
6399#define BCH_FLASH1LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_ECCN_MASK)
6400#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U)
6401#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U)
6402#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK)
6403/*! @} */
6404
6405/*! @name FLASH1LAYOUT1_TOG - Hardware BCH ECC Flash 1 Layout 1 Register */
6406/*! @{ */
6407#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU)
6408#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U)
6409#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK)
6410#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U)
6411#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U)
6412#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_MASK)
6413#define BCH_FLASH1LAYOUT1_TOG_ECCN_MASK (0xF800U)
6414#define BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT (11U)
6415/*! ECCN
6416 * 0b00000..No ECC to be performed
6417 * 0b00001..ECC 2 to be performed
6418 * 0b00010..ECC 4 to be performed
6419 * 0b11110..ECC 60 to be performed
6420 * 0b11111..ECC 62 to be performed
6421 */
6422#define BCH_FLASH1LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_ECCN_MASK)
6423#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U)
6424#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U)
6425#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK)
6426/*! @} */
6427
6428/*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */
6429/*! @{ */
6430#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
6431#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U)
6432#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK)
6433#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
6434#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
6435#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK)
6436#define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF800U)
6437#define BCH_FLASH2LAYOUT0_ECC0_SHIFT (11U)
6438/*! ECC0
6439 * 0b00000..No ECC to be performed
6440 * 0b00001..ECC 2 to be performed
6441 * 0b00010..ECC 4 to be performed
6442 * 0b11110..ECC 60 to be performed
6443 * 0b11111..ECC 62 to be performed
6444 */
6445#define BCH_FLASH2LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK)
6446#define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U)
6447#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U)
6448#define BCH_FLASH2LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK)
6449#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U)
6450#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U)
6451#define BCH_FLASH2LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK)
6452/*! @} */
6453
6454/*! @name FLASH2LAYOUT0_SET - Hardware BCH ECC Flash 2 Layout 0 Register */
6455/*! @{ */
6456#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU)
6457#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT (0U)
6458#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK)
6459#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U)
6460#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U)
6461#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_MASK)
6462#define BCH_FLASH2LAYOUT0_SET_ECC0_MASK (0xF800U)
6463#define BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT (11U)
6464/*! ECC0
6465 * 0b00000..No ECC to be performed
6466 * 0b00001..ECC 2 to be performed
6467 * 0b00010..ECC 4 to be performed
6468 * 0b11110..ECC 60 to be performed
6469 * 0b11111..ECC 62 to be performed
6470 */
6471#define BCH_FLASH2LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_SET_ECC0_MASK)
6472#define BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK (0xFF0000U)
6473#define BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT (16U)
6474#define BCH_FLASH2LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK)
6475#define BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U)
6476#define BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT (24U)
6477#define BCH_FLASH2LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK)
6478/*! @} */
6479
6480/*! @name FLASH2LAYOUT0_CLR - Hardware BCH ECC Flash 2 Layout 0 Register */
6481/*! @{ */
6482#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU)
6483#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U)
6484#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK)
6485#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U)
6486#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U)
6487#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_MASK)
6488#define BCH_FLASH2LAYOUT0_CLR_ECC0_MASK (0xF800U)
6489#define BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT (11U)
6490/*! ECC0
6491 * 0b00000..No ECC to be performed
6492 * 0b00001..ECC 2 to be performed
6493 * 0b00010..ECC 4 to be performed
6494 * 0b11110..ECC 60 to be performed
6495 * 0b11111..ECC 62 to be performed
6496 */
6497#define BCH_FLASH2LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_ECC0_MASK)
6498#define BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U)
6499#define BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT (16U)
6500#define BCH_FLASH2LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK)
6501#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U)
6502#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT (24U)
6503#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK)
6504/*! @} */
6505
6506/*! @name FLASH2LAYOUT0_TOG - Hardware BCH ECC Flash 2 Layout 0 Register */
6507/*! @{ */
6508#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU)
6509#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U)
6510#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK)
6511#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U)
6512#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U)
6513#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_MASK)
6514#define BCH_FLASH2LAYOUT0_TOG_ECC0_MASK (0xF800U)
6515#define BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT (11U)
6516/*! ECC0
6517 * 0b00000..No ECC to be performed
6518 * 0b00001..ECC 2 to be performed
6519 * 0b00010..ECC 4 to be performed
6520 * 0b11110..ECC 60 to be performed
6521 * 0b11111..ECC 62 to be performed
6522 */
6523#define BCH_FLASH2LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_ECC0_MASK)
6524#define BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U)
6525#define BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT (16U)
6526#define BCH_FLASH2LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK)
6527#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U)
6528#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT (24U)
6529#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK)
6530/*! @} */
6531
6532/*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */
6533/*! @{ */
6534#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
6535#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U)
6536#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK)
6537#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
6538#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
6539#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK)
6540#define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF800U)
6541#define BCH_FLASH2LAYOUT1_ECCN_SHIFT (11U)
6542/*! ECCN
6543 * 0b00000..No ECC to be performed
6544 * 0b00001..ECC 2 to be performed
6545 * 0b00010..ECC 4 to be performed
6546 * 0b11110..ECC 60 to be performed
6547 * 0b11111..ECC 62 to be performed
6548 */
6549#define BCH_FLASH2LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK)
6550#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
6551#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U)
6552#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK)
6553/*! @} */
6554
6555/*! @name FLASH2LAYOUT1_SET - Hardware BCH ECC Flash 2 Layout 1 Register */
6556/*! @{ */
6557#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU)
6558#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT (0U)
6559#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK)
6560#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U)
6561#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U)
6562#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_MASK)
6563#define BCH_FLASH2LAYOUT1_SET_ECCN_MASK (0xF800U)
6564#define BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT (11U)
6565/*! ECCN
6566 * 0b00000..No ECC to be performed
6567 * 0b00001..ECC 2 to be performed
6568 * 0b00010..ECC 4 to be performed
6569 * 0b11110..ECC 60 to be performed
6570 * 0b11111..ECC 62 to be performed
6571 */
6572#define BCH_FLASH2LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_SET_ECCN_MASK)
6573#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U)
6574#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT (16U)
6575#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK)
6576/*! @} */
6577
6578/*! @name FLASH2LAYOUT1_CLR - Hardware BCH ECC Flash 2 Layout 1 Register */
6579/*! @{ */
6580#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU)
6581#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U)
6582#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK)
6583#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U)
6584#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U)
6585#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_MASK)
6586#define BCH_FLASH2LAYOUT1_CLR_ECCN_MASK (0xF800U)
6587#define BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT (11U)
6588/*! ECCN
6589 * 0b00000..No ECC to be performed
6590 * 0b00001..ECC 2 to be performed
6591 * 0b00010..ECC 4 to be performed
6592 * 0b11110..ECC 60 to be performed
6593 * 0b11111..ECC 62 to be performed
6594 */
6595#define BCH_FLASH2LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_ECCN_MASK)
6596#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U)
6597#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U)
6598#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK)
6599/*! @} */
6600
6601/*! @name FLASH2LAYOUT1_TOG - Hardware BCH ECC Flash 2 Layout 1 Register */
6602/*! @{ */
6603#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU)
6604#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U)
6605#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK)
6606#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U)
6607#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U)
6608#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_MASK)
6609#define BCH_FLASH2LAYOUT1_TOG_ECCN_MASK (0xF800U)
6610#define BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT (11U)
6611/*! ECCN
6612 * 0b00000..No ECC to be performed
6613 * 0b00001..ECC 2 to be performed
6614 * 0b00010..ECC 4 to be performed
6615 * 0b11110..ECC 60 to be performed
6616 * 0b11111..ECC 62 to be performed
6617 */
6618#define BCH_FLASH2LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_ECCN_MASK)
6619#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U)
6620#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U)
6621#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK)
6622/*! @} */
6623
6624/*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */
6625/*! @{ */
6626#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
6627#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U)
6628#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK)
6629#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
6630#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
6631#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK)
6632#define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF800U)
6633#define BCH_FLASH3LAYOUT0_ECC0_SHIFT (11U)
6634/*! ECC0
6635 * 0b00000..No ECC to be performed
6636 * 0b00001..ECC 2 to be performed
6637 * 0b00010..ECC 4 to be performed
6638 * 0b11110..ECC 60 to be performed
6639 * 0b11111..ECC 62 to be performed
6640 */
6641#define BCH_FLASH3LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK)
6642#define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U)
6643#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U)
6644#define BCH_FLASH3LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK)
6645#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U)
6646#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U)
6647#define BCH_FLASH3LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK)
6648/*! @} */
6649
6650/*! @name FLASH3LAYOUT0_SET - Hardware BCH ECC Flash 3 Layout 0 Register */
6651/*! @{ */
6652#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU)
6653#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT (0U)
6654#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK)
6655#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U)
6656#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U)
6657#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_MASK)
6658#define BCH_FLASH3LAYOUT0_SET_ECC0_MASK (0xF800U)
6659#define BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT (11U)
6660/*! ECC0
6661 * 0b00000..No ECC to be performed
6662 * 0b00001..ECC 2 to be performed
6663 * 0b00010..ECC 4 to be performed
6664 * 0b11110..ECC 60 to be performed
6665 * 0b11111..ECC 62 to be performed
6666 */
6667#define BCH_FLASH3LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_SET_ECC0_MASK)
6668#define BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK (0xFF0000U)
6669#define BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT (16U)
6670#define BCH_FLASH3LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK)
6671#define BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U)
6672#define BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT (24U)
6673#define BCH_FLASH3LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK)
6674/*! @} */
6675
6676/*! @name FLASH3LAYOUT0_CLR - Hardware BCH ECC Flash 3 Layout 0 Register */
6677/*! @{ */
6678#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU)
6679#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U)
6680#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK)
6681#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U)
6682#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U)
6683#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_MASK)
6684#define BCH_FLASH3LAYOUT0_CLR_ECC0_MASK (0xF800U)
6685#define BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT (11U)
6686/*! ECC0
6687 * 0b00000..No ECC to be performed
6688 * 0b00001..ECC 2 to be performed
6689 * 0b00010..ECC 4 to be performed
6690 * 0b11110..ECC 60 to be performed
6691 * 0b11111..ECC 62 to be performed
6692 */
6693#define BCH_FLASH3LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_ECC0_MASK)
6694#define BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U)
6695#define BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT (16U)
6696#define BCH_FLASH3LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK)
6697#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U)
6698#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT (24U)
6699#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK)
6700/*! @} */
6701
6702/*! @name FLASH3LAYOUT0_TOG - Hardware BCH ECC Flash 3 Layout 0 Register */
6703/*! @{ */
6704#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU)
6705#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U)
6706#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK)
6707#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U)
6708#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U)
6709#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_MASK)
6710#define BCH_FLASH3LAYOUT0_TOG_ECC0_MASK (0xF800U)
6711#define BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT (11U)
6712/*! ECC0
6713 * 0b00000..No ECC to be performed
6714 * 0b00001..ECC 2 to be performed
6715 * 0b00010..ECC 4 to be performed
6716 * 0b11110..ECC 60 to be performed
6717 * 0b11111..ECC 62 to be performed
6718 */
6719#define BCH_FLASH3LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_ECC0_MASK)
6720#define BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U)
6721#define BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT (16U)
6722#define BCH_FLASH3LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK)
6723#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U)
6724#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT (24U)
6725#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK)
6726/*! @} */
6727
6728/*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */
6729/*! @{ */
6730#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
6731#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U)
6732#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK)
6733#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
6734#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
6735#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK)
6736#define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF800U)
6737#define BCH_FLASH3LAYOUT1_ECCN_SHIFT (11U)
6738/*! ECCN
6739 * 0b00000..No ECC to be performed
6740 * 0b00001..ECC 2 to be performed
6741 * 0b00010..ECC 4 to be performed
6742 * 0b11110..ECC 60 to be performed
6743 * 0b11111..ECC 62 to be performed
6744 */
6745#define BCH_FLASH3LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK)
6746#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
6747#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U)
6748#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK)
6749/*! @} */
6750
6751/*! @name FLASH3LAYOUT1_SET - Hardware BCH ECC Flash 3 Layout 1 Register */
6752/*! @{ */
6753#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU)
6754#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT (0U)
6755#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK)
6756#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U)
6757#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U)
6758#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_MASK)
6759#define BCH_FLASH3LAYOUT1_SET_ECCN_MASK (0xF800U)
6760#define BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT (11U)
6761/*! ECCN
6762 * 0b00000..No ECC to be performed
6763 * 0b00001..ECC 2 to be performed
6764 * 0b00010..ECC 4 to be performed
6765 * 0b11110..ECC 60 to be performed
6766 * 0b11111..ECC 62 to be performed
6767 */
6768#define BCH_FLASH3LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_SET_ECCN_MASK)
6769#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U)
6770#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT (16U)
6771#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK)
6772/*! @} */
6773
6774/*! @name FLASH3LAYOUT1_CLR - Hardware BCH ECC Flash 3 Layout 1 Register */
6775/*! @{ */
6776#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU)
6777#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U)
6778#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK)
6779#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U)
6780#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U)
6781#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_MASK)
6782#define BCH_FLASH3LAYOUT1_CLR_ECCN_MASK (0xF800U)
6783#define BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT (11U)
6784/*! ECCN
6785 * 0b00000..No ECC to be performed
6786 * 0b00001..ECC 2 to be performed
6787 * 0b00010..ECC 4 to be performed
6788 * 0b11110..ECC 60 to be performed
6789 * 0b11111..ECC 62 to be performed
6790 */
6791#define BCH_FLASH3LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_ECCN_MASK)
6792#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U)
6793#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U)
6794#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK)
6795/*! @} */
6796
6797/*! @name FLASH3LAYOUT1_TOG - Hardware BCH ECC Flash 3 Layout 1 Register */
6798/*! @{ */
6799#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU)
6800#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U)
6801#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK)
6802#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U)
6803#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U)
6804#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_MASK)
6805#define BCH_FLASH3LAYOUT1_TOG_ECCN_MASK (0xF800U)
6806#define BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT (11U)
6807/*! ECCN
6808 * 0b00000..No ECC to be performed
6809 * 0b00001..ECC 2 to be performed
6810 * 0b00010..ECC 4 to be performed
6811 * 0b11110..ECC 60 to be performed
6812 * 0b11111..ECC 62 to be performed
6813 */
6814#define BCH_FLASH3LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_ECCN_MASK)
6815#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U)
6816#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U)
6817#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK)
6818/*! @} */
6819
6820/*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */
6821/*! @{ */
6822#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU)
6823#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U)
6824#define BCH_DEBUG0_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK)
6825#define BCH_DEBUG0_RSVD0_MASK (0xC0U)
6826#define BCH_DEBUG0_RSVD0_SHIFT (6U)
6827#define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK)
6828#define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK (0x100U)
6829#define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT (8U)
6830/*! BM_KES_TEST_BYPASS
6831 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
6832 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
6833 */
6834#define BCH_DEBUG0_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK)
6835#define BCH_DEBUG0_KES_DEBUG_STALL_MASK (0x200U)
6836#define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT (9U)
6837/*! KES_DEBUG_STALL
6838 * 0b0..KES FSM proceeds to next block supplied by bus master.
6839 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
6840 */
6841#define BCH_DEBUG0_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK)
6842#define BCH_DEBUG0_KES_DEBUG_STEP_MASK (0x400U)
6843#define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT (10U)
6844#define BCH_DEBUG0_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK)
6845#define BCH_DEBUG0_KES_STANDALONE_MASK (0x800U)
6846#define BCH_DEBUG0_KES_STANDALONE_SHIFT (11U)
6847/*! KES_STANDALONE
6848 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
6849 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
6850 */
6851#define BCH_DEBUG0_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK)
6852#define BCH_DEBUG0_KES_DEBUG_KICK_MASK (0x1000U)
6853#define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT (12U)
6854#define BCH_DEBUG0_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK)
6855#define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK (0x2000U)
6856#define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT (13U)
6857/*! KES_DEBUG_MODE4K
6858 * 0b1..Mode is set for 4K NAND pages.
6859 * 0b1..Mode is set for 2K NAND pages.
6860 */
6861#define BCH_DEBUG0_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK)
6862#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
6863#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
6864/*! KES_DEBUG_PAYLOAD_FLAG
6865 * 0b1..Payload is set for 512 bytes data block.
6866 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
6867 */
6868#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK)
6869#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
6870#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
6871#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK)
6872#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
6873#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
6874/*! KES_DEBUG_SYNDROME_SYMBOL
6875 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
6876 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
6877 */
6878#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK)
6879#define BCH_DEBUG0_RSVD1_MASK (0xFE000000U)
6880#define BCH_DEBUG0_RSVD1_SHIFT (25U)
6881#define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK)
6882/*! @} */
6883
6884/*! @name DEBUG0_SET - Hardware BCH ECC Debug Register0 */
6885/*! @{ */
6886#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK (0x3FU)
6887#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT (0U)
6888#define BCH_DEBUG0_SET_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK)
6889#define BCH_DEBUG0_SET_RSVD0_MASK (0xC0U)
6890#define BCH_DEBUG0_SET_RSVD0_SHIFT (6U)
6891#define BCH_DEBUG0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD0_SHIFT)) & BCH_DEBUG0_SET_RSVD0_MASK)
6892#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK (0x100U)
6893#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT (8U)
6894/*! BM_KES_TEST_BYPASS
6895 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
6896 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
6897 */
6898#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK)
6899#define BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK (0x200U)
6900#define BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT (9U)
6901/*! KES_DEBUG_STALL
6902 * 0b0..KES FSM proceeds to next block supplied by bus master.
6903 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
6904 */
6905#define BCH_DEBUG0_SET_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK)
6906#define BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK (0x400U)
6907#define BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT (10U)
6908#define BCH_DEBUG0_SET_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK)
6909#define BCH_DEBUG0_SET_KES_STANDALONE_MASK (0x800U)
6910#define BCH_DEBUG0_SET_KES_STANDALONE_SHIFT (11U)
6911/*! KES_STANDALONE
6912 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
6913 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
6914 */
6915#define BCH_DEBUG0_SET_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_SET_KES_STANDALONE_MASK)
6916#define BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK (0x1000U)
6917#define BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT (12U)
6918#define BCH_DEBUG0_SET_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK)
6919#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK (0x2000U)
6920#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT (13U)
6921/*! KES_DEBUG_MODE4K
6922 * 0b1..Mode is set for 4K NAND pages.
6923 * 0b1..Mode is set for 2K NAND pages.
6924 */
6925#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK)
6926#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
6927#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
6928/*! KES_DEBUG_PAYLOAD_FLAG
6929 * 0b1..Payload is set for 512 bytes data block.
6930 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
6931 */
6932#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK)
6933#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
6934#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
6935#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK)
6936#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
6937#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
6938/*! KES_DEBUG_SYNDROME_SYMBOL
6939 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
6940 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
6941 */
6942#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK)
6943#define BCH_DEBUG0_SET_RSVD1_MASK (0xFE000000U)
6944#define BCH_DEBUG0_SET_RSVD1_SHIFT (25U)
6945#define BCH_DEBUG0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD1_SHIFT)) & BCH_DEBUG0_SET_RSVD1_MASK)
6946/*! @} */
6947
6948/*! @name DEBUG0_CLR - Hardware BCH ECC Debug Register0 */
6949/*! @{ */
6950#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK (0x3FU)
6951#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT (0U)
6952#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK)
6953#define BCH_DEBUG0_CLR_RSVD0_MASK (0xC0U)
6954#define BCH_DEBUG0_CLR_RSVD0_SHIFT (6U)
6955#define BCH_DEBUG0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD0_SHIFT)) & BCH_DEBUG0_CLR_RSVD0_MASK)
6956#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK (0x100U)
6957#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT (8U)
6958/*! BM_KES_TEST_BYPASS
6959 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
6960 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
6961 */
6962#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK)
6963#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK (0x200U)
6964#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT (9U)
6965/*! KES_DEBUG_STALL
6966 * 0b0..KES FSM proceeds to next block supplied by bus master.
6967 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
6968 */
6969#define BCH_DEBUG0_CLR_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK)
6970#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK (0x400U)
6971#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT (10U)
6972#define BCH_DEBUG0_CLR_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK)
6973#define BCH_DEBUG0_CLR_KES_STANDALONE_MASK (0x800U)
6974#define BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT (11U)
6975/*! KES_STANDALONE
6976 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
6977 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
6978 */
6979#define BCH_DEBUG0_CLR_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_CLR_KES_STANDALONE_MASK)
6980#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK (0x1000U)
6981#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT (12U)
6982#define BCH_DEBUG0_CLR_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK)
6983#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK (0x2000U)
6984#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT (13U)
6985/*! KES_DEBUG_MODE4K
6986 * 0b1..Mode is set for 4K NAND pages.
6987 * 0b1..Mode is set for 2K NAND pages.
6988 */
6989#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK)
6990#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
6991#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
6992/*! KES_DEBUG_PAYLOAD_FLAG
6993 * 0b1..Payload is set for 512 bytes data block.
6994 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
6995 */
6996#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK)
6997#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
6998#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
6999#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK)
7000#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
7001#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
7002/*! KES_DEBUG_SYNDROME_SYMBOL
7003 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
7004 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
7005 */
7006#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK)
7007#define BCH_DEBUG0_CLR_RSVD1_MASK (0xFE000000U)
7008#define BCH_DEBUG0_CLR_RSVD1_SHIFT (25U)
7009#define BCH_DEBUG0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD1_SHIFT)) & BCH_DEBUG0_CLR_RSVD1_MASK)
7010/*! @} */
7011
7012/*! @name DEBUG0_TOG - Hardware BCH ECC Debug Register0 */
7013/*! @{ */
7014#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK (0x3FU)
7015#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT (0U)
7016#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK)
7017#define BCH_DEBUG0_TOG_RSVD0_MASK (0xC0U)
7018#define BCH_DEBUG0_TOG_RSVD0_SHIFT (6U)
7019#define BCH_DEBUG0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD0_SHIFT)) & BCH_DEBUG0_TOG_RSVD0_MASK)
7020#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK (0x100U)
7021#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT (8U)
7022/*! BM_KES_TEST_BYPASS
7023 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
7024 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
7025 */
7026#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK)
7027#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK (0x200U)
7028#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT (9U)
7029/*! KES_DEBUG_STALL
7030 * 0b0..KES FSM proceeds to next block supplied by bus master.
7031 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
7032 */
7033#define BCH_DEBUG0_TOG_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK)
7034#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK (0x400U)
7035#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT (10U)
7036#define BCH_DEBUG0_TOG_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK)
7037#define BCH_DEBUG0_TOG_KES_STANDALONE_MASK (0x800U)
7038#define BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT (11U)
7039/*! KES_STANDALONE
7040 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
7041 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
7042 */
7043#define BCH_DEBUG0_TOG_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_TOG_KES_STANDALONE_MASK)
7044#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK (0x1000U)
7045#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT (12U)
7046#define BCH_DEBUG0_TOG_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK)
7047#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK (0x2000U)
7048#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT (13U)
7049/*! KES_DEBUG_MODE4K
7050 * 0b1..Mode is set for 4K NAND pages.
7051 * 0b1..Mode is set for 2K NAND pages.
7052 */
7053#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK)
7054#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
7055#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
7056/*! KES_DEBUG_PAYLOAD_FLAG
7057 * 0b1..Payload is set for 512 bytes data block.
7058 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
7059 */
7060#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK)
7061#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
7062#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
7063#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK)
7064#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
7065#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
7066/*! KES_DEBUG_SYNDROME_SYMBOL
7067 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
7068 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
7069 */
7070#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK)
7071#define BCH_DEBUG0_TOG_RSVD1_MASK (0xFE000000U)
7072#define BCH_DEBUG0_TOG_RSVD1_SHIFT (25U)
7073#define BCH_DEBUG0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD1_SHIFT)) & BCH_DEBUG0_TOG_RSVD1_MASK)
7074/*! @} */
7075
7076/*! @name DBGKESREAD - KES Debug Read Register */
7077/*! @{ */
7078#define BCH_DBGKESREAD_VALUES_MASK (0xFFFFFFFFU)
7079#define BCH_DBGKESREAD_VALUES_SHIFT (0U)
7080#define BCH_DBGKESREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK)
7081/*! @} */
7082
7083/*! @name DBGKESREAD_SET - KES Debug Read Register */
7084/*! @{ */
7085#define BCH_DBGKESREAD_SET_VALUES_MASK (0xFFFFFFFFU)
7086#define BCH_DBGKESREAD_SET_VALUES_SHIFT (0U)
7087#define BCH_DBGKESREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_SET_VALUES_SHIFT)) & BCH_DBGKESREAD_SET_VALUES_MASK)
7088/*! @} */
7089
7090/*! @name DBGKESREAD_CLR - KES Debug Read Register */
7091/*! @{ */
7092#define BCH_DBGKESREAD_CLR_VALUES_MASK (0xFFFFFFFFU)
7093#define BCH_DBGKESREAD_CLR_VALUES_SHIFT (0U)
7094#define BCH_DBGKESREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_CLR_VALUES_SHIFT)) & BCH_DBGKESREAD_CLR_VALUES_MASK)
7095/*! @} */
7096
7097/*! @name DBGKESREAD_TOG - KES Debug Read Register */
7098/*! @{ */
7099#define BCH_DBGKESREAD_TOG_VALUES_MASK (0xFFFFFFFFU)
7100#define BCH_DBGKESREAD_TOG_VALUES_SHIFT (0U)
7101#define BCH_DBGKESREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_TOG_VALUES_SHIFT)) & BCH_DBGKESREAD_TOG_VALUES_MASK)
7102/*! @} */
7103
7104/*! @name DBGCSFEREAD - Chien Search Debug Read Register */
7105/*! @{ */
7106#define BCH_DBGCSFEREAD_VALUES_MASK (0xFFFFFFFFU)
7107#define BCH_DBGCSFEREAD_VALUES_SHIFT (0U)
7108#define BCH_DBGCSFEREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK)
7109/*! @} */
7110
7111/*! @name DBGCSFEREAD_SET - Chien Search Debug Read Register */
7112/*! @{ */
7113#define BCH_DBGCSFEREAD_SET_VALUES_MASK (0xFFFFFFFFU)
7114#define BCH_DBGCSFEREAD_SET_VALUES_SHIFT (0U)
7115#define BCH_DBGCSFEREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_SET_VALUES_SHIFT)) & BCH_DBGCSFEREAD_SET_VALUES_MASK)
7116/*! @} */
7117
7118/*! @name DBGCSFEREAD_CLR - Chien Search Debug Read Register */
7119/*! @{ */
7120#define BCH_DBGCSFEREAD_CLR_VALUES_MASK (0xFFFFFFFFU)
7121#define BCH_DBGCSFEREAD_CLR_VALUES_SHIFT (0U)
7122#define BCH_DBGCSFEREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_CLR_VALUES_SHIFT)) & BCH_DBGCSFEREAD_CLR_VALUES_MASK)
7123/*! @} */
7124
7125/*! @name DBGCSFEREAD_TOG - Chien Search Debug Read Register */
7126/*! @{ */
7127#define BCH_DBGCSFEREAD_TOG_VALUES_MASK (0xFFFFFFFFU)
7128#define BCH_DBGCSFEREAD_TOG_VALUES_SHIFT (0U)
7129#define BCH_DBGCSFEREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_TOG_VALUES_SHIFT)) & BCH_DBGCSFEREAD_TOG_VALUES_MASK)
7130/*! @} */
7131
7132/*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */
7133/*! @{ */
7134#define BCH_DBGSYNDGENREAD_VALUES_MASK (0xFFFFFFFFU)
7135#define BCH_DBGSYNDGENREAD_VALUES_SHIFT (0U)
7136#define BCH_DBGSYNDGENREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK)
7137/*! @} */
7138
7139/*! @name DBGSYNDGENREAD_SET - Syndrome Generator Debug Read Register */
7140/*! @{ */
7141#define BCH_DBGSYNDGENREAD_SET_VALUES_MASK (0xFFFFFFFFU)
7142#define BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT (0U)
7143#define BCH_DBGSYNDGENREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_SET_VALUES_MASK)
7144/*! @} */
7145
7146/*! @name DBGSYNDGENREAD_CLR - Syndrome Generator Debug Read Register */
7147/*! @{ */
7148#define BCH_DBGSYNDGENREAD_CLR_VALUES_MASK (0xFFFFFFFFU)
7149#define BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT (0U)
7150#define BCH_DBGSYNDGENREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_CLR_VALUES_MASK)
7151/*! @} */
7152
7153/*! @name DBGSYNDGENREAD_TOG - Syndrome Generator Debug Read Register */
7154/*! @{ */
7155#define BCH_DBGSYNDGENREAD_TOG_VALUES_MASK (0xFFFFFFFFU)
7156#define BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT (0U)
7157#define BCH_DBGSYNDGENREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_TOG_VALUES_MASK)
7158/*! @} */
7159
7160/*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */
7161/*! @{ */
7162#define BCH_DBGAHBMREAD_VALUES_MASK (0xFFFFFFFFU)
7163#define BCH_DBGAHBMREAD_VALUES_SHIFT (0U)
7164#define BCH_DBGAHBMREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK)
7165/*! @} */
7166
7167/*! @name DBGAHBMREAD_SET - Bus Master and ECC Controller Debug Read Register */
7168/*! @{ */
7169#define BCH_DBGAHBMREAD_SET_VALUES_MASK (0xFFFFFFFFU)
7170#define BCH_DBGAHBMREAD_SET_VALUES_SHIFT (0U)
7171#define BCH_DBGAHBMREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_SET_VALUES_SHIFT)) & BCH_DBGAHBMREAD_SET_VALUES_MASK)
7172/*! @} */
7173
7174/*! @name DBGAHBMREAD_CLR - Bus Master and ECC Controller Debug Read Register */
7175/*! @{ */
7176#define BCH_DBGAHBMREAD_CLR_VALUES_MASK (0xFFFFFFFFU)
7177#define BCH_DBGAHBMREAD_CLR_VALUES_SHIFT (0U)
7178#define BCH_DBGAHBMREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_CLR_VALUES_SHIFT)) & BCH_DBGAHBMREAD_CLR_VALUES_MASK)
7179/*! @} */
7180
7181/*! @name DBGAHBMREAD_TOG - Bus Master and ECC Controller Debug Read Register */
7182/*! @{ */
7183#define BCH_DBGAHBMREAD_TOG_VALUES_MASK (0xFFFFFFFFU)
7184#define BCH_DBGAHBMREAD_TOG_VALUES_SHIFT (0U)
7185#define BCH_DBGAHBMREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_TOG_VALUES_SHIFT)) & BCH_DBGAHBMREAD_TOG_VALUES_MASK)
7186/*! @} */
7187
7188/*! @name BLOCKNAME - Block Name Register */
7189/*! @{ */
7190#define BCH_BLOCKNAME_NAME_MASK (0xFFFFFFFFU)
7191#define BCH_BLOCKNAME_NAME_SHIFT (0U)
7192#define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK)
7193/*! @} */
7194
7195/*! @name BLOCKNAME_SET - Block Name Register */
7196/*! @{ */
7197#define BCH_BLOCKNAME_SET_NAME_MASK (0xFFFFFFFFU)
7198#define BCH_BLOCKNAME_SET_NAME_SHIFT (0U)
7199#define BCH_BLOCKNAME_SET_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_SET_NAME_SHIFT)) & BCH_BLOCKNAME_SET_NAME_MASK)
7200/*! @} */
7201
7202/*! @name BLOCKNAME_CLR - Block Name Register */
7203/*! @{ */
7204#define BCH_BLOCKNAME_CLR_NAME_MASK (0xFFFFFFFFU)
7205#define BCH_BLOCKNAME_CLR_NAME_SHIFT (0U)
7206#define BCH_BLOCKNAME_CLR_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_CLR_NAME_SHIFT)) & BCH_BLOCKNAME_CLR_NAME_MASK)
7207/*! @} */
7208
7209/*! @name BLOCKNAME_TOG - Block Name Register */
7210/*! @{ */
7211#define BCH_BLOCKNAME_TOG_NAME_MASK (0xFFFFFFFFU)
7212#define BCH_BLOCKNAME_TOG_NAME_SHIFT (0U)
7213#define BCH_BLOCKNAME_TOG_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_TOG_NAME_SHIFT)) & BCH_BLOCKNAME_TOG_NAME_MASK)
7214/*! @} */
7215
7216/*! @name VERSION - BCH Version Register */
7217/*! @{ */
7218#define BCH_VERSION_STEP_MASK (0xFFFFU)
7219#define BCH_VERSION_STEP_SHIFT (0U)
7220#define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK)
7221#define BCH_VERSION_MINOR_MASK (0xFF0000U)
7222#define BCH_VERSION_MINOR_SHIFT (16U)
7223#define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK)
7224#define BCH_VERSION_MAJOR_MASK (0xFF000000U)
7225#define BCH_VERSION_MAJOR_SHIFT (24U)
7226#define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK)
7227/*! @} */
7228
7229/*! @name VERSION_SET - BCH Version Register */
7230/*! @{ */
7231#define BCH_VERSION_SET_STEP_MASK (0xFFFFU)
7232#define BCH_VERSION_SET_STEP_SHIFT (0U)
7233#define BCH_VERSION_SET_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_STEP_SHIFT)) & BCH_VERSION_SET_STEP_MASK)
7234#define BCH_VERSION_SET_MINOR_MASK (0xFF0000U)
7235#define BCH_VERSION_SET_MINOR_SHIFT (16U)
7236#define BCH_VERSION_SET_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_MINOR_SHIFT)) & BCH_VERSION_SET_MINOR_MASK)
7237#define BCH_VERSION_SET_MAJOR_MASK (0xFF000000U)
7238#define BCH_VERSION_SET_MAJOR_SHIFT (24U)
7239#define BCH_VERSION_SET_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_MAJOR_SHIFT)) & BCH_VERSION_SET_MAJOR_MASK)
7240/*! @} */
7241
7242/*! @name VERSION_CLR - BCH Version Register */
7243/*! @{ */
7244#define BCH_VERSION_CLR_STEP_MASK (0xFFFFU)
7245#define BCH_VERSION_CLR_STEP_SHIFT (0U)
7246#define BCH_VERSION_CLR_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_STEP_SHIFT)) & BCH_VERSION_CLR_STEP_MASK)
7247#define BCH_VERSION_CLR_MINOR_MASK (0xFF0000U)
7248#define BCH_VERSION_CLR_MINOR_SHIFT (16U)
7249#define BCH_VERSION_CLR_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_MINOR_SHIFT)) & BCH_VERSION_CLR_MINOR_MASK)
7250#define BCH_VERSION_CLR_MAJOR_MASK (0xFF000000U)
7251#define BCH_VERSION_CLR_MAJOR_SHIFT (24U)
7252#define BCH_VERSION_CLR_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_MAJOR_SHIFT)) & BCH_VERSION_CLR_MAJOR_MASK)
7253/*! @} */
7254
7255/*! @name VERSION_TOG - BCH Version Register */
7256/*! @{ */
7257#define BCH_VERSION_TOG_STEP_MASK (0xFFFFU)
7258#define BCH_VERSION_TOG_STEP_SHIFT (0U)
7259#define BCH_VERSION_TOG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_STEP_SHIFT)) & BCH_VERSION_TOG_STEP_MASK)
7260#define BCH_VERSION_TOG_MINOR_MASK (0xFF0000U)
7261#define BCH_VERSION_TOG_MINOR_SHIFT (16U)
7262#define BCH_VERSION_TOG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_MINOR_SHIFT)) & BCH_VERSION_TOG_MINOR_MASK)
7263#define BCH_VERSION_TOG_MAJOR_MASK (0xFF000000U)
7264#define BCH_VERSION_TOG_MAJOR_SHIFT (24U)
7265#define BCH_VERSION_TOG_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_MAJOR_SHIFT)) & BCH_VERSION_TOG_MAJOR_MASK)
7266/*! @} */
7267
7268/*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */
7269/*! @{ */
7270#define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK (0x1FFU)
7271#define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT (0U)
7272#define BCH_DEBUG1_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK)
7273#define BCH_DEBUG1_RSVD_MASK (0x7FFFFE00U)
7274#define BCH_DEBUG1_RSVD_SHIFT (9U)
7275#define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK)
7276#define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK (0x80000000U)
7277#define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT (31U)
7278/*! DEBUG1_PREERASECHK
7279 * 0b0..Turn off pre-erase check
7280 * 0b1..Turn on pre-erase check
7281 */
7282#define BCH_DEBUG1_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK)
7283/*! @} */
7284
7285/*! @name DEBUG1_SET - Hardware BCH ECC Debug Register 1 */
7286/*! @{ */
7287#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK (0x1FFU)
7288#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT (0U)
7289#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK)
7290#define BCH_DEBUG1_SET_RSVD_MASK (0x7FFFFE00U)
7291#define BCH_DEBUG1_SET_RSVD_SHIFT (9U)
7292#define BCH_DEBUG1_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_RSVD_SHIFT)) & BCH_DEBUG1_SET_RSVD_MASK)
7293#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_MASK (0x80000000U)
7294#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_SHIFT (31U)
7295/*! DEBUG1_PREERASECHK
7296 * 0b0..Turn off pre-erase check
7297 * 0b1..Turn on pre-erase check
7298 */
7299#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_SET_DEBUG1_PREERASECHK_MASK)
7300/*! @} */
7301
7302/*! @name DEBUG1_CLR - Hardware BCH ECC Debug Register 1 */
7303/*! @{ */
7304#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK (0x1FFU)
7305#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT (0U)
7306#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK)
7307#define BCH_DEBUG1_CLR_RSVD_MASK (0x7FFFFE00U)
7308#define BCH_DEBUG1_CLR_RSVD_SHIFT (9U)
7309#define BCH_DEBUG1_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_RSVD_SHIFT)) & BCH_DEBUG1_CLR_RSVD_MASK)
7310#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_MASK (0x80000000U)
7311#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_SHIFT (31U)
7312/*! DEBUG1_PREERASECHK
7313 * 0b0..Turn off pre-erase check
7314 * 0b1..Turn on pre-erase check
7315 */
7316#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_MASK)
7317/*! @} */
7318
7319/*! @name DEBUG1_TOG - Hardware BCH ECC Debug Register 1 */
7320/*! @{ */
7321#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK (0x1FFU)
7322#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT (0U)
7323#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK)
7324#define BCH_DEBUG1_TOG_RSVD_MASK (0x7FFFFE00U)
7325#define BCH_DEBUG1_TOG_RSVD_SHIFT (9U)
7326#define BCH_DEBUG1_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_RSVD_SHIFT)) & BCH_DEBUG1_TOG_RSVD_MASK)
7327#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_MASK (0x80000000U)
7328#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_SHIFT (31U)
7329/*! DEBUG1_PREERASECHK
7330 * 0b0..Turn off pre-erase check
7331 * 0b1..Turn on pre-erase check
7332 */
7333#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_MASK)
7334/*! @} */
7335
7336
7337/*!
7338 * @}
7339 */ /* end of group BCH_Register_Masks */
7340
7341
7342/* BCH - Peripheral instance base addresses */
7343/** Peripheral BCH base address */
7344#define BCH_BASE (0x33004000u)
7345/** Peripheral BCH base pointer */
7346#define BCH ((BCH_Type *)BCH_BASE)
7347/** Array initializer of BCH peripheral base addresses */
7348#define BCH_BASE_ADDRS { BCH_BASE }
7349/** Array initializer of BCH peripheral base pointers */
7350#define BCH_BASE_PTRS { BCH }
7351/** Interrupt vectors for the BCH peripheral type */
7352#define BCH_IRQS { BCH_IRQn }
7353
7354/*!
7355 * @}
7356 */ /* end of group BCH_Peripheral_Access_Layer */
7357
7358
7359/* ----------------------------------------------------------------------------
7360 -- BLK_CTL Peripheral Access Layer
7361 ---------------------------------------------------------------------------- */
7362
7363/*!
7364 * @addtogroup BLK_CTL_Peripheral_Access_Layer BLK_CTL Peripheral Access Layer
7365 * @{
7366 */
7367
7368/** BLK_CTL - Register Layout Typedef */
7369typedef struct {
7370 struct { /* offset: 0x0 */
7371 __IO uint32_t RW; /**< Reset Control, offset: 0x0 */
7372 __IO uint32_t SET; /**< Reset Control, offset: 0x4 */
7373 __IO uint32_t CLR; /**< Reset Control, offset: 0x8 */
7374 __IO uint32_t TOG; /**< Reset Control, offset: 0xC */
7375 } RESET_CTRL;
7376 struct { /* offset: 0x10 */
7377 __IO uint32_t RW; /**< Control, offset: 0x10 */
7378 __IO uint32_t SET; /**< Control, offset: 0x14 */
7379 __IO uint32_t CLR; /**< Control, offset: 0x18 */
7380 __IO uint32_t TOG; /**< Control, offset: 0x1C */
7381 } CONTROL0;
7382 struct { /* offset: 0x20 */
7383 __IO uint32_t RW; /**< Spare Control0, offset: 0x20 */
7384 __IO uint32_t SET; /**< Spare Control0, offset: 0x24 */
7385 __IO uint32_t CLR; /**< Spare Control0, offset: 0x28 */
7386 __IO uint32_t TOG; /**< Spare Control0, offset: 0x2C */
7387 } SPARE_CTRL0;
7388 struct { /* offset: 0x30 */
7389 __IO uint32_t RW; /**< Spare Control1, offset: 0x30 */
7390 __IO uint32_t SET; /**< Spare Control1, offset: 0x34 */
7391 __IO uint32_t CLR; /**< Spare Control1, offset: 0x38 */
7392 __IO uint32_t TOG; /**< Spare Control1, offset: 0x3C */
7393 } SPARE_CTRL1;
7394 struct { /* offset: 0x40 */
7395 __I uint32_t RW; /**< Spare Status0, offset: 0x40 */
7396 __I uint32_t SET; /**< Spare Status0, offset: 0x44 */
7397 __I uint32_t CLR; /**< Spare Status0, offset: 0x48 */
7398 __I uint32_t TOG; /**< Spare Status0, offset: 0x4C */
7399 } SPARE_STATUS0;
7400} BLK_CTL_Type;
7401
7402/* ----------------------------------------------------------------------------
7403 -- BLK_CTL Register Masks
7404 ---------------------------------------------------------------------------- */
7405
7406/*!
7407 * @addtogroup BLK_CTL_Register_Masks BLK_CTL Register Masks
7408 * @{
7409 */
7410
7411/*! @name RESET_CTRL - Reset Control */
7412/*! @{ */
7413#define BLK_CTL_RESET_CTRL_B_CLK_RESETN_MASK (0x1U)
7414#define BLK_CTL_RESET_CTRL_B_CLK_RESETN_SHIFT (0U)
7415#define BLK_CTL_RESET_CTRL_B_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_RESET_CTRL_B_CLK_RESETN_SHIFT)) & BLK_CTL_RESET_CTRL_B_CLK_RESETN_MASK)
7416#define BLK_CTL_RESET_CTRL_APB_CLK_RESETN_MASK (0x2U)
7417#define BLK_CTL_RESET_CTRL_APB_CLK_RESETN_SHIFT (1U)
7418#define BLK_CTL_RESET_CTRL_APB_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_RESET_CTRL_APB_CLK_RESETN_SHIFT)) & BLK_CTL_RESET_CTRL_APB_CLK_RESETN_MASK)
7419#define BLK_CTL_RESET_CTRL_P_CLK_RESETN_MASK (0x4U)
7420#define BLK_CTL_RESET_CTRL_P_CLK_RESETN_SHIFT (2U)
7421#define BLK_CTL_RESET_CTRL_P_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_RESET_CTRL_P_CLK_RESETN_SHIFT)) & BLK_CTL_RESET_CTRL_P_CLK_RESETN_MASK)
7422#define BLK_CTL_RESET_CTRL_RTR_CLK_RESETN_MASK (0x8U)
7423#define BLK_CTL_RESET_CTRL_RTR_CLK_RESETN_SHIFT (3U)
7424#define BLK_CTL_RESET_CTRL_RTR_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_RESET_CTRL_RTR_CLK_RESETN_SHIFT)) & BLK_CTL_RESET_CTRL_RTR_CLK_RESETN_MASK)
7425#define BLK_CTL_RESET_CTRL_SPARE_CLK_RESETN_MASK (0xFF0000U)
7426#define BLK_CTL_RESET_CTRL_SPARE_CLK_RESETN_SHIFT (16U)
7427#define BLK_CTL_RESET_CTRL_SPARE_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_RESET_CTRL_SPARE_CLK_RESETN_SHIFT)) & BLK_CTL_RESET_CTRL_SPARE_CLK_RESETN_MASK)
7428/*! @} */
7429
7430/*! @name CONTROL0 - Control */
7431/*! @{ */
7432#define BLK_CTL_CONTROL0_DISPMIX_REFCLK_SEL_MASK (0x30U)
7433#define BLK_CTL_CONTROL0_DISPMIX_REFCLK_SEL_SHIFT (4U)
7434#define BLK_CTL_CONTROL0_DISPMIX_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_CONTROL0_DISPMIX_REFCLK_SEL_SHIFT)) & BLK_CTL_CONTROL0_DISPMIX_REFCLK_SEL_MASK)
7435#define BLK_CTL_CONTROL0_DISPMIX_PIXCLK_SEL_MASK (0x100U)
7436#define BLK_CTL_CONTROL0_DISPMIX_PIXCLK_SEL_SHIFT (8U)
7437#define BLK_CTL_CONTROL0_DISPMIX_PIXCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_CONTROL0_DISPMIX_PIXCLK_SEL_SHIFT)) & BLK_CTL_CONTROL0_DISPMIX_PIXCLK_SEL_MASK)
7438/*! @} */
7439
7440/*! @name SPARE_CTRL0 - Spare Control0 */
7441/*! @{ */
7442#define BLK_CTL_SPARE_CTRL0_SPARE_CTRL_MASK (0xFFFFFFFFU)
7443#define BLK_CTL_SPARE_CTRL0_SPARE_CTRL_SHIFT (0U)
7444#define BLK_CTL_SPARE_CTRL0_SPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_SPARE_CTRL0_SPARE_CTRL_SHIFT)) & BLK_CTL_SPARE_CTRL0_SPARE_CTRL_MASK)
7445/*! @} */
7446
7447/*! @name SPARE_CTRL1 - Spare Control1 */
7448/*! @{ */
7449#define BLK_CTL_SPARE_CTRL1_SPARE_CTRL_MASK (0xFFFFFFFFU)
7450#define BLK_CTL_SPARE_CTRL1_SPARE_CTRL_SHIFT (0U)
7451#define BLK_CTL_SPARE_CTRL1_SPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_SPARE_CTRL1_SPARE_CTRL_SHIFT)) & BLK_CTL_SPARE_CTRL1_SPARE_CTRL_MASK)
7452/*! @} */
7453
7454/*! @name SPARE_STATUS0 - Spare Status0 */
7455/*! @{ */
7456#define BLK_CTL_SPARE_STATUS0_SPARE_STATUS_MASK (0xFFFFFFFFU)
7457#define BLK_CTL_SPARE_STATUS0_SPARE_STATUS_SHIFT (0U)
7458#define BLK_CTL_SPARE_STATUS0_SPARE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_SPARE_STATUS0_SPARE_STATUS_SHIFT)) & BLK_CTL_SPARE_STATUS0_SPARE_STATUS_MASK)
7459/*! @} */
7460
7461
7462/*!
7463 * @}
7464 */ /* end of group BLK_CTL_Register_Masks */
7465
7466
7467/* BLK_CTL - Peripheral instance base addresses */
7468/** Peripheral DCSS__BLK_CTL base address */
7469#define DCSS__BLK_CTL_BASE (0x32E2F000u)
7470/** Peripheral DCSS__BLK_CTL base pointer */
7471#define DCSS__BLK_CTL ((BLK_CTL_Type *)DCSS__BLK_CTL_BASE)
7472/** Array initializer of BLK_CTL peripheral base addresses */
7473#define BLK_CTL_BASE_ADDRS { DCSS__BLK_CTL_BASE }
7474/** Array initializer of BLK_CTL peripheral base pointers */
7475#define BLK_CTL_BASE_PTRS { DCSS__BLK_CTL }
7476
7477/*!
7478 * @}
7479 */ /* end of group BLK_CTL_Peripheral_Access_Layer */
7480
7481
7482/* ----------------------------------------------------------------------------
7483 -- CCM Peripheral Access Layer
7484 ---------------------------------------------------------------------------- */
7485
7486/*!
7487 * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
7488 * @{
7489 */
7490
7491/** CCM - Register Layout Typedef */
7492typedef struct {
7493 __IO uint32_t GPR0; /**< General Purpose Register, offset: 0x0 */
7494 __IO uint32_t GPR0_SET; /**< General Purpose Register, offset: 0x4 */
7495 __IO uint32_t GPR0_CLR; /**< General Purpose Register, offset: 0x8 */
7496 __IO uint32_t GPR0_TOG; /**< General Purpose Register, offset: 0xC */
7497 uint8_t RESERVED_0[2032];
7498 struct { /* offset: 0x800, array step: 0x10 */
7499 __IO uint32_t PLL_CTRL; /**< CCM PLL Control Register, array offset: 0x800, array step: 0x10 */
7500 __IO uint32_t PLL_CTRL_SET; /**< CCM PLL Control Register, array offset: 0x804, array step: 0x10 */
7501 __IO uint32_t PLL_CTRL_CLR; /**< CCM PLL Control Register, array offset: 0x808, array step: 0x10 */
7502 __IO uint32_t PLL_CTRL_TOG; /**< CCM PLL Control Register, array offset: 0x80C, array step: 0x10 */
7503 } PLL_CTRL[39];
7504 uint8_t RESERVED_1[13712];
7505 struct { /* offset: 0x4000, array step: 0x10 */
7506 __IO uint32_t CCGR; /**< CCM Clock Gating Register, array offset: 0x4000, array step: 0x10 */
7507 __IO uint32_t CCGR_SET; /**< CCM Clock Gating Register, array offset: 0x4004, array step: 0x10 */
7508 __IO uint32_t CCGR_CLR; /**< CCM Clock Gating Register, array offset: 0x4008, array step: 0x10 */
7509 __IO uint32_t CCGR_TOG; /**< CCM Clock Gating Register, array offset: 0x400C, array step: 0x10 */
7510 } CCGR[191];
7511 uint8_t RESERVED_2[13328];
7512 struct { /* offset: 0x8000, array step: 0x80 */
7513 __IO uint32_t TARGET_ROOT; /**< Target Register, array offset: 0x8000, array step: 0x80 */
7514 __IO uint32_t TARGET_ROOT_SET; /**< Target Register, array offset: 0x8004, array step: 0x80 */
7515 __IO uint32_t TARGET_ROOT_CLR; /**< Target Register, array offset: 0x8008, array step: 0x80 */
7516 __IO uint32_t TARGET_ROOT_TOG; /**< Target Register, array offset: 0x800C, array step: 0x80 */
7517 __IO uint32_t MISC; /**< Miscellaneous Register, array offset: 0x8010, array step: 0x80 */
7518 __IO uint32_t MISC_ROOT_SET; /**< Miscellaneous Register, array offset: 0x8014, array step: 0x80 */
7519 __IO uint32_t MISC_ROOT_CLR; /**< Miscellaneous Register, array offset: 0x8018, array step: 0x80 */
7520 __IO uint32_t MISC_ROOT_TOG; /**< Miscellaneous Register, array offset: 0x801C, array step: 0x80 */
7521 __IO uint32_t POST; /**< Post Divider Register, array offset: 0x8020, array step: 0x80 */
7522 __IO uint32_t POST_ROOT_SET; /**< Post Divider Register, array offset: 0x8024, array step: 0x80 */
7523 __IO uint32_t POST_ROOT_CLR; /**< Post Divider Register, array offset: 0x8028, array step: 0x80 */
7524 __IO uint32_t POST_ROOT_TOG; /**< Post Divider Register, array offset: 0x802C, array step: 0x80 */
7525 __IO uint32_t PRE; /**< Pre Divider Register, array offset: 0x8030, array step: 0x80 */
7526 __IO uint32_t PRE_ROOT_SET; /**< Pre Divider Register, array offset: 0x8034, array step: 0x80 */
7527 __IO uint32_t PRE_ROOT_CLR; /**< Pre Divider Register, array offset: 0x8038, array step: 0x80 */
7528 __IO uint32_t PRE_ROOT_TOG; /**< Pre Divider Register, array offset: 0x803C, array step: 0x80 */
7529 uint8_t RESERVED_0[48];
7530 __IO uint32_t ACCESS_CTRL; /**< Access Control Register, array offset: 0x8070, array step: 0x80 */
7531 __IO uint32_t ACCESS_CTRL_ROOT_SET; /**< Access Control Register, array offset: 0x8074, array step: 0x80 */
7532 __IO uint32_t ACCESS_CTRL_ROOT_CLR; /**< Access Control Register, array offset: 0x8078, array step: 0x80 */
7533 __IO uint32_t ACCESS_CTRL_ROOT_TOG; /**< Access Control Register, array offset: 0x807C, array step: 0x80 */
7534 } ROOT[142];
7535} CCM_Type;
7536
7537/* ----------------------------------------------------------------------------
7538 -- CCM Register Masks
7539 ---------------------------------------------------------------------------- */
7540
7541/*!
7542 * @addtogroup CCM_Register_Masks CCM Register Masks
7543 * @{
7544 */
7545
7546/*! @name GPR0 - General Purpose Register */
7547/*! @{ */
7548#define CCM_GPR0_GP0_MASK (0xFFFFFFFFU)
7549#define CCM_GPR0_GP0_SHIFT (0U)
7550#define CCM_GPR0_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_GP0_SHIFT)) & CCM_GPR0_GP0_MASK)
7551/*! @} */
7552
7553/*! @name GPR0_SET - General Purpose Register */
7554/*! @{ */
7555#define CCM_GPR0_SET_GP0_MASK (0xFFFFFFFFU)
7556#define CCM_GPR0_SET_GP0_SHIFT (0U)
7557#define CCM_GPR0_SET_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_SET_GP0_SHIFT)) & CCM_GPR0_SET_GP0_MASK)
7558/*! @} */
7559
7560/*! @name GPR0_CLR - General Purpose Register */
7561/*! @{ */
7562#define CCM_GPR0_CLR_GP0_MASK (0xFFFFFFFFU)
7563#define CCM_GPR0_CLR_GP0_SHIFT (0U)
7564#define CCM_GPR0_CLR_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_CLR_GP0_SHIFT)) & CCM_GPR0_CLR_GP0_MASK)
7565/*! @} */
7566
7567/*! @name GPR0_TOG - General Purpose Register */
7568/*! @{ */
7569#define CCM_GPR0_TOG_GP0_MASK (0xFFFFFFFFU)
7570#define CCM_GPR0_TOG_GP0_SHIFT (0U)
7571#define CCM_GPR0_TOG_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_TOG_GP0_SHIFT)) & CCM_GPR0_TOG_GP0_MASK)
7572/*! @} */
7573
7574/*! @name PLL_CTRL - CCM PLL Control Register */
7575/*! @{ */
7576#define CCM_PLL_CTRL_SETTING0_MASK (0x3U)
7577#define CCM_PLL_CTRL_SETTING0_SHIFT (0U)
7578/*! SETTING0
7579 * 0b00..Domain clocks not needed
7580 * 0b01..Domain clocks needed when in RUN
7581 * 0b10..Domain clocks needed when in RUN and WAIT
7582 * 0b11..Domain clocks needed all the time
7583 */
7584#define CCM_PLL_CTRL_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING0_SHIFT)) & CCM_PLL_CTRL_SETTING0_MASK)
7585#define CCM_PLL_CTRL_SETTING1_MASK (0x30U)
7586#define CCM_PLL_CTRL_SETTING1_SHIFT (4U)
7587/*! SETTING1
7588 * 0b00..Domain clocks not needed
7589 * 0b01..Domain clocks needed when in RUN
7590 * 0b10..Domain clocks needed when in RUN and WAIT
7591 * 0b11..Domain clocks needed all the time
7592 */
7593#define CCM_PLL_CTRL_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING1_SHIFT)) & CCM_PLL_CTRL_SETTING1_MASK)
7594#define CCM_PLL_CTRL_SETTING2_MASK (0x300U)
7595#define CCM_PLL_CTRL_SETTING2_SHIFT (8U)
7596/*! SETTING2
7597 * 0b00..Domain clocks not needed
7598 * 0b01..Domain clocks needed when in RUN
7599 * 0b10..Domain clocks needed when in RUN and WAIT
7600 * 0b11..Domain clocks needed all the time
7601 */
7602#define CCM_PLL_CTRL_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING2_SHIFT)) & CCM_PLL_CTRL_SETTING2_MASK)
7603#define CCM_PLL_CTRL_SETTING3_MASK (0x3000U)
7604#define CCM_PLL_CTRL_SETTING3_SHIFT (12U)
7605/*! SETTING3
7606 * 0b00..Domain clocks not needed
7607 * 0b01..Domain clocks needed when in RUN
7608 * 0b10..Domain clocks needed when in RUN and WAIT
7609 * 0b11..Domain clocks needed all the time
7610 */
7611#define CCM_PLL_CTRL_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING3_SHIFT)) & CCM_PLL_CTRL_SETTING3_MASK)
7612/*! @} */
7613
7614/* The count of CCM_PLL_CTRL */
7615#define CCM_PLL_CTRL_COUNT (39U)
7616
7617/*! @name PLL_CTRL_SET - CCM PLL Control Register */
7618/*! @{ */
7619#define CCM_PLL_CTRL_SET_SETTING0_MASK (0x3U)
7620#define CCM_PLL_CTRL_SET_SETTING0_SHIFT (0U)
7621/*! SETTING0
7622 * 0b00..Domain clocks not needed
7623 * 0b01..Domain clocks needed when in RUN
7624 * 0b10..Domain clocks needed when in RUN and WAIT
7625 * 0b11..Domain clocks needed all the time
7626 */
7627#define CCM_PLL_CTRL_SET_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING0_SHIFT)) & CCM_PLL_CTRL_SET_SETTING0_MASK)
7628#define CCM_PLL_CTRL_SET_SETTING1_MASK (0x30U)
7629#define CCM_PLL_CTRL_SET_SETTING1_SHIFT (4U)
7630/*! SETTING1
7631 * 0b00..Domain clocks not needed
7632 * 0b01..Domain clocks needed when in RUN
7633 * 0b10..Domain clocks needed when in RUN and WAIT
7634 * 0b11..Domain clocks needed all the time
7635 */
7636#define CCM_PLL_CTRL_SET_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING1_SHIFT)) & CCM_PLL_CTRL_SET_SETTING1_MASK)
7637#define CCM_PLL_CTRL_SET_SETTING2_MASK (0x300U)
7638#define CCM_PLL_CTRL_SET_SETTING2_SHIFT (8U)
7639/*! SETTING2
7640 * 0b00..Domain clocks not needed
7641 * 0b01..Domain clocks needed when in RUN
7642 * 0b10..Domain clocks needed when in RUN and WAIT
7643 * 0b11..Domain clocks needed all the time
7644 */
7645#define CCM_PLL_CTRL_SET_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING2_SHIFT)) & CCM_PLL_CTRL_SET_SETTING2_MASK)
7646#define CCM_PLL_CTRL_SET_SETTING3_MASK (0x3000U)
7647#define CCM_PLL_CTRL_SET_SETTING3_SHIFT (12U)
7648/*! SETTING3
7649 * 0b00..Domain clocks not needed
7650 * 0b01..Domain clocks needed when in RUN
7651 * 0b10..Domain clocks needed when in RUN and WAIT
7652 * 0b11..Domain clocks needed all the time
7653 */
7654#define CCM_PLL_CTRL_SET_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING3_SHIFT)) & CCM_PLL_CTRL_SET_SETTING3_MASK)
7655/*! @} */
7656
7657/* The count of CCM_PLL_CTRL_SET */
7658#define CCM_PLL_CTRL_SET_COUNT (39U)
7659
7660/*! @name PLL_CTRL_CLR - CCM PLL Control Register */
7661/*! @{ */
7662#define CCM_PLL_CTRL_CLR_SETTING0_MASK (0x3U)
7663#define CCM_PLL_CTRL_CLR_SETTING0_SHIFT (0U)
7664/*! SETTING0
7665 * 0b00..Domain clocks not needed
7666 * 0b01..Domain clocks needed when in RUN
7667 * 0b10..Domain clocks needed when in RUN and WAIT
7668 * 0b11..Domain clocks needed all the time
7669 */
7670#define CCM_PLL_CTRL_CLR_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING0_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING0_MASK)
7671#define CCM_PLL_CTRL_CLR_SETTING1_MASK (0x30U)
7672#define CCM_PLL_CTRL_CLR_SETTING1_SHIFT (4U)
7673/*! SETTING1
7674 * 0b00..Domain clocks not needed
7675 * 0b01..Domain clocks needed when in RUN
7676 * 0b10..Domain clocks needed when in RUN and WAIT
7677 * 0b11..Domain clocks needed all the time
7678 */
7679#define CCM_PLL_CTRL_CLR_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING1_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING1_MASK)
7680#define CCM_PLL_CTRL_CLR_SETTING2_MASK (0x300U)
7681#define CCM_PLL_CTRL_CLR_SETTING2_SHIFT (8U)
7682/*! SETTING2
7683 * 0b00..Domain clocks not needed
7684 * 0b01..Domain clocks needed when in RUN
7685 * 0b10..Domain clocks needed when in RUN and WAIT
7686 * 0b11..Domain clocks needed all the time
7687 */
7688#define CCM_PLL_CTRL_CLR_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING2_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING2_MASK)
7689#define CCM_PLL_CTRL_CLR_SETTING3_MASK (0x3000U)
7690#define CCM_PLL_CTRL_CLR_SETTING3_SHIFT (12U)
7691/*! SETTING3
7692 * 0b00..Domain clocks not needed
7693 * 0b01..Domain clocks needed when in RUN
7694 * 0b10..Domain clocks needed when in RUN and WAIT
7695 * 0b11..Domain clocks needed all the time
7696 */
7697#define CCM_PLL_CTRL_CLR_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING3_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING3_MASK)
7698/*! @} */
7699
7700/* The count of CCM_PLL_CTRL_CLR */
7701#define CCM_PLL_CTRL_CLR_COUNT (39U)
7702
7703/*! @name PLL_CTRL_TOG - CCM PLL Control Register */
7704/*! @{ */
7705#define CCM_PLL_CTRL_TOG_SETTING0_MASK (0x3U)
7706#define CCM_PLL_CTRL_TOG_SETTING0_SHIFT (0U)
7707/*! SETTING0
7708 * 0b00..Domain clocks not needed
7709 * 0b01..Domain clocks needed when in RUN
7710 * 0b10..Domain clocks needed when in RUN and WAIT
7711 * 0b11..Domain clocks needed all the time
7712 */
7713#define CCM_PLL_CTRL_TOG_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING0_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING0_MASK)
7714#define CCM_PLL_CTRL_TOG_SETTING1_MASK (0x30U)
7715#define CCM_PLL_CTRL_TOG_SETTING1_SHIFT (4U)
7716/*! SETTING1
7717 * 0b00..Domain clocks not needed
7718 * 0b01..Domain clocks needed when in RUN
7719 * 0b10..Domain clocks needed when in RUN and WAIT
7720 * 0b11..Domain clocks needed all the time
7721 */
7722#define CCM_PLL_CTRL_TOG_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING1_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING1_MASK)
7723#define CCM_PLL_CTRL_TOG_SETTING2_MASK (0x300U)
7724#define CCM_PLL_CTRL_TOG_SETTING2_SHIFT (8U)
7725/*! SETTING2
7726 * 0b00..Domain clocks not needed
7727 * 0b01..Domain clocks needed when in RUN
7728 * 0b10..Domain clocks needed when in RUN and WAIT
7729 * 0b11..Domain clocks needed all the time
7730 */
7731#define CCM_PLL_CTRL_TOG_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING2_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING2_MASK)
7732#define CCM_PLL_CTRL_TOG_SETTING3_MASK (0x3000U)
7733#define CCM_PLL_CTRL_TOG_SETTING3_SHIFT (12U)
7734/*! SETTING3
7735 * 0b00..Domain clocks not needed
7736 * 0b01..Domain clocks needed when in RUN
7737 * 0b10..Domain clocks needed when in RUN and WAIT
7738 * 0b11..Domain clocks needed all the time
7739 */
7740#define CCM_PLL_CTRL_TOG_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING3_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING3_MASK)
7741/*! @} */
7742
7743/* The count of CCM_PLL_CTRL_TOG */
7744#define CCM_PLL_CTRL_TOG_COUNT (39U)
7745
7746/*! @name CCGR - CCM Clock Gating Register */
7747/*! @{ */
7748#define CCM_CCGR_SETTING0_MASK (0x3U)
7749#define CCM_CCGR_SETTING0_SHIFT (0U)
7750/*! SETTING0
7751 * 0b00..Domain clocks not needed
7752 * 0b01..Domain clocks needed when in RUN
7753 * 0b10..Domain clocks needed when in RUN and WAIT
7754 * 0b11..Domain clocks needed all the time
7755 */
7756#define CCM_CCGR_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING0_SHIFT)) & CCM_CCGR_SETTING0_MASK)
7757#define CCM_CCGR_SETTING1_MASK (0x30U)
7758#define CCM_CCGR_SETTING1_SHIFT (4U)
7759/*! SETTING1
7760 * 0b00..Domain clocks not needed
7761 * 0b01..Domain clocks needed when in RUN
7762 * 0b10..Domain clocks needed when in RUN and WAIT
7763 * 0b11..Domain clocks needed all the time
7764 */
7765#define CCM_CCGR_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING1_SHIFT)) & CCM_CCGR_SETTING1_MASK)
7766#define CCM_CCGR_SETTING2_MASK (0x300U)
7767#define CCM_CCGR_SETTING2_SHIFT (8U)
7768/*! SETTING2
7769 * 0b00..Domain clocks not needed
7770 * 0b01..Domain clocks needed when in RUN
7771 * 0b10..Domain clocks needed when in RUN and WAIT
7772 * 0b11..Domain clocks needed all the time
7773 */
7774#define CCM_CCGR_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING2_SHIFT)) & CCM_CCGR_SETTING2_MASK)
7775#define CCM_CCGR_SETTING3_MASK (0x3000U)
7776#define CCM_CCGR_SETTING3_SHIFT (12U)
7777/*! SETTING3
7778 * 0b00..Domain clocks not needed
7779 * 0b01..Domain clocks needed when in RUN
7780 * 0b10..Domain clocks needed when in RUN and WAIT
7781 * 0b11..Domain clocks needed all the time
7782 */
7783#define CCM_CCGR_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING3_SHIFT)) & CCM_CCGR_SETTING3_MASK)
7784/*! @} */
7785
7786/* The count of CCM_CCGR */
7787#define CCM_CCGR_COUNT (191U)
7788
7789/*! @name CCGR_SET - CCM Clock Gating Register */
7790/*! @{ */
7791#define CCM_CCGR_SET_SETTING0_MASK (0x3U)
7792#define CCM_CCGR_SET_SETTING0_SHIFT (0U)
7793/*! SETTING0
7794 * 0b00..Domain clocks not needed
7795 * 0b01..Domain clocks needed when in RUN
7796 * 0b10..Domain clocks needed when in RUN and WAIT
7797 * 0b11..Domain clocks needed all the time
7798 */
7799#define CCM_CCGR_SET_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING0_SHIFT)) & CCM_CCGR_SET_SETTING0_MASK)
7800#define CCM_CCGR_SET_SETTING1_MASK (0x30U)
7801#define CCM_CCGR_SET_SETTING1_SHIFT (4U)
7802/*! SETTING1
7803 * 0b00..Domain clocks not needed
7804 * 0b01..Domain clocks needed when in RUN
7805 * 0b10..Domain clocks needed when in RUN and WAIT
7806 * 0b11..Domain clocks needed all the time
7807 */
7808#define CCM_CCGR_SET_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING1_SHIFT)) & CCM_CCGR_SET_SETTING1_MASK)
7809#define CCM_CCGR_SET_SETTING2_MASK (0x300U)
7810#define CCM_CCGR_SET_SETTING2_SHIFT (8U)
7811/*! SETTING2
7812 * 0b00..Domain clocks not needed
7813 * 0b01..Domain clocks needed when in RUN
7814 * 0b10..Domain clocks needed when in RUN and WAIT
7815 * 0b11..Domain clocks needed all the time
7816 */
7817#define CCM_CCGR_SET_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING2_SHIFT)) & CCM_CCGR_SET_SETTING2_MASK)
7818#define CCM_CCGR_SET_SETTING3_MASK (0x3000U)
7819#define CCM_CCGR_SET_SETTING3_SHIFT (12U)
7820/*! SETTING3
7821 * 0b00..Domain clocks not needed
7822 * 0b01..Domain clocks needed when in RUN
7823 * 0b10..Domain clocks needed when in RUN and WAIT
7824 * 0b11..Domain clocks needed all the time
7825 */
7826#define CCM_CCGR_SET_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING3_SHIFT)) & CCM_CCGR_SET_SETTING3_MASK)
7827/*! @} */
7828
7829/* The count of CCM_CCGR_SET */
7830#define CCM_CCGR_SET_COUNT (191U)
7831
7832/*! @name CCGR_CLR - CCM Clock Gating Register */
7833/*! @{ */
7834#define CCM_CCGR_CLR_SETTING0_MASK (0x3U)
7835#define CCM_CCGR_CLR_SETTING0_SHIFT (0U)
7836/*! SETTING0
7837 * 0b00..Domain clocks not needed
7838 * 0b01..Domain clocks needed when in RUN
7839 * 0b10..Domain clocks needed when in RUN and WAIT
7840 * 0b11..Domain clocks needed all the time
7841 */
7842#define CCM_CCGR_CLR_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING0_SHIFT)) & CCM_CCGR_CLR_SETTING0_MASK)
7843#define CCM_CCGR_CLR_SETTING1_MASK (0x30U)
7844#define CCM_CCGR_CLR_SETTING1_SHIFT (4U)
7845/*! SETTING1
7846 * 0b00..Domain clocks not needed
7847 * 0b01..Domain clocks needed when in RUN
7848 * 0b10..Domain clocks needed when in RUN and WAIT
7849 * 0b11..Domain clocks needed all the time
7850 */
7851#define CCM_CCGR_CLR_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING1_SHIFT)) & CCM_CCGR_CLR_SETTING1_MASK)
7852#define CCM_CCGR_CLR_SETTING2_MASK (0x300U)
7853#define CCM_CCGR_CLR_SETTING2_SHIFT (8U)
7854/*! SETTING2
7855 * 0b00..Domain clocks not needed
7856 * 0b01..Domain clocks needed when in RUN
7857 * 0b10..Domain clocks needed when in RUN and WAIT
7858 * 0b11..Domain clocks needed all the time
7859 */
7860#define CCM_CCGR_CLR_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING2_SHIFT)) & CCM_CCGR_CLR_SETTING2_MASK)
7861#define CCM_CCGR_CLR_SETTING3_MASK (0x3000U)
7862#define CCM_CCGR_CLR_SETTING3_SHIFT (12U)
7863/*! SETTING3
7864 * 0b00..Domain clocks not needed
7865 * 0b01..Domain clocks needed when in RUN
7866 * 0b10..Domain clocks needed when in RUN and WAIT
7867 * 0b11..Domain clocks needed all the time
7868 */
7869#define CCM_CCGR_CLR_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING3_SHIFT)) & CCM_CCGR_CLR_SETTING3_MASK)
7870/*! @} */
7871
7872/* The count of CCM_CCGR_CLR */
7873#define CCM_CCGR_CLR_COUNT (191U)
7874
7875/*! @name CCGR_TOG - CCM Clock Gating Register */
7876/*! @{ */
7877#define CCM_CCGR_TOG_SETTING0_MASK (0x3U)
7878#define CCM_CCGR_TOG_SETTING0_SHIFT (0U)
7879/*! SETTING0
7880 * 0b00..Domain clocks not needed
7881 * 0b01..Domain clocks needed when in RUN
7882 * 0b10..Domain clocks needed when in RUN and WAIT
7883 * 0b11..Domain clocks needed all the time
7884 */
7885#define CCM_CCGR_TOG_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING0_SHIFT)) & CCM_CCGR_TOG_SETTING0_MASK)
7886#define CCM_CCGR_TOG_SETTING1_MASK (0x30U)
7887#define CCM_CCGR_TOG_SETTING1_SHIFT (4U)
7888/*! SETTING1
7889 * 0b00..Domain clocks not needed
7890 * 0b01..Domain clocks needed when in RUN
7891 * 0b10..Domain clocks needed when in RUN and WAIT
7892 * 0b11..Domain clocks needed all the time
7893 */
7894#define CCM_CCGR_TOG_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING1_SHIFT)) & CCM_CCGR_TOG_SETTING1_MASK)
7895#define CCM_CCGR_TOG_SETTING2_MASK (0x300U)
7896#define CCM_CCGR_TOG_SETTING2_SHIFT (8U)
7897/*! SETTING2
7898 * 0b00..Domain clocks not needed
7899 * 0b01..Domain clocks needed when in RUN
7900 * 0b10..Domain clocks needed when in RUN and WAIT
7901 * 0b11..Domain clocks needed all the time
7902 */
7903#define CCM_CCGR_TOG_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING2_SHIFT)) & CCM_CCGR_TOG_SETTING2_MASK)
7904#define CCM_CCGR_TOG_SETTING3_MASK (0x3000U)
7905#define CCM_CCGR_TOG_SETTING3_SHIFT (12U)
7906/*! SETTING3
7907 * 0b00..Domain clocks not needed
7908 * 0b01..Domain clocks needed when in RUN
7909 * 0b10..Domain clocks needed when in RUN and WAIT
7910 * 0b11..Domain clocks needed all the time
7911 */
7912#define CCM_CCGR_TOG_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING3_SHIFT)) & CCM_CCGR_TOG_SETTING3_MASK)
7913/*! @} */
7914
7915/* The count of CCM_CCGR_TOG */
7916#define CCM_CCGR_TOG_COUNT (191U)
7917
7918/*! @name TARGET_ROOT - Target Register */
7919/*! @{ */
7920#define CCM_TARGET_ROOT_POST_PODF_MASK (0x3FU)
7921#define CCM_TARGET_ROOT_POST_PODF_SHIFT (0U)
7922/*! POST_PODF
7923 * 0b000000..Divide by 1
7924 * 0b000001..Divide by 2
7925 * 0b000010..Divide by 3
7926 * 0b000011..Divide by 4
7927 * 0b000100..Divide by 5
7928 * 0b000101..Divide by 6
7929 * 0b111111..Divide by 64
7930 */
7931#define CCM_TARGET_ROOT_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_POST_PODF_MASK)
7932#define CCM_TARGET_ROOT_PRE_PODF_MASK (0x70000U)
7933#define CCM_TARGET_ROOT_PRE_PODF_SHIFT (16U)
7934/*! PRE_PODF
7935 * 0b000..Divide by 1
7936 * 0b001..Divide by 2
7937 * 0b010..Divide by 3
7938 * 0b011..Divide by 4
7939 * 0b100..Divide by 5
7940 * 0b101..Divide by 6
7941 * 0b110..Divide by 7
7942 * 0b111..Divide by 8
7943 */
7944#define CCM_TARGET_ROOT_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_PRE_PODF_MASK)
7945#define CCM_TARGET_ROOT_MUX_MASK (0x7000000U)
7946#define CCM_TARGET_ROOT_MUX_SHIFT (24U)
7947#define CCM_TARGET_ROOT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_MUX_SHIFT)) & CCM_TARGET_ROOT_MUX_MASK)
7948#define CCM_TARGET_ROOT_ENABLE_MASK (0x10000000U)
7949#define CCM_TARGET_ROOT_ENABLE_SHIFT (28U)
7950/*! ENABLE
7951 * 0b0..clock root is OFF
7952 * 0b1..clock root is ON
7953 */
7954#define CCM_TARGET_ROOT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_ENABLE_SHIFT)) & CCM_TARGET_ROOT_ENABLE_MASK)
7955/*! @} */
7956
7957/* The count of CCM_TARGET_ROOT */
7958#define CCM_TARGET_ROOT_COUNT (142U)
7959
7960/*! @name TARGET_ROOT_SET - Target Register */
7961/*! @{ */
7962#define CCM_TARGET_ROOT_SET_POST_PODF_MASK (0x3FU)
7963#define CCM_TARGET_ROOT_SET_POST_PODF_SHIFT (0U)
7964/*! POST_PODF
7965 * 0b000000..Divide by 1
7966 * 0b000001..Divide by 2
7967 * 0b000010..Divide by 3
7968 * 0b000011..Divide by 4
7969 * 0b000100..Divide by 5
7970 * 0b000101..Divide by 6
7971 * 0b111111..Divide by 64
7972 */
7973#define CCM_TARGET_ROOT_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_POST_PODF_MASK)
7974#define CCM_TARGET_ROOT_SET_PRE_PODF_MASK (0x70000U)
7975#define CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT (16U)
7976/*! PRE_PODF
7977 * 0b000..Divide by 1
7978 * 0b001..Divide by 2
7979 * 0b010..Divide by 3
7980 * 0b011..Divide by 4
7981 * 0b100..Divide by 5
7982 * 0b101..Divide by 6
7983 * 0b110..Divide by 7
7984 * 0b111..Divide by 8
7985 */
7986#define CCM_TARGET_ROOT_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_PRE_PODF_MASK)
7987#define CCM_TARGET_ROOT_SET_MUX_MASK (0x7000000U)
7988#define CCM_TARGET_ROOT_SET_MUX_SHIFT (24U)
7989#define CCM_TARGET_ROOT_SET_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_MUX_SHIFT)) & CCM_TARGET_ROOT_SET_MUX_MASK)
7990#define CCM_TARGET_ROOT_SET_ENABLE_MASK (0x10000000U)
7991#define CCM_TARGET_ROOT_SET_ENABLE_SHIFT (28U)
7992/*! ENABLE
7993 * 0b0..clock root is OFF
7994 * 0b1..clock root is ON
7995 */
7996#define CCM_TARGET_ROOT_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_ENABLE_SHIFT)) & CCM_TARGET_ROOT_SET_ENABLE_MASK)
7997/*! @} */
7998
7999/* The count of CCM_TARGET_ROOT_SET */
8000#define CCM_TARGET_ROOT_SET_COUNT (142U)
8001
8002/*! @name TARGET_ROOT_CLR - Target Register */
8003/*! @{ */
8004#define CCM_TARGET_ROOT_CLR_POST_PODF_MASK (0x3FU)
8005#define CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT (0U)
8006/*! POST_PODF
8007 * 0b000000..Divide by 1
8008 * 0b000001..Divide by 2
8009 * 0b000010..Divide by 3
8010 * 0b000011..Divide by 4
8011 * 0b000100..Divide by 5
8012 * 0b000101..Divide by 6
8013 * 0b111111..Divide by 64
8014 */
8015#define CCM_TARGET_ROOT_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_POST_PODF_MASK)
8016#define CCM_TARGET_ROOT_CLR_PRE_PODF_MASK (0x70000U)
8017#define CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT (16U)
8018/*! PRE_PODF
8019 * 0b000..Divide by 1
8020 * 0b001..Divide by 2
8021 * 0b010..Divide by 3
8022 * 0b011..Divide by 4
8023 * 0b100..Divide by 5
8024 * 0b101..Divide by 6
8025 * 0b110..Divide by 7
8026 * 0b111..Divide by 8
8027 */
8028#define CCM_TARGET_ROOT_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_PRE_PODF_MASK)
8029#define CCM_TARGET_ROOT_CLR_MUX_MASK (0x7000000U)
8030#define CCM_TARGET_ROOT_CLR_MUX_SHIFT (24U)
8031#define CCM_TARGET_ROOT_CLR_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_MUX_SHIFT)) & CCM_TARGET_ROOT_CLR_MUX_MASK)
8032#define CCM_TARGET_ROOT_CLR_ENABLE_MASK (0x10000000U)
8033#define CCM_TARGET_ROOT_CLR_ENABLE_SHIFT (28U)
8034/*! ENABLE
8035 * 0b0..clock root is OFF
8036 * 0b1..clock root is ON
8037 */
8038#define CCM_TARGET_ROOT_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_ENABLE_SHIFT)) & CCM_TARGET_ROOT_CLR_ENABLE_MASK)
8039/*! @} */
8040
8041/* The count of CCM_TARGET_ROOT_CLR */
8042#define CCM_TARGET_ROOT_CLR_COUNT (142U)
8043
8044/*! @name TARGET_ROOT_TOG - Target Register */
8045/*! @{ */
8046#define CCM_TARGET_ROOT_TOG_POST_PODF_MASK (0x3FU)
8047#define CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT (0U)
8048/*! POST_PODF
8049 * 0b000000..Divide by 1
8050 * 0b000001..Divide by 2
8051 * 0b000010..Divide by 3
8052 * 0b000011..Divide by 4
8053 * 0b000100..Divide by 5
8054 * 0b000101..Divide by 6
8055 * 0b111111..Divide by 64
8056 */
8057#define CCM_TARGET_ROOT_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_POST_PODF_MASK)
8058#define CCM_TARGET_ROOT_TOG_PRE_PODF_MASK (0x70000U)
8059#define CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT (16U)
8060/*! PRE_PODF
8061 * 0b000..Divide by 1
8062 * 0b001..Divide by 2
8063 * 0b010..Divide by 3
8064 * 0b011..Divide by 4
8065 * 0b100..Divide by 5
8066 * 0b101..Divide by 6
8067 * 0b110..Divide by 7
8068 * 0b111..Divide by 8
8069 */
8070#define CCM_TARGET_ROOT_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_PRE_PODF_MASK)
8071#define CCM_TARGET_ROOT_TOG_MUX_MASK (0x7000000U)
8072#define CCM_TARGET_ROOT_TOG_MUX_SHIFT (24U)
8073#define CCM_TARGET_ROOT_TOG_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_MUX_SHIFT)) & CCM_TARGET_ROOT_TOG_MUX_MASK)
8074#define CCM_TARGET_ROOT_TOG_ENABLE_MASK (0x10000000U)
8075#define CCM_TARGET_ROOT_TOG_ENABLE_SHIFT (28U)
8076/*! ENABLE
8077 * 0b0..clock root is OFF
8078 * 0b1..clock root is ON
8079 */
8080#define CCM_TARGET_ROOT_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_ENABLE_SHIFT)) & CCM_TARGET_ROOT_TOG_ENABLE_MASK)
8081/*! @} */
8082
8083/* The count of CCM_TARGET_ROOT_TOG */
8084#define CCM_TARGET_ROOT_TOG_COUNT (142U)
8085
8086/*! @name MISC - Miscellaneous Register */
8087/*! @{ */
8088#define CCM_MISC_AUTHEN_FAIL_MASK (0x1U)
8089#define CCM_MISC_AUTHEN_FAIL_SHIFT (0U)
8090#define CCM_MISC_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_AUTHEN_FAIL_SHIFT)) & CCM_MISC_AUTHEN_FAIL_MASK)
8091#define CCM_MISC_TIMEOUT_MASK (0x10U)
8092#define CCM_MISC_TIMEOUT_SHIFT (4U)
8093#define CCM_MISC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_TIMEOUT_SHIFT)) & CCM_MISC_TIMEOUT_MASK)
8094#define CCM_MISC_VIOLATE_MASK (0x100U)
8095#define CCM_MISC_VIOLATE_SHIFT (8U)
8096#define CCM_MISC_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_VIOLATE_SHIFT)) & CCM_MISC_VIOLATE_MASK)
8097/*! @} */
8098
8099/* The count of CCM_MISC */
8100#define CCM_MISC_COUNT (142U)
8101
8102/*! @name MISC_ROOT_SET - Miscellaneous Register */
8103/*! @{ */
8104#define CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK (0x1U)
8105#define CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT (0U)
8106#define CCM_MISC_ROOT_SET_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK)
8107#define CCM_MISC_ROOT_SET_TIMEOUT_MASK (0x10U)
8108#define CCM_MISC_ROOT_SET_TIMEOUT_SHIFT (4U)
8109#define CCM_MISC_ROOT_SET_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_SET_TIMEOUT_MASK)
8110#define CCM_MISC_ROOT_SET_VIOLATE_MASK (0x100U)
8111#define CCM_MISC_ROOT_SET_VIOLATE_SHIFT (8U)
8112#define CCM_MISC_ROOT_SET_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_VIOLATE_SHIFT)) & CCM_MISC_ROOT_SET_VIOLATE_MASK)
8113/*! @} */
8114
8115/* The count of CCM_MISC_ROOT_SET */
8116#define CCM_MISC_ROOT_SET_COUNT (142U)
8117
8118/*! @name MISC_ROOT_CLR - Miscellaneous Register */
8119/*! @{ */
8120#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK (0x1U)
8121#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT (0U)
8122#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK)
8123#define CCM_MISC_ROOT_CLR_TIMEOUT_MASK (0x10U)
8124#define CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT (4U)
8125#define CCM_MISC_ROOT_CLR_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_CLR_TIMEOUT_MASK)
8126#define CCM_MISC_ROOT_CLR_VIOLATE_MASK (0x100U)
8127#define CCM_MISC_ROOT_CLR_VIOLATE_SHIFT (8U)
8128#define CCM_MISC_ROOT_CLR_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_VIOLATE_SHIFT)) & CCM_MISC_ROOT_CLR_VIOLATE_MASK)
8129/*! @} */
8130
8131/* The count of CCM_MISC_ROOT_CLR */
8132#define CCM_MISC_ROOT_CLR_COUNT (142U)
8133
8134/*! @name MISC_ROOT_TOG - Miscellaneous Register */
8135/*! @{ */
8136#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK (0x1U)
8137#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT (0U)
8138#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK)
8139#define CCM_MISC_ROOT_TOG_TIMEOUT_MASK (0x10U)
8140#define CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT (4U)
8141#define CCM_MISC_ROOT_TOG_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_TOG_TIMEOUT_MASK)
8142#define CCM_MISC_ROOT_TOG_VIOLATE_MASK (0x100U)
8143#define CCM_MISC_ROOT_TOG_VIOLATE_SHIFT (8U)
8144#define CCM_MISC_ROOT_TOG_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_VIOLATE_SHIFT)) & CCM_MISC_ROOT_TOG_VIOLATE_MASK)
8145/*! @} */
8146
8147/* The count of CCM_MISC_ROOT_TOG */
8148#define CCM_MISC_ROOT_TOG_COUNT (142U)
8149
8150/*! @name POST - Post Divider Register */
8151/*! @{ */
8152#define CCM_POST_POST_PODF_MASK (0x3FU)
8153#define CCM_POST_POST_PODF_SHIFT (0U)
8154/*! POST_PODF
8155 * 0b000000..Divide by 1
8156 * 0b000001..Divide by 2
8157 * 0b000010..Divide by 3
8158 * 0b000011..Divide by 4
8159 * 0b000100..Divide by 5
8160 * 0b000101..Divide by 6
8161 * 0b111111..Divide by 64
8162 */
8163#define CCM_POST_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_POST_PODF_SHIFT)) & CCM_POST_POST_PODF_MASK)
8164#define CCM_POST_BUSY1_MASK (0x80U)
8165#define CCM_POST_BUSY1_SHIFT (7U)
8166#define CCM_POST_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY1_SHIFT)) & CCM_POST_BUSY1_MASK)
8167#define CCM_POST_SELECT_MASK (0x10000000U)
8168#define CCM_POST_SELECT_SHIFT (28U)
8169/*! SELECT
8170 * 0b0..select branch A
8171 * 0b1..select branch B
8172 */
8173#define CCM_POST_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_SELECT_SHIFT)) & CCM_POST_SELECT_MASK)
8174#define CCM_POST_BUSY2_MASK (0x80000000U)
8175#define CCM_POST_BUSY2_SHIFT (31U)
8176#define CCM_POST_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY2_SHIFT)) & CCM_POST_BUSY2_MASK)
8177/*! @} */
8178
8179/* The count of CCM_POST */
8180#define CCM_POST_COUNT (142U)
8181
8182/*! @name POST_ROOT_SET - Post Divider Register */
8183/*! @{ */
8184#define CCM_POST_ROOT_SET_POST_PODF_MASK (0x3FU)
8185#define CCM_POST_ROOT_SET_POST_PODF_SHIFT (0U)
8186/*! POST_PODF
8187 * 0b000000..Divide by 1
8188 * 0b000001..Divide by 2
8189 * 0b000010..Divide by 3
8190 * 0b000011..Divide by 4
8191 * 0b000100..Divide by 5
8192 * 0b000101..Divide by 6
8193 * 0b111111..Divide by 64
8194 */
8195#define CCM_POST_ROOT_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_POST_PODF_SHIFT)) & CCM_POST_ROOT_SET_POST_PODF_MASK)
8196#define CCM_POST_ROOT_SET_BUSY1_MASK (0x80U)
8197#define CCM_POST_ROOT_SET_BUSY1_SHIFT (7U)
8198#define CCM_POST_ROOT_SET_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY1_SHIFT)) & CCM_POST_ROOT_SET_BUSY1_MASK)
8199#define CCM_POST_ROOT_SET_SELECT_MASK (0x10000000U)
8200#define CCM_POST_ROOT_SET_SELECT_SHIFT (28U)
8201/*! SELECT
8202 * 0b0..select branch A
8203 * 0b1..select branch B
8204 */
8205#define CCM_POST_ROOT_SET_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_SELECT_SHIFT)) & CCM_POST_ROOT_SET_SELECT_MASK)
8206#define CCM_POST_ROOT_SET_BUSY2_MASK (0x80000000U)
8207#define CCM_POST_ROOT_SET_BUSY2_SHIFT (31U)
8208#define CCM_POST_ROOT_SET_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY2_SHIFT)) & CCM_POST_ROOT_SET_BUSY2_MASK)
8209/*! @} */
8210
8211/* The count of CCM_POST_ROOT_SET */
8212#define CCM_POST_ROOT_SET_COUNT (142U)
8213
8214/*! @name POST_ROOT_CLR - Post Divider Register */
8215/*! @{ */
8216#define CCM_POST_ROOT_CLR_POST_PODF_MASK (0x3FU)
8217#define CCM_POST_ROOT_CLR_POST_PODF_SHIFT (0U)
8218/*! POST_PODF
8219 * 0b000000..Divide by 1
8220 * 0b000001..Divide by 2
8221 * 0b000010..Divide by 3
8222 * 0b000011..Divide by 4
8223 * 0b000100..Divide by 5
8224 * 0b000101..Divide by 6
8225 * 0b111111..Divide by 64
8226 */
8227#define CCM_POST_ROOT_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_POST_PODF_SHIFT)) & CCM_POST_ROOT_CLR_POST_PODF_MASK)
8228#define CCM_POST_ROOT_CLR_BUSY1_MASK (0x80U)
8229#define CCM_POST_ROOT_CLR_BUSY1_SHIFT (7U)
8230#define CCM_POST_ROOT_CLR_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY1_SHIFT)) & CCM_POST_ROOT_CLR_BUSY1_MASK)
8231#define CCM_POST_ROOT_CLR_SELECT_MASK (0x10000000U)
8232#define CCM_POST_ROOT_CLR_SELECT_SHIFT (28U)
8233/*! SELECT
8234 * 0b0..select branch A
8235 * 0b1..select branch B
8236 */
8237#define CCM_POST_ROOT_CLR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_SELECT_SHIFT)) & CCM_POST_ROOT_CLR_SELECT_MASK)
8238#define CCM_POST_ROOT_CLR_BUSY2_MASK (0x80000000U)
8239#define CCM_POST_ROOT_CLR_BUSY2_SHIFT (31U)
8240#define CCM_POST_ROOT_CLR_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY2_SHIFT)) & CCM_POST_ROOT_CLR_BUSY2_MASK)
8241/*! @} */
8242
8243/* The count of CCM_POST_ROOT_CLR */
8244#define CCM_POST_ROOT_CLR_COUNT (142U)
8245
8246/*! @name POST_ROOT_TOG - Post Divider Register */
8247/*! @{ */
8248#define CCM_POST_ROOT_TOG_POST_PODF_MASK (0x3FU)
8249#define CCM_POST_ROOT_TOG_POST_PODF_SHIFT (0U)
8250/*! POST_PODF
8251 * 0b000000..Divide by 1
8252 * 0b000001..Divide by 2
8253 * 0b000010..Divide by 3
8254 * 0b000011..Divide by 4
8255 * 0b000100..Divide by 5
8256 * 0b000101..Divide by 6
8257 * 0b111111..Divide by 64
8258 */
8259#define CCM_POST_ROOT_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_POST_PODF_SHIFT)) & CCM_POST_ROOT_TOG_POST_PODF_MASK)
8260#define CCM_POST_ROOT_TOG_BUSY1_MASK (0x80U)
8261#define CCM_POST_ROOT_TOG_BUSY1_SHIFT (7U)
8262#define CCM_POST_ROOT_TOG_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY1_SHIFT)) & CCM_POST_ROOT_TOG_BUSY1_MASK)
8263#define CCM_POST_ROOT_TOG_SELECT_MASK (0x10000000U)
8264#define CCM_POST_ROOT_TOG_SELECT_SHIFT (28U)
8265/*! SELECT
8266 * 0b0..select branch A
8267 * 0b1..select branch B
8268 */
8269#define CCM_POST_ROOT_TOG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_SELECT_SHIFT)) & CCM_POST_ROOT_TOG_SELECT_MASK)
8270#define CCM_POST_ROOT_TOG_BUSY2_MASK (0x80000000U)
8271#define CCM_POST_ROOT_TOG_BUSY2_SHIFT (31U)
8272#define CCM_POST_ROOT_TOG_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY2_SHIFT)) & CCM_POST_ROOT_TOG_BUSY2_MASK)
8273/*! @} */
8274
8275/* The count of CCM_POST_ROOT_TOG */
8276#define CCM_POST_ROOT_TOG_COUNT (142U)
8277
8278/*! @name PRE - Pre Divider Register */
8279/*! @{ */
8280#define CCM_PRE_PRE_PODF_B_MASK (0x7U)
8281#define CCM_PRE_PRE_PODF_B_SHIFT (0U)
8282/*! PRE_PODF_B
8283 * 0b000..Divide by 1
8284 * 0b001..Divide by 2
8285 * 0b010..Divide by 3
8286 * 0b011..Divide by 4
8287 * 0b100..Divide by 5
8288 * 0b101..Divide by 6
8289 * 0b110..Divide by 7
8290 * 0b111..Divide by 8
8291 */
8292#define CCM_PRE_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_B_SHIFT)) & CCM_PRE_PRE_PODF_B_MASK)
8293#define CCM_PRE_BUSY0_MASK (0x8U)
8294#define CCM_PRE_BUSY0_SHIFT (3U)
8295#define CCM_PRE_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY0_SHIFT)) & CCM_PRE_BUSY0_MASK)
8296#define CCM_PRE_MUX_B_MASK (0x700U)
8297#define CCM_PRE_MUX_B_SHIFT (8U)
8298#define CCM_PRE_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_B_SHIFT)) & CCM_PRE_MUX_B_MASK)
8299#define CCM_PRE_EN_B_MASK (0x1000U)
8300#define CCM_PRE_EN_B_SHIFT (12U)
8301/*! EN_B
8302 * 0b0..Clock shutdown
8303 * 0b1..Clock ON
8304 */
8305#define CCM_PRE_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_B_SHIFT)) & CCM_PRE_EN_B_MASK)
8306#define CCM_PRE_BUSY1_MASK (0x8000U)
8307#define CCM_PRE_BUSY1_SHIFT (15U)
8308#define CCM_PRE_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY1_SHIFT)) & CCM_PRE_BUSY1_MASK)
8309#define CCM_PRE_PRE_PODF_A_MASK (0x70000U)
8310#define CCM_PRE_PRE_PODF_A_SHIFT (16U)
8311/*! PRE_PODF_A
8312 * 0b000..Divide by 1
8313 * 0b001..Divide by 2
8314 * 0b010..Divide by 3
8315 * 0b011..Divide by 4
8316 * 0b100..Divide by 5
8317 * 0b101..Divide by 6
8318 * 0b110..Divide by 7
8319 * 0b111..Divide by 8
8320 */
8321#define CCM_PRE_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_A_SHIFT)) & CCM_PRE_PRE_PODF_A_MASK)
8322#define CCM_PRE_BUSY3_MASK (0x80000U)
8323#define CCM_PRE_BUSY3_SHIFT (19U)
8324#define CCM_PRE_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY3_SHIFT)) & CCM_PRE_BUSY3_MASK)
8325#define CCM_PRE_MUX_A_MASK (0x7000000U)
8326#define CCM_PRE_MUX_A_SHIFT (24U)
8327#define CCM_PRE_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_A_SHIFT)) & CCM_PRE_MUX_A_MASK)
8328#define CCM_PRE_EN_A_MASK (0x10000000U)
8329#define CCM_PRE_EN_A_SHIFT (28U)
8330/*! EN_A
8331 * 0b0..Clock shutdown
8332 * 0b1..clock ON
8333 */
8334#define CCM_PRE_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_A_SHIFT)) & CCM_PRE_EN_A_MASK)
8335#define CCM_PRE_BUSY4_MASK (0x80000000U)
8336#define CCM_PRE_BUSY4_SHIFT (31U)
8337#define CCM_PRE_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY4_SHIFT)) & CCM_PRE_BUSY4_MASK)
8338/*! @} */
8339
8340/* The count of CCM_PRE */
8341#define CCM_PRE_COUNT (142U)
8342
8343/*! @name PRE_ROOT_SET - Pre Divider Register */
8344/*! @{ */
8345#define CCM_PRE_ROOT_SET_PRE_PODF_B_MASK (0x7U)
8346#define CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT (0U)
8347/*! PRE_PODF_B
8348 * 0b000..Divide by 1
8349 * 0b001..Divide by 2
8350 * 0b010..Divide by 3
8351 * 0b011..Divide by 4
8352 * 0b100..Divide by 5
8353 * 0b101..Divide by 6
8354 * 0b110..Divide by 7
8355 * 0b111..Divide by 8
8356 */
8357#define CCM_PRE_ROOT_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_B_MASK)
8358#define CCM_PRE_ROOT_SET_BUSY0_MASK (0x8U)
8359#define CCM_PRE_ROOT_SET_BUSY0_SHIFT (3U)
8360#define CCM_PRE_ROOT_SET_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY0_SHIFT)) & CCM_PRE_ROOT_SET_BUSY0_MASK)
8361#define CCM_PRE_ROOT_SET_MUX_B_MASK (0x700U)
8362#define CCM_PRE_ROOT_SET_MUX_B_SHIFT (8U)
8363#define CCM_PRE_ROOT_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_B_SHIFT)) & CCM_PRE_ROOT_SET_MUX_B_MASK)
8364#define CCM_PRE_ROOT_SET_EN_B_MASK (0x1000U)
8365#define CCM_PRE_ROOT_SET_EN_B_SHIFT (12U)
8366/*! EN_B
8367 * 0b0..Clock shutdown
8368 * 0b1..Clock ON
8369 */
8370#define CCM_PRE_ROOT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_B_SHIFT)) & CCM_PRE_ROOT_SET_EN_B_MASK)
8371#define CCM_PRE_ROOT_SET_BUSY1_MASK (0x8000U)
8372#define CCM_PRE_ROOT_SET_BUSY1_SHIFT (15U)
8373#define CCM_PRE_ROOT_SET_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY1_SHIFT)) & CCM_PRE_ROOT_SET_BUSY1_MASK)
8374#define CCM_PRE_ROOT_SET_PRE_PODF_A_MASK (0x70000U)
8375#define CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT (16U)
8376/*! PRE_PODF_A
8377 * 0b000..Divide by 1
8378 * 0b001..Divide by 2
8379 * 0b010..Divide by 3
8380 * 0b011..Divide by 4
8381 * 0b100..Divide by 5
8382 * 0b101..Divide by 6
8383 * 0b110..Divide by 7
8384 * 0b111..Divide by 8
8385 */
8386#define CCM_PRE_ROOT_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_A_MASK)
8387#define CCM_PRE_ROOT_SET_BUSY3_MASK (0x80000U)
8388#define CCM_PRE_ROOT_SET_BUSY3_SHIFT (19U)
8389#define CCM_PRE_ROOT_SET_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY3_SHIFT)) & CCM_PRE_ROOT_SET_BUSY3_MASK)
8390#define CCM_PRE_ROOT_SET_MUX_A_MASK (0x7000000U)
8391#define CCM_PRE_ROOT_SET_MUX_A_SHIFT (24U)
8392#define CCM_PRE_ROOT_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_A_SHIFT)) & CCM_PRE_ROOT_SET_MUX_A_MASK)
8393#define CCM_PRE_ROOT_SET_EN_A_MASK (0x10000000U)
8394#define CCM_PRE_ROOT_SET_EN_A_SHIFT (28U)
8395/*! EN_A
8396 * 0b0..Clock shutdown
8397 * 0b1..clock ON
8398 */
8399#define CCM_PRE_ROOT_SET_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_A_SHIFT)) & CCM_PRE_ROOT_SET_EN_A_MASK)
8400#define CCM_PRE_ROOT_SET_BUSY4_MASK (0x80000000U)
8401#define CCM_PRE_ROOT_SET_BUSY4_SHIFT (31U)
8402#define CCM_PRE_ROOT_SET_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY4_SHIFT)) & CCM_PRE_ROOT_SET_BUSY4_MASK)
8403/*! @} */
8404
8405/* The count of CCM_PRE_ROOT_SET */
8406#define CCM_PRE_ROOT_SET_COUNT (142U)
8407
8408/*! @name PRE_ROOT_CLR - Pre Divider Register */
8409/*! @{ */
8410#define CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK (0x7U)
8411#define CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT (0U)
8412/*! PRE_PODF_B
8413 * 0b000..Divide by 1
8414 * 0b001..Divide by 2
8415 * 0b010..Divide by 3
8416 * 0b011..Divide by 4
8417 * 0b100..Divide by 5
8418 * 0b101..Divide by 6
8419 * 0b110..Divide by 7
8420 * 0b111..Divide by 8
8421 */
8422#define CCM_PRE_ROOT_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK)
8423#define CCM_PRE_ROOT_CLR_BUSY0_MASK (0x8U)
8424#define CCM_PRE_ROOT_CLR_BUSY0_SHIFT (3U)
8425#define CCM_PRE_ROOT_CLR_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY0_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY0_MASK)
8426#define CCM_PRE_ROOT_CLR_MUX_B_MASK (0x700U)
8427#define CCM_PRE_ROOT_CLR_MUX_B_SHIFT (8U)
8428#define CCM_PRE_ROOT_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_B_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_B_MASK)
8429#define CCM_PRE_ROOT_CLR_EN_B_MASK (0x1000U)
8430#define CCM_PRE_ROOT_CLR_EN_B_SHIFT (12U)
8431/*! EN_B
8432 * 0b0..Clock shutdown
8433 * 0b1..Clock ON
8434 */
8435#define CCM_PRE_ROOT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_B_SHIFT)) & CCM_PRE_ROOT_CLR_EN_B_MASK)
8436#define CCM_PRE_ROOT_CLR_BUSY1_MASK (0x8000U)
8437#define CCM_PRE_ROOT_CLR_BUSY1_SHIFT (15U)
8438#define CCM_PRE_ROOT_CLR_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY1_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY1_MASK)
8439#define CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK (0x70000U)
8440#define CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT (16U)
8441/*! PRE_PODF_A
8442 * 0b000..Divide by 1
8443 * 0b001..Divide by 2
8444 * 0b010..Divide by 3
8445 * 0b011..Divide by 4
8446 * 0b100..Divide by 5
8447 * 0b101..Divide by 6
8448 * 0b110..Divide by 7
8449 * 0b111..Divide by 8
8450 */
8451#define CCM_PRE_ROOT_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK)
8452#define CCM_PRE_ROOT_CLR_BUSY3_MASK (0x80000U)
8453#define CCM_PRE_ROOT_CLR_BUSY3_SHIFT (19U)
8454#define CCM_PRE_ROOT_CLR_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY3_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY3_MASK)
8455#define CCM_PRE_ROOT_CLR_MUX_A_MASK (0x7000000U)
8456#define CCM_PRE_ROOT_CLR_MUX_A_SHIFT (24U)
8457#define CCM_PRE_ROOT_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_A_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_A_MASK)
8458#define CCM_PRE_ROOT_CLR_EN_A_MASK (0x10000000U)
8459#define CCM_PRE_ROOT_CLR_EN_A_SHIFT (28U)
8460/*! EN_A
8461 * 0b0..Clock shutdown
8462 * 0b1..clock ON
8463 */
8464#define CCM_PRE_ROOT_CLR_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_A_SHIFT)) & CCM_PRE_ROOT_CLR_EN_A_MASK)
8465#define CCM_PRE_ROOT_CLR_BUSY4_MASK (0x80000000U)
8466#define CCM_PRE_ROOT_CLR_BUSY4_SHIFT (31U)
8467#define CCM_PRE_ROOT_CLR_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY4_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY4_MASK)
8468/*! @} */
8469
8470/* The count of CCM_PRE_ROOT_CLR */
8471#define CCM_PRE_ROOT_CLR_COUNT (142U)
8472
8473/*! @name PRE_ROOT_TOG - Pre Divider Register */
8474/*! @{ */
8475#define CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK (0x7U)
8476#define CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT (0U)
8477/*! PRE_PODF_B
8478 * 0b000..Divide by 1
8479 * 0b001..Divide by 2
8480 * 0b010..Divide by 3
8481 * 0b011..Divide by 4
8482 * 0b100..Divide by 5
8483 * 0b101..Divide by 6
8484 * 0b110..Divide by 7
8485 * 0b111..Divide by 8
8486 */
8487#define CCM_PRE_ROOT_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK)
8488#define CCM_PRE_ROOT_TOG_BUSY0_MASK (0x8U)
8489#define CCM_PRE_ROOT_TOG_BUSY0_SHIFT (3U)
8490#define CCM_PRE_ROOT_TOG_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY0_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY0_MASK)
8491#define CCM_PRE_ROOT_TOG_MUX_B_MASK (0x700U)
8492#define CCM_PRE_ROOT_TOG_MUX_B_SHIFT (8U)
8493#define CCM_PRE_ROOT_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_B_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_B_MASK)
8494#define CCM_PRE_ROOT_TOG_EN_B_MASK (0x1000U)
8495#define CCM_PRE_ROOT_TOG_EN_B_SHIFT (12U)
8496/*! EN_B
8497 * 0b0..Clock shutdown
8498 * 0b1..Clock ON
8499 */
8500#define CCM_PRE_ROOT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_B_SHIFT)) & CCM_PRE_ROOT_TOG_EN_B_MASK)
8501#define CCM_PRE_ROOT_TOG_BUSY1_MASK (0x8000U)
8502#define CCM_PRE_ROOT_TOG_BUSY1_SHIFT (15U)
8503#define CCM_PRE_ROOT_TOG_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY1_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY1_MASK)
8504#define CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK (0x70000U)
8505#define CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT (16U)
8506/*! PRE_PODF_A
8507 * 0b000..Divide by 1
8508 * 0b001..Divide by 2
8509 * 0b010..Divide by 3
8510 * 0b011..Divide by 4
8511 * 0b100..Divide by 5
8512 * 0b101..Divide by 6
8513 * 0b110..Divide by 7
8514 * 0b111..Divide by 8
8515 */
8516#define CCM_PRE_ROOT_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK)
8517#define CCM_PRE_ROOT_TOG_BUSY3_MASK (0x80000U)
8518#define CCM_PRE_ROOT_TOG_BUSY3_SHIFT (19U)
8519#define CCM_PRE_ROOT_TOG_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY3_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY3_MASK)
8520#define CCM_PRE_ROOT_TOG_MUX_A_MASK (0x7000000U)
8521#define CCM_PRE_ROOT_TOG_MUX_A_SHIFT (24U)
8522#define CCM_PRE_ROOT_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_A_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_A_MASK)
8523#define CCM_PRE_ROOT_TOG_EN_A_MASK (0x10000000U)
8524#define CCM_PRE_ROOT_TOG_EN_A_SHIFT (28U)
8525/*! EN_A
8526 * 0b0..Clock shutdown
8527 * 0b1..clock ON
8528 */
8529#define CCM_PRE_ROOT_TOG_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_A_SHIFT)) & CCM_PRE_ROOT_TOG_EN_A_MASK)
8530#define CCM_PRE_ROOT_TOG_BUSY4_MASK (0x80000000U)
8531#define CCM_PRE_ROOT_TOG_BUSY4_SHIFT (31U)
8532#define CCM_PRE_ROOT_TOG_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY4_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY4_MASK)
8533/*! @} */
8534
8535/* The count of CCM_PRE_ROOT_TOG */
8536#define CCM_PRE_ROOT_TOG_COUNT (142U)
8537
8538/*! @name ACCESS_CTRL - Access Control Register */
8539/*! @{ */
8540#define CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK (0xFU)
8541#define CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT (0U)
8542#define CCM_ACCESS_CTRL_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK)
8543#define CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK (0xF0U)
8544#define CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT (4U)
8545#define CCM_ACCESS_CTRL_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK)
8546#define CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK (0xF00U)
8547#define CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT (8U)
8548#define CCM_ACCESS_CTRL_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK)
8549#define CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK (0xF000U)
8550#define CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT (12U)
8551#define CCM_ACCESS_CTRL_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK)
8552#define CCM_ACCESS_CTRL_OWNER_ID_MASK (0x30000U)
8553#define CCM_ACCESS_CTRL_OWNER_ID_SHIFT (16U)
8554/*! OWNER_ID
8555 * 0b00..domaino
8556 * 0b01..domain1
8557 * 0b10..domain2
8558 * 0b11..domain3
8559 */
8560#define CCM_ACCESS_CTRL_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_OWNER_ID_MASK)
8561#define CCM_ACCESS_CTRL_MUTEX_MASK (0x100000U)
8562#define CCM_ACCESS_CTRL_MUTEX_SHIFT (20U)
8563/*! MUTEX
8564 * 0b0..Semaphore is free to take
8565 * 0b1..Semaphore is taken
8566 */
8567#define CCM_ACCESS_CTRL_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_MUTEX_MASK)
8568#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK (0x1000000U)
8569#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT (24U)
8570/*! DOMAIN0_WHITELIST
8571 * 0b0..Domain cannot change the setting
8572 * 0b1..Domain can change the setting
8573 */
8574#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK)
8575#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK (0x2000000U)
8576#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT (25U)
8577/*! DOMAIN1_WHITELIST
8578 * 0b0..Domain cannot change the setting
8579 * 0b1..Domain can change the setting
8580 */
8581#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK)
8582#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK (0x4000000U)
8583#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT (26U)
8584/*! DOMAIN2_WHITELIST
8585 * 0b0..Domain cannot change the setting
8586 * 0b1..Domain can change the setting
8587 */
8588#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK)
8589#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK (0x8000000U)
8590#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT (27U)
8591/*! DOMAIN3_WHITELIST
8592 * 0b0..Domain cannot change the setting
8593 * 0b1..Domain can change the setting
8594 */
8595#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK)
8596#define CCM_ACCESS_CTRL_SEMA_EN_MASK (0x10000000U)
8597#define CCM_ACCESS_CTRL_SEMA_EN_SHIFT (28U)
8598/*! SEMA_EN
8599 * 0b0..Disable
8600 * 0b1..Enable
8601 */
8602#define CCM_ACCESS_CTRL_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_SEMA_EN_MASK)
8603#define CCM_ACCESS_CTRL_LOCK_MASK (0x80000000U)
8604#define CCM_ACCESS_CTRL_LOCK_SHIFT (31U)
8605/*! LOCK
8606 * 0b0..Access control inactive
8607 * 0b1..Access control active
8608 */
8609#define CCM_ACCESS_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_LOCK_SHIFT)) & CCM_ACCESS_CTRL_LOCK_MASK)
8610/*! @} */
8611
8612/* The count of CCM_ACCESS_CTRL */
8613#define CCM_ACCESS_CTRL_COUNT (142U)
8614
8615/*! @name ACCESS_CTRL_ROOT_SET - Access Control Register */
8616/*! @{ */
8617#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK (0xFU)
8618#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT (0U)
8619#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK)
8620#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK (0xF0U)
8621#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT (4U)
8622#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK)
8623#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK (0xF00U)
8624#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT (8U)
8625#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK)
8626#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK (0xF000U)
8627#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT (12U)
8628#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK)
8629#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK (0x30000U)
8630#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT (16U)
8631/*! OWNER_ID
8632 * 0b00..domaino
8633 * 0b01..domain1
8634 * 0b10..domain2
8635 * 0b11..domain3
8636 */
8637#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK)
8638#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK (0x100000U)
8639#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT (20U)
8640/*! MUTEX
8641 * 0b0..Semaphore is free to take
8642 * 0b1..Semaphore is taken
8643 */
8644#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK)
8645#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK (0x1000000U)
8646#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT (24U)
8647/*! DOMAIN0_WHITELIST
8648 * 0b0..Domain cannot change the setting
8649 * 0b1..Domain can change the setting
8650 */
8651#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK)
8652#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK (0x2000000U)
8653#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT (25U)
8654/*! DOMAIN1_WHITELIST
8655 * 0b0..Domain cannot change the setting
8656 * 0b1..Domain can change the setting
8657 */
8658#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK)
8659#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK (0x4000000U)
8660#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT (26U)
8661/*! DOMAIN2_WHITELIST
8662 * 0b0..Domain cannot change the setting
8663 * 0b1..Domain can change the setting
8664 */
8665#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK)
8666#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK (0x8000000U)
8667#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT (27U)
8668/*! DOMAIN3_WHITELIST
8669 * 0b0..Domain cannot change the setting
8670 * 0b1..Domain can change the setting
8671 */
8672#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK)
8673#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK (0x10000000U)
8674#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT (28U)
8675/*! SEMA_EN
8676 * 0b0..Disable
8677 * 0b1..Enable
8678 */
8679#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK)
8680#define CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK (0x80000000U)
8681#define CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT (31U)
8682/*! LOCK
8683 * 0b0..Access control inactive
8684 * 0b1..Access control active
8685 */
8686#define CCM_ACCESS_CTRL_ROOT_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK)
8687/*! @} */
8688
8689/* The count of CCM_ACCESS_CTRL_ROOT_SET */
8690#define CCM_ACCESS_CTRL_ROOT_SET_COUNT (142U)
8691
8692/*! @name ACCESS_CTRL_ROOT_CLR - Access Control Register */
8693/*! @{ */
8694#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK (0xFU)
8695#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT (0U)
8696#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK)
8697#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK (0xF0U)
8698#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT (4U)
8699#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK)
8700#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK (0xF00U)
8701#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT (8U)
8702#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK)
8703#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK (0xF000U)
8704#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT (12U)
8705#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK)
8706#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK (0x30000U)
8707#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT (16U)
8708/*! OWNER_ID
8709 * 0b00..domaino
8710 * 0b01..domain1
8711 * 0b10..domain2
8712 * 0b11..domain3
8713 */
8714#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK)
8715#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK (0x100000U)
8716#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT (20U)
8717/*! MUTEX
8718 * 0b0..Semaphore is free to take
8719 * 0b1..Semaphore is taken
8720 */
8721#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK)
8722#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK (0x1000000U)
8723#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT (24U)
8724/*! DOMAIN0_WHITELIST
8725 * 0b0..Domain cannot change the setting
8726 * 0b1..Domain can change the setting
8727 */
8728#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK)
8729#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK (0x2000000U)
8730#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT (25U)
8731/*! DOMAIN1_WHITELIST
8732 * 0b0..Domain cannot change the setting
8733 * 0b1..Domain can change the setting
8734 */
8735#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK)
8736#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK (0x4000000U)
8737#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT (26U)
8738/*! DOMAIN2_WHITELIST
8739 * 0b0..Domain cannot change the setting
8740 * 0b1..Domain can change the setting
8741 */
8742#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK)
8743#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK (0x8000000U)
8744#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT (27U)
8745/*! DOMAIN3_WHITELIST
8746 * 0b0..Domain cannot change the setting
8747 * 0b1..Domain can change the setting
8748 */
8749#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK)
8750#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK (0x10000000U)
8751#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT (28U)
8752/*! SEMA_EN
8753 * 0b0..Disable
8754 * 0b1..Enable
8755 */
8756#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK)
8757#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK (0x80000000U)
8758#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT (31U)
8759/*! LOCK
8760 * 0b0..Access control inactive
8761 * 0b1..Access control active
8762 */
8763#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK)
8764/*! @} */
8765
8766/* The count of CCM_ACCESS_CTRL_ROOT_CLR */
8767#define CCM_ACCESS_CTRL_ROOT_CLR_COUNT (142U)
8768
8769/*! @name ACCESS_CTRL_ROOT_TOG - Access Control Register */
8770/*! @{ */
8771#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK (0xFU)
8772#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT (0U)
8773#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK)
8774#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK (0xF0U)
8775#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT (4U)
8776#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK)
8777#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK (0xF00U)
8778#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT (8U)
8779#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK)
8780#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK (0xF000U)
8781#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT (12U)
8782#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK)
8783#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK (0x30000U)
8784#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT (16U)
8785/*! OWNER_ID
8786 * 0b00..domaino
8787 * 0b01..domain1
8788 * 0b10..domain2
8789 * 0b11..domain3
8790 */
8791#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK)
8792#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK (0x100000U)
8793#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT (20U)
8794/*! MUTEX
8795 * 0b0..Semaphore is free to take
8796 * 0b1..Semaphore is taken
8797 */
8798#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK)
8799#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK (0x1000000U)
8800#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT (24U)
8801/*! DOMAIN0_WHITELIST
8802 * 0b0..Domain cannot change the setting
8803 * 0b1..Domain can change the setting
8804 */
8805#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK)
8806#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK (0x2000000U)
8807#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT (25U)
8808/*! DOMAIN1_WHITELIST
8809 * 0b0..Domain cannot change the setting
8810 * 0b1..Domain can change the setting
8811 */
8812#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK)
8813#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK (0x4000000U)
8814#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT (26U)
8815/*! DOMAIN2_WHITELIST
8816 * 0b0..Domain cannot change the setting
8817 * 0b1..Domain can change the setting
8818 */
8819#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK)
8820#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK (0x8000000U)
8821#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT (27U)
8822/*! DOMAIN3_WHITELIST
8823 * 0b0..Domain cannot change the setting
8824 * 0b1..Domain can change the setting
8825 */
8826#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK)
8827#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK (0x10000000U)
8828#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT (28U)
8829/*! SEMA_EN
8830 * 0b0..Disable
8831 * 0b1..Enable
8832 */
8833#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK)
8834#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK (0x80000000U)
8835#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT (31U)
8836/*! LOCK
8837 * 0b0..Access control inactive
8838 * 0b1..Access control active
8839 */
8840#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK)
8841/*! @} */
8842
8843/* The count of CCM_ACCESS_CTRL_ROOT_TOG */
8844#define CCM_ACCESS_CTRL_ROOT_TOG_COUNT (142U)
8845
8846
8847/*!
8848 * @}
8849 */ /* end of group CCM_Register_Masks */
8850
8851
8852/* CCM - Peripheral instance base addresses */
8853/** Peripheral CCM base address */
8854#define CCM_BASE (0x30380000u)
8855/** Peripheral CCM base pointer */
8856#define CCM ((CCM_Type *)CCM_BASE)
8857/** Array initializer of CCM peripheral base addresses */
8858#define CCM_BASE_ADDRS { CCM_BASE }
8859/** Array initializer of CCM peripheral base pointers */
8860#define CCM_BASE_PTRS { CCM }
8861/** Interrupt vectors for the CCM peripheral type */
8862#define CCM_IRQS { CCM_IRQ1_IRQn, CCM_IRQ2_IRQn }
8863
8864/*!
8865 * @}
8866 */ /* end of group CCM_Peripheral_Access_Layer */
8867
8868
8869/* ----------------------------------------------------------------------------
8870 -- CCM_ANALOG Peripheral Access Layer
8871 ---------------------------------------------------------------------------- */
8872
8873/*!
8874 * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer
8875 * @{
8876 */
8877
8878/** CCM_ANALOG - Register Layout Typedef */
8879typedef struct {
8880 __IO uint32_t AUDIO_PLL1_CFG0; /**< AUDIO PLL1 Configuration 0 Register, offset: 0x0 */
8881 __IO uint32_t AUDIO_PLL1_CFG1; /**< AUDIO PLL1 Configuration 1 Register, offset: 0x4 */
8882 __IO uint32_t AUDIO_PLL2_CFG0; /**< AUDIO PLL2 Configuration 0 Register, offset: 0x8 */
8883 __IO uint32_t AUDIO_PLL2_CFG1; /**< AUDIO PLL2 Configuration 1 Register, offset: 0xC */
8884 __IO uint32_t VIDEO_PLL1_CFG0; /**< VIDEO PLL Configuration 0 Register, offset: 0x10 */
8885 __IO uint32_t VIDEO_PLL1_CFG1; /**< VIDEO PLL Configuration 1 Register, offset: 0x14 */
8886 __IO uint32_t GPU_PLL_CFG0; /**< GPU PLL Configuration 0 Register, offset: 0x18 */
8887 __IO uint32_t GPU_PLL_CFG1; /**< GPU PLL Configuration 1 Register, offset: 0x1C */
8888 __IO uint32_t VPU_PLL_CFG0; /**< VPU PLL Configuration 0 Register, offset: 0x20 */
8889 __IO uint32_t VPU_PLL_CFG1; /**< VPU PLL Configuration 1 Register, offset: 0x24 */
8890 __IO uint32_t ARM_PLL_CFG0; /**< ARM PLL Configuration 0 Register, offset: 0x28 */
8891 __IO uint32_t ARM_PLL_CFG1; /**< ARM PLL Configuration 1 Register, offset: 0x2C */
8892 __IO uint32_t SYS_PLL1_CFG0; /**< System PLL Configuration 0 Register, offset: 0x30 */
8893 __IO uint32_t SYS_PLL1_CFG1; /**< System_PLL Configuration 1 Register, offset: 0x34 */
8894 __IO uint32_t SYS_PLL1_CFG2; /**< System_PLL Configuration 2 Register, offset: 0x38 */
8895 __IO uint32_t SYS_PLL2_CFG0; /**< System PLL Configuration 0 Register, offset: 0x3C */
8896 __IO uint32_t SYS_PLL2_CFG1; /**< System_PLL Configuration 1 Register, offset: 0x40 */
8897 __IO uint32_t SYS_PLL2_CFG2; /**< System_PLL Configuration 2 Register, offset: 0x44 */
8898 __IO uint32_t SYS_PLL3_CFG0; /**< System PLL Configuration 0 Register, offset: 0x48 */
8899 __IO uint32_t SYS_PLL3_CFG1; /**< System_PLL Configuration 1 Register, offset: 0x4C */
8900 __IO uint32_t SYS_PLL3_CFG2; /**< System_PLL Configuration 2 Register, offset: 0x50 */
8901 __IO uint32_t VIDEO_PLL2_CFG0; /**< VIDEO PLL2 Configuration 0 Register, offset: 0x54 */
8902 __IO uint32_t VIDEO_PLL2_CFG1; /**< VIDEO PLL2 Configuration 1 Register, offset: 0x58 */
8903 __IO uint32_t VIDEO_PLL2_CFG2; /**< VIDEO PLL2 Configuration 2 Register, offset: 0x5C */
8904 __IO uint32_t DRAM_PLL_CFG0; /**< DRAM PLL Configuration 0 Register, offset: 0x60 */
8905 __IO uint32_t DRAM_PLL_CFG1; /**< DRAM PLL Configuration 1 Register, offset: 0x64 */
8906 __IO uint32_t DRAM_PLL_CFG2; /**< DRAM PLL Configuration 2 Register, offset: 0x68 */
8907 __I uint32_t DIGPROG; /**< DIGPROG Register, offset: 0x6C */
8908 __IO uint32_t OSC_MISC_CFG; /**< Osc Misc Configuration Register, offset: 0x70 */
8909 __IO uint32_t PLLOUT_MONITOR_CFG; /**< PLLOUT Monitor Configuration Register, offset: 0x74 */
8910 __IO uint32_t FRAC_PLLOUT_DIV_CFG; /**< Fractional PLLOUT Divider Configuration Register, offset: 0x78 */
8911 __IO uint32_t SCCG_PLLOUT_DIV_CFG; /**< SCCG PLLOUT Divider Configuration Register, offset: 0x7C */
8912} CCM_ANALOG_Type;
8913
8914/* ----------------------------------------------------------------------------
8915 -- CCM_ANALOG Register Masks
8916 ---------------------------------------------------------------------------- */
8917
8918/*!
8919 * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks
8920 * @{
8921 */
8922
8923/*! @name AUDIO_PLL1_CFG0 - AUDIO PLL1 Configuration 0 Register */
8924/*! @{ */
8925#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK (0x1FU)
8926#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT (0U)
8927#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK)
8928#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK (0x7E0U)
8929#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_SHIFT (5U)
8930#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK)
8931#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_ACK_MASK (0x800U)
8932#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_ACK_SHIFT (11U)
8933#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_ACK_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_ACK_MASK)
8934#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL_MASK (0x1000U)
8935#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL_SHIFT (12U)
8936#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL_MASK)
8937#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_COUNTCLK_SEL_MASK (0x2000U)
8938#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_COUNTCLK_SEL_SHIFT (13U)
8939/*! PLL_COUNTCLK_SEL
8940 * 0b0..25M_REF_CLK
8941 * 0b1..27M_REF_CLK
8942 */
8943#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_COUNTCLK_SEL_MASK)
8944#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS_MASK (0x4000U)
8945#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS_SHIFT (14U)
8946#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS_MASK)
8947#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SEL_MASK (0x8000U)
8948#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SEL_SHIFT (15U)
8949/*! PLL_LOCK_SEL
8950 * 0b0..Select PLL lock output
8951 * 0b1..Select maximum lock time counter output
8952 */
8953#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SEL_MASK)
8954#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_MASK (0x30000U)
8955#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT (16U)
8956/*! PLL_REFCLK_SEL
8957 * 0b00..25M_REF_CLK
8958 * 0b01..27M_REF_CLK
8959 * 0b10..HDMI_PHY_27M_CLK
8960 * 0b11..CLK_P_N
8961 */
8962#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_MASK)
8963#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_OVERRIDE_MASK (0x40000U)
8964#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_OVERRIDE_SHIFT (18U)
8965#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_OVERRIDE_MASK)
8966#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_MASK (0x80000U)
8967#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_SHIFT (19U)
8968#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_MASK)
8969#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100000U)
8970#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_OVERRIDE_SHIFT (20U)
8971#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_OVERRIDE_MASK)
8972#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_MASK (0x200000U)
8973#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_SHIFT (21U)
8974#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_MASK)
8975#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_MASK (0x80000000U)
8976#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SHIFT (31U)
8977#define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_MASK)
8978/*! @} */
8979
8980/*! @name AUDIO_PLL1_CFG1 - AUDIO PLL1 Configuration 1 Register */
8981/*! @{ */
8982#define CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK (0x7FU)
8983#define CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_SHIFT (0U)
8984#define CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK)
8985#define CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK (0x7FFFFF80U)
8986#define CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_SHIFT (7U)
8987#define CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK)
8988/*! @} */
8989
8990/*! @name AUDIO_PLL2_CFG0 - AUDIO PLL2 Configuration 0 Register */
8991/*! @{ */
8992#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_OUTPUT_DIV_VAL_MASK (0x1FU)
8993#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT (0U)
8994#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_OUTPUT_DIV_VAL_MASK)
8995#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_DIV_VAL_MASK (0x7E0U)
8996#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_DIV_VAL_SHIFT (5U)
8997#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_DIV_VAL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_DIV_VAL_MASK)
8998#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_ACK_MASK (0x800U)
8999#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_ACK_SHIFT (11U)
9000#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_ACK_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_ACK_MASK)
9001#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_VAL_MASK (0x1000U)
9002#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_VAL_SHIFT (12U)
9003#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_VAL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_VAL_MASK)
9004#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_COUNTCLK_SEL_MASK (0x2000U)
9005#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_COUNTCLK_SEL_SHIFT (13U)
9006/*! PLL_COUNTCLK_SEL
9007 * 0b0..25M_REF_CLK
9008 * 0b1..27M_REF_CLK
9009 */
9010#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_COUNTCLK_SEL_MASK)
9011#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS_MASK (0x4000U)
9012#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS_SHIFT (14U)
9013#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS_MASK)
9014#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SEL_MASK (0x8000U)
9015#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SEL_SHIFT (15U)
9016/*! PLL_LOCK_SEL
9017 * 0b0..Select PLL lock output
9018 * 0b1..Select maximum lock time counter output
9019 */
9020#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SEL_MASK)
9021#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_SEL_MASK (0x30000U)
9022#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_SEL_SHIFT (16U)
9023/*! PLL_REFCLK_SEL
9024 * 0b00..25M_REF_CLK
9025 * 0b01..27M_REF_CLK
9026 * 0b10..HDMI_PHY_27M_CLK
9027 * 0b11..CLK_P_N
9028 */
9029#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_SEL_MASK)
9030#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_OVERRIDE_MASK (0x40000U)
9031#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_OVERRIDE_SHIFT (18U)
9032#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_OVERRIDE_MASK)
9033#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_MASK (0x80000U)
9034#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_SHIFT (19U)
9035#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_MASK)
9036#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100000U)
9037#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_OVERRIDE_SHIFT (20U)
9038#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_OVERRIDE_MASK)
9039#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_MASK (0x200000U)
9040#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_SHIFT (21U)
9041#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_MASK)
9042#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_MASK (0x80000000U)
9043#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SHIFT (31U)
9044#define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_MASK)
9045/*! @} */
9046
9047/*! @name AUDIO_PLL2_CFG1 - AUDIO PLL2 Configuration 1 Register */
9048/*! @{ */
9049#define CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_INT_DIV_CTL_MASK (0x7FU)
9050#define CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_INT_DIV_CTL_SHIFT (0U)
9051#define CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_INT_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_INT_DIV_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_INT_DIV_CTL_MASK)
9052#define CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_FRAC_DIV_CTL_MASK (0x7FFFFF80U)
9053#define CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_FRAC_DIV_CTL_SHIFT (7U)
9054#define CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_FRAC_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_FRAC_DIV_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_FRAC_DIV_CTL_MASK)
9055/*! @} */
9056
9057/*! @name VIDEO_PLL1_CFG0 - VIDEO PLL Configuration 0 Register */
9058/*! @{ */
9059#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK (0x1FU)
9060#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT (0U)
9061#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK)
9062#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK (0x7E0U)
9063#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_SHIFT (5U)
9064#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK)
9065#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_ACK_MASK (0x800U)
9066#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_ACK_SHIFT (11U)
9067#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_ACK_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_ACK_MASK)
9068#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_VAL_MASK (0x1000U)
9069#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_VAL_SHIFT (12U)
9070#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_VAL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_VAL_MASK)
9071#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_COUNTCLK_SEL_MASK (0x2000U)
9072#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_COUNTCLK_SEL_SHIFT (13U)
9073/*! PLL_COUNTCLK_SEL
9074 * 0b0..25M_REF_CLK
9075 * 0b1..27M_REF_CLK
9076 */
9077#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_COUNTCLK_SEL_MASK)
9078#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS_MASK (0x4000U)
9079#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS_SHIFT (14U)
9080#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS_MASK)
9081#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SEL_MASK (0x8000U)
9082#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SEL_SHIFT (15U)
9083/*! PLL_LOCK_SEL
9084 * 0b0..Select PLL lock output
9085 * 0b1..Select maximum lock time counter output
9086 */
9087#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SEL_MASK)
9088#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_SEL_MASK (0x30000U)
9089#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT (16U)
9090/*! PLL_REFCLK_SEL
9091 * 0b00..25M_REF_CLK
9092 * 0b01..27M_REF_CLK
9093 * 0b10..HDMI_PHY_27M_CLK
9094 * 0b11..CLK_P_N
9095 */
9096#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_SEL_MASK)
9097#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_OVERRIDE_MASK (0x40000U)
9098#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_OVERRIDE_SHIFT (18U)
9099#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_OVERRIDE_MASK)
9100#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_MASK (0x80000U)
9101#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_SHIFT (19U)
9102#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_MASK)
9103#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100000U)
9104#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_OVERRIDE_SHIFT (20U)
9105#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_OVERRIDE_MASK)
9106#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_MASK (0x200000U)
9107#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_SHIFT (21U)
9108#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_MASK)
9109#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_MASK (0x80000000U)
9110#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SHIFT (31U)
9111#define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_MASK)
9112/*! @} */
9113
9114/*! @name VIDEO_PLL1_CFG1 - VIDEO PLL Configuration 1 Register */
9115/*! @{ */
9116#define CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK (0x7FU)
9117#define CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_INT_DIV_CTL_SHIFT (0U)
9118#define CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_INT_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_INT_DIV_CTL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK)
9119#define CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK (0x7FFFFF80U)
9120#define CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_FRAC_DIV_CTL_SHIFT (7U)
9121#define CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_FRAC_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_FRAC_DIV_CTL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK)
9122/*! @} */
9123
9124/*! @name GPU_PLL_CFG0 - GPU PLL Configuration 0 Register */
9125/*! @{ */
9126#define CCM_ANALOG_GPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_MASK (0x1FU)
9127#define CCM_ANALOG_GPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT (0U)
9128#define CCM_ANALOG_GPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_MASK)
9129#define CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_MASK (0x7E0U)
9130#define CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_SHIFT (5U)
9131#define CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_MASK)
9132#define CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_ACK_MASK (0x800U)
9133#define CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_ACK_SHIFT (11U)
9134#define CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_ACK_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_ACK_MASK)
9135#define CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_VAL_MASK (0x1000U)
9136#define CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_VAL_SHIFT (12U)
9137#define CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_VAL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_VAL_MASK)
9138#define CCM_ANALOG_GPU_PLL_CFG0_PLL_COUNTCLK_SEL_MASK (0x2000U)
9139#define CCM_ANALOG_GPU_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT (13U)
9140/*! PLL_COUNTCLK_SEL
9141 * 0b0..25M_REF_CLK
9142 * 0b1..27M_REF_CLK
9143 */
9144#define CCM_ANALOG_GPU_PLL_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_COUNTCLK_SEL_MASK)
9145#define CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS_MASK (0x4000U)
9146#define CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS_SHIFT (14U)
9147#define CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS_MASK)
9148#define CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SEL_MASK (0x8000U)
9149#define CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SEL_SHIFT (15U)
9150/*! PLL_LOCK_SEL
9151 * 0b0..Select PLL lock output
9152 * 0b1..Select maximum lock time counter output
9153 */
9154#define CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SEL_MASK)
9155#define CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_SEL_MASK (0x30000U)
9156#define CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_SEL_SHIFT (16U)
9157/*! PLL_REFCLK_SEL
9158 * 0b00..25M_REF_CLK
9159 * 0b01..27M_REF_CLK
9160 * 0b10..HDMI_PHY_27M_CLK
9161 * 0b11..CLK_P_N
9162 */
9163#define CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_SEL_MASK)
9164#define CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_OVERRIDE_MASK (0x40000U)
9165#define CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT (18U)
9166#define CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_OVERRIDE_MASK)
9167#define CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_MASK (0x80000U)
9168#define CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_SHIFT (19U)
9169#define CCM_ANALOG_GPU_PLL_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_MASK)
9170#define CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100000U)
9171#define CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT (20U)
9172#define CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK)
9173#define CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_MASK (0x200000U)
9174#define CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_SHIFT (21U)
9175#define CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_MASK)
9176#define CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_MASK (0x80000000U)
9177#define CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SHIFT (31U)
9178#define CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_MASK)
9179/*! @} */
9180
9181/*! @name GPU_PLL_CFG1 - GPU PLL Configuration 1 Register */
9182/*! @{ */
9183#define CCM_ANALOG_GPU_PLL_CFG1_PLL_INT_DIV_CTL_MASK (0x7FU)
9184#define CCM_ANALOG_GPU_PLL_CFG1_PLL_INT_DIV_CTL_SHIFT (0U)
9185#define CCM_ANALOG_GPU_PLL_CFG1_PLL_INT_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG1_PLL_INT_DIV_CTL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG1_PLL_INT_DIV_CTL_MASK)
9186#define CCM_ANALOG_GPU_PLL_CFG1_PLL_FRAC_DIV_CTL_MASK (0x7FFFFF80U)
9187#define CCM_ANALOG_GPU_PLL_CFG1_PLL_FRAC_DIV_CTL_SHIFT (7U)
9188#define CCM_ANALOG_GPU_PLL_CFG1_PLL_FRAC_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG1_PLL_FRAC_DIV_CTL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG1_PLL_FRAC_DIV_CTL_MASK)
9189/*! @} */
9190
9191/*! @name VPU_PLL_CFG0 - VPU PLL Configuration 0 Register */
9192/*! @{ */
9193#define CCM_ANALOG_VPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_MASK (0x1FU)
9194#define CCM_ANALOG_VPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT (0U)
9195#define CCM_ANALOG_VPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_MASK)
9196#define CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_MASK (0x7E0U)
9197#define CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_SHIFT (5U)
9198#define CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_MASK)
9199#define CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_ACK_MASK (0x800U)
9200#define CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_ACK_SHIFT (11U)
9201#define CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_ACK_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_ACK_MASK)
9202#define CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_VAL_MASK (0x1000U)
9203#define CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_VAL_SHIFT (12U)
9204#define CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_VAL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_VAL_MASK)
9205#define CCM_ANALOG_VPU_PLL_CFG0_PLL_COUNTCLK_SEL_MASK (0x2000U)
9206#define CCM_ANALOG_VPU_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT (13U)
9207/*! PLL_COUNTCLK_SEL
9208 * 0b0..25M_REF_CLK
9209 * 0b1..27M_REF_CLK
9210 */
9211#define CCM_ANALOG_VPU_PLL_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_COUNTCLK_SEL_MASK)
9212#define CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS_MASK (0x4000U)
9213#define CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS_SHIFT (14U)
9214#define CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS_MASK)
9215#define CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SEL_MASK (0x8000U)
9216#define CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SEL_SHIFT (15U)
9217/*! PLL_LOCK_SEL
9218 * 0b0..Select PLL lock output
9219 * 0b1..Select maximum lock time counter output
9220 */
9221#define CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SEL_MASK)
9222#define CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_SEL_MASK (0x30000U)
9223#define CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_SEL_SHIFT (16U)
9224/*! PLL_REFCLK_SEL
9225 * 0b00..25M_REF_CLK
9226 * 0b01..27M_REF_CLK
9227 * 0b10..HDMI_PHY_27M_CLK
9228 * 0b11..CLK_P_N
9229 */
9230#define CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_SEL_MASK)
9231#define CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_OVERRIDE_MASK (0x40000U)
9232#define CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT (18U)
9233#define CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_OVERRIDE_MASK)
9234#define CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_MASK (0x80000U)
9235#define CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_SHIFT (19U)
9236#define CCM_ANALOG_VPU_PLL_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_MASK)
9237#define CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100000U)
9238#define CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT (20U)
9239#define CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK)
9240#define CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_MASK (0x200000U)
9241#define CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_SHIFT (21U)
9242#define CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_MASK)
9243#define CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_MASK (0x80000000U)
9244#define CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SHIFT (31U)
9245#define CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_MASK)
9246/*! @} */
9247
9248/*! @name VPU_PLL_CFG1 - VPU PLL Configuration 1 Register */
9249/*! @{ */
9250#define CCM_ANALOG_VPU_PLL_CFG1_PLL_INT_DIV_CTL_MASK (0x7FU)
9251#define CCM_ANALOG_VPU_PLL_CFG1_PLL_INT_DIV_CTL_SHIFT (0U)
9252#define CCM_ANALOG_VPU_PLL_CFG1_PLL_INT_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG1_PLL_INT_DIV_CTL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG1_PLL_INT_DIV_CTL_MASK)
9253#define CCM_ANALOG_VPU_PLL_CFG1_PLL_FRAC_DIV_CTL_MASK (0x7FFFFF80U)
9254#define CCM_ANALOG_VPU_PLL_CFG1_PLL_FRAC_DIV_CTL_SHIFT (7U)
9255#define CCM_ANALOG_VPU_PLL_CFG1_PLL_FRAC_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG1_PLL_FRAC_DIV_CTL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG1_PLL_FRAC_DIV_CTL_MASK)
9256/*! @} */
9257
9258/*! @name ARM_PLL_CFG0 - ARM PLL Configuration 0 Register */
9259/*! @{ */
9260#define CCM_ANALOG_ARM_PLL_CFG0_PLL_OUTPUT_DIV_VAL_MASK (0x1FU)
9261#define CCM_ANALOG_ARM_PLL_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT (0U)
9262#define CCM_ANALOG_ARM_PLL_CFG0_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_OUTPUT_DIV_VAL_MASK)
9263#define CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_DIV_VAL_MASK (0x7E0U)
9264#define CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_DIV_VAL_SHIFT (5U)
9265#define CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_DIV_VAL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_DIV_VAL_MASK)
9266#define CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_ACK_MASK (0x800U)
9267#define CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_ACK_SHIFT (11U)
9268#define CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_ACK_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_ACK_MASK)
9269#define CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_VAL_MASK (0x1000U)
9270#define CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_VAL_SHIFT (12U)
9271#define CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_VAL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_VAL_MASK)
9272#define CCM_ANALOG_ARM_PLL_CFG0_PLL_COUNTCLK_SEL_MASK (0x2000U)
9273#define CCM_ANALOG_ARM_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT (13U)
9274/*! PLL_COUNTCLK_SEL
9275 * 0b0..25M_REF_CLK
9276 * 0b1..27M_REF_CLK
9277 */
9278#define CCM_ANALOG_ARM_PLL_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_COUNTCLK_SEL_MASK)
9279#define CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS_MASK (0x4000U)
9280#define CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS_SHIFT (14U)
9281#define CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS_MASK)
9282#define CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SEL_MASK (0x8000U)
9283#define CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SEL_SHIFT (15U)
9284/*! PLL_LOCK_SEL
9285 * 0b0..Select PLL lock output
9286 * 0b1..Select maximum lock time counter output
9287 */
9288#define CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SEL_MASK)
9289#define CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_SEL_MASK (0x30000U)
9290#define CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_SEL_SHIFT (16U)
9291/*! PLL_REFCLK_SEL
9292 * 0b00..25M_REF_CLK
9293 * 0b01..27M_REF_CLK
9294 * 0b10..HDMI_PHY_27M_CLK
9295 * 0b11..CLK_P_N
9296 */
9297#define CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_SEL_MASK)
9298#define CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_OVERRIDE_MASK (0x40000U)
9299#define CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT (18U)
9300#define CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_OVERRIDE_MASK)
9301#define CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_MASK (0x80000U)
9302#define CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_SHIFT (19U)
9303#define CCM_ANALOG_ARM_PLL_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_MASK)
9304#define CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100000U)
9305#define CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT (20U)
9306#define CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK)
9307#define CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_MASK (0x200000U)
9308#define CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_SHIFT (21U)
9309#define CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_MASK)
9310#define CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_MASK (0x80000000U)
9311#define CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SHIFT (31U)
9312#define CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_MASK)
9313/*! @} */
9314
9315/*! @name ARM_PLL_CFG1 - ARM PLL Configuration 1 Register */
9316/*! @{ */
9317#define CCM_ANALOG_ARM_PLL_CFG1_PLL_INT_DIV_CTL_MASK (0x7FU)
9318#define CCM_ANALOG_ARM_PLL_CFG1_PLL_INT_DIV_CTL_SHIFT (0U)
9319#define CCM_ANALOG_ARM_PLL_CFG1_PLL_INT_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG1_PLL_INT_DIV_CTL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG1_PLL_INT_DIV_CTL_MASK)
9320#define CCM_ANALOG_ARM_PLL_CFG1_PLL_FRAC_DIV_CTL_MASK (0x7FFFFF80U)
9321#define CCM_ANALOG_ARM_PLL_CFG1_PLL_FRAC_DIV_CTL_SHIFT (7U)
9322#define CCM_ANALOG_ARM_PLL_CFG1_PLL_FRAC_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG1_PLL_FRAC_DIV_CTL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG1_PLL_FRAC_DIV_CTL_MASK)
9323/*! @} */
9324
9325/*! @name SYS_PLL1_CFG0 - System PLL Configuration 0 Register */
9326/*! @{ */
9327#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_MASK (0x3U)
9328#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT (0U)
9329/*! PLL_REFCLK_SEL
9330 * 0b00..25M_REF_CLK
9331 * 0b01..27M_REF_CLK
9332 * 0b10..HDMI_PHY_27M_CLK
9333 * 0b11..CLK_P_N
9334 */
9335#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_MASK)
9336#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_COUNTCLK_SEL_MASK (0x4U)
9337#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_COUNTCLK_SEL_SHIFT (2U)
9338/*! PLL_COUNTCLK_SEL
9339 * 0b0..25M_REF_CLK
9340 * 0b1..27M_REF_CLK
9341 */
9342#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_COUNTCLK_SEL_MASK)
9343#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SEL_MASK (0x8U)
9344#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SEL_SHIFT (3U)
9345/*! PLL_LOCK_SEL
9346 * 0b0..Select PLL lock output
9347 * 0b1..Select maximum lock time counter output
9348 */
9349#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SEL_MASK)
9350#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2_MASK (0x10U)
9351#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2_SHIFT (4U)
9352#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2_MASK)
9353#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_MASK (0x20U)
9354#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_SHIFT (5U)
9355#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_MASK)
9356#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_OVERRIDE_MASK (0x40U)
9357#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_OVERRIDE_SHIFT (6U)
9358#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_OVERRIDE_MASK)
9359#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_MASK (0x80U)
9360#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_SHIFT (7U)
9361#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_MASK)
9362#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_OVERRIDE_MASK (0x100U)
9363#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_OVERRIDE_SHIFT (8U)
9364#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_OVERRIDE_MASK)
9365#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE_MASK (0x200U)
9366#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE_SHIFT (9U)
9367#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE_MASK)
9368#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_OVERRIDE_MASK (0x400U)
9369#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_OVERRIDE_SHIFT (10U)
9370#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_OVERRIDE_MASK)
9371#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE_MASK (0x800U)
9372#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE_SHIFT (11U)
9373#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE_MASK)
9374#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_OVERRIDE_MASK (0x1000U)
9375#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_OVERRIDE_SHIFT (12U)
9376#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_OVERRIDE_MASK)
9377#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE_MASK (0x2000U)
9378#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE_SHIFT (13U)
9379#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE_MASK)
9380#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_OVERRIDE_MASK (0x4000U)
9381#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_OVERRIDE_SHIFT (14U)
9382#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_OVERRIDE_MASK)
9383#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE_MASK (0x8000U)
9384#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE_SHIFT (15U)
9385#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE_MASK)
9386#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_OVERRIDE_MASK (0x10000U)
9387#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_OVERRIDE_SHIFT (16U)
9388#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_OVERRIDE_MASK)
9389#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE_MASK (0x20000U)
9390#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE_SHIFT (17U)
9391#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE_MASK)
9392#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_OVERRIDE_MASK (0x40000U)
9393#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_OVERRIDE_SHIFT (18U)
9394#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_OVERRIDE_MASK)
9395#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE_MASK (0x80000U)
9396#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE_SHIFT (19U)
9397#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE_MASK)
9398#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_OVERRIDE_MASK (0x100000U)
9399#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_OVERRIDE_SHIFT (20U)
9400#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_OVERRIDE_MASK)
9401#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE_MASK (0x200000U)
9402#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE_SHIFT (21U)
9403#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE_MASK)
9404#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_OVERRIDE_MASK (0x400000U)
9405#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_OVERRIDE_SHIFT (22U)
9406#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_OVERRIDE_MASK)
9407#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE_MASK (0x800000U)
9408#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE_SHIFT (23U)
9409#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE_MASK)
9410#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_OVERRIDE_MASK (0x1000000U)
9411#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_OVERRIDE_SHIFT (24U)
9412#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_OVERRIDE_MASK)
9413#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_MASK (0x2000000U)
9414#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_SHIFT (25U)
9415#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_MASK)
9416#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_MASK (0x80000000U)
9417#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SHIFT (31U)
9418#define CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_MASK)
9419/*! @} */
9420
9421/*! @name SYS_PLL1_CFG1 - System_PLL Configuration 1 Register */
9422/*! @{ */
9423#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE_MASK (0x1U)
9424#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE_SHIFT (0U)
9425#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE_MASK)
9426#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMF_MASK (0x1EU)
9427#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMF_SHIFT (1U)
9428#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMF_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMF_MASK)
9429#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMD_MASK (0xE0U)
9430#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMD_SHIFT (5U)
9431/*! PLL_SSMD
9432 * 0b000..0.25
9433 * 0b001..0.5
9434 * 0b010..0.75
9435 * 0b011..1.0
9436 * 0b100..1.5
9437 * 0b101..2.0
9438 * 0b110..3.0
9439 * 0b111..4.0
9440 */
9441#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMD_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMD_MASK)
9442#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSDS_MASK (0x100U)
9443#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSDS_SHIFT (8U)
9444/*! PLL_SSDS
9445 * 0b0..Center Spread
9446 * 0b1..Down Spread
9447 */
9448#define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSDS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSDS_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSDS_MASK)
9449/*! @} */
9450
9451/*! @name SYS_PLL1_CFG2 - System_PLL Configuration 2 Register */
9452/*! @{ */
9453#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FILTER_RANGE_MASK (0x1U)
9454#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FILTER_RANGE_SHIFT (0U)
9455/*! PLL_FILTER_RANGE
9456 * 0b0..25 to 35 MHz
9457 * 0b1..35 to 54 MHz
9458 */
9459#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FILTER_RANGE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG2_PLL_FILTER_RANGE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG2_PLL_FILTER_RANGE_MASK)
9460#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_MASK (0x7EU)
9461#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT (1U)
9462#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_MASK)
9463#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_MASK (0x1F80U)
9464#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_SHIFT (7U)
9465#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_MASK)
9466#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_MASK (0x7E000U)
9467#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_SHIFT (13U)
9468#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_MASK)
9469#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK (0x1F80000U)
9470#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_SHIFT (19U)
9471#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK)
9472#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_MASK (0xE000000U)
9473#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_SHIFT (25U)
9474#define CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_MASK)
9475/*! @} */
9476
9477/*! @name SYS_PLL2_CFG0 - System PLL Configuration 0 Register */
9478/*! @{ */
9479#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_REFCLK_SEL_MASK (0x3U)
9480#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_REFCLK_SEL_SHIFT (0U)
9481/*! PLL_REFCLK_SEL
9482 * 0b00..25M_REF_CLK
9483 * 0b01..27M_REF_CLK
9484 * 0b10..HDMI_PHY_27M_CLK
9485 * 0b11..CLK_P_N
9486 */
9487#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_REFCLK_SEL_MASK)
9488#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_COUNTCLK_SEL_MASK (0x4U)
9489#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_COUNTCLK_SEL_SHIFT (2U)
9490/*! PLL_COUNTCLK_SEL
9491 * 0b0..25M_REF_CLK
9492 * 0b1..27M_REF_CLK
9493 */
9494#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_COUNTCLK_SEL_MASK)
9495#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SEL_MASK (0x8U)
9496#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SEL_SHIFT (3U)
9497/*! PLL_LOCK_SEL
9498 * 0b0..Select PLL lock output
9499 * 0b1..Select maximum lock time counter output
9500 */
9501#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SEL_MASK)
9502#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2_MASK (0x10U)
9503#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2_SHIFT (4U)
9504#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2_MASK)
9505#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1_MASK (0x20U)
9506#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1_SHIFT (5U)
9507#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1_MASK)
9508#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_OVERRIDE_MASK (0x40U)
9509#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_OVERRIDE_SHIFT (6U)
9510#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_OVERRIDE_MASK)
9511#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_MASK (0x80U)
9512#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_SHIFT (7U)
9513#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_MASK)
9514#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_OVERRIDE_MASK (0x100U)
9515#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_OVERRIDE_SHIFT (8U)
9516#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_OVERRIDE_MASK)
9517#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE_MASK (0x200U)
9518#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE_SHIFT (9U)
9519#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE_MASK)
9520#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_OVERRIDE_MASK (0x400U)
9521#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_OVERRIDE_SHIFT (10U)
9522#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_OVERRIDE_MASK)
9523#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE_MASK (0x800U)
9524#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE_SHIFT (11U)
9525#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE_MASK)
9526#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_OVERRIDE_MASK (0x1000U)
9527#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_OVERRIDE_SHIFT (12U)
9528#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_OVERRIDE_MASK)
9529#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE_MASK (0x2000U)
9530#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE_SHIFT (13U)
9531#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE_MASK)
9532#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_OVERRIDE_MASK (0x4000U)
9533#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_OVERRIDE_SHIFT (14U)
9534#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_OVERRIDE_MASK)
9535#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE_MASK (0x8000U)
9536#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE_SHIFT (15U)
9537#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE_MASK)
9538#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_OVERRIDE_MASK (0x10000U)
9539#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_OVERRIDE_SHIFT (16U)
9540#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_OVERRIDE_MASK)
9541#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE_MASK (0x20000U)
9542#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE_SHIFT (17U)
9543#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE_MASK)
9544#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_OVERRIDE_MASK (0x40000U)
9545#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_OVERRIDE_SHIFT (18U)
9546#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_OVERRIDE_MASK)
9547#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE_MASK (0x80000U)
9548#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE_SHIFT (19U)
9549#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE_MASK)
9550#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_OVERRIDE_MASK (0x100000U)
9551#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_OVERRIDE_SHIFT (20U)
9552#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_OVERRIDE_MASK)
9553#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE_MASK (0x200000U)
9554#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE_SHIFT (21U)
9555#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE_MASK)
9556#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_OVERRIDE_MASK (0x400000U)
9557#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_OVERRIDE_SHIFT (22U)
9558#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_OVERRIDE_MASK)
9559#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE_MASK (0x800000U)
9560#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE_SHIFT (23U)
9561#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE_MASK)
9562#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_OVERRIDE_MASK (0x1000000U)
9563#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_OVERRIDE_SHIFT (24U)
9564#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_OVERRIDE_MASK)
9565#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_MASK (0x2000000U)
9566#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_SHIFT (25U)
9567#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_MASK)
9568#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_MASK (0x80000000U)
9569#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SHIFT (31U)
9570#define CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_MASK)
9571/*! @} */
9572
9573/*! @name SYS_PLL2_CFG1 - System_PLL Configuration 1 Register */
9574/*! @{ */
9575#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSE_MASK (0x1U)
9576#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSE_SHIFT (0U)
9577#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSE_MASK)
9578#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMF_MASK (0x1EU)
9579#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMF_SHIFT (1U)
9580#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMF_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMF_MASK)
9581#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMD_MASK (0xE0U)
9582#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMD_SHIFT (5U)
9583/*! PLL_SSMD
9584 * 0b000..0.25
9585 * 0b001..0.5
9586 * 0b010..0.75
9587 * 0b011..1.0
9588 * 0b100..1.5
9589 * 0b101..2.0
9590 * 0b110..3.0
9591 * 0b111..4.0
9592 */
9593#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMD_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMD_MASK)
9594#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSDS_MASK (0x100U)
9595#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSDS_SHIFT (8U)
9596/*! PLL_SSDS
9597 * 0b0..Center Spread
9598 * 0b1..Down Spread
9599 */
9600#define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSDS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSDS_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSDS_MASK)
9601/*! @} */
9602
9603/*! @name SYS_PLL2_CFG2 - System_PLL Configuration 2 Register */
9604/*! @{ */
9605#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FILTER_RANGE_MASK (0x1U)
9606#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FILTER_RANGE_SHIFT (0U)
9607/*! PLL_FILTER_RANGE
9608 * 0b0..25 to 35 MHz
9609 * 0b1..35 to 54 MHz
9610 */
9611#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FILTER_RANGE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG2_PLL_FILTER_RANGE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG2_PLL_FILTER_RANGE_MASK)
9612#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_MASK (0x7EU)
9613#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT (1U)
9614#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_MASK)
9615#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF2_MASK (0x1F80U)
9616#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF2_SHIFT (7U)
9617#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF2_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF2_MASK)
9618#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF1_MASK (0x7E000U)
9619#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF1_SHIFT (13U)
9620#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF1_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF1_MASK)
9621#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR2_MASK (0x1F80000U)
9622#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR2_SHIFT (19U)
9623#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR2_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR2_MASK)
9624#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR1_MASK (0xE000000U)
9625#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR1_SHIFT (25U)
9626#define CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR1_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR1_MASK)
9627/*! @} */
9628
9629/*! @name SYS_PLL3_CFG0 - System PLL Configuration 0 Register */
9630/*! @{ */
9631#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_REFCLK_SEL_MASK (0x3U)
9632#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_REFCLK_SEL_SHIFT (0U)
9633/*! PLL_REFCLK_SEL
9634 * 0b00..25M_REF_CLK
9635 * 0b01..27M_REF_CLK
9636 * 0b10..HDMI_PHY_27M_CLK
9637 * 0b11..CLK_P_N
9638 */
9639#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_REFCLK_SEL_MASK)
9640#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_COUNTCLK_SEL_MASK (0x4U)
9641#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_COUNTCLK_SEL_SHIFT (2U)
9642/*! PLL_COUNTCLK_SEL
9643 * 0b0..25M_REF_CLK
9644 * 0b1..27M_REF_CLK
9645 */
9646#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_COUNTCLK_SEL_MASK)
9647#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SEL_MASK (0x8U)
9648#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SEL_SHIFT (3U)
9649/*! PLL_LOCK_SEL
9650 * 0b0..Select PLL lock output
9651 * 0b1..Select maximum lock time counter output
9652 */
9653#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SEL_MASK)
9654#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2_MASK (0x10U)
9655#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2_SHIFT (4U)
9656#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2_MASK)
9657#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1_MASK (0x20U)
9658#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1_SHIFT (5U)
9659#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1_MASK)
9660#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_OVERRIDE_MASK (0x40U)
9661#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_OVERRIDE_SHIFT (6U)
9662#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_OVERRIDE_MASK)
9663#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_MASK (0x80U)
9664#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_SHIFT (7U)
9665#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_MASK)
9666#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_OVERRIDE_MASK (0x100U)
9667#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_OVERRIDE_SHIFT (8U)
9668#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_OVERRIDE_MASK)
9669#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_CLKE_MASK (0x200U)
9670#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_CLKE_SHIFT (9U)
9671#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_CLKE_MASK)
9672#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_OVERRIDE_MASK (0x400U)
9673#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_OVERRIDE_SHIFT (10U)
9674#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_OVERRIDE_MASK)
9675#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_CLKE_MASK (0x800U)
9676#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_CLKE_SHIFT (11U)
9677#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_CLKE_MASK)
9678#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_OVERRIDE_MASK (0x1000U)
9679#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_OVERRIDE_SHIFT (12U)
9680#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_OVERRIDE_MASK)
9681#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_CLKE_MASK (0x2000U)
9682#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_CLKE_SHIFT (13U)
9683#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_CLKE_MASK)
9684#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_OVERRIDE_MASK (0x4000U)
9685#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_OVERRIDE_SHIFT (14U)
9686#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_OVERRIDE_MASK)
9687#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_CLKE_MASK (0x8000U)
9688#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_CLKE_SHIFT (15U)
9689#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_CLKE_MASK)
9690#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_OVERRIDE_MASK (0x10000U)
9691#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_OVERRIDE_SHIFT (16U)
9692#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_OVERRIDE_MASK)
9693#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_CLKE_MASK (0x20000U)
9694#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_CLKE_SHIFT (17U)
9695#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_CLKE_MASK)
9696#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_OVERRIDE_MASK (0x40000U)
9697#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_OVERRIDE_SHIFT (18U)
9698#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_OVERRIDE_MASK)
9699#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_CLKE_MASK (0x80000U)
9700#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_CLKE_SHIFT (19U)
9701#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_CLKE_MASK)
9702#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_OVERRIDE_MASK (0x100000U)
9703#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_OVERRIDE_SHIFT (20U)
9704#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_OVERRIDE_MASK)
9705#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_CLKE_MASK (0x200000U)
9706#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_CLKE_SHIFT (21U)
9707#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_CLKE_MASK)
9708#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_OVERRIDE_MASK (0x400000U)
9709#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_OVERRIDE_SHIFT (22U)
9710#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_OVERRIDE_MASK)
9711#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_CLKE_MASK (0x800000U)
9712#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_CLKE_SHIFT (23U)
9713#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_CLKE_MASK)
9714#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_OVERRIDE_MASK (0x1000000U)
9715#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_OVERRIDE_SHIFT (24U)
9716#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_OVERRIDE_MASK)
9717#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_MASK (0x2000000U)
9718#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_SHIFT (25U)
9719#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_MASK)
9720#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_MASK (0x80000000U)
9721#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SHIFT (31U)
9722#define CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_MASK)
9723/*! @} */
9724
9725/*! @name SYS_PLL3_CFG1 - System_PLL Configuration 1 Register */
9726/*! @{ */
9727#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSE_MASK (0x1U)
9728#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSE_SHIFT (0U)
9729#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSE_MASK)
9730#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMF_MASK (0x1EU)
9731#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMF_SHIFT (1U)
9732#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMF_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMF_MASK)
9733#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMD_MASK (0xE0U)
9734#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMD_SHIFT (5U)
9735/*! PLL_SSMD
9736 * 0b000..0.25
9737 * 0b001..0.5
9738 * 0b010..0.75
9739 * 0b011..1.0
9740 * 0b100..1.5
9741 * 0b101..2.0
9742 * 0b110..3.0
9743 * 0b111..4.0
9744 */
9745#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMD_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMD_MASK)
9746#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSDS_MASK (0x100U)
9747#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSDS_SHIFT (8U)
9748/*! PLL_SSDS
9749 * 0b0..Center Spread
9750 * 0b1..Down Spread
9751 */
9752#define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSDS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSDS_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSDS_MASK)
9753/*! @} */
9754
9755/*! @name SYS_PLL3_CFG2 - System_PLL Configuration 2 Register */
9756/*! @{ */
9757#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FILTER_RANGE_MASK (0x1U)
9758#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FILTER_RANGE_SHIFT (0U)
9759/*! PLL_FILTER_RANGE
9760 * 0b0..25 to 35 MHz
9761 * 0b1..35 to 54 MHz
9762 */
9763#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FILTER_RANGE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG2_PLL_FILTER_RANGE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG2_PLL_FILTER_RANGE_MASK)
9764#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_OUTPUT_DIV_VAL_MASK (0x7EU)
9765#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT (1U)
9766#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG2_PLL_OUTPUT_DIV_VAL_MASK)
9767#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF2_MASK (0x1F80U)
9768#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF2_SHIFT (7U)
9769#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF2_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF2_MASK)
9770#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF1_MASK (0x7E000U)
9771#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF1_SHIFT (13U)
9772#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF1_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF1_MASK)
9773#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR2_MASK (0x1F80000U)
9774#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR2_SHIFT (19U)
9775#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR2_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR2_MASK)
9776#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR1_MASK (0xE000000U)
9777#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR1_SHIFT (25U)
9778#define CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR1_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR1_MASK)
9779/*! @} */
9780
9781/*! @name VIDEO_PLL2_CFG0 - VIDEO PLL2 Configuration 0 Register */
9782/*! @{ */
9783#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_REFCLK_SEL_MASK (0x3U)
9784#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_REFCLK_SEL_SHIFT (0U)
9785/*! PLL_REFCLK_SEL
9786 * 0b00..25M_REF_CLK
9787 * 0b01..27M_REF_CLK
9788 * 0b10..HDMI_PHY_27M_CLK
9789 * 0b11..CLK_P_N
9790 */
9791#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_REFCLK_SEL_MASK)
9792#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_COUNTCLK_SEL_MASK (0x4U)
9793#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_COUNTCLK_SEL_SHIFT (2U)
9794/*! PLL_COUNTCLK_SEL
9795 * 0b0..25M_REF_CLK
9796 * 0b1..27M_REF_CLK
9797 */
9798#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_COUNTCLK_SEL_MASK)
9799#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SEL_MASK (0x8U)
9800#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SEL_SHIFT (3U)
9801/*! PLL_LOCK_SEL
9802 * 0b0..Select PLL lock output
9803 * 0b1..Select maximum lock time counter output
9804 */
9805#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SEL_MASK)
9806#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2_MASK (0x10U)
9807#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2_SHIFT (4U)
9808#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2_MASK)
9809#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1_MASK (0x20U)
9810#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1_SHIFT (5U)
9811#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1_MASK)
9812#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_OVERRIDE_MASK (0x40U)
9813#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_OVERRIDE_SHIFT (6U)
9814#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_OVERRIDE_MASK)
9815#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_MASK (0x80U)
9816#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_SHIFT (7U)
9817#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_MASK)
9818#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100U)
9819#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_OVERRIDE_SHIFT (8U)
9820#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_OVERRIDE_MASK)
9821#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_MASK (0x200U)
9822#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_SHIFT (9U)
9823#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_MASK)
9824#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_MASK (0x80000000U)
9825#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SHIFT (31U)
9826#define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_MASK)
9827/*! @} */
9828
9829/*! @name VIDEO_PLL2_CFG1 - VIDEO PLL2 Configuration 1 Register */
9830/*! @{ */
9831#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSE_MASK (0x1U)
9832#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSE_SHIFT (0U)
9833#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSE_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSE_MASK)
9834#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMF_MASK (0x1EU)
9835#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMF_SHIFT (1U)
9836#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMF_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMF_MASK)
9837#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMD_MASK (0xE0U)
9838#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMD_SHIFT (5U)
9839/*! PLL_SSMD
9840 * 0b000..0.25
9841 * 0b001..0.5
9842 * 0b010..0.75
9843 * 0b011..1.0
9844 * 0b100..1.5
9845 * 0b101..2.0
9846 * 0b110..3.0
9847 * 0b111..4.0
9848 */
9849#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMD_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMD_MASK)
9850#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSDS_MASK (0x100U)
9851#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSDS_SHIFT (8U)
9852/*! PLL_SSDS
9853 * 0b0..Center Spread
9854 * 0b1..Down Spread
9855 */
9856#define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSDS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSDS_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSDS_MASK)
9857/*! @} */
9858
9859/*! @name VIDEO_PLL2_CFG2 - VIDEO PLL2 Configuration 2 Register */
9860/*! @{ */
9861#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FILTER_RANGE_MASK (0x1U)
9862#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FILTER_RANGE_SHIFT (0U)
9863/*! PLL_FILTER_RANGE
9864 * 0b0..25 to 35 MHz
9865 * 0b1..35 to 54 MHz
9866 */
9867#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FILTER_RANGE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FILTER_RANGE_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FILTER_RANGE_MASK)
9868#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_MASK (0x7EU)
9869#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT (1U)
9870#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_MASK)
9871#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF2_MASK (0x1F80U)
9872#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF2_SHIFT (7U)
9873#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF2_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF2_MASK)
9874#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF1_MASK (0x7E000U)
9875#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF1_SHIFT (13U)
9876#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF1_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF1_MASK)
9877#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR2_MASK (0x1F80000U)
9878#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR2_SHIFT (19U)
9879#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR2_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR2_MASK)
9880#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR1_MASK (0xE000000U)
9881#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR1_SHIFT (25U)
9882#define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR1_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR1_MASK)
9883/*! @} */
9884
9885/*! @name DRAM_PLL_CFG0 - DRAM PLL Configuration 0 Register */
9886/*! @{ */
9887#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_REFCLK_SEL_MASK (0x3U)
9888#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_REFCLK_SEL_SHIFT (0U)
9889/*! PLL_REFCLK_SEL
9890 * 0b00..25M_REF_CLK
9891 * 0b01..27M_REF_CLK
9892 * 0b10..HDMI_PHY_27M_CLK
9893 * 0b11..CLK_P_N
9894 */
9895#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_REFCLK_SEL_MASK)
9896#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_COUNTCLK_SEL_MASK (0x4U)
9897#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT (2U)
9898/*! PLL_COUNTCLK_SEL
9899 * 0b0..25M_REF_CLK
9900 * 0b1..27M_REF_CLK
9901 */
9902#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_COUNTCLK_SEL_MASK)
9903#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SEL_MASK (0x8U)
9904#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SEL_SHIFT (3U)
9905/*! PLL_LOCK_SEL
9906 * 0b0..Select PLL lock output
9907 * 0b1..Select maximum lock time counter output
9908 */
9909#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SEL_MASK)
9910#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2_MASK (0x10U)
9911#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2_SHIFT (4U)
9912#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2_MASK)
9913#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1_MASK (0x20U)
9914#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1_SHIFT (5U)
9915#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1_MASK)
9916#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_OVERRIDE_MASK (0x40U)
9917#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT (6U)
9918#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_OVERRIDE_MASK)
9919#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_MASK (0x80U)
9920#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_SHIFT (7U)
9921#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_MASK)
9922#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100U)
9923#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT (8U)
9924#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK)
9925#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_MASK (0x200U)
9926#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_SHIFT (9U)
9927#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_MASK)
9928#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_MASK (0x80000000U)
9929#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SHIFT (31U)
9930#define CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_MASK)
9931/*! @} */
9932
9933/*! @name DRAM_PLL_CFG1 - DRAM PLL Configuration 1 Register */
9934/*! @{ */
9935#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSE_MASK (0x1U)
9936#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSE_SHIFT (0U)
9937#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSE_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSE_MASK)
9938#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMF_MASK (0x1EU)
9939#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMF_SHIFT (1U)
9940#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMF_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMF_MASK)
9941#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMD_MASK (0xE0U)
9942#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMD_SHIFT (5U)
9943/*! PLL_SSMD
9944 * 0b000..0.25
9945 * 0b001..0.5
9946 * 0b010..0.75
9947 * 0b011..1.0
9948 * 0b100..1.5
9949 * 0b101..2.0
9950 * 0b110..3.0
9951 * 0b111..4.0
9952 */
9953#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMD_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMD_MASK)
9954#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSDS_MASK (0x100U)
9955#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSDS_SHIFT (8U)
9956/*! PLL_SSDS
9957 * 0b0..Center Spread
9958 * 0b1..Down Spread
9959 */
9960#define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSDS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSDS_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSDS_MASK)
9961/*! @} */
9962
9963/*! @name DRAM_PLL_CFG2 - DRAM PLL Configuration 2 Register */
9964/*! @{ */
9965#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FILTER_RANGE_MASK (0x1U)
9966#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FILTER_RANGE_SHIFT (0U)
9967/*! PLL_FILTER_RANGE
9968 * 0b0..25 to 35 MHz
9969 * 0b1..35 to 54 MHz
9970 */
9971#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FILTER_RANGE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG2_PLL_FILTER_RANGE_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG2_PLL_FILTER_RANGE_MASK)
9972#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_OUTPUT_DIV_VAL_MASK (0x7EU)
9973#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT (1U)
9974#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG2_PLL_OUTPUT_DIV_VAL_MASK)
9975#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF2_MASK (0x1F80U)
9976#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF2_SHIFT (7U)
9977#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF2_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF2_MASK)
9978#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF1_MASK (0x7E000U)
9979#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF1_SHIFT (13U)
9980#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF1_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF1_MASK)
9981#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR2_MASK (0x1F80000U)
9982#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR2_SHIFT (19U)
9983#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR2_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR2_MASK)
9984#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR1_MASK (0xE000000U)
9985#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR1_SHIFT (25U)
9986#define CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR1_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR1_MASK)
9987/*! @} */
9988
9989/*! @name DIGPROG - DIGPROG Register */
9990/*! @{ */
9991#define CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK (0xFFU)
9992#define CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT (0U)
9993#define CCM_ANALOG_DIGPROG_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK)
9994#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK (0xFF00U)
9995#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT (8U)
9996#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK)
9997#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U)
9998#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT (16U)
9999#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK)
10000/*! @} */
10001
10002/*! @name OSC_MISC_CFG - Osc Misc Configuration Register */
10003/*! @{ */
10004#define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK (0x1U)
10005#define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT (0U)
10006/*! OSC_32K_SEL
10007 * 0b0..25M_REF_CLK_DIV800
10008 * 0b1..RTC
10009 */
10010#define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK)
10011#define CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_OVERRIDE_MASK (0x2U)
10012#define CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_OVERRIDE_SHIFT (1U)
10013#define CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_OVERRIDE_MASK)
10014#define CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_MASK (0x4U)
10015#define CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_SHIFT (2U)
10016#define CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_MASK)
10017#define CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_OVERRIDE_MASK (0x8U)
10018#define CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_OVERRIDE_SHIFT (3U)
10019#define CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_OVERRIDE_MASK)
10020#define CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_MASK (0x10U)
10021#define CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_SHIFT (4U)
10022#define CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_MASK)
10023/*! @} */
10024
10025/*! @name PLLOUT_MONITOR_CFG - PLLOUT Monitor Configuration Register */
10026/*! @{ */
10027#define CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CLK_SEL_MASK (0xFU)
10028#define CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CLK_SEL_SHIFT (0U)
10029#define CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CLK_SEL_SHIFT)) & CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CLK_SEL_MASK)
10030#define CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CKE_MASK (0x10U)
10031#define CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CKE_SHIFT (4U)
10032#define CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CKE_SHIFT)) & CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CKE_MASK)
10033/*! @} */
10034
10035/*! @name FRAC_PLLOUT_DIV_CFG - Fractional PLLOUT Divider Configuration Register */
10036/*! @{ */
10037#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL1_DIV_VAL_MASK (0x7U)
10038#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL1_DIV_VAL_SHIFT (0U)
10039/*! AUDIO_PLL1_DIV_VAL
10040 * 0b000..Divide by 1
10041 * 0b001..Divide by 2
10042 * 0b010..Divide by 3
10043 * 0b011..Divide by 4
10044 * 0b100..Divide by 5
10045 * 0b101..Divide by 6
10046 * 0b110..Divide by 7
10047 * 0b111..Divide by 8
10048 */
10049#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL1_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL1_DIV_VAL_SHIFT)) & CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL1_DIV_VAL_MASK)
10050#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL2_DIV_VAL_MASK (0x70U)
10051#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL2_DIV_VAL_SHIFT (4U)
10052/*! AUDIO_PLL2_DIV_VAL
10053 * 0b000..Divide by 1
10054 * 0b001..Divide by 2
10055 * 0b010..Divide by 3
10056 * 0b011..Divide by 4
10057 * 0b100..Divide by 5
10058 * 0b101..Divide by 6
10059 * 0b110..Divide by 7
10060 * 0b111..Divide by 8
10061 */
10062#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL2_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL2_DIV_VAL_SHIFT)) & CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL2_DIV_VAL_MASK)
10063#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VIDEO_PLL1_DIV_VAL_MASK (0x700U)
10064#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VIDEO_PLL1_DIV_VAL_SHIFT (8U)
10065/*! VIDEO_PLL1_DIV_VAL
10066 * 0b000..Divide by 1
10067 * 0b001..Divide by 2
10068 * 0b010..Divide by 3
10069 * 0b011..Divide by 4
10070 * 0b100..Divide by 5
10071 * 0b101..Divide by 6
10072 * 0b110..Divide by 7
10073 * 0b111..Divide by 8
10074 */
10075#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VIDEO_PLL1_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VIDEO_PLL1_DIV_VAL_SHIFT)) & CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VIDEO_PLL1_DIV_VAL_MASK)
10076#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_GPU_PLL_DIV_VAL_MASK (0x7000U)
10077#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_GPU_PLL_DIV_VAL_SHIFT (12U)
10078/*! GPU_PLL_DIV_VAL
10079 * 0b000..Divide by 1
10080 * 0b001..Divide by 2
10081 * 0b010..Divide by 3
10082 * 0b011..Divide by 4
10083 * 0b100..Divide by 5
10084 * 0b101..Divide by 6
10085 * 0b110..Divide by 7
10086 * 0b111..Divide by 8
10087 */
10088#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_GPU_PLL_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_GPU_PLL_DIV_VAL_SHIFT)) & CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_GPU_PLL_DIV_VAL_MASK)
10089#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VPU_PLL_DIV_VAL_MASK (0x70000U)
10090#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VPU_PLL_DIV_VAL_SHIFT (16U)
10091/*! VPU_PLL_DIV_VAL
10092 * 0b000..Divide by 1
10093 * 0b001..Divide by 2
10094 * 0b010..Divide by 3
10095 * 0b011..Divide by 4
10096 * 0b100..Divide by 5
10097 * 0b101..Divide by 6
10098 * 0b110..Divide by 7
10099 * 0b111..Divide by 8
10100 */
10101#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VPU_PLL_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VPU_PLL_DIV_VAL_SHIFT)) & CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VPU_PLL_DIV_VAL_MASK)
10102#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_ARM_PLL_DIV_VAL_MASK (0x700000U)
10103#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_ARM_PLL_DIV_VAL_SHIFT (20U)
10104/*! ARM_PLL_DIV_VAL
10105 * 0b000..Divide by 1
10106 * 0b001..Divide by 2
10107 * 0b010..Divide by 3
10108 * 0b011..Divide by 4
10109 * 0b100..Divide by 5
10110 * 0b101..Divide by 6
10111 * 0b110..Divide by 7
10112 * 0b111..Divide by 8
10113 */
10114#define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_ARM_PLL_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_ARM_PLL_DIV_VAL_SHIFT)) & CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_ARM_PLL_DIV_VAL_MASK)
10115/*! @} */
10116
10117/*! @name SCCG_PLLOUT_DIV_CFG - SCCG PLLOUT Divider Configuration Register */
10118/*! @{ */
10119#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL1_DIV_VAL_MASK (0x7U)
10120#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL1_DIV_VAL_SHIFT (0U)
10121/*! SYSTEM_PLL1_DIV_VAL
10122 * 0b000..Divide by 1
10123 * 0b001..Divide by 2
10124 * 0b010..Divide by 3
10125 * 0b011..Divide by 4
10126 * 0b100..Divide by 5
10127 * 0b101..Divide by 6
10128 * 0b110..Divide by 7
10129 * 0b111..Divide by 8
10130 */
10131#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL1_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL1_DIV_VAL_SHIFT)) & CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL1_DIV_VAL_MASK)
10132#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL2_DIV_VAL_MASK (0x70U)
10133#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL2_DIV_VAL_SHIFT (4U)
10134/*! SYSTEM_PLL2_DIV_VAL
10135 * 0b000..Divide by 1
10136 * 0b001..Divide by 2
10137 * 0b010..Divide by 3
10138 * 0b011..Divide by 4
10139 * 0b100..Divide by 5
10140 * 0b101..Divide by 6
10141 * 0b110..Divide by 7
10142 * 0b111..Divide by 8
10143 */
10144#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL2_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL2_DIV_VAL_SHIFT)) & CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL2_DIV_VAL_MASK)
10145#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL3_DIV_VAL_MASK (0x700U)
10146#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL3_DIV_VAL_SHIFT (8U)
10147/*! SYSTEM_PLL3_DIV_VAL
10148 * 0b000..Divide by 1
10149 * 0b001..Divide by 2
10150 * 0b010..Divide by 3
10151 * 0b011..Divide by 4
10152 * 0b100..Divide by 5
10153 * 0b101..Divide by 6
10154 * 0b110..Divide by 7
10155 * 0b111..Divide by 8
10156 */
10157#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL3_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL3_DIV_VAL_SHIFT)) & CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL3_DIV_VAL_MASK)
10158#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_DRAM_PLL_DIV_VAL_MASK (0x7000U)
10159#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_DRAM_PLL_DIV_VAL_SHIFT (12U)
10160/*! DRAM_PLL_DIV_VAL
10161 * 0b000..Divide by 1
10162 * 0b001..Divide by 2
10163 * 0b010..Divide by 3
10164 * 0b011..Divide by 4
10165 * 0b100..Divide by 5
10166 * 0b101..Divide by 6
10167 * 0b110..Divide by 7
10168 * 0b111..Divide by 8
10169 */
10170#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_DRAM_PLL_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_DRAM_PLL_DIV_VAL_SHIFT)) & CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_DRAM_PLL_DIV_VAL_MASK)
10171#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_VIDEO_PLL2_DIV_VAL_MASK (0x70000U)
10172#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_VIDEO_PLL2_DIV_VAL_SHIFT (16U)
10173/*! VIDEO_PLL2_DIV_VAL
10174 * 0b000..Divide by 1
10175 * 0b001..Divide by 2
10176 * 0b010..Divide by 3
10177 * 0b011..Divide by 4
10178 * 0b100..Divide by 5
10179 * 0b101..Divide by 6
10180 * 0b110..Divide by 7
10181 * 0b111..Divide by 8
10182 */
10183#define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_VIDEO_PLL2_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_VIDEO_PLL2_DIV_VAL_SHIFT)) & CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_VIDEO_PLL2_DIV_VAL_MASK)
10184/*! @} */
10185
10186
10187/*!
10188 * @}
10189 */ /* end of group CCM_ANALOG_Register_Masks */
10190
10191
10192/* CCM_ANALOG - Peripheral instance base addresses */
10193/** Peripheral CCM_ANALOG base address */
10194#define CCM_ANALOG_BASE (0x30360000u)
10195/** Peripheral CCM_ANALOG base pointer */
10196#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
10197/** Array initializer of CCM_ANALOG peripheral base addresses */
10198#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }
10199/** Array initializer of CCM_ANALOG peripheral base pointers */
10200#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG }
10201
10202/*!
10203 * @}
10204 */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */
10205
10206
10207/* ----------------------------------------------------------------------------
10208 -- CTX_LD Peripheral Access Layer
10209 ---------------------------------------------------------------------------- */
10210
10211/*!
10212 * @addtogroup CTX_LD_Peripheral_Access_Layer CTX_LD Peripheral Access Layer
10213 * @{
10214 */
10215
10216/** CTX_LD - Register Layout Typedef */
10217typedef struct {
10218 struct { /* offset: 0x0 */
10219 __IO uint32_t RW; /**< Control status register for Context Loader., offset: 0x0 */
10220 __IO uint32_t SET; /**< Control status register for Context Loader., offset: 0x4 */
10221 __IO uint32_t CLR; /**< Control status register for Context Loader., offset: 0x8 */
10222 __IO uint32_t TOG; /**< Control status register for Context Loader., offset: 0xC */
10223 } CTRL_STATUS;
10224 __IO uint32_t DB_BASE_ADDR; /**< DRAM addr for double buffered register fetch., offset: 0x10 */
10225 __IO uint32_t DB_COUNT; /**< Double buffer register count, offset: 0x14 */
10226 __IO uint32_t SB_BASE_ADDR; /**< DRAM addr for single buffered registers., offset: 0x18 */
10227 __IO uint32_t SB_COUNT; /**< Single buffer register count, offset: 0x1C */
10228 __I uint32_t AHB_ERR_ADDR; /**< AHB address with error response., offset: 0x20 */
10229} CTX_LD_Type;
10230
10231/* ----------------------------------------------------------------------------
10232 -- CTX_LD Register Masks
10233 ---------------------------------------------------------------------------- */
10234
10235/*!
10236 * @addtogroup CTX_LD_Register_Masks CTX_LD Register Masks
10237 * @{
10238 */
10239
10240/*! @name CTRL_STATUS - Control status register for Context Loader. */
10241/*! @{ */
10242#define CTX_LD_CTRL_STATUS_ENABLE_MASK (0x1U)
10243#define CTX_LD_CTRL_STATUS_ENABLE_SHIFT (0U)
10244#define CTX_LD_CTRL_STATUS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_ENABLE_SHIFT)) & CTX_LD_CTRL_STATUS_ENABLE_MASK)
10245#define CTX_LD_CTRL_STATUS_ARB_SEL_MASK (0x2U)
10246#define CTX_LD_CTRL_STATUS_ARB_SEL_SHIFT (1U)
10247#define CTX_LD_CTRL_STATUS_ARB_SEL(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_ARB_SEL_SHIFT)) & CTX_LD_CTRL_STATUS_ARB_SEL_MASK)
10248#define CTX_LD_CTRL_STATUS_RD_ERR_EN_MASK (0x4U)
10249#define CTX_LD_CTRL_STATUS_RD_ERR_EN_SHIFT (2U)
10250#define CTX_LD_CTRL_STATUS_RD_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_RD_ERR_EN_SHIFT)) & CTX_LD_CTRL_STATUS_RD_ERR_EN_MASK)
10251#define CTX_LD_CTRL_STATUS_DB_COMP_EN_MASK (0x8U)
10252#define CTX_LD_CTRL_STATUS_DB_COMP_EN_SHIFT (3U)
10253#define CTX_LD_CTRL_STATUS_DB_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_DB_COMP_EN_SHIFT)) & CTX_LD_CTRL_STATUS_DB_COMP_EN_MASK)
10254#define CTX_LD_CTRL_STATUS_SB_HP_COMP_EN_MASK (0x10U)
10255#define CTX_LD_CTRL_STATUS_SB_HP_COMP_EN_SHIFT (4U)
10256#define CTX_LD_CTRL_STATUS_SB_HP_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_SB_HP_COMP_EN_SHIFT)) & CTX_LD_CTRL_STATUS_SB_HP_COMP_EN_MASK)
10257#define CTX_LD_CTRL_STATUS_SB_LP_COMP_EN_MASK (0x20U)
10258#define CTX_LD_CTRL_STATUS_SB_LP_COMP_EN_SHIFT (5U)
10259#define CTX_LD_CTRL_STATUS_SB_LP_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_SB_LP_COMP_EN_SHIFT)) & CTX_LD_CTRL_STATUS_SB_LP_COMP_EN_MASK)
10260#define CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_EN_MASK (0x40U)
10261#define CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_EN_SHIFT (6U)
10262#define CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_EN_SHIFT)) & CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_EN_MASK)
10263#define CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_EN_MASK (0x80U)
10264#define CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_EN_SHIFT (7U)
10265#define CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_EN_SHIFT)) & CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_EN_MASK)
10266#define CTX_LD_CTRL_STATUS_AHB_ERR_EN_MASK (0x100U)
10267#define CTX_LD_CTRL_STATUS_AHB_ERR_EN_SHIFT (8U)
10268#define CTX_LD_CTRL_STATUS_AHB_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_AHB_ERR_EN_SHIFT)) & CTX_LD_CTRL_STATUS_AHB_ERR_EN_MASK)
10269#define CTX_LD_CTRL_STATUS_RD_ERR_MASK (0x10000U)
10270#define CTX_LD_CTRL_STATUS_RD_ERR_SHIFT (16U)
10271#define CTX_LD_CTRL_STATUS_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_RD_ERR_SHIFT)) & CTX_LD_CTRL_STATUS_RD_ERR_MASK)
10272#define CTX_LD_CTRL_STATUS_DB_COMP_MASK (0x20000U)
10273#define CTX_LD_CTRL_STATUS_DB_COMP_SHIFT (17U)
10274#define CTX_LD_CTRL_STATUS_DB_COMP(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_DB_COMP_SHIFT)) & CTX_LD_CTRL_STATUS_DB_COMP_MASK)
10275#define CTX_LD_CTRL_STATUS_SB_HP_COMP_MASK (0x40000U)
10276#define CTX_LD_CTRL_STATUS_SB_HP_COMP_SHIFT (18U)
10277#define CTX_LD_CTRL_STATUS_SB_HP_COMP(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_SB_HP_COMP_SHIFT)) & CTX_LD_CTRL_STATUS_SB_HP_COMP_MASK)
10278#define CTX_LD_CTRL_STATUS_SB_LP_COMP_MASK (0x80000U)
10279#define CTX_LD_CTRL_STATUS_SB_LP_COMP_SHIFT (19U)
10280#define CTX_LD_CTRL_STATUS_SB_LP_COMP(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_SB_LP_COMP_SHIFT)) & CTX_LD_CTRL_STATUS_SB_LP_COMP_MASK)
10281#define CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_MASK (0x100000U)
10282#define CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_SHIFT (20U)
10283#define CTX_LD_CTRL_STATUS_DB_PEND_SB_REC(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_SHIFT)) & CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_MASK)
10284#define CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_MASK (0x200000U)
10285#define CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_SHIFT (21U)
10286#define CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_SHIFT)) & CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_MASK)
10287#define CTX_LD_CTRL_STATUS_AHB_ERR_MASK (0x400000U)
10288#define CTX_LD_CTRL_STATUS_AHB_ERR_SHIFT (22U)
10289#define CTX_LD_CTRL_STATUS_AHB_ERR(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_AHB_ERR_SHIFT)) & CTX_LD_CTRL_STATUS_AHB_ERR_MASK)
10290/*! @} */
10291
10292/*! @name DB_BASE_ADDR - DRAM addr for double buffered register fetch. */
10293/*! @{ */
10294#define CTX_LD_DB_BASE_ADDR_DB_BASE_ADDR_MASK (0xFFFFFFFFU)
10295#define CTX_LD_DB_BASE_ADDR_DB_BASE_ADDR_SHIFT (0U)
10296#define CTX_LD_DB_BASE_ADDR_DB_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_DB_BASE_ADDR_DB_BASE_ADDR_SHIFT)) & CTX_LD_DB_BASE_ADDR_DB_BASE_ADDR_MASK)
10297/*! @} */
10298
10299/*! @name DB_COUNT - Double buffer register count */
10300/*! @{ */
10301#define CTX_LD_DB_COUNT_DB_COUNT_MASK (0xFFFFU)
10302#define CTX_LD_DB_COUNT_DB_COUNT_SHIFT (0U)
10303#define CTX_LD_DB_COUNT_DB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_DB_COUNT_DB_COUNT_SHIFT)) & CTX_LD_DB_COUNT_DB_COUNT_MASK)
10304/*! @} */
10305
10306/*! @name SB_BASE_ADDR - DRAM addr for single buffered registers. */
10307/*! @{ */
10308#define CTX_LD_SB_BASE_ADDR_SB_BASE_ADDR_MASK (0xFFFFFFFFU)
10309#define CTX_LD_SB_BASE_ADDR_SB_BASE_ADDR_SHIFT (0U)
10310#define CTX_LD_SB_BASE_ADDR_SB_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_SB_BASE_ADDR_SB_BASE_ADDR_SHIFT)) & CTX_LD_SB_BASE_ADDR_SB_BASE_ADDR_MASK)
10311/*! @} */
10312
10313/*! @name SB_COUNT - Single buffer register count */
10314/*! @{ */
10315#define CTX_LD_SB_COUNT_HP_COUNT_MASK (0xFFFFU)
10316#define CTX_LD_SB_COUNT_HP_COUNT_SHIFT (0U)
10317#define CTX_LD_SB_COUNT_HP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_SB_COUNT_HP_COUNT_SHIFT)) & CTX_LD_SB_COUNT_HP_COUNT_MASK)
10318#define CTX_LD_SB_COUNT_LP_COUNT_MASK (0xFFFF0000U)
10319#define CTX_LD_SB_COUNT_LP_COUNT_SHIFT (16U)
10320#define CTX_LD_SB_COUNT_LP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_SB_COUNT_LP_COUNT_SHIFT)) & CTX_LD_SB_COUNT_LP_COUNT_MASK)
10321/*! @} */
10322
10323/*! @name AHB_ERR_ADDR - AHB address with error response. */
10324/*! @{ */
10325#define CTX_LD_AHB_ERR_ADDR_AHB_ERR_ADDR_MASK (0xFFFFFFFFU)
10326#define CTX_LD_AHB_ERR_ADDR_AHB_ERR_ADDR_SHIFT (0U)
10327#define CTX_LD_AHB_ERR_ADDR_AHB_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_AHB_ERR_ADDR_AHB_ERR_ADDR_SHIFT)) & CTX_LD_AHB_ERR_ADDR_AHB_ERR_ADDR_MASK)
10328/*! @} */
10329
10330
10331/*!
10332 * @}
10333 */ /* end of group CTX_LD_Register_Masks */
10334
10335
10336/* CTX_LD - Peripheral instance base addresses */
10337/** Peripheral DCSS__CTX_LD base address */
10338#define DCSS__CTX_LD_BASE (0x32E23000u)
10339/** Peripheral DCSS__CTX_LD base pointer */
10340#define DCSS__CTX_LD ((CTX_LD_Type *)DCSS__CTX_LD_BASE)
10341/** Array initializer of CTX_LD peripheral base addresses */
10342#define CTX_LD_BASE_ADDRS { DCSS__CTX_LD_BASE }
10343/** Array initializer of CTX_LD peripheral base pointers */
10344#define CTX_LD_BASE_PTRS { DCSS__CTX_LD }
10345
10346/*!
10347 * @}
10348 */ /* end of group CTX_LD_Peripheral_Access_Layer */
10349
10350
10351/* ----------------------------------------------------------------------------
10352 -- DDRC_REGS Peripheral Access Layer
10353 ---------------------------------------------------------------------------- */
10354
10355/*!
10356 * @addtogroup DDRC_REGS_Peripheral_Access_Layer DDRC_REGS Peripheral Access Layer
10357 * @{
10358 */
10359
10360/** DDRC_REGS - Register Layout Typedef */
10361typedef struct {
10362 __IO uint32_t MSTR; /**< Master Register0, offset: 0x0 */
10363 __I uint32_t STAT; /**< Operating Mode Status Register, offset: 0x4 */
10364 uint8_t RESERVED_0[8];
10365 __IO uint32_t MRCTRL0; /**< Mode Register Read/Write Control Register 0., offset: 0x10 */
10366 __IO uint32_t MRCTRL1; /**< Mode Register Read/Write Control Register 1, offset: 0x14 */
10367 __I uint32_t MRSTAT; /**< Mode Register Read/Write Status Register, offset: 0x18 */
10368 __IO uint32_t MRCTRL2; /**< Mode Register Read/Write Control Register 2, offset: 0x1C */
10369 __IO uint32_t DERATEEN; /**< Temperature Derate Enable Register, offset: 0x20 */
10370 __IO uint32_t DERATEINT; /**< Temperature Derate Interval Register, offset: 0x24 */
10371 uint8_t RESERVED_1[8];
10372 __IO uint32_t PWRCTL; /**< Low Power Control Register, offset: 0x30 */
10373 __IO uint32_t PWRTMG; /**< Low Power Timing Register, offset: 0x34 */
10374 __IO uint32_t HWLPCTL; /**< Hardware Low Power Control Register, offset: 0x38 */
10375 uint8_t RESERVED_2[20];
10376 __IO uint32_t RFSHCTL0; /**< Refresh Control Register 0, offset: 0x50 */
10377 __IO uint32_t RFSHCTL1; /**< Refresh Control Register 1, offset: 0x54 */
10378 uint8_t RESERVED_3[8];
10379 __IO uint32_t RFSHCTL3; /**< Refresh Control Register 3, offset: 0x60 */
10380 __IO uint32_t RFSHTMG; /**< Refresh Timing Register, offset: 0x64 */
10381 uint8_t RESERVED_4[88];
10382 __IO uint32_t CRCPARCTL0; /**< CRC Parity Control Register0, offset: 0xC0 */
10383 __IO uint32_t CRCPARCTL1; /**< CRC Parity Control Register1, offset: 0xC4 */
10384 uint8_t RESERVED_5[4];
10385 __I uint32_t CRCPARSTAT; /**< CRC Parity Status Register, offset: 0xCC */
10386 __IO uint32_t INIT0; /**< SDRAM Initialization Register 0, offset: 0xD0 */
10387 __IO uint32_t INIT1; /**< SDRAM Initialization Register 1, offset: 0xD4 */
10388 __IO uint32_t INIT2; /**< SDRAM Initialization Register 2, offset: 0xD8 */
10389 __IO uint32_t INIT3; /**< SDRAM Initialization Register 3, offset: 0xDC */
10390 __IO uint32_t INIT4; /**< SDRAM Initialization Register 4, offset: 0xE0 */
10391 __IO uint32_t INIT5; /**< SDRAM Initialization Register 5, offset: 0xE4 */
10392 __IO uint32_t INIT6; /**< SDRAM Initialization Register 6, offset: 0xE8 */
10393 __IO uint32_t INIT7; /**< SDRAM Initialization Register 7, offset: 0xEC */
10394 __IO uint32_t DIMMCTL; /**< DIMM Control Register, offset: 0xF0 */
10395 __IO uint32_t RANKCTL; /**< Rank Control Register, offset: 0xF4 */
10396 uint8_t RESERVED_6[8];
10397 __IO uint32_t DRAMTMG0; /**< SDRAM Timing Register 0, offset: 0x100 */
10398 __IO uint32_t DRAMTMG1; /**< SDRAM Timing Register 1, offset: 0x104 */
10399 __IO uint32_t DRAMTMG2; /**< SDRAM Timing Register 2, offset: 0x108 */
10400 __IO uint32_t DRAMTMG3; /**< SDRAM Timing Register 3, offset: 0x10C */
10401 __IO uint32_t DRAMTMG4; /**< SDRAM Timing Register 4, offset: 0x110 */
10402 __IO uint32_t DRAMTMG5; /**< SDRAM Timing Register 5, offset: 0x114 */
10403 __IO uint32_t DRAMTMG6; /**< SDRAM Timing Register 6, offset: 0x118 */
10404 __IO uint32_t DRAMTMG7; /**< SDRAM Timing Register 7, offset: 0x11C */
10405 __IO uint32_t DRAMTMG8; /**< SDRAM Timing Register 8, offset: 0x120 */
10406 __IO uint32_t DRAMTMG9; /**< SDRAM Timing Register 9, offset: 0x124 */
10407 __IO uint32_t DRAMTMG10; /**< SDRAM Timing Register 10, offset: 0x128 */
10408 __IO uint32_t DRAMTMG11; /**< SDRAM Timing Register 11, offset: 0x12C */
10409 __IO uint32_t DRAMTMG12; /**< SDRAM Timing Register 12, offset: 0x130 */
10410 __IO uint32_t DRAMTMG13; /**< SDRAM Timing Register 13, offset: 0x134 */
10411 __IO uint32_t DRAMTMG14; /**< SDRAM Timing Register 14, offset: 0x138 */
10412 __IO uint32_t DRAMTMG15; /**< SDRAM Timing Register 15, offset: 0x13C */
10413 uint8_t RESERVED_7[64];
10414 __IO uint32_t ZQCTL0; /**< ZQ Control Register 0, offset: 0x180 */
10415 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */
10416 __IO uint32_t ZQCTL2; /**< ZQ Control Register 2, offset: 0x188 */
10417 __I uint32_t ZQSTAT; /**< ZQ Status Register, offset: 0x18C */
10418 __IO uint32_t DFITMG0; /**< DFI Timing Register 0, offset: 0x190 */
10419 __IO uint32_t DFITMG1; /**< DFI Timing Register 1, offset: 0x194 */
10420 __IO uint32_t DFILPCFG0; /**< DFI Low Power Configuration Register 0, offset: 0x198 */
10421 __IO uint32_t DFILPCFG1; /**< DFI Low Power Configuration Register 1, offset: 0x19C */
10422 __IO uint32_t DFIUPD0; /**< DFI Update Register 0, offset: 0x1A0 */
10423 __IO uint32_t DFIUPD1; /**< DFI Update Register 1, offset: 0x1A4 */
10424 __IO uint32_t DFIUPD2; /**< DFI Update Register 2, offset: 0x1A8 */
10425 uint8_t RESERVED_8[4];
10426 __IO uint32_t DFIMISC; /**< DFI Miscellaneous Control Register, offset: 0x1B0 */
10427 __IO uint32_t DFITMG2; /**< DFI Timing Register 2, offset: 0x1B4 */
10428 __IO uint32_t DFITMG3; /**< DFI Timing Register 3, offset: 0x1B8 */
10429 __I uint32_t DFISTAT; /**< DFI Status Register, offset: 0x1BC */
10430 __IO uint32_t DBICTL; /**< DM/DBI Control Register, offset: 0x1C0 */
10431 uint8_t RESERVED_9[60];
10432 __IO uint32_t ADDRMAP0; /**< Address Map Register 0, offset: 0x200 */
10433 __IO uint32_t ADDRMAP1; /**< Address Map Register 1, offset: 0x204 */
10434 __IO uint32_t ADDRMAP2; /**< Address Map Register 2, offset: 0x208 */
10435 __IO uint32_t ADDRMAP3; /**< Address Map Register 3, offset: 0x20C */
10436 __IO uint32_t ADDRMAP4; /**< Address Map Register 4, offset: 0x210 */
10437 __IO uint32_t ADDRMAP5; /**< Address Map Register 5, offset: 0x214 */
10438 __IO uint32_t ADDRMAP6; /**< Address Map Register 6, offset: 0x218 */
10439 __IO uint32_t ADDRMAP7; /**< Address Map Register 7, offset: 0x21C */
10440 __IO uint32_t ADDRMAP8; /**< Address Map Register 8, offset: 0x220 */
10441 __IO uint32_t ADDRMAP9; /**< Address Map Register 9, offset: 0x224 */
10442 __IO uint32_t ADDRMAP10; /**< Address Map Register 10, offset: 0x228 */
10443 __IO uint32_t ADDRMAP11; /**< Address Map Register 11, offset: 0x22C */
10444 uint8_t RESERVED_10[16];
10445 __IO uint32_t ODTCFG; /**< ODT Configuration Register, offset: 0x240 */
10446 __IO uint32_t ODTMAP; /**< ODT/Rank Map Register, offset: 0x244 */
10447 uint8_t RESERVED_11[8];
10448 __IO uint32_t SCHED; /**< Scheduler Control Register, offset: 0x250 */
10449 __IO uint32_t SCHED1; /**< Scheduler Control Register 1, offset: 0x254 */
10450 uint8_t RESERVED_12[4];
10451 __IO uint32_t PERFHPR1; /**< High Priority Read CAM Register 1, offset: 0x25C */
10452 uint8_t RESERVED_13[4];
10453 __IO uint32_t PERFLPR1; /**< Low Priority Read CAM Register 1, offset: 0x264 */
10454 uint8_t RESERVED_14[4];
10455 __IO uint32_t PERFWR1; /**< Write CAM Register 1, offset: 0x26C */
10456 uint8_t RESERVED_15[144];
10457 __IO uint32_t DBG0; /**< Debug Register 0, offset: 0x300 */
10458 __IO uint32_t DBG1; /**< Debug Register 1, offset: 0x304 */
10459 __I uint32_t DBGCAM; /**< CAM Debug Register, offset: 0x308 */
10460 __IO uint32_t DBGCMD; /**< Command Debug Register, offset: 0x30C */
10461 __I uint32_t DBGSTAT; /**< Status Debug Register, offset: 0x310 */
10462 uint8_t RESERVED_16[12];
10463 __IO uint32_t SWCTL; /**< Software Register Programming Control Enable, offset: 0x320 */
10464 __I uint32_t SWSTAT; /**< Software Register Programming Control Status, offset: 0x324 */
10465 uint8_t RESERVED_17[68];
10466 __IO uint32_t POISONCFG; /**< AXI Poison Configuration Register., offset: 0x36C */
10467 __I uint32_t POISONSTAT; /**< AXI Poison Status Register, offset: 0x370 */
10468 uint8_t RESERVED_18[136];
10469 __I uint32_t PSTAT; /**< Port Status Register, offset: 0x3FC */
10470 __IO uint32_t PCCFG; /**< Port Common Configuration Register, offset: 0x400 */
10471 __IO uint32_t PCFGR_0; /**< Port n Configuration Read Register, offset: 0x404 */
10472 __IO uint32_t PCFGW_0; /**< Port n Configuration Write Register, offset: 0x408 */
10473 uint8_t RESERVED_19[132];
10474 __IO uint32_t PCTRL_0; /**< Port n Control Register, offset: 0x490 */
10475 __IO uint32_t PCFGQOS0_0; /**< Port n Read QoS Configuration Register 0, offset: 0x494 */
10476 __IO uint32_t PCFGQOS1_0; /**< Port n Read QoS Configuration Register 1, offset: 0x498 */
10477 __IO uint32_t PCFGWQOS0_0; /**< Port n Write QoS Configuration Register 0, offset: 0x49C */
10478 __IO uint32_t PCFGWQOS1_0; /**< Port n Write QoS Configuration Register 1, offset: 0x4A0 */
10479 uint8_t RESERVED_20[7036];
10480 __IO uint32_t DERATEEN_SHADOW; /**< [SHADOW] Temperature Derate Enable Register, offset: 0x2020 */
10481 __IO uint32_t DERATEINT_SHADOW; /**< [SHADOW] Temperature Derate Interval Register, offset: 0x2024 */
10482 uint8_t RESERVED_21[40];
10483 __IO uint32_t RFSHCTL0_SHADOW; /**< [SHADOW] Refresh Control Register 0, offset: 0x2050 */
10484 uint8_t RESERVED_22[16];
10485 __IO uint32_t RFSHTMG_SHADOW; /**< [SHADOW] Refresh Timing Register, offset: 0x2064 */
10486 uint8_t RESERVED_23[116];
10487 __IO uint32_t INIT3_SHADOW; /**< [SHADOW] SDRAM Initialization Register 3, offset: 0x20DC */
10488 __IO uint32_t INIT4_SHADOW; /**< [SHADOW] SDRAM Initialization Register 4, offset: 0x20E0 */
10489 uint8_t RESERVED_24[4];
10490 __IO uint32_t INIT6_SHADOW; /**< [SHADOW] SDRAM Initialization Register 6, offset: 0x20E8 */
10491 __IO uint32_t INIT7_SHADOW; /**< [SHADOW] SDRAM Initialization Register 7, offset: 0x20EC */
10492 uint8_t RESERVED_25[16];
10493 __IO uint32_t DRAMTMG0_SHADOW; /**< [SHADOW] SDRAM Timing Register 0, offset: 0x2100 */
10494 __IO uint32_t DRAMTMG1_SHADOW; /**< [SHADOW] SDRAM Timing Register 1, offset: 0x2104 */
10495 __IO uint32_t DRAMTMG2_SHADOW; /**< [SHADOW] SDRAM Timing Register 2, offset: 0x2108 */
10496 __IO uint32_t DRAMTMG3_SHADOW; /**< [SHADOW] SDRAM Timing Register 3, offset: 0x210C */
10497 __IO uint32_t DRAMTMG4_SHADOW; /**< [SHADOW] SDRAM Timing Register 4, offset: 0x2110 */
10498 __IO uint32_t DRAMTMG5_SHADOW; /**< [SHADOW] SDRAM Timing Register 5, offset: 0x2114 */
10499 __IO uint32_t DRAMTMG6_SHADOW; /**< [SHADOW] SDRAM Timing Register 6, offset: 0x2118 */
10500 __IO uint32_t DRAMTMG7_SHADOW; /**< [SHADOW] SDRAM Timing Register 7, offset: 0x211C */
10501 __IO uint32_t DRAMTMG8_SHADOW; /**< [SHADOW] SDRAM Timing Register 8, offset: 0x2120 */
10502 __IO uint32_t DRAMTMG9_SHADOW; /**< [SHADOW] SDRAM Timing Register 9, offset: 0x2124 */
10503 __IO uint32_t DRAMTMG10_SHADOW; /**< [SHADOW] SDRAM Timing Register 10, offset: 0x2128 */
10504 __IO uint32_t DRAMTMG11_SHADOW; /**< [SHADOW] SDRAM Timing Register 11, offset: 0x212C */
10505 __IO uint32_t DRAMTMG12_SHADOW; /**< [SHADOW] SDRAM Timing Register 12, offset: 0x2130 */
10506 __IO uint32_t DRAMTMG13_SHADOW; /**< [SHADOW] SDRAM Timing Register 13, offset: 0x2134 */
10507 __IO uint32_t DRAMTMG14_SHADOW; /**< [SHADOW] SDRAM Timing Register 14, offset: 0x2138 */
10508 __IO uint32_t DRAMTMG15_SHADOW; /**< [SHADOW] SDRAM Timing Register 15, offset: 0x213C */
10509 uint8_t RESERVED_26[64];
10510 __IO uint32_t ZQCTL0_SHADOW; /**< [SHADOW] ZQ Control Register 0, offset: 0x2180 */
10511 uint8_t RESERVED_27[12];
10512 __IO uint32_t DFITMG0_SHADOW; /**< [SHADOW] DFI Timing Register 0, offset: 0x2190 */
10513 __IO uint32_t DFITMG1_SHADOW; /**< [SHADOW] DFI Timing Register 1, offset: 0x2194 */
10514 uint8_t RESERVED_28[28];
10515 __IO uint32_t DFITMG2_SHADOW; /**< [SHADOW] DFI Timing Register 2, offset: 0x21B4 */
10516 __IO uint32_t DFITMG3_SHADOW; /**< [SHADOW] DFI Timing Register 3, offset: 0x21B8 */
10517 uint8_t RESERVED_29[132];
10518 __IO uint32_t ODTCFG_SHADOW; /**< [SHADOW] ODT Configuration Register, offset: 0x2240 */
10519} DDRC_REGS_Type;
10520
10521/* ----------------------------------------------------------------------------
10522 -- DDRC_REGS Register Masks
10523 ---------------------------------------------------------------------------- */
10524
10525/*!
10526 * @addtogroup DDRC_REGS_Register_Masks DDRC_REGS Register Masks
10527 * @{
10528 */
10529
10530/*! @name MSTR - Master Register0 */
10531/*! @{ */
10532#define DDRC_REGS_MSTR_ddr3_MASK (0x1U)
10533#define DDRC_REGS_MSTR_ddr3_SHIFT (0U)
10534#define DDRC_REGS_MSTR_ddr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_ddr3_SHIFT)) & DDRC_REGS_MSTR_ddr3_MASK)
10535#define DDRC_REGS_MSTR_lpddr2_MASK (0x4U)
10536#define DDRC_REGS_MSTR_lpddr2_SHIFT (2U)
10537#define DDRC_REGS_MSTR_lpddr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_lpddr2_SHIFT)) & DDRC_REGS_MSTR_lpddr2_MASK)
10538#define DDRC_REGS_MSTR_lpddr3_MASK (0x8U)
10539#define DDRC_REGS_MSTR_lpddr3_SHIFT (3U)
10540#define DDRC_REGS_MSTR_lpddr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_lpddr3_SHIFT)) & DDRC_REGS_MSTR_lpddr3_MASK)
10541#define DDRC_REGS_MSTR_ddr4_MASK (0x10U)
10542#define DDRC_REGS_MSTR_ddr4_SHIFT (4U)
10543#define DDRC_REGS_MSTR_ddr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_ddr4_SHIFT)) & DDRC_REGS_MSTR_ddr4_MASK)
10544#define DDRC_REGS_MSTR_lpddr4_MASK (0x20U)
10545#define DDRC_REGS_MSTR_lpddr4_SHIFT (5U)
10546#define DDRC_REGS_MSTR_lpddr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_lpddr4_SHIFT)) & DDRC_REGS_MSTR_lpddr4_MASK)
10547#define DDRC_REGS_MSTR_burstchop_MASK (0x200U)
10548#define DDRC_REGS_MSTR_burstchop_SHIFT (9U)
10549#define DDRC_REGS_MSTR_burstchop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_burstchop_SHIFT)) & DDRC_REGS_MSTR_burstchop_MASK)
10550#define DDRC_REGS_MSTR_en_2t_timing_mode_MASK (0x400U)
10551#define DDRC_REGS_MSTR_en_2t_timing_mode_SHIFT (10U)
10552#define DDRC_REGS_MSTR_en_2t_timing_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_en_2t_timing_mode_SHIFT)) & DDRC_REGS_MSTR_en_2t_timing_mode_MASK)
10553#define DDRC_REGS_MSTR_geardown_mode_MASK (0x800U)
10554#define DDRC_REGS_MSTR_geardown_mode_SHIFT (11U)
10555#define DDRC_REGS_MSTR_geardown_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_geardown_mode_SHIFT)) & DDRC_REGS_MSTR_geardown_mode_MASK)
10556#define DDRC_REGS_MSTR_data_bus_width_MASK (0x3000U)
10557#define DDRC_REGS_MSTR_data_bus_width_SHIFT (12U)
10558#define DDRC_REGS_MSTR_data_bus_width(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_data_bus_width_SHIFT)) & DDRC_REGS_MSTR_data_bus_width_MASK)
10559#define DDRC_REGS_MSTR_dll_off_mode_MASK (0x8000U)
10560#define DDRC_REGS_MSTR_dll_off_mode_SHIFT (15U)
10561#define DDRC_REGS_MSTR_dll_off_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_dll_off_mode_SHIFT)) & DDRC_REGS_MSTR_dll_off_mode_MASK)
10562#define DDRC_REGS_MSTR_burst_rdwr_MASK (0xF0000U)
10563#define DDRC_REGS_MSTR_burst_rdwr_SHIFT (16U)
10564/*! burst_rdwr - SDRAM burst length used
10565 * 0b0001..Burst length of 2 (only supported for mDDR)
10566 * 0b0010..Burst length of 4
10567 * 0b0100..Burst length of 8
10568 * 0b1000..Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4)
10569 */
10570#define DDRC_REGS_MSTR_burst_rdwr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_burst_rdwr_SHIFT)) & DDRC_REGS_MSTR_burst_rdwr_MASK)
10571#define DDRC_REGS_MSTR_frequency_ratio_MASK (0x400000U)
10572#define DDRC_REGS_MSTR_frequency_ratio_SHIFT (22U)
10573/*! frequency_ratio - Selects the Frequency Ratio
10574 * 0b0..1:2 Mode
10575 * 0b1..1:1 Mode
10576 */
10577#define DDRC_REGS_MSTR_frequency_ratio(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_frequency_ratio_SHIFT)) & DDRC_REGS_MSTR_frequency_ratio_MASK)
10578#define DDRC_REGS_MSTR_active_ranks_MASK (0x3000000U)
10579#define DDRC_REGS_MSTR_active_ranks_SHIFT (24U)
10580#define DDRC_REGS_MSTR_active_ranks(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_active_ranks_SHIFT)) & DDRC_REGS_MSTR_active_ranks_MASK)
10581#define DDRC_REGS_MSTR_frequency_mode_MASK (0x20000000U)
10582#define DDRC_REGS_MSTR_frequency_mode_SHIFT (29U)
10583/*! frequency_mode - Choose which registers are used.
10584 * 0b0..Original Registers
10585 * 0b1..Shadow Registers
10586 */
10587#define DDRC_REGS_MSTR_frequency_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_frequency_mode_SHIFT)) & DDRC_REGS_MSTR_frequency_mode_MASK)
10588#define DDRC_REGS_MSTR_device_config_MASK (0xC0000000U)
10589#define DDRC_REGS_MSTR_device_config_SHIFT (30U)
10590/*! device_config - Indicates the configuration of the device used in the system.
10591 * 0b00..x4 device
10592 * 0b01..x8 device
10593 * 0b10..x16 device
10594 * 0b11..x32 device
10595 */
10596#define DDRC_REGS_MSTR_device_config(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_device_config_SHIFT)) & DDRC_REGS_MSTR_device_config_MASK)
10597/*! @} */
10598
10599/*! @name STAT - Operating Mode Status Register */
10600/*! @{ */
10601#define DDRC_REGS_STAT_operating_mode_MASK (0x7U)
10602#define DDRC_REGS_STAT_operating_mode_SHIFT (0U)
10603#define DDRC_REGS_STAT_operating_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_STAT_operating_mode_SHIFT)) & DDRC_REGS_STAT_operating_mode_MASK)
10604#define DDRC_REGS_STAT_selfref_type_MASK (0x30U)
10605#define DDRC_REGS_STAT_selfref_type_SHIFT (4U)
10606/*! selfref_type - Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not.
10607 * 0b00..SDRAM is not in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still in parity error window or retry is in-progress.
10608 * 0b11..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was caused by Automatic Self Refresh only. If retry is enabled, this guarantees SRE command is executed correctly without parity error.
10609 * 0b10..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was not caused solely under Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software (reg_ddrc_selfref_sw). If retry is enabled, this guarantees SRE command is executed correctly without parity
10610 */
10611#define DDRC_REGS_STAT_selfref_type(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_STAT_selfref_type_SHIFT)) & DDRC_REGS_STAT_selfref_type_MASK)
10612#define DDRC_REGS_STAT_selfref_state_MASK (0x300U)
10613#define DDRC_REGS_STAT_selfref_state_SHIFT (8U)
10614/*! selfref_state - Self refresh state. This indicates self refresh or self refresh power down state for LPDDR4. This register is used for frequency change and MRR/MRW access during self refresh.
10615 * 0b00..SDRAM is not in Self Refresh.
10616 * 0b01..Self refresh 1
10617 * 0b10..Self refresh power down
10618 * 0b11..Self refresh
10619 */
10620#define DDRC_REGS_STAT_selfref_state(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_STAT_selfref_state_SHIFT)) & DDRC_REGS_STAT_selfref_state_MASK)
10621/*! @} */
10622
10623/*! @name MRCTRL0 - Mode Register Read/Write Control Register 0. */
10624/*! @{ */
10625#define DDRC_REGS_MRCTRL0_mr_type_MASK (0x1U)
10626#define DDRC_REGS_MRCTRL0_mr_type_SHIFT (0U)
10627/*! mr_type - Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4.
10628 * 0b0..Write
10629 * 0b1..Read
10630 */
10631#define DDRC_REGS_MRCTRL0_mr_type(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL0_mr_type_SHIFT)) & DDRC_REGS_MRCTRL0_mr_type_MASK)
10632#define DDRC_REGS_MRCTRL0_mpr_en_MASK (0x2U)
10633#define DDRC_REGS_MRCTRL0_mpr_en_SHIFT (1U)
10634/*! mpr_en - Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4).
10635 * 0b0..MRS
10636 * 0b1..WR/RD for MPR
10637 */
10638#define DDRC_REGS_MRCTRL0_mpr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL0_mpr_en_SHIFT)) & DDRC_REGS_MRCTRL0_mpr_en_MASK)
10639#define DDRC_REGS_MRCTRL0_pda_en_MASK (0x4U)
10640#define DDRC_REGS_MRCTRL0_pda_en_SHIFT (2U)
10641/*! pda_en - Indicates whether the mode register operation is MRS in PDA mode or not.Note that when pba_mode=1, PBA access is initiated instead of PDA access.
10642 * 0b0..MRS
10643 * 0b1..MRS in Per DRAM Addressability
10644 */
10645#define DDRC_REGS_MRCTRL0_pda_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL0_pda_en_SHIFT)) & DDRC_REGS_MRCTRL0_pda_en_MASK)
10646#define DDRC_REGS_MRCTRL0_sw_init_int_MASK (0x8U)
10647#define DDRC_REGS_MRCTRL0_sw_init_int_SHIFT (3U)
10648/*! sw_init_int - Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. For DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit can be used to program additional mode registers before automatic SDRAM initialization if necessary. In LPDDR4 independent channel mode, note that this must be programmed to both channels beforehand. Note that this must be cleared to 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start.
10649 * 0b0..Software intervention is not allowed
10650 * 0b1..Software intervention is allowed
10651 */
10652#define DDRC_REGS_MRCTRL0_sw_init_int(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL0_sw_init_int_SHIFT)) & DDRC_REGS_MRCTRL0_sw_init_int_MASK)
10653#define DDRC_REGS_MRCTRL0_mr_rank_MASK (0x30U)
10654#define DDRC_REGS_MRCTRL0_mr_rank_SHIFT (4U)
10655#define DDRC_REGS_MRCTRL0_mr_rank(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL0_mr_rank_SHIFT)) & DDRC_REGS_MRCTRL0_mr_rank_MASK)
10656#define DDRC_REGS_MRCTRL0_mr_addr_MASK (0xF000U)
10657#define DDRC_REGS_MRCTRL0_mr_addr_SHIFT (12U)
10658/*! mr_addr - Address of the mode register that is to be written to.
10659 * 0b0000..MR0
10660 * 0b0001..MR1
10661 * 0b0010..MR2
10662 * 0b0011..MR3
10663 * 0b0100..MR4
10664 * 0b0101..MR5
10665 * 0b0110..MR6
10666 * 0b0111..MR7
10667 */
10668#define DDRC_REGS_MRCTRL0_mr_addr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL0_mr_addr_SHIFT)) & DDRC_REGS_MRCTRL0_mr_addr_MASK)
10669#define DDRC_REGS_MRCTRL0_pba_mode_MASK (0x40000000U)
10670#define DDRC_REGS_MRCTRL0_pba_mode_SHIFT (30U)
10671#define DDRC_REGS_MRCTRL0_pba_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL0_pba_mode_SHIFT)) & DDRC_REGS_MRCTRL0_pba_mode_MASK)
10672#define DDRC_REGS_MRCTRL0_mr_wr_MASK (0x80000000U)
10673#define DDRC_REGS_MRCTRL0_mr_wr_SHIFT (31U)
10674#define DDRC_REGS_MRCTRL0_mr_wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL0_mr_wr_SHIFT)) & DDRC_REGS_MRCTRL0_mr_wr_MASK)
10675/*! @} */
10676
10677/*! @name MRCTRL1 - Mode Register Read/Write Control Register 1 */
10678/*! @{ */
10679#define DDRC_REGS_MRCTRL1_mr_data_MASK (0x3FFFFU)
10680#define DDRC_REGS_MRCTRL1_mr_data_SHIFT (0U)
10681#define DDRC_REGS_MRCTRL1_mr_data(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL1_mr_data_SHIFT)) & DDRC_REGS_MRCTRL1_mr_data_MASK)
10682/*! @} */
10683
10684/*! @name MRSTAT - Mode Register Read/Write Status Register */
10685/*! @{ */
10686#define DDRC_REGS_MRSTAT_mr_wr_busy_MASK (0x1U)
10687#define DDRC_REGS_MRSTAT_mr_wr_busy_SHIFT (0U)
10688/*! mr_wr_busy - The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRC accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when 'MRSTAT.mr_wr_busy' is high.
10689 * 0b0..Indicates that the SoC core can initiate a mode register write operation
10690 * 0b1..Indicates that mode register write operation is in progress
10691 */
10692#define DDRC_REGS_MRSTAT_mr_wr_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRSTAT_mr_wr_busy_SHIFT)) & DDRC_REGS_MRSTAT_mr_wr_busy_MASK)
10693#define DDRC_REGS_MRSTAT_pda_done_MASK (0x100U)
10694#define DDRC_REGS_MRSTAT_pda_done_SHIFT (8U)
10695/*! pda_done - The SoC core may initiate a MR write operation in PDA/PBA mode only if this signal is low. This signal goes high when three consecutive MRS commands related to the PDA/PBA mode are issued to the SDRAM. This signal goes low when MRCTRL0.pda_en becomes 0. Therefore, it is recommended to write MRCTRL0.pda_en to 0 after this signal goes high in order to prepare to perform PDA operation next time
10696 * 0b0..Indicates that mode register write operation related to PDA/PBA is in progress or has not started yet.
10697 * 0b1..Indicates that mode register write operation related to PDA/PBA has competed.
10698 */
10699#define DDRC_REGS_MRSTAT_pda_done(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRSTAT_pda_done_SHIFT)) & DDRC_REGS_MRSTAT_pda_done_MASK)
10700/*! @} */
10701
10702/*! @name MRCTRL2 - Mode Register Read/Write Control Register 2 */
10703/*! @{ */
10704#define DDRC_REGS_MRCTRL2_mr_device_sel_MASK (0xFFFFFFFFU)
10705#define DDRC_REGS_MRCTRL2_mr_device_sel_SHIFT (0U)
10706#define DDRC_REGS_MRCTRL2_mr_device_sel(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL2_mr_device_sel_SHIFT)) & DDRC_REGS_MRCTRL2_mr_device_sel_MASK)
10707/*! @} */
10708
10709/*! @name DERATEEN - Temperature Derate Enable Register */
10710/*! @{ */
10711#define DDRC_REGS_DERATEEN_derate_enable_MASK (0x1U)
10712#define DDRC_REGS_DERATEEN_derate_enable_SHIFT (0U)
10713/*! derate_enable - Enables derating. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
10714 * 0b0..Timing parameter derating is disabled
10715 * 0b1..Timing parameter derating is enabled using MR4 read value.
10716 */
10717#define DDRC_REGS_DERATEEN_derate_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEEN_derate_enable_SHIFT)) & DDRC_REGS_DERATEEN_derate_enable_MASK)
10718#define DDRC_REGS_DERATEEN_derate_value_MASK (0x2U)
10719#define DDRC_REGS_DERATEEN_derate_value_SHIFT (1U)
10720/*! derate_value - Derate value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this register field should be set to 1; otherwise it should be set to 0.
10721 * 0b0..Derating uses +1
10722 * 0b1..Derating uses +2
10723 */
10724#define DDRC_REGS_DERATEEN_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEEN_derate_value_SHIFT)) & DDRC_REGS_DERATEEN_derate_value_MASK)
10725#define DDRC_REGS_DERATEEN_derate_byte_MASK (0xF0U)
10726#define DDRC_REGS_DERATEEN_derate_byte_SHIFT (4U)
10727#define DDRC_REGS_DERATEEN_derate_byte(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEEN_derate_byte_SHIFT)) & DDRC_REGS_DERATEEN_derate_byte_MASK)
10728#define DDRC_REGS_DERATEEN_rc_derate_value_MASK (0x300U)
10729#define DDRC_REGS_DERATEEN_rc_derate_value_SHIFT (8U)
10730/*! rc_derate_value - Derate value of tRC for LPDDR4. Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.
10731 * 0b00..Derating uses +1
10732 * 0b01..Derating uses +2
10733 * 0b10..Derating uses +3
10734 * 0b11..Derating uses +4
10735 */
10736#define DDRC_REGS_DERATEEN_rc_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEEN_rc_derate_value_SHIFT)) & DDRC_REGS_DERATEEN_rc_derate_value_MASK)
10737/*! @} */
10738
10739/*! @name DERATEINT - Temperature Derate Interval Register */
10740/*! @{ */
10741#define DDRC_REGS_DERATEINT_mr4_read_interval_MASK (0xFFFFFFFFU)
10742#define DDRC_REGS_DERATEINT_mr4_read_interval_SHIFT (0U)
10743#define DDRC_REGS_DERATEINT_mr4_read_interval(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEINT_mr4_read_interval_SHIFT)) & DDRC_REGS_DERATEINT_mr4_read_interval_MASK)
10744/*! @} */
10745
10746/*! @name PWRCTL - Low Power Control Register */
10747/*! @{ */
10748#define DDRC_REGS_PWRCTL_selfref_en_MASK (0x1U)
10749#define DDRC_REGS_PWRCTL_selfref_en_SHIFT (0U)
10750#define DDRC_REGS_PWRCTL_selfref_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRCTL_selfref_en_SHIFT)) & DDRC_REGS_PWRCTL_selfref_en_MASK)
10751#define DDRC_REGS_PWRCTL_powerdown_en_MASK (0x2U)
10752#define DDRC_REGS_PWRCTL_powerdown_en_SHIFT (1U)
10753#define DDRC_REGS_PWRCTL_powerdown_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRCTL_powerdown_en_SHIFT)) & DDRC_REGS_PWRCTL_powerdown_en_MASK)
10754#define DDRC_REGS_PWRCTL_deeppowerdown_en_MASK (0x4U)
10755#define DDRC_REGS_PWRCTL_deeppowerdown_en_SHIFT (2U)
10756#define DDRC_REGS_PWRCTL_deeppowerdown_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRCTL_deeppowerdown_en_SHIFT)) & DDRC_REGS_PWRCTL_deeppowerdown_en_MASK)
10757#define DDRC_REGS_PWRCTL_en_dfi_dram_clk_disable_MASK (0x8U)
10758#define DDRC_REGS_PWRCTL_en_dfi_dram_clk_disable_SHIFT (3U)
10759#define DDRC_REGS_PWRCTL_en_dfi_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRCTL_en_dfi_dram_clk_disable_SHIFT)) & DDRC_REGS_PWRCTL_en_dfi_dram_clk_disable_MASK)
10760#define DDRC_REGS_PWRCTL_mpsm_en_MASK (0x10U)
10761#define DDRC_REGS_PWRCTL_mpsm_en_SHIFT (4U)
10762#define DDRC_REGS_PWRCTL_mpsm_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRCTL_mpsm_en_SHIFT)) & DDRC_REGS_PWRCTL_mpsm_en_MASK)
10763#define DDRC_REGS_PWRCTL_selfref_sw_MASK (0x20U)
10764#define DDRC_REGS_PWRCTL_selfref_sw_SHIFT (5U)
10765/*! selfref_sw - A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh.
10766 * 0b0..Software Exit from Self Refresh
10767 * 0b1..Software Entry to Self Refresh
10768 */
10769#define DDRC_REGS_PWRCTL_selfref_sw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRCTL_selfref_sw_SHIFT)) & DDRC_REGS_PWRCTL_selfref_sw_MASK)
10770#define DDRC_REGS_PWRCTL_stay_in_selfref_MASK (0x40U)
10771#define DDRC_REGS_PWRCTL_stay_in_selfref_SHIFT (6U)
10772#define DDRC_REGS_PWRCTL_stay_in_selfref(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRCTL_stay_in_selfref_SHIFT)) & DDRC_REGS_PWRCTL_stay_in_selfref_MASK)
10773/*! @} */
10774
10775/*! @name PWRTMG - Low Power Timing Register */
10776/*! @{ */
10777#define DDRC_REGS_PWRTMG_powerdown_to_x32_MASK (0x1FU)
10778#define DDRC_REGS_PWRTMG_powerdown_to_x32_SHIFT (0U)
10779#define DDRC_REGS_PWRTMG_powerdown_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRTMG_powerdown_to_x32_SHIFT)) & DDRC_REGS_PWRTMG_powerdown_to_x32_MASK)
10780#define DDRC_REGS_PWRTMG_t_dpd_x4096_MASK (0xFF00U)
10781#define DDRC_REGS_PWRTMG_t_dpd_x4096_SHIFT (8U)
10782#define DDRC_REGS_PWRTMG_t_dpd_x4096(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRTMG_t_dpd_x4096_SHIFT)) & DDRC_REGS_PWRTMG_t_dpd_x4096_MASK)
10783#define DDRC_REGS_PWRTMG_selfref_to_x32_MASK (0xFF0000U)
10784#define DDRC_REGS_PWRTMG_selfref_to_x32_SHIFT (16U)
10785#define DDRC_REGS_PWRTMG_selfref_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRTMG_selfref_to_x32_SHIFT)) & DDRC_REGS_PWRTMG_selfref_to_x32_MASK)
10786/*! @} */
10787
10788/*! @name HWLPCTL - Hardware Low Power Control Register */
10789/*! @{ */
10790#define DDRC_REGS_HWLPCTL_hw_lp_en_MASK (0x1U)
10791#define DDRC_REGS_HWLPCTL_hw_lp_en_SHIFT (0U)
10792#define DDRC_REGS_HWLPCTL_hw_lp_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_HWLPCTL_hw_lp_en_SHIFT)) & DDRC_REGS_HWLPCTL_hw_lp_en_MASK)
10793#define DDRC_REGS_HWLPCTL_hw_lp_exit_idle_en_MASK (0x2U)
10794#define DDRC_REGS_HWLPCTL_hw_lp_exit_idle_en_SHIFT (1U)
10795#define DDRC_REGS_HWLPCTL_hw_lp_exit_idle_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_HWLPCTL_hw_lp_exit_idle_en_SHIFT)) & DDRC_REGS_HWLPCTL_hw_lp_exit_idle_en_MASK)
10796#define DDRC_REGS_HWLPCTL_hw_lp_idle_x32_MASK (0xFFF0000U)
10797#define DDRC_REGS_HWLPCTL_hw_lp_idle_x32_SHIFT (16U)
10798#define DDRC_REGS_HWLPCTL_hw_lp_idle_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_HWLPCTL_hw_lp_idle_x32_SHIFT)) & DDRC_REGS_HWLPCTL_hw_lp_idle_x32_MASK)
10799/*! @} */
10800
10801/*! @name RFSHCTL0 - Refresh Control Register 0 */
10802/*! @{ */
10803#define DDRC_REGS_RFSHCTL0_per_bank_refresh_MASK (0x4U)
10804#define DDRC_REGS_RFSHCTL0_per_bank_refresh_SHIFT (2U)
10805/*! per_bank_refresh - Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
10806 * 0b1..Per bank refresh
10807 * 0b0..All bank refresh
10808 */
10809#define DDRC_REGS_RFSHCTL0_per_bank_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL0_per_bank_refresh_SHIFT)) & DDRC_REGS_RFSHCTL0_per_bank_refresh_MASK)
10810#define DDRC_REGS_RFSHCTL0_refresh_burst_MASK (0x1F0U)
10811#define DDRC_REGS_RFSHCTL0_refresh_burst_SHIFT (4U)
10812#define DDRC_REGS_RFSHCTL0_refresh_burst(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL0_refresh_burst_SHIFT)) & DDRC_REGS_RFSHCTL0_refresh_burst_MASK)
10813#define DDRC_REGS_RFSHCTL0_refresh_to_x32_MASK (0x1F000U)
10814#define DDRC_REGS_RFSHCTL0_refresh_to_x32_SHIFT (12U)
10815#define DDRC_REGS_RFSHCTL0_refresh_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL0_refresh_to_x32_SHIFT)) & DDRC_REGS_RFSHCTL0_refresh_to_x32_MASK)
10816#define DDRC_REGS_RFSHCTL0_refresh_margin_MASK (0xF00000U)
10817#define DDRC_REGS_RFSHCTL0_refresh_margin_SHIFT (20U)
10818#define DDRC_REGS_RFSHCTL0_refresh_margin(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL0_refresh_margin_SHIFT)) & DDRC_REGS_RFSHCTL0_refresh_margin_MASK)
10819/*! @} */
10820
10821/*! @name RFSHCTL1 - Refresh Control Register 1 */
10822/*! @{ */
10823#define DDRC_REGS_RFSHCTL1_refresh_timer0_start_value_x32_MASK (0xFFFU)
10824#define DDRC_REGS_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT (0U)
10825#define DDRC_REGS_RFSHCTL1_refresh_timer0_start_value_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT)) & DDRC_REGS_RFSHCTL1_refresh_timer0_start_value_x32_MASK)
10826#define DDRC_REGS_RFSHCTL1_refresh_timer1_start_value_x32_MASK (0xFFF0000U)
10827#define DDRC_REGS_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT (16U)
10828#define DDRC_REGS_RFSHCTL1_refresh_timer1_start_value_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT)) & DDRC_REGS_RFSHCTL1_refresh_timer1_start_value_x32_MASK)
10829/*! @} */
10830
10831/*! @name RFSHCTL3 - Refresh Control Register 3 */
10832/*! @{ */
10833#define DDRC_REGS_RFSHCTL3_dis_auto_refresh_MASK (0x1U)
10834#define DDRC_REGS_RFSHCTL3_dis_auto_refresh_SHIFT (0U)
10835#define DDRC_REGS_RFSHCTL3_dis_auto_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL3_dis_auto_refresh_SHIFT)) & DDRC_REGS_RFSHCTL3_dis_auto_refresh_MASK)
10836#define DDRC_REGS_RFSHCTL3_refresh_update_level_MASK (0x2U)
10837#define DDRC_REGS_RFSHCTL3_refresh_update_level_SHIFT (1U)
10838#define DDRC_REGS_RFSHCTL3_refresh_update_level(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL3_refresh_update_level_SHIFT)) & DDRC_REGS_RFSHCTL3_refresh_update_level_MASK)
10839#define DDRC_REGS_RFSHCTL3_refresh_mode_MASK (0x70U)
10840#define DDRC_REGS_RFSHCTL3_refresh_mode_SHIFT (4U)
10841#define DDRC_REGS_RFSHCTL3_refresh_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL3_refresh_mode_SHIFT)) & DDRC_REGS_RFSHCTL3_refresh_mode_MASK)
10842/*! @} */
10843
10844/*! @name RFSHTMG - Refresh Timing Register */
10845/*! @{ */
10846#define DDRC_REGS_RFSHTMG_t_rfc_min_MASK (0x3FFU)
10847#define DDRC_REGS_RFSHTMG_t_rfc_min_SHIFT (0U)
10848#define DDRC_REGS_RFSHTMG_t_rfc_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHTMG_t_rfc_min_SHIFT)) & DDRC_REGS_RFSHTMG_t_rfc_min_MASK)
10849#define DDRC_REGS_RFSHTMG_lpddr3_trefbw_en_MASK (0x8000U)
10850#define DDRC_REGS_RFSHTMG_lpddr3_trefbw_en_SHIFT (15U)
10851#define DDRC_REGS_RFSHTMG_lpddr3_trefbw_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHTMG_lpddr3_trefbw_en_SHIFT)) & DDRC_REGS_RFSHTMG_lpddr3_trefbw_en_MASK)
10852#define DDRC_REGS_RFSHTMG_t_rfc_nom_x32_MASK (0xFFF0000U)
10853#define DDRC_REGS_RFSHTMG_t_rfc_nom_x32_SHIFT (16U)
10854#define DDRC_REGS_RFSHTMG_t_rfc_nom_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHTMG_t_rfc_nom_x32_SHIFT)) & DDRC_REGS_RFSHTMG_t_rfc_nom_x32_MASK)
10855/*! @} */
10856
10857/*! @name CRCPARCTL0 - CRC Parity Control Register0 */
10858/*! @{ */
10859#define DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_en_MASK (0x1U)
10860#define DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_en_SHIFT (0U)
10861#define DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_en_SHIFT)) & DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_en_MASK)
10862#define DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_clr_MASK (0x2U)
10863#define DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_clr_SHIFT (1U)
10864#define DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_clr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_clr_SHIFT)) & DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_clr_MASK)
10865#define DDRC_REGS_CRCPARCTL0_dfi_alert_err_cnt_clr_MASK (0x4U)
10866#define DDRC_REGS_CRCPARCTL0_dfi_alert_err_cnt_clr_SHIFT (2U)
10867#define DDRC_REGS_CRCPARCTL0_dfi_alert_err_cnt_clr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_CRCPARCTL0_dfi_alert_err_cnt_clr_SHIFT)) & DDRC_REGS_CRCPARCTL0_dfi_alert_err_cnt_clr_MASK)
10868/*! @} */
10869
10870/*! @name CRCPARCTL1 - CRC Parity Control Register1 */
10871/*! @{ */
10872#define DDRC_REGS_CRCPARCTL1_parity_enable_MASK (0x1U)
10873#define DDRC_REGS_CRCPARCTL1_parity_enable_SHIFT (0U)
10874/*! parity_enable - C/A Parity enable register. If RCD's parity error detection or SDRAM's parity detection is enabled, this register should be 1.
10875 * 0b0..Disable generation of C/A parity and disable detection of C/A parity error
10876 * 0b1..Enable generation of C/A parity and detection of C/A parity error
10877 */
10878#define DDRC_REGS_CRCPARCTL1_parity_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_CRCPARCTL1_parity_enable_SHIFT)) & DDRC_REGS_CRCPARCTL1_parity_enable_MASK)
10879#define DDRC_REGS_CRCPARCTL1_crc_enable_MASK (0x10U)
10880#define DDRC_REGS_CRCPARCTL1_crc_enable_SHIFT (4U)
10881/*! crc_enable - CRC enable Register. The setting of this register should match the CRC mode register setting in the DRAM.
10882 * 0b0..isable generation of CRC
10883 * 0b1..Enable generation of CRC
10884 */
10885#define DDRC_REGS_CRCPARCTL1_crc_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_CRCPARCTL1_crc_enable_SHIFT)) & DDRC_REGS_CRCPARCTL1_crc_enable_MASK)
10886#define DDRC_REGS_CRCPARCTL1_crc_inc_dm_MASK (0x80U)
10887#define DDRC_REGS_CRCPARCTL1_crc_inc_dm_SHIFT (7U)
10888/*! crc_inc_dm - CRC Calculation setting register. Present only in designs configured to support DDR4.
10889 * 0b0..CRC not includes DM signal
10890 * 0b1..CRC includes DM signal
10891 */
10892#define DDRC_REGS_CRCPARCTL1_crc_inc_dm(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_CRCPARCTL1_crc_inc_dm_SHIFT)) & DDRC_REGS_CRCPARCTL1_crc_inc_dm_MASK)
10893#define DDRC_REGS_CRCPARCTL1_caparity_disable_before_sr_MASK (0x1000U)
10894#define DDRC_REGS_CRCPARCTL1_caparity_disable_before_sr_SHIFT (12U)
10895/*! caparity_disable_before_sr - If DDR4-SDRAM's CA parity is enabled by INIT6.mr5[2:0]!=0 and this register is set to 1, CA parity is automatically disabled before Self-Refresh entry and enabled after Self-Refresh exit by issuing MR5. - 1: CA parity is disabled before Self-Refresh entry - 0: CA parity is not disabled before Self-Refresh entry If Geardown is used by MSTR.geardown_mode=1, this register must be set to 1. If this register set to 0, DRAMTMG5.t_ckesr and DRAMTMG5.t_cksre must be increased by PL(Parity latency)
10896 * 0b0..CA parity is not disabled before Self-Refresh entry
10897 * 0b1..CA parity is disabled before Self-Refresh entry
10898 */
10899#define DDRC_REGS_CRCPARCTL1_caparity_disable_before_sr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_CRCPARCTL1_caparity_disable_before_sr_SHIFT)) & DDRC_REGS_CRCPARCTL1_caparity_disable_before_sr_MASK)
10900/*! @} */
10901
10902/*! @name CRCPARSTAT - CRC Parity Status Register */
10903/*! @{ */
10904#define DDRC_REGS_CRCPARSTAT_dfi_alert_err_cnt_MASK (0xFFFFU)
10905#define DDRC_REGS_CRCPARSTAT_dfi_alert_err_cnt_SHIFT (0U)
10906#define DDRC_REGS_CRCPARSTAT_dfi_alert_err_cnt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_CRCPARSTAT_dfi_alert_err_cnt_SHIFT)) & DDRC_REGS_CRCPARSTAT_dfi_alert_err_cnt_MASK)
10907#define DDRC_REGS_CRCPARSTAT_dfi_alert_err_int_MASK (0x10000U)
10908#define DDRC_REGS_CRCPARSTAT_dfi_alert_err_int_SHIFT (16U)
10909#define DDRC_REGS_CRCPARSTAT_dfi_alert_err_int(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_CRCPARSTAT_dfi_alert_err_int_SHIFT)) & DDRC_REGS_CRCPARSTAT_dfi_alert_err_int_MASK)
10910/*! @} */
10911
10912/*! @name INIT0 - SDRAM Initialization Register 0 */
10913/*! @{ */
10914#define DDRC_REGS_INIT0_pre_cke_x1024_MASK (0xFFFU)
10915#define DDRC_REGS_INIT0_pre_cke_x1024_SHIFT (0U)
10916#define DDRC_REGS_INIT0_pre_cke_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT0_pre_cke_x1024_SHIFT)) & DDRC_REGS_INIT0_pre_cke_x1024_MASK)
10917#define DDRC_REGS_INIT0_post_cke_x1024_MASK (0x3FF0000U)
10918#define DDRC_REGS_INIT0_post_cke_x1024_SHIFT (16U)
10919#define DDRC_REGS_INIT0_post_cke_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT0_post_cke_x1024_SHIFT)) & DDRC_REGS_INIT0_post_cke_x1024_MASK)
10920#define DDRC_REGS_INIT0_skip_dram_init_MASK (0xC0000000U)
10921#define DDRC_REGS_INIT0_skip_dram_init_SHIFT (30U)
10922/*! skip_dram_init - If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Initialization routine is skipped after power-up. Controller starts up in Normal Mode - 11 - SDRAM Initialization routine is skipped after power-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Initialization routine is run after power-up.
10923 * 0b00..SDRAM Initialization routine is run after power-up
10924 * 0b01..SDRAM Initialization routine is skipped after power-up
10925 * 0b10..SDRAM Initialization routine is run after power-up
10926 * 0b11..SDRAM Initialization routine is skipped after power-up
10927 */
10928#define DDRC_REGS_INIT0_skip_dram_init(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT0_skip_dram_init_SHIFT)) & DDRC_REGS_INIT0_skip_dram_init_MASK)
10929/*! @} */
10930
10931/*! @name INIT1 - SDRAM Initialization Register 1 */
10932/*! @{ */
10933#define DDRC_REGS_INIT1_pre_ocd_x32_MASK (0xFU)
10934#define DDRC_REGS_INIT1_pre_ocd_x32_SHIFT (0U)
10935#define DDRC_REGS_INIT1_pre_ocd_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT1_pre_ocd_x32_SHIFT)) & DDRC_REGS_INIT1_pre_ocd_x32_MASK)
10936#define DDRC_REGS_INIT1_dram_rstn_x1024_MASK (0x1FF0000U)
10937#define DDRC_REGS_INIT1_dram_rstn_x1024_SHIFT (16U)
10938#define DDRC_REGS_INIT1_dram_rstn_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT1_dram_rstn_x1024_SHIFT)) & DDRC_REGS_INIT1_dram_rstn_x1024_MASK)
10939/*! @} */
10940
10941/*! @name INIT2 - SDRAM Initialization Register 2 */
10942/*! @{ */
10943#define DDRC_REGS_INIT2_min_stable_clock_x1_MASK (0xFU)
10944#define DDRC_REGS_INIT2_min_stable_clock_x1_SHIFT (0U)
10945#define DDRC_REGS_INIT2_min_stable_clock_x1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT2_min_stable_clock_x1_SHIFT)) & DDRC_REGS_INIT2_min_stable_clock_x1_MASK)
10946#define DDRC_REGS_INIT2_idle_after_reset_x32_MASK (0xFF00U)
10947#define DDRC_REGS_INIT2_idle_after_reset_x32_SHIFT (8U)
10948#define DDRC_REGS_INIT2_idle_after_reset_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT2_idle_after_reset_x32_SHIFT)) & DDRC_REGS_INIT2_idle_after_reset_x32_MASK)
10949/*! @} */
10950
10951/*! @name INIT3 - SDRAM Initialization Register 3 */
10952/*! @{ */
10953#define DDRC_REGS_INIT3_emr_MASK (0xFFFFU)
10954#define DDRC_REGS_INIT3_emr_SHIFT (0U)
10955#define DDRC_REGS_INIT3_emr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT3_emr_SHIFT)) & DDRC_REGS_INIT3_emr_MASK)
10956#define DDRC_REGS_INIT3_mr_MASK (0xFFFF0000U)
10957#define DDRC_REGS_INIT3_mr_SHIFT (16U)
10958#define DDRC_REGS_INIT3_mr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT3_mr_SHIFT)) & DDRC_REGS_INIT3_mr_MASK)
10959/*! @} */
10960
10961/*! @name INIT4 - SDRAM Initialization Register 4 */
10962/*! @{ */
10963#define DDRC_REGS_INIT4_emr3_MASK (0xFFFFU)
10964#define DDRC_REGS_INIT4_emr3_SHIFT (0U)
10965#define DDRC_REGS_INIT4_emr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT4_emr3_SHIFT)) & DDRC_REGS_INIT4_emr3_MASK)
10966#define DDRC_REGS_INIT4_emr2_MASK (0xFFFF0000U)
10967#define DDRC_REGS_INIT4_emr2_SHIFT (16U)
10968#define DDRC_REGS_INIT4_emr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT4_emr2_SHIFT)) & DDRC_REGS_INIT4_emr2_MASK)
10969/*! @} */
10970
10971/*! @name INIT5 - SDRAM Initialization Register 5 */
10972/*! @{ */
10973#define DDRC_REGS_INIT5_max_auto_init_x1024_MASK (0x3FFU)
10974#define DDRC_REGS_INIT5_max_auto_init_x1024_SHIFT (0U)
10975#define DDRC_REGS_INIT5_max_auto_init_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT5_max_auto_init_x1024_SHIFT)) & DDRC_REGS_INIT5_max_auto_init_x1024_MASK)
10976#define DDRC_REGS_INIT5_dev_zqinit_x32_MASK (0xFF0000U)
10977#define DDRC_REGS_INIT5_dev_zqinit_x32_SHIFT (16U)
10978#define DDRC_REGS_INIT5_dev_zqinit_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT5_dev_zqinit_x32_SHIFT)) & DDRC_REGS_INIT5_dev_zqinit_x32_MASK)
10979/*! @} */
10980
10981/*! @name INIT6 - SDRAM Initialization Register 6 */
10982/*! @{ */
10983#define DDRC_REGS_INIT6_mr5_MASK (0xFFFFU)
10984#define DDRC_REGS_INIT6_mr5_SHIFT (0U)
10985#define DDRC_REGS_INIT6_mr5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT6_mr5_SHIFT)) & DDRC_REGS_INIT6_mr5_MASK)
10986#define DDRC_REGS_INIT6_mr4_MASK (0xFFFF0000U)
10987#define DDRC_REGS_INIT6_mr4_SHIFT (16U)
10988#define DDRC_REGS_INIT6_mr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT6_mr4_SHIFT)) & DDRC_REGS_INIT6_mr4_MASK)
10989/*! @} */
10990
10991/*! @name INIT7 - SDRAM Initialization Register 7 */
10992/*! @{ */
10993#define DDRC_REGS_INIT7_mr6_MASK (0xFFFF0000U)
10994#define DDRC_REGS_INIT7_mr6_SHIFT (16U)
10995#define DDRC_REGS_INIT7_mr6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT7_mr6_SHIFT)) & DDRC_REGS_INIT7_mr6_MASK)
10996/*! @} */
10997
10998/*! @name DIMMCTL - DIMM Control Register */
10999/*! @{ */
11000#define DDRC_REGS_DIMMCTL_dimm_stagger_cs_en_MASK (0x1U)
11001#define DDRC_REGS_DIMMCTL_dimm_stagger_cs_en_SHIFT (0U)
11002/*! dimm_stagger_cs_en - Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs.Even if this bit is set it does not take care of software driven MR commands (via MRCTRL0/MRCTRL1), where software is responsible to send them to separate ranks as appropriate.
11003 * 0b0..Do not stagger accesses
11004 * 0b1..(non-DDR4) Send all commands to even and odd ranks separately
11005 * 0b1..(DDR4) Send MRS commands to each ranks separately
11006 */
11007#define DDRC_REGS_DIMMCTL_dimm_stagger_cs_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DIMMCTL_dimm_stagger_cs_en_SHIFT)) & DDRC_REGS_DIMMCTL_dimm_stagger_cs_en_MASK)
11008#define DDRC_REGS_DIMMCTL_dimm_addr_mirr_en_MASK (0x2U)
11009#define DDRC_REGS_DIMMCTL_dimm_addr_mirr_en_SHIFT (1U)
11010/*! dimm_addr_mirr_en - Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures that, for mode register accesses during the automatic initialization routine, these bits are swapped within the DDRC to compensate for this UDIMM/RDIMM/LRDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM/LRDIMM, they are swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1.
11011 * 0b0..Do not implement address mirroring
11012 * 0b1..For odd ranks, implement address mirroring for MRS commands to during initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM/LRDIMM implements address mirroring)
11013 */
11014#define DDRC_REGS_DIMMCTL_dimm_addr_mirr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DIMMCTL_dimm_addr_mirr_en_SHIFT)) & DDRC_REGS_DIMMCTL_dimm_addr_mirr_en_MASK)
11015#define DDRC_REGS_DIMMCTL_dimm_output_inv_en_MASK (0x4U)
11016#define DDRC_REGS_DIMMCTL_dimm_output_inv_en_SHIFT (2U)
11017/*! dimm_output_inv_en - Output Inversion Enable (for DDR4 RDIMM/LRDIMM implementations only). DDR4 RDIMM/LRDIMM implements the Output Inversion feature by default, which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the DDRC during the automatic initialization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. For B-side mode register accesses, these bits are inverted within the DDRC to compensate for this RDIMM/LRDIMM inversion. It is recommended to set this bit always, if using DDR4 RDIMMs/LRDIMMs. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses.
11018 * 0b0..Do not implement output inversion for B-side DRAMs.
11019 * 0b1..Implement output inversion for B-side DRAMs.
11020 */
11021#define DDRC_REGS_DIMMCTL_dimm_output_inv_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DIMMCTL_dimm_output_inv_en_SHIFT)) & DDRC_REGS_DIMMCTL_dimm_output_inv_en_MASK)
11022#define DDRC_REGS_DIMMCTL_mrs_a17_en_MASK (0x8U)
11023#define DDRC_REGS_DIMMCTL_mrs_a17_en_SHIFT (3U)
11024/*! mrs_a17_en - Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, this must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses.
11025 * 0b0..Disabled
11026 * 0b1..Enabled
11027 */
11028#define DDRC_REGS_DIMMCTL_mrs_a17_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DIMMCTL_mrs_a17_en_SHIFT)) & DDRC_REGS_DIMMCTL_mrs_a17_en_MASK)
11029#define DDRC_REGS_DIMMCTL_mrs_bg1_en_MASK (0x10U)
11030#define DDRC_REGS_DIMMCTL_mrs_bg1_en_SHIFT (4U)
11031/*! mrs_bg1_en - Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output Inversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is enabled, this is applied to BG1 of even ranks and BG0 of odd ranks.
11032 * 0b0..Disabled
11033 * 0b1..Enabled
11034 */
11035#define DDRC_REGS_DIMMCTL_mrs_bg1_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DIMMCTL_mrs_bg1_en_SHIFT)) & DDRC_REGS_DIMMCTL_mrs_bg1_en_MASK)
11036#define DDRC_REGS_DIMMCTL_dimm_dis_bg_mirroring_MASK (0x20U)
11037#define DDRC_REGS_DIMMCTL_dimm_dis_bg_mirroring_SHIFT (5U)
11038/*! dimm_dis_bg_mirroring - Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enabled. This will be required for DDR4 DIMMs with x16 devices.
11039 * 0b0..BG0 and BG1 are swapped if address mirroring is enabled.
11040 * 0b1..BG0 and BG1 are NOT swapped.
11041 */
11042#define DDRC_REGS_DIMMCTL_dimm_dis_bg_mirroring(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DIMMCTL_dimm_dis_bg_mirroring_SHIFT)) & DDRC_REGS_DIMMCTL_dimm_dis_bg_mirroring_MASK)
11043#define DDRC_REGS_DIMMCTL_lrdimm_bcom_cmd_prot_MASK (0x40U)
11044#define DDRC_REGS_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT (6U)
11045#define DDRC_REGS_DIMMCTL_lrdimm_bcom_cmd_prot(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT)) & DDRC_REGS_DIMMCTL_lrdimm_bcom_cmd_prot_MASK)
11046/*! @} */
11047
11048/*! @name RANKCTL - Rank Control Register */
11049/*! @{ */
11050#define DDRC_REGS_RANKCTL_max_rank_rd_MASK (0xFU)
11051#define DDRC_REGS_RANKCTL_max_rank_rd_SHIFT (0U)
11052#define DDRC_REGS_RANKCTL_max_rank_rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RANKCTL_max_rank_rd_SHIFT)) & DDRC_REGS_RANKCTL_max_rank_rd_MASK)
11053#define DDRC_REGS_RANKCTL_diff_rank_rd_gap_MASK (0xF0U)
11054#define DDRC_REGS_RANKCTL_diff_rank_rd_gap_SHIFT (4U)
11055#define DDRC_REGS_RANKCTL_diff_rank_rd_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RANKCTL_diff_rank_rd_gap_SHIFT)) & DDRC_REGS_RANKCTL_diff_rank_rd_gap_MASK)
11056#define DDRC_REGS_RANKCTL_diff_rank_wr_gap_MASK (0xF00U)
11057#define DDRC_REGS_RANKCTL_diff_rank_wr_gap_SHIFT (8U)
11058#define DDRC_REGS_RANKCTL_diff_rank_wr_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RANKCTL_diff_rank_wr_gap_SHIFT)) & DDRC_REGS_RANKCTL_diff_rank_wr_gap_MASK)
11059/*! @} */
11060
11061/*! @name DRAMTMG0 - SDRAM Timing Register 0 */
11062/*! @{ */
11063#define DDRC_REGS_DRAMTMG0_t_ras_min_MASK (0x3FU)
11064#define DDRC_REGS_DRAMTMG0_t_ras_min_SHIFT (0U)
11065#define DDRC_REGS_DRAMTMG0_t_ras_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG0_t_ras_min_SHIFT)) & DDRC_REGS_DRAMTMG0_t_ras_min_MASK)
11066#define DDRC_REGS_DRAMTMG0_t_ras_max_MASK (0x7F00U)
11067#define DDRC_REGS_DRAMTMG0_t_ras_max_SHIFT (8U)
11068#define DDRC_REGS_DRAMTMG0_t_ras_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG0_t_ras_max_SHIFT)) & DDRC_REGS_DRAMTMG0_t_ras_max_MASK)
11069#define DDRC_REGS_DRAMTMG0_t_faw_MASK (0x3F0000U)
11070#define DDRC_REGS_DRAMTMG0_t_faw_SHIFT (16U)
11071#define DDRC_REGS_DRAMTMG0_t_faw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG0_t_faw_SHIFT)) & DDRC_REGS_DRAMTMG0_t_faw_MASK)
11072#define DDRC_REGS_DRAMTMG0_wr2pre_MASK (0x7F000000U)
11073#define DDRC_REGS_DRAMTMG0_wr2pre_SHIFT (24U)
11074#define DDRC_REGS_DRAMTMG0_wr2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG0_wr2pre_SHIFT)) & DDRC_REGS_DRAMTMG0_wr2pre_MASK)
11075/*! @} */
11076
11077/*! @name DRAMTMG1 - SDRAM Timing Register 1 */
11078/*! @{ */
11079#define DDRC_REGS_DRAMTMG1_t_rc_MASK (0x7FU)
11080#define DDRC_REGS_DRAMTMG1_t_rc_SHIFT (0U)
11081#define DDRC_REGS_DRAMTMG1_t_rc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG1_t_rc_SHIFT)) & DDRC_REGS_DRAMTMG1_t_rc_MASK)
11082#define DDRC_REGS_DRAMTMG1_rd2pre_MASK (0x3F00U)
11083#define DDRC_REGS_DRAMTMG1_rd2pre_SHIFT (8U)
11084#define DDRC_REGS_DRAMTMG1_rd2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG1_rd2pre_SHIFT)) & DDRC_REGS_DRAMTMG1_rd2pre_MASK)
11085#define DDRC_REGS_DRAMTMG1_t_xp_MASK (0x1F0000U)
11086#define DDRC_REGS_DRAMTMG1_t_xp_SHIFT (16U)
11087#define DDRC_REGS_DRAMTMG1_t_xp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG1_t_xp_SHIFT)) & DDRC_REGS_DRAMTMG1_t_xp_MASK)
11088/*! @} */
11089
11090/*! @name DRAMTMG2 - SDRAM Timing Register 2 */
11091/*! @{ */
11092#define DDRC_REGS_DRAMTMG2_wr2rd_MASK (0x3FU)
11093#define DDRC_REGS_DRAMTMG2_wr2rd_SHIFT (0U)
11094#define DDRC_REGS_DRAMTMG2_wr2rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG2_wr2rd_SHIFT)) & DDRC_REGS_DRAMTMG2_wr2rd_MASK)
11095#define DDRC_REGS_DRAMTMG2_rd2wr_MASK (0x3F00U)
11096#define DDRC_REGS_DRAMTMG2_rd2wr_SHIFT (8U)
11097#define DDRC_REGS_DRAMTMG2_rd2wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG2_rd2wr_SHIFT)) & DDRC_REGS_DRAMTMG2_rd2wr_MASK)
11098#define DDRC_REGS_DRAMTMG2_read_latency_MASK (0x3F0000U)
11099#define DDRC_REGS_DRAMTMG2_read_latency_SHIFT (16U)
11100#define DDRC_REGS_DRAMTMG2_read_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG2_read_latency_SHIFT)) & DDRC_REGS_DRAMTMG2_read_latency_MASK)
11101#define DDRC_REGS_DRAMTMG2_write_latency_MASK (0x3F000000U)
11102#define DDRC_REGS_DRAMTMG2_write_latency_SHIFT (24U)
11103#define DDRC_REGS_DRAMTMG2_write_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG2_write_latency_SHIFT)) & DDRC_REGS_DRAMTMG2_write_latency_MASK)
11104/*! @} */
11105
11106/*! @name DRAMTMG3 - SDRAM Timing Register 3 */
11107/*! @{ */
11108#define DDRC_REGS_DRAMTMG3_t_mod_MASK (0x3FFU)
11109#define DDRC_REGS_DRAMTMG3_t_mod_SHIFT (0U)
11110#define DDRC_REGS_DRAMTMG3_t_mod(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG3_t_mod_SHIFT)) & DDRC_REGS_DRAMTMG3_t_mod_MASK)
11111#define DDRC_REGS_DRAMTMG3_t_mrd_MASK (0x3F000U)
11112#define DDRC_REGS_DRAMTMG3_t_mrd_SHIFT (12U)
11113#define DDRC_REGS_DRAMTMG3_t_mrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG3_t_mrd_SHIFT)) & DDRC_REGS_DRAMTMG3_t_mrd_MASK)
11114#define DDRC_REGS_DRAMTMG3_t_mrw_MASK (0x3FF00000U)
11115#define DDRC_REGS_DRAMTMG3_t_mrw_SHIFT (20U)
11116#define DDRC_REGS_DRAMTMG3_t_mrw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG3_t_mrw_SHIFT)) & DDRC_REGS_DRAMTMG3_t_mrw_MASK)
11117/*! @} */
11118
11119/*! @name DRAMTMG4 - SDRAM Timing Register 4 */
11120/*! @{ */
11121#define DDRC_REGS_DRAMTMG4_t_rp_MASK (0x1FU)
11122#define DDRC_REGS_DRAMTMG4_t_rp_SHIFT (0U)
11123#define DDRC_REGS_DRAMTMG4_t_rp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG4_t_rp_SHIFT)) & DDRC_REGS_DRAMTMG4_t_rp_MASK)
11124#define DDRC_REGS_DRAMTMG4_t_rrd_MASK (0xF00U)
11125#define DDRC_REGS_DRAMTMG4_t_rrd_SHIFT (8U)
11126#define DDRC_REGS_DRAMTMG4_t_rrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG4_t_rrd_SHIFT)) & DDRC_REGS_DRAMTMG4_t_rrd_MASK)
11127#define DDRC_REGS_DRAMTMG4_t_ccd_MASK (0xF0000U)
11128#define DDRC_REGS_DRAMTMG4_t_ccd_SHIFT (16U)
11129#define DDRC_REGS_DRAMTMG4_t_ccd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG4_t_ccd_SHIFT)) & DDRC_REGS_DRAMTMG4_t_ccd_MASK)
11130#define DDRC_REGS_DRAMTMG4_t_rcd_MASK (0x1F000000U)
11131#define DDRC_REGS_DRAMTMG4_t_rcd_SHIFT (24U)
11132#define DDRC_REGS_DRAMTMG4_t_rcd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG4_t_rcd_SHIFT)) & DDRC_REGS_DRAMTMG4_t_rcd_MASK)
11133/*! @} */
11134
11135/*! @name DRAMTMG5 - SDRAM Timing Register 5 */
11136/*! @{ */
11137#define DDRC_REGS_DRAMTMG5_t_cke_MASK (0x1FU)
11138#define DDRC_REGS_DRAMTMG5_t_cke_SHIFT (0U)
11139#define DDRC_REGS_DRAMTMG5_t_cke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG5_t_cke_SHIFT)) & DDRC_REGS_DRAMTMG5_t_cke_MASK)
11140#define DDRC_REGS_DRAMTMG5_t_ckesr_MASK (0x3F00U)
11141#define DDRC_REGS_DRAMTMG5_t_ckesr_SHIFT (8U)
11142#define DDRC_REGS_DRAMTMG5_t_ckesr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG5_t_ckesr_SHIFT)) & DDRC_REGS_DRAMTMG5_t_ckesr_MASK)
11143#define DDRC_REGS_DRAMTMG5_t_cksre_MASK (0xF0000U)
11144#define DDRC_REGS_DRAMTMG5_t_cksre_SHIFT (16U)
11145#define DDRC_REGS_DRAMTMG5_t_cksre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG5_t_cksre_SHIFT)) & DDRC_REGS_DRAMTMG5_t_cksre_MASK)
11146#define DDRC_REGS_DRAMTMG5_t_cksrx_MASK (0xF000000U)
11147#define DDRC_REGS_DRAMTMG5_t_cksrx_SHIFT (24U)
11148#define DDRC_REGS_DRAMTMG5_t_cksrx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG5_t_cksrx_SHIFT)) & DDRC_REGS_DRAMTMG5_t_cksrx_MASK)
11149/*! @} */
11150
11151/*! @name DRAMTMG6 - SDRAM Timing Register 6 */
11152/*! @{ */
11153#define DDRC_REGS_DRAMTMG6_t_ckcsx_MASK (0xFU)
11154#define DDRC_REGS_DRAMTMG6_t_ckcsx_SHIFT (0U)
11155#define DDRC_REGS_DRAMTMG6_t_ckcsx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG6_t_ckcsx_SHIFT)) & DDRC_REGS_DRAMTMG6_t_ckcsx_MASK)
11156#define DDRC_REGS_DRAMTMG6_t_ckdpdx_MASK (0xF0000U)
11157#define DDRC_REGS_DRAMTMG6_t_ckdpdx_SHIFT (16U)
11158#define DDRC_REGS_DRAMTMG6_t_ckdpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG6_t_ckdpdx_SHIFT)) & DDRC_REGS_DRAMTMG6_t_ckdpdx_MASK)
11159#define DDRC_REGS_DRAMTMG6_t_ckdpde_MASK (0xF000000U)
11160#define DDRC_REGS_DRAMTMG6_t_ckdpde_SHIFT (24U)
11161#define DDRC_REGS_DRAMTMG6_t_ckdpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG6_t_ckdpde_SHIFT)) & DDRC_REGS_DRAMTMG6_t_ckdpde_MASK)
11162/*! @} */
11163
11164/*! @name DRAMTMG7 - SDRAM Timing Register 7 */
11165/*! @{ */
11166#define DDRC_REGS_DRAMTMG7_t_ckpdx_MASK (0xFU)
11167#define DDRC_REGS_DRAMTMG7_t_ckpdx_SHIFT (0U)
11168#define DDRC_REGS_DRAMTMG7_t_ckpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG7_t_ckpdx_SHIFT)) & DDRC_REGS_DRAMTMG7_t_ckpdx_MASK)
11169#define DDRC_REGS_DRAMTMG7_t_ckpde_MASK (0xF00U)
11170#define DDRC_REGS_DRAMTMG7_t_ckpde_SHIFT (8U)
11171#define DDRC_REGS_DRAMTMG7_t_ckpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG7_t_ckpde_SHIFT)) & DDRC_REGS_DRAMTMG7_t_ckpde_MASK)
11172/*! @} */
11173
11174/*! @name DRAMTMG8 - SDRAM Timing Register 8 */
11175/*! @{ */
11176#define DDRC_REGS_DRAMTMG8_t_xs_x32_MASK (0x7FU)
11177#define DDRC_REGS_DRAMTMG8_t_xs_x32_SHIFT (0U)
11178#define DDRC_REGS_DRAMTMG8_t_xs_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG8_t_xs_x32_SHIFT)) & DDRC_REGS_DRAMTMG8_t_xs_x32_MASK)
11179#define DDRC_REGS_DRAMTMG8_t_xs_dll_x32_MASK (0x7F00U)
11180#define DDRC_REGS_DRAMTMG8_t_xs_dll_x32_SHIFT (8U)
11181#define DDRC_REGS_DRAMTMG8_t_xs_dll_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG8_t_xs_dll_x32_SHIFT)) & DDRC_REGS_DRAMTMG8_t_xs_dll_x32_MASK)
11182#define DDRC_REGS_DRAMTMG8_t_xs_abort_x32_MASK (0x7F0000U)
11183#define DDRC_REGS_DRAMTMG8_t_xs_abort_x32_SHIFT (16U)
11184#define DDRC_REGS_DRAMTMG8_t_xs_abort_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG8_t_xs_abort_x32_SHIFT)) & DDRC_REGS_DRAMTMG8_t_xs_abort_x32_MASK)
11185#define DDRC_REGS_DRAMTMG8_t_xs_fast_x32_MASK (0x7F000000U)
11186#define DDRC_REGS_DRAMTMG8_t_xs_fast_x32_SHIFT (24U)
11187#define DDRC_REGS_DRAMTMG8_t_xs_fast_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG8_t_xs_fast_x32_SHIFT)) & DDRC_REGS_DRAMTMG8_t_xs_fast_x32_MASK)
11188/*! @} */
11189
11190/*! @name DRAMTMG9 - SDRAM Timing Register 9 */
11191/*! @{ */
11192#define DDRC_REGS_DRAMTMG9_wr2rd_s_MASK (0x3FU)
11193#define DDRC_REGS_DRAMTMG9_wr2rd_s_SHIFT (0U)
11194#define DDRC_REGS_DRAMTMG9_wr2rd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG9_wr2rd_s_SHIFT)) & DDRC_REGS_DRAMTMG9_wr2rd_s_MASK)
11195#define DDRC_REGS_DRAMTMG9_t_rrd_s_MASK (0xF00U)
11196#define DDRC_REGS_DRAMTMG9_t_rrd_s_SHIFT (8U)
11197#define DDRC_REGS_DRAMTMG9_t_rrd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG9_t_rrd_s_SHIFT)) & DDRC_REGS_DRAMTMG9_t_rrd_s_MASK)
11198#define DDRC_REGS_DRAMTMG9_t_ccd_s_MASK (0x70000U)
11199#define DDRC_REGS_DRAMTMG9_t_ccd_s_SHIFT (16U)
11200#define DDRC_REGS_DRAMTMG9_t_ccd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG9_t_ccd_s_SHIFT)) & DDRC_REGS_DRAMTMG9_t_ccd_s_MASK)
11201#define DDRC_REGS_DRAMTMG9_ddr4_wr_preamble_MASK (0x40000000U)
11202#define DDRC_REGS_DRAMTMG9_ddr4_wr_preamble_SHIFT (30U)
11203#define DDRC_REGS_DRAMTMG9_ddr4_wr_preamble(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG9_ddr4_wr_preamble_SHIFT)) & DDRC_REGS_DRAMTMG9_ddr4_wr_preamble_MASK)
11204/*! @} */
11205
11206/*! @name DRAMTMG10 - SDRAM Timing Register 10 */
11207/*! @{ */
11208#define DDRC_REGS_DRAMTMG10_t_gear_hold_MASK (0x3U)
11209#define DDRC_REGS_DRAMTMG10_t_gear_hold_SHIFT (0U)
11210#define DDRC_REGS_DRAMTMG10_t_gear_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG10_t_gear_hold_SHIFT)) & DDRC_REGS_DRAMTMG10_t_gear_hold_MASK)
11211#define DDRC_REGS_DRAMTMG10_t_gear_setup_MASK (0xCU)
11212#define DDRC_REGS_DRAMTMG10_t_gear_setup_SHIFT (2U)
11213#define DDRC_REGS_DRAMTMG10_t_gear_setup(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG10_t_gear_setup_SHIFT)) & DDRC_REGS_DRAMTMG10_t_gear_setup_MASK)
11214#define DDRC_REGS_DRAMTMG10_t_cmd_gear_MASK (0x1F00U)
11215#define DDRC_REGS_DRAMTMG10_t_cmd_gear_SHIFT (8U)
11216#define DDRC_REGS_DRAMTMG10_t_cmd_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG10_t_cmd_gear_SHIFT)) & DDRC_REGS_DRAMTMG10_t_cmd_gear_MASK)
11217#define DDRC_REGS_DRAMTMG10_t_sync_gear_MASK (0x1F0000U)
11218#define DDRC_REGS_DRAMTMG10_t_sync_gear_SHIFT (16U)
11219#define DDRC_REGS_DRAMTMG10_t_sync_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG10_t_sync_gear_SHIFT)) & DDRC_REGS_DRAMTMG10_t_sync_gear_MASK)
11220/*! @} */
11221
11222/*! @name DRAMTMG11 - SDRAM Timing Register 11 */
11223/*! @{ */
11224#define DDRC_REGS_DRAMTMG11_t_ckmpe_MASK (0x1FU)
11225#define DDRC_REGS_DRAMTMG11_t_ckmpe_SHIFT (0U)
11226#define DDRC_REGS_DRAMTMG11_t_ckmpe(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG11_t_ckmpe_SHIFT)) & DDRC_REGS_DRAMTMG11_t_ckmpe_MASK)
11227#define DDRC_REGS_DRAMTMG11_t_mpx_s_MASK (0x300U)
11228#define DDRC_REGS_DRAMTMG11_t_mpx_s_SHIFT (8U)
11229#define DDRC_REGS_DRAMTMG11_t_mpx_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG11_t_mpx_s_SHIFT)) & DDRC_REGS_DRAMTMG11_t_mpx_s_MASK)
11230#define DDRC_REGS_DRAMTMG11_t_mpx_lh_MASK (0x1F0000U)
11231#define DDRC_REGS_DRAMTMG11_t_mpx_lh_SHIFT (16U)
11232#define DDRC_REGS_DRAMTMG11_t_mpx_lh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG11_t_mpx_lh_SHIFT)) & DDRC_REGS_DRAMTMG11_t_mpx_lh_MASK)
11233#define DDRC_REGS_DRAMTMG11_post_mpsm_gap_x32_MASK (0x7F000000U)
11234#define DDRC_REGS_DRAMTMG11_post_mpsm_gap_x32_SHIFT (24U)
11235#define DDRC_REGS_DRAMTMG11_post_mpsm_gap_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG11_post_mpsm_gap_x32_SHIFT)) & DDRC_REGS_DRAMTMG11_post_mpsm_gap_x32_MASK)
11236/*! @} */
11237
11238/*! @name DRAMTMG12 - SDRAM Timing Register 12 */
11239/*! @{ */
11240#define DDRC_REGS_DRAMTMG12_t_mrd_pda_MASK (0x1FU)
11241#define DDRC_REGS_DRAMTMG12_t_mrd_pda_SHIFT (0U)
11242#define DDRC_REGS_DRAMTMG12_t_mrd_pda(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG12_t_mrd_pda_SHIFT)) & DDRC_REGS_DRAMTMG12_t_mrd_pda_MASK)
11243#define DDRC_REGS_DRAMTMG12_t_ckehcmd_MASK (0xF00U)
11244#define DDRC_REGS_DRAMTMG12_t_ckehcmd_SHIFT (8U)
11245#define DDRC_REGS_DRAMTMG12_t_ckehcmd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG12_t_ckehcmd_SHIFT)) & DDRC_REGS_DRAMTMG12_t_ckehcmd_MASK)
11246#define DDRC_REGS_DRAMTMG12_t_cmdcke_MASK (0x30000U)
11247#define DDRC_REGS_DRAMTMG12_t_cmdcke_SHIFT (16U)
11248#define DDRC_REGS_DRAMTMG12_t_cmdcke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG12_t_cmdcke_SHIFT)) & DDRC_REGS_DRAMTMG12_t_cmdcke_MASK)
11249/*! @} */
11250
11251/*! @name DRAMTMG13 - SDRAM Timing Register 13 */
11252/*! @{ */
11253#define DDRC_REGS_DRAMTMG13_t_ppd_MASK (0x7U)
11254#define DDRC_REGS_DRAMTMG13_t_ppd_SHIFT (0U)
11255#define DDRC_REGS_DRAMTMG13_t_ppd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG13_t_ppd_SHIFT)) & DDRC_REGS_DRAMTMG13_t_ppd_MASK)
11256#define DDRC_REGS_DRAMTMG13_t_ccd_mw_MASK (0x3F0000U)
11257#define DDRC_REGS_DRAMTMG13_t_ccd_mw_SHIFT (16U)
11258#define DDRC_REGS_DRAMTMG13_t_ccd_mw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG13_t_ccd_mw_SHIFT)) & DDRC_REGS_DRAMTMG13_t_ccd_mw_MASK)
11259#define DDRC_REGS_DRAMTMG13_odtloff_MASK (0x7F000000U)
11260#define DDRC_REGS_DRAMTMG13_odtloff_SHIFT (24U)
11261#define DDRC_REGS_DRAMTMG13_odtloff(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG13_odtloff_SHIFT)) & DDRC_REGS_DRAMTMG13_odtloff_MASK)
11262/*! @} */
11263
11264/*! @name DRAMTMG14 - SDRAM Timing Register 14 */
11265/*! @{ */
11266#define DDRC_REGS_DRAMTMG14_t_xsr_MASK (0xFFFU)
11267#define DDRC_REGS_DRAMTMG14_t_xsr_SHIFT (0U)
11268#define DDRC_REGS_DRAMTMG14_t_xsr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG14_t_xsr_SHIFT)) & DDRC_REGS_DRAMTMG14_t_xsr_MASK)
11269/*! @} */
11270
11271/*! @name DRAMTMG15 - SDRAM Timing Register 15 */
11272/*! @{ */
11273#define DDRC_REGS_DRAMTMG15_t_stab_x32_MASK (0xFFU)
11274#define DDRC_REGS_DRAMTMG15_t_stab_x32_SHIFT (0U)
11275#define DDRC_REGS_DRAMTMG15_t_stab_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG15_t_stab_x32_SHIFT)) & DDRC_REGS_DRAMTMG15_t_stab_x32_MASK)
11276#define DDRC_REGS_DRAMTMG15_en_dfi_lp_t_stab_MASK (0x80000000U)
11277#define DDRC_REGS_DRAMTMG15_en_dfi_lp_t_stab_SHIFT (31U)
11278/*! en_dfi_lp_t_stab - Enable DFI tSTAB
11279 * 0b0..Disable using tSTAB when exiting DFI LP
11280 * 0b1..Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power.
11281 */
11282#define DDRC_REGS_DRAMTMG15_en_dfi_lp_t_stab(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG15_en_dfi_lp_t_stab_SHIFT)) & DDRC_REGS_DRAMTMG15_en_dfi_lp_t_stab_MASK)
11283/*! @} */
11284
11285/*! @name ZQCTL0 - ZQ Control Register 0 */
11286/*! @{ */
11287#define DDRC_REGS_ZQCTL0_t_zq_short_nop_MASK (0x3FFU)
11288#define DDRC_REGS_ZQCTL0_t_zq_short_nop_SHIFT (0U)
11289#define DDRC_REGS_ZQCTL0_t_zq_short_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_t_zq_short_nop_SHIFT)) & DDRC_REGS_ZQCTL0_t_zq_short_nop_MASK)
11290#define DDRC_REGS_ZQCTL0_t_zq_long_nop_MASK (0x7FF0000U)
11291#define DDRC_REGS_ZQCTL0_t_zq_long_nop_SHIFT (16U)
11292#define DDRC_REGS_ZQCTL0_t_zq_long_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_t_zq_long_nop_SHIFT)) & DDRC_REGS_ZQCTL0_t_zq_long_nop_MASK)
11293#define DDRC_REGS_ZQCTL0_dis_mpsmx_zqcl_MASK (0x10000000U)
11294#define DDRC_REGS_ZQCTL0_dis_mpsmx_zqcl_SHIFT (28U)
11295/*! dis_mpsmx_zqcl - Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting MPSM mode.
11296 * 0b0..Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for designs supporting DDR4 devices.
11297 * 0b1..Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode.
11298 */
11299#define DDRC_REGS_ZQCTL0_dis_mpsmx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_dis_mpsmx_zqcl_SHIFT)) & DDRC_REGS_ZQCTL0_dis_mpsmx_zqcl_MASK)
11300#define DDRC_REGS_ZQCTL0_zq_resistor_shared_MASK (0x20000000U)
11301#define DDRC_REGS_ZQCTL0_zq_resistor_shared_SHIFT (29U)
11302/*! zq_resistor_shared - ZQ resistor sharing
11303 * 0b0..ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
11304 * 0b1..Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap.
11305 */
11306#define DDRC_REGS_ZQCTL0_zq_resistor_shared(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_zq_resistor_shared_SHIFT)) & DDRC_REGS_ZQCTL0_zq_resistor_shared_MASK)
11307#define DDRC_REGS_ZQCTL0_dis_srx_zqcl_MASK (0x40000000U)
11308#define DDRC_REGS_ZQCTL0_dis_srx_zqcl_SHIFT (30U)
11309/*! dis_srx_zqcl - Disable ZQCL/MPC
11310 * 0b0..Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
11311 * 0b1..Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode.
11312 */
11313#define DDRC_REGS_ZQCTL0_dis_srx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_dis_srx_zqcl_SHIFT)) & DDRC_REGS_ZQCTL0_dis_srx_zqcl_MASK)
11314#define DDRC_REGS_ZQCTL0_dis_auto_zq_MASK (0x80000000U)
11315#define DDRC_REGS_ZQCTL0_dis_auto_zq_SHIFT (31U)
11316/*! dis_auto_zq - Disable Auto ZQCS/MPC
11317 * 0b0..Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024.
11318 * 0b1..Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module.
11319 */
11320#define DDRC_REGS_ZQCTL0_dis_auto_zq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_dis_auto_zq_SHIFT)) & DDRC_REGS_ZQCTL0_dis_auto_zq_MASK)
11321/*! @} */
11322
11323/*! @name ZQCTL1 - ZQ Control Register 1 */
11324/*! @{ */
11325#define DDRC_REGS_ZQCTL1_t_zq_short_interval_x1024_MASK (0xFFFFFU)
11326#define DDRC_REGS_ZQCTL1_t_zq_short_interval_x1024_SHIFT (0U)
11327#define DDRC_REGS_ZQCTL1_t_zq_short_interval_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL1_t_zq_short_interval_x1024_SHIFT)) & DDRC_REGS_ZQCTL1_t_zq_short_interval_x1024_MASK)
11328#define DDRC_REGS_ZQCTL1_t_zq_reset_nop_MASK (0x3FF00000U)
11329#define DDRC_REGS_ZQCTL1_t_zq_reset_nop_SHIFT (20U)
11330#define DDRC_REGS_ZQCTL1_t_zq_reset_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL1_t_zq_reset_nop_SHIFT)) & DDRC_REGS_ZQCTL1_t_zq_reset_nop_MASK)
11331/*! @} */
11332
11333/*! @name ZQCTL2 - ZQ Control Register 2 */
11334/*! @{ */
11335#define DDRC_REGS_ZQCTL2_zq_reset_MASK (0x1U)
11336#define DDRC_REGS_ZQCTL2_zq_reset_SHIFT (0U)
11337#define DDRC_REGS_ZQCTL2_zq_reset(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL2_zq_reset_SHIFT)) & DDRC_REGS_ZQCTL2_zq_reset_MASK)
11338/*! @} */
11339
11340/*! @name ZQSTAT - ZQ Status Register */
11341/*! @{ */
11342#define DDRC_REGS_ZQSTAT_zq_reset_busy_MASK (0x1U)
11343#define DDRC_REGS_ZQSTAT_zq_reset_busy_SHIFT (0U)
11344/*! zq_reset_busy - SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRC accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high.
11345 * 0b0..Indicates that the SoC core can initiate a ZQ Reset operation
11346 * 0b1..Indicates that ZQ Reset operation is in progress
11347 */
11348#define DDRC_REGS_ZQSTAT_zq_reset_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQSTAT_zq_reset_busy_SHIFT)) & DDRC_REGS_ZQSTAT_zq_reset_busy_MASK)
11349/*! @} */
11350
11351/*! @name DFITMG0 - DFI Timing Register 0 */
11352/*! @{ */
11353#define DDRC_REGS_DFITMG0_dfi_tphy_wrlat_MASK (0x3FU)
11354#define DDRC_REGS_DFITMG0_dfi_tphy_wrlat_SHIFT (0U)
11355#define DDRC_REGS_DFITMG0_dfi_tphy_wrlat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_dfi_tphy_wrlat_SHIFT)) & DDRC_REGS_DFITMG0_dfi_tphy_wrlat_MASK)
11356#define DDRC_REGS_DFITMG0_dfi_tphy_wrdata_MASK (0x3F00U)
11357#define DDRC_REGS_DFITMG0_dfi_tphy_wrdata_SHIFT (8U)
11358#define DDRC_REGS_DFITMG0_dfi_tphy_wrdata(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_dfi_tphy_wrdata_SHIFT)) & DDRC_REGS_DFITMG0_dfi_tphy_wrdata_MASK)
11359#define DDRC_REGS_DFITMG0_dfi_wrdata_use_sdr_MASK (0x8000U)
11360#define DDRC_REGS_DFITMG0_dfi_wrdata_use_sdr_SHIFT (15U)
11361#define DDRC_REGS_DFITMG0_dfi_wrdata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_dfi_wrdata_use_sdr_SHIFT)) & DDRC_REGS_DFITMG0_dfi_wrdata_use_sdr_MASK)
11362#define DDRC_REGS_DFITMG0_dfi_t_rddata_en_MASK (0x7F0000U)
11363#define DDRC_REGS_DFITMG0_dfi_t_rddata_en_SHIFT (16U)
11364#define DDRC_REGS_DFITMG0_dfi_t_rddata_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_dfi_t_rddata_en_SHIFT)) & DDRC_REGS_DFITMG0_dfi_t_rddata_en_MASK)
11365#define DDRC_REGS_DFITMG0_dfi_rddata_use_sdr_MASK (0x800000U)
11366#define DDRC_REGS_DFITMG0_dfi_rddata_use_sdr_SHIFT (23U)
11367#define DDRC_REGS_DFITMG0_dfi_rddata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_dfi_rddata_use_sdr_SHIFT)) & DDRC_REGS_DFITMG0_dfi_rddata_use_sdr_MASK)
11368#define DDRC_REGS_DFITMG0_dfi_t_ctrl_delay_MASK (0x1F000000U)
11369#define DDRC_REGS_DFITMG0_dfi_t_ctrl_delay_SHIFT (24U)
11370#define DDRC_REGS_DFITMG0_dfi_t_ctrl_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_dfi_t_ctrl_delay_SHIFT)) & DDRC_REGS_DFITMG0_dfi_t_ctrl_delay_MASK)
11371/*! @} */
11372
11373/*! @name DFITMG1 - DFI Timing Register 1 */
11374/*! @{ */
11375#define DDRC_REGS_DFITMG1_dfi_t_dram_clk_enable_MASK (0x1FU)
11376#define DDRC_REGS_DFITMG1_dfi_t_dram_clk_enable_SHIFT (0U)
11377#define DDRC_REGS_DFITMG1_dfi_t_dram_clk_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_dfi_t_dram_clk_enable_SHIFT)) & DDRC_REGS_DFITMG1_dfi_t_dram_clk_enable_MASK)
11378#define DDRC_REGS_DFITMG1_dfi_t_dram_clk_disable_MASK (0x1F00U)
11379#define DDRC_REGS_DFITMG1_dfi_t_dram_clk_disable_SHIFT (8U)
11380#define DDRC_REGS_DFITMG1_dfi_t_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_dfi_t_dram_clk_disable_SHIFT)) & DDRC_REGS_DFITMG1_dfi_t_dram_clk_disable_MASK)
11381#define DDRC_REGS_DFITMG1_dfi_t_wrdata_delay_MASK (0x1F0000U)
11382#define DDRC_REGS_DFITMG1_dfi_t_wrdata_delay_SHIFT (16U)
11383#define DDRC_REGS_DFITMG1_dfi_t_wrdata_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_dfi_t_wrdata_delay_SHIFT)) & DDRC_REGS_DFITMG1_dfi_t_wrdata_delay_MASK)
11384#define DDRC_REGS_DFITMG1_dfi_t_parin_lat_MASK (0x3000000U)
11385#define DDRC_REGS_DFITMG1_dfi_t_parin_lat_SHIFT (24U)
11386#define DDRC_REGS_DFITMG1_dfi_t_parin_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_dfi_t_parin_lat_SHIFT)) & DDRC_REGS_DFITMG1_dfi_t_parin_lat_MASK)
11387#define DDRC_REGS_DFITMG1_dfi_t_cmd_lat_MASK (0xF0000000U)
11388#define DDRC_REGS_DFITMG1_dfi_t_cmd_lat_SHIFT (28U)
11389#define DDRC_REGS_DFITMG1_dfi_t_cmd_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_dfi_t_cmd_lat_SHIFT)) & DDRC_REGS_DFITMG1_dfi_t_cmd_lat_MASK)
11390/*! @} */
11391
11392/*! @name DFILPCFG0 - DFI Low Power Configuration Register 0 */
11393/*! @{ */
11394#define DDRC_REGS_DFILPCFG0_dfi_lp_en_pd_MASK (0x1U)
11395#define DDRC_REGS_DFILPCFG0_dfi_lp_en_pd_SHIFT (0U)
11396#define DDRC_REGS_DFILPCFG0_dfi_lp_en_pd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFILPCFG0_dfi_lp_en_pd_SHIFT)) & DDRC_REGS_DFILPCFG0_dfi_lp_en_pd_MASK)
11397#define DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_pd_MASK (0xF0U)
11398#define DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT (4U)
11399/*! dfi_lp_wakeup_pd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time:
11400 * 0b0000..16 cycles
11401 * 0b0001..32 cycles
11402 * 0b0010..64 cycles
11403 * 0b0011..128 cycles
11404 * 0b0100..256 cycles
11405 * 0b0101..512 cycles
11406 * 0b0110..1024 cycles
11407 * 0b0111..2048 cycles
11408 * 0b1000..4096 cycles
11409 * 0b1001..8192 cycles
11410 * 0b1010..16384 cycles
11411 * 0b1011..32768 cycles
11412 * 0b1100..65536 cycles
11413 * 0b1101..131072 cycles
11414 * 0b1110..262144 cycles
11415 * 0b1111..Unlimited cycles
11416 */
11417#define DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_pd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT)) & DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_pd_MASK)
11418#define DDRC_REGS_DFILPCFG0_dfi_lp_en_sr_MASK (0x100U)
11419#define DDRC_REGS_DFILPCFG0_dfi_lp_en_sr_SHIFT (8U)
11420/*! dfi_lp_en_sr - Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled
11421 * 0b0..Disabled
11422 * 0b1..Enabled
11423 */
11424#define DDRC_REGS_DFILPCFG0_dfi_lp_en_sr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFILPCFG0_dfi_lp_en_sr_SHIFT)) & DDRC_REGS_DFILPCFG0_dfi_lp_en_sr_MASK)
11425#define DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_sr_MASK (0xF000U)
11426#define DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT (12U)
11427/*! dfi_lp_wakeup_sr - Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time:
11428 * 0b0000..16 cycles
11429 * 0b0001..32 cycles
11430 * 0b0010..64 cycles
11431 * 0b0011..128 cycles
11432 * 0b0100..256 cycles
11433 * 0b0101..512 cycles
11434 * 0b0110..1024 cycles
11435 * 0b0111..2048 cycles
11436 * 0b1000..4096 cycles
11437 * 0b1001..8192 cycles
11438 * 0b1010..16384 cycles
11439 * 0b1011..32768 cycles
11440 * 0b1100..65536 cycles
11441 * 0b1101..131072 cycles
11442 * 0b1110..262144 cycles
11443 * 0b1111..Unlimited cycles
11444 */
11445#define DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_sr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT)) & DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_sr_MASK)
11446#define DDRC_REGS_DFILPCFG0_dfi_lp_en_dpd_MASK (0x10000U)
11447#define DDRC_REGS_DFILPCFG0_dfi_lp_en_dpd_SHIFT (16U)
11448#define DDRC_REGS_DFILPCFG0_dfi_lp_en_dpd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFILPCFG0_dfi_lp_en_dpd_SHIFT)) & DDRC_REGS_DFILPCFG0_dfi_lp_en_dpd_MASK)
11449#define DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_dpd_MASK (0xF00000U)
11450#define DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT (20U)
11451/*! dfi_lp_wakeup_dpd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices.
11452 * 0b0000..16 cycles
11453 * 0b0001..32 cycles
11454 * 0b0010..64 cycles
11455 * 0b0011..128 cycles
11456 * 0b0100..256 cycles
11457 * 0b0101..512 cycles
11458 * 0b0110..1024 cycles
11459 * 0b0111..2048 cycles
11460 * 0b1000..4096 cycles
11461 * 0b1001..8192 cycles
11462 * 0b1010..16384 cycles
11463 * 0b1011..32768 cycles
11464 * 0b1100..65536 cycles
11465 * 0b1101..131072 cycles
11466 * 0b1110..262144 cycles
11467 * 0b1111..Unlimited cycles
11468 */
11469#define DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_dpd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT)) & DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_dpd_MASK)
11470#define DDRC_REGS_DFILPCFG0_dfi_tlp_resp_MASK (0x1F000000U)
11471#define DDRC_REGS_DFILPCFG0_dfi_tlp_resp_SHIFT (24U)
11472#define DDRC_REGS_DFILPCFG0_dfi_tlp_resp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFILPCFG0_dfi_tlp_resp_SHIFT)) & DDRC_REGS_DFILPCFG0_dfi_tlp_resp_MASK)
11473/*! @} */
11474
11475/*! @name DFILPCFG1 - DFI Low Power Configuration Register 1 */
11476/*! @{ */
11477#define DDRC_REGS_DFILPCFG1_dfi_lp_en_mpsm_MASK (0x1U)
11478#define DDRC_REGS_DFILPCFG1_dfi_lp_en_mpsm_SHIFT (0U)
11479#define DDRC_REGS_DFILPCFG1_dfi_lp_en_mpsm(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFILPCFG1_dfi_lp_en_mpsm_SHIFT)) & DDRC_REGS_DFILPCFG1_dfi_lp_en_mpsm_MASK)
11480#define DDRC_REGS_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK (0xF0U)
11481#define DDRC_REGS_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT (4U)
11482/*! dfi_lp_wakeup_mpsm - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time:
11483 * 0b0000..16 cycles
11484 * 0b0001..32 cycles
11485 * 0b0010..64 cycles
11486 * 0b0011..128 cycles
11487 * 0b0100..256 cycles
11488 * 0b0101..512 cycles
11489 * 0b0110..1024 cycles
11490 * 0b0111..2048 cycles
11491 * 0b1000..4096 cycles
11492 * 0b1001..8192 cycles
11493 * 0b1010..16384 cycles
11494 * 0b1011..32768 cycles
11495 * 0b1100..65536 cycles
11496 * 0b1101..131072 cycles
11497 * 0b1110..262144 cycles
11498 * 0b1111..Unlimited cycles
11499 */
11500#define DDRC_REGS_DFILPCFG1_dfi_lp_wakeup_mpsm(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT)) & DDRC_REGS_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK)
11501/*! @} */
11502
11503/*! @name DFIUPD0 - DFI Update Register 0 */
11504/*! @{ */
11505#define DDRC_REGS_DFIUPD0_dfi_t_ctrlup_min_MASK (0x3FFU)
11506#define DDRC_REGS_DFIUPD0_dfi_t_ctrlup_min_SHIFT (0U)
11507#define DDRC_REGS_DFIUPD0_dfi_t_ctrlup_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIUPD0_dfi_t_ctrlup_min_SHIFT)) & DDRC_REGS_DFIUPD0_dfi_t_ctrlup_min_MASK)
11508#define DDRC_REGS_DFIUPD0_dfi_t_ctrlup_max_MASK (0x3FF0000U)
11509#define DDRC_REGS_DFIUPD0_dfi_t_ctrlup_max_SHIFT (16U)
11510#define DDRC_REGS_DFIUPD0_dfi_t_ctrlup_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIUPD0_dfi_t_ctrlup_max_SHIFT)) & DDRC_REGS_DFIUPD0_dfi_t_ctrlup_max_MASK)
11511#define DDRC_REGS_DFIUPD0_ctrlupd_pre_srx_MASK (0x20000000U)
11512#define DDRC_REGS_DFIUPD0_ctrlupd_pre_srx_SHIFT (29U)
11513/*! ctrlupd_pre_srx - Selects dfi_ctrlupd_req requirements at SRX: - 0 : send ctrlupd after SRX - 1 : send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact, because no dfi_ctrlupd_req will be issued when SRX.
11514 * 0b0..send ctrlupd after SRX
11515 * 0b1..send ctrlupd before SRX
11516 */
11517#define DDRC_REGS_DFIUPD0_ctrlupd_pre_srx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIUPD0_ctrlupd_pre_srx_SHIFT)) & DDRC_REGS_DFIUPD0_ctrlupd_pre_srx_MASK)
11518#define DDRC_REGS_DFIUPD0_dis_auto_ctrlupd_srx_MASK (0x40000000U)
11519#define DDRC_REGS_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT (30U)
11520/*! dis_auto_ctrlupd_srx - Auto ctrlupd request generation
11521 * 0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC at self-refresh exit.
11522 * 0b0..DDRC issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on DFIUPD0.ctrlupd_pre_srx.
11523 */
11524#define DDRC_REGS_DFIUPD0_dis_auto_ctrlupd_srx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT)) & DDRC_REGS_DFIUPD0_dis_auto_ctrlupd_srx_MASK)
11525#define DDRC_REGS_DFIUPD0_dis_auto_ctrlupd_MASK (0x80000000U)
11526#define DDRC_REGS_DFIUPD0_dis_auto_ctrlupd_SHIFT (31U)
11527/*! dis_auto_ctrlupd - automatic dfi_ctrlupd_req generation by the DDRC
11528 * 0b0..DDRC issues dfi_ctrlupd_req periodically.
11529 * 0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC. The core must issue the dfi_ctrlupd_req signal using register reg_ddrc_ctrlupd.
11530 */
11531#define DDRC_REGS_DFIUPD0_dis_auto_ctrlupd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIUPD0_dis_auto_ctrlupd_SHIFT)) & DDRC_REGS_DFIUPD0_dis_auto_ctrlupd_MASK)
11532/*! @} */
11533
11534/*! @name DFIUPD1 - DFI Update Register 1 */
11535/*! @{ */
11536#define DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK (0xFFU)
11537#define DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT (0U)
11538#define DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT)) & DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK)
11539#define DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK (0xFF0000U)
11540#define DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT (16U)
11541#define DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT)) & DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK)
11542/*! @} */
11543
11544/*! @name DFIUPD2 - DFI Update Register 2 */
11545/*! @{ */
11546#define DDRC_REGS_DFIUPD2_dfi_phyupd_en_MASK (0x80000000U)
11547#define DDRC_REGS_DFIUPD2_dfi_phyupd_en_SHIFT (31U)
11548/*! dfi_phyupd_en - Enables the support for acknowledging PHY-initiated updates:
11549 * 0b0..Disabled
11550 * 0b1..Enabled
11551 */
11552#define DDRC_REGS_DFIUPD2_dfi_phyupd_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIUPD2_dfi_phyupd_en_SHIFT)) & DDRC_REGS_DFIUPD2_dfi_phyupd_en_MASK)
11553/*! @} */
11554
11555/*! @name DFIMISC - DFI Miscellaneous Control Register */
11556/*! @{ */
11557#define DDRC_REGS_DFIMISC_dfi_init_complete_en_MASK (0x1U)
11558#define DDRC_REGS_DFIMISC_dfi_init_complete_en_SHIFT (0U)
11559#define DDRC_REGS_DFIMISC_dfi_init_complete_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIMISC_dfi_init_complete_en_SHIFT)) & DDRC_REGS_DFIMISC_dfi_init_complete_en_MASK)
11560#define DDRC_REGS_DFIMISC_phy_dbi_mode_MASK (0x2U)
11561#define DDRC_REGS_DFIMISC_phy_dbi_mode_SHIFT (1U)
11562/*! phy_dbi_mode - DBI implemented in DDRC or PHY. Present only in designs configured to support DDR4 and LPDDR4.
11563 * 0b0..DDRC implements DBI functionality.
11564 * 0b1..PHY implements DBI functionality.
11565 */
11566#define DDRC_REGS_DFIMISC_phy_dbi_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIMISC_phy_dbi_mode_SHIFT)) & DDRC_REGS_DFIMISC_phy_dbi_mode_MASK)
11567#define DDRC_REGS_DFIMISC_dfi_data_cs_polarity_MASK (0x4U)
11568#define DDRC_REGS_DFIMISC_dfi_data_cs_polarity_SHIFT (2U)
11569/*! dfi_data_cs_polarity - Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals.
11570 * 0b0..Signals are active low
11571 * 0b1..Signals are active high
11572 */
11573#define DDRC_REGS_DFIMISC_dfi_data_cs_polarity(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIMISC_dfi_data_cs_polarity_SHIFT)) & DDRC_REGS_DFIMISC_dfi_data_cs_polarity_MASK)
11574#define DDRC_REGS_DFIMISC_ctl_idle_en_MASK (0x10U)
11575#define DDRC_REGS_DFIMISC_ctl_idle_en_SHIFT (4U)
11576#define DDRC_REGS_DFIMISC_ctl_idle_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIMISC_ctl_idle_en_SHIFT)) & DDRC_REGS_DFIMISC_ctl_idle_en_MASK)
11577#define DDRC_REGS_DFIMISC_dfi_init_start_MASK (0x20U)
11578#define DDRC_REGS_DFIMISC_dfi_init_start_SHIFT (5U)
11579#define DDRC_REGS_DFIMISC_dfi_init_start(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIMISC_dfi_init_start_SHIFT)) & DDRC_REGS_DFIMISC_dfi_init_start_MASK)
11580#define DDRC_REGS_DFIMISC_dfi_frequency_MASK (0x1F00U)
11581#define DDRC_REGS_DFIMISC_dfi_frequency_SHIFT (8U)
11582#define DDRC_REGS_DFIMISC_dfi_frequency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIMISC_dfi_frequency_SHIFT)) & DDRC_REGS_DFIMISC_dfi_frequency_MASK)
11583/*! @} */
11584
11585/*! @name DFITMG2 - DFI Timing Register 2 */
11586/*! @{ */
11587#define DDRC_REGS_DFITMG2_dfi_tphy_wrcslat_MASK (0x3FU)
11588#define DDRC_REGS_DFITMG2_dfi_tphy_wrcslat_SHIFT (0U)
11589#define DDRC_REGS_DFITMG2_dfi_tphy_wrcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG2_dfi_tphy_wrcslat_SHIFT)) & DDRC_REGS_DFITMG2_dfi_tphy_wrcslat_MASK)
11590#define DDRC_REGS_DFITMG2_dfi_tphy_rdcslat_MASK (0x7F00U)
11591#define DDRC_REGS_DFITMG2_dfi_tphy_rdcslat_SHIFT (8U)
11592#define DDRC_REGS_DFITMG2_dfi_tphy_rdcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG2_dfi_tphy_rdcslat_SHIFT)) & DDRC_REGS_DFITMG2_dfi_tphy_rdcslat_MASK)
11593/*! @} */
11594
11595/*! @name DFITMG3 - DFI Timing Register 3 */
11596/*! @{ */
11597#define DDRC_REGS_DFITMG3_dfi_t_geardown_delay_MASK (0x1FU)
11598#define DDRC_REGS_DFITMG3_dfi_t_geardown_delay_SHIFT (0U)
11599#define DDRC_REGS_DFITMG3_dfi_t_geardown_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG3_dfi_t_geardown_delay_SHIFT)) & DDRC_REGS_DFITMG3_dfi_t_geardown_delay_MASK)
11600/*! @} */
11601
11602/*! @name DFISTAT - DFI Status Register */
11603/*! @{ */
11604#define DDRC_REGS_DFISTAT_dfi_init_complete_MASK (0x1U)
11605#define DDRC_REGS_DFISTAT_dfi_init_complete_SHIFT (0U)
11606#define DDRC_REGS_DFISTAT_dfi_init_complete(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFISTAT_dfi_init_complete_SHIFT)) & DDRC_REGS_DFISTAT_dfi_init_complete_MASK)
11607#define DDRC_REGS_DFISTAT_dfi_lp_ack_MASK (0x2U)
11608#define DDRC_REGS_DFISTAT_dfi_lp_ack_SHIFT (1U)
11609#define DDRC_REGS_DFISTAT_dfi_lp_ack(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFISTAT_dfi_lp_ack_SHIFT)) & DDRC_REGS_DFISTAT_dfi_lp_ack_MASK)
11610/*! @} */
11611
11612/*! @name DBICTL - DM/DBI Control Register */
11613/*! @{ */
11614#define DDRC_REGS_DBICTL_dm_en_MASK (0x1U)
11615#define DDRC_REGS_DBICTL_dm_en_SHIFT (0U)
11616/*! dm_en - DM enable signal in DDRC. This signal must be set the same logical value as DRAM's mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR4: Set this to inverted value of MR13[5] which is opposite polarity from this signal
11617 * 0b0..DM is disabled
11618 * 0b1..DM is enabled
11619 */
11620#define DDRC_REGS_DBICTL_dm_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBICTL_dm_en_SHIFT)) & DDRC_REGS_DBICTL_dm_en_MASK)
11621#define DDRC_REGS_DBICTL_wr_dbi_en_MASK (0x2U)
11622#define DDRC_REGS_DBICTL_wr_dbi_en_SHIFT (1U)
11623/*! wr_dbi_en - This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]
11624 * 0b0..Write DBI is disabled
11625 * 0b1..Write DBI is enabled.
11626 */
11627#define DDRC_REGS_DBICTL_wr_dbi_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBICTL_wr_dbi_en_SHIFT)) & DDRC_REGS_DBICTL_wr_dbi_en_MASK)
11628#define DDRC_REGS_DBICTL_rd_dbi_en_MASK (0x4U)
11629#define DDRC_REGS_DBICTL_rd_dbi_en_SHIFT (2U)
11630#define DDRC_REGS_DBICTL_rd_dbi_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBICTL_rd_dbi_en_SHIFT)) & DDRC_REGS_DBICTL_rd_dbi_en_MASK)
11631/*! @} */
11632
11633/*! @name ADDRMAP0 - Address Map Register 0 */
11634/*! @{ */
11635#define DDRC_REGS_ADDRMAP0_addrmap_cs_bit0_MASK (0x1FU)
11636#define DDRC_REGS_ADDRMAP0_addrmap_cs_bit0_SHIFT (0U)
11637#define DDRC_REGS_ADDRMAP0_addrmap_cs_bit0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP0_addrmap_cs_bit0_SHIFT)) & DDRC_REGS_ADDRMAP0_addrmap_cs_bit0_MASK)
11638/*! @} */
11639
11640/*! @name ADDRMAP1 - Address Map Register 1 */
11641/*! @{ */
11642#define DDRC_REGS_ADDRMAP1_addrmap_bank_b0_MASK (0x1FU)
11643#define DDRC_REGS_ADDRMAP1_addrmap_bank_b0_SHIFT (0U)
11644#define DDRC_REGS_ADDRMAP1_addrmap_bank_b0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP1_addrmap_bank_b0_SHIFT)) & DDRC_REGS_ADDRMAP1_addrmap_bank_b0_MASK)
11645#define DDRC_REGS_ADDRMAP1_addrmap_bank_b1_MASK (0x1F00U)
11646#define DDRC_REGS_ADDRMAP1_addrmap_bank_b1_SHIFT (8U)
11647#define DDRC_REGS_ADDRMAP1_addrmap_bank_b1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP1_addrmap_bank_b1_SHIFT)) & DDRC_REGS_ADDRMAP1_addrmap_bank_b1_MASK)
11648#define DDRC_REGS_ADDRMAP1_addrmap_bank_b2_MASK (0x1F0000U)
11649#define DDRC_REGS_ADDRMAP1_addrmap_bank_b2_SHIFT (16U)
11650#define DDRC_REGS_ADDRMAP1_addrmap_bank_b2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP1_addrmap_bank_b2_SHIFT)) & DDRC_REGS_ADDRMAP1_addrmap_bank_b2_MASK)
11651/*! @} */
11652
11653/*! @name ADDRMAP2 - Address Map Register 2 */
11654/*! @{ */
11655#define DDRC_REGS_ADDRMAP2_addrmap_col_b2_MASK (0xFU)
11656#define DDRC_REGS_ADDRMAP2_addrmap_col_b2_SHIFT (0U)
11657#define DDRC_REGS_ADDRMAP2_addrmap_col_b2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP2_addrmap_col_b2_SHIFT)) & DDRC_REGS_ADDRMAP2_addrmap_col_b2_MASK)
11658#define DDRC_REGS_ADDRMAP2_addrmap_col_b3_MASK (0xF00U)
11659#define DDRC_REGS_ADDRMAP2_addrmap_col_b3_SHIFT (8U)
11660#define DDRC_REGS_ADDRMAP2_addrmap_col_b3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP2_addrmap_col_b3_SHIFT)) & DDRC_REGS_ADDRMAP2_addrmap_col_b3_MASK)
11661#define DDRC_REGS_ADDRMAP2_addrmap_col_b4_MASK (0xF0000U)
11662#define DDRC_REGS_ADDRMAP2_addrmap_col_b4_SHIFT (16U)
11663#define DDRC_REGS_ADDRMAP2_addrmap_col_b4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP2_addrmap_col_b4_SHIFT)) & DDRC_REGS_ADDRMAP2_addrmap_col_b4_MASK)
11664#define DDRC_REGS_ADDRMAP2_addrmap_col_b5_MASK (0xF000000U)
11665#define DDRC_REGS_ADDRMAP2_addrmap_col_b5_SHIFT (24U)
11666#define DDRC_REGS_ADDRMAP2_addrmap_col_b5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP2_addrmap_col_b5_SHIFT)) & DDRC_REGS_ADDRMAP2_addrmap_col_b5_MASK)
11667/*! @} */
11668
11669/*! @name ADDRMAP3 - Address Map Register 3 */
11670/*! @{ */
11671#define DDRC_REGS_ADDRMAP3_addrmap_col_b6_MASK (0xFU)
11672#define DDRC_REGS_ADDRMAP3_addrmap_col_b6_SHIFT (0U)
11673#define DDRC_REGS_ADDRMAP3_addrmap_col_b6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP3_addrmap_col_b6_SHIFT)) & DDRC_REGS_ADDRMAP3_addrmap_col_b6_MASK)
11674#define DDRC_REGS_ADDRMAP3_addrmap_col_b7_MASK (0xF00U)
11675#define DDRC_REGS_ADDRMAP3_addrmap_col_b7_SHIFT (8U)
11676#define DDRC_REGS_ADDRMAP3_addrmap_col_b7(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP3_addrmap_col_b7_SHIFT)) & DDRC_REGS_ADDRMAP3_addrmap_col_b7_MASK)
11677#define DDRC_REGS_ADDRMAP3_addrmap_col_b8_MASK (0xF0000U)
11678#define DDRC_REGS_ADDRMAP3_addrmap_col_b8_SHIFT (16U)
11679#define DDRC_REGS_ADDRMAP3_addrmap_col_b8(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP3_addrmap_col_b8_SHIFT)) & DDRC_REGS_ADDRMAP3_addrmap_col_b8_MASK)
11680#define DDRC_REGS_ADDRMAP3_addrmap_col_b9_MASK (0xF000000U)
11681#define DDRC_REGS_ADDRMAP3_addrmap_col_b9_SHIFT (24U)
11682#define DDRC_REGS_ADDRMAP3_addrmap_col_b9(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP3_addrmap_col_b9_SHIFT)) & DDRC_REGS_ADDRMAP3_addrmap_col_b9_MASK)
11683/*! @} */
11684
11685/*! @name ADDRMAP4 - Address Map Register 4 */
11686/*! @{ */
11687#define DDRC_REGS_ADDRMAP4_addrmap_col_b10_MASK (0xFU)
11688#define DDRC_REGS_ADDRMAP4_addrmap_col_b10_SHIFT (0U)
11689#define DDRC_REGS_ADDRMAP4_addrmap_col_b10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP4_addrmap_col_b10_SHIFT)) & DDRC_REGS_ADDRMAP4_addrmap_col_b10_MASK)
11690#define DDRC_REGS_ADDRMAP4_addrmap_col_b11_MASK (0xF00U)
11691#define DDRC_REGS_ADDRMAP4_addrmap_col_b11_SHIFT (8U)
11692#define DDRC_REGS_ADDRMAP4_addrmap_col_b11(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP4_addrmap_col_b11_SHIFT)) & DDRC_REGS_ADDRMAP4_addrmap_col_b11_MASK)
11693/*! @} */
11694
11695/*! @name ADDRMAP5 - Address Map Register 5 */
11696/*! @{ */
11697#define DDRC_REGS_ADDRMAP5_addrmap_row_b0_MASK (0xFU)
11698#define DDRC_REGS_ADDRMAP5_addrmap_row_b0_SHIFT (0U)
11699#define DDRC_REGS_ADDRMAP5_addrmap_row_b0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP5_addrmap_row_b0_SHIFT)) & DDRC_REGS_ADDRMAP5_addrmap_row_b0_MASK)
11700#define DDRC_REGS_ADDRMAP5_addrmap_row_b1_MASK (0xF00U)
11701#define DDRC_REGS_ADDRMAP5_addrmap_row_b1_SHIFT (8U)
11702#define DDRC_REGS_ADDRMAP5_addrmap_row_b1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP5_addrmap_row_b1_SHIFT)) & DDRC_REGS_ADDRMAP5_addrmap_row_b1_MASK)
11703#define DDRC_REGS_ADDRMAP5_addrmap_row_b2_10_MASK (0xF0000U)
11704#define DDRC_REGS_ADDRMAP5_addrmap_row_b2_10_SHIFT (16U)
11705#define DDRC_REGS_ADDRMAP5_addrmap_row_b2_10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP5_addrmap_row_b2_10_SHIFT)) & DDRC_REGS_ADDRMAP5_addrmap_row_b2_10_MASK)
11706#define DDRC_REGS_ADDRMAP5_addrmap_row_b11_MASK (0xF000000U)
11707#define DDRC_REGS_ADDRMAP5_addrmap_row_b11_SHIFT (24U)
11708#define DDRC_REGS_ADDRMAP5_addrmap_row_b11(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP5_addrmap_row_b11_SHIFT)) & DDRC_REGS_ADDRMAP5_addrmap_row_b11_MASK)
11709/*! @} */
11710
11711/*! @name ADDRMAP6 - Address Map Register 6 */
11712/*! @{ */
11713#define DDRC_REGS_ADDRMAP6_addrmap_row_b12_MASK (0xFU)
11714#define DDRC_REGS_ADDRMAP6_addrmap_row_b12_SHIFT (0U)
11715#define DDRC_REGS_ADDRMAP6_addrmap_row_b12(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP6_addrmap_row_b12_SHIFT)) & DDRC_REGS_ADDRMAP6_addrmap_row_b12_MASK)
11716#define DDRC_REGS_ADDRMAP6_addrmap_row_b13_MASK (0xF00U)
11717#define DDRC_REGS_ADDRMAP6_addrmap_row_b13_SHIFT (8U)
11718#define DDRC_REGS_ADDRMAP6_addrmap_row_b13(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP6_addrmap_row_b13_SHIFT)) & DDRC_REGS_ADDRMAP6_addrmap_row_b13_MASK)
11719#define DDRC_REGS_ADDRMAP6_addrmap_row_b14_MASK (0xF0000U)
11720#define DDRC_REGS_ADDRMAP6_addrmap_row_b14_SHIFT (16U)
11721#define DDRC_REGS_ADDRMAP6_addrmap_row_b14(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP6_addrmap_row_b14_SHIFT)) & DDRC_REGS_ADDRMAP6_addrmap_row_b14_MASK)
11722#define DDRC_REGS_ADDRMAP6_addrmap_row_b15_MASK (0xF000000U)
11723#define DDRC_REGS_ADDRMAP6_addrmap_row_b15_SHIFT (24U)
11724#define DDRC_REGS_ADDRMAP6_addrmap_row_b15(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP6_addrmap_row_b15_SHIFT)) & DDRC_REGS_ADDRMAP6_addrmap_row_b15_MASK)
11725#define DDRC_REGS_ADDRMAP6_lpddr3_6gb_12gb_MASK (0x80000000U)
11726#define DDRC_REGS_ADDRMAP6_lpddr3_6gb_12gb_SHIFT (31U)
11727#define DDRC_REGS_ADDRMAP6_lpddr3_6gb_12gb(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP6_lpddr3_6gb_12gb_SHIFT)) & DDRC_REGS_ADDRMAP6_lpddr3_6gb_12gb_MASK)
11728/*! @} */
11729
11730/*! @name ADDRMAP7 - Address Map Register 7 */
11731/*! @{ */
11732#define DDRC_REGS_ADDRMAP7_addrmap_row_b16_MASK (0xFU)
11733#define DDRC_REGS_ADDRMAP7_addrmap_row_b16_SHIFT (0U)
11734#define DDRC_REGS_ADDRMAP7_addrmap_row_b16(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP7_addrmap_row_b16_SHIFT)) & DDRC_REGS_ADDRMAP7_addrmap_row_b16_MASK)
11735#define DDRC_REGS_ADDRMAP7_addrmap_row_b17_MASK (0xF00U)
11736#define DDRC_REGS_ADDRMAP7_addrmap_row_b17_SHIFT (8U)
11737#define DDRC_REGS_ADDRMAP7_addrmap_row_b17(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP7_addrmap_row_b17_SHIFT)) & DDRC_REGS_ADDRMAP7_addrmap_row_b17_MASK)
11738/*! @} */
11739
11740/*! @name ADDRMAP8 - Address Map Register 8 */
11741/*! @{ */
11742#define DDRC_REGS_ADDRMAP8_addrmap_bg_b0_MASK (0x1FU)
11743#define DDRC_REGS_ADDRMAP8_addrmap_bg_b0_SHIFT (0U)
11744#define DDRC_REGS_ADDRMAP8_addrmap_bg_b0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP8_addrmap_bg_b0_SHIFT)) & DDRC_REGS_ADDRMAP8_addrmap_bg_b0_MASK)
11745#define DDRC_REGS_ADDRMAP8_addrmap_bg_b1_MASK (0x3F00U)
11746#define DDRC_REGS_ADDRMAP8_addrmap_bg_b1_SHIFT (8U)
11747#define DDRC_REGS_ADDRMAP8_addrmap_bg_b1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP8_addrmap_bg_b1_SHIFT)) & DDRC_REGS_ADDRMAP8_addrmap_bg_b1_MASK)
11748/*! @} */
11749
11750/*! @name ADDRMAP9 - Address Map Register 9 */
11751/*! @{ */
11752#define DDRC_REGS_ADDRMAP9_addrmap_row_b2_MASK (0xFU)
11753#define DDRC_REGS_ADDRMAP9_addrmap_row_b2_SHIFT (0U)
11754#define DDRC_REGS_ADDRMAP9_addrmap_row_b2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP9_addrmap_row_b2_SHIFT)) & DDRC_REGS_ADDRMAP9_addrmap_row_b2_MASK)
11755#define DDRC_REGS_ADDRMAP9_addrmap_row_b3_MASK (0xF00U)
11756#define DDRC_REGS_ADDRMAP9_addrmap_row_b3_SHIFT (8U)
11757#define DDRC_REGS_ADDRMAP9_addrmap_row_b3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP9_addrmap_row_b3_SHIFT)) & DDRC_REGS_ADDRMAP9_addrmap_row_b3_MASK)
11758#define DDRC_REGS_ADDRMAP9_addrmap_row_b4_MASK (0xF0000U)
11759#define DDRC_REGS_ADDRMAP9_addrmap_row_b4_SHIFT (16U)
11760#define DDRC_REGS_ADDRMAP9_addrmap_row_b4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP9_addrmap_row_b4_SHIFT)) & DDRC_REGS_ADDRMAP9_addrmap_row_b4_MASK)
11761#define DDRC_REGS_ADDRMAP9_addrmap_row_b5_MASK (0xF000000U)
11762#define DDRC_REGS_ADDRMAP9_addrmap_row_b5_SHIFT (24U)
11763#define DDRC_REGS_ADDRMAP9_addrmap_row_b5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP9_addrmap_row_b5_SHIFT)) & DDRC_REGS_ADDRMAP9_addrmap_row_b5_MASK)
11764/*! @} */
11765
11766/*! @name ADDRMAP10 - Address Map Register 10 */
11767/*! @{ */
11768#define DDRC_REGS_ADDRMAP10_addrmap_row_b6_MASK (0xFU)
11769#define DDRC_REGS_ADDRMAP10_addrmap_row_b6_SHIFT (0U)
11770#define DDRC_REGS_ADDRMAP10_addrmap_row_b6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP10_addrmap_row_b6_SHIFT)) & DDRC_REGS_ADDRMAP10_addrmap_row_b6_MASK)
11771#define DDRC_REGS_ADDRMAP10_addrmap_row_b7_MASK (0xF00U)
11772#define DDRC_REGS_ADDRMAP10_addrmap_row_b7_SHIFT (8U)
11773#define DDRC_REGS_ADDRMAP10_addrmap_row_b7(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP10_addrmap_row_b7_SHIFT)) & DDRC_REGS_ADDRMAP10_addrmap_row_b7_MASK)
11774#define DDRC_REGS_ADDRMAP10_addrmap_row_b8_MASK (0xF0000U)
11775#define DDRC_REGS_ADDRMAP10_addrmap_row_b8_SHIFT (16U)
11776#define DDRC_REGS_ADDRMAP10_addrmap_row_b8(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP10_addrmap_row_b8_SHIFT)) & DDRC_REGS_ADDRMAP10_addrmap_row_b8_MASK)
11777#define DDRC_REGS_ADDRMAP10_addrmap_row_b9_MASK (0xF000000U)
11778#define DDRC_REGS_ADDRMAP10_addrmap_row_b9_SHIFT (24U)
11779#define DDRC_REGS_ADDRMAP10_addrmap_row_b9(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP10_addrmap_row_b9_SHIFT)) & DDRC_REGS_ADDRMAP10_addrmap_row_b9_MASK)
11780/*! @} */
11781
11782/*! @name ADDRMAP11 - Address Map Register 11 */
11783/*! @{ */
11784#define DDRC_REGS_ADDRMAP11_addrmap_row_b10_MASK (0xFU)
11785#define DDRC_REGS_ADDRMAP11_addrmap_row_b10_SHIFT (0U)
11786#define DDRC_REGS_ADDRMAP11_addrmap_row_b10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP11_addrmap_row_b10_SHIFT)) & DDRC_REGS_ADDRMAP11_addrmap_row_b10_MASK)
11787/*! @} */
11788
11789/*! @name ODTCFG - ODT Configuration Register */
11790/*! @{ */
11791#define DDRC_REGS_ODTCFG_rd_odt_delay_MASK (0x7CU)
11792#define DDRC_REGS_ODTCFG_rd_odt_delay_SHIFT (2U)
11793#define DDRC_REGS_ODTCFG_rd_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTCFG_rd_odt_delay_SHIFT)) & DDRC_REGS_ODTCFG_rd_odt_delay_MASK)
11794#define DDRC_REGS_ODTCFG_rd_odt_hold_MASK (0xF00U)
11795#define DDRC_REGS_ODTCFG_rd_odt_hold_SHIFT (8U)
11796#define DDRC_REGS_ODTCFG_rd_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTCFG_rd_odt_hold_SHIFT)) & DDRC_REGS_ODTCFG_rd_odt_hold_MASK)
11797#define DDRC_REGS_ODTCFG_wr_odt_delay_MASK (0x1F0000U)
11798#define DDRC_REGS_ODTCFG_wr_odt_delay_SHIFT (16U)
11799#define DDRC_REGS_ODTCFG_wr_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTCFG_wr_odt_delay_SHIFT)) & DDRC_REGS_ODTCFG_wr_odt_delay_MASK)
11800#define DDRC_REGS_ODTCFG_wr_odt_hold_MASK (0xF000000U)
11801#define DDRC_REGS_ODTCFG_wr_odt_hold_SHIFT (24U)
11802#define DDRC_REGS_ODTCFG_wr_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTCFG_wr_odt_hold_SHIFT)) & DDRC_REGS_ODTCFG_wr_odt_hold_MASK)
11803/*! @} */
11804
11805/*! @name ODTMAP - ODT/Rank Map Register */
11806/*! @{ */
11807#define DDRC_REGS_ODTMAP_rank0_wr_odt_MASK (0x3U)
11808#define DDRC_REGS_ODTMAP_rank0_wr_odt_SHIFT (0U)
11809#define DDRC_REGS_ODTMAP_rank0_wr_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTMAP_rank0_wr_odt_SHIFT)) & DDRC_REGS_ODTMAP_rank0_wr_odt_MASK)
11810#define DDRC_REGS_ODTMAP_rank0_rd_odt_MASK (0x30U)
11811#define DDRC_REGS_ODTMAP_rank0_rd_odt_SHIFT (4U)
11812#define DDRC_REGS_ODTMAP_rank0_rd_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTMAP_rank0_rd_odt_SHIFT)) & DDRC_REGS_ODTMAP_rank0_rd_odt_MASK)
11813#define DDRC_REGS_ODTMAP_rank1_wr_odt_MASK (0x300U)
11814#define DDRC_REGS_ODTMAP_rank1_wr_odt_SHIFT (8U)
11815#define DDRC_REGS_ODTMAP_rank1_wr_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTMAP_rank1_wr_odt_SHIFT)) & DDRC_REGS_ODTMAP_rank1_wr_odt_MASK)
11816#define DDRC_REGS_ODTMAP_rank1_rd_odt_MASK (0x3000U)
11817#define DDRC_REGS_ODTMAP_rank1_rd_odt_SHIFT (12U)
11818#define DDRC_REGS_ODTMAP_rank1_rd_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTMAP_rank1_rd_odt_SHIFT)) & DDRC_REGS_ODTMAP_rank1_rd_odt_MASK)
11819/*! @} */
11820
11821/*! @name SCHED - Scheduler Control Register */
11822/*! @{ */
11823#define DDRC_REGS_SCHED_force_low_pri_n_MASK (0x1U)
11824#define DDRC_REGS_SCHED_force_low_pri_n_SHIFT (0U)
11825#define DDRC_REGS_SCHED_force_low_pri_n(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_SCHED_force_low_pri_n_SHIFT)) & DDRC_REGS_SCHED_force_low_pri_n_MASK)
11826#define DDRC_REGS_SCHED_prefer_write_MASK (0x2U)
11827#define DDRC_REGS_SCHED_prefer_write_SHIFT (1U)
11828#define DDRC_REGS_SCHED_prefer_write(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_SCHED_prefer_write_SHIFT)) & DDRC_REGS_SCHED_prefer_write_MASK)
11829#define DDRC_REGS_SCHED_pageclose_MASK (0x4U)
11830#define DDRC_REGS_SCHED_pageclose_SHIFT (2U)
11831#define DDRC_REGS_SCHED_pageclose(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_SCHED_pageclose_SHIFT)) & DDRC_REGS_SCHED_pageclose_MASK)
11832#define DDRC_REGS_SCHED_lpr_num_entries_MASK (0x1F00U)
11833#define DDRC_REGS_SCHED_lpr_num_entries_SHIFT (8U)
11834#define DDRC_REGS_SCHED_lpr_num_entries(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_SCHED_lpr_num_entries_SHIFT)) & DDRC_REGS_SCHED_lpr_num_entries_MASK)
11835#define DDRC_REGS_SCHED_go2critical_hysteresis_MASK (0xFF0000U)
11836#define DDRC_REGS_SCHED_go2critical_hysteresis_SHIFT (16U)
11837#define DDRC_REGS_SCHED_go2critical_hysteresis(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_SCHED_go2critical_hysteresis_SHIFT)) & DDRC_REGS_SCHED_go2critical_hysteresis_MASK)
11838#define DDRC_REGS_SCHED_rdwr_idle_gap_MASK (0x7F000000U)
11839#define DDRC_REGS_SCHED_rdwr_idle_gap_SHIFT (24U)
11840#define DDRC_REGS_SCHED_rdwr_idle_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_SCHED_rdwr_idle_gap_SHIFT)) & DDRC_REGS_SCHED_rdwr_idle_gap_MASK)
11841/*! @} */
11842
11843/*! @name SCHED1 - Scheduler Control Register 1 */
11844/*! @{ */
11845#define DDRC_REGS_SCHED1_pageclose_timer_MASK (0xFFU)
11846#define DDRC_REGS_SCHED1_pageclose_timer_SHIFT (0U)
11847#define DDRC_REGS_SCHED1_pageclose_timer(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_SCHED1_pageclose_timer_SHIFT)) & DDRC_REGS_SCHED1_pageclose_timer_MASK)
11848/*! @} */
11849
11850/*! @name PERFHPR1 - High Priority Read CAM Register 1 */
11851/*! @{ */
11852#define DDRC_REGS_PERFHPR1_hpr_max_starve_MASK (0xFFFFU)
11853#define DDRC_REGS_PERFHPR1_hpr_max_starve_SHIFT (0U)
11854#define DDRC_REGS_PERFHPR1_hpr_max_starve(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PERFHPR1_hpr_max_starve_SHIFT)) & DDRC_REGS_PERFHPR1_hpr_max_starve_MASK)
11855#define DDRC_REGS_PERFHPR1_hpr_xact_run_length_MASK (0xFF000000U)
11856#define DDRC_REGS_PERFHPR1_hpr_xact_run_length_SHIFT (24U)
11857#define DDRC_REGS_PERFHPR1_hpr_xact_run_length(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PERFHPR1_hpr_xact_run_length_SHIFT)) & DDRC_REGS_PERFHPR1_hpr_xact_run_length_MASK)
11858/*! @} */
11859
11860/*! @name PERFLPR1 - Low Priority Read CAM Register 1 */
11861/*! @{ */
11862#define DDRC_REGS_PERFLPR1_lpr_max_starve_MASK (0xFFFFU)
11863#define DDRC_REGS_PERFLPR1_lpr_max_starve_SHIFT (0U)
11864#define DDRC_REGS_PERFLPR1_lpr_max_starve(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PERFLPR1_lpr_max_starve_SHIFT)) & DDRC_REGS_PERFLPR1_lpr_max_starve_MASK)
11865#define DDRC_REGS_PERFLPR1_lpr_xact_run_length_MASK (0xFF000000U)
11866#define DDRC_REGS_PERFLPR1_lpr_xact_run_length_SHIFT (24U)
11867#define DDRC_REGS_PERFLPR1_lpr_xact_run_length(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PERFLPR1_lpr_xact_run_length_SHIFT)) & DDRC_REGS_PERFLPR1_lpr_xact_run_length_MASK)
11868/*! @} */
11869
11870/*! @name PERFWR1 - Write CAM Register 1 */
11871/*! @{ */
11872#define DDRC_REGS_PERFWR1_w_max_starve_MASK (0xFFFFU)
11873#define DDRC_REGS_PERFWR1_w_max_starve_SHIFT (0U)
11874#define DDRC_REGS_PERFWR1_w_max_starve(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PERFWR1_w_max_starve_SHIFT)) & DDRC_REGS_PERFWR1_w_max_starve_MASK)
11875#define DDRC_REGS_PERFWR1_w_xact_run_length_MASK (0xFF000000U)
11876#define DDRC_REGS_PERFWR1_w_xact_run_length_SHIFT (24U)
11877#define DDRC_REGS_PERFWR1_w_xact_run_length(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PERFWR1_w_xact_run_length_SHIFT)) & DDRC_REGS_PERFWR1_w_xact_run_length_MASK)
11878/*! @} */
11879
11880/*! @name DBG0 - Debug Register 0 */
11881/*! @{ */
11882#define DDRC_REGS_DBG0_dis_wc_MASK (0x1U)
11883#define DDRC_REGS_DBG0_dis_wc_SHIFT (0U)
11884#define DDRC_REGS_DBG0_dis_wc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBG0_dis_wc_SHIFT)) & DDRC_REGS_DBG0_dis_wc_MASK)
11885#define DDRC_REGS_DBG0_dis_rd_bypass_MASK (0x2U)
11886#define DDRC_REGS_DBG0_dis_rd_bypass_SHIFT (1U)
11887#define DDRC_REGS_DBG0_dis_rd_bypass(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBG0_dis_rd_bypass_SHIFT)) & DDRC_REGS_DBG0_dis_rd_bypass_MASK)
11888#define DDRC_REGS_DBG0_dis_act_bypass_MASK (0x4U)
11889#define DDRC_REGS_DBG0_dis_act_bypass_SHIFT (2U)
11890#define DDRC_REGS_DBG0_dis_act_bypass(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBG0_dis_act_bypass_SHIFT)) & DDRC_REGS_DBG0_dis_act_bypass_MASK)
11891#define DDRC_REGS_DBG0_dis_collision_page_opt_MASK (0x10U)
11892#define DDRC_REGS_DBG0_dis_collision_page_opt_SHIFT (4U)
11893#define DDRC_REGS_DBG0_dis_collision_page_opt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBG0_dis_collision_page_opt_SHIFT)) & DDRC_REGS_DBG0_dis_collision_page_opt_MASK)
11894/*! @} */
11895
11896/*! @name DBG1 - Debug Register 1 */
11897/*! @{ */
11898#define DDRC_REGS_DBG1_dis_dq_MASK (0x1U)
11899#define DDRC_REGS_DBG1_dis_dq_SHIFT (0U)
11900#define DDRC_REGS_DBG1_dis_dq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBG1_dis_dq_SHIFT)) & DDRC_REGS_DBG1_dis_dq_MASK)
11901#define DDRC_REGS_DBG1_dis_hif_MASK (0x2U)
11902#define DDRC_REGS_DBG1_dis_hif_SHIFT (1U)
11903#define DDRC_REGS_DBG1_dis_hif(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBG1_dis_hif_SHIFT)) & DDRC_REGS_DBG1_dis_hif_MASK)
11904/*! @} */
11905
11906/*! @name DBGCAM - CAM Debug Register */
11907/*! @{ */
11908#define DDRC_REGS_DBGCAM_dbg_hpr_q_depth_MASK (0x3FU)
11909#define DDRC_REGS_DBGCAM_dbg_hpr_q_depth_SHIFT (0U)
11910#define DDRC_REGS_DBGCAM_dbg_hpr_q_depth(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_dbg_hpr_q_depth_SHIFT)) & DDRC_REGS_DBGCAM_dbg_hpr_q_depth_MASK)
11911#define DDRC_REGS_DBGCAM_dbg_lpr_q_depth_MASK (0x3F00U)
11912#define DDRC_REGS_DBGCAM_dbg_lpr_q_depth_SHIFT (8U)
11913#define DDRC_REGS_DBGCAM_dbg_lpr_q_depth(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_dbg_lpr_q_depth_SHIFT)) & DDRC_REGS_DBGCAM_dbg_lpr_q_depth_MASK)
11914#define DDRC_REGS_DBGCAM_dbg_w_q_depth_MASK (0x3F0000U)
11915#define DDRC_REGS_DBGCAM_dbg_w_q_depth_SHIFT (16U)
11916#define DDRC_REGS_DBGCAM_dbg_w_q_depth(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_dbg_w_q_depth_SHIFT)) & DDRC_REGS_DBGCAM_dbg_w_q_depth_MASK)
11917#define DDRC_REGS_DBGCAM_dbg_stall_MASK (0x1000000U)
11918#define DDRC_REGS_DBGCAM_dbg_stall_SHIFT (24U)
11919#define DDRC_REGS_DBGCAM_dbg_stall(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_dbg_stall_SHIFT)) & DDRC_REGS_DBGCAM_dbg_stall_MASK)
11920#define DDRC_REGS_DBGCAM_dbg_rd_q_empty_MASK (0x2000000U)
11921#define DDRC_REGS_DBGCAM_dbg_rd_q_empty_SHIFT (25U)
11922#define DDRC_REGS_DBGCAM_dbg_rd_q_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_dbg_rd_q_empty_SHIFT)) & DDRC_REGS_DBGCAM_dbg_rd_q_empty_MASK)
11923#define DDRC_REGS_DBGCAM_dbg_wr_q_empty_MASK (0x4000000U)
11924#define DDRC_REGS_DBGCAM_dbg_wr_q_empty_SHIFT (26U)
11925#define DDRC_REGS_DBGCAM_dbg_wr_q_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_dbg_wr_q_empty_SHIFT)) & DDRC_REGS_DBGCAM_dbg_wr_q_empty_MASK)
11926#define DDRC_REGS_DBGCAM_rd_data_pipeline_empty_MASK (0x10000000U)
11927#define DDRC_REGS_DBGCAM_rd_data_pipeline_empty_SHIFT (28U)
11928#define DDRC_REGS_DBGCAM_rd_data_pipeline_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_rd_data_pipeline_empty_SHIFT)) & DDRC_REGS_DBGCAM_rd_data_pipeline_empty_MASK)
11929#define DDRC_REGS_DBGCAM_wr_data_pipeline_empty_MASK (0x20000000U)
11930#define DDRC_REGS_DBGCAM_wr_data_pipeline_empty_SHIFT (29U)
11931#define DDRC_REGS_DBGCAM_wr_data_pipeline_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_wr_data_pipeline_empty_SHIFT)) & DDRC_REGS_DBGCAM_wr_data_pipeline_empty_MASK)
11932#define DDRC_REGS_DBGCAM_dbg_stall_wr_MASK (0x40000000U)
11933#define DDRC_REGS_DBGCAM_dbg_stall_wr_SHIFT (30U)
11934#define DDRC_REGS_DBGCAM_dbg_stall_wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_dbg_stall_wr_SHIFT)) & DDRC_REGS_DBGCAM_dbg_stall_wr_MASK)
11935#define DDRC_REGS_DBGCAM_dbg_stall_rd_MASK (0x80000000U)
11936#define DDRC_REGS_DBGCAM_dbg_stall_rd_SHIFT (31U)
11937#define DDRC_REGS_DBGCAM_dbg_stall_rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_dbg_stall_rd_SHIFT)) & DDRC_REGS_DBGCAM_dbg_stall_rd_MASK)
11938/*! @} */
11939
11940/*! @name DBGCMD - Command Debug Register */
11941/*! @{ */
11942#define DDRC_REGS_DBGCMD_rank0_refresh_MASK (0x1U)
11943#define DDRC_REGS_DBGCMD_rank0_refresh_SHIFT (0U)
11944#define DDRC_REGS_DBGCMD_rank0_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCMD_rank0_refresh_SHIFT)) & DDRC_REGS_DBGCMD_rank0_refresh_MASK)
11945#define DDRC_REGS_DBGCMD_rank1_refresh_MASK (0x2U)
11946#define DDRC_REGS_DBGCMD_rank1_refresh_SHIFT (1U)
11947#define DDRC_REGS_DBGCMD_rank1_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCMD_rank1_refresh_SHIFT)) & DDRC_REGS_DBGCMD_rank1_refresh_MASK)
11948#define DDRC_REGS_DBGCMD_zq_calib_short_MASK (0x10U)
11949#define DDRC_REGS_DBGCMD_zq_calib_short_SHIFT (4U)
11950#define DDRC_REGS_DBGCMD_zq_calib_short(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCMD_zq_calib_short_SHIFT)) & DDRC_REGS_DBGCMD_zq_calib_short_MASK)
11951#define DDRC_REGS_DBGCMD_ctrlupd_MASK (0x20U)
11952#define DDRC_REGS_DBGCMD_ctrlupd_SHIFT (5U)
11953#define DDRC_REGS_DBGCMD_ctrlupd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCMD_ctrlupd_SHIFT)) & DDRC_REGS_DBGCMD_ctrlupd_MASK)
11954/*! @} */
11955
11956/*! @name DBGSTAT - Status Debug Register */
11957/*! @{ */
11958#define DDRC_REGS_DBGSTAT_rank0_refresh_busy_MASK (0x1U)
11959#define DDRC_REGS_DBGSTAT_rank0_refresh_busy_SHIFT (0U)
11960#define DDRC_REGS_DBGSTAT_rank0_refresh_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGSTAT_rank0_refresh_busy_SHIFT)) & DDRC_REGS_DBGSTAT_rank0_refresh_busy_MASK)
11961#define DDRC_REGS_DBGSTAT_rank1_refresh_busy_MASK (0x2U)
11962#define DDRC_REGS_DBGSTAT_rank1_refresh_busy_SHIFT (1U)
11963#define DDRC_REGS_DBGSTAT_rank1_refresh_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGSTAT_rank1_refresh_busy_SHIFT)) & DDRC_REGS_DBGSTAT_rank1_refresh_busy_MASK)
11964#define DDRC_REGS_DBGSTAT_zq_calib_short_busy_MASK (0x10U)
11965#define DDRC_REGS_DBGSTAT_zq_calib_short_busy_SHIFT (4U)
11966#define DDRC_REGS_DBGSTAT_zq_calib_short_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGSTAT_zq_calib_short_busy_SHIFT)) & DDRC_REGS_DBGSTAT_zq_calib_short_busy_MASK)
11967#define DDRC_REGS_DBGSTAT_ctrlupd_busy_MASK (0x20U)
11968#define DDRC_REGS_DBGSTAT_ctrlupd_busy_SHIFT (5U)
11969#define DDRC_REGS_DBGSTAT_ctrlupd_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGSTAT_ctrlupd_busy_SHIFT)) & DDRC_REGS_DBGSTAT_ctrlupd_busy_MASK)
11970/*! @} */
11971
11972/*! @name SWCTL - Software Register Programming Control Enable */
11973/*! @{ */
11974#define DDRC_REGS_SWCTL_sw_done_MASK (0x1U)
11975#define DDRC_REGS_SWCTL_sw_done_SHIFT (0U)
11976#define DDRC_REGS_SWCTL_sw_done(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_SWCTL_sw_done_SHIFT)) & DDRC_REGS_SWCTL_sw_done_MASK)
11977/*! @} */
11978
11979/*! @name SWSTAT - Software Register Programming Control Status */
11980/*! @{ */
11981#define DDRC_REGS_SWSTAT_sw_done_ack_MASK (0x1U)
11982#define DDRC_REGS_SWSTAT_sw_done_ack_SHIFT (0U)
11983#define DDRC_REGS_SWSTAT_sw_done_ack(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_SWSTAT_sw_done_ack_SHIFT)) & DDRC_REGS_SWSTAT_sw_done_ack_MASK)
11984/*! @} */
11985
11986/*! @name POISONCFG - AXI Poison Configuration Register. */
11987/*! @{ */
11988#define DDRC_REGS_POISONCFG_wr_poison_slverr_en_MASK (0x1U)
11989#define DDRC_REGS_POISONCFG_wr_poison_slverr_en_SHIFT (0U)
11990#define DDRC_REGS_POISONCFG_wr_poison_slverr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_POISONCFG_wr_poison_slverr_en_SHIFT)) & DDRC_REGS_POISONCFG_wr_poison_slverr_en_MASK)
11991#define DDRC_REGS_POISONCFG_wr_poison_intr_en_MASK (0x10U)
11992#define DDRC_REGS_POISONCFG_wr_poison_intr_en_SHIFT (4U)
11993#define DDRC_REGS_POISONCFG_wr_poison_intr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_POISONCFG_wr_poison_intr_en_SHIFT)) & DDRC_REGS_POISONCFG_wr_poison_intr_en_MASK)
11994#define DDRC_REGS_POISONCFG_wr_poison_intr_clr_MASK (0x100U)
11995#define DDRC_REGS_POISONCFG_wr_poison_intr_clr_SHIFT (8U)
11996#define DDRC_REGS_POISONCFG_wr_poison_intr_clr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_POISONCFG_wr_poison_intr_clr_SHIFT)) & DDRC_REGS_POISONCFG_wr_poison_intr_clr_MASK)
11997#define DDRC_REGS_POISONCFG_rd_poison_slverr_en_MASK (0x10000U)
11998#define DDRC_REGS_POISONCFG_rd_poison_slverr_en_SHIFT (16U)
11999#define DDRC_REGS_POISONCFG_rd_poison_slverr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_POISONCFG_rd_poison_slverr_en_SHIFT)) & DDRC_REGS_POISONCFG_rd_poison_slverr_en_MASK)
12000#define DDRC_REGS_POISONCFG_rd_poison_intr_en_MASK (0x100000U)
12001#define DDRC_REGS_POISONCFG_rd_poison_intr_en_SHIFT (20U)
12002#define DDRC_REGS_POISONCFG_rd_poison_intr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_POISONCFG_rd_poison_intr_en_SHIFT)) & DDRC_REGS_POISONCFG_rd_poison_intr_en_MASK)
12003#define DDRC_REGS_POISONCFG_rd_poison_intr_clr_MASK (0x1000000U)
12004#define DDRC_REGS_POISONCFG_rd_poison_intr_clr_SHIFT (24U)
12005#define DDRC_REGS_POISONCFG_rd_poison_intr_clr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_POISONCFG_rd_poison_intr_clr_SHIFT)) & DDRC_REGS_POISONCFG_rd_poison_intr_clr_MASK)
12006/*! @} */
12007
12008/*! @name POISONSTAT - AXI Poison Status Register */
12009/*! @{ */
12010#define DDRC_REGS_POISONSTAT_wr_poison_intr_0_MASK (0x1U)
12011#define DDRC_REGS_POISONSTAT_wr_poison_intr_0_SHIFT (0U)
12012#define DDRC_REGS_POISONSTAT_wr_poison_intr_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_POISONSTAT_wr_poison_intr_0_SHIFT)) & DDRC_REGS_POISONSTAT_wr_poison_intr_0_MASK)
12013#define DDRC_REGS_POISONSTAT_rd_poison_intr_0_MASK (0x10000U)
12014#define DDRC_REGS_POISONSTAT_rd_poison_intr_0_SHIFT (16U)
12015#define DDRC_REGS_POISONSTAT_rd_poison_intr_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_POISONSTAT_rd_poison_intr_0_SHIFT)) & DDRC_REGS_POISONSTAT_rd_poison_intr_0_MASK)
12016/*! @} */
12017
12018/*! @name PSTAT - Port Status Register */
12019/*! @{ */
12020#define DDRC_REGS_PSTAT_rd_port_busy_0_MASK (0x1U)
12021#define DDRC_REGS_PSTAT_rd_port_busy_0_SHIFT (0U)
12022#define DDRC_REGS_PSTAT_rd_port_busy_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PSTAT_rd_port_busy_0_SHIFT)) & DDRC_REGS_PSTAT_rd_port_busy_0_MASK)
12023#define DDRC_REGS_PSTAT_wr_port_busy_0_MASK (0x10000U)
12024#define DDRC_REGS_PSTAT_wr_port_busy_0_SHIFT (16U)
12025#define DDRC_REGS_PSTAT_wr_port_busy_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PSTAT_wr_port_busy_0_SHIFT)) & DDRC_REGS_PSTAT_wr_port_busy_0_MASK)
12026/*! @} */
12027
12028/*! @name PCCFG - Port Common Configuration Register */
12029/*! @{ */
12030#define DDRC_REGS_PCCFG_go2critical_en_MASK (0x1U)
12031#define DDRC_REGS_PCCFG_go2critical_en_SHIFT (0U)
12032#define DDRC_REGS_PCCFG_go2critical_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCCFG_go2critical_en_SHIFT)) & DDRC_REGS_PCCFG_go2critical_en_MASK)
12033#define DDRC_REGS_PCCFG_pagematch_limit_MASK (0x10U)
12034#define DDRC_REGS_PCCFG_pagematch_limit_SHIFT (4U)
12035#define DDRC_REGS_PCCFG_pagematch_limit(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCCFG_pagematch_limit_SHIFT)) & DDRC_REGS_PCCFG_pagematch_limit_MASK)
12036#define DDRC_REGS_PCCFG_bl_exp_mode_MASK (0x100U)
12037#define DDRC_REGS_PCCFG_bl_exp_mode_SHIFT (8U)
12038#define DDRC_REGS_PCCFG_bl_exp_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCCFG_bl_exp_mode_SHIFT)) & DDRC_REGS_PCCFG_bl_exp_mode_MASK)
12039/*! @} */
12040
12041/*! @name PCFGR_0 - Port n Configuration Read Register */
12042/*! @{ */
12043#define DDRC_REGS_PCFGR_0_rd_port_priority_MASK (0x3FFU)
12044#define DDRC_REGS_PCFGR_0_rd_port_priority_SHIFT (0U)
12045#define DDRC_REGS_PCFGR_0_rd_port_priority(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGR_0_rd_port_priority_SHIFT)) & DDRC_REGS_PCFGR_0_rd_port_priority_MASK)
12046#define DDRC_REGS_PCFGR_0_rd_port_aging_en_MASK (0x1000U)
12047#define DDRC_REGS_PCFGR_0_rd_port_aging_en_SHIFT (12U)
12048#define DDRC_REGS_PCFGR_0_rd_port_aging_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGR_0_rd_port_aging_en_SHIFT)) & DDRC_REGS_PCFGR_0_rd_port_aging_en_MASK)
12049#define DDRC_REGS_PCFGR_0_rd_port_urgent_en_MASK (0x2000U)
12050#define DDRC_REGS_PCFGR_0_rd_port_urgent_en_SHIFT (13U)
12051#define DDRC_REGS_PCFGR_0_rd_port_urgent_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGR_0_rd_port_urgent_en_SHIFT)) & DDRC_REGS_PCFGR_0_rd_port_urgent_en_MASK)
12052#define DDRC_REGS_PCFGR_0_rd_port_pagematch_en_MASK (0x4000U)
12053#define DDRC_REGS_PCFGR_0_rd_port_pagematch_en_SHIFT (14U)
12054#define DDRC_REGS_PCFGR_0_rd_port_pagematch_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGR_0_rd_port_pagematch_en_SHIFT)) & DDRC_REGS_PCFGR_0_rd_port_pagematch_en_MASK)
12055#define DDRC_REGS_PCFGR_0_rdwr_ordered_en_MASK (0x10000U)
12056#define DDRC_REGS_PCFGR_0_rdwr_ordered_en_SHIFT (16U)
12057#define DDRC_REGS_PCFGR_0_rdwr_ordered_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGR_0_rdwr_ordered_en_SHIFT)) & DDRC_REGS_PCFGR_0_rdwr_ordered_en_MASK)
12058/*! @} */
12059
12060/*! @name PCFGW_0 - Port n Configuration Write Register */
12061/*! @{ */
12062#define DDRC_REGS_PCFGW_0_wr_port_priority_MASK (0x3FFU)
12063#define DDRC_REGS_PCFGW_0_wr_port_priority_SHIFT (0U)
12064#define DDRC_REGS_PCFGW_0_wr_port_priority(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGW_0_wr_port_priority_SHIFT)) & DDRC_REGS_PCFGW_0_wr_port_priority_MASK)
12065#define DDRC_REGS_PCFGW_0_wr_port_aging_en_MASK (0x1000U)
12066#define DDRC_REGS_PCFGW_0_wr_port_aging_en_SHIFT (12U)
12067#define DDRC_REGS_PCFGW_0_wr_port_aging_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGW_0_wr_port_aging_en_SHIFT)) & DDRC_REGS_PCFGW_0_wr_port_aging_en_MASK)
12068#define DDRC_REGS_PCFGW_0_wr_port_urgent_en_MASK (0x2000U)
12069#define DDRC_REGS_PCFGW_0_wr_port_urgent_en_SHIFT (13U)
12070#define DDRC_REGS_PCFGW_0_wr_port_urgent_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGW_0_wr_port_urgent_en_SHIFT)) & DDRC_REGS_PCFGW_0_wr_port_urgent_en_MASK)
12071#define DDRC_REGS_PCFGW_0_wr_port_pagematch_en_MASK (0x4000U)
12072#define DDRC_REGS_PCFGW_0_wr_port_pagematch_en_SHIFT (14U)
12073#define DDRC_REGS_PCFGW_0_wr_port_pagematch_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGW_0_wr_port_pagematch_en_SHIFT)) & DDRC_REGS_PCFGW_0_wr_port_pagematch_en_MASK)
12074/*! @} */
12075
12076/*! @name PCTRL_0 - Port n Control Register */
12077/*! @{ */
12078#define DDRC_REGS_PCTRL_0_port_en_MASK (0x1U)
12079#define DDRC_REGS_PCTRL_0_port_en_SHIFT (0U)
12080#define DDRC_REGS_PCTRL_0_port_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCTRL_0_port_en_SHIFT)) & DDRC_REGS_PCTRL_0_port_en_MASK)
12081/*! @} */
12082
12083/*! @name PCFGQOS0_0 - Port n Read QoS Configuration Register 0 */
12084/*! @{ */
12085#define DDRC_REGS_PCFGQOS0_0_rqos_map_level1_MASK (0xFU)
12086#define DDRC_REGS_PCFGQOS0_0_rqos_map_level1_SHIFT (0U)
12087#define DDRC_REGS_PCFGQOS0_0_rqos_map_level1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGQOS0_0_rqos_map_level1_SHIFT)) & DDRC_REGS_PCFGQOS0_0_rqos_map_level1_MASK)
12088#define DDRC_REGS_PCFGQOS0_0_rqos_map_region0_MASK (0x30000U)
12089#define DDRC_REGS_PCFGQOS0_0_rqos_map_region0_SHIFT (16U)
12090#define DDRC_REGS_PCFGQOS0_0_rqos_map_region0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGQOS0_0_rqos_map_region0_SHIFT)) & DDRC_REGS_PCFGQOS0_0_rqos_map_region0_MASK)
12091#define DDRC_REGS_PCFGQOS0_0_rqos_map_region1_MASK (0x300000U)
12092#define DDRC_REGS_PCFGQOS0_0_rqos_map_region1_SHIFT (20U)
12093#define DDRC_REGS_PCFGQOS0_0_rqos_map_region1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGQOS0_0_rqos_map_region1_SHIFT)) & DDRC_REGS_PCFGQOS0_0_rqos_map_region1_MASK)
12094/*! @} */
12095
12096/*! @name PCFGQOS1_0 - Port n Read QoS Configuration Register 1 */
12097/*! @{ */
12098#define DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutb_MASK (0x7FFU)
12099#define DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutb_SHIFT (0U)
12100#define DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutb(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutb_SHIFT)) & DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutb_MASK)
12101#define DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutr_MASK (0x7FF0000U)
12102#define DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutr_SHIFT (16U)
12103#define DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutr_SHIFT)) & DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutr_MASK)
12104/*! @} */
12105
12106/*! @name PCFGWQOS0_0 - Port n Write QoS Configuration Register 0 */
12107/*! @{ */
12108#define DDRC_REGS_PCFGWQOS0_0_wqos_map_level_MASK (0xFU)
12109#define DDRC_REGS_PCFGWQOS0_0_wqos_map_level_SHIFT (0U)
12110#define DDRC_REGS_PCFGWQOS0_0_wqos_map_level(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGWQOS0_0_wqos_map_level_SHIFT)) & DDRC_REGS_PCFGWQOS0_0_wqos_map_level_MASK)
12111#define DDRC_REGS_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U)
12112#define DDRC_REGS_PCFGWQOS0_0_wqos_map_region0_SHIFT (16U)
12113#define DDRC_REGS_PCFGWQOS0_0_wqos_map_region0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_REGS_PCFGWQOS0_0_wqos_map_region0_MASK)
12114#define DDRC_REGS_PCFGWQOS0_0_wqos_map_region1_MASK (0x300000U)
12115#define DDRC_REGS_PCFGWQOS0_0_wqos_map_region1_SHIFT (20U)
12116#define DDRC_REGS_PCFGWQOS0_0_wqos_map_region1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGWQOS0_0_wqos_map_region1_SHIFT)) & DDRC_REGS_PCFGWQOS0_0_wqos_map_region1_MASK)
12117/*! @} */
12118
12119/*! @name PCFGWQOS1_0 - Port n Write QoS Configuration Register 1 */
12120/*! @{ */
12121#define DDRC_REGS_PCFGWQOS1_0_wqos_map_timeout_MASK (0x7FFU)
12122#define DDRC_REGS_PCFGWQOS1_0_wqos_map_timeout_SHIFT (0U)
12123#define DDRC_REGS_PCFGWQOS1_0_wqos_map_timeout(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGWQOS1_0_wqos_map_timeout_SHIFT)) & DDRC_REGS_PCFGWQOS1_0_wqos_map_timeout_MASK)
12124/*! @} */
12125
12126/*! @name DERATEEN_SHADOW - [SHADOW] Temperature Derate Enable Register */
12127/*! @{ */
12128#define DDRC_REGS_DERATEEN_SHADOW_derate_enable_MASK (0x1U)
12129#define DDRC_REGS_DERATEEN_SHADOW_derate_enable_SHIFT (0U)
12130#define DDRC_REGS_DERATEEN_SHADOW_derate_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEEN_SHADOW_derate_enable_SHIFT)) & DDRC_REGS_DERATEEN_SHADOW_derate_enable_MASK)
12131#define DDRC_REGS_DERATEEN_SHADOW_derate_value_MASK (0x2U)
12132#define DDRC_REGS_DERATEEN_SHADOW_derate_value_SHIFT (1U)
12133#define DDRC_REGS_DERATEEN_SHADOW_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEEN_SHADOW_derate_value_SHIFT)) & DDRC_REGS_DERATEEN_SHADOW_derate_value_MASK)
12134#define DDRC_REGS_DERATEEN_SHADOW_derate_byte_MASK (0xF0U)
12135#define DDRC_REGS_DERATEEN_SHADOW_derate_byte_SHIFT (4U)
12136#define DDRC_REGS_DERATEEN_SHADOW_derate_byte(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEEN_SHADOW_derate_byte_SHIFT)) & DDRC_REGS_DERATEEN_SHADOW_derate_byte_MASK)
12137#define DDRC_REGS_DERATEEN_SHADOW_rc_derate_value_MASK (0x300U)
12138#define DDRC_REGS_DERATEEN_SHADOW_rc_derate_value_SHIFT (8U)
12139#define DDRC_REGS_DERATEEN_SHADOW_rc_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEEN_SHADOW_rc_derate_value_SHIFT)) & DDRC_REGS_DERATEEN_SHADOW_rc_derate_value_MASK)
12140/*! @} */
12141
12142/*! @name DERATEINT_SHADOW - [SHADOW] Temperature Derate Interval Register */
12143/*! @{ */
12144#define DDRC_REGS_DERATEINT_SHADOW_mr4_read_interval_MASK (0xFFFFFFFFU)
12145#define DDRC_REGS_DERATEINT_SHADOW_mr4_read_interval_SHIFT (0U)
12146#define DDRC_REGS_DERATEINT_SHADOW_mr4_read_interval(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEINT_SHADOW_mr4_read_interval_SHIFT)) & DDRC_REGS_DERATEINT_SHADOW_mr4_read_interval_MASK)
12147/*! @} */
12148
12149/*! @name RFSHCTL0_SHADOW - [SHADOW] Refresh Control Register 0 */
12150/*! @{ */
12151#define DDRC_REGS_RFSHCTL0_SHADOW_per_bank_refresh_MASK (0x4U)
12152#define DDRC_REGS_RFSHCTL0_SHADOW_per_bank_refresh_SHIFT (2U)
12153#define DDRC_REGS_RFSHCTL0_SHADOW_per_bank_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL0_SHADOW_per_bank_refresh_SHIFT)) & DDRC_REGS_RFSHCTL0_SHADOW_per_bank_refresh_MASK)
12154#define DDRC_REGS_RFSHCTL0_SHADOW_refresh_burst_MASK (0x1F0U)
12155#define DDRC_REGS_RFSHCTL0_SHADOW_refresh_burst_SHIFT (4U)
12156#define DDRC_REGS_RFSHCTL0_SHADOW_refresh_burst(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL0_SHADOW_refresh_burst_SHIFT)) & DDRC_REGS_RFSHCTL0_SHADOW_refresh_burst_MASK)
12157#define DDRC_REGS_RFSHCTL0_SHADOW_refresh_to_x32_MASK (0x1F000U)
12158#define DDRC_REGS_RFSHCTL0_SHADOW_refresh_to_x32_SHIFT (12U)
12159#define DDRC_REGS_RFSHCTL0_SHADOW_refresh_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL0_SHADOW_refresh_to_x32_SHIFT)) & DDRC_REGS_RFSHCTL0_SHADOW_refresh_to_x32_MASK)
12160#define DDRC_REGS_RFSHCTL0_SHADOW_refresh_margin_MASK (0xF00000U)
12161#define DDRC_REGS_RFSHCTL0_SHADOW_refresh_margin_SHIFT (20U)
12162#define DDRC_REGS_RFSHCTL0_SHADOW_refresh_margin(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL0_SHADOW_refresh_margin_SHIFT)) & DDRC_REGS_RFSHCTL0_SHADOW_refresh_margin_MASK)
12163/*! @} */
12164
12165/*! @name RFSHTMG_SHADOW - [SHADOW] Refresh Timing Register */
12166/*! @{ */
12167#define DDRC_REGS_RFSHTMG_SHADOW_t_rfc_min_MASK (0x3FFU)
12168#define DDRC_REGS_RFSHTMG_SHADOW_t_rfc_min_SHIFT (0U)
12169#define DDRC_REGS_RFSHTMG_SHADOW_t_rfc_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHTMG_SHADOW_t_rfc_min_SHIFT)) & DDRC_REGS_RFSHTMG_SHADOW_t_rfc_min_MASK)
12170#define DDRC_REGS_RFSHTMG_SHADOW_lpddr3_trefbw_en_MASK (0x8000U)
12171#define DDRC_REGS_RFSHTMG_SHADOW_lpddr3_trefbw_en_SHIFT (15U)
12172#define DDRC_REGS_RFSHTMG_SHADOW_lpddr3_trefbw_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHTMG_SHADOW_lpddr3_trefbw_en_SHIFT)) & DDRC_REGS_RFSHTMG_SHADOW_lpddr3_trefbw_en_MASK)
12173#define DDRC_REGS_RFSHTMG_SHADOW_t_rfc_nom_x32_MASK (0xFFF0000U)
12174#define DDRC_REGS_RFSHTMG_SHADOW_t_rfc_nom_x32_SHIFT (16U)
12175#define DDRC_REGS_RFSHTMG_SHADOW_t_rfc_nom_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHTMG_SHADOW_t_rfc_nom_x32_SHIFT)) & DDRC_REGS_RFSHTMG_SHADOW_t_rfc_nom_x32_MASK)
12176/*! @} */
12177
12178/*! @name INIT3_SHADOW - [SHADOW] SDRAM Initialization Register 3 */
12179/*! @{ */
12180#define DDRC_REGS_INIT3_SHADOW_emr_MASK (0xFFFFU)
12181#define DDRC_REGS_INIT3_SHADOW_emr_SHIFT (0U)
12182#define DDRC_REGS_INIT3_SHADOW_emr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT3_SHADOW_emr_SHIFT)) & DDRC_REGS_INIT3_SHADOW_emr_MASK)
12183#define DDRC_REGS_INIT3_SHADOW_mr_MASK (0xFFFF0000U)
12184#define DDRC_REGS_INIT3_SHADOW_mr_SHIFT (16U)
12185#define DDRC_REGS_INIT3_SHADOW_mr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT3_SHADOW_mr_SHIFT)) & DDRC_REGS_INIT3_SHADOW_mr_MASK)
12186/*! @} */
12187
12188/*! @name INIT4_SHADOW - [SHADOW] SDRAM Initialization Register 4 */
12189/*! @{ */
12190#define DDRC_REGS_INIT4_SHADOW_emr3_MASK (0xFFFFU)
12191#define DDRC_REGS_INIT4_SHADOW_emr3_SHIFT (0U)
12192#define DDRC_REGS_INIT4_SHADOW_emr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT4_SHADOW_emr3_SHIFT)) & DDRC_REGS_INIT4_SHADOW_emr3_MASK)
12193#define DDRC_REGS_INIT4_SHADOW_emr2_MASK (0xFFFF0000U)
12194#define DDRC_REGS_INIT4_SHADOW_emr2_SHIFT (16U)
12195#define DDRC_REGS_INIT4_SHADOW_emr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT4_SHADOW_emr2_SHIFT)) & DDRC_REGS_INIT4_SHADOW_emr2_MASK)
12196/*! @} */
12197
12198/*! @name INIT6_SHADOW - [SHADOW] SDRAM Initialization Register 6 */
12199/*! @{ */
12200#define DDRC_REGS_INIT6_SHADOW_mr5_MASK (0xFFFFU)
12201#define DDRC_REGS_INIT6_SHADOW_mr5_SHIFT (0U)
12202#define DDRC_REGS_INIT6_SHADOW_mr5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT6_SHADOW_mr5_SHIFT)) & DDRC_REGS_INIT6_SHADOW_mr5_MASK)
12203#define DDRC_REGS_INIT6_SHADOW_mr4_MASK (0xFFFF0000U)
12204#define DDRC_REGS_INIT6_SHADOW_mr4_SHIFT (16U)
12205#define DDRC_REGS_INIT6_SHADOW_mr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT6_SHADOW_mr4_SHIFT)) & DDRC_REGS_INIT6_SHADOW_mr4_MASK)
12206/*! @} */
12207
12208/*! @name INIT7_SHADOW - [SHADOW] SDRAM Initialization Register 7 */
12209/*! @{ */
12210#define DDRC_REGS_INIT7_SHADOW_mr6_MASK (0xFFFF0000U)
12211#define DDRC_REGS_INIT7_SHADOW_mr6_SHIFT (16U)
12212#define DDRC_REGS_INIT7_SHADOW_mr6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT7_SHADOW_mr6_SHIFT)) & DDRC_REGS_INIT7_SHADOW_mr6_MASK)
12213/*! @} */
12214
12215/*! @name DRAMTMG0_SHADOW - [SHADOW] SDRAM Timing Register 0 */
12216/*! @{ */
12217#define DDRC_REGS_DRAMTMG0_SHADOW_t_ras_min_MASK (0x3FU)
12218#define DDRC_REGS_DRAMTMG0_SHADOW_t_ras_min_SHIFT (0U)
12219#define DDRC_REGS_DRAMTMG0_SHADOW_t_ras_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG0_SHADOW_t_ras_min_SHIFT)) & DDRC_REGS_DRAMTMG0_SHADOW_t_ras_min_MASK)
12220#define DDRC_REGS_DRAMTMG0_SHADOW_t_ras_max_MASK (0x7F00U)
12221#define DDRC_REGS_DRAMTMG0_SHADOW_t_ras_max_SHIFT (8U)
12222#define DDRC_REGS_DRAMTMG0_SHADOW_t_ras_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG0_SHADOW_t_ras_max_SHIFT)) & DDRC_REGS_DRAMTMG0_SHADOW_t_ras_max_MASK)
12223#define DDRC_REGS_DRAMTMG0_SHADOW_t_faw_MASK (0x3F0000U)
12224#define DDRC_REGS_DRAMTMG0_SHADOW_t_faw_SHIFT (16U)
12225#define DDRC_REGS_DRAMTMG0_SHADOW_t_faw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG0_SHADOW_t_faw_SHIFT)) & DDRC_REGS_DRAMTMG0_SHADOW_t_faw_MASK)
12226#define DDRC_REGS_DRAMTMG0_SHADOW_wr2pre_MASK (0x7F000000U)
12227#define DDRC_REGS_DRAMTMG0_SHADOW_wr2pre_SHIFT (24U)
12228#define DDRC_REGS_DRAMTMG0_SHADOW_wr2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG0_SHADOW_wr2pre_SHIFT)) & DDRC_REGS_DRAMTMG0_SHADOW_wr2pre_MASK)
12229/*! @} */
12230
12231/*! @name DRAMTMG1_SHADOW - [SHADOW] SDRAM Timing Register 1 */
12232/*! @{ */
12233#define DDRC_REGS_DRAMTMG1_SHADOW_t_rc_MASK (0x7FU)
12234#define DDRC_REGS_DRAMTMG1_SHADOW_t_rc_SHIFT (0U)
12235#define DDRC_REGS_DRAMTMG1_SHADOW_t_rc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG1_SHADOW_t_rc_SHIFT)) & DDRC_REGS_DRAMTMG1_SHADOW_t_rc_MASK)
12236#define DDRC_REGS_DRAMTMG1_SHADOW_rd2pre_MASK (0x3F00U)
12237#define DDRC_REGS_DRAMTMG1_SHADOW_rd2pre_SHIFT (8U)
12238#define DDRC_REGS_DRAMTMG1_SHADOW_rd2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG1_SHADOW_rd2pre_SHIFT)) & DDRC_REGS_DRAMTMG1_SHADOW_rd2pre_MASK)
12239#define DDRC_REGS_DRAMTMG1_SHADOW_t_xp_MASK (0x1F0000U)
12240#define DDRC_REGS_DRAMTMG1_SHADOW_t_xp_SHIFT (16U)
12241#define DDRC_REGS_DRAMTMG1_SHADOW_t_xp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG1_SHADOW_t_xp_SHIFT)) & DDRC_REGS_DRAMTMG1_SHADOW_t_xp_MASK)
12242/*! @} */
12243
12244/*! @name DRAMTMG2_SHADOW - [SHADOW] SDRAM Timing Register 2 */
12245/*! @{ */
12246#define DDRC_REGS_DRAMTMG2_SHADOW_wr2rd_MASK (0x3FU)
12247#define DDRC_REGS_DRAMTMG2_SHADOW_wr2rd_SHIFT (0U)
12248#define DDRC_REGS_DRAMTMG2_SHADOW_wr2rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG2_SHADOW_wr2rd_SHIFT)) & DDRC_REGS_DRAMTMG2_SHADOW_wr2rd_MASK)
12249#define DDRC_REGS_DRAMTMG2_SHADOW_rd2wr_MASK (0x3F00U)
12250#define DDRC_REGS_DRAMTMG2_SHADOW_rd2wr_SHIFT (8U)
12251#define DDRC_REGS_DRAMTMG2_SHADOW_rd2wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG2_SHADOW_rd2wr_SHIFT)) & DDRC_REGS_DRAMTMG2_SHADOW_rd2wr_MASK)
12252#define DDRC_REGS_DRAMTMG2_SHADOW_read_latency_MASK (0x3F0000U)
12253#define DDRC_REGS_DRAMTMG2_SHADOW_read_latency_SHIFT (16U)
12254#define DDRC_REGS_DRAMTMG2_SHADOW_read_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG2_SHADOW_read_latency_SHIFT)) & DDRC_REGS_DRAMTMG2_SHADOW_read_latency_MASK)
12255#define DDRC_REGS_DRAMTMG2_SHADOW_write_latency_MASK (0x3F000000U)
12256#define DDRC_REGS_DRAMTMG2_SHADOW_write_latency_SHIFT (24U)
12257#define DDRC_REGS_DRAMTMG2_SHADOW_write_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG2_SHADOW_write_latency_SHIFT)) & DDRC_REGS_DRAMTMG2_SHADOW_write_latency_MASK)
12258/*! @} */
12259
12260/*! @name DRAMTMG3_SHADOW - [SHADOW] SDRAM Timing Register 3 */
12261/*! @{ */
12262#define DDRC_REGS_DRAMTMG3_SHADOW_t_mod_MASK (0x3FFU)
12263#define DDRC_REGS_DRAMTMG3_SHADOW_t_mod_SHIFT (0U)
12264#define DDRC_REGS_DRAMTMG3_SHADOW_t_mod(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG3_SHADOW_t_mod_SHIFT)) & DDRC_REGS_DRAMTMG3_SHADOW_t_mod_MASK)
12265#define DDRC_REGS_DRAMTMG3_SHADOW_t_mrd_MASK (0x3F000U)
12266#define DDRC_REGS_DRAMTMG3_SHADOW_t_mrd_SHIFT (12U)
12267#define DDRC_REGS_DRAMTMG3_SHADOW_t_mrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG3_SHADOW_t_mrd_SHIFT)) & DDRC_REGS_DRAMTMG3_SHADOW_t_mrd_MASK)
12268#define DDRC_REGS_DRAMTMG3_SHADOW_t_mrw_MASK (0x3FF00000U)
12269#define DDRC_REGS_DRAMTMG3_SHADOW_t_mrw_SHIFT (20U)
12270#define DDRC_REGS_DRAMTMG3_SHADOW_t_mrw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG3_SHADOW_t_mrw_SHIFT)) & DDRC_REGS_DRAMTMG3_SHADOW_t_mrw_MASK)
12271/*! @} */
12272
12273/*! @name DRAMTMG4_SHADOW - [SHADOW] SDRAM Timing Register 4 */
12274/*! @{ */
12275#define DDRC_REGS_DRAMTMG4_SHADOW_t_rp_MASK (0x1FU)
12276#define DDRC_REGS_DRAMTMG4_SHADOW_t_rp_SHIFT (0U)
12277#define DDRC_REGS_DRAMTMG4_SHADOW_t_rp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG4_SHADOW_t_rp_SHIFT)) & DDRC_REGS_DRAMTMG4_SHADOW_t_rp_MASK)
12278#define DDRC_REGS_DRAMTMG4_SHADOW_t_rrd_MASK (0xF00U)
12279#define DDRC_REGS_DRAMTMG4_SHADOW_t_rrd_SHIFT (8U)
12280#define DDRC_REGS_DRAMTMG4_SHADOW_t_rrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG4_SHADOW_t_rrd_SHIFT)) & DDRC_REGS_DRAMTMG4_SHADOW_t_rrd_MASK)
12281#define DDRC_REGS_DRAMTMG4_SHADOW_t_ccd_MASK (0xF0000U)
12282#define DDRC_REGS_DRAMTMG4_SHADOW_t_ccd_SHIFT (16U)
12283#define DDRC_REGS_DRAMTMG4_SHADOW_t_ccd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG4_SHADOW_t_ccd_SHIFT)) & DDRC_REGS_DRAMTMG4_SHADOW_t_ccd_MASK)
12284#define DDRC_REGS_DRAMTMG4_SHADOW_t_rcd_MASK (0x1F000000U)
12285#define DDRC_REGS_DRAMTMG4_SHADOW_t_rcd_SHIFT (24U)
12286#define DDRC_REGS_DRAMTMG4_SHADOW_t_rcd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG4_SHADOW_t_rcd_SHIFT)) & DDRC_REGS_DRAMTMG4_SHADOW_t_rcd_MASK)
12287/*! @} */
12288
12289/*! @name DRAMTMG5_SHADOW - [SHADOW] SDRAM Timing Register 5 */
12290/*! @{ */
12291#define DDRC_REGS_DRAMTMG5_SHADOW_t_cke_MASK (0x1FU)
12292#define DDRC_REGS_DRAMTMG5_SHADOW_t_cke_SHIFT (0U)
12293#define DDRC_REGS_DRAMTMG5_SHADOW_t_cke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG5_SHADOW_t_cke_SHIFT)) & DDRC_REGS_DRAMTMG5_SHADOW_t_cke_MASK)
12294#define DDRC_REGS_DRAMTMG5_SHADOW_t_ckesr_MASK (0x3F00U)
12295#define DDRC_REGS_DRAMTMG5_SHADOW_t_ckesr_SHIFT (8U)
12296#define DDRC_REGS_DRAMTMG5_SHADOW_t_ckesr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG5_SHADOW_t_ckesr_SHIFT)) & DDRC_REGS_DRAMTMG5_SHADOW_t_ckesr_MASK)
12297#define DDRC_REGS_DRAMTMG5_SHADOW_t_cksre_MASK (0xF0000U)
12298#define DDRC_REGS_DRAMTMG5_SHADOW_t_cksre_SHIFT (16U)
12299#define DDRC_REGS_DRAMTMG5_SHADOW_t_cksre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG5_SHADOW_t_cksre_SHIFT)) & DDRC_REGS_DRAMTMG5_SHADOW_t_cksre_MASK)
12300#define DDRC_REGS_DRAMTMG5_SHADOW_t_cksrx_MASK (0xF000000U)
12301#define DDRC_REGS_DRAMTMG5_SHADOW_t_cksrx_SHIFT (24U)
12302#define DDRC_REGS_DRAMTMG5_SHADOW_t_cksrx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG5_SHADOW_t_cksrx_SHIFT)) & DDRC_REGS_DRAMTMG5_SHADOW_t_cksrx_MASK)
12303/*! @} */
12304
12305/*! @name DRAMTMG6_SHADOW - [SHADOW] SDRAM Timing Register 6 */
12306/*! @{ */
12307#define DDRC_REGS_DRAMTMG6_SHADOW_t_ckcsx_MASK (0xFU)
12308#define DDRC_REGS_DRAMTMG6_SHADOW_t_ckcsx_SHIFT (0U)
12309#define DDRC_REGS_DRAMTMG6_SHADOW_t_ckcsx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG6_SHADOW_t_ckcsx_SHIFT)) & DDRC_REGS_DRAMTMG6_SHADOW_t_ckcsx_MASK)
12310#define DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpdx_MASK (0xF0000U)
12311#define DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpdx_SHIFT (16U)
12312#define DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpdx_SHIFT)) & DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpdx_MASK)
12313#define DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpde_MASK (0xF000000U)
12314#define DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpde_SHIFT (24U)
12315#define DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpde_SHIFT)) & DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpde_MASK)
12316/*! @} */
12317
12318/*! @name DRAMTMG7_SHADOW - [SHADOW] SDRAM Timing Register 7 */
12319/*! @{ */
12320#define DDRC_REGS_DRAMTMG7_SHADOW_t_ckpdx_MASK (0xFU)
12321#define DDRC_REGS_DRAMTMG7_SHADOW_t_ckpdx_SHIFT (0U)
12322#define DDRC_REGS_DRAMTMG7_SHADOW_t_ckpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG7_SHADOW_t_ckpdx_SHIFT)) & DDRC_REGS_DRAMTMG7_SHADOW_t_ckpdx_MASK)
12323#define DDRC_REGS_DRAMTMG7_SHADOW_t_ckpde_MASK (0xF00U)
12324#define DDRC_REGS_DRAMTMG7_SHADOW_t_ckpde_SHIFT (8U)
12325#define DDRC_REGS_DRAMTMG7_SHADOW_t_ckpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG7_SHADOW_t_ckpde_SHIFT)) & DDRC_REGS_DRAMTMG7_SHADOW_t_ckpde_MASK)
12326/*! @} */
12327
12328/*! @name DRAMTMG8_SHADOW - [SHADOW] SDRAM Timing Register 8 */
12329/*! @{ */
12330#define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_x32_MASK (0x7FU)
12331#define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_x32_SHIFT (0U)
12332#define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG8_SHADOW_t_xs_x32_SHIFT)) & DDRC_REGS_DRAMTMG8_SHADOW_t_xs_x32_MASK)
12333#define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_dll_x32_MASK (0x7F00U)
12334#define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_dll_x32_SHIFT (8U)
12335#define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_dll_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG8_SHADOW_t_xs_dll_x32_SHIFT)) & DDRC_REGS_DRAMTMG8_SHADOW_t_xs_dll_x32_MASK)
12336#define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_abort_x32_MASK (0x7F0000U)
12337#define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_abort_x32_SHIFT (16U)
12338#define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_abort_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG8_SHADOW_t_xs_abort_x32_SHIFT)) & DDRC_REGS_DRAMTMG8_SHADOW_t_xs_abort_x32_MASK)
12339#define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_fast_x32_MASK (0x7F000000U)
12340#define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_fast_x32_SHIFT (24U)
12341#define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_fast_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG8_SHADOW_t_xs_fast_x32_SHIFT)) & DDRC_REGS_DRAMTMG8_SHADOW_t_xs_fast_x32_MASK)
12342/*! @} */
12343
12344/*! @name DRAMTMG9_SHADOW - [SHADOW] SDRAM Timing Register 9 */
12345/*! @{ */
12346#define DDRC_REGS_DRAMTMG9_SHADOW_wr2rd_s_MASK (0x3FU)
12347#define DDRC_REGS_DRAMTMG9_SHADOW_wr2rd_s_SHIFT (0U)
12348#define DDRC_REGS_DRAMTMG9_SHADOW_wr2rd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG9_SHADOW_wr2rd_s_SHIFT)) & DDRC_REGS_DRAMTMG9_SHADOW_wr2rd_s_MASK)
12349#define DDRC_REGS_DRAMTMG9_SHADOW_t_rrd_s_MASK (0xF00U)
12350#define DDRC_REGS_DRAMTMG9_SHADOW_t_rrd_s_SHIFT (8U)
12351#define DDRC_REGS_DRAMTMG9_SHADOW_t_rrd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG9_SHADOW_t_rrd_s_SHIFT)) & DDRC_REGS_DRAMTMG9_SHADOW_t_rrd_s_MASK)
12352#define DDRC_REGS_DRAMTMG9_SHADOW_t_ccd_s_MASK (0x70000U)
12353#define DDRC_REGS_DRAMTMG9_SHADOW_t_ccd_s_SHIFT (16U)
12354#define DDRC_REGS_DRAMTMG9_SHADOW_t_ccd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG9_SHADOW_t_ccd_s_SHIFT)) & DDRC_REGS_DRAMTMG9_SHADOW_t_ccd_s_MASK)
12355#define DDRC_REGS_DRAMTMG9_SHADOW_ddr4_wr_preamble_MASK (0x40000000U)
12356#define DDRC_REGS_DRAMTMG9_SHADOW_ddr4_wr_preamble_SHIFT (30U)
12357#define DDRC_REGS_DRAMTMG9_SHADOW_ddr4_wr_preamble(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG9_SHADOW_ddr4_wr_preamble_SHIFT)) & DDRC_REGS_DRAMTMG9_SHADOW_ddr4_wr_preamble_MASK)
12358/*! @} */
12359
12360/*! @name DRAMTMG10_SHADOW - [SHADOW] SDRAM Timing Register 10 */
12361/*! @{ */
12362#define DDRC_REGS_DRAMTMG10_SHADOW_t_gear_hold_MASK (0x3U)
12363#define DDRC_REGS_DRAMTMG10_SHADOW_t_gear_hold_SHIFT (0U)
12364#define DDRC_REGS_DRAMTMG10_SHADOW_t_gear_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG10_SHADOW_t_gear_hold_SHIFT)) & DDRC_REGS_DRAMTMG10_SHADOW_t_gear_hold_MASK)
12365#define DDRC_REGS_DRAMTMG10_SHADOW_t_gear_setup_MASK (0xCU)
12366#define DDRC_REGS_DRAMTMG10_SHADOW_t_gear_setup_SHIFT (2U)
12367#define DDRC_REGS_DRAMTMG10_SHADOW_t_gear_setup(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG10_SHADOW_t_gear_setup_SHIFT)) & DDRC_REGS_DRAMTMG10_SHADOW_t_gear_setup_MASK)
12368#define DDRC_REGS_DRAMTMG10_SHADOW_t_cmd_gear_MASK (0x1F00U)
12369#define DDRC_REGS_DRAMTMG10_SHADOW_t_cmd_gear_SHIFT (8U)
12370#define DDRC_REGS_DRAMTMG10_SHADOW_t_cmd_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG10_SHADOW_t_cmd_gear_SHIFT)) & DDRC_REGS_DRAMTMG10_SHADOW_t_cmd_gear_MASK)
12371#define DDRC_REGS_DRAMTMG10_SHADOW_t_sync_gear_MASK (0x1F0000U)
12372#define DDRC_REGS_DRAMTMG10_SHADOW_t_sync_gear_SHIFT (16U)
12373#define DDRC_REGS_DRAMTMG10_SHADOW_t_sync_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG10_SHADOW_t_sync_gear_SHIFT)) & DDRC_REGS_DRAMTMG10_SHADOW_t_sync_gear_MASK)
12374/*! @} */
12375
12376/*! @name DRAMTMG11_SHADOW - [SHADOW] SDRAM Timing Register 11 */
12377/*! @{ */
12378#define DDRC_REGS_DRAMTMG11_SHADOW_t_ckmpe_MASK (0x1FU)
12379#define DDRC_REGS_DRAMTMG11_SHADOW_t_ckmpe_SHIFT (0U)
12380#define DDRC_REGS_DRAMTMG11_SHADOW_t_ckmpe(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG11_SHADOW_t_ckmpe_SHIFT)) & DDRC_REGS_DRAMTMG11_SHADOW_t_ckmpe_MASK)
12381#define DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_s_MASK (0x300U)
12382#define DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_s_SHIFT (8U)
12383#define DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_s_SHIFT)) & DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_s_MASK)
12384#define DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_lh_MASK (0x1F0000U)
12385#define DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_lh_SHIFT (16U)
12386#define DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_lh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_lh_SHIFT)) & DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_lh_MASK)
12387#define DDRC_REGS_DRAMTMG11_SHADOW_post_mpsm_gap_x32_MASK (0x7F000000U)
12388#define DDRC_REGS_DRAMTMG11_SHADOW_post_mpsm_gap_x32_SHIFT (24U)
12389#define DDRC_REGS_DRAMTMG11_SHADOW_post_mpsm_gap_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG11_SHADOW_post_mpsm_gap_x32_SHIFT)) & DDRC_REGS_DRAMTMG11_SHADOW_post_mpsm_gap_x32_MASK)
12390/*! @} */
12391
12392/*! @name DRAMTMG12_SHADOW - [SHADOW] SDRAM Timing Register 12 */
12393/*! @{ */
12394#define DDRC_REGS_DRAMTMG12_SHADOW_t_mrd_pda_MASK (0x1FU)
12395#define DDRC_REGS_DRAMTMG12_SHADOW_t_mrd_pda_SHIFT (0U)
12396#define DDRC_REGS_DRAMTMG12_SHADOW_t_mrd_pda(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG12_SHADOW_t_mrd_pda_SHIFT)) & DDRC_REGS_DRAMTMG12_SHADOW_t_mrd_pda_MASK)
12397#define DDRC_REGS_DRAMTMG12_SHADOW_t_ckehcmd_MASK (0xF00U)
12398#define DDRC_REGS_DRAMTMG12_SHADOW_t_ckehcmd_SHIFT (8U)
12399#define DDRC_REGS_DRAMTMG12_SHADOW_t_ckehcmd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG12_SHADOW_t_ckehcmd_SHIFT)) & DDRC_REGS_DRAMTMG12_SHADOW_t_ckehcmd_MASK)
12400#define DDRC_REGS_DRAMTMG12_SHADOW_t_cmdcke_MASK (0x30000U)
12401#define DDRC_REGS_DRAMTMG12_SHADOW_t_cmdcke_SHIFT (16U)
12402#define DDRC_REGS_DRAMTMG12_SHADOW_t_cmdcke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG12_SHADOW_t_cmdcke_SHIFT)) & DDRC_REGS_DRAMTMG12_SHADOW_t_cmdcke_MASK)
12403/*! @} */
12404
12405/*! @name DRAMTMG13_SHADOW - [SHADOW] SDRAM Timing Register 13 */
12406/*! @{ */
12407#define DDRC_REGS_DRAMTMG13_SHADOW_t_ppd_MASK (0x7U)
12408#define DDRC_REGS_DRAMTMG13_SHADOW_t_ppd_SHIFT (0U)
12409#define DDRC_REGS_DRAMTMG13_SHADOW_t_ppd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG13_SHADOW_t_ppd_SHIFT)) & DDRC_REGS_DRAMTMG13_SHADOW_t_ppd_MASK)
12410#define DDRC_REGS_DRAMTMG13_SHADOW_t_ccd_mw_MASK (0x3F0000U)
12411#define DDRC_REGS_DRAMTMG13_SHADOW_t_ccd_mw_SHIFT (16U)
12412#define DDRC_REGS_DRAMTMG13_SHADOW_t_ccd_mw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG13_SHADOW_t_ccd_mw_SHIFT)) & DDRC_REGS_DRAMTMG13_SHADOW_t_ccd_mw_MASK)
12413#define DDRC_REGS_DRAMTMG13_SHADOW_odtloff_MASK (0x7F000000U)
12414#define DDRC_REGS_DRAMTMG13_SHADOW_odtloff_SHIFT (24U)
12415#define DDRC_REGS_DRAMTMG13_SHADOW_odtloff(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG13_SHADOW_odtloff_SHIFT)) & DDRC_REGS_DRAMTMG13_SHADOW_odtloff_MASK)
12416/*! @} */
12417
12418/*! @name DRAMTMG14_SHADOW - [SHADOW] SDRAM Timing Register 14 */
12419/*! @{ */
12420#define DDRC_REGS_DRAMTMG14_SHADOW_t_xsr_MASK (0xFFFU)
12421#define DDRC_REGS_DRAMTMG14_SHADOW_t_xsr_SHIFT (0U)
12422#define DDRC_REGS_DRAMTMG14_SHADOW_t_xsr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG14_SHADOW_t_xsr_SHIFT)) & DDRC_REGS_DRAMTMG14_SHADOW_t_xsr_MASK)
12423/*! @} */
12424
12425/*! @name DRAMTMG15_SHADOW - [SHADOW] SDRAM Timing Register 15 */
12426/*! @{ */
12427#define DDRC_REGS_DRAMTMG15_SHADOW_t_stab_x32_MASK (0xFFU)
12428#define DDRC_REGS_DRAMTMG15_SHADOW_t_stab_x32_SHIFT (0U)
12429#define DDRC_REGS_DRAMTMG15_SHADOW_t_stab_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG15_SHADOW_t_stab_x32_SHIFT)) & DDRC_REGS_DRAMTMG15_SHADOW_t_stab_x32_MASK)
12430#define DDRC_REGS_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_MASK (0x80000000U)
12431#define DDRC_REGS_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_SHIFT (31U)
12432#define DDRC_REGS_DRAMTMG15_SHADOW_en_dfi_lp_t_stab(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_SHIFT)) & DDRC_REGS_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_MASK)
12433/*! @} */
12434
12435/*! @name ZQCTL0_SHADOW - [SHADOW] ZQ Control Register 0 */
12436/*! @{ */
12437#define DDRC_REGS_ZQCTL0_SHADOW_t_zq_short_nop_MASK (0x3FFU)
12438#define DDRC_REGS_ZQCTL0_SHADOW_t_zq_short_nop_SHIFT (0U)
12439#define DDRC_REGS_ZQCTL0_SHADOW_t_zq_short_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_SHADOW_t_zq_short_nop_SHIFT)) & DDRC_REGS_ZQCTL0_SHADOW_t_zq_short_nop_MASK)
12440#define DDRC_REGS_ZQCTL0_SHADOW_t_zq_long_nop_MASK (0x7FF0000U)
12441#define DDRC_REGS_ZQCTL0_SHADOW_t_zq_long_nop_SHIFT (16U)
12442#define DDRC_REGS_ZQCTL0_SHADOW_t_zq_long_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_SHADOW_t_zq_long_nop_SHIFT)) & DDRC_REGS_ZQCTL0_SHADOW_t_zq_long_nop_MASK)
12443#define DDRC_REGS_ZQCTL0_SHADOW_dis_mpsmx_zqcl_MASK (0x10000000U)
12444#define DDRC_REGS_ZQCTL0_SHADOW_dis_mpsmx_zqcl_SHIFT (28U)
12445#define DDRC_REGS_ZQCTL0_SHADOW_dis_mpsmx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_SHADOW_dis_mpsmx_zqcl_SHIFT)) & DDRC_REGS_ZQCTL0_SHADOW_dis_mpsmx_zqcl_MASK)
12446#define DDRC_REGS_ZQCTL0_SHADOW_zq_resistor_shared_MASK (0x20000000U)
12447#define DDRC_REGS_ZQCTL0_SHADOW_zq_resistor_shared_SHIFT (29U)
12448#define DDRC_REGS_ZQCTL0_SHADOW_zq_resistor_shared(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_SHADOW_zq_resistor_shared_SHIFT)) & DDRC_REGS_ZQCTL0_SHADOW_zq_resistor_shared_MASK)
12449#define DDRC_REGS_ZQCTL0_SHADOW_dis_srx_zqcl_MASK (0x40000000U)
12450#define DDRC_REGS_ZQCTL0_SHADOW_dis_srx_zqcl_SHIFT (30U)
12451#define DDRC_REGS_ZQCTL0_SHADOW_dis_srx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_SHADOW_dis_srx_zqcl_SHIFT)) & DDRC_REGS_ZQCTL0_SHADOW_dis_srx_zqcl_MASK)
12452#define DDRC_REGS_ZQCTL0_SHADOW_dis_auto_zq_MASK (0x80000000U)
12453#define DDRC_REGS_ZQCTL0_SHADOW_dis_auto_zq_SHIFT (31U)
12454#define DDRC_REGS_ZQCTL0_SHADOW_dis_auto_zq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_SHADOW_dis_auto_zq_SHIFT)) & DDRC_REGS_ZQCTL0_SHADOW_dis_auto_zq_MASK)
12455/*! @} */
12456
12457/*! @name DFITMG0_SHADOW - [SHADOW] DFI Timing Register 0 */
12458/*! @{ */
12459#define DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrlat_MASK (0x3FU)
12460#define DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrlat_SHIFT (0U)
12461#define DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrlat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrlat_SHIFT)) & DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrlat_MASK)
12462#define DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrdata_MASK (0x3F00U)
12463#define DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrdata_SHIFT (8U)
12464#define DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrdata(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrdata_SHIFT)) & DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrdata_MASK)
12465#define DDRC_REGS_DFITMG0_SHADOW_dfi_wrdata_use_sdr_MASK (0x8000U)
12466#define DDRC_REGS_DFITMG0_SHADOW_dfi_wrdata_use_sdr_SHIFT (15U)
12467#define DDRC_REGS_DFITMG0_SHADOW_dfi_wrdata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_SHADOW_dfi_wrdata_use_sdr_SHIFT)) & DDRC_REGS_DFITMG0_SHADOW_dfi_wrdata_use_sdr_MASK)
12468#define DDRC_REGS_DFITMG0_SHADOW_dfi_t_rddata_en_MASK (0x7F0000U)
12469#define DDRC_REGS_DFITMG0_SHADOW_dfi_t_rddata_en_SHIFT (16U)
12470#define DDRC_REGS_DFITMG0_SHADOW_dfi_t_rddata_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_SHADOW_dfi_t_rddata_en_SHIFT)) & DDRC_REGS_DFITMG0_SHADOW_dfi_t_rddata_en_MASK)
12471#define DDRC_REGS_DFITMG0_SHADOW_dfi_rddata_use_sdr_MASK (0x800000U)
12472#define DDRC_REGS_DFITMG0_SHADOW_dfi_rddata_use_sdr_SHIFT (23U)
12473#define DDRC_REGS_DFITMG0_SHADOW_dfi_rddata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_SHADOW_dfi_rddata_use_sdr_SHIFT)) & DDRC_REGS_DFITMG0_SHADOW_dfi_rddata_use_sdr_MASK)
12474#define DDRC_REGS_DFITMG0_SHADOW_dfi_t_ctrl_delay_MASK (0x1F000000U)
12475#define DDRC_REGS_DFITMG0_SHADOW_dfi_t_ctrl_delay_SHIFT (24U)
12476#define DDRC_REGS_DFITMG0_SHADOW_dfi_t_ctrl_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_SHADOW_dfi_t_ctrl_delay_SHIFT)) & DDRC_REGS_DFITMG0_SHADOW_dfi_t_ctrl_delay_MASK)
12477/*! @} */
12478
12479/*! @name DFITMG1_SHADOW - [SHADOW] DFI Timing Register 1 */
12480/*! @{ */
12481#define DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_enable_MASK (0x1FU)
12482#define DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_enable_SHIFT (0U)
12483#define DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_enable_SHIFT)) & DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_enable_MASK)
12484#define DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_disable_MASK (0x1F00U)
12485#define DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_disable_SHIFT (8U)
12486#define DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_disable_SHIFT)) & DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_disable_MASK)
12487#define DDRC_REGS_DFITMG1_SHADOW_dfi_t_wrdata_delay_MASK (0x1F0000U)
12488#define DDRC_REGS_DFITMG1_SHADOW_dfi_t_wrdata_delay_SHIFT (16U)
12489#define DDRC_REGS_DFITMG1_SHADOW_dfi_t_wrdata_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_SHADOW_dfi_t_wrdata_delay_SHIFT)) & DDRC_REGS_DFITMG1_SHADOW_dfi_t_wrdata_delay_MASK)
12490#define DDRC_REGS_DFITMG1_SHADOW_dfi_t_parin_lat_MASK (0x3000000U)
12491#define DDRC_REGS_DFITMG1_SHADOW_dfi_t_parin_lat_SHIFT (24U)
12492#define DDRC_REGS_DFITMG1_SHADOW_dfi_t_parin_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_SHADOW_dfi_t_parin_lat_SHIFT)) & DDRC_REGS_DFITMG1_SHADOW_dfi_t_parin_lat_MASK)
12493#define DDRC_REGS_DFITMG1_SHADOW_dfi_t_cmd_lat_MASK (0xF0000000U)
12494#define DDRC_REGS_DFITMG1_SHADOW_dfi_t_cmd_lat_SHIFT (28U)
12495#define DDRC_REGS_DFITMG1_SHADOW_dfi_t_cmd_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_SHADOW_dfi_t_cmd_lat_SHIFT)) & DDRC_REGS_DFITMG1_SHADOW_dfi_t_cmd_lat_MASK)
12496/*! @} */
12497
12498/*! @name DFITMG2_SHADOW - [SHADOW] DFI Timing Register 2 */
12499/*! @{ */
12500#define DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_wrcslat_MASK (0x3FU)
12501#define DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_wrcslat_SHIFT (0U)
12502#define DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_wrcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_wrcslat_SHIFT)) & DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_wrcslat_MASK)
12503#define DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_rdcslat_MASK (0x7F00U)
12504#define DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_rdcslat_SHIFT (8U)
12505#define DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_rdcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_rdcslat_SHIFT)) & DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_rdcslat_MASK)
12506/*! @} */
12507
12508/*! @name DFITMG3_SHADOW - [SHADOW] DFI Timing Register 3 */
12509/*! @{ */
12510#define DDRC_REGS_DFITMG3_SHADOW_dfi_t_geardown_delay_MASK (0x1FU)
12511#define DDRC_REGS_DFITMG3_SHADOW_dfi_t_geardown_delay_SHIFT (0U)
12512#define DDRC_REGS_DFITMG3_SHADOW_dfi_t_geardown_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG3_SHADOW_dfi_t_geardown_delay_SHIFT)) & DDRC_REGS_DFITMG3_SHADOW_dfi_t_geardown_delay_MASK)
12513/*! @} */
12514
12515/*! @name ODTCFG_SHADOW - [SHADOW] ODT Configuration Register */
12516/*! @{ */
12517#define DDRC_REGS_ODTCFG_SHADOW_rd_odt_delay_MASK (0x7CU)
12518#define DDRC_REGS_ODTCFG_SHADOW_rd_odt_delay_SHIFT (2U)
12519#define DDRC_REGS_ODTCFG_SHADOW_rd_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTCFG_SHADOW_rd_odt_delay_SHIFT)) & DDRC_REGS_ODTCFG_SHADOW_rd_odt_delay_MASK)
12520#define DDRC_REGS_ODTCFG_SHADOW_rd_odt_hold_MASK (0xF00U)
12521#define DDRC_REGS_ODTCFG_SHADOW_rd_odt_hold_SHIFT (8U)
12522#define DDRC_REGS_ODTCFG_SHADOW_rd_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTCFG_SHADOW_rd_odt_hold_SHIFT)) & DDRC_REGS_ODTCFG_SHADOW_rd_odt_hold_MASK)
12523#define DDRC_REGS_ODTCFG_SHADOW_wr_odt_delay_MASK (0x1F0000U)
12524#define DDRC_REGS_ODTCFG_SHADOW_wr_odt_delay_SHIFT (16U)
12525#define DDRC_REGS_ODTCFG_SHADOW_wr_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTCFG_SHADOW_wr_odt_delay_SHIFT)) & DDRC_REGS_ODTCFG_SHADOW_wr_odt_delay_MASK)
12526#define DDRC_REGS_ODTCFG_SHADOW_wr_odt_hold_MASK (0xF000000U)
12527#define DDRC_REGS_ODTCFG_SHADOW_wr_odt_hold_SHIFT (24U)
12528#define DDRC_REGS_ODTCFG_SHADOW_wr_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTCFG_SHADOW_wr_odt_hold_SHIFT)) & DDRC_REGS_ODTCFG_SHADOW_wr_odt_hold_MASK)
12529/*! @} */
12530
12531
12532/*!
12533 * @}
12534 */ /* end of group DDRC_REGS_Register_Masks */
12535
12536
12537/* DDRC_REGS - Peripheral instance base addresses */
12538/** Peripheral DDRC base address */
12539#define DDRC_BASE (0x3D400000u)
12540/** Peripheral DDRC base pointer */
12541#define DDRC ((DDRC_REGS_Type *)DDRC_BASE)
12542/** Array initializer of DDRC_REGS peripheral base addresses */
12543#define DDRC_REGS_BASE_ADDRS { DDRC_BASE }
12544/** Array initializer of DDRC_REGS peripheral base pointers */
12545#define DDRC_REGS_BASE_PTRS { DDRC }
12546
12547/*!
12548 * @}
12549 */ /* end of group DDRC_REGS_Peripheral_Access_Layer */
12550
12551
12552/* ----------------------------------------------------------------------------
12553 -- DEC400D Peripheral Access Layer
12554 ---------------------------------------------------------------------------- */
12555
12556/*!
12557 * @addtogroup DEC400D_Peripheral_Access_Layer DEC400D Peripheral Access Layer
12558 * @{
12559 */
12560
12561/** DEC400D - Register Layout Typedef */
12562typedef struct {
12563 uint8_t RESERVED_0[36];
12564 __I uint32_t GCCHIPREV; /**< Revision ID, offset: 0x24 */
12565 __I uint32_t GCCHIPDATE; /**< Release Date, offset: 0x28 */
12566 uint8_t RESERVED_1[108];
12567 __I uint32_t GCREGHICHIPPATCHREV; /**< Patch Revision, offset: 0x98 */
12568 uint8_t RESERVED_2[12];
12569 __I uint32_t GCPRODUCTID; /**< Product ID, offset: 0xA8 */
12570 uint8_t RESERVED_3[1876];
12571 __IO uint32_t GCREGAHBDECREADCONFIG[32]; /**< Decode Read Configuration, array offset: 0x800, array step: 0x4 */
12572 uint8_t RESERVED_4[128];
12573 __IO uint32_t GCREGAHBDECREADBUFFERBASE[32]; /**< Decode Read Buffer Base, array offset: 0x900, array step: 0x4 */
12574 __IO uint32_t GCREGAHBDECREADCACHEBASE[32]; /**< Decode Read Cache Base, array offset: 0x980, array step: 0x4 */
12575 uint8_t RESERVED_5[256];
12576 __IO uint32_t GCREGAHBDECCONTROL; /**< Dec400D Control, offset: 0xB00 */
12577 __I uint32_t GCREGAHBDECINTRACKNOWLEDGE; /**< Interrupt Acknowledge, offset: 0xB04 */
12578 __IO uint32_t GCREGAHBDECINTRENBL; /**< Interrupt Enable, offset: 0xB08 */
12579 __I uint32_t GCREGAHBDECTILESTATUSDEBUG; /**< Tile Status Module Debug, offset: 0xB0C */
12580 uint8_t RESERVED_6[4];
12581 __I uint32_t GCREGAHBDECDECODERDEBUG; /**< Decompression Module Debug, offset: 0xB14 */
12582 __I uint32_t GCREGAHBDECTOTALREADSIN; /**< Total Reads In, offset: 0xB18 */
12583 uint8_t RESERVED_7[4];
12584 __I uint32_t GCREGAHBDECTOTALREADBURSTSIN; /**< Total Read Data Count, offset: 0xB20 */
12585 uint8_t RESERVED_8[4];
12586 __I uint32_t GCREGAHBDECTOTALREADREQIN; /**< Total Read Request In, offset: 0xB28 */
12587 uint8_t RESERVED_9[4];
12588 __I uint32_t GCREGAHBDECTOTALREADLASTSIN; /**< Total Input Read Last Number, offset: 0xB30 */
12589 uint8_t RESERVED_10[4];
12590 __I uint32_t GCREGAHBDECTOTALREADSOUT; /**< Total Reads Out, offset: 0xB38 */
12591 uint8_t RESERVED_11[4];
12592 __I uint32_t GCREGAHBDECTOTALREADBURSTSOUT; /**< Total Read Bursts Out, offset: 0xB40 */
12593 uint8_t RESERVED_12[4];
12594 __I uint32_t GCREGAHBDECTOTALREADREQOUT; /**< Total Read Request Out, offset: 0xB48 */
12595 uint8_t RESERVED_13[4];
12596 __I uint32_t GCREGAHBDECTOTALREADLASTSOUT; /**< Total Read Last Out, offset: 0xB50 */
12597 uint8_t RESERVED_14[4];
12598 __I uint32_t GCREGAHBDECDEBUG0; /**< Debug Register 0, offset: 0xB58 */
12599 __I uint32_t GCREGAHBDECDEBUG1; /**< Debug Register 1, offset: 0xB5C */
12600 __I uint32_t GCREGAHBDECDEBUG2; /**< Debug register 2, offset: 0xB60 */
12601 __I uint32_t GCREGAHBDECDEBUG3; /**< Debug Register 3, offset: 0xB64 */
12602 __IO uint32_t GCREGAHBDECCONTROLEX; /**< GCREGAHBDECCONTROLEX, offset: 0xB68 */
12603 __IO uint32_t GCREGAHBDECSTATECOMMIT; /**< GCREGAHBDECSTATECOMMIT, offset: 0xB6C */
12604 __I uint32_t GCREGAHBDECSTATELOCK; /**< GCREGAHBDECSTATELOCK, offset: 0xB70 */
12605 uint8_t RESERVED_15[140];
12606 __IO uint32_t GCREGAHBDECREADEXCONFIG[32]; /**< Decode Read Extra Configuration, array offset: 0xC00, array step: 0x4 */
12607 __IO uint32_t GCREGAHBDECREADSTRIDE[32]; /**< Decoder Read Stride, array offset: 0xC80, array step: 0x4 */
12608 uint8_t RESERVED_16[256];
12609 __IO uint32_t GCREGAHBDECREADBUFFEREND[32]; /**< Decoder Read Buffer End, array offset: 0xE00, array step: 0x4 */
12610} DEC400D_Type;
12611
12612/* ----------------------------------------------------------------------------
12613 -- DEC400D Register Masks
12614 ---------------------------------------------------------------------------- */
12615
12616/*!
12617 * @addtogroup DEC400D_Register_Masks DEC400D Register Masks
12618 * @{
12619 */
12620
12621/*! @name GCCHIPREV - Revision ID */
12622/*! @{ */
12623#define DEC400D_GCCHIPREV_GCCHIPREV_MASK (0xFFFFFFFFU)
12624#define DEC400D_GCCHIPREV_GCCHIPREV_SHIFT (0U)
12625#define DEC400D_GCCHIPREV_GCCHIPREV(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCCHIPREV_GCCHIPREV_SHIFT)) & DEC400D_GCCHIPREV_GCCHIPREV_MASK)
12626/*! @} */
12627
12628/*! @name GCCHIPDATE - Release Date */
12629/*! @{ */
12630#define DEC400D_GCCHIPDATE_GCCHIPDATE_MASK (0xFFFFFFFFU)
12631#define DEC400D_GCCHIPDATE_GCCHIPDATE_SHIFT (0U)
12632#define DEC400D_GCCHIPDATE_GCCHIPDATE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCCHIPDATE_GCCHIPDATE_SHIFT)) & DEC400D_GCCHIPDATE_GCCHIPDATE_MASK)
12633/*! @} */
12634
12635/*! @name GCREGHICHIPPATCHREV - Patch Revision */
12636/*! @{ */
12637#define DEC400D_GCREGHICHIPPATCHREV_GCREGHICHIPPATCHREV_MASK (0xFFFFFFFFU)
12638#define DEC400D_GCREGHICHIPPATCHREV_GCREGHICHIPPATCHREV_SHIFT (0U)
12639#define DEC400D_GCREGHICHIPPATCHREV_GCREGHICHIPPATCHREV(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGHICHIPPATCHREV_GCREGHICHIPPATCHREV_SHIFT)) & DEC400D_GCREGHICHIPPATCHREV_GCREGHICHIPPATCHREV_MASK)
12640/*! @} */
12641
12642/*! @name GCPRODUCTID - Product ID */
12643/*! @{ */
12644#define DEC400D_GCPRODUCTID_GCPRODUCTID_MASK (0xFFFFFFFFU)
12645#define DEC400D_GCPRODUCTID_GCPRODUCTID_SHIFT (0U)
12646#define DEC400D_GCPRODUCTID_GCPRODUCTID(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCPRODUCTID_GCPRODUCTID_SHIFT)) & DEC400D_GCPRODUCTID_GCPRODUCTID_MASK)
12647/*! @} */
12648
12649/*! @name GCREGAHBDECREADCONFIG - Decode Read Configuration */
12650/*! @{ */
12651#define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ENABLE_MASK (0x1U)
12652#define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ENABLE_SHIFT (0U)
12653/*! COMPRESSION_ENABLE - Compression Enable
12654 * 0b0..Disable
12655 * 0b1..Enable
12656 */
12657#define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ENABLE_SHIFT)) & DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ENABLE_MASK)
12658#define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_FORMAT_MASK (0xF8U)
12659#define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_FORMAT_SHIFT (3U)
12660/*! COMPRESSION_FORMAT - Compression Format
12661 * 0b00000..ARGB8
12662 */
12663#define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_FORMAT_SHIFT)) & DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_FORMAT_MASK)
12664#define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ALIGN_MODE_MASK (0x30000U)
12665#define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ALIGN_MODE_SHIFT (16U)
12666/*! COMPRESSION_ALIGN_MODE - Compression Align Mode
12667 * 0b00..ALIGN1_BYTE
12668 * 0b01..ALIGN16_BYTE
12669 * 0b10..ALIGN32_BYTE
12670 * 0b11..ALIGN64_BYTE
12671 */
12672#define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ALIGN_MODE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ALIGN_MODE_SHIFT)) & DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ALIGN_MODE_MASK)
12673#define DEC400D_GCREGAHBDECREADCONFIG_TILE_ALIGN_MODE_MASK (0x1C00000U)
12674#define DEC400D_GCREGAHBDECREADCONFIG_TILE_ALIGN_MODE_SHIFT (22U)
12675/*! TILE_ALIGN_MODE - Tile Align Mode
12676 * 0b000..TILE1_ALIGN
12677 * 0b001..TILE2_ALIGN
12678 * 0b010..TILE4_ALIGN
12679 * 0b011..CBSR_ALIGN
12680 */
12681#define DEC400D_GCREGAHBDECREADCONFIG_TILE_ALIGN_MODE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADCONFIG_TILE_ALIGN_MODE_SHIFT)) & DEC400D_GCREGAHBDECREADCONFIG_TILE_ALIGN_MODE_MASK)
12682#define DEC400D_GCREGAHBDECREADCONFIG_TILE_MODE_MASK (0x3E000000U)
12683#define DEC400D_GCREGAHBDECREADCONFIG_TILE_MODE_SHIFT (25U)
12684/*! TILE_MODE - Tile Mode
12685 * 0b00000..TILE8X8_XMAJOR
12686 * 0b00001..TILE8X8_YMAJOR
12687 * 0b00010..TILE16X4
12688 * 0b00011..TILE8X4
12689 * 0b00100..TILE4X8
12690 * 0b00101..TILE4X4
12691 * 0b00110..RASTER16X4
12692 * 0b00111..TILE64X4
12693 * 0b01000..TILE32X4
12694 * 0b01001..RASTER256X1
12695 * 0b01010..RASTER128X1
12696 * 0b01011..RASTER64X4
12697 * 0b01100..RASTER256X2
12698 * 0b01101..RASTER128X2
12699 * 0b01110..RASTER128X4
12700 * 0b01111..RASTER64X1
12701 */
12702#define DEC400D_GCREGAHBDECREADCONFIG_TILE_MODE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADCONFIG_TILE_MODE_SHIFT)) & DEC400D_GCREGAHBDECREADCONFIG_TILE_MODE_MASK)
12703/*! @} */
12704
12705/* The count of DEC400D_GCREGAHBDECREADCONFIG */
12706#define DEC400D_GCREGAHBDECREADCONFIG_COUNT (32U)
12707
12708/*! @name GCREGAHBDECREADBUFFERBASE - Decode Read Buffer Base */
12709/*! @{ */
12710#define DEC400D_GCREGAHBDECREADBUFFERBASE_BUFFER_ADDRESS_MASK (0xFFFFFFFFU)
12711#define DEC400D_GCREGAHBDECREADBUFFERBASE_BUFFER_ADDRESS_SHIFT (0U)
12712#define DEC400D_GCREGAHBDECREADBUFFERBASE_BUFFER_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADBUFFERBASE_BUFFER_ADDRESS_SHIFT)) & DEC400D_GCREGAHBDECREADBUFFERBASE_BUFFER_ADDRESS_MASK)
12713/*! @} */
12714
12715/* The count of DEC400D_GCREGAHBDECREADBUFFERBASE */
12716#define DEC400D_GCREGAHBDECREADBUFFERBASE_COUNT (32U)
12717
12718/*! @name GCREGAHBDECREADCACHEBASE - Decode Read Cache Base */
12719/*! @{ */
12720#define DEC400D_GCREGAHBDECREADCACHEBASE_CACHE_ADDRESS_MASK (0xFFFFFFFFU)
12721#define DEC400D_GCREGAHBDECREADCACHEBASE_CACHE_ADDRESS_SHIFT (0U)
12722#define DEC400D_GCREGAHBDECREADCACHEBASE_CACHE_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADCACHEBASE_CACHE_ADDRESS_SHIFT)) & DEC400D_GCREGAHBDECREADCACHEBASE_CACHE_ADDRESS_MASK)
12723/*! @} */
12724
12725/* The count of DEC400D_GCREGAHBDECREADCACHEBASE */
12726#define DEC400D_GCREGAHBDECREADCACHEBASE_COUNT (32U)
12727
12728/*! @name GCREGAHBDECCONTROL - Dec400D Control */
12729/*! @{ */
12730#define DEC400D_GCREGAHBDECCONTROL_FLUSH_MASK (0x1U)
12731#define DEC400D_GCREGAHBDECCONTROL_FLUSH_SHIFT (0U)
12732/*! FLUSH - Flush tile status cache.
12733 * 0b0..Disable
12734 * 0b1..Enable
12735 */
12736#define DEC400D_GCREGAHBDECCONTROL_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_FLUSH_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_FLUSH_MASK)
12737#define DEC400D_GCREGAHBDECCONTROL_DISABLE_COMPRESSION_MASK (0x2U)
12738#define DEC400D_GCREGAHBDECCONTROL_DISABLE_COMPRESSION_SHIFT (1U)
12739/*! DISABLE_COMPRESSION - Bypass compression for all streams.
12740 * 0b0..Disable
12741 * 0b1..Enable
12742 */
12743#define DEC400D_GCREGAHBDECCONTROL_DISABLE_COMPRESSION(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_DISABLE_COMPRESSION_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_DISABLE_COMPRESSION_MASK)
12744#define DEC400D_GCREGAHBDECCONTROL_DISABLE_RAM_CLOCK_GATING_MASK (0x4U)
12745#define DEC400D_GCREGAHBDECCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT (2U)
12746/*! DISABLE_RAM_CLOCK_GATING - Disable clock gating for RAMs.
12747 * 0b0..Disable
12748 * 0b1..Enable
12749 */
12750#define DEC400D_GCREGAHBDECCONTROL_DISABLE_RAM_CLOCK_GATING(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_DISABLE_RAM_CLOCK_GATING_MASK)
12751#define DEC400D_GCREGAHBDECCONTROL_DISABLE_DEBUG_REGISTERS_MASK (0x8U)
12752#define DEC400D_GCREGAHBDECCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT (3U)
12753/*! DISABLE_DEBUG_REGISTERS - Disable debug registers.
12754 * 0b0..Disable
12755 * 0b1..Enable
12756 */
12757#define DEC400D_GCREGAHBDECCONTROL_DISABLE_DEBUG_REGISTERS(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_DISABLE_DEBUG_REGISTERS_MASK)
12758#define DEC400D_GCREGAHBDECCONTROL_SOFT_RESET_MASK (0x10U)
12759#define DEC400D_GCREGAHBDECCONTROL_SOFT_RESET_SHIFT (4U)
12760/*! SOFT_RESET - Soft reset the Dec400D.
12761 * 0b0..Disable
12762 * 0b1..Enable
12763 */
12764#define DEC400D_GCREGAHBDECCONTROL_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_SOFT_RESET_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_SOFT_RESET_MASK)
12765#define DEC400D_GCREGAHBDECCONTROL_TILE_STATUS_READ_ID_MASK (0x7C0U)
12766#define DEC400D_GCREGAHBDECCONTROL_TILE_STATUS_READ_ID_SHIFT (6U)
12767#define DEC400D_GCREGAHBDECCONTROL_TILE_STATUS_READ_ID(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_TILE_STATUS_READ_ID_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_TILE_STATUS_READ_ID_MASK)
12768#define DEC400D_GCREGAHBDECCONTROL_DISABLE_HW_FLUSH_MASK (0x10000U)
12769#define DEC400D_GCREGAHBDECCONTROL_DISABLE_HW_FLUSH_SHIFT (16U)
12770/*! DISABLE_HW_FLUSH - Tile status cache flush through frame end pin is disabled.
12771 * 0b0..Disable
12772 * 0b1..Enable
12773 */
12774#define DEC400D_GCREGAHBDECCONTROL_DISABLE_HW_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_DISABLE_HW_FLUSH_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_DISABLE_HW_FLUSH_MASK)
12775#define DEC400D_GCREGAHBDECCONTROL_CLK_DIS_MASK (0x20000U)
12776#define DEC400D_GCREGAHBDECCONTROL_CLK_DIS_SHIFT (17U)
12777/*! CLK_DIS - Disable clock.
12778 * 0b0..Disable
12779 * 0b1..Enable
12780 */
12781#define DEC400D_GCREGAHBDECCONTROL_CLK_DIS(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_CLK_DIS_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_CLK_DIS_MASK)
12782#define DEC400D_GCREGAHBDECCONTROL_SW_FLUSH_ID_MASK (0xFC0000U)
12783#define DEC400D_GCREGAHBDECCONTROL_SW_FLUSH_ID_SHIFT (18U)
12784#define DEC400D_GCREGAHBDECCONTROL_SW_FLUSH_ID(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_SW_FLUSH_ID_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_SW_FLUSH_ID_MASK)
12785#define DEC400D_GCREGAHBDECCONTROL_DISABLE_MODULE_CLOCK_GATING_MASK (0x40000000U)
12786#define DEC400D_GCREGAHBDECCONTROL_DISABLE_MODULE_CLOCK_GATING_SHIFT (30U)
12787/*! DISABLE_MODULE_CLOCK_GATING - Disable clock gating for sub modules
12788 * 0b0..Disable
12789 * 0b1..Enable
12790 */
12791#define DEC400D_GCREGAHBDECCONTROL_DISABLE_MODULE_CLOCK_GATING(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_DISABLE_MODULE_CLOCK_GATING_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_DISABLE_MODULE_CLOCK_GATING_MASK)
12792/*! @} */
12793
12794/*! @name GCREGAHBDECINTRACKNOWLEDGE - Interrupt Acknowledge */
12795/*! @{ */
12796#define DEC400D_GCREGAHBDECINTRACKNOWLEDGE_INTR_VEC_MASK (0xFFFFFFFFU)
12797#define DEC400D_GCREGAHBDECINTRACKNOWLEDGE_INTR_VEC_SHIFT (0U)
12798#define DEC400D_GCREGAHBDECINTRACKNOWLEDGE_INTR_VEC(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECINTRACKNOWLEDGE_INTR_VEC_SHIFT)) & DEC400D_GCREGAHBDECINTRACKNOWLEDGE_INTR_VEC_MASK)
12799/*! @} */
12800
12801/*! @name GCREGAHBDECINTRENBL - Interrupt Enable */
12802/*! @{ */
12803#define DEC400D_GCREGAHBDECINTRENBL_INTR_ENBL_VEC_MASK (0xFFFFFFFFU)
12804#define DEC400D_GCREGAHBDECINTRENBL_INTR_ENBL_VEC_SHIFT (0U)
12805#define DEC400D_GCREGAHBDECINTRENBL_INTR_ENBL_VEC(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECINTRENBL_INTR_ENBL_VEC_SHIFT)) & DEC400D_GCREGAHBDECINTRENBL_INTR_ENBL_VEC_MASK)
12806/*! @} */
12807
12808/*! @name GCREGAHBDECTILESTATUSDEBUG - Tile Status Module Debug */
12809/*! @{ */
12810#define DEC400D_GCREGAHBDECTILESTATUSDEBUG_TILE_DEBUG_MASK (0xFFFFFFFFU)
12811#define DEC400D_GCREGAHBDECTILESTATUSDEBUG_TILE_DEBUG_SHIFT (0U)
12812#define DEC400D_GCREGAHBDECTILESTATUSDEBUG_TILE_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTILESTATUSDEBUG_TILE_DEBUG_SHIFT)) & DEC400D_GCREGAHBDECTILESTATUSDEBUG_TILE_DEBUG_MASK)
12813/*! @} */
12814
12815/*! @name GCREGAHBDECDECODERDEBUG - Decompression Module Debug */
12816/*! @{ */
12817#define DEC400D_GCREGAHBDECDECODERDEBUG_DEC_DEBUG_MASK (0xFFFFFFFFU)
12818#define DEC400D_GCREGAHBDECDECODERDEBUG_DEC_DEBUG_SHIFT (0U)
12819#define DEC400D_GCREGAHBDECDECODERDEBUG_DEC_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECDECODERDEBUG_DEC_DEBUG_SHIFT)) & DEC400D_GCREGAHBDECDECODERDEBUG_DEC_DEBUG_MASK)
12820/*! @} */
12821
12822/*! @name GCREGAHBDECTOTALREADSIN - Total Reads In */
12823/*! @{ */
12824#define DEC400D_GCREGAHBDECTOTALREADSIN_RDIN_COUNT_MASK (0xFFFFFFFFU)
12825#define DEC400D_GCREGAHBDECTOTALREADSIN_RDIN_COUNT_SHIFT (0U)
12826#define DEC400D_GCREGAHBDECTOTALREADSIN_RDIN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADSIN_RDIN_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADSIN_RDIN_COUNT_MASK)
12827/*! @} */
12828
12829/*! @name GCREGAHBDECTOTALREADBURSTSIN - Total Read Data Count */
12830/*! @{ */
12831#define DEC400D_GCREGAHBDECTOTALREADBURSTSIN_RDIN_BURST_COUNT_MASK (0xFFFFFFFFU)
12832#define DEC400D_GCREGAHBDECTOTALREADBURSTSIN_RDIN_BURST_COUNT_SHIFT (0U)
12833#define DEC400D_GCREGAHBDECTOTALREADBURSTSIN_RDIN_BURST_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADBURSTSIN_RDIN_BURST_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADBURSTSIN_RDIN_BURST_COUNT_MASK)
12834/*! @} */
12835
12836/*! @name GCREGAHBDECTOTALREADREQIN - Total Read Request In */
12837/*! @{ */
12838#define DEC400D_GCREGAHBDECTOTALREADREQIN_RDIN_REQ_COUNT_MASK (0xFFFFFFFFU)
12839#define DEC400D_GCREGAHBDECTOTALREADREQIN_RDIN_REQ_COUNT_SHIFT (0U)
12840#define DEC400D_GCREGAHBDECTOTALREADREQIN_RDIN_REQ_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADREQIN_RDIN_REQ_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADREQIN_RDIN_REQ_COUNT_MASK)
12841/*! @} */
12842
12843/*! @name GCREGAHBDECTOTALREADLASTSIN - Total Input Read Last Number */
12844/*! @{ */
12845#define DEC400D_GCREGAHBDECTOTALREADLASTSIN_RDIN_LAST_COUNT_MASK (0xFFFFFFFFU)
12846#define DEC400D_GCREGAHBDECTOTALREADLASTSIN_RDIN_LAST_COUNT_SHIFT (0U)
12847#define DEC400D_GCREGAHBDECTOTALREADLASTSIN_RDIN_LAST_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADLASTSIN_RDIN_LAST_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADLASTSIN_RDIN_LAST_COUNT_MASK)
12848/*! @} */
12849
12850/*! @name GCREGAHBDECTOTALREADSOUT - Total Reads Out */
12851/*! @{ */
12852#define DEC400D_GCREGAHBDECTOTALREADSOUT_RDOUT_COUNT_MASK (0xFFFFFFFFU)
12853#define DEC400D_GCREGAHBDECTOTALREADSOUT_RDOUT_COUNT_SHIFT (0U)
12854#define DEC400D_GCREGAHBDECTOTALREADSOUT_RDOUT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADSOUT_RDOUT_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADSOUT_RDOUT_COUNT_MASK)
12855/*! @} */
12856
12857/*! @name GCREGAHBDECTOTALREADBURSTSOUT - Total Read Bursts Out */
12858/*! @{ */
12859#define DEC400D_GCREGAHBDECTOTALREADBURSTSOUT_RDOUT_BURST_COUNT_MASK (0xFFFFFFFFU)
12860#define DEC400D_GCREGAHBDECTOTALREADBURSTSOUT_RDOUT_BURST_COUNT_SHIFT (0U)
12861#define DEC400D_GCREGAHBDECTOTALREADBURSTSOUT_RDOUT_BURST_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADBURSTSOUT_RDOUT_BURST_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADBURSTSOUT_RDOUT_BURST_COUNT_MASK)
12862/*! @} */
12863
12864/*! @name GCREGAHBDECTOTALREADREQOUT - Total Read Request Out */
12865/*! @{ */
12866#define DEC400D_GCREGAHBDECTOTALREADREQOUT_RDOUT_REQ_COUNT_MASK (0xFFFFFFFFU)
12867#define DEC400D_GCREGAHBDECTOTALREADREQOUT_RDOUT_REQ_COUNT_SHIFT (0U)
12868#define DEC400D_GCREGAHBDECTOTALREADREQOUT_RDOUT_REQ_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADREQOUT_RDOUT_REQ_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADREQOUT_RDOUT_REQ_COUNT_MASK)
12869/*! @} */
12870
12871/*! @name GCREGAHBDECTOTALREADLASTSOUT - Total Read Last Out */
12872/*! @{ */
12873#define DEC400D_GCREGAHBDECTOTALREADLASTSOUT_RDOUT_LAST_COUNT_MASK (0xFFFFFFFFU)
12874#define DEC400D_GCREGAHBDECTOTALREADLASTSOUT_RDOUT_LAST_COUNT_SHIFT (0U)
12875#define DEC400D_GCREGAHBDECTOTALREADLASTSOUT_RDOUT_LAST_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADLASTSOUT_RDOUT_LAST_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADLASTSOUT_RDOUT_LAST_COUNT_MASK)
12876/*! @} */
12877
12878/*! @name GCREGAHBDECDEBUG0 - Debug Register 0 */
12879/*! @{ */
12880#define DEC400D_GCREGAHBDECDEBUG0_DEBUG0_MASK (0xFFFFFFFFU)
12881#define DEC400D_GCREGAHBDECDEBUG0_DEBUG0_SHIFT (0U)
12882#define DEC400D_GCREGAHBDECDEBUG0_DEBUG0(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECDEBUG0_DEBUG0_SHIFT)) & DEC400D_GCREGAHBDECDEBUG0_DEBUG0_MASK)
12883/*! @} */
12884
12885/*! @name GCREGAHBDECDEBUG1 - Debug Register 1 */
12886/*! @{ */
12887#define DEC400D_GCREGAHBDECDEBUG1_DEBUG1_MASK (0xFFFFFFFFU)
12888#define DEC400D_GCREGAHBDECDEBUG1_DEBUG1_SHIFT (0U)
12889#define DEC400D_GCREGAHBDECDEBUG1_DEBUG1(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECDEBUG1_DEBUG1_SHIFT)) & DEC400D_GCREGAHBDECDEBUG1_DEBUG1_MASK)
12890/*! @} */
12891
12892/*! @name GCREGAHBDECDEBUG2 - Debug register 2 */
12893/*! @{ */
12894#define DEC400D_GCREGAHBDECDEBUG2_DEBUG2_MASK (0xFFFFFFFFU)
12895#define DEC400D_GCREGAHBDECDEBUG2_DEBUG2_SHIFT (0U)
12896#define DEC400D_GCREGAHBDECDEBUG2_DEBUG2(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECDEBUG2_DEBUG2_SHIFT)) & DEC400D_GCREGAHBDECDEBUG2_DEBUG2_MASK)
12897/*! @} */
12898
12899/*! @name GCREGAHBDECDEBUG3 - Debug Register 3 */
12900/*! @{ */
12901#define DEC400D_GCREGAHBDECDEBUG3_DEBUG3_MASK (0xFFFFFFFFU)
12902#define DEC400D_GCREGAHBDECDEBUG3_DEBUG3_SHIFT (0U)
12903#define DEC400D_GCREGAHBDECDEBUG3_DEBUG3(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECDEBUG3_DEBUG3_SHIFT)) & DEC400D_GCREGAHBDECDEBUG3_DEBUG3_MASK)
12904/*! @} */
12905
12906/*! @name GCREGAHBDECCONTROLEX - GCREGAHBDECCONTROLEX */
12907/*! @{ */
12908#define DEC400D_GCREGAHBDECCONTROLEX_GCREGAHBDECCONTROLEX_MASK (0xFFFFFFFFU)
12909#define DEC400D_GCREGAHBDECCONTROLEX_GCREGAHBDECCONTROLEX_SHIFT (0U)
12910#define DEC400D_GCREGAHBDECCONTROLEX_GCREGAHBDECCONTROLEX(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROLEX_GCREGAHBDECCONTROLEX_SHIFT)) & DEC400D_GCREGAHBDECCONTROLEX_GCREGAHBDECCONTROLEX_MASK)
12911/*! @} */
12912
12913/*! @name GCREGAHBDECSTATECOMMIT - GCREGAHBDECSTATECOMMIT */
12914/*! @{ */
12915#define DEC400D_GCREGAHBDECSTATECOMMIT_GCREGAHBDECSTATECOMMIT_MASK (0xFFFFFFFFU)
12916#define DEC400D_GCREGAHBDECSTATECOMMIT_GCREGAHBDECSTATECOMMIT_SHIFT (0U)
12917#define DEC400D_GCREGAHBDECSTATECOMMIT_GCREGAHBDECSTATECOMMIT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECSTATECOMMIT_GCREGAHBDECSTATECOMMIT_SHIFT)) & DEC400D_GCREGAHBDECSTATECOMMIT_GCREGAHBDECSTATECOMMIT_MASK)
12918/*! @} */
12919
12920/*! @name GCREGAHBDECSTATELOCK - GCREGAHBDECSTATELOCK */
12921/*! @{ */
12922#define DEC400D_GCREGAHBDECSTATELOCK_GCREGAHBDECSTATELOCK_MASK (0xFFFFFFFFU)
12923#define DEC400D_GCREGAHBDECSTATELOCK_GCREGAHBDECSTATELOCK_SHIFT (0U)
12924#define DEC400D_GCREGAHBDECSTATELOCK_GCREGAHBDECSTATELOCK(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECSTATELOCK_GCREGAHBDECSTATELOCK_SHIFT)) & DEC400D_GCREGAHBDECSTATELOCK_GCREGAHBDECSTATELOCK_MASK)
12925/*! @} */
12926
12927/*! @name GCREGAHBDECREADEXCONFIG - Decode Read Extra Configuration */
12928/*! @{ */
12929#define DEC400D_GCREGAHBDECREADEXCONFIG_CBSR_WIDTH_MASK (0xFFF8U)
12930#define DEC400D_GCREGAHBDECREADEXCONFIG_CBSR_WIDTH_SHIFT (3U)
12931#define DEC400D_GCREGAHBDECREADEXCONFIG_CBSR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_CBSR_WIDTH_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_CBSR_WIDTH_MASK)
12932#define DEC400D_GCREGAHBDECREADEXCONFIG_BIT_DEPTH_MASK (0x70000U)
12933#define DEC400D_GCREGAHBDECREADEXCONFIG_BIT_DEPTH_SHIFT (16U)
12934/*! BIT_DEPTH - Bit depth
12935 * 0b000..8 bit
12936 * 0b001..10 bit
12937 * 0b010..12 bit
12938 * 0b011..16 bit
12939 */
12940#define DEC400D_GCREGAHBDECREADEXCONFIG_BIT_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_BIT_DEPTH_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_BIT_DEPTH_MASK)
12941#define DEC400D_GCREGAHBDECREADEXCONFIG_TILE_Y_MASK (0x80000U)
12942#define DEC400D_GCREGAHBDECREADEXCONFIG_TILE_Y_SHIFT (19U)
12943/*! TILE_Y - Tile Y
12944 * 0b0..Disable
12945 * 0b1..Enable
12946 */
12947#define DEC400D_GCREGAHBDECREADEXCONFIG_TILE_Y(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_TILE_Y_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_TILE_Y_MASK)
12948#define DEC400D_GCREGAHBDECREADEXCONFIG_STREAM_MODE_MASK (0x1F00000U)
12949#define DEC400D_GCREGAHBDECREADEXCONFIG_STREAM_MODE_SHIFT (20U)
12950/*! STREAM_MODE - Stream mode
12951 * 0b00000..Default
12952 * 0b00001..ISA_STREAM0
12953 * 0b00010..ISA_STREAM1
12954 * 0b00011..ISA_STREAM2
12955 * 0b00100..ISA_STREAM3
12956 * 0b00101..TNR_STREAM_Y
12957 * 0b00110..TNR_STREAM_UV
12958 * 0b00111..GDC_STREAM_Y
12959 * 0b01000..GDC_STREAM_U
12960 * 0b01001..GDC_STREAM_V
12961 * 0b01010..VPU_SRC_Y
12962 * 0b01011..VPR_SRC_UV
12963 * 0b01100..VPU_REF_Y
12964 * 0b01101..VPU_REF_UV
12965 * 0b01110..XYZ_STREAM_AY
12966 * 0b01111..XYZ_STREAM_AU
12967 * 0b10000..XYZ_STREAM_AV
12968 * 0b10001..XYZ_STREAM_BY
12969 * 0b10010..XYZ_STREAM_BU
12970 * 0b10011..XYZ_STREAM_BV
12971 */
12972#define DEC400D_GCREGAHBDECREADEXCONFIG_STREAM_MODE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_STREAM_MODE_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_STREAM_MODE_MASK)
12973#define DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_READ_MODE_MASK (0x4000000U)
12974#define DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_READ_MODE_SHIFT (26U)
12975/*! TS_CACHE_READ_MODE - TS cache read mode
12976 * 0b0..Disable
12977 * 0b1..Enable
12978 */
12979#define DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_READ_MODE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_READ_MODE_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_READ_MODE_MASK)
12980#define DEC400D_GCREGAHBDECREADEXCONFIG_PIXEL_CACHE_REPLACEMENT_MASK (0x8000000U)
12981#define DEC400D_GCREGAHBDECREADEXCONFIG_PIXEL_CACHE_REPLACEMENT_SHIFT (27U)
12982/*! PIXEL_CACHE_REPLACEMENT - Pixel cache replacement
12983 * 0b0..LRU
12984 * 0b1..FIFO
12985 */
12986#define DEC400D_GCREGAHBDECREADEXCONFIG_PIXEL_CACHE_REPLACEMENT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_PIXEL_CACHE_REPLACEMENT_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_PIXEL_CACHE_REPLACEMENT_MASK)
12987#define DEC400D_GCREGAHBDECREADEXCONFIG_INTEL_P010_MASK (0x10000000U)
12988#define DEC400D_GCREGAHBDECREADEXCONFIG_INTEL_P010_SHIFT (28U)
12989/*! INTEL_P010 - Intel's P010 format
12990 * 0b0..Disable
12991 * 0b1..Enable
12992 */
12993#define DEC400D_GCREGAHBDECREADEXCONFIG_INTEL_P010(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_INTEL_P010_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_INTEL_P010_MASK)
12994#define DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_REPLACEMENT_MASK (0x20000000U)
12995#define DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_REPLACEMENT_SHIFT (29U)
12996/*! TS_CACHE_REPLACEMENT - TS cache replacement
12997 * 0b0..LRU
12998 * 0b1..FIFO
12999 */
13000#define DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_REPLACEMENT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_REPLACEMENT_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_REPLACEMENT_MASK)
13001/*! @} */
13002
13003/* The count of DEC400D_GCREGAHBDECREADEXCONFIG */
13004#define DEC400D_GCREGAHBDECREADEXCONFIG_COUNT (32U)
13005
13006/*! @name GCREGAHBDECREADSTRIDE - Decoder Read Stride */
13007/*! @{ */
13008#define DEC400D_GCREGAHBDECREADSTRIDE_STRIDE_MASK (0x3FFFFU)
13009#define DEC400D_GCREGAHBDECREADSTRIDE_STRIDE_SHIFT (0U)
13010#define DEC400D_GCREGAHBDECREADSTRIDE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADSTRIDE_STRIDE_SHIFT)) & DEC400D_GCREGAHBDECREADSTRIDE_STRIDE_MASK)
13011/*! @} */
13012
13013/* The count of DEC400D_GCREGAHBDECREADSTRIDE */
13014#define DEC400D_GCREGAHBDECREADSTRIDE_COUNT (32U)
13015
13016/*! @name GCREGAHBDECREADBUFFEREND - Decoder Read Buffer End */
13017/*! @{ */
13018#define DEC400D_GCREGAHBDECREADBUFFEREND_RD_BUFF_END_MASK (0xFFFFFFFFU)
13019#define DEC400D_GCREGAHBDECREADBUFFEREND_RD_BUFF_END_SHIFT (0U)
13020#define DEC400D_GCREGAHBDECREADBUFFEREND_RD_BUFF_END(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADBUFFEREND_RD_BUFF_END_SHIFT)) & DEC400D_GCREGAHBDECREADBUFFEREND_RD_BUFF_END_MASK)
13021/*! @} */
13022
13023/* The count of DEC400D_GCREGAHBDECREADBUFFEREND */
13024#define DEC400D_GCREGAHBDECREADBUFFEREND_COUNT (32U)
13025
13026
13027/*!
13028 * @}
13029 */ /* end of group DEC400D_Register_Masks */
13030
13031
13032/* DEC400D - Peripheral instance base addresses */
13033/** Peripheral DCSS__DEC400D base address */
13034#define DCSS__DEC400D_BASE (0x32E15000u)
13035/** Peripheral DCSS__DEC400D base pointer */
13036#define DCSS__DEC400D ((DEC400D_Type *)DCSS__DEC400D_BASE)
13037/** Array initializer of DEC400D peripheral base addresses */
13038#define DEC400D_BASE_ADDRS { DCSS__DEC400D_BASE }
13039/** Array initializer of DEC400D peripheral base pointers */
13040#define DEC400D_BASE_PTRS { DCSS__DEC400D }
13041
13042/*!
13043 * @}
13044 */ /* end of group DEC400D_Peripheral_Access_Layer */
13045
13046
13047/* ----------------------------------------------------------------------------
13048 -- DPR Peripheral Access Layer
13049 ---------------------------------------------------------------------------- */
13050
13051/*!
13052 * @addtogroup DPR_Peripheral_Access_Layer DPR Peripheral Access Layer
13053 * @{
13054 */
13055
13056/** DPR - Register Layout Typedef */
13057typedef struct {
13058 struct { /* offset: 0x0 */
13059 __IO uint32_t RW; /**< System Control 0, offset: 0x0 */
13060 __IO uint32_t SET; /**< System Control 0, offset: 0x4 */
13061 __IO uint32_t CLR; /**< System Control 0, offset: 0x8 */
13062 __IO uint32_t TOG; /**< System Control 0, offset: 0xC */
13063 } SYSTEM_CTRL0;
13064 uint8_t RESERVED_0[16];
13065 struct { /* offset: 0x20 */
13066 __IO uint32_t RW; /**< Interrupt Mask, offset: 0x20 */
13067 __IO uint32_t SET; /**< Interrupt Mask, offset: 0x24 */
13068 __IO uint32_t CLR; /**< Interrupt Mask, offset: 0x28 */
13069 __IO uint32_t TOG; /**< Interrupt Mask, offset: 0x2C */
13070 } IRQ_MASK;
13071 struct { /* offset: 0x30 */
13072 __I uint32_t RW; /**< Status Register of Masked IRQ, offset: 0x30 */
13073 __I uint32_t SET; /**< Status Register of Masked IRQ, offset: 0x34 */
13074 __I uint32_t CLR; /**< Status Register of Masked IRQ, offset: 0x38 */
13075 __I uint32_t TOG; /**< Status Register of Masked IRQ, offset: 0x3C */
13076 } IRQ_MASK_STATUS;
13077 struct { /* offset: 0x40 */
13078 __IO uint32_t RW; /**< Status of Non-Masked IRQ, offset: 0x40 */
13079 __IO uint32_t SET; /**< Status of Non-Masked IRQ, offset: 0x44 */
13080 __IO uint32_t CLR; /**< Status of Non-Masked IRQ, offset: 0x48 */
13081 __IO uint32_t TOG; /**< Status of Non-Masked IRQ, offset: 0x4C */
13082 } IRQ_NONMASK_STATUS;
13083 struct { /* offset: 0x50 */
13084 __IO uint32_t RW; /**< Mode Control 0, offset: 0x50 */
13085 __IO uint32_t SET; /**< Mode Control 0, offset: 0x54 */
13086 __IO uint32_t CLR; /**< Mode Control 0, offset: 0x58 */
13087 __IO uint32_t TOG; /**< Mode Control 0, offset: 0x5C */
13088 } MODE_CTRL0;
13089 uint8_t RESERVED_1[16];
13090 struct { /* offset: 0x70 */
13091 __IO uint32_t RW; /**< Frame Control 0, offset: 0x70 */
13092 __IO uint32_t SET; /**< Frame Control 0, offset: 0x74 */
13093 __IO uint32_t CLR; /**< Frame Control 0, offset: 0x78 */
13094 __IO uint32_t TOG; /**< Frame Control 0, offset: 0x7C */
13095 } FRAME_CTRL0;
13096 uint8_t RESERVED_2[16];
13097 struct { /* offset: 0x90 */
13098 __IO uint32_t RW; /**< Frame 1-Plane Control 0, offset: 0x90 */
13099 __IO uint32_t SET; /**< Frame 1-Plane Control 0, offset: 0x94 */
13100 __IO uint32_t CLR; /**< Frame 1-Plane Control 0, offset: 0x98 */
13101 __IO uint32_t TOG; /**< Frame 1-Plane Control 0, offset: 0x9C */
13102 } FRAME_1P_CTRL0;
13103 struct { /* offset: 0xA0 */
13104 __IO uint32_t RW; /**< Frame 1-Plane Pix X Control, offset: 0xA0 */
13105 __IO uint32_t SET; /**< Frame 1-Plane Pix X Control, offset: 0xA4 */
13106 __IO uint32_t CLR; /**< Frame 1-Plane Pix X Control, offset: 0xA8 */
13107 __IO uint32_t TOG; /**< Frame 1-Plane Pix X Control, offset: 0xAC */
13108 } FRAME_1P_PIX_X_CTRL;
13109 struct { /* offset: 0xB0 */
13110 __IO uint32_t RW; /**< Frame 1-Plane Pix Y Control, offset: 0xB0 */
13111 __IO uint32_t SET; /**< Frame 1-Plane Pix Y Control, offset: 0xB4 */
13112 __IO uint32_t CLR; /**< Frame 1-Plane Pix Y Control, offset: 0xB8 */
13113 __IO uint32_t TOG; /**< Frame 1-Plane Pix Y Control, offset: 0xBC */
13114 } FRAME_1P_PIX_Y_CTRL;
13115 struct { /* offset: 0xC0 */
13116 __IO uint32_t RW; /**< Frame 1-Plane Base Address Control 0, offset: 0xC0 */
13117 __IO uint32_t SET; /**< Frame 1-Plane Base Address Control 0, offset: 0xC4 */
13118 __IO uint32_t CLR; /**< Frame 1-Plane Base Address Control 0, offset: 0xC8 */
13119 __IO uint32_t TOG; /**< Frame 1-Plane Base Address Control 0, offset: 0xCC */
13120 } FRAME_1P_BASE_ADDR_CTRL0;
13121 uint8_t RESERVED_3[16];
13122 struct { /* offset: 0xE0 */
13123 __IO uint32_t RW; /**< Frame 2-Plane Control 0, offset: 0xE0 */
13124 __IO uint32_t SET; /**< Frame 2-Plane Control 0, offset: 0xE4 */
13125 __IO uint32_t CLR; /**< Frame 2-Plane Control 0, offset: 0xE8 */
13126 __IO uint32_t TOG; /**< Frame 2-Plane Control 0, offset: 0xEC */
13127 } FRAME_2P_CTRL0;
13128 struct { /* offset: 0xF0 */
13129 __IO uint32_t RW; /**< Frame 2-Plane Pix X Control, offset: 0xF0 */
13130 __IO uint32_t SET; /**< Frame 2-Plane Pix X Control, offset: 0xF4 */
13131 __IO uint32_t CLR; /**< Frame 2-Plane Pix X Control, offset: 0xF8 */
13132 __IO uint32_t TOG; /**< Frame 2-Plane Pix X Control, offset: 0xFC */
13133 } FRAME_2P_PIX_X_CTRL;
13134 struct { /* offset: 0x100 */
13135 __IO uint32_t RW; /**< Frame 2-Plane Pix Y Control, offset: 0x100 */
13136 __IO uint32_t SET; /**< Frame 2-Plane Pix Y Control, offset: 0x104 */
13137 __IO uint32_t CLR; /**< Frame 2-Plane Pix Y Control, offset: 0x108 */
13138 __IO uint32_t TOG; /**< Frame 2-Plane Pix Y Control, offset: 0x10C */
13139 } FRAME_2P_PIX_Y_CTRL;
13140 struct { /* offset: 0x110 */
13141 __IO uint32_t RW; /**< Frame 2-Plane Base Address Control 0, offset: 0x110 */
13142 __IO uint32_t SET; /**< Frame 2-Plane Base Address Control 0, offset: 0x114 */
13143 __IO uint32_t CLR; /**< Frame 2-Plane Base Address Control 0, offset: 0x118 */
13144 __IO uint32_t TOG; /**< Frame 2-Plane Base Address Control 0, offset: 0x11C */
13145 } FRAME_2P_BASE_ADDR_CTRL0;
13146 uint8_t RESERVED_4[224];
13147 struct { /* offset: 0x200 */
13148 __IO uint32_t RW; /**< RTRAM Control 0, offset: 0x200 */
13149 __IO uint32_t SET; /**< RTRAM Control 0, offset: 0x204 */
13150 __IO uint32_t CLR; /**< RTRAM Control 0, offset: 0x208 */
13151 __IO uint32_t TOG; /**< RTRAM Control 0, offset: 0x20C */
13152 } RTRAM_CTRL0;
13153} DPR_Type;
13154
13155/* ----------------------------------------------------------------------------
13156 -- DPR Register Masks
13157 ---------------------------------------------------------------------------- */
13158
13159/*!
13160 * @addtogroup DPR_Register_Masks DPR Register Masks
13161 * @{
13162 */
13163
13164/*! @name SYSTEM_CTRL0 - System Control 0 */
13165/*! @{ */
13166#define DPR_SYSTEM_CTRL0_RUN_EN_MASK (0x1U)
13167#define DPR_SYSTEM_CTRL0_RUN_EN_SHIFT (0U)
13168#define DPR_SYSTEM_CTRL0_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_RUN_EN_SHIFT)) & DPR_SYSTEM_CTRL0_RUN_EN_MASK)
13169#define DPR_SYSTEM_CTRL0_SOFT_RESET_MASK (0x2U)
13170#define DPR_SYSTEM_CTRL0_SOFT_RESET_SHIFT (1U)
13171#define DPR_SYSTEM_CTRL0_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SOFT_RESET_SHIFT)) & DPR_SYSTEM_CTRL0_SOFT_RESET_MASK)
13172#define DPR_SYSTEM_CTRL0_REPEAT_EN_MASK (0x4U)
13173#define DPR_SYSTEM_CTRL0_REPEAT_EN_SHIFT (2U)
13174#define DPR_SYSTEM_CTRL0_REPEAT_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_REPEAT_EN_SHIFT)) & DPR_SYSTEM_CTRL0_REPEAT_EN_MASK)
13175#define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_MASK (0x8U)
13176#define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_SHIFT (3U)
13177#define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_SHIFT)) & DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_MASK)
13178#define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_MASK (0x10U)
13179#define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_SHIFT (4U)
13180#define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_SHIFT)) & DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_MASK)
13181#define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_MASK (0x10000U)
13182#define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_SHIFT (16U)
13183#define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_SHIFT)) & DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_MASK)
13184/*! @} */
13185
13186/*! @name IRQ_MASK - Interrupt Mask */
13187/*! @{ */
13188#define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_MASK (0x1U)
13189#define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_SHIFT (0U)
13190#define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_MASK)
13191#define DPR_IRQ_MASK_IRQ_DPR_RUN_MASK (0x2U)
13192#define DPR_IRQ_MASK_IRQ_DPR_RUN_SHIFT (1U)
13193#define DPR_IRQ_MASK_IRQ_DPR_RUN(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_RUN_MASK)
13194#define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_MASK (0x4U)
13195#define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_SHIFT (2U)
13196#define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_MASK)
13197#define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_MASK (0x8U)
13198#define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_SHIFT (3U)
13199#define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_MASK)
13200#define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U)
13201#define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U)
13202#define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_MASK)
13203#define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U)
13204#define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U)
13205#define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_MASK)
13206#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U)
13207#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U)
13208#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK)
13209#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U)
13210#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U)
13211#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK)
13212/*! @} */
13213
13214/*! @name IRQ_MASK_STATUS - Status Register of Masked IRQ */
13215/*! @{ */
13216#define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_MASK (0x1U)
13217#define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT (0U)
13218#define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_MASK)
13219#define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_MASK (0x2U)
13220#define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_SHIFT (1U)
13221#define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_MASK)
13222#define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_MASK (0x4U)
13223#define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_SHIFT (2U)
13224#define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_MASK)
13225#define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_MASK (0x8U)
13226#define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT (3U)
13227#define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_MASK)
13228#define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U)
13229#define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U)
13230#define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK)
13231#define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U)
13232#define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U)
13233#define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK)
13234#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U)
13235#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U)
13236#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK)
13237#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U)
13238#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U)
13239#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK)
13240/*! @} */
13241
13242/*! @name IRQ_NONMASK_STATUS - Status of Non-Masked IRQ */
13243/*! @{ */
13244#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_MASK (0x1U)
13245#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT (0U)
13246#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_MASK)
13247#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_MASK (0x2U)
13248#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_SHIFT (1U)
13249#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_MASK)
13250#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_MASK (0x4U)
13251#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_SHIFT (2U)
13252#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_MASK)
13253#define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_MASK (0x8U)
13254#define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT (3U)
13255#define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_MASK)
13256#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U)
13257#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U)
13258#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK)
13259#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U)
13260#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U)
13261#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK)
13262#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U)
13263#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U)
13264#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK)
13265#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U)
13266#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U)
13267#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK)
13268/*! @} */
13269
13270/*! @name MODE_CTRL0 - Mode Control 0 */
13271/*! @{ */
13272#define DPR_MODE_CTRL0_RTR_3BUF_EN_MASK (0x1U)
13273#define DPR_MODE_CTRL0_RTR_3BUF_EN_SHIFT (0U)
13274#define DPR_MODE_CTRL0_RTR_3BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_RTR_3BUF_EN_SHIFT)) & DPR_MODE_CTRL0_RTR_3BUF_EN_MASK)
13275#define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_MASK (0x2U)
13276#define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_SHIFT (1U)
13277#define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_SHIFT)) & DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_MASK)
13278#define DPR_MODE_CTRL0_TILE_TYPE_MASK (0x1CU)
13279#define DPR_MODE_CTRL0_TILE_TYPE_SHIFT (2U)
13280#define DPR_MODE_CTRL0_TILE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_TILE_TYPE_SHIFT)) & DPR_MODE_CTRL0_TILE_TYPE_MASK)
13281#define DPR_MODE_CTRL0_YUV_EN_MASK (0x40U)
13282#define DPR_MODE_CTRL0_YUV_EN_SHIFT (6U)
13283#define DPR_MODE_CTRL0_YUV_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_YUV_EN_SHIFT)) & DPR_MODE_CTRL0_YUV_EN_MASK)
13284#define DPR_MODE_CTRL0_COMP_2PLANE_EN_MASK (0x80U)
13285#define DPR_MODE_CTRL0_COMP_2PLANE_EN_SHIFT (7U)
13286#define DPR_MODE_CTRL0_COMP_2PLANE_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_COMP_2PLANE_EN_SHIFT)) & DPR_MODE_CTRL0_COMP_2PLANE_EN_MASK)
13287#define DPR_MODE_CTRL0_PIX_SIZE_MASK (0x300U)
13288#define DPR_MODE_CTRL0_PIX_SIZE_SHIFT (8U)
13289#define DPR_MODE_CTRL0_PIX_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_SIZE_SHIFT)) & DPR_MODE_CTRL0_PIX_SIZE_MASK)
13290#define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_MASK (0x400U)
13291#define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_SHIFT (10U)
13292#define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_SHIFT)) & DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_MASK)
13293#define DPR_MODE_CTRL0_PIX_UV_SWAP_MASK (0x800U)
13294#define DPR_MODE_CTRL0_PIX_UV_SWAP_SHIFT (11U)
13295#define DPR_MODE_CTRL0_PIX_UV_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_UV_SWAP_SHIFT)) & DPR_MODE_CTRL0_PIX_UV_SWAP_MASK)
13296#define DPR_MODE_CTRL0_B_COMP_SEL_MASK (0x3000U)
13297#define DPR_MODE_CTRL0_B_COMP_SEL_SHIFT (12U)
13298#define DPR_MODE_CTRL0_B_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_B_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_B_COMP_SEL_MASK)
13299#define DPR_MODE_CTRL0_G_COMP_SEL_MASK (0xC000U)
13300#define DPR_MODE_CTRL0_G_COMP_SEL_SHIFT (14U)
13301#define DPR_MODE_CTRL0_G_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_G_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_G_COMP_SEL_MASK)
13302#define DPR_MODE_CTRL0_R_COMP_SEL_MASK (0x30000U)
13303#define DPR_MODE_CTRL0_R_COMP_SEL_SHIFT (16U)
13304#define DPR_MODE_CTRL0_R_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_R_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_R_COMP_SEL_MASK)
13305#define DPR_MODE_CTRL0_A_COMP_SEL_MASK (0xC0000U)
13306#define DPR_MODE_CTRL0_A_COMP_SEL_SHIFT (18U)
13307#define DPR_MODE_CTRL0_A_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_A_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_A_COMP_SEL_MASK)
13308/*! @} */
13309
13310/*! @name FRAME_CTRL0 - Frame Control 0 */
13311/*! @{ */
13312#define DPR_FRAME_CTRL0_HFLIP_EN_MASK (0x1U)
13313#define DPR_FRAME_CTRL0_HFLIP_EN_SHIFT (0U)
13314#define DPR_FRAME_CTRL0_HFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_HFLIP_EN_SHIFT)) & DPR_FRAME_CTRL0_HFLIP_EN_MASK)
13315#define DPR_FRAME_CTRL0_VFLIP_EN_MASK (0x2U)
13316#define DPR_FRAME_CTRL0_VFLIP_EN_SHIFT (1U)
13317#define DPR_FRAME_CTRL0_VFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_VFLIP_EN_SHIFT)) & DPR_FRAME_CTRL0_VFLIP_EN_MASK)
13318#define DPR_FRAME_CTRL0_ROT_ENC_MASK (0xCU)
13319#define DPR_FRAME_CTRL0_ROT_ENC_SHIFT (2U)
13320#define DPR_FRAME_CTRL0_ROT_ENC(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_ROT_ENC_SHIFT)) & DPR_FRAME_CTRL0_ROT_ENC_MASK)
13321#define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_MASK (0x10U)
13322#define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_SHIFT (4U)
13323#define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_SHIFT)) & DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_MASK)
13324#define DPR_FRAME_CTRL0_PITCH_MASK (0xFFFF0000U)
13325#define DPR_FRAME_CTRL0_PITCH_SHIFT (16U)
13326#define DPR_FRAME_CTRL0_PITCH(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_PITCH_SHIFT)) & DPR_FRAME_CTRL0_PITCH_MASK)
13327/*! @} */
13328
13329/*! @name FRAME_1P_CTRL0 - Frame 1-Plane Control 0 */
13330/*! @{ */
13331#define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_MASK (0x7U)
13332#define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_SHIFT (0U)
13333#define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_SHIFT)) & DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_MASK)
13334/*! @} */
13335
13336/*! @name FRAME_1P_PIX_X_CTRL - Frame 1-Plane Pix X Control */
13337/*! @{ */
13338#define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK (0xFFFFU)
13339#define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT (0U)
13340#define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT)) & DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK)
13341#define DPR_FRAME_1P_PIX_X_CTRL_CROP_ULC_X_MASK (0xFFFF0000U)
13342#define DPR_FRAME_1P_PIX_X_CTRL_CROP_ULC_X_SHIFT (16U)
13343#define DPR_FRAME_1P_PIX_X_CTRL_CROP_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_X_CTRL_CROP_ULC_X_SHIFT)) & DPR_FRAME_1P_PIX_X_CTRL_CROP_ULC_X_MASK)
13344/*! @} */
13345
13346/*! @name FRAME_1P_PIX_Y_CTRL - Frame 1-Plane Pix Y Control */
13347/*! @{ */
13348#define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK (0xFFFFU)
13349#define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT (0U)
13350#define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT)) & DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK)
13351#define DPR_FRAME_1P_PIX_Y_CTRL_CROP_ULC_Y_MASK (0xFFFF0000U)
13352#define DPR_FRAME_1P_PIX_Y_CTRL_CROP_ULC_Y_SHIFT (16U)
13353#define DPR_FRAME_1P_PIX_Y_CTRL_CROP_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_Y_CTRL_CROP_ULC_Y_SHIFT)) & DPR_FRAME_1P_PIX_Y_CTRL_CROP_ULC_Y_MASK)
13354/*! @} */
13355
13356/*! @name FRAME_1P_BASE_ADDR_CTRL0 - Frame 1-Plane Base Address Control 0 */
13357/*! @{ */
13358#define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_MASK (0xFFFFFFFFU)
13359#define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT (0U)
13360#define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT)) & DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_MASK)
13361/*! @} */
13362
13363/*! @name FRAME_2P_CTRL0 - Frame 2-Plane Control 0 */
13364/*! @{ */
13365#define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_MASK (0x7U)
13366#define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_SHIFT (0U)
13367#define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_SHIFT)) & DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_MASK)
13368/*! @} */
13369
13370/*! @name FRAME_2P_PIX_X_CTRL - Frame 2-Plane Pix X Control */
13371/*! @{ */
13372#define DPR_FRAME_2P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK (0xFFFFU)
13373#define DPR_FRAME_2P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT (0U)
13374#define DPR_FRAME_2P_PIX_X_CTRL_NUM_X_PIX_WIDE(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT)) & DPR_FRAME_2P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK)
13375#define DPR_FRAME_2P_PIX_X_CTRL_CROP_ULC_X_MASK (0xFFFF0000U)
13376#define DPR_FRAME_2P_PIX_X_CTRL_CROP_ULC_X_SHIFT (16U)
13377#define DPR_FRAME_2P_PIX_X_CTRL_CROP_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_PIX_X_CTRL_CROP_ULC_X_SHIFT)) & DPR_FRAME_2P_PIX_X_CTRL_CROP_ULC_X_MASK)
13378/*! @} */
13379
13380/*! @name FRAME_2P_PIX_Y_CTRL - Frame 2-Plane Pix Y Control */
13381/*! @{ */
13382#define DPR_FRAME_2P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK (0xFFFFU)
13383#define DPR_FRAME_2P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT (0U)
13384#define DPR_FRAME_2P_PIX_Y_CTRL_NUM_Y_PIX_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT)) & DPR_FRAME_2P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK)
13385#define DPR_FRAME_2P_PIX_Y_CTRL_CROP_ULC_Y_MASK (0xFFFF0000U)
13386#define DPR_FRAME_2P_PIX_Y_CTRL_CROP_ULC_Y_SHIFT (16U)
13387#define DPR_FRAME_2P_PIX_Y_CTRL_CROP_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_PIX_Y_CTRL_CROP_ULC_Y_SHIFT)) & DPR_FRAME_2P_PIX_Y_CTRL_CROP_ULC_Y_MASK)
13388/*! @} */
13389
13390/*! @name FRAME_2P_BASE_ADDR_CTRL0 - Frame 2-Plane Base Address Control 0 */
13391/*! @{ */
13392#define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_MASK (0xFFFFFFFFU)
13393#define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT (0U)
13394#define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT)) & DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_MASK)
13395/*! @} */
13396
13397/*! @name RTRAM_CTRL0 - RTRAM Control 0 */
13398/*! @{ */
13399#define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_MASK (0x1U)
13400#define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_SHIFT (0U)
13401#define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_SHIFT)) & DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_MASK)
13402#define DPR_RTRAM_CTRL0_THRES_HIGH_MASK (0xEU)
13403#define DPR_RTRAM_CTRL0_THRES_HIGH_SHIFT (1U)
13404#define DPR_RTRAM_CTRL0_THRES_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_THRES_HIGH_SHIFT)) & DPR_RTRAM_CTRL0_THRES_HIGH_MASK)
13405#define DPR_RTRAM_CTRL0_THRES_LOW_MASK (0x70U)
13406#define DPR_RTRAM_CTRL0_THRES_LOW_SHIFT (4U)
13407#define DPR_RTRAM_CTRL0_THRES_LOW(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_THRES_LOW_SHIFT)) & DPR_RTRAM_CTRL0_THRES_LOW_MASK)
13408#define DPR_RTRAM_CTRL0_ABORT_SEL_MASK (0x80U)
13409#define DPR_RTRAM_CTRL0_ABORT_SEL_SHIFT (7U)
13410#define DPR_RTRAM_CTRL0_ABORT_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_ABORT_SEL_SHIFT)) & DPR_RTRAM_CTRL0_ABORT_SEL_MASK)
13411/*! @} */
13412
13413
13414/*!
13415 * @}
13416 */ /* end of group DPR_Register_Masks */
13417
13418
13419/* DPR - Peripheral instance base addresses */
13420/** Peripheral DCSS__DPR1 base address */
13421#define DCSS__DPR1_BASE (0x32E18000u)
13422/** Peripheral DCSS__DPR1 base pointer */
13423#define DCSS__DPR1 ((DPR_Type *)DCSS__DPR1_BASE)
13424/** Peripheral DCSS__DPR2 base address */
13425#define DCSS__DPR2_BASE (0x32E19000u)
13426/** Peripheral DCSS__DPR2 base pointer */
13427#define DCSS__DPR2 ((DPR_Type *)DCSS__DPR2_BASE)
13428/** Peripheral DCSS__DPR3 base address */
13429#define DCSS__DPR3_BASE (0x32E1A000u)
13430/** Peripheral DCSS__DPR3 base pointer */
13431#define DCSS__DPR3 ((DPR_Type *)DCSS__DPR3_BASE)
13432/** Array initializer of DPR peripheral base addresses */
13433#define DPR_BASE_ADDRS { 0u, DCSS__DPR1_BASE, DCSS__DPR2_BASE, DCSS__DPR3_BASE }
13434/** Array initializer of DPR peripheral base pointers */
13435#define DPR_BASE_PTRS { (DPR_Type *)0u, DCSS__DPR1, DCSS__DPR2, DCSS__DPR3 }
13436
13437/*!
13438 * @}
13439 */ /* end of group DPR_Peripheral_Access_Layer */
13440
13441
13442/* ----------------------------------------------------------------------------
13443 -- DTG Peripheral Access Layer
13444 ---------------------------------------------------------------------------- */
13445
13446/*!
13447 * @addtogroup DTG_Peripheral_Access_Layer DTG Peripheral Access Layer
13448 * @{
13449 */
13450
13451/** DTG - Register Layout Typedef */
13452typedef struct {
13453 __IO uint32_t TC_CONTROL_STATUS; /**< Timing Controller Control Register, offset: 0x0 */
13454 __IO uint32_t TC_DTG_REG1; /**< DTG lower right corner locations, offset: 0x4 */
13455 __IO uint32_t TC_DISPLAY_REG2; /**< Display Register: TOP Window Coordinates for Active display area, offset: 0x8 */
13456 __IO uint32_t TC_DISPLAY_REG3; /**< Display Register: BOTTOM Window Coordinates for Active display area, offset: 0xC */
13457 __IO uint32_t TC_CH1_REG4; /**< Channel 1 window Register: TOP Window Coordinates for channel1, offset: 0x10 */
13458 __IO uint32_t TC_CH1_REG5; /**< Channel_1 window Register: BOTTOM Window Coordinates for channel_1 window, offset: 0x14 */
13459 __IO uint32_t TC_CH2_REG6; /**< Channel 2 window Register: TOP Window Coordinates for channel_2, offset: 0x18 */
13460 __IO uint32_t TC_CH2_REG7; /**< Channel_2 window Register: BOTTOM Window Coordinates for channel_2 pixel window, offset: 0x1C */
13461 __IO uint32_t TC_CH3_REG8; /**< Channel 3 window Register: TOP Window Coordinates for channel_3, offset: 0x20 */
13462 __IO uint32_t TC_CH3_REG9; /**< Channel_3 window Register: BOTTOM Window Coordinates for channel_3 pixel window, offset: 0x24 */
13463 __IO uint32_t TC_CTX_LD_REG10; /**< Context Loader Register: Coordinates in the raster table where the context loader is started., offset: 0x28 */
13464 __IO uint32_t TC_CH1_BKRND_REG11; /**< Channel_1 background pixel color., offset: 0x2C */
13465 __IO uint32_t TC_CH2_BKRND_REG12; /**< Channel_2 background pixel color., offset: 0x30 */
13466 uint8_t RESERVED_0[4];
13467 __IO uint32_t BLENDER_DBY_EOTF_RANGEINV; /**< DBY MODE Blender control., offset: 0x38 */
13468 __IO uint32_t BLENDER_DBY_EOTF_RANGEMIN; /**< DBY MODE Blender control., offset: 0x3C */
13469 __IO uint32_t BLENDER_DBY_BDP; /**< DBY MODE blender control., offset: 0x40 */
13470 __IO uint32_t BLENDER_BKRND_I_GRAPHICS; /**< Backgound pixel color component sent to blender. Used when no valid pixels, offset: 0x44 */
13471 __IO uint32_t BLENDER_BKRND_P_GRAPHICS; /**< Backgound pixel color component sent to blender. Used when no valid pixels, offset: 0x48 */
13472 __IO uint32_t BLENDER_BKRND_T_GRAPHICS; /**< Backgound pixel color component sent to blender. Used when no valid pixels, offset: 0x4C */
13473 __IO uint32_t TC_LINE1_INT_REG13; /**< LINE1 interrupt control: Coordinate where line1 interrupt is asserted, offset: 0x50 */
13474 __IO uint32_t TC_LINE2_INT_REG14; /**< LINE2 interrupt control: Coordinate where line2 interrupt is asserted, offset: 0x54 */
13475 __IO uint32_t TC_ALPHA_DEFAULT_REG15; /**< default alpha, offset: 0x58 */
13476 __I uint32_t TC_INTERRUPT_STATUS; /**< Timing Controller interrupt status, offset: 0x5C */
13477 __IO uint32_t TC_INTRERRUPT_CONTROL_REG17; /**< Timing Controller interrupt control., offset: 0x60 */
13478 __IO uint32_t TC_CH3_BKRND_REG18; /**< Channel_3 background pixel color., offset: 0x64 */
13479 __IO uint32_t TC_INTRERRUPT_MASK; /**< Timing Controller interrupt masks, offset: 0x68 */
13480 __IO uint32_t TC_LINE3_INT_REG; /**< LINE3 interrupt control: Coordinate where line3 interrupt is asserted, offset: 0x6C */
13481 __IO uint32_t TC_LINE4_INT_REG; /**< LINE4 interrupt control: Coordinate where line4 interrupt is asserted, offset: 0x70 */
13482 __IO uint32_t TC_OL_DE_CONTROL_REG; /**< For DBY Mode: Controls the assertion and de-assertion DE signal (Overlay channel)., offset: 0x74 */
13483 __IO uint32_t TC_BL_DE_CONTROL_REG; /**< For DBY Mode: Controls the assertion and de-assertion DE signal (Base layer (BL) channel)., offset: 0x78 */
13484 __IO uint32_t TC_EL_DE_CONTROL_REG; /**< For DBY Mode: Controls the assertion and de-assertion DE signal (Enhancement layer (EL) channel)., offset: 0x7C */
13485} DTG_Type;
13486
13487/* ----------------------------------------------------------------------------
13488 -- DTG Register Masks
13489 ---------------------------------------------------------------------------- */
13490
13491/*!
13492 * @addtogroup DTG_Register_Masks DTG Register Masks
13493 * @{
13494 */
13495
13496/*! @name TC_CONTROL_STATUS - Timing Controller Control Register */
13497/*! @{ */
13498#define DTG_TC_CONTROL_STATUS_TC_VIDEO_BASE_PATH_ENABLE_MASK (0x1U)
13499#define DTG_TC_CONTROL_STATUS_TC_VIDEO_BASE_PATH_ENABLE_SHIFT (0U)
13500#define DTG_TC_CONTROL_STATUS_TC_VIDEO_BASE_PATH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_VIDEO_BASE_PATH_ENABLE_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_VIDEO_BASE_PATH_ENABLE_MASK)
13501#define DTG_TC_CONTROL_STATUS_TC_VIDEO_ENH_PATH_ENABLE_MASK (0x2U)
13502#define DTG_TC_CONTROL_STATUS_TC_VIDEO_ENH_PATH_ENABLE_SHIFT (1U)
13503#define DTG_TC_CONTROL_STATUS_TC_VIDEO_ENH_PATH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_VIDEO_ENH_PATH_ENABLE_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_VIDEO_ENH_PATH_ENABLE_MASK)
13504#define DTG_TC_CONTROL_STATUS_TC_OVERLAY_PATH_ENABLE_MASK (0x4U)
13505#define DTG_TC_CONTROL_STATUS_TC_OVERLAY_PATH_ENABLE_SHIFT (2U)
13506#define DTG_TC_CONTROL_STATUS_TC_OVERLAY_PATH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_OVERLAY_PATH_ENABLE_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_OVERLAY_PATH_ENABLE_MASK)
13507#define DTG_TC_CONTROL_STATUS_TC_OVERLAY_FIFO_DATA_MODE_MASK (0x8U)
13508#define DTG_TC_CONTROL_STATUS_TC_OVERLAY_FIFO_DATA_MODE_SHIFT (3U)
13509#define DTG_TC_CONTROL_STATUS_TC_OVERLAY_FIFO_DATA_MODE(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_OVERLAY_FIFO_DATA_MODE_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_OVERLAY_FIFO_DATA_MODE_MASK)
13510#define DTG_TC_CONTROL_STATUS_TC_BLENDER_VIDEO_ALPHA_SELECT_MASK (0x80U)
13511#define DTG_TC_CONTROL_STATUS_TC_BLENDER_VIDEO_ALPHA_SELECT_SHIFT (7U)
13512#define DTG_TC_CONTROL_STATUS_TC_BLENDER_VIDEO_ALPHA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_BLENDER_VIDEO_ALPHA_SELECT_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_BLENDER_VIDEO_ALPHA_SELECT_MASK)
13513#define DTG_TC_CONTROL_STATUS_TC_GO_MASK (0x100U)
13514#define DTG_TC_CONTROL_STATUS_TC_GO_SHIFT (8U)
13515#define DTG_TC_CONTROL_STATUS_TC_GO(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_GO_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_GO_MASK)
13516#define DTG_TC_CONTROL_STATUS_TC_DOLBY_MODE_MASK (0x200U)
13517#define DTG_TC_CONTROL_STATUS_TC_DOLBY_MODE_SHIFT (9U)
13518#define DTG_TC_CONTROL_STATUS_TC_DOLBY_MODE(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_DOLBY_MODE_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_DOLBY_MODE_MASK)
13519#define DTG_TC_CONTROL_STATUS_TC_CH1_PER_PEL_ALPHA_SEL_MASK (0x400U)
13520#define DTG_TC_CONTROL_STATUS_TC_CH1_PER_PEL_ALPHA_SEL_SHIFT (10U)
13521#define DTG_TC_CONTROL_STATUS_TC_CH1_PER_PEL_ALPHA_SEL(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_CH1_PER_PEL_ALPHA_SEL_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_CH1_PER_PEL_ALPHA_SEL_MASK)
13522#define DTG_TC_CONTROL_STATUS_TC_CSS_PIX_COMP_SWAP_MASK (0x7000U)
13523#define DTG_TC_CONTROL_STATUS_TC_CSS_PIX_COMP_SWAP_SHIFT (12U)
13524#define DTG_TC_CONTROL_STATUS_TC_CSS_PIX_COMP_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_CSS_PIX_COMP_SWAP_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_CSS_PIX_COMP_SWAP_MASK)
13525#define DTG_TC_CONTROL_STATUS_TC_DEFAULT_OVERLAY_ALPHA_MASK (0xFF000000U)
13526#define DTG_TC_CONTROL_STATUS_TC_DEFAULT_OVERLAY_ALPHA_SHIFT (24U)
13527#define DTG_TC_CONTROL_STATUS_TC_DEFAULT_OVERLAY_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_DEFAULT_OVERLAY_ALPHA_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_DEFAULT_OVERLAY_ALPHA_MASK)
13528/*! @} */
13529
13530/*! @name TC_DTG_REG1 - DTG lower right corner locations */
13531/*! @{ */
13532#define DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_X_MASK (0x1FFFU)
13533#define DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_X_SHIFT (0U)
13534#define DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_X_SHIFT)) & DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_X_MASK)
13535#define DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_Y_MASK (0x1FFF0000U)
13536#define DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_Y_SHIFT (16U)
13537#define DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_Y_SHIFT)) & DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_Y_MASK)
13538/*! @} */
13539
13540/*! @name TC_DISPLAY_REG2 - Display Register: TOP Window Coordinates for Active display area */
13541/*! @{ */
13542#define DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_X_MASK (0x1FFFU)
13543#define DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_X_SHIFT (0U)
13544#define DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_X_SHIFT)) & DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_X_MASK)
13545#define DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_Y_MASK (0x1FFF0000U)
13546#define DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_Y_SHIFT (16U)
13547#define DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_Y_SHIFT)) & DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_Y_MASK)
13548/*! @} */
13549
13550/*! @name TC_DISPLAY_REG3 - Display Register: BOTTOM Window Coordinates for Active display area */
13551/*! @{ */
13552#define DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_X_MASK (0x1FFFU)
13553#define DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_X_SHIFT (0U)
13554#define DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_X_SHIFT)) & DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_X_MASK)
13555#define DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_Y_MASK (0x1FFF0000U)
13556#define DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_Y_SHIFT (16U)
13557#define DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_Y_SHIFT)) & DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_Y_MASK)
13558/*! @} */
13559
13560/*! @name TC_CH1_REG4 - Channel 1 window Register: TOP Window Coordinates for channel1 */
13561/*! @{ */
13562#define DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_X_MASK (0x1FFFU)
13563#define DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_X_SHIFT (0U)
13564#define DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_X_SHIFT)) & DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_X_MASK)
13565#define DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_Y_MASK (0x1FFF0000U)
13566#define DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_Y_SHIFT (16U)
13567#define DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_Y_SHIFT)) & DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_Y_MASK)
13568/*! @} */
13569
13570/*! @name TC_CH1_REG5 - Channel_1 window Register: BOTTOM Window Coordinates for channel_1 window */
13571/*! @{ */
13572#define DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_X_MASK (0x1FFFU)
13573#define DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_X_SHIFT (0U)
13574#define DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_X_SHIFT)) & DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_X_MASK)
13575#define DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_Y_MASK (0x1FFF0000U)
13576#define DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_Y_SHIFT (16U)
13577#define DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_Y_SHIFT)) & DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_Y_MASK)
13578/*! @} */
13579
13580/*! @name TC_CH2_REG6 - Channel 2 window Register: TOP Window Coordinates for channel_2 */
13581/*! @{ */
13582#define DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_X_MASK (0x1FFFU)
13583#define DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_X_SHIFT (0U)
13584#define DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_X_SHIFT)) & DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_X_MASK)
13585#define DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_Y_MASK (0x1FFF0000U)
13586#define DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_Y_SHIFT (16U)
13587#define DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_Y_SHIFT)) & DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_Y_MASK)
13588/*! @} */
13589
13590/*! @name TC_CH2_REG7 - Channel_2 window Register: BOTTOM Window Coordinates for channel_2 pixel window */
13591/*! @{ */
13592#define DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_X_MASK (0x1FFFU)
13593#define DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_X_SHIFT (0U)
13594#define DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_X_SHIFT)) & DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_X_MASK)
13595#define DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_Y_MASK (0x1FFF0000U)
13596#define DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_Y_SHIFT (16U)
13597#define DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_Y_SHIFT)) & DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_Y_MASK)
13598/*! @} */
13599
13600/*! @name TC_CH3_REG8 - Channel 3 window Register: TOP Window Coordinates for channel_3 */
13601/*! @{ */
13602#define DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_X_MASK (0x1FFFU)
13603#define DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_X_SHIFT (0U)
13604#define DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_X_SHIFT)) & DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_X_MASK)
13605#define DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_Y_MASK (0x1FFF0000U)
13606#define DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_Y_SHIFT (16U)
13607#define DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_Y_SHIFT)) & DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_Y_MASK)
13608/*! @} */
13609
13610/*! @name TC_CH3_REG9 - Channel_3 window Register: BOTTOM Window Coordinates for channel_3 pixel window */
13611/*! @{ */
13612#define DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_X_MASK (0x1FFFU)
13613#define DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_X_SHIFT (0U)
13614#define DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_X_SHIFT)) & DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_X_MASK)
13615#define DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_Y_MASK (0x1FFF0000U)
13616#define DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_Y_SHIFT (16U)
13617#define DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_Y_SHIFT)) & DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_Y_MASK)
13618/*! @} */
13619
13620/*! @name TC_CTX_LD_REG10 - Context Loader Register: Coordinates in the raster table where the context loader is started. */
13621/*! @{ */
13622#define DTG_TC_CTX_LD_REG10_TC_CNTXT_DB_LINE_COUNT_MASK (0x1FFFU)
13623#define DTG_TC_CTX_LD_REG10_TC_CNTXT_DB_LINE_COUNT_SHIFT (0U)
13624#define DTG_TC_CTX_LD_REG10_TC_CNTXT_DB_LINE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CTX_LD_REG10_TC_CNTXT_DB_LINE_COUNT_SHIFT)) & DTG_TC_CTX_LD_REG10_TC_CNTXT_DB_LINE_COUNT_MASK)
13625#define DTG_TC_CTX_LD_REG10_TC_CNTXT_SB_LINE_COUNT_MASK (0x1FFF0000U)
13626#define DTG_TC_CTX_LD_REG10_TC_CNTXT_SB_LINE_COUNT_SHIFT (16U)
13627#define DTG_TC_CTX_LD_REG10_TC_CNTXT_SB_LINE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CTX_LD_REG10_TC_CNTXT_SB_LINE_COUNT_SHIFT)) & DTG_TC_CTX_LD_REG10_TC_CNTXT_SB_LINE_COUNT_MASK)
13628/*! @} */
13629
13630/*! @name TC_CH1_BKRND_REG11 - Channel_1 background pixel color. */
13631/*! @{ */
13632#define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_3_MASK (0x3FFU)
13633#define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_3_SHIFT (0U)
13634#define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_3(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_3_SHIFT)) & DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_3_MASK)
13635#define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_2_MASK (0xFFC00U)
13636#define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_2_SHIFT (10U)
13637#define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_2(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_2_SHIFT)) & DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_2_MASK)
13638#define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_1_MASK (0x3FF00000U)
13639#define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_1_SHIFT (20U)
13640#define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_1(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_1_SHIFT)) & DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_1_MASK)
13641/*! @} */
13642
13643/*! @name TC_CH2_BKRND_REG12 - Channel_2 background pixel color. */
13644/*! @{ */
13645#define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_3_MASK (0x3FFU)
13646#define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_3_SHIFT (0U)
13647#define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_3(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_3_SHIFT)) & DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_3_MASK)
13648#define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_2_MASK (0xFFC00U)
13649#define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_2_SHIFT (10U)
13650#define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_2(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_2_SHIFT)) & DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_2_MASK)
13651#define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_1_MASK (0x3FF00000U)
13652#define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_1_SHIFT (20U)
13653#define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_1(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_1_SHIFT)) & DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_1_MASK)
13654/*! @} */
13655
13656/*! @name BLENDER_DBY_EOTF_RANGEINV - DBY MODE Blender control. */
13657/*! @{ */
13658#define DTG_BLENDER_DBY_EOTF_RANGEINV_BLENDER_EOTF_RANGEINV_MASK (0x1FFFFU)
13659#define DTG_BLENDER_DBY_EOTF_RANGEINV_BLENDER_EOTF_RANGEINV_SHIFT (0U)
13660#define DTG_BLENDER_DBY_EOTF_RANGEINV_BLENDER_EOTF_RANGEINV(x) (((uint32_t)(((uint32_t)(x)) << DTG_BLENDER_DBY_EOTF_RANGEINV_BLENDER_EOTF_RANGEINV_SHIFT)) & DTG_BLENDER_DBY_EOTF_RANGEINV_BLENDER_EOTF_RANGEINV_MASK)
13661/*! @} */
13662
13663/*! @name BLENDER_DBY_EOTF_RANGEMIN - DBY MODE Blender control. */
13664/*! @{ */
13665#define DTG_BLENDER_DBY_EOTF_RANGEMIN_BLENDER_EOTF_RANGEMIN_MASK (0x1FFFFU)
13666#define DTG_BLENDER_DBY_EOTF_RANGEMIN_BLENDER_EOTF_RANGEMIN_SHIFT (0U)
13667#define DTG_BLENDER_DBY_EOTF_RANGEMIN_BLENDER_EOTF_RANGEMIN(x) (((uint32_t)(((uint32_t)(x)) << DTG_BLENDER_DBY_EOTF_RANGEMIN_BLENDER_EOTF_RANGEMIN_SHIFT)) & DTG_BLENDER_DBY_EOTF_RANGEMIN_BLENDER_EOTF_RANGEMIN_MASK)
13668/*! @} */
13669
13670/*! @name BLENDER_DBY_BDP - DBY MODE blender control. */
13671/*! @{ */
13672#define DTG_BLENDER_DBY_BDP_BLENDER_BDP_MASK (0x1FU)
13673#define DTG_BLENDER_DBY_BDP_BLENDER_BDP_SHIFT (0U)
13674#define DTG_BLENDER_DBY_BDP_BLENDER_BDP(x) (((uint32_t)(((uint32_t)(x)) << DTG_BLENDER_DBY_BDP_BLENDER_BDP_SHIFT)) & DTG_BLENDER_DBY_BDP_BLENDER_BDP_MASK)
13675/*! @} */
13676
13677/*! @name BLENDER_BKRND_I_GRAPHICS - Backgound pixel color component sent to blender. Used when no valid pixels */
13678/*! @{ */
13679#define DTG_BLENDER_BKRND_I_GRAPHICS_BLENDER_BCKRND_I_COMP_MASK (0xFFFFFFFU)
13680#define DTG_BLENDER_BKRND_I_GRAPHICS_BLENDER_BCKRND_I_COMP_SHIFT (0U)
13681#define DTG_BLENDER_BKRND_I_GRAPHICS_BLENDER_BCKRND_I_COMP(x) (((uint32_t)(((uint32_t)(x)) << DTG_BLENDER_BKRND_I_GRAPHICS_BLENDER_BCKRND_I_COMP_SHIFT)) & DTG_BLENDER_BKRND_I_GRAPHICS_BLENDER_BCKRND_I_COMP_MASK)
13682/*! @} */
13683
13684/*! @name BLENDER_BKRND_P_GRAPHICS - Backgound pixel color component sent to blender. Used when no valid pixels */
13685/*! @{ */
13686#define DTG_BLENDER_BKRND_P_GRAPHICS_BLENDER_BCKRND_P_COMP_MASK (0xFFFFFFFU)
13687#define DTG_BLENDER_BKRND_P_GRAPHICS_BLENDER_BCKRND_P_COMP_SHIFT (0U)
13688#define DTG_BLENDER_BKRND_P_GRAPHICS_BLENDER_BCKRND_P_COMP(x) (((uint32_t)(((uint32_t)(x)) << DTG_BLENDER_BKRND_P_GRAPHICS_BLENDER_BCKRND_P_COMP_SHIFT)) & DTG_BLENDER_BKRND_P_GRAPHICS_BLENDER_BCKRND_P_COMP_MASK)
13689/*! @} */
13690
13691/*! @name BLENDER_BKRND_T_GRAPHICS - Backgound pixel color component sent to blender. Used when no valid pixels */
13692/*! @{ */
13693#define DTG_BLENDER_BKRND_T_GRAPHICS_BLENDER_BCKRND_T_COMP_MASK (0xFFFFFFFU)
13694#define DTG_BLENDER_BKRND_T_GRAPHICS_BLENDER_BCKRND_T_COMP_SHIFT (0U)
13695#define DTG_BLENDER_BKRND_T_GRAPHICS_BLENDER_BCKRND_T_COMP(x) (((uint32_t)(((uint32_t)(x)) << DTG_BLENDER_BKRND_T_GRAPHICS_BLENDER_BCKRND_T_COMP_SHIFT)) & DTG_BLENDER_BKRND_T_GRAPHICS_BLENDER_BCKRND_T_COMP_MASK)
13696/*! @} */
13697
13698/*! @name TC_LINE1_INT_REG13 - LINE1 interrupt control: Coordinate where line1 interrupt is asserted */
13699/*! @{ */
13700#define DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_X_MASK (0x1FFFU)
13701#define DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_X_SHIFT (0U)
13702#define DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_X_SHIFT)) & DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_X_MASK)
13703#define DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_Y_MASK (0x1FFF0000U)
13704#define DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_Y_SHIFT (16U)
13705#define DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_Y_SHIFT)) & DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_Y_MASK)
13706/*! @} */
13707
13708/*! @name TC_LINE2_INT_REG14 - LINE2 interrupt control: Coordinate where line2 interrupt is asserted */
13709/*! @{ */
13710#define DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_X_MASK (0x1FFFU)
13711#define DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_X_SHIFT (0U)
13712#define DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_X_SHIFT)) & DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_X_MASK)
13713#define DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_Y_MASK (0x1FFF0000U)
13714#define DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_Y_SHIFT (16U)
13715#define DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_Y_SHIFT)) & DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_Y_MASK)
13716/*! @} */
13717
13718/*! @name TC_ALPHA_DEFAULT_REG15 - default alpha */
13719/*! @{ */
13720#define DTG_TC_ALPHA_DEFAULT_REG15_TC_ALPHA_DEF_MASK (0xFFU)
13721#define DTG_TC_ALPHA_DEFAULT_REG15_TC_ALPHA_DEF_SHIFT (0U)
13722#define DTG_TC_ALPHA_DEFAULT_REG15_TC_ALPHA_DEF(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_ALPHA_DEFAULT_REG15_TC_ALPHA_DEF_SHIFT)) & DTG_TC_ALPHA_DEFAULT_REG15_TC_ALPHA_DEF_MASK)
13723/*! @} */
13724
13725/*! @name TC_INTERRUPT_STATUS - Timing Controller interrupt status */
13726/*! @{ */
13727#define DTG_TC_INTERRUPT_STATUS_TC_LINE0_INTERRUPT_MASK (0x1U)
13728#define DTG_TC_INTERRUPT_STATUS_TC_LINE0_INTERRUPT_SHIFT (0U)
13729#define DTG_TC_INTERRUPT_STATUS_TC_LINE0_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_LINE0_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_LINE0_INTERRUPT_MASK)
13730#define DTG_TC_INTERRUPT_STATUS_TC_LINE1_INTERRUPT_MASK (0x2U)
13731#define DTG_TC_INTERRUPT_STATUS_TC_LINE1_INTERRUPT_SHIFT (1U)
13732#define DTG_TC_INTERRUPT_STATUS_TC_LINE1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_LINE1_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_LINE1_INTERRUPT_MASK)
13733#define DTG_TC_INTERRUPT_STATUS_TC_LINE2_INTERRUPT_MASK (0x4U)
13734#define DTG_TC_INTERRUPT_STATUS_TC_LINE2_INTERRUPT_SHIFT (2U)
13735#define DTG_TC_INTERRUPT_STATUS_TC_LINE2_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_LINE2_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_LINE2_INTERRUPT_MASK)
13736#define DTG_TC_INTERRUPT_STATUS_TC_LINE3_INTERRUPT_MASK (0x8U)
13737#define DTG_TC_INTERRUPT_STATUS_TC_LINE3_INTERRUPT_SHIFT (3U)
13738#define DTG_TC_INTERRUPT_STATUS_TC_LINE3_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_LINE3_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_LINE3_INTERRUPT_MASK)
13739#define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH1_PANIC_INTERRUPT_MASK (0x10U)
13740#define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH1_PANIC_INTERRUPT_SHIFT (4U)
13741#define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH1_PANIC_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH1_PANIC_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH1_PANIC_INTERRUPT_MASK)
13742#define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH2_PANIC_INTERRUPT_MASK (0x20U)
13743#define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH2_PANIC_INTERRUPT_SHIFT (5U)
13744#define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH2_PANIC_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH2_PANIC_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH2_PANIC_INTERRUPT_MASK)
13745#define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH3_PANIC_INTERRUPT_MASK (0x40U)
13746#define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH3_PANIC_INTERRUPT_SHIFT (6U)
13747#define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH3_PANIC_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH3_PANIC_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH3_PANIC_INTERRUPT_MASK)
13748/*! @} */
13749
13750/*! @name TC_INTRERRUPT_CONTROL_REG17 - Timing Controller interrupt control. */
13751/*! @{ */
13752#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE0_INTERRUPT_CLR_MASK (0x1U)
13753#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE0_INTERRUPT_CLR_SHIFT (0U)
13754#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE0_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE0_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE0_INTERRUPT_CLR_MASK)
13755#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE1_INTERRUPT_CLR_MASK (0x2U)
13756#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE1_INTERRUPT_CLR_SHIFT (1U)
13757#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE1_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE1_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE1_INTERRUPT_CLR_MASK)
13758#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE2_INTERRUPT_CLR_MASK (0x4U)
13759#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE2_INTERRUPT_CLR_SHIFT (2U)
13760#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE2_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE2_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE2_INTERRUPT_CLR_MASK)
13761#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE3_INTERRUPT_CLR_MASK (0x8U)
13762#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE3_INTERRUPT_CLR_SHIFT (3U)
13763#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE3_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE3_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE3_INTERRUPT_CLR_MASK)
13764#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH1_PANIC_INTERRUPT_CLR_MASK (0x10U)
13765#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH1_PANIC_INTERRUPT_CLR_SHIFT (4U)
13766#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH1_PANIC_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH1_PANIC_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH1_PANIC_INTERRUPT_CLR_MASK)
13767#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH2_PANIC_INTERRUPT_CLR_MASK (0x20U)
13768#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH2_PANIC_INTERRUPT_CLR_SHIFT (5U)
13769#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH2_PANIC_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH2_PANIC_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH2_PANIC_INTERRUPT_CLR_MASK)
13770#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH3_PANIC_INTERRUPT_CLR_MASK (0x40U)
13771#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH3_PANIC_INTERRUPT_CLR_SHIFT (6U)
13772#define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH3_PANIC_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH3_PANIC_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH3_PANIC_INTERRUPT_CLR_MASK)
13773/*! @} */
13774
13775/*! @name TC_CH3_BKRND_REG18 - Channel_3 background pixel color. */
13776/*! @{ */
13777#define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_3_MASK (0x3FFU)
13778#define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_3_SHIFT (0U)
13779#define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_3(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_3_SHIFT)) & DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_3_MASK)
13780#define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_2_MASK (0xFFC00U)
13781#define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_2_SHIFT (10U)
13782#define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_2(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_2_SHIFT)) & DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_2_MASK)
13783#define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_1_MASK (0x3FF00000U)
13784#define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_1_SHIFT (20U)
13785#define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_1(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_1_SHIFT)) & DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_1_MASK)
13786/*! @} */
13787
13788/*! @name TC_INTRERRUPT_MASK - Timing Controller interrupt masks */
13789/*! @{ */
13790#define DTG_TC_INTRERRUPT_MASK_TC_LINE0_INT_MASK_MASK (0x1U)
13791#define DTG_TC_INTRERRUPT_MASK_TC_LINE0_INT_MASK_SHIFT (0U)
13792#define DTG_TC_INTRERRUPT_MASK_TC_LINE0_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_LINE0_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_LINE0_INT_MASK_MASK)
13793#define DTG_TC_INTRERRUPT_MASK_TC_LINE1_INT_MASK_MASK (0x2U)
13794#define DTG_TC_INTRERRUPT_MASK_TC_LINE1_INT_MASK_SHIFT (1U)
13795#define DTG_TC_INTRERRUPT_MASK_TC_LINE1_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_LINE1_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_LINE1_INT_MASK_MASK)
13796#define DTG_TC_INTRERRUPT_MASK_TC_LINE2_INT_MASK_MASK (0x4U)
13797#define DTG_TC_INTRERRUPT_MASK_TC_LINE2_INT_MASK_SHIFT (2U)
13798#define DTG_TC_INTRERRUPT_MASK_TC_LINE2_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_LINE2_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_LINE2_INT_MASK_MASK)
13799#define DTG_TC_INTRERRUPT_MASK_TC_LINE3_INT_MASK_MASK (0x8U)
13800#define DTG_TC_INTRERRUPT_MASK_TC_LINE3_INT_MASK_SHIFT (3U)
13801#define DTG_TC_INTRERRUPT_MASK_TC_LINE3_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_LINE3_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_LINE3_INT_MASK_MASK)
13802#define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH1_PANIC_INT_MASK_MASK (0x10U)
13803#define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH1_PANIC_INT_MASK_SHIFT (4U)
13804#define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH1_PANIC_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH1_PANIC_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH1_PANIC_INT_MASK_MASK)
13805#define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH2_PANIC_INT_MASK_MASK (0x20U)
13806#define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH2_PANIC_INT_MASK_SHIFT (5U)
13807#define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH2_PANIC_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH2_PANIC_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH2_PANIC_INT_MASK_MASK)
13808#define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH3_PANIC_INT_MASK_MASK (0x40U)
13809#define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH3_PANIC_INT_MASK_SHIFT (6U)
13810#define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH3_PANIC_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH3_PANIC_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH3_PANIC_INT_MASK_MASK)
13811/*! @} */
13812
13813/*! @name TC_LINE3_INT_REG - LINE3 interrupt control: Coordinate where line3 interrupt is asserted */
13814/*! @{ */
13815#define DTG_TC_LINE3_INT_REG_TC_LINE3_INT_X_MASK (0x1FFFU)
13816#define DTG_TC_LINE3_INT_REG_TC_LINE3_INT_X_SHIFT (0U)
13817#define DTG_TC_LINE3_INT_REG_TC_LINE3_INT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE3_INT_REG_TC_LINE3_INT_X_SHIFT)) & DTG_TC_LINE3_INT_REG_TC_LINE3_INT_X_MASK)
13818#define DTG_TC_LINE3_INT_REG_TC_LINE3_INT_Y_MASK (0x1FFF0000U)
13819#define DTG_TC_LINE3_INT_REG_TC_LINE3_INT_Y_SHIFT (16U)
13820#define DTG_TC_LINE3_INT_REG_TC_LINE3_INT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE3_INT_REG_TC_LINE3_INT_Y_SHIFT)) & DTG_TC_LINE3_INT_REG_TC_LINE3_INT_Y_MASK)
13821/*! @} */
13822
13823/*! @name TC_LINE4_INT_REG - LINE4 interrupt control: Coordinate where line4 interrupt is asserted */
13824/*! @{ */
13825#define DTG_TC_LINE4_INT_REG_TC_LINE4_INT_X_MASK (0x1FFFU)
13826#define DTG_TC_LINE4_INT_REG_TC_LINE4_INT_X_SHIFT (0U)
13827#define DTG_TC_LINE4_INT_REG_TC_LINE4_INT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE4_INT_REG_TC_LINE4_INT_X_SHIFT)) & DTG_TC_LINE4_INT_REG_TC_LINE4_INT_X_MASK)
13828#define DTG_TC_LINE4_INT_REG_TC_LINE4_INT_Y_MASK (0x1FFF0000U)
13829#define DTG_TC_LINE4_INT_REG_TC_LINE4_INT_Y_SHIFT (16U)
13830#define DTG_TC_LINE4_INT_REG_TC_LINE4_INT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE4_INT_REG_TC_LINE4_INT_Y_SHIFT)) & DTG_TC_LINE4_INT_REG_TC_LINE4_INT_Y_MASK)
13831/*! @} */
13832
13833/*! @name TC_OL_DE_CONTROL_REG - For DBY Mode: Controls the assertion and de-assertion DE signal (Overlay channel). */
13834/*! @{ */
13835#define DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_LOW_X_MASK (0x1FFFU)
13836#define DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_LOW_X_SHIFT (0U)
13837#define DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_LOW_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_LOW_X_SHIFT)) & DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_LOW_X_MASK)
13838#define DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_MASK (0x1FFF0000U)
13839#define DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_SHIFT (16U)
13840#define DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_HIGH_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_SHIFT)) & DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_MASK)
13841#define DTG_TC_OL_DE_CONTROL_REG_TC_INVERT_DE_X_MASK (0x80000000U)
13842#define DTG_TC_OL_DE_CONTROL_REG_TC_INVERT_DE_X_SHIFT (31U)
13843#define DTG_TC_OL_DE_CONTROL_REG_TC_INVERT_DE_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_OL_DE_CONTROL_REG_TC_INVERT_DE_X_SHIFT)) & DTG_TC_OL_DE_CONTROL_REG_TC_INVERT_DE_X_MASK)
13844/*! @} */
13845
13846/*! @name TC_BL_DE_CONTROL_REG - For DBY Mode: Controls the assertion and de-assertion DE signal (Base layer (BL) channel). */
13847/*! @{ */
13848#define DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_LOW_X_MASK (0x1FFFU)
13849#define DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_LOW_X_SHIFT (0U)
13850#define DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_LOW_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_LOW_X_SHIFT)) & DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_LOW_X_MASK)
13851#define DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_MASK (0x1FFF0000U)
13852#define DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_SHIFT (16U)
13853#define DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_HIGH_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_SHIFT)) & DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_MASK)
13854#define DTG_TC_BL_DE_CONTROL_REG_TC_INVERT_DE_X_MASK (0x80000000U)
13855#define DTG_TC_BL_DE_CONTROL_REG_TC_INVERT_DE_X_SHIFT (31U)
13856#define DTG_TC_BL_DE_CONTROL_REG_TC_INVERT_DE_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_BL_DE_CONTROL_REG_TC_INVERT_DE_X_SHIFT)) & DTG_TC_BL_DE_CONTROL_REG_TC_INVERT_DE_X_MASK)
13857/*! @} */
13858
13859/*! @name TC_EL_DE_CONTROL_REG - For DBY Mode: Controls the assertion and de-assertion DE signal (Enhancement layer (EL) channel). */
13860/*! @{ */
13861#define DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_LOW_X_MASK (0x1FFFU)
13862#define DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_LOW_X_SHIFT (0U)
13863#define DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_LOW_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_LOW_X_SHIFT)) & DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_LOW_X_MASK)
13864#define DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_MASK (0x1FFF0000U)
13865#define DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_SHIFT (16U)
13866#define DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_HIGH_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_SHIFT)) & DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_MASK)
13867#define DTG_TC_EL_DE_CONTROL_REG_TC_INVERT_DE_X_MASK (0x80000000U)
13868#define DTG_TC_EL_DE_CONTROL_REG_TC_INVERT_DE_X_SHIFT (31U)
13869#define DTG_TC_EL_DE_CONTROL_REG_TC_INVERT_DE_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_EL_DE_CONTROL_REG_TC_INVERT_DE_X_SHIFT)) & DTG_TC_EL_DE_CONTROL_REG_TC_INVERT_DE_X_MASK)
13870/*! @} */
13871
13872
13873/*!
13874 * @}
13875 */ /* end of group DTG_Register_Masks */
13876
13877
13878/* DTG - Peripheral instance base addresses */
13879/** Peripheral DCSS__DTG base address */
13880#define DCSS__DTG_BASE (0x32E20000u)
13881/** Peripheral DCSS__DTG base pointer */
13882#define DCSS__DTG ((DTG_Type *)DCSS__DTG_BASE)
13883/** Array initializer of DTG peripheral base addresses */
13884#define DTG_BASE_ADDRS { DCSS__DTG_BASE }
13885/** Array initializer of DTG peripheral base pointers */
13886#define DTG_BASE_PTRS { DCSS__DTG }
13887
13888/*!
13889 * @}
13890 */ /* end of group DTG_Peripheral_Access_Layer */
13891
13892
13893/* ----------------------------------------------------------------------------
13894 -- DTRC Peripheral Access Layer
13895 ---------------------------------------------------------------------------- */
13896
13897/*!
13898 * @addtogroup DTRC_Peripheral_Access_Layer DTRC Peripheral Access Layer
13899 * @{
13900 */
13901
13902/** DTRC - Register Layout Typedef */
13903typedef struct {
13904 struct { /* offset: 0x0, array step: 0x60 */
13905 __IO uint32_t FDYDSADDR; /**< Luma video data start address, array offset: 0x0, array step: 0x60 */
13906 __IO uint32_t FDCDSADDR; /**< Chroma video data start address, array offset: 0x4, array step: 0x60 */
13907 __IO uint32_t FDYTSADDR; /**< Luma table data start address, array offset: 0x8, array step: 0x60 */
13908 __IO uint32_t FDCTSADDR; /**< Chroma table data start address, array offset: 0xC, array step: 0x60 */
13909 __IO uint32_t FSIZE; /**< Frame size, array offset: 0x10, array step: 0x60 */
13910 __IO uint32_t FSYSSA; /**< Luma data slave start address, array offset: 0x14, array step: 0x60 */
13911 __IO uint32_t FSYSEA; /**< Luma data slave end address, array offset: 0x18, array step: 0x60 */
13912 __IO uint32_t FSUVSSA; /**< Chroma data slave start address, array offset: 0x1C, array step: 0x60 */
13913 __IO uint32_t FSUVSEA; /**< Chroma data slave end address, array offset: 0x20, array step: 0x60 */
13914 __IO uint32_t FCROPORIG; /**< Cropped picture origin, array offset: 0x24, array step: 0x60 */
13915 __IO uint32_t FCROPSIZE; /**< Cropped picture size, array offset: 0x28, array step: 0x60 */
13916 __IO uint32_t FDCTL; /**< Frame data control, array offset: 0x2C, array step: 0x60 */
13917 uint8_t RESERVED_0[48];
13918 } FRAME_REGISTERS[2];
13919 __IO uint32_t DTRCINTEN; /**< DTRC Interrupt enables, offset: 0xC0 */
13920 __IO uint32_t FDINTR; /**< DTRC Interrupt Requests, offset: 0xC4 */
13921 __IO uint32_t DTCTRL; /**< DTRC Control, offset: 0xC8 */
13922 __IO uint32_t ARIDR; /**< ARIDR, offset: 0xCC */
13923 __IO uint32_t DTID2DDR; /**< DTID2DDR, offset: 0xD0 */
13924 __I uint32_t DTRCCONFIG; /**< DTRCCONFIG, offset: 0xD4 */
13925 __I uint32_t DTRCVERSION; /**< DTRC Version, offset: 0xD8 */
13926 uint8_t RESERVED_0[20];
13927 __IO uint32_t PFCTRL; /**< Performance counter control, offset: 0xF0 */
13928 __IO uint32_t PFCR; /**< Performance counter, offset: 0xF4 */
13929 __IO uint32_t TOCR; /**< Time Out Cycles, offset: 0xF8 */
13930} DTRC_Type;
13931
13932/* ----------------------------------------------------------------------------
13933 -- DTRC Register Masks
13934 ---------------------------------------------------------------------------- */
13935
13936/*!
13937 * @addtogroup DTRC_Register_Masks DTRC Register Masks
13938 * @{
13939 */
13940
13941/*! @name FDYDSADDR - Luma video data start address */
13942/*! @{ */
13943#define DTRC_FDYDSADDR_F0DYDSADDR_MASK (0xFFFFFFFFU)
13944#define DTRC_FDYDSADDR_F0DYDSADDR_SHIFT (0U)
13945#define DTRC_FDYDSADDR_F0DYDSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDYDSADDR_F0DYDSADDR_SHIFT)) & DTRC_FDYDSADDR_F0DYDSADDR_MASK)
13946#define DTRC_FDYDSADDR_F1DYDSADDR_MASK (0xFFFFFFFFU)
13947#define DTRC_FDYDSADDR_F1DYDSADDR_SHIFT (0U)
13948#define DTRC_FDYDSADDR_F1DYDSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDYDSADDR_F1DYDSADDR_SHIFT)) & DTRC_FDYDSADDR_F1DYDSADDR_MASK)
13949/*! @} */
13950
13951/* The count of DTRC_FDYDSADDR */
13952#define DTRC_FDYDSADDR_COUNT (2U)
13953
13954/*! @name FDCDSADDR - Chroma video data start address */
13955/*! @{ */
13956#define DTRC_FDCDSADDR_F0DCDSADDR_MASK (0xFFFFFFFFU)
13957#define DTRC_FDCDSADDR_F0DCDSADDR_SHIFT (0U)
13958#define DTRC_FDCDSADDR_F0DCDSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCDSADDR_F0DCDSADDR_SHIFT)) & DTRC_FDCDSADDR_F0DCDSADDR_MASK)
13959#define DTRC_FDCDSADDR_F1DCDSADDR_MASK (0xFFFFFFFFU)
13960#define DTRC_FDCDSADDR_F1DCDSADDR_SHIFT (0U)
13961#define DTRC_FDCDSADDR_F1DCDSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCDSADDR_F1DCDSADDR_SHIFT)) & DTRC_FDCDSADDR_F1DCDSADDR_MASK)
13962/*! @} */
13963
13964/* The count of DTRC_FDCDSADDR */
13965#define DTRC_FDCDSADDR_COUNT (2U)
13966
13967/*! @name FDYTSADDR - Luma table data start address */
13968/*! @{ */
13969#define DTRC_FDYTSADDR_F0DYTSADDR_MASK (0xFFFFFFFFU)
13970#define DTRC_FDYTSADDR_F0DYTSADDR_SHIFT (0U)
13971#define DTRC_FDYTSADDR_F0DYTSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDYTSADDR_F0DYTSADDR_SHIFT)) & DTRC_FDYTSADDR_F0DYTSADDR_MASK)
13972#define DTRC_FDYTSADDR_F1DYTSADDR_MASK (0xFFFFFFFFU)
13973#define DTRC_FDYTSADDR_F1DYTSADDR_SHIFT (0U)
13974#define DTRC_FDYTSADDR_F1DYTSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDYTSADDR_F1DYTSADDR_SHIFT)) & DTRC_FDYTSADDR_F1DYTSADDR_MASK)
13975/*! @} */
13976
13977/* The count of DTRC_FDYTSADDR */
13978#define DTRC_FDYTSADDR_COUNT (2U)
13979
13980/*! @name FDCTSADDR - Chroma table data start address */
13981/*! @{ */
13982#define DTRC_FDCTSADDR_F0DCTSADDR_MASK (0xFFFFFFFFU)
13983#define DTRC_FDCTSADDR_F0DCTSADDR_SHIFT (0U)
13984#define DTRC_FDCTSADDR_F0DCTSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTSADDR_F0DCTSADDR_SHIFT)) & DTRC_FDCTSADDR_F0DCTSADDR_MASK)
13985#define DTRC_FDCTSADDR_F1DCTSADDR_MASK (0xFFFFFFFFU)
13986#define DTRC_FDCTSADDR_F1DCTSADDR_SHIFT (0U)
13987#define DTRC_FDCTSADDR_F1DCTSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTSADDR_F1DCTSADDR_SHIFT)) & DTRC_FDCTSADDR_F1DCTSADDR_MASK)
13988/*! @} */
13989
13990/* The count of DTRC_FDCTSADDR */
13991#define DTRC_FDCTSADDR_COUNT (2U)
13992
13993/*! @name FSIZE - Frame size */
13994/*! @{ */
13995#define DTRC_FSIZE_F0WIDTH_MASK (0x3FFU)
13996#define DTRC_FSIZE_F0WIDTH_SHIFT (0U)
13997#define DTRC_FSIZE_F0WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSIZE_F0WIDTH_SHIFT)) & DTRC_FSIZE_F0WIDTH_MASK)
13998#define DTRC_FSIZE_F1WIDTH_MASK (0x3FFU)
13999#define DTRC_FSIZE_F1WIDTH_SHIFT (0U)
14000#define DTRC_FSIZE_F1WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSIZE_F1WIDTH_SHIFT)) & DTRC_FSIZE_F1WIDTH_MASK)
14001#define DTRC_FSIZE_F0HEIGHT_MASK (0x3FF0000U)
14002#define DTRC_FSIZE_F0HEIGHT_SHIFT (16U)
14003#define DTRC_FSIZE_F0HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSIZE_F0HEIGHT_SHIFT)) & DTRC_FSIZE_F0HEIGHT_MASK)
14004#define DTRC_FSIZE_F1HEIGHT_MASK (0x3FF0000U)
14005#define DTRC_FSIZE_F1HEIGHT_SHIFT (16U)
14006#define DTRC_FSIZE_F1HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSIZE_F1HEIGHT_SHIFT)) & DTRC_FSIZE_F1HEIGHT_MASK)
14007/*! @} */
14008
14009/* The count of DTRC_FSIZE */
14010#define DTRC_FSIZE_COUNT (2U)
14011
14012/*! @name FSYSSA - Luma data slave start address */
14013/*! @{ */
14014#define DTRC_FSYSSA_F0YSTRBYPASS_MASK (0x1U)
14015#define DTRC_FSYSSA_F0YSTRBYPASS_SHIFT (0U)
14016/*! F0YSTRBYPASS - Luma Start Tile to Raster scan Bypass
14017 * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic.
14018 * 0b1..All ARADDR bypasses the tile-to-rasterscan logic.
14019 */
14020#define DTRC_FSYSSA_F0YSTRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSSA_F0YSTRBYPASS_SHIFT)) & DTRC_FSYSSA_F0YSTRBYPASS_MASK)
14021#define DTRC_FSYSSA_F1YSTRBYPASS_MASK (0x1U)
14022#define DTRC_FSYSSA_F1YSTRBYPASS_SHIFT (0U)
14023/*! F1YSTRBYPASS - Luma Start Tile to Raster scan Bypass
14024 * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic.
14025 * 0b1..All ARADDR bypasses the tile-to-rasterscan logic.
14026 */
14027#define DTRC_FSYSSA_F1YSTRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSSA_F1YSTRBYPASS_SHIFT)) & DTRC_FSYSSA_F1YSTRBYPASS_MASK)
14028#define DTRC_FSYSSA_F0SYSSA_MASK (0xFFFFFFF0U)
14029#define DTRC_FSYSSA_F0SYSSA_SHIFT (4U)
14030#define DTRC_FSYSSA_F0SYSSA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSSA_F0SYSSA_SHIFT)) & DTRC_FSYSSA_F0SYSSA_MASK)
14031#define DTRC_FSYSSA_F1SYSSA_MASK (0xFFFFFFF0U)
14032#define DTRC_FSYSSA_F1SYSSA_SHIFT (4U)
14033#define DTRC_FSYSSA_F1SYSSA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSSA_F1SYSSA_SHIFT)) & DTRC_FSYSSA_F1SYSSA_MASK)
14034/*! @} */
14035
14036/* The count of DTRC_FSYSSA */
14037#define DTRC_FSYSSA_COUNT (2U)
14038
14039/*! @name FSYSEA - Luma data slave end address */
14040/*! @{ */
14041#define DTRC_FSYSEA_F0YETRBYPASS_MASK (0x1U)
14042#define DTRC_FSYSEA_F0YETRBYPASS_SHIFT (0U)
14043/*! F0YETRBYPASS - End Tile to Raster scan Bypass
14044 * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic.
14045 * 0b1..All ARADDR bypasses the tile-to-rasterscan logic.
14046 */
14047#define DTRC_FSYSEA_F0YETRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSEA_F0YETRBYPASS_SHIFT)) & DTRC_FSYSEA_F0YETRBYPASS_MASK)
14048#define DTRC_FSYSEA_F1YETRBYPASS_MASK (0x1U)
14049#define DTRC_FSYSEA_F1YETRBYPASS_SHIFT (0U)
14050/*! F1YETRBYPASS - End Tile to Raster scan Bypass
14051 * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic.
14052 * 0b1..All ARADDR bypasses the tile-to-rasterscan logic.
14053 */
14054#define DTRC_FSYSEA_F1YETRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSEA_F1YETRBYPASS_SHIFT)) & DTRC_FSYSEA_F1YETRBYPASS_MASK)
14055#define DTRC_FSYSEA_F0SYSEA_MASK (0xFFFFFFF0U)
14056#define DTRC_FSYSEA_F0SYSEA_SHIFT (4U)
14057#define DTRC_FSYSEA_F0SYSEA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSEA_F0SYSEA_SHIFT)) & DTRC_FSYSEA_F0SYSEA_MASK)
14058#define DTRC_FSYSEA_F1SYSEA_MASK (0xFFFFFFF0U)
14059#define DTRC_FSYSEA_F1SYSEA_SHIFT (4U)
14060#define DTRC_FSYSEA_F1SYSEA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSEA_F1SYSEA_SHIFT)) & DTRC_FSYSEA_F1SYSEA_MASK)
14061/*! @} */
14062
14063/* The count of DTRC_FSYSEA */
14064#define DTRC_FSYSEA_COUNT (2U)
14065
14066/*! @name FSUVSSA - Chroma data slave start address */
14067/*! @{ */
14068#define DTRC_FSUVSSA_F0CSTRBYPASS_MASK (0x1U)
14069#define DTRC_FSUVSSA_F0CSTRBYPASS_SHIFT (0U)
14070/*! F0CSTRBYPASS - Chroma Start Tile to Raster scan Bypass
14071 * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic.
14072 * 0b1..All ARADDR bypasses the tile-to-rasterscan logic.
14073 */
14074#define DTRC_FSUVSSA_F0CSTRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSSA_F0CSTRBYPASS_SHIFT)) & DTRC_FSUVSSA_F0CSTRBYPASS_MASK)
14075#define DTRC_FSUVSSA_F1CSTRBYPASS_MASK (0x1U)
14076#define DTRC_FSUVSSA_F1CSTRBYPASS_SHIFT (0U)
14077/*! F1CSTRBYPASS - Chroma Start Tile to Raster scan Bypass
14078 * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic.
14079 * 0b1..All ARADDR bypasses the tile-to-rasterscan logic.
14080 */
14081#define DTRC_FSUVSSA_F1CSTRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSSA_F1CSTRBYPASS_SHIFT)) & DTRC_FSUVSSA_F1CSTRBYPASS_MASK)
14082#define DTRC_FSUVSSA_F0SUVSSA_MASK (0xFFFFFFF0U)
14083#define DTRC_FSUVSSA_F0SUVSSA_SHIFT (4U)
14084#define DTRC_FSUVSSA_F0SUVSSA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSSA_F0SUVSSA_SHIFT)) & DTRC_FSUVSSA_F0SUVSSA_MASK)
14085#define DTRC_FSUVSSA_F1SUVSSA_MASK (0xFFFFFFF0U)
14086#define DTRC_FSUVSSA_F1SUVSSA_SHIFT (4U)
14087#define DTRC_FSUVSSA_F1SUVSSA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSSA_F1SUVSSA_SHIFT)) & DTRC_FSUVSSA_F1SUVSSA_MASK)
14088/*! @} */
14089
14090/* The count of DTRC_FSUVSSA */
14091#define DTRC_FSUVSSA_COUNT (2U)
14092
14093/*! @name FSUVSEA - Chroma data slave end address */
14094/*! @{ */
14095#define DTRC_FSUVSEA_F0CETRBYPASS_MASK (0x1U)
14096#define DTRC_FSUVSEA_F0CETRBYPASS_SHIFT (0U)
14097/*! F0CETRBYPASS - End Tile to Raster scan Bypass
14098 * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic.
14099 * 0b1..All ARADDR bypasses the tile-to-rasterscan logic.
14100 */
14101#define DTRC_FSUVSEA_F0CETRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSEA_F0CETRBYPASS_SHIFT)) & DTRC_FSUVSEA_F0CETRBYPASS_MASK)
14102#define DTRC_FSUVSEA_F1CETRBYPASS_MASK (0x1U)
14103#define DTRC_FSUVSEA_F1CETRBYPASS_SHIFT (0U)
14104/*! F1CETRBYPASS - End Tile to Raster scan Bypass
14105 * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic.
14106 * 0b1..All ARADDR bypasses the tile-to-rasterscan logic.
14107 */
14108#define DTRC_FSUVSEA_F1CETRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSEA_F1CETRBYPASS_SHIFT)) & DTRC_FSUVSEA_F1CETRBYPASS_MASK)
14109#define DTRC_FSUVSEA_F0SUVSEA_MASK (0xFFFFFFF0U)
14110#define DTRC_FSUVSEA_F0SUVSEA_SHIFT (4U)
14111#define DTRC_FSUVSEA_F0SUVSEA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSEA_F0SUVSEA_SHIFT)) & DTRC_FSUVSEA_F0SUVSEA_MASK)
14112#define DTRC_FSUVSEA_F1SUVSEA_MASK (0xFFFFFFF0U)
14113#define DTRC_FSUVSEA_F1SUVSEA_SHIFT (4U)
14114#define DTRC_FSUVSEA_F1SUVSEA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSEA_F1SUVSEA_SHIFT)) & DTRC_FSUVSEA_F1SUVSEA_MASK)
14115/*! @} */
14116
14117/* The count of DTRC_FSUVSEA */
14118#define DTRC_FSUVSEA_COUNT (2U)
14119
14120/*! @name FCROPORIG - Cropped picture origin */
14121/*! @{ */
14122#define DTRC_FCROPORIG_F0CROPORIGX_MASK (0x1FFFU)
14123#define DTRC_FCROPORIG_F0CROPORIGX_SHIFT (0U)
14124#define DTRC_FCROPORIG_F0CROPORIGX(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPORIG_F0CROPORIGX_SHIFT)) & DTRC_FCROPORIG_F0CROPORIGX_MASK)
14125#define DTRC_FCROPORIG_F1CROPORIGX_MASK (0x1FFFU)
14126#define DTRC_FCROPORIG_F1CROPORIGX_SHIFT (0U)
14127#define DTRC_FCROPORIG_F1CROPORIGX(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPORIG_F1CROPORIGX_SHIFT)) & DTRC_FCROPORIG_F1CROPORIGX_MASK)
14128#define DTRC_FCROPORIG_F0CROPORIGY_MASK (0x1FFF0000U)
14129#define DTRC_FCROPORIG_F0CROPORIGY_SHIFT (16U)
14130#define DTRC_FCROPORIG_F0CROPORIGY(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPORIG_F0CROPORIGY_SHIFT)) & DTRC_FCROPORIG_F0CROPORIGY_MASK)
14131#define DTRC_FCROPORIG_F1CROPORIGY_MASK (0x1FFF0000U)
14132#define DTRC_FCROPORIG_F1CROPORIGY_SHIFT (16U)
14133#define DTRC_FCROPORIG_F1CROPORIGY(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPORIG_F1CROPORIGY_SHIFT)) & DTRC_FCROPORIG_F1CROPORIGY_MASK)
14134/*! @} */
14135
14136/* The count of DTRC_FCROPORIG */
14137#define DTRC_FCROPORIG_COUNT (2U)
14138
14139/*! @name FCROPSIZE - Cropped picture size */
14140/*! @{ */
14141#define DTRC_FCROPSIZE_F0CROPWIDTH_MASK (0x1FFFU)
14142#define DTRC_FCROPSIZE_F0CROPWIDTH_SHIFT (0U)
14143#define DTRC_FCROPSIZE_F0CROPWIDTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPSIZE_F0CROPWIDTH_SHIFT)) & DTRC_FCROPSIZE_F0CROPWIDTH_MASK)
14144#define DTRC_FCROPSIZE_F1CROPWIDTH_MASK (0x1FFFU)
14145#define DTRC_FCROPSIZE_F1CROPWIDTH_SHIFT (0U)
14146#define DTRC_FCROPSIZE_F1CROPWIDTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPSIZE_F1CROPWIDTH_SHIFT)) & DTRC_FCROPSIZE_F1CROPWIDTH_MASK)
14147#define DTRC_FCROPSIZE_F0CROPHEIGHT_MASK (0x1FFF0000U)
14148#define DTRC_FCROPSIZE_F0CROPHEIGHT_SHIFT (16U)
14149#define DTRC_FCROPSIZE_F0CROPHEIGHT(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPSIZE_F0CROPHEIGHT_SHIFT)) & DTRC_FCROPSIZE_F0CROPHEIGHT_MASK)
14150#define DTRC_FCROPSIZE_F1CROPHEIGHT_MASK (0x1FFF0000U)
14151#define DTRC_FCROPSIZE_F1CROPHEIGHT_SHIFT (16U)
14152#define DTRC_FCROPSIZE_F1CROPHEIGHT(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPSIZE_F1CROPHEIGHT_SHIFT)) & DTRC_FCROPSIZE_F1CROPHEIGHT_MASK)
14153/*! @} */
14154
14155/* The count of DTRC_FCROPSIZE */
14156#define DTRC_FCROPSIZE_COUNT (2U)
14157
14158/*! @name FDCTL - Frame data control */
14159/*! @{ */
14160#define DTRC_FDCTL_F0FRAMECFG_MASK (0x1U)
14161#define DTRC_FDCTL_F0FRAMECFG_SHIFT (0U)
14162/*! F0FRAMECFG - Frame configuration ready
14163 * 0b0..Frame 0 configuration is not ready.
14164 * 0b1..Frame 0 configuration is ready and decompress can start for the frame. All other configuration, such as main8/main10 are updated before setting this bit to 1. If there is no G1/G2 video transaction, set this bit to 0.
14165 */
14166#define DTRC_FDCTL_F0FRAMECFG(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F0FRAMECFG_SHIFT)) & DTRC_FDCTL_F0FRAMECFG_MASK)
14167#define DTRC_FDCTL_F1FRAMECFG_MASK (0x1U)
14168#define DTRC_FDCTL_F1FRAMECFG_SHIFT (0U)
14169/*! F1FRAMECFG - Frame configuration ready
14170 * 0b0..Frame 0 configuration is not ready.
14171 * 0b1..Frame 0 configuration is ready and decompress can start for the frame. All other configuration, such as main8/main10 are updated before setting this bit to 1. If there is no G1/G2 video transaction, set this bit to 0.
14172 */
14173#define DTRC_FDCTL_F1FRAMECFG(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F1FRAMECFG_SHIFT)) & DTRC_FDCTL_F1FRAMECFG_MASK)
14174#define DTRC_FDCTL_F0PIXELBITDEPTH_MASK (0x2U)
14175#define DTRC_FDCTL_F0PIXELBITDEPTH_SHIFT (1U)
14176/*! F0PIXELBITDEPTH - Pixel bit depth
14177 * 0b0..10-bit pixel depth
14178 * 0b1..8-bit pixel depth
14179 */
14180#define DTRC_FDCTL_F0PIXELBITDEPTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F0PIXELBITDEPTH_SHIFT)) & DTRC_FDCTL_F0PIXELBITDEPTH_MASK)
14181#define DTRC_FDCTL_F1PIXELBITDEPTH_MASK (0x2U)
14182#define DTRC_FDCTL_F1PIXELBITDEPTH_SHIFT (1U)
14183/*! F1PIXELBITDEPTH - Pixel bit depth
14184 * 0b0..10-bit pixel depth
14185 * 0b1..8-bit pixel depth
14186 */
14187#define DTRC_FDCTL_F1PIXELBITDEPTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F1PIXELBITDEPTH_SHIFT)) & DTRC_FDCTL_F1PIXELBITDEPTH_MASK)
14188#define DTRC_FDCTL_F0DECOMPRESS_MASK (0x20000U)
14189#define DTRC_FDCTL_F0DECOMPRESS_SHIFT (17U)
14190/*! F0DECOMPRESS - Decompress bypass
14191 * 0b0..G2 reference frame is compressed.
14192 * 0b1..G2/G1 reference frame is not compressed.
14193 */
14194#define DTRC_FDCTL_F0DECOMPRESS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F0DECOMPRESS_SHIFT)) & DTRC_FDCTL_F0DECOMPRESS_MASK)
14195#define DTRC_FDCTL_F1DECOMPRESS_MASK (0x20000U)
14196#define DTRC_FDCTL_F1DECOMPRESS_SHIFT (17U)
14197/*! F1DECOMPRESS - Decompress bypass
14198 * 0b0..G2 reference frame is compressed.
14199 * 0b1..G2/G1 reference frame is not compressed.
14200 */
14201#define DTRC_FDCTL_F1DECOMPRESS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F1DECOMPRESS_SHIFT)) & DTRC_FDCTL_F1DECOMPRESS_MASK)
14202#define DTRC_FDCTL_F0CROPENABLE_MASK (0x40000U)
14203#define DTRC_FDCTL_F0CROPENABLE_SHIFT (18U)
14204#define DTRC_FDCTL_F0CROPENABLE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F0CROPENABLE_SHIFT)) & DTRC_FDCTL_F0CROPENABLE_MASK)
14205#define DTRC_FDCTL_F1CROPENABLE_MASK (0x40000U)
14206#define DTRC_FDCTL_F1CROPENABLE_SHIFT (18U)
14207#define DTRC_FDCTL_F1CROPENABLE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F1CROPENABLE_SHIFT)) & DTRC_FDCTL_F1CROPENABLE_MASK)
14208/*! @} */
14209
14210/* The count of DTRC_FDCTL */
14211#define DTRC_FDCTL_COUNT (2U)
14212
14213/*! @name DTRCINTEN - DTRC Interrupt enables */
14214/*! @{ */
14215#define DTRC_DTRCINTEN_FRAMEFETCHDONE_EN_MASK (0x1U)
14216#define DTRC_DTRCINTEN_FRAMEFETCHDONE_EN_SHIFT (0U)
14217/*! FRAMEFETCHDONE_EN - Frame fetch done interrupt enable
14218 * 0b0..Frame fetch done interrupt disabled.
14219 * 0b1..Frame fetch done interrupt enabled.
14220 */
14221#define DTRC_DTRCINTEN_FRAMEFETCHDONE_EN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCINTEN_FRAMEFETCHDONE_EN_SHIFT)) & DTRC_DTRCINTEN_FRAMEFETCHDONE_EN_MASK)
14222#define DTRC_DTRCINTEN_BUSERROR_EN_MASK (0x2U)
14223#define DTRC_DTRCINTEN_BUSERROR_EN_SHIFT (1U)
14224/*! BUSERROR_EN - Bus error interrupt enable
14225 * 0b0..Bus error interrupt disabled.
14226 * 0b1..Bus error interrupt enabled.
14227 */
14228#define DTRC_DTRCINTEN_BUSERROR_EN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCINTEN_BUSERROR_EN_SHIFT)) & DTRC_DTRCINTEN_BUSERROR_EN_MASK)
14229#define DTRC_DTRCINTEN_TIMEOUT_EN_MASK (0x4U)
14230#define DTRC_DTRCINTEN_TIMEOUT_EN_SHIFT (2U)
14231/*! TIMEOUT_EN - Time out enable
14232 * 0b0..Time out disabled.
14233 * 0b1..Time out enabled.
14234 */
14235#define DTRC_DTRCINTEN_TIMEOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCINTEN_TIMEOUT_EN_SHIFT)) & DTRC_DTRCINTEN_TIMEOUT_EN_MASK)
14236#define DTRC_DTRCINTEN_SLFRAMEFETCHDONE_EN_MASK (0x8U)
14237#define DTRC_DTRCINTEN_SLFRAMEFETCHDONE_EN_SHIFT (3U)
14238/*! SLFRAMEFETCHDONE_EN - Slave frame fetch done
14239 * 0b0..Slave frame fetch done disabled.
14240 * 0b1..Slave frame fetch done enabled.
14241 */
14242#define DTRC_DTRCINTEN_SLFRAMEFETCHDONE_EN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCINTEN_SLFRAMEFETCHDONE_EN_SHIFT)) & DTRC_DTRCINTEN_SLFRAMEFETCHDONE_EN_MASK)
14243#define DTRC_DTRCINTEN_HOTRESETFINISH_EN_MASK (0x10U)
14244#define DTRC_DTRCINTEN_HOTRESETFINISH_EN_SHIFT (4U)
14245/*! HOTRESETFINISH_EN - Hot reset finish
14246 * 0b0..Hot reset finish disabled.
14247 * 0b1..Hot reset finish enabled.
14248 */
14249#define DTRC_DTRCINTEN_HOTRESETFINISH_EN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCINTEN_HOTRESETFINISH_EN_SHIFT)) & DTRC_DTRCINTEN_HOTRESETFINISH_EN_MASK)
14250/*! @} */
14251
14252/*! @name FDINTR - DTRC Interrupt Requests */
14253/*! @{ */
14254#define DTRC_FDINTR_FRAMEFETCHDONE_MASK (0x1U)
14255#define DTRC_FDINTR_FRAMEFETCHDONE_SHIFT (0U)
14256#define DTRC_FDINTR_FRAMEFETCHDONE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDINTR_FRAMEFETCHDONE_SHIFT)) & DTRC_FDINTR_FRAMEFETCHDONE_MASK)
14257#define DTRC_FDINTR_BUSERROR_MASK (0x2U)
14258#define DTRC_FDINTR_BUSERROR_SHIFT (1U)
14259#define DTRC_FDINTR_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDINTR_BUSERROR_SHIFT)) & DTRC_FDINTR_BUSERROR_MASK)
14260#define DTRC_FDINTR_TIMEOUT_MASK (0x4U)
14261#define DTRC_FDINTR_TIMEOUT_SHIFT (2U)
14262#define DTRC_FDINTR_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDINTR_TIMEOUT_SHIFT)) & DTRC_FDINTR_TIMEOUT_MASK)
14263#define DTRC_FDINTR_SLFRAMEFETCHDONE_MASK (0x8U)
14264#define DTRC_FDINTR_SLFRAMEFETCHDONE_SHIFT (3U)
14265#define DTRC_FDINTR_SLFRAMEFETCHDONE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDINTR_SLFRAMEFETCHDONE_SHIFT)) & DTRC_FDINTR_SLFRAMEFETCHDONE_MASK)
14266#define DTRC_FDINTR_HOTRESETFINISH_MASK (0x10U)
14267#define DTRC_FDINTR_HOTRESETFINISH_SHIFT (4U)
14268#define DTRC_FDINTR_HOTRESETFINISH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDINTR_HOTRESETFINISH_SHIFT)) & DTRC_FDINTR_HOTRESETFINISH_MASK)
14269/*! @} */
14270
14271/*! @name DTCTRL - DTRC Control */
14272/*! @{ */
14273#define DTRC_DTCTRL_ARIDRCFG_MASK (0x3U)
14274#define DTRC_DTCTRL_ARIDRCFG_SHIFT (0U)
14275/*! ARIDRCFG - ARIDR configuration
14276 * 0b00..All ARID is de-tiled.
14277 * 0b01..ARID in ARIDR is de-tiled, and others are bypass. NOTE: ARID[0] specify decode luma or chroma, so 4 ARIDs in ARIDR should include both of ARID[0] ==1 and ARID[0] ==0.
14278 * 0b10..ARID in ARIDR is bypass_de-tile, and others are de-tiled.
14279 * 0b11..Same as 2'b01.
14280 */
14281#define DTRC_DTCTRL_ARIDRCFG(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_ARIDRCFG_SHIFT)) & DTRC_DTCTRL_ARIDRCFG_MASK)
14282#define DTRC_DTCTRL_HOTRESETTRIG_MASK (0x4U)
14283#define DTRC_DTCTRL_HOTRESETTRIG_SHIFT (2U)
14284#define DTRC_DTCTRL_HOTRESETTRIG(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_HOTRESETTRIG_SHIFT)) & DTRC_DTCTRL_HOTRESETTRIG_MASK)
14285#define DTRC_DTCTRL_G1G2DATA_MASK (0x8U)
14286#define DTRC_DTCTRL_G1G2DATA_SHIFT (3U)
14287/*! G1G2DATA - G2 or G1 source data
14288 * 0b0..The source data is G2 data.
14289 * 0b1..The source data is G1 tile data
14290 */
14291#define DTRC_DTCTRL_G1G2DATA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_G1G2DATA_SHIFT)) & DTRC_DTCTRL_G1G2DATA_MASK)
14292#define DTRC_DTCTRL_AXIMAXBURSTL_MASK (0xFF0U)
14293#define DTRC_DTCTRL_AXIMAXBURSTL_SHIFT (4U)
14294#define DTRC_DTCTRL_AXIMAXBURSTL(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_AXIMAXBURSTL_SHIFT)) & DTRC_DTCTRL_AXIMAXBURSTL_MASK)
14295#define DTRC_DTCTRL_BYTESWAP_SLRAST_MASK (0xF000U)
14296#define DTRC_DTCTRL_BYTESWAP_SLRAST_SHIFT (12U)
14297#define DTRC_DTCTRL_BYTESWAP_SLRAST(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_BYTESWAP_SLRAST_SHIFT)) & DTRC_DTCTRL_BYTESWAP_SLRAST_MASK)
14298#define DTRC_DTCTRL_BYTESWAP_MCOMPTILE_MASK (0xF0000U)
14299#define DTRC_DTCTRL_BYTESWAP_MCOMPTILE_SHIFT (16U)
14300#define DTRC_DTCTRL_BYTESWAP_MCOMPTILE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_BYTESWAP_MCOMPTILE_SHIFT)) & DTRC_DTCTRL_BYTESWAP_MCOMPTILE_MASK)
14301#define DTRC_DTCTRL_BYTESWAP_MTABLE_MASK (0xF00000U)
14302#define DTRC_DTCTRL_BYTESWAP_MTABLE_SHIFT (20U)
14303#define DTRC_DTCTRL_BYTESWAP_MTABLE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_BYTESWAP_MTABLE_SHIFT)) & DTRC_DTCTRL_BYTESWAP_MTABLE_MASK)
14304#define DTRC_DTCTRL_BYTESWAP_M_NONG1G2_MASK (0xF000000U)
14305#define DTRC_DTCTRL_BYTESWAP_M_NONG1G2_SHIFT (24U)
14306#define DTRC_DTCTRL_BYTESWAP_M_NONG1G2(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_BYTESWAP_M_NONG1G2_SHIFT)) & DTRC_DTCTRL_BYTESWAP_M_NONG1G2_MASK)
14307#define DTRC_DTCTRL_MERGEG1G2_ARIDEN_MASK (0x10000000U)
14308#define DTRC_DTCTRL_MERGEG1G2_ARIDEN_SHIFT (28U)
14309/*! MERGEG1G2_ARIDEN - Merge G2/G1 ARID enable
14310 * 0b0..G2/G1 transactions at AXI master interface use different id for table/chroma and data/luma according to DTID2DDR definition.
14311 * 0b1..All G2/G1 transactions at AXI master interface use the same id configured in DTID2DDR[15:8] Please note that DTID2DDR[15:8] and DTID2DDR[7:0] still need to be set the same way as when DTCTRL[28] is 0.
14312 */
14313#define DTRC_DTCTRL_MERGEG1G2_ARIDEN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_MERGEG1G2_ARIDEN_SHIFT)) & DTRC_DTCTRL_MERGEG1G2_ARIDEN_MASK)
14314#define DTRC_DTCTRL_RAST_ENDIAN_MASK (0x20000000U)
14315#define DTRC_DTCTRL_RAST_ENDIAN_SHIFT (29U)
14316/*! RAST_ENDIAN - Raster endian mode
14317 * 0b0..10-bit output format is little-endian. Byte swap setting of DTCTRL[15:12] is used.
14318 * 0b1..10-bit output format is big-endian. Byte swap setting of DTCTRL[15:12] is ignored.
14319 */
14320#define DTRC_DTCTRL_RAST_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_RAST_ENDIAN_SHIFT)) & DTRC_DTCTRL_RAST_ENDIAN_MASK)
14321#define DTRC_DTCTRL_ADDR_ARID_MASK (0x40000000U)
14322#define DTRC_DTCTRL_ADDR_ARID_SHIFT (30U)
14323/*! ADDR_ARID - ADDR_ARID
14324 * 0b0..By ARID (See bit[1:0] of this register).
14325 * 0b1..By ARADDR
14326 */
14327#define DTRC_DTCTRL_ADDR_ARID(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_ADDR_ARID_SHIFT)) & DTRC_DTCTRL_ADDR_ARID_MASK)
14328#define DTRC_DTCTRL_FRBUFF_PTR_MASK (0x80000000U)
14329#define DTRC_DTCTRL_FRBUFF_PTR_SHIFT (31U)
14330/*! FRBUFF_PTR - FRBUFF_PTR
14331 * 0b0..Configure frame 0 registers.
14332 * 0b1..Configure frame 1 registers.
14333 */
14334#define DTRC_DTCTRL_FRBUFF_PTR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_FRBUFF_PTR_SHIFT)) & DTRC_DTCTRL_FRBUFF_PTR_MASK)
14335/*! @} */
14336
14337/*! @name ARIDR - ARIDR */
14338/*! @{ */
14339#define DTRC_ARIDR_ARIDR_MASK (0xFFFFFFFFU)
14340#define DTRC_ARIDR_ARIDR_SHIFT (0U)
14341#define DTRC_ARIDR_ARIDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_ARIDR_ARIDR_SHIFT)) & DTRC_ARIDR_ARIDR_MASK)
14342/*! @} */
14343
14344/*! @name DTID2DDR - DTID2DDR */
14345/*! @{ */
14346#define DTRC_DTID2DDR_ARID_COMPR_MASK (0xFFU)
14347#define DTRC_DTID2DDR_ARID_COMPR_SHIFT (0U)
14348#define DTRC_DTID2DDR_ARID_COMPR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTID2DDR_ARID_COMPR_SHIFT)) & DTRC_DTID2DDR_ARID_COMPR_MASK)
14349#define DTRC_DTID2DDR_ARID_TABLE_MASK (0xFF00U)
14350#define DTRC_DTID2DDR_ARID_TABLE_SHIFT (8U)
14351#define DTRC_DTID2DDR_ARID_TABLE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTID2DDR_ARID_TABLE_SHIFT)) & DTRC_DTID2DDR_ARID_TABLE_MASK)
14352/*! @} */
14353
14354/*! @name DTRCCONFIG - DTRCCONFIG */
14355/*! @{ */
14356#define DTRC_DTRCCONFIG_G1G2_KEEPORDER_MASK (0x2U)
14357#define DTRC_DTRCCONFIG_G1G2_KEEPORDER_SHIFT (1U)
14358/*! G1G2_KEEPORDER - G1G2_KEEPORDER
14359 * 0b0..Not supported. DTRC sends out data transactions as soon as they are ready regardless of the address transactions order, The master connected to AXI slave interface must recognize the data transactions by the RID.
14360 * 0b1..Supported, DTRC ensure return read data from a sequence of read transactions in the same order in which it received the address.
14361 */
14362#define DTRC_DTRCCONFIG_G1G2_KEEPORDER(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCCONFIG_G1G2_KEEPORDER_SHIFT)) & DTRC_DTRCCONFIG_G1G2_KEEPORDER_MASK)
14363#define DTRC_DTRCCONFIG_AXI_MAXBURSTL_MASK (0x4U)
14364#define DTRC_DTRCCONFIG_AXI_MAXBURSTL_SHIFT (2U)
14365/*! AXI_MAXBURSTL - AXI_MAXBURSTL
14366 * 0b0..Not supported.
14367 * 0b1..Supported. DTRC sends the G1/G2 relating requests with ARLEN <= (the maximum burst length - 1). The maximum burst length is set by DTCTRL[16:8].
14368 */
14369#define DTRC_DTRCCONFIG_AXI_MAXBURSTL(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCCONFIG_AXI_MAXBURSTL_SHIFT)) & DTRC_DTRCCONFIG_AXI_MAXBURSTL_MASK)
14370#define DTRC_DTRCCONFIG_G1TILE_INPUT_MASK (0x8U)
14371#define DTRC_DTRCCONFIG_G1TILE_INPUT_SHIFT (3U)
14372/*! G1TILE_INPUT - G1TILE_INPUT
14373 * 0b0..Not supported.
14374 * 0b1..Supported.
14375 */
14376#define DTRC_DTRCCONFIG_G1TILE_INPUT(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCCONFIG_G1TILE_INPUT_SHIFT)) & DTRC_DTRCCONFIG_G1TILE_INPUT_MASK)
14377#define DTRC_DTRCCONFIG_MAX_PIC_WIDTH_MASK (0x30U)
14378#define DTRC_DTRCCONFIG_MAX_PIC_WIDTH_SHIFT (4U)
14379/*! MAX_PIC_WIDTH - MAX_PIC_WIDTH
14380 * 0b00..4096
14381 * 0b01..1920
14382 * 0b10..Reserved.
14383 * 0b11..Reserved.
14384 */
14385#define DTRC_DTRCCONFIG_MAX_PIC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCCONFIG_MAX_PIC_WIDTH_SHIFT)) & DTRC_DTRCCONFIG_MAX_PIC_WIDTH_MASK)
14386/*! @} */
14387
14388/*! @name DTRCVERSION - DTRC Version */
14389/*! @{ */
14390#define DTRC_DTRCVERSION_CUST_VERSION_MASK (0xFU)
14391#define DTRC_DTRCVERSION_CUST_VERSION_SHIFT (0U)
14392#define DTRC_DTRCVERSION_CUST_VERSION(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCVERSION_CUST_VERSION_SHIFT)) & DTRC_DTRCVERSION_CUST_VERSION_MASK)
14393#define DTRC_DTRCVERSION_MINOR_MASK (0x3F0U)
14394#define DTRC_DTRCVERSION_MINOR_SHIFT (4U)
14395#define DTRC_DTRCVERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCVERSION_MINOR_SHIFT)) & DTRC_DTRCVERSION_MINOR_MASK)
14396#define DTRC_DTRCVERSION_MAJOR_MASK (0xFC00U)
14397#define DTRC_DTRCVERSION_MAJOR_SHIFT (10U)
14398#define DTRC_DTRCVERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCVERSION_MAJOR_SHIFT)) & DTRC_DTRCVERSION_MAJOR_MASK)
14399/*! @} */
14400
14401/*! @name PFCTRL - Performance counter control */
14402/*! @{ */
14403#define DTRC_PFCTRL_PFC_EN_MASK (0x1U)
14404#define DTRC_PFCTRL_PFC_EN_SHIFT (0U)
14405/*! PFC_EN - PFC_EN
14406 * 0b0..Performance Counter disabled.
14407 * 0b1..Performance Counter enabled.
14408 */
14409#define DTRC_PFCTRL_PFC_EN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_PFCTRL_PFC_EN_SHIFT)) & DTRC_PFCTRL_PFC_EN_MASK)
14410/*! @} */
14411
14412/*! @name PFCR - Performance counter */
14413/*! @{ */
14414#define DTRC_PFCR_PFCR_MASK (0xFFFFFFFFU)
14415#define DTRC_PFCR_PFCR_SHIFT (0U)
14416#define DTRC_PFCR_PFCR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_PFCR_PFCR_SHIFT)) & DTRC_PFCR_PFCR_MASK)
14417/*! @} */
14418
14419/*! @name TOCR - Time Out Cycles */
14420/*! @{ */
14421#define DTRC_TOCR_TOCR_MASK (0xFFFFFFFFU)
14422#define DTRC_TOCR_TOCR_SHIFT (0U)
14423#define DTRC_TOCR_TOCR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_TOCR_TOCR_SHIFT)) & DTRC_TOCR_TOCR_MASK)
14424/*! @} */
14425
14426
14427/*!
14428 * @}
14429 */ /* end of group DTRC_Register_Masks */
14430
14431
14432/* DTRC - Peripheral instance base addresses */
14433/** Peripheral DCSS__DTRC1 base address */
14434#define DCSS__DTRC1_BASE (0x32E16000u)
14435/** Peripheral DCSS__DTRC1 base pointer */
14436#define DCSS__DTRC1 ((DTRC_Type *)DCSS__DTRC1_BASE)
14437/** Peripheral DCSS__DTRC2 base address */
14438#define DCSS__DTRC2_BASE (0x32E17000u)
14439/** Peripheral DCSS__DTRC2 base pointer */
14440#define DCSS__DTRC2 ((DTRC_Type *)DCSS__DTRC2_BASE)
14441/** Array initializer of DTRC peripheral base addresses */
14442#define DTRC_BASE_ADDRS { 0u, DCSS__DTRC1_BASE, DCSS__DTRC2_BASE }
14443/** Array initializer of DTRC peripheral base pointers */
14444#define DTRC_BASE_PTRS { (DTRC_Type *)0u, DCSS__DTRC1, DCSS__DTRC2 }
14445
14446/*!
14447 * @}
14448 */ /* end of group DTRC_Peripheral_Access_Layer */
14449
14450
14451/* ----------------------------------------------------------------------------
14452 -- ECSPI Peripheral Access Layer
14453 ---------------------------------------------------------------------------- */
14454
14455/*!
14456 * @addtogroup ECSPI_Peripheral_Access_Layer ECSPI Peripheral Access Layer
14457 * @{
14458 */
14459
14460/** ECSPI - Register Layout Typedef */
14461typedef struct {
14462 __I uint32_t RXDATA; /**< Receive Data Register, offset: 0x0 */
14463 __O uint32_t TXDATA; /**< Transmit Data Register, offset: 0x4 */
14464 __IO uint32_t CONREG; /**< Control Register, offset: 0x8 */
14465 __IO uint32_t CONFIGREG; /**< Config Register, offset: 0xC */
14466 __IO uint32_t INTREG; /**< Interrupt Control Register, offset: 0x10 */
14467 __IO uint32_t DMAREG; /**< DMA Control Register, offset: 0x14 */
14468 __IO uint32_t STATREG; /**< Status Register, offset: 0x18 */
14469 __IO uint32_t PERIODREG; /**< Sample Period Control Register, offset: 0x1C */
14470 __IO uint32_t TESTREG; /**< Test Control Register, offset: 0x20 */
14471 uint8_t RESERVED_0[28];
14472 __O uint32_t MSGDATA; /**< Message Data Register, offset: 0x40 */
14473} ECSPI_Type;
14474
14475/* ----------------------------------------------------------------------------
14476 -- ECSPI Register Masks
14477 ---------------------------------------------------------------------------- */
14478
14479/*!
14480 * @addtogroup ECSPI_Register_Masks ECSPI Register Masks
14481 * @{
14482 */
14483
14484/*! @name RXDATA - Receive Data Register */
14485/*! @{ */
14486#define ECSPI_RXDATA_ECSPI_RXDATA_MASK (0xFFFFFFFFU)
14487#define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT (0U)
14488#define ECSPI_RXDATA_ECSPI_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_RXDATA_ECSPI_RXDATA_SHIFT)) & ECSPI_RXDATA_ECSPI_RXDATA_MASK)
14489/*! @} */
14490
14491/*! @name TXDATA - Transmit Data Register */
14492/*! @{ */
14493#define ECSPI_TXDATA_ECSPI_TXDATA_MASK (0xFFFFFFFFU)
14494#define ECSPI_TXDATA_ECSPI_TXDATA_SHIFT (0U)
14495#define ECSPI_TXDATA_ECSPI_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TXDATA_ECSPI_TXDATA_SHIFT)) & ECSPI_TXDATA_ECSPI_TXDATA_MASK)
14496/*! @} */
14497
14498/*! @name CONREG - Control Register */
14499/*! @{ */
14500#define ECSPI_CONREG_EN_MASK (0x1U)
14501#define ECSPI_CONREG_EN_SHIFT (0U)
14502/*! EN
14503 * 0b0..Disable the block.
14504 * 0b1..Enable the block.
14505 */
14506#define ECSPI_CONREG_EN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_EN_SHIFT)) & ECSPI_CONREG_EN_MASK)
14507#define ECSPI_CONREG_HT_MASK (0x2U)
14508#define ECSPI_CONREG_HT_SHIFT (1U)
14509/*! HT
14510 * 0b0..Disable HT mode.
14511 * 0b1..Enable HT mode.
14512 */
14513#define ECSPI_CONREG_HT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_HT_SHIFT)) & ECSPI_CONREG_HT_MASK)
14514#define ECSPI_CONREG_XCH_MASK (0x4U)
14515#define ECSPI_CONREG_XCH_SHIFT (2U)
14516/*! XCH
14517 * 0b0..Idle.
14518 * 0b1..Initiates exchange (write) or busy (read).
14519 */
14520#define ECSPI_CONREG_XCH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_XCH_SHIFT)) & ECSPI_CONREG_XCH_MASK)
14521#define ECSPI_CONREG_SMC_MASK (0x8U)
14522#define ECSPI_CONREG_SMC_SHIFT (3U)
14523/*! SMC
14524 * 0b0..SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst or multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer to XCH and SS_CTL descriptions.
14525 * 0b1..Immediately starts a SPI burst when data is written in TXFIFO.
14526 */
14527#define ECSPI_CONREG_SMC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_SMC_SHIFT)) & ECSPI_CONREG_SMC_MASK)
14528#define ECSPI_CONREG_CHANNEL_MODE_MASK (0xF0U)
14529#define ECSPI_CONREG_CHANNEL_MODE_SHIFT (4U)
14530/*! CHANNEL_MODE
14531 * 0b0000..Slave mode.
14532 * 0b0001..Master mode.
14533 */
14534#define ECSPI_CONREG_CHANNEL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_MODE_SHIFT)) & ECSPI_CONREG_CHANNEL_MODE_MASK)
14535#define ECSPI_CONREG_POST_DIVIDER_MASK (0xF00U)
14536#define ECSPI_CONREG_POST_DIVIDER_SHIFT (8U)
14537/*! POST_DIVIDER
14538 * 0b0000..Divide by 1.
14539 * 0b0001..Divide by 2.
14540 * 0b0010..Divide by 4.
14541 * 0b1110..Divide by 2 14 .
14542 * 0b1111..Divide by 2 15 .
14543 */
14544#define ECSPI_CONREG_POST_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_POST_DIVIDER_SHIFT)) & ECSPI_CONREG_POST_DIVIDER_MASK)
14545#define ECSPI_CONREG_PRE_DIVIDER_MASK (0xF000U)
14546#define ECSPI_CONREG_PRE_DIVIDER_SHIFT (12U)
14547/*! PRE_DIVIDER
14548 * 0b0000..Divide by 1.
14549 * 0b0001..Divide by 2.
14550 * 0b0010..Divide by 3.
14551 * 0b1101..Divide by 14.
14552 * 0b1110..Divide by 15.
14553 * 0b1111..Divide by 16.
14554 */
14555#define ECSPI_CONREG_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_PRE_DIVIDER_SHIFT)) & ECSPI_CONREG_PRE_DIVIDER_MASK)
14556#define ECSPI_CONREG_DRCTL_MASK (0x30000U)
14557#define ECSPI_CONREG_DRCTL_SHIFT (16U)
14558/*! DRCTL
14559 * 0b00..The SPI_RDY signal is a don't care.
14560 * 0b01..Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered).
14561 * 0b10..Burst will be triggered by a low level of the SPI_RDY signal (level-triggered).
14562 * 0b11..Reserved.
14563 */
14564#define ECSPI_CONREG_DRCTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_DRCTL_SHIFT)) & ECSPI_CONREG_DRCTL_MASK)
14565#define ECSPI_CONREG_CHANNEL_SELECT_MASK (0xC0000U)
14566#define ECSPI_CONREG_CHANNEL_SELECT_SHIFT (18U)
14567/*! CHANNEL_SELECT
14568 * 0b00..Channel 0 is selected. Chip Select 0 (SS0) will be asserted.
14569 * 0b01..Channel 1 is selected. Chip Select 1 (SS1) will be asserted.
14570 * 0b10..Channel 2 is selected. Chip Select 2 (SS2) will be asserted.
14571 * 0b11..Channel 3 is selected. Chip Select 3 (SS3) will be asserted.
14572 */
14573#define ECSPI_CONREG_CHANNEL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_SELECT_SHIFT)) & ECSPI_CONREG_CHANNEL_SELECT_MASK)
14574#define ECSPI_CONREG_BURST_LENGTH_MASK (0xFFF00000U)
14575#define ECSPI_CONREG_BURST_LENGTH_SHIFT (20U)
14576/*! BURST_LENGTH
14577 * 0b000000000000..A SPI burst contains the 1 LSB in a word.
14578 * 0b000000000001..A SPI burst contains the 2 LSB in a word.
14579 * 0b000000000010..A SPI burst contains the 3 LSB in a word.
14580 * 0b000000011111..A SPI burst contains all 32 bits in a word.
14581 * 0b000000100000..A SPI burst contains the 1 LSB in first word and all 32 bits in second word.
14582 * 0b000000100001..A SPI burst contains the 2 LSB in first word and all 32 bits in second word.
14583 * 0b111111111110..A SPI burst contains the 31 LSB in first word and 2^7 -1 words.
14584 * 0b111111111111..A SPI burst contains 2^7 words.
14585 */
14586#define ECSPI_CONREG_BURST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_BURST_LENGTH_SHIFT)) & ECSPI_CONREG_BURST_LENGTH_MASK)
14587/*! @} */
14588
14589/*! @name CONFIGREG - Config Register */
14590/*! @{ */
14591#define ECSPI_CONFIGREG_SCLK_PHA_MASK (0xFU)
14592#define ECSPI_CONFIGREG_SCLK_PHA_SHIFT (0U)
14593/*! SCLK_PHA
14594 * 0b0000..Phase 0 operation.
14595 * 0b0001..Phase 1 operation.
14596 */
14597#define ECSPI_CONFIGREG_SCLK_PHA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_PHA_SHIFT)) & ECSPI_CONFIGREG_SCLK_PHA_MASK)
14598#define ECSPI_CONFIGREG_SCLK_POL_MASK (0xF0U)
14599#define ECSPI_CONFIGREG_SCLK_POL_SHIFT (4U)
14600/*! SCLK_POL
14601 * 0b0000..Active high polarity (0 = Idle).
14602 * 0b0001..Active low polarity (1 = Idle).
14603 */
14604#define ECSPI_CONFIGREG_SCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_POL_SHIFT)) & ECSPI_CONFIGREG_SCLK_POL_MASK)
14605#define ECSPI_CONFIGREG_SS_CTL_MASK (0xF00U)
14606#define ECSPI_CONFIGREG_SS_CTL_SHIFT (8U)
14607/*! SS_CTL
14608 * 0b0000..In master mode - only one SPI burst will be transmitted.
14609 * 0b0001..In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be transmitted. The SPI transfer will automatically stop when the TXFIFO is empty.
14610 * 0b0000..In slave mode - an SPI burst is completed when the number of bits received in the shift register is equal to (BURST LENGTH + 1). Only the n least-significant bits (n = BURST LENGTH[4:0] + 1) of the first received word are valid. All bits subsequent to the first received word in RXFIFO are valid.
14611 * 0b0001..Reserved
14612 */
14613#define ECSPI_CONFIGREG_SS_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_CTL_SHIFT)) & ECSPI_CONFIGREG_SS_CTL_MASK)
14614#define ECSPI_CONFIGREG_SS_POL_MASK (0xF000U)
14615#define ECSPI_CONFIGREG_SS_POL_SHIFT (12U)
14616/*! SS_POL
14617 * 0b0000..Active low.
14618 * 0b0001..Active high.
14619 */
14620#define ECSPI_CONFIGREG_SS_POL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_POL_SHIFT)) & ECSPI_CONFIGREG_SS_POL_MASK)
14621#define ECSPI_CONFIGREG_DATA_CTL_MASK (0xF0000U)
14622#define ECSPI_CONFIGREG_DATA_CTL_SHIFT (16U)
14623/*! DATA_CTL
14624 * 0b0000..Stay high.
14625 * 0b0001..Stay low.
14626 */
14627#define ECSPI_CONFIGREG_DATA_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_DATA_CTL_SHIFT)) & ECSPI_CONFIGREG_DATA_CTL_MASK)
14628#define ECSPI_CONFIGREG_SCLK_CTL_MASK (0xF00000U)
14629#define ECSPI_CONFIGREG_SCLK_CTL_SHIFT (20U)
14630/*! SCLK_CTL
14631 * 0b0000..Stay low.
14632 * 0b0001..Stay high.
14633 */
14634#define ECSPI_CONFIGREG_SCLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_CTL_SHIFT)) & ECSPI_CONFIGREG_SCLK_CTL_MASK)
14635#define ECSPI_CONFIGREG_HT_LENGTH_MASK (0x1F000000U)
14636#define ECSPI_CONFIGREG_HT_LENGTH_SHIFT (24U)
14637#define ECSPI_CONFIGREG_HT_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_HT_LENGTH_SHIFT)) & ECSPI_CONFIGREG_HT_LENGTH_MASK)
14638/*! @} */
14639
14640/*! @name INTREG - Interrupt Control Register */
14641/*! @{ */
14642#define ECSPI_INTREG_TEEN_MASK (0x1U)
14643#define ECSPI_INTREG_TEEN_SHIFT (0U)
14644/*! TEEN
14645 * 0b0..Disable
14646 * 0b1..Enable
14647 */
14648#define ECSPI_INTREG_TEEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TEEN_SHIFT)) & ECSPI_INTREG_TEEN_MASK)
14649#define ECSPI_INTREG_TDREN_MASK (0x2U)
14650#define ECSPI_INTREG_TDREN_SHIFT (1U)
14651/*! TDREN
14652 * 0b0..Disable
14653 * 0b1..Enable
14654 */
14655#define ECSPI_INTREG_TDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TDREN_SHIFT)) & ECSPI_INTREG_TDREN_MASK)
14656#define ECSPI_INTREG_TFEN_MASK (0x4U)
14657#define ECSPI_INTREG_TFEN_SHIFT (2U)
14658/*! TFEN
14659 * 0b0..Disable
14660 * 0b1..Enable
14661 */
14662#define ECSPI_INTREG_TFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TFEN_SHIFT)) & ECSPI_INTREG_TFEN_MASK)
14663#define ECSPI_INTREG_RREN_MASK (0x8U)
14664#define ECSPI_INTREG_RREN_SHIFT (3U)
14665/*! RREN
14666 * 0b0..Disable
14667 * 0b1..Enable
14668 */
14669#define ECSPI_INTREG_RREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RREN_SHIFT)) & ECSPI_INTREG_RREN_MASK)
14670#define ECSPI_INTREG_RDREN_MASK (0x10U)
14671#define ECSPI_INTREG_RDREN_SHIFT (4U)
14672/*! RDREN
14673 * 0b0..Disable
14674 * 0b1..Enable
14675 */
14676#define ECSPI_INTREG_RDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RDREN_SHIFT)) & ECSPI_INTREG_RDREN_MASK)
14677#define ECSPI_INTREG_RFEN_MASK (0x20U)
14678#define ECSPI_INTREG_RFEN_SHIFT (5U)
14679/*! RFEN
14680 * 0b0..Disable
14681 * 0b1..Enable
14682 */
14683#define ECSPI_INTREG_RFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RFEN_SHIFT)) & ECSPI_INTREG_RFEN_MASK)
14684#define ECSPI_INTREG_ROEN_MASK (0x40U)
14685#define ECSPI_INTREG_ROEN_SHIFT (6U)
14686/*! ROEN
14687 * 0b0..Disable
14688 * 0b1..Enable
14689 */
14690#define ECSPI_INTREG_ROEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_ROEN_SHIFT)) & ECSPI_INTREG_ROEN_MASK)
14691#define ECSPI_INTREG_TCEN_MASK (0x80U)
14692#define ECSPI_INTREG_TCEN_SHIFT (7U)
14693/*! TCEN
14694 * 0b0..Disable
14695 * 0b1..Enable
14696 */
14697#define ECSPI_INTREG_TCEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TCEN_SHIFT)) & ECSPI_INTREG_TCEN_MASK)
14698/*! @} */
14699
14700/*! @name DMAREG - DMA Control Register */
14701/*! @{ */
14702#define ECSPI_DMAREG_TX_THRESHOLD_MASK (0x3FU)
14703#define ECSPI_DMAREG_TX_THRESHOLD_SHIFT (0U)
14704#define ECSPI_DMAREG_TX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_TX_THRESHOLD_MASK)
14705#define ECSPI_DMAREG_TEDEN_MASK (0x80U)
14706#define ECSPI_DMAREG_TEDEN_SHIFT (7U)
14707/*! TEDEN
14708 * 0b0..Disable
14709 * 0b1..Enable
14710 */
14711#define ECSPI_DMAREG_TEDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TEDEN_SHIFT)) & ECSPI_DMAREG_TEDEN_MASK)
14712#define ECSPI_DMAREG_RX_THRESHOLD_MASK (0x3F0000U)
14713#define ECSPI_DMAREG_RX_THRESHOLD_SHIFT (16U)
14714#define ECSPI_DMAREG_RX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_RX_THRESHOLD_MASK)
14715#define ECSPI_DMAREG_RXDEN_MASK (0x800000U)
14716#define ECSPI_DMAREG_RXDEN_SHIFT (23U)
14717/*! RXDEN
14718 * 0b0..Disable
14719 * 0b1..Enable
14720 */
14721#define ECSPI_DMAREG_RXDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXDEN_SHIFT)) & ECSPI_DMAREG_RXDEN_MASK)
14722#define ECSPI_DMAREG_RX_DMA_LENGTH_MASK (0x3F000000U)
14723#define ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT (24U)
14724#define ECSPI_DMAREG_RX_DMA_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT)) & ECSPI_DMAREG_RX_DMA_LENGTH_MASK)
14725#define ECSPI_DMAREG_RXTDEN_MASK (0x80000000U)
14726#define ECSPI_DMAREG_RXTDEN_SHIFT (31U)
14727/*! RXTDEN
14728 * 0b0..Disable
14729 * 0b1..Enable
14730 */
14731#define ECSPI_DMAREG_RXTDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXTDEN_SHIFT)) & ECSPI_DMAREG_RXTDEN_MASK)
14732/*! @} */
14733
14734/*! @name STATREG - Status Register */
14735/*! @{ */
14736#define ECSPI_STATREG_TE_MASK (0x1U)
14737#define ECSPI_STATREG_TE_SHIFT (0U)
14738/*! TE
14739 * 0b0..TXFIFO contains one or more words.
14740 * 0b1..TXFIFO is empty.
14741 */
14742#define ECSPI_STATREG_TE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TE_SHIFT)) & ECSPI_STATREG_TE_MASK)
14743#define ECSPI_STATREG_TDR_MASK (0x2U)
14744#define ECSPI_STATREG_TDR_SHIFT (1U)
14745/*! TDR
14746 * 0b0..Number of valid data slots in TXFIFO is greater than TX_THRESHOLD.
14747 * 0b1..Number of valid data slots in TXFIFO is not greater than TX_THRESHOLD.
14748 */
14749#define ECSPI_STATREG_TDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TDR_SHIFT)) & ECSPI_STATREG_TDR_MASK)
14750#define ECSPI_STATREG_TF_MASK (0x4U)
14751#define ECSPI_STATREG_TF_SHIFT (2U)
14752/*! TF
14753 * 0b0..TXFIFO is not Full.
14754 * 0b1..TXFIFO is Full.
14755 */
14756#define ECSPI_STATREG_TF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TF_SHIFT)) & ECSPI_STATREG_TF_MASK)
14757#define ECSPI_STATREG_RR_MASK (0x8U)
14758#define ECSPI_STATREG_RR_SHIFT (3U)
14759/*! RR
14760 * 0b0..No valid data in RXFIFO.
14761 * 0b1..More than 1 word in RXFIFO.
14762 */
14763#define ECSPI_STATREG_RR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RR_SHIFT)) & ECSPI_STATREG_RR_MASK)
14764#define ECSPI_STATREG_RDR_MASK (0x10U)
14765#define ECSPI_STATREG_RDR_SHIFT (4U)
14766/*! RDR
14767 * 0b0..When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD.
14768 * 0b1..When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a DMA TAIL DMA condition exists.
14769 * 0b0..When RXTDE is clear - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD.
14770 * 0b1..When RXTDE is clear - Number of data entries in the RXFIFO is greater than RX_THRESHOLD.
14771 */
14772#define ECSPI_STATREG_RDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RDR_SHIFT)) & ECSPI_STATREG_RDR_MASK)
14773#define ECSPI_STATREG_RF_MASK (0x20U)
14774#define ECSPI_STATREG_RF_SHIFT (5U)
14775/*! RF
14776 * 0b0..Not Full.
14777 * 0b1..Full.
14778 */
14779#define ECSPI_STATREG_RF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RF_SHIFT)) & ECSPI_STATREG_RF_MASK)
14780#define ECSPI_STATREG_RO_MASK (0x40U)
14781#define ECSPI_STATREG_RO_SHIFT (6U)
14782/*! RO
14783 * 0b0..RXFIFO has no overflow.
14784 * 0b1..RXFIFO has overflowed.
14785 */
14786#define ECSPI_STATREG_RO(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RO_SHIFT)) & ECSPI_STATREG_RO_MASK)
14787#define ECSPI_STATREG_TC_MASK (0x80U)
14788#define ECSPI_STATREG_TC_SHIFT (7U)
14789/*! TC
14790 * 0b0..Transfer in progress.
14791 * 0b1..Transfer completed.
14792 */
14793#define ECSPI_STATREG_TC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TC_SHIFT)) & ECSPI_STATREG_TC_MASK)
14794/*! @} */
14795
14796/*! @name PERIODREG - Sample Period Control Register */
14797/*! @{ */
14798#define ECSPI_PERIODREG_SAMPLE_PERIOD_MASK (0x7FFFU)
14799#define ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT (0U)
14800/*! SAMPLE_PERIOD
14801 * 0b000000000000000..0 wait states inserted
14802 * 0b000000000000001..1 wait state inserted
14803 * 0b111111111111110..32766 wait states inserted
14804 * 0b111111111111111..32767 wait states inserted
14805 */
14806#define ECSPI_PERIODREG_SAMPLE_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT)) & ECSPI_PERIODREG_SAMPLE_PERIOD_MASK)
14807#define ECSPI_PERIODREG_CSRC_MASK (0x8000U)
14808#define ECSPI_PERIODREG_CSRC_SHIFT (15U)
14809/*! CSRC
14810 * 0b0..SPI Clock (SCLK)
14811 * 0b1..Low-Frequency Reference Clock (32.768 KHz)
14812 */
14813#define ECSPI_PERIODREG_CSRC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSRC_SHIFT)) & ECSPI_PERIODREG_CSRC_MASK)
14814#define ECSPI_PERIODREG_CSD_CTL_MASK (0x3F0000U)
14815#define ECSPI_PERIODREG_CSD_CTL_SHIFT (16U)
14816#define ECSPI_PERIODREG_CSD_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSD_CTL_SHIFT)) & ECSPI_PERIODREG_CSD_CTL_MASK)
14817/*! @} */
14818
14819/*! @name TESTREG - Test Control Register */
14820/*! @{ */
14821#define ECSPI_TESTREG_TXCNT_MASK (0x7FU)
14822#define ECSPI_TESTREG_TXCNT_SHIFT (0U)
14823#define ECSPI_TESTREG_TXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_TXCNT_SHIFT)) & ECSPI_TESTREG_TXCNT_MASK)
14824#define ECSPI_TESTREG_RXCNT_MASK (0x7F00U)
14825#define ECSPI_TESTREG_RXCNT_SHIFT (8U)
14826#define ECSPI_TESTREG_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_RXCNT_SHIFT)) & ECSPI_TESTREG_RXCNT_MASK)
14827#define ECSPI_TESTREG_LBC_MASK (0x80000000U)
14828#define ECSPI_TESTREG_LBC_SHIFT (31U)
14829/*! LBC
14830 * 0b0..Not connected.
14831 * 0b1..Transmitter and receiver sections internally connected for Loopback.
14832 */
14833#define ECSPI_TESTREG_LBC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_LBC_SHIFT)) & ECSPI_TESTREG_LBC_MASK)
14834/*! @} */
14835
14836/*! @name MSGDATA - Message Data Register */
14837/*! @{ */
14838#define ECSPI_MSGDATA_ECSPI_MSGDATA_MASK (0xFFFFFFFFU)
14839#define ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT (0U)
14840#define ECSPI_MSGDATA_ECSPI_MSGDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT)) & ECSPI_MSGDATA_ECSPI_MSGDATA_MASK)
14841/*! @} */
14842
14843
14844/*!
14845 * @}
14846 */ /* end of group ECSPI_Register_Masks */
14847
14848
14849/* ECSPI - Peripheral instance base addresses */
14850/** Peripheral ECSPI1 base address */
14851#define ECSPI1_BASE (0x30820000u)
14852/** Peripheral ECSPI1 base pointer */
14853#define ECSPI1 ((ECSPI_Type *)ECSPI1_BASE)
14854/** Peripheral ECSPI2 base address */
14855#define ECSPI2_BASE (0x30830000u)
14856/** Peripheral ECSPI2 base pointer */
14857#define ECSPI2 ((ECSPI_Type *)ECSPI2_BASE)
14858/** Peripheral ECSPI3 base address */
14859#define ECSPI3_BASE (0x30840000u)
14860/** Peripheral ECSPI3 base pointer */
14861#define ECSPI3 ((ECSPI_Type *)ECSPI3_BASE)
14862/** Array initializer of ECSPI peripheral base addresses */
14863#define ECSPI_BASE_ADDRS { 0u, ECSPI1_BASE, ECSPI2_BASE, ECSPI3_BASE }
14864/** Array initializer of ECSPI peripheral base pointers */
14865#define ECSPI_BASE_PTRS { (ECSPI_Type *)0u, ECSPI1, ECSPI2, ECSPI3 }
14866/** Interrupt vectors for the ECSPI peripheral type */
14867#define ECSPI_IRQS { NotAvail_IRQn, ECSPI1_IRQn, ECSPI2_IRQn, ECSPI3_IRQn }
14868
14869/*!
14870 * @}
14871 */ /* end of group ECSPI_Peripheral_Access_Layer */
14872
14873
14874/* ----------------------------------------------------------------------------
14875 -- ENET Peripheral Access Layer
14876 ---------------------------------------------------------------------------- */
14877
14878/*!
14879 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
14880 * @{
14881 */
14882
14883/** ENET - Register Layout Typedef */
14884typedef struct {
14885 uint8_t RESERVED_0[4];
14886 __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
14887 __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
14888 uint8_t RESERVED_1[4];
14889 __IO uint32_t RDAR; /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */
14890 __IO uint32_t TDAR; /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */
14891 uint8_t RESERVED_2[12];
14892 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
14893 uint8_t RESERVED_3[24];
14894 __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
14895 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
14896 uint8_t RESERVED_4[28];
14897 __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
14898 uint8_t RESERVED_5[28];
14899 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
14900 uint8_t RESERVED_6[60];
14901 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
14902 uint8_t RESERVED_7[28];
14903 __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
14904 __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
14905 __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
14906 __IO uint32_t TXIC[3]; /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */
14907 uint8_t RESERVED_8[4];
14908 __IO uint32_t RXIC[3]; /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */
14909 uint8_t RESERVED_9[12];
14910 __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
14911 __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
14912 __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
14913 __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
14914 uint8_t RESERVED_10[28];
14915 __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
14916 uint8_t RESERVED_11[24];
14917 __IO uint32_t RDSR1; /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */
14918 __IO uint32_t TDSR1; /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */
14919 __IO uint32_t MRBR1; /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */
14920 __IO uint32_t RDSR2; /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */
14921 __IO uint32_t TDSR2; /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */
14922 __IO uint32_t MRBR2; /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */
14923 uint8_t RESERVED_12[8];
14924 __IO uint32_t RDSR; /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */
14925 __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */
14926 __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */
14927 uint8_t RESERVED_13[4];
14928 __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
14929 __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
14930 __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
14931 __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
14932 __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
14933 __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
14934 __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
14935 __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
14936 __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
14937 uint8_t RESERVED_14[12];
14938 __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
14939 __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
14940 __IO uint32_t RCMR[2]; /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */
14941 uint8_t RESERVED_15[8];
14942 __IO uint32_t DMACFG[2]; /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */
14943 __IO uint32_t RDAR1; /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */
14944 __IO uint32_t TDAR1; /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */
14945 __IO uint32_t RDAR2; /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */
14946 __IO uint32_t TDAR2; /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */
14947 __IO uint32_t QOS; /**< QOS Scheme, offset: 0x1F0 */
14948 uint8_t RESERVED_16[12];
14949 uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */
14950 __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
14951 __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
14952 __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
14953 __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
14954 __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
14955 __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
14956 __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
14957 __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
14958 __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
14959 __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
14960 __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
14961 __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
14962 __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
14963 __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
14964 __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
14965 __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
14966 __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
14967 uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */
14968 __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
14969 __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
14970 __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
14971 __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
14972 __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
14973 __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
14974 __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
14975 __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
14976 __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */
14977 __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
14978 __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
14979 uint8_t RESERVED_17[12];
14980 __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
14981 __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
14982 __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
14983 __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
14984 __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
14985 __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
14986 __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
14987 __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
14988 uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */
14989 __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
14990 __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
14991 __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
14992 __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
14993 __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
14994 __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
14995 __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
14996 __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
14997 __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
14998 __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
14999 __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
15000 __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
15001 __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
15002 __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
15003 __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
15004 uint8_t RESERVED_18[284];
15005 __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
15006 __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
15007 __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
15008 __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
15009 __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
15010 __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
15011 __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
15012 uint8_t RESERVED_19[488];
15013 __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
15014 struct { /* offset: 0x608, array step: 0x8 */
15015 __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
15016 __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
15017 } CHANNEL[4];
15018} ENET_Type;
15019
15020/* ----------------------------------------------------------------------------
15021 -- ENET Register Masks
15022 ---------------------------------------------------------------------------- */
15023
15024/*!
15025 * @addtogroup ENET_Register_Masks ENET Register Masks
15026 * @{
15027 */
15028
15029/*! @name EIR - Interrupt Event Register */
15030/*! @{ */
15031#define ENET_EIR_RXB1_MASK (0x1U)
15032#define ENET_EIR_RXB1_SHIFT (0U)
15033#define ENET_EIR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK)
15034#define ENET_EIR_RXF1_MASK (0x2U)
15035#define ENET_EIR_RXF1_SHIFT (1U)
15036#define ENET_EIR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK)
15037#define ENET_EIR_TXB1_MASK (0x4U)
15038#define ENET_EIR_TXB1_SHIFT (2U)
15039#define ENET_EIR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK)
15040#define ENET_EIR_TXF1_MASK (0x8U)
15041#define ENET_EIR_TXF1_SHIFT (3U)
15042#define ENET_EIR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK)
15043#define ENET_EIR_RXB2_MASK (0x10U)
15044#define ENET_EIR_RXB2_SHIFT (4U)
15045#define ENET_EIR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK)
15046#define ENET_EIR_RXF2_MASK (0x20U)
15047#define ENET_EIR_RXF2_SHIFT (5U)
15048#define ENET_EIR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK)
15049#define ENET_EIR_TXB2_MASK (0x40U)
15050#define ENET_EIR_TXB2_SHIFT (6U)
15051#define ENET_EIR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK)
15052#define ENET_EIR_TXF2_MASK (0x80U)
15053#define ENET_EIR_TXF2_SHIFT (7U)
15054#define ENET_EIR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK)
15055#define ENET_EIR_RXFLUSH_0_MASK (0x1000U)
15056#define ENET_EIR_RXFLUSH_0_SHIFT (12U)
15057#define ENET_EIR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK)
15058#define ENET_EIR_RXFLUSH_1_MASK (0x2000U)
15059#define ENET_EIR_RXFLUSH_1_SHIFT (13U)
15060#define ENET_EIR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK)
15061#define ENET_EIR_RXFLUSH_2_MASK (0x4000U)
15062#define ENET_EIR_RXFLUSH_2_SHIFT (14U)
15063#define ENET_EIR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK)
15064#define ENET_EIR_TS_TIMER_MASK (0x8000U)
15065#define ENET_EIR_TS_TIMER_SHIFT (15U)
15066#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
15067#define ENET_EIR_TS_AVAIL_MASK (0x10000U)
15068#define ENET_EIR_TS_AVAIL_SHIFT (16U)
15069#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
15070#define ENET_EIR_WAKEUP_MASK (0x20000U)
15071#define ENET_EIR_WAKEUP_SHIFT (17U)
15072#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
15073#define ENET_EIR_PLR_MASK (0x40000U)
15074#define ENET_EIR_PLR_SHIFT (18U)
15075#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
15076#define ENET_EIR_UN_MASK (0x80000U)
15077#define ENET_EIR_UN_SHIFT (19U)
15078#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
15079#define ENET_EIR_RL_MASK (0x100000U)
15080#define ENET_EIR_RL_SHIFT (20U)
15081#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
15082#define ENET_EIR_LC_MASK (0x200000U)
15083#define ENET_EIR_LC_SHIFT (21U)
15084#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
15085#define ENET_EIR_EBERR_MASK (0x400000U)
15086#define ENET_EIR_EBERR_SHIFT (22U)
15087#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
15088#define ENET_EIR_MII_MASK (0x800000U)
15089#define ENET_EIR_MII_SHIFT (23U)
15090#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
15091#define ENET_EIR_RXB_MASK (0x1000000U)
15092#define ENET_EIR_RXB_SHIFT (24U)
15093#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
15094#define ENET_EIR_RXF_MASK (0x2000000U)
15095#define ENET_EIR_RXF_SHIFT (25U)
15096#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
15097#define ENET_EIR_TXB_MASK (0x4000000U)
15098#define ENET_EIR_TXB_SHIFT (26U)
15099#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
15100#define ENET_EIR_TXF_MASK (0x8000000U)
15101#define ENET_EIR_TXF_SHIFT (27U)
15102#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
15103#define ENET_EIR_GRA_MASK (0x10000000U)
15104#define ENET_EIR_GRA_SHIFT (28U)
15105#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
15106#define ENET_EIR_BABT_MASK (0x20000000U)
15107#define ENET_EIR_BABT_SHIFT (29U)
15108#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
15109#define ENET_EIR_BABR_MASK (0x40000000U)
15110#define ENET_EIR_BABR_SHIFT (30U)
15111#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
15112/*! @} */
15113
15114/*! @name EIMR - Interrupt Mask Register */
15115/*! @{ */
15116#define ENET_EIMR_RXB1_MASK (0x1U)
15117#define ENET_EIMR_RXB1_SHIFT (0U)
15118#define ENET_EIMR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK)
15119#define ENET_EIMR_RXF1_MASK (0x2U)
15120#define ENET_EIMR_RXF1_SHIFT (1U)
15121#define ENET_EIMR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK)
15122#define ENET_EIMR_TXB1_MASK (0x4U)
15123#define ENET_EIMR_TXB1_SHIFT (2U)
15124#define ENET_EIMR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK)
15125#define ENET_EIMR_TXF1_MASK (0x8U)
15126#define ENET_EIMR_TXF1_SHIFT (3U)
15127#define ENET_EIMR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK)
15128#define ENET_EIMR_RXB2_MASK (0x10U)
15129#define ENET_EIMR_RXB2_SHIFT (4U)
15130#define ENET_EIMR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK)
15131#define ENET_EIMR_RXF2_MASK (0x20U)
15132#define ENET_EIMR_RXF2_SHIFT (5U)
15133#define ENET_EIMR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK)
15134#define ENET_EIMR_TXB2_MASK (0x40U)
15135#define ENET_EIMR_TXB2_SHIFT (6U)
15136#define ENET_EIMR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK)
15137#define ENET_EIMR_TXF2_MASK (0x80U)
15138#define ENET_EIMR_TXF2_SHIFT (7U)
15139#define ENET_EIMR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK)
15140#define ENET_EIMR_RXFLUSH_0_MASK (0x1000U)
15141#define ENET_EIMR_RXFLUSH_0_SHIFT (12U)
15142#define ENET_EIMR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK)
15143#define ENET_EIMR_RXFLUSH_1_MASK (0x2000U)
15144#define ENET_EIMR_RXFLUSH_1_SHIFT (13U)
15145#define ENET_EIMR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK)
15146#define ENET_EIMR_RXFLUSH_2_MASK (0x4000U)
15147#define ENET_EIMR_RXFLUSH_2_SHIFT (14U)
15148#define ENET_EIMR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK)
15149#define ENET_EIMR_TS_TIMER_MASK (0x8000U)
15150#define ENET_EIMR_TS_TIMER_SHIFT (15U)
15151#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
15152#define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
15153#define ENET_EIMR_TS_AVAIL_SHIFT (16U)
15154#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
15155#define ENET_EIMR_WAKEUP_MASK (0x20000U)
15156#define ENET_EIMR_WAKEUP_SHIFT (17U)
15157#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
15158#define ENET_EIMR_PLR_MASK (0x40000U)
15159#define ENET_EIMR_PLR_SHIFT (18U)
15160#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
15161#define ENET_EIMR_UN_MASK (0x80000U)
15162#define ENET_EIMR_UN_SHIFT (19U)
15163#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
15164#define ENET_EIMR_RL_MASK (0x100000U)
15165#define ENET_EIMR_RL_SHIFT (20U)
15166#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
15167#define ENET_EIMR_LC_MASK (0x200000U)
15168#define ENET_EIMR_LC_SHIFT (21U)
15169#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
15170#define ENET_EIMR_EBERR_MASK (0x400000U)
15171#define ENET_EIMR_EBERR_SHIFT (22U)
15172#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
15173#define ENET_EIMR_MII_MASK (0x800000U)
15174#define ENET_EIMR_MII_SHIFT (23U)
15175#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
15176#define ENET_EIMR_RXB_MASK (0x1000000U)
15177#define ENET_EIMR_RXB_SHIFT (24U)
15178#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
15179#define ENET_EIMR_RXF_MASK (0x2000000U)
15180#define ENET_EIMR_RXF_SHIFT (25U)
15181#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
15182#define ENET_EIMR_TXB_MASK (0x4000000U)
15183#define ENET_EIMR_TXB_SHIFT (26U)
15184/*! TXB - TXB Interrupt Mask
15185 * 0b0..The corresponding interrupt source is masked.
15186 * 0b1..The corresponding interrupt source is not masked.
15187 */
15188#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
15189#define ENET_EIMR_TXF_MASK (0x8000000U)
15190#define ENET_EIMR_TXF_SHIFT (27U)
15191/*! TXF - TXF Interrupt Mask
15192 * 0b0..The corresponding interrupt source is masked.
15193 * 0b1..The corresponding interrupt source is not masked.
15194 */
15195#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
15196#define ENET_EIMR_GRA_MASK (0x10000000U)
15197#define ENET_EIMR_GRA_SHIFT (28U)
15198/*! GRA - GRA Interrupt Mask
15199 * 0b0..The corresponding interrupt source is masked.
15200 * 0b1..The corresponding interrupt source is not masked.
15201 */
15202#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
15203#define ENET_EIMR_BABT_MASK (0x20000000U)
15204#define ENET_EIMR_BABT_SHIFT (29U)
15205/*! BABT - BABT Interrupt Mask
15206 * 0b0..The corresponding interrupt source is masked.
15207 * 0b1..The corresponding interrupt source is not masked.
15208 */
15209#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
15210#define ENET_EIMR_BABR_MASK (0x40000000U)
15211#define ENET_EIMR_BABR_SHIFT (30U)
15212/*! BABR - BABR Interrupt Mask
15213 * 0b0..The corresponding interrupt source is masked.
15214 * 0b1..The corresponding interrupt source is not masked.
15215 */
15216#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
15217/*! @} */
15218
15219/*! @name RDAR - Receive Descriptor Active Register - Ring 0 */
15220/*! @{ */
15221#define ENET_RDAR_RDAR_MASK (0x1000000U)
15222#define ENET_RDAR_RDAR_SHIFT (24U)
15223#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
15224/*! @} */
15225
15226/*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */
15227/*! @{ */
15228#define ENET_TDAR_TDAR_MASK (0x1000000U)
15229#define ENET_TDAR_TDAR_SHIFT (24U)
15230#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
15231/*! @} */
15232
15233/*! @name ECR - Ethernet Control Register */
15234/*! @{ */
15235#define ENET_ECR_RESET_MASK (0x1U)
15236#define ENET_ECR_RESET_SHIFT (0U)
15237#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
15238#define ENET_ECR_ETHEREN_MASK (0x2U)
15239#define ENET_ECR_ETHEREN_SHIFT (1U)
15240/*! ETHEREN - Ethernet Enable
15241 * 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.
15242 * 0b1..MAC is enabled, and reception and transmission are possible.
15243 */
15244#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
15245#define ENET_ECR_MAGICEN_MASK (0x4U)
15246#define ENET_ECR_MAGICEN_SHIFT (2U)
15247/*! MAGICEN - Magic Packet Detection Enable
15248 * 0b0..Magic detection logic disabled.
15249 * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
15250 */
15251#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
15252#define ENET_ECR_SLEEP_MASK (0x8U)
15253#define ENET_ECR_SLEEP_SHIFT (3U)
15254/*! SLEEP - Sleep Mode Enable
15255 * 0b0..Normal operating mode.
15256 * 0b1..Sleep mode.
15257 */
15258#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
15259#define ENET_ECR_EN1588_MASK (0x10U)
15260#define ENET_ECR_EN1588_SHIFT (4U)
15261/*! EN1588 - EN1588 Enable
15262 * 0b0..Legacy FEC buffer descriptors and functions enabled.
15263 * 0b1..Enhanced frame time-stamping functions enabled.
15264 */
15265#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
15266#define ENET_ECR_SPEED_MASK (0x20U)
15267#define ENET_ECR_SPEED_SHIFT (5U)
15268/*! SPEED
15269 * 0b0..10/100-Mbit/s mode
15270 * 0b1..1000-Mbit/s mode
15271 */
15272#define ENET_ECR_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK)
15273#define ENET_ECR_DBGEN_MASK (0x40U)
15274#define ENET_ECR_DBGEN_SHIFT (6U)
15275/*! DBGEN - Debug Enable
15276 * 0b0..MAC continues operation in debug mode.
15277 * 0b1..MAC enters hardware freeze mode when the processor is in debug mode.
15278 */
15279#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
15280#define ENET_ECR_DBSWP_MASK (0x100U)
15281#define ENET_ECR_DBSWP_SHIFT (8U)
15282/*! DBSWP - Descriptor Byte Swapping Enable
15283 * 0b0..The buffer descriptor bytes are not swapped to support big-endian devices.
15284 * 0b1..The buffer descriptor bytes are swapped to support little-endian devices.
15285 */
15286#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
15287#define ENET_ECR_SVLANEN_MASK (0x200U)
15288#define ENET_ECR_SVLANEN_SHIFT (9U)
15289/*! SVLANEN - S-VLAN enable
15290 * 0b0..Only the EtherType 0x8100 will be considered for VLAN detection.
15291 * 0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the classification match comparators, RCMRn.
15292 */
15293#define ENET_ECR_SVLANEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK)
15294#define ENET_ECR_VLANUSE2ND_MASK (0x400U)
15295#define ENET_ECR_VLANUSE2ND_SHIFT (10U)
15296/*! VLANUSE2ND - VLAN use second tag
15297 * 0b0..Always extract data from the first VLAN tag if it exists.
15298 * 0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The second tag must be a C-VLAN
15299 */
15300#define ENET_ECR_VLANUSE2ND(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK)
15301#define ENET_ECR_SVLANDBL_MASK (0x800U)
15302#define ENET_ECR_SVLANDBL_SHIFT (11U)
15303#define ENET_ECR_SVLANDBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK)
15304/*! @} */
15305
15306/*! @name MMFR - MII Management Frame Register */
15307/*! @{ */
15308#define ENET_MMFR_DATA_MASK (0xFFFFU)
15309#define ENET_MMFR_DATA_SHIFT (0U)
15310#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
15311#define ENET_MMFR_TA_MASK (0x30000U)
15312#define ENET_MMFR_TA_SHIFT (16U)
15313#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
15314#define ENET_MMFR_RA_MASK (0x7C0000U)
15315#define ENET_MMFR_RA_SHIFT (18U)
15316#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
15317#define ENET_MMFR_PA_MASK (0xF800000U)
15318#define ENET_MMFR_PA_SHIFT (23U)
15319#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
15320#define ENET_MMFR_OP_MASK (0x30000000U)
15321#define ENET_MMFR_OP_SHIFT (28U)
15322#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
15323#define ENET_MMFR_ST_MASK (0xC0000000U)
15324#define ENET_MMFR_ST_SHIFT (30U)
15325#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
15326/*! @} */
15327
15328/*! @name MSCR - MII Speed Control Register */
15329/*! @{ */
15330#define ENET_MSCR_MII_SPEED_MASK (0x7EU)
15331#define ENET_MSCR_MII_SPEED_SHIFT (1U)
15332#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
15333#define ENET_MSCR_DIS_PRE_MASK (0x80U)
15334#define ENET_MSCR_DIS_PRE_SHIFT (7U)
15335/*! DIS_PRE - Disable Preamble
15336 * 0b0..Preamble enabled.
15337 * 0b1..Preamble (32 ones) is not prepended to the MII management frame.
15338 */
15339#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
15340#define ENET_MSCR_HOLDTIME_MASK (0x700U)
15341#define ENET_MSCR_HOLDTIME_SHIFT (8U)
15342/*! HOLDTIME - Hold time On MDIO Output
15343 * 0b000..1 internal module clock cycle
15344 * 0b001..2 internal module clock cycles
15345 * 0b010..3 internal module clock cycles
15346 * 0b111..8 internal module clock cycles
15347 */
15348#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
15349/*! @} */
15350
15351/*! @name MIBC - MIB Control Register */
15352/*! @{ */
15353#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
15354#define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
15355/*! MIB_CLEAR - MIB Clear
15356 * 0b0..See note above.
15357 * 0b1..All statistics counters are reset to 0.
15358 */
15359#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
15360#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
15361#define ENET_MIBC_MIB_IDLE_SHIFT (30U)
15362/*! MIB_IDLE - MIB Idle
15363 * 0b0..The MIB block is updating MIB counters.
15364 * 0b1..The MIB block is not currently updating any MIB counters.
15365 */
15366#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
15367#define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
15368#define ENET_MIBC_MIB_DIS_SHIFT (31U)
15369/*! MIB_DIS - Disable MIB Logic
15370 * 0b0..MIB logic is enabled.
15371 * 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
15372 */
15373#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
15374/*! @} */
15375
15376/*! @name RCR - Receive Control Register */
15377/*! @{ */
15378#define ENET_RCR_LOOP_MASK (0x1U)
15379#define ENET_RCR_LOOP_SHIFT (0U)
15380/*! LOOP - Internal Loopback
15381 * 0b0..Loopback disabled.
15382 * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
15383 */
15384#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
15385#define ENET_RCR_DRT_MASK (0x2U)
15386#define ENET_RCR_DRT_SHIFT (1U)
15387/*! DRT - Disable Receive On Transmit
15388 * 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode.
15389 * 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
15390 */
15391#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
15392#define ENET_RCR_MII_MODE_MASK (0x4U)
15393#define ENET_RCR_MII_MODE_SHIFT (2U)
15394/*! MII_MODE - Media Independent Interface Mode
15395 * 0b0..Reserved.
15396 * 0b1..MII or RMII mode, as indicated by the RMII_MODE field.
15397 */
15398#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
15399#define ENET_RCR_PROM_MASK (0x8U)
15400#define ENET_RCR_PROM_SHIFT (3U)
15401/*! PROM - Promiscuous Mode
15402 * 0b0..Disabled.
15403 * 0b1..Enabled.
15404 */
15405#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
15406#define ENET_RCR_BC_REJ_MASK (0x10U)
15407#define ENET_RCR_BC_REJ_SHIFT (4U)
15408#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
15409#define ENET_RCR_FCE_MASK (0x20U)
15410#define ENET_RCR_FCE_SHIFT (5U)
15411#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
15412#define ENET_RCR_RGMII_EN_MASK (0x40U)
15413#define ENET_RCR_RGMII_EN_SHIFT (6U)
15414/*! RGMII_EN - RGMII Mode Enable
15415 * 0b0..MAC configured for non-RGMII operation
15416 * 0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode.
15417 */
15418#define ENET_RCR_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK)
15419#define ENET_RCR_RMII_MODE_MASK (0x100U)
15420#define ENET_RCR_RMII_MODE_SHIFT (8U)
15421/*! RMII_MODE - RMII Mode Enable
15422 * 0b0..MAC configured for MII mode.
15423 * 0b1..MAC configured for RMII operation.
15424 */
15425#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
15426#define ENET_RCR_RMII_10T_MASK (0x200U)
15427#define ENET_RCR_RMII_10T_SHIFT (9U)
15428/*! RMII_10T
15429 * 0b0..100-Mbit/s operation.
15430 * 0b1..10-Mbit/s operation.
15431 */
15432#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
15433#define ENET_RCR_PADEN_MASK (0x1000U)
15434#define ENET_RCR_PADEN_SHIFT (12U)
15435/*! PADEN - Enable Frame Padding Remove On Receive
15436 * 0b0..No padding is removed on receive by the MAC.
15437 * 0b1..Padding is removed from received frames.
15438 */
15439#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
15440#define ENET_RCR_PAUFWD_MASK (0x2000U)
15441#define ENET_RCR_PAUFWD_SHIFT (13U)
15442/*! PAUFWD - Terminate/Forward Pause Frames
15443 * 0b0..Pause frames are terminated and discarded in the MAC.
15444 * 0b1..Pause frames are forwarded to the user application.
15445 */
15446#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
15447#define ENET_RCR_CRCFWD_MASK (0x4000U)
15448#define ENET_RCR_CRCFWD_SHIFT (14U)
15449/*! CRCFWD - Terminate/Forward Received CRC
15450 * 0b0..The CRC field of received frames is transmitted to the user application.
15451 * 0b1..The CRC field is stripped from the frame.
15452 */
15453#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
15454#define ENET_RCR_CFEN_MASK (0x8000U)
15455#define ENET_RCR_CFEN_SHIFT (15U)
15456/*! CFEN - MAC Control Frame Enable
15457 * 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface.
15458 * 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
15459 */
15460#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
15461#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
15462#define ENET_RCR_MAX_FL_SHIFT (16U)
15463#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
15464#define ENET_RCR_NLC_MASK (0x40000000U)
15465#define ENET_RCR_NLC_SHIFT (30U)
15466/*! NLC - Payload Length Check Disable
15467 * 0b0..The payload length check is disabled.
15468 * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.
15469 */
15470#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
15471#define ENET_RCR_GRS_MASK (0x80000000U)
15472#define ENET_RCR_GRS_SHIFT (31U)
15473#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
15474/*! @} */
15475
15476/*! @name TCR - Transmit Control Register */
15477/*! @{ */
15478#define ENET_TCR_GTS_MASK (0x1U)
15479#define ENET_TCR_GTS_SHIFT (0U)
15480#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
15481#define ENET_TCR_FDEN_MASK (0x4U)
15482#define ENET_TCR_FDEN_SHIFT (2U)
15483#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
15484#define ENET_TCR_TFC_PAUSE_MASK (0x8U)
15485#define ENET_TCR_TFC_PAUSE_SHIFT (3U)
15486/*! TFC_PAUSE - Transmit Frame Control Pause
15487 * 0b0..No PAUSE frame transmitted.
15488 * 0b1..The MAC stops transmission of data frames after the current transmission is complete.
15489 */
15490#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
15491#define ENET_TCR_RFC_PAUSE_MASK (0x10U)
15492#define ENET_TCR_RFC_PAUSE_SHIFT (4U)
15493#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
15494#define ENET_TCR_ADDSEL_MASK (0xE0U)
15495#define ENET_TCR_ADDSEL_SHIFT (5U)
15496/*! ADDSEL - Source MAC Address Select On Transmit
15497 * 0b000..Node MAC address programmed on PADDR1/2 registers.
15498 * 0b100..Reserved.
15499 * 0b101..Reserved.
15500 * 0b110..Reserved.
15501 */
15502#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
15503#define ENET_TCR_ADDINS_MASK (0x100U)
15504#define ENET_TCR_ADDINS_SHIFT (8U)
15505/*! ADDINS - Set MAC Address On Transmit
15506 * 0b0..The source MAC address is not modified by the MAC.
15507 * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
15508 */
15509#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
15510#define ENET_TCR_CRCFWD_MASK (0x200U)
15511#define ENET_TCR_CRCFWD_SHIFT (9U)
15512/*! CRCFWD - Forward Frame From Application With CRC
15513 * 0b0..TxBD[TC] controls whether the frame has a CRC from the application.
15514 * 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
15515 */
15516#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
15517/*! @} */
15518
15519/*! @name PALR - Physical Address Lower Register */
15520/*! @{ */
15521#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
15522#define ENET_PALR_PADDR1_SHIFT (0U)
15523#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
15524/*! @} */
15525
15526/*! @name PAUR - Physical Address Upper Register */
15527/*! @{ */
15528#define ENET_PAUR_TYPE_MASK (0xFFFFU)
15529#define ENET_PAUR_TYPE_SHIFT (0U)
15530#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
15531#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
15532#define ENET_PAUR_PADDR2_SHIFT (16U)
15533#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
15534/*! @} */
15535
15536/*! @name OPD - Opcode/Pause Duration Register */
15537/*! @{ */
15538#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
15539#define ENET_OPD_PAUSE_DUR_SHIFT (0U)
15540#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
15541#define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
15542#define ENET_OPD_OPCODE_SHIFT (16U)
15543#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
15544/*! @} */
15545
15546/*! @name TXIC - Transmit Interrupt Coalescing Register */
15547/*! @{ */
15548#define ENET_TXIC_ICTT_MASK (0xFFFFU)
15549#define ENET_TXIC_ICTT_SHIFT (0U)
15550#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
15551#define ENET_TXIC_ICFT_MASK (0xFF00000U)
15552#define ENET_TXIC_ICFT_SHIFT (20U)
15553#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
15554#define ENET_TXIC_ICCS_MASK (0x40000000U)
15555#define ENET_TXIC_ICCS_SHIFT (30U)
15556/*! ICCS - Interrupt Coalescing Timer Clock Source Select
15557 * 0b0..Use MII/GMII TX clocks.
15558 * 0b1..Use ENET system clock.
15559 */
15560#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
15561#define ENET_TXIC_ICEN_MASK (0x80000000U)
15562#define ENET_TXIC_ICEN_SHIFT (31U)
15563/*! ICEN - Interrupt Coalescing Enable
15564 * 0b0..Disable Interrupt coalescing.
15565 * 0b1..Enable Interrupt coalescing.
15566 */
15567#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
15568/*! @} */
15569
15570/* The count of ENET_TXIC */
15571#define ENET_TXIC_COUNT (3U)
15572
15573/*! @name RXIC - Receive Interrupt Coalescing Register */
15574/*! @{ */
15575#define ENET_RXIC_ICTT_MASK (0xFFFFU)
15576#define ENET_RXIC_ICTT_SHIFT (0U)
15577#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
15578#define ENET_RXIC_ICFT_MASK (0xFF00000U)
15579#define ENET_RXIC_ICFT_SHIFT (20U)
15580#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
15581#define ENET_RXIC_ICCS_MASK (0x40000000U)
15582#define ENET_RXIC_ICCS_SHIFT (30U)
15583/*! ICCS - Interrupt Coalescing Timer Clock Source Select
15584 * 0b0..Use MII/GMII TX clocks.
15585 * 0b1..Use ENET system clock.
15586 */
15587#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
15588#define ENET_RXIC_ICEN_MASK (0x80000000U)
15589#define ENET_RXIC_ICEN_SHIFT (31U)
15590/*! ICEN - Interrupt Coalescing Enable
15591 * 0b0..Disable Interrupt coalescing.
15592 * 0b1..Enable Interrupt coalescing.
15593 */
15594#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
15595/*! @} */
15596
15597/* The count of ENET_RXIC */
15598#define ENET_RXIC_COUNT (3U)
15599
15600/*! @name IAUR - Descriptor Individual Upper Address Register */
15601/*! @{ */
15602#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
15603#define ENET_IAUR_IADDR1_SHIFT (0U)
15604#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
15605/*! @} */
15606
15607/*! @name IALR - Descriptor Individual Lower Address Register */
15608/*! @{ */
15609#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
15610#define ENET_IALR_IADDR2_SHIFT (0U)
15611#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
15612/*! @} */
15613
15614/*! @name GAUR - Descriptor Group Upper Address Register */
15615/*! @{ */
15616#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
15617#define ENET_GAUR_GADDR1_SHIFT (0U)
15618#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
15619/*! @} */
15620
15621/*! @name GALR - Descriptor Group Lower Address Register */
15622/*! @{ */
15623#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
15624#define ENET_GALR_GADDR2_SHIFT (0U)
15625#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
15626/*! @} */
15627
15628/*! @name TFWR - Transmit FIFO Watermark Register */
15629/*! @{ */
15630#define ENET_TFWR_TFWR_MASK (0x3FU)
15631#define ENET_TFWR_TFWR_SHIFT (0U)
15632/*! TFWR - Transmit FIFO Write
15633 * 0b000000..64 bytes written.
15634 * 0b000001..64 bytes written.
15635 * 0b000010..128 bytes written.
15636 * 0b000011..192 bytes written.
15637 * 0b111111..4032 bytes written.
15638 */
15639#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
15640#define ENET_TFWR_STRFWD_MASK (0x100U)
15641#define ENET_TFWR_STRFWD_SHIFT (8U)
15642/*! STRFWD - Store And Forward Enable
15643 * 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR].
15644 * 0b1..Enabled.
15645 */
15646#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
15647/*! @} */
15648
15649/*! @name RDSR1 - Receive Descriptor Ring 1 Start Register */
15650/*! @{ */
15651#define ENET_RDSR1_R_DES_START_MASK (0xFFFFFFF8U)
15652#define ENET_RDSR1_R_DES_START_SHIFT (3U)
15653#define ENET_RDSR1_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK)
15654/*! @} */
15655
15656/*! @name TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register */
15657/*! @{ */
15658#define ENET_TDSR1_X_DES_START_MASK (0xFFFFFFF8U)
15659#define ENET_TDSR1_X_DES_START_SHIFT (3U)
15660#define ENET_TDSR1_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK)
15661/*! @} */
15662
15663/*! @name MRBR1 - Maximum Receive Buffer Size Register - Ring 1 */
15664/*! @{ */
15665#define ENET_MRBR1_R_BUF_SIZE_MASK (0x7F0U)
15666#define ENET_MRBR1_R_BUF_SIZE_SHIFT (4U)
15667#define ENET_MRBR1_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK)
15668/*! @} */
15669
15670/*! @name RDSR2 - Receive Descriptor Ring 2 Start Register */
15671/*! @{ */
15672#define ENET_RDSR2_R_DES_START_MASK (0xFFFFFFF8U)
15673#define ENET_RDSR2_R_DES_START_SHIFT (3U)
15674#define ENET_RDSR2_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK)
15675/*! @} */
15676
15677/*! @name TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register */
15678/*! @{ */
15679#define ENET_TDSR2_X_DES_START_MASK (0xFFFFFFF8U)
15680#define ENET_TDSR2_X_DES_START_SHIFT (3U)
15681#define ENET_TDSR2_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK)
15682/*! @} */
15683
15684/*! @name MRBR2 - Maximum Receive Buffer Size Register - Ring 2 */
15685/*! @{ */
15686#define ENET_MRBR2_R_BUF_SIZE_MASK (0x7F0U)
15687#define ENET_MRBR2_R_BUF_SIZE_SHIFT (4U)
15688#define ENET_MRBR2_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK)
15689/*! @} */
15690
15691/*! @name RDSR - Receive Descriptor Ring 0 Start Register */
15692/*! @{ */
15693#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
15694#define ENET_RDSR_R_DES_START_SHIFT (3U)
15695#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
15696/*! @} */
15697
15698/*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */
15699/*! @{ */
15700#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
15701#define ENET_TDSR_X_DES_START_SHIFT (3U)
15702#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
15703/*! @} */
15704
15705/*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */
15706/*! @{ */
15707#define ENET_MRBR_R_BUF_SIZE_MASK (0x7F0U)
15708#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
15709#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
15710/*! @} */
15711
15712/*! @name RSFL - Receive FIFO Section Full Threshold */
15713/*! @{ */
15714#define ENET_RSFL_RX_SECTION_FULL_MASK (0x3FFU)
15715#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
15716#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
15717/*! @} */
15718
15719/*! @name RSEM - Receive FIFO Section Empty Threshold */
15720/*! @{ */
15721#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0x3FFU)
15722#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
15723#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
15724#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
15725#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
15726#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
15727/*! @} */
15728
15729/*! @name RAEM - Receive FIFO Almost Empty Threshold */
15730/*! @{ */
15731#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0x3FFU)
15732#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
15733#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
15734/*! @} */
15735
15736/*! @name RAFL - Receive FIFO Almost Full Threshold */
15737/*! @{ */
15738#define ENET_RAFL_RX_ALMOST_FULL_MASK (0x3FFU)
15739#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
15740#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
15741/*! @} */
15742
15743/*! @name TSEM - Transmit FIFO Section Empty Threshold */
15744/*! @{ */
15745#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0x3FFU)
15746#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
15747#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
15748/*! @} */
15749
15750/*! @name TAEM - Transmit FIFO Almost Empty Threshold */
15751/*! @{ */
15752#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0x3FFU)
15753#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
15754#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
15755/*! @} */
15756
15757/*! @name TAFL - Transmit FIFO Almost Full Threshold */
15758/*! @{ */
15759#define ENET_TAFL_TX_ALMOST_FULL_MASK (0x3FFU)
15760#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
15761#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
15762/*! @} */
15763
15764/*! @name TIPG - Transmit Inter-Packet Gap */
15765/*! @{ */
15766#define ENET_TIPG_IPG_MASK (0x1FU)
15767#define ENET_TIPG_IPG_SHIFT (0U)
15768#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
15769/*! @} */
15770
15771/*! @name FTRL - Frame Truncation Length */
15772/*! @{ */
15773#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
15774#define ENET_FTRL_TRUNC_FL_SHIFT (0U)
15775#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
15776/*! @} */
15777
15778/*! @name TACC - Transmit Accelerator Function Configuration */
15779/*! @{ */
15780#define ENET_TACC_SHIFT16_MASK (0x1U)
15781#define ENET_TACC_SHIFT16_SHIFT (0U)
15782/*! SHIFT16 - TX FIFO Shift-16
15783 * 0b0..Disabled.
15784 * 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.
15785 */
15786#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
15787#define ENET_TACC_IPCHK_MASK (0x8U)
15788#define ENET_TACC_IPCHK_SHIFT (3U)
15789/*! IPCHK
15790 * 0b0..Checksum is not inserted.
15791 * 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.
15792 */
15793#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
15794#define ENET_TACC_PROCHK_MASK (0x10U)
15795#define ENET_TACC_PROCHK_SHIFT (4U)
15796/*! PROCHK
15797 * 0b0..Checksum not inserted.
15798 * 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.
15799 */
15800#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
15801/*! @} */
15802
15803/*! @name RACC - Receive Accelerator Function Configuration */
15804/*! @{ */
15805#define ENET_RACC_PADREM_MASK (0x1U)
15806#define ENET_RACC_PADREM_SHIFT (0U)
15807/*! PADREM - Enable Padding Removal For Short IP Frames
15808 * 0b0..Padding not removed.
15809 * 0b1..Any bytes following the IP payload section of the frame are removed from the frame.
15810 */
15811#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
15812#define ENET_RACC_IPDIS_MASK (0x2U)
15813#define ENET_RACC_IPDIS_SHIFT (1U)
15814/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum
15815 * 0b0..Frames with wrong IPv4 header checksum are not discarded.
15816 * 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).
15817 */
15818#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
15819#define ENET_RACC_PRODIS_MASK (0x4U)
15820#define ENET_RACC_PRODIS_SHIFT (2U)
15821/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum
15822 * 0b0..Frames with wrong checksum are not discarded.
15823 * 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).
15824 */
15825#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
15826#define ENET_RACC_LINEDIS_MASK (0x40U)
15827#define ENET_RACC_LINEDIS_SHIFT (6U)
15828/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors
15829 * 0b0..Frames with errors are not discarded.
15830 * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
15831 */
15832#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
15833#define ENET_RACC_SHIFT16_MASK (0x80U)
15834#define ENET_RACC_SHIFT16_SHIFT (7U)
15835/*! SHIFT16 - RX FIFO Shift-16
15836 * 0b0..Disabled.
15837 * 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
15838 */
15839#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
15840/*! @} */
15841
15842/*! @name RCMR - Receive Classification Match Register for Class n */
15843/*! @{ */
15844#define ENET_RCMR_CMP0_MASK (0x7U)
15845#define ENET_RCMR_CMP0_SHIFT (0U)
15846#define ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK)
15847#define ENET_RCMR_CMP1_MASK (0x70U)
15848#define ENET_RCMR_CMP1_SHIFT (4U)
15849#define ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK)
15850#define ENET_RCMR_CMP2_MASK (0x700U)
15851#define ENET_RCMR_CMP2_SHIFT (8U)
15852#define ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK)
15853#define ENET_RCMR_CMP3_MASK (0x7000U)
15854#define ENET_RCMR_CMP3_SHIFT (12U)
15855#define ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK)
15856#define ENET_RCMR_MATCHEN_MASK (0x10000U)
15857#define ENET_RCMR_MATCHEN_SHIFT (16U)
15858/*! MATCHEN - Match Enable
15859 * 0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert.
15860 * 0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received.
15861 */
15862#define ENET_RCMR_MATCHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK)
15863/*! @} */
15864
15865/* The count of ENET_RCMR */
15866#define ENET_RCMR_COUNT (2U)
15867
15868/*! @name DMACFG - DMA Class Based Configuration */
15869/*! @{ */
15870#define ENET_DMACFG_IDLE_SLOPE_MASK (0xFFFFU)
15871#define ENET_DMACFG_IDLE_SLOPE_SHIFT (0U)
15872#define ENET_DMACFG_IDLE_SLOPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK)
15873#define ENET_DMACFG_DMA_CLASS_EN_MASK (0x10000U)
15874#define ENET_DMACFG_DMA_CLASS_EN_SHIFT (16U)
15875/*! DMA_CLASS_EN - DMA class enable
15876 * 0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2 queues are disabled then their frames will be placed in queue 0.
15877 * 0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic.
15878 */
15879#define ENET_DMACFG_DMA_CLASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK)
15880#define ENET_DMACFG_CALC_NOIPG_MASK (0x20000U)
15881#define ENET_DMACFG_CALC_NOIPG_SHIFT (17U)
15882/*! CALC_NOIPG - Calculate no IPG
15883 * 0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred for a frame when doing bandwidth calculations. This is the default.
15884 * 0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping, when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames will become more bandwidth than large frames due to the relation of data to IPG overhead).
15885 */
15886#define ENET_DMACFG_CALC_NOIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK)
15887/*! @} */
15888
15889/* The count of ENET_DMACFG */
15890#define ENET_DMACFG_COUNT (2U)
15891
15892/*! @name RDAR1 - Receive Descriptor Active Register - Ring 1 */
15893/*! @{ */
15894#define ENET_RDAR1_RDAR_MASK (0x1000000U)
15895#define ENET_RDAR1_RDAR_SHIFT (24U)
15896#define ENET_RDAR1_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK)
15897/*! @} */
15898
15899/*! @name TDAR1 - Transmit Descriptor Active Register - Ring 1 */
15900/*! @{ */
15901#define ENET_TDAR1_TDAR_MASK (0x1000000U)
15902#define ENET_TDAR1_TDAR_SHIFT (24U)
15903#define ENET_TDAR1_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK)
15904/*! @} */
15905
15906/*! @name RDAR2 - Receive Descriptor Active Register - Ring 2 */
15907/*! @{ */
15908#define ENET_RDAR2_RDAR_MASK (0x1000000U)
15909#define ENET_RDAR2_RDAR_SHIFT (24U)
15910#define ENET_RDAR2_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK)
15911/*! @} */
15912
15913/*! @name TDAR2 - Transmit Descriptor Active Register - Ring 2 */
15914/*! @{ */
15915#define ENET_TDAR2_TDAR_MASK (0x1000000U)
15916#define ENET_TDAR2_TDAR_SHIFT (24U)
15917#define ENET_TDAR2_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK)
15918/*! @} */
15919
15920/*! @name QOS - QOS Scheme */
15921/*! @{ */
15922#define ENET_QOS_TX_SCHEME_MASK (0x7U)
15923#define ENET_QOS_TX_SCHEME_SHIFT (0U)
15924/*! TX_SCHEME - TX scheme configuration
15925 * 0b000..Credit-based scheme
15926 * 0b001..Round-robin scheme
15927 */
15928#define ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK)
15929#define ENET_QOS_RX_FLUSH0_MASK (0x8U)
15930#define ENET_QOS_RX_FLUSH0_SHIFT (3U)
15931/*! RX_FLUSH0 - RX Flush Ring 0
15932 * 0b0..Disable
15933 * 0b1..Enable
15934 */
15935#define ENET_QOS_RX_FLUSH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK)
15936#define ENET_QOS_RX_FLUSH1_MASK (0x10U)
15937#define ENET_QOS_RX_FLUSH1_SHIFT (4U)
15938/*! RX_FLUSH1 - RX Flush Ring 1
15939 * 0b0..Disable
15940 * 0b1..Enable
15941 */
15942#define ENET_QOS_RX_FLUSH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK)
15943#define ENET_QOS_RX_FLUSH2_MASK (0x20U)
15944#define ENET_QOS_RX_FLUSH2_SHIFT (5U)
15945/*! RX_FLUSH2 - RX Flush Ring 2
15946 * 0b0..Disable
15947 * 0b1..Enable
15948 */
15949#define ENET_QOS_RX_FLUSH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK)
15950/*! @} */
15951
15952/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
15953/*! @{ */
15954#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
15955#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
15956#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
15957/*! @} */
15958
15959/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
15960/*! @{ */
15961#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
15962#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
15963#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
15964/*! @} */
15965
15966/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
15967/*! @{ */
15968#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
15969#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
15970#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
15971/*! @} */
15972
15973/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
15974/*! @{ */
15975#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
15976#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
15977#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
15978/*! @} */
15979
15980/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
15981/*! @{ */
15982#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
15983#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
15984#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
15985/*! @} */
15986
15987/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
15988/*! @{ */
15989#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
15990#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
15991#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
15992/*! @} */
15993
15994/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
15995/*! @{ */
15996#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
15997#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
15998#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
15999/*! @} */
16000
16001/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
16002/*! @{ */
16003#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
16004#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
16005#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
16006/*! @} */
16007
16008/*! @name RMON_T_COL - Tx Collision Count Statistic Register */
16009/*! @{ */
16010#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
16011#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
16012#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
16013/*! @} */
16014
16015/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
16016/*! @{ */
16017#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
16018#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
16019#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
16020/*! @} */
16021
16022/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
16023/*! @{ */
16024#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
16025#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
16026#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
16027/*! @} */
16028
16029/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
16030/*! @{ */
16031#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
16032#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
16033#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
16034/*! @} */
16035
16036/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
16037/*! @{ */
16038#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
16039#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
16040#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
16041/*! @} */
16042
16043/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
16044/*! @{ */
16045#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
16046#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
16047#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
16048/*! @} */
16049
16050/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
16051/*! @{ */
16052#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
16053#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
16054#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
16055/*! @} */
16056
16057/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
16058/*! @{ */
16059#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
16060#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
16061#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
16062/*! @} */
16063
16064/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
16065/*! @{ */
16066#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
16067#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
16068#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
16069/*! @} */
16070
16071/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
16072/*! @{ */
16073#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
16074#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
16075#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
16076/*! @} */
16077
16078/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
16079/*! @{ */
16080#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
16081#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
16082#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
16083/*! @} */
16084
16085/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
16086/*! @{ */
16087#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
16088#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
16089#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
16090/*! @} */
16091
16092/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
16093/*! @{ */
16094#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
16095#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
16096#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
16097/*! @} */
16098
16099/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
16100/*! @{ */
16101#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
16102#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
16103#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
16104/*! @} */
16105
16106/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
16107/*! @{ */
16108#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
16109#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
16110#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
16111/*! @} */
16112
16113/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
16114/*! @{ */
16115#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
16116#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
16117#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
16118/*! @} */
16119
16120/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
16121/*! @{ */
16122#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
16123#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
16124#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
16125/*! @} */
16126
16127/*! @name IEEE_T_SQE - Reserved Statistic Register */
16128/*! @{ */
16129#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
16130#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
16131#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
16132/*! @} */
16133
16134/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
16135/*! @{ */
16136#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
16137#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
16138#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
16139/*! @} */
16140
16141/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
16142/*! @{ */
16143#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
16144#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
16145#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
16146/*! @} */
16147
16148/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
16149/*! @{ */
16150#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
16151#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
16152#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
16153/*! @} */
16154
16155/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
16156/*! @{ */
16157#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
16158#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
16159#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
16160/*! @} */
16161
16162/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
16163/*! @{ */
16164#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
16165#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
16166#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
16167/*! @} */
16168
16169/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
16170/*! @{ */
16171#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
16172#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
16173#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
16174/*! @} */
16175
16176/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
16177/*! @{ */
16178#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
16179#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
16180#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
16181/*! @} */
16182
16183/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
16184/*! @{ */
16185#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
16186#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
16187#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
16188/*! @} */
16189
16190/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
16191/*! @{ */
16192#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
16193#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
16194#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
16195/*! @} */
16196
16197/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
16198/*! @{ */
16199#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
16200#define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
16201#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
16202/*! @} */
16203
16204/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
16205/*! @{ */
16206#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
16207#define ENET_RMON_R_P64_COUNT_SHIFT (0U)
16208#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
16209/*! @} */
16210
16211/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
16212/*! @{ */
16213#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
16214#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
16215#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
16216/*! @} */
16217
16218/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
16219/*! @{ */
16220#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
16221#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
16222#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
16223/*! @} */
16224
16225/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
16226/*! @{ */
16227#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
16228#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
16229#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
16230/*! @} */
16231
16232/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
16233/*! @{ */
16234#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
16235#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
16236#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
16237/*! @} */
16238
16239/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
16240/*! @{ */
16241#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
16242#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
16243#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
16244/*! @} */
16245
16246/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
16247/*! @{ */
16248#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
16249#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
16250#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
16251/*! @} */
16252
16253/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
16254/*! @{ */
16255#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
16256#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
16257#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
16258/*! @} */
16259
16260/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
16261/*! @{ */
16262#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
16263#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
16264#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
16265/*! @} */
16266
16267/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
16268/*! @{ */
16269#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
16270#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
16271#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
16272/*! @} */
16273
16274/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
16275/*! @{ */
16276#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
16277#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
16278#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
16279/*! @} */
16280
16281/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
16282/*! @{ */
16283#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
16284#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
16285#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
16286/*! @} */
16287
16288/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
16289/*! @{ */
16290#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
16291#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
16292#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
16293/*! @} */
16294
16295/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
16296/*! @{ */
16297#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
16298#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
16299#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
16300/*! @} */
16301
16302/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
16303/*! @{ */
16304#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
16305#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
16306#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
16307/*! @} */
16308
16309/*! @name ATCR - Adjustable Timer Control Register */
16310/*! @{ */
16311#define ENET_ATCR_EN_MASK (0x1U)
16312#define ENET_ATCR_EN_SHIFT (0U)
16313/*! EN - Enable Timer
16314 * 0b0..The timer stops at the current value.
16315 * 0b1..The timer starts incrementing.
16316 */
16317#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
16318#define ENET_ATCR_OFFEN_MASK (0x4U)
16319#define ENET_ATCR_OFFEN_SHIFT (2U)
16320/*! OFFEN - Enable One-Shot Offset Event
16321 * 0b0..Disable.
16322 * 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field.
16323 */
16324#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
16325#define ENET_ATCR_OFFRST_MASK (0x8U)
16326#define ENET_ATCR_OFFRST_SHIFT (3U)
16327/*! OFFRST - Reset Timer On Offset Event
16328 * 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
16329 * 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
16330 */
16331#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
16332#define ENET_ATCR_PEREN_MASK (0x10U)
16333#define ENET_ATCR_PEREN_SHIFT (4U)
16334/*! PEREN - Enable Periodical Event
16335 * 0b0..Disable.
16336 * 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details.
16337 */
16338#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
16339#define ENET_ATCR_PINPER_MASK (0x80U)
16340#define ENET_ATCR_PINPER_SHIFT (7U)
16341/*! PINPER
16342 * 0b0..Disable.
16343 * 0b1..Enable.
16344 */
16345#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
16346#define ENET_ATCR_RESTART_MASK (0x200U)
16347#define ENET_ATCR_RESTART_SHIFT (9U)
16348#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
16349#define ENET_ATCR_CAPTURE_MASK (0x800U)
16350#define ENET_ATCR_CAPTURE_SHIFT (11U)
16351/*! CAPTURE - Capture Timer Value
16352 * 0b0..No effect.
16353 * 0b1..The current time is captured and can be read from the ATVR register.
16354 */
16355#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
16356#define ENET_ATCR_SLAVE_MASK (0x2000U)
16357#define ENET_ATCR_SLAVE_SHIFT (13U)
16358/*! SLAVE - Enable Timer Slave Mode
16359 * 0b0..The timer is active and all configuration fields in this register are relevant.
16360 * 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
16361 */
16362#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
16363/*! @} */
16364
16365/*! @name ATVR - Timer Value Register */
16366/*! @{ */
16367#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
16368#define ENET_ATVR_ATIME_SHIFT (0U)
16369#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
16370/*! @} */
16371
16372/*! @name ATOFF - Timer Offset Register */
16373/*! @{ */
16374#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
16375#define ENET_ATOFF_OFFSET_SHIFT (0U)
16376#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
16377/*! @} */
16378
16379/*! @name ATPER - Timer Period Register */
16380/*! @{ */
16381#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
16382#define ENET_ATPER_PERIOD_SHIFT (0U)
16383#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
16384/*! @} */
16385
16386/*! @name ATCOR - Timer Correction Register */
16387/*! @{ */
16388#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
16389#define ENET_ATCOR_COR_SHIFT (0U)
16390#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
16391/*! @} */
16392
16393/*! @name ATINC - Time-Stamping Clock Period Register */
16394/*! @{ */
16395#define ENET_ATINC_INC_MASK (0x7FU)
16396#define ENET_ATINC_INC_SHIFT (0U)
16397#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
16398#define ENET_ATINC_INC_CORR_MASK (0x7F00U)
16399#define ENET_ATINC_INC_CORR_SHIFT (8U)
16400#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
16401/*! @} */
16402
16403/*! @name ATSTMP - Timestamp of Last Transmitted Frame */
16404/*! @{ */
16405#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
16406#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
16407#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
16408/*! @} */
16409
16410/*! @name TGSR - Timer Global Status Register */
16411/*! @{ */
16412#define ENET_TGSR_TF0_MASK (0x1U)
16413#define ENET_TGSR_TF0_SHIFT (0U)
16414/*! TF0 - Copy Of Timer Flag For Channel 0
16415 * 0b0..Timer Flag for Channel 0 is clear
16416 * 0b1..Timer Flag for Channel 0 is set
16417 */
16418#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
16419#define ENET_TGSR_TF1_MASK (0x2U)
16420#define ENET_TGSR_TF1_SHIFT (1U)
16421/*! TF1 - Copy Of Timer Flag For Channel 1
16422 * 0b0..Timer Flag for Channel 1 is clear
16423 * 0b1..Timer Flag for Channel 1 is set
16424 */
16425#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
16426#define ENET_TGSR_TF2_MASK (0x4U)
16427#define ENET_TGSR_TF2_SHIFT (2U)
16428/*! TF2 - Copy Of Timer Flag For Channel 2
16429 * 0b0..Timer Flag for Channel 2 is clear
16430 * 0b1..Timer Flag for Channel 2 is set
16431 */
16432#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
16433#define ENET_TGSR_TF3_MASK (0x8U)
16434#define ENET_TGSR_TF3_SHIFT (3U)
16435/*! TF3 - Copy Of Timer Flag For Channel 3
16436 * 0b0..Timer Flag for Channel 3 is clear
16437 * 0b1..Timer Flag for Channel 3 is set
16438 */
16439#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
16440/*! @} */
16441
16442/*! @name TCSR - Timer Control Status Register */
16443/*! @{ */
16444#define ENET_TCSR_TDRE_MASK (0x1U)
16445#define ENET_TCSR_TDRE_SHIFT (0U)
16446/*! TDRE - Timer DMA Request Enable
16447 * 0b0..DMA request is disabled
16448 * 0b1..DMA request is enabled
16449 */
16450#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
16451#define ENET_TCSR_TMODE_MASK (0x3CU)
16452#define ENET_TCSR_TMODE_SHIFT (2U)
16453/*! TMODE - Timer Mode
16454 * 0b0000..Timer Channel is disabled.
16455 * 0b0001..Timer Channel is configured for Input Capture on rising edge.
16456 * 0b0010..Timer Channel is configured for Input Capture on falling edge.
16457 * 0b0011..Timer Channel is configured for Input Capture on both edges.
16458 * 0b0100..Timer Channel is configured for Output Compare - software only.
16459 * 0b0101..Timer Channel is configured for Output Compare - toggle output on compare.
16460 * 0b0110..Timer Channel is configured for Output Compare - clear output on compare.
16461 * 0b0111..Timer Channel is configured for Output Compare - set output on compare.
16462 * 0b1000..Reserved
16463 * 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
16464 * 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
16465 * 0b110x..Reserved
16466 * 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle.
16467 * 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle.
16468 */
16469#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
16470#define ENET_TCSR_TIE_MASK (0x40U)
16471#define ENET_TCSR_TIE_SHIFT (6U)
16472/*! TIE - Timer Interrupt Enable
16473 * 0b0..Interrupt is disabled
16474 * 0b1..Interrupt is enabled
16475 */
16476#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
16477#define ENET_TCSR_TF_MASK (0x80U)
16478#define ENET_TCSR_TF_SHIFT (7U)
16479/*! TF - Timer Flag
16480 * 0b0..Input Capture or Output Compare has not occurred.
16481 * 0b1..Input Capture or Output Compare has occurred.
16482 */
16483#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
16484/*! @} */
16485
16486/* The count of ENET_TCSR */
16487#define ENET_TCSR_COUNT (4U)
16488
16489/*! @name TCCR - Timer Compare Capture Register */
16490/*! @{ */
16491#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
16492#define ENET_TCCR_TCC_SHIFT (0U)
16493#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
16494/*! @} */
16495
16496/* The count of ENET_TCCR */
16497#define ENET_TCCR_COUNT (4U)
16498
16499
16500/*!
16501 * @}
16502 */ /* end of group ENET_Register_Masks */
16503
16504
16505/* ENET - Peripheral instance base addresses */
16506/** Peripheral ENET base address */
16507#define ENET_BASE (0x30BE0000u)
16508/** Peripheral ENET base pointer */
16509#define ENET ((ENET_Type *)ENET_BASE)
16510/** Array initializer of ENET peripheral base addresses */
16511#define ENET_BASE_ADDRS { ENET_BASE }
16512/** Array initializer of ENET peripheral base pointers */
16513#define ENET_BASE_PTRS { ENET }
16514/** Interrupt vectors for the ENET peripheral type */
16515#define ENET_Transmit_IRQS { ENET_IRQn }
16516#define ENET_Receive_IRQS { ENET_IRQn }
16517#define ENET_Error_IRQS { ENET_IRQn }
16518#define ENET_1588_Timer_IRQS { ENET_IRQn }
16519/* ENET Buffer Descriptor and Buffer Address Alignment. */
16520#define ENET_BUFF_ALIGNMENT (64U)
16521
16522
16523/*!
16524 * @}
16525 */ /* end of group ENET_Peripheral_Access_Layer */
16526
16527
16528/* ----------------------------------------------------------------------------
16529 -- GPC Peripheral Access Layer
16530 ---------------------------------------------------------------------------- */
16531
16532/*!
16533 * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer
16534 * @{
16535 */
16536
16537/** GPC - Register Layout Typedef */
16538typedef struct {
16539 __IO uint32_t LPCR_A53_BSC; /**< Basic Low power control register of A53 platform, offset: 0x0 */
16540 __IO uint32_t LPCR_A53_AD; /**< Advanced Low power control register of A53 platform, offset: 0x4 */
16541 __IO uint32_t LPCR_M4; /**< Low power control register of CPU1, offset: 0x8 */
16542 uint8_t RESERVED_0[8];
16543 __IO uint32_t SLPCR; /**< System low power control register, offset: 0x14 */
16544 __IO uint32_t MST_CPU_MAPPING; /**< MASTER LPM Handshake, offset: 0x18 */
16545 uint8_t RESERVED_1[4];
16546 __IO uint32_t MLPCR; /**< Memory low power control register, offset: 0x20 */
16547 __IO uint32_t PGC_ACK_SEL_A53; /**< PGC acknowledge signal selection of A53 platform, offset: 0x24 */
16548 __IO uint32_t PGC_ACK_SEL_M4; /**< PGC acknowledge signal selection of M4 platform, offset: 0x28 */
16549 __IO uint32_t MISC; /**< GPC Miscellaneous register, offset: 0x2C */
16550 __IO uint32_t IMR_CORE0_A53[4]; /**< IRQ masking register 1 of A53 core0..IRQ masking register 4 of A53 core0, array offset: 0x30, array step: 0x4 */
16551 __IO uint32_t IMR_CORE1_A53[4]; /**< IRQ masking register 1 of A53 core1..IRQ masking register 4 of A53 core1, array offset: 0x40, array step: 0x4 */
16552 __IO uint32_t IMR_M4[4]; /**< IRQ masking register 1 of M4..IRQ masking register 4 of M4, array offset: 0x50, array step: 0x4 */
16553 uint8_t RESERVED_2[16];
16554 __I uint32_t ISR_A53[4]; /**< IRQ status register 1 of A53..IRQ status register 4 of A53, array offset: 0x70, array step: 0x4 */
16555 __I uint32_t ISR_M4[4]; /**< IRQ status register 1 of M4..IRQ status register 4 of M4, array offset: 0x80, array step: 0x4 */
16556 uint8_t RESERVED_3[32];
16557 __IO uint32_t SLT0_CFG; /**< Slot configure register for A53 core, offset: 0xB0 */
16558 __IO uint32_t SLT1_CFG; /**< Slot configure register for A53 core, offset: 0xB4 */
16559 __IO uint32_t SLT2_CFG; /**< Slot configure register for A53 core, offset: 0xB8 */
16560 __IO uint32_t SLT3_CFG; /**< Slot configure register for A53 core, offset: 0xBC */
16561 __IO uint32_t SLT4_CFG; /**< Slot configure register for A53 core, offset: 0xC0 */
16562 __IO uint32_t SLT5_CFG; /**< Slot configure register for A53 core, offset: 0xC4 */
16563 __IO uint32_t SLT6_CFG; /**< Slot configure register for A53 core, offset: 0xC8 */
16564 __IO uint32_t SLT7_CFG; /**< Slot configure register for A53 core, offset: 0xCC */
16565 __IO uint32_t SLT8_CFG; /**< Slot configure register for A53 core, offset: 0xD0 */
16566 __IO uint32_t SLT9_CFG; /**< Slot configure register for A53 core, offset: 0xD4 */
16567 __IO uint32_t SLT10_CFG; /**< Slot configure register for A53 core, offset: 0xD8 */
16568 __IO uint32_t SLT11_CFG; /**< Slot configure register for A53 core, offset: 0xDC */
16569 __IO uint32_t SLT12_CFG; /**< Slot configure register for A53 core, offset: 0xE0 */
16570 __IO uint32_t SLT13_CFG; /**< Slot configure register for A53 core, offset: 0xE4 */
16571 __IO uint32_t SLT14_CFG; /**< Slot configure register for A53 core, offset: 0xE8 */
16572 __IO uint32_t PGC_CPU_0_1_MAPPING; /**< PGC CPU mapping, offset: 0xEC */
16573 __IO uint32_t CPU_PGC_SW_PUP_REQ; /**< CPU PGC software power up trigger, offset: 0xF0 */
16574 __IO uint32_t MIX_PGC_SW_PUP_REQ; /**< MIX PGC software power up trigger, offset: 0xF4 */
16575 __IO uint32_t PU_PGC_SW_PUP_REQ; /**< PU PGC software up trigger, offset: 0xF8 */
16576 __IO uint32_t CPU_PGC_SW_PDN_REQ; /**< CPU PGC software down trigger, offset: 0xFC */
16577 __IO uint32_t MIX_PGC_SW_PDN_REQ; /**< MIX PGC software power down trigger, offset: 0x100 */
16578 __IO uint32_t PU_PGC_SW_PDN_REQ; /**< PU PGC software down trigger, offset: 0x104 */
16579 __IO uint32_t LPCR_A53_BSC2; /**< Basic Low power control register of A53 platform, offset: 0x108 */
16580 uint8_t RESERVED_4[36];
16581 __I uint32_t CPU_PGC_PUP_STATUS1; /**< CPU PGC software up trigger status1, offset: 0x130 */
16582 __I uint32_t A53_MIX_PGC_PUP_STATUS[3]; /**< A53 MIX software up trigger status register, array offset: 0x134, array step: 0x4 */
16583 __I uint32_t M4_MIX_PGC_PUP_STATUS[3]; /**< M4 MIX PGC software up trigger status register, array offset: 0x140, array step: 0x4 */
16584 __I uint32_t A53_PU_PGC_PUP_STATUS[3]; /**< A53 PU software up trigger status register, array offset: 0x14C, array step: 0x4 */
16585 __I uint32_t M4_PU_PGC_PUP_STATUS[3]; /**< M4 PU PGC software up trigger status register, array offset: 0x158, array step: 0x4 */
16586 uint8_t RESERVED_5[12];
16587 __IO uint32_t CPU_PGC_PDN_STATUS1; /**< CPU PGC software dn trigger status1, offset: 0x170 */
16588 __I uint32_t A53_MIX_PGC_PDN_STATUS[3]; /**< A53 MIX software down trigger status register, array offset: 0x174, array step: 0x4 */
16589 __I uint32_t M4_MIX_PGC_PDN_STATUS[3]; /**< M4 MIX PGC software power down trigger status register, array offset: 0x180, array step: 0x4 */
16590 __I uint32_t A53_PU_PGC_PDN_STATUS[3]; /**< A53 PU PGC software down trigger status, array offset: 0x18C, array step: 0x4 */
16591 __I uint32_t M4_PU_PGC_PDN_STATUS[3]; /**< M4 PU PGC software down trigger status, array offset: 0x198, array step: 0x4 */
16592 uint8_t RESERVED_6[12];
16593 __IO uint32_t A53_MIX_PDN_FLG; /**< A53 MIX PDN FLG, offset: 0x1B0 */
16594 __IO uint32_t A53_PU_PDN_FLG; /**< A53 PU PDN FLG, offset: 0x1B4 */
16595 __IO uint32_t M4_MIX_PDN_FLG; /**< M4 MIX PDN FLG, offset: 0x1B8 */
16596 __IO uint32_t M4_PU_PDN_FLG; /**< M4 PU PDN FLG, offset: 0x1BC */
16597 __IO uint32_t IMR_CORE2_A53[4]; /**< IRQ masking register 1 of A53 core2..IRQ masking register 4 of A53 core2, array offset: 0x1C0, array step: 0x4 */
16598 __IO uint32_t IMR_CORE3_A53[4]; /**< IRQ masking register 1 of A53 core3..IRQ masking register 4 of A53 core3, array offset: 0x1D0, array step: 0x4 */
16599 __IO uint32_t ACK_SEL_A53_PU; /**< PGC acknowledge signal selection of A53 platform for PUs, offset: 0x1E0 */
16600 __IO uint32_t ACK_SEL_M4_PU; /**< PGC acknowledge signal selection of M4 platform for PUs, offset: 0x1E4 */
16601 __IO uint32_t SLT15_CFG; /**< Slot configure register for A53 core, offset: 0x1E8 */
16602 __IO uint32_t SLT16_CFG; /**< Slot configure register for A53 core, offset: 0x1EC */
16603 __IO uint32_t SLT17_CFG; /**< Slot configure register for A53 core, offset: 0x1F0 */
16604 __IO uint32_t SLT18_CFG; /**< Slot configure register for A53 core, offset: 0x1F4 */
16605 __IO uint32_t SLT19_CFG; /**< Slot configure register for A53 core, offset: 0x1F8 */
16606 __IO uint32_t PU_PWRHSK; /**< Power handshake register, offset: 0x1FC */
16607 __IO uint32_t SLT_CFG_PU[20]; /**< Slot configure register for PUs, array offset: 0x200, array step: 0x4 */
16608} GPC_Type;
16609
16610/* ----------------------------------------------------------------------------
16611 -- GPC Register Masks
16612 ---------------------------------------------------------------------------- */
16613
16614/*!
16615 * @addtogroup GPC_Register_Masks GPC Register Masks
16616 * @{
16617 */
16618
16619/*! @name LPCR_A53_BSC - Basic Low power control register of A53 platform */
16620/*! @{ */
16621#define GPC_LPCR_A53_BSC_LPM0_MASK (0x3U)
16622#define GPC_LPCR_A53_BSC_LPM0_SHIFT (0U)
16623/*! LPM0
16624 * 0b00..Remain in RUN mode
16625 * 0b01..Transfer to WAIT mode
16626 * 0b10..Transfer to STOP mode
16627 * 0b11..Reserved
16628 */
16629#define GPC_LPCR_A53_BSC_LPM0(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_LPM0_SHIFT)) & GPC_LPCR_A53_BSC_LPM0_MASK)
16630#define GPC_LPCR_A53_BSC_LPM1_MASK (0xCU)
16631#define GPC_LPCR_A53_BSC_LPM1_SHIFT (2U)
16632/*! LPM1
16633 * 0b00..Remain in RUN mode
16634 * 0b01..Transfer to WAIT mode
16635 * 0b10..Transfer to STOP mode
16636 * 0b11..Reserved
16637 */
16638#define GPC_LPCR_A53_BSC_LPM1(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_LPM1_SHIFT)) & GPC_LPCR_A53_BSC_LPM1_MASK)
16639#define GPC_LPCR_A53_BSC_MST_LPM_HSK_MASK_MASK (0x40U)
16640#define GPC_LPCR_A53_BSC_MST_LPM_HSK_MASK_SHIFT (6U)
16641/*! MST_LPM_HSK_MASK - MASTER0 LPM handshake mask
16642 * 0b0..enable MASTER0 LPM handshake, wait ACK from MASTER0
16643 * 0b1..disable MASKTER0 LPM handshake, mask ACK from MASTER0
16644 */
16645#define GPC_LPCR_A53_BSC_MST_LPM_HSK_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST_LPM_HSK_MASK_SHIFT)) & GPC_LPCR_A53_BSC_MST_LPM_HSK_MASK_MASK)
16646#define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_MASK (0x4000U)
16647#define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_SHIFT (14U)
16648/*! CPU_CLK_ON_LPM
16649 * 0b0..A53 clock disabled on wait/stop mode
16650 * 0b1..A53 clock enabled on wait/stop mode
16651 */
16652#define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_SHIFT)) & GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_MASK)
16653#define GPC_LPCR_A53_BSC_MASK_CORE0_WFI_MASK (0x10000U)
16654#define GPC_LPCR_A53_BSC_MASK_CORE0_WFI_SHIFT (16U)
16655/*! MASK_CORE0_WFI
16656 * 0b0..WFI for CORE0 is not masked
16657 * 0b1..WFI for CORE0 is masked
16658 */
16659#define GPC_LPCR_A53_BSC_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE0_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE0_WFI_MASK)
16660#define GPC_LPCR_A53_BSC_MASK_CORE1_WFI_MASK (0x20000U)
16661#define GPC_LPCR_A53_BSC_MASK_CORE1_WFI_SHIFT (17U)
16662/*! MASK_CORE1_WFI
16663 * 0b0..WFI for CORE1 is not masked
16664 * 0b1..WFI for CORE1 is masked
16665 */
16666#define GPC_LPCR_A53_BSC_MASK_CORE1_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE1_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE1_WFI_MASK)
16667#define GPC_LPCR_A53_BSC_MASK_CORE2_WFI_MASK (0x40000U)
16668#define GPC_LPCR_A53_BSC_MASK_CORE2_WFI_SHIFT (18U)
16669/*! MASK_CORE2_WFI
16670 * 0b0..WFI for CORE2 is not masked
16671 * 0b1..WFI for CORE2 is masked
16672 */
16673#define GPC_LPCR_A53_BSC_MASK_CORE2_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE2_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE2_WFI_MASK)
16674#define GPC_LPCR_A53_BSC_MASK_CORE3_WFI_MASK (0x80000U)
16675#define GPC_LPCR_A53_BSC_MASK_CORE3_WFI_SHIFT (19U)
16676/*! MASK_CORE3_WFI
16677 * 0b0..WFI for CORE3 is not masked
16678 * 0b1..WFI for CORE3 is masked
16679 */
16680#define GPC_LPCR_A53_BSC_MASK_CORE3_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE3_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE3_WFI_MASK)
16681#define GPC_LPCR_A53_BSC_IRQ_SRC_C2_MASK (0x400000U)
16682#define GPC_LPCR_A53_BSC_IRQ_SRC_C2_SHIFT (22U)
16683/*! IRQ_SRC_C2
16684 * 0b0..core2 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53 Platform for more specific information.
16685 * 0b1..core2 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down during low power mode when this bit is set to 1'b1.
16686 */
16687#define GPC_LPCR_A53_BSC_IRQ_SRC_C2(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C2_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C2_MASK)
16688#define GPC_LPCR_A53_BSC_IRQ_SRC_C3_MASK (0x800000U)
16689#define GPC_LPCR_A53_BSC_IRQ_SRC_C3_SHIFT (23U)
16690/*! IRQ_SRC_C3
16691 * 0b0..core3 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53 Platform for more specific information.
16692 * 0b1..core3 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down during low power mode when this bit is set to 1'b1.
16693 */
16694#define GPC_LPCR_A53_BSC_IRQ_SRC_C3(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C3_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C3_MASK)
16695#define GPC_LPCR_A53_BSC_MASK_SCU_WFI_MASK (0x1000000U)
16696#define GPC_LPCR_A53_BSC_MASK_SCU_WFI_SHIFT (24U)
16697/*! MASK_SCU_WFI
16698 * 0b0..WFI for SCU is not masked
16699 * 0b1..WFI for SCU is masked
16700 */
16701#define GPC_LPCR_A53_BSC_MASK_SCU_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_SCU_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_SCU_WFI_MASK)
16702#define GPC_LPCR_A53_BSC_MASK_L2CC_WFI_MASK (0x4000000U)
16703#define GPC_LPCR_A53_BSC_MASK_L2CC_WFI_SHIFT (26U)
16704/*! MASK_L2CC_WFI
16705 * 0b0..WFI for L2 cache controller is not masked
16706 * 0b1..WFI for L2 cache controller is masked
16707 */
16708#define GPC_LPCR_A53_BSC_MASK_L2CC_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_L2CC_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_L2CC_WFI_MASK)
16709#define GPC_LPCR_A53_BSC_IRQ_SRC_C0_MASK (0x10000000U)
16710#define GPC_LPCR_A53_BSC_IRQ_SRC_C0_SHIFT (28U)
16711/*! IRQ_SRC_C0
16712 * 0b0..core0 wakeup source from external INT[127:0], masked by IMR0 refer to "Power up process for A53 platform" for more specific information
16713 * 0b1..core0 wakeup source from GIC(nFIQ[0]/nIRQ[0] ), SCU should not be power down during low power mode when this bit is set to 1'b1
16714 */
16715#define GPC_LPCR_A53_BSC_IRQ_SRC_C0(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C0_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C0_MASK)
16716#define GPC_LPCR_A53_BSC_IRQ_SRC_C1_MASK (0x20000000U)
16717#define GPC_LPCR_A53_BSC_IRQ_SRC_C1_SHIFT (29U)
16718/*! IRQ_SRC_C1
16719 * 0b0..core1 wakeup source from external INT[127:0], masked by IMR1 refer to "Power up process for A53 platform" for more specific information
16720 * 0b1..core1 wakeup source from GIC(nFIQ[1]/nIRQ[1] ), SCU should not be power down during low power mode when this bit is set to 1'b1
16721 */
16722#define GPC_LPCR_A53_BSC_IRQ_SRC_C1(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C1_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C1_MASK)
16723#define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_MASK (0x40000000U)
16724#define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_SHIFT (30U)
16725/*! IRQ_SRC_A53_WUP
16726 * 0b0..LPM wakeup source be "OR" result of LPCR_A53_BSC[IRQ_SRC_C0]/LPCR_A53_BSC[IRQ_SRC_C1]/LPCR_A53_BSC[IRQ_SRC_C2]/LPCR_A53_BSC[IRQ_SRC_C3] setting
16727 * 0b1..LPM wakeup source from external INT[127:0], masked by IMR0
16728 */
16729#define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_MASK)
16730#define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_MASK (0x80000000U)
16731#define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_SHIFT (31U)
16732/*! MASK_DSM_TRIGGER
16733 * 0b0..DSM trigger of A53 platform will not be masked
16734 * 0b1..DSM trigger of A53 platform will be masked
16735 */
16736#define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_SHIFT)) & GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_MASK)
16737/*! @} */
16738
16739/*! @name LPCR_A53_AD - Advanced Low power control register of A53 platform */
16740/*! @{ */
16741#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_MASK (0x1U)
16742#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_SHIFT (0U)
16743/*! EN_C0_WFI_PDN
16744 * 0b0..CORE0 will not be power down with WFI request
16745 * 0b1..CORE0 will be power down with WFI request
16746 */
16747#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_WFI_PDN_MASK)
16748#define GPC_LPCR_A53_AD_EN_C0_PDN_MASK (0x2U)
16749#define GPC_LPCR_A53_AD_EN_C0_PDN_SHIFT (1U)
16750/*! EN_C0_PDN
16751 * 0b0..CORE0 will not be power down with low power mode request
16752 * 0b1..CORE0 will be power down with low power mode request
16753 */
16754#define GPC_LPCR_A53_AD_EN_C0_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_PDN_MASK)
16755#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_MASK (0x4U)
16756#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_SHIFT (2U)
16757/*! EN_C1_WFI_PDN
16758 * 0b0..CORE1 will not be power down with WFI request
16759 * 0b1..CORE1 will be power down with WFI request
16760 */
16761#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_WFI_PDN_MASK)
16762#define GPC_LPCR_A53_AD_EN_C1_PDN_MASK (0x8U)
16763#define GPC_LPCR_A53_AD_EN_C1_PDN_SHIFT (3U)
16764/*! EN_C1_PDN
16765 * 0b0..CORE1 will not be power down with low power mode request
16766 * 0b1..CORE1 will be power down with low power mode request
16767 */
16768#define GPC_LPCR_A53_AD_EN_C1_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_PDN_MASK)
16769#define GPC_LPCR_A53_AD_EN_PLAT_PDN_MASK (0x10U)
16770#define GPC_LPCR_A53_AD_EN_PLAT_PDN_SHIFT (4U)
16771/*! EN_PLAT_PDN
16772 * 0b0..SCU and L2 cache RAM will not be power down with low power mode request
16773 * 0b1..SCU and L2 cache RAM will be power down with low power mode request
16774 */
16775#define GPC_LPCR_A53_AD_EN_PLAT_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_PLAT_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_PLAT_PDN_MASK)
16776#define GPC_LPCR_A53_AD_EN_L2_WFI_PDN_MASK (0x20U)
16777#define GPC_LPCR_A53_AD_EN_L2_WFI_PDN_SHIFT (5U)
16778/*! EN_L2_WFI_PDN
16779 * 0b0..SCU and L2 will not be power down with WFI request
16780 * 0b1..SCU and L2 will be power down with WFI request (default)
16781 */
16782#define GPC_LPCR_A53_AD_EN_L2_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_L2_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_L2_WFI_PDN_MASK)
16783#define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_MASK (0x100U)
16784#define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_SHIFT (8U)
16785/*! EN_C0_IRQ_PUP
16786 * 0b0..CORE0 will power up with IRQ request
16787 * 0b1..CORE0 will not power up with IRQ request
16788 */
16789#define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_MASK)
16790#define GPC_LPCR_A53_AD_EN_C0_PUP_MASK (0x200U)
16791#define GPC_LPCR_A53_AD_EN_C0_PUP_SHIFT (9U)
16792/*! EN_C0_PUP
16793 * 0b0..CORE0 will power up with low power mode request
16794 * 0b1..CORE0 will not power up with low power mode request
16795 */
16796#define GPC_LPCR_A53_AD_EN_C0_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_PUP_MASK)
16797#define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_MASK (0x400U)
16798#define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_SHIFT (10U)
16799/*! EN_C1_IRQ_PUP
16800 * 0b0..CORE1 will power up with IRQ request
16801 * 0b1..CORE1 will not power up with IRQ request
16802 */
16803#define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_MASK)
16804#define GPC_LPCR_A53_AD_EN_C1_PUP_MASK (0x800U)
16805#define GPC_LPCR_A53_AD_EN_C1_PUP_SHIFT (11U)
16806/*! EN_C1_PUP
16807 * 0b0..CORE1 will not power up with low power mode request (only used wake up from CPU01_OFF mode)
16808 * 0b1..CORE1 will power up with low power mode request
16809 */
16810#define GPC_LPCR_A53_AD_EN_C1_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_PUP_MASK)
16811#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_MASK (0x10000U)
16812#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_SHIFT (16U)
16813/*! EN_C2_WFI_PDN
16814 * 0b0..CORE2 will not be power down with WFI request
16815 * 0b1..CORE2 will be power down with WFI request
16816 */
16817#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_WFI_PDN_MASK)
16818#define GPC_LPCR_A53_AD_EN_C2_PDN_MASK (0x20000U)
16819#define GPC_LPCR_A53_AD_EN_C2_PDN_SHIFT (17U)
16820/*! EN_C2_PDN
16821 * 0b0..CORE2 will not be power down with low power mode request
16822 * 0b1..CORE2 will be power down with low power mode request
16823 */
16824#define GPC_LPCR_A53_AD_EN_C2_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_PDN_MASK)
16825#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_MASK (0x40000U)
16826#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_SHIFT (18U)
16827/*! EN_C3_WFI_PDN
16828 * 0b0..CORE3 will not be power down with WFI request
16829 * 0b1..CORE3 will be power down with WFI request
16830 */
16831#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_WFI_PDN_MASK)
16832#define GPC_LPCR_A53_AD_EN_C3_PDN_MASK (0x80000U)
16833#define GPC_LPCR_A53_AD_EN_C3_PDN_SHIFT (19U)
16834/*! EN_C3_PDN
16835 * 0b0..CORE3 will not be power down with low power mode request
16836 * 0b1..CORE3 will be power down with low power mode request
16837 */
16838#define GPC_LPCR_A53_AD_EN_C3_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_PDN_MASK)
16839#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_MASK (0x100000U)
16840#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_SHIFT (20U)
16841/*! EN_C0_WFI_PDN_DIS
16842 * 0b0..Disnable WFI power down core0
16843 * 0b1..Enable WFI power down core0
16844 */
16845#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_MASK)
16846#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_MASK (0x200000U)
16847#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_SHIFT (21U)
16848/*! EN_C1_WFI_PDN_DIS
16849 * 0b0..Disnable WFI power down core1
16850 * 0b1..Enable WFI power down core1
16851 */
16852#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_MASK)
16853#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_MASK (0x400000U)
16854#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_SHIFT (22U)
16855/*! EN_C2_WFI_PDN_DIS
16856 * 0b0..Disnable WFI power down core2
16857 * 0b1..Enable WFI power down core2
16858 */
16859#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_MASK)
16860#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_MASK (0x800000U)
16861#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_SHIFT (23U)
16862/*! EN_C3_WFI_PDN_DIS
16863 * 0b0..Disnable WFI power down core3
16864 * 0b1..Enable WFI power down core3
16865 */
16866#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_MASK)
16867#define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_MASK (0x1000000U)
16868#define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_SHIFT (24U)
16869/*! EN_C2_IRQ_PUP
16870 * 0b0..CORE2 will power up with IRQ request
16871 * 0b1..CORE2 will not power up with IRQ request
16872 */
16873#define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_MASK)
16874#define GPC_LPCR_A53_AD_EN_C2_PUP_MASK (0x2000000U)
16875#define GPC_LPCR_A53_AD_EN_C2_PUP_SHIFT (25U)
16876/*! EN_C2_PUP
16877 * 0b0..CORE2 will power up with lower power mode request
16878 * 0b1..CORE2 will not power up with low power mode request (only used wake up from CPU_OFF)
16879 */
16880#define GPC_LPCR_A53_AD_EN_C2_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_PUP_MASK)
16881#define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_MASK (0x4000000U)
16882#define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_SHIFT (26U)
16883/*! EN_C3_IRQ_PUP
16884 * 0b0..CORE3 will power up with IRQ request
16885 * 0b1..CORE3 will not power up with IRQ request
16886 */
16887#define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_MASK)
16888#define GPC_LPCR_A53_AD_EN_C3_PUP_MASK (0x8000000U)
16889#define GPC_LPCR_A53_AD_EN_C3_PUP_SHIFT (27U)
16890/*! EN_C3_PUP
16891 * 0b0..CORE3 will power up with lower power mode request
16892 * 0b1..CORE3 will not power up with low power mode request (only used wake up from CPU_OFF)
16893 */
16894#define GPC_LPCR_A53_AD_EN_C3_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_PUP_MASK)
16895#define GPC_LPCR_A53_AD_L2PGE_MASK (0x80000000U)
16896#define GPC_LPCR_A53_AD_L2PGE_SHIFT (31U)
16897/*! L2PGE
16898 * 0b0..L2 cache RAM will power down with SCU power domain in A53 platform (used for ALL_OFF mode)
16899 * 0b1..L2 cache RAM will not power down with SCU power domain in A53 platform (used for ALL_OFF mode)
16900 */
16901#define GPC_LPCR_A53_AD_L2PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_L2PGE_SHIFT)) & GPC_LPCR_A53_AD_L2PGE_MASK)
16902/*! @} */
16903
16904/*! @name LPCR_M4 - Low power control register of CPU1 */
16905/*! @{ */
16906#define GPC_LPCR_M4_LPM0_MASK (0x3U)
16907#define GPC_LPCR_M4_LPM0_SHIFT (0U)
16908/*! LPM0
16909 * 0b00..Remain in RUN mode
16910 * 0b01..Transfer to WAIT mode
16911 * 0b10..Transfer to STOP mode
16912 * 0b11..Reserved
16913 */
16914#define GPC_LPCR_M4_LPM0(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M4_LPM0_SHIFT)) & GPC_LPCR_M4_LPM0_MASK)
16915#define GPC_LPCR_M4_EN_M4_PDN_MASK (0x4U)
16916#define GPC_LPCR_M4_EN_M4_PDN_SHIFT (2U)
16917#define GPC_LPCR_M4_EN_M4_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M4_EN_M4_PDN_SHIFT)) & GPC_LPCR_M4_EN_M4_PDN_MASK)
16918#define GPC_LPCR_M4_EN_M4_PUP_MASK (0x8U)
16919#define GPC_LPCR_M4_EN_M4_PUP_SHIFT (3U)
16920#define GPC_LPCR_M4_EN_M4_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M4_EN_M4_PUP_SHIFT)) & GPC_LPCR_M4_EN_M4_PUP_MASK)
16921#define GPC_LPCR_M4_CPU_CLK_ON_LPM_MASK (0x4000U)
16922#define GPC_LPCR_M4_CPU_CLK_ON_LPM_SHIFT (14U)
16923/*! CPU_CLK_ON_LPM
16924 * 0b0..M4 clock disabled on wait/stop mode.
16925 * 0b1..M4 clock enabled on wait/stop mode.
16926 */
16927#define GPC_LPCR_M4_CPU_CLK_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M4_CPU_CLK_ON_LPM_SHIFT)) & GPC_LPCR_M4_CPU_CLK_ON_LPM_MASK)
16928#define GPC_LPCR_M4_MASK_M4_WFI_MASK (0x10000U)
16929#define GPC_LPCR_M4_MASK_M4_WFI_SHIFT (16U)
16930/*! MASK_M4_WFI
16931 * 0b0..WFI for M4 is not masked
16932 * 0b1..WFI for M4 is masked
16933 */
16934#define GPC_LPCR_M4_MASK_M4_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M4_MASK_M4_WFI_SHIFT)) & GPC_LPCR_M4_MASK_M4_WFI_MASK)
16935#define GPC_LPCR_M4_MASK_DSM_TRIGGER_MASK (0x80000000U)
16936#define GPC_LPCR_M4_MASK_DSM_TRIGGER_SHIFT (31U)
16937/*! MASK_DSM_TRIGGER
16938 * 0b0..DSM trigger of M4 platform will not be masked
16939 * 0b1..DSM trigger of M4 platform will be masked
16940 */
16941#define GPC_LPCR_M4_MASK_DSM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M4_MASK_DSM_TRIGGER_SHIFT)) & GPC_LPCR_M4_MASK_DSM_TRIGGER_MASK)
16942/*! @} */
16943
16944/*! @name SLPCR - System low power control register */
16945/*! @{ */
16946#define GPC_SLPCR_BYPASS_PMIC_READY_MASK (0x1U)
16947#define GPC_SLPCR_BYPASS_PMIC_READY_SHIFT (0U)
16948/*! BYPASS_PMIC_READY
16949 * 0b0..Don't bypass the PMIC_READY signal - GPC will wait for its assertion during exit of low power mode if standby voltage was enabled
16950 * 0b1..Bypass the PMIC_READY signal - GPC will wait for its assertion during exit of low power mode if standby voltage was enabled
16951 */
16952#define GPC_SLPCR_BYPASS_PMIC_READY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_BYPASS_PMIC_READY_SHIFT)) & GPC_SLPCR_BYPASS_PMIC_READY_MASK)
16953#define GPC_SLPCR_SBYOS_MASK (0x2U)
16954#define GPC_SLPCR_SBYOS_SHIFT (1U)
16955/*! SBYOS
16956 * 0b0..On chip oscillator will not be powered down, after next entrance to DSM.
16957 * 0b1..On chip oscillator will be powered down, after next entrance to DSM. When returning from DSM, external oscillator will be enabled again, on chip oscillator will return to oscillator mode , and after oscnt count GPC will continue with the exit from DSM process.
16958 */
16959#define GPC_SLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_SBYOS_SHIFT)) & GPC_SLPCR_SBYOS_MASK)
16960#define GPC_SLPCR_VSTBY_MASK (0x4U)
16961#define GPC_SLPCR_VSTBY_SHIFT (2U)
16962/*! VSTBY
16963 * 0b0..Voltage will not be changed to standby voltage after next entrance to stop mode. (PMIC_STBY_REQ will remain negated - '0')
16964 * 0b1..Voltage will be changed to standby voltage after next entrance to stop mode.
16965 */
16966#define GPC_SLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_VSTBY_SHIFT)) & GPC_SLPCR_VSTBY_MASK)
16967#define GPC_SLPCR_STBY_COUNT_MASK (0x38U)
16968#define GPC_SLPCR_STBY_COUNT_SHIFT (3U)
16969/*! STBY_COUNT
16970 * 0b000..GPC will wait 4 ckil clock cycles
16971 * 0b001..GPC will wait 8 ckil clock cycles
16972 * 0b010..GPC will wait 16 ckil clock cycles
16973 * 0b011..GPC will wait 32 ckil clock cycles
16974 * 0b100..GPC will wait 64 ckil clock cycles
16975 * 0b101..GPC will wait 128 ckil clock cycles
16976 * 0b110..GPC will wait 256 ckil clock cycles
16977 * 0b111..GPC will wait 512 ckil clock cycles
16978 */
16979#define GPC_SLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_STBY_COUNT_SHIFT)) & GPC_SLPCR_STBY_COUNT_MASK)
16980#define GPC_SLPCR_COSC_PWRDOWN_MASK (0x40U)
16981#define GPC_SLPCR_COSC_PWRDOWN_SHIFT (6U)
16982/*! COSC_PWRDOWN
16983 * 0b0..On-chip oscillator will not be powered down, i.e. cosc_pwrdown = 0
16984 * 0b1..On-chip oscillator will be powered down, i.e. cosc_pwrdown = 1
16985 */
16986#define GPC_SLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_COSC_PWRDOWN_SHIFT)) & GPC_SLPCR_COSC_PWRDOWN_MASK)
16987#define GPC_SLPCR_COSC_EN_MASK (0x80U)
16988#define GPC_SLPCR_COSC_EN_SHIFT (7U)
16989/*! COSC_EN
16990 * 0b0..Disable on-chip oscillator
16991 * 0b1..Enable on-chip oscillator
16992 */
16993#define GPC_SLPCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_COSC_EN_SHIFT)) & GPC_SLPCR_COSC_EN_MASK)
16994#define GPC_SLPCR_OSCCNT_MASK (0xFF00U)
16995#define GPC_SLPCR_OSCCNT_SHIFT (8U)
16996/*! OSCCNT
16997 * 0b00000000..count 1 ckil
16998 * 0b11111111..count 256 ckils
16999 */
17000#define GPC_SLPCR_OSCCNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_OSCCNT_SHIFT)) & GPC_SLPCR_OSCCNT_MASK)
17001#define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_MASK (0x10000U)
17002#define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_SHIFT (16U)
17003#define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_SHIFT)) & GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_MASK)
17004#define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_MASK (0x20000U)
17005#define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_SHIFT (17U)
17006#define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_SHIFT)) & GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_MASK)
17007#define GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE_MASK (0x40000U)
17008#define GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE_SHIFT (18U)
17009#define GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE_SHIFT)) & GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE_MASK)
17010#define GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE_MASK (0x80000U)
17011#define GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE_SHIFT (19U)
17012#define GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE_SHIFT)) & GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE_MASK)
17013#define GPC_SLPCR_DISABLE_A53_IS_DSM_MASK (0x800000U)
17014#define GPC_SLPCR_DISABLE_A53_IS_DSM_SHIFT (23U)
17015/*! DISABLE_A53_IS_DSM
17016 * 0b0..Enable A53 isolation signal in DSM
17017 * 0b1..Disable A53 isolation signal in DSM
17018 */
17019#define GPC_SLPCR_DISABLE_A53_IS_DSM(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_DISABLE_A53_IS_DSM_SHIFT)) & GPC_SLPCR_DISABLE_A53_IS_DSM_MASK)
17020#define GPC_SLPCR_REG_BYPASS_COUNT_MASK (0x3F000000U)
17021#define GPC_SLPCR_REG_BYPASS_COUNT_SHIFT (24U)
17022/*! REG_BYPASS_COUNT
17023 * 0b000000..no delay
17024 * 0b000001..1 CKIL clock period delay
17025 * 0b111111..63 CKIL clock period delay
17026 */
17027#define GPC_SLPCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_REG_BYPASS_COUNT_SHIFT)) & GPC_SLPCR_REG_BYPASS_COUNT_MASK)
17028#define GPC_SLPCR_RBC_EN_MASK (0x40000000U)
17029#define GPC_SLPCR_RBC_EN_SHIFT (30U)
17030/*! RBC_EN
17031 * 0b0..REG_BYPASS_COUNTER disabled
17032 * 0b1..REG_BYPASS_COUNTER enabled
17033 */
17034#define GPC_SLPCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_RBC_EN_SHIFT)) & GPC_SLPCR_RBC_EN_MASK)
17035#define GPC_SLPCR_EN_DSM_MASK (0x80000000U)
17036#define GPC_SLPCR_EN_DSM_SHIFT (31U)
17037/*! EN_DSM
17038 * 0b0..DSM disabled
17039 * 0b1..DSM enabled
17040 */
17041#define GPC_SLPCR_EN_DSM(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_DSM_SHIFT)) & GPC_SLPCR_EN_DSM_MASK)
17042/*! @} */
17043
17044/*! @name MST_CPU_MAPPING - MASTER LPM Handshake */
17045/*! @{ */
17046#define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_MASK (0x1U)
17047#define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_SHIFT (0U)
17048/*! MST0_CPU_MAPPING - MASTER0 CPU Mapping
17049 * 0b0..GPC will not send out power off requirement
17050 * 0b1..GPC will send out power off requirement
17051 */
17052#define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_SHIFT)) & GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_MASK)
17053#define GPC_MST_CPU_MAPPING_MEMLP_RET_PGEN_MASK (0xFFFFFFFEU)
17054#define GPC_MST_CPU_MAPPING_MEMLP_RET_PGEN_SHIFT (1U)
17055#define GPC_MST_CPU_MAPPING_MEMLP_RET_PGEN(x) (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MEMLP_RET_PGEN_SHIFT)) & GPC_MST_CPU_MAPPING_MEMLP_RET_PGEN_MASK)
17056/*! @} */
17057
17058/*! @name MLPCR - Memory low power control register */
17059/*! @{ */
17060#define GPC_MLPCR_MEMLP_CTL_DIS_MASK (0x1U)
17061#define GPC_MLPCR_MEMLP_CTL_DIS_SHIFT (0U)
17062/*! MEMLP_CTL_DIS
17063 * 0b0..Enable RAM low power control
17064 * 0b1..Disable RAM low power control
17065 */
17066#define GPC_MLPCR_MEMLP_CTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_CTL_DIS_SHIFT)) & GPC_MLPCR_MEMLP_CTL_DIS_MASK)
17067#define GPC_MLPCR_MEMLP_RET_SEL_MASK (0x2U)
17068#define GPC_MLPCR_MEMLP_RET_SEL_SHIFT (1U)
17069/*! MEMLP_RET_SEL
17070 * 0b0..retention mode 2
17071 * 0b1..retention mode 1
17072 */
17073#define GPC_MLPCR_MEMLP_RET_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_RET_SEL_SHIFT)) & GPC_MLPCR_MEMLP_RET_SEL_MASK)
17074#define GPC_MLPCR_ROMLP_PDN_DIS_MASK (0x4U)
17075#define GPC_MLPCR_ROMLP_PDN_DIS_SHIFT (2U)
17076/*! ROMLP_PDN_DIS
17077 * 0b0..Enable ROM shut down control(should also enable RAM low power control);
17078 * 0b1..Disable ROM shut down control
17079 */
17080#define GPC_MLPCR_ROMLP_PDN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_ROMLP_PDN_DIS_SHIFT)) & GPC_MLPCR_ROMLP_PDN_DIS_MASK)
17081#define GPC_MLPCR_MEMLP_ENT_CNT_MASK (0xFF00U)
17082#define GPC_MLPCR_MEMLP_ENT_CNT_SHIFT (8U)
17083#define GPC_MLPCR_MEMLP_ENT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_ENT_CNT_SHIFT)) & GPC_MLPCR_MEMLP_ENT_CNT_MASK)
17084#define GPC_MLPCR_MEM_EXT_CNT_MASK (0xFF0000U)
17085#define GPC_MLPCR_MEM_EXT_CNT_SHIFT (16U)
17086#define GPC_MLPCR_MEM_EXT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEM_EXT_CNT_SHIFT)) & GPC_MLPCR_MEM_EXT_CNT_MASK)
17087#define GPC_MLPCR_MEMLP_RET_PGEN_MASK (0xFF000000U)
17088#define GPC_MLPCR_MEMLP_RET_PGEN_SHIFT (24U)
17089#define GPC_MLPCR_MEMLP_RET_PGEN(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_RET_PGEN_SHIFT)) & GPC_MLPCR_MEMLP_RET_PGEN_MASK)
17090/*! @} */
17091
17092/*! @name PGC_ACK_SEL_A53 - PGC acknowledge signal selection of A53 platform */
17093/*! @{ */
17094#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_MASK (0x1U)
17095#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_SHIFT (0U)
17096#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_MASK)
17097#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_MASK (0x2U)
17098#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_SHIFT (1U)
17099#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_MASK)
17100#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_MASK (0x4U)
17101#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_SHIFT (2U)
17102#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_MASK)
17103#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_MASK (0x2000U)
17104#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_SHIFT (13U)
17105#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_MASK)
17106#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_MASK (0x4000U)
17107#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_SHIFT (14U)
17108#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_MASK)
17109#define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_MASK (0x8000U)
17110#define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_SHIFT (15U)
17111#define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_MASK)
17112#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_MASK (0x10000U)
17113#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_SHIFT (16U)
17114#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_MASK)
17115#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_MASK (0x20000U)
17116#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_SHIFT (17U)
17117#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_MASK)
17118#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_MASK (0x40000U)
17119#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_SHIFT (18U)
17120#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_MASK)
17121#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_MASK (0x20000000U)
17122#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_SHIFT (29U)
17123#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_MASK)
17124#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_MASK (0x40000000U)
17125#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_SHIFT (30U)
17126#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_MASK)
17127#define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_MASK (0x80000000U)
17128#define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_SHIFT (31U)
17129#define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_MASK)
17130/*! @} */
17131
17132/*! @name PGC_ACK_SEL_M4 - PGC acknowledge signal selection of M4 platform */
17133/*! @{ */
17134#define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK_MASK (0x1U)
17135#define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK_SHIFT (0U)
17136#define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK_MASK)
17137#define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK_MASK (0x8000U)
17138#define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK_SHIFT (15U)
17139#define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK_MASK)
17140#define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK_MASK (0x10000U)
17141#define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK_SHIFT (16U)
17142#define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK_MASK)
17143#define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK_MASK (0x80000000U)
17144#define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK_SHIFT (31U)
17145#define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK_MASK)
17146/*! @} */
17147
17148/*! @name MISC - GPC Miscellaneous register */
17149/*! @{ */
17150#define GPC_MISC_M4_SLEEP_HOLD_REQ_B_MASK (0x1U)
17151#define GPC_MISC_M4_SLEEP_HOLD_REQ_B_SHIFT (0U)
17152/*! M4_SLEEP_HOLD_REQ_B
17153 * 0b0..Hold M4 platform in sleep mode. This bit is a software control bit to M4 platform.
17154 * 0b1..Don't hold M4 platform in sleep mode.
17155 */
17156#define GPC_MISC_M4_SLEEP_HOLD_REQ_B(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M4_SLEEP_HOLD_REQ_B_SHIFT)) & GPC_MISC_M4_SLEEP_HOLD_REQ_B_MASK)
17157#define GPC_MISC_A53_SLEEP_HOLD_REQ_B_MASK (0x2U)
17158#define GPC_MISC_A53_SLEEP_HOLD_REQ_B_SHIFT (1U)
17159/*! A53_SLEEP_HOLD_REQ_B
17160 * 0b0..Hold A53 platform in sleep mode. This bit is a software control bit to A53 platform.
17161 * 0b1..Don't hold A53 platform in sleep mode.
17162 */
17163#define GPC_MISC_A53_SLEEP_HOLD_REQ_B(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_A53_SLEEP_HOLD_REQ_B_SHIFT)) & GPC_MISC_A53_SLEEP_HOLD_REQ_B_MASK)
17164#define GPC_MISC_GPC_IRQ_MASK_MASK (0x20U)
17165#define GPC_MISC_GPC_IRQ_MASK_SHIFT (5U)
17166/*! GPC_IRQ_MASK
17167 * 0b0..Not masked
17168 * 0b1..Interrupt / event is masked
17169 */
17170#define GPC_MISC_GPC_IRQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_GPC_IRQ_MASK_SHIFT)) & GPC_MISC_GPC_IRQ_MASK_MASK)
17171#define GPC_MISC_M4_PDN_REQ_MASK_MASK (0x100U)
17172#define GPC_MISC_M4_PDN_REQ_MASK_SHIFT (8U)
17173/*! M4_PDN_REQ_MASK
17174 * 0b0..M4 power down request to virtual M4 PGC will be masked.
17175 * 0b1..M4 power down request to virtual M4 PGC will not be masked. Set this bit to 1'b1 when M4 virtual PGC is used.
17176 */
17177#define GPC_MISC_M4_PDN_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M4_PDN_REQ_MASK_SHIFT)) & GPC_MISC_M4_PDN_REQ_MASK_MASK)
17178#define GPC_MISC_A53_BYPASS_PUP_MASK_MASK (0x1000000U)
17179#define GPC_MISC_A53_BYPASS_PUP_MASK_SHIFT (24U)
17180#define GPC_MISC_A53_BYPASS_PUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_A53_BYPASS_PUP_MASK_SHIFT)) & GPC_MISC_A53_BYPASS_PUP_MASK_MASK)
17181#define GPC_MISC_M4_BYPASS_PUP_MASK_MASK (0x2000000U)
17182#define GPC_MISC_M4_BYPASS_PUP_MASK_SHIFT (25U)
17183#define GPC_MISC_M4_BYPASS_PUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M4_BYPASS_PUP_MASK_SHIFT)) & GPC_MISC_M4_BYPASS_PUP_MASK_MASK)
17184/*! @} */
17185
17186/*! @name IMR_CORE0_A53 - IRQ masking register 1 of A53 core0..IRQ masking register 4 of A53 core0 */
17187/*! @{ */
17188#define GPC_IMR_CORE0_A53_IMR1_CORE0_A53_MASK (0xFFFFFFFFU)
17189#define GPC_IMR_CORE0_A53_IMR1_CORE0_A53_SHIFT (0U)
17190/*! IMR1_CORE0_A53
17191 * 0b00000000000000000000000000000000..IRQ not masked
17192 * 0b00000000000000000000000000000001..IRQ masked
17193 */
17194#define GPC_IMR_CORE0_A53_IMR1_CORE0_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR1_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR1_CORE0_A53_MASK)
17195#define GPC_IMR_CORE0_A53_IMR2_CORE0_A53_MASK (0xFFFFFFFFU)
17196#define GPC_IMR_CORE0_A53_IMR2_CORE0_A53_SHIFT (0U)
17197/*! IMR2_CORE0_A53
17198 * 0b00000000000000000000000000000000..IRQ not masked
17199 * 0b00000000000000000000000000000001..IRQ masked
17200 */
17201#define GPC_IMR_CORE0_A53_IMR2_CORE0_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR2_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR2_CORE0_A53_MASK)
17202#define GPC_IMR_CORE0_A53_IMR3_CORE0_A53_MASK (0xFFFFFFFFU)
17203#define GPC_IMR_CORE0_A53_IMR3_CORE0_A53_SHIFT (0U)
17204/*! IMR3_CORE0_A53
17205 * 0b00000000000000000000000000000000..IRQ not masked
17206 * 0b00000000000000000000000000000001..IRQ masked
17207 */
17208#define GPC_IMR_CORE0_A53_IMR3_CORE0_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR3_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR3_CORE0_A53_MASK)
17209#define GPC_IMR_CORE0_A53_IMR4_CORE0_A53_MASK (0xFFFFFFFFU)
17210#define GPC_IMR_CORE0_A53_IMR4_CORE0_A53_SHIFT (0U)
17211/*! IMR4_CORE0_A53
17212 * 0b00000000000000000000000000000000..IRQ not masked
17213 * 0b00000000000000000000000000000001..IRQ masked
17214 */
17215#define GPC_IMR_CORE0_A53_IMR4_CORE0_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR4_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR4_CORE0_A53_MASK)
17216/*! @} */
17217
17218/* The count of GPC_IMR_CORE0_A53 */
17219#define GPC_IMR_CORE0_A53_COUNT (4U)
17220
17221/*! @name IMR_CORE1_A53 - IRQ masking register 1 of A53 core1..IRQ masking register 4 of A53 core1 */
17222/*! @{ */
17223#define GPC_IMR_CORE1_A53_IMR1_CORE1_A53_MASK (0xFFFFFFFFU)
17224#define GPC_IMR_CORE1_A53_IMR1_CORE1_A53_SHIFT (0U)
17225/*! IMR1_CORE1_A53
17226 * 0b00000000000000000000000000000000..IRQ not masked
17227 * 0b00000000000000000000000000000001..IRQ masked
17228 */
17229#define GPC_IMR_CORE1_A53_IMR1_CORE1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR1_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR1_CORE1_A53_MASK)
17230#define GPC_IMR_CORE1_A53_IMR2_CORE1_A53_MASK (0xFFFFFFFFU)
17231#define GPC_IMR_CORE1_A53_IMR2_CORE1_A53_SHIFT (0U)
17232/*! IMR2_CORE1_A53
17233 * 0b00000000000000000000000000000000..IRQ not masked
17234 * 0b00000000000000000000000000000001..IRQ masked
17235 */
17236#define GPC_IMR_CORE1_A53_IMR2_CORE1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR2_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR2_CORE1_A53_MASK)
17237#define GPC_IMR_CORE1_A53_IMR3_CORE1_A53_MASK (0xFFFFFFFFU)
17238#define GPC_IMR_CORE1_A53_IMR3_CORE1_A53_SHIFT (0U)
17239/*! IMR3_CORE1_A53
17240 * 0b00000000000000000000000000000000..IRQ not masked
17241 * 0b00000000000000000000000000000001..IRQ masked
17242 */
17243#define GPC_IMR_CORE1_A53_IMR3_CORE1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR3_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR3_CORE1_A53_MASK)
17244#define GPC_IMR_CORE1_A53_IMR4_CORE1_A53_MASK (0xFFFFFFFFU)
17245#define GPC_IMR_CORE1_A53_IMR4_CORE1_A53_SHIFT (0U)
17246/*! IMR4_CORE1_A53
17247 * 0b00000000000000000000000000000000..IRQ not masked
17248 * 0b00000000000000000000000000000001..IRQ masked
17249 */
17250#define GPC_IMR_CORE1_A53_IMR4_CORE1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR4_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR4_CORE1_A53_MASK)
17251/*! @} */
17252
17253/* The count of GPC_IMR_CORE1_A53 */
17254#define GPC_IMR_CORE1_A53_COUNT (4U)
17255
17256/*! @name IMR_M4 - IRQ masking register 1 of M4..IRQ masking register 4 of M4 */
17257/*! @{ */
17258#define GPC_IMR_M4_IMR1_M4_MASK (0xFFFFFFFFU)
17259#define GPC_IMR_M4_IMR1_M4_SHIFT (0U)
17260/*! IMR1_M4
17261 * 0b00000000000000000000000000000000..IRQ not masked
17262 * 0b00000000000000000000000000000001..IRQ masked
17263 */
17264#define GPC_IMR_M4_IMR1_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M4_IMR1_M4_SHIFT)) & GPC_IMR_M4_IMR1_M4_MASK)
17265#define GPC_IMR_M4_IMR2_M4_MASK (0xFFFFFFFFU)
17266#define GPC_IMR_M4_IMR2_M4_SHIFT (0U)
17267/*! IMR2_M4
17268 * 0b00000000000000000000000000000000..IRQ not masked
17269 * 0b00000000000000000000000000000001..IRQ masked
17270 */
17271#define GPC_IMR_M4_IMR2_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M4_IMR2_M4_SHIFT)) & GPC_IMR_M4_IMR2_M4_MASK)
17272#define GPC_IMR_M4_IMR3_M4_MASK (0xFFFFFFFFU)
17273#define GPC_IMR_M4_IMR3_M4_SHIFT (0U)
17274/*! IMR3_M4
17275 * 0b00000000000000000000000000000000..IRQ not masked
17276 * 0b00000000000000000000000000000001..IRQ masked
17277 */
17278#define GPC_IMR_M4_IMR3_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M4_IMR3_M4_SHIFT)) & GPC_IMR_M4_IMR3_M4_MASK)
17279#define GPC_IMR_M4_IMR4_M4_MASK (0xFFFFFFFFU)
17280#define GPC_IMR_M4_IMR4_M4_SHIFT (0U)
17281/*! IMR4_M4
17282 * 0b00000000000000000000000000000000..IRQ not masked
17283 * 0b00000000000000000000000000000001..IRQ masked
17284 */
17285#define GPC_IMR_M4_IMR4_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M4_IMR4_M4_SHIFT)) & GPC_IMR_M4_IMR4_M4_MASK)
17286/*! @} */
17287
17288/* The count of GPC_IMR_M4 */
17289#define GPC_IMR_M4_COUNT (4U)
17290
17291/*! @name ISR_A53 - IRQ status register 1 of A53..IRQ status register 4 of A53 */
17292/*! @{ */
17293#define GPC_ISR_A53_ISR1_A53_MASK (0xFFFFFFFFU)
17294#define GPC_ISR_A53_ISR1_A53_SHIFT (0U)
17295#define GPC_ISR_A53_ISR1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR1_A53_SHIFT)) & GPC_ISR_A53_ISR1_A53_MASK)
17296#define GPC_ISR_A53_ISR2_A53_MASK (0xFFFFFFFFU)
17297#define GPC_ISR_A53_ISR2_A53_SHIFT (0U)
17298#define GPC_ISR_A53_ISR2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR2_A53_SHIFT)) & GPC_ISR_A53_ISR2_A53_MASK)
17299#define GPC_ISR_A53_ISR3_A53_MASK (0xFFFFFFFFU)
17300#define GPC_ISR_A53_ISR3_A53_SHIFT (0U)
17301#define GPC_ISR_A53_ISR3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR3_A53_SHIFT)) & GPC_ISR_A53_ISR3_A53_MASK)
17302#define GPC_ISR_A53_ISR4_A53_MASK (0xFFFFFFFFU)
17303#define GPC_ISR_A53_ISR4_A53_SHIFT (0U)
17304#define GPC_ISR_A53_ISR4_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR4_A53_SHIFT)) & GPC_ISR_A53_ISR4_A53_MASK)
17305/*! @} */
17306
17307/* The count of GPC_ISR_A53 */
17308#define GPC_ISR_A53_COUNT (4U)
17309
17310/*! @name ISR_M4 - IRQ status register 1 of M4..IRQ status register 4 of M4 */
17311/*! @{ */
17312#define GPC_ISR_M4_ISR1_M4_MASK (0xFFFFFFFFU)
17313#define GPC_ISR_M4_ISR1_M4_SHIFT (0U)
17314#define GPC_ISR_M4_ISR1_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M4_ISR1_M4_SHIFT)) & GPC_ISR_M4_ISR1_M4_MASK)
17315#define GPC_ISR_M4_ISR2_M4_MASK (0xFFFFFFFFU)
17316#define GPC_ISR_M4_ISR2_M4_SHIFT (0U)
17317#define GPC_ISR_M4_ISR2_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M4_ISR2_M4_SHIFT)) & GPC_ISR_M4_ISR2_M4_MASK)
17318#define GPC_ISR_M4_ISR3_M4_MASK (0xFFFFFFFFU)
17319#define GPC_ISR_M4_ISR3_M4_SHIFT (0U)
17320#define GPC_ISR_M4_ISR3_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M4_ISR3_M4_SHIFT)) & GPC_ISR_M4_ISR3_M4_MASK)
17321#define GPC_ISR_M4_ISR4_M4_MASK (0xFFFFFFFFU)
17322#define GPC_ISR_M4_ISR4_M4_SHIFT (0U)
17323#define GPC_ISR_M4_ISR4_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M4_ISR4_M4_SHIFT)) & GPC_ISR_M4_ISR4_M4_MASK)
17324/*! @} */
17325
17326/* The count of GPC_ISR_M4 */
17327#define GPC_ISR_M4_COUNT (4U)
17328
17329/*! @name SLT0_CFG - Slot configure register for A53 core */
17330/*! @{ */
17331#define GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
17332#define GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
17333#define GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
17334#define GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
17335#define GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
17336#define GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
17337#define GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
17338#define GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
17339#define GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
17340#define GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
17341#define GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
17342#define GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
17343#define GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
17344#define GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
17345#define GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
17346#define GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
17347#define GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
17348#define GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
17349#define GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
17350#define GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
17351#define GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
17352#define GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
17353#define GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
17354#define GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
17355#define GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
17356#define GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
17357#define GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_MASK)
17358#define GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
17359#define GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
17360#define GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_MASK)
17361/*! @} */
17362
17363/*! @name SLT1_CFG - Slot configure register for A53 core */
17364/*! @{ */
17365#define GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
17366#define GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
17367#define GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
17368#define GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
17369#define GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
17370#define GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
17371#define GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
17372#define GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
17373#define GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
17374#define GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
17375#define GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
17376#define GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
17377#define GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
17378#define GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
17379#define GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
17380#define GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
17381#define GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
17382#define GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
17383#define GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
17384#define GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
17385#define GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
17386#define GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
17387#define GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
17388#define GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
17389#define GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
17390#define GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
17391#define GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_MASK)
17392#define GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
17393#define GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
17394#define GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_MASK)
17395/*! @} */
17396
17397/*! @name SLT2_CFG - Slot configure register for A53 core */
17398/*! @{ */
17399#define GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
17400#define GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
17401#define GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
17402#define GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
17403#define GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
17404#define GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
17405#define GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
17406#define GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
17407#define GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
17408#define GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
17409#define GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
17410#define GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
17411#define GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
17412#define GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
17413#define GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
17414#define GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
17415#define GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
17416#define GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
17417#define GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
17418#define GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
17419#define GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
17420#define GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
17421#define GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
17422#define GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
17423#define GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
17424#define GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
17425#define GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_MASK)
17426#define GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
17427#define GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
17428#define GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_MASK)
17429/*! @} */
17430
17431/*! @name SLT3_CFG - Slot configure register for A53 core */
17432/*! @{ */
17433#define GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
17434#define GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
17435#define GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
17436#define GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
17437#define GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
17438#define GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
17439#define GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
17440#define GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
17441#define GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
17442#define GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
17443#define GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
17444#define GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
17445#define GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
17446#define GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
17447#define GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
17448#define GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
17449#define GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
17450#define GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
17451#define GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
17452#define GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
17453#define GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
17454#define GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
17455#define GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
17456#define GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
17457#define GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
17458#define GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
17459#define GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_MASK)
17460#define GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
17461#define GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
17462#define GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_MASK)
17463/*! @} */
17464
17465/*! @name SLT4_CFG - Slot configure register for A53 core */
17466/*! @{ */
17467#define GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
17468#define GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
17469#define GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
17470#define GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
17471#define GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
17472#define GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
17473#define GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
17474#define GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
17475#define GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
17476#define GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
17477#define GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
17478#define GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
17479#define GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
17480#define GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
17481#define GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
17482#define GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
17483#define GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
17484#define GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
17485#define GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
17486#define GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
17487#define GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
17488#define GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
17489#define GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
17490#define GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
17491#define GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
17492#define GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
17493#define GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_MASK)
17494#define GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
17495#define GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
17496#define GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_MASK)
17497/*! @} */
17498
17499/*! @name SLT5_CFG - Slot configure register for A53 core */
17500/*! @{ */
17501#define GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
17502#define GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
17503#define GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
17504#define GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
17505#define GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
17506#define GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
17507#define GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
17508#define GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
17509#define GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
17510#define GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
17511#define GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
17512#define GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
17513#define GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
17514#define GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
17515#define GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
17516#define GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
17517#define GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
17518#define GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
17519#define GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
17520#define GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
17521#define GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
17522#define GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
17523#define GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
17524#define GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
17525#define GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
17526#define GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
17527#define GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_MASK)
17528#define GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
17529#define GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
17530#define GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_MASK)
17531/*! @} */
17532
17533/*! @name SLT6_CFG - Slot configure register for A53 core */
17534/*! @{ */
17535#define GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
17536#define GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
17537#define GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
17538#define GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
17539#define GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
17540#define GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
17541#define GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
17542#define GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
17543#define GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
17544#define GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
17545#define GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
17546#define GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
17547#define GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
17548#define GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
17549#define GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
17550#define GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
17551#define GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
17552#define GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
17553#define GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
17554#define GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
17555#define GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
17556#define GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
17557#define GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
17558#define GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
17559#define GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
17560#define GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
17561#define GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_MASK)
17562#define GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
17563#define GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
17564#define GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_MASK)
17565/*! @} */
17566
17567/*! @name SLT7_CFG - Slot configure register for A53 core */
17568/*! @{ */
17569#define GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
17570#define GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
17571#define GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
17572#define GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
17573#define GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
17574#define GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
17575#define GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
17576#define GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
17577#define GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
17578#define GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
17579#define GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
17580#define GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
17581#define GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
17582#define GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
17583#define GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
17584#define GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
17585#define GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
17586#define GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
17587#define GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
17588#define GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
17589#define GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
17590#define GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
17591#define GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
17592#define GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
17593#define GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
17594#define GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
17595#define GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_MASK)
17596#define GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
17597#define GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
17598#define GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_MASK)
17599/*! @} */
17600
17601/*! @name SLT8_CFG - Slot configure register for A53 core */
17602/*! @{ */
17603#define GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
17604#define GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
17605#define GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
17606#define GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
17607#define GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
17608#define GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
17609#define GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
17610#define GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
17611#define GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
17612#define GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
17613#define GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
17614#define GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
17615#define GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
17616#define GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
17617#define GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
17618#define GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
17619#define GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
17620#define GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
17621#define GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
17622#define GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
17623#define GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
17624#define GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
17625#define GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
17626#define GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
17627#define GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
17628#define GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
17629#define GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_MASK)
17630#define GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
17631#define GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
17632#define GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_MASK)
17633/*! @} */
17634
17635/*! @name SLT9_CFG - Slot configure register for A53 core */
17636/*! @{ */
17637#define GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
17638#define GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
17639#define GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
17640#define GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
17641#define GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
17642#define GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
17643#define GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
17644#define GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
17645#define GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
17646#define GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
17647#define GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
17648#define GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
17649#define GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
17650#define GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
17651#define GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
17652#define GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
17653#define GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
17654#define GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
17655#define GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
17656#define GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
17657#define GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
17658#define GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
17659#define GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
17660#define GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
17661#define GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
17662#define GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
17663#define GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_MASK)
17664#define GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
17665#define GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
17666#define GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_MASK)
17667/*! @} */
17668
17669/*! @name SLT10_CFG - Slot configure register for A53 core */
17670/*! @{ */
17671#define GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
17672#define GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
17673#define GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
17674#define GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
17675#define GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
17676#define GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
17677#define GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
17678#define GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
17679#define GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
17680#define GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
17681#define GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
17682#define GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
17683#define GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
17684#define GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
17685#define GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
17686#define GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
17687#define GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
17688#define GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
17689#define GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
17690#define GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
17691#define GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
17692#define GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
17693#define GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
17694#define GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
17695#define GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
17696#define GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
17697#define GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_MASK)
17698#define GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
17699#define GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
17700#define GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_MASK)
17701/*! @} */
17702
17703/*! @name SLT11_CFG - Slot configure register for A53 core */
17704/*! @{ */
17705#define GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
17706#define GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
17707#define GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
17708#define GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
17709#define GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
17710#define GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
17711#define GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
17712#define GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
17713#define GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
17714#define GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
17715#define GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
17716#define GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
17717#define GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
17718#define GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
17719#define GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
17720#define GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
17721#define GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
17722#define GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
17723#define GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
17724#define GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
17725#define GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
17726#define GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
17727#define GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
17728#define GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
17729#define GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
17730#define GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
17731#define GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_MASK)
17732#define GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
17733#define GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
17734#define GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_MASK)
17735/*! @} */
17736
17737/*! @name SLT12_CFG - Slot configure register for A53 core */
17738/*! @{ */
17739#define GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
17740#define GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
17741#define GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
17742#define GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
17743#define GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
17744#define GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
17745#define GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
17746#define GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
17747#define GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
17748#define GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
17749#define GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
17750#define GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
17751#define GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
17752#define GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
17753#define GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
17754#define GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
17755#define GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
17756#define GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
17757#define GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
17758#define GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
17759#define GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
17760#define GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
17761#define GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
17762#define GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
17763#define GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
17764#define GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
17765#define GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_MASK)
17766#define GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
17767#define GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
17768#define GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_MASK)
17769/*! @} */
17770
17771/*! @name SLT13_CFG - Slot configure register for A53 core */
17772/*! @{ */
17773#define GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
17774#define GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
17775#define GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
17776#define GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
17777#define GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
17778#define GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
17779#define GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
17780#define GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
17781#define GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
17782#define GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
17783#define GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
17784#define GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
17785#define GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
17786#define GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
17787#define GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
17788#define GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
17789#define GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
17790#define GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
17791#define GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
17792#define GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
17793#define GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
17794#define GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
17795#define GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
17796#define GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
17797#define GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
17798#define GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
17799#define GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_MASK)
17800#define GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
17801#define GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
17802#define GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_MASK)
17803/*! @} */
17804
17805/*! @name SLT14_CFG - Slot configure register for A53 core */
17806/*! @{ */
17807#define GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
17808#define GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
17809#define GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
17810#define GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
17811#define GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
17812#define GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
17813#define GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
17814#define GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
17815#define GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
17816#define GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
17817#define GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
17818#define GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
17819#define GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
17820#define GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
17821#define GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
17822#define GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
17823#define GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
17824#define GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
17825#define GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
17826#define GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
17827#define GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
17828#define GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
17829#define GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
17830#define GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
17831#define GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
17832#define GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
17833#define GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_MASK)
17834#define GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
17835#define GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
17836#define GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_MASK)
17837/*! @} */
17838
17839/*! @name PGC_CPU_0_1_MAPPING - PGC CPU mapping */
17840/*! @{ */
17841#define GPC_PGC_CPU_0_1_MAPPING_MF_A53_DOMAIN_MASK (0x1U)
17842#define GPC_PGC_CPU_0_1_MAPPING_MF_A53_DOMAIN_SHIFT (0U)
17843#define GPC_PGC_CPU_0_1_MAPPING_MF_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MF_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MF_A53_DOMAIN_MASK)
17844#define GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_MASK (0x4U)
17845#define GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_SHIFT (2U)
17846#define GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_MASK)
17847#define GPC_PGC_CPU_0_1_MAPPING_PCIE_A53_DOMAIN_MASK (0x8U)
17848#define GPC_PGC_CPU_0_1_MAPPING_PCIE_A53_DOMAIN_SHIFT (3U)
17849#define GPC_PGC_CPU_0_1_MAPPING_PCIE_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_PCIE_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_PCIE_A53_DOMAIN_MASK)
17850#define GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_MASK (0x10U)
17851#define GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_SHIFT (4U)
17852#define GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_MASK)
17853#define GPC_PGC_CPU_0_1_MAPPING_OTG2_A53_DOMAIN_MASK (0x20U)
17854#define GPC_PGC_CPU_0_1_MAPPING_OTG2_A53_DOMAIN_SHIFT (5U)
17855#define GPC_PGC_CPU_0_1_MAPPING_OTG2_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_OTG2_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_OTG2_A53_DOMAIN_MASK)
17856#define GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_MASK (0x80U)
17857#define GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_SHIFT (7U)
17858#define GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_MASK)
17859#define GPC_PGC_CPU_0_1_MAPPING_DDR2_A53_DOMAIN_MASK (0x100U)
17860#define GPC_PGC_CPU_0_1_MAPPING_DDR2_A53_DOMAIN_SHIFT (8U)
17861#define GPC_PGC_CPU_0_1_MAPPING_DDR2_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DDR2_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_DDR2_A53_DOMAIN_MASK)
17862#define GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_MASK (0x200U)
17863#define GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_SHIFT (9U)
17864#define GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_MASK)
17865#define GPC_PGC_CPU_0_1_MAPPING_VPU_A53_DOMAIN_MASK (0x400U)
17866#define GPC_PGC_CPU_0_1_MAPPING_VPU_A53_DOMAIN_SHIFT (10U)
17867#define GPC_PGC_CPU_0_1_MAPPING_VPU_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_VPU_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_VPU_A53_DOMAIN_MASK)
17868#define GPC_PGC_CPU_0_1_MAPPING_HDMI_A53_DOMAIN_MASK (0x800U)
17869#define GPC_PGC_CPU_0_1_MAPPING_HDMI_A53_DOMAIN_SHIFT (11U)
17870#define GPC_PGC_CPU_0_1_MAPPING_HDMI_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_HDMI_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_HDMI_A53_DOMAIN_MASK)
17871#define GPC_PGC_CPU_0_1_MAPPING_DISP_A53_DOMAIN_MASK (0x1000U)
17872#define GPC_PGC_CPU_0_1_MAPPING_DISP_A53_DOMAIN_SHIFT (12U)
17873#define GPC_PGC_CPU_0_1_MAPPING_DISP_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DISP_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_DISP_A53_DOMAIN_MASK)
17874#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_A53_DOMAIN_MASK (0x2000U)
17875#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_A53_DOMAIN_SHIFT (13U)
17876#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_A53_DOMAIN_MASK)
17877#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_A53_DOMAIN_MASK (0x4000U)
17878#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_A53_DOMAIN_SHIFT (14U)
17879#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_A53_DOMAIN_MASK)
17880#define GPC_PGC_CPU_0_1_MAPPING_PCIE2_A53_DOMAIN_MASK (0x8000U)
17881#define GPC_PGC_CPU_0_1_MAPPING_PCIE2_A53_DOMAIN_SHIFT (15U)
17882#define GPC_PGC_CPU_0_1_MAPPING_PCIE2_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_PCIE2_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_PCIE2_A53_DOMAIN_MASK)
17883#define GPC_PGC_CPU_0_1_MAPPING_MF_M4_DOMAIN_MASK (0x10000U)
17884#define GPC_PGC_CPU_0_1_MAPPING_MF_M4_DOMAIN_SHIFT (16U)
17885#define GPC_PGC_CPU_0_1_MAPPING_MF_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MF_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MF_M4_DOMAIN_MASK)
17886#define GPC_PGC_CPU_0_1_MAPPING_MIPI_M4_DOMAIN_MASK (0x40000U)
17887#define GPC_PGC_CPU_0_1_MAPPING_MIPI_M4_DOMAIN_SHIFT (18U)
17888#define GPC_PGC_CPU_0_1_MAPPING_MIPI_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MIPI_M4_DOMAIN_MASK)
17889#define GPC_PGC_CPU_0_1_MAPPING_PCIE_M4_DOMAIN_MASK (0x80000U)
17890#define GPC_PGC_CPU_0_1_MAPPING_PCIE_M4_DOMAIN_SHIFT (19U)
17891#define GPC_PGC_CPU_0_1_MAPPING_PCIE_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_PCIE_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_PCIE_M4_DOMAIN_MASK)
17892#define GPC_PGC_CPU_0_1_MAPPING_OTG1_M4_DOMAIN_MASK (0x100000U)
17893#define GPC_PGC_CPU_0_1_MAPPING_OTG1_M4_DOMAIN_SHIFT (20U)
17894#define GPC_PGC_CPU_0_1_MAPPING_OTG1_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_OTG1_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_OTG1_M4_DOMAIN_MASK)
17895#define GPC_PGC_CPU_0_1_MAPPING_OTG2_M4_DOMAIN_MASK (0x200000U)
17896#define GPC_PGC_CPU_0_1_MAPPING_OTG2_M4_DOMAIN_SHIFT (21U)
17897#define GPC_PGC_CPU_0_1_MAPPING_OTG2_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_OTG2_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_OTG2_M4_DOMAIN_MASK)
17898#define GPC_PGC_CPU_0_1_MAPPING_DDR1_M4_DOMAIN_MASK (0x800000U)
17899#define GPC_PGC_CPU_0_1_MAPPING_DDR1_M4_DOMAIN_SHIFT (23U)
17900#define GPC_PGC_CPU_0_1_MAPPING_DDR1_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DDR1_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_DDR1_M4_DOMAIN_MASK)
17901#define GPC_PGC_CPU_0_1_MAPPING_DDR2_M4_DOMAIN_MASK (0x1000000U)
17902#define GPC_PGC_CPU_0_1_MAPPING_DDR2_M4_DOMAIN_SHIFT (24U)
17903#define GPC_PGC_CPU_0_1_MAPPING_DDR2_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DDR2_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_DDR2_M4_DOMAIN_MASK)
17904#define GPC_PGC_CPU_0_1_MAPPING_GPU_M4_DOMAIN_MASK (0x2000000U)
17905#define GPC_PGC_CPU_0_1_MAPPING_GPU_M4_DOMAIN_SHIFT (25U)
17906#define GPC_PGC_CPU_0_1_MAPPING_GPU_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_GPU_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_GPU_M4_DOMAIN_MASK)
17907#define GPC_PGC_CPU_0_1_MAPPING_VPU_M4_DOMAIN_MASK (0x4000000U)
17908#define GPC_PGC_CPU_0_1_MAPPING_VPU_M4_DOMAIN_SHIFT (26U)
17909#define GPC_PGC_CPU_0_1_MAPPING_VPU_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_VPU_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_VPU_M4_DOMAIN_MASK)
17910#define GPC_PGC_CPU_0_1_MAPPING_HDMI_M4_DOMAIN_MASK (0x8000000U)
17911#define GPC_PGC_CPU_0_1_MAPPING_HDMI_M4_DOMAIN_SHIFT (27U)
17912#define GPC_PGC_CPU_0_1_MAPPING_HDMI_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_HDMI_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_HDMI_M4_DOMAIN_MASK)
17913#define GPC_PGC_CPU_0_1_MAPPING_DISP_M4_DOMAIN_MASK (0x10000000U)
17914#define GPC_PGC_CPU_0_1_MAPPING_DISP_M4_DOMAIN_SHIFT (28U)
17915#define GPC_PGC_CPU_0_1_MAPPING_DISP_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DISP_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_DISP_M4_DOMAIN_MASK)
17916#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_M4_DOMAIN_MASK (0x20000000U)
17917#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_M4_DOMAIN_SHIFT (29U)
17918#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_M4_DOMAIN_MASK)
17919#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_M4_DOMAIN_MASK (0x40000000U)
17920#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_M4_DOMAIN_SHIFT (30U)
17921#define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_M4_DOMAIN_MASK)
17922#define GPC_PGC_CPU_0_1_MAPPING_PCIE2_M4_DOMAIN_MASK (0x80000000U)
17923#define GPC_PGC_CPU_0_1_MAPPING_PCIE2_M4_DOMAIN_SHIFT (31U)
17924#define GPC_PGC_CPU_0_1_MAPPING_PCIE2_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_PCIE2_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_PCIE2_M4_DOMAIN_MASK)
17925/*! @} */
17926
17927/*! @name CPU_PGC_SW_PUP_REQ - CPU PGC software power up trigger */
17928/*! @{ */
17929#define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_MASK (0x1U)
17930#define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_SHIFT (0U)
17931#define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_MASK)
17932#define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_MASK (0x2U)
17933#define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_SHIFT (1U)
17934#define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_MASK)
17935#define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_MASK (0x4U)
17936#define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_SHIFT (2U)
17937#define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_MASK)
17938#define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_MASK (0x8U)
17939#define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_SHIFT (3U)
17940#define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_MASK)
17941#define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_MASK (0x10U)
17942#define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_SHIFT (4U)
17943#define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_MASK)
17944/*! @} */
17945
17946/*! @name MIX_PGC_SW_PUP_REQ - MIX PGC software power up trigger */
17947/*! @{ */
17948#define GPC_MIX_PGC_SW_PUP_REQ_MIX_SW_PUP_REQ_MASK (0x1U)
17949#define GPC_MIX_PGC_SW_PUP_REQ_MIX_SW_PUP_REQ_SHIFT (0U)
17950#define GPC_MIX_PGC_SW_PUP_REQ_MIX_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_MIX_PGC_SW_PUP_REQ_MIX_SW_PUP_REQ_SHIFT)) & GPC_MIX_PGC_SW_PUP_REQ_MIX_SW_PUP_REQ_MASK)
17951/*! @} */
17952
17953/*! @name PU_PGC_SW_PUP_REQ - PU PGC software up trigger */
17954/*! @{ */
17955#define GPC_PU_PGC_SW_PUP_REQ_MIPI_SW_PUP_REQ_MASK (0x1U)
17956#define GPC_PU_PGC_SW_PUP_REQ_MIPI_SW_PUP_REQ_SHIFT (0U)
17957#define GPC_PU_PGC_SW_PUP_REQ_MIPI_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MIPI_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MIPI_SW_PUP_REQ_MASK)
17958#define GPC_PU_PGC_SW_PUP_REQ_PCIE_SW_PUP_REQ_MASK (0x2U)
17959#define GPC_PU_PGC_SW_PUP_REQ_PCIE_SW_PUP_REQ_SHIFT (1U)
17960#define GPC_PU_PGC_SW_PUP_REQ_PCIE_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_PCIE_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_PCIE_SW_PUP_REQ_MASK)
17961#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_MASK (0x4U)
17962#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_SHIFT (2U)
17963#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_MASK)
17964#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_SW_PUP_REQ_MASK (0x8U)
17965#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_SW_PUP_REQ_SHIFT (3U)
17966#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_SW_PUP_REQ_MASK)
17967#define GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_MASK (0x20U)
17968#define GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_SHIFT (5U)
17969#define GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_MASK)
17970#define GPC_PU_PGC_SW_PUP_REQ_DDR2_SW_PUP_REQ_MASK (0x40U)
17971#define GPC_PU_PGC_SW_PUP_REQ_DDR2_SW_PUP_REQ_SHIFT (6U)
17972#define GPC_PU_PGC_SW_PUP_REQ_DDR2_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_DDR2_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_DDR2_SW_PUP_REQ_MASK)
17973#define GPC_PU_PGC_SW_PUP_REQ_GPU_SW_PUP_REQ_MASK (0x80U)
17974#define GPC_PU_PGC_SW_PUP_REQ_GPU_SW_PUP_REQ_SHIFT (7U)
17975#define GPC_PU_PGC_SW_PUP_REQ_GPU_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_GPU_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_GPU_SW_PUP_REQ_MASK)
17976#define GPC_PU_PGC_SW_PUP_REQ_VPU_SW_PUP_REQ_MASK (0x100U)
17977#define GPC_PU_PGC_SW_PUP_REQ_VPU_SW_PUP_REQ_SHIFT (8U)
17978#define GPC_PU_PGC_SW_PUP_REQ_VPU_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_VPU_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_VPU_SW_PUP_REQ_MASK)
17979#define GPC_PU_PGC_SW_PUP_REQ_HDMI_SW_PUP_REQ_MASK (0x200U)
17980#define GPC_PU_PGC_SW_PUP_REQ_HDMI_SW_PUP_REQ_SHIFT (9U)
17981#define GPC_PU_PGC_SW_PUP_REQ_HDMI_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_HDMI_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_HDMI_SW_PUP_REQ_MASK)
17982#define GPC_PU_PGC_SW_PUP_REQ_DISP_SW_PUP_REQ_MASK (0x400U)
17983#define GPC_PU_PGC_SW_PUP_REQ_DISP_SW_PUP_REQ_SHIFT (10U)
17984#define GPC_PU_PGC_SW_PUP_REQ_DISP_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_DISP_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_DISP_SW_PUP_REQ_MASK)
17985#define GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI1_SW_PUP_REQ_MASK (0x800U)
17986#define GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI1_SW_PUP_REQ_SHIFT (11U)
17987#define GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI1_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI1_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI1_SW_PUP_REQ_MASK)
17988#define GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI2_SW_PUP_REQ_MASK (0x1000U)
17989#define GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI2_SW_PUP_REQ_SHIFT (12U)
17990#define GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI2_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI2_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI2_SW_PUP_REQ_MASK)
17991#define GPC_PU_PGC_SW_PUP_REQ_PCIE2_SW_PUP_REQ_MASK (0x2000U)
17992#define GPC_PU_PGC_SW_PUP_REQ_PCIE2_SW_PUP_REQ_SHIFT (13U)
17993#define GPC_PU_PGC_SW_PUP_REQ_PCIE2_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_PCIE2_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_PCIE2_SW_PUP_REQ_MASK)
17994/*! @} */
17995
17996/*! @name CPU_PGC_SW_PDN_REQ - CPU PGC software down trigger */
17997/*! @{ */
17998#define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_MASK (0x1U)
17999#define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_SHIFT (0U)
18000#define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_MASK)
18001#define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_MASK (0x2U)
18002#define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_SHIFT (1U)
18003#define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_MASK)
18004#define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PDN_REQ_MASK (0x4U)
18005#define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PDN_REQ_SHIFT (2U)
18006#define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PDN_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PDN_REQ_MASK)
18007#define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PUP_REQ_MASK (0x8U)
18008#define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PUP_REQ_SHIFT (3U)
18009#define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PUP_REQ_MASK)
18010#define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_MASK (0x10U)
18011#define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_SHIFT (4U)
18012#define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_MASK)
18013/*! @} */
18014
18015/*! @name MIX_PGC_SW_PDN_REQ - MIX PGC software power down trigger */
18016/*! @{ */
18017#define GPC_MIX_PGC_SW_PDN_REQ_MIX_SW_PDN_REQ_MASK (0x1U)
18018#define GPC_MIX_PGC_SW_PDN_REQ_MIX_SW_PDN_REQ_SHIFT (0U)
18019#define GPC_MIX_PGC_SW_PDN_REQ_MIX_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_MIX_PGC_SW_PDN_REQ_MIX_SW_PDN_REQ_SHIFT)) & GPC_MIX_PGC_SW_PDN_REQ_MIX_SW_PDN_REQ_MASK)
18020/*! @} */
18021
18022/*! @name PU_PGC_SW_PDN_REQ - PU PGC software down trigger */
18023/*! @{ */
18024#define GPC_PU_PGC_SW_PDN_REQ_MIPI_SW_PDN_REQ_MASK (0x1U)
18025#define GPC_PU_PGC_SW_PDN_REQ_MIPI_SW_PDN_REQ_SHIFT (0U)
18026#define GPC_PU_PGC_SW_PDN_REQ_MIPI_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MIPI_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MIPI_SW_PDN_REQ_MASK)
18027#define GPC_PU_PGC_SW_PDN_REQ_PCIE_SW_PDN_REQ_MASK (0x2U)
18028#define GPC_PU_PGC_SW_PDN_REQ_PCIE_SW_PDN_REQ_SHIFT (1U)
18029#define GPC_PU_PGC_SW_PDN_REQ_PCIE_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_PCIE_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_PCIE_SW_PDN_REQ_MASK)
18030#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_MASK (0x4U)
18031#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_SHIFT (2U)
18032#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_MASK)
18033#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_SW_PDN_REQ_MASK (0x8U)
18034#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_SW_PDN_REQ_SHIFT (3U)
18035#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_SW_PDN_REQ_MASK)
18036#define GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_MASK (0x20U)
18037#define GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_SHIFT (5U)
18038#define GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_MASK)
18039#define GPC_PU_PGC_SW_PDN_REQ_DDR2_SW_PDN_REQ_MASK (0x40U)
18040#define GPC_PU_PGC_SW_PDN_REQ_DDR2_SW_PDN_REQ_SHIFT (6U)
18041#define GPC_PU_PGC_SW_PDN_REQ_DDR2_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_DDR2_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_DDR2_SW_PDN_REQ_MASK)
18042#define GPC_PU_PGC_SW_PDN_REQ_GPU_SW_PDN_REQ_MASK (0x80U)
18043#define GPC_PU_PGC_SW_PDN_REQ_GPU_SW_PDN_REQ_SHIFT (7U)
18044#define GPC_PU_PGC_SW_PDN_REQ_GPU_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_GPU_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_GPU_SW_PDN_REQ_MASK)
18045#define GPC_PU_PGC_SW_PDN_REQ_VPU_SW_PDN_REQ_MASK (0x100U)
18046#define GPC_PU_PGC_SW_PDN_REQ_VPU_SW_PDN_REQ_SHIFT (8U)
18047#define GPC_PU_PGC_SW_PDN_REQ_VPU_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_VPU_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_VPU_SW_PDN_REQ_MASK)
18048#define GPC_PU_PGC_SW_PDN_REQ_HDMI_SW_PDN_REQ_MASK (0x200U)
18049#define GPC_PU_PGC_SW_PDN_REQ_HDMI_SW_PDN_REQ_SHIFT (9U)
18050#define GPC_PU_PGC_SW_PDN_REQ_HDMI_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_HDMI_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_HDMI_SW_PDN_REQ_MASK)
18051#define GPC_PU_PGC_SW_PDN_REQ_DISP_SW_PDN_REQ_MASK (0x400U)
18052#define GPC_PU_PGC_SW_PDN_REQ_DISP_SW_PDN_REQ_SHIFT (10U)
18053#define GPC_PU_PGC_SW_PDN_REQ_DISP_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_DISP_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_DISP_SW_PDN_REQ_MASK)
18054#define GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI1_SW_PDN_REQ_MASK (0x800U)
18055#define GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI1_SW_PDN_REQ_SHIFT (11U)
18056#define GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI1_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI1_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI1_SW_PDN_REQ_MASK)
18057#define GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI2_SW_PDN_REQ_MASK (0x1000U)
18058#define GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI2_SW_PDN_REQ_SHIFT (12U)
18059#define GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI2_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI2_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI2_SW_PDN_REQ_MASK)
18060#define GPC_PU_PGC_SW_PDN_REQ_PCIE2_SW_PDN_REQ_MASK (0x2000U)
18061#define GPC_PU_PGC_SW_PDN_REQ_PCIE2_SW_PDN_REQ_SHIFT (13U)
18062#define GPC_PU_PGC_SW_PDN_REQ_PCIE2_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_PCIE2_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_PCIE2_SW_PDN_REQ_MASK)
18063/*! @} */
18064
18065/*! @name LPCR_A53_BSC2 - Basic Low power control register of A53 platform */
18066/*! @{ */
18067#define GPC_LPCR_A53_BSC2_LPM2_MASK (0x3U)
18068#define GPC_LPCR_A53_BSC2_LPM2_SHIFT (0U)
18069/*! LPM2
18070 * 0b00..Remain in RUN mode
18071 * 0b01..Transfer to WAIT mode
18072 * 0b10..Transfer to STOP mode
18073 * 0b11..Reserved
18074 */
18075#define GPC_LPCR_A53_BSC2_LPM2(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC2_LPM2_SHIFT)) & GPC_LPCR_A53_BSC2_LPM2_MASK)
18076#define GPC_LPCR_A53_BSC2_LPM3_MASK (0xCU)
18077#define GPC_LPCR_A53_BSC2_LPM3_SHIFT (2U)
18078/*! LPM3
18079 * 0b00..Remain in RUN mode
18080 * 0b01..Transfer to WAIT mode
18081 * 0b10..Transfer to STOP mode
18082 * 0b11..Reserved
18083 */
18084#define GPC_LPCR_A53_BSC2_LPM3(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC2_LPM3_SHIFT)) & GPC_LPCR_A53_BSC2_LPM3_MASK)
18085/*! @} */
18086
18087/*! @name CPU_PGC_PUP_STATUS1 - CPU PGC software up trigger status1 */
18088/*! @{ */
18089#define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_MASK (0x1U)
18090#define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_SHIFT (0U)
18091#define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_MASK)
18092#define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_MASK (0x2U)
18093#define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_SHIFT (1U)
18094#define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_MASK)
18095#define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_STATUS_MASK (0x4U)
18096#define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_STATUS_SHIFT (2U)
18097#define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_STATUS_MASK)
18098#define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_MASK (0x8U)
18099#define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_SHIFT (3U)
18100#define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_MASK)
18101#define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_REQ_MASK (0x10U)
18102#define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_REQ_SHIFT (4U)
18103#define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_REQ_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_REQ_MASK)
18104/*! @} */
18105
18106/*! @name A53_MIX_PGC_PUP_STATUS - A53 MIX software up trigger status register */
18107/*! @{ */
18108#define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_MASK (0x1U)
18109#define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_SHIFT (0U)
18110#define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_SHIFT)) & GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_MASK)
18111/*! @} */
18112
18113/* The count of GPC_A53_MIX_PGC_PUP_STATUS */
18114#define GPC_A53_MIX_PGC_PUP_STATUS_COUNT (3U)
18115
18116/*! @name M4_MIX_PGC_PUP_STATUS - M4 MIX PGC software up trigger status register */
18117/*! @{ */
18118#define GPC_M4_MIX_PGC_PUP_STATUS_M4_MIX_PGC_PUP_STATUS_MASK (0x1U)
18119#define GPC_M4_MIX_PGC_PUP_STATUS_M4_MIX_PGC_PUP_STATUS_SHIFT (0U)
18120#define GPC_M4_MIX_PGC_PUP_STATUS_M4_MIX_PGC_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_MIX_PGC_PUP_STATUS_M4_MIX_PGC_PUP_STATUS_SHIFT)) & GPC_M4_MIX_PGC_PUP_STATUS_M4_MIX_PGC_PUP_STATUS_MASK)
18121/*! @} */
18122
18123/* The count of GPC_M4_MIX_PGC_PUP_STATUS */
18124#define GPC_M4_MIX_PGC_PUP_STATUS_COUNT (3U)
18125
18126/*! @name A53_PU_PGC_PUP_STATUS - A53 PU software up trigger status register */
18127/*! @{ */
18128#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PUP_STATUS_MASK (0x1U)
18129#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PUP_STATUS_SHIFT (0U)
18130#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PUP_STATUS_MASK)
18131#define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PUP_STATUS_MASK (0x2U)
18132#define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PUP_STATUS_SHIFT (1U)
18133#define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PUP_STATUS_MASK)
18134#define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_MASK (0x4U)
18135#define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_SHIFT (2U)
18136#define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_MASK)
18137#define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG2_PUP_STATUS_MASK (0x8U)
18138#define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG2_PUP_STATUS_SHIFT (3U)
18139#define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_OTG2_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_OTG2_PUP_STATUS_MASK)
18140#define GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_MASK (0x20U)
18141#define GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_SHIFT (5U)
18142#define GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_MASK)
18143#define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_PUP_STATUS_MASK (0x80U)
18144#define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_PUP_STATUS_SHIFT (7U)
18145#define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_PUP_STATUS_MASK)
18146#define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_PUP_STATUS_MASK (0x100U)
18147#define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_PUP_STATUS_SHIFT (8U)
18148#define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_PUP_STATUS_MASK)
18149#define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PUP_STATUS_MASK (0x200U)
18150#define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PUP_STATUS_SHIFT (9U)
18151#define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PUP_STATUS_MASK)
18152#define GPC_A53_PU_PGC_PUP_STATUS_A53_DISP_PUP_STATUS_MASK (0x400U)
18153#define GPC_A53_PU_PGC_PUP_STATUS_A53_DISP_PUP_STATUS_SHIFT (10U)
18154#define GPC_A53_PU_PGC_PUP_STATUS_A53_DISP_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_DISP_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_DISP_PUP_STATUS_MASK)
18155#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI1_PUP_STATUS_MASK (0x800U)
18156#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI1_PUP_STATUS_SHIFT (11U)
18157#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI1_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI1_PUP_STATUS_MASK)
18158#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI2_PUP_STATUS_MASK (0x1000U)
18159#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI2_PUP_STATUS_SHIFT (12U)
18160#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI2_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI2_PUP_STATUS_MASK)
18161#define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE2_PUP_STATUS_MASK (0x2000U)
18162#define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE2_PUP_STATUS_SHIFT (13U)
18163#define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE2_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE2_PUP_STATUS_MASK)
18164/*! @} */
18165
18166/* The count of GPC_A53_PU_PGC_PUP_STATUS */
18167#define GPC_A53_PU_PGC_PUP_STATUS_COUNT (3U)
18168
18169/*! @name M4_PU_PGC_PUP_STATUS - M4 PU PGC software up trigger status register */
18170/*! @{ */
18171#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PUP_STATUS_MASK (0x1U)
18172#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PUP_STATUS_SHIFT (0U)
18173#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PUP_STATUS_MASK)
18174#define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PUP_STATUS_MASK (0x2U)
18175#define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PUP_STATUS_SHIFT (1U)
18176#define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PUP_STATUS_MASK)
18177#define GPC_M4_PU_PGC_PUP_STATUS_M4_OTG1_PUP_STATUS_MASK (0x4U)
18178#define GPC_M4_PU_PGC_PUP_STATUS_M4_OTG1_PUP_STATUS_SHIFT (2U)
18179#define GPC_M4_PU_PGC_PUP_STATUS_M4_OTG1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_OTG1_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_OTG1_PUP_STATUS_MASK)
18180#define GPC_M4_PU_PGC_PUP_STATUS_M4_OTG2_PUP_STATUS_MASK (0x8U)
18181#define GPC_M4_PU_PGC_PUP_STATUS_M4_OTG2_PUP_STATUS_SHIFT (3U)
18182#define GPC_M4_PU_PGC_PUP_STATUS_M4_OTG2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_OTG2_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_OTG2_PUP_STATUS_MASK)
18183#define GPC_M4_PU_PGC_PUP_STATUS_M4_DDR1_PUP_STATUS_MASK (0x20U)
18184#define GPC_M4_PU_PGC_PUP_STATUS_M4_DDR1_PUP_STATUS_SHIFT (5U)
18185#define GPC_M4_PU_PGC_PUP_STATUS_M4_DDR1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_DDR1_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_DDR1_PUP_STATUS_MASK)
18186#define GPC_M4_PU_PGC_PUP_STATUS_M4_GPU_PUP_STATUS_MASK (0x80U)
18187#define GPC_M4_PU_PGC_PUP_STATUS_M4_GPU_PUP_STATUS_SHIFT (7U)
18188#define GPC_M4_PU_PGC_PUP_STATUS_M4_GPU_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_GPU_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_GPU_PUP_STATUS_MASK)
18189#define GPC_M4_PU_PGC_PUP_STATUS_M4_VPU_PUP_STATUS_MASK (0x100U)
18190#define GPC_M4_PU_PGC_PUP_STATUS_M4_VPU_PUP_STATUS_SHIFT (8U)
18191#define GPC_M4_PU_PGC_PUP_STATUS_M4_VPU_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_VPU_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_VPU_PUP_STATUS_MASK)
18192#define GPC_M4_PU_PGC_PUP_STATUS_M4_HDMI_PUP_STATUS_MASK (0x200U)
18193#define GPC_M4_PU_PGC_PUP_STATUS_M4_HDMI_PUP_STATUS_SHIFT (9U)
18194#define GPC_M4_PU_PGC_PUP_STATUS_M4_HDMI_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_HDMI_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_HDMI_PUP_STATUS_MASK)
18195#define GPC_M4_PU_PGC_PUP_STATUS_M4_DISP_PUP_STATUS_MASK (0x400U)
18196#define GPC_M4_PU_PGC_PUP_STATUS_M4_DISP_PUP_STATUS_SHIFT (10U)
18197#define GPC_M4_PU_PGC_PUP_STATUS_M4_DISP_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_DISP_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_DISP_PUP_STATUS_MASK)
18198#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI1_PUP_STATUS_MASK (0x800U)
18199#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI1_PUP_STATUS_SHIFT (11U)
18200#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI1_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI1_PUP_STATUS_MASK)
18201#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI2_PUP_STATUS_MASK (0x1000U)
18202#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI2_PUP_STATUS_SHIFT (12U)
18203#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI2_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI2_PUP_STATUS_MASK)
18204#define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE2_PUP_STATUS_MASK (0x2000U)
18205#define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE2_PUP_STATUS_SHIFT (13U)
18206#define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE2_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE2_PUP_STATUS_MASK)
18207/*! @} */
18208
18209/* The count of GPC_M4_PU_PGC_PUP_STATUS */
18210#define GPC_M4_PU_PGC_PUP_STATUS_COUNT (3U)
18211
18212/*! @name CPU_PGC_PDN_STATUS1 - CPU PGC software dn trigger status1 */
18213/*! @{ */
18214#define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_MASK (0x1U)
18215#define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_SHIFT (0U)
18216#define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_MASK)
18217#define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_MASK (0x2U)
18218#define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_SHIFT (1U)
18219#define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_MASK)
18220#define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_STATUS_MASK (0x4U)
18221#define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_STATUS_SHIFT (2U)
18222#define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_STATUS_MASK)
18223#define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_MASK (0x8U)
18224#define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_SHIFT (3U)
18225#define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_MASK)
18226#define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_REQ_MASK (0x10U)
18227#define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_REQ_SHIFT (4U)
18228#define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_REQ_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_REQ_MASK)
18229/*! @} */
18230
18231/*! @name A53_MIX_PGC_PDN_STATUS - A53 MIX software down trigger status register */
18232/*! @{ */
18233#define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_MASK (0x1U)
18234#define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_SHIFT (0U)
18235#define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_SHIFT)) & GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_MASK)
18236/*! @} */
18237
18238/* The count of GPC_A53_MIX_PGC_PDN_STATUS */
18239#define GPC_A53_MIX_PGC_PDN_STATUS_COUNT (3U)
18240
18241/*! @name M4_MIX_PGC_PDN_STATUS - M4 MIX PGC software power down trigger status register */
18242/*! @{ */
18243#define GPC_M4_MIX_PGC_PDN_STATUS_M4_MIX_PGC_PDN_STATUS_MASK (0x1U)
18244#define GPC_M4_MIX_PGC_PDN_STATUS_M4_MIX_PGC_PDN_STATUS_SHIFT (0U)
18245#define GPC_M4_MIX_PGC_PDN_STATUS_M4_MIX_PGC_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_MIX_PGC_PDN_STATUS_M4_MIX_PGC_PDN_STATUS_SHIFT)) & GPC_M4_MIX_PGC_PDN_STATUS_M4_MIX_PGC_PDN_STATUS_MASK)
18246/*! @} */
18247
18248/* The count of GPC_M4_MIX_PGC_PDN_STATUS */
18249#define GPC_M4_MIX_PGC_PDN_STATUS_COUNT (3U)
18250
18251/*! @name A53_PU_PGC_PDN_STATUS - A53 PU PGC software down trigger status */
18252/*! @{ */
18253#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PDN_STATUS_MASK (0x1U)
18254#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PDN_STATUS_SHIFT (0U)
18255#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PDN_STATUS_MASK)
18256#define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE_PDN_STATUS_MASK (0x2U)
18257#define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE_PDN_STATUS_SHIFT (1U)
18258#define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE_PDN_STATUS_MASK)
18259#define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_MASK (0x4U)
18260#define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_SHIFT (2U)
18261#define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_MASK)
18262#define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG2_PDN_STATUS_MASK (0x8U)
18263#define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG2_PDN_STATUS_SHIFT (3U)
18264#define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_OTG2_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_OTG2_PDN_STATUS_MASK)
18265#define GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_MASK (0x20U)
18266#define GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_SHIFT (5U)
18267#define GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_MASK)
18268#define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_PDN_STATUS_MASK (0x80U)
18269#define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_PDN_STATUS_SHIFT (7U)
18270#define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_PDN_STATUS_MASK)
18271#define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_PDN_STATUS_MASK (0x100U)
18272#define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_PDN_STATUS_SHIFT (8U)
18273#define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_PDN_STATUS_MASK)
18274#define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PDN_STATUS_MASK (0x200U)
18275#define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PDN_STATUS_SHIFT (9U)
18276#define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PDN_STATUS_MASK)
18277#define GPC_A53_PU_PGC_PDN_STATUS_A53_DISP_PDN_STATUS_MASK (0x400U)
18278#define GPC_A53_PU_PGC_PDN_STATUS_A53_DISP_PDN_STATUS_SHIFT (10U)
18279#define GPC_A53_PU_PGC_PDN_STATUS_A53_DISP_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_DISP_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_DISP_PDN_STATUS_MASK)
18280#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI1_PDN_STATUS_MASK (0x800U)
18281#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI1_PDN_STATUS_SHIFT (11U)
18282#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI1_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI1_PDN_STATUS_MASK)
18283#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI2_PDN_STATUS_MASK (0x1000U)
18284#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI2_PDN_STATUS_SHIFT (12U)
18285#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI2_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI2_PDN_STATUS_MASK)
18286#define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE2_PDN_STATUS_MASK (0x2000U)
18287#define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE2_PDN_STATUS_SHIFT (13U)
18288#define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE2_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE2_PDN_STATUS_MASK)
18289/*! @} */
18290
18291/* The count of GPC_A53_PU_PGC_PDN_STATUS */
18292#define GPC_A53_PU_PGC_PDN_STATUS_COUNT (3U)
18293
18294/*! @name M4_PU_PGC_PDN_STATUS - M4 PU PGC software down trigger status */
18295/*! @{ */
18296#define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_PDN_STATUS_MASK (0x1U)
18297#define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_PDN_STATUS_SHIFT (0U)
18298#define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_PDN_STATUS_MASK)
18299#define GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE_PDN_STATUS_MASK (0x2U)
18300#define GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE_PDN_STATUS_SHIFT (1U)
18301#define GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE_PDN_STATUS_MASK)
18302#define GPC_M4_PU_PGC_PDN_STATUS_M4_OTG1_PDN_STATUS_MASK (0x4U)
18303#define GPC_M4_PU_PGC_PDN_STATUS_M4_OTG1_PDN_STATUS_SHIFT (2U)
18304#define GPC_M4_PU_PGC_PDN_STATUS_M4_OTG1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_OTG1_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_OTG1_PDN_STATUS_MASK)
18305#define GPC_M4_PU_PGC_PDN_STATUS_M4_OTG2_PDN_STATUS_MASK (0x8U)
18306#define GPC_M4_PU_PGC_PDN_STATUS_M4_OTG2_PDN_STATUS_SHIFT (3U)
18307#define GPC_M4_PU_PGC_PDN_STATUS_M4_OTG2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_OTG2_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_OTG2_PDN_STATUS_MASK)
18308#define GPC_M4_PU_PGC_PDN_STATUS_M4_DDR1_PDN_STATUS_MASK (0x20U)
18309#define GPC_M4_PU_PGC_PDN_STATUS_M4_DDR1_PDN_STATUS_SHIFT (5U)
18310#define GPC_M4_PU_PGC_PDN_STATUS_M4_DDR1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_DDR1_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_DDR1_PDN_STATUS_MASK)
18311#define GPC_M4_PU_PGC_PDN_STATUS_M4_GPU_PDN_STATUS_MASK (0x80U)
18312#define GPC_M4_PU_PGC_PDN_STATUS_M4_GPU_PDN_STATUS_SHIFT (7U)
18313#define GPC_M4_PU_PGC_PDN_STATUS_M4_GPU_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_GPU_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_GPU_PDN_STATUS_MASK)
18314#define GPC_M4_PU_PGC_PDN_STATUS_M4_VPU_PDN_STATUS_MASK (0x100U)
18315#define GPC_M4_PU_PGC_PDN_STATUS_M4_VPU_PDN_STATUS_SHIFT (8U)
18316#define GPC_M4_PU_PGC_PDN_STATUS_M4_VPU_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_VPU_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_VPU_PDN_STATUS_MASK)
18317#define GPC_M4_PU_PGC_PDN_STATUS_M4_HDMI_PDN_STATUS_MASK (0x200U)
18318#define GPC_M4_PU_PGC_PDN_STATUS_M4_HDMI_PDN_STATUS_SHIFT (9U)
18319#define GPC_M4_PU_PGC_PDN_STATUS_M4_HDMI_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_HDMI_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_HDMI_PDN_STATUS_MASK)
18320#define GPC_M4_PU_PGC_PDN_STATUS_M4_DISP_PDN_STATUS_MASK (0x400U)
18321#define GPC_M4_PU_PGC_PDN_STATUS_M4_DISP_PDN_STATUS_SHIFT (10U)
18322#define GPC_M4_PU_PGC_PDN_STATUS_M4_DISP_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_DISP_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_DISP_PDN_STATUS_MASK)
18323#define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI1_PDN_STATUS_MASK (0x800U)
18324#define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI1_PDN_STATUS_SHIFT (11U)
18325#define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI1_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI1_PDN_STATUS_MASK)
18326#define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI2_PDN_STATUS_MASK (0x1000U)
18327#define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI2_PDN_STATUS_SHIFT (12U)
18328#define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI2_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI2_PDN_STATUS_MASK)
18329#define GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE2_PDN_STATUS_MASK (0x2000U)
18330#define GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE2_PDN_STATUS_SHIFT (13U)
18331#define GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE2_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE2_PDN_STATUS_MASK)
18332/*! @} */
18333
18334/* The count of GPC_M4_PU_PGC_PDN_STATUS */
18335#define GPC_M4_PU_PGC_PDN_STATUS_COUNT (3U)
18336
18337/*! @name A53_MIX_PDN_FLG - A53 MIX PDN FLG */
18338/*! @{ */
18339#define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_MASK (0x1U)
18340#define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_SHIFT (0U)
18341#define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_SHIFT)) & GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_MASK)
18342/*! @} */
18343
18344/*! @name A53_PU_PDN_FLG - A53 PU PDN FLG */
18345/*! @{ */
18346#define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_MASK (0x3FFFU)
18347#define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_SHIFT (0U)
18348#define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_SHIFT)) & GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_MASK)
18349/*! @} */
18350
18351/*! @name M4_MIX_PDN_FLG - M4 MIX PDN FLG */
18352/*! @{ */
18353#define GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG_MASK (0x1U)
18354#define GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG_SHIFT (0U)
18355#define GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG_SHIFT)) & GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG_MASK)
18356/*! @} */
18357
18358/*! @name M4_PU_PDN_FLG - M4 PU PDN FLG */
18359/*! @{ */
18360#define GPC_M4_PU_PDN_FLG_M4_PU_PDN_FLG_MASK (0x3FFFU)
18361#define GPC_M4_PU_PDN_FLG_M4_PU_PDN_FLG_SHIFT (0U)
18362#define GPC_M4_PU_PDN_FLG_M4_PU_PDN_FLG(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PDN_FLG_M4_PU_PDN_FLG_SHIFT)) & GPC_M4_PU_PDN_FLG_M4_PU_PDN_FLG_MASK)
18363/*! @} */
18364
18365/*! @name IMR_CORE2_A53 - IRQ masking register 1 of A53 core2..IRQ masking register 4 of A53 core2 */
18366/*! @{ */
18367#define GPC_IMR_CORE2_A53_IMR1_CORE2_A53_MASK (0xFFFFFFFFU)
18368#define GPC_IMR_CORE2_A53_IMR1_CORE2_A53_SHIFT (0U)
18369/*! IMR1_CORE2_A53
18370 * 0b00000000000000000000000000000000..IRQ not masked
18371 * 0b00000000000000000000000000000001..IRQ masked
18372 */
18373#define GPC_IMR_CORE2_A53_IMR1_CORE2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR1_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR1_CORE2_A53_MASK)
18374#define GPC_IMR_CORE2_A53_IMR2_CORE2_A53_MASK (0xFFFFFFFFU)
18375#define GPC_IMR_CORE2_A53_IMR2_CORE2_A53_SHIFT (0U)
18376/*! IMR2_CORE2_A53
18377 * 0b00000000000000000000000000000000..IRQ not masked
18378 * 0b00000000000000000000000000000001..IRQ masked
18379 */
18380#define GPC_IMR_CORE2_A53_IMR2_CORE2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR2_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR2_CORE2_A53_MASK)
18381#define GPC_IMR_CORE2_A53_IMR3_CORE2_A53_MASK (0xFFFFFFFFU)
18382#define GPC_IMR_CORE2_A53_IMR3_CORE2_A53_SHIFT (0U)
18383/*! IMR3_CORE2_A53
18384 * 0b00000000000000000000000000000000..IRQ not masked
18385 * 0b00000000000000000000000000000001..IRQ masked
18386 */
18387#define GPC_IMR_CORE2_A53_IMR3_CORE2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR3_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR3_CORE2_A53_MASK)
18388#define GPC_IMR_CORE2_A53_IMR4_CORE2_A53_MASK (0xFFFFFFFFU)
18389#define GPC_IMR_CORE2_A53_IMR4_CORE2_A53_SHIFT (0U)
18390/*! IMR4_CORE2_A53
18391 * 0b00000000000000000000000000000000..IRQ not masked
18392 * 0b00000000000000000000000000000001..IRQ masked
18393 */
18394#define GPC_IMR_CORE2_A53_IMR4_CORE2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR4_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR4_CORE2_A53_MASK)
18395/*! @} */
18396
18397/* The count of GPC_IMR_CORE2_A53 */
18398#define GPC_IMR_CORE2_A53_COUNT (4U)
18399
18400/*! @name IMR_CORE3_A53 - IRQ masking register 1 of A53 core3..IRQ masking register 4 of A53 core3 */
18401/*! @{ */
18402#define GPC_IMR_CORE3_A53_IMR1_CORE3_A53_MASK (0xFFFFFFFFU)
18403#define GPC_IMR_CORE3_A53_IMR1_CORE3_A53_SHIFT (0U)
18404/*! IMR1_CORE3_A53
18405 * 0b00000000000000000000000000000000..IRQ not masked
18406 * 0b00000000000000000000000000000001..IRQ masked
18407 */
18408#define GPC_IMR_CORE3_A53_IMR1_CORE3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR1_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR1_CORE3_A53_MASK)
18409#define GPC_IMR_CORE3_A53_IMR2_CORE3_A53_MASK (0xFFFFFFFFU)
18410#define GPC_IMR_CORE3_A53_IMR2_CORE3_A53_SHIFT (0U)
18411/*! IMR2_CORE3_A53
18412 * 0b00000000000000000000000000000000..IRQ not masked
18413 * 0b00000000000000000000000000000001..IRQ masked
18414 */
18415#define GPC_IMR_CORE3_A53_IMR2_CORE3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR2_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR2_CORE3_A53_MASK)
18416#define GPC_IMR_CORE3_A53_IMR3_CORE3_A53_MASK (0xFFFFFFFFU)
18417#define GPC_IMR_CORE3_A53_IMR3_CORE3_A53_SHIFT (0U)
18418/*! IMR3_CORE3_A53
18419 * 0b00000000000000000000000000000000..IRQ not masked
18420 * 0b00000000000000000000000000000001..IRQ masked
18421 */
18422#define GPC_IMR_CORE3_A53_IMR3_CORE3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR3_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR3_CORE3_A53_MASK)
18423#define GPC_IMR_CORE3_A53_IMR4_CORE3_A53_MASK (0xFFFFFFFFU)
18424#define GPC_IMR_CORE3_A53_IMR4_CORE3_A53_SHIFT (0U)
18425/*! IMR4_CORE3_A53
18426 * 0b00000000000000000000000000000000..IRQ not masked
18427 * 0b00000000000000000000000000000001..IRQ masked
18428 */
18429#define GPC_IMR_CORE3_A53_IMR4_CORE3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR4_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR4_CORE3_A53_MASK)
18430/*! @} */
18431
18432/* The count of GPC_IMR_CORE3_A53 */
18433#define GPC_IMR_CORE3_A53_COUNT (4U)
18434
18435/*! @name ACK_SEL_A53_PU - PGC acknowledge signal selection of A53 platform for PUs */
18436/*! @{ */
18437#define GPC_ACK_SEL_A53_PU_MF_PGC_PDN_ACK_MASK (0x1U)
18438#define GPC_ACK_SEL_A53_PU_MF_PGC_PDN_ACK_SHIFT (0U)
18439#define GPC_ACK_SEL_A53_PU_MF_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MF_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MF_PGC_PDN_ACK_MASK)
18440#define GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_MASK (0x4U)
18441#define GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_SHIFT (2U)
18442#define GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_MASK)
18443#define GPC_ACK_SEL_A53_PU_PCIE_PGC_PDN_ACK_MASK (0x8U)
18444#define GPC_ACK_SEL_A53_PU_PCIE_PGC_PDN_ACK_SHIFT (3U)
18445#define GPC_ACK_SEL_A53_PU_PCIE_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_PCIE_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_PCIE_PGC_PDN_ACK_MASK)
18446#define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_MASK (0x10U)
18447#define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_SHIFT (4U)
18448#define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_MASK)
18449#define GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PDN_ACK_MASK (0x20U)
18450#define GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PDN_ACK_SHIFT (5U)
18451#define GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PDN_ACK_MASK)
18452#define GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_MASK (0x80U)
18453#define GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_SHIFT (7U)
18454#define GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_MASK)
18455#define GPC_ACK_SEL_A53_PU_DDR2_PGC_PDN_ACK_MASK (0x100U)
18456#define GPC_ACK_SEL_A53_PU_DDR2_PGC_PDN_ACK_SHIFT (8U)
18457#define GPC_ACK_SEL_A53_PU_DDR2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DDR2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_DDR2_PGC_PDN_ACK_MASK)
18458#define GPC_ACK_SEL_A53_PU_GPU_PGC_PDN_ACK_MASK (0x200U)
18459#define GPC_ACK_SEL_A53_PU_GPU_PGC_PDN_ACK_SHIFT (9U)
18460#define GPC_ACK_SEL_A53_PU_GPU_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPU_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_GPU_PGC_PDN_ACK_MASK)
18461#define GPC_ACK_SEL_A53_PU_VPU_PGC_PDN_ACK_MASK (0x400U)
18462#define GPC_ACK_SEL_A53_PU_VPU_PGC_PDN_ACK_SHIFT (10U)
18463#define GPC_ACK_SEL_A53_PU_VPU_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPU_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPU_PGC_PDN_ACK_MASK)
18464#define GPC_ACK_SEL_A53_PU_HDMI_PGC_PDN_ACK_MASK (0x800U)
18465#define GPC_ACK_SEL_A53_PU_HDMI_PGC_PDN_ACK_SHIFT (11U)
18466#define GPC_ACK_SEL_A53_PU_HDMI_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_HDMI_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_HDMI_PGC_PDN_ACK_MASK)
18467#define GPC_ACK_SEL_A53_PU_DISP_PGC_PDN_ACK_MASK (0x1000U)
18468#define GPC_ACK_SEL_A53_PU_DISP_PGC_PDN_ACK_SHIFT (12U)
18469#define GPC_ACK_SEL_A53_PU_DISP_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DISP_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_DISP_PGC_PDN_ACK_MASK)
18470#define GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PDN_ACK_MASK (0x2000U)
18471#define GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PDN_ACK_SHIFT (13U)
18472#define GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PDN_ACK_MASK)
18473#define GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PDN_ACK_MASK (0x4000U)
18474#define GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PDN_ACK_SHIFT (14U)
18475#define GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PDN_ACK_MASK)
18476#define GPC_ACK_SEL_A53_PU_PCIE2_PGC_PDN_ACK_MASK (0x8000U)
18477#define GPC_ACK_SEL_A53_PU_PCIE2_PGC_PDN_ACK_SHIFT (15U)
18478#define GPC_ACK_SEL_A53_PU_PCIE2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_PCIE2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_PCIE2_PGC_PDN_ACK_MASK)
18479#define GPC_ACK_SEL_A53_PU_MF_PGC_PUP_ACK_MASK (0x10000U)
18480#define GPC_ACK_SEL_A53_PU_MF_PGC_PUP_ACK_SHIFT (16U)
18481#define GPC_ACK_SEL_A53_PU_MF_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MF_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MF_PGC_PUP_ACK_MASK)
18482#define GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_MASK (0x40000U)
18483#define GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_SHIFT (18U)
18484#define GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_MASK)
18485#define GPC_ACK_SEL_A53_PU_PCIE_PGC_PUP_ACK_MASK (0x80000U)
18486#define GPC_ACK_SEL_A53_PU_PCIE_PGC_PUP_ACK_SHIFT (19U)
18487#define GPC_ACK_SEL_A53_PU_PCIE_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_PCIE_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_PCIE_PGC_PUP_ACK_MASK)
18488#define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_MASK (0x100000U)
18489#define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_SHIFT (20U)
18490#define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_MASK)
18491#define GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PUP_ACK_MASK (0x200000U)
18492#define GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PUP_ACK_SHIFT (21U)
18493#define GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PUP_ACK_MASK)
18494#define GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_MASK (0x800000U)
18495#define GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_SHIFT (23U)
18496#define GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_MASK)
18497#define GPC_ACK_SEL_A53_PU_DDR2_PGC_PUP_ACK_MASK (0x1000000U)
18498#define GPC_ACK_SEL_A53_PU_DDR2_PGC_PUP_ACK_SHIFT (24U)
18499#define GPC_ACK_SEL_A53_PU_DDR2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DDR2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_DDR2_PGC_PUP_ACK_MASK)
18500#define GPC_ACK_SEL_A53_PU_GPU_PGC_PUP_ACK_MASK (0x2000000U)
18501#define GPC_ACK_SEL_A53_PU_GPU_PGC_PUP_ACK_SHIFT (25U)
18502#define GPC_ACK_SEL_A53_PU_GPU_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPU_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_GPU_PGC_PUP_ACK_MASK)
18503#define GPC_ACK_SEL_A53_PU_VPU_PGC_PUP_ACK_MASK (0x4000000U)
18504#define GPC_ACK_SEL_A53_PU_VPU_PGC_PUP_ACK_SHIFT (26U)
18505#define GPC_ACK_SEL_A53_PU_VPU_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPU_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPU_PGC_PUP_ACK_MASK)
18506#define GPC_ACK_SEL_A53_PU_HDMI_PGC_PUP_ACK_MASK (0x8000000U)
18507#define GPC_ACK_SEL_A53_PU_HDMI_PGC_PUP_ACK_SHIFT (27U)
18508#define GPC_ACK_SEL_A53_PU_HDMI_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_HDMI_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_HDMI_PGC_PUP_ACK_MASK)
18509#define GPC_ACK_SEL_A53_PU_DISP_PGC_PUP_ACK_MASK (0x10000000U)
18510#define GPC_ACK_SEL_A53_PU_DISP_PGC_PUP_ACK_SHIFT (28U)
18511#define GPC_ACK_SEL_A53_PU_DISP_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DISP_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_DISP_PGC_PUP_ACK_MASK)
18512#define GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PUP_ACK_MASK (0x20000000U)
18513#define GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PUP_ACK_SHIFT (29U)
18514#define GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PUP_ACK_MASK)
18515#define GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PUP_ACK_MASK (0x40000000U)
18516#define GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PUP_ACK_SHIFT (30U)
18517#define GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PUP_ACK_MASK)
18518#define GPC_ACK_SEL_A53_PU_PCIE2_PGC_PUP_ACK_MASK (0x80000000U)
18519#define GPC_ACK_SEL_A53_PU_PCIE2_PGC_PUP_ACK_SHIFT (31U)
18520#define GPC_ACK_SEL_A53_PU_PCIE2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_PCIE2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_PCIE2_PGC_PUP_ACK_MASK)
18521/*! @} */
18522
18523/*! @name ACK_SEL_M4_PU - PGC acknowledge signal selection of M4 platform for PUs */
18524/*! @{ */
18525#define GPC_ACK_SEL_M4_PU_MF_PGC_PDN_ACK_MASK (0x1U)
18526#define GPC_ACK_SEL_M4_PU_MF_PGC_PDN_ACK_SHIFT (0U)
18527#define GPC_ACK_SEL_M4_PU_MF_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MF_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MF_PGC_PDN_ACK_MASK)
18528#define GPC_ACK_SEL_M4_PU_MIPI_PGC_PDN_ACK_MASK (0x4U)
18529#define GPC_ACK_SEL_M4_PU_MIPI_PGC_PDN_ACK_SHIFT (2U)
18530#define GPC_ACK_SEL_M4_PU_MIPI_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MIPI_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MIPI_PGC_PDN_ACK_MASK)
18531#define GPC_ACK_SEL_M4_PU_PCIE_PGC_PDN_ACK_MASK (0x8U)
18532#define GPC_ACK_SEL_M4_PU_PCIE_PGC_PDN_ACK_SHIFT (3U)
18533#define GPC_ACK_SEL_M4_PU_PCIE_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_PCIE_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_PCIE_PGC_PDN_ACK_MASK)
18534#define GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PDN_ACK_MASK (0x10U)
18535#define GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PDN_ACK_SHIFT (4U)
18536#define GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PDN_ACK_MASK)
18537#define GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PDN_ACK_MASK (0x20U)
18538#define GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PDN_ACK_SHIFT (5U)
18539#define GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PDN_ACK_MASK)
18540#define GPC_ACK_SEL_M4_PU_DDR1_PGC_PDN_ACK_MASK (0x80U)
18541#define GPC_ACK_SEL_M4_PU_DDR1_PGC_PDN_ACK_SHIFT (7U)
18542#define GPC_ACK_SEL_M4_PU_DDR1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_DDR1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_DDR1_PGC_PDN_ACK_MASK)
18543#define GPC_ACK_SEL_M4_PU_DDR2_PGC_PDN_ACK_MASK (0x100U)
18544#define GPC_ACK_SEL_M4_PU_DDR2_PGC_PDN_ACK_SHIFT (8U)
18545#define GPC_ACK_SEL_M4_PU_DDR2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_DDR2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_DDR2_PGC_PDN_ACK_MASK)
18546#define GPC_ACK_SEL_M4_PU_GPU_PGC_PDN_ACK_MASK (0x200U)
18547#define GPC_ACK_SEL_M4_PU_GPU_PGC_PDN_ACK_SHIFT (9U)
18548#define GPC_ACK_SEL_M4_PU_GPU_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_GPU_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_GPU_PGC_PDN_ACK_MASK)
18549#define GPC_ACK_SEL_M4_PU_VPU_PGC_PDN_ACK_MASK (0x400U)
18550#define GPC_ACK_SEL_M4_PU_VPU_PGC_PDN_ACK_SHIFT (10U)
18551#define GPC_ACK_SEL_M4_PU_VPU_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_VPU_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_VPU_PGC_PDN_ACK_MASK)
18552#define GPC_ACK_SEL_M4_PU_HDMI_PGC_PDN_ACK_MASK (0x800U)
18553#define GPC_ACK_SEL_M4_PU_HDMI_PGC_PDN_ACK_SHIFT (11U)
18554#define GPC_ACK_SEL_M4_PU_HDMI_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_HDMI_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_HDMI_PGC_PDN_ACK_MASK)
18555#define GPC_ACK_SEL_M4_PU_DISP_PGC_PDN_ACK_MASK (0x1000U)
18556#define GPC_ACK_SEL_M4_PU_DISP_PGC_PDN_ACK_SHIFT (12U)
18557#define GPC_ACK_SEL_M4_PU_DISP_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_DISP_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_DISP_PGC_PDN_ACK_MASK)
18558#define GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PDN_ACK_MASK (0x2000U)
18559#define GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PDN_ACK_SHIFT (13U)
18560#define GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PDN_ACK_MASK)
18561#define GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PDN_ACK_MASK (0x4000U)
18562#define GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PDN_ACK_SHIFT (14U)
18563#define GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PDN_ACK_MASK)
18564#define GPC_ACK_SEL_M4_PU_PCIE2_PGC_PDN_ACK_MASK (0x8000U)
18565#define GPC_ACK_SEL_M4_PU_PCIE2_PGC_PDN_ACK_SHIFT (15U)
18566#define GPC_ACK_SEL_M4_PU_PCIE2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_PCIE2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_PCIE2_PGC_PDN_ACK_MASK)
18567#define GPC_ACK_SEL_M4_PU_MF_PGC_PUP_ACK_MASK (0x10000U)
18568#define GPC_ACK_SEL_M4_PU_MF_PGC_PUP_ACK_SHIFT (16U)
18569#define GPC_ACK_SEL_M4_PU_MF_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MF_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MF_PGC_PUP_ACK_MASK)
18570#define GPC_ACK_SEL_M4_PU_MIPI_PGC_PUP_ACK_MASK (0x40000U)
18571#define GPC_ACK_SEL_M4_PU_MIPI_PGC_PUP_ACK_SHIFT (18U)
18572#define GPC_ACK_SEL_M4_PU_MIPI_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MIPI_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MIPI_PGC_PUP_ACK_MASK)
18573#define GPC_ACK_SEL_M4_PU_PCIE_PGC_PUP_ACK_MASK (0x80000U)
18574#define GPC_ACK_SEL_M4_PU_PCIE_PGC_PUP_ACK_SHIFT (19U)
18575#define GPC_ACK_SEL_M4_PU_PCIE_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_PCIE_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_PCIE_PGC_PUP_ACK_MASK)
18576#define GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PUP_ACK_MASK (0x100000U)
18577#define GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PUP_ACK_SHIFT (20U)
18578#define GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PUP_ACK_MASK)
18579#define GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PUP_ACK_MASK (0x200000U)
18580#define GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PUP_ACK_SHIFT (21U)
18581#define GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PUP_ACK_MASK)
18582#define GPC_ACK_SEL_M4_PU_DDR1_PGC_PUP_ACK_MASK (0x800000U)
18583#define GPC_ACK_SEL_M4_PU_DDR1_PGC_PUP_ACK_SHIFT (23U)
18584#define GPC_ACK_SEL_M4_PU_DDR1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_DDR1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_DDR1_PGC_PUP_ACK_MASK)
18585#define GPC_ACK_SEL_M4_PU_DDR2_PGC_PUP_ACK_MASK (0x1000000U)
18586#define GPC_ACK_SEL_M4_PU_DDR2_PGC_PUP_ACK_SHIFT (24U)
18587#define GPC_ACK_SEL_M4_PU_DDR2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_DDR2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_DDR2_PGC_PUP_ACK_MASK)
18588#define GPC_ACK_SEL_M4_PU_GPU_PGC_PUP_ACK_MASK (0x2000000U)
18589#define GPC_ACK_SEL_M4_PU_GPU_PGC_PUP_ACK_SHIFT (25U)
18590#define GPC_ACK_SEL_M4_PU_GPU_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_GPU_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_GPU_PGC_PUP_ACK_MASK)
18591#define GPC_ACK_SEL_M4_PU_VPU_PGC_PUP_ACK_MASK (0x4000000U)
18592#define GPC_ACK_SEL_M4_PU_VPU_PGC_PUP_ACK_SHIFT (26U)
18593#define GPC_ACK_SEL_M4_PU_VPU_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_VPU_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_VPU_PGC_PUP_ACK_MASK)
18594#define GPC_ACK_SEL_M4_PU_HDMI_PGC_PUP_ACK_MASK (0x8000000U)
18595#define GPC_ACK_SEL_M4_PU_HDMI_PGC_PUP_ACK_SHIFT (27U)
18596#define GPC_ACK_SEL_M4_PU_HDMI_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_HDMI_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_HDMI_PGC_PUP_ACK_MASK)
18597#define GPC_ACK_SEL_M4_PU_DISP_PGC_PUP_ACK_MASK (0x10000000U)
18598#define GPC_ACK_SEL_M4_PU_DISP_PGC_PUP_ACK_SHIFT (28U)
18599#define GPC_ACK_SEL_M4_PU_DISP_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_DISP_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_DISP_PGC_PUP_ACK_MASK)
18600#define GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PUP_ACK_MASK (0x20000000U)
18601#define GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PUP_ACK_SHIFT (29U)
18602#define GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PUP_ACK_MASK)
18603#define GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PUP_ACK_MASK (0x40000000U)
18604#define GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PUP_ACK_SHIFT (30U)
18605#define GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PUP_ACK_MASK)
18606#define GPC_ACK_SEL_M4_PU_PCIE2_PGC_PUP_ACK_MASK (0x80000000U)
18607#define GPC_ACK_SEL_M4_PU_PCIE2_PGC_PUP_ACK_SHIFT (31U)
18608#define GPC_ACK_SEL_M4_PU_PCIE2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_PCIE2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_PCIE2_PGC_PUP_ACK_MASK)
18609/*! @} */
18610
18611/*! @name SLT15_CFG - Slot configure register for A53 core */
18612/*! @{ */
18613#define GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
18614#define GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
18615#define GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
18616#define GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
18617#define GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
18618#define GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
18619#define GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
18620#define GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
18621#define GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
18622#define GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
18623#define GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
18624#define GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
18625#define GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
18626#define GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
18627#define GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
18628#define GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
18629#define GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
18630#define GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
18631#define GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
18632#define GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
18633#define GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
18634#define GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
18635#define GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
18636#define GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
18637#define GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
18638#define GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
18639#define GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_MASK)
18640#define GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
18641#define GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
18642#define GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_MASK)
18643/*! @} */
18644
18645/*! @name SLT16_CFG - Slot configure register for A53 core */
18646/*! @{ */
18647#define GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
18648#define GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
18649#define GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
18650#define GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
18651#define GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
18652#define GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
18653#define GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
18654#define GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
18655#define GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
18656#define GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
18657#define GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
18658#define GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
18659#define GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
18660#define GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
18661#define GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
18662#define GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
18663#define GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
18664#define GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
18665#define GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
18666#define GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
18667#define GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
18668#define GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
18669#define GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
18670#define GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
18671#define GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
18672#define GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
18673#define GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_MASK)
18674#define GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
18675#define GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
18676#define GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_MASK)
18677/*! @} */
18678
18679/*! @name SLT17_CFG - Slot configure register for A53 core */
18680/*! @{ */
18681#define GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
18682#define GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
18683#define GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
18684#define GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
18685#define GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
18686#define GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
18687#define GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
18688#define GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
18689#define GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
18690#define GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
18691#define GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
18692#define GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
18693#define GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
18694#define GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
18695#define GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
18696#define GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
18697#define GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
18698#define GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
18699#define GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
18700#define GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
18701#define GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
18702#define GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
18703#define GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
18704#define GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
18705#define GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
18706#define GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
18707#define GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_MASK)
18708#define GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
18709#define GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
18710#define GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_MASK)
18711/*! @} */
18712
18713/*! @name SLT18_CFG - Slot configure register for A53 core */
18714/*! @{ */
18715#define GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
18716#define GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
18717#define GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
18718#define GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
18719#define GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
18720#define GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
18721#define GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
18722#define GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
18723#define GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
18724#define GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
18725#define GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
18726#define GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
18727#define GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
18728#define GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
18729#define GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
18730#define GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
18731#define GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
18732#define GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
18733#define GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
18734#define GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
18735#define GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
18736#define GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
18737#define GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
18738#define GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
18739#define GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
18740#define GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
18741#define GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_MASK)
18742#define GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
18743#define GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
18744#define GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_MASK)
18745/*! @} */
18746
18747/*! @name SLT19_CFG - Slot configure register for A53 core */
18748/*! @{ */
18749#define GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
18750#define GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
18751#define GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
18752#define GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
18753#define GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
18754#define GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
18755#define GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
18756#define GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
18757#define GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
18758#define GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
18759#define GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
18760#define GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
18761#define GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
18762#define GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
18763#define GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
18764#define GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
18765#define GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
18766#define GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
18767#define GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
18768#define GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
18769#define GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
18770#define GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
18771#define GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
18772#define GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
18773#define GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
18774#define GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
18775#define GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_MASK)
18776#define GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
18777#define GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
18778#define GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_MASK)
18779/*! @} */
18780
18781/*! @name PU_PWRHSK - Power handshake register */
18782/*! @{ */
18783#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_MASK (0x1U)
18784#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_SHIFT (0U)
18785#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_MASK)
18786#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_MASK (0x2U)
18787#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_SHIFT (1U)
18788#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_MASK)
18789#define GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSREQ_MASK (0x4U)
18790#define GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSREQ_SHIFT (2U)
18791#define GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSREQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSREQ_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSREQ_MASK)
18792#define GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSREQ_MASK (0x8U)
18793#define GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSREQ_SHIFT (3U)
18794#define GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSREQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSREQ_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSREQ_MASK)
18795#define GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNREQN_MASK (0x10U)
18796#define GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNREQN_SHIFT (4U)
18797#define GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNREQN_MASK)
18798#define GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNREQN_MASK (0x20U)
18799#define GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNREQN_SHIFT (5U)
18800#define GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNREQN_MASK)
18801#define GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNREQN_MASK (0x40U)
18802#define GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNREQN_SHIFT (6U)
18803#define GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNREQN_MASK)
18804#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_MASK (0x10000U)
18805#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_SHIFT (16U)
18806#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_MASK)
18807#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_MASK (0x20000U)
18808#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_SHIFT (17U)
18809#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_MASK)
18810#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_MASK (0x40000U)
18811#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_SHIFT (18U)
18812#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_MASK)
18813#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_MASK (0x80000U)
18814#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_SHIFT (19U)
18815#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_MASK)
18816#define GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSACK_MASK (0x100000U)
18817#define GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSACK_SHIFT (20U)
18818#define GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSACK_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSACK_MASK)
18819#define GPC_PU_PWRHSK_GPC_DDR2_CORE_CACTIVE_MASK (0x200000U)
18820#define GPC_PU_PWRHSK_GPC_DDR2_CORE_CACTIVE_SHIFT (21U)
18821#define GPC_PU_PWRHSK_GPC_DDR2_CORE_CACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR2_CORE_CACTIVE_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR2_CORE_CACTIVE_MASK)
18822#define GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSACK_MASK (0x400000U)
18823#define GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSACK_SHIFT (22U)
18824#define GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSACK_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSACK_MASK)
18825#define GPC_PU_PWRHSK_GPC_DDR2_AXI_CACTIVE_MASK (0x800000U)
18826#define GPC_PU_PWRHSK_GPC_DDR2_AXI_CACTIVE_SHIFT (23U)
18827#define GPC_PU_PWRHSK_GPC_DDR2_AXI_CACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR2_AXI_CACTIVE_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR2_AXI_CACTIVE_MASK)
18828#define GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNACKN_MASK (0x1000000U)
18829#define GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNACKN_SHIFT (24U)
18830#define GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNACKN_MASK)
18831#define GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNACKN_MASK (0x2000000U)
18832#define GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNACKN_SHIFT (25U)
18833#define GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNACKN_MASK)
18834#define GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNACKN_MASK (0x4000000U)
18835#define GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNACKN_SHIFT (26U)
18836#define GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNACKN_MASK)
18837/*! @} */
18838
18839/*! @name SLT_CFG_PU - Slot configure register for PUs */
18840/*! @{ */
18841#define GPC_SLT_CFG_PU_MF_PDN_SLOT_CONTROL_MASK (0x1U)
18842#define GPC_SLT_CFG_PU_MF_PDN_SLOT_CONTROL_SHIFT (0U)
18843#define GPC_SLT_CFG_PU_MF_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MF_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MF_PDN_SLOT_CONTROL_MASK)
18844#define GPC_SLT_CFG_PU_MF_PUP_SLOT_CONTROL_MASK (0x2U)
18845#define GPC_SLT_CFG_PU_MF_PUP_SLOT_CONTROL_SHIFT (1U)
18846#define GPC_SLT_CFG_PU_MF_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MF_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MF_PUP_SLOT_CONTROL_MASK)
18847#define GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_MASK (0x4U)
18848#define GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_SHIFT (2U)
18849#define GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_MASK)
18850#define GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_MASK (0x8U)
18851#define GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_SHIFT (3U)
18852#define GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_MASK)
18853#define GPC_SLT_CFG_PU_PCIE_PDN_SLOT_CONTROL_MASK (0x10U)
18854#define GPC_SLT_CFG_PU_PCIE_PDN_SLOT_CONTROL_SHIFT (4U)
18855#define GPC_SLT_CFG_PU_PCIE_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_PCIE_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_PCIE_PDN_SLOT_CONTROL_MASK)
18856#define GPC_SLT_CFG_PU_PCIE_PUP_SLOT_CONTROL_MASK (0x20U)
18857#define GPC_SLT_CFG_PU_PCIE_PUP_SLOT_CONTROL_SHIFT (5U)
18858#define GPC_SLT_CFG_PU_PCIE_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_PCIE_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_PCIE_PUP_SLOT_CONTROL_MASK)
18859#define GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_MASK (0x40U)
18860#define GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_SHIFT (6U)
18861#define GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_MASK)
18862#define GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_MASK (0x80U)
18863#define GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_SHIFT (7U)
18864#define GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_MASK)
18865#define GPC_SLT_CFG_PU_OTG2_PDN_SLOT_CONTROL_MASK (0x100U)
18866#define GPC_SLT_CFG_PU_OTG2_PDN_SLOT_CONTROL_SHIFT (8U)
18867#define GPC_SLT_CFG_PU_OTG2_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_OTG2_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_OTG2_PDN_SLOT_CONTROL_MASK)
18868#define GPC_SLT_CFG_PU_OTG2_PUP_SLOT_CONTROL_MASK (0x200U)
18869#define GPC_SLT_CFG_PU_OTG2_PUP_SLOT_CONTROL_SHIFT (9U)
18870#define GPC_SLT_CFG_PU_OTG2_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_OTG2_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_OTG2_PUP_SLOT_CONTROL_MASK)
18871#define GPC_SLT_CFG_PU_M4_PDN_SLOT_CONTROL_MASK (0x1000U)
18872#define GPC_SLT_CFG_PU_M4_PDN_SLOT_CONTROL_SHIFT (12U)
18873#define GPC_SLT_CFG_PU_M4_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_M4_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_M4_PDN_SLOT_CONTROL_MASK)
18874#define GPC_SLT_CFG_PU_M4_PUP_SLOT_CONTROL_MASK (0x2000U)
18875#define GPC_SLT_CFG_PU_M4_PUP_SLOT_CONTROL_SHIFT (13U)
18876#define GPC_SLT_CFG_PU_M4_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_M4_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_M4_PUP_SLOT_CONTROL_MASK)
18877#define GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_MASK (0x4000U)
18878#define GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_SHIFT (14U)
18879#define GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_MASK)
18880#define GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_MASK (0x8000U)
18881#define GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_SHIFT (15U)
18882#define GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_MASK)
18883#define GPC_SLT_CFG_PU_DDR2_PDN_SLOT_CONTROL_MASK (0x10000U)
18884#define GPC_SLT_CFG_PU_DDR2_PDN_SLOT_CONTROL_SHIFT (16U)
18885#define GPC_SLT_CFG_PU_DDR2_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DDR2_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_DDR2_PDN_SLOT_CONTROL_MASK)
18886#define GPC_SLT_CFG_PU_DDR2_PUP_SLOT_CONTROL_MASK (0x20000U)
18887#define GPC_SLT_CFG_PU_DDR2_PUP_SLOT_CONTROL_SHIFT (17U)
18888#define GPC_SLT_CFG_PU_DDR2_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DDR2_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_DDR2_PUP_SLOT_CONTROL_MASK)
18889#define GPC_SLT_CFG_PU_GPU_PDN_SLOT_CONTROL_MASK (0x40000U)
18890#define GPC_SLT_CFG_PU_GPU_PDN_SLOT_CONTROL_SHIFT (18U)
18891#define GPC_SLT_CFG_PU_GPU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_GPU_PDN_SLOT_CONTROL_MASK)
18892#define GPC_SLT_CFG_PU_GPU_PUP_SLOT_CONTROL_MASK (0x80000U)
18893#define GPC_SLT_CFG_PU_GPU_PUP_SLOT_CONTROL_SHIFT (19U)
18894#define GPC_SLT_CFG_PU_GPU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_GPU_PUP_SLOT_CONTROL_MASK)
18895#define GPC_SLT_CFG_PU_VPU_PDN_SLOT_CONTROL_MASK (0x100000U)
18896#define GPC_SLT_CFG_PU_VPU_PDN_SLOT_CONTROL_SHIFT (20U)
18897#define GPC_SLT_CFG_PU_VPU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPU_PDN_SLOT_CONTROL_MASK)
18898#define GPC_SLT_CFG_PU_VPU_PUP_SLOT_CONTROL_MASK (0x200000U)
18899#define GPC_SLT_CFG_PU_VPU_PUP_SLOT_CONTROL_SHIFT (21U)
18900#define GPC_SLT_CFG_PU_VPU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPU_PUP_SLOT_CONTROL_MASK)
18901#define GPC_SLT_CFG_PU_HDMI_PDN_SLOT_CONTROL_MASK (0x400000U)
18902#define GPC_SLT_CFG_PU_HDMI_PDN_SLOT_CONTROL_SHIFT (22U)
18903#define GPC_SLT_CFG_PU_HDMI_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_HDMI_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_HDMI_PDN_SLOT_CONTROL_MASK)
18904#define GPC_SLT_CFG_PU_HDMI_PUP_SLOT_CONTROL_MASK (0x800000U)
18905#define GPC_SLT_CFG_PU_HDMI_PUP_SLOT_CONTROL_SHIFT (23U)
18906#define GPC_SLT_CFG_PU_HDMI_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_HDMI_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_HDMI_PUP_SLOT_CONTROL_MASK)
18907#define GPC_SLT_CFG_PU_DISP_PDN_SLOT_CONTROL_MASK (0x1000000U)
18908#define GPC_SLT_CFG_PU_DISP_PDN_SLOT_CONTROL_SHIFT (24U)
18909#define GPC_SLT_CFG_PU_DISP_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DISP_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_DISP_PDN_SLOT_CONTROL_MASK)
18910#define GPC_SLT_CFG_PU_DISP_PUP_SLOT_CONTROL_MASK (0x2000000U)
18911#define GPC_SLT_CFG_PU_DISP_PUP_SLOT_CONTROL_SHIFT (25U)
18912#define GPC_SLT_CFG_PU_DISP_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DISP_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_DISP_PUP_SLOT_CONTROL_MASK)
18913#define GPC_SLT_CFG_PU_MIPI_CSI1_PDN_SLOT_CONTROL_MASK (0x4000000U)
18914#define GPC_SLT_CFG_PU_MIPI_CSI1_PDN_SLOT_CONTROL_SHIFT (26U)
18915#define GPC_SLT_CFG_PU_MIPI_CSI1_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_CSI1_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_CSI1_PDN_SLOT_CONTROL_MASK)
18916#define GPC_SLT_CFG_PU_MIPI_CSI1_PUP_SLOT_CONTROL_MASK (0x8000000U)
18917#define GPC_SLT_CFG_PU_MIPI_CSI1_PUP_SLOT_CONTROL_SHIFT (27U)
18918#define GPC_SLT_CFG_PU_MIPI_CSI1_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_CSI1_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_CSI1_PUP_SLOT_CONTROL_MASK)
18919#define GPC_SLT_CFG_PU_MIPI_CSI2_PDN_SLOT_CONTROL_MASK (0x10000000U)
18920#define GPC_SLT_CFG_PU_MIPI_CSI2_PDN_SLOT_CONTROL_SHIFT (28U)
18921#define GPC_SLT_CFG_PU_MIPI_CSI2_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_CSI2_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_CSI2_PDN_SLOT_CONTROL_MASK)
18922#define GPC_SLT_CFG_PU_MIPI_CSI2_PUP_SLOT_CONTROL_MASK (0x20000000U)
18923#define GPC_SLT_CFG_PU_MIPI_CSI2_PUP_SLOT_CONTROL_SHIFT (29U)
18924#define GPC_SLT_CFG_PU_MIPI_CSI2_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_CSI2_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_CSI2_PUP_SLOT_CONTROL_MASK)
18925#define GPC_SLT_CFG_PU_PCIE2_PDN_SLOT_CONTROL_MASK (0x40000000U)
18926#define GPC_SLT_CFG_PU_PCIE2_PDN_SLOT_CONTROL_SHIFT (30U)
18927#define GPC_SLT_CFG_PU_PCIE2_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_PCIE2_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_PCIE2_PDN_SLOT_CONTROL_MASK)
18928#define GPC_SLT_CFG_PU_PCIE2_PUP_SLOT_CONTROL_MASK (0x80000000U)
18929#define GPC_SLT_CFG_PU_PCIE2_PUP_SLOT_CONTROL_SHIFT (31U)
18930#define GPC_SLT_CFG_PU_PCIE2_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_PCIE2_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_PCIE2_PUP_SLOT_CONTROL_MASK)
18931/*! @} */
18932
18933/* The count of GPC_SLT_CFG_PU */
18934#define GPC_SLT_CFG_PU_COUNT (20U)
18935
18936
18937/*!
18938 * @}
18939 */ /* end of group GPC_Register_Masks */
18940
18941
18942/* GPC - Peripheral instance base addresses */
18943/** Peripheral GPC base address */
18944#define GPC_BASE (0x303A0000u)
18945/** Peripheral GPC base pointer */
18946#define GPC ((GPC_Type *)GPC_BASE)
18947/** Array initializer of GPC peripheral base addresses */
18948#define GPC_BASE_ADDRS { GPC_BASE }
18949/** Array initializer of GPC peripheral base pointers */
18950#define GPC_BASE_PTRS { GPC }
18951/** Interrupt vectors for the GPC peripheral type */
18952#define GPC_IRQS { GPC_IRQn }
18953
18954/*!
18955 * @}
18956 */ /* end of group GPC_Peripheral_Access_Layer */
18957
18958
18959/* ----------------------------------------------------------------------------
18960 -- GPC_PGC Peripheral Access Layer
18961 ---------------------------------------------------------------------------- */
18962
18963/*!
18964 * @addtogroup GPC_PGC_Peripheral_Access_Layer GPC_PGC Peripheral Access Layer
18965 * @{
18966 */
18967
18968/** GPC_PGC - Register Layout Typedef */
18969typedef struct {
18970 __IO uint32_t A53CORE0_CTRL; /**< GPC PGC Control Register, offset: 0x0 */
18971 __IO uint32_t A53CORE0_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x4 */
18972 __IO uint32_t A53CORE0_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x8 */
18973 __IO uint32_t A53CORE0_SR; /**< GPC PGC Status Register, offset: 0xC */
18974 __IO uint32_t A53CORE0_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x10 */
18975 uint8_t RESERVED_0[44];
18976 __IO uint32_t A53CORE1_CTRL; /**< GPC PGC Control Register, offset: 0x40 */
18977 __IO uint32_t A53CORE1_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x44 */
18978 __IO uint32_t A53CORE1_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x48 */
18979 __IO uint32_t A53CORE1_SR; /**< GPC PGC Status Register, offset: 0x4C */
18980 __IO uint32_t A53CORE1_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x50 */
18981 uint8_t RESERVED_1[44];
18982 __IO uint32_t A53CORE2_CTRL; /**< GPC PGC Control Register, offset: 0x80 */
18983 __IO uint32_t A53CORE2_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x84 */
18984 __IO uint32_t A53CORE2_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x88 */
18985 __IO uint32_t A53CORE2_SR; /**< GPC PGC Status Register, offset: 0x8C */
18986 __IO uint32_t A53CORE2_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x90 */
18987 uint8_t RESERVED_2[44];
18988 __IO uint32_t A53CORE3_CTRL; /**< GPC PGC Control Register, offset: 0xC0 */
18989 __IO uint32_t A53CORE3_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0xC4 */
18990 __IO uint32_t A53CORE3_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0xC8 */
18991 __IO uint32_t A53CORE3_SR; /**< GPC PGC Status Register, offset: 0xCC */
18992 __IO uint32_t A53CORE3_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0xD0 */
18993 uint8_t RESERVED_3[44];
18994 __IO uint32_t A53SCU_CTRL; /**< GPC PGC Control Register, offset: 0x100 */
18995 __IO uint32_t A53SCU_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x104 */
18996 __IO uint32_t A53SCU_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x108 */
18997 __IO uint32_t A53SCU_SR; /**< GPC PGC Status Register, offset: 0x10C */
18998 __IO uint32_t A53SCU_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x110 */
18999 uint8_t RESERVED_4[236];
19000 __IO uint32_t MIX_CTRL; /**< GPC PGC Control Register, offset: 0x200 */
19001 __IO uint32_t MIX_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x204 */
19002 __IO uint32_t MIX_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x208 */
19003 __IO uint32_t MIX_SR; /**< GPC PGC Status Register, offset: 0x20C */
19004 __IO uint32_t MIX_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x210 */
19005 uint8_t RESERVED_5[492];
19006 __IO uint32_t PU0_CTRL; /**< GPC PGC Control Register, offset: 0x400 */
19007 __IO uint32_t PU0_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x404 */
19008 __IO uint32_t PU0_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x408 */
19009 __IO uint32_t PU0_SR; /**< GPC PGC Status Register, offset: 0x40C */
19010 __IO uint32_t PU0_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x410 */
19011 uint8_t RESERVED_6[44];
19012 __IO uint32_t PU1_CTRL; /**< GPC PGC Control Register, offset: 0x440 */
19013 __IO uint32_t PU1_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x444 */
19014 __IO uint32_t PU1_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x448 */
19015 __IO uint32_t PU1_SR; /**< GPC PGC Status Register, offset: 0x44C */
19016 __IO uint32_t PU1_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x450 */
19017 uint8_t RESERVED_7[44];
19018 __IO uint32_t PU2_CTRL; /**< GPC PGC Control Register, offset: 0x480 */
19019 __IO uint32_t PU2_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x484 */
19020 __IO uint32_t PU2_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x488 */
19021 __IO uint32_t PU2_SR; /**< GPC PGC Status Register, offset: 0x48C */
19022 __IO uint32_t PU2_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x490 */
19023 uint8_t RESERVED_8[44];
19024 __IO uint32_t PU3_CTRL; /**< GPC PGC Control Register, offset: 0x4C0 */
19025 __IO uint32_t PU3_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x4C4 */
19026 __IO uint32_t PU3_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x4C8 */
19027 __IO uint32_t PU3_SR; /**< GPC PGC Status Register, offset: 0x4CC */
19028 __IO uint32_t PU3_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x4D0 */
19029 uint8_t RESERVED_9[44];
19030 __IO uint32_t PU4_CTRL; /**< GPC PGC Control Register, offset: 0x500 */
19031 __IO uint32_t PU4_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x504 */
19032 __IO uint32_t PU4_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x508 */
19033 __IO uint32_t PU4_SR; /**< GPC PGC Status Register, offset: 0x50C */
19034 __IO uint32_t PU4_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x510 */
19035 uint8_t RESERVED_10[44];
19036 __IO uint32_t PU5_CTRL; /**< GPC PGC Control Register, offset: 0x540 */
19037 __IO uint32_t PU5_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x544 */
19038 __IO uint32_t PU5_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x548 */
19039 __IO uint32_t PU5_SR; /**< GPC PGC Status Register, offset: 0x54C */
19040 __IO uint32_t PU5_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x550 */
19041 uint8_t RESERVED_11[44];
19042 __IO uint32_t PU6_CTRL; /**< GPC PGC Control Register, offset: 0x580 */
19043 __IO uint32_t PU6_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x584 */
19044 __IO uint32_t PU6_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x588 */
19045 __IO uint32_t PU6_SR; /**< GPC PGC Status Register, offset: 0x58C */
19046 __IO uint32_t PU6_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x590 */
19047 uint8_t RESERVED_12[44];
19048 __IO uint32_t PU7_CTRL; /**< GPC PGC Control Register, offset: 0x5C0 */
19049 __IO uint32_t PU7_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x5C4 */
19050 __IO uint32_t PU7_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x5C8 */
19051 __IO uint32_t PU7_SR; /**< GPC PGC Status Register, offset: 0x5CC */
19052 __IO uint32_t PU7_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x5D0 */
19053 uint8_t RESERVED_13[44];
19054 __IO uint32_t PU8_CTRL; /**< GPC PGC Control Register, offset: 0x600 */
19055 __IO uint32_t PU8_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x604 */
19056 __IO uint32_t PU8_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x608 */
19057 __IO uint32_t PU8_SR; /**< GPC PGC Status Register, offset: 0x60C */
19058 __IO uint32_t PU8_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x610 */
19059 uint8_t RESERVED_14[44];
19060 __IO uint32_t PU9_CTRL; /**< GPC PGC Control Register, offset: 0x640 */
19061 __IO uint32_t PU9_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x644 */
19062 __IO uint32_t PU9_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x648 */
19063 __IO uint32_t PU9_SR; /**< GPC PGC Status Register, offset: 0x64C */
19064 __IO uint32_t PU9_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x650 */
19065 uint8_t RESERVED_15[44];
19066 __IO uint32_t PU10_CTRL; /**< GPC PGC Control Register, offset: 0x680 */
19067 __IO uint32_t PU10_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x684 */
19068 __IO uint32_t PU10_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x688 */
19069 __IO uint32_t PU10_SR; /**< GPC PGC Status Register, offset: 0x68C */
19070 __IO uint32_t PU10_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x690 */
19071 uint8_t RESERVED_16[44];
19072 __IO uint32_t PU11_CTRL; /**< GPC PGC Control Register, offset: 0x6C0 */
19073 __IO uint32_t PU11_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x6C4 */
19074 __IO uint32_t PU11_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x6C8 */
19075 __IO uint32_t PU11_SR; /**< GPC PGC Status Register, offset: 0x6CC */
19076 __IO uint32_t PU11_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x6D0 */
19077 uint8_t RESERVED_17[44];
19078 __IO uint32_t PU12_CTRL; /**< GPC PGC Control Register, offset: 0x700 */
19079 __IO uint32_t PU12_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x704 */
19080 __IO uint32_t PU12_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x708 */
19081 __IO uint32_t PU12_SR; /**< GPC PGC Status Register, offset: 0x70C */
19082 __IO uint32_t PU12_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x710 */
19083 uint8_t RESERVED_18[44];
19084 __IO uint32_t PU13_CTRL; /**< GPC PGC Control Register, offset: 0x740 */
19085 __IO uint32_t PU13_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x744 */
19086 __IO uint32_t PU13_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x748 */
19087 __IO uint32_t PU13_SR; /**< GPC PGC Status Register, offset: 0x74C */
19088 __IO uint32_t PU13_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x750 */
19089} GPC_PGC_Type;
19090
19091/* ----------------------------------------------------------------------------
19092 -- GPC_PGC Register Masks
19093 ---------------------------------------------------------------------------- */
19094
19095/*!
19096 * @addtogroup GPC_PGC_Register_Masks GPC_PGC Register Masks
19097 * @{
19098 */
19099
19100/*! @name A53CORE0_CTRL - GPC PGC Control Register */
19101/*! @{ */
19102#define GPC_PGC_A53CORE0_CTRL_PCR_MASK (0x1U)
19103#define GPC_PGC_A53CORE0_CTRL_PCR_SHIFT (0U)
19104/*! PCR
19105 * 0b0..Do not switch off power even if pdn_req is asserted.
19106 * 0b1..Switch off power when pdn_req is asserted.
19107 */
19108#define GPC_PGC_A53CORE0_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_CTRL_PCR_SHIFT)) & GPC_PGC_A53CORE0_CTRL_PCR_MASK)
19109#define GPC_PGC_A53CORE0_CTRL_L2RSTDIS_MASK (0x7EU)
19110#define GPC_PGC_A53CORE0_CTRL_L2RSTDIS_SHIFT (1U)
19111#define GPC_PGC_A53CORE0_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53CORE0_CTRL_L2RSTDIS_MASK)
19112#define GPC_PGC_A53CORE0_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
19113#define GPC_PGC_A53CORE0_CTRL_DFTRAM_TCD1_SHIFT (8U)
19114#define GPC_PGC_A53CORE0_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53CORE0_CTRL_DFTRAM_TCD1_MASK)
19115#define GPC_PGC_A53CORE0_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
19116#define GPC_PGC_A53CORE0_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
19117#define GPC_PGC_A53CORE0_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_A53CORE0_CTRL_L2RETN_TCD1_TDR_MASK)
19118#define GPC_PGC_A53CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
19119#define GPC_PGC_A53CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
19120#define GPC_PGC_A53CORE0_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_A53CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
19121/*! @} */
19122
19123/*! @name A53CORE0_PUPSCR - GPC PGC Up Sequence Control Register */
19124/*! @{ */
19125#define GPC_PGC_A53CORE0_PUPSCR_SW_MASK (0x3FU)
19126#define GPC_PGC_A53CORE0_PUPSCR_SW_SHIFT (0U)
19127#define GPC_PGC_A53CORE0_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PUPSCR_SW_SHIFT)) & GPC_PGC_A53CORE0_PUPSCR_SW_MASK)
19128#define GPC_PGC_A53CORE0_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
19129#define GPC_PGC_A53CORE0_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
19130#define GPC_PGC_A53CORE0_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE0_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
19131#define GPC_PGC_A53CORE0_PUPSCR_SW2ISO_MASK (0x7FFF80U)
19132#define GPC_PGC_A53CORE0_PUPSCR_SW2ISO_SHIFT (7U)
19133#define GPC_PGC_A53CORE0_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53CORE0_PUPSCR_SW2ISO_MASK)
19134#define GPC_PGC_A53CORE0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
19135#define GPC_PGC_A53CORE0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
19136#define GPC_PGC_A53CORE0_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
19137/*! @} */
19138
19139/*! @name A53CORE0_PDNSCR - GPC PGC Down Sequence Control Register */
19140/*! @{ */
19141#define GPC_PGC_A53CORE0_PDNSCR_ISO_MASK (0x3FU)
19142#define GPC_PGC_A53CORE0_PDNSCR_ISO_SHIFT (0U)
19143#define GPC_PGC_A53CORE0_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53CORE0_PDNSCR_ISO_MASK)
19144#define GPC_PGC_A53CORE0_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
19145#define GPC_PGC_A53CORE0_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
19146#define GPC_PGC_A53CORE0_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE0_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
19147#define GPC_PGC_A53CORE0_PDNSCR_ISO2SW_MASK (0x3F00U)
19148#define GPC_PGC_A53CORE0_PDNSCR_ISO2SW_SHIFT (8U)
19149#define GPC_PGC_A53CORE0_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53CORE0_PDNSCR_ISO2SW_MASK)
19150#define GPC_PGC_A53CORE0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
19151#define GPC_PGC_A53CORE0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
19152#define GPC_PGC_A53CORE0_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
19153#define GPC_PGC_A53CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
19154#define GPC_PGC_A53CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
19155#define GPC_PGC_A53CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_A53CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
19156/*! @} */
19157
19158/*! @name A53CORE0_SR - GPC PGC Status Register */
19159/*! @{ */
19160#define GPC_PGC_A53CORE0_SR_PSR_MASK (0x1U)
19161#define GPC_PGC_A53CORE0_SR_PSR_SHIFT (0U)
19162/*! PSR
19163 * 0b0..The target subsystem was not powered down for the previous power-down request.
19164 * 0b1..The target subsystem was powered down for the previous power-down request.
19165 */
19166#define GPC_PGC_A53CORE0_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_SR_PSR_SHIFT)) & GPC_PGC_A53CORE0_SR_PSR_MASK)
19167#define GPC_PGC_A53CORE0_SR_L2RETN_FLAG_MASK (0x2U)
19168#define GPC_PGC_A53CORE0_SR_L2RETN_FLAG_SHIFT (1U)
19169/*! L2RETN_FLAG
19170 * 0b0..A53 is not wakeup from L2 retention mode.
19171 * 0b1..A53 is wakeup from L2 retention mode.
19172 */
19173#define GPC_PGC_A53CORE0_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53CORE0_SR_L2RETN_FLAG_MASK)
19174#define GPC_PGC_A53CORE0_SR_ALLOFF_FLAG_MASK (0x4U)
19175#define GPC_PGC_A53CORE0_SR_ALLOFF_FLAG_SHIFT (2U)
19176/*! ALLOFF_FLAG
19177 * 0b0..A53 is not wakeup from ALL_OFF mode.
19178 * 0b1..A53 is wakeup from ALL_OFF mode.
19179 */
19180#define GPC_PGC_A53CORE0_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53CORE0_SR_ALLOFF_FLAG_MASK)
19181#define GPC_PGC_A53CORE0_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
19182#define GPC_PGC_A53CORE0_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
19183/*! PUP_CLK_DIV_SEL
19184 * 0b0000..1
19185 * 0b0001..1/2 count_clk
19186 * 0b0010..1/4 count_clk
19187 * 0b0011..1/8 count_clk
19188 * 0b0100..1/16 count_clk
19189 * 0b0101..1/32 count_clk
19190 * 0b0110..1/64 count_clk
19191 * 0b0111..1/128 count_clk
19192 * 0b1000..1/256 count_clk
19193 * 0b1001..1/512 count_clk
19194 * 0b1010..1/1024 count_clk
19195 * 0b1011..1/2056 count_clk
19196 * 0b1100..1/4096 count_clk
19197 * 0b1101..1/8192 count_clk
19198 * 0b1110..1/16384 count_clk
19199 * 0b1111..1/32768 count_clk
19200 */
19201#define GPC_PGC_A53CORE0_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE0_SR_PUP_CLK_DIV_SEL_MASK)
19202#define GPC_PGC_A53CORE0_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
19203#define GPC_PGC_A53CORE0_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
19204#define GPC_PGC_A53CORE0_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_A53CORE0_SR_L2RSTDIS_DEASSERT_CNT_MASK)
19205/*! @} */
19206
19207/*! @name A53CORE0_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
19208/*! @{ */
19209#define GPC_PGC_A53CORE0_AUXSW_SW2_MASK (0x3FU)
19210#define GPC_PGC_A53CORE0_AUXSW_SW2_SHIFT (0U)
19211#define GPC_PGC_A53CORE0_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_AUXSW_SW2_SHIFT)) & GPC_PGC_A53CORE0_AUXSW_SW2_MASK)
19212#define GPC_PGC_A53CORE0_AUXSW_ISO2SW2_MASK (0x3F00U)
19213#define GPC_PGC_A53CORE0_AUXSW_ISO2SW2_SHIFT (8U)
19214/*! ISO2SW2
19215 * 0b000000..A53 is not wakeup from ALL_OFF mode.
19216 * 0b000001..A53 is wakeup from ALL_OFF mode.
19217 */
19218#define GPC_PGC_A53CORE0_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_A53CORE0_AUXSW_ISO2SW2_MASK)
19219#define GPC_PGC_A53CORE0_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
19220#define GPC_PGC_A53CORE0_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
19221/*! PDN_CLK_DIV_SEL
19222 * 0b0000..1
19223 * 0b0001..1/2 count_clk
19224 * 0b0010..1/4 count_clk
19225 * 0b0011..1/8 count_clk
19226 * 0b0100..1/16 count_clk
19227 * 0b0101..1/32 count_clk
19228 * 0b0110..1/64 count_clk
19229 * 0b0111..1/128 count_clk
19230 * 0b1000..1/256 count_clk
19231 * 0b1001..1/512 count_clk
19232 * 0b1010..1/1024 count_clk
19233 * 0b1011..1/2056 count_clk
19234 * 0b1100..1/4096 count_clk
19235 * 0b1101..1/8192 count_clk
19236 * 0b1110..1/16384 count_clk
19237 * 0b1111..1/32768 count_clk
19238 */
19239#define GPC_PGC_A53CORE0_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE0_AUXSW_PDN_CLK_DIV_SEL_MASK)
19240/*! @} */
19241
19242/*! @name A53CORE1_CTRL - GPC PGC Control Register */
19243/*! @{ */
19244#define GPC_PGC_A53CORE1_CTRL_PCR_MASK (0x1U)
19245#define GPC_PGC_A53CORE1_CTRL_PCR_SHIFT (0U)
19246/*! PCR
19247 * 0b0..Do not switch off power even if pdn_req is asserted.
19248 * 0b1..Switch off power when pdn_req is asserted.
19249 */
19250#define GPC_PGC_A53CORE1_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_CTRL_PCR_SHIFT)) & GPC_PGC_A53CORE1_CTRL_PCR_MASK)
19251#define GPC_PGC_A53CORE1_CTRL_L2RSTDIS_MASK (0x7EU)
19252#define GPC_PGC_A53CORE1_CTRL_L2RSTDIS_SHIFT (1U)
19253#define GPC_PGC_A53CORE1_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53CORE1_CTRL_L2RSTDIS_MASK)
19254#define GPC_PGC_A53CORE1_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
19255#define GPC_PGC_A53CORE1_CTRL_DFTRAM_TCD1_SHIFT (8U)
19256#define GPC_PGC_A53CORE1_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53CORE1_CTRL_DFTRAM_TCD1_MASK)
19257#define GPC_PGC_A53CORE1_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
19258#define GPC_PGC_A53CORE1_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
19259#define GPC_PGC_A53CORE1_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_A53CORE1_CTRL_L2RETN_TCD1_TDR_MASK)
19260#define GPC_PGC_A53CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
19261#define GPC_PGC_A53CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
19262#define GPC_PGC_A53CORE1_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_A53CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
19263/*! @} */
19264
19265/*! @name A53CORE1_PUPSCR - GPC PGC Up Sequence Control Register */
19266/*! @{ */
19267#define GPC_PGC_A53CORE1_PUPSCR_SW_MASK (0x3FU)
19268#define GPC_PGC_A53CORE1_PUPSCR_SW_SHIFT (0U)
19269#define GPC_PGC_A53CORE1_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PUPSCR_SW_SHIFT)) & GPC_PGC_A53CORE1_PUPSCR_SW_MASK)
19270#define GPC_PGC_A53CORE1_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
19271#define GPC_PGC_A53CORE1_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
19272#define GPC_PGC_A53CORE1_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE1_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
19273#define GPC_PGC_A53CORE1_PUPSCR_SW2ISO_MASK (0x7FFF80U)
19274#define GPC_PGC_A53CORE1_PUPSCR_SW2ISO_SHIFT (7U)
19275#define GPC_PGC_A53CORE1_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53CORE1_PUPSCR_SW2ISO_MASK)
19276#define GPC_PGC_A53CORE1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
19277#define GPC_PGC_A53CORE1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
19278#define GPC_PGC_A53CORE1_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
19279/*! @} */
19280
19281/*! @name A53CORE1_PDNSCR - GPC PGC Down Sequence Control Register */
19282/*! @{ */
19283#define GPC_PGC_A53CORE1_PDNSCR_ISO_MASK (0x3FU)
19284#define GPC_PGC_A53CORE1_PDNSCR_ISO_SHIFT (0U)
19285#define GPC_PGC_A53CORE1_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53CORE1_PDNSCR_ISO_MASK)
19286#define GPC_PGC_A53CORE1_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
19287#define GPC_PGC_A53CORE1_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
19288#define GPC_PGC_A53CORE1_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE1_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
19289#define GPC_PGC_A53CORE1_PDNSCR_ISO2SW_MASK (0x3F00U)
19290#define GPC_PGC_A53CORE1_PDNSCR_ISO2SW_SHIFT (8U)
19291#define GPC_PGC_A53CORE1_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53CORE1_PDNSCR_ISO2SW_MASK)
19292#define GPC_PGC_A53CORE1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
19293#define GPC_PGC_A53CORE1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
19294#define GPC_PGC_A53CORE1_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
19295#define GPC_PGC_A53CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
19296#define GPC_PGC_A53CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
19297#define GPC_PGC_A53CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_A53CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
19298/*! @} */
19299
19300/*! @name A53CORE1_SR - GPC PGC Status Register */
19301/*! @{ */
19302#define GPC_PGC_A53CORE1_SR_PSR_MASK (0x1U)
19303#define GPC_PGC_A53CORE1_SR_PSR_SHIFT (0U)
19304/*! PSR
19305 * 0b0..The target subsystem was not powered down for the previous power-down request.
19306 * 0b1..The target subsystem was powered down for the previous power-down request.
19307 */
19308#define GPC_PGC_A53CORE1_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_SR_PSR_SHIFT)) & GPC_PGC_A53CORE1_SR_PSR_MASK)
19309#define GPC_PGC_A53CORE1_SR_L2RETN_FLAG_MASK (0x2U)
19310#define GPC_PGC_A53CORE1_SR_L2RETN_FLAG_SHIFT (1U)
19311/*! L2RETN_FLAG
19312 * 0b0..A53 is not wakeup from L2 retention mode.
19313 * 0b1..A53 is wakeup from L2 retention mode.
19314 */
19315#define GPC_PGC_A53CORE1_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53CORE1_SR_L2RETN_FLAG_MASK)
19316#define GPC_PGC_A53CORE1_SR_ALLOFF_FLAG_MASK (0x4U)
19317#define GPC_PGC_A53CORE1_SR_ALLOFF_FLAG_SHIFT (2U)
19318/*! ALLOFF_FLAG
19319 * 0b0..A53 is not wakeup from ALL_OFF mode.
19320 * 0b1..A53 is wakeup from ALL_OFF mode.
19321 */
19322#define GPC_PGC_A53CORE1_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53CORE1_SR_ALLOFF_FLAG_MASK)
19323#define GPC_PGC_A53CORE1_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
19324#define GPC_PGC_A53CORE1_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
19325/*! PUP_CLK_DIV_SEL
19326 * 0b0000..1
19327 * 0b0001..1/2 count_clk
19328 * 0b0010..1/4 count_clk
19329 * 0b0011..1/8 count_clk
19330 * 0b0100..1/16 count_clk
19331 * 0b0101..1/32 count_clk
19332 * 0b0110..1/64 count_clk
19333 * 0b0111..1/128 count_clk
19334 * 0b1000..1/256 count_clk
19335 * 0b1001..1/512 count_clk
19336 * 0b1010..1/1024 count_clk
19337 * 0b1011..1/2056 count_clk
19338 * 0b1100..1/4096 count_clk
19339 * 0b1101..1/8192 count_clk
19340 * 0b1110..1/16384 count_clk
19341 * 0b1111..1/32768 count_clk
19342 */
19343#define GPC_PGC_A53CORE1_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE1_SR_PUP_CLK_DIV_SEL_MASK)
19344#define GPC_PGC_A53CORE1_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
19345#define GPC_PGC_A53CORE1_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
19346#define GPC_PGC_A53CORE1_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_A53CORE1_SR_L2RSTDIS_DEASSERT_CNT_MASK)
19347/*! @} */
19348
19349/*! @name A53CORE1_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
19350/*! @{ */
19351#define GPC_PGC_A53CORE1_AUXSW_SW2_MASK (0x3FU)
19352#define GPC_PGC_A53CORE1_AUXSW_SW2_SHIFT (0U)
19353#define GPC_PGC_A53CORE1_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_AUXSW_SW2_SHIFT)) & GPC_PGC_A53CORE1_AUXSW_SW2_MASK)
19354#define GPC_PGC_A53CORE1_AUXSW_ISO2SW2_MASK (0x3F00U)
19355#define GPC_PGC_A53CORE1_AUXSW_ISO2SW2_SHIFT (8U)
19356/*! ISO2SW2
19357 * 0b000000..A53 is not wakeup from ALL_OFF mode.
19358 * 0b000001..A53 is wakeup from ALL_OFF mode.
19359 */
19360#define GPC_PGC_A53CORE1_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_A53CORE1_AUXSW_ISO2SW2_MASK)
19361#define GPC_PGC_A53CORE1_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
19362#define GPC_PGC_A53CORE1_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
19363/*! PDN_CLK_DIV_SEL
19364 * 0b0000..1
19365 * 0b0001..1/2 count_clk
19366 * 0b0010..1/4 count_clk
19367 * 0b0011..1/8 count_clk
19368 * 0b0100..1/16 count_clk
19369 * 0b0101..1/32 count_clk
19370 * 0b0110..1/64 count_clk
19371 * 0b0111..1/128 count_clk
19372 * 0b1000..1/256 count_clk
19373 * 0b1001..1/512 count_clk
19374 * 0b1010..1/1024 count_clk
19375 * 0b1011..1/2056 count_clk
19376 * 0b1100..1/4096 count_clk
19377 * 0b1101..1/8192 count_clk
19378 * 0b1110..1/16384 count_clk
19379 * 0b1111..1/32768 count_clk
19380 */
19381#define GPC_PGC_A53CORE1_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE1_AUXSW_PDN_CLK_DIV_SEL_MASK)
19382/*! @} */
19383
19384/*! @name A53CORE2_CTRL - GPC PGC Control Register */
19385/*! @{ */
19386#define GPC_PGC_A53CORE2_CTRL_PCR_MASK (0x1U)
19387#define GPC_PGC_A53CORE2_CTRL_PCR_SHIFT (0U)
19388/*! PCR
19389 * 0b0..Do not switch off power even if pdn_req is asserted.
19390 * 0b1..Switch off power when pdn_req is asserted.
19391 */
19392#define GPC_PGC_A53CORE2_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_CTRL_PCR_SHIFT)) & GPC_PGC_A53CORE2_CTRL_PCR_MASK)
19393#define GPC_PGC_A53CORE2_CTRL_L2RSTDIS_MASK (0x7EU)
19394#define GPC_PGC_A53CORE2_CTRL_L2RSTDIS_SHIFT (1U)
19395#define GPC_PGC_A53CORE2_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53CORE2_CTRL_L2RSTDIS_MASK)
19396#define GPC_PGC_A53CORE2_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
19397#define GPC_PGC_A53CORE2_CTRL_DFTRAM_TCD1_SHIFT (8U)
19398#define GPC_PGC_A53CORE2_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53CORE2_CTRL_DFTRAM_TCD1_MASK)
19399#define GPC_PGC_A53CORE2_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
19400#define GPC_PGC_A53CORE2_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
19401#define GPC_PGC_A53CORE2_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_A53CORE2_CTRL_L2RETN_TCD1_TDR_MASK)
19402#define GPC_PGC_A53CORE2_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
19403#define GPC_PGC_A53CORE2_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
19404#define GPC_PGC_A53CORE2_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_A53CORE2_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
19405/*! @} */
19406
19407/*! @name A53CORE2_PUPSCR - GPC PGC Up Sequence Control Register */
19408/*! @{ */
19409#define GPC_PGC_A53CORE2_PUPSCR_SW_MASK (0x3FU)
19410#define GPC_PGC_A53CORE2_PUPSCR_SW_SHIFT (0U)
19411#define GPC_PGC_A53CORE2_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PUPSCR_SW_SHIFT)) & GPC_PGC_A53CORE2_PUPSCR_SW_MASK)
19412#define GPC_PGC_A53CORE2_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
19413#define GPC_PGC_A53CORE2_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
19414#define GPC_PGC_A53CORE2_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE2_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
19415#define GPC_PGC_A53CORE2_PUPSCR_SW2ISO_MASK (0x7FFF80U)
19416#define GPC_PGC_A53CORE2_PUPSCR_SW2ISO_SHIFT (7U)
19417#define GPC_PGC_A53CORE2_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53CORE2_PUPSCR_SW2ISO_MASK)
19418#define GPC_PGC_A53CORE2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
19419#define GPC_PGC_A53CORE2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
19420#define GPC_PGC_A53CORE2_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
19421/*! @} */
19422
19423/*! @name A53CORE2_PDNSCR - GPC PGC Down Sequence Control Register */
19424/*! @{ */
19425#define GPC_PGC_A53CORE2_PDNSCR_ISO_MASK (0x3FU)
19426#define GPC_PGC_A53CORE2_PDNSCR_ISO_SHIFT (0U)
19427#define GPC_PGC_A53CORE2_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53CORE2_PDNSCR_ISO_MASK)
19428#define GPC_PGC_A53CORE2_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
19429#define GPC_PGC_A53CORE2_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
19430#define GPC_PGC_A53CORE2_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE2_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
19431#define GPC_PGC_A53CORE2_PDNSCR_ISO2SW_MASK (0x3F00U)
19432#define GPC_PGC_A53CORE2_PDNSCR_ISO2SW_SHIFT (8U)
19433#define GPC_PGC_A53CORE2_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53CORE2_PDNSCR_ISO2SW_MASK)
19434#define GPC_PGC_A53CORE2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
19435#define GPC_PGC_A53CORE2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
19436#define GPC_PGC_A53CORE2_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
19437#define GPC_PGC_A53CORE2_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
19438#define GPC_PGC_A53CORE2_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
19439#define GPC_PGC_A53CORE2_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_A53CORE2_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
19440/*! @} */
19441
19442/*! @name A53CORE2_SR - GPC PGC Status Register */
19443/*! @{ */
19444#define GPC_PGC_A53CORE2_SR_PSR_MASK (0x1U)
19445#define GPC_PGC_A53CORE2_SR_PSR_SHIFT (0U)
19446/*! PSR
19447 * 0b0..The target subsystem was not powered down for the previous power-down request.
19448 * 0b1..The target subsystem was powered down for the previous power-down request.
19449 */
19450#define GPC_PGC_A53CORE2_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_SR_PSR_SHIFT)) & GPC_PGC_A53CORE2_SR_PSR_MASK)
19451#define GPC_PGC_A53CORE2_SR_L2RETN_FLAG_MASK (0x2U)
19452#define GPC_PGC_A53CORE2_SR_L2RETN_FLAG_SHIFT (1U)
19453/*! L2RETN_FLAG
19454 * 0b0..A53 is not wakeup from L2 retention mode.
19455 * 0b1..A53 is wakeup from L2 retention mode.
19456 */
19457#define GPC_PGC_A53CORE2_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53CORE2_SR_L2RETN_FLAG_MASK)
19458#define GPC_PGC_A53CORE2_SR_ALLOFF_FLAG_MASK (0x4U)
19459#define GPC_PGC_A53CORE2_SR_ALLOFF_FLAG_SHIFT (2U)
19460/*! ALLOFF_FLAG
19461 * 0b0..A53 is not wakeup from ALL_OFF mode.
19462 * 0b1..A53 is wakeup from ALL_OFF mode.
19463 */
19464#define GPC_PGC_A53CORE2_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53CORE2_SR_ALLOFF_FLAG_MASK)
19465#define GPC_PGC_A53CORE2_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
19466#define GPC_PGC_A53CORE2_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
19467/*! PUP_CLK_DIV_SEL
19468 * 0b0000..1
19469 * 0b0001..1/2 count_clk
19470 * 0b0010..1/4 count_clk
19471 * 0b0011..1/8 count_clk
19472 * 0b0100..1/16 count_clk
19473 * 0b0101..1/32 count_clk
19474 * 0b0110..1/64 count_clk
19475 * 0b0111..1/128 count_clk
19476 * 0b1000..1/256 count_clk
19477 * 0b1001..1/512 count_clk
19478 * 0b1010..1/1024 count_clk
19479 * 0b1011..1/2056 count_clk
19480 * 0b1100..1/4096 count_clk
19481 * 0b1101..1/8192 count_clk
19482 * 0b1110..1/16384 count_clk
19483 * 0b1111..1/32768 count_clk
19484 */
19485#define GPC_PGC_A53CORE2_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE2_SR_PUP_CLK_DIV_SEL_MASK)
19486#define GPC_PGC_A53CORE2_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
19487#define GPC_PGC_A53CORE2_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
19488#define GPC_PGC_A53CORE2_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_A53CORE2_SR_L2RSTDIS_DEASSERT_CNT_MASK)
19489/*! @} */
19490
19491/*! @name A53CORE2_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
19492/*! @{ */
19493#define GPC_PGC_A53CORE2_AUXSW_SW2_MASK (0x3FU)
19494#define GPC_PGC_A53CORE2_AUXSW_SW2_SHIFT (0U)
19495#define GPC_PGC_A53CORE2_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_AUXSW_SW2_SHIFT)) & GPC_PGC_A53CORE2_AUXSW_SW2_MASK)
19496#define GPC_PGC_A53CORE2_AUXSW_ISO2SW2_MASK (0x3F00U)
19497#define GPC_PGC_A53CORE2_AUXSW_ISO2SW2_SHIFT (8U)
19498/*! ISO2SW2
19499 * 0b000000..A53 is not wakeup from ALL_OFF mode.
19500 * 0b000001..A53 is wakeup from ALL_OFF mode.
19501 */
19502#define GPC_PGC_A53CORE2_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_A53CORE2_AUXSW_ISO2SW2_MASK)
19503#define GPC_PGC_A53CORE2_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
19504#define GPC_PGC_A53CORE2_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
19505/*! PDN_CLK_DIV_SEL
19506 * 0b0000..1
19507 * 0b0001..1/2 count_clk
19508 * 0b0010..1/4 count_clk
19509 * 0b0011..1/8 count_clk
19510 * 0b0100..1/16 count_clk
19511 * 0b0101..1/32 count_clk
19512 * 0b0110..1/64 count_clk
19513 * 0b0111..1/128 count_clk
19514 * 0b1000..1/256 count_clk
19515 * 0b1001..1/512 count_clk
19516 * 0b1010..1/1024 count_clk
19517 * 0b1011..1/2056 count_clk
19518 * 0b1100..1/4096 count_clk
19519 * 0b1101..1/8192 count_clk
19520 * 0b1110..1/16384 count_clk
19521 * 0b1111..1/32768 count_clk
19522 */
19523#define GPC_PGC_A53CORE2_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE2_AUXSW_PDN_CLK_DIV_SEL_MASK)
19524/*! @} */
19525
19526/*! @name A53CORE3_CTRL - GPC PGC Control Register */
19527/*! @{ */
19528#define GPC_PGC_A53CORE3_CTRL_PCR_MASK (0x1U)
19529#define GPC_PGC_A53CORE3_CTRL_PCR_SHIFT (0U)
19530/*! PCR
19531 * 0b0..Do not switch off power even if pdn_req is asserted.
19532 * 0b1..Switch off power when pdn_req is asserted.
19533 */
19534#define GPC_PGC_A53CORE3_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_CTRL_PCR_SHIFT)) & GPC_PGC_A53CORE3_CTRL_PCR_MASK)
19535#define GPC_PGC_A53CORE3_CTRL_L2RSTDIS_MASK (0x7EU)
19536#define GPC_PGC_A53CORE3_CTRL_L2RSTDIS_SHIFT (1U)
19537#define GPC_PGC_A53CORE3_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53CORE3_CTRL_L2RSTDIS_MASK)
19538#define GPC_PGC_A53CORE3_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
19539#define GPC_PGC_A53CORE3_CTRL_DFTRAM_TCD1_SHIFT (8U)
19540#define GPC_PGC_A53CORE3_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53CORE3_CTRL_DFTRAM_TCD1_MASK)
19541#define GPC_PGC_A53CORE3_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
19542#define GPC_PGC_A53CORE3_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
19543#define GPC_PGC_A53CORE3_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_A53CORE3_CTRL_L2RETN_TCD1_TDR_MASK)
19544#define GPC_PGC_A53CORE3_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
19545#define GPC_PGC_A53CORE3_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
19546#define GPC_PGC_A53CORE3_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_A53CORE3_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
19547/*! @} */
19548
19549/*! @name A53CORE3_PUPSCR - GPC PGC Up Sequence Control Register */
19550/*! @{ */
19551#define GPC_PGC_A53CORE3_PUPSCR_SW_MASK (0x3FU)
19552#define GPC_PGC_A53CORE3_PUPSCR_SW_SHIFT (0U)
19553#define GPC_PGC_A53CORE3_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PUPSCR_SW_SHIFT)) & GPC_PGC_A53CORE3_PUPSCR_SW_MASK)
19554#define GPC_PGC_A53CORE3_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
19555#define GPC_PGC_A53CORE3_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
19556#define GPC_PGC_A53CORE3_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE3_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
19557#define GPC_PGC_A53CORE3_PUPSCR_SW2ISO_MASK (0x7FFF80U)
19558#define GPC_PGC_A53CORE3_PUPSCR_SW2ISO_SHIFT (7U)
19559#define GPC_PGC_A53CORE3_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53CORE3_PUPSCR_SW2ISO_MASK)
19560#define GPC_PGC_A53CORE3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
19561#define GPC_PGC_A53CORE3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
19562#define GPC_PGC_A53CORE3_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
19563/*! @} */
19564
19565/*! @name A53CORE3_PDNSCR - GPC PGC Down Sequence Control Register */
19566/*! @{ */
19567#define GPC_PGC_A53CORE3_PDNSCR_ISO_MASK (0x3FU)
19568#define GPC_PGC_A53CORE3_PDNSCR_ISO_SHIFT (0U)
19569#define GPC_PGC_A53CORE3_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53CORE3_PDNSCR_ISO_MASK)
19570#define GPC_PGC_A53CORE3_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
19571#define GPC_PGC_A53CORE3_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
19572#define GPC_PGC_A53CORE3_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE3_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
19573#define GPC_PGC_A53CORE3_PDNSCR_ISO2SW_MASK (0x3F00U)
19574#define GPC_PGC_A53CORE3_PDNSCR_ISO2SW_SHIFT (8U)
19575#define GPC_PGC_A53CORE3_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53CORE3_PDNSCR_ISO2SW_MASK)
19576#define GPC_PGC_A53CORE3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
19577#define GPC_PGC_A53CORE3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
19578#define GPC_PGC_A53CORE3_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
19579#define GPC_PGC_A53CORE3_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
19580#define GPC_PGC_A53CORE3_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
19581#define GPC_PGC_A53CORE3_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_A53CORE3_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
19582/*! @} */
19583
19584/*! @name A53CORE3_SR - GPC PGC Status Register */
19585/*! @{ */
19586#define GPC_PGC_A53CORE3_SR_PSR_MASK (0x1U)
19587#define GPC_PGC_A53CORE3_SR_PSR_SHIFT (0U)
19588/*! PSR
19589 * 0b0..The target subsystem was not powered down for the previous power-down request.
19590 * 0b1..The target subsystem was powered down for the previous power-down request.
19591 */
19592#define GPC_PGC_A53CORE3_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_SR_PSR_SHIFT)) & GPC_PGC_A53CORE3_SR_PSR_MASK)
19593#define GPC_PGC_A53CORE3_SR_L2RETN_FLAG_MASK (0x2U)
19594#define GPC_PGC_A53CORE3_SR_L2RETN_FLAG_SHIFT (1U)
19595/*! L2RETN_FLAG
19596 * 0b0..A53 is not wakeup from L2 retention mode.
19597 * 0b1..A53 is wakeup from L2 retention mode.
19598 */
19599#define GPC_PGC_A53CORE3_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53CORE3_SR_L2RETN_FLAG_MASK)
19600#define GPC_PGC_A53CORE3_SR_ALLOFF_FLAG_MASK (0x4U)
19601#define GPC_PGC_A53CORE3_SR_ALLOFF_FLAG_SHIFT (2U)
19602/*! ALLOFF_FLAG
19603 * 0b0..A53 is not wakeup from ALL_OFF mode.
19604 * 0b1..A53 is wakeup from ALL_OFF mode.
19605 */
19606#define GPC_PGC_A53CORE3_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53CORE3_SR_ALLOFF_FLAG_MASK)
19607#define GPC_PGC_A53CORE3_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
19608#define GPC_PGC_A53CORE3_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
19609/*! PUP_CLK_DIV_SEL
19610 * 0b0000..1
19611 * 0b0001..1/2 count_clk
19612 * 0b0010..1/4 count_clk
19613 * 0b0011..1/8 count_clk
19614 * 0b0100..1/16 count_clk
19615 * 0b0101..1/32 count_clk
19616 * 0b0110..1/64 count_clk
19617 * 0b0111..1/128 count_clk
19618 * 0b1000..1/256 count_clk
19619 * 0b1001..1/512 count_clk
19620 * 0b1010..1/1024 count_clk
19621 * 0b1011..1/2056 count_clk
19622 * 0b1100..1/4096 count_clk
19623 * 0b1101..1/8192 count_clk
19624 * 0b1110..1/16384 count_clk
19625 * 0b1111..1/32768 count_clk
19626 */
19627#define GPC_PGC_A53CORE3_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE3_SR_PUP_CLK_DIV_SEL_MASK)
19628#define GPC_PGC_A53CORE3_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
19629#define GPC_PGC_A53CORE3_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
19630#define GPC_PGC_A53CORE3_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_A53CORE3_SR_L2RSTDIS_DEASSERT_CNT_MASK)
19631/*! @} */
19632
19633/*! @name A53CORE3_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
19634/*! @{ */
19635#define GPC_PGC_A53CORE3_AUXSW_SW2_MASK (0x3FU)
19636#define GPC_PGC_A53CORE3_AUXSW_SW2_SHIFT (0U)
19637#define GPC_PGC_A53CORE3_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_AUXSW_SW2_SHIFT)) & GPC_PGC_A53CORE3_AUXSW_SW2_MASK)
19638#define GPC_PGC_A53CORE3_AUXSW_ISO2SW2_MASK (0x3F00U)
19639#define GPC_PGC_A53CORE3_AUXSW_ISO2SW2_SHIFT (8U)
19640/*! ISO2SW2
19641 * 0b000000..A53 is not wakeup from ALL_OFF mode.
19642 * 0b000001..A53 is wakeup from ALL_OFF mode.
19643 */
19644#define GPC_PGC_A53CORE3_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_A53CORE3_AUXSW_ISO2SW2_MASK)
19645#define GPC_PGC_A53CORE3_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
19646#define GPC_PGC_A53CORE3_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
19647/*! PDN_CLK_DIV_SEL
19648 * 0b0000..1
19649 * 0b0001..1/2 count_clk
19650 * 0b0010..1/4 count_clk
19651 * 0b0011..1/8 count_clk
19652 * 0b0100..1/16 count_clk
19653 * 0b0101..1/32 count_clk
19654 * 0b0110..1/64 count_clk
19655 * 0b0111..1/128 count_clk
19656 * 0b1000..1/256 count_clk
19657 * 0b1001..1/512 count_clk
19658 * 0b1010..1/1024 count_clk
19659 * 0b1011..1/2056 count_clk
19660 * 0b1100..1/4096 count_clk
19661 * 0b1101..1/8192 count_clk
19662 * 0b1110..1/16384 count_clk
19663 * 0b1111..1/32768 count_clk
19664 */
19665#define GPC_PGC_A53CORE3_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE3_AUXSW_PDN_CLK_DIV_SEL_MASK)
19666/*! @} */
19667
19668/*! @name A53SCU_CTRL - GPC PGC Control Register */
19669/*! @{ */
19670#define GPC_PGC_A53SCU_CTRL_PCR_MASK (0x1U)
19671#define GPC_PGC_A53SCU_CTRL_PCR_SHIFT (0U)
19672/*! PCR
19673 * 0b0..Do not switch off power even if pdn_req is asserted.
19674 * 0b1..Switch off power when pdn_req is asserted.
19675 */
19676#define GPC_PGC_A53SCU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_PCR_SHIFT)) & GPC_PGC_A53SCU_CTRL_PCR_MASK)
19677#define GPC_PGC_A53SCU_CTRL_L2RSTDIS_MASK (0x7EU)
19678#define GPC_PGC_A53SCU_CTRL_L2RSTDIS_SHIFT (1U)
19679#define GPC_PGC_A53SCU_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53SCU_CTRL_L2RSTDIS_MASK)
19680#define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
19681#define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_SHIFT (8U)
19682#define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_MASK)
19683#define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
19684#define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
19685#define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_MASK)
19686#define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
19687#define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
19688#define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
19689/*! @} */
19690
19691/*! @name A53SCU_PUPSCR - GPC PGC Up Sequence Control Register */
19692/*! @{ */
19693#define GPC_PGC_A53SCU_PUPSCR_SW_MASK (0x3FU)
19694#define GPC_PGC_A53SCU_PUPSCR_SW_SHIFT (0U)
19695#define GPC_PGC_A53SCU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_SW_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_SW_MASK)
19696#define GPC_PGC_A53SCU_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
19697#define GPC_PGC_A53SCU_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
19698#define GPC_PGC_A53SCU_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
19699#define GPC_PGC_A53SCU_PUPSCR_SW2ISO_MASK (0x7FFF80U)
19700#define GPC_PGC_A53SCU_PUPSCR_SW2ISO_SHIFT (7U)
19701#define GPC_PGC_A53SCU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_SW2ISO_MASK)
19702#define GPC_PGC_A53SCU_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
19703#define GPC_PGC_A53SCU_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
19704#define GPC_PGC_A53SCU_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
19705/*! @} */
19706
19707/*! @name A53SCU_PDNSCR - GPC PGC Down Sequence Control Register */
19708/*! @{ */
19709#define GPC_PGC_A53SCU_PDNSCR_ISO_MASK (0x3FU)
19710#define GPC_PGC_A53SCU_PDNSCR_ISO_SHIFT (0U)
19711#define GPC_PGC_A53SCU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_ISO_MASK)
19712#define GPC_PGC_A53SCU_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
19713#define GPC_PGC_A53SCU_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
19714#define GPC_PGC_A53SCU_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
19715#define GPC_PGC_A53SCU_PDNSCR_ISO2SW_MASK (0x3F00U)
19716#define GPC_PGC_A53SCU_PDNSCR_ISO2SW_SHIFT (8U)
19717#define GPC_PGC_A53SCU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_ISO2SW_MASK)
19718#define GPC_PGC_A53SCU_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
19719#define GPC_PGC_A53SCU_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
19720#define GPC_PGC_A53SCU_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
19721#define GPC_PGC_A53SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
19722#define GPC_PGC_A53SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
19723#define GPC_PGC_A53SCU_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
19724/*! @} */
19725
19726/*! @name A53SCU_SR - GPC PGC Status Register */
19727/*! @{ */
19728#define GPC_PGC_A53SCU_SR_PSR_MASK (0x1U)
19729#define GPC_PGC_A53SCU_SR_PSR_SHIFT (0U)
19730/*! PSR
19731 * 0b0..The target subsystem was not powered down for the previous power-down request.
19732 * 0b1..The target subsystem was powered down for the previous power-down request.
19733 */
19734#define GPC_PGC_A53SCU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_PSR_SHIFT)) & GPC_PGC_A53SCU_SR_PSR_MASK)
19735#define GPC_PGC_A53SCU_SR_L2RETN_FLAG_MASK (0x2U)
19736#define GPC_PGC_A53SCU_SR_L2RETN_FLAG_SHIFT (1U)
19737/*! L2RETN_FLAG
19738 * 0b0..A53 is not wakeup from L2 retention mode.
19739 * 0b1..A53 is wakeup from L2 retention mode.
19740 */
19741#define GPC_PGC_A53SCU_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53SCU_SR_L2RETN_FLAG_MASK)
19742#define GPC_PGC_A53SCU_SR_ALLOFF_FLAG_MASK (0x4U)
19743#define GPC_PGC_A53SCU_SR_ALLOFF_FLAG_SHIFT (2U)
19744/*! ALLOFF_FLAG
19745 * 0b0..A53 is not wakeup from ALL_OFF mode.
19746 * 0b1..A53 is wakeup from ALL_OFF mode.
19747 */
19748#define GPC_PGC_A53SCU_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53SCU_SR_ALLOFF_FLAG_MASK)
19749#define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
19750#define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
19751/*! PUP_CLK_DIV_SEL
19752 * 0b0000..1
19753 * 0b0001..1/2 count_clk
19754 * 0b0010..1/4 count_clk
19755 * 0b0011..1/8 count_clk
19756 * 0b0100..1/16 count_clk
19757 * 0b0101..1/32 count_clk
19758 * 0b0110..1/64 count_clk
19759 * 0b0111..1/128 count_clk
19760 * 0b1000..1/256 count_clk
19761 * 0b1001..1/512 count_clk
19762 * 0b1010..1/1024 count_clk
19763 * 0b1011..1/2056 count_clk
19764 * 0b1100..1/4096 count_clk
19765 * 0b1101..1/8192 count_clk
19766 * 0b1110..1/16384 count_clk
19767 * 0b1111..1/32768 count_clk
19768 */
19769#define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_MASK)
19770#define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
19771#define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
19772#define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_MASK)
19773/*! @} */
19774
19775/*! @name A53SCU_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
19776/*! @{ */
19777#define GPC_PGC_A53SCU_AUXSW_SW2_MASK (0x3FU)
19778#define GPC_PGC_A53SCU_AUXSW_SW2_SHIFT (0U)
19779#define GPC_PGC_A53SCU_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_AUXSW_SW2_SHIFT)) & GPC_PGC_A53SCU_AUXSW_SW2_MASK)
19780#define GPC_PGC_A53SCU_AUXSW_ISO2SW2_MASK (0x3F00U)
19781#define GPC_PGC_A53SCU_AUXSW_ISO2SW2_SHIFT (8U)
19782/*! ISO2SW2
19783 * 0b000000..A53 is not wakeup from ALL_OFF mode.
19784 * 0b000001..A53 is wakeup from ALL_OFF mode.
19785 */
19786#define GPC_PGC_A53SCU_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_A53SCU_AUXSW_ISO2SW2_MASK)
19787#define GPC_PGC_A53SCU_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
19788#define GPC_PGC_A53SCU_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
19789/*! PDN_CLK_DIV_SEL
19790 * 0b0000..1
19791 * 0b0001..1/2 count_clk
19792 * 0b0010..1/4 count_clk
19793 * 0b0011..1/8 count_clk
19794 * 0b0100..1/16 count_clk
19795 * 0b0101..1/32 count_clk
19796 * 0b0110..1/64 count_clk
19797 * 0b0111..1/128 count_clk
19798 * 0b1000..1/256 count_clk
19799 * 0b1001..1/512 count_clk
19800 * 0b1010..1/1024 count_clk
19801 * 0b1011..1/2056 count_clk
19802 * 0b1100..1/4096 count_clk
19803 * 0b1101..1/8192 count_clk
19804 * 0b1110..1/16384 count_clk
19805 * 0b1111..1/32768 count_clk
19806 */
19807#define GPC_PGC_A53SCU_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53SCU_AUXSW_PDN_CLK_DIV_SEL_MASK)
19808/*! @} */
19809
19810/*! @name MIX_CTRL - GPC PGC Control Register */
19811/*! @{ */
19812#define GPC_PGC_MIX_CTRL_MIX_PCR_MASK (0x1U)
19813#define GPC_PGC_MIX_CTRL_MIX_PCR_SHIFT (0U)
19814/*! MIX_PCR
19815 * 0b0..Do not switch off power even if pdn_req is asserted.
19816 * 0b1..Switch off power when pdn_req is asserted.
19817 */
19818#define GPC_PGC_MIX_CTRL_MIX_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_CTRL_MIX_PCR_SHIFT)) & GPC_PGC_MIX_CTRL_MIX_PCR_MASK)
19819#define GPC_PGC_MIX_CTRL_L2RSTDIS_MASK (0x7EU)
19820#define GPC_PGC_MIX_CTRL_L2RSTDIS_SHIFT (1U)
19821#define GPC_PGC_MIX_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_MIX_CTRL_L2RSTDIS_MASK)
19822#define GPC_PGC_MIX_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
19823#define GPC_PGC_MIX_CTRL_DFTRAM_TCD1_SHIFT (8U)
19824#define GPC_PGC_MIX_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_MIX_CTRL_DFTRAM_TCD1_MASK)
19825#define GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
19826#define GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
19827#define GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_MASK)
19828#define GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
19829#define GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
19830#define GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
19831/*! @} */
19832
19833/*! @name MIX_PUPSCR - GPC PGC Up Sequence Control Register */
19834/*! @{ */
19835#define GPC_PGC_MIX_PUPSCR_SW_MASK (0x3FU)
19836#define GPC_PGC_MIX_PUPSCR_SW_SHIFT (0U)
19837#define GPC_PGC_MIX_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PUPSCR_SW_SHIFT)) & GPC_PGC_MIX_PUPSCR_SW_MASK)
19838#define GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
19839#define GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
19840#define GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
19841#define GPC_PGC_MIX_PUPSCR_SW2ISO_MASK (0x7FFF80U)
19842#define GPC_PGC_MIX_PUPSCR_SW2ISO_SHIFT (7U)
19843#define GPC_PGC_MIX_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_MIX_PUPSCR_SW2ISO_MASK)
19844#define GPC_PGC_MIX_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
19845#define GPC_PGC_MIX_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
19846#define GPC_PGC_MIX_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_MIX_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
19847/*! @} */
19848
19849/*! @name MIX_PDNSCR - GPC PGC Down Sequence Control Register */
19850/*! @{ */
19851#define GPC_PGC_MIX_PDNSCR_ISO_MASK (0x3FU)
19852#define GPC_PGC_MIX_PDNSCR_ISO_SHIFT (0U)
19853#define GPC_PGC_MIX_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PDNSCR_ISO_SHIFT)) & GPC_PGC_MIX_PDNSCR_ISO_MASK)
19854#define GPC_PGC_MIX_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
19855#define GPC_PGC_MIX_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
19856#define GPC_PGC_MIX_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_MIX_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
19857#define GPC_PGC_MIX_PDNSCR_ISO2SW_MASK (0x3F00U)
19858#define GPC_PGC_MIX_PDNSCR_ISO2SW_SHIFT (8U)
19859#define GPC_PGC_MIX_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_MIX_PDNSCR_ISO2SW_MASK)
19860#define GPC_PGC_MIX_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
19861#define GPC_PGC_MIX_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
19862#define GPC_PGC_MIX_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_MIX_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
19863#define GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
19864#define GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
19865#define GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
19866/*! @} */
19867
19868/*! @name MIX_SR - GPC PGC Status Register */
19869/*! @{ */
19870#define GPC_PGC_MIX_SR_PSR_MASK (0x1U)
19871#define GPC_PGC_MIX_SR_PSR_SHIFT (0U)
19872/*! PSR
19873 * 0b0..The target subsystem was not powered down for the previous power-down request.
19874 * 0b1..The target subsystem was powered down for the previous power-down request.
19875 */
19876#define GPC_PGC_MIX_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_SR_PSR_SHIFT)) & GPC_PGC_MIX_SR_PSR_MASK)
19877#define GPC_PGC_MIX_SR_L2RETN_FLAG_MASK (0x2U)
19878#define GPC_PGC_MIX_SR_L2RETN_FLAG_SHIFT (1U)
19879/*! L2RETN_FLAG
19880 * 0b0..A53 is not wakeup from L2 retention mode.
19881 * 0b1..A53 is wakeup from L2 retention mode.
19882 */
19883#define GPC_PGC_MIX_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_MIX_SR_L2RETN_FLAG_MASK)
19884#define GPC_PGC_MIX_SR_ALLOFF_FLAG_MASK (0x4U)
19885#define GPC_PGC_MIX_SR_ALLOFF_FLAG_SHIFT (2U)
19886/*! ALLOFF_FLAG
19887 * 0b0..A53 is not wakeup from ALL_OFF mode.
19888 * 0b1..A53 is wakeup from ALL_OFF mode.
19889 */
19890#define GPC_PGC_MIX_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_MIX_SR_ALLOFF_FLAG_MASK)
19891#define GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
19892#define GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
19893/*! PUP_CLK_DIV_SEL
19894 * 0b0000..1
19895 * 0b0001..1/2 count_clk
19896 * 0b0010..1/4 count_clk
19897 * 0b0011..1/8 count_clk
19898 * 0b0100..1/16 count_clk
19899 * 0b0101..1/32 count_clk
19900 * 0b0110..1/64 count_clk
19901 * 0b0111..1/128 count_clk
19902 * 0b1000..1/256 count_clk
19903 * 0b1001..1/512 count_clk
19904 * 0b1010..1/1024 count_clk
19905 * 0b1011..1/2056 count_clk
19906 * 0b1100..1/4096 count_clk
19907 * 0b1101..1/8192 count_clk
19908 * 0b1110..1/16384 count_clk
19909 * 0b1111..1/32768 count_clk
19910 */
19911#define GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_MASK)
19912#define GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
19913#define GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
19914#define GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_MASK)
19915/*! @} */
19916
19917/*! @name MIX_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
19918/*! @{ */
19919#define GPC_PGC_MIX_AUXSW_SW2_MASK (0x3FU)
19920#define GPC_PGC_MIX_AUXSW_SW2_SHIFT (0U)
19921#define GPC_PGC_MIX_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_AUXSW_SW2_SHIFT)) & GPC_PGC_MIX_AUXSW_SW2_MASK)
19922#define GPC_PGC_MIX_AUXSW_ISO2SW2_MASK (0x3F00U)
19923#define GPC_PGC_MIX_AUXSW_ISO2SW2_SHIFT (8U)
19924/*! ISO2SW2
19925 * 0b000000..A53 is not wakeup from ALL_OFF mode.
19926 * 0b000001..A53 is wakeup from ALL_OFF mode.
19927 */
19928#define GPC_PGC_MIX_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_MIX_AUXSW_ISO2SW2_MASK)
19929#define GPC_PGC_MIX_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
19930#define GPC_PGC_MIX_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
19931/*! PDN_CLK_DIV_SEL
19932 * 0b0000..1
19933 * 0b0001..1/2 count_clk
19934 * 0b0010..1/4 count_clk
19935 * 0b0011..1/8 count_clk
19936 * 0b0100..1/16 count_clk
19937 * 0b0101..1/32 count_clk
19938 * 0b0110..1/64 count_clk
19939 * 0b0111..1/128 count_clk
19940 * 0b1000..1/256 count_clk
19941 * 0b1001..1/512 count_clk
19942 * 0b1010..1/1024 count_clk
19943 * 0b1011..1/2056 count_clk
19944 * 0b1100..1/4096 count_clk
19945 * 0b1101..1/8192 count_clk
19946 * 0b1110..1/16384 count_clk
19947 * 0b1111..1/32768 count_clk
19948 */
19949#define GPC_PGC_MIX_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_MIX_AUXSW_PDN_CLK_DIV_SEL_MASK)
19950/*! @} */
19951
19952/*! @name PU0_CTRL - GPC PGC Control Register */
19953/*! @{ */
19954#define GPC_PGC_PU0_CTRL_PCR_MASK (0x1U)
19955#define GPC_PGC_PU0_CTRL_PCR_SHIFT (0U)
19956/*! PCR
19957 * 0b0..Do not switch off power even if pdn_req is asserted.
19958 * 0b1..Switch off power when pdn_req is asserted.
19959 */
19960#define GPC_PGC_PU0_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_CTRL_PCR_SHIFT)) & GPC_PGC_PU0_CTRL_PCR_MASK)
19961#define GPC_PGC_PU0_CTRL_L2RSTDIS_MASK (0x7EU)
19962#define GPC_PGC_PU0_CTRL_L2RSTDIS_SHIFT (1U)
19963#define GPC_PGC_PU0_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU0_CTRL_L2RSTDIS_MASK)
19964#define GPC_PGC_PU0_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
19965#define GPC_PGC_PU0_CTRL_DFTRAM_TCD1_SHIFT (8U)
19966#define GPC_PGC_PU0_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU0_CTRL_DFTRAM_TCD1_MASK)
19967#define GPC_PGC_PU0_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
19968#define GPC_PGC_PU0_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
19969#define GPC_PGC_PU0_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU0_CTRL_L2RETN_TCD1_TDR_MASK)
19970#define GPC_PGC_PU0_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
19971#define GPC_PGC_PU0_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
19972#define GPC_PGC_PU0_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU0_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
19973/*! @} */
19974
19975/*! @name PU0_PUPSCR - GPC PGC Up Sequence Control Register */
19976/*! @{ */
19977#define GPC_PGC_PU0_PUPSCR_SW_MASK (0x3FU)
19978#define GPC_PGC_PU0_PUPSCR_SW_SHIFT (0U)
19979#define GPC_PGC_PU0_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PUPSCR_SW_SHIFT)) & GPC_PGC_PU0_PUPSCR_SW_MASK)
19980#define GPC_PGC_PU0_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
19981#define GPC_PGC_PU0_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
19982#define GPC_PGC_PU0_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU0_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
19983#define GPC_PGC_PU0_PUPSCR_SW2ISO_MASK (0x7FFF80U)
19984#define GPC_PGC_PU0_PUPSCR_SW2ISO_SHIFT (7U)
19985#define GPC_PGC_PU0_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU0_PUPSCR_SW2ISO_MASK)
19986#define GPC_PGC_PU0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
19987#define GPC_PGC_PU0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
19988#define GPC_PGC_PU0_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
19989/*! @} */
19990
19991/*! @name PU0_PDNSCR - GPC PGC Down Sequence Control Register */
19992/*! @{ */
19993#define GPC_PGC_PU0_PDNSCR_ISO_MASK (0x3FU)
19994#define GPC_PGC_PU0_PDNSCR_ISO_SHIFT (0U)
19995#define GPC_PGC_PU0_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU0_PDNSCR_ISO_MASK)
19996#define GPC_PGC_PU0_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
19997#define GPC_PGC_PU0_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
19998#define GPC_PGC_PU0_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU0_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
19999#define GPC_PGC_PU0_PDNSCR_ISO2SW_MASK (0x3F00U)
20000#define GPC_PGC_PU0_PDNSCR_ISO2SW_SHIFT (8U)
20001#define GPC_PGC_PU0_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU0_PDNSCR_ISO2SW_MASK)
20002#define GPC_PGC_PU0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
20003#define GPC_PGC_PU0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
20004#define GPC_PGC_PU0_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
20005#define GPC_PGC_PU0_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
20006#define GPC_PGC_PU0_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
20007#define GPC_PGC_PU0_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU0_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
20008/*! @} */
20009
20010/*! @name PU0_SR - GPC PGC Status Register */
20011/*! @{ */
20012#define GPC_PGC_PU0_SR_PSR_MASK (0x1U)
20013#define GPC_PGC_PU0_SR_PSR_SHIFT (0U)
20014/*! PSR
20015 * 0b0..The target subsystem was not powered down for the previous power-down request.
20016 * 0b1..The target subsystem was powered down for the previous power-down request.
20017 */
20018#define GPC_PGC_PU0_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_SR_PSR_SHIFT)) & GPC_PGC_PU0_SR_PSR_MASK)
20019#define GPC_PGC_PU0_SR_L2RETN_FLAG_MASK (0x2U)
20020#define GPC_PGC_PU0_SR_L2RETN_FLAG_SHIFT (1U)
20021/*! L2RETN_FLAG
20022 * 0b0..A53 is not wakeup from L2 retention mode.
20023 * 0b1..A53 is wakeup from L2 retention mode.
20024 */
20025#define GPC_PGC_PU0_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU0_SR_L2RETN_FLAG_MASK)
20026#define GPC_PGC_PU0_SR_ALLOFF_FLAG_MASK (0x4U)
20027#define GPC_PGC_PU0_SR_ALLOFF_FLAG_SHIFT (2U)
20028/*! ALLOFF_FLAG
20029 * 0b0..A53 is not wakeup from ALL_OFF mode.
20030 * 0b1..A53 is wakeup from ALL_OFF mode.
20031 */
20032#define GPC_PGC_PU0_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU0_SR_ALLOFF_FLAG_MASK)
20033#define GPC_PGC_PU0_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
20034#define GPC_PGC_PU0_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
20035/*! PUP_CLK_DIV_SEL
20036 * 0b0000..1
20037 * 0b0001..1/2 count_clk
20038 * 0b0010..1/4 count_clk
20039 * 0b0011..1/8 count_clk
20040 * 0b0100..1/16 count_clk
20041 * 0b0101..1/32 count_clk
20042 * 0b0110..1/64 count_clk
20043 * 0b0111..1/128 count_clk
20044 * 0b1000..1/256 count_clk
20045 * 0b1001..1/512 count_clk
20046 * 0b1010..1/1024 count_clk
20047 * 0b1011..1/2056 count_clk
20048 * 0b1100..1/4096 count_clk
20049 * 0b1101..1/8192 count_clk
20050 * 0b1110..1/16384 count_clk
20051 * 0b1111..1/32768 count_clk
20052 */
20053#define GPC_PGC_PU0_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU0_SR_PUP_CLK_DIV_SEL_MASK)
20054#define GPC_PGC_PU0_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
20055#define GPC_PGC_PU0_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
20056#define GPC_PGC_PU0_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU0_SR_L2RSTDIS_DEASSERT_CNT_MASK)
20057/*! @} */
20058
20059/*! @name PU0_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
20060/*! @{ */
20061#define GPC_PGC_PU0_AUXSW_SW2_MASK (0x3FU)
20062#define GPC_PGC_PU0_AUXSW_SW2_SHIFT (0U)
20063#define GPC_PGC_PU0_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_AUXSW_SW2_SHIFT)) & GPC_PGC_PU0_AUXSW_SW2_MASK)
20064#define GPC_PGC_PU0_AUXSW_ISO2SW2_MASK (0x3F00U)
20065#define GPC_PGC_PU0_AUXSW_ISO2SW2_SHIFT (8U)
20066/*! ISO2SW2
20067 * 0b000000..A53 is not wakeup from ALL_OFF mode.
20068 * 0b000001..A53 is wakeup from ALL_OFF mode.
20069 */
20070#define GPC_PGC_PU0_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU0_AUXSW_ISO2SW2_MASK)
20071#define GPC_PGC_PU0_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
20072#define GPC_PGC_PU0_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
20073/*! PDN_CLK_DIV_SEL
20074 * 0b0000..1
20075 * 0b0001..1/2 count_clk
20076 * 0b0010..1/4 count_clk
20077 * 0b0011..1/8 count_clk
20078 * 0b0100..1/16 count_clk
20079 * 0b0101..1/32 count_clk
20080 * 0b0110..1/64 count_clk
20081 * 0b0111..1/128 count_clk
20082 * 0b1000..1/256 count_clk
20083 * 0b1001..1/512 count_clk
20084 * 0b1010..1/1024 count_clk
20085 * 0b1011..1/2056 count_clk
20086 * 0b1100..1/4096 count_clk
20087 * 0b1101..1/8192 count_clk
20088 * 0b1110..1/16384 count_clk
20089 * 0b1111..1/32768 count_clk
20090 */
20091#define GPC_PGC_PU0_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU0_AUXSW_PDN_CLK_DIV_SEL_MASK)
20092/*! @} */
20093
20094/*! @name PU1_CTRL - GPC PGC Control Register */
20095/*! @{ */
20096#define GPC_PGC_PU1_CTRL_PCR_MASK (0x1U)
20097#define GPC_PGC_PU1_CTRL_PCR_SHIFT (0U)
20098/*! PCR
20099 * 0b0..Do not switch off power even if pdn_req is asserted.
20100 * 0b1..Switch off power when pdn_req is asserted.
20101 */
20102#define GPC_PGC_PU1_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_CTRL_PCR_SHIFT)) & GPC_PGC_PU1_CTRL_PCR_MASK)
20103#define GPC_PGC_PU1_CTRL_L2RSTDIS_MASK (0x7EU)
20104#define GPC_PGC_PU1_CTRL_L2RSTDIS_SHIFT (1U)
20105#define GPC_PGC_PU1_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU1_CTRL_L2RSTDIS_MASK)
20106#define GPC_PGC_PU1_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
20107#define GPC_PGC_PU1_CTRL_DFTRAM_TCD1_SHIFT (8U)
20108#define GPC_PGC_PU1_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU1_CTRL_DFTRAM_TCD1_MASK)
20109#define GPC_PGC_PU1_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
20110#define GPC_PGC_PU1_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
20111#define GPC_PGC_PU1_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU1_CTRL_L2RETN_TCD1_TDR_MASK)
20112#define GPC_PGC_PU1_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
20113#define GPC_PGC_PU1_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
20114#define GPC_PGC_PU1_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU1_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
20115/*! @} */
20116
20117/*! @name PU1_PUPSCR - GPC PGC Up Sequence Control Register */
20118/*! @{ */
20119#define GPC_PGC_PU1_PUPSCR_SW_MASK (0x3FU)
20120#define GPC_PGC_PU1_PUPSCR_SW_SHIFT (0U)
20121#define GPC_PGC_PU1_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PUPSCR_SW_SHIFT)) & GPC_PGC_PU1_PUPSCR_SW_MASK)
20122#define GPC_PGC_PU1_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
20123#define GPC_PGC_PU1_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
20124#define GPC_PGC_PU1_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU1_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
20125#define GPC_PGC_PU1_PUPSCR_SW2ISO_MASK (0x7FFF80U)
20126#define GPC_PGC_PU1_PUPSCR_SW2ISO_SHIFT (7U)
20127#define GPC_PGC_PU1_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU1_PUPSCR_SW2ISO_MASK)
20128#define GPC_PGC_PU1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
20129#define GPC_PGC_PU1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
20130#define GPC_PGC_PU1_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
20131/*! @} */
20132
20133/*! @name PU1_PDNSCR - GPC PGC Down Sequence Control Register */
20134/*! @{ */
20135#define GPC_PGC_PU1_PDNSCR_ISO_MASK (0x3FU)
20136#define GPC_PGC_PU1_PDNSCR_ISO_SHIFT (0U)
20137#define GPC_PGC_PU1_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU1_PDNSCR_ISO_MASK)
20138#define GPC_PGC_PU1_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
20139#define GPC_PGC_PU1_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
20140#define GPC_PGC_PU1_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU1_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
20141#define GPC_PGC_PU1_PDNSCR_ISO2SW_MASK (0x3F00U)
20142#define GPC_PGC_PU1_PDNSCR_ISO2SW_SHIFT (8U)
20143#define GPC_PGC_PU1_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU1_PDNSCR_ISO2SW_MASK)
20144#define GPC_PGC_PU1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
20145#define GPC_PGC_PU1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
20146#define GPC_PGC_PU1_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
20147#define GPC_PGC_PU1_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
20148#define GPC_PGC_PU1_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
20149#define GPC_PGC_PU1_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU1_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
20150/*! @} */
20151
20152/*! @name PU1_SR - GPC PGC Status Register */
20153/*! @{ */
20154#define GPC_PGC_PU1_SR_PSR_MASK (0x1U)
20155#define GPC_PGC_PU1_SR_PSR_SHIFT (0U)
20156/*! PSR
20157 * 0b0..The target subsystem was not powered down for the previous power-down request.
20158 * 0b1..The target subsystem was powered down for the previous power-down request.
20159 */
20160#define GPC_PGC_PU1_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_SR_PSR_SHIFT)) & GPC_PGC_PU1_SR_PSR_MASK)
20161#define GPC_PGC_PU1_SR_L2RETN_FLAG_MASK (0x2U)
20162#define GPC_PGC_PU1_SR_L2RETN_FLAG_SHIFT (1U)
20163/*! L2RETN_FLAG
20164 * 0b0..A53 is not wakeup from L2 retention mode.
20165 * 0b1..A53 is wakeup from L2 retention mode.
20166 */
20167#define GPC_PGC_PU1_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU1_SR_L2RETN_FLAG_MASK)
20168#define GPC_PGC_PU1_SR_ALLOFF_FLAG_MASK (0x4U)
20169#define GPC_PGC_PU1_SR_ALLOFF_FLAG_SHIFT (2U)
20170/*! ALLOFF_FLAG
20171 * 0b0..A53 is not wakeup from ALL_OFF mode.
20172 * 0b1..A53 is wakeup from ALL_OFF mode.
20173 */
20174#define GPC_PGC_PU1_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU1_SR_ALLOFF_FLAG_MASK)
20175#define GPC_PGC_PU1_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
20176#define GPC_PGC_PU1_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
20177/*! PUP_CLK_DIV_SEL
20178 * 0b0000..1
20179 * 0b0001..1/2 count_clk
20180 * 0b0010..1/4 count_clk
20181 * 0b0011..1/8 count_clk
20182 * 0b0100..1/16 count_clk
20183 * 0b0101..1/32 count_clk
20184 * 0b0110..1/64 count_clk
20185 * 0b0111..1/128 count_clk
20186 * 0b1000..1/256 count_clk
20187 * 0b1001..1/512 count_clk
20188 * 0b1010..1/1024 count_clk
20189 * 0b1011..1/2056 count_clk
20190 * 0b1100..1/4096 count_clk
20191 * 0b1101..1/8192 count_clk
20192 * 0b1110..1/16384 count_clk
20193 * 0b1111..1/32768 count_clk
20194 */
20195#define GPC_PGC_PU1_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU1_SR_PUP_CLK_DIV_SEL_MASK)
20196#define GPC_PGC_PU1_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
20197#define GPC_PGC_PU1_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
20198#define GPC_PGC_PU1_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU1_SR_L2RSTDIS_DEASSERT_CNT_MASK)
20199/*! @} */
20200
20201/*! @name PU1_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
20202/*! @{ */
20203#define GPC_PGC_PU1_AUXSW_SW2_MASK (0x3FU)
20204#define GPC_PGC_PU1_AUXSW_SW2_SHIFT (0U)
20205#define GPC_PGC_PU1_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_AUXSW_SW2_SHIFT)) & GPC_PGC_PU1_AUXSW_SW2_MASK)
20206#define GPC_PGC_PU1_AUXSW_ISO2SW2_MASK (0x3F00U)
20207#define GPC_PGC_PU1_AUXSW_ISO2SW2_SHIFT (8U)
20208/*! ISO2SW2
20209 * 0b000000..A53 is not wakeup from ALL_OFF mode.
20210 * 0b000001..A53 is wakeup from ALL_OFF mode.
20211 */
20212#define GPC_PGC_PU1_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU1_AUXSW_ISO2SW2_MASK)
20213#define GPC_PGC_PU1_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
20214#define GPC_PGC_PU1_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
20215/*! PDN_CLK_DIV_SEL
20216 * 0b0000..1
20217 * 0b0001..1/2 count_clk
20218 * 0b0010..1/4 count_clk
20219 * 0b0011..1/8 count_clk
20220 * 0b0100..1/16 count_clk
20221 * 0b0101..1/32 count_clk
20222 * 0b0110..1/64 count_clk
20223 * 0b0111..1/128 count_clk
20224 * 0b1000..1/256 count_clk
20225 * 0b1001..1/512 count_clk
20226 * 0b1010..1/1024 count_clk
20227 * 0b1011..1/2056 count_clk
20228 * 0b1100..1/4096 count_clk
20229 * 0b1101..1/8192 count_clk
20230 * 0b1110..1/16384 count_clk
20231 * 0b1111..1/32768 count_clk
20232 */
20233#define GPC_PGC_PU1_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU1_AUXSW_PDN_CLK_DIV_SEL_MASK)
20234/*! @} */
20235
20236/*! @name PU2_CTRL - GPC PGC Control Register */
20237/*! @{ */
20238#define GPC_PGC_PU2_CTRL_PCR_MASK (0x1U)
20239#define GPC_PGC_PU2_CTRL_PCR_SHIFT (0U)
20240/*! PCR
20241 * 0b0..Do not switch off power even if pdn_req is asserted.
20242 * 0b1..Switch off power when pdn_req is asserted.
20243 */
20244#define GPC_PGC_PU2_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_CTRL_PCR_SHIFT)) & GPC_PGC_PU2_CTRL_PCR_MASK)
20245#define GPC_PGC_PU2_CTRL_L2RSTDIS_MASK (0x7EU)
20246#define GPC_PGC_PU2_CTRL_L2RSTDIS_SHIFT (1U)
20247#define GPC_PGC_PU2_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU2_CTRL_L2RSTDIS_MASK)
20248#define GPC_PGC_PU2_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
20249#define GPC_PGC_PU2_CTRL_DFTRAM_TCD1_SHIFT (8U)
20250#define GPC_PGC_PU2_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU2_CTRL_DFTRAM_TCD1_MASK)
20251#define GPC_PGC_PU2_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
20252#define GPC_PGC_PU2_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
20253#define GPC_PGC_PU2_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU2_CTRL_L2RETN_TCD1_TDR_MASK)
20254#define GPC_PGC_PU2_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
20255#define GPC_PGC_PU2_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
20256#define GPC_PGC_PU2_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU2_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
20257/*! @} */
20258
20259/*! @name PU2_PUPSCR - GPC PGC Up Sequence Control Register */
20260/*! @{ */
20261#define GPC_PGC_PU2_PUPSCR_SW_MASK (0x3FU)
20262#define GPC_PGC_PU2_PUPSCR_SW_SHIFT (0U)
20263#define GPC_PGC_PU2_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PUPSCR_SW_SHIFT)) & GPC_PGC_PU2_PUPSCR_SW_MASK)
20264#define GPC_PGC_PU2_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
20265#define GPC_PGC_PU2_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
20266#define GPC_PGC_PU2_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU2_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
20267#define GPC_PGC_PU2_PUPSCR_SW2ISO_MASK (0x7FFF80U)
20268#define GPC_PGC_PU2_PUPSCR_SW2ISO_SHIFT (7U)
20269#define GPC_PGC_PU2_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU2_PUPSCR_SW2ISO_MASK)
20270#define GPC_PGC_PU2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
20271#define GPC_PGC_PU2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
20272#define GPC_PGC_PU2_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
20273/*! @} */
20274
20275/*! @name PU2_PDNSCR - GPC PGC Down Sequence Control Register */
20276/*! @{ */
20277#define GPC_PGC_PU2_PDNSCR_ISO_MASK (0x3FU)
20278#define GPC_PGC_PU2_PDNSCR_ISO_SHIFT (0U)
20279#define GPC_PGC_PU2_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU2_PDNSCR_ISO_MASK)
20280#define GPC_PGC_PU2_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
20281#define GPC_PGC_PU2_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
20282#define GPC_PGC_PU2_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU2_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
20283#define GPC_PGC_PU2_PDNSCR_ISO2SW_MASK (0x3F00U)
20284#define GPC_PGC_PU2_PDNSCR_ISO2SW_SHIFT (8U)
20285#define GPC_PGC_PU2_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU2_PDNSCR_ISO2SW_MASK)
20286#define GPC_PGC_PU2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
20287#define GPC_PGC_PU2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
20288#define GPC_PGC_PU2_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
20289#define GPC_PGC_PU2_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
20290#define GPC_PGC_PU2_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
20291#define GPC_PGC_PU2_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU2_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
20292/*! @} */
20293
20294/*! @name PU2_SR - GPC PGC Status Register */
20295/*! @{ */
20296#define GPC_PGC_PU2_SR_PSR_MASK (0x1U)
20297#define GPC_PGC_PU2_SR_PSR_SHIFT (0U)
20298/*! PSR
20299 * 0b0..The target subsystem was not powered down for the previous power-down request.
20300 * 0b1..The target subsystem was powered down for the previous power-down request.
20301 */
20302#define GPC_PGC_PU2_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_SR_PSR_SHIFT)) & GPC_PGC_PU2_SR_PSR_MASK)
20303#define GPC_PGC_PU2_SR_L2RETN_FLAG_MASK (0x2U)
20304#define GPC_PGC_PU2_SR_L2RETN_FLAG_SHIFT (1U)
20305/*! L2RETN_FLAG
20306 * 0b0..A53 is not wakeup from L2 retention mode.
20307 * 0b1..A53 is wakeup from L2 retention mode.
20308 */
20309#define GPC_PGC_PU2_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU2_SR_L2RETN_FLAG_MASK)
20310#define GPC_PGC_PU2_SR_ALLOFF_FLAG_MASK (0x4U)
20311#define GPC_PGC_PU2_SR_ALLOFF_FLAG_SHIFT (2U)
20312/*! ALLOFF_FLAG
20313 * 0b0..A53 is not wakeup from ALL_OFF mode.
20314 * 0b1..A53 is wakeup from ALL_OFF mode.
20315 */
20316#define GPC_PGC_PU2_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU2_SR_ALLOFF_FLAG_MASK)
20317#define GPC_PGC_PU2_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
20318#define GPC_PGC_PU2_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
20319/*! PUP_CLK_DIV_SEL
20320 * 0b0000..1
20321 * 0b0001..1/2 count_clk
20322 * 0b0010..1/4 count_clk
20323 * 0b0011..1/8 count_clk
20324 * 0b0100..1/16 count_clk
20325 * 0b0101..1/32 count_clk
20326 * 0b0110..1/64 count_clk
20327 * 0b0111..1/128 count_clk
20328 * 0b1000..1/256 count_clk
20329 * 0b1001..1/512 count_clk
20330 * 0b1010..1/1024 count_clk
20331 * 0b1011..1/2056 count_clk
20332 * 0b1100..1/4096 count_clk
20333 * 0b1101..1/8192 count_clk
20334 * 0b1110..1/16384 count_clk
20335 * 0b1111..1/32768 count_clk
20336 */
20337#define GPC_PGC_PU2_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU2_SR_PUP_CLK_DIV_SEL_MASK)
20338#define GPC_PGC_PU2_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
20339#define GPC_PGC_PU2_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
20340#define GPC_PGC_PU2_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU2_SR_L2RSTDIS_DEASSERT_CNT_MASK)
20341/*! @} */
20342
20343/*! @name PU2_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
20344/*! @{ */
20345#define GPC_PGC_PU2_AUXSW_SW2_MASK (0x3FU)
20346#define GPC_PGC_PU2_AUXSW_SW2_SHIFT (0U)
20347#define GPC_PGC_PU2_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_AUXSW_SW2_SHIFT)) & GPC_PGC_PU2_AUXSW_SW2_MASK)
20348#define GPC_PGC_PU2_AUXSW_ISO2SW2_MASK (0x3F00U)
20349#define GPC_PGC_PU2_AUXSW_ISO2SW2_SHIFT (8U)
20350/*! ISO2SW2
20351 * 0b000000..A53 is not wakeup from ALL_OFF mode.
20352 * 0b000001..A53 is wakeup from ALL_OFF mode.
20353 */
20354#define GPC_PGC_PU2_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU2_AUXSW_ISO2SW2_MASK)
20355#define GPC_PGC_PU2_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
20356#define GPC_PGC_PU2_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
20357/*! PDN_CLK_DIV_SEL
20358 * 0b0000..1
20359 * 0b0001..1/2 count_clk
20360 * 0b0010..1/4 count_clk
20361 * 0b0011..1/8 count_clk
20362 * 0b0100..1/16 count_clk
20363 * 0b0101..1/32 count_clk
20364 * 0b0110..1/64 count_clk
20365 * 0b0111..1/128 count_clk
20366 * 0b1000..1/256 count_clk
20367 * 0b1001..1/512 count_clk
20368 * 0b1010..1/1024 count_clk
20369 * 0b1011..1/2056 count_clk
20370 * 0b1100..1/4096 count_clk
20371 * 0b1101..1/8192 count_clk
20372 * 0b1110..1/16384 count_clk
20373 * 0b1111..1/32768 count_clk
20374 */
20375#define GPC_PGC_PU2_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU2_AUXSW_PDN_CLK_DIV_SEL_MASK)
20376/*! @} */
20377
20378/*! @name PU3_CTRL - GPC PGC Control Register */
20379/*! @{ */
20380#define GPC_PGC_PU3_CTRL_PCR_MASK (0x1U)
20381#define GPC_PGC_PU3_CTRL_PCR_SHIFT (0U)
20382/*! PCR
20383 * 0b0..Do not switch off power even if pdn_req is asserted.
20384 * 0b1..Switch off power when pdn_req is asserted.
20385 */
20386#define GPC_PGC_PU3_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_CTRL_PCR_SHIFT)) & GPC_PGC_PU3_CTRL_PCR_MASK)
20387#define GPC_PGC_PU3_CTRL_L2RSTDIS_MASK (0x7EU)
20388#define GPC_PGC_PU3_CTRL_L2RSTDIS_SHIFT (1U)
20389#define GPC_PGC_PU3_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU3_CTRL_L2RSTDIS_MASK)
20390#define GPC_PGC_PU3_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
20391#define GPC_PGC_PU3_CTRL_DFTRAM_TCD1_SHIFT (8U)
20392#define GPC_PGC_PU3_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU3_CTRL_DFTRAM_TCD1_MASK)
20393#define GPC_PGC_PU3_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
20394#define GPC_PGC_PU3_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
20395#define GPC_PGC_PU3_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU3_CTRL_L2RETN_TCD1_TDR_MASK)
20396#define GPC_PGC_PU3_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
20397#define GPC_PGC_PU3_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
20398#define GPC_PGC_PU3_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU3_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
20399/*! @} */
20400
20401/*! @name PU3_PUPSCR - GPC PGC Up Sequence Control Register */
20402/*! @{ */
20403#define GPC_PGC_PU3_PUPSCR_SW_MASK (0x3FU)
20404#define GPC_PGC_PU3_PUPSCR_SW_SHIFT (0U)
20405#define GPC_PGC_PU3_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PUPSCR_SW_SHIFT)) & GPC_PGC_PU3_PUPSCR_SW_MASK)
20406#define GPC_PGC_PU3_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
20407#define GPC_PGC_PU3_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
20408#define GPC_PGC_PU3_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU3_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
20409#define GPC_PGC_PU3_PUPSCR_SW2ISO_MASK (0x7FFF80U)
20410#define GPC_PGC_PU3_PUPSCR_SW2ISO_SHIFT (7U)
20411#define GPC_PGC_PU3_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU3_PUPSCR_SW2ISO_MASK)
20412#define GPC_PGC_PU3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
20413#define GPC_PGC_PU3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
20414#define GPC_PGC_PU3_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
20415/*! @} */
20416
20417/*! @name PU3_PDNSCR - GPC PGC Down Sequence Control Register */
20418/*! @{ */
20419#define GPC_PGC_PU3_PDNSCR_ISO_MASK (0x3FU)
20420#define GPC_PGC_PU3_PDNSCR_ISO_SHIFT (0U)
20421#define GPC_PGC_PU3_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU3_PDNSCR_ISO_MASK)
20422#define GPC_PGC_PU3_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
20423#define GPC_PGC_PU3_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
20424#define GPC_PGC_PU3_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU3_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
20425#define GPC_PGC_PU3_PDNSCR_ISO2SW_MASK (0x3F00U)
20426#define GPC_PGC_PU3_PDNSCR_ISO2SW_SHIFT (8U)
20427#define GPC_PGC_PU3_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU3_PDNSCR_ISO2SW_MASK)
20428#define GPC_PGC_PU3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
20429#define GPC_PGC_PU3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
20430#define GPC_PGC_PU3_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
20431#define GPC_PGC_PU3_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
20432#define GPC_PGC_PU3_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
20433#define GPC_PGC_PU3_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU3_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
20434/*! @} */
20435
20436/*! @name PU3_SR - GPC PGC Status Register */
20437/*! @{ */
20438#define GPC_PGC_PU3_SR_PSR_MASK (0x1U)
20439#define GPC_PGC_PU3_SR_PSR_SHIFT (0U)
20440/*! PSR
20441 * 0b0..The target subsystem was not powered down for the previous power-down request.
20442 * 0b1..The target subsystem was powered down for the previous power-down request.
20443 */
20444#define GPC_PGC_PU3_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_SR_PSR_SHIFT)) & GPC_PGC_PU3_SR_PSR_MASK)
20445#define GPC_PGC_PU3_SR_L2RETN_FLAG_MASK (0x2U)
20446#define GPC_PGC_PU3_SR_L2RETN_FLAG_SHIFT (1U)
20447/*! L2RETN_FLAG
20448 * 0b0..A53 is not wakeup from L2 retention mode.
20449 * 0b1..A53 is wakeup from L2 retention mode.
20450 */
20451#define GPC_PGC_PU3_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU3_SR_L2RETN_FLAG_MASK)
20452#define GPC_PGC_PU3_SR_ALLOFF_FLAG_MASK (0x4U)
20453#define GPC_PGC_PU3_SR_ALLOFF_FLAG_SHIFT (2U)
20454/*! ALLOFF_FLAG
20455 * 0b0..A53 is not wakeup from ALL_OFF mode.
20456 * 0b1..A53 is wakeup from ALL_OFF mode.
20457 */
20458#define GPC_PGC_PU3_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU3_SR_ALLOFF_FLAG_MASK)
20459#define GPC_PGC_PU3_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
20460#define GPC_PGC_PU3_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
20461/*! PUP_CLK_DIV_SEL
20462 * 0b0000..1
20463 * 0b0001..1/2 count_clk
20464 * 0b0010..1/4 count_clk
20465 * 0b0011..1/8 count_clk
20466 * 0b0100..1/16 count_clk
20467 * 0b0101..1/32 count_clk
20468 * 0b0110..1/64 count_clk
20469 * 0b0111..1/128 count_clk
20470 * 0b1000..1/256 count_clk
20471 * 0b1001..1/512 count_clk
20472 * 0b1010..1/1024 count_clk
20473 * 0b1011..1/2056 count_clk
20474 * 0b1100..1/4096 count_clk
20475 * 0b1101..1/8192 count_clk
20476 * 0b1110..1/16384 count_clk
20477 * 0b1111..1/32768 count_clk
20478 */
20479#define GPC_PGC_PU3_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU3_SR_PUP_CLK_DIV_SEL_MASK)
20480#define GPC_PGC_PU3_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
20481#define GPC_PGC_PU3_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
20482#define GPC_PGC_PU3_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU3_SR_L2RSTDIS_DEASSERT_CNT_MASK)
20483/*! @} */
20484
20485/*! @name PU3_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
20486/*! @{ */
20487#define GPC_PGC_PU3_AUXSW_SW2_MASK (0x3FU)
20488#define GPC_PGC_PU3_AUXSW_SW2_SHIFT (0U)
20489#define GPC_PGC_PU3_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_AUXSW_SW2_SHIFT)) & GPC_PGC_PU3_AUXSW_SW2_MASK)
20490#define GPC_PGC_PU3_AUXSW_ISO2SW2_MASK (0x3F00U)
20491#define GPC_PGC_PU3_AUXSW_ISO2SW2_SHIFT (8U)
20492/*! ISO2SW2
20493 * 0b000000..A53 is not wakeup from ALL_OFF mode.
20494 * 0b000001..A53 is wakeup from ALL_OFF mode.
20495 */
20496#define GPC_PGC_PU3_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU3_AUXSW_ISO2SW2_MASK)
20497#define GPC_PGC_PU3_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
20498#define GPC_PGC_PU3_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
20499/*! PDN_CLK_DIV_SEL
20500 * 0b0000..1
20501 * 0b0001..1/2 count_clk
20502 * 0b0010..1/4 count_clk
20503 * 0b0011..1/8 count_clk
20504 * 0b0100..1/16 count_clk
20505 * 0b0101..1/32 count_clk
20506 * 0b0110..1/64 count_clk
20507 * 0b0111..1/128 count_clk
20508 * 0b1000..1/256 count_clk
20509 * 0b1001..1/512 count_clk
20510 * 0b1010..1/1024 count_clk
20511 * 0b1011..1/2056 count_clk
20512 * 0b1100..1/4096 count_clk
20513 * 0b1101..1/8192 count_clk
20514 * 0b1110..1/16384 count_clk
20515 * 0b1111..1/32768 count_clk
20516 */
20517#define GPC_PGC_PU3_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU3_AUXSW_PDN_CLK_DIV_SEL_MASK)
20518/*! @} */
20519
20520/*! @name PU4_CTRL - GPC PGC Control Register */
20521/*! @{ */
20522#define GPC_PGC_PU4_CTRL_PCR_MASK (0x1U)
20523#define GPC_PGC_PU4_CTRL_PCR_SHIFT (0U)
20524/*! PCR
20525 * 0b0..Do not switch off power even if pdn_req is asserted.
20526 * 0b1..Switch off power when pdn_req is asserted.
20527 */
20528#define GPC_PGC_PU4_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_CTRL_PCR_SHIFT)) & GPC_PGC_PU4_CTRL_PCR_MASK)
20529#define GPC_PGC_PU4_CTRL_L2RSTDIS_MASK (0x7EU)
20530#define GPC_PGC_PU4_CTRL_L2RSTDIS_SHIFT (1U)
20531#define GPC_PGC_PU4_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU4_CTRL_L2RSTDIS_MASK)
20532#define GPC_PGC_PU4_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
20533#define GPC_PGC_PU4_CTRL_DFTRAM_TCD1_SHIFT (8U)
20534#define GPC_PGC_PU4_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU4_CTRL_DFTRAM_TCD1_MASK)
20535#define GPC_PGC_PU4_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
20536#define GPC_PGC_PU4_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
20537#define GPC_PGC_PU4_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU4_CTRL_L2RETN_TCD1_TDR_MASK)
20538#define GPC_PGC_PU4_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
20539#define GPC_PGC_PU4_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
20540#define GPC_PGC_PU4_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU4_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
20541/*! @} */
20542
20543/*! @name PU4_PUPSCR - GPC PGC Up Sequence Control Register */
20544/*! @{ */
20545#define GPC_PGC_PU4_PUPSCR_SW_MASK (0x3FU)
20546#define GPC_PGC_PU4_PUPSCR_SW_SHIFT (0U)
20547#define GPC_PGC_PU4_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PUPSCR_SW_SHIFT)) & GPC_PGC_PU4_PUPSCR_SW_MASK)
20548#define GPC_PGC_PU4_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
20549#define GPC_PGC_PU4_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
20550#define GPC_PGC_PU4_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU4_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
20551#define GPC_PGC_PU4_PUPSCR_SW2ISO_MASK (0x7FFF80U)
20552#define GPC_PGC_PU4_PUPSCR_SW2ISO_SHIFT (7U)
20553#define GPC_PGC_PU4_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU4_PUPSCR_SW2ISO_MASK)
20554#define GPC_PGC_PU4_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
20555#define GPC_PGC_PU4_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
20556#define GPC_PGC_PU4_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU4_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
20557/*! @} */
20558
20559/*! @name PU4_PDNSCR - GPC PGC Down Sequence Control Register */
20560/*! @{ */
20561#define GPC_PGC_PU4_PDNSCR_ISO_MASK (0x3FU)
20562#define GPC_PGC_PU4_PDNSCR_ISO_SHIFT (0U)
20563#define GPC_PGC_PU4_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU4_PDNSCR_ISO_MASK)
20564#define GPC_PGC_PU4_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
20565#define GPC_PGC_PU4_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
20566#define GPC_PGC_PU4_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU4_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
20567#define GPC_PGC_PU4_PDNSCR_ISO2SW_MASK (0x3F00U)
20568#define GPC_PGC_PU4_PDNSCR_ISO2SW_SHIFT (8U)
20569#define GPC_PGC_PU4_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU4_PDNSCR_ISO2SW_MASK)
20570#define GPC_PGC_PU4_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
20571#define GPC_PGC_PU4_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
20572#define GPC_PGC_PU4_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU4_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
20573#define GPC_PGC_PU4_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
20574#define GPC_PGC_PU4_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
20575#define GPC_PGC_PU4_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU4_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
20576/*! @} */
20577
20578/*! @name PU4_SR - GPC PGC Status Register */
20579/*! @{ */
20580#define GPC_PGC_PU4_SR_PSR_MASK (0x1U)
20581#define GPC_PGC_PU4_SR_PSR_SHIFT (0U)
20582/*! PSR
20583 * 0b0..The target subsystem was not powered down for the previous power-down request.
20584 * 0b1..The target subsystem was powered down for the previous power-down request.
20585 */
20586#define GPC_PGC_PU4_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_SR_PSR_SHIFT)) & GPC_PGC_PU4_SR_PSR_MASK)
20587#define GPC_PGC_PU4_SR_L2RETN_FLAG_MASK (0x2U)
20588#define GPC_PGC_PU4_SR_L2RETN_FLAG_SHIFT (1U)
20589/*! L2RETN_FLAG
20590 * 0b0..A53 is not wakeup from L2 retention mode.
20591 * 0b1..A53 is wakeup from L2 retention mode.
20592 */
20593#define GPC_PGC_PU4_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU4_SR_L2RETN_FLAG_MASK)
20594#define GPC_PGC_PU4_SR_ALLOFF_FLAG_MASK (0x4U)
20595#define GPC_PGC_PU4_SR_ALLOFF_FLAG_SHIFT (2U)
20596/*! ALLOFF_FLAG
20597 * 0b0..A53 is not wakeup from ALL_OFF mode.
20598 * 0b1..A53 is wakeup from ALL_OFF mode.
20599 */
20600#define GPC_PGC_PU4_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU4_SR_ALLOFF_FLAG_MASK)
20601#define GPC_PGC_PU4_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
20602#define GPC_PGC_PU4_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
20603/*! PUP_CLK_DIV_SEL
20604 * 0b0000..1
20605 * 0b0001..1/2 count_clk
20606 * 0b0010..1/4 count_clk
20607 * 0b0011..1/8 count_clk
20608 * 0b0100..1/16 count_clk
20609 * 0b0101..1/32 count_clk
20610 * 0b0110..1/64 count_clk
20611 * 0b0111..1/128 count_clk
20612 * 0b1000..1/256 count_clk
20613 * 0b1001..1/512 count_clk
20614 * 0b1010..1/1024 count_clk
20615 * 0b1011..1/2056 count_clk
20616 * 0b1100..1/4096 count_clk
20617 * 0b1101..1/8192 count_clk
20618 * 0b1110..1/16384 count_clk
20619 * 0b1111..1/32768 count_clk
20620 */
20621#define GPC_PGC_PU4_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU4_SR_PUP_CLK_DIV_SEL_MASK)
20622#define GPC_PGC_PU4_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
20623#define GPC_PGC_PU4_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
20624#define GPC_PGC_PU4_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU4_SR_L2RSTDIS_DEASSERT_CNT_MASK)
20625/*! @} */
20626
20627/*! @name PU4_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
20628/*! @{ */
20629#define GPC_PGC_PU4_AUXSW_SW2_MASK (0x3FU)
20630#define GPC_PGC_PU4_AUXSW_SW2_SHIFT (0U)
20631#define GPC_PGC_PU4_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_AUXSW_SW2_SHIFT)) & GPC_PGC_PU4_AUXSW_SW2_MASK)
20632#define GPC_PGC_PU4_AUXSW_ISO2SW2_MASK (0x3F00U)
20633#define GPC_PGC_PU4_AUXSW_ISO2SW2_SHIFT (8U)
20634/*! ISO2SW2
20635 * 0b000000..A53 is not wakeup from ALL_OFF mode.
20636 * 0b000001..A53 is wakeup from ALL_OFF mode.
20637 */
20638#define GPC_PGC_PU4_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU4_AUXSW_ISO2SW2_MASK)
20639#define GPC_PGC_PU4_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
20640#define GPC_PGC_PU4_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
20641/*! PDN_CLK_DIV_SEL
20642 * 0b0000..1
20643 * 0b0001..1/2 count_clk
20644 * 0b0010..1/4 count_clk
20645 * 0b0011..1/8 count_clk
20646 * 0b0100..1/16 count_clk
20647 * 0b0101..1/32 count_clk
20648 * 0b0110..1/64 count_clk
20649 * 0b0111..1/128 count_clk
20650 * 0b1000..1/256 count_clk
20651 * 0b1001..1/512 count_clk
20652 * 0b1010..1/1024 count_clk
20653 * 0b1011..1/2056 count_clk
20654 * 0b1100..1/4096 count_clk
20655 * 0b1101..1/8192 count_clk
20656 * 0b1110..1/16384 count_clk
20657 * 0b1111..1/32768 count_clk
20658 */
20659#define GPC_PGC_PU4_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU4_AUXSW_PDN_CLK_DIV_SEL_MASK)
20660/*! @} */
20661
20662/*! @name PU5_CTRL - GPC PGC Control Register */
20663/*! @{ */
20664#define GPC_PGC_PU5_CTRL_PCR_MASK (0x1U)
20665#define GPC_PGC_PU5_CTRL_PCR_SHIFT (0U)
20666/*! PCR
20667 * 0b0..Do not switch off power even if pdn_req is asserted.
20668 * 0b1..Switch off power when pdn_req is asserted.
20669 */
20670#define GPC_PGC_PU5_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_CTRL_PCR_SHIFT)) & GPC_PGC_PU5_CTRL_PCR_MASK)
20671#define GPC_PGC_PU5_CTRL_L2RSTDIS_MASK (0x7EU)
20672#define GPC_PGC_PU5_CTRL_L2RSTDIS_SHIFT (1U)
20673#define GPC_PGC_PU5_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU5_CTRL_L2RSTDIS_MASK)
20674#define GPC_PGC_PU5_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
20675#define GPC_PGC_PU5_CTRL_DFTRAM_TCD1_SHIFT (8U)
20676#define GPC_PGC_PU5_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU5_CTRL_DFTRAM_TCD1_MASK)
20677#define GPC_PGC_PU5_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
20678#define GPC_PGC_PU5_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
20679#define GPC_PGC_PU5_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU5_CTRL_L2RETN_TCD1_TDR_MASK)
20680#define GPC_PGC_PU5_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
20681#define GPC_PGC_PU5_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
20682#define GPC_PGC_PU5_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU5_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
20683/*! @} */
20684
20685/*! @name PU5_PUPSCR - GPC PGC Up Sequence Control Register */
20686/*! @{ */
20687#define GPC_PGC_PU5_PUPSCR_SW_MASK (0x3FU)
20688#define GPC_PGC_PU5_PUPSCR_SW_SHIFT (0U)
20689#define GPC_PGC_PU5_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PUPSCR_SW_SHIFT)) & GPC_PGC_PU5_PUPSCR_SW_MASK)
20690#define GPC_PGC_PU5_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
20691#define GPC_PGC_PU5_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
20692#define GPC_PGC_PU5_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU5_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
20693#define GPC_PGC_PU5_PUPSCR_SW2ISO_MASK (0x7FFF80U)
20694#define GPC_PGC_PU5_PUPSCR_SW2ISO_SHIFT (7U)
20695#define GPC_PGC_PU5_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU5_PUPSCR_SW2ISO_MASK)
20696#define GPC_PGC_PU5_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
20697#define GPC_PGC_PU5_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
20698#define GPC_PGC_PU5_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU5_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
20699/*! @} */
20700
20701/*! @name PU5_PDNSCR - GPC PGC Down Sequence Control Register */
20702/*! @{ */
20703#define GPC_PGC_PU5_PDNSCR_ISO_MASK (0x3FU)
20704#define GPC_PGC_PU5_PDNSCR_ISO_SHIFT (0U)
20705#define GPC_PGC_PU5_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU5_PDNSCR_ISO_MASK)
20706#define GPC_PGC_PU5_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
20707#define GPC_PGC_PU5_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
20708#define GPC_PGC_PU5_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU5_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
20709#define GPC_PGC_PU5_PDNSCR_ISO2SW_MASK (0x3F00U)
20710#define GPC_PGC_PU5_PDNSCR_ISO2SW_SHIFT (8U)
20711#define GPC_PGC_PU5_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU5_PDNSCR_ISO2SW_MASK)
20712#define GPC_PGC_PU5_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
20713#define GPC_PGC_PU5_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
20714#define GPC_PGC_PU5_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU5_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
20715#define GPC_PGC_PU5_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
20716#define GPC_PGC_PU5_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
20717#define GPC_PGC_PU5_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU5_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
20718/*! @} */
20719
20720/*! @name PU5_SR - GPC PGC Status Register */
20721/*! @{ */
20722#define GPC_PGC_PU5_SR_PSR_MASK (0x1U)
20723#define GPC_PGC_PU5_SR_PSR_SHIFT (0U)
20724/*! PSR
20725 * 0b0..The target subsystem was not powered down for the previous power-down request.
20726 * 0b1..The target subsystem was powered down for the previous power-down request.
20727 */
20728#define GPC_PGC_PU5_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_SR_PSR_SHIFT)) & GPC_PGC_PU5_SR_PSR_MASK)
20729#define GPC_PGC_PU5_SR_L2RETN_FLAG_MASK (0x2U)
20730#define GPC_PGC_PU5_SR_L2RETN_FLAG_SHIFT (1U)
20731/*! L2RETN_FLAG
20732 * 0b0..A53 is not wakeup from L2 retention mode.
20733 * 0b1..A53 is wakeup from L2 retention mode.
20734 */
20735#define GPC_PGC_PU5_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU5_SR_L2RETN_FLAG_MASK)
20736#define GPC_PGC_PU5_SR_ALLOFF_FLAG_MASK (0x4U)
20737#define GPC_PGC_PU5_SR_ALLOFF_FLAG_SHIFT (2U)
20738/*! ALLOFF_FLAG
20739 * 0b0..A53 is not wakeup from ALL_OFF mode.
20740 * 0b1..A53 is wakeup from ALL_OFF mode.
20741 */
20742#define GPC_PGC_PU5_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU5_SR_ALLOFF_FLAG_MASK)
20743#define GPC_PGC_PU5_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
20744#define GPC_PGC_PU5_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
20745/*! PUP_CLK_DIV_SEL
20746 * 0b0000..1
20747 * 0b0001..1/2 count_clk
20748 * 0b0010..1/4 count_clk
20749 * 0b0011..1/8 count_clk
20750 * 0b0100..1/16 count_clk
20751 * 0b0101..1/32 count_clk
20752 * 0b0110..1/64 count_clk
20753 * 0b0111..1/128 count_clk
20754 * 0b1000..1/256 count_clk
20755 * 0b1001..1/512 count_clk
20756 * 0b1010..1/1024 count_clk
20757 * 0b1011..1/2056 count_clk
20758 * 0b1100..1/4096 count_clk
20759 * 0b1101..1/8192 count_clk
20760 * 0b1110..1/16384 count_clk
20761 * 0b1111..1/32768 count_clk
20762 */
20763#define GPC_PGC_PU5_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU5_SR_PUP_CLK_DIV_SEL_MASK)
20764#define GPC_PGC_PU5_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
20765#define GPC_PGC_PU5_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
20766#define GPC_PGC_PU5_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU5_SR_L2RSTDIS_DEASSERT_CNT_MASK)
20767/*! @} */
20768
20769/*! @name PU5_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
20770/*! @{ */
20771#define GPC_PGC_PU5_AUXSW_SW2_MASK (0x3FU)
20772#define GPC_PGC_PU5_AUXSW_SW2_SHIFT (0U)
20773#define GPC_PGC_PU5_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_AUXSW_SW2_SHIFT)) & GPC_PGC_PU5_AUXSW_SW2_MASK)
20774#define GPC_PGC_PU5_AUXSW_ISO2SW2_MASK (0x3F00U)
20775#define GPC_PGC_PU5_AUXSW_ISO2SW2_SHIFT (8U)
20776/*! ISO2SW2
20777 * 0b000000..A53 is not wakeup from ALL_OFF mode.
20778 * 0b000001..A53 is wakeup from ALL_OFF mode.
20779 */
20780#define GPC_PGC_PU5_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU5_AUXSW_ISO2SW2_MASK)
20781#define GPC_PGC_PU5_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
20782#define GPC_PGC_PU5_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
20783/*! PDN_CLK_DIV_SEL
20784 * 0b0000..1
20785 * 0b0001..1/2 count_clk
20786 * 0b0010..1/4 count_clk
20787 * 0b0011..1/8 count_clk
20788 * 0b0100..1/16 count_clk
20789 * 0b0101..1/32 count_clk
20790 * 0b0110..1/64 count_clk
20791 * 0b0111..1/128 count_clk
20792 * 0b1000..1/256 count_clk
20793 * 0b1001..1/512 count_clk
20794 * 0b1010..1/1024 count_clk
20795 * 0b1011..1/2056 count_clk
20796 * 0b1100..1/4096 count_clk
20797 * 0b1101..1/8192 count_clk
20798 * 0b1110..1/16384 count_clk
20799 * 0b1111..1/32768 count_clk
20800 */
20801#define GPC_PGC_PU5_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU5_AUXSW_PDN_CLK_DIV_SEL_MASK)
20802/*! @} */
20803
20804/*! @name PU6_CTRL - GPC PGC Control Register */
20805/*! @{ */
20806#define GPC_PGC_PU6_CTRL_PCR_MASK (0x1U)
20807#define GPC_PGC_PU6_CTRL_PCR_SHIFT (0U)
20808/*! PCR
20809 * 0b0..Do not switch off power even if pdn_req is asserted.
20810 * 0b1..Switch off power when pdn_req is asserted.
20811 */
20812#define GPC_PGC_PU6_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_CTRL_PCR_SHIFT)) & GPC_PGC_PU6_CTRL_PCR_MASK)
20813#define GPC_PGC_PU6_CTRL_L2RSTDIS_MASK (0x7EU)
20814#define GPC_PGC_PU6_CTRL_L2RSTDIS_SHIFT (1U)
20815#define GPC_PGC_PU6_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU6_CTRL_L2RSTDIS_MASK)
20816#define GPC_PGC_PU6_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
20817#define GPC_PGC_PU6_CTRL_DFTRAM_TCD1_SHIFT (8U)
20818#define GPC_PGC_PU6_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU6_CTRL_DFTRAM_TCD1_MASK)
20819#define GPC_PGC_PU6_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
20820#define GPC_PGC_PU6_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
20821#define GPC_PGC_PU6_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU6_CTRL_L2RETN_TCD1_TDR_MASK)
20822#define GPC_PGC_PU6_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
20823#define GPC_PGC_PU6_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
20824#define GPC_PGC_PU6_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU6_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
20825/*! @} */
20826
20827/*! @name PU6_PUPSCR - GPC PGC Up Sequence Control Register */
20828/*! @{ */
20829#define GPC_PGC_PU6_PUPSCR_SW_MASK (0x3FU)
20830#define GPC_PGC_PU6_PUPSCR_SW_SHIFT (0U)
20831#define GPC_PGC_PU6_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PUPSCR_SW_SHIFT)) & GPC_PGC_PU6_PUPSCR_SW_MASK)
20832#define GPC_PGC_PU6_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
20833#define GPC_PGC_PU6_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
20834#define GPC_PGC_PU6_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU6_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
20835#define GPC_PGC_PU6_PUPSCR_SW2ISO_MASK (0x7FFF80U)
20836#define GPC_PGC_PU6_PUPSCR_SW2ISO_SHIFT (7U)
20837#define GPC_PGC_PU6_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU6_PUPSCR_SW2ISO_MASK)
20838#define GPC_PGC_PU6_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
20839#define GPC_PGC_PU6_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
20840#define GPC_PGC_PU6_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU6_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
20841/*! @} */
20842
20843/*! @name PU6_PDNSCR - GPC PGC Down Sequence Control Register */
20844/*! @{ */
20845#define GPC_PGC_PU6_PDNSCR_ISO_MASK (0x3FU)
20846#define GPC_PGC_PU6_PDNSCR_ISO_SHIFT (0U)
20847#define GPC_PGC_PU6_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU6_PDNSCR_ISO_MASK)
20848#define GPC_PGC_PU6_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
20849#define GPC_PGC_PU6_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
20850#define GPC_PGC_PU6_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU6_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
20851#define GPC_PGC_PU6_PDNSCR_ISO2SW_MASK (0x3F00U)
20852#define GPC_PGC_PU6_PDNSCR_ISO2SW_SHIFT (8U)
20853#define GPC_PGC_PU6_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU6_PDNSCR_ISO2SW_MASK)
20854#define GPC_PGC_PU6_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
20855#define GPC_PGC_PU6_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
20856#define GPC_PGC_PU6_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU6_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
20857#define GPC_PGC_PU6_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
20858#define GPC_PGC_PU6_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
20859#define GPC_PGC_PU6_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU6_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
20860/*! @} */
20861
20862/*! @name PU6_SR - GPC PGC Status Register */
20863/*! @{ */
20864#define GPC_PGC_PU6_SR_PSR_MASK (0x1U)
20865#define GPC_PGC_PU6_SR_PSR_SHIFT (0U)
20866/*! PSR
20867 * 0b0..The target subsystem was not powered down for the previous power-down request.
20868 * 0b1..The target subsystem was powered down for the previous power-down request.
20869 */
20870#define GPC_PGC_PU6_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_SR_PSR_SHIFT)) & GPC_PGC_PU6_SR_PSR_MASK)
20871#define GPC_PGC_PU6_SR_L2RETN_FLAG_MASK (0x2U)
20872#define GPC_PGC_PU6_SR_L2RETN_FLAG_SHIFT (1U)
20873/*! L2RETN_FLAG
20874 * 0b0..A53 is not wakeup from L2 retention mode.
20875 * 0b1..A53 is wakeup from L2 retention mode.
20876 */
20877#define GPC_PGC_PU6_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU6_SR_L2RETN_FLAG_MASK)
20878#define GPC_PGC_PU6_SR_ALLOFF_FLAG_MASK (0x4U)
20879#define GPC_PGC_PU6_SR_ALLOFF_FLAG_SHIFT (2U)
20880/*! ALLOFF_FLAG
20881 * 0b0..A53 is not wakeup from ALL_OFF mode.
20882 * 0b1..A53 is wakeup from ALL_OFF mode.
20883 */
20884#define GPC_PGC_PU6_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU6_SR_ALLOFF_FLAG_MASK)
20885#define GPC_PGC_PU6_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
20886#define GPC_PGC_PU6_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
20887/*! PUP_CLK_DIV_SEL
20888 * 0b0000..1
20889 * 0b0001..1/2 count_clk
20890 * 0b0010..1/4 count_clk
20891 * 0b0011..1/8 count_clk
20892 * 0b0100..1/16 count_clk
20893 * 0b0101..1/32 count_clk
20894 * 0b0110..1/64 count_clk
20895 * 0b0111..1/128 count_clk
20896 * 0b1000..1/256 count_clk
20897 * 0b1001..1/512 count_clk
20898 * 0b1010..1/1024 count_clk
20899 * 0b1011..1/2056 count_clk
20900 * 0b1100..1/4096 count_clk
20901 * 0b1101..1/8192 count_clk
20902 * 0b1110..1/16384 count_clk
20903 * 0b1111..1/32768 count_clk
20904 */
20905#define GPC_PGC_PU6_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU6_SR_PUP_CLK_DIV_SEL_MASK)
20906#define GPC_PGC_PU6_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
20907#define GPC_PGC_PU6_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
20908#define GPC_PGC_PU6_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU6_SR_L2RSTDIS_DEASSERT_CNT_MASK)
20909/*! @} */
20910
20911/*! @name PU6_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
20912/*! @{ */
20913#define GPC_PGC_PU6_AUXSW_SW2_MASK (0x3FU)
20914#define GPC_PGC_PU6_AUXSW_SW2_SHIFT (0U)
20915#define GPC_PGC_PU6_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_AUXSW_SW2_SHIFT)) & GPC_PGC_PU6_AUXSW_SW2_MASK)
20916#define GPC_PGC_PU6_AUXSW_ISO2SW2_MASK (0x3F00U)
20917#define GPC_PGC_PU6_AUXSW_ISO2SW2_SHIFT (8U)
20918/*! ISO2SW2
20919 * 0b000000..A53 is not wakeup from ALL_OFF mode.
20920 * 0b000001..A53 is wakeup from ALL_OFF mode.
20921 */
20922#define GPC_PGC_PU6_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU6_AUXSW_ISO2SW2_MASK)
20923#define GPC_PGC_PU6_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
20924#define GPC_PGC_PU6_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
20925/*! PDN_CLK_DIV_SEL
20926 * 0b0000..1
20927 * 0b0001..1/2 count_clk
20928 * 0b0010..1/4 count_clk
20929 * 0b0011..1/8 count_clk
20930 * 0b0100..1/16 count_clk
20931 * 0b0101..1/32 count_clk
20932 * 0b0110..1/64 count_clk
20933 * 0b0111..1/128 count_clk
20934 * 0b1000..1/256 count_clk
20935 * 0b1001..1/512 count_clk
20936 * 0b1010..1/1024 count_clk
20937 * 0b1011..1/2056 count_clk
20938 * 0b1100..1/4096 count_clk
20939 * 0b1101..1/8192 count_clk
20940 * 0b1110..1/16384 count_clk
20941 * 0b1111..1/32768 count_clk
20942 */
20943#define GPC_PGC_PU6_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU6_AUXSW_PDN_CLK_DIV_SEL_MASK)
20944/*! @} */
20945
20946/*! @name PU7_CTRL - GPC PGC Control Register */
20947/*! @{ */
20948#define GPC_PGC_PU7_CTRL_PCR_MASK (0x1U)
20949#define GPC_PGC_PU7_CTRL_PCR_SHIFT (0U)
20950/*! PCR
20951 * 0b0..Do not switch off power even if pdn_req is asserted.
20952 * 0b1..Switch off power when pdn_req is asserted.
20953 */
20954#define GPC_PGC_PU7_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_CTRL_PCR_SHIFT)) & GPC_PGC_PU7_CTRL_PCR_MASK)
20955#define GPC_PGC_PU7_CTRL_L2RSTDIS_MASK (0x7EU)
20956#define GPC_PGC_PU7_CTRL_L2RSTDIS_SHIFT (1U)
20957#define GPC_PGC_PU7_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU7_CTRL_L2RSTDIS_MASK)
20958#define GPC_PGC_PU7_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
20959#define GPC_PGC_PU7_CTRL_DFTRAM_TCD1_SHIFT (8U)
20960#define GPC_PGC_PU7_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU7_CTRL_DFTRAM_TCD1_MASK)
20961#define GPC_PGC_PU7_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
20962#define GPC_PGC_PU7_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
20963#define GPC_PGC_PU7_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU7_CTRL_L2RETN_TCD1_TDR_MASK)
20964#define GPC_PGC_PU7_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
20965#define GPC_PGC_PU7_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
20966#define GPC_PGC_PU7_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU7_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
20967/*! @} */
20968
20969/*! @name PU7_PUPSCR - GPC PGC Up Sequence Control Register */
20970/*! @{ */
20971#define GPC_PGC_PU7_PUPSCR_SW_MASK (0x3FU)
20972#define GPC_PGC_PU7_PUPSCR_SW_SHIFT (0U)
20973#define GPC_PGC_PU7_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PUPSCR_SW_SHIFT)) & GPC_PGC_PU7_PUPSCR_SW_MASK)
20974#define GPC_PGC_PU7_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
20975#define GPC_PGC_PU7_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
20976#define GPC_PGC_PU7_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU7_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
20977#define GPC_PGC_PU7_PUPSCR_SW2ISO_MASK (0x7FFF80U)
20978#define GPC_PGC_PU7_PUPSCR_SW2ISO_SHIFT (7U)
20979#define GPC_PGC_PU7_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU7_PUPSCR_SW2ISO_MASK)
20980#define GPC_PGC_PU7_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
20981#define GPC_PGC_PU7_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
20982#define GPC_PGC_PU7_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU7_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
20983/*! @} */
20984
20985/*! @name PU7_PDNSCR - GPC PGC Down Sequence Control Register */
20986/*! @{ */
20987#define GPC_PGC_PU7_PDNSCR_ISO_MASK (0x3FU)
20988#define GPC_PGC_PU7_PDNSCR_ISO_SHIFT (0U)
20989#define GPC_PGC_PU7_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU7_PDNSCR_ISO_MASK)
20990#define GPC_PGC_PU7_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
20991#define GPC_PGC_PU7_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
20992#define GPC_PGC_PU7_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU7_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
20993#define GPC_PGC_PU7_PDNSCR_ISO2SW_MASK (0x3F00U)
20994#define GPC_PGC_PU7_PDNSCR_ISO2SW_SHIFT (8U)
20995#define GPC_PGC_PU7_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU7_PDNSCR_ISO2SW_MASK)
20996#define GPC_PGC_PU7_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
20997#define GPC_PGC_PU7_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
20998#define GPC_PGC_PU7_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU7_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
20999#define GPC_PGC_PU7_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
21000#define GPC_PGC_PU7_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
21001#define GPC_PGC_PU7_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU7_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
21002/*! @} */
21003
21004/*! @name PU7_SR - GPC PGC Status Register */
21005/*! @{ */
21006#define GPC_PGC_PU7_SR_PSR_MASK (0x1U)
21007#define GPC_PGC_PU7_SR_PSR_SHIFT (0U)
21008/*! PSR
21009 * 0b0..The target subsystem was not powered down for the previous power-down request.
21010 * 0b1..The target subsystem was powered down for the previous power-down request.
21011 */
21012#define GPC_PGC_PU7_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_SR_PSR_SHIFT)) & GPC_PGC_PU7_SR_PSR_MASK)
21013#define GPC_PGC_PU7_SR_L2RETN_FLAG_MASK (0x2U)
21014#define GPC_PGC_PU7_SR_L2RETN_FLAG_SHIFT (1U)
21015/*! L2RETN_FLAG
21016 * 0b0..A53 is not wakeup from L2 retention mode.
21017 * 0b1..A53 is wakeup from L2 retention mode.
21018 */
21019#define GPC_PGC_PU7_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU7_SR_L2RETN_FLAG_MASK)
21020#define GPC_PGC_PU7_SR_ALLOFF_FLAG_MASK (0x4U)
21021#define GPC_PGC_PU7_SR_ALLOFF_FLAG_SHIFT (2U)
21022/*! ALLOFF_FLAG
21023 * 0b0..A53 is not wakeup from ALL_OFF mode.
21024 * 0b1..A53 is wakeup from ALL_OFF mode.
21025 */
21026#define GPC_PGC_PU7_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU7_SR_ALLOFF_FLAG_MASK)
21027#define GPC_PGC_PU7_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
21028#define GPC_PGC_PU7_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
21029/*! PUP_CLK_DIV_SEL
21030 * 0b0000..1
21031 * 0b0001..1/2 count_clk
21032 * 0b0010..1/4 count_clk
21033 * 0b0011..1/8 count_clk
21034 * 0b0100..1/16 count_clk
21035 * 0b0101..1/32 count_clk
21036 * 0b0110..1/64 count_clk
21037 * 0b0111..1/128 count_clk
21038 * 0b1000..1/256 count_clk
21039 * 0b1001..1/512 count_clk
21040 * 0b1010..1/1024 count_clk
21041 * 0b1011..1/2056 count_clk
21042 * 0b1100..1/4096 count_clk
21043 * 0b1101..1/8192 count_clk
21044 * 0b1110..1/16384 count_clk
21045 * 0b1111..1/32768 count_clk
21046 */
21047#define GPC_PGC_PU7_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU7_SR_PUP_CLK_DIV_SEL_MASK)
21048#define GPC_PGC_PU7_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
21049#define GPC_PGC_PU7_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
21050#define GPC_PGC_PU7_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU7_SR_L2RSTDIS_DEASSERT_CNT_MASK)
21051/*! @} */
21052
21053/*! @name PU7_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
21054/*! @{ */
21055#define GPC_PGC_PU7_AUXSW_SW2_MASK (0x3FU)
21056#define GPC_PGC_PU7_AUXSW_SW2_SHIFT (0U)
21057#define GPC_PGC_PU7_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_AUXSW_SW2_SHIFT)) & GPC_PGC_PU7_AUXSW_SW2_MASK)
21058#define GPC_PGC_PU7_AUXSW_ISO2SW2_MASK (0x3F00U)
21059#define GPC_PGC_PU7_AUXSW_ISO2SW2_SHIFT (8U)
21060/*! ISO2SW2
21061 * 0b000000..A53 is not wakeup from ALL_OFF mode.
21062 * 0b000001..A53 is wakeup from ALL_OFF mode.
21063 */
21064#define GPC_PGC_PU7_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU7_AUXSW_ISO2SW2_MASK)
21065#define GPC_PGC_PU7_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
21066#define GPC_PGC_PU7_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
21067/*! PDN_CLK_DIV_SEL
21068 * 0b0000..1
21069 * 0b0001..1/2 count_clk
21070 * 0b0010..1/4 count_clk
21071 * 0b0011..1/8 count_clk
21072 * 0b0100..1/16 count_clk
21073 * 0b0101..1/32 count_clk
21074 * 0b0110..1/64 count_clk
21075 * 0b0111..1/128 count_clk
21076 * 0b1000..1/256 count_clk
21077 * 0b1001..1/512 count_clk
21078 * 0b1010..1/1024 count_clk
21079 * 0b1011..1/2056 count_clk
21080 * 0b1100..1/4096 count_clk
21081 * 0b1101..1/8192 count_clk
21082 * 0b1110..1/16384 count_clk
21083 * 0b1111..1/32768 count_clk
21084 */
21085#define GPC_PGC_PU7_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU7_AUXSW_PDN_CLK_DIV_SEL_MASK)
21086/*! @} */
21087
21088/*! @name PU8_CTRL - GPC PGC Control Register */
21089/*! @{ */
21090#define GPC_PGC_PU8_CTRL_PCR_MASK (0x1U)
21091#define GPC_PGC_PU8_CTRL_PCR_SHIFT (0U)
21092/*! PCR
21093 * 0b0..Do not switch off power even if pdn_req is asserted.
21094 * 0b1..Switch off power when pdn_req is asserted.
21095 */
21096#define GPC_PGC_PU8_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_CTRL_PCR_SHIFT)) & GPC_PGC_PU8_CTRL_PCR_MASK)
21097#define GPC_PGC_PU8_CTRL_L2RSTDIS_MASK (0x7EU)
21098#define GPC_PGC_PU8_CTRL_L2RSTDIS_SHIFT (1U)
21099#define GPC_PGC_PU8_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU8_CTRL_L2RSTDIS_MASK)
21100#define GPC_PGC_PU8_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
21101#define GPC_PGC_PU8_CTRL_DFTRAM_TCD1_SHIFT (8U)
21102#define GPC_PGC_PU8_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU8_CTRL_DFTRAM_TCD1_MASK)
21103#define GPC_PGC_PU8_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
21104#define GPC_PGC_PU8_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
21105#define GPC_PGC_PU8_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU8_CTRL_L2RETN_TCD1_TDR_MASK)
21106#define GPC_PGC_PU8_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
21107#define GPC_PGC_PU8_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
21108#define GPC_PGC_PU8_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU8_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
21109/*! @} */
21110
21111/*! @name PU8_PUPSCR - GPC PGC Up Sequence Control Register */
21112/*! @{ */
21113#define GPC_PGC_PU8_PUPSCR_SW_MASK (0x3FU)
21114#define GPC_PGC_PU8_PUPSCR_SW_SHIFT (0U)
21115#define GPC_PGC_PU8_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PUPSCR_SW_SHIFT)) & GPC_PGC_PU8_PUPSCR_SW_MASK)
21116#define GPC_PGC_PU8_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
21117#define GPC_PGC_PU8_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
21118#define GPC_PGC_PU8_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU8_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
21119#define GPC_PGC_PU8_PUPSCR_SW2ISO_MASK (0x7FFF80U)
21120#define GPC_PGC_PU8_PUPSCR_SW2ISO_SHIFT (7U)
21121#define GPC_PGC_PU8_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU8_PUPSCR_SW2ISO_MASK)
21122#define GPC_PGC_PU8_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
21123#define GPC_PGC_PU8_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
21124#define GPC_PGC_PU8_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU8_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
21125/*! @} */
21126
21127/*! @name PU8_PDNSCR - GPC PGC Down Sequence Control Register */
21128/*! @{ */
21129#define GPC_PGC_PU8_PDNSCR_ISO_MASK (0x3FU)
21130#define GPC_PGC_PU8_PDNSCR_ISO_SHIFT (0U)
21131#define GPC_PGC_PU8_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU8_PDNSCR_ISO_MASK)
21132#define GPC_PGC_PU8_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
21133#define GPC_PGC_PU8_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
21134#define GPC_PGC_PU8_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU8_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
21135#define GPC_PGC_PU8_PDNSCR_ISO2SW_MASK (0x3F00U)
21136#define GPC_PGC_PU8_PDNSCR_ISO2SW_SHIFT (8U)
21137#define GPC_PGC_PU8_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU8_PDNSCR_ISO2SW_MASK)
21138#define GPC_PGC_PU8_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
21139#define GPC_PGC_PU8_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
21140#define GPC_PGC_PU8_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU8_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
21141#define GPC_PGC_PU8_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
21142#define GPC_PGC_PU8_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
21143#define GPC_PGC_PU8_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU8_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
21144/*! @} */
21145
21146/*! @name PU8_SR - GPC PGC Status Register */
21147/*! @{ */
21148#define GPC_PGC_PU8_SR_PSR_MASK (0x1U)
21149#define GPC_PGC_PU8_SR_PSR_SHIFT (0U)
21150/*! PSR
21151 * 0b0..The target subsystem was not powered down for the previous power-down request.
21152 * 0b1..The target subsystem was powered down for the previous power-down request.
21153 */
21154#define GPC_PGC_PU8_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_SR_PSR_SHIFT)) & GPC_PGC_PU8_SR_PSR_MASK)
21155#define GPC_PGC_PU8_SR_L2RETN_FLAG_MASK (0x2U)
21156#define GPC_PGC_PU8_SR_L2RETN_FLAG_SHIFT (1U)
21157/*! L2RETN_FLAG
21158 * 0b0..A53 is not wakeup from L2 retention mode.
21159 * 0b1..A53 is wakeup from L2 retention mode.
21160 */
21161#define GPC_PGC_PU8_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU8_SR_L2RETN_FLAG_MASK)
21162#define GPC_PGC_PU8_SR_ALLOFF_FLAG_MASK (0x4U)
21163#define GPC_PGC_PU8_SR_ALLOFF_FLAG_SHIFT (2U)
21164/*! ALLOFF_FLAG
21165 * 0b0..A53 is not wakeup from ALL_OFF mode.
21166 * 0b1..A53 is wakeup from ALL_OFF mode.
21167 */
21168#define GPC_PGC_PU8_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU8_SR_ALLOFF_FLAG_MASK)
21169#define GPC_PGC_PU8_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
21170#define GPC_PGC_PU8_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
21171/*! PUP_CLK_DIV_SEL
21172 * 0b0000..1
21173 * 0b0001..1/2 count_clk
21174 * 0b0010..1/4 count_clk
21175 * 0b0011..1/8 count_clk
21176 * 0b0100..1/16 count_clk
21177 * 0b0101..1/32 count_clk
21178 * 0b0110..1/64 count_clk
21179 * 0b0111..1/128 count_clk
21180 * 0b1000..1/256 count_clk
21181 * 0b1001..1/512 count_clk
21182 * 0b1010..1/1024 count_clk
21183 * 0b1011..1/2056 count_clk
21184 * 0b1100..1/4096 count_clk
21185 * 0b1101..1/8192 count_clk
21186 * 0b1110..1/16384 count_clk
21187 * 0b1111..1/32768 count_clk
21188 */
21189#define GPC_PGC_PU8_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU8_SR_PUP_CLK_DIV_SEL_MASK)
21190#define GPC_PGC_PU8_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
21191#define GPC_PGC_PU8_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
21192#define GPC_PGC_PU8_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU8_SR_L2RSTDIS_DEASSERT_CNT_MASK)
21193/*! @} */
21194
21195/*! @name PU8_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
21196/*! @{ */
21197#define GPC_PGC_PU8_AUXSW_SW2_MASK (0x3FU)
21198#define GPC_PGC_PU8_AUXSW_SW2_SHIFT (0U)
21199#define GPC_PGC_PU8_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_AUXSW_SW2_SHIFT)) & GPC_PGC_PU8_AUXSW_SW2_MASK)
21200#define GPC_PGC_PU8_AUXSW_ISO2SW2_MASK (0x3F00U)
21201#define GPC_PGC_PU8_AUXSW_ISO2SW2_SHIFT (8U)
21202/*! ISO2SW2
21203 * 0b000000..A53 is not wakeup from ALL_OFF mode.
21204 * 0b000001..A53 is wakeup from ALL_OFF mode.
21205 */
21206#define GPC_PGC_PU8_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU8_AUXSW_ISO2SW2_MASK)
21207#define GPC_PGC_PU8_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
21208#define GPC_PGC_PU8_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
21209/*! PDN_CLK_DIV_SEL
21210 * 0b0000..1
21211 * 0b0001..1/2 count_clk
21212 * 0b0010..1/4 count_clk
21213 * 0b0011..1/8 count_clk
21214 * 0b0100..1/16 count_clk
21215 * 0b0101..1/32 count_clk
21216 * 0b0110..1/64 count_clk
21217 * 0b0111..1/128 count_clk
21218 * 0b1000..1/256 count_clk
21219 * 0b1001..1/512 count_clk
21220 * 0b1010..1/1024 count_clk
21221 * 0b1011..1/2056 count_clk
21222 * 0b1100..1/4096 count_clk
21223 * 0b1101..1/8192 count_clk
21224 * 0b1110..1/16384 count_clk
21225 * 0b1111..1/32768 count_clk
21226 */
21227#define GPC_PGC_PU8_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU8_AUXSW_PDN_CLK_DIV_SEL_MASK)
21228/*! @} */
21229
21230/*! @name PU9_CTRL - GPC PGC Control Register */
21231/*! @{ */
21232#define GPC_PGC_PU9_CTRL_PCR_MASK (0x1U)
21233#define GPC_PGC_PU9_CTRL_PCR_SHIFT (0U)
21234/*! PCR
21235 * 0b0..Do not switch off power even if pdn_req is asserted.
21236 * 0b1..Switch off power when pdn_req is asserted.
21237 */
21238#define GPC_PGC_PU9_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_CTRL_PCR_SHIFT)) & GPC_PGC_PU9_CTRL_PCR_MASK)
21239#define GPC_PGC_PU9_CTRL_L2RSTDIS_MASK (0x7EU)
21240#define GPC_PGC_PU9_CTRL_L2RSTDIS_SHIFT (1U)
21241#define GPC_PGC_PU9_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU9_CTRL_L2RSTDIS_MASK)
21242#define GPC_PGC_PU9_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
21243#define GPC_PGC_PU9_CTRL_DFTRAM_TCD1_SHIFT (8U)
21244#define GPC_PGC_PU9_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU9_CTRL_DFTRAM_TCD1_MASK)
21245#define GPC_PGC_PU9_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
21246#define GPC_PGC_PU9_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
21247#define GPC_PGC_PU9_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU9_CTRL_L2RETN_TCD1_TDR_MASK)
21248#define GPC_PGC_PU9_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
21249#define GPC_PGC_PU9_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
21250#define GPC_PGC_PU9_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU9_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
21251/*! @} */
21252
21253/*! @name PU9_PUPSCR - GPC PGC Up Sequence Control Register */
21254/*! @{ */
21255#define GPC_PGC_PU9_PUPSCR_SW_MASK (0x3FU)
21256#define GPC_PGC_PU9_PUPSCR_SW_SHIFT (0U)
21257#define GPC_PGC_PU9_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PUPSCR_SW_SHIFT)) & GPC_PGC_PU9_PUPSCR_SW_MASK)
21258#define GPC_PGC_PU9_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
21259#define GPC_PGC_PU9_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
21260#define GPC_PGC_PU9_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU9_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
21261#define GPC_PGC_PU9_PUPSCR_SW2ISO_MASK (0x7FFF80U)
21262#define GPC_PGC_PU9_PUPSCR_SW2ISO_SHIFT (7U)
21263#define GPC_PGC_PU9_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU9_PUPSCR_SW2ISO_MASK)
21264#define GPC_PGC_PU9_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
21265#define GPC_PGC_PU9_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
21266#define GPC_PGC_PU9_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU9_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
21267/*! @} */
21268
21269/*! @name PU9_PDNSCR - GPC PGC Down Sequence Control Register */
21270/*! @{ */
21271#define GPC_PGC_PU9_PDNSCR_ISO_MASK (0x3FU)
21272#define GPC_PGC_PU9_PDNSCR_ISO_SHIFT (0U)
21273#define GPC_PGC_PU9_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU9_PDNSCR_ISO_MASK)
21274#define GPC_PGC_PU9_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
21275#define GPC_PGC_PU9_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
21276#define GPC_PGC_PU9_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU9_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
21277#define GPC_PGC_PU9_PDNSCR_ISO2SW_MASK (0x3F00U)
21278#define GPC_PGC_PU9_PDNSCR_ISO2SW_SHIFT (8U)
21279#define GPC_PGC_PU9_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU9_PDNSCR_ISO2SW_MASK)
21280#define GPC_PGC_PU9_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
21281#define GPC_PGC_PU9_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
21282#define GPC_PGC_PU9_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU9_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
21283#define GPC_PGC_PU9_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
21284#define GPC_PGC_PU9_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
21285#define GPC_PGC_PU9_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU9_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
21286/*! @} */
21287
21288/*! @name PU9_SR - GPC PGC Status Register */
21289/*! @{ */
21290#define GPC_PGC_PU9_SR_PSR_MASK (0x1U)
21291#define GPC_PGC_PU9_SR_PSR_SHIFT (0U)
21292/*! PSR
21293 * 0b0..The target subsystem was not powered down for the previous power-down request.
21294 * 0b1..The target subsystem was powered down for the previous power-down request.
21295 */
21296#define GPC_PGC_PU9_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_SR_PSR_SHIFT)) & GPC_PGC_PU9_SR_PSR_MASK)
21297#define GPC_PGC_PU9_SR_L2RETN_FLAG_MASK (0x2U)
21298#define GPC_PGC_PU9_SR_L2RETN_FLAG_SHIFT (1U)
21299/*! L2RETN_FLAG
21300 * 0b0..A53 is not wakeup from L2 retention mode.
21301 * 0b1..A53 is wakeup from L2 retention mode.
21302 */
21303#define GPC_PGC_PU9_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU9_SR_L2RETN_FLAG_MASK)
21304#define GPC_PGC_PU9_SR_ALLOFF_FLAG_MASK (0x4U)
21305#define GPC_PGC_PU9_SR_ALLOFF_FLAG_SHIFT (2U)
21306/*! ALLOFF_FLAG
21307 * 0b0..A53 is not wakeup from ALL_OFF mode.
21308 * 0b1..A53 is wakeup from ALL_OFF mode.
21309 */
21310#define GPC_PGC_PU9_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU9_SR_ALLOFF_FLAG_MASK)
21311#define GPC_PGC_PU9_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
21312#define GPC_PGC_PU9_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
21313/*! PUP_CLK_DIV_SEL
21314 * 0b0000..1
21315 * 0b0001..1/2 count_clk
21316 * 0b0010..1/4 count_clk
21317 * 0b0011..1/8 count_clk
21318 * 0b0100..1/16 count_clk
21319 * 0b0101..1/32 count_clk
21320 * 0b0110..1/64 count_clk
21321 * 0b0111..1/128 count_clk
21322 * 0b1000..1/256 count_clk
21323 * 0b1001..1/512 count_clk
21324 * 0b1010..1/1024 count_clk
21325 * 0b1011..1/2056 count_clk
21326 * 0b1100..1/4096 count_clk
21327 * 0b1101..1/8192 count_clk
21328 * 0b1110..1/16384 count_clk
21329 * 0b1111..1/32768 count_clk
21330 */
21331#define GPC_PGC_PU9_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU9_SR_PUP_CLK_DIV_SEL_MASK)
21332#define GPC_PGC_PU9_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
21333#define GPC_PGC_PU9_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
21334#define GPC_PGC_PU9_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU9_SR_L2RSTDIS_DEASSERT_CNT_MASK)
21335/*! @} */
21336
21337/*! @name PU9_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
21338/*! @{ */
21339#define GPC_PGC_PU9_AUXSW_SW2_MASK (0x3FU)
21340#define GPC_PGC_PU9_AUXSW_SW2_SHIFT (0U)
21341#define GPC_PGC_PU9_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_AUXSW_SW2_SHIFT)) & GPC_PGC_PU9_AUXSW_SW2_MASK)
21342#define GPC_PGC_PU9_AUXSW_ISO2SW2_MASK (0x3F00U)
21343#define GPC_PGC_PU9_AUXSW_ISO2SW2_SHIFT (8U)
21344/*! ISO2SW2
21345 * 0b000000..A53 is not wakeup from ALL_OFF mode.
21346 * 0b000001..A53 is wakeup from ALL_OFF mode.
21347 */
21348#define GPC_PGC_PU9_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU9_AUXSW_ISO2SW2_MASK)
21349#define GPC_PGC_PU9_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
21350#define GPC_PGC_PU9_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
21351/*! PDN_CLK_DIV_SEL
21352 * 0b0000..1
21353 * 0b0001..1/2 count_clk
21354 * 0b0010..1/4 count_clk
21355 * 0b0011..1/8 count_clk
21356 * 0b0100..1/16 count_clk
21357 * 0b0101..1/32 count_clk
21358 * 0b0110..1/64 count_clk
21359 * 0b0111..1/128 count_clk
21360 * 0b1000..1/256 count_clk
21361 * 0b1001..1/512 count_clk
21362 * 0b1010..1/1024 count_clk
21363 * 0b1011..1/2056 count_clk
21364 * 0b1100..1/4096 count_clk
21365 * 0b1101..1/8192 count_clk
21366 * 0b1110..1/16384 count_clk
21367 * 0b1111..1/32768 count_clk
21368 */
21369#define GPC_PGC_PU9_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU9_AUXSW_PDN_CLK_DIV_SEL_MASK)
21370/*! @} */
21371
21372/*! @name PU10_CTRL - GPC PGC Control Register */
21373/*! @{ */
21374#define GPC_PGC_PU10_CTRL_PCR_MASK (0x1U)
21375#define GPC_PGC_PU10_CTRL_PCR_SHIFT (0U)
21376/*! PCR
21377 * 0b0..Do not switch off power even if pdn_req is asserted.
21378 * 0b1..Switch off power when pdn_req is asserted.
21379 */
21380#define GPC_PGC_PU10_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_CTRL_PCR_SHIFT)) & GPC_PGC_PU10_CTRL_PCR_MASK)
21381#define GPC_PGC_PU10_CTRL_L2RSTDIS_MASK (0x7EU)
21382#define GPC_PGC_PU10_CTRL_L2RSTDIS_SHIFT (1U)
21383#define GPC_PGC_PU10_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU10_CTRL_L2RSTDIS_MASK)
21384#define GPC_PGC_PU10_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
21385#define GPC_PGC_PU10_CTRL_DFTRAM_TCD1_SHIFT (8U)
21386#define GPC_PGC_PU10_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU10_CTRL_DFTRAM_TCD1_MASK)
21387#define GPC_PGC_PU10_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
21388#define GPC_PGC_PU10_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
21389#define GPC_PGC_PU10_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU10_CTRL_L2RETN_TCD1_TDR_MASK)
21390#define GPC_PGC_PU10_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
21391#define GPC_PGC_PU10_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
21392#define GPC_PGC_PU10_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU10_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
21393/*! @} */
21394
21395/*! @name PU10_PUPSCR - GPC PGC Up Sequence Control Register */
21396/*! @{ */
21397#define GPC_PGC_PU10_PUPSCR_SW_MASK (0x3FU)
21398#define GPC_PGC_PU10_PUPSCR_SW_SHIFT (0U)
21399#define GPC_PGC_PU10_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PUPSCR_SW_SHIFT)) & GPC_PGC_PU10_PUPSCR_SW_MASK)
21400#define GPC_PGC_PU10_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
21401#define GPC_PGC_PU10_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
21402#define GPC_PGC_PU10_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU10_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
21403#define GPC_PGC_PU10_PUPSCR_SW2ISO_MASK (0x7FFF80U)
21404#define GPC_PGC_PU10_PUPSCR_SW2ISO_SHIFT (7U)
21405#define GPC_PGC_PU10_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU10_PUPSCR_SW2ISO_MASK)
21406#define GPC_PGC_PU10_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
21407#define GPC_PGC_PU10_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
21408#define GPC_PGC_PU10_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU10_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
21409/*! @} */
21410
21411/*! @name PU10_PDNSCR - GPC PGC Down Sequence Control Register */
21412/*! @{ */
21413#define GPC_PGC_PU10_PDNSCR_ISO_MASK (0x3FU)
21414#define GPC_PGC_PU10_PDNSCR_ISO_SHIFT (0U)
21415#define GPC_PGC_PU10_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU10_PDNSCR_ISO_MASK)
21416#define GPC_PGC_PU10_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
21417#define GPC_PGC_PU10_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
21418#define GPC_PGC_PU10_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU10_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
21419#define GPC_PGC_PU10_PDNSCR_ISO2SW_MASK (0x3F00U)
21420#define GPC_PGC_PU10_PDNSCR_ISO2SW_SHIFT (8U)
21421#define GPC_PGC_PU10_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU10_PDNSCR_ISO2SW_MASK)
21422#define GPC_PGC_PU10_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
21423#define GPC_PGC_PU10_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
21424#define GPC_PGC_PU10_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU10_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
21425#define GPC_PGC_PU10_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
21426#define GPC_PGC_PU10_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
21427#define GPC_PGC_PU10_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU10_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
21428/*! @} */
21429
21430/*! @name PU10_SR - GPC PGC Status Register */
21431/*! @{ */
21432#define GPC_PGC_PU10_SR_PSR_MASK (0x1U)
21433#define GPC_PGC_PU10_SR_PSR_SHIFT (0U)
21434/*! PSR
21435 * 0b0..The target subsystem was not powered down for the previous power-down request.
21436 * 0b1..The target subsystem was powered down for the previous power-down request.
21437 */
21438#define GPC_PGC_PU10_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_SR_PSR_SHIFT)) & GPC_PGC_PU10_SR_PSR_MASK)
21439#define GPC_PGC_PU10_SR_L2RETN_FLAG_MASK (0x2U)
21440#define GPC_PGC_PU10_SR_L2RETN_FLAG_SHIFT (1U)
21441/*! L2RETN_FLAG
21442 * 0b0..A53 is not wakeup from L2 retention mode.
21443 * 0b1..A53 is wakeup from L2 retention mode.
21444 */
21445#define GPC_PGC_PU10_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU10_SR_L2RETN_FLAG_MASK)
21446#define GPC_PGC_PU10_SR_ALLOFF_FLAG_MASK (0x4U)
21447#define GPC_PGC_PU10_SR_ALLOFF_FLAG_SHIFT (2U)
21448/*! ALLOFF_FLAG
21449 * 0b0..A53 is not wakeup from ALL_OFF mode.
21450 * 0b1..A53 is wakeup from ALL_OFF mode.
21451 */
21452#define GPC_PGC_PU10_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU10_SR_ALLOFF_FLAG_MASK)
21453#define GPC_PGC_PU10_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
21454#define GPC_PGC_PU10_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
21455/*! PUP_CLK_DIV_SEL
21456 * 0b0000..1
21457 * 0b0001..1/2 count_clk
21458 * 0b0010..1/4 count_clk
21459 * 0b0011..1/8 count_clk
21460 * 0b0100..1/16 count_clk
21461 * 0b0101..1/32 count_clk
21462 * 0b0110..1/64 count_clk
21463 * 0b0111..1/128 count_clk
21464 * 0b1000..1/256 count_clk
21465 * 0b1001..1/512 count_clk
21466 * 0b1010..1/1024 count_clk
21467 * 0b1011..1/2056 count_clk
21468 * 0b1100..1/4096 count_clk
21469 * 0b1101..1/8192 count_clk
21470 * 0b1110..1/16384 count_clk
21471 * 0b1111..1/32768 count_clk
21472 */
21473#define GPC_PGC_PU10_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU10_SR_PUP_CLK_DIV_SEL_MASK)
21474#define GPC_PGC_PU10_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
21475#define GPC_PGC_PU10_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
21476#define GPC_PGC_PU10_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU10_SR_L2RSTDIS_DEASSERT_CNT_MASK)
21477/*! @} */
21478
21479/*! @name PU10_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
21480/*! @{ */
21481#define GPC_PGC_PU10_AUXSW_SW2_MASK (0x3FU)
21482#define GPC_PGC_PU10_AUXSW_SW2_SHIFT (0U)
21483#define GPC_PGC_PU10_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_AUXSW_SW2_SHIFT)) & GPC_PGC_PU10_AUXSW_SW2_MASK)
21484#define GPC_PGC_PU10_AUXSW_ISO2SW2_MASK (0x3F00U)
21485#define GPC_PGC_PU10_AUXSW_ISO2SW2_SHIFT (8U)
21486/*! ISO2SW2
21487 * 0b000000..A53 is not wakeup from ALL_OFF mode.
21488 * 0b000001..A53 is wakeup from ALL_OFF mode.
21489 */
21490#define GPC_PGC_PU10_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU10_AUXSW_ISO2SW2_MASK)
21491#define GPC_PGC_PU10_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
21492#define GPC_PGC_PU10_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
21493/*! PDN_CLK_DIV_SEL
21494 * 0b0000..1
21495 * 0b0001..1/2 count_clk
21496 * 0b0010..1/4 count_clk
21497 * 0b0011..1/8 count_clk
21498 * 0b0100..1/16 count_clk
21499 * 0b0101..1/32 count_clk
21500 * 0b0110..1/64 count_clk
21501 * 0b0111..1/128 count_clk
21502 * 0b1000..1/256 count_clk
21503 * 0b1001..1/512 count_clk
21504 * 0b1010..1/1024 count_clk
21505 * 0b1011..1/2056 count_clk
21506 * 0b1100..1/4096 count_clk
21507 * 0b1101..1/8192 count_clk
21508 * 0b1110..1/16384 count_clk
21509 * 0b1111..1/32768 count_clk
21510 */
21511#define GPC_PGC_PU10_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU10_AUXSW_PDN_CLK_DIV_SEL_MASK)
21512/*! @} */
21513
21514/*! @name PU11_CTRL - GPC PGC Control Register */
21515/*! @{ */
21516#define GPC_PGC_PU11_CTRL_PCR_MASK (0x1U)
21517#define GPC_PGC_PU11_CTRL_PCR_SHIFT (0U)
21518/*! PCR
21519 * 0b0..Do not switch off power even if pdn_req is asserted.
21520 * 0b1..Switch off power when pdn_req is asserted.
21521 */
21522#define GPC_PGC_PU11_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_CTRL_PCR_SHIFT)) & GPC_PGC_PU11_CTRL_PCR_MASK)
21523#define GPC_PGC_PU11_CTRL_L2RSTDIS_MASK (0x7EU)
21524#define GPC_PGC_PU11_CTRL_L2RSTDIS_SHIFT (1U)
21525#define GPC_PGC_PU11_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU11_CTRL_L2RSTDIS_MASK)
21526#define GPC_PGC_PU11_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
21527#define GPC_PGC_PU11_CTRL_DFTRAM_TCD1_SHIFT (8U)
21528#define GPC_PGC_PU11_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU11_CTRL_DFTRAM_TCD1_MASK)
21529#define GPC_PGC_PU11_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
21530#define GPC_PGC_PU11_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
21531#define GPC_PGC_PU11_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU11_CTRL_L2RETN_TCD1_TDR_MASK)
21532#define GPC_PGC_PU11_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
21533#define GPC_PGC_PU11_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
21534#define GPC_PGC_PU11_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU11_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
21535/*! @} */
21536
21537/*! @name PU11_PUPSCR - GPC PGC Up Sequence Control Register */
21538/*! @{ */
21539#define GPC_PGC_PU11_PUPSCR_SW_MASK (0x3FU)
21540#define GPC_PGC_PU11_PUPSCR_SW_SHIFT (0U)
21541#define GPC_PGC_PU11_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PUPSCR_SW_SHIFT)) & GPC_PGC_PU11_PUPSCR_SW_MASK)
21542#define GPC_PGC_PU11_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
21543#define GPC_PGC_PU11_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
21544#define GPC_PGC_PU11_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU11_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
21545#define GPC_PGC_PU11_PUPSCR_SW2ISO_MASK (0x7FFF80U)
21546#define GPC_PGC_PU11_PUPSCR_SW2ISO_SHIFT (7U)
21547#define GPC_PGC_PU11_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU11_PUPSCR_SW2ISO_MASK)
21548#define GPC_PGC_PU11_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
21549#define GPC_PGC_PU11_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
21550#define GPC_PGC_PU11_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU11_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
21551/*! @} */
21552
21553/*! @name PU11_PDNSCR - GPC PGC Down Sequence Control Register */
21554/*! @{ */
21555#define GPC_PGC_PU11_PDNSCR_ISO_MASK (0x3FU)
21556#define GPC_PGC_PU11_PDNSCR_ISO_SHIFT (0U)
21557#define GPC_PGC_PU11_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU11_PDNSCR_ISO_MASK)
21558#define GPC_PGC_PU11_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
21559#define GPC_PGC_PU11_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
21560#define GPC_PGC_PU11_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU11_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
21561#define GPC_PGC_PU11_PDNSCR_ISO2SW_MASK (0x3F00U)
21562#define GPC_PGC_PU11_PDNSCR_ISO2SW_SHIFT (8U)
21563#define GPC_PGC_PU11_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU11_PDNSCR_ISO2SW_MASK)
21564#define GPC_PGC_PU11_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
21565#define GPC_PGC_PU11_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
21566#define GPC_PGC_PU11_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU11_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
21567#define GPC_PGC_PU11_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
21568#define GPC_PGC_PU11_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
21569#define GPC_PGC_PU11_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU11_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
21570/*! @} */
21571
21572/*! @name PU11_SR - GPC PGC Status Register */
21573/*! @{ */
21574#define GPC_PGC_PU11_SR_PSR_MASK (0x1U)
21575#define GPC_PGC_PU11_SR_PSR_SHIFT (0U)
21576/*! PSR
21577 * 0b0..The target subsystem was not powered down for the previous power-down request.
21578 * 0b1..The target subsystem was powered down for the previous power-down request.
21579 */
21580#define GPC_PGC_PU11_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_SR_PSR_SHIFT)) & GPC_PGC_PU11_SR_PSR_MASK)
21581#define GPC_PGC_PU11_SR_L2RETN_FLAG_MASK (0x2U)
21582#define GPC_PGC_PU11_SR_L2RETN_FLAG_SHIFT (1U)
21583/*! L2RETN_FLAG
21584 * 0b0..A53 is not wakeup from L2 retention mode.
21585 * 0b1..A53 is wakeup from L2 retention mode.
21586 */
21587#define GPC_PGC_PU11_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU11_SR_L2RETN_FLAG_MASK)
21588#define GPC_PGC_PU11_SR_ALLOFF_FLAG_MASK (0x4U)
21589#define GPC_PGC_PU11_SR_ALLOFF_FLAG_SHIFT (2U)
21590/*! ALLOFF_FLAG
21591 * 0b0..A53 is not wakeup from ALL_OFF mode.
21592 * 0b1..A53 is wakeup from ALL_OFF mode.
21593 */
21594#define GPC_PGC_PU11_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU11_SR_ALLOFF_FLAG_MASK)
21595#define GPC_PGC_PU11_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
21596#define GPC_PGC_PU11_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
21597/*! PUP_CLK_DIV_SEL
21598 * 0b0000..1
21599 * 0b0001..1/2 count_clk
21600 * 0b0010..1/4 count_clk
21601 * 0b0011..1/8 count_clk
21602 * 0b0100..1/16 count_clk
21603 * 0b0101..1/32 count_clk
21604 * 0b0110..1/64 count_clk
21605 * 0b0111..1/128 count_clk
21606 * 0b1000..1/256 count_clk
21607 * 0b1001..1/512 count_clk
21608 * 0b1010..1/1024 count_clk
21609 * 0b1011..1/2056 count_clk
21610 * 0b1100..1/4096 count_clk
21611 * 0b1101..1/8192 count_clk
21612 * 0b1110..1/16384 count_clk
21613 * 0b1111..1/32768 count_clk
21614 */
21615#define GPC_PGC_PU11_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU11_SR_PUP_CLK_DIV_SEL_MASK)
21616#define GPC_PGC_PU11_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
21617#define GPC_PGC_PU11_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
21618#define GPC_PGC_PU11_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU11_SR_L2RSTDIS_DEASSERT_CNT_MASK)
21619/*! @} */
21620
21621/*! @name PU11_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
21622/*! @{ */
21623#define GPC_PGC_PU11_AUXSW_SW2_MASK (0x3FU)
21624#define GPC_PGC_PU11_AUXSW_SW2_SHIFT (0U)
21625#define GPC_PGC_PU11_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_AUXSW_SW2_SHIFT)) & GPC_PGC_PU11_AUXSW_SW2_MASK)
21626#define GPC_PGC_PU11_AUXSW_ISO2SW2_MASK (0x3F00U)
21627#define GPC_PGC_PU11_AUXSW_ISO2SW2_SHIFT (8U)
21628/*! ISO2SW2
21629 * 0b000000..A53 is not wakeup from ALL_OFF mode.
21630 * 0b000001..A53 is wakeup from ALL_OFF mode.
21631 */
21632#define GPC_PGC_PU11_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU11_AUXSW_ISO2SW2_MASK)
21633#define GPC_PGC_PU11_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
21634#define GPC_PGC_PU11_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
21635/*! PDN_CLK_DIV_SEL
21636 * 0b0000..1
21637 * 0b0001..1/2 count_clk
21638 * 0b0010..1/4 count_clk
21639 * 0b0011..1/8 count_clk
21640 * 0b0100..1/16 count_clk
21641 * 0b0101..1/32 count_clk
21642 * 0b0110..1/64 count_clk
21643 * 0b0111..1/128 count_clk
21644 * 0b1000..1/256 count_clk
21645 * 0b1001..1/512 count_clk
21646 * 0b1010..1/1024 count_clk
21647 * 0b1011..1/2056 count_clk
21648 * 0b1100..1/4096 count_clk
21649 * 0b1101..1/8192 count_clk
21650 * 0b1110..1/16384 count_clk
21651 * 0b1111..1/32768 count_clk
21652 */
21653#define GPC_PGC_PU11_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU11_AUXSW_PDN_CLK_DIV_SEL_MASK)
21654/*! @} */
21655
21656/*! @name PU12_CTRL - GPC PGC Control Register */
21657/*! @{ */
21658#define GPC_PGC_PU12_CTRL_PCR_MASK (0x1U)
21659#define GPC_PGC_PU12_CTRL_PCR_SHIFT (0U)
21660/*! PCR
21661 * 0b0..Do not switch off power even if pdn_req is asserted.
21662 * 0b1..Switch off power when pdn_req is asserted.
21663 */
21664#define GPC_PGC_PU12_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_CTRL_PCR_SHIFT)) & GPC_PGC_PU12_CTRL_PCR_MASK)
21665#define GPC_PGC_PU12_CTRL_L2RSTDIS_MASK (0x7EU)
21666#define GPC_PGC_PU12_CTRL_L2RSTDIS_SHIFT (1U)
21667#define GPC_PGC_PU12_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU12_CTRL_L2RSTDIS_MASK)
21668#define GPC_PGC_PU12_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
21669#define GPC_PGC_PU12_CTRL_DFTRAM_TCD1_SHIFT (8U)
21670#define GPC_PGC_PU12_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU12_CTRL_DFTRAM_TCD1_MASK)
21671#define GPC_PGC_PU12_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
21672#define GPC_PGC_PU12_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
21673#define GPC_PGC_PU12_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU12_CTRL_L2RETN_TCD1_TDR_MASK)
21674#define GPC_PGC_PU12_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
21675#define GPC_PGC_PU12_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
21676#define GPC_PGC_PU12_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU12_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
21677/*! @} */
21678
21679/*! @name PU12_PUPSCR - GPC PGC Up Sequence Control Register */
21680/*! @{ */
21681#define GPC_PGC_PU12_PUPSCR_SW_MASK (0x3FU)
21682#define GPC_PGC_PU12_PUPSCR_SW_SHIFT (0U)
21683#define GPC_PGC_PU12_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PUPSCR_SW_SHIFT)) & GPC_PGC_PU12_PUPSCR_SW_MASK)
21684#define GPC_PGC_PU12_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
21685#define GPC_PGC_PU12_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
21686#define GPC_PGC_PU12_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU12_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
21687#define GPC_PGC_PU12_PUPSCR_SW2ISO_MASK (0x7FFF80U)
21688#define GPC_PGC_PU12_PUPSCR_SW2ISO_SHIFT (7U)
21689#define GPC_PGC_PU12_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU12_PUPSCR_SW2ISO_MASK)
21690#define GPC_PGC_PU12_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
21691#define GPC_PGC_PU12_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
21692#define GPC_PGC_PU12_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU12_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
21693/*! @} */
21694
21695/*! @name PU12_PDNSCR - GPC PGC Down Sequence Control Register */
21696/*! @{ */
21697#define GPC_PGC_PU12_PDNSCR_ISO_MASK (0x3FU)
21698#define GPC_PGC_PU12_PDNSCR_ISO_SHIFT (0U)
21699#define GPC_PGC_PU12_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU12_PDNSCR_ISO_MASK)
21700#define GPC_PGC_PU12_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
21701#define GPC_PGC_PU12_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
21702#define GPC_PGC_PU12_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU12_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
21703#define GPC_PGC_PU12_PDNSCR_ISO2SW_MASK (0x3F00U)
21704#define GPC_PGC_PU12_PDNSCR_ISO2SW_SHIFT (8U)
21705#define GPC_PGC_PU12_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU12_PDNSCR_ISO2SW_MASK)
21706#define GPC_PGC_PU12_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
21707#define GPC_PGC_PU12_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
21708#define GPC_PGC_PU12_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU12_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
21709#define GPC_PGC_PU12_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
21710#define GPC_PGC_PU12_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
21711#define GPC_PGC_PU12_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU12_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
21712/*! @} */
21713
21714/*! @name PU12_SR - GPC PGC Status Register */
21715/*! @{ */
21716#define GPC_PGC_PU12_SR_PSR_MASK (0x1U)
21717#define GPC_PGC_PU12_SR_PSR_SHIFT (0U)
21718/*! PSR
21719 * 0b0..The target subsystem was not powered down for the previous power-down request.
21720 * 0b1..The target subsystem was powered down for the previous power-down request.
21721 */
21722#define GPC_PGC_PU12_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_SR_PSR_SHIFT)) & GPC_PGC_PU12_SR_PSR_MASK)
21723#define GPC_PGC_PU12_SR_L2RETN_FLAG_MASK (0x2U)
21724#define GPC_PGC_PU12_SR_L2RETN_FLAG_SHIFT (1U)
21725/*! L2RETN_FLAG
21726 * 0b0..A53 is not wakeup from L2 retention mode.
21727 * 0b1..A53 is wakeup from L2 retention mode.
21728 */
21729#define GPC_PGC_PU12_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU12_SR_L2RETN_FLAG_MASK)
21730#define GPC_PGC_PU12_SR_ALLOFF_FLAG_MASK (0x4U)
21731#define GPC_PGC_PU12_SR_ALLOFF_FLAG_SHIFT (2U)
21732/*! ALLOFF_FLAG
21733 * 0b0..A53 is not wakeup from ALL_OFF mode.
21734 * 0b1..A53 is wakeup from ALL_OFF mode.
21735 */
21736#define GPC_PGC_PU12_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU12_SR_ALLOFF_FLAG_MASK)
21737#define GPC_PGC_PU12_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
21738#define GPC_PGC_PU12_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
21739/*! PUP_CLK_DIV_SEL
21740 * 0b0000..1
21741 * 0b0001..1/2 count_clk
21742 * 0b0010..1/4 count_clk
21743 * 0b0011..1/8 count_clk
21744 * 0b0100..1/16 count_clk
21745 * 0b0101..1/32 count_clk
21746 * 0b0110..1/64 count_clk
21747 * 0b0111..1/128 count_clk
21748 * 0b1000..1/256 count_clk
21749 * 0b1001..1/512 count_clk
21750 * 0b1010..1/1024 count_clk
21751 * 0b1011..1/2056 count_clk
21752 * 0b1100..1/4096 count_clk
21753 * 0b1101..1/8192 count_clk
21754 * 0b1110..1/16384 count_clk
21755 * 0b1111..1/32768 count_clk
21756 */
21757#define GPC_PGC_PU12_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU12_SR_PUP_CLK_DIV_SEL_MASK)
21758#define GPC_PGC_PU12_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
21759#define GPC_PGC_PU12_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
21760#define GPC_PGC_PU12_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU12_SR_L2RSTDIS_DEASSERT_CNT_MASK)
21761/*! @} */
21762
21763/*! @name PU12_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
21764/*! @{ */
21765#define GPC_PGC_PU12_AUXSW_SW2_MASK (0x3FU)
21766#define GPC_PGC_PU12_AUXSW_SW2_SHIFT (0U)
21767#define GPC_PGC_PU12_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_AUXSW_SW2_SHIFT)) & GPC_PGC_PU12_AUXSW_SW2_MASK)
21768#define GPC_PGC_PU12_AUXSW_ISO2SW2_MASK (0x3F00U)
21769#define GPC_PGC_PU12_AUXSW_ISO2SW2_SHIFT (8U)
21770/*! ISO2SW2
21771 * 0b000000..A53 is not wakeup from ALL_OFF mode.
21772 * 0b000001..A53 is wakeup from ALL_OFF mode.
21773 */
21774#define GPC_PGC_PU12_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU12_AUXSW_ISO2SW2_MASK)
21775#define GPC_PGC_PU12_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
21776#define GPC_PGC_PU12_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
21777/*! PDN_CLK_DIV_SEL
21778 * 0b0000..1
21779 * 0b0001..1/2 count_clk
21780 * 0b0010..1/4 count_clk
21781 * 0b0011..1/8 count_clk
21782 * 0b0100..1/16 count_clk
21783 * 0b0101..1/32 count_clk
21784 * 0b0110..1/64 count_clk
21785 * 0b0111..1/128 count_clk
21786 * 0b1000..1/256 count_clk
21787 * 0b1001..1/512 count_clk
21788 * 0b1010..1/1024 count_clk
21789 * 0b1011..1/2056 count_clk
21790 * 0b1100..1/4096 count_clk
21791 * 0b1101..1/8192 count_clk
21792 * 0b1110..1/16384 count_clk
21793 * 0b1111..1/32768 count_clk
21794 */
21795#define GPC_PGC_PU12_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU12_AUXSW_PDN_CLK_DIV_SEL_MASK)
21796/*! @} */
21797
21798/*! @name PU13_CTRL - GPC PGC Control Register */
21799/*! @{ */
21800#define GPC_PGC_PU13_CTRL_PCR_MASK (0x1U)
21801#define GPC_PGC_PU13_CTRL_PCR_SHIFT (0U)
21802/*! PCR
21803 * 0b0..Do not switch off power even if pdn_req is asserted.
21804 * 0b1..Switch off power when pdn_req is asserted.
21805 */
21806#define GPC_PGC_PU13_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_CTRL_PCR_SHIFT)) & GPC_PGC_PU13_CTRL_PCR_MASK)
21807#define GPC_PGC_PU13_CTRL_L2RSTDIS_MASK (0x7EU)
21808#define GPC_PGC_PU13_CTRL_L2RSTDIS_SHIFT (1U)
21809#define GPC_PGC_PU13_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU13_CTRL_L2RSTDIS_MASK)
21810#define GPC_PGC_PU13_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
21811#define GPC_PGC_PU13_CTRL_DFTRAM_TCD1_SHIFT (8U)
21812#define GPC_PGC_PU13_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU13_CTRL_DFTRAM_TCD1_MASK)
21813#define GPC_PGC_PU13_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
21814#define GPC_PGC_PU13_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
21815#define GPC_PGC_PU13_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU13_CTRL_L2RETN_TCD1_TDR_MASK)
21816#define GPC_PGC_PU13_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
21817#define GPC_PGC_PU13_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
21818#define GPC_PGC_PU13_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU13_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
21819/*! @} */
21820
21821/*! @name PU13_PUPSCR - GPC PGC Up Sequence Control Register */
21822/*! @{ */
21823#define GPC_PGC_PU13_PUPSCR_SW_MASK (0x3FU)
21824#define GPC_PGC_PU13_PUPSCR_SW_SHIFT (0U)
21825#define GPC_PGC_PU13_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PUPSCR_SW_SHIFT)) & GPC_PGC_PU13_PUPSCR_SW_MASK)
21826#define GPC_PGC_PU13_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
21827#define GPC_PGC_PU13_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
21828#define GPC_PGC_PU13_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU13_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
21829#define GPC_PGC_PU13_PUPSCR_SW2ISO_MASK (0x7FFF80U)
21830#define GPC_PGC_PU13_PUPSCR_SW2ISO_SHIFT (7U)
21831#define GPC_PGC_PU13_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU13_PUPSCR_SW2ISO_MASK)
21832#define GPC_PGC_PU13_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U)
21833#define GPC_PGC_PU13_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U)
21834#define GPC_PGC_PU13_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU13_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK)
21835/*! @} */
21836
21837/*! @name PU13_PDNSCR - GPC PGC Down Sequence Control Register */
21838/*! @{ */
21839#define GPC_PGC_PU13_PDNSCR_ISO_MASK (0x3FU)
21840#define GPC_PGC_PU13_PDNSCR_ISO_SHIFT (0U)
21841#define GPC_PGC_PU13_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU13_PDNSCR_ISO_MASK)
21842#define GPC_PGC_PU13_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U)
21843#define GPC_PGC_PU13_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U)
21844#define GPC_PGC_PU13_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU13_PDNSCR_PDN_WAIT_SCALL_OUT_MASK)
21845#define GPC_PGC_PU13_PDNSCR_ISO2SW_MASK (0x3F00U)
21846#define GPC_PGC_PU13_PDNSCR_ISO2SW_SHIFT (8U)
21847#define GPC_PGC_PU13_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU13_PDNSCR_ISO2SW_MASK)
21848#define GPC_PGC_PU13_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U)
21849#define GPC_PGC_PU13_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U)
21850#define GPC_PGC_PU13_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU13_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK)
21851#define GPC_PGC_PU13_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U)
21852#define GPC_PGC_PU13_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U)
21853#define GPC_PGC_PU13_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU13_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK)
21854/*! @} */
21855
21856/*! @name PU13_SR - GPC PGC Status Register */
21857/*! @{ */
21858#define GPC_PGC_PU13_SR_PSR_MASK (0x1U)
21859#define GPC_PGC_PU13_SR_PSR_SHIFT (0U)
21860/*! PSR
21861 * 0b0..The target subsystem was not powered down for the previous power-down request.
21862 * 0b1..The target subsystem was powered down for the previous power-down request.
21863 */
21864#define GPC_PGC_PU13_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_SR_PSR_SHIFT)) & GPC_PGC_PU13_SR_PSR_MASK)
21865#define GPC_PGC_PU13_SR_L2RETN_FLAG_MASK (0x2U)
21866#define GPC_PGC_PU13_SR_L2RETN_FLAG_SHIFT (1U)
21867/*! L2RETN_FLAG
21868 * 0b0..A53 is not wakeup from L2 retention mode.
21869 * 0b1..A53 is wakeup from L2 retention mode.
21870 */
21871#define GPC_PGC_PU13_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU13_SR_L2RETN_FLAG_MASK)
21872#define GPC_PGC_PU13_SR_ALLOFF_FLAG_MASK (0x4U)
21873#define GPC_PGC_PU13_SR_ALLOFF_FLAG_SHIFT (2U)
21874/*! ALLOFF_FLAG
21875 * 0b0..A53 is not wakeup from ALL_OFF mode.
21876 * 0b1..A53 is wakeup from ALL_OFF mode.
21877 */
21878#define GPC_PGC_PU13_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU13_SR_ALLOFF_FLAG_MASK)
21879#define GPC_PGC_PU13_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
21880#define GPC_PGC_PU13_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
21881/*! PUP_CLK_DIV_SEL
21882 * 0b0000..1
21883 * 0b0001..1/2 count_clk
21884 * 0b0010..1/4 count_clk
21885 * 0b0011..1/8 count_clk
21886 * 0b0100..1/16 count_clk
21887 * 0b0101..1/32 count_clk
21888 * 0b0110..1/64 count_clk
21889 * 0b0111..1/128 count_clk
21890 * 0b1000..1/256 count_clk
21891 * 0b1001..1/512 count_clk
21892 * 0b1010..1/1024 count_clk
21893 * 0b1011..1/2056 count_clk
21894 * 0b1100..1/4096 count_clk
21895 * 0b1101..1/8192 count_clk
21896 * 0b1110..1/16384 count_clk
21897 * 0b1111..1/32768 count_clk
21898 */
21899#define GPC_PGC_PU13_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU13_SR_PUP_CLK_DIV_SEL_MASK)
21900#define GPC_PGC_PU13_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
21901#define GPC_PGC_PU13_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
21902#define GPC_PGC_PU13_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU13_SR_L2RSTDIS_DEASSERT_CNT_MASK)
21903/*! @} */
21904
21905/*! @name PU13_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
21906/*! @{ */
21907#define GPC_PGC_PU13_AUXSW_SW2_MASK (0x3FU)
21908#define GPC_PGC_PU13_AUXSW_SW2_SHIFT (0U)
21909#define GPC_PGC_PU13_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_AUXSW_SW2_SHIFT)) & GPC_PGC_PU13_AUXSW_SW2_MASK)
21910#define GPC_PGC_PU13_AUXSW_ISO2SW2_MASK (0x3F00U)
21911#define GPC_PGC_PU13_AUXSW_ISO2SW2_SHIFT (8U)
21912/*! ISO2SW2
21913 * 0b000000..A53 is not wakeup from ALL_OFF mode.
21914 * 0b000001..A53 is wakeup from ALL_OFF mode.
21915 */
21916#define GPC_PGC_PU13_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU13_AUXSW_ISO2SW2_MASK)
21917#define GPC_PGC_PU13_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U)
21918#define GPC_PGC_PU13_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U)
21919/*! PDN_CLK_DIV_SEL
21920 * 0b0000..1
21921 * 0b0001..1/2 count_clk
21922 * 0b0010..1/4 count_clk
21923 * 0b0011..1/8 count_clk
21924 * 0b0100..1/16 count_clk
21925 * 0b0101..1/32 count_clk
21926 * 0b0110..1/64 count_clk
21927 * 0b0111..1/128 count_clk
21928 * 0b1000..1/256 count_clk
21929 * 0b1001..1/512 count_clk
21930 * 0b1010..1/1024 count_clk
21931 * 0b1011..1/2056 count_clk
21932 * 0b1100..1/4096 count_clk
21933 * 0b1101..1/8192 count_clk
21934 * 0b1110..1/16384 count_clk
21935 * 0b1111..1/32768 count_clk
21936 */
21937#define GPC_PGC_PU13_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU13_AUXSW_PDN_CLK_DIV_SEL_MASK)
21938/*! @} */
21939
21940
21941/*!
21942 * @}
21943 */ /* end of group GPC_PGC_Register_Masks */
21944
21945
21946/* GPC_PGC - Peripheral instance base addresses */
21947/** Peripheral GPC_PGC base address */
21948#define GPC_PGC_BASE (0x303A0800u)
21949/** Peripheral GPC_PGC base pointer */
21950#define GPC_PGC ((GPC_PGC_Type *)GPC_PGC_BASE)
21951/** Array initializer of GPC_PGC peripheral base addresses */
21952#define GPC_PGC_BASE_ADDRS { GPC_PGC_BASE }
21953/** Array initializer of GPC_PGC peripheral base pointers */
21954#define GPC_PGC_BASE_PTRS { GPC_PGC }
21955
21956/*!
21957 * @}
21958 */ /* end of group GPC_PGC_Peripheral_Access_Layer */
21959
21960
21961/* ----------------------------------------------------------------------------
21962 -- GPIO Peripheral Access Layer
21963 ---------------------------------------------------------------------------- */
21964
21965/*!
21966 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
21967 * @{
21968 */
21969
21970/** GPIO - Register Layout Typedef */
21971typedef struct {
21972 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */
21973 __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */
21974 __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */
21975 __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */
21976 __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */
21977 __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */
21978 __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */
21979 __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */
21980} GPIO_Type;
21981
21982/* ----------------------------------------------------------------------------
21983 -- GPIO Register Masks
21984 ---------------------------------------------------------------------------- */
21985
21986/*!
21987 * @addtogroup GPIO_Register_Masks GPIO Register Masks
21988 * @{
21989 */
21990
21991/*! @name DR - GPIO data register */
21992/*! @{ */
21993#define GPIO_DR_DR_MASK (0xFFFFFFFFU)
21994#define GPIO_DR_DR_SHIFT (0U)
21995#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
21996/*! @} */
21997
21998/*! @name GDIR - GPIO direction register */
21999/*! @{ */
22000#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)
22001#define GPIO_GDIR_GDIR_SHIFT (0U)
22002/*! GDIR
22003 * 0b00000000000000000000000000000000..GPIO is configured as input.
22004 * 0b00000000000000000000000000000001..GPIO is configured as output.
22005 */
22006#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
22007/*! @} */
22008
22009/*! @name PSR - GPIO pad status register */
22010/*! @{ */
22011#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU)
22012#define GPIO_PSR_PSR_SHIFT (0U)
22013#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
22014/*! @} */
22015
22016/*! @name ICR1 - GPIO interrupt configuration register1 */
22017/*! @{ */
22018#define GPIO_ICR1_ICR0_MASK (0x3U)
22019#define GPIO_ICR1_ICR0_SHIFT (0U)
22020/*! ICR0
22021 * 0b00..Interrupt n is low-level sensitive.
22022 * 0b01..Interrupt n is high-level sensitive.
22023 * 0b10..Interrupt n is rising-edge sensitive.
22024 * 0b11..Interrupt n is falling-edge sensitive.
22025 */
22026#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
22027#define GPIO_ICR1_ICR1_MASK (0xCU)
22028#define GPIO_ICR1_ICR1_SHIFT (2U)
22029/*! ICR1
22030 * 0b00..Interrupt n is low-level sensitive.
22031 * 0b01..Interrupt n is high-level sensitive.
22032 * 0b10..Interrupt n is rising-edge sensitive.
22033 * 0b11..Interrupt n is falling-edge sensitive.
22034 */
22035#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
22036#define GPIO_ICR1_ICR2_MASK (0x30U)
22037#define GPIO_ICR1_ICR2_SHIFT (4U)
22038/*! ICR2
22039 * 0b00..Interrupt n is low-level sensitive.
22040 * 0b01..Interrupt n is high-level sensitive.
22041 * 0b10..Interrupt n is rising-edge sensitive.
22042 * 0b11..Interrupt n is falling-edge sensitive.
22043 */
22044#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
22045#define GPIO_ICR1_ICR3_MASK (0xC0U)
22046#define GPIO_ICR1_ICR3_SHIFT (6U)
22047/*! ICR3
22048 * 0b00..Interrupt n is low-level sensitive.
22049 * 0b01..Interrupt n is high-level sensitive.
22050 * 0b10..Interrupt n is rising-edge sensitive.
22051 * 0b11..Interrupt n is falling-edge sensitive.
22052 */
22053#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
22054#define GPIO_ICR1_ICR4_MASK (0x300U)
22055#define GPIO_ICR1_ICR4_SHIFT (8U)
22056/*! ICR4
22057 * 0b00..Interrupt n is low-level sensitive.
22058 * 0b01..Interrupt n is high-level sensitive.
22059 * 0b10..Interrupt n is rising-edge sensitive.
22060 * 0b11..Interrupt n is falling-edge sensitive.
22061 */
22062#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
22063#define GPIO_ICR1_ICR5_MASK (0xC00U)
22064#define GPIO_ICR1_ICR5_SHIFT (10U)
22065/*! ICR5
22066 * 0b00..Interrupt n is low-level sensitive.
22067 * 0b01..Interrupt n is high-level sensitive.
22068 * 0b10..Interrupt n is rising-edge sensitive.
22069 * 0b11..Interrupt n is falling-edge sensitive.
22070 */
22071#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
22072#define GPIO_ICR1_ICR6_MASK (0x3000U)
22073#define GPIO_ICR1_ICR6_SHIFT (12U)
22074/*! ICR6
22075 * 0b00..Interrupt n is low-level sensitive.
22076 * 0b01..Interrupt n is high-level sensitive.
22077 * 0b10..Interrupt n is rising-edge sensitive.
22078 * 0b11..Interrupt n is falling-edge sensitive.
22079 */
22080#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
22081#define GPIO_ICR1_ICR7_MASK (0xC000U)
22082#define GPIO_ICR1_ICR7_SHIFT (14U)
22083/*! ICR7
22084 * 0b00..Interrupt n is low-level sensitive.
22085 * 0b01..Interrupt n is high-level sensitive.
22086 * 0b10..Interrupt n is rising-edge sensitive.
22087 * 0b11..Interrupt n is falling-edge sensitive.
22088 */
22089#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
22090#define GPIO_ICR1_ICR8_MASK (0x30000U)
22091#define GPIO_ICR1_ICR8_SHIFT (16U)
22092/*! ICR8
22093 * 0b00..Interrupt n is low-level sensitive.
22094 * 0b01..Interrupt n is high-level sensitive.
22095 * 0b10..Interrupt n is rising-edge sensitive.
22096 * 0b11..Interrupt n is falling-edge sensitive.
22097 */
22098#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
22099#define GPIO_ICR1_ICR9_MASK (0xC0000U)
22100#define GPIO_ICR1_ICR9_SHIFT (18U)
22101/*! ICR9
22102 * 0b00..Interrupt n is low-level sensitive.
22103 * 0b01..Interrupt n is high-level sensitive.
22104 * 0b10..Interrupt n is rising-edge sensitive.
22105 * 0b11..Interrupt n is falling-edge sensitive.
22106 */
22107#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
22108#define GPIO_ICR1_ICR10_MASK (0x300000U)
22109#define GPIO_ICR1_ICR10_SHIFT (20U)
22110/*! ICR10
22111 * 0b00..Interrupt n is low-level sensitive.
22112 * 0b01..Interrupt n is high-level sensitive.
22113 * 0b10..Interrupt n is rising-edge sensitive.
22114 * 0b11..Interrupt n is falling-edge sensitive.
22115 */
22116#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
22117#define GPIO_ICR1_ICR11_MASK (0xC00000U)
22118#define GPIO_ICR1_ICR11_SHIFT (22U)
22119/*! ICR11
22120 * 0b00..Interrupt n is low-level sensitive.
22121 * 0b01..Interrupt n is high-level sensitive.
22122 * 0b10..Interrupt n is rising-edge sensitive.
22123 * 0b11..Interrupt n is falling-edge sensitive.
22124 */
22125#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
22126#define GPIO_ICR1_ICR12_MASK (0x3000000U)
22127#define GPIO_ICR1_ICR12_SHIFT (24U)
22128/*! ICR12
22129 * 0b00..Interrupt n is low-level sensitive.
22130 * 0b01..Interrupt n is high-level sensitive.
22131 * 0b10..Interrupt n is rising-edge sensitive.
22132 * 0b11..Interrupt n is falling-edge sensitive.
22133 */
22134#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
22135#define GPIO_ICR1_ICR13_MASK (0xC000000U)
22136#define GPIO_ICR1_ICR13_SHIFT (26U)
22137/*! ICR13
22138 * 0b00..Interrupt n is low-level sensitive.
22139 * 0b01..Interrupt n is high-level sensitive.
22140 * 0b10..Interrupt n is rising-edge sensitive.
22141 * 0b11..Interrupt n is falling-edge sensitive.
22142 */
22143#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
22144#define GPIO_ICR1_ICR14_MASK (0x30000000U)
22145#define GPIO_ICR1_ICR14_SHIFT (28U)
22146/*! ICR14
22147 * 0b00..Interrupt n is low-level sensitive.
22148 * 0b01..Interrupt n is high-level sensitive.
22149 * 0b10..Interrupt n is rising-edge sensitive.
22150 * 0b11..Interrupt n is falling-edge sensitive.
22151 */
22152#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
22153#define GPIO_ICR1_ICR15_MASK (0xC0000000U)
22154#define GPIO_ICR1_ICR15_SHIFT (30U)
22155/*! ICR15
22156 * 0b00..Interrupt n is low-level sensitive.
22157 * 0b01..Interrupt n is high-level sensitive.
22158 * 0b10..Interrupt n is rising-edge sensitive.
22159 * 0b11..Interrupt n is falling-edge sensitive.
22160 */
22161#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
22162/*! @} */
22163
22164/*! @name ICR2 - GPIO interrupt configuration register2 */
22165/*! @{ */
22166#define GPIO_ICR2_ICR16_MASK (0x3U)
22167#define GPIO_ICR2_ICR16_SHIFT (0U)
22168/*! ICR16
22169 * 0b00..Interrupt n is low-level sensitive.
22170 * 0b01..Interrupt n is high-level sensitive.
22171 * 0b10..Interrupt n is rising-edge sensitive.
22172 * 0b11..Interrupt n is falling-edge sensitive.
22173 */
22174#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
22175#define GPIO_ICR2_ICR17_MASK (0xCU)
22176#define GPIO_ICR2_ICR17_SHIFT (2U)
22177/*! ICR17
22178 * 0b00..Interrupt n is low-level sensitive.
22179 * 0b01..Interrupt n is high-level sensitive.
22180 * 0b10..Interrupt n is rising-edge sensitive.
22181 * 0b11..Interrupt n is falling-edge sensitive.
22182 */
22183#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
22184#define GPIO_ICR2_ICR18_MASK (0x30U)
22185#define GPIO_ICR2_ICR18_SHIFT (4U)
22186/*! ICR18
22187 * 0b00..Interrupt n is low-level sensitive.
22188 * 0b01..Interrupt n is high-level sensitive.
22189 * 0b10..Interrupt n is rising-edge sensitive.
22190 * 0b11..Interrupt n is falling-edge sensitive.
22191 */
22192#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
22193#define GPIO_ICR2_ICR19_MASK (0xC0U)
22194#define GPIO_ICR2_ICR19_SHIFT (6U)
22195/*! ICR19
22196 * 0b00..Interrupt n is low-level sensitive.
22197 * 0b01..Interrupt n is high-level sensitive.
22198 * 0b10..Interrupt n is rising-edge sensitive.
22199 * 0b11..Interrupt n is falling-edge sensitive.
22200 */
22201#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
22202#define GPIO_ICR2_ICR20_MASK (0x300U)
22203#define GPIO_ICR2_ICR20_SHIFT (8U)
22204/*! ICR20
22205 * 0b00..Interrupt n is low-level sensitive.
22206 * 0b01..Interrupt n is high-level sensitive.
22207 * 0b10..Interrupt n is rising-edge sensitive.
22208 * 0b11..Interrupt n is falling-edge sensitive.
22209 */
22210#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
22211#define GPIO_ICR2_ICR21_MASK (0xC00U)
22212#define GPIO_ICR2_ICR21_SHIFT (10U)
22213/*! ICR21
22214 * 0b00..Interrupt n is low-level sensitive.
22215 * 0b01..Interrupt n is high-level sensitive.
22216 * 0b10..Interrupt n is rising-edge sensitive.
22217 * 0b11..Interrupt n is falling-edge sensitive.
22218 */
22219#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
22220#define GPIO_ICR2_ICR22_MASK (0x3000U)
22221#define GPIO_ICR2_ICR22_SHIFT (12U)
22222/*! ICR22
22223 * 0b00..Interrupt n is low-level sensitive.
22224 * 0b01..Interrupt n is high-level sensitive.
22225 * 0b10..Interrupt n is rising-edge sensitive.
22226 * 0b11..Interrupt n is falling-edge sensitive.
22227 */
22228#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
22229#define GPIO_ICR2_ICR23_MASK (0xC000U)
22230#define GPIO_ICR2_ICR23_SHIFT (14U)
22231/*! ICR23
22232 * 0b00..Interrupt n is low-level sensitive.
22233 * 0b01..Interrupt n is high-level sensitive.
22234 * 0b10..Interrupt n is rising-edge sensitive.
22235 * 0b11..Interrupt n is falling-edge sensitive.
22236 */
22237#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
22238#define GPIO_ICR2_ICR24_MASK (0x30000U)
22239#define GPIO_ICR2_ICR24_SHIFT (16U)
22240/*! ICR24
22241 * 0b00..Interrupt n is low-level sensitive.
22242 * 0b01..Interrupt n is high-level sensitive.
22243 * 0b10..Interrupt n is rising-edge sensitive.
22244 * 0b11..Interrupt n is falling-edge sensitive.
22245 */
22246#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
22247#define GPIO_ICR2_ICR25_MASK (0xC0000U)
22248#define GPIO_ICR2_ICR25_SHIFT (18U)
22249/*! ICR25
22250 * 0b00..Interrupt n is low-level sensitive.
22251 * 0b01..Interrupt n is high-level sensitive.
22252 * 0b10..Interrupt n is rising-edge sensitive.
22253 * 0b11..Interrupt n is falling-edge sensitive.
22254 */
22255#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
22256#define GPIO_ICR2_ICR26_MASK (0x300000U)
22257#define GPIO_ICR2_ICR26_SHIFT (20U)
22258/*! ICR26
22259 * 0b00..Interrupt n is low-level sensitive.
22260 * 0b01..Interrupt n is high-level sensitive.
22261 * 0b10..Interrupt n is rising-edge sensitive.
22262 * 0b11..Interrupt n is falling-edge sensitive.
22263 */
22264#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
22265#define GPIO_ICR2_ICR27_MASK (0xC00000U)
22266#define GPIO_ICR2_ICR27_SHIFT (22U)
22267/*! ICR27
22268 * 0b00..Interrupt n is low-level sensitive.
22269 * 0b01..Interrupt n is high-level sensitive.
22270 * 0b10..Interrupt n is rising-edge sensitive.
22271 * 0b11..Interrupt n is falling-edge sensitive.
22272 */
22273#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
22274#define GPIO_ICR2_ICR28_MASK (0x3000000U)
22275#define GPIO_ICR2_ICR28_SHIFT (24U)
22276/*! ICR28
22277 * 0b00..Interrupt n is low-level sensitive.
22278 * 0b01..Interrupt n is high-level sensitive.
22279 * 0b10..Interrupt n is rising-edge sensitive.
22280 * 0b11..Interrupt n is falling-edge sensitive.
22281 */
22282#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
22283#define GPIO_ICR2_ICR29_MASK (0xC000000U)
22284#define GPIO_ICR2_ICR29_SHIFT (26U)
22285/*! ICR29
22286 * 0b00..Interrupt n is low-level sensitive.
22287 * 0b01..Interrupt n is high-level sensitive.
22288 * 0b10..Interrupt n is rising-edge sensitive.
22289 * 0b11..Interrupt n is falling-edge sensitive.
22290 */
22291#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
22292#define GPIO_ICR2_ICR30_MASK (0x30000000U)
22293#define GPIO_ICR2_ICR30_SHIFT (28U)
22294/*! ICR30
22295 * 0b00..Interrupt n is low-level sensitive.
22296 * 0b01..Interrupt n is high-level sensitive.
22297 * 0b10..Interrupt n is rising-edge sensitive.
22298 * 0b11..Interrupt n is falling-edge sensitive.
22299 */
22300#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
22301#define GPIO_ICR2_ICR31_MASK (0xC0000000U)
22302#define GPIO_ICR2_ICR31_SHIFT (30U)
22303/*! ICR31
22304 * 0b00..Interrupt n is low-level sensitive.
22305 * 0b01..Interrupt n is high-level sensitive.
22306 * 0b10..Interrupt n is rising-edge sensitive.
22307 * 0b11..Interrupt n is falling-edge sensitive.
22308 */
22309#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
22310/*! @} */
22311
22312/*! @name IMR - GPIO interrupt mask register */
22313/*! @{ */
22314#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU)
22315#define GPIO_IMR_IMR_SHIFT (0U)
22316/*! IMR
22317 * 0b00000000000000000000000000000000..Interrupt n is disabled.
22318 * 0b00000000000000000000000000000001..Interrupt n is enabled.
22319 */
22320#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
22321/*! @} */
22322
22323/*! @name ISR - GPIO interrupt status register */
22324/*! @{ */
22325#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU)
22326#define GPIO_ISR_ISR_SHIFT (0U)
22327#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
22328/*! @} */
22329
22330/*! @name EDGE_SEL - GPIO edge select register */
22331/*! @{ */
22332#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)
22333#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)
22334#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
22335/*! @} */
22336
22337
22338/*!
22339 * @}
22340 */ /* end of group GPIO_Register_Masks */
22341
22342
22343/* GPIO - Peripheral instance base addresses */
22344/** Peripheral GPIO1 base address */
22345#define GPIO1_BASE (0x30200000u)
22346/** Peripheral GPIO1 base pointer */
22347#define GPIO1 ((GPIO_Type *)GPIO1_BASE)
22348/** Peripheral GPIO2 base address */
22349#define GPIO2_BASE (0x30210000u)
22350/** Peripheral GPIO2 base pointer */
22351#define GPIO2 ((GPIO_Type *)GPIO2_BASE)
22352/** Peripheral GPIO3 base address */
22353#define GPIO3_BASE (0x30220000u)
22354/** Peripheral GPIO3 base pointer */
22355#define GPIO3 ((GPIO_Type *)GPIO3_BASE)
22356/** Peripheral GPIO4 base address */
22357#define GPIO4_BASE (0x30230000u)
22358/** Peripheral GPIO4 base pointer */
22359#define GPIO4 ((GPIO_Type *)GPIO4_BASE)
22360/** Peripheral GPIO5 base address */
22361#define GPIO5_BASE (0x30240000u)
22362/** Peripheral GPIO5 base pointer */
22363#define GPIO5 ((GPIO_Type *)GPIO5_BASE)
22364/** Array initializer of GPIO peripheral base addresses */
22365#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE }
22366/** Array initializer of GPIO peripheral base pointers */
22367#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 }
22368/** Interrupt vectors for the GPIO peripheral type */
22369#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
22370#define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn }
22371#define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn }
22372
22373/*!
22374 * @}
22375 */ /* end of group GPIO_Peripheral_Access_Layer */
22376
22377
22378/* ----------------------------------------------------------------------------
22379 -- GPMI Peripheral Access Layer
22380 ---------------------------------------------------------------------------- */
22381
22382/*!
22383 * @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer
22384 * @{
22385 */
22386
22387/** GPMI - Register Layout Typedef */
22388typedef struct {
22389 __IO uint32_t CTRL0; /**< GPMI Control Register 0 Description, offset: 0x0 */
22390 __IO uint32_t CTRL0_SET; /**< GPMI Control Register 0 Description, offset: 0x4 */
22391 __IO uint32_t CTRL0_CLR; /**< GPMI Control Register 0 Description, offset: 0x8 */
22392 __IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset: 0xC */
22393 __IO uint32_t COMPARE; /**< GPMI Compare Register Description, offset: 0x10 */
22394 uint8_t RESERVED_0[12];
22395 __IO uint32_t ECCCTRL; /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */
22396 __IO uint32_t ECCCTRL_SET; /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */
22397 __IO uint32_t ECCCTRL_CLR; /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */
22398 __IO uint32_t ECCCTRL_TOG; /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */
22399 __IO uint32_t ECCCOUNT; /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */
22400 uint8_t RESERVED_1[12];
22401 __IO uint32_t PAYLOAD; /**< GPMI Payload Address Register Description, offset: 0x40 */
22402 uint8_t RESERVED_2[12];
22403 __IO uint32_t AUXILIARY; /**< GPMI Auxiliary Address Register Description, offset: 0x50 */
22404 uint8_t RESERVED_3[12];
22405 __IO uint32_t CTRL1; /**< GPMI Control Register 1 Description, offset: 0x60 */
22406 __IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset: 0x64 */
22407 __IO uint32_t CTRL1_CLR; /**< GPMI Control Register 1 Description, offset: 0x68 */
22408 __IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset: 0x6C */
22409 __IO uint32_t TIMING0; /**< GPMI Timing Register 0 Description, offset: 0x70 */
22410 uint8_t RESERVED_4[12];
22411 __IO uint32_t TIMING1; /**< GPMI Timing Register 1 Description, offset: 0x80 */
22412 uint8_t RESERVED_5[12];
22413 __IO uint32_t TIMING2; /**< GPMI Timing Register 2 Description, offset: 0x90 */
22414 uint8_t RESERVED_6[12];
22415 __IO uint32_t DATA; /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */
22416 uint8_t RESERVED_7[12];
22417 __I uint32_t STAT; /**< GPMI Status Register Description, offset: 0xB0 */
22418 uint8_t RESERVED_8[12];
22419 __I uint32_t DEBUGr; /**< GPMI Debug Information Register Description, offset: 0xC0 */
22420 uint8_t RESERVED_9[12];
22421 __I uint32_t VERSION; /**< GPMI Version Register Description, offset: 0xD0 */
22422 uint8_t RESERVED_10[12];
22423 __IO uint32_t DEBUG2; /**< GPMI Debug2 Information Register Description, offset: 0xE0 */
22424 uint8_t RESERVED_11[12];
22425 __I uint32_t DEBUG3; /**< GPMI Debug3 Information Register Description, offset: 0xF0 */
22426 uint8_t RESERVED_12[12];
22427 __IO uint32_t READ_DDR_DLL_CTRL; /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */
22428 uint8_t RESERVED_13[12];
22429 __IO uint32_t WRITE_DDR_DLL_CTRL; /**< GPMI Double Rate Write DLL Control Register Description, offset: 0x110 */
22430 uint8_t RESERVED_14[12];
22431 __I uint32_t READ_DDR_DLL_STS; /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */
22432 uint8_t RESERVED_15[12];
22433 __I uint32_t WRITE_DDR_DLL_STS; /**< GPMI Double Rate Write DLL Status Register Description, offset: 0x130 */
22434} GPMI_Type;
22435
22436/* ----------------------------------------------------------------------------
22437 -- GPMI Register Masks
22438 ---------------------------------------------------------------------------- */
22439
22440/*!
22441 * @addtogroup GPMI_Register_Masks GPMI Register Masks
22442 * @{
22443 */
22444
22445/*! @name CTRL0 - GPMI Control Register 0 Description */
22446/*! @{ */
22447#define GPMI_CTRL0_XFER_COUNT_MASK (0xFFFFU)
22448#define GPMI_CTRL0_XFER_COUNT_SHIFT (0U)
22449#define GPMI_CTRL0_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_XFER_COUNT_SHIFT)) & GPMI_CTRL0_XFER_COUNT_MASK)
22450#define GPMI_CTRL0_ADDRESS_INCREMENT_MASK (0x10000U)
22451#define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT (16U)
22452/*! ADDRESS_INCREMENT
22453 * 0b0..Address does not increment.
22454 * 0b1..Increment address.
22455 */
22456#define GPMI_CTRL0_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_ADDRESS_INCREMENT_MASK)
22457#define GPMI_CTRL0_ADDRESS_MASK (0xE0000U)
22458#define GPMI_CTRL0_ADDRESS_SHIFT (17U)
22459#define GPMI_CTRL0_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_SHIFT)) & GPMI_CTRL0_ADDRESS_MASK)
22460#define GPMI_CTRL0_CS_MASK (0x700000U)
22461#define GPMI_CTRL0_CS_SHIFT (20U)
22462#define GPMI_CTRL0_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CS_SHIFT)) & GPMI_CTRL0_CS_MASK)
22463#define GPMI_CTRL0_WORD_LENGTH_MASK (0x800000U)
22464#define GPMI_CTRL0_WORD_LENGTH_SHIFT (23U)
22465/*! WORD_LENGTH
22466 * 0b0..Reserved.
22467 * 0b1..8-bit Data Bus mode.
22468 */
22469#define GPMI_CTRL0_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_WORD_LENGTH_MASK)
22470#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3000000U)
22471#define GPMI_CTRL0_COMMAND_MODE_SHIFT (24U)
22472/*! COMMAND_MODE
22473 * 0b00..Write mode.
22474 * 0b01..Read Mode.
22475 * 0b10..Read and Compare Mode (setting sense flop).
22476 * 0b11..Wait for Ready.
22477 */
22478#define GPMI_CTRL0_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_COMMAND_MODE_MASK)
22479#define GPMI_CTRL0_UDMA_MASK (0x4000000U)
22480#define GPMI_CTRL0_UDMA_SHIFT (26U)
22481/*! UDMA
22482 * 0b0..Use ATA-PIO mode on the external bus.
22483 * 0b1..Use ATA-Ultra DMA mode on the external bus.
22484 */
22485#define GPMI_CTRL0_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_UDMA_SHIFT)) & GPMI_CTRL0_UDMA_MASK)
22486#define GPMI_CTRL0_LOCK_CS_MASK (0x8000000U)
22487#define GPMI_CTRL0_LOCK_CS_SHIFT (27U)
22488#define GPMI_CTRL0_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_LOCK_CS_SHIFT)) & GPMI_CTRL0_LOCK_CS_MASK)
22489#define GPMI_CTRL0_DEV_IRQ_EN_MASK (0x10000000U)
22490#define GPMI_CTRL0_DEV_IRQ_EN_SHIFT (28U)
22491#define GPMI_CTRL0_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_DEV_IRQ_EN_MASK)
22492#define GPMI_CTRL0_RUN_MASK (0x20000000U)
22493#define GPMI_CTRL0_RUN_SHIFT (29U)
22494#define GPMI_CTRL0_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_RUN_SHIFT)) & GPMI_CTRL0_RUN_MASK)
22495#define GPMI_CTRL0_CLKGATE_MASK (0x40000000U)
22496#define GPMI_CTRL0_CLKGATE_SHIFT (30U)
22497#define GPMI_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLKGATE_SHIFT)) & GPMI_CTRL0_CLKGATE_MASK)
22498#define GPMI_CTRL0_SFTRST_MASK (0x80000000U)
22499#define GPMI_CTRL0_SFTRST_SHIFT (31U)
22500#define GPMI_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SFTRST_SHIFT)) & GPMI_CTRL0_SFTRST_MASK)
22501/*! @} */
22502
22503/*! @name CTRL0_SET - GPMI Control Register 0 Description */
22504/*! @{ */
22505#define GPMI_CTRL0_SET_XFER_COUNT_MASK (0xFFFFU)
22506#define GPMI_CTRL0_SET_XFER_COUNT_SHIFT (0U)
22507#define GPMI_CTRL0_SET_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_XFER_COUNT_SHIFT)) & GPMI_CTRL0_SET_XFER_COUNT_MASK)
22508#define GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK (0x10000U)
22509#define GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT (16U)
22510/*! ADDRESS_INCREMENT
22511 * 0b0..Address does not increment.
22512 * 0b1..Increment address.
22513 */
22514#define GPMI_CTRL0_SET_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK)
22515#define GPMI_CTRL0_SET_ADDRESS_MASK (0xE0000U)
22516#define GPMI_CTRL0_SET_ADDRESS_SHIFT (17U)
22517#define GPMI_CTRL0_SET_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_MASK)
22518#define GPMI_CTRL0_SET_CS_MASK (0x700000U)
22519#define GPMI_CTRL0_SET_CS_SHIFT (20U)
22520#define GPMI_CTRL0_SET_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CS_SHIFT)) & GPMI_CTRL0_SET_CS_MASK)
22521#define GPMI_CTRL0_SET_WORD_LENGTH_MASK (0x800000U)
22522#define GPMI_CTRL0_SET_WORD_LENGTH_SHIFT (23U)
22523/*! WORD_LENGTH
22524 * 0b0..Reserved.
22525 * 0b1..8-bit Data Bus mode.
22526 */
22527#define GPMI_CTRL0_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_SET_WORD_LENGTH_MASK)
22528#define GPMI_CTRL0_SET_COMMAND_MODE_MASK (0x3000000U)
22529#define GPMI_CTRL0_SET_COMMAND_MODE_SHIFT (24U)
22530/*! COMMAND_MODE
22531 * 0b00..Write mode.
22532 * 0b01..Read Mode.
22533 * 0b10..Read and Compare Mode (setting sense flop).
22534 * 0b11..Wait for Ready.
22535 */
22536#define GPMI_CTRL0_SET_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_SET_COMMAND_MODE_MASK)
22537#define GPMI_CTRL0_SET_UDMA_MASK (0x4000000U)
22538#define GPMI_CTRL0_SET_UDMA_SHIFT (26U)
22539/*! UDMA
22540 * 0b0..Use ATA-PIO mode on the external bus.
22541 * 0b1..Use ATA-Ultra DMA mode on the external bus.
22542 */
22543#define GPMI_CTRL0_SET_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_UDMA_SHIFT)) & GPMI_CTRL0_SET_UDMA_MASK)
22544#define GPMI_CTRL0_SET_LOCK_CS_MASK (0x8000000U)
22545#define GPMI_CTRL0_SET_LOCK_CS_SHIFT (27U)
22546#define GPMI_CTRL0_SET_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_LOCK_CS_SHIFT)) & GPMI_CTRL0_SET_LOCK_CS_MASK)
22547#define GPMI_CTRL0_SET_DEV_IRQ_EN_MASK (0x10000000U)
22548#define GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT (28U)
22549#define GPMI_CTRL0_SET_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_SET_DEV_IRQ_EN_MASK)
22550#define GPMI_CTRL0_SET_RUN_MASK (0x20000000U)
22551#define GPMI_CTRL0_SET_RUN_SHIFT (29U)
22552#define GPMI_CTRL0_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_RUN_SHIFT)) & GPMI_CTRL0_SET_RUN_MASK)
22553#define GPMI_CTRL0_SET_CLKGATE_MASK (0x40000000U)
22554#define GPMI_CTRL0_SET_CLKGATE_SHIFT (30U)
22555#define GPMI_CTRL0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CLKGATE_SHIFT)) & GPMI_CTRL0_SET_CLKGATE_MASK)
22556#define GPMI_CTRL0_SET_SFTRST_MASK (0x80000000U)
22557#define GPMI_CTRL0_SET_SFTRST_SHIFT (31U)
22558#define GPMI_CTRL0_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_SFTRST_SHIFT)) & GPMI_CTRL0_SET_SFTRST_MASK)
22559/*! @} */
22560
22561/*! @name CTRL0_CLR - GPMI Control Register 0 Description */
22562/*! @{ */
22563#define GPMI_CTRL0_CLR_XFER_COUNT_MASK (0xFFFFU)
22564#define GPMI_CTRL0_CLR_XFER_COUNT_SHIFT (0U)
22565#define GPMI_CTRL0_CLR_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_XFER_COUNT_SHIFT)) & GPMI_CTRL0_CLR_XFER_COUNT_MASK)
22566#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK (0x10000U)
22567#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT (16U)
22568/*! ADDRESS_INCREMENT
22569 * 0b0..Address does not increment.
22570 * 0b1..Increment address.
22571 */
22572#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK)
22573#define GPMI_CTRL0_CLR_ADDRESS_MASK (0xE0000U)
22574#define GPMI_CTRL0_CLR_ADDRESS_SHIFT (17U)
22575#define GPMI_CTRL0_CLR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_MASK)
22576#define GPMI_CTRL0_CLR_CS_MASK (0x700000U)
22577#define GPMI_CTRL0_CLR_CS_SHIFT (20U)
22578#define GPMI_CTRL0_CLR_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CS_SHIFT)) & GPMI_CTRL0_CLR_CS_MASK)
22579#define GPMI_CTRL0_CLR_WORD_LENGTH_MASK (0x800000U)
22580#define GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT (23U)
22581/*! WORD_LENGTH
22582 * 0b0..Reserved.
22583 * 0b1..8-bit Data Bus mode.
22584 */
22585#define GPMI_CTRL0_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_CLR_WORD_LENGTH_MASK)
22586#define GPMI_CTRL0_CLR_COMMAND_MODE_MASK (0x3000000U)
22587#define GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT (24U)
22588/*! COMMAND_MODE
22589 * 0b00..Write mode.
22590 * 0b01..Read Mode.
22591 * 0b10..Read and Compare Mode (setting sense flop).
22592 * 0b11..Wait for Ready.
22593 */
22594#define GPMI_CTRL0_CLR_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_CLR_COMMAND_MODE_MASK)
22595#define GPMI_CTRL0_CLR_UDMA_MASK (0x4000000U)
22596#define GPMI_CTRL0_CLR_UDMA_SHIFT (26U)
22597/*! UDMA
22598 * 0b0..Use ATA-PIO mode on the external bus.
22599 * 0b1..Use ATA-Ultra DMA mode on the external bus.
22600 */
22601#define GPMI_CTRL0_CLR_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_UDMA_SHIFT)) & GPMI_CTRL0_CLR_UDMA_MASK)
22602#define GPMI_CTRL0_CLR_LOCK_CS_MASK (0x8000000U)
22603#define GPMI_CTRL0_CLR_LOCK_CS_SHIFT (27U)
22604#define GPMI_CTRL0_CLR_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_LOCK_CS_SHIFT)) & GPMI_CTRL0_CLR_LOCK_CS_MASK)
22605#define GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK (0x10000000U)
22606#define GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT (28U)
22607#define GPMI_CTRL0_CLR_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK)
22608#define GPMI_CTRL0_CLR_RUN_MASK (0x20000000U)
22609#define GPMI_CTRL0_CLR_RUN_SHIFT (29U)
22610#define GPMI_CTRL0_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_RUN_SHIFT)) & GPMI_CTRL0_CLR_RUN_MASK)
22611#define GPMI_CTRL0_CLR_CLKGATE_MASK (0x40000000U)
22612#define GPMI_CTRL0_CLR_CLKGATE_SHIFT (30U)
22613#define GPMI_CTRL0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CLKGATE_SHIFT)) & GPMI_CTRL0_CLR_CLKGATE_MASK)
22614#define GPMI_CTRL0_CLR_SFTRST_MASK (0x80000000U)
22615#define GPMI_CTRL0_CLR_SFTRST_SHIFT (31U)
22616#define GPMI_CTRL0_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_SFTRST_SHIFT)) & GPMI_CTRL0_CLR_SFTRST_MASK)
22617/*! @} */
22618
22619/*! @name CTRL0_TOG - GPMI Control Register 0 Description */
22620/*! @{ */
22621#define GPMI_CTRL0_TOG_XFER_COUNT_MASK (0xFFFFU)
22622#define GPMI_CTRL0_TOG_XFER_COUNT_SHIFT (0U)
22623#define GPMI_CTRL0_TOG_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_XFER_COUNT_SHIFT)) & GPMI_CTRL0_TOG_XFER_COUNT_MASK)
22624#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK (0x10000U)
22625#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT (16U)
22626/*! ADDRESS_INCREMENT
22627 * 0b0..Address does not increment.
22628 * 0b1..Increment address.
22629 */
22630#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK)
22631#define GPMI_CTRL0_TOG_ADDRESS_MASK (0xE0000U)
22632#define GPMI_CTRL0_TOG_ADDRESS_SHIFT (17U)
22633#define GPMI_CTRL0_TOG_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_MASK)
22634#define GPMI_CTRL0_TOG_CS_MASK (0x700000U)
22635#define GPMI_CTRL0_TOG_CS_SHIFT (20U)
22636#define GPMI_CTRL0_TOG_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CS_SHIFT)) & GPMI_CTRL0_TOG_CS_MASK)
22637#define GPMI_CTRL0_TOG_WORD_LENGTH_MASK (0x800000U)
22638#define GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT (23U)
22639/*! WORD_LENGTH
22640 * 0b0..Reserved.
22641 * 0b1..8-bit Data Bus mode.
22642 */
22643#define GPMI_CTRL0_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_TOG_WORD_LENGTH_MASK)
22644#define GPMI_CTRL0_TOG_COMMAND_MODE_MASK (0x3000000U)
22645#define GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT (24U)
22646/*! COMMAND_MODE
22647 * 0b00..Write mode.
22648 * 0b01..Read Mode.
22649 * 0b10..Read and Compare Mode (setting sense flop).
22650 * 0b11..Wait for Ready.
22651 */
22652#define GPMI_CTRL0_TOG_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_TOG_COMMAND_MODE_MASK)
22653#define GPMI_CTRL0_TOG_UDMA_MASK (0x4000000U)
22654#define GPMI_CTRL0_TOG_UDMA_SHIFT (26U)
22655/*! UDMA
22656 * 0b0..Use ATA-PIO mode on the external bus.
22657 * 0b1..Use ATA-Ultra DMA mode on the external bus.
22658 */
22659#define GPMI_CTRL0_TOG_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_UDMA_SHIFT)) & GPMI_CTRL0_TOG_UDMA_MASK)
22660#define GPMI_CTRL0_TOG_LOCK_CS_MASK (0x8000000U)
22661#define GPMI_CTRL0_TOG_LOCK_CS_SHIFT (27U)
22662#define GPMI_CTRL0_TOG_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_LOCK_CS_SHIFT)) & GPMI_CTRL0_TOG_LOCK_CS_MASK)
22663#define GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK (0x10000000U)
22664#define GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT (28U)
22665#define GPMI_CTRL0_TOG_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK)
22666#define GPMI_CTRL0_TOG_RUN_MASK (0x20000000U)
22667#define GPMI_CTRL0_TOG_RUN_SHIFT (29U)
22668#define GPMI_CTRL0_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_RUN_SHIFT)) & GPMI_CTRL0_TOG_RUN_MASK)
22669#define GPMI_CTRL0_TOG_CLKGATE_MASK (0x40000000U)
22670#define GPMI_CTRL0_TOG_CLKGATE_SHIFT (30U)
22671#define GPMI_CTRL0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CLKGATE_SHIFT)) & GPMI_CTRL0_TOG_CLKGATE_MASK)
22672#define GPMI_CTRL0_TOG_SFTRST_MASK (0x80000000U)
22673#define GPMI_CTRL0_TOG_SFTRST_SHIFT (31U)
22674#define GPMI_CTRL0_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_SFTRST_SHIFT)) & GPMI_CTRL0_TOG_SFTRST_MASK)
22675/*! @} */
22676
22677/*! @name COMPARE - GPMI Compare Register Description */
22678/*! @{ */
22679#define GPMI_COMPARE_REFERENCE_MASK (0xFFFFU)
22680#define GPMI_COMPARE_REFERENCE_SHIFT (0U)
22681#define GPMI_COMPARE_REFERENCE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_REFERENCE_SHIFT)) & GPMI_COMPARE_REFERENCE_MASK)
22682#define GPMI_COMPARE_MASK_MASK (0xFFFF0000U)
22683#define GPMI_COMPARE_MASK_SHIFT (16U)
22684#define GPMI_COMPARE_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_MASK_SHIFT)) & GPMI_COMPARE_MASK_MASK)
22685/*! @} */
22686
22687/*! @name ECCCTRL - GPMI Integrated ECC Control Register Description */
22688/*! @{ */
22689#define GPMI_ECCCTRL_BUFFER_MASK_MASK (0x1FFU)
22690#define GPMI_ECCCTRL_BUFFER_MASK_SHIFT (0U)
22691#define GPMI_ECCCTRL_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_BUFFER_MASK_MASK)
22692#define GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK (0x600U)
22693#define GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT (9U)
22694/*! RANDOMIZER_TYPE
22695 * 0b00..Type 0
22696 * 0b01..Type 1
22697 */
22698#define GPMI_ECCCTRL_RANDOMIZER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK)
22699#define GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK (0x800U)
22700#define GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT (11U)
22701/*! RANDOMIZER_ENABLE
22702 * 0b0..disable
22703 * 0b1..enable
22704 */
22705#define GPMI_ECCCTRL_RANDOMIZER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK)
22706#define GPMI_ECCCTRL_ENABLE_ECC_MASK (0x1000U)
22707#define GPMI_ECCCTRL_ENABLE_ECC_SHIFT (12U)
22708#define GPMI_ECCCTRL_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_ENABLE_ECC_MASK)
22709#define GPMI_ECCCTRL_ECC_CMD_MASK (0x6000U)
22710#define GPMI_ECCCTRL_ECC_CMD_SHIFT (13U)
22711#define GPMI_ECCCTRL_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_ECC_CMD_MASK)
22712#define GPMI_ECCCTRL_RSVD2_MASK (0x8000U)
22713#define GPMI_ECCCTRL_RSVD2_SHIFT (15U)
22714#define GPMI_ECCCTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD2_SHIFT)) & GPMI_ECCCTRL_RSVD2_MASK)
22715#define GPMI_ECCCTRL_HANDLE_MASK (0xFFFF0000U)
22716#define GPMI_ECCCTRL_HANDLE_SHIFT (16U)
22717#define GPMI_ECCCTRL_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_HANDLE_SHIFT)) & GPMI_ECCCTRL_HANDLE_MASK)
22718/*! @} */
22719
22720/*! @name ECCCTRL_SET - GPMI Integrated ECC Control Register Description */
22721/*! @{ */
22722#define GPMI_ECCCTRL_SET_BUFFER_MASK_MASK (0x1FFU)
22723#define GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT (0U)
22724#define GPMI_ECCCTRL_SET_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_SET_BUFFER_MASK_MASK)
22725#define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_MASK (0x600U)
22726#define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_SHIFT (9U)
22727/*! RANDOMIZER_TYPE
22728 * 0b00..Type 0
22729 * 0b01..Type 1
22730 */
22731#define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_MASK)
22732#define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_MASK (0x800U)
22733#define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_SHIFT (11U)
22734/*! RANDOMIZER_ENABLE
22735 * 0b0..disable
22736 * 0b1..enable
22737 */
22738#define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_MASK)
22739#define GPMI_ECCCTRL_SET_ENABLE_ECC_MASK (0x1000U)
22740#define GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT (12U)
22741#define GPMI_ECCCTRL_SET_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_SET_ENABLE_ECC_MASK)
22742#define GPMI_ECCCTRL_SET_ECC_CMD_MASK (0x6000U)
22743#define GPMI_ECCCTRL_SET_ECC_CMD_SHIFT (13U)
22744#define GPMI_ECCCTRL_SET_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_SET_ECC_CMD_MASK)
22745#define GPMI_ECCCTRL_SET_RSVD2_MASK (0x8000U)
22746#define GPMI_ECCCTRL_SET_RSVD2_SHIFT (15U)
22747#define GPMI_ECCCTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RSVD2_SHIFT)) & GPMI_ECCCTRL_SET_RSVD2_MASK)
22748#define GPMI_ECCCTRL_SET_HANDLE_MASK (0xFFFF0000U)
22749#define GPMI_ECCCTRL_SET_HANDLE_SHIFT (16U)
22750#define GPMI_ECCCTRL_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_HANDLE_SHIFT)) & GPMI_ECCCTRL_SET_HANDLE_MASK)
22751/*! @} */
22752
22753/*! @name ECCCTRL_CLR - GPMI Integrated ECC Control Register Description */
22754/*! @{ */
22755#define GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK (0x1FFU)
22756#define GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT (0U)
22757#define GPMI_ECCCTRL_CLR_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK)
22758#define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_MASK (0x600U)
22759#define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_SHIFT (9U)
22760/*! RANDOMIZER_TYPE
22761 * 0b00..Type 0
22762 * 0b01..Type 1
22763 */
22764#define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_MASK)
22765#define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_MASK (0x800U)
22766#define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_SHIFT (11U)
22767/*! RANDOMIZER_ENABLE
22768 * 0b0..disable
22769 * 0b1..enable
22770 */
22771#define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_MASK)
22772#define GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK (0x1000U)
22773#define GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT (12U)
22774#define GPMI_ECCCTRL_CLR_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK)
22775#define GPMI_ECCCTRL_CLR_ECC_CMD_MASK (0x6000U)
22776#define GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT (13U)
22777#define GPMI_ECCCTRL_CLR_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_CLR_ECC_CMD_MASK)
22778#define GPMI_ECCCTRL_CLR_RSVD2_MASK (0x8000U)
22779#define GPMI_ECCCTRL_CLR_RSVD2_SHIFT (15U)
22780#define GPMI_ECCCTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RSVD2_SHIFT)) & GPMI_ECCCTRL_CLR_RSVD2_MASK)
22781#define GPMI_ECCCTRL_CLR_HANDLE_MASK (0xFFFF0000U)
22782#define GPMI_ECCCTRL_CLR_HANDLE_SHIFT (16U)
22783#define GPMI_ECCCTRL_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_HANDLE_SHIFT)) & GPMI_ECCCTRL_CLR_HANDLE_MASK)
22784/*! @} */
22785
22786/*! @name ECCCTRL_TOG - GPMI Integrated ECC Control Register Description */
22787/*! @{ */
22788#define GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK (0x1FFU)
22789#define GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT (0U)
22790#define GPMI_ECCCTRL_TOG_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK)
22791#define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_MASK (0x600U)
22792#define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_SHIFT (9U)
22793/*! RANDOMIZER_TYPE
22794 * 0b00..Type 0
22795 * 0b01..Type 1
22796 */
22797#define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_MASK)
22798#define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_MASK (0x800U)
22799#define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_SHIFT (11U)
22800/*! RANDOMIZER_ENABLE
22801 * 0b0..disable
22802 * 0b1..enable
22803 */
22804#define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_MASK)
22805#define GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK (0x1000U)
22806#define GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT (12U)
22807#define GPMI_ECCCTRL_TOG_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK)
22808#define GPMI_ECCCTRL_TOG_ECC_CMD_MASK (0x6000U)
22809#define GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT (13U)
22810#define GPMI_ECCCTRL_TOG_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_TOG_ECC_CMD_MASK)
22811#define GPMI_ECCCTRL_TOG_RSVD2_MASK (0x8000U)
22812#define GPMI_ECCCTRL_TOG_RSVD2_SHIFT (15U)
22813#define GPMI_ECCCTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RSVD2_SHIFT)) & GPMI_ECCCTRL_TOG_RSVD2_MASK)
22814#define GPMI_ECCCTRL_TOG_HANDLE_MASK (0xFFFF0000U)
22815#define GPMI_ECCCTRL_TOG_HANDLE_SHIFT (16U)
22816#define GPMI_ECCCTRL_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_HANDLE_SHIFT)) & GPMI_ECCCTRL_TOG_HANDLE_MASK)
22817/*! @} */
22818
22819/*! @name ECCCOUNT - GPMI Integrated ECC Transfer Count Register Description */
22820/*! @{ */
22821#define GPMI_ECCCOUNT_COUNT_MASK (0xFFFFU)
22822#define GPMI_ECCCOUNT_COUNT_SHIFT (0U)
22823#define GPMI_ECCCOUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_COUNT_SHIFT)) & GPMI_ECCCOUNT_COUNT_MASK)
22824#define GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK (0xFF0000U)
22825#define GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT (16U)
22826#define GPMI_ECCCOUNT_RANDOMIZER_PAGE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT)) & GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK)
22827/*! @} */
22828
22829/*! @name PAYLOAD - GPMI Payload Address Register Description */
22830/*! @{ */
22831#define GPMI_PAYLOAD_RSVD0_MASK (0x3U)
22832#define GPMI_PAYLOAD_RSVD0_SHIFT (0U)
22833#define GPMI_PAYLOAD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_RSVD0_SHIFT)) & GPMI_PAYLOAD_RSVD0_MASK)
22834#define GPMI_PAYLOAD_ADDRESS_MASK (0xFFFFFFFCU)
22835#define GPMI_PAYLOAD_ADDRESS_SHIFT (2U)
22836#define GPMI_PAYLOAD_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_ADDRESS_SHIFT)) & GPMI_PAYLOAD_ADDRESS_MASK)
22837/*! @} */
22838
22839/*! @name AUXILIARY - GPMI Auxiliary Address Register Description */
22840/*! @{ */
22841#define GPMI_AUXILIARY_RSVD0_MASK (0x3U)
22842#define GPMI_AUXILIARY_RSVD0_SHIFT (0U)
22843#define GPMI_AUXILIARY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_RSVD0_SHIFT)) & GPMI_AUXILIARY_RSVD0_MASK)
22844#define GPMI_AUXILIARY_ADDRESS_MASK (0xFFFFFFFCU)
22845#define GPMI_AUXILIARY_ADDRESS_SHIFT (2U)
22846#define GPMI_AUXILIARY_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_ADDRESS_SHIFT)) & GPMI_AUXILIARY_ADDRESS_MASK)
22847/*! @} */
22848
22849/*! @name CTRL1 - GPMI Control Register 1 Description */
22850/*! @{ */
22851#define GPMI_CTRL1_GPMI_MODE_MASK (0x1U)
22852#define GPMI_CTRL1_GPMI_MODE_SHIFT (0U)
22853/*! GPMI_MODE
22854 * 0b0..NAND mode.
22855 * 0b1..ATA mode.
22856 */
22857#define GPMI_CTRL1_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_MODE_SHIFT)) & GPMI_CTRL1_GPMI_MODE_MASK)
22858#define GPMI_CTRL1_CAMERA_MODE_MASK (0x2U)
22859#define GPMI_CTRL1_CAMERA_MODE_SHIFT (1U)
22860#define GPMI_CTRL1_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CAMERA_MODE_MASK)
22861#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK (0x4U)
22862#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT (2U)
22863/*! ATA_IRQRDY_POLARITY
22864 * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
22865 * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
22866 */
22867#define GPMI_CTRL1_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK)
22868#define GPMI_CTRL1_DEV_RESET_MASK (0x8U)
22869#define GPMI_CTRL1_DEV_RESET_SHIFT (3U)
22870/*! DEV_RESET
22871 * 0b0..NANDF_WP_B pin is held low (asserted).
22872 * 0b1..NANDF_WP_B pin is held high (de-asserted).
22873 */
22874#define GPMI_CTRL1_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_RESET_SHIFT)) & GPMI_CTRL1_DEV_RESET_MASK)
22875#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
22876#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
22877#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
22878#define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK (0x80U)
22879#define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT (7U)
22880#define GPMI_CTRL1_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK)
22881#define GPMI_CTRL1_BURST_EN_MASK (0x100U)
22882#define GPMI_CTRL1_BURST_EN_SHIFT (8U)
22883#define GPMI_CTRL1_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BURST_EN_SHIFT)) & GPMI_CTRL1_BURST_EN_MASK)
22884#define GPMI_CTRL1_TIMEOUT_IRQ_MASK (0x200U)
22885#define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT (9U)
22886#define GPMI_CTRL1_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_MASK)
22887#define GPMI_CTRL1_DEV_IRQ_MASK (0x400U)
22888#define GPMI_CTRL1_DEV_IRQ_SHIFT (10U)
22889#define GPMI_CTRL1_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_IRQ_SHIFT)) & GPMI_CTRL1_DEV_IRQ_MASK)
22890#define GPMI_CTRL1_DMA2ECC_MODE_MASK (0x800U)
22891#define GPMI_CTRL1_DMA2ECC_MODE_SHIFT (11U)
22892#define GPMI_CTRL1_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_DMA2ECC_MODE_MASK)
22893#define GPMI_CTRL1_RDN_DELAY_MASK (0xF000U)
22894#define GPMI_CTRL1_RDN_DELAY_SHIFT (12U)
22895#define GPMI_CTRL1_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RDN_DELAY_SHIFT)) & GPMI_CTRL1_RDN_DELAY_MASK)
22896#define GPMI_CTRL1_HALF_PERIOD_MASK (0x10000U)
22897#define GPMI_CTRL1_HALF_PERIOD_SHIFT (16U)
22898#define GPMI_CTRL1_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_HALF_PERIOD_MASK)
22899#define GPMI_CTRL1_DLL_ENABLE_MASK (0x20000U)
22900#define GPMI_CTRL1_DLL_ENABLE_SHIFT (17U)
22901#define GPMI_CTRL1_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_DLL_ENABLE_MASK)
22902#define GPMI_CTRL1_BCH_MODE_MASK (0x40000U)
22903#define GPMI_CTRL1_BCH_MODE_SHIFT (18U)
22904#define GPMI_CTRL1_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BCH_MODE_SHIFT)) & GPMI_CTRL1_BCH_MODE_MASK)
22905#define GPMI_CTRL1_GANGED_RDYBUSY_MASK (0x80000U)
22906#define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT (19U)
22907#define GPMI_CTRL1_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_GANGED_RDYBUSY_MASK)
22908#define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK (0x100000U)
22909#define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT (20U)
22910#define GPMI_CTRL1_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK)
22911#define GPMI_CTRL1_TEST_TRIGGER_MASK (0x200000U)
22912#define GPMI_CTRL1_TEST_TRIGGER_SHIFT (21U)
22913/*! TEST_TRIGGER
22914 * 0b0..Disable
22915 * 0b1..Enable
22916 */
22917#define GPMI_CTRL1_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TEST_TRIGGER_MASK)
22918#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0xC00000U)
22919#define GPMI_CTRL1_WRN_DLY_SEL_SHIFT (22U)
22920#define GPMI_CTRL1_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_WRN_DLY_SEL_MASK)
22921#define GPMI_CTRL1_DECOUPLE_CS_MASK (0x1000000U)
22922#define GPMI_CTRL1_DECOUPLE_CS_SHIFT (24U)
22923#define GPMI_CTRL1_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_DECOUPLE_CS_MASK)
22924#define GPMI_CTRL1_SSYNCMODE_MASK (0x2000000U)
22925#define GPMI_CTRL1_SSYNCMODE_SHIFT (25U)
22926#define GPMI_CTRL1_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SSYNCMODE_MASK)
22927#define GPMI_CTRL1_UPDATE_CS_MASK (0x4000000U)
22928#define GPMI_CTRL1_UPDATE_CS_SHIFT (26U)
22929#define GPMI_CTRL1_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_UPDATE_CS_SHIFT)) & GPMI_CTRL1_UPDATE_CS_MASK)
22930#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK (0x8000000U)
22931#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT (27U)
22932/*! GPMI_CLK_DIV2_EN
22933 * 0b0..internal factor-2 clock divider is disabled
22934 * 0b1..internal factor-2 clock divider is enabled.
22935 */
22936#define GPMI_CTRL1_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK)
22937#define GPMI_CTRL1_TOGGLE_MODE_MASK (0x10000000U)
22938#define GPMI_CTRL1_TOGGLE_MODE_SHIFT (28U)
22939#define GPMI_CTRL1_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOGGLE_MODE_MASK)
22940#define GPMI_CTRL1_WRITE_CLK_STOP_MASK (0x20000000U)
22941#define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT (29U)
22942#define GPMI_CTRL1_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_WRITE_CLK_STOP_MASK)
22943#define GPMI_CTRL1_SSYNC_CLK_STOP_MASK (0x40000000U)
22944#define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT (30U)
22945#define GPMI_CTRL1_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SSYNC_CLK_STOP_MASK)
22946#define GPMI_CTRL1_DEV_CLK_STOP_MASK (0x80000000U)
22947#define GPMI_CTRL1_DEV_CLK_STOP_SHIFT (31U)
22948#define GPMI_CTRL1_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_DEV_CLK_STOP_MASK)
22949/*! @} */
22950
22951/*! @name CTRL1_SET - GPMI Control Register 1 Description */
22952/*! @{ */
22953#define GPMI_CTRL1_SET_GPMI_MODE_MASK (0x1U)
22954#define GPMI_CTRL1_SET_GPMI_MODE_SHIFT (0U)
22955/*! GPMI_MODE
22956 * 0b0..NAND mode.
22957 * 0b1..ATA mode.
22958 */
22959#define GPMI_CTRL1_SET_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_MODE_SHIFT)) & GPMI_CTRL1_SET_GPMI_MODE_MASK)
22960#define GPMI_CTRL1_SET_CAMERA_MODE_MASK (0x2U)
22961#define GPMI_CTRL1_SET_CAMERA_MODE_SHIFT (1U)
22962#define GPMI_CTRL1_SET_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_SET_CAMERA_MODE_MASK)
22963#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK (0x4U)
22964#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT (2U)
22965/*! ATA_IRQRDY_POLARITY
22966 * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
22967 * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
22968 */
22969#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK)
22970#define GPMI_CTRL1_SET_DEV_RESET_MASK (0x8U)
22971#define GPMI_CTRL1_SET_DEV_RESET_SHIFT (3U)
22972/*! DEV_RESET
22973 * 0b0..NANDF_WP_B pin is held low (asserted).
22974 * 0b1..NANDF_WP_B pin is held high (de-asserted).
22975 */
22976#define GPMI_CTRL1_SET_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_RESET_SHIFT)) & GPMI_CTRL1_SET_DEV_RESET_MASK)
22977#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
22978#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
22979#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
22980#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK (0x80U)
22981#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT (7U)
22982#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK)
22983#define GPMI_CTRL1_SET_BURST_EN_MASK (0x100U)
22984#define GPMI_CTRL1_SET_BURST_EN_SHIFT (8U)
22985#define GPMI_CTRL1_SET_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BURST_EN_SHIFT)) & GPMI_CTRL1_SET_BURST_EN_MASK)
22986#define GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK (0x200U)
22987#define GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT (9U)
22988#define GPMI_CTRL1_SET_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK)
22989#define GPMI_CTRL1_SET_DEV_IRQ_MASK (0x400U)
22990#define GPMI_CTRL1_SET_DEV_IRQ_SHIFT (10U)
22991#define GPMI_CTRL1_SET_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_IRQ_SHIFT)) & GPMI_CTRL1_SET_DEV_IRQ_MASK)
22992#define GPMI_CTRL1_SET_DMA2ECC_MODE_MASK (0x800U)
22993#define GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT (11U)
22994#define GPMI_CTRL1_SET_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_SET_DMA2ECC_MODE_MASK)
22995#define GPMI_CTRL1_SET_RDN_DELAY_MASK (0xF000U)
22996#define GPMI_CTRL1_SET_RDN_DELAY_SHIFT (12U)
22997#define GPMI_CTRL1_SET_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_RDN_DELAY_SHIFT)) & GPMI_CTRL1_SET_RDN_DELAY_MASK)
22998#define GPMI_CTRL1_SET_HALF_PERIOD_MASK (0x10000U)
22999#define GPMI_CTRL1_SET_HALF_PERIOD_SHIFT (16U)
23000#define GPMI_CTRL1_SET_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_SET_HALF_PERIOD_MASK)
23001#define GPMI_CTRL1_SET_DLL_ENABLE_MASK (0x20000U)
23002#define GPMI_CTRL1_SET_DLL_ENABLE_SHIFT (17U)
23003#define GPMI_CTRL1_SET_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_SET_DLL_ENABLE_MASK)
23004#define GPMI_CTRL1_SET_BCH_MODE_MASK (0x40000U)
23005#define GPMI_CTRL1_SET_BCH_MODE_SHIFT (18U)
23006#define GPMI_CTRL1_SET_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BCH_MODE_SHIFT)) & GPMI_CTRL1_SET_BCH_MODE_MASK)
23007#define GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK (0x80000U)
23008#define GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT (19U)
23009#define GPMI_CTRL1_SET_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK)
23010#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK (0x100000U)
23011#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT (20U)
23012#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK)
23013#define GPMI_CTRL1_SET_TEST_TRIGGER_MASK (0x200000U)
23014#define GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT (21U)
23015/*! TEST_TRIGGER
23016 * 0b0..Disable
23017 * 0b1..Enable
23018 */
23019#define GPMI_CTRL1_SET_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_SET_TEST_TRIGGER_MASK)
23020#define GPMI_CTRL1_SET_WRN_DLY_SEL_MASK (0xC00000U)
23021#define GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT (22U)
23022#define GPMI_CTRL1_SET_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_SET_WRN_DLY_SEL_MASK)
23023#define GPMI_CTRL1_SET_DECOUPLE_CS_MASK (0x1000000U)
23024#define GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT (24U)
23025#define GPMI_CTRL1_SET_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_SET_DECOUPLE_CS_MASK)
23026#define GPMI_CTRL1_SET_SSYNCMODE_MASK (0x2000000U)
23027#define GPMI_CTRL1_SET_SSYNCMODE_SHIFT (25U)
23028#define GPMI_CTRL1_SET_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SET_SSYNCMODE_MASK)
23029#define GPMI_CTRL1_SET_UPDATE_CS_MASK (0x4000000U)
23030#define GPMI_CTRL1_SET_UPDATE_CS_SHIFT (26U)
23031#define GPMI_CTRL1_SET_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_UPDATE_CS_SHIFT)) & GPMI_CTRL1_SET_UPDATE_CS_MASK)
23032#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK (0x8000000U)
23033#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT (27U)
23034/*! GPMI_CLK_DIV2_EN
23035 * 0b0..internal factor-2 clock divider is disabled
23036 * 0b1..internal factor-2 clock divider is enabled.
23037 */
23038#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK)
23039#define GPMI_CTRL1_SET_TOGGLE_MODE_MASK (0x10000000U)
23040#define GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT (28U)
23041#define GPMI_CTRL1_SET_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_SET_TOGGLE_MODE_MASK)
23042#define GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK (0x20000000U)
23043#define GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT (29U)
23044#define GPMI_CTRL1_SET_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK)
23045#define GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK (0x40000000U)
23046#define GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT (30U)
23047#define GPMI_CTRL1_SET_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK)
23048#define GPMI_CTRL1_SET_DEV_CLK_STOP_MASK (0x80000000U)
23049#define GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT (31U)
23050#define GPMI_CTRL1_SET_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_DEV_CLK_STOP_MASK)
23051/*! @} */
23052
23053/*! @name CTRL1_CLR - GPMI Control Register 1 Description */
23054/*! @{ */
23055#define GPMI_CTRL1_CLR_GPMI_MODE_MASK (0x1U)
23056#define GPMI_CTRL1_CLR_GPMI_MODE_SHIFT (0U)
23057/*! GPMI_MODE
23058 * 0b0..NAND mode.
23059 * 0b1..ATA mode.
23060 */
23061#define GPMI_CTRL1_CLR_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_MODE_SHIFT)) & GPMI_CTRL1_CLR_GPMI_MODE_MASK)
23062#define GPMI_CTRL1_CLR_CAMERA_MODE_MASK (0x2U)
23063#define GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT (1U)
23064#define GPMI_CTRL1_CLR_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CLR_CAMERA_MODE_MASK)
23065#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK (0x4U)
23066#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT (2U)
23067/*! ATA_IRQRDY_POLARITY
23068 * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
23069 * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
23070 */
23071#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK)
23072#define GPMI_CTRL1_CLR_DEV_RESET_MASK (0x8U)
23073#define GPMI_CTRL1_CLR_DEV_RESET_SHIFT (3U)
23074/*! DEV_RESET
23075 * 0b0..NANDF_WP_B pin is held low (asserted).
23076 * 0b1..NANDF_WP_B pin is held high (de-asserted).
23077 */
23078#define GPMI_CTRL1_CLR_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_RESET_SHIFT)) & GPMI_CTRL1_CLR_DEV_RESET_MASK)
23079#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
23080#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
23081#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
23082#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK (0x80U)
23083#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT (7U)
23084#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK)
23085#define GPMI_CTRL1_CLR_BURST_EN_MASK (0x100U)
23086#define GPMI_CTRL1_CLR_BURST_EN_SHIFT (8U)
23087#define GPMI_CTRL1_CLR_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BURST_EN_SHIFT)) & GPMI_CTRL1_CLR_BURST_EN_MASK)
23088#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK (0x200U)
23089#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT (9U)
23090#define GPMI_CTRL1_CLR_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK)
23091#define GPMI_CTRL1_CLR_DEV_IRQ_MASK (0x400U)
23092#define GPMI_CTRL1_CLR_DEV_IRQ_SHIFT (10U)
23093#define GPMI_CTRL1_CLR_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_IRQ_SHIFT)) & GPMI_CTRL1_CLR_DEV_IRQ_MASK)
23094#define GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK (0x800U)
23095#define GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT (11U)
23096#define GPMI_CTRL1_CLR_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK)
23097#define GPMI_CTRL1_CLR_RDN_DELAY_MASK (0xF000U)
23098#define GPMI_CTRL1_CLR_RDN_DELAY_SHIFT (12U)
23099#define GPMI_CTRL1_CLR_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_RDN_DELAY_SHIFT)) & GPMI_CTRL1_CLR_RDN_DELAY_MASK)
23100#define GPMI_CTRL1_CLR_HALF_PERIOD_MASK (0x10000U)
23101#define GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT (16U)
23102#define GPMI_CTRL1_CLR_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_CLR_HALF_PERIOD_MASK)
23103#define GPMI_CTRL1_CLR_DLL_ENABLE_MASK (0x20000U)
23104#define GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT (17U)
23105#define GPMI_CTRL1_CLR_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_CLR_DLL_ENABLE_MASK)
23106#define GPMI_CTRL1_CLR_BCH_MODE_MASK (0x40000U)
23107#define GPMI_CTRL1_CLR_BCH_MODE_SHIFT (18U)
23108#define GPMI_CTRL1_CLR_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BCH_MODE_SHIFT)) & GPMI_CTRL1_CLR_BCH_MODE_MASK)
23109#define GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK (0x80000U)
23110#define GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT (19U)
23111#define GPMI_CTRL1_CLR_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK)
23112#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK (0x100000U)
23113#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT (20U)
23114#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK)
23115#define GPMI_CTRL1_CLR_TEST_TRIGGER_MASK (0x200000U)
23116#define GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT (21U)
23117/*! TEST_TRIGGER
23118 * 0b0..Disable
23119 * 0b1..Enable
23120 */
23121#define GPMI_CTRL1_CLR_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_CLR_TEST_TRIGGER_MASK)
23122#define GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK (0xC00000U)
23123#define GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT (22U)
23124#define GPMI_CTRL1_CLR_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK)
23125#define GPMI_CTRL1_CLR_DECOUPLE_CS_MASK (0x1000000U)
23126#define GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT (24U)
23127#define GPMI_CTRL1_CLR_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_CLR_DECOUPLE_CS_MASK)
23128#define GPMI_CTRL1_CLR_SSYNCMODE_MASK (0x2000000U)
23129#define GPMI_CTRL1_CLR_SSYNCMODE_SHIFT (25U)
23130#define GPMI_CTRL1_CLR_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNCMODE_SHIFT)) & GPMI_CTRL1_CLR_SSYNCMODE_MASK)
23131#define GPMI_CTRL1_CLR_UPDATE_CS_MASK (0x4000000U)
23132#define GPMI_CTRL1_CLR_UPDATE_CS_SHIFT (26U)
23133#define GPMI_CTRL1_CLR_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_UPDATE_CS_SHIFT)) & GPMI_CTRL1_CLR_UPDATE_CS_MASK)
23134#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK (0x8000000U)
23135#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT (27U)
23136/*! GPMI_CLK_DIV2_EN
23137 * 0b0..internal factor-2 clock divider is disabled
23138 * 0b1..internal factor-2 clock divider is enabled.
23139 */
23140#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK)
23141#define GPMI_CTRL1_CLR_TOGGLE_MODE_MASK (0x10000000U)
23142#define GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT (28U)
23143#define GPMI_CTRL1_CLR_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_CLR_TOGGLE_MODE_MASK)
23144#define GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK (0x20000000U)
23145#define GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT (29U)
23146#define GPMI_CTRL1_CLR_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK)
23147#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK (0x40000000U)
23148#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT (30U)
23149#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK)
23150#define GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK (0x80000000U)
23151#define GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT (31U)
23152#define GPMI_CTRL1_CLR_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK)
23153/*! @} */
23154
23155/*! @name CTRL1_TOG - GPMI Control Register 1 Description */
23156/*! @{ */
23157#define GPMI_CTRL1_TOG_GPMI_MODE_MASK (0x1U)
23158#define GPMI_CTRL1_TOG_GPMI_MODE_SHIFT (0U)
23159/*! GPMI_MODE
23160 * 0b0..NAND mode.
23161 * 0b1..ATA mode.
23162 */
23163#define GPMI_CTRL1_TOG_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_MODE_SHIFT)) & GPMI_CTRL1_TOG_GPMI_MODE_MASK)
23164#define GPMI_CTRL1_TOG_CAMERA_MODE_MASK (0x2U)
23165#define GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT (1U)
23166#define GPMI_CTRL1_TOG_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_TOG_CAMERA_MODE_MASK)
23167#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK (0x4U)
23168#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT (2U)
23169/*! ATA_IRQRDY_POLARITY
23170 * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
23171 * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
23172 */
23173#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK)
23174#define GPMI_CTRL1_TOG_DEV_RESET_MASK (0x8U)
23175#define GPMI_CTRL1_TOG_DEV_RESET_SHIFT (3U)
23176/*! DEV_RESET
23177 * 0b0..NANDF_WP_B pin is held low (asserted).
23178 * 0b1..NANDF_WP_B pin is held high (de-asserted).
23179 */
23180#define GPMI_CTRL1_TOG_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_RESET_SHIFT)) & GPMI_CTRL1_TOG_DEV_RESET_MASK)
23181#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
23182#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
23183#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
23184#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK (0x80U)
23185#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT (7U)
23186#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK)
23187#define GPMI_CTRL1_TOG_BURST_EN_MASK (0x100U)
23188#define GPMI_CTRL1_TOG_BURST_EN_SHIFT (8U)
23189#define GPMI_CTRL1_TOG_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BURST_EN_SHIFT)) & GPMI_CTRL1_TOG_BURST_EN_MASK)
23190#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK (0x200U)
23191#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT (9U)
23192#define GPMI_CTRL1_TOG_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK)
23193#define GPMI_CTRL1_TOG_DEV_IRQ_MASK (0x400U)
23194#define GPMI_CTRL1_TOG_DEV_IRQ_SHIFT (10U)
23195#define GPMI_CTRL1_TOG_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_IRQ_SHIFT)) & GPMI_CTRL1_TOG_DEV_IRQ_MASK)
23196#define GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK (0x800U)
23197#define GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT (11U)
23198#define GPMI_CTRL1_TOG_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK)
23199#define GPMI_CTRL1_TOG_RDN_DELAY_MASK (0xF000U)
23200#define GPMI_CTRL1_TOG_RDN_DELAY_SHIFT (12U)
23201#define GPMI_CTRL1_TOG_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_RDN_DELAY_SHIFT)) & GPMI_CTRL1_TOG_RDN_DELAY_MASK)
23202#define GPMI_CTRL1_TOG_HALF_PERIOD_MASK (0x10000U)
23203#define GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT (16U)
23204#define GPMI_CTRL1_TOG_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_TOG_HALF_PERIOD_MASK)
23205#define GPMI_CTRL1_TOG_DLL_ENABLE_MASK (0x20000U)
23206#define GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT (17U)
23207#define GPMI_CTRL1_TOG_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_TOG_DLL_ENABLE_MASK)
23208#define GPMI_CTRL1_TOG_BCH_MODE_MASK (0x40000U)
23209#define GPMI_CTRL1_TOG_BCH_MODE_SHIFT (18U)
23210#define GPMI_CTRL1_TOG_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BCH_MODE_SHIFT)) & GPMI_CTRL1_TOG_BCH_MODE_MASK)
23211#define GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK (0x80000U)
23212#define GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT (19U)
23213#define GPMI_CTRL1_TOG_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK)
23214#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK (0x100000U)
23215#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT (20U)
23216#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK)
23217#define GPMI_CTRL1_TOG_TEST_TRIGGER_MASK (0x200000U)
23218#define GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT (21U)
23219/*! TEST_TRIGGER
23220 * 0b0..Disable
23221 * 0b1..Enable
23222 */
23223#define GPMI_CTRL1_TOG_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TOG_TEST_TRIGGER_MASK)
23224#define GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK (0xC00000U)
23225#define GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT (22U)
23226#define GPMI_CTRL1_TOG_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK)
23227#define GPMI_CTRL1_TOG_DECOUPLE_CS_MASK (0x1000000U)
23228#define GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT (24U)
23229#define GPMI_CTRL1_TOG_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_TOG_DECOUPLE_CS_MASK)
23230#define GPMI_CTRL1_TOG_SSYNCMODE_MASK (0x2000000U)
23231#define GPMI_CTRL1_TOG_SSYNCMODE_SHIFT (25U)
23232#define GPMI_CTRL1_TOG_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNCMODE_SHIFT)) & GPMI_CTRL1_TOG_SSYNCMODE_MASK)
23233#define GPMI_CTRL1_TOG_UPDATE_CS_MASK (0x4000000U)
23234#define GPMI_CTRL1_TOG_UPDATE_CS_SHIFT (26U)
23235#define GPMI_CTRL1_TOG_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_UPDATE_CS_SHIFT)) & GPMI_CTRL1_TOG_UPDATE_CS_MASK)
23236#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK (0x8000000U)
23237#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT (27U)
23238/*! GPMI_CLK_DIV2_EN
23239 * 0b0..internal factor-2 clock divider is disabled
23240 * 0b1..internal factor-2 clock divider is enabled.
23241 */
23242#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK)
23243#define GPMI_CTRL1_TOG_TOGGLE_MODE_MASK (0x10000000U)
23244#define GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT (28U)
23245#define GPMI_CTRL1_TOG_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOG_TOGGLE_MODE_MASK)
23246#define GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK (0x20000000U)
23247#define GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT (29U)
23248#define GPMI_CTRL1_TOG_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK)
23249#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK (0x40000000U)
23250#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT (30U)
23251#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK)
23252#define GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK (0x80000000U)
23253#define GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT (31U)
23254#define GPMI_CTRL1_TOG_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK)
23255/*! @} */
23256
23257/*! @name TIMING0 - GPMI Timing Register 0 Description */
23258/*! @{ */
23259#define GPMI_TIMING0_DATA_SETUP_MASK (0xFFU)
23260#define GPMI_TIMING0_DATA_SETUP_SHIFT (0U)
23261#define GPMI_TIMING0_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_SETUP_SHIFT)) & GPMI_TIMING0_DATA_SETUP_MASK)
23262#define GPMI_TIMING0_DATA_HOLD_MASK (0xFF00U)
23263#define GPMI_TIMING0_DATA_HOLD_SHIFT (8U)
23264#define GPMI_TIMING0_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_HOLD_SHIFT)) & GPMI_TIMING0_DATA_HOLD_MASK)
23265#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xFF0000U)
23266#define GPMI_TIMING0_ADDRESS_SETUP_SHIFT (16U)
23267#define GPMI_TIMING0_ADDRESS_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_ADDRESS_SETUP_SHIFT)) & GPMI_TIMING0_ADDRESS_SETUP_MASK)
23268#define GPMI_TIMING0_RSVD1_MASK (0xFF000000U)
23269#define GPMI_TIMING0_RSVD1_SHIFT (24U)
23270#define GPMI_TIMING0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_RSVD1_SHIFT)) & GPMI_TIMING0_RSVD1_MASK)
23271/*! @} */
23272
23273/*! @name TIMING1 - GPMI Timing Register 1 Description */
23274/*! @{ */
23275#define GPMI_TIMING1_RSVD1_MASK (0xFFFFU)
23276#define GPMI_TIMING1_RSVD1_SHIFT (0U)
23277#define GPMI_TIMING1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_RSVD1_SHIFT)) & GPMI_TIMING1_RSVD1_MASK)
23278#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xFFFF0000U)
23279#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT (16U)
23280#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT)) & GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK)
23281/*! @} */
23282
23283/*! @name TIMING2 - GPMI Timing Register 2 Description */
23284/*! @{ */
23285#define GPMI_TIMING2_DATA_PAUSE_MASK (0xFU)
23286#define GPMI_TIMING2_DATA_PAUSE_SHIFT (0U)
23287#define GPMI_TIMING2_DATA_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_DATA_PAUSE_SHIFT)) & GPMI_TIMING2_DATA_PAUSE_MASK)
23288#define GPMI_TIMING2_CMDADD_PAUSE_MASK (0xF0U)
23289#define GPMI_TIMING2_CMDADD_PAUSE_SHIFT (4U)
23290#define GPMI_TIMING2_CMDADD_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CMDADD_PAUSE_SHIFT)) & GPMI_TIMING2_CMDADD_PAUSE_MASK)
23291#define GPMI_TIMING2_POSTAMBLE_DELAY_MASK (0xF00U)
23292#define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT (8U)
23293#define GPMI_TIMING2_POSTAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_POSTAMBLE_DELAY_MASK)
23294#define GPMI_TIMING2_PREAMBLE_DELAY_MASK (0xF000U)
23295#define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT (12U)
23296#define GPMI_TIMING2_PREAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_PREAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_PREAMBLE_DELAY_MASK)
23297#define GPMI_TIMING2_CE_DELAY_MASK (0x1F0000U)
23298#define GPMI_TIMING2_CE_DELAY_SHIFT (16U)
23299#define GPMI_TIMING2_CE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CE_DELAY_SHIFT)) & GPMI_TIMING2_CE_DELAY_MASK)
23300#define GPMI_TIMING2_RSVD0_MASK (0xE00000U)
23301#define GPMI_TIMING2_RSVD0_SHIFT (21U)
23302#define GPMI_TIMING2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_RSVD0_SHIFT)) & GPMI_TIMING2_RSVD0_MASK)
23303#define GPMI_TIMING2_READ_LATENCY_MASK (0x7000000U)
23304#define GPMI_TIMING2_READ_LATENCY_SHIFT (24U)
23305/*! READ_LATENCY
23306 * 0b000..READ LATENCY is 0
23307 * 0b001..READ LATENCY is 1
23308 * 0b010..READ LATENCY is 2
23309 * 0b011..READ LATENCY is 3
23310 * 0b100..READ LATENCY is 4
23311 * 0b101..READ LATENCY is 5
23312 */
23313#define GPMI_TIMING2_READ_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_READ_LATENCY_SHIFT)) & GPMI_TIMING2_READ_LATENCY_MASK)
23314#define GPMI_TIMING2_TCR_MASK (0x18000000U)
23315#define GPMI_TIMING2_TCR_SHIFT (27U)
23316#define GPMI_TIMING2_TCR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TCR_SHIFT)) & GPMI_TIMING2_TCR_MASK)
23317#define GPMI_TIMING2_TRPSTH_MASK (0xE0000000U)
23318#define GPMI_TIMING2_TRPSTH_SHIFT (29U)
23319#define GPMI_TIMING2_TRPSTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TRPSTH_SHIFT)) & GPMI_TIMING2_TRPSTH_MASK)
23320/*! @} */
23321
23322/*! @name DATA - GPMI DMA Data Transfer Register Description */
23323/*! @{ */
23324#define GPMI_DATA_DATA_MASK (0xFFFFFFFFU)
23325#define GPMI_DATA_DATA_SHIFT (0U)
23326#define GPMI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DATA_DATA_SHIFT)) & GPMI_DATA_DATA_MASK)
23327/*! @} */
23328
23329/*! @name STAT - GPMI Status Register Description */
23330/*! @{ */
23331#define GPMI_STAT_PRESENT_MASK (0x1U)
23332#define GPMI_STAT_PRESENT_SHIFT (0U)
23333/*! PRESENT
23334 * 0b0..GPMI is not present in this product.
23335 * 0b1..GPMI is present is in this product.
23336 */
23337#define GPMI_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_PRESENT_SHIFT)) & GPMI_STAT_PRESENT_MASK)
23338#define GPMI_STAT_FIFO_FULL_MASK (0x2U)
23339#define GPMI_STAT_FIFO_FULL_SHIFT (1U)
23340/*! FIFO_FULL
23341 * 0b0..FIFO is not full.
23342 * 0b1..FIFO is full.
23343 */
23344#define GPMI_STAT_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_FULL_SHIFT)) & GPMI_STAT_FIFO_FULL_MASK)
23345#define GPMI_STAT_FIFO_EMPTY_MASK (0x4U)
23346#define GPMI_STAT_FIFO_EMPTY_SHIFT (2U)
23347/*! FIFO_EMPTY
23348 * 0b0..FIFO is not empty.
23349 * 0b1..FIFO is empty.
23350 */
23351#define GPMI_STAT_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_EMPTY_SHIFT)) & GPMI_STAT_FIFO_EMPTY_MASK)
23352#define GPMI_STAT_INVALID_BUFFER_MASK_MASK (0x8U)
23353#define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT (3U)
23354/*! INVALID_BUFFER_MASK
23355 * 0b0..ECC Buffer Mask is not invalid.
23356 * 0b1..ECC Buffer Mask is invalid.
23357 */
23358#define GPMI_STAT_INVALID_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_INVALID_BUFFER_MASK_SHIFT)) & GPMI_STAT_INVALID_BUFFER_MASK_MASK)
23359#define GPMI_STAT_ATA_IRQ_MASK (0x10U)
23360#define GPMI_STAT_ATA_IRQ_SHIFT (4U)
23361#define GPMI_STAT_ATA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_ATA_IRQ_SHIFT)) & GPMI_STAT_ATA_IRQ_MASK)
23362#define GPMI_STAT_RSVD1_MASK (0xE0U)
23363#define GPMI_STAT_RSVD1_SHIFT (5U)
23364#define GPMI_STAT_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RSVD1_SHIFT)) & GPMI_STAT_RSVD1_MASK)
23365#define GPMI_STAT_DEV0_ERROR_MASK (0x100U)
23366#define GPMI_STAT_DEV0_ERROR_SHIFT (8U)
23367/*! DEV0_ERROR
23368 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 0.
23369 * 0b1..An Error has occurred on ATA/NAND Device accessed by
23370 */
23371#define GPMI_STAT_DEV0_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV0_ERROR_SHIFT)) & GPMI_STAT_DEV0_ERROR_MASK)
23372#define GPMI_STAT_DEV1_ERROR_MASK (0x200U)
23373#define GPMI_STAT_DEV1_ERROR_SHIFT (9U)
23374/*! DEV1_ERROR
23375 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 1.
23376 * 0b1..An Error has occurred on ATA/NAND Device accessed by
23377 */
23378#define GPMI_STAT_DEV1_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV1_ERROR_SHIFT)) & GPMI_STAT_DEV1_ERROR_MASK)
23379#define GPMI_STAT_DEV2_ERROR_MASK (0x400U)
23380#define GPMI_STAT_DEV2_ERROR_SHIFT (10U)
23381/*! DEV2_ERROR
23382 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 2.
23383 * 0b1..An Error has occurred on ATA/NAND Device accessed by
23384 */
23385#define GPMI_STAT_DEV2_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV2_ERROR_SHIFT)) & GPMI_STAT_DEV2_ERROR_MASK)
23386#define GPMI_STAT_DEV3_ERROR_MASK (0x800U)
23387#define GPMI_STAT_DEV3_ERROR_SHIFT (11U)
23388/*! DEV3_ERROR
23389 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 3.
23390 * 0b1..An Error has occurred on ATA/NAND Device accessed by
23391 */
23392#define GPMI_STAT_DEV3_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV3_ERROR_SHIFT)) & GPMI_STAT_DEV3_ERROR_MASK)
23393#define GPMI_STAT_DEV4_ERROR_MASK (0x1000U)
23394#define GPMI_STAT_DEV4_ERROR_SHIFT (12U)
23395/*! DEV4_ERROR
23396 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 4.
23397 * 0b1..An Error has occurred on ATA/NAND Device accessed by
23398 */
23399#define GPMI_STAT_DEV4_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV4_ERROR_SHIFT)) & GPMI_STAT_DEV4_ERROR_MASK)
23400#define GPMI_STAT_DEV5_ERROR_MASK (0x2000U)
23401#define GPMI_STAT_DEV5_ERROR_SHIFT (13U)
23402/*! DEV5_ERROR
23403 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 5.
23404 * 0b1..An Error has occurred on ATA/NAND Device accessed by
23405 */
23406#define GPMI_STAT_DEV5_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV5_ERROR_SHIFT)) & GPMI_STAT_DEV5_ERROR_MASK)
23407#define GPMI_STAT_DEV6_ERROR_MASK (0x4000U)
23408#define GPMI_STAT_DEV6_ERROR_SHIFT (14U)
23409/*! DEV6_ERROR
23410 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 6.
23411 * 0b1..An Error has occurred on ATA/NAND Device accessed by
23412 */
23413#define GPMI_STAT_DEV6_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV6_ERROR_SHIFT)) & GPMI_STAT_DEV6_ERROR_MASK)
23414#define GPMI_STAT_DEV7_ERROR_MASK (0x8000U)
23415#define GPMI_STAT_DEV7_ERROR_SHIFT (15U)
23416/*! DEV7_ERROR
23417 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 7.
23418 * 0b1..An Error has occurred on ATA/NAND Device accessed by
23419 */
23420#define GPMI_STAT_DEV7_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV7_ERROR_SHIFT)) & GPMI_STAT_DEV7_ERROR_MASK)
23421#define GPMI_STAT_RDY_TIMEOUT_MASK (0xFF0000U)
23422#define GPMI_STAT_RDY_TIMEOUT_SHIFT (16U)
23423#define GPMI_STAT_RDY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RDY_TIMEOUT_SHIFT)) & GPMI_STAT_RDY_TIMEOUT_MASK)
23424#define GPMI_STAT_READY_BUSY_MASK (0xFF000000U)
23425#define GPMI_STAT_READY_BUSY_SHIFT (24U)
23426#define GPMI_STAT_READY_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_READY_BUSY_SHIFT)) & GPMI_STAT_READY_BUSY_MASK)
23427/*! @} */
23428
23429/*! @name DEBUG - GPMI Debug Information Register Description */
23430/*! @{ */
23431#define GPMI_DEBUG_CMD_END_MASK (0xFFU)
23432#define GPMI_DEBUG_CMD_END_SHIFT (0U)
23433#define GPMI_DEBUG_CMD_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_CMD_END_SHIFT)) & GPMI_DEBUG_CMD_END_MASK)
23434#define GPMI_DEBUG_DMAREQ_MASK (0xFF00U)
23435#define GPMI_DEBUG_DMAREQ_SHIFT (8U)
23436#define GPMI_DEBUG_DMAREQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMAREQ_SHIFT)) & GPMI_DEBUG_DMAREQ_MASK)
23437#define GPMI_DEBUG_DMA_SENSE_MASK (0xFF0000U)
23438#define GPMI_DEBUG_DMA_SENSE_SHIFT (16U)
23439#define GPMI_DEBUG_DMA_SENSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMA_SENSE_SHIFT)) & GPMI_DEBUG_DMA_SENSE_MASK)
23440#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xFF000000U)
23441#define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT (24U)
23442#define GPMI_DEBUG_WAIT_FOR_READY_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT)) & GPMI_DEBUG_WAIT_FOR_READY_END_MASK)
23443/*! @} */
23444
23445/*! @name VERSION - GPMI Version Register Description */
23446/*! @{ */
23447#define GPMI_VERSION_STEP_MASK (0xFFFFU)
23448#define GPMI_VERSION_STEP_SHIFT (0U)
23449#define GPMI_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_STEP_SHIFT)) & GPMI_VERSION_STEP_MASK)
23450#define GPMI_VERSION_MINOR_MASK (0xFF0000U)
23451#define GPMI_VERSION_MINOR_SHIFT (16U)
23452#define GPMI_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MINOR_SHIFT)) & GPMI_VERSION_MINOR_MASK)
23453#define GPMI_VERSION_MAJOR_MASK (0xFF000000U)
23454#define GPMI_VERSION_MAJOR_SHIFT (24U)
23455#define GPMI_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MAJOR_SHIFT)) & GPMI_VERSION_MAJOR_MASK)
23456/*! @} */
23457
23458/*! @name DEBUG2 - GPMI Debug2 Information Register Description */
23459/*! @{ */
23460#define GPMI_DEBUG2_RDN_TAP_MASK (0x3FU)
23461#define GPMI_DEBUG2_RDN_TAP_SHIFT (0U)
23462#define GPMI_DEBUG2_RDN_TAP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RDN_TAP_SHIFT)) & GPMI_DEBUG2_RDN_TAP_MASK)
23463#define GPMI_DEBUG2_UPDATE_WINDOW_MASK (0x40U)
23464#define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT (6U)
23465#define GPMI_DEBUG2_UPDATE_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UPDATE_WINDOW_SHIFT)) & GPMI_DEBUG2_UPDATE_WINDOW_MASK)
23466#define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK (0x80U)
23467#define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT (7U)
23468#define GPMI_DEBUG2_VIEW_DELAYED_RDN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT)) & GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK)
23469#define GPMI_DEBUG2_SYND2GPMI_READY_MASK (0x100U)
23470#define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT (8U)
23471#define GPMI_DEBUG2_SYND2GPMI_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_READY_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_READY_MASK)
23472#define GPMI_DEBUG2_SYND2GPMI_VALID_MASK (0x200U)
23473#define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT (9U)
23474#define GPMI_DEBUG2_SYND2GPMI_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_VALID_MASK)
23475#define GPMI_DEBUG2_GPMI2SYND_READY_MASK (0x400U)
23476#define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT (10U)
23477#define GPMI_DEBUG2_GPMI2SYND_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_READY_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_READY_MASK)
23478#define GPMI_DEBUG2_GPMI2SYND_VALID_MASK (0x800U)
23479#define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT (11U)
23480#define GPMI_DEBUG2_GPMI2SYND_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_VALID_MASK)
23481#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xF000U)
23482#define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT (12U)
23483#define GPMI_DEBUG2_SYND2GPMI_BE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_BE_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_BE_MASK)
23484#define GPMI_DEBUG2_MAIN_STATE_MASK (0xF0000U)
23485#define GPMI_DEBUG2_MAIN_STATE_SHIFT (16U)
23486#define GPMI_DEBUG2_MAIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_MAIN_STATE_SHIFT)) & GPMI_DEBUG2_MAIN_STATE_MASK)
23487#define GPMI_DEBUG2_PIN_STATE_MASK (0x700000U)
23488#define GPMI_DEBUG2_PIN_STATE_SHIFT (20U)
23489#define GPMI_DEBUG2_PIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_PIN_STATE_SHIFT)) & GPMI_DEBUG2_PIN_STATE_MASK)
23490#define GPMI_DEBUG2_BUSY_MASK (0x800000U)
23491#define GPMI_DEBUG2_BUSY_SHIFT (23U)
23492#define GPMI_DEBUG2_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_BUSY_SHIFT)) & GPMI_DEBUG2_BUSY_MASK)
23493#define GPMI_DEBUG2_UDMA_STATE_MASK (0xF000000U)
23494#define GPMI_DEBUG2_UDMA_STATE_SHIFT (24U)
23495#define GPMI_DEBUG2_UDMA_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UDMA_STATE_SHIFT)) & GPMI_DEBUG2_UDMA_STATE_MASK)
23496#define GPMI_DEBUG2_RSVD1_MASK (0xF0000000U)
23497#define GPMI_DEBUG2_RSVD1_SHIFT (28U)
23498#define GPMI_DEBUG2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RSVD1_SHIFT)) & GPMI_DEBUG2_RSVD1_MASK)
23499/*! @} */
23500
23501/*! @name DEBUG3 - GPMI Debug3 Information Register Description */
23502/*! @{ */
23503#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK (0xFFFFU)
23504#define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT (0U)
23505#define GPMI_DEBUG3_DEV_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_DEV_WORD_CNTR_MASK)
23506#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xFFFF0000U)
23507#define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT (16U)
23508#define GPMI_DEBUG3_APB_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_APB_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_APB_WORD_CNTR_MASK)
23509/*! @} */
23510
23511/*! @name READ_DDR_DLL_CTRL - GPMI Double Rate Read DLL Control Register Description */
23512/*! @{ */
23513#define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK (0x1U)
23514#define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT (0U)
23515#define GPMI_READ_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK)
23516#define GPMI_READ_DDR_DLL_CTRL_RESET_MASK (0x2U)
23517#define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT (1U)
23518#define GPMI_READ_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RESET_MASK)
23519#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
23520#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
23521#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK)
23522#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
23523#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
23524#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK)
23525#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
23526#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
23527#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK)
23528#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U)
23529#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U)
23530#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK)
23531#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U)
23532#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U)
23533#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK)
23534#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U)
23535#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U)
23536#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
23537#define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U)
23538#define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT (18U)
23539#define GPMI_READ_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK)
23540#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
23541#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
23542#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK)
23543#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
23544#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
23545#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK)
23546/*! @} */
23547
23548/*! @name WRITE_DDR_DLL_CTRL - GPMI Double Rate Write DLL Control Register Description */
23549/*! @{ */
23550#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK (0x1U)
23551#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT (0U)
23552#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK)
23553#define GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK (0x2U)
23554#define GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT (1U)
23555#define GPMI_WRITE_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK)
23556#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
23557#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
23558#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK)
23559#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
23560#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
23561#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK)
23562#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
23563#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
23564#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK)
23565#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U)
23566#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U)
23567#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK)
23568#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U)
23569#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U)
23570#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK)
23571#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U)
23572#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U)
23573#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
23574#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U)
23575#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT (18U)
23576#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK)
23577#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
23578#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
23579#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK)
23580#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
23581#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
23582#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK)
23583/*! @} */
23584
23585/*! @name READ_DDR_DLL_STS - GPMI Double Rate Read DLL Status Register Description */
23586/*! @{ */
23587#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK (0x1U)
23588#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT (0U)
23589#define GPMI_READ_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK)
23590#define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU)
23591#define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT (1U)
23592#define GPMI_READ_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK)
23593#define GPMI_READ_DDR_DLL_STS_RSVD0_MASK (0xFE00U)
23594#define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT (9U)
23595#define GPMI_READ_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD0_MASK)
23596#define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK (0x10000U)
23597#define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT (16U)
23598#define GPMI_READ_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK)
23599#define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U)
23600#define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT (17U)
23601#define GPMI_READ_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_SEL_MASK)
23602#define GPMI_READ_DDR_DLL_STS_RSVD1_MASK (0xFE000000U)
23603#define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT (25U)
23604#define GPMI_READ_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD1_MASK)
23605/*! @} */
23606
23607/*! @name WRITE_DDR_DLL_STS - GPMI Double Rate Write DLL Status Register Description */
23608/*! @{ */
23609#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK (0x1U)
23610#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT (0U)
23611#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK)
23612#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU)
23613#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT (1U)
23614#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK)
23615#define GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK (0xFE00U)
23616#define GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT (9U)
23617#define GPMI_WRITE_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK)
23618#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK (0x10000U)
23619#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT (16U)
23620#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK)
23621#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U)
23622#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT (17U)
23623#define GPMI_WRITE_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK)
23624#define GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK (0xFE000000U)
23625#define GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT (25U)
23626#define GPMI_WRITE_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK)
23627/*! @} */
23628
23629
23630/*!
23631 * @}
23632 */ /* end of group GPMI_Register_Masks */
23633
23634
23635/* GPMI - Peripheral instance base addresses */
23636/** Peripheral GPMI base address */
23637#define GPMI_BASE (0x33002000u)
23638/** Peripheral GPMI base pointer */
23639#define GPMI ((GPMI_Type *)GPMI_BASE)
23640/** Array initializer of GPMI peripheral base addresses */
23641#define GPMI_BASE_ADDRS { GPMI_BASE }
23642/** Array initializer of GPMI peripheral base pointers */
23643#define GPMI_BASE_PTRS { GPMI }
23644/** Interrupt vectors for the GPMI peripheral type */
23645#define GPMI_IRQS { GPMI_IRQn }
23646
23647/*!
23648 * @}
23649 */ /* end of group GPMI_Peripheral_Access_Layer */
23650
23651
23652/* ----------------------------------------------------------------------------
23653 -- GPT Peripheral Access Layer
23654 ---------------------------------------------------------------------------- */
23655
23656/*!
23657 * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
23658 * @{
23659 */
23660
23661/** GPT - Register Layout Typedef */
23662typedef struct {
23663 __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */
23664 __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */
23665 __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */
23666 __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */
23667 __IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */
23668 __I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */
23669 __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */
23670} GPT_Type;
23671
23672/* ----------------------------------------------------------------------------
23673 -- GPT Register Masks
23674 ---------------------------------------------------------------------------- */
23675
23676/*!
23677 * @addtogroup GPT_Register_Masks GPT Register Masks
23678 * @{
23679 */
23680
23681/*! @name CR - GPT Control Register */
23682/*! @{ */
23683#define GPT_CR_EN_MASK (0x1U)
23684#define GPT_CR_EN_SHIFT (0U)
23685/*! EN
23686 * 0b0..GPT is disabled.
23687 * 0b1..GPT is enabled.
23688 */
23689#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
23690#define GPT_CR_ENMOD_MASK (0x2U)
23691#define GPT_CR_ENMOD_SHIFT (1U)
23692/*! ENMOD
23693 * 0b0..GPT counter will retain its value when it is disabled.
23694 * 0b1..GPT counter value is reset to 0 when it is disabled.
23695 */
23696#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
23697#define GPT_CR_DBGEN_MASK (0x4U)
23698#define GPT_CR_DBGEN_SHIFT (2U)
23699/*! DBGEN
23700 * 0b0..GPT is disabled in debug mode.
23701 * 0b1..GPT is enabled in debug mode.
23702 */
23703#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
23704#define GPT_CR_WAITEN_MASK (0x8U)
23705#define GPT_CR_WAITEN_SHIFT (3U)
23706/*! WAITEN
23707 * 0b0..GPT is disabled in wait mode.
23708 * 0b1..GPT is enabled in wait mode.
23709 */
23710#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
23711#define GPT_CR_DOZEEN_MASK (0x10U)
23712#define GPT_CR_DOZEEN_SHIFT (4U)
23713/*! DOZEEN
23714 * 0b0..GPT is disabled in doze mode.
23715 * 0b1..GPT is enabled in doze mode.
23716 */
23717#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
23718#define GPT_CR_STOPEN_MASK (0x20U)
23719#define GPT_CR_STOPEN_SHIFT (5U)
23720/*! STOPEN
23721 * 0b0..GPT is disabled in Stop mode.
23722 * 0b1..GPT is enabled in Stop mode.
23723 */
23724#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
23725#define GPT_CR_CLKSRC_MASK (0x1C0U)
23726#define GPT_CR_CLKSRC_SHIFT (6U)
23727/*! CLKSRC
23728 * 0b000..No clock
23729 * 0b001..Peripheral Clock (ipg_clk)
23730 * 0b010..High Frequency Reference Clock (ipg_clk_highfreq)
23731 * 0b011..External Clock
23732 * 0b100..Low Frequency Reference Clock (ipg_clk_32k)
23733 * 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M)
23734 */
23735#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
23736#define GPT_CR_FRR_MASK (0x200U)
23737#define GPT_CR_FRR_SHIFT (9U)
23738/*! FRR
23739 * 0b0..Restart mode
23740 * 0b1..Free-Run mode
23741 */
23742#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
23743#define GPT_CR_EN_24M_MASK (0x400U)
23744#define GPT_CR_EN_24M_SHIFT (10U)
23745/*! EN_24M
23746 * 0b0..24M clock disabled
23747 * 0b1..24M clock enabled
23748 */
23749#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
23750#define GPT_CR_SWR_MASK (0x8000U)
23751#define GPT_CR_SWR_SHIFT (15U)
23752/*! SWR
23753 * 0b0..GPT is not in reset state
23754 * 0b1..GPT is in reset state
23755 */
23756#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
23757#define GPT_CR_IM1_MASK (0x30000U)
23758#define GPT_CR_IM1_SHIFT (16U)
23759#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
23760#define GPT_CR_IM2_MASK (0xC0000U)
23761#define GPT_CR_IM2_SHIFT (18U)
23762/*! IM2
23763 * 0b00..capture disabled
23764 * 0b01..capture on rising edge only
23765 * 0b10..capture on falling edge only
23766 * 0b11..capture on both edges
23767 */
23768#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
23769#define GPT_CR_OM1_MASK (0x700000U)
23770#define GPT_CR_OM1_SHIFT (20U)
23771#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
23772#define GPT_CR_OM2_MASK (0x3800000U)
23773#define GPT_CR_OM2_SHIFT (23U)
23774#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
23775#define GPT_CR_OM3_MASK (0x1C000000U)
23776#define GPT_CR_OM3_SHIFT (26U)
23777/*! OM3
23778 * 0b000..Output disconnected. No response on pin.
23779 * 0b001..Toggle output pin
23780 * 0b010..Clear output pin
23781 * 0b011..Set output pin
23782 * 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin.
23783 */
23784#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
23785#define GPT_CR_FO1_MASK (0x20000000U)
23786#define GPT_CR_FO1_SHIFT (29U)
23787#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
23788#define GPT_CR_FO2_MASK (0x40000000U)
23789#define GPT_CR_FO2_SHIFT (30U)
23790#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
23791#define GPT_CR_FO3_MASK (0x80000000U)
23792#define GPT_CR_FO3_SHIFT (31U)
23793/*! FO3
23794 * 0b0..Writing a 0 has no effect.
23795 * 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set.
23796 */
23797#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
23798/*! @} */
23799
23800/*! @name PR - GPT Prescaler Register */
23801/*! @{ */
23802#define GPT_PR_PRESCALER_MASK (0xFFFU)
23803#define GPT_PR_PRESCALER_SHIFT (0U)
23804/*! PRESCALER
23805 * 0b000000000000..Divide by 1
23806 * 0b000000000001..Divide by 2
23807 * 0b111111111111..Divide by 4096
23808 */
23809#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
23810#define GPT_PR_PRESCALER24M_MASK (0xF000U)
23811#define GPT_PR_PRESCALER24M_SHIFT (12U)
23812/*! PRESCALER24M
23813 * 0b0000..Divide by 1
23814 * 0b0001..Divide by 2
23815 * 0b1111..Divide by 16
23816 */
23817#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
23818/*! @} */
23819
23820/*! @name SR - GPT Status Register */
23821/*! @{ */
23822#define GPT_SR_OF1_MASK (0x1U)
23823#define GPT_SR_OF1_SHIFT (0U)
23824#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
23825#define GPT_SR_OF2_MASK (0x2U)
23826#define GPT_SR_OF2_SHIFT (1U)
23827#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
23828#define GPT_SR_OF3_MASK (0x4U)
23829#define GPT_SR_OF3_SHIFT (2U)
23830/*! OF3
23831 * 0b0..Compare event has not occurred.
23832 * 0b1..Compare event has occurred.
23833 */
23834#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
23835#define GPT_SR_IF1_MASK (0x8U)
23836#define GPT_SR_IF1_SHIFT (3U)
23837#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
23838#define GPT_SR_IF2_MASK (0x10U)
23839#define GPT_SR_IF2_SHIFT (4U)
23840/*! IF2
23841 * 0b0..Capture event has not occurred.
23842 * 0b1..Capture event has occurred.
23843 */
23844#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
23845#define GPT_SR_ROV_MASK (0x20U)
23846#define GPT_SR_ROV_SHIFT (5U)
23847/*! ROV
23848 * 0b0..Rollover has not occurred.
23849 * 0b1..Rollover has occurred.
23850 */
23851#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
23852/*! @} */
23853
23854/*! @name IR - GPT Interrupt Register */
23855/*! @{ */
23856#define GPT_IR_OF1IE_MASK (0x1U)
23857#define GPT_IR_OF1IE_SHIFT (0U)
23858#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
23859#define GPT_IR_OF2IE_MASK (0x2U)
23860#define GPT_IR_OF2IE_SHIFT (1U)
23861#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
23862#define GPT_IR_OF3IE_MASK (0x4U)
23863#define GPT_IR_OF3IE_SHIFT (2U)
23864/*! OF3IE
23865 * 0b0..Output Compare Channel n interrupt is disabled.
23866 * 0b1..Output Compare Channel n interrupt is enabled.
23867 */
23868#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
23869#define GPT_IR_IF1IE_MASK (0x8U)
23870#define GPT_IR_IF1IE_SHIFT (3U)
23871#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
23872#define GPT_IR_IF2IE_MASK (0x10U)
23873#define GPT_IR_IF2IE_SHIFT (4U)
23874/*! IF2IE
23875 * 0b0..IF2IE Input Capture n Interrupt Enable is disabled.
23876 * 0b1..IF2IE Input Capture n Interrupt Enable is enabled.
23877 */
23878#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
23879#define GPT_IR_ROVIE_MASK (0x20U)
23880#define GPT_IR_ROVIE_SHIFT (5U)
23881/*! ROVIE
23882 * 0b0..Rollover interrupt is disabled.
23883 * 0b1..Rollover interrupt enabled.
23884 */
23885#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
23886/*! @} */
23887
23888/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */
23889/*! @{ */
23890#define GPT_OCR_COMP_MASK (0xFFFFFFFFU)
23891#define GPT_OCR_COMP_SHIFT (0U)
23892#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
23893/*! @} */
23894
23895/* The count of GPT_OCR */
23896#define GPT_OCR_COUNT (3U)
23897
23898/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */
23899/*! @{ */
23900#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU)
23901#define GPT_ICR_CAPT_SHIFT (0U)
23902#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
23903/*! @} */
23904
23905/* The count of GPT_ICR */
23906#define GPT_ICR_COUNT (2U)
23907
23908/*! @name CNT - GPT Counter Register */
23909/*! @{ */
23910#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU)
23911#define GPT_CNT_COUNT_SHIFT (0U)
23912#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
23913/*! @} */
23914
23915
23916/*!
23917 * @}
23918 */ /* end of group GPT_Register_Masks */
23919
23920
23921/* GPT - Peripheral instance base addresses */
23922/** Peripheral GPT1 base address */
23923#define GPT1_BASE (0x302D0000u)
23924/** Peripheral GPT1 base pointer */
23925#define GPT1 ((GPT_Type *)GPT1_BASE)
23926/** Peripheral GPT2 base address */
23927#define GPT2_BASE (0x302E0000u)
23928/** Peripheral GPT2 base pointer */
23929#define GPT2 ((GPT_Type *)GPT2_BASE)
23930/** Peripheral GPT3 base address */
23931#define GPT3_BASE (0x302F0000u)
23932/** Peripheral GPT3 base pointer */
23933#define GPT3 ((GPT_Type *)GPT3_BASE)
23934/** Peripheral GPT4 base address */
23935#define GPT4_BASE (0x30700000u)
23936/** Peripheral GPT4 base pointer */
23937#define GPT4 ((GPT_Type *)GPT4_BASE)
23938/** Peripheral GPT5 base address */
23939#define GPT5_BASE (0x306F0000u)
23940/** Peripheral GPT5 base pointer */
23941#define GPT5 ((GPT_Type *)GPT5_BASE)
23942/** Peripheral GPT6 base address */
23943#define GPT6_BASE (0x306E0000u)
23944/** Peripheral GPT6 base pointer */
23945#define GPT6 ((GPT_Type *)GPT6_BASE)
23946/** Array initializer of GPT peripheral base addresses */
23947#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE, GPT5_BASE, GPT6_BASE }
23948/** Array initializer of GPT peripheral base pointers */
23949#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6 }
23950/** Interrupt vectors for the GPT peripheral type */
23951#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn, GPT3_IRQn, GPT4_IRQn, GPT5_IRQn, GPT6_IRQn }
23952
23953/*!
23954 * @}
23955 */ /* end of group GPT_Peripheral_Access_Layer */
23956
23957
23958/* ----------------------------------------------------------------------------
23959 -- HDMI_TX Peripheral Access Layer
23960 ---------------------------------------------------------------------------- */
23961
23962/*!
23963 * @addtogroup HDMI_TX_Peripheral_Access_Layer HDMI_TX Peripheral Access Layer
23964 * @{
23965 */
23966
23967/** HDMI_TX - Register Layout Typedef */
23968typedef struct {
23969 __IO uint32_t APB_CTRL; /**< , offset: 0x0 */
23970 __IO uint32_t XT_INT_CTRL; /**< , offset: 0x4 */
23971 __I uint32_t MAILBOX_FULL_ADDR; /**< , offset: 0x8 */
23972 __I uint32_t MAILBOX_EMPTY_ADDR; /**< , offset: 0xC */
23973 __IO uint32_t MAILBOX0_WR_DATA; /**< , offset: 0x10 */
23974 __I uint32_t MAILBOX0_RD_DATA; /**< , offset: 0x14 */
23975 __I uint32_t KEEP_ALIVE; /**< , offset: 0x18 */
23976 __I uint32_t VER_L; /**< , offset: 0x1C */
23977 __I uint32_t VER_H; /**< , offset: 0x20 */
23978 __I uint32_t VER_LIB_L_ADDR; /**< , offset: 0x24 */
23979 __I uint32_t VER_LIB_H_ADDR; /**< , offset: 0x28 */
23980 __I uint32_t SW_DEBUG_L; /**< , offset: 0x2C */
23981 __I uint32_t SW_DEBUG_H; /**< , offset: 0x30 */
23982 __IO uint32_t MAILBOX_INT_MASK; /**< , offset: 0x34 */
23983 __I uint32_t MAILBOX_INT_STATUS; /**< , offset: 0x38 */
23984 __IO uint32_t SW_CLK_L; /**< , offset: 0x3C */
23985 __IO uint32_t SW_CLK_H; /**< , offset: 0x40 */
23986 __I uint32_t SW_EVENTS0; /**< , offset: 0x44 */
23987 __I uint32_t SW_EVENTS1; /**< , offset: 0x48 */
23988 __I uint32_t SW_EVENTS2; /**< , offset: 0x4C */
23989 __I uint32_t SW_EVENTS3; /**< , offset: 0x50 */
23990 uint8_t RESERVED_0[12];
23991 __IO uint32_t XT_OCD_CTRL; /**< , offset: 0x60 */
23992 __I uint32_t XT_OCD_CTRL_RO; /**< , offset: 0x64 */
23993 uint8_t RESERVED_1[4];
23994 __IO uint32_t APB_INT_MASK; /**< , offset: 0x6C */
23995 __I uint32_t APB_STATUS_MASK; /**< , offset: 0x70 */
23996 uint8_t RESERVED_2[196492];
23997 __IO uint32_t AUDIO_SRC_CNTL; /**< , offset: 0x30000 */
23998 __IO uint32_t AUDIO_SRC_CNFG; /**< , offset: 0x30004 */
23999 __IO uint32_t COM_CH_STTS_BITS; /**< , offset: 0x30008 */
24000 __IO uint32_t STTS_BIT_CH01; /**< , offset: 0x3000C */
24001 __IO uint32_t STTS_BIT_CH23; /**< , offset: 0x30010 */
24002 __IO uint32_t STTS_BIT_CH45; /**< , offset: 0x30014 */
24003 __IO uint32_t STTS_BIT_CH67; /**< , offset: 0x30018 */
24004 __IO uint32_t STTS_BIT_CH89; /**< , offset: 0x3001C */
24005 __IO uint32_t STTS_BIT_CH1011; /**< , offset: 0x30020 */
24006 __IO uint32_t STTS_BIT_CH1213; /**< , offset: 0x30024 */
24007 __IO uint32_t STTS_BIT_CH1415; /**< , offset: 0x30028 */
24008 __IO uint32_t STTS_BIT_CH1617; /**< , offset: 0x3002C */
24009 __IO uint32_t STTS_BIT_CH1819; /**< , offset: 0x30030 */
24010 __IO uint32_t STTS_BIT_CH2021; /**< , offset: 0x30034 */
24011 __IO uint32_t STTS_BIT_CH2223; /**< , offset: 0x30038 */
24012 __IO uint32_t STTS_BIT_CH2425; /**< , offset: 0x3003C */
24013 __IO uint32_t STTS_BIT_CH2627; /**< , offset: 0x30040 */
24014 __IO uint32_t STTS_BIT_CH2829; /**< , offset: 0x30044 */
24015 __IO uint32_t STTS_BIT_CH3031; /**< , offset: 0x30048 */
24016 __IO uint32_t SPDIF_CTRL_ADDR; /**< , offset: 0x3004C */
24017 __I uint32_t SPDIF_CH1_CS_3100_ADDR; /**< , offset: 0x30050 */
24018 __I uint32_t SPDIF_CH1_CS_6332_ADDR; /**< , offset: 0x30054 */
24019 __I uint32_t SPDIF_CH1_CS_9564_ADDR; /**< , offset: 0x30058 */
24020 __I uint32_t SPDIF_CH1_CS_12796_ADDR; /**< , offset: 0x3005C */
24021 __I uint32_t SPDIF_CH1_CS_159128_ADDR; /**< , offset: 0x30060 */
24022 __I uint32_t SPDIF_CH1_CS_191160_ADDR; /**< , offset: 0x30064 */
24023 __I uint32_t SPDIF_CH2_CS_3100_ADDR; /**< , offset: 0x30068 */
24024 __I uint32_t SPDIF_CH2_CS_6332_ADDR; /**< , offset: 0x3006C */
24025 __I uint32_t SPDIF_CH2_CS_9564_ADDR; /**< , offset: 0x30070 */
24026 __I uint32_t SPDIF_CH2_CS_12796_ADDR; /**< , offset: 0x30074 */
24027 __I uint32_t SPDIF_CH2_CS_159128_ADDR; /**< , offset: 0x30078 */
24028 __I uint32_t SPDIF_CH2_CS_191160_ADDR; /**< , offset: 0x3007C */
24029 __IO uint32_t SMPL2PKT_CNTL; /**< , offset: 0x30080 */
24030 __IO uint32_t SMPL2PKT_CNFG; /**< , offset: 0x30084 */
24031 __IO uint32_t FIFO_CNTL; /**< , offset: 0x30088 */
24032 __I uint32_t FIFO_STTS; /**< , offset: 0x3008C */
24033 __IO uint32_t SUB_PCKT_THRSH; /**< , offset: 0x30090 */
24034 uint8_t RESERVED_3[1900];
24035 __IO uint32_t SOURCE_PIF_WR_ADDR; /**< , offset: 0x30800 */
24036 __IO uint32_t SOURCE_PIF_WR_REQ; /**< , offset: 0x30804 */
24037 __IO uint32_t SOURCE_PIF_RD_ADDR; /**< , offset: 0x30808 */
24038 __IO uint32_t SOURCE_PIF_RD_REQ; /**< , offset: 0x3080C */
24039 __IO uint32_t SOURCE_PIF_DATA_WR; /**< , offset: 0x30810 */
24040 __I uint32_t SOURCE_PIF_DATA_RD; /**< , offset: 0x30814 */
24041 __IO uint32_t SOURCE_PIF_FIFO1_FLUSH; /**< , offset: 0x30818 */
24042 __IO uint32_t SOURCE_PIF_FIFO2_FLUSH; /**< , offset: 0x3081C */
24043 __I uint32_t SOURCE_PIF_STATUS; /**< , offset: 0x30820 */
24044 __I uint32_t SOURCE_PIF_INTERRUPT_SOURCE; /**< , offset: 0x30824 */
24045 __IO uint32_t SOURCE_PIF_INTERRUPT_MASK; /**< , offset: 0x30828 */
24046 __IO uint32_t SOURCE_PIF_PKT_ALLOC_REG; /**< , offset: 0x3082C */
24047 __IO uint32_t SOURCE_PIF_PKT_ALLOC_WR_EN; /**< , offset: 0x30830 */
24048 __IO uint32_t SOURCE_PIF_SW_RESET; /**< , offset: 0x30834 */
24049} HDMI_TX_Type;
24050
24051/* ----------------------------------------------------------------------------
24052 -- HDMI_TX Register Masks
24053 ---------------------------------------------------------------------------- */
24054
24055/*!
24056 * @addtogroup HDMI_TX_Register_Masks HDMI_TX Register Masks
24057 * @{
24058 */
24059
24060/*! @name APB_CTRL - */
24061/*! @{ */
24062#define HDMI_TX_APB_CTRL_apb_xt_reset_MASK (0x1U)
24063#define HDMI_TX_APB_CTRL_apb_xt_reset_SHIFT (0U)
24064#define HDMI_TX_APB_CTRL_apb_xt_reset(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_CTRL_apb_xt_reset_SHIFT)) & HDMI_TX_APB_CTRL_apb_xt_reset_MASK)
24065#define HDMI_TX_APB_CTRL_apb_dram_path_MASK (0x2U)
24066#define HDMI_TX_APB_CTRL_apb_dram_path_SHIFT (1U)
24067#define HDMI_TX_APB_CTRL_apb_dram_path(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_CTRL_apb_dram_path_SHIFT)) & HDMI_TX_APB_CTRL_apb_dram_path_MASK)
24068#define HDMI_TX_APB_CTRL_apb_iram_path_MASK (0x4U)
24069#define HDMI_TX_APB_CTRL_apb_iram_path_SHIFT (2U)
24070#define HDMI_TX_APB_CTRL_apb_iram_path(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_CTRL_apb_iram_path_SHIFT)) & HDMI_TX_APB_CTRL_apb_iram_path_MASK)
24071#define HDMI_TX_APB_CTRL_reserved_0_MASK (0xFFFFFFF8U)
24072#define HDMI_TX_APB_CTRL_reserved_0_SHIFT (3U)
24073#define HDMI_TX_APB_CTRL_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_CTRL_reserved_0_SHIFT)) & HDMI_TX_APB_CTRL_reserved_0_MASK)
24074/*! @} */
24075
24076/*! @name XT_INT_CTRL - */
24077/*! @{ */
24078#define HDMI_TX_XT_INT_CTRL_xt_int_polarity_MASK (0x3U)
24079#define HDMI_TX_XT_INT_CTRL_xt_int_polarity_SHIFT (0U)
24080#define HDMI_TX_XT_INT_CTRL_xt_int_polarity(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_INT_CTRL_xt_int_polarity_SHIFT)) & HDMI_TX_XT_INT_CTRL_xt_int_polarity_MASK)
24081#define HDMI_TX_XT_INT_CTRL_reserved_0_MASK (0xFFFFFFFCU)
24082#define HDMI_TX_XT_INT_CTRL_reserved_0_SHIFT (2U)
24083#define HDMI_TX_XT_INT_CTRL_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_INT_CTRL_reserved_0_SHIFT)) & HDMI_TX_XT_INT_CTRL_reserved_0_MASK)
24084/*! @} */
24085
24086/*! @name MAILBOX_FULL_ADDR - */
24087/*! @{ */
24088#define HDMI_TX_MAILBOX_FULL_ADDR_mailbox_full_MASK (0x1U)
24089#define HDMI_TX_MAILBOX_FULL_ADDR_mailbox_full_SHIFT (0U)
24090#define HDMI_TX_MAILBOX_FULL_ADDR_mailbox_full(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_FULL_ADDR_mailbox_full_SHIFT)) & HDMI_TX_MAILBOX_FULL_ADDR_mailbox_full_MASK)
24091#define HDMI_TX_MAILBOX_FULL_ADDR_reserved_0_MASK (0xFFFFFFFEU)
24092#define HDMI_TX_MAILBOX_FULL_ADDR_reserved_0_SHIFT (1U)
24093#define HDMI_TX_MAILBOX_FULL_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_FULL_ADDR_reserved_0_SHIFT)) & HDMI_TX_MAILBOX_FULL_ADDR_reserved_0_MASK)
24094/*! @} */
24095
24096/*! @name MAILBOX_EMPTY_ADDR - */
24097/*! @{ */
24098#define HDMI_TX_MAILBOX_EMPTY_ADDR_mailbox_empty_MASK (0x1U)
24099#define HDMI_TX_MAILBOX_EMPTY_ADDR_mailbox_empty_SHIFT (0U)
24100#define HDMI_TX_MAILBOX_EMPTY_ADDR_mailbox_empty(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_EMPTY_ADDR_mailbox_empty_SHIFT)) & HDMI_TX_MAILBOX_EMPTY_ADDR_mailbox_empty_MASK)
24101#define HDMI_TX_MAILBOX_EMPTY_ADDR_reserved_0_MASK (0xFFFFFFFEU)
24102#define HDMI_TX_MAILBOX_EMPTY_ADDR_reserved_0_SHIFT (1U)
24103#define HDMI_TX_MAILBOX_EMPTY_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_EMPTY_ADDR_reserved_0_SHIFT)) & HDMI_TX_MAILBOX_EMPTY_ADDR_reserved_0_MASK)
24104/*! @} */
24105
24106/*! @name MAILBOX0_WR_DATA - */
24107/*! @{ */
24108#define HDMI_TX_MAILBOX0_WR_DATA_mailbox0_wr_data_MASK (0xFFU)
24109#define HDMI_TX_MAILBOX0_WR_DATA_mailbox0_wr_data_SHIFT (0U)
24110#define HDMI_TX_MAILBOX0_WR_DATA_mailbox0_wr_data(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX0_WR_DATA_mailbox0_wr_data_SHIFT)) & HDMI_TX_MAILBOX0_WR_DATA_mailbox0_wr_data_MASK)
24111#define HDMI_TX_MAILBOX0_WR_DATA_reserved_0_MASK (0xFFFFFF00U)
24112#define HDMI_TX_MAILBOX0_WR_DATA_reserved_0_SHIFT (8U)
24113#define HDMI_TX_MAILBOX0_WR_DATA_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX0_WR_DATA_reserved_0_SHIFT)) & HDMI_TX_MAILBOX0_WR_DATA_reserved_0_MASK)
24114/*! @} */
24115
24116/*! @name MAILBOX0_RD_DATA - */
24117/*! @{ */
24118#define HDMI_TX_MAILBOX0_RD_DATA_mailbox0_rd_data_MASK (0xFFU)
24119#define HDMI_TX_MAILBOX0_RD_DATA_mailbox0_rd_data_SHIFT (0U)
24120#define HDMI_TX_MAILBOX0_RD_DATA_mailbox0_rd_data(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX0_RD_DATA_mailbox0_rd_data_SHIFT)) & HDMI_TX_MAILBOX0_RD_DATA_mailbox0_rd_data_MASK)
24121#define HDMI_TX_MAILBOX0_RD_DATA_reserved_0_MASK (0xFFFFFF00U)
24122#define HDMI_TX_MAILBOX0_RD_DATA_reserved_0_SHIFT (8U)
24123#define HDMI_TX_MAILBOX0_RD_DATA_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX0_RD_DATA_reserved_0_SHIFT)) & HDMI_TX_MAILBOX0_RD_DATA_reserved_0_MASK)
24124/*! @} */
24125
24126/*! @name KEEP_ALIVE - */
24127/*! @{ */
24128#define HDMI_TX_KEEP_ALIVE_keep_alive_cnt_MASK (0xFFU)
24129#define HDMI_TX_KEEP_ALIVE_keep_alive_cnt_SHIFT (0U)
24130#define HDMI_TX_KEEP_ALIVE_keep_alive_cnt(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_KEEP_ALIVE_keep_alive_cnt_SHIFT)) & HDMI_TX_KEEP_ALIVE_keep_alive_cnt_MASK)
24131#define HDMI_TX_KEEP_ALIVE_reserved_0_MASK (0xFFFFFF00U)
24132#define HDMI_TX_KEEP_ALIVE_reserved_0_SHIFT (8U)
24133#define HDMI_TX_KEEP_ALIVE_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_KEEP_ALIVE_reserved_0_SHIFT)) & HDMI_TX_KEEP_ALIVE_reserved_0_MASK)
24134/*! @} */
24135
24136/*! @name VER_L - */
24137/*! @{ */
24138#define HDMI_TX_VER_L_ver_lsb_MASK (0xFFU)
24139#define HDMI_TX_VER_L_ver_lsb_SHIFT (0U)
24140#define HDMI_TX_VER_L_ver_lsb(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_L_ver_lsb_SHIFT)) & HDMI_TX_VER_L_ver_lsb_MASK)
24141#define HDMI_TX_VER_L_reserved_0_MASK (0xFFFFFF00U)
24142#define HDMI_TX_VER_L_reserved_0_SHIFT (8U)
24143#define HDMI_TX_VER_L_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_L_reserved_0_SHIFT)) & HDMI_TX_VER_L_reserved_0_MASK)
24144/*! @} */
24145
24146/*! @name VER_H - */
24147/*! @{ */
24148#define HDMI_TX_VER_H_ver_msb_MASK (0xFFU)
24149#define HDMI_TX_VER_H_ver_msb_SHIFT (0U)
24150#define HDMI_TX_VER_H_ver_msb(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_H_ver_msb_SHIFT)) & HDMI_TX_VER_H_ver_msb_MASK)
24151#define HDMI_TX_VER_H_reserved_0_MASK (0xFFFFFF00U)
24152#define HDMI_TX_VER_H_reserved_0_SHIFT (8U)
24153#define HDMI_TX_VER_H_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_H_reserved_0_SHIFT)) & HDMI_TX_VER_H_reserved_0_MASK)
24154/*! @} */
24155
24156/*! @name VER_LIB_L_ADDR - */
24157/*! @{ */
24158#define HDMI_TX_VER_LIB_L_ADDR_sw_lib_ver_l_MASK (0xFFU)
24159#define HDMI_TX_VER_LIB_L_ADDR_sw_lib_ver_l_SHIFT (0U)
24160#define HDMI_TX_VER_LIB_L_ADDR_sw_lib_ver_l(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_LIB_L_ADDR_sw_lib_ver_l_SHIFT)) & HDMI_TX_VER_LIB_L_ADDR_sw_lib_ver_l_MASK)
24161#define HDMI_TX_VER_LIB_L_ADDR_reserved_0_MASK (0xFFFFFF00U)
24162#define HDMI_TX_VER_LIB_L_ADDR_reserved_0_SHIFT (8U)
24163#define HDMI_TX_VER_LIB_L_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_LIB_L_ADDR_reserved_0_SHIFT)) & HDMI_TX_VER_LIB_L_ADDR_reserved_0_MASK)
24164/*! @} */
24165
24166/*! @name VER_LIB_H_ADDR - */
24167/*! @{ */
24168#define HDMI_TX_VER_LIB_H_ADDR_sw_lib_ver_h_MASK (0xFFU)
24169#define HDMI_TX_VER_LIB_H_ADDR_sw_lib_ver_h_SHIFT (0U)
24170#define HDMI_TX_VER_LIB_H_ADDR_sw_lib_ver_h(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_LIB_H_ADDR_sw_lib_ver_h_SHIFT)) & HDMI_TX_VER_LIB_H_ADDR_sw_lib_ver_h_MASK)
24171#define HDMI_TX_VER_LIB_H_ADDR_reserved_0_MASK (0xFFFFFF00U)
24172#define HDMI_TX_VER_LIB_H_ADDR_reserved_0_SHIFT (8U)
24173#define HDMI_TX_VER_LIB_H_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_LIB_H_ADDR_reserved_0_SHIFT)) & HDMI_TX_VER_LIB_H_ADDR_reserved_0_MASK)
24174/*! @} */
24175
24176/*! @name SW_DEBUG_L - */
24177/*! @{ */
24178#define HDMI_TX_SW_DEBUG_L_sw_debug_7_0_MASK (0xFFU)
24179#define HDMI_TX_SW_DEBUG_L_sw_debug_7_0_SHIFT (0U)
24180#define HDMI_TX_SW_DEBUG_L_sw_debug_7_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_DEBUG_L_sw_debug_7_0_SHIFT)) & HDMI_TX_SW_DEBUG_L_sw_debug_7_0_MASK)
24181#define HDMI_TX_SW_DEBUG_L_reserved_0_MASK (0xFFFFFF00U)
24182#define HDMI_TX_SW_DEBUG_L_reserved_0_SHIFT (8U)
24183#define HDMI_TX_SW_DEBUG_L_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_DEBUG_L_reserved_0_SHIFT)) & HDMI_TX_SW_DEBUG_L_reserved_0_MASK)
24184/*! @} */
24185
24186/*! @name SW_DEBUG_H - */
24187/*! @{ */
24188#define HDMI_TX_SW_DEBUG_H_sw_debug_15_8_MASK (0xFFU)
24189#define HDMI_TX_SW_DEBUG_H_sw_debug_15_8_SHIFT (0U)
24190#define HDMI_TX_SW_DEBUG_H_sw_debug_15_8(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_DEBUG_H_sw_debug_15_8_SHIFT)) & HDMI_TX_SW_DEBUG_H_sw_debug_15_8_MASK)
24191#define HDMI_TX_SW_DEBUG_H_reserved_0_MASK (0xFFFFFF00U)
24192#define HDMI_TX_SW_DEBUG_H_reserved_0_SHIFT (8U)
24193#define HDMI_TX_SW_DEBUG_H_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_DEBUG_H_reserved_0_SHIFT)) & HDMI_TX_SW_DEBUG_H_reserved_0_MASK)
24194/*! @} */
24195
24196/*! @name MAILBOX_INT_MASK - */
24197/*! @{ */
24198#define HDMI_TX_MAILBOX_INT_MASK_mailbox_int_mask_MASK (0x3U)
24199#define HDMI_TX_MAILBOX_INT_MASK_mailbox_int_mask_SHIFT (0U)
24200#define HDMI_TX_MAILBOX_INT_MASK_mailbox_int_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_INT_MASK_mailbox_int_mask_SHIFT)) & HDMI_TX_MAILBOX_INT_MASK_mailbox_int_mask_MASK)
24201#define HDMI_TX_MAILBOX_INT_MASK_reserved_0_MASK (0xFFFFFFFCU)
24202#define HDMI_TX_MAILBOX_INT_MASK_reserved_0_SHIFT (2U)
24203#define HDMI_TX_MAILBOX_INT_MASK_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_INT_MASK_reserved_0_SHIFT)) & HDMI_TX_MAILBOX_INT_MASK_reserved_0_MASK)
24204/*! @} */
24205
24206/*! @name MAILBOX_INT_STATUS - */
24207/*! @{ */
24208#define HDMI_TX_MAILBOX_INT_STATUS_mailbox_int_status_MASK (0x3U)
24209#define HDMI_TX_MAILBOX_INT_STATUS_mailbox_int_status_SHIFT (0U)
24210#define HDMI_TX_MAILBOX_INT_STATUS_mailbox_int_status(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_INT_STATUS_mailbox_int_status_SHIFT)) & HDMI_TX_MAILBOX_INT_STATUS_mailbox_int_status_MASK)
24211#define HDMI_TX_MAILBOX_INT_STATUS_reserved_0_MASK (0xFFFFFFFCU)
24212#define HDMI_TX_MAILBOX_INT_STATUS_reserved_0_SHIFT (2U)
24213#define HDMI_TX_MAILBOX_INT_STATUS_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_INT_STATUS_reserved_0_SHIFT)) & HDMI_TX_MAILBOX_INT_STATUS_reserved_0_MASK)
24214/*! @} */
24215
24216/*! @name SW_CLK_L - */
24217/*! @{ */
24218#define HDMI_TX_SW_CLK_L_sw_clock_val_l_MASK (0xFFU)
24219#define HDMI_TX_SW_CLK_L_sw_clock_val_l_SHIFT (0U)
24220#define HDMI_TX_SW_CLK_L_sw_clock_val_l(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_CLK_L_sw_clock_val_l_SHIFT)) & HDMI_TX_SW_CLK_L_sw_clock_val_l_MASK)
24221#define HDMI_TX_SW_CLK_L_reserved_0_MASK (0xFFFFFF00U)
24222#define HDMI_TX_SW_CLK_L_reserved_0_SHIFT (8U)
24223#define HDMI_TX_SW_CLK_L_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_CLK_L_reserved_0_SHIFT)) & HDMI_TX_SW_CLK_L_reserved_0_MASK)
24224/*! @} */
24225
24226/*! @name SW_CLK_H - */
24227/*! @{ */
24228#define HDMI_TX_SW_CLK_H_sw_clock_val_h_MASK (0xFFU)
24229#define HDMI_TX_SW_CLK_H_sw_clock_val_h_SHIFT (0U)
24230#define HDMI_TX_SW_CLK_H_sw_clock_val_h(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_CLK_H_sw_clock_val_h_SHIFT)) & HDMI_TX_SW_CLK_H_sw_clock_val_h_MASK)
24231#define HDMI_TX_SW_CLK_H_reserved_0_MASK (0xFFFFFF00U)
24232#define HDMI_TX_SW_CLK_H_reserved_0_SHIFT (8U)
24233#define HDMI_TX_SW_CLK_H_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_CLK_H_reserved_0_SHIFT)) & HDMI_TX_SW_CLK_H_reserved_0_MASK)
24234/*! @} */
24235
24236/*! @name SW_EVENTS0 - */
24237/*! @{ */
24238#define HDMI_TX_SW_EVENTS0_sw_events7_0_MASK (0xFFU)
24239#define HDMI_TX_SW_EVENTS0_sw_events7_0_SHIFT (0U)
24240#define HDMI_TX_SW_EVENTS0_sw_events7_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS0_sw_events7_0_SHIFT)) & HDMI_TX_SW_EVENTS0_sw_events7_0_MASK)
24241#define HDMI_TX_SW_EVENTS0_reserved_0_MASK (0xFFFFFF00U)
24242#define HDMI_TX_SW_EVENTS0_reserved_0_SHIFT (8U)
24243#define HDMI_TX_SW_EVENTS0_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS0_reserved_0_SHIFT)) & HDMI_TX_SW_EVENTS0_reserved_0_MASK)
24244/*! @} */
24245
24246/*! @name SW_EVENTS1 - */
24247/*! @{ */
24248#define HDMI_TX_SW_EVENTS1_sw_events15_8_MASK (0xFFU)
24249#define HDMI_TX_SW_EVENTS1_sw_events15_8_SHIFT (0U)
24250#define HDMI_TX_SW_EVENTS1_sw_events15_8(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS1_sw_events15_8_SHIFT)) & HDMI_TX_SW_EVENTS1_sw_events15_8_MASK)
24251#define HDMI_TX_SW_EVENTS1_reserved_0_MASK (0xFFFFFF00U)
24252#define HDMI_TX_SW_EVENTS1_reserved_0_SHIFT (8U)
24253#define HDMI_TX_SW_EVENTS1_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS1_reserved_0_SHIFT)) & HDMI_TX_SW_EVENTS1_reserved_0_MASK)
24254/*! @} */
24255
24256/*! @name SW_EVENTS2 - */
24257/*! @{ */
24258#define HDMI_TX_SW_EVENTS2_sw_events23_16_MASK (0xFFU)
24259#define HDMI_TX_SW_EVENTS2_sw_events23_16_SHIFT (0U)
24260#define HDMI_TX_SW_EVENTS2_sw_events23_16(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS2_sw_events23_16_SHIFT)) & HDMI_TX_SW_EVENTS2_sw_events23_16_MASK)
24261#define HDMI_TX_SW_EVENTS2_reserved_0_MASK (0xFFFFFF00U)
24262#define HDMI_TX_SW_EVENTS2_reserved_0_SHIFT (8U)
24263#define HDMI_TX_SW_EVENTS2_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS2_reserved_0_SHIFT)) & HDMI_TX_SW_EVENTS2_reserved_0_MASK)
24264/*! @} */
24265
24266/*! @name SW_EVENTS3 - */
24267/*! @{ */
24268#define HDMI_TX_SW_EVENTS3_sw_events31_24_MASK (0xFFU)
24269#define HDMI_TX_SW_EVENTS3_sw_events31_24_SHIFT (0U)
24270#define HDMI_TX_SW_EVENTS3_sw_events31_24(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS3_sw_events31_24_SHIFT)) & HDMI_TX_SW_EVENTS3_sw_events31_24_MASK)
24271#define HDMI_TX_SW_EVENTS3_reserved_0_MASK (0xFFFFFF00U)
24272#define HDMI_TX_SW_EVENTS3_reserved_0_SHIFT (8U)
24273#define HDMI_TX_SW_EVENTS3_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS3_reserved_0_SHIFT)) & HDMI_TX_SW_EVENTS3_reserved_0_MASK)
24274/*! @} */
24275
24276/*! @name XT_OCD_CTRL - */
24277/*! @{ */
24278#define HDMI_TX_XT_OCD_CTRL_xt_dreset_MASK (0x1U)
24279#define HDMI_TX_XT_OCD_CTRL_xt_dreset_SHIFT (0U)
24280#define HDMI_TX_XT_OCD_CTRL_xt_dreset(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_OCD_CTRL_xt_dreset_SHIFT)) & HDMI_TX_XT_OCD_CTRL_xt_dreset_MASK)
24281#define HDMI_TX_XT_OCD_CTRL_xt_ocdhaltonreset_MASK (0x2U)
24282#define HDMI_TX_XT_OCD_CTRL_xt_ocdhaltonreset_SHIFT (1U)
24283#define HDMI_TX_XT_OCD_CTRL_xt_ocdhaltonreset(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_OCD_CTRL_xt_ocdhaltonreset_SHIFT)) & HDMI_TX_XT_OCD_CTRL_xt_ocdhaltonreset_MASK)
24284#define HDMI_TX_XT_OCD_CTRL_reserved_0_MASK (0xFFFFFFFCU)
24285#define HDMI_TX_XT_OCD_CTRL_reserved_0_SHIFT (2U)
24286#define HDMI_TX_XT_OCD_CTRL_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_OCD_CTRL_reserved_0_SHIFT)) & HDMI_TX_XT_OCD_CTRL_reserved_0_MASK)
24287/*! @} */
24288
24289/*! @name XT_OCD_CTRL_RO - */
24290/*! @{ */
24291#define HDMI_TX_XT_OCD_CTRL_RO_xt_xocdmode_MASK (0x1U)
24292#define HDMI_TX_XT_OCD_CTRL_RO_xt_xocdmode_SHIFT (0U)
24293#define HDMI_TX_XT_OCD_CTRL_RO_xt_xocdmode(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_OCD_CTRL_RO_xt_xocdmode_SHIFT)) & HDMI_TX_XT_OCD_CTRL_RO_xt_xocdmode_MASK)
24294#define HDMI_TX_XT_OCD_CTRL_RO_reserved_0_MASK (0xFFFFFFFEU)
24295#define HDMI_TX_XT_OCD_CTRL_RO_reserved_0_SHIFT (1U)
24296#define HDMI_TX_XT_OCD_CTRL_RO_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_OCD_CTRL_RO_reserved_0_SHIFT)) & HDMI_TX_XT_OCD_CTRL_RO_reserved_0_MASK)
24297/*! @} */
24298
24299/*! @name APB_INT_MASK - */
24300/*! @{ */
24301#define HDMI_TX_APB_INT_MASK_apb_intr_mask_MASK (0x7U)
24302#define HDMI_TX_APB_INT_MASK_apb_intr_mask_SHIFT (0U)
24303#define HDMI_TX_APB_INT_MASK_apb_intr_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_INT_MASK_apb_intr_mask_SHIFT)) & HDMI_TX_APB_INT_MASK_apb_intr_mask_MASK)
24304#define HDMI_TX_APB_INT_MASK_reserved_0_MASK (0xFFFFFFF8U)
24305#define HDMI_TX_APB_INT_MASK_reserved_0_SHIFT (3U)
24306#define HDMI_TX_APB_INT_MASK_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_INT_MASK_reserved_0_SHIFT)) & HDMI_TX_APB_INT_MASK_reserved_0_MASK)
24307/*! @} */
24308
24309/*! @name APB_STATUS_MASK - */
24310/*! @{ */
24311#define HDMI_TX_APB_STATUS_MASK_apb_intr_status_MASK (0x7U)
24312#define HDMI_TX_APB_STATUS_MASK_apb_intr_status_SHIFT (0U)
24313#define HDMI_TX_APB_STATUS_MASK_apb_intr_status(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_STATUS_MASK_apb_intr_status_SHIFT)) & HDMI_TX_APB_STATUS_MASK_apb_intr_status_MASK)
24314#define HDMI_TX_APB_STATUS_MASK_reserved_0_MASK (0xFFFFFFF8U)
24315#define HDMI_TX_APB_STATUS_MASK_reserved_0_SHIFT (3U)
24316#define HDMI_TX_APB_STATUS_MASK_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_STATUS_MASK_reserved_0_SHIFT)) & HDMI_TX_APB_STATUS_MASK_reserved_0_MASK)
24317/*! @} */
24318
24319/*! @name AUDIO_SRC_CNTL - */
24320/*! @{ */
24321#define HDMI_TX_AUDIO_SRC_CNTL_sw_rst_MASK (0x1U)
24322#define HDMI_TX_AUDIO_SRC_CNTL_sw_rst_SHIFT (0U)
24323#define HDMI_TX_AUDIO_SRC_CNTL_sw_rst(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_sw_rst_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_sw_rst_MASK)
24324#define HDMI_TX_AUDIO_SRC_CNTL_i2s_dec_start_MASK (0x2U)
24325#define HDMI_TX_AUDIO_SRC_CNTL_i2s_dec_start_SHIFT (1U)
24326#define HDMI_TX_AUDIO_SRC_CNTL_i2s_dec_start(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_i2s_dec_start_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_i2s_dec_start_MASK)
24327#define HDMI_TX_AUDIO_SRC_CNTL_i2s_block_start_force_MASK (0x4U)
24328#define HDMI_TX_AUDIO_SRC_CNTL_i2s_block_start_force_SHIFT (2U)
24329#define HDMI_TX_AUDIO_SRC_CNTL_i2s_block_start_force(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_i2s_block_start_force_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_i2s_block_start_force_MASK)
24330#define HDMI_TX_AUDIO_SRC_CNTL_spdif_ts_en_MASK (0x8U)
24331#define HDMI_TX_AUDIO_SRC_CNTL_spdif_ts_en_SHIFT (3U)
24332#define HDMI_TX_AUDIO_SRC_CNTL_spdif_ts_en(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_spdif_ts_en_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_spdif_ts_en_MASK)
24333#define HDMI_TX_AUDIO_SRC_CNTL_i2s_ts_en_MASK (0x10U)
24334#define HDMI_TX_AUDIO_SRC_CNTL_i2s_ts_en_SHIFT (4U)
24335#define HDMI_TX_AUDIO_SRC_CNTL_i2s_ts_en(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_i2s_ts_en_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_i2s_ts_en_MASK)
24336#define HDMI_TX_AUDIO_SRC_CNTL_valid_bits_force_MASK (0x20U)
24337#define HDMI_TX_AUDIO_SRC_CNTL_valid_bits_force_SHIFT (5U)
24338#define HDMI_TX_AUDIO_SRC_CNTL_valid_bits_force(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_valid_bits_force_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_valid_bits_force_MASK)
24339#define HDMI_TX_AUDIO_SRC_CNTL_valid_all_MASK (0x40U)
24340#define HDMI_TX_AUDIO_SRC_CNTL_valid_all_SHIFT (6U)
24341#define HDMI_TX_AUDIO_SRC_CNTL_valid_all(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_valid_all_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_valid_all_MASK)
24342#define HDMI_TX_AUDIO_SRC_CNTL_reserved_0_MASK (0xFFFFFF80U)
24343#define HDMI_TX_AUDIO_SRC_CNTL_reserved_0_SHIFT (7U)
24344#define HDMI_TX_AUDIO_SRC_CNTL_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_reserved_0_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_reserved_0_MASK)
24345/*! @} */
24346
24347/*! @name AUDIO_SRC_CNFG - */
24348/*! @{ */
24349#define HDMI_TX_AUDIO_SRC_CNFG_low_index_msb_MASK (0x1U)
24350#define HDMI_TX_AUDIO_SRC_CNFG_low_index_msb_SHIFT (0U)
24351#define HDMI_TX_AUDIO_SRC_CNFG_low_index_msb(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_low_index_msb_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_low_index_msb_MASK)
24352#define HDMI_TX_AUDIO_SRC_CNFG_ws_polarity_MASK (0x2U)
24353#define HDMI_TX_AUDIO_SRC_CNFG_ws_polarity_SHIFT (1U)
24354#define HDMI_TX_AUDIO_SRC_CNFG_ws_polarity(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_ws_polarity_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_ws_polarity_MASK)
24355#define HDMI_TX_AUDIO_SRC_CNFG_audio_ch_num_MASK (0x7CU)
24356#define HDMI_TX_AUDIO_SRC_CNFG_audio_ch_num_SHIFT (2U)
24357#define HDMI_TX_AUDIO_SRC_CNFG_audio_ch_num(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_audio_ch_num_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_audio_ch_num_MASK)
24358#define HDMI_TX_AUDIO_SRC_CNFG_audio_sample_just_MASK (0x180U)
24359#define HDMI_TX_AUDIO_SRC_CNFG_audio_sample_just_SHIFT (7U)
24360#define HDMI_TX_AUDIO_SRC_CNFG_audio_sample_just(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_audio_sample_just_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_audio_sample_just_MASK)
24361#define HDMI_TX_AUDIO_SRC_CNFG_audio_sample_width_MASK (0x600U)
24362#define HDMI_TX_AUDIO_SRC_CNFG_audio_sample_width_SHIFT (9U)
24363#define HDMI_TX_AUDIO_SRC_CNFG_audio_sample_width(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_audio_sample_width_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_audio_sample_width_MASK)
24364#define HDMI_TX_AUDIO_SRC_CNFG_trans_smpl_width_MASK (0x1800U)
24365#define HDMI_TX_AUDIO_SRC_CNFG_trans_smpl_width_SHIFT (11U)
24366#define HDMI_TX_AUDIO_SRC_CNFG_trans_smpl_width(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_trans_smpl_width_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_trans_smpl_width_MASK)
24367#define HDMI_TX_AUDIO_SRC_CNFG_audio_channel_type_MASK (0x1E000U)
24368#define HDMI_TX_AUDIO_SRC_CNFG_audio_channel_type_SHIFT (13U)
24369#define HDMI_TX_AUDIO_SRC_CNFG_audio_channel_type(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_audio_channel_type_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_audio_channel_type_MASK)
24370#define HDMI_TX_AUDIO_SRC_CNFG_i2s_dec_port_en_MASK (0x1E0000U)
24371#define HDMI_TX_AUDIO_SRC_CNFG_i2s_dec_port_en_SHIFT (17U)
24372#define HDMI_TX_AUDIO_SRC_CNFG_i2s_dec_port_en(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_i2s_dec_port_en_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_i2s_dec_port_en_MASK)
24373#define HDMI_TX_AUDIO_SRC_CNFG_reserved_0_MASK (0xFFE00000U)
24374#define HDMI_TX_AUDIO_SRC_CNFG_reserved_0_SHIFT (21U)
24375#define HDMI_TX_AUDIO_SRC_CNFG_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_reserved_0_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_reserved_0_MASK)
24376/*! @} */
24377
24378/*! @name COM_CH_STTS_BITS - */
24379/*! @{ */
24380#define HDMI_TX_COM_CH_STTS_BITS_Byte0_MASK (0xFFU)
24381#define HDMI_TX_COM_CH_STTS_BITS_Byte0_SHIFT (0U)
24382#define HDMI_TX_COM_CH_STTS_BITS_Byte0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_COM_CH_STTS_BITS_Byte0_SHIFT)) & HDMI_TX_COM_CH_STTS_BITS_Byte0_MASK)
24383#define HDMI_TX_COM_CH_STTS_BITS_Category_Code_MASK (0xFF00U)
24384#define HDMI_TX_COM_CH_STTS_BITS_Category_Code_SHIFT (8U)
24385#define HDMI_TX_COM_CH_STTS_BITS_Category_Code(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_COM_CH_STTS_BITS_Category_Code_SHIFT)) & HDMI_TX_COM_CH_STTS_BITS_Category_Code_MASK)
24386#define HDMI_TX_COM_CH_STTS_BITS_Sampling_Freq_MASK (0xF0000U)
24387#define HDMI_TX_COM_CH_STTS_BITS_Sampling_Freq_SHIFT (16U)
24388#define HDMI_TX_COM_CH_STTS_BITS_Sampling_Freq(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_COM_CH_STTS_BITS_Sampling_Freq_SHIFT)) & HDMI_TX_COM_CH_STTS_BITS_Sampling_Freq_MASK)
24389#define HDMI_TX_COM_CH_STTS_BITS_Clock_accuracy_MASK (0xF00000U)
24390#define HDMI_TX_COM_CH_STTS_BITS_Clock_accuracy_SHIFT (20U)
24391#define HDMI_TX_COM_CH_STTS_BITS_Clock_accuracy(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_COM_CH_STTS_BITS_Clock_accuracy_SHIFT)) & HDMI_TX_COM_CH_STTS_BITS_Clock_accuracy_MASK)
24392#define HDMI_TX_COM_CH_STTS_BITS_Original_samp_freq_MASK (0xF000000U)
24393#define HDMI_TX_COM_CH_STTS_BITS_Original_samp_freq_SHIFT (24U)
24394#define HDMI_TX_COM_CH_STTS_BITS_Original_samp_freq(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_COM_CH_STTS_BITS_Original_samp_freq_SHIFT)) & HDMI_TX_COM_CH_STTS_BITS_Original_samp_freq_MASK)
24395#define HDMI_TX_COM_CH_STTS_BITS_reserved_0_MASK (0xF0000000U)
24396#define HDMI_TX_COM_CH_STTS_BITS_reserved_0_SHIFT (28U)
24397#define HDMI_TX_COM_CH_STTS_BITS_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_COM_CH_STTS_BITS_reserved_0_SHIFT)) & HDMI_TX_COM_CH_STTS_BITS_reserved_0_MASK)
24398/*! @} */
24399
24400/*! @name STTS_BIT_CH01 - */
24401/*! @{ */
24402#define HDMI_TX_STTS_BIT_CH01_source_num_ch0_MASK (0xFU)
24403#define HDMI_TX_STTS_BIT_CH01_source_num_ch0_SHIFT (0U)
24404#define HDMI_TX_STTS_BIT_CH01_source_num_ch0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_source_num_ch0_SHIFT)) & HDMI_TX_STTS_BIT_CH01_source_num_ch0_MASK)
24405#define HDMI_TX_STTS_BIT_CH01_channel_num_ch0_MASK (0xF0U)
24406#define HDMI_TX_STTS_BIT_CH01_channel_num_ch0_SHIFT (4U)
24407#define HDMI_TX_STTS_BIT_CH01_channel_num_ch0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_channel_num_ch0_SHIFT)) & HDMI_TX_STTS_BIT_CH01_channel_num_ch0_MASK)
24408#define HDMI_TX_STTS_BIT_CH01_word_length_ch0_MASK (0xF00U)
24409#define HDMI_TX_STTS_BIT_CH01_word_length_ch0_SHIFT (8U)
24410#define HDMI_TX_STTS_BIT_CH01_word_length_ch0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_word_length_ch0_SHIFT)) & HDMI_TX_STTS_BIT_CH01_word_length_ch0_MASK)
24411#define HDMI_TX_STTS_BIT_CH01_source_num_ch1_MASK (0xF000U)
24412#define HDMI_TX_STTS_BIT_CH01_source_num_ch1_SHIFT (12U)
24413#define HDMI_TX_STTS_BIT_CH01_source_num_ch1(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_source_num_ch1_SHIFT)) & HDMI_TX_STTS_BIT_CH01_source_num_ch1_MASK)
24414#define HDMI_TX_STTS_BIT_CH01_channel_num_ch1_MASK (0xF0000U)
24415#define HDMI_TX_STTS_BIT_CH01_channel_num_ch1_SHIFT (16U)
24416#define HDMI_TX_STTS_BIT_CH01_channel_num_ch1(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_channel_num_ch1_SHIFT)) & HDMI_TX_STTS_BIT_CH01_channel_num_ch1_MASK)
24417#define HDMI_TX_STTS_BIT_CH01_word_length_ch1_MASK (0xF00000U)
24418#define HDMI_TX_STTS_BIT_CH01_word_length_ch1_SHIFT (20U)
24419#define HDMI_TX_STTS_BIT_CH01_word_length_ch1(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_word_length_ch1_SHIFT)) & HDMI_TX_STTS_BIT_CH01_word_length_ch1_MASK)
24420#define HDMI_TX_STTS_BIT_CH01_valid_bits1_0_MASK (0x3000000U)
24421#define HDMI_TX_STTS_BIT_CH01_valid_bits1_0_SHIFT (24U)
24422#define HDMI_TX_STTS_BIT_CH01_valid_bits1_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_valid_bits1_0_SHIFT)) & HDMI_TX_STTS_BIT_CH01_valid_bits1_0_MASK)
24423#define HDMI_TX_STTS_BIT_CH01_reserved_0_MASK (0xFC000000U)
24424#define HDMI_TX_STTS_BIT_CH01_reserved_0_SHIFT (26U)
24425#define HDMI_TX_STTS_BIT_CH01_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH01_reserved_0_MASK)
24426/*! @} */
24427
24428/*! @name STTS_BIT_CH23 - */
24429/*! @{ */
24430#define HDMI_TX_STTS_BIT_CH23_source_num_ch2_MASK (0xFU)
24431#define HDMI_TX_STTS_BIT_CH23_source_num_ch2_SHIFT (0U)
24432#define HDMI_TX_STTS_BIT_CH23_source_num_ch2(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_source_num_ch2_SHIFT)) & HDMI_TX_STTS_BIT_CH23_source_num_ch2_MASK)
24433#define HDMI_TX_STTS_BIT_CH23_channel_num_ch2_MASK (0xF0U)
24434#define HDMI_TX_STTS_BIT_CH23_channel_num_ch2_SHIFT (4U)
24435#define HDMI_TX_STTS_BIT_CH23_channel_num_ch2(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_channel_num_ch2_SHIFT)) & HDMI_TX_STTS_BIT_CH23_channel_num_ch2_MASK)
24436#define HDMI_TX_STTS_BIT_CH23_word_length_ch2_MASK (0xF00U)
24437#define HDMI_TX_STTS_BIT_CH23_word_length_ch2_SHIFT (8U)
24438#define HDMI_TX_STTS_BIT_CH23_word_length_ch2(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_word_length_ch2_SHIFT)) & HDMI_TX_STTS_BIT_CH23_word_length_ch2_MASK)
24439#define HDMI_TX_STTS_BIT_CH23_source_num_ch3_MASK (0xF000U)
24440#define HDMI_TX_STTS_BIT_CH23_source_num_ch3_SHIFT (12U)
24441#define HDMI_TX_STTS_BIT_CH23_source_num_ch3(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_source_num_ch3_SHIFT)) & HDMI_TX_STTS_BIT_CH23_source_num_ch3_MASK)
24442#define HDMI_TX_STTS_BIT_CH23_channel_num_ch3_MASK (0xF0000U)
24443#define HDMI_TX_STTS_BIT_CH23_channel_num_ch3_SHIFT (16U)
24444#define HDMI_TX_STTS_BIT_CH23_channel_num_ch3(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_channel_num_ch3_SHIFT)) & HDMI_TX_STTS_BIT_CH23_channel_num_ch3_MASK)
24445#define HDMI_TX_STTS_BIT_CH23_word_length_ch3_MASK (0xF00000U)
24446#define HDMI_TX_STTS_BIT_CH23_word_length_ch3_SHIFT (20U)
24447#define HDMI_TX_STTS_BIT_CH23_word_length_ch3(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_word_length_ch3_SHIFT)) & HDMI_TX_STTS_BIT_CH23_word_length_ch3_MASK)
24448#define HDMI_TX_STTS_BIT_CH23_valid_bits3_2_MASK (0x3000000U)
24449#define HDMI_TX_STTS_BIT_CH23_valid_bits3_2_SHIFT (24U)
24450#define HDMI_TX_STTS_BIT_CH23_valid_bits3_2(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_valid_bits3_2_SHIFT)) & HDMI_TX_STTS_BIT_CH23_valid_bits3_2_MASK)
24451#define HDMI_TX_STTS_BIT_CH23_reserved_0_MASK (0xFC000000U)
24452#define HDMI_TX_STTS_BIT_CH23_reserved_0_SHIFT (26U)
24453#define HDMI_TX_STTS_BIT_CH23_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH23_reserved_0_MASK)
24454/*! @} */
24455
24456/*! @name STTS_BIT_CH45 - */
24457/*! @{ */
24458#define HDMI_TX_STTS_BIT_CH45_source_num_ch4_MASK (0xFU)
24459#define HDMI_TX_STTS_BIT_CH45_source_num_ch4_SHIFT (0U)
24460#define HDMI_TX_STTS_BIT_CH45_source_num_ch4(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_source_num_ch4_SHIFT)) & HDMI_TX_STTS_BIT_CH45_source_num_ch4_MASK)
24461#define HDMI_TX_STTS_BIT_CH45_channel_num_ch4_MASK (0xF0U)
24462#define HDMI_TX_STTS_BIT_CH45_channel_num_ch4_SHIFT (4U)
24463#define HDMI_TX_STTS_BIT_CH45_channel_num_ch4(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_channel_num_ch4_SHIFT)) & HDMI_TX_STTS_BIT_CH45_channel_num_ch4_MASK)
24464#define HDMI_TX_STTS_BIT_CH45_word_length_ch4_MASK (0xF00U)
24465#define HDMI_TX_STTS_BIT_CH45_word_length_ch4_SHIFT (8U)
24466#define HDMI_TX_STTS_BIT_CH45_word_length_ch4(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_word_length_ch4_SHIFT)) & HDMI_TX_STTS_BIT_CH45_word_length_ch4_MASK)
24467#define HDMI_TX_STTS_BIT_CH45_source_num_ch5_MASK (0xF000U)
24468#define HDMI_TX_STTS_BIT_CH45_source_num_ch5_SHIFT (12U)
24469#define HDMI_TX_STTS_BIT_CH45_source_num_ch5(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_source_num_ch5_SHIFT)) & HDMI_TX_STTS_BIT_CH45_source_num_ch5_MASK)
24470#define HDMI_TX_STTS_BIT_CH45_channel_num_ch5_MASK (0xF0000U)
24471#define HDMI_TX_STTS_BIT_CH45_channel_num_ch5_SHIFT (16U)
24472#define HDMI_TX_STTS_BIT_CH45_channel_num_ch5(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_channel_num_ch5_SHIFT)) & HDMI_TX_STTS_BIT_CH45_channel_num_ch5_MASK)
24473#define HDMI_TX_STTS_BIT_CH45_word_length_ch5_MASK (0xF00000U)
24474#define HDMI_TX_STTS_BIT_CH45_word_length_ch5_SHIFT (20U)
24475#define HDMI_TX_STTS_BIT_CH45_word_length_ch5(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_word_length_ch5_SHIFT)) & HDMI_TX_STTS_BIT_CH45_word_length_ch5_MASK)
24476#define HDMI_TX_STTS_BIT_CH45_valid_bits5_4_MASK (0x3000000U)
24477#define HDMI_TX_STTS_BIT_CH45_valid_bits5_4_SHIFT (24U)
24478#define HDMI_TX_STTS_BIT_CH45_valid_bits5_4(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_valid_bits5_4_SHIFT)) & HDMI_TX_STTS_BIT_CH45_valid_bits5_4_MASK)
24479#define HDMI_TX_STTS_BIT_CH45_reserved_0_MASK (0xFC000000U)
24480#define HDMI_TX_STTS_BIT_CH45_reserved_0_SHIFT (26U)
24481#define HDMI_TX_STTS_BIT_CH45_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH45_reserved_0_MASK)
24482/*! @} */
24483
24484/*! @name STTS_BIT_CH67 - */
24485/*! @{ */
24486#define HDMI_TX_STTS_BIT_CH67_source_num_ch6_MASK (0xFU)
24487#define HDMI_TX_STTS_BIT_CH67_source_num_ch6_SHIFT (0U)
24488#define HDMI_TX_STTS_BIT_CH67_source_num_ch6(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_source_num_ch6_SHIFT)) & HDMI_TX_STTS_BIT_CH67_source_num_ch6_MASK)
24489#define HDMI_TX_STTS_BIT_CH67_channel_num_ch6_MASK (0xF0U)
24490#define HDMI_TX_STTS_BIT_CH67_channel_num_ch6_SHIFT (4U)
24491#define HDMI_TX_STTS_BIT_CH67_channel_num_ch6(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_channel_num_ch6_SHIFT)) & HDMI_TX_STTS_BIT_CH67_channel_num_ch6_MASK)
24492#define HDMI_TX_STTS_BIT_CH67_word_length_ch6_MASK (0xF00U)
24493#define HDMI_TX_STTS_BIT_CH67_word_length_ch6_SHIFT (8U)
24494#define HDMI_TX_STTS_BIT_CH67_word_length_ch6(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_word_length_ch6_SHIFT)) & HDMI_TX_STTS_BIT_CH67_word_length_ch6_MASK)
24495#define HDMI_TX_STTS_BIT_CH67_source_num_ch7_MASK (0xF000U)
24496#define HDMI_TX_STTS_BIT_CH67_source_num_ch7_SHIFT (12U)
24497#define HDMI_TX_STTS_BIT_CH67_source_num_ch7(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_source_num_ch7_SHIFT)) & HDMI_TX_STTS_BIT_CH67_source_num_ch7_MASK)
24498#define HDMI_TX_STTS_BIT_CH67_channel_num_ch7_MASK (0xF0000U)
24499#define HDMI_TX_STTS_BIT_CH67_channel_num_ch7_SHIFT (16U)
24500#define HDMI_TX_STTS_BIT_CH67_channel_num_ch7(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_channel_num_ch7_SHIFT)) & HDMI_TX_STTS_BIT_CH67_channel_num_ch7_MASK)
24501#define HDMI_TX_STTS_BIT_CH67_word_length_ch7_MASK (0xF00000U)
24502#define HDMI_TX_STTS_BIT_CH67_word_length_ch7_SHIFT (20U)
24503#define HDMI_TX_STTS_BIT_CH67_word_length_ch7(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_word_length_ch7_SHIFT)) & HDMI_TX_STTS_BIT_CH67_word_length_ch7_MASK)
24504#define HDMI_TX_STTS_BIT_CH67_valid_bits7_6_MASK (0x3000000U)
24505#define HDMI_TX_STTS_BIT_CH67_valid_bits7_6_SHIFT (24U)
24506#define HDMI_TX_STTS_BIT_CH67_valid_bits7_6(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_valid_bits7_6_SHIFT)) & HDMI_TX_STTS_BIT_CH67_valid_bits7_6_MASK)
24507#define HDMI_TX_STTS_BIT_CH67_reserved_0_MASK (0xFC000000U)
24508#define HDMI_TX_STTS_BIT_CH67_reserved_0_SHIFT (26U)
24509#define HDMI_TX_STTS_BIT_CH67_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH67_reserved_0_MASK)
24510/*! @} */
24511
24512/*! @name STTS_BIT_CH89 - */
24513/*! @{ */
24514#define HDMI_TX_STTS_BIT_CH89_source_num_ch8_MASK (0xFU)
24515#define HDMI_TX_STTS_BIT_CH89_source_num_ch8_SHIFT (0U)
24516#define HDMI_TX_STTS_BIT_CH89_source_num_ch8(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_source_num_ch8_SHIFT)) & HDMI_TX_STTS_BIT_CH89_source_num_ch8_MASK)
24517#define HDMI_TX_STTS_BIT_CH89_channel_num_ch8_MASK (0xF0U)
24518#define HDMI_TX_STTS_BIT_CH89_channel_num_ch8_SHIFT (4U)
24519#define HDMI_TX_STTS_BIT_CH89_channel_num_ch8(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_channel_num_ch8_SHIFT)) & HDMI_TX_STTS_BIT_CH89_channel_num_ch8_MASK)
24520#define HDMI_TX_STTS_BIT_CH89_word_length_ch8_MASK (0xF00U)
24521#define HDMI_TX_STTS_BIT_CH89_word_length_ch8_SHIFT (8U)
24522#define HDMI_TX_STTS_BIT_CH89_word_length_ch8(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_word_length_ch8_SHIFT)) & HDMI_TX_STTS_BIT_CH89_word_length_ch8_MASK)
24523#define HDMI_TX_STTS_BIT_CH89_source_num_ch9_MASK (0xF000U)
24524#define HDMI_TX_STTS_BIT_CH89_source_num_ch9_SHIFT (12U)
24525#define HDMI_TX_STTS_BIT_CH89_source_num_ch9(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_source_num_ch9_SHIFT)) & HDMI_TX_STTS_BIT_CH89_source_num_ch9_MASK)
24526#define HDMI_TX_STTS_BIT_CH89_channel_num_ch9_MASK (0xF0000U)
24527#define HDMI_TX_STTS_BIT_CH89_channel_num_ch9_SHIFT (16U)
24528#define HDMI_TX_STTS_BIT_CH89_channel_num_ch9(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_channel_num_ch9_SHIFT)) & HDMI_TX_STTS_BIT_CH89_channel_num_ch9_MASK)
24529#define HDMI_TX_STTS_BIT_CH89_word_length_ch9_MASK (0xF00000U)
24530#define HDMI_TX_STTS_BIT_CH89_word_length_ch9_SHIFT (20U)
24531#define HDMI_TX_STTS_BIT_CH89_word_length_ch9(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_word_length_ch9_SHIFT)) & HDMI_TX_STTS_BIT_CH89_word_length_ch9_MASK)
24532#define HDMI_TX_STTS_BIT_CH89_valid_bits9_8_MASK (0x3000000U)
24533#define HDMI_TX_STTS_BIT_CH89_valid_bits9_8_SHIFT (24U)
24534#define HDMI_TX_STTS_BIT_CH89_valid_bits9_8(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_valid_bits9_8_SHIFT)) & HDMI_TX_STTS_BIT_CH89_valid_bits9_8_MASK)
24535#define HDMI_TX_STTS_BIT_CH89_reserved_0_MASK (0xFC000000U)
24536#define HDMI_TX_STTS_BIT_CH89_reserved_0_SHIFT (26U)
24537#define HDMI_TX_STTS_BIT_CH89_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH89_reserved_0_MASK)
24538/*! @} */
24539
24540/*! @name STTS_BIT_CH1011 - */
24541/*! @{ */
24542#define HDMI_TX_STTS_BIT_CH1011_source_num_ch10_MASK (0xFU)
24543#define HDMI_TX_STTS_BIT_CH1011_source_num_ch10_SHIFT (0U)
24544#define HDMI_TX_STTS_BIT_CH1011_source_num_ch10(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_source_num_ch10_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_source_num_ch10_MASK)
24545#define HDMI_TX_STTS_BIT_CH1011_channel_num_ch10_MASK (0xF0U)
24546#define HDMI_TX_STTS_BIT_CH1011_channel_num_ch10_SHIFT (4U)
24547#define HDMI_TX_STTS_BIT_CH1011_channel_num_ch10(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_channel_num_ch10_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_channel_num_ch10_MASK)
24548#define HDMI_TX_STTS_BIT_CH1011_word_length_ch10_MASK (0xF00U)
24549#define HDMI_TX_STTS_BIT_CH1011_word_length_ch10_SHIFT (8U)
24550#define HDMI_TX_STTS_BIT_CH1011_word_length_ch10(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_word_length_ch10_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_word_length_ch10_MASK)
24551#define HDMI_TX_STTS_BIT_CH1011_source_num_ch11_MASK (0xF000U)
24552#define HDMI_TX_STTS_BIT_CH1011_source_num_ch11_SHIFT (12U)
24553#define HDMI_TX_STTS_BIT_CH1011_source_num_ch11(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_source_num_ch11_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_source_num_ch11_MASK)
24554#define HDMI_TX_STTS_BIT_CH1011_channel_num_ch11_MASK (0xF0000U)
24555#define HDMI_TX_STTS_BIT_CH1011_channel_num_ch11_SHIFT (16U)
24556#define HDMI_TX_STTS_BIT_CH1011_channel_num_ch11(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_channel_num_ch11_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_channel_num_ch11_MASK)
24557#define HDMI_TX_STTS_BIT_CH1011_word_length_ch11_MASK (0xF00000U)
24558#define HDMI_TX_STTS_BIT_CH1011_word_length_ch11_SHIFT (20U)
24559#define HDMI_TX_STTS_BIT_CH1011_word_length_ch11(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_word_length_ch11_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_word_length_ch11_MASK)
24560#define HDMI_TX_STTS_BIT_CH1011_valid_bits11_10_MASK (0x3000000U)
24561#define HDMI_TX_STTS_BIT_CH1011_valid_bits11_10_SHIFT (24U)
24562#define HDMI_TX_STTS_BIT_CH1011_valid_bits11_10(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_valid_bits11_10_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_valid_bits11_10_MASK)
24563#define HDMI_TX_STTS_BIT_CH1011_reserved_0_MASK (0xFC000000U)
24564#define HDMI_TX_STTS_BIT_CH1011_reserved_0_SHIFT (26U)
24565#define HDMI_TX_STTS_BIT_CH1011_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_reserved_0_MASK)
24566/*! @} */
24567
24568/*! @name STTS_BIT_CH1213 - */
24569/*! @{ */
24570#define HDMI_TX_STTS_BIT_CH1213_source_num_ch12_MASK (0xFU)
24571#define HDMI_TX_STTS_BIT_CH1213_source_num_ch12_SHIFT (0U)
24572#define HDMI_TX_STTS_BIT_CH1213_source_num_ch12(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_source_num_ch12_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_source_num_ch12_MASK)
24573#define HDMI_TX_STTS_BIT_CH1213_channel_num_ch12_MASK (0xF0U)
24574#define HDMI_TX_STTS_BIT_CH1213_channel_num_ch12_SHIFT (4U)
24575#define HDMI_TX_STTS_BIT_CH1213_channel_num_ch12(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_channel_num_ch12_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_channel_num_ch12_MASK)
24576#define HDMI_TX_STTS_BIT_CH1213_word_length_ch12_MASK (0xF00U)
24577#define HDMI_TX_STTS_BIT_CH1213_word_length_ch12_SHIFT (8U)
24578#define HDMI_TX_STTS_BIT_CH1213_word_length_ch12(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_word_length_ch12_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_word_length_ch12_MASK)
24579#define HDMI_TX_STTS_BIT_CH1213_source_num_ch13_MASK (0xF000U)
24580#define HDMI_TX_STTS_BIT_CH1213_source_num_ch13_SHIFT (12U)
24581#define HDMI_TX_STTS_BIT_CH1213_source_num_ch13(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_source_num_ch13_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_source_num_ch13_MASK)
24582#define HDMI_TX_STTS_BIT_CH1213_channel_num_ch13_MASK (0xF0000U)
24583#define HDMI_TX_STTS_BIT_CH1213_channel_num_ch13_SHIFT (16U)
24584#define HDMI_TX_STTS_BIT_CH1213_channel_num_ch13(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_channel_num_ch13_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_channel_num_ch13_MASK)
24585#define HDMI_TX_STTS_BIT_CH1213_word_length_ch13_MASK (0xF00000U)
24586#define HDMI_TX_STTS_BIT_CH1213_word_length_ch13_SHIFT (20U)
24587#define HDMI_TX_STTS_BIT_CH1213_word_length_ch13(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_word_length_ch13_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_word_length_ch13_MASK)
24588#define HDMI_TX_STTS_BIT_CH1213_valid_bits13_12_MASK (0x3000000U)
24589#define HDMI_TX_STTS_BIT_CH1213_valid_bits13_12_SHIFT (24U)
24590#define HDMI_TX_STTS_BIT_CH1213_valid_bits13_12(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_valid_bits13_12_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_valid_bits13_12_MASK)
24591#define HDMI_TX_STTS_BIT_CH1213_reserved_0_MASK (0xFC000000U)
24592#define HDMI_TX_STTS_BIT_CH1213_reserved_0_SHIFT (26U)
24593#define HDMI_TX_STTS_BIT_CH1213_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_reserved_0_MASK)
24594/*! @} */
24595
24596/*! @name STTS_BIT_CH1415 - */
24597/*! @{ */
24598#define HDMI_TX_STTS_BIT_CH1415_source_num_ch14_MASK (0xFU)
24599#define HDMI_TX_STTS_BIT_CH1415_source_num_ch14_SHIFT (0U)
24600#define HDMI_TX_STTS_BIT_CH1415_source_num_ch14(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_source_num_ch14_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_source_num_ch14_MASK)
24601#define HDMI_TX_STTS_BIT_CH1415_channel_num_ch14_MASK (0xF0U)
24602#define HDMI_TX_STTS_BIT_CH1415_channel_num_ch14_SHIFT (4U)
24603#define HDMI_TX_STTS_BIT_CH1415_channel_num_ch14(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_channel_num_ch14_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_channel_num_ch14_MASK)
24604#define HDMI_TX_STTS_BIT_CH1415_word_length_ch14_MASK (0xF00U)
24605#define HDMI_TX_STTS_BIT_CH1415_word_length_ch14_SHIFT (8U)
24606#define HDMI_TX_STTS_BIT_CH1415_word_length_ch14(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_word_length_ch14_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_word_length_ch14_MASK)
24607#define HDMI_TX_STTS_BIT_CH1415_source_num_ch15_MASK (0xF000U)
24608#define HDMI_TX_STTS_BIT_CH1415_source_num_ch15_SHIFT (12U)
24609#define HDMI_TX_STTS_BIT_CH1415_source_num_ch15(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_source_num_ch15_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_source_num_ch15_MASK)
24610#define HDMI_TX_STTS_BIT_CH1415_channel_num_ch15_MASK (0xF0000U)
24611#define HDMI_TX_STTS_BIT_CH1415_channel_num_ch15_SHIFT (16U)
24612#define HDMI_TX_STTS_BIT_CH1415_channel_num_ch15(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_channel_num_ch15_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_channel_num_ch15_MASK)
24613#define HDMI_TX_STTS_BIT_CH1415_word_length_ch15_MASK (0xF00000U)
24614#define HDMI_TX_STTS_BIT_CH1415_word_length_ch15_SHIFT (20U)
24615#define HDMI_TX_STTS_BIT_CH1415_word_length_ch15(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_word_length_ch15_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_word_length_ch15_MASK)
24616#define HDMI_TX_STTS_BIT_CH1415_valid_bits15_14_MASK (0x3000000U)
24617#define HDMI_TX_STTS_BIT_CH1415_valid_bits15_14_SHIFT (24U)
24618#define HDMI_TX_STTS_BIT_CH1415_valid_bits15_14(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_valid_bits15_14_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_valid_bits15_14_MASK)
24619#define HDMI_TX_STTS_BIT_CH1415_reserved_0_MASK (0xFC000000U)
24620#define HDMI_TX_STTS_BIT_CH1415_reserved_0_SHIFT (26U)
24621#define HDMI_TX_STTS_BIT_CH1415_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_reserved_0_MASK)
24622/*! @} */
24623
24624/*! @name STTS_BIT_CH1617 - */
24625/*! @{ */
24626#define HDMI_TX_STTS_BIT_CH1617_source_num_ch16_MASK (0xFU)
24627#define HDMI_TX_STTS_BIT_CH1617_source_num_ch16_SHIFT (0U)
24628#define HDMI_TX_STTS_BIT_CH1617_source_num_ch16(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_source_num_ch16_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_source_num_ch16_MASK)
24629#define HDMI_TX_STTS_BIT_CH1617_channel_num_ch16_MASK (0xF0U)
24630#define HDMI_TX_STTS_BIT_CH1617_channel_num_ch16_SHIFT (4U)
24631#define HDMI_TX_STTS_BIT_CH1617_channel_num_ch16(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_channel_num_ch16_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_channel_num_ch16_MASK)
24632#define HDMI_TX_STTS_BIT_CH1617_word_length_ch16_MASK (0xF00U)
24633#define HDMI_TX_STTS_BIT_CH1617_word_length_ch16_SHIFT (8U)
24634#define HDMI_TX_STTS_BIT_CH1617_word_length_ch16(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_word_length_ch16_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_word_length_ch16_MASK)
24635#define HDMI_TX_STTS_BIT_CH1617_source_num_ch17_MASK (0xF000U)
24636#define HDMI_TX_STTS_BIT_CH1617_source_num_ch17_SHIFT (12U)
24637#define HDMI_TX_STTS_BIT_CH1617_source_num_ch17(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_source_num_ch17_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_source_num_ch17_MASK)
24638#define HDMI_TX_STTS_BIT_CH1617_channel_num_ch17_MASK (0xF0000U)
24639#define HDMI_TX_STTS_BIT_CH1617_channel_num_ch17_SHIFT (16U)
24640#define HDMI_TX_STTS_BIT_CH1617_channel_num_ch17(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_channel_num_ch17_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_channel_num_ch17_MASK)
24641#define HDMI_TX_STTS_BIT_CH1617_word_length_ch17_MASK (0xF00000U)
24642#define HDMI_TX_STTS_BIT_CH1617_word_length_ch17_SHIFT (20U)
24643#define HDMI_TX_STTS_BIT_CH1617_word_length_ch17(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_word_length_ch17_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_word_length_ch17_MASK)
24644#define HDMI_TX_STTS_BIT_CH1617_valid_bits17_16_MASK (0x3000000U)
24645#define HDMI_TX_STTS_BIT_CH1617_valid_bits17_16_SHIFT (24U)
24646#define HDMI_TX_STTS_BIT_CH1617_valid_bits17_16(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_valid_bits17_16_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_valid_bits17_16_MASK)
24647#define HDMI_TX_STTS_BIT_CH1617_reserved_0_MASK (0xFC000000U)
24648#define HDMI_TX_STTS_BIT_CH1617_reserved_0_SHIFT (26U)
24649#define HDMI_TX_STTS_BIT_CH1617_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_reserved_0_MASK)
24650/*! @} */
24651
24652/*! @name STTS_BIT_CH1819 - */
24653/*! @{ */
24654#define HDMI_TX_STTS_BIT_CH1819_source_num_ch18_MASK (0xFU)
24655#define HDMI_TX_STTS_BIT_CH1819_source_num_ch18_SHIFT (0U)
24656#define HDMI_TX_STTS_BIT_CH1819_source_num_ch18(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_source_num_ch18_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_source_num_ch18_MASK)
24657#define HDMI_TX_STTS_BIT_CH1819_channel_num_ch18_MASK (0xF0U)
24658#define HDMI_TX_STTS_BIT_CH1819_channel_num_ch18_SHIFT (4U)
24659#define HDMI_TX_STTS_BIT_CH1819_channel_num_ch18(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_channel_num_ch18_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_channel_num_ch18_MASK)
24660#define HDMI_TX_STTS_BIT_CH1819_word_length_ch18_MASK (0xF00U)
24661#define HDMI_TX_STTS_BIT_CH1819_word_length_ch18_SHIFT (8U)
24662#define HDMI_TX_STTS_BIT_CH1819_word_length_ch18(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_word_length_ch18_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_word_length_ch18_MASK)
24663#define HDMI_TX_STTS_BIT_CH1819_source_num_ch19_MASK (0xF000U)
24664#define HDMI_TX_STTS_BIT_CH1819_source_num_ch19_SHIFT (12U)
24665#define HDMI_TX_STTS_BIT_CH1819_source_num_ch19(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_source_num_ch19_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_source_num_ch19_MASK)
24666#define HDMI_TX_STTS_BIT_CH1819_channel_num_ch19_MASK (0xF0000U)
24667#define HDMI_TX_STTS_BIT_CH1819_channel_num_ch19_SHIFT (16U)
24668#define HDMI_TX_STTS_BIT_CH1819_channel_num_ch19(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_channel_num_ch19_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_channel_num_ch19_MASK)
24669#define HDMI_TX_STTS_BIT_CH1819_word_length_ch19_MASK (0xF00000U)
24670#define HDMI_TX_STTS_BIT_CH1819_word_length_ch19_SHIFT (20U)
24671#define HDMI_TX_STTS_BIT_CH1819_word_length_ch19(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_word_length_ch19_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_word_length_ch19_MASK)
24672#define HDMI_TX_STTS_BIT_CH1819_valid_bits19_18_MASK (0x3000000U)
24673#define HDMI_TX_STTS_BIT_CH1819_valid_bits19_18_SHIFT (24U)
24674#define HDMI_TX_STTS_BIT_CH1819_valid_bits19_18(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_valid_bits19_18_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_valid_bits19_18_MASK)
24675#define HDMI_TX_STTS_BIT_CH1819_reserved_0_MASK (0xFC000000U)
24676#define HDMI_TX_STTS_BIT_CH1819_reserved_0_SHIFT (26U)
24677#define HDMI_TX_STTS_BIT_CH1819_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_reserved_0_MASK)
24678/*! @} */
24679
24680/*! @name STTS_BIT_CH2021 - */
24681/*! @{ */
24682#define HDMI_TX_STTS_BIT_CH2021_source_num_ch20_MASK (0xFU)
24683#define HDMI_TX_STTS_BIT_CH2021_source_num_ch20_SHIFT (0U)
24684#define HDMI_TX_STTS_BIT_CH2021_source_num_ch20(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_source_num_ch20_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_source_num_ch20_MASK)
24685#define HDMI_TX_STTS_BIT_CH2021_channel_num_ch20_MASK (0xF0U)
24686#define HDMI_TX_STTS_BIT_CH2021_channel_num_ch20_SHIFT (4U)
24687#define HDMI_TX_STTS_BIT_CH2021_channel_num_ch20(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_channel_num_ch20_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_channel_num_ch20_MASK)
24688#define HDMI_TX_STTS_BIT_CH2021_word_length_ch20_MASK (0xF00U)
24689#define HDMI_TX_STTS_BIT_CH2021_word_length_ch20_SHIFT (8U)
24690#define HDMI_TX_STTS_BIT_CH2021_word_length_ch20(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_word_length_ch20_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_word_length_ch20_MASK)
24691#define HDMI_TX_STTS_BIT_CH2021_source_num_ch21_MASK (0xF000U)
24692#define HDMI_TX_STTS_BIT_CH2021_source_num_ch21_SHIFT (12U)
24693#define HDMI_TX_STTS_BIT_CH2021_source_num_ch21(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_source_num_ch21_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_source_num_ch21_MASK)
24694#define HDMI_TX_STTS_BIT_CH2021_channel_num_ch21_MASK (0xF0000U)
24695#define HDMI_TX_STTS_BIT_CH2021_channel_num_ch21_SHIFT (16U)
24696#define HDMI_TX_STTS_BIT_CH2021_channel_num_ch21(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_channel_num_ch21_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_channel_num_ch21_MASK)
24697#define HDMI_TX_STTS_BIT_CH2021_word_length_ch21_MASK (0xF00000U)
24698#define HDMI_TX_STTS_BIT_CH2021_word_length_ch21_SHIFT (20U)
24699#define HDMI_TX_STTS_BIT_CH2021_word_length_ch21(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_word_length_ch21_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_word_length_ch21_MASK)
24700#define HDMI_TX_STTS_BIT_CH2021_valid_bits21_20_MASK (0x3000000U)
24701#define HDMI_TX_STTS_BIT_CH2021_valid_bits21_20_SHIFT (24U)
24702#define HDMI_TX_STTS_BIT_CH2021_valid_bits21_20(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_valid_bits21_20_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_valid_bits21_20_MASK)
24703#define HDMI_TX_STTS_BIT_CH2021_reserved_0_MASK (0xFC000000U)
24704#define HDMI_TX_STTS_BIT_CH2021_reserved_0_SHIFT (26U)
24705#define HDMI_TX_STTS_BIT_CH2021_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_reserved_0_MASK)
24706/*! @} */
24707
24708/*! @name STTS_BIT_CH2223 - */
24709/*! @{ */
24710#define HDMI_TX_STTS_BIT_CH2223_source_num_ch22_MASK (0xFU)
24711#define HDMI_TX_STTS_BIT_CH2223_source_num_ch22_SHIFT (0U)
24712#define HDMI_TX_STTS_BIT_CH2223_source_num_ch22(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_source_num_ch22_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_source_num_ch22_MASK)
24713#define HDMI_TX_STTS_BIT_CH2223_channel_num_ch22_MASK (0xF0U)
24714#define HDMI_TX_STTS_BIT_CH2223_channel_num_ch22_SHIFT (4U)
24715#define HDMI_TX_STTS_BIT_CH2223_channel_num_ch22(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_channel_num_ch22_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_channel_num_ch22_MASK)
24716#define HDMI_TX_STTS_BIT_CH2223_word_length_ch22_MASK (0xF00U)
24717#define HDMI_TX_STTS_BIT_CH2223_word_length_ch22_SHIFT (8U)
24718#define HDMI_TX_STTS_BIT_CH2223_word_length_ch22(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_word_length_ch22_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_word_length_ch22_MASK)
24719#define HDMI_TX_STTS_BIT_CH2223_source_num_ch23_MASK (0xF000U)
24720#define HDMI_TX_STTS_BIT_CH2223_source_num_ch23_SHIFT (12U)
24721#define HDMI_TX_STTS_BIT_CH2223_source_num_ch23(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_source_num_ch23_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_source_num_ch23_MASK)
24722#define HDMI_TX_STTS_BIT_CH2223_channel_num_ch23_MASK (0xF0000U)
24723#define HDMI_TX_STTS_BIT_CH2223_channel_num_ch23_SHIFT (16U)
24724#define HDMI_TX_STTS_BIT_CH2223_channel_num_ch23(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_channel_num_ch23_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_channel_num_ch23_MASK)
24725#define HDMI_TX_STTS_BIT_CH2223_word_length_ch23_MASK (0xF00000U)
24726#define HDMI_TX_STTS_BIT_CH2223_word_length_ch23_SHIFT (20U)
24727#define HDMI_TX_STTS_BIT_CH2223_word_length_ch23(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_word_length_ch23_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_word_length_ch23_MASK)
24728#define HDMI_TX_STTS_BIT_CH2223_valid_bits23_22_MASK (0x3000000U)
24729#define HDMI_TX_STTS_BIT_CH2223_valid_bits23_22_SHIFT (24U)
24730#define HDMI_TX_STTS_BIT_CH2223_valid_bits23_22(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_valid_bits23_22_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_valid_bits23_22_MASK)
24731#define HDMI_TX_STTS_BIT_CH2223_reserved_0_MASK (0xFC000000U)
24732#define HDMI_TX_STTS_BIT_CH2223_reserved_0_SHIFT (26U)
24733#define HDMI_TX_STTS_BIT_CH2223_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_reserved_0_MASK)
24734/*! @} */
24735
24736/*! @name STTS_BIT_CH2425 - */
24737/*! @{ */
24738#define HDMI_TX_STTS_BIT_CH2425_source_num_ch24_MASK (0xFU)
24739#define HDMI_TX_STTS_BIT_CH2425_source_num_ch24_SHIFT (0U)
24740#define HDMI_TX_STTS_BIT_CH2425_source_num_ch24(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_source_num_ch24_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_source_num_ch24_MASK)
24741#define HDMI_TX_STTS_BIT_CH2425_channel_num_ch24_MASK (0xF0U)
24742#define HDMI_TX_STTS_BIT_CH2425_channel_num_ch24_SHIFT (4U)
24743#define HDMI_TX_STTS_BIT_CH2425_channel_num_ch24(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_channel_num_ch24_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_channel_num_ch24_MASK)
24744#define HDMI_TX_STTS_BIT_CH2425_word_length_ch24_MASK (0xF00U)
24745#define HDMI_TX_STTS_BIT_CH2425_word_length_ch24_SHIFT (8U)
24746#define HDMI_TX_STTS_BIT_CH2425_word_length_ch24(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_word_length_ch24_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_word_length_ch24_MASK)
24747#define HDMI_TX_STTS_BIT_CH2425_source_num_ch25_MASK (0xF000U)
24748#define HDMI_TX_STTS_BIT_CH2425_source_num_ch25_SHIFT (12U)
24749#define HDMI_TX_STTS_BIT_CH2425_source_num_ch25(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_source_num_ch25_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_source_num_ch25_MASK)
24750#define HDMI_TX_STTS_BIT_CH2425_channel_num_ch25_MASK (0xF0000U)
24751#define HDMI_TX_STTS_BIT_CH2425_channel_num_ch25_SHIFT (16U)
24752#define HDMI_TX_STTS_BIT_CH2425_channel_num_ch25(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_channel_num_ch25_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_channel_num_ch25_MASK)
24753#define HDMI_TX_STTS_BIT_CH2425_word_length_ch25_MASK (0xF00000U)
24754#define HDMI_TX_STTS_BIT_CH2425_word_length_ch25_SHIFT (20U)
24755#define HDMI_TX_STTS_BIT_CH2425_word_length_ch25(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_word_length_ch25_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_word_length_ch25_MASK)
24756#define HDMI_TX_STTS_BIT_CH2425_valid_bits25_24_MASK (0x3000000U)
24757#define HDMI_TX_STTS_BIT_CH2425_valid_bits25_24_SHIFT (24U)
24758#define HDMI_TX_STTS_BIT_CH2425_valid_bits25_24(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_valid_bits25_24_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_valid_bits25_24_MASK)
24759#define HDMI_TX_STTS_BIT_CH2425_reserved_0_MASK (0xFC000000U)
24760#define HDMI_TX_STTS_BIT_CH2425_reserved_0_SHIFT (26U)
24761#define HDMI_TX_STTS_BIT_CH2425_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_reserved_0_MASK)
24762/*! @} */
24763
24764/*! @name STTS_BIT_CH2627 - */
24765/*! @{ */
24766#define HDMI_TX_STTS_BIT_CH2627_source_num_ch26_MASK (0xFU)
24767#define HDMI_TX_STTS_BIT_CH2627_source_num_ch26_SHIFT (0U)
24768#define HDMI_TX_STTS_BIT_CH2627_source_num_ch26(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_source_num_ch26_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_source_num_ch26_MASK)
24769#define HDMI_TX_STTS_BIT_CH2627_channel_num_ch26_MASK (0xF0U)
24770#define HDMI_TX_STTS_BIT_CH2627_channel_num_ch26_SHIFT (4U)
24771#define HDMI_TX_STTS_BIT_CH2627_channel_num_ch26(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_channel_num_ch26_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_channel_num_ch26_MASK)
24772#define HDMI_TX_STTS_BIT_CH2627_word_length_ch26_MASK (0xF00U)
24773#define HDMI_TX_STTS_BIT_CH2627_word_length_ch26_SHIFT (8U)
24774#define HDMI_TX_STTS_BIT_CH2627_word_length_ch26(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_word_length_ch26_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_word_length_ch26_MASK)
24775#define HDMI_TX_STTS_BIT_CH2627_source_num_ch27_MASK (0xF000U)
24776#define HDMI_TX_STTS_BIT_CH2627_source_num_ch27_SHIFT (12U)
24777#define HDMI_TX_STTS_BIT_CH2627_source_num_ch27(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_source_num_ch27_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_source_num_ch27_MASK)
24778#define HDMI_TX_STTS_BIT_CH2627_channel_num_ch27_MASK (0xF0000U)
24779#define HDMI_TX_STTS_BIT_CH2627_channel_num_ch27_SHIFT (16U)
24780#define HDMI_TX_STTS_BIT_CH2627_channel_num_ch27(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_channel_num_ch27_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_channel_num_ch27_MASK)
24781#define HDMI_TX_STTS_BIT_CH2627_word_length_ch27_MASK (0xF00000U)
24782#define HDMI_TX_STTS_BIT_CH2627_word_length_ch27_SHIFT (20U)
24783#define HDMI_TX_STTS_BIT_CH2627_word_length_ch27(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_word_length_ch27_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_word_length_ch27_MASK)
24784#define HDMI_TX_STTS_BIT_CH2627_valid_bits27_26_MASK (0x3000000U)
24785#define HDMI_TX_STTS_BIT_CH2627_valid_bits27_26_SHIFT (24U)
24786#define HDMI_TX_STTS_BIT_CH2627_valid_bits27_26(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_valid_bits27_26_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_valid_bits27_26_MASK)
24787#define HDMI_TX_STTS_BIT_CH2627_reserved_0_MASK (0xFC000000U)
24788#define HDMI_TX_STTS_BIT_CH2627_reserved_0_SHIFT (26U)
24789#define HDMI_TX_STTS_BIT_CH2627_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_reserved_0_MASK)
24790/*! @} */
24791
24792/*! @name STTS_BIT_CH2829 - */
24793/*! @{ */
24794#define HDMI_TX_STTS_BIT_CH2829_source_num_ch28_MASK (0xFU)
24795#define HDMI_TX_STTS_BIT_CH2829_source_num_ch28_SHIFT (0U)
24796#define HDMI_TX_STTS_BIT_CH2829_source_num_ch28(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_source_num_ch28_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_source_num_ch28_MASK)
24797#define HDMI_TX_STTS_BIT_CH2829_channel_num_ch28_MASK (0xF0U)
24798#define HDMI_TX_STTS_BIT_CH2829_channel_num_ch28_SHIFT (4U)
24799#define HDMI_TX_STTS_BIT_CH2829_channel_num_ch28(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_channel_num_ch28_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_channel_num_ch28_MASK)
24800#define HDMI_TX_STTS_BIT_CH2829_word_length_ch28_MASK (0xF00U)
24801#define HDMI_TX_STTS_BIT_CH2829_word_length_ch28_SHIFT (8U)
24802#define HDMI_TX_STTS_BIT_CH2829_word_length_ch28(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_word_length_ch28_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_word_length_ch28_MASK)
24803#define HDMI_TX_STTS_BIT_CH2829_source_num_ch29_MASK (0xF000U)
24804#define HDMI_TX_STTS_BIT_CH2829_source_num_ch29_SHIFT (12U)
24805#define HDMI_TX_STTS_BIT_CH2829_source_num_ch29(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_source_num_ch29_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_source_num_ch29_MASK)
24806#define HDMI_TX_STTS_BIT_CH2829_channel_num_ch29_MASK (0xF0000U)
24807#define HDMI_TX_STTS_BIT_CH2829_channel_num_ch29_SHIFT (16U)
24808#define HDMI_TX_STTS_BIT_CH2829_channel_num_ch29(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_channel_num_ch29_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_channel_num_ch29_MASK)
24809#define HDMI_TX_STTS_BIT_CH2829_word_length_ch29_MASK (0xF00000U)
24810#define HDMI_TX_STTS_BIT_CH2829_word_length_ch29_SHIFT (20U)
24811#define HDMI_TX_STTS_BIT_CH2829_word_length_ch29(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_word_length_ch29_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_word_length_ch29_MASK)
24812#define HDMI_TX_STTS_BIT_CH2829_valid_bits29_28_MASK (0x3000000U)
24813#define HDMI_TX_STTS_BIT_CH2829_valid_bits29_28_SHIFT (24U)
24814#define HDMI_TX_STTS_BIT_CH2829_valid_bits29_28(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_valid_bits29_28_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_valid_bits29_28_MASK)
24815#define HDMI_TX_STTS_BIT_CH2829_reserved_0_MASK (0xFC000000U)
24816#define HDMI_TX_STTS_BIT_CH2829_reserved_0_SHIFT (26U)
24817#define HDMI_TX_STTS_BIT_CH2829_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_reserved_0_MASK)
24818/*! @} */
24819
24820/*! @name STTS_BIT_CH3031 - */
24821/*! @{ */
24822#define HDMI_TX_STTS_BIT_CH3031_source_num_ch30_MASK (0xFU)
24823#define HDMI_TX_STTS_BIT_CH3031_source_num_ch30_SHIFT (0U)
24824#define HDMI_TX_STTS_BIT_CH3031_source_num_ch30(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_source_num_ch30_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_source_num_ch30_MASK)
24825#define HDMI_TX_STTS_BIT_CH3031_channel_num_ch30_MASK (0xF0U)
24826#define HDMI_TX_STTS_BIT_CH3031_channel_num_ch30_SHIFT (4U)
24827#define HDMI_TX_STTS_BIT_CH3031_channel_num_ch30(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_channel_num_ch30_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_channel_num_ch30_MASK)
24828#define HDMI_TX_STTS_BIT_CH3031_word_length_ch30_MASK (0xF00U)
24829#define HDMI_TX_STTS_BIT_CH3031_word_length_ch30_SHIFT (8U)
24830#define HDMI_TX_STTS_BIT_CH3031_word_length_ch30(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_word_length_ch30_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_word_length_ch30_MASK)
24831#define HDMI_TX_STTS_BIT_CH3031_source_num_ch31_MASK (0xF000U)
24832#define HDMI_TX_STTS_BIT_CH3031_source_num_ch31_SHIFT (12U)
24833#define HDMI_TX_STTS_BIT_CH3031_source_num_ch31(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_source_num_ch31_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_source_num_ch31_MASK)
24834#define HDMI_TX_STTS_BIT_CH3031_channel_num_ch31_MASK (0xF0000U)
24835#define HDMI_TX_STTS_BIT_CH3031_channel_num_ch31_SHIFT (16U)
24836#define HDMI_TX_STTS_BIT_CH3031_channel_num_ch31(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_channel_num_ch31_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_channel_num_ch31_MASK)
24837#define HDMI_TX_STTS_BIT_CH3031_word_length_ch31_MASK (0xF00000U)
24838#define HDMI_TX_STTS_BIT_CH3031_word_length_ch31_SHIFT (20U)
24839#define HDMI_TX_STTS_BIT_CH3031_word_length_ch31(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_word_length_ch31_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_word_length_ch31_MASK)
24840#define HDMI_TX_STTS_BIT_CH3031_valid_bits31_30_MASK (0x3000000U)
24841#define HDMI_TX_STTS_BIT_CH3031_valid_bits31_30_SHIFT (24U)
24842#define HDMI_TX_STTS_BIT_CH3031_valid_bits31_30(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_valid_bits31_30_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_valid_bits31_30_MASK)
24843#define HDMI_TX_STTS_BIT_CH3031_reserved_0_MASK (0xFC000000U)
24844#define HDMI_TX_STTS_BIT_CH3031_reserved_0_SHIFT (26U)
24845#define HDMI_TX_STTS_BIT_CH3031_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_reserved_0_MASK)
24846/*! @} */
24847
24848/*! @name SPDIF_CTRL_ADDR - */
24849/*! @{ */
24850#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_avg_win_MASK (0x7U)
24851#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_avg_win_SHIFT (0U)
24852#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_avg_win(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_avg_win_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_avg_win_MASK)
24853#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_thrsh_MASK (0x7F8U)
24854#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_thrsh_SHIFT (3U)
24855#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_thrsh(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_thrsh_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_thrsh_MASK)
24856#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_fifo_mid_range_MASK (0x7F800U)
24857#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_fifo_mid_range_SHIFT (11U)
24858#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_fifo_mid_range(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_fifo_mid_range_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_fifo_mid_range_MASK)
24859#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_bypass_MASK (0x80000U)
24860#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_bypass_SHIFT (19U)
24861#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_bypass(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_bypass_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_bypass_MASK)
24862#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_avg_sel_MASK (0x100000U)
24863#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_avg_sel_SHIFT (20U)
24864#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_avg_sel(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_avg_sel_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_avg_sel_MASK)
24865#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_enable_MASK (0x200000U)
24866#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_enable_SHIFT (21U)
24867#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_enable(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_enable_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_enable_MASK)
24868#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_status_MASK (0x3C00000U)
24869#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_status_SHIFT (22U)
24870#define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_status(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_status_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_status_MASK)
24871#define HDMI_TX_SPDIF_CTRL_ADDR_reserved_0_MASK (0xFC000000U)
24872#define HDMI_TX_SPDIF_CTRL_ADDR_reserved_0_SHIFT (26U)
24873#define HDMI_TX_SPDIF_CTRL_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_reserved_0_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_reserved_0_MASK)
24874/*! @} */
24875
24876/*! @name SPDIF_CH1_CS_3100_ADDR - */
24877/*! @{ */
24878#define HDMI_TX_SPDIF_CH1_CS_3100_ADDR_spdif_ch1_st_stts_bits3100_MASK (0xFFFFFFFFU)
24879#define HDMI_TX_SPDIF_CH1_CS_3100_ADDR_spdif_ch1_st_stts_bits3100_SHIFT (0U)
24880#define HDMI_TX_SPDIF_CH1_CS_3100_ADDR_spdif_ch1_st_stts_bits3100(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH1_CS_3100_ADDR_spdif_ch1_st_stts_bits3100_SHIFT)) & HDMI_TX_SPDIF_CH1_CS_3100_ADDR_spdif_ch1_st_stts_bits3100_MASK)
24881/*! @} */
24882
24883/*! @name SPDIF_CH1_CS_6332_ADDR - */
24884/*! @{ */
24885#define HDMI_TX_SPDIF_CH1_CS_6332_ADDR_spdif_ch1_st_stts_bits6332_MASK (0xFFFFFFFFU)
24886#define HDMI_TX_SPDIF_CH1_CS_6332_ADDR_spdif_ch1_st_stts_bits6332_SHIFT (0U)
24887#define HDMI_TX_SPDIF_CH1_CS_6332_ADDR_spdif_ch1_st_stts_bits6332(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH1_CS_6332_ADDR_spdif_ch1_st_stts_bits6332_SHIFT)) & HDMI_TX_SPDIF_CH1_CS_6332_ADDR_spdif_ch1_st_stts_bits6332_MASK)
24888/*! @} */
24889
24890/*! @name SPDIF_CH1_CS_9564_ADDR - */
24891/*! @{ */
24892#define HDMI_TX_SPDIF_CH1_CS_9564_ADDR_spdif_ch1_st_stts_bits9564_MASK (0xFFFFFFFFU)
24893#define HDMI_TX_SPDIF_CH1_CS_9564_ADDR_spdif_ch1_st_stts_bits9564_SHIFT (0U)
24894#define HDMI_TX_SPDIF_CH1_CS_9564_ADDR_spdif_ch1_st_stts_bits9564(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH1_CS_9564_ADDR_spdif_ch1_st_stts_bits9564_SHIFT)) & HDMI_TX_SPDIF_CH1_CS_9564_ADDR_spdif_ch1_st_stts_bits9564_MASK)
24895/*! @} */
24896
24897/*! @name SPDIF_CH1_CS_12796_ADDR - */
24898/*! @{ */
24899#define HDMI_TX_SPDIF_CH1_CS_12796_ADDR_spdif_ch1_st_stts_bits12796_MASK (0xFFFFFFFFU)
24900#define HDMI_TX_SPDIF_CH1_CS_12796_ADDR_spdif_ch1_st_stts_bits12796_SHIFT (0U)
24901#define HDMI_TX_SPDIF_CH1_CS_12796_ADDR_spdif_ch1_st_stts_bits12796(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH1_CS_12796_ADDR_spdif_ch1_st_stts_bits12796_SHIFT)) & HDMI_TX_SPDIF_CH1_CS_12796_ADDR_spdif_ch1_st_stts_bits12796_MASK)
24902/*! @} */
24903
24904/*! @name SPDIF_CH1_CS_159128_ADDR - */
24905/*! @{ */
24906#define HDMI_TX_SPDIF_CH1_CS_159128_ADDR_spdif_ch1_st_stts_bits159128_MASK (0xFFFFFFFFU)
24907#define HDMI_TX_SPDIF_CH1_CS_159128_ADDR_spdif_ch1_st_stts_bits159128_SHIFT (0U)
24908#define HDMI_TX_SPDIF_CH1_CS_159128_ADDR_spdif_ch1_st_stts_bits159128(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH1_CS_159128_ADDR_spdif_ch1_st_stts_bits159128_SHIFT)) & HDMI_TX_SPDIF_CH1_CS_159128_ADDR_spdif_ch1_st_stts_bits159128_MASK)
24909/*! @} */
24910
24911/*! @name SPDIF_CH1_CS_191160_ADDR - */
24912/*! @{ */
24913#define HDMI_TX_SPDIF_CH1_CS_191160_ADDR_spdif_ch1_st_stts_bits191160_MASK (0xFFFFFFFFU)
24914#define HDMI_TX_SPDIF_CH1_CS_191160_ADDR_spdif_ch1_st_stts_bits191160_SHIFT (0U)
24915#define HDMI_TX_SPDIF_CH1_CS_191160_ADDR_spdif_ch1_st_stts_bits191160(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH1_CS_191160_ADDR_spdif_ch1_st_stts_bits191160_SHIFT)) & HDMI_TX_SPDIF_CH1_CS_191160_ADDR_spdif_ch1_st_stts_bits191160_MASK)
24916/*! @} */
24917
24918/*! @name SPDIF_CH2_CS_3100_ADDR - */
24919/*! @{ */
24920#define HDMI_TX_SPDIF_CH2_CS_3100_ADDR_spdif_ch2_st_stts_bits3100_MASK (0xFFFFFFFFU)
24921#define HDMI_TX_SPDIF_CH2_CS_3100_ADDR_spdif_ch2_st_stts_bits3100_SHIFT (0U)
24922#define HDMI_TX_SPDIF_CH2_CS_3100_ADDR_spdif_ch2_st_stts_bits3100(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH2_CS_3100_ADDR_spdif_ch2_st_stts_bits3100_SHIFT)) & HDMI_TX_SPDIF_CH2_CS_3100_ADDR_spdif_ch2_st_stts_bits3100_MASK)
24923/*! @} */
24924
24925/*! @name SPDIF_CH2_CS_6332_ADDR - */
24926/*! @{ */
24927#define HDMI_TX_SPDIF_CH2_CS_6332_ADDR_spdif_ch2_st_stts_bits6332_MASK (0xFFFFFFFFU)
24928#define HDMI_TX_SPDIF_CH2_CS_6332_ADDR_spdif_ch2_st_stts_bits6332_SHIFT (0U)
24929#define HDMI_TX_SPDIF_CH2_CS_6332_ADDR_spdif_ch2_st_stts_bits6332(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH2_CS_6332_ADDR_spdif_ch2_st_stts_bits6332_SHIFT)) & HDMI_TX_SPDIF_CH2_CS_6332_ADDR_spdif_ch2_st_stts_bits6332_MASK)
24930/*! @} */
24931
24932/*! @name SPDIF_CH2_CS_9564_ADDR - */
24933/*! @{ */
24934#define HDMI_TX_SPDIF_CH2_CS_9564_ADDR_spdif_ch2_st_stts_bits9564_MASK (0xFFFFFFFFU)
24935#define HDMI_TX_SPDIF_CH2_CS_9564_ADDR_spdif_ch2_st_stts_bits9564_SHIFT (0U)
24936#define HDMI_TX_SPDIF_CH2_CS_9564_ADDR_spdif_ch2_st_stts_bits9564(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH2_CS_9564_ADDR_spdif_ch2_st_stts_bits9564_SHIFT)) & HDMI_TX_SPDIF_CH2_CS_9564_ADDR_spdif_ch2_st_stts_bits9564_MASK)
24937/*! @} */
24938
24939/*! @name SPDIF_CH2_CS_12796_ADDR - */
24940/*! @{ */
24941#define HDMI_TX_SPDIF_CH2_CS_12796_ADDR_spdif_ch2_st_stts_bits12796_MASK (0xFFFFFFFFU)
24942#define HDMI_TX_SPDIF_CH2_CS_12796_ADDR_spdif_ch2_st_stts_bits12796_SHIFT (0U)
24943#define HDMI_TX_SPDIF_CH2_CS_12796_ADDR_spdif_ch2_st_stts_bits12796(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH2_CS_12796_ADDR_spdif_ch2_st_stts_bits12796_SHIFT)) & HDMI_TX_SPDIF_CH2_CS_12796_ADDR_spdif_ch2_st_stts_bits12796_MASK)
24944/*! @} */
24945
24946/*! @name SPDIF_CH2_CS_159128_ADDR - */
24947/*! @{ */
24948#define HDMI_TX_SPDIF_CH2_CS_159128_ADDR_spdif_ch2_st_stts_bits159128_MASK (0xFFFFFFFFU)
24949#define HDMI_TX_SPDIF_CH2_CS_159128_ADDR_spdif_ch2_st_stts_bits159128_SHIFT (0U)
24950#define HDMI_TX_SPDIF_CH2_CS_159128_ADDR_spdif_ch2_st_stts_bits159128(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH2_CS_159128_ADDR_spdif_ch2_st_stts_bits159128_SHIFT)) & HDMI_TX_SPDIF_CH2_CS_159128_ADDR_spdif_ch2_st_stts_bits159128_MASK)
24951/*! @} */
24952
24953/*! @name SPDIF_CH2_CS_191160_ADDR - */
24954/*! @{ */
24955#define HDMI_TX_SPDIF_CH2_CS_191160_ADDR_spdif_ch2_st_stts_bits191160_MASK (0xFFFFFFFFU)
24956#define HDMI_TX_SPDIF_CH2_CS_191160_ADDR_spdif_ch2_st_stts_bits191160_SHIFT (0U)
24957#define HDMI_TX_SPDIF_CH2_CS_191160_ADDR_spdif_ch2_st_stts_bits191160(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH2_CS_191160_ADDR_spdif_ch2_st_stts_bits191160_SHIFT)) & HDMI_TX_SPDIF_CH2_CS_191160_ADDR_spdif_ch2_st_stts_bits191160_MASK)
24958/*! @} */
24959
24960/*! @name SMPL2PKT_CNTL - */
24961/*! @{ */
24962#define HDMI_TX_SMPL2PKT_CNTL_sw_rst_MASK (0x1U)
24963#define HDMI_TX_SMPL2PKT_CNTL_sw_rst_SHIFT (0U)
24964#define HDMI_TX_SMPL2PKT_CNTL_sw_rst(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNTL_sw_rst_SHIFT)) & HDMI_TX_SMPL2PKT_CNTL_sw_rst_MASK)
24965#define HDMI_TX_SMPL2PKT_CNTL_smpl2pkt_en_MASK (0x2U)
24966#define HDMI_TX_SMPL2PKT_CNTL_smpl2pkt_en_SHIFT (1U)
24967#define HDMI_TX_SMPL2PKT_CNTL_smpl2pkt_en(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNTL_smpl2pkt_en_SHIFT)) & HDMI_TX_SMPL2PKT_CNTL_smpl2pkt_en_MASK)
24968#define HDMI_TX_SMPL2PKT_CNTL_reserved_0_MASK (0xFFFFFFFCU)
24969#define HDMI_TX_SMPL2PKT_CNTL_reserved_0_SHIFT (2U)
24970#define HDMI_TX_SMPL2PKT_CNTL_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNTL_reserved_0_SHIFT)) & HDMI_TX_SMPL2PKT_CNTL_reserved_0_MASK)
24971/*! @} */
24972
24973/*! @name SMPL2PKT_CNFG - */
24974/*! @{ */
24975#define HDMI_TX_SMPL2PKT_CNFG_max_num_ch_MASK (0x1FU)
24976#define HDMI_TX_SMPL2PKT_CNFG_max_num_ch_SHIFT (0U)
24977#define HDMI_TX_SMPL2PKT_CNFG_max_num_ch(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_max_num_ch_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_max_num_ch_MASK)
24978#define HDMI_TX_SMPL2PKT_CNFG_num_of_i2s_ports_MASK (0x60U)
24979#define HDMI_TX_SMPL2PKT_CNFG_num_of_i2s_ports_SHIFT (5U)
24980#define HDMI_TX_SMPL2PKT_CNFG_num_of_i2s_ports(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_num_of_i2s_ports_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_num_of_i2s_ports_MASK)
24981#define HDMI_TX_SMPL2PKT_CNFG_audio_type_MASK (0x780U)
24982#define HDMI_TX_SMPL2PKT_CNFG_audio_type_SHIFT (7U)
24983#define HDMI_TX_SMPL2PKT_CNFG_audio_type(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_audio_type_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_audio_type_MASK)
24984#define HDMI_TX_SMPL2PKT_CNFG_cfg_sub_pckt_num_MASK (0x3800U)
24985#define HDMI_TX_SMPL2PKT_CNFG_cfg_sub_pckt_num_SHIFT (11U)
24986#define HDMI_TX_SMPL2PKT_CNFG_cfg_sub_pckt_num(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_cfg_sub_pckt_num_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_cfg_sub_pckt_num_MASK)
24987#define HDMI_TX_SMPL2PKT_CNFG_cfg_block_lpcm_first_pkt_MASK (0x4000U)
24988#define HDMI_TX_SMPL2PKT_CNFG_cfg_block_lpcm_first_pkt_SHIFT (14U)
24989#define HDMI_TX_SMPL2PKT_CNFG_cfg_block_lpcm_first_pkt(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_cfg_block_lpcm_first_pkt_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_cfg_block_lpcm_first_pkt_MASK)
24990#define HDMI_TX_SMPL2PKT_CNFG_cfg_en_auto_sub_pckt_num_MASK (0x8000U)
24991#define HDMI_TX_SMPL2PKT_CNFG_cfg_en_auto_sub_pckt_num_SHIFT (15U)
24992#define HDMI_TX_SMPL2PKT_CNFG_cfg_en_auto_sub_pckt_num(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_cfg_en_auto_sub_pckt_num_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_cfg_en_auto_sub_pckt_num_MASK)
24993#define HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_MASK (0xF0000U)
24994#define HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_SHIFT (16U)
24995#define HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_MASK)
24996#define HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_force_MASK (0x100000U)
24997#define HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_force_SHIFT (20U)
24998#define HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_force(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_force_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_force_MASK)
24999#define HDMI_TX_SMPL2PKT_CNFG_reserved_0_MASK (0xFFE00000U)
25000#define HDMI_TX_SMPL2PKT_CNFG_reserved_0_SHIFT (21U)
25001#define HDMI_TX_SMPL2PKT_CNFG_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_reserved_0_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_reserved_0_MASK)
25002/*! @} */
25003
25004/*! @name FIFO_CNTL - */
25005/*! @{ */
25006#define HDMI_TX_FIFO_CNTL_fifo_sw_rst_MASK (0x1U)
25007#define HDMI_TX_FIFO_CNTL_fifo_sw_rst_SHIFT (0U)
25008#define HDMI_TX_FIFO_CNTL_fifo_sw_rst(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_CNTL_fifo_sw_rst_SHIFT)) & HDMI_TX_FIFO_CNTL_fifo_sw_rst_MASK)
25009#define HDMI_TX_FIFO_CNTL_sync_wr_to_ch_zero_MASK (0x2U)
25010#define HDMI_TX_FIFO_CNTL_sync_wr_to_ch_zero_SHIFT (1U)
25011#define HDMI_TX_FIFO_CNTL_sync_wr_to_ch_zero(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_CNTL_sync_wr_to_ch_zero_SHIFT)) & HDMI_TX_FIFO_CNTL_sync_wr_to_ch_zero_MASK)
25012#define HDMI_TX_FIFO_CNTL_fifo_dir_MASK (0x4U)
25013#define HDMI_TX_FIFO_CNTL_fifo_dir_SHIFT (2U)
25014#define HDMI_TX_FIFO_CNTL_fifo_dir(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_CNTL_fifo_dir_SHIFT)) & HDMI_TX_FIFO_CNTL_fifo_dir_MASK)
25015#define HDMI_TX_FIFO_CNTL_fifo_empty_calc_MASK (0x8U)
25016#define HDMI_TX_FIFO_CNTL_fifo_empty_calc_SHIFT (3U)
25017#define HDMI_TX_FIFO_CNTL_fifo_empty_calc(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_CNTL_fifo_empty_calc_SHIFT)) & HDMI_TX_FIFO_CNTL_fifo_empty_calc_MASK)
25018#define HDMI_TX_FIFO_CNTL_cfg_dis_port3_MASK (0x10U)
25019#define HDMI_TX_FIFO_CNTL_cfg_dis_port3_SHIFT (4U)
25020#define HDMI_TX_FIFO_CNTL_cfg_dis_port3(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_CNTL_cfg_dis_port3_SHIFT)) & HDMI_TX_FIFO_CNTL_cfg_dis_port3_MASK)
25021#define HDMI_TX_FIFO_CNTL_reserved_0_MASK (0xFFFFFFE0U)
25022#define HDMI_TX_FIFO_CNTL_reserved_0_SHIFT (5U)
25023#define HDMI_TX_FIFO_CNTL_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_CNTL_reserved_0_SHIFT)) & HDMI_TX_FIFO_CNTL_reserved_0_MASK)
25024/*! @} */
25025
25026/*! @name FIFO_STTS - */
25027/*! @{ */
25028#define HDMI_TX_FIFO_STTS_wfull_MASK (0x1U)
25029#define HDMI_TX_FIFO_STTS_wfull_SHIFT (0U)
25030#define HDMI_TX_FIFO_STTS_wfull(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_STTS_wfull_SHIFT)) & HDMI_TX_FIFO_STTS_wfull_MASK)
25031#define HDMI_TX_FIFO_STTS_rempty_MASK (0x2U)
25032#define HDMI_TX_FIFO_STTS_rempty_SHIFT (1U)
25033#define HDMI_TX_FIFO_STTS_rempty(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_STTS_rempty_SHIFT)) & HDMI_TX_FIFO_STTS_rempty_MASK)
25034#define HDMI_TX_FIFO_STTS_overrun_MASK (0x4U)
25035#define HDMI_TX_FIFO_STTS_overrun_SHIFT (2U)
25036#define HDMI_TX_FIFO_STTS_overrun(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_STTS_overrun_SHIFT)) & HDMI_TX_FIFO_STTS_overrun_MASK)
25037#define HDMI_TX_FIFO_STTS_underrun_MASK (0x8U)
25038#define HDMI_TX_FIFO_STTS_underrun_SHIFT (3U)
25039#define HDMI_TX_FIFO_STTS_underrun(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_STTS_underrun_SHIFT)) & HDMI_TX_FIFO_STTS_underrun_MASK)
25040#define HDMI_TX_FIFO_STTS_reserved_0_MASK (0xFFFFFFF0U)
25041#define HDMI_TX_FIFO_STTS_reserved_0_SHIFT (4U)
25042#define HDMI_TX_FIFO_STTS_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_STTS_reserved_0_SHIFT)) & HDMI_TX_FIFO_STTS_reserved_0_MASK)
25043/*! @} */
25044
25045/*! @name SUB_PCKT_THRSH - */
25046/*! @{ */
25047#define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh1_MASK (0xFFU)
25048#define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh1_SHIFT (0U)
25049#define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh1(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh1_SHIFT)) & HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh1_MASK)
25050#define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh2_MASK (0xFF00U)
25051#define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh2_SHIFT (8U)
25052#define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh2(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh2_SHIFT)) & HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh2_MASK)
25053#define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh3_MASK (0xFF0000U)
25054#define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh3_SHIFT (16U)
25055#define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh3(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh3_SHIFT)) & HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh3_MASK)
25056#define HDMI_TX_SUB_PCKT_THRSH_reserved_0_MASK (0xFF000000U)
25057#define HDMI_TX_SUB_PCKT_THRSH_reserved_0_SHIFT (24U)
25058#define HDMI_TX_SUB_PCKT_THRSH_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SUB_PCKT_THRSH_reserved_0_SHIFT)) & HDMI_TX_SUB_PCKT_THRSH_reserved_0_MASK)
25059/*! @} */
25060
25061/*! @name SOURCE_PIF_WR_ADDR - */
25062/*! @{ */
25063#define HDMI_TX_SOURCE_PIF_WR_ADDR_wr_addr_MASK (0xFU)
25064#define HDMI_TX_SOURCE_PIF_WR_ADDR_wr_addr_SHIFT (0U)
25065#define HDMI_TX_SOURCE_PIF_WR_ADDR_wr_addr(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_WR_ADDR_wr_addr_SHIFT)) & HDMI_TX_SOURCE_PIF_WR_ADDR_wr_addr_MASK)
25066#define HDMI_TX_SOURCE_PIF_WR_ADDR_reserved_0_MASK (0xFFFFFFF0U)
25067#define HDMI_TX_SOURCE_PIF_WR_ADDR_reserved_0_SHIFT (4U)
25068#define HDMI_TX_SOURCE_PIF_WR_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_WR_ADDR_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_WR_ADDR_reserved_0_MASK)
25069/*! @} */
25070
25071/*! @name SOURCE_PIF_WR_REQ - */
25072/*! @{ */
25073#define HDMI_TX_SOURCE_PIF_WR_REQ_host_wr_MASK (0x1U)
25074#define HDMI_TX_SOURCE_PIF_WR_REQ_host_wr_SHIFT (0U)
25075#define HDMI_TX_SOURCE_PIF_WR_REQ_host_wr(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_WR_REQ_host_wr_SHIFT)) & HDMI_TX_SOURCE_PIF_WR_REQ_host_wr_MASK)
25076#define HDMI_TX_SOURCE_PIF_WR_REQ_reserved_0_MASK (0xFFFFFFFEU)
25077#define HDMI_TX_SOURCE_PIF_WR_REQ_reserved_0_SHIFT (1U)
25078#define HDMI_TX_SOURCE_PIF_WR_REQ_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_WR_REQ_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_WR_REQ_reserved_0_MASK)
25079/*! @} */
25080
25081/*! @name SOURCE_PIF_RD_ADDR - */
25082/*! @{ */
25083#define HDMI_TX_SOURCE_PIF_RD_ADDR_rd_addr_MASK (0xFU)
25084#define HDMI_TX_SOURCE_PIF_RD_ADDR_rd_addr_SHIFT (0U)
25085#define HDMI_TX_SOURCE_PIF_RD_ADDR_rd_addr(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_RD_ADDR_rd_addr_SHIFT)) & HDMI_TX_SOURCE_PIF_RD_ADDR_rd_addr_MASK)
25086#define HDMI_TX_SOURCE_PIF_RD_ADDR_reserved_0_MASK (0xFFFFFFF0U)
25087#define HDMI_TX_SOURCE_PIF_RD_ADDR_reserved_0_SHIFT (4U)
25088#define HDMI_TX_SOURCE_PIF_RD_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_RD_ADDR_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_RD_ADDR_reserved_0_MASK)
25089/*! @} */
25090
25091/*! @name SOURCE_PIF_RD_REQ - */
25092/*! @{ */
25093#define HDMI_TX_SOURCE_PIF_RD_REQ_host_rd_MASK (0x1U)
25094#define HDMI_TX_SOURCE_PIF_RD_REQ_host_rd_SHIFT (0U)
25095#define HDMI_TX_SOURCE_PIF_RD_REQ_host_rd(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_RD_REQ_host_rd_SHIFT)) & HDMI_TX_SOURCE_PIF_RD_REQ_host_rd_MASK)
25096#define HDMI_TX_SOURCE_PIF_RD_REQ_reserved_0_MASK (0xFFFFFFFEU)
25097#define HDMI_TX_SOURCE_PIF_RD_REQ_reserved_0_SHIFT (1U)
25098#define HDMI_TX_SOURCE_PIF_RD_REQ_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_RD_REQ_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_RD_REQ_reserved_0_MASK)
25099/*! @} */
25100
25101/*! @name SOURCE_PIF_DATA_WR - */
25102/*! @{ */
25103#define HDMI_TX_SOURCE_PIF_DATA_WR_data_wr_MASK (0xFFFFFFFFU)
25104#define HDMI_TX_SOURCE_PIF_DATA_WR_data_wr_SHIFT (0U)
25105#define HDMI_TX_SOURCE_PIF_DATA_WR_data_wr(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_DATA_WR_data_wr_SHIFT)) & HDMI_TX_SOURCE_PIF_DATA_WR_data_wr_MASK)
25106/*! @} */
25107
25108/*! @name SOURCE_PIF_DATA_RD - */
25109/*! @{ */
25110#define HDMI_TX_SOURCE_PIF_DATA_RD_fifo2_data_out_MASK (0xFFFFFFFFU)
25111#define HDMI_TX_SOURCE_PIF_DATA_RD_fifo2_data_out_SHIFT (0U)
25112#define HDMI_TX_SOURCE_PIF_DATA_RD_fifo2_data_out(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_DATA_RD_fifo2_data_out_SHIFT)) & HDMI_TX_SOURCE_PIF_DATA_RD_fifo2_data_out_MASK)
25113/*! @} */
25114
25115/*! @name SOURCE_PIF_FIFO1_FLUSH - */
25116/*! @{ */
25117#define HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_fifo1_flush_MASK (0x1U)
25118#define HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_fifo1_flush_SHIFT (0U)
25119#define HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_fifo1_flush(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_fifo1_flush_SHIFT)) & HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_fifo1_flush_MASK)
25120#define HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_reserved_0_MASK (0xFFFFFFFEU)
25121#define HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_reserved_0_SHIFT (1U)
25122#define HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_reserved_0_MASK)
25123/*! @} */
25124
25125/*! @name SOURCE_PIF_FIFO2_FLUSH - */
25126/*! @{ */
25127#define HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_fifo2_flush_MASK (0x1U)
25128#define HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_fifo2_flush_SHIFT (0U)
25129#define HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_fifo2_flush(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_fifo2_flush_SHIFT)) & HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_fifo2_flush_MASK)
25130#define HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_reserved_0_MASK (0xFFFFFFFEU)
25131#define HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_reserved_0_SHIFT (1U)
25132#define HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_reserved_0_MASK)
25133/*! @} */
25134
25135/*! @name SOURCE_PIF_STATUS - */
25136/*! @{ */
25137#define HDMI_TX_SOURCE_PIF_STATUS_source_pkt_mem_ctrl_fsm_state_MASK (0x3U)
25138#define HDMI_TX_SOURCE_PIF_STATUS_source_pkt_mem_ctrl_fsm_state_SHIFT (0U)
25139#define HDMI_TX_SOURCE_PIF_STATUS_source_pkt_mem_ctrl_fsm_state(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_STATUS_source_pkt_mem_ctrl_fsm_state_SHIFT)) & HDMI_TX_SOURCE_PIF_STATUS_source_pkt_mem_ctrl_fsm_state_MASK)
25140#define HDMI_TX_SOURCE_PIF_STATUS_fifo1_full_MASK (0x4U)
25141#define HDMI_TX_SOURCE_PIF_STATUS_fifo1_full_SHIFT (2U)
25142#define HDMI_TX_SOURCE_PIF_STATUS_fifo1_full(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_STATUS_fifo1_full_SHIFT)) & HDMI_TX_SOURCE_PIF_STATUS_fifo1_full_MASK)
25143#define HDMI_TX_SOURCE_PIF_STATUS_fifo2_empty_MASK (0x8U)
25144#define HDMI_TX_SOURCE_PIF_STATUS_fifo2_empty_SHIFT (3U)
25145#define HDMI_TX_SOURCE_PIF_STATUS_fifo2_empty(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_STATUS_fifo2_empty_SHIFT)) & HDMI_TX_SOURCE_PIF_STATUS_fifo2_empty_MASK)
25146#define HDMI_TX_SOURCE_PIF_STATUS_reserved_0_MASK (0xFFFFFFF0U)
25147#define HDMI_TX_SOURCE_PIF_STATUS_reserved_0_SHIFT (4U)
25148#define HDMI_TX_SOURCE_PIF_STATUS_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_STATUS_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_STATUS_reserved_0_MASK)
25149/*! @} */
25150
25151/*! @name SOURCE_PIF_INTERRUPT_SOURCE - */
25152/*! @{ */
25153#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_wr_done_int_MASK (0x1U)
25154#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_wr_done_int_SHIFT (0U)
25155#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_wr_done_int(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_wr_done_int_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_wr_done_int_MASK)
25156#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_rd_done_int_MASK (0x2U)
25157#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_rd_done_int_SHIFT (1U)
25158#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_rd_done_int(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_rd_done_int_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_rd_done_int_MASK)
25159#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_nonvalid_type_requested_int_MASK (0x4U)
25160#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_nonvalid_type_requested_int_SHIFT (2U)
25161#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_nonvalid_type_requested_int(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_nonvalid_type_requested_int_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_nonvalid_type_requested_int_MASK)
25162#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_pslverr_MASK (0x8U)
25163#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_pslverr_SHIFT (3U)
25164#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_pslverr(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_pslverr_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_pslverr_MASK)
25165#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_done_MASK (0x10U)
25166#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_done_SHIFT (4U)
25167#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_done(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_done_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_done_MASK)
25168#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_error_MASK (0x20U)
25169#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_error_SHIFT (5U)
25170#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_error(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_error_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_error_MASK)
25171#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_overflow_MASK (0x40U)
25172#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_overflow_SHIFT (6U)
25173#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_overflow(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_overflow_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_overflow_MASK)
25174#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_underflow_MASK (0x80U)
25175#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_underflow_SHIFT (7U)
25176#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_underflow(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_underflow_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_underflow_MASK)
25177#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_overflow_MASK (0x100U)
25178#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_overflow_SHIFT (8U)
25179#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_overflow(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_overflow_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_overflow_MASK)
25180#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_underflow_MASK (0x200U)
25181#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_underflow_SHIFT (9U)
25182#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_underflow(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_underflow_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_underflow_MASK)
25183#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_reserved_0_MASK (0xFFFFFC00U)
25184#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_reserved_0_SHIFT (10U)
25185#define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_reserved_0_MASK)
25186/*! @} */
25187
25188/*! @name SOURCE_PIF_INTERRUPT_MASK - */
25189/*! @{ */
25190#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_wr_done_int_mask_MASK (0x1U)
25191#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_wr_done_int_mask_SHIFT (0U)
25192#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_wr_done_int_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_wr_done_int_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_wr_done_int_mask_MASK)
25193#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_rd_done_int_mask_MASK (0x2U)
25194#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_rd_done_int_mask_SHIFT (1U)
25195#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_rd_done_int_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_rd_done_int_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_rd_done_int_mask_MASK)
25196#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_nonvalid_type_requested_int_mask_MASK (0x4U)
25197#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_nonvalid_type_requested_int_mask_SHIFT (2U)
25198#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_nonvalid_type_requested_int_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_nonvalid_type_requested_int_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_nonvalid_type_requested_int_mask_MASK)
25199#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_pslverr_mask_MASK (0x8U)
25200#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_pslverr_mask_SHIFT (3U)
25201#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_pslverr_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_pslverr_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_pslverr_mask_MASK)
25202#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_done_mask_MASK (0x10U)
25203#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_done_mask_SHIFT (4U)
25204#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_done_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_done_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_done_mask_MASK)
25205#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_error_mask_MASK (0x20U)
25206#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_error_mask_SHIFT (5U)
25207#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_error_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_error_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_error_mask_MASK)
25208#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_overflow_mask_MASK (0x40U)
25209#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_overflow_mask_SHIFT (6U)
25210#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_overflow_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_overflow_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_overflow_mask_MASK)
25211#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_underflow_mask_MASK (0x80U)
25212#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_underflow_mask_SHIFT (7U)
25213#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_underflow_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_underflow_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_underflow_mask_MASK)
25214#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_overflow_mask_MASK (0x100U)
25215#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_overflow_mask_SHIFT (8U)
25216#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_overflow_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_overflow_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_overflow_mask_MASK)
25217#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_underflow_mask_MASK (0x200U)
25218#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_underflow_mask_SHIFT (9U)
25219#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_underflow_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_underflow_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_underflow_mask_MASK)
25220#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_reserved_0_MASK (0xFFFFFC00U)
25221#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_reserved_0_SHIFT (10U)
25222#define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_reserved_0_MASK)
25223/*! @} */
25224
25225/*! @name SOURCE_PIF_PKT_ALLOC_REG - */
25226/*! @{ */
25227#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_pkt_alloc_address_MASK (0xFU)
25228#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_pkt_alloc_address_SHIFT (0U)
25229#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_pkt_alloc_address(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_pkt_alloc_address_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_pkt_alloc_address_MASK)
25230#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_0_MASK (0xF0U)
25231#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_0_SHIFT (4U)
25232#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_0_MASK)
25233#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_packet_type_MASK (0xFF00U)
25234#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_packet_type_SHIFT (8U)
25235#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_packet_type(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_packet_type_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_packet_type_MASK)
25236#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_type_valid_MASK (0x10000U)
25237#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_type_valid_SHIFT (16U)
25238#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_type_valid(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_type_valid_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_type_valid_MASK)
25239#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_active_idle_type_MASK (0x20000U)
25240#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_active_idle_type_SHIFT (17U)
25241#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_active_idle_type(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_active_idle_type_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_active_idle_type_MASK)
25242#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_1_MASK (0xFFFC0000U)
25243#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_1_SHIFT (18U)
25244#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_1(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_1_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_1_MASK)
25245/*! @} */
25246
25247/*! @name SOURCE_PIF_PKT_ALLOC_WR_EN - */
25248/*! @{ */
25249#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_pkt_alloc_wr_en_MASK (0x1U)
25250#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_pkt_alloc_wr_en_SHIFT (0U)
25251#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_pkt_alloc_wr_en(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_pkt_alloc_wr_en_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_pkt_alloc_wr_en_MASK)
25252#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_reserved_0_MASK (0xFFFFFFFEU)
25253#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_reserved_0_SHIFT (1U)
25254#define HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_reserved_0_MASK)
25255/*! @} */
25256
25257/*! @name SOURCE_PIF_SW_RESET - */
25258/*! @{ */
25259#define HDMI_TX_SOURCE_PIF_SW_RESET_sw_rst_MASK (0x1U)
25260#define HDMI_TX_SOURCE_PIF_SW_RESET_sw_rst_SHIFT (0U)
25261#define HDMI_TX_SOURCE_PIF_SW_RESET_sw_rst(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_SW_RESET_sw_rst_SHIFT)) & HDMI_TX_SOURCE_PIF_SW_RESET_sw_rst_MASK)
25262#define HDMI_TX_SOURCE_PIF_SW_RESET_reserved_0_MASK (0xFFFFFFFEU)
25263#define HDMI_TX_SOURCE_PIF_SW_RESET_reserved_0_SHIFT (1U)
25264#define HDMI_TX_SOURCE_PIF_SW_RESET_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_SW_RESET_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_SW_RESET_reserved_0_MASK)
25265/*! @} */
25266
25267
25268/*!
25269 * @}
25270 */ /* end of group HDMI_TX_Register_Masks */
25271
25272
25273/* HDMI_TX - Peripheral instance base addresses */
25274/** Peripheral HDMI_TX base address */
25275#define HDMI_TX_BASE (0x32C00000u)
25276/** Peripheral HDMI_TX base pointer */
25277#define HDMI_TX ((HDMI_TX_Type *)HDMI_TX_BASE)
25278/** Array initializer of HDMI_TX peripheral base addresses */
25279#define HDMI_TX_BASE_ADDRS { HDMI_TX_BASE }
25280/** Array initializer of HDMI_TX peripheral base pointers */
25281#define HDMI_TX_BASE_PTRS { HDMI_TX }
25282
25283/*!
25284 * @}
25285 */ /* end of group HDMI_TX_Peripheral_Access_Layer */
25286
25287
25288/* ----------------------------------------------------------------------------
25289 -- I2C Peripheral Access Layer
25290 ---------------------------------------------------------------------------- */
25291
25292/*!
25293 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
25294 * @{
25295 */
25296
25297/** I2C - Register Layout Typedef */
25298typedef struct {
25299 __IO uint16_t IADR; /**< I2C Address Register, offset: 0x0 */
25300 uint8_t RESERVED_0[2];
25301 __IO uint16_t IFDR; /**< I2C Frequency Divider Register, offset: 0x4 */
25302 uint8_t RESERVED_1[2];
25303 __IO uint16_t I2CR; /**< I2C Control Register, offset: 0x8 */
25304 uint8_t RESERVED_2[2];
25305 __IO uint16_t I2SR; /**< I2C Status Register, offset: 0xC */
25306 uint8_t RESERVED_3[2];
25307 __IO uint16_t I2DR; /**< I2C Data I/O Register, offset: 0x10 */
25308} I2C_Type;
25309
25310/* ----------------------------------------------------------------------------
25311 -- I2C Register Masks
25312 ---------------------------------------------------------------------------- */
25313
25314/*!
25315 * @addtogroup I2C_Register_Masks I2C Register Masks
25316 * @{
25317 */
25318
25319/*! @name IADR - I2C Address Register */
25320/*! @{ */
25321#define I2C_IADR_ADR_MASK (0xFEU)
25322#define I2C_IADR_ADR_SHIFT (1U)
25323#define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x)) << I2C_IADR_ADR_SHIFT)) & I2C_IADR_ADR_MASK)
25324/*! @} */
25325
25326/*! @name IFDR - I2C Frequency Divider Register */
25327/*! @{ */
25328#define I2C_IFDR_IC_MASK (0x3FU)
25329#define I2C_IFDR_IC_SHIFT (0U)
25330#define I2C_IFDR_IC(x) (((uint16_t)(((uint16_t)(x)) << I2C_IFDR_IC_SHIFT)) & I2C_IFDR_IC_MASK)
25331/*! @} */
25332
25333/*! @name I2CR - I2C Control Register */
25334/*! @{ */
25335#define I2C_I2CR_RSTA_MASK (0x4U)
25336#define I2C_I2CR_RSTA_SHIFT (2U)
25337/*! RSTA
25338 * 0b0..No repeat start
25339 * 0b1..Generates a Repeated Start condition
25340 */
25341#define I2C_I2CR_RSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_RSTA_SHIFT)) & I2C_I2CR_RSTA_MASK)
25342#define I2C_I2CR_TXAK_MASK (0x8U)
25343#define I2C_I2CR_TXAK_SHIFT (3U)
25344/*! TXAK
25345 * 0b0..An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data.
25346 * 0b1..No acknowledge signal response is sent (that is, the acknowledge bit = 1).
25347 */
25348#define I2C_I2CR_TXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_TXAK_SHIFT)) & I2C_I2CR_TXAK_MASK)
25349#define I2C_I2CR_MTX_MASK (0x10U)
25350#define I2C_I2CR_MTX_SHIFT (4U)
25351/*! MTX
25352 * 0b0..Receive.When a slave is addressed, the software should set MTX according to the slave read/write bit in the I2C status register (I2C_I2SR[SRW]).
25353 * 0b1..Transmit.In Master mode, MTX should be set according to the type of transfer required. Therefore, for address cycles, MTX is always 1.
25354 */
25355#define I2C_I2CR_MTX(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MTX_SHIFT)) & I2C_I2CR_MTX_MASK)
25356#define I2C_I2CR_MSTA_MASK (0x20U)
25357#define I2C_I2CR_MSTA_SHIFT (5U)
25358/*! MSTA
25359 * 0b0..Slave mode. Changing MSTA from 1 to 0 generates a Stop and selects Slave mode.
25360 * 0b1..Master mode. Changing MSTA from 0 to 1 signals a Start on the bus and selects Master mode.
25361 */
25362#define I2C_I2CR_MSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MSTA_SHIFT)) & I2C_I2CR_MSTA_MASK)
25363#define I2C_I2CR_IIEN_MASK (0x40U)
25364#define I2C_I2CR_IIEN_SHIFT (6U)
25365/*! IIEN
25366 * 0b0..I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an Interrupt condition occurs.
25367 * 0b1..I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set.
25368 */
25369#define I2C_I2CR_IIEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IIEN_SHIFT)) & I2C_I2CR_IIEN_MASK)
25370#define I2C_I2CR_IEN_MASK (0x80U)
25371#define I2C_I2CR_IEN_SHIFT (7U)
25372/*! IEN
25373 * 0b0..The block is disabled, but registers can still be accessed.
25374 * 0b1..The I2C is enabled. This bit must be set before any other I2C_I2CR bits have an effect.
25375 */
25376#define I2C_I2CR_IEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IEN_SHIFT)) & I2C_I2CR_IEN_MASK)
25377/*! @} */
25378
25379/*! @name I2SR - I2C Status Register */
25380/*! @{ */
25381#define I2C_I2SR_RXAK_MASK (0x1U)
25382#define I2C_I2SR_RXAK_SHIFT (0U)
25383/*! RXAK
25384 * 0b0..An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus.
25385 * 0b1..A "No acknowledge" signal was detected at the ninth clock.
25386 */
25387#define I2C_I2SR_RXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_RXAK_SHIFT)) & I2C_I2SR_RXAK_MASK)
25388#define I2C_I2SR_IIF_MASK (0x2U)
25389#define I2C_I2SR_IIF_SHIFT (1U)
25390/*! IIF
25391 * 0b0..No I2C interrupt pending.
25392 * 0b1..An interrupt is pending.This causes a processor interrupt request (if the interrupt enable is asserted [IIEN = 1]). The interrupt is set when one of the following occurs: One byte transfer is completed (the interrupt is set at the falling edge of the ninth clock). An address is received that matches its own specific address in Slave Receive mode. Arbitration is lost.
25393 */
25394#define I2C_I2SR_IIF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IIF_SHIFT)) & I2C_I2SR_IIF_MASK)
25395#define I2C_I2SR_SRW_MASK (0x4U)
25396#define I2C_I2SR_SRW_SHIFT (2U)
25397/*! SRW
25398 * 0b0..Slave receive, master writing to slave
25399 * 0b1..Slave transmit, master reading from slave
25400 */
25401#define I2C_I2SR_SRW(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_SRW_SHIFT)) & I2C_I2SR_SRW_MASK)
25402#define I2C_I2SR_IAL_MASK (0x10U)
25403#define I2C_I2SR_IAL_SHIFT (4U)
25404/*! IAL
25405 * 0b0..No arbitration lost.
25406 * 0b1..Arbitration is lost.
25407 */
25408#define I2C_I2SR_IAL(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAL_SHIFT)) & I2C_I2SR_IAL_MASK)
25409#define I2C_I2SR_IBB_MASK (0x20U)
25410#define I2C_I2SR_IBB_SHIFT (5U)
25411/*! IBB
25412 * 0b0..Bus is idle. If a Stop signal is detected, IBB is cleared.
25413 * 0b1..Bus is busy. When Start is detected, IBB is set.
25414 */
25415#define I2C_I2SR_IBB(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IBB_SHIFT)) & I2C_I2SR_IBB_MASK)
25416#define I2C_I2SR_IAAS_MASK (0x40U)
25417#define I2C_I2SR_IAAS_SHIFT (6U)
25418/*! IAAS
25419 * 0b0..Not addressed
25420 * 0b1..Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address.
25421 */
25422#define I2C_I2SR_IAAS(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAAS_SHIFT)) & I2C_I2SR_IAAS_MASK)
25423#define I2C_I2SR_ICF_MASK (0x80U)
25424#define I2C_I2SR_ICF_SHIFT (7U)
25425/*! ICF
25426 * 0b0..Transfer is in progress.
25427 * 0b1..Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte transfer.
25428 */
25429#define I2C_I2SR_ICF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_ICF_SHIFT)) & I2C_I2SR_ICF_MASK)
25430/*! @} */
25431
25432/*! @name I2DR - I2C Data I/O Register */
25433/*! @{ */
25434#define I2C_I2DR_DATA_MASK (0xFFU)
25435#define I2C_I2DR_DATA_SHIFT (0U)
25436#define I2C_I2DR_DATA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2DR_DATA_SHIFT)) & I2C_I2DR_DATA_MASK)
25437/*! @} */
25438
25439
25440/*!
25441 * @}
25442 */ /* end of group I2C_Register_Masks */
25443
25444
25445/* I2C - Peripheral instance base addresses */
25446/** Peripheral I2C1 base address */
25447#define I2C1_BASE (0x30A20000u)
25448/** Peripheral I2C1 base pointer */
25449#define I2C1 ((I2C_Type *)I2C1_BASE)
25450/** Peripheral I2C2 base address */
25451#define I2C2_BASE (0x30A30000u)
25452/** Peripheral I2C2 base pointer */
25453#define I2C2 ((I2C_Type *)I2C2_BASE)
25454/** Peripheral I2C3 base address */
25455#define I2C3_BASE (0x30A40000u)
25456/** Peripheral I2C3 base pointer */
25457#define I2C3 ((I2C_Type *)I2C3_BASE)
25458/** Peripheral I2C4 base address */
25459#define I2C4_BASE (0x30A50000u)
25460/** Peripheral I2C4 base pointer */
25461#define I2C4 ((I2C_Type *)I2C4_BASE)
25462/** Array initializer of I2C peripheral base addresses */
25463#define I2C_BASE_ADDRS { 0u, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE }
25464/** Array initializer of I2C peripheral base pointers */
25465#define I2C_BASE_PTRS { (I2C_Type *)0u, I2C1, I2C2, I2C3, I2C4 }
25466/** Interrupt vectors for the I2C peripheral type */
25467#define I2C_IRQS { NotAvail_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn, I2C4_IRQn }
25468
25469/*!
25470 * @}
25471 */ /* end of group I2C_Peripheral_Access_Layer */
25472
25473
25474/* ----------------------------------------------------------------------------
25475 -- I2S Peripheral Access Layer
25476 ---------------------------------------------------------------------------- */
25477
25478/*!
25479 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
25480 * @{
25481 */
25482
25483/** I2S - Register Layout Typedef */
25484typedef struct {
25485 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
25486 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
25487 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */
25488 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */
25489 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */
25490 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */
25491 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */
25492 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */
25493 __O uint32_t TDR[8]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
25494 __I uint32_t TFR[8]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
25495 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
25496 uint8_t RESERVED_0[36];
25497 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */
25498 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */
25499 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */
25500 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */
25501 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */
25502 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */
25503 __I uint32_t RDR[8]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
25504 __I uint32_t RFR[8]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
25505 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
25506} I2S_Type;
25507
25508/* ----------------------------------------------------------------------------
25509 -- I2S Register Masks
25510 ---------------------------------------------------------------------------- */
25511
25512/*!
25513 * @addtogroup I2S_Register_Masks I2S Register Masks
25514 * @{
25515 */
25516
25517/*! @name VERID - Version ID Register */
25518/*! @{ */
25519#define I2S_VERID_FEATURE_MASK (0xFFFFU)
25520#define I2S_VERID_FEATURE_SHIFT (0U)
25521/*! FEATURE - Feature Specification Number
25522 * 0b0000000000000000..Standard feature set.
25523 */
25524#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
25525#define I2S_VERID_MINOR_MASK (0xFF0000U)
25526#define I2S_VERID_MINOR_SHIFT (16U)
25527#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
25528#define I2S_VERID_MAJOR_MASK (0xFF000000U)
25529#define I2S_VERID_MAJOR_SHIFT (24U)
25530#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
25531/*! @} */
25532
25533/*! @name PARAM - Parameter Register */
25534/*! @{ */
25535#define I2S_PARAM_DATALINE_MASK (0xFU)
25536#define I2S_PARAM_DATALINE_SHIFT (0U)
25537#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
25538#define I2S_PARAM_FIFO_MASK (0xF00U)
25539#define I2S_PARAM_FIFO_SHIFT (8U)
25540#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
25541#define I2S_PARAM_FRAME_MASK (0xF0000U)
25542#define I2S_PARAM_FRAME_SHIFT (16U)
25543#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
25544/*! @} */
25545
25546/*! @name TCSR - SAI Transmit Control Register */
25547/*! @{ */
25548#define I2S_TCSR_FRDE_MASK (0x1U)
25549#define I2S_TCSR_FRDE_SHIFT (0U)
25550/*! FRDE - FIFO Request DMA Enable
25551 * 0b0..Disables the DMA request.
25552 * 0b1..Enables the DMA request.
25553 */
25554#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
25555#define I2S_TCSR_FWDE_MASK (0x2U)
25556#define I2S_TCSR_FWDE_SHIFT (1U)
25557/*! FWDE - FIFO Warning DMA Enable
25558 * 0b0..Disables the DMA request.
25559 * 0b1..Enables the DMA request.
25560 */
25561#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
25562#define I2S_TCSR_FRIE_MASK (0x100U)
25563#define I2S_TCSR_FRIE_SHIFT (8U)
25564/*! FRIE - FIFO Request Interrupt Enable
25565 * 0b0..Disables the interrupt.
25566 * 0b1..Enables the interrupt.
25567 */
25568#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
25569#define I2S_TCSR_FWIE_MASK (0x200U)
25570#define I2S_TCSR_FWIE_SHIFT (9U)
25571/*! FWIE - FIFO Warning Interrupt Enable
25572 * 0b0..Disables the interrupt.
25573 * 0b1..Enables the interrupt.
25574 */
25575#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
25576#define I2S_TCSR_FEIE_MASK (0x400U)
25577#define I2S_TCSR_FEIE_SHIFT (10U)
25578/*! FEIE - FIFO Error Interrupt Enable
25579 * 0b0..Disables the interrupt.
25580 * 0b1..Enables the interrupt.
25581 */
25582#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
25583#define I2S_TCSR_SEIE_MASK (0x800U)
25584#define I2S_TCSR_SEIE_SHIFT (11U)
25585/*! SEIE - Sync Error Interrupt Enable
25586 * 0b0..Disables interrupt.
25587 * 0b1..Enables interrupt.
25588 */
25589#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
25590#define I2S_TCSR_WSIE_MASK (0x1000U)
25591#define I2S_TCSR_WSIE_SHIFT (12U)
25592/*! WSIE - Word Start Interrupt Enable
25593 * 0b0..Disables interrupt.
25594 * 0b1..Enables interrupt.
25595 */
25596#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
25597#define I2S_TCSR_FRF_MASK (0x10000U)
25598#define I2S_TCSR_FRF_SHIFT (16U)
25599/*! FRF - FIFO Request Flag
25600 * 0b0..Transmit FIFO watermark has not been reached.
25601 * 0b1..Transmit FIFO watermark has been reached.
25602 */
25603#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
25604#define I2S_TCSR_FWF_MASK (0x20000U)
25605#define I2S_TCSR_FWF_SHIFT (17U)
25606/*! FWF - FIFO Warning Flag
25607 * 0b0..No enabled transmit FIFO is empty.
25608 * 0b1..Enabled transmit FIFO is empty.
25609 */
25610#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
25611#define I2S_TCSR_FEF_MASK (0x40000U)
25612#define I2S_TCSR_FEF_SHIFT (18U)
25613/*! FEF - FIFO Error Flag
25614 * 0b0..Transmit underrun not detected.
25615 * 0b1..Transmit underrun detected.
25616 */
25617#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
25618#define I2S_TCSR_SEF_MASK (0x80000U)
25619#define I2S_TCSR_SEF_SHIFT (19U)
25620/*! SEF - Sync Error Flag
25621 * 0b0..Sync error not detected.
25622 * 0b1..Frame sync error detected.
25623 */
25624#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
25625#define I2S_TCSR_WSF_MASK (0x100000U)
25626#define I2S_TCSR_WSF_SHIFT (20U)
25627/*! WSF - Word Start Flag
25628 * 0b0..Start of word not detected.
25629 * 0b1..Start of word detected.
25630 */
25631#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
25632#define I2S_TCSR_SR_MASK (0x1000000U)
25633#define I2S_TCSR_SR_SHIFT (24U)
25634/*! SR - Software Reset
25635 * 0b0..No effect.
25636 * 0b1..Software reset.
25637 */
25638#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
25639#define I2S_TCSR_FR_MASK (0x2000000U)
25640#define I2S_TCSR_FR_SHIFT (25U)
25641/*! FR - FIFO Reset
25642 * 0b0..No effect.
25643 * 0b1..FIFO reset.
25644 */
25645#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
25646#define I2S_TCSR_BCE_MASK (0x10000000U)
25647#define I2S_TCSR_BCE_SHIFT (28U)
25648/*! BCE - Bit Clock Enable
25649 * 0b0..Transmit bit clock is disabled.
25650 * 0b1..Transmit bit clock is enabled.
25651 */
25652#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
25653#define I2S_TCSR_DBGE_MASK (0x20000000U)
25654#define I2S_TCSR_DBGE_SHIFT (29U)
25655/*! DBGE - Debug Enable
25656 * 0b0..Transmitter is disabled in Debug mode, after completing the current frame.
25657 * 0b1..Transmitter is enabled in Debug mode.
25658 */
25659#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
25660#define I2S_TCSR_TE_MASK (0x80000000U)
25661#define I2S_TCSR_TE_SHIFT (31U)
25662/*! TE - Transmitter Enable
25663 * 0b0..Transmitter is disabled.
25664 * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
25665 */
25666#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
25667/*! @} */
25668
25669/*! @name TCR1 - SAI Transmit Configuration 1 Register */
25670/*! @{ */
25671#define I2S_TCR1_TFW_MASK (0x7FU)
25672#define I2S_TCR1_TFW_SHIFT (0U)
25673#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
25674/*! @} */
25675
25676/*! @name TCR2 - SAI Transmit Configuration 2 Register */
25677/*! @{ */
25678#define I2S_TCR2_DIV_MASK (0xFFU)
25679#define I2S_TCR2_DIV_SHIFT (0U)
25680#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
25681#define I2S_TCR2_BCD_MASK (0x1000000U)
25682#define I2S_TCR2_BCD_SHIFT (24U)
25683/*! BCD - Bit Clock Direction
25684 * 0b0..Bit clock is generated externally in Slave mode.
25685 * 0b1..Bit clock is generated internally in Master mode.
25686 */
25687#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
25688#define I2S_TCR2_BCP_MASK (0x2000000U)
25689#define I2S_TCR2_BCP_SHIFT (25U)
25690/*! BCP - Bit Clock Polarity
25691 * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
25692 * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
25693 */
25694#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
25695#define I2S_TCR2_MSEL_MASK (0xC000000U)
25696#define I2S_TCR2_MSEL_SHIFT (26U)
25697/*! MSEL - MCLK Select
25698 * 0b00..Bus Clock selected.
25699 * 0b01..Master Clock (MCLK) 1 option selected.
25700 * 0b10..Master Clock (MCLK) 2 option selected.
25701 * 0b11..Master Clock (MCLK) 3 option selected.
25702 */
25703#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
25704#define I2S_TCR2_BCI_MASK (0x10000000U)
25705#define I2S_TCR2_BCI_SHIFT (28U)
25706/*! BCI - Bit Clock Input
25707 * 0b0..No effect.
25708 * 0b1..Internal logic is clocked as if bit clock was externally generated.
25709 */
25710#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
25711#define I2S_TCR2_BCS_MASK (0x20000000U)
25712#define I2S_TCR2_BCS_SHIFT (29U)
25713/*! BCS - Bit Clock Swap
25714 * 0b0..Use the normal bit clock source.
25715 * 0b1..Swap the bit clock source.
25716 */
25717#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
25718#define I2S_TCR2_SYNC_MASK (0xC0000000U)
25719#define I2S_TCR2_SYNC_SHIFT (30U)
25720/*! SYNC - Synchronous Mode
25721 * 0b00..Asynchronous mode.
25722 * 0b01..Synchronous with receiver.
25723 * 0b10..Reserved.
25724 * 0b11..Reserved.
25725 */
25726#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
25727/*! @} */
25728
25729/*! @name TCR3 - SAI Transmit Configuration 3 Register */
25730/*! @{ */
25731#define I2S_TCR3_WDFL_MASK (0x1FU)
25732#define I2S_TCR3_WDFL_SHIFT (0U)
25733#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
25734#define I2S_TCR3_TCE_MASK (0xFF0000U) /* Merged from fields with different position or width, of widths (1, 8), largest definition used */
25735#define I2S_TCR3_TCE_SHIFT (16U)
25736#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 8), largest definition used */
25737#define I2S_TCR3_CFR_MASK (0xFF000000U)
25738#define I2S_TCR3_CFR_SHIFT (24U)
25739#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
25740/*! @} */
25741
25742/*! @name TCR4 - SAI Transmit Configuration 4 Register */
25743/*! @{ */
25744#define I2S_TCR4_FSD_MASK (0x1U)
25745#define I2S_TCR4_FSD_SHIFT (0U)
25746/*! FSD - Frame Sync Direction
25747 * 0b0..Frame sync is generated externally in Slave mode.
25748 * 0b1..Frame sync is generated internally in Master mode.
25749 */
25750#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
25751#define I2S_TCR4_FSP_MASK (0x2U)
25752#define I2S_TCR4_FSP_SHIFT (1U)
25753/*! FSP - Frame Sync Polarity
25754 * 0b0..Frame sync is active high.
25755 * 0b1..Frame sync is active low.
25756 */
25757#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
25758#define I2S_TCR4_ONDEM_MASK (0x4U)
25759#define I2S_TCR4_ONDEM_SHIFT (2U)
25760/*! ONDEM - On Demand Mode
25761 * 0b0..Internal frame sync is generated continuously.
25762 * 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
25763 */
25764#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
25765#define I2S_TCR4_FSE_MASK (0x8U)
25766#define I2S_TCR4_FSE_SHIFT (3U)
25767/*! FSE - Frame Sync Early
25768 * 0b0..Frame sync asserts with the first bit of the frame.
25769 * 0b1..Frame sync asserts one bit before the first bit of the frame.
25770 */
25771#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
25772#define I2S_TCR4_MF_MASK (0x10U)
25773#define I2S_TCR4_MF_SHIFT (4U)
25774/*! MF - MSB First
25775 * 0b0..LSB is transmitted first.
25776 * 0b1..MSB is transmitted first.
25777 */
25778#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
25779#define I2S_TCR4_CHMOD_MASK (0x20U)
25780#define I2S_TCR4_CHMOD_SHIFT (5U)
25781/*! CHMOD - Channel Mode
25782 * 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.
25783 * 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.
25784 */
25785#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
25786#define I2S_TCR4_SYWD_MASK (0x1F00U)
25787#define I2S_TCR4_SYWD_SHIFT (8U)
25788#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
25789#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
25790#define I2S_TCR4_FRSZ_SHIFT (16U)
25791#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
25792#define I2S_TCR4_FPACK_MASK (0x3000000U)
25793#define I2S_TCR4_FPACK_SHIFT (24U)
25794/*! FPACK - FIFO Packing Mode
25795 * 0b00..FIFO packing is disabled
25796 * 0b01..Reserved
25797 * 0b10..8-bit FIFO packing is enabled
25798 * 0b11..16-bit FIFO packing is enabled
25799 */
25800#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
25801#define I2S_TCR4_FCOMB_MASK (0xC000000U)
25802#define I2S_TCR4_FCOMB_SHIFT (26U)
25803/*! FCOMB - FIFO Combine Mode
25804 * 0b00..FIFO combine mode disabled.
25805 * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
25806 * 0b10..FIFO combine mode enabled on FIFO writes (by software).
25807 * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
25808 */
25809#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
25810#define I2S_TCR4_FCONT_MASK (0x10000000U)
25811#define I2S_TCR4_FCONT_SHIFT (28U)
25812/*! FCONT - FIFO Continue on Error
25813 * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
25814 * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
25815 */
25816#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
25817/*! @} */
25818
25819/*! @name TCR5 - SAI Transmit Configuration 5 Register */
25820/*! @{ */
25821#define I2S_TCR5_FBT_MASK (0x1F00U)
25822#define I2S_TCR5_FBT_SHIFT (8U)
25823#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
25824#define I2S_TCR5_W0W_MASK (0x1F0000U)
25825#define I2S_TCR5_W0W_SHIFT (16U)
25826#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
25827#define I2S_TCR5_WNW_MASK (0x1F000000U)
25828#define I2S_TCR5_WNW_SHIFT (24U)
25829#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
25830/*! @} */
25831
25832/*! @name TDR - SAI Transmit Data Register */
25833/*! @{ */
25834#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
25835#define I2S_TDR_TDR_SHIFT (0U)
25836#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
25837/*! @} */
25838
25839/* The count of I2S_TDR */
25840#define I2S_TDR_COUNT (8U)
25841
25842/*! @name TFR - SAI Transmit FIFO Register */
25843/*! @{ */
25844#define I2S_TFR_RFP_MASK (0xFFU)
25845#define I2S_TFR_RFP_SHIFT (0U)
25846#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
25847#define I2S_TFR_WFP_MASK (0xFF0000U)
25848#define I2S_TFR_WFP_SHIFT (16U)
25849#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
25850#define I2S_TFR_WCP_MASK (0x80000000U)
25851#define I2S_TFR_WCP_SHIFT (31U)
25852/*! WCP - Write Channel Pointer
25853 * 0b0..No effect.
25854 * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
25855 */
25856#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
25857/*! @} */
25858
25859/* The count of I2S_TFR */
25860#define I2S_TFR_COUNT (8U)
25861
25862/*! @name TMR - SAI Transmit Mask Register */
25863/*! @{ */
25864#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
25865#define I2S_TMR_TWM_SHIFT (0U)
25866/*! TWM - Transmit Word Mask
25867 * 0b00000000000000000000000000000000..Word N is enabled.
25868 * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.
25869 */
25870#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
25871/*! @} */
25872
25873/*! @name RCSR - SAI Receive Control Register */
25874/*! @{ */
25875#define I2S_RCSR_FRDE_MASK (0x1U)
25876#define I2S_RCSR_FRDE_SHIFT (0U)
25877/*! FRDE - FIFO Request DMA Enable
25878 * 0b0..Disables the DMA request.
25879 * 0b1..Enables the DMA request.
25880 */
25881#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
25882#define I2S_RCSR_FWDE_MASK (0x2U)
25883#define I2S_RCSR_FWDE_SHIFT (1U)
25884/*! FWDE - FIFO Warning DMA Enable
25885 * 0b0..Disables the DMA request.
25886 * 0b1..Enables the DMA request.
25887 */
25888#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
25889#define I2S_RCSR_FRIE_MASK (0x100U)
25890#define I2S_RCSR_FRIE_SHIFT (8U)
25891/*! FRIE - FIFO Request Interrupt Enable
25892 * 0b0..Disables the interrupt.
25893 * 0b1..Enables the interrupt.
25894 */
25895#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
25896#define I2S_RCSR_FWIE_MASK (0x200U)
25897#define I2S_RCSR_FWIE_SHIFT (9U)
25898/*! FWIE - FIFO Warning Interrupt Enable
25899 * 0b0..Disables the interrupt.
25900 * 0b1..Enables the interrupt.
25901 */
25902#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
25903#define I2S_RCSR_FEIE_MASK (0x400U)
25904#define I2S_RCSR_FEIE_SHIFT (10U)
25905/*! FEIE - FIFO Error Interrupt Enable
25906 * 0b0..Disables the interrupt.
25907 * 0b1..Enables the interrupt.
25908 */
25909#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
25910#define I2S_RCSR_SEIE_MASK (0x800U)
25911#define I2S_RCSR_SEIE_SHIFT (11U)
25912/*! SEIE - Sync Error Interrupt Enable
25913 * 0b0..Disables interrupt.
25914 * 0b1..Enables interrupt.
25915 */
25916#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
25917#define I2S_RCSR_WSIE_MASK (0x1000U)
25918#define I2S_RCSR_WSIE_SHIFT (12U)
25919/*! WSIE - Word Start Interrupt Enable
25920 * 0b0..Disables interrupt.
25921 * 0b1..Enables interrupt.
25922 */
25923#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
25924#define I2S_RCSR_FRF_MASK (0x10000U)
25925#define I2S_RCSR_FRF_SHIFT (16U)
25926/*! FRF - FIFO Request Flag
25927 * 0b0..Receive FIFO watermark not reached.
25928 * 0b1..Receive FIFO watermark has been reached.
25929 */
25930#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
25931#define I2S_RCSR_FWF_MASK (0x20000U)
25932#define I2S_RCSR_FWF_SHIFT (17U)
25933/*! FWF - FIFO Warning Flag
25934 * 0b0..No enabled receive FIFO is full.
25935 * 0b1..Enabled receive FIFO is full.
25936 */
25937#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
25938#define I2S_RCSR_FEF_MASK (0x40000U)
25939#define I2S_RCSR_FEF_SHIFT (18U)
25940/*! FEF - FIFO Error Flag
25941 * 0b0..Receive overflow not detected.
25942 * 0b1..Receive overflow detected.
25943 */
25944#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
25945#define I2S_RCSR_SEF_MASK (0x80000U)
25946#define I2S_RCSR_SEF_SHIFT (19U)
25947/*! SEF - Sync Error Flag
25948 * 0b0..Sync error not detected.
25949 * 0b1..Frame sync error detected.
25950 */
25951#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
25952#define I2S_RCSR_WSF_MASK (0x100000U)
25953#define I2S_RCSR_WSF_SHIFT (20U)
25954/*! WSF - Word Start Flag
25955 * 0b0..Start of word not detected.
25956 * 0b1..Start of word detected.
25957 */
25958#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
25959#define I2S_RCSR_SR_MASK (0x1000000U)
25960#define I2S_RCSR_SR_SHIFT (24U)
25961/*! SR - Software Reset
25962 * 0b0..No effect.
25963 * 0b1..Software reset.
25964 */
25965#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
25966#define I2S_RCSR_FR_MASK (0x2000000U)
25967#define I2S_RCSR_FR_SHIFT (25U)
25968/*! FR - FIFO Reset
25969 * 0b0..No effect.
25970 * 0b1..FIFO reset.
25971 */
25972#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
25973#define I2S_RCSR_BCE_MASK (0x10000000U)
25974#define I2S_RCSR_BCE_SHIFT (28U)
25975/*! BCE - Bit Clock Enable
25976 * 0b0..Receive bit clock is disabled.
25977 * 0b1..Receive bit clock is enabled.
25978 */
25979#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
25980#define I2S_RCSR_DBGE_MASK (0x20000000U)
25981#define I2S_RCSR_DBGE_SHIFT (29U)
25982/*! DBGE - Debug Enable
25983 * 0b0..Receiver is disabled in Debug mode, after completing the current frame.
25984 * 0b1..Receiver is enabled in Debug mode.
25985 */
25986#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
25987#define I2S_RCSR_RE_MASK (0x80000000U)
25988#define I2S_RCSR_RE_SHIFT (31U)
25989/*! RE - Receiver Enable
25990 * 0b0..Receiver is disabled.
25991 * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
25992 */
25993#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
25994/*! @} */
25995
25996/*! @name RCR1 - SAI Receive Configuration 1 Register */
25997/*! @{ */
25998#define I2S_RCR1_RFW_MASK (0x7FU)
25999#define I2S_RCR1_RFW_SHIFT (0U)
26000#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
26001/*! @} */
26002
26003/*! @name RCR2 - SAI Receive Configuration 2 Register */
26004/*! @{ */
26005#define I2S_RCR2_DIV_MASK (0xFFU)
26006#define I2S_RCR2_DIV_SHIFT (0U)
26007#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
26008#define I2S_RCR2_BCD_MASK (0x1000000U)
26009#define I2S_RCR2_BCD_SHIFT (24U)
26010/*! BCD - Bit Clock Direction
26011 * 0b0..Bit clock is generated externally in Slave mode.
26012 * 0b1..Bit clock is generated internally in Master mode.
26013 */
26014#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
26015#define I2S_RCR2_BCP_MASK (0x2000000U)
26016#define I2S_RCR2_BCP_SHIFT (25U)
26017/*! BCP - Bit Clock Polarity
26018 * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
26019 * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
26020 */
26021#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
26022#define I2S_RCR2_MSEL_MASK (0xC000000U)
26023#define I2S_RCR2_MSEL_SHIFT (26U)
26024/*! MSEL - MCLK Select
26025 * 0b00..Bus Clock selected.
26026 * 0b01..Master Clock (MCLK) 1 option selected.
26027 * 0b10..Master Clock (MCLK) 2 option selected.
26028 * 0b11..Master Clock (MCLK) 3 option selected.
26029 */
26030#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
26031#define I2S_RCR2_BCI_MASK (0x10000000U)
26032#define I2S_RCR2_BCI_SHIFT (28U)
26033/*! BCI - Bit Clock Input
26034 * 0b0..No effect.
26035 * 0b1..Internal logic is clocked as if bit clock was externally generated.
26036 */
26037#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
26038#define I2S_RCR2_BCS_MASK (0x20000000U)
26039#define I2S_RCR2_BCS_SHIFT (29U)
26040/*! BCS - Bit Clock Swap
26041 * 0b0..Use the normal bit clock source.
26042 * 0b1..Swap the bit clock source.
26043 */
26044#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
26045#define I2S_RCR2_SYNC_MASK (0xC0000000U)
26046#define I2S_RCR2_SYNC_SHIFT (30U)
26047/*! SYNC - Synchronous Mode
26048 * 0b00..Asynchronous mode.
26049 * 0b01..Synchronous with transmitter.
26050 * 0b10..Reserved.
26051 * 0b11..Reserved.
26052 */
26053#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
26054/*! @} */
26055
26056/*! @name RCR3 - SAI Receive Configuration 3 Register */
26057/*! @{ */
26058#define I2S_RCR3_WDFL_MASK (0x1FU)
26059#define I2S_RCR3_WDFL_SHIFT (0U)
26060#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
26061#define I2S_RCR3_RCE_MASK (0xFF0000U) /* Merged from fields with different position or width, of widths (1, 8), largest definition used */
26062#define I2S_RCR3_RCE_SHIFT (16U)
26063#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 8), largest definition used */
26064#define I2S_RCR3_CFR_MASK (0xFF000000U)
26065#define I2S_RCR3_CFR_SHIFT (24U)
26066#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
26067/*! @} */
26068
26069/*! @name RCR4 - SAI Receive Configuration 4 Register */
26070/*! @{ */
26071#define I2S_RCR4_FSD_MASK (0x1U)
26072#define I2S_RCR4_FSD_SHIFT (0U)
26073/*! FSD - Frame Sync Direction
26074 * 0b0..Frame Sync is generated externally in Slave mode.
26075 * 0b1..Frame Sync is generated internally in Master mode.
26076 */
26077#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
26078#define I2S_RCR4_FSP_MASK (0x2U)
26079#define I2S_RCR4_FSP_SHIFT (1U)
26080/*! FSP - Frame Sync Polarity
26081 * 0b0..Frame sync is active high.
26082 * 0b1..Frame sync is active low.
26083 */
26084#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
26085#define I2S_RCR4_ONDEM_MASK (0x4U)
26086#define I2S_RCR4_ONDEM_SHIFT (2U)
26087/*! ONDEM - On Demand Mode
26088 * 0b0..Internal frame sync is generated continuously.
26089 * 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
26090 */
26091#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
26092#define I2S_RCR4_FSE_MASK (0x8U)
26093#define I2S_RCR4_FSE_SHIFT (3U)
26094/*! FSE - Frame Sync Early
26095 * 0b0..Frame sync asserts with the first bit of the frame.
26096 * 0b1..Frame sync asserts one bit before the first bit of the frame.
26097 */
26098#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
26099#define I2S_RCR4_MF_MASK (0x10U)
26100#define I2S_RCR4_MF_SHIFT (4U)
26101/*! MF - MSB First
26102 * 0b0..LSB is received first.
26103 * 0b1..MSB is received first.
26104 */
26105#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
26106#define I2S_RCR4_SYWD_MASK (0x1F00U)
26107#define I2S_RCR4_SYWD_SHIFT (8U)
26108#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
26109#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
26110#define I2S_RCR4_FRSZ_SHIFT (16U)
26111#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
26112#define I2S_RCR4_FPACK_MASK (0x3000000U)
26113#define I2S_RCR4_FPACK_SHIFT (24U)
26114/*! FPACK - FIFO Packing Mode
26115 * 0b00..FIFO packing is disabled
26116 * 0b01..Reserved.
26117 * 0b10..8-bit FIFO packing is enabled
26118 * 0b11..16-bit FIFO packing is enabled
26119 */
26120#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
26121#define I2S_RCR4_FCOMB_MASK (0xC000000U)
26122#define I2S_RCR4_FCOMB_SHIFT (26U)
26123/*! FCOMB - FIFO Combine Mode
26124 * 0b00..FIFO combine mode disabled.
26125 * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
26126 * 0b10..FIFO combine mode enabled on FIFO reads (by software).
26127 * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
26128 */
26129#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
26130#define I2S_RCR4_FCONT_MASK (0x10000000U)
26131#define I2S_RCR4_FCONT_SHIFT (28U)
26132/*! FCONT - FIFO Continue on Error
26133 * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
26134 * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
26135 */
26136#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
26137/*! @} */
26138
26139/*! @name RCR5 - SAI Receive Configuration 5 Register */
26140/*! @{ */
26141#define I2S_RCR5_FBT_MASK (0x1F00U)
26142#define I2S_RCR5_FBT_SHIFT (8U)
26143#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
26144#define I2S_RCR5_W0W_MASK (0x1F0000U)
26145#define I2S_RCR5_W0W_SHIFT (16U)
26146#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
26147#define I2S_RCR5_WNW_MASK (0x1F000000U)
26148#define I2S_RCR5_WNW_SHIFT (24U)
26149#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
26150/*! @} */
26151
26152/*! @name RDR - SAI Receive Data Register */
26153/*! @{ */
26154#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
26155#define I2S_RDR_RDR_SHIFT (0U)
26156#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
26157/*! @} */
26158
26159/* The count of I2S_RDR */
26160#define I2S_RDR_COUNT (8U)
26161
26162/*! @name RFR - SAI Receive FIFO Register */
26163/*! @{ */
26164#define I2S_RFR_RFP_MASK (0xFFU)
26165#define I2S_RFR_RFP_SHIFT (0U)
26166#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
26167#define I2S_RFR_RCP_MASK (0x8000U)
26168#define I2S_RFR_RCP_SHIFT (15U)
26169/*! RCP - Receive Channel Pointer
26170 * 0b0..No effect.
26171 * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
26172 */
26173#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
26174#define I2S_RFR_WFP_MASK (0xFF0000U)
26175#define I2S_RFR_WFP_SHIFT (16U)
26176#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
26177/*! @} */
26178
26179/* The count of I2S_RFR */
26180#define I2S_RFR_COUNT (8U)
26181
26182/*! @name RMR - SAI Receive Mask Register */
26183/*! @{ */
26184#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
26185#define I2S_RMR_RWM_SHIFT (0U)
26186/*! RWM - Receive Word Mask
26187 * 0b00000000000000000000000000000000..Word N is enabled.
26188 * 0b00000000000000000000000000000001..Word N is masked.
26189 */
26190#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
26191/*! @} */
26192
26193
26194/*!
26195 * @}
26196 */ /* end of group I2S_Register_Masks */
26197
26198
26199/* I2S - Peripheral instance base addresses */
26200/** Peripheral I2S1 base address */
26201#define I2S1_BASE (0x30010000u)
26202/** Peripheral I2S1 base pointer */
26203#define I2S1 ((I2S_Type *)I2S1_BASE)
26204/** Peripheral I2S2 base address */
26205#define I2S2_BASE (0x308B0000u)
26206/** Peripheral I2S2 base pointer */
26207#define I2S2 ((I2S_Type *)I2S2_BASE)
26208/** Peripheral I2S3 base address */
26209#define I2S3_BASE (0x308C0000u)
26210/** Peripheral I2S3 base pointer */
26211#define I2S3 ((I2S_Type *)I2S3_BASE)
26212/** Peripheral I2S4 base address */
26213#define I2S4_BASE (0x30050000u)
26214/** Peripheral I2S4 base pointer */
26215#define I2S4 ((I2S_Type *)I2S4_BASE)
26216/** Peripheral I2S5 base address */
26217#define I2S5_BASE (0x30040000u)
26218/** Peripheral I2S5 base pointer */
26219#define I2S5 ((I2S_Type *)I2S5_BASE)
26220/** Peripheral I2S6 base address */
26221#define I2S6_BASE (0x30030000u)
26222/** Peripheral I2S6 base pointer */
26223#define I2S6 ((I2S_Type *)I2S6_BASE)
26224/** Array initializer of I2S peripheral base addresses */
26225#define I2S_BASE_ADDRS { 0u, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE }
26226/** Array initializer of I2S peripheral base pointers */
26227#define I2S_BASE_PTRS { (I2S_Type *)0u, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6 }
26228/** Interrupt vectors for the I2S peripheral type */
26229#define I2S_RX_IRQS { NotAvail_IRQn, I2S1_IRQn, I2S2_IRQn, I2S3_IRQn, I2S4_IRQn, I2S56_IRQn, I2S56_IRQn }
26230#define I2S_TX_IRQS { NotAvail_IRQn, I2S1_IRQn, I2S2_IRQn, I2S3_IRQn, I2S4_IRQn, I2S56_IRQn, I2S56_IRQn }
26231
26232/*!
26233 * @}
26234 */ /* end of group I2S_Peripheral_Access_Layer */
26235
26236
26237/* ----------------------------------------------------------------------------
26238 -- IOMUXC Peripheral Access Layer
26239 ---------------------------------------------------------------------------- */
26240
26241/*!
26242 * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer
26243 * @{
26244 */
26245
26246/** IOMUXC - Register Layout Typedef */
26247typedef struct {
26248 uint8_t RESERVED_0[20];
26249 __IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ; /**< SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register, offset: 0x14 */
26250 __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ; /**< SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register, offset: 0x18 */
26251 __IO uint32_t SW_MUX_CTL_PAD_ONOFF; /**< SW_MUX_CTL_PAD_ONOFF SW MUX Control Register, offset: 0x1C */
26252 __IO uint32_t SW_MUX_CTL_PAD_POR_B; /**< SW_MUX_CTL_PAD_POR_B SW MUX Control Register, offset: 0x20 */
26253 __IO uint32_t SW_MUX_CTL_PAD_RTC_RESET_B; /**< SW_MUX_CTL_PAD_RTC_RESET_B SW MUX Control Register, offset: 0x24 */
26254 __IO uint32_t SW_MUX_CTL_PAD[139]; /**< SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register..SW_MUX_CTL_PAD_UART4_TXD SW MUX Control Register, array offset: 0x28, array step: 0x4 */
26255 __IO uint32_t SW_PAD_CTL_PAD[154]; /**< SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register..SW_PAD_CTL_PAD_UART4_TXD SW PAD Control Register, array offset: 0x254, array step: 0x4 */
26256 __IO uint32_t SELECT_INPUT[30]; /**< CCM_PMIC_READY_SELECT_INPUT DAISY Register..SAI6_MCLK_SELECT_INPUT DAISY Register, array offset: 0x4BC, array step: 0x4 */
26257} IOMUXC_Type;
26258
26259/* ----------------------------------------------------------------------------
26260 -- IOMUXC Register Masks
26261 ---------------------------------------------------------------------------- */
26262
26263/*!
26264 * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks
26265 * @{
26266 */
26267
26268/*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */
26269/*! @{ */
26270#define IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x40U)
26271#define IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (6U)
26272/*! SION - Software Input On Field
26273 * 0b0..Input Path of pad PMIC_STBY_REQ is determined by functionality
26274 * 0b1..Force Input Path of pad PMIC_STBY_REQ
26275 */
26276#define IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)
26277/*! @} */
26278
26279/*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */
26280/*! @{ */
26281#define IOMUXC_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x40U)
26282#define IOMUXC_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (6U)
26283/*! SION - Software Input On Field
26284 * 0b0..Input Path of pad PMIC_ON_REQ is determined by functionality
26285 * 0b1..Force Input Path of pad PMIC_ON_REQ
26286 */
26287#define IOMUXC_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)
26288/*! @} */
26289
26290/*! @name SW_MUX_CTL_PAD_ONOFF - SW_MUX_CTL_PAD_ONOFF SW MUX Control Register */
26291/*! @{ */
26292#define IOMUXC_SW_MUX_CTL_PAD_ONOFF_SION_MASK (0x40U)
26293#define IOMUXC_SW_MUX_CTL_PAD_ONOFF_SION_SHIFT (6U)
26294/*! SION - Software Input On Field
26295 * 0b0..Input Path of pad ONOFF is determined by functionality
26296 * 0b1..Force Input Path of pad ONOFF
26297 */
26298#define IOMUXC_SW_MUX_CTL_PAD_ONOFF_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_ONOFF_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_ONOFF_SION_MASK)
26299/*! @} */
26300
26301/*! @name SW_MUX_CTL_PAD_POR_B - SW_MUX_CTL_PAD_POR_B SW MUX Control Register */
26302/*! @{ */
26303#define IOMUXC_SW_MUX_CTL_PAD_POR_B_SION_MASK (0x40U)
26304#define IOMUXC_SW_MUX_CTL_PAD_POR_B_SION_SHIFT (6U)
26305/*! SION - Software Input On Field
26306 * 0b0..Input Path of pad POR_B is determined by functionality
26307 * 0b1..Force Input Path of pad POR_B
26308 */
26309#define IOMUXC_SW_MUX_CTL_PAD_POR_B_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_POR_B_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_POR_B_SION_MASK)
26310/*! @} */
26311
26312/*! @name SW_MUX_CTL_PAD_RTC_RESET_B - SW_MUX_CTL_PAD_RTC_RESET_B SW MUX Control Register */
26313/*! @{ */
26314#define IOMUXC_SW_MUX_CTL_PAD_RTC_RESET_B_SION_MASK (0x40U)
26315#define IOMUXC_SW_MUX_CTL_PAD_RTC_RESET_B_SION_SHIFT (6U)
26316/*! SION - Software Input On Field
26317 * 0b0..Input Path of pad RTC_RESET_B is determined by functionality
26318 * 0b1..Force Input Path of pad RTC_RESET_B
26319 */
26320#define IOMUXC_SW_MUX_CTL_PAD_RTC_RESET_B_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_RTC_RESET_B_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_RTC_RESET_B_SION_MASK)
26321/*! @} */
26322
26323/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register..SW_MUX_CTL_PAD_UART4_TXD SW MUX Control Register */
26324/*! @{ */
26325#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U)
26326#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
26327/*! MUX_MODE - MUX Mode Select Field
26328 * 0b000..Select mux mode: ALT0 mux port: RX_DATA5 of instance: SAI1
26329 * 0b001..Select mux mode: ALT1 mux port: TX_DATA0 of instance: SAI6
26330 * 0b010..Select mux mode: ALT2 mux port: RX_DATA0 of instance: SAI6
26331 * 0b011..Select mux mode: ALT3 mux port: RX_SYNC of instance: SAI1
26332 * 0b100..Select mux mode: ALT4 mux port: TRACE5 of instance: CORESIGHT
26333 * 0b101..Select mux mode: ALT5 mux port: IO07 of instance: GPIO4
26334 * 0b110..Select mux mode: ALT6 mux port: BOOT_CFG5 of instance: SRC
26335 */
26336#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
26337#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)
26338#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)
26339/*! SION - Software Input On Field
26340 * 0b0..Input Path of pad SPDIF_EXT_CLK is determined by functionality
26341 * 0b1..Force Input Path of pad SPDIF_EXT_CLK
26342 */
26343#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
26344/*! @} */
26345
26346/* The count of IOMUXC_SW_MUX_CTL_PAD */
26347#define IOMUXC_SW_MUX_CTL_PAD_COUNT (139U)
26348
26349/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register..SW_PAD_CTL_PAD_UART4_TXD SW PAD Control Register */
26350/*! @{ */
26351#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x7U)
26352#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (0U)
26353/*! DSE - Drive Strength Field
26354 * 0b000..HI-Z
26355 * 0b001..255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
26356 * 0b010..105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
26357 * 0b011..75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
26358 * 0b100..85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
26359 * 0b101..65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
26360 * 0b110..45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
26361 * 0b111..40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
26362 */
26363#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
26364#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x18U)
26365#define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (3U)
26366/*! SRE - Slew Rate Field
26367 * 0b00..Slow Frequency Slew Rate (50Mhz)
26368 * 0b01..Medium Frequency Slew Rate (100Mhz)
26369 * 0b10..Fast Frequency Slew Rate (150Mhz)
26370 * 0b11..Max Frequency Slew Rate (200Mhz)
26371 */
26372#define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
26373#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x20U)
26374#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (5U)
26375/*! ODE - Open Drain Enable Field
26376 * 0b0..Open Drain Disabled
26377 * 0b1..Open Drain Enabled
26378 */
26379#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
26380#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x40U)
26381#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (6U)
26382/*! PUE - Pull Up Enable Field
26383 * 0b0..Pull Up Resistor Disabled
26384 * 0b1..Pull Up Resistor Enabled
26385 */
26386#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
26387#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x80U)
26388#define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (7U)
26389/*! HYS - Schmitt trigger Enable Field
26390 * 0b0..Schmitt Trigger Disabled
26391 * 0b1..Schmitt Trigger Enabled
26392 */
26393#define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)
26394#define IOMUXC_SW_PAD_CTL_PAD_LVTTL_MASK (0x100U)
26395#define IOMUXC_SW_PAD_CTL_PAD_LVTTL_SHIFT (8U)
26396/*! LVTTL - Lvttl Enable Field
26397 * 0b0..LVTTL Disabled
26398 * 0b1..LVTTL Enabled
26399 */
26400#define IOMUXC_SW_PAD_CTL_PAD_LVTTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_LVTTL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_LVTTL_MASK)
26401#define IOMUXC_SW_PAD_CTL_PAD_VSEL_MASK (0x3800U)
26402#define IOMUXC_SW_PAD_CTL_PAD_VSEL_SHIFT (11U)
26403/*! VSEL - Voltage Select Field
26404 * 0b000..Auto Detect 3.3/2.5/1.2/1.8 V mode
26405 * 0b001..Auto Detect 3.3/2.5/1.2/1.8 V mode
26406 * 0b010..Auto Detect 3.3/2.5/1.2/1.8 V mode
26407 * 0b011..Auto Detect 3.3/2.5/1.2/1.8 V mode
26408 * 0b100..Manually Set 3.3V mode
26409 * 0b101..Manually Set 2.5V mode
26410 * 0b110..Manually Set 2.5V mode
26411 * 0b111..Manually Set 1.2V/1.8V mode
26412 */
26413#define IOMUXC_SW_PAD_CTL_PAD_VSEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_VSEL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_VSEL_MASK)
26414/*! @} */
26415
26416/* The count of IOMUXC_SW_PAD_CTL_PAD */
26417#define IOMUXC_SW_PAD_CTL_PAD_COUNT (154U)
26418
26419/*! @name SELECT_INPUT - CCM_PMIC_READY_SELECT_INPUT DAISY Register..SAI6_MCLK_SELECT_INPUT DAISY Register */
26420/*! @{ */
26421#define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
26422#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U)
26423/*! DAISY - Input Select (DAISY) Field
26424 * 0b000..Selecting Pad: SAI5_RXD1 Mode: ALT2 for SAI1_TX_SYNC
26425 * 0b001..Selecting Pad: SAI5_RXD2 Mode: ALT2 for SAI1_TX_SYNC
26426 * 0b010..Selecting Pad: SAI5_RXD3 Mode: ALT2 for SAI1_TX_SYNC
26427 * 0b011..Selecting Pad: SAI1_TXFS Mode: ALT0 for SAI1_TX_SYNC
26428 * 0b100..Selecting Pad: SAI1_RXD7 Mode: ALT2 for SAI1_TX_SYNC
26429 */
26430#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
26431/*! @} */
26432
26433/* The count of IOMUXC_SELECT_INPUT */
26434#define IOMUXC_SELECT_INPUT_COUNT (30U)
26435
26436
26437/*!
26438 * @}
26439 */ /* end of group IOMUXC_Register_Masks */
26440
26441
26442/* IOMUXC - Peripheral instance base addresses */
26443/** Peripheral IOMUXC base address */
26444#define IOMUXC_BASE (0x30330000u)
26445/** Peripheral IOMUXC base pointer */
26446#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE)
26447/** Array initializer of IOMUXC peripheral base addresses */
26448#define IOMUXC_BASE_ADDRS { IOMUXC_BASE }
26449/** Array initializer of IOMUXC peripheral base pointers */
26450#define IOMUXC_BASE_PTRS { IOMUXC }
26451
26452/*!
26453 * @}
26454 */ /* end of group IOMUXC_Peripheral_Access_Layer */
26455
26456
26457/* ----------------------------------------------------------------------------
26458 -- IOMUXC_GPR Peripheral Access Layer
26459 ---------------------------------------------------------------------------- */
26460
26461/*!
26462 * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer
26463 * @{
26464 */
26465
26466/** IOMUXC_GPR - Register Layout Typedef */
26467typedef struct {
26468 __IO uint32_t GPR[48]; /**< GPR0 General Purpose Register..GPR47 General Purpose Register, array offset: 0x0, array step: 0x4 */
26469} IOMUXC_GPR_Type;
26470
26471/* ----------------------------------------------------------------------------
26472 -- IOMUXC_GPR Register Masks
26473 ---------------------------------------------------------------------------- */
26474
26475/*!
26476 * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks
26477 * @{
26478 */
26479
26480/*! @name GPR - GPR0 General Purpose Register..GPR47 General Purpose Register */
26481/*! @{ */
26482#define IOMUXC_GPR_GPR_ARCACHE_USDHC_MASK (0x1U)
26483#define IOMUXC_GPR_GPR_ARCACHE_USDHC_SHIFT (0U)
26484/*! ARCACHE_USDHC
26485 * 0b0..Drive USDHC AXI Master ARCACHE[1] to 0
26486 * 0b1..Drive USDHC AXI Master ARCACHE[1] to 1
26487 */
26488#define IOMUXC_GPR_GPR_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_USDHC_MASK)
26489#define IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_BYTE_CNT_MASK (0x3FFU)
26490#define IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_BYTE_CNT_SHIFT (0U)
26491#define IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_BYTE_CNT_MASK)
26492#define IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_BYTE_CNT_MASK (0x3FFU)
26493#define IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_BYTE_CNT_SHIFT (0U)
26494#define IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_BYTE_CNT_MASK)
26495#define IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_BYTE_CNT_MASK (0x3FFU)
26496#define IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_BYTE_CNT_SHIFT (0U)
26497#define IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_BYTE_CNT_MASK)
26498#define IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_BYTE_CNT_MASK (0x3FFU)
26499#define IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_BYTE_CNT_SHIFT (0U)
26500#define IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_BYTE_CNT_MASK)
26501#define IOMUXC_GPR_GPR_CSI2_1_ECC_TWO_BIT_ERROR_MASK (0x1U)
26502#define IOMUXC_GPR_GPR_CSI2_1_ECC_TWO_BIT_ERROR_SHIFT (0U)
26503#define IOMUXC_GPR_GPR_CSI2_1_ECC_TWO_BIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ECC_TWO_BIT_ERROR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ECC_TWO_BIT_ERROR_MASK)
26504#define IOMUXC_GPR_GPR_CSI2_1_RX_RCAL_MASK (0x3U)
26505#define IOMUXC_GPR_GPR_CSI2_1_RX_RCAL_SHIFT (0U)
26506#define IOMUXC_GPR_GPR_CSI2_1_RX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_RX_RCAL_MASK)
26507#define IOMUXC_GPR_GPR_CSI2_1_TEST_PATTERN_MASK (0xFFFFFFFFU)
26508#define IOMUXC_GPR_GPR_CSI2_1_TEST_PATTERN_SHIFT (0U)
26509#define IOMUXC_GPR_GPR_CSI2_1_TEST_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_TEST_PATTERN_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_TEST_PATTERN_MASK)
26510#define IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_BYTE_CNT_MASK (0x3FFU)
26511#define IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_BYTE_CNT_SHIFT (0U)
26512#define IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_BYTE_CNT_MASK)
26513#define IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_BYTE_CNT_MASK (0x3FFU)
26514#define IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_BYTE_CNT_SHIFT (0U)
26515#define IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_BYTE_CNT_MASK)
26516#define IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_BYTE_CNT_MASK (0x3FFU)
26517#define IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_BYTE_CNT_SHIFT (0U)
26518#define IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_BYTE_CNT_MASK)
26519#define IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_BYTE_CNT_MASK (0x3FFU)
26520#define IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_BYTE_CNT_SHIFT (0U)
26521#define IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_BYTE_CNT_MASK)
26522#define IOMUXC_GPR_GPR_CSI2_2_ECC_TWO_BIT_ERROR_MASK (0x1U)
26523#define IOMUXC_GPR_GPR_CSI2_2_ECC_TWO_BIT_ERROR_SHIFT (0U)
26524#define IOMUXC_GPR_GPR_CSI2_2_ECC_TWO_BIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ECC_TWO_BIT_ERROR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ECC_TWO_BIT_ERROR_MASK)
26525#define IOMUXC_GPR_GPR_CSI2_2_RX_RCAL_MASK (0x3U)
26526#define IOMUXC_GPR_GPR_CSI2_2_RX_RCAL_SHIFT (0U)
26527#define IOMUXC_GPR_GPR_CSI2_2_RX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_RX_RCAL_MASK)
26528#define IOMUXC_GPR_GPR_CSI2_2_TEST_PATTERN_MASK (0xFFFFFFFFU)
26529#define IOMUXC_GPR_GPR_CSI2_2_TEST_PATTERN_SHIFT (0U)
26530#define IOMUXC_GPR_GPR_CSI2_2_TEST_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_TEST_PATTERN_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_TEST_PATTERN_MASK)
26531#define IOMUXC_GPR_GPR_DSI_D0_INT_LB_BYTE_CNT_MASK (0x3FFU)
26532#define IOMUXC_GPR_GPR_DSI_D0_INT_LB_BYTE_CNT_SHIFT (0U)
26533#define IOMUXC_GPR_GPR_DSI_D0_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D0_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D0_INT_LB_BYTE_CNT_MASK)
26534#define IOMUXC_GPR_GPR_DSI_D1_INT_LB_BYTE_CNT_MASK (0x3FFU)
26535#define IOMUXC_GPR_GPR_DSI_D1_INT_LB_BYTE_CNT_SHIFT (0U)
26536#define IOMUXC_GPR_GPR_DSI_D1_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D1_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D1_INT_LB_BYTE_CNT_MASK)
26537#define IOMUXC_GPR_GPR_DSI_D2_INT_LB_BYTE_CNT_MASK (0x3FFU)
26538#define IOMUXC_GPR_GPR_DSI_D2_INT_LB_BYTE_CNT_SHIFT (0U)
26539#define IOMUXC_GPR_GPR_DSI_D2_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D2_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D2_INT_LB_BYTE_CNT_MASK)
26540#define IOMUXC_GPR_GPR_DSI_D3_INT_LB_BYTE_CNT_MASK (0x3FFU)
26541#define IOMUXC_GPR_GPR_DSI_D3_INT_LB_BYTE_CNT_SHIFT (0U)
26542#define IOMUXC_GPR_GPR_DSI_D3_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D3_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D3_INT_LB_BYTE_CNT_MASK)
26543#define IOMUXC_GPR_GPR_DSI_RX_RCAL_MASK (0x3U)
26544#define IOMUXC_GPR_GPR_DSI_RX_RCAL_SHIFT (0U)
26545#define IOMUXC_GPR_GPR_DSI_RX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR_DSI_RX_RCAL_MASK)
26546#define IOMUXC_GPR_GPR_DSI_TEST_PATTERN_MASK (0xFFFFFFFFU)
26547#define IOMUXC_GPR_GPR_DSI_TEST_PATTERN_SHIFT (0U)
26548#define IOMUXC_GPR_GPR_DSI_TEST_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_TEST_PATTERN_SHIFT)) & IOMUXC_GPR_GPR_DSI_TEST_PATTERN_MASK)
26549#define IOMUXC_GPR_GPR_DSI_TWO_BIT_ERR_MASK (0x1U)
26550#define IOMUXC_GPR_GPR_DSI_TWO_BIT_ERR_SHIFT (0U)
26551#define IOMUXC_GPR_GPR_DSI_TWO_BIT_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_TWO_BIT_ERR_SHIFT)) & IOMUXC_GPR_GPR_DSI_TWO_BIT_ERR_MASK)
26552#define IOMUXC_GPR_GPR_DSI_UI_STATUS0_RO_MASK (0xFFFFFFFFU)
26553#define IOMUXC_GPR_GPR_DSI_UI_STATUS0_RO_SHIFT (0U)
26554#define IOMUXC_GPR_GPR_DSI_UI_STATUS0_RO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_UI_STATUS0_RO_SHIFT)) & IOMUXC_GPR_GPR_DSI_UI_STATUS0_RO_MASK)
26555#define IOMUXC_GPR_GPR_DSI_UI_STATUS1_RO_MASK (0xFFFFFFFFU)
26556#define IOMUXC_GPR_GPR_DSI_UI_STATUS1_RO_SHIFT (0U)
26557#define IOMUXC_GPR_GPR_DSI_UI_STATUS1_RO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_UI_STATUS1_RO_SHIFT)) & IOMUXC_GPR_GPR_DSI_UI_STATUS1_RO_MASK)
26558#define IOMUXC_GPR_GPR_DSI_UI_STATUS2_RO_MASK (0xFFFFFFFFU)
26559#define IOMUXC_GPR_GPR_DSI_UI_STATUS2_RO_SHIFT (0U)
26560#define IOMUXC_GPR_GPR_DSI_UI_STATUS2_RO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_UI_STATUS2_RO_SHIFT)) & IOMUXC_GPR_GPR_DSI_UI_STATUS2_RO_MASK)
26561#define IOMUXC_GPR_GPR_DSI_UI_STATUS3_RO_MASK (0x3FFFFFFFU)
26562#define IOMUXC_GPR_GPR_DSI_UI_STATUS3_RO_SHIFT (0U)
26563#define IOMUXC_GPR_GPR_DSI_UI_STATUS3_RO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_UI_STATUS3_RO_SHIFT)) & IOMUXC_GPR_GPR_DSI_UI_STATUS3_RO_MASK)
26564#define IOMUXC_GPR_GPR_GPR_SAI1_EXT_MCLK_EN_MASK (0x1U)
26565#define IOMUXC_GPR_GPR_GPR_SAI1_EXT_MCLK_EN_SHIFT (0U)
26566#define IOMUXC_GPR_GPR_GPR_SAI1_EXT_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_SAI1_EXT_MCLK_EN_SHIFT)) & IOMUXC_GPR_GPR_GPR_SAI1_EXT_MCLK_EN_MASK)
26567#define IOMUXC_GPR_GPR_HDMI_HPD_PD_MASK (0x1U)
26568#define IOMUXC_GPR_GPR_HDMI_HPD_PD_SHIFT (0U)
26569#define IOMUXC_GPR_GPR_HDMI_HPD_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_HDMI_HPD_PD_SHIFT)) & IOMUXC_GPR_GPR_HDMI_HPD_PD_MASK)
26570#define IOMUXC_GPR_GPR_OCRAM_TZ_EN_MASK (0x1U)
26571#define IOMUXC_GPR_GPR_OCRAM_TZ_EN_SHIFT (0U)
26572/*! OCRAM_TZ_EN
26573 * 0b0..The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor).
26574 * 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter.
26575 */
26576#define IOMUXC_GPR_GPR_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_TZ_EN_MASK)
26577#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_LOW_MASK (0x7FU)
26578#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_LOW_SHIFT (0U)
26579#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_LOW_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_LOW_MASK)
26580#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_LOW_MASK (0x7FU)
26581#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_LOW_SHIFT (0U)
26582#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_LOW_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_LOW_MASK)
26583#define IOMUXC_GPR_GPR_PCIE_DIAG_STATUS_MASK (0xFFFFFFFFU)
26584#define IOMUXC_GPR_GPR_PCIE_DIAG_STATUS_SHIFT (0U)
26585#define IOMUXC_GPR_GPR_PCIE_DIAG_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE_DIAG_STATUS_SHIFT)) & IOMUXC_GPR_GPR_PCIE_DIAG_STATUS_MASK)
26586#define IOMUXC_GPR_GPR_RDATA_WAIT_EN_MASK (0x1U)
26587#define IOMUXC_GPR_GPR_RDATA_WAIT_EN_SHIFT (0U)
26588/*! RDATA_WAIT_EN
26589 * 0b0..read data wait state disabled
26590 * 0b1..read data wait state enabled
26591 */
26592#define IOMUXC_GPR_GPR_RDATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_RDATA_WAIT_EN_SHIFT)) & IOMUXC_GPR_GPR_RDATA_WAIT_EN_MASK)
26593#define IOMUXC_GPR_GPR_SDMA1_IPG_STOP_MASK (0x1U)
26594#define IOMUXC_GPR_GPR_SDMA1_IPG_STOP_SHIFT (0U)
26595/*! SDMA1_IPG_STOP
26596 * 0b0..stop request off
26597 * 0b1..stop request on
26598 */
26599#define IOMUXC_GPR_GPR_SDMA1_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SDMA1_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR_SDMA1_IPG_STOP_MASK)
26600#define IOMUXC_GPR_GPR_TZASC_EN_MASK (0x1U)
26601#define IOMUXC_GPR_GPR_TZASC_EN_SHIFT (0U)
26602#define IOMUXC_GPR_GPR_TZASC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_TZASC_EN_SHIFT)) & IOMUXC_GPR_GPR_TZASC_EN_MASK)
26603#define IOMUXC_GPR_GPR_AWCACHE_USDHC_MASK (0x2U)
26604#define IOMUXC_GPR_GPR_AWCACHE_USDHC_SHIFT (1U)
26605/*! AWCACHE_USDHC
26606 * 0b0..Drive USDHC AXI Master AWCACHE[1] to 0
26607 * 0b1..Drive USDHC AXI Master AWCACHE[1] to 1
26608 */
26609#define IOMUXC_GPR_GPR_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR_AWCACHE_USDHC_MASK)
26610#define IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERR_POS_MASK (0x3EU)
26611#define IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERR_POS_SHIFT (1U)
26612#define IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERR_POS_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERR_POS_MASK)
26613#define IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERR_POS_MASK (0x3EU)
26614#define IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERR_POS_SHIFT (1U)
26615#define IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERR_POS_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERR_POS_MASK)
26616#define IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_POS_MASK (0x3EU)
26617#define IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_POS_SHIFT (1U)
26618#define IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_POS_SHIFT)) & IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_POS_MASK)
26619#define IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL0_MASK (0x2U)
26620#define IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL0_SHIFT (1U)
26621/*! ENET1_IPD_REQ_TIMER_SEL0
26622 * 0b0..Select ipd_req_mac0_timer2 to SDMA IRQ 45
26623 * 0b1..Select ipd_req_mac0_timer0 to SDMA IRQ 45
26624 */
26625#define IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL0_SHIFT)) & IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL0_MASK)
26626#define IOMUXC_GPR_GPR_GPR_SAI2_EXT_MCLK_EN_MASK (0x2U)
26627#define IOMUXC_GPR_GPR_GPR_SAI2_EXT_MCLK_EN_SHIFT (1U)
26628#define IOMUXC_GPR_GPR_GPR_SAI2_EXT_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_SAI2_EXT_MCLK_EN_SHIFT)) & IOMUXC_GPR_GPR_GPR_SAI2_EXT_MCLK_EN_MASK)
26629#define IOMUXC_GPR_GPR_HDMI_DDC_SDA_PD_MASK (0x2U)
26630#define IOMUXC_GPR_GPR_HDMI_DDC_SDA_PD_SHIFT (1U)
26631#define IOMUXC_GPR_GPR_HDMI_DDC_SDA_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_HDMI_DDC_SDA_PD_SHIFT)) & IOMUXC_GPR_GPR_HDMI_DDC_SDA_PD_MASK)
26632#define IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_MASK (0x3EU)
26633#define IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_SHIFT (1U)
26634#define IOMUXC_GPR_GPR_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_MASK)
26635#define IOMUXC_GPR_GPR_RADDR_PIPE_EN_MASK (0x2U)
26636#define IOMUXC_GPR_GPR_RADDR_PIPE_EN_SHIFT (1U)
26637/*! RADDR_PIPE_EN
26638 * 0b0..read address pipeline is disabled
26639 * 0b1..read address pipeline is enabled
26640 */
26641#define IOMUXC_GPR_GPR_RADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_RADDR_PIPE_EN_SHIFT)) & IOMUXC_GPR_GPR_RADDR_PIPE_EN_MASK)
26642#define IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_MASK (0x2U)
26643#define IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_SHIFT (1U)
26644#define IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_SHIFT)) & IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_MASK)
26645#define IOMUXC_GPR_GPR_CSI2_1_S_PRG_RXHS_SETTLE_MASK (0xFCU)
26646#define IOMUXC_GPR_GPR_CSI2_1_S_PRG_RXHS_SETTLE_SHIFT (2U)
26647#define IOMUXC_GPR_GPR_CSI2_1_S_PRG_RXHS_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_S_PRG_RXHS_SETTLE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_S_PRG_RXHS_SETTLE_MASK)
26648#define IOMUXC_GPR_GPR_CSI2_2_S_PRG_RXHS_SETTLE_MASK (0xFCU)
26649#define IOMUXC_GPR_GPR_CSI2_2_S_PRG_RXHS_SETTLE_SHIFT (2U)
26650#define IOMUXC_GPR_GPR_CSI2_2_S_PRG_RXHS_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_S_PRG_RXHS_SETTLE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_S_PRG_RXHS_SETTLE_MASK)
26651#define IOMUXC_GPR_GPR_DSI_RTERM_SEL_MASK (0x4U)
26652#define IOMUXC_GPR_GPR_DSI_RTERM_SEL_SHIFT (2U)
26653#define IOMUXC_GPR_GPR_DSI_RTERM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_RTERM_SEL_SHIFT)) & IOMUXC_GPR_GPR_DSI_RTERM_SEL_MASK)
26654#define IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL1_MASK (0x4U)
26655#define IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL1_SHIFT (2U)
26656/*! ENET1_IPD_REQ_TIMER_SEL1
26657 * 0b0..Select ipd_req_mac0_timer3 to SDMA IRQ 47
26658 * 0b1..Select ipd_req_mac0_timer1 to SDMA IRQ 47
26659 */
26660#define IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL1_SHIFT)) & IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL1_MASK)
26661#define IOMUXC_GPR_GPR_GPR_SAI3_EXT_MCLK_EN_MASK (0x4U)
26662#define IOMUXC_GPR_GPR_GPR_SAI3_EXT_MCLK_EN_SHIFT (2U)
26663#define IOMUXC_GPR_GPR_GPR_SAI3_EXT_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_SAI3_EXT_MCLK_EN_SHIFT)) & IOMUXC_GPR_GPR_GPR_SAI3_EXT_MCLK_EN_MASK)
26664#define IOMUXC_GPR_GPR_HDMI_DDC_SCL_PD_MASK (0x4U)
26665#define IOMUXC_GPR_GPR_HDMI_DDC_SCL_PD_SHIFT (2U)
26666#define IOMUXC_GPR_GPR_HDMI_DDC_SCL_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_HDMI_DDC_SCL_PD_SHIFT)) & IOMUXC_GPR_GPR_HDMI_DDC_SCL_PD_MASK)
26667#define IOMUXC_GPR_GPR_MIPI_MUX_SEL_MASK (0x4U)
26668#define IOMUXC_GPR_GPR_MIPI_MUX_SEL_SHIFT (2U)
26669#define IOMUXC_GPR_GPR_MIPI_MUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_MIPI_MUX_SEL_SHIFT)) & IOMUXC_GPR_GPR_MIPI_MUX_SEL_MASK)
26670#define IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_MASK (0x4U)
26671#define IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_SHIFT (2U)
26672/*! SEC_ERR_RESP_EN
26673 * 0b0..OKAY response
26674 * 0b1..SLVERR response
26675 */
26676#define IOMUXC_GPR_GPR_SEC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_SHIFT)) & IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_MASK)
26677#define IOMUXC_GPR_GPR_WDATA_PIPE_EN_MASK (0x4U)
26678#define IOMUXC_GPR_GPR_WDATA_PIPE_EN_SHIFT (2U)
26679/*! WDATA_PIPE_EN
26680 * 0b0..write data pipeline is disabled
26681 * 0b1..write data pipeline is enabled
26682 */
26683#define IOMUXC_GPR_GPR_WDATA_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WDATA_PIPE_EN_SHIFT)) & IOMUXC_GPR_GPR_WDATA_PIPE_EN_MASK)
26684#define IOMUXC_GPR_GPR_DSI_RCALT_MASK (0x18U)
26685#define IOMUXC_GPR_GPR_DSI_RCALT_SHIFT (3U)
26686#define IOMUXC_GPR_GPR_DSI_RCALT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_RCALT_SHIFT)) & IOMUXC_GPR_GPR_DSI_RCALT_MASK)
26687#define IOMUXC_GPR_GPR_ENET1_IPG_STOP_MASK (0x8U)
26688#define IOMUXC_GPR_GPR_ENET1_IPG_STOP_SHIFT (3U)
26689/*! ENET1_IPG_STOP
26690 * 0b0..stop request off
26691 * 0b1..stop request on
26692 */
26693#define IOMUXC_GPR_GPR_ENET1_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ENET1_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR_ENET1_IPG_STOP_MASK)
26694#define IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_MASK (0x8U)
26695#define IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_SHIFT (3U)
26696/*! EXC_ERR_RESP_EN
26697 * 0b0..OK response on the AXI for an exclusive access error
26698 * 0b1..ERR response on the AXI for an exclusive access error
26699 */
26700#define IOMUXC_GPR_GPR_EXC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_SHIFT)) & IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_MASK)
26701#define IOMUXC_GPR_GPR_GPR_SAI4_EXT_MCLK_EN_MASK (0x8U)
26702#define IOMUXC_GPR_GPR_GPR_SAI4_EXT_MCLK_EN_SHIFT (3U)
26703#define IOMUXC_GPR_GPR_GPR_SAI4_EXT_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_SAI4_EXT_MCLK_EN_SHIFT)) & IOMUXC_GPR_GPR_GPR_SAI4_EXT_MCLK_EN_MASK)
26704#define IOMUXC_GPR_GPR_HDMI_CEC_PD_MASK (0x8U)
26705#define IOMUXC_GPR_GPR_HDMI_CEC_PD_SHIFT (3U)
26706#define IOMUXC_GPR_GPR_HDMI_CEC_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_HDMI_CEC_PD_SHIFT)) & IOMUXC_GPR_GPR_HDMI_CEC_PD_MASK)
26707#define IOMUXC_GPR_GPR_MIPI_MUX_INV_MASK (0x8U)
26708#define IOMUXC_GPR_GPR_MIPI_MUX_INV_SHIFT (3U)
26709#define IOMUXC_GPR_GPR_MIPI_MUX_INV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_MIPI_MUX_INV_SHIFT)) & IOMUXC_GPR_GPR_MIPI_MUX_INV_MASK)
26710#define IOMUXC_GPR_GPR_WADDR_PIPE_EN_MASK (0x8U)
26711#define IOMUXC_GPR_GPR_WADDR_PIPE_EN_SHIFT (3U)
26712/*! WADDR_PIPE_EN
26713 * 0b0..write address pipeline is disabled
26714 * 0b1..write address pipeline is enabled
26715 */
26716#define IOMUXC_GPR_GPR_WADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WADDR_PIPE_EN_SHIFT)) & IOMUXC_GPR_GPR_WADDR_PIPE_EN_MASK)
26717#define IOMUXC_GPR_GPR_ARCACHE_PCIE1_MASK (0x10U)
26718#define IOMUXC_GPR_GPR_ARCACHE_PCIE1_SHIFT (4U)
26719/*! ARCACHE_PCIE1
26720 * 0b0..Drive PCIe AXI Master Port ARCACHE[1] to 0
26721 * 0b1..Drive PCIe AXI Master Port ARCACHE[1] to 1
26722 */
26723#define IOMUXC_GPR_GPR_ARCACHE_PCIE1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_PCIE1_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_PCIE1_MASK)
26724#define IOMUXC_GPR_GPR_GPR_SAI5_EXT_MCLK_EN_MASK (0x10U)
26725#define IOMUXC_GPR_GPR_GPR_SAI5_EXT_MCLK_EN_SHIFT (4U)
26726#define IOMUXC_GPR_GPR_GPR_SAI5_EXT_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_SAI5_EXT_MCLK_EN_SHIFT)) & IOMUXC_GPR_GPR_GPR_SAI5_EXT_MCLK_EN_MASK)
26727#define IOMUXC_GPR_GPR_SDMA2_IPG_STOP_MASK (0x10U)
26728#define IOMUXC_GPR_GPR_SDMA2_IPG_STOP_SHIFT (4U)
26729/*! SDMA2_IPG_STOP
26730 * 0b0..stop request off
26731 * 0b1..stop request on
26732 */
26733#define IOMUXC_GPR_GPR_SDMA2_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SDMA2_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR_SDMA2_IPG_STOP_MASK)
26734#define IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_MASK (0x10U)
26735#define IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_SHIFT (4U)
26736#define IOMUXC_GPR_GPR_S_RDATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_SHIFT)) & IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_MASK)
26737#define IOMUXC_GPR_GPR_AWCACHE_PCIE1_MASK (0x20U)
26738#define IOMUXC_GPR_GPR_AWCACHE_PCIE1_SHIFT (5U)
26739/*! AWCACHE_PCIE1
26740 * 0b0..Drive PCIe AXI Master Port AWCACHE[1] to 0
26741 * 0b1..Drive PCIe AXI Master Port AWCACHE[1] to 1
26742 */
26743#define IOMUXC_GPR_GPR_AWCACHE_PCIE1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_AWCACHE_PCIE1_SHIFT)) & IOMUXC_GPR_GPR_AWCACHE_PCIE1_MASK)
26744#define IOMUXC_GPR_GPR_DSI_NOCAL_MASK (0x20U)
26745#define IOMUXC_GPR_GPR_DSI_NOCAL_SHIFT (5U)
26746#define IOMUXC_GPR_GPR_DSI_NOCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_NOCAL_SHIFT)) & IOMUXC_GPR_GPR_DSI_NOCAL_MASK)
26747#define IOMUXC_GPR_GPR_GPR_SAI6_EXT_MCLK_EN_MASK (0x20U)
26748#define IOMUXC_GPR_GPR_GPR_SAI6_EXT_MCLK_EN_SHIFT (5U)
26749#define IOMUXC_GPR_GPR_GPR_SAI6_EXT_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_SAI6_EXT_MCLK_EN_SHIFT)) & IOMUXC_GPR_GPR_GPR_SAI6_EXT_MCLK_EN_MASK)
26750#define IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_MASK (0x20U)
26751#define IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_SHIFT (5U)
26752#define IOMUXC_GPR_GPR_S_RADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_SHIFT)) & IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_MASK)
26753#define IOMUXC_GPR_GPR_ARCACHE_LCDIF_MASK (0x40U)
26754#define IOMUXC_GPR_GPR_ARCACHE_LCDIF_SHIFT (6U)
26755/*! ARCACHE_LCDIF
26756 * 0b0..Drive LCDIF AXI Master Port ARCACHE[1] to 0
26757 * 0b1..Drive LCDIF AXI Master Port ARCACHE[1] to 1
26758 */
26759#define IOMUXC_GPR_GPR_ARCACHE_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_LCDIF_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_LCDIF_MASK)
26760#define IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERROR_MASK (0x40U)
26761#define IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERROR_SHIFT (6U)
26762#define IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERROR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERROR_MASK)
26763#define IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERROR_MASK (0x40U)
26764#define IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERROR_SHIFT (6U)
26765#define IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERROR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERROR_MASK)
26766#define IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_MASK (0x40U)
26767#define IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_SHIFT (6U)
26768#define IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_SHIFT)) & IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_MASK)
26769#define IOMUXC_GPR_GPR_DSI_HSEL_MASK (0x40U)
26770#define IOMUXC_GPR_GPR_DSI_HSEL_SHIFT (6U)
26771#define IOMUXC_GPR_GPR_DSI_HSEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_HSEL_SHIFT)) & IOMUXC_GPR_GPR_DSI_HSEL_MASK)
26772#define IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_MASK (0x40U)
26773#define IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_SHIFT (6U)
26774#define IOMUXC_GPR_GPR_S_WDATA_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_SHIFT)) & IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_MASK)
26775#define IOMUXC_GPR_GPR_WDOG1_MASK_MASK (0x40U)
26776#define IOMUXC_GPR_GPR_WDOG1_MASK_SHIFT (6U)
26777/*! WDOG1_MASK
26778 * 0b0..WDOG1 Timeout behaves normally
26779 * 0b1..WDOG1 Timeout is masked
26780 */
26781#define IOMUXC_GPR_GPR_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR_WDOG1_MASK_MASK)
26782#define IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_POS_MASK (0x380U)
26783#define IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_POS_SHIFT (7U)
26784#define IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_POS_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_POS_MASK)
26785#define IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_POS_MASK (0x380U)
26786#define IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_POS_SHIFT (7U)
26787#define IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_POS_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_POS_MASK)
26788#define IOMUXC_GPR_GPR_DSI_ECC_ERR_POS_MASK (0x380U)
26789#define IOMUXC_GPR_GPR_DSI_ECC_ERR_POS_SHIFT (7U)
26790#define IOMUXC_GPR_GPR_DSI_ECC_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_ECC_ERR_POS_SHIFT)) & IOMUXC_GPR_GPR_DSI_ECC_ERR_POS_MASK)
26791#define IOMUXC_GPR_GPR_DSI_TX_ULPS_ENABLE_MASK (0xF80U)
26792#define IOMUXC_GPR_GPR_DSI_TX_ULPS_ENABLE_SHIFT (7U)
26793#define IOMUXC_GPR_GPR_DSI_TX_ULPS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_TX_ULPS_ENABLE_SHIFT)) & IOMUXC_GPR_GPR_DSI_TX_ULPS_ENABLE_MASK)
26794#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_FULL_MASK (0x3F80U)
26795#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_FULL_SHIFT (7U)
26796#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_FULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_FULL_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_FULL_MASK)
26797#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_FULL_MASK (0x3F80U)
26798#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_FULL_SHIFT (7U)
26799#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_FULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_FULL_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_FULL_MASK)
26800#define IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_MASK (0x80U)
26801#define IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_SHIFT (7U)
26802#define IOMUXC_GPR_GPR_S_WADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_SHIFT)) & IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_MASK)
26803#define IOMUXC_GPR_GPR_WDOG2_MASK_MASK (0x80U)
26804#define IOMUXC_GPR_GPR_WDOG2_MASK_SHIFT (7U)
26805/*! WDOG2_MASK
26806 * 0b0..WDOG2 Timeout behaves normally
26807 * 0b1..WDOG2 Timeout is masked
26808 */
26809#define IOMUXC_GPR_GPR_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR_WDOG2_MASK_MASK)
26810#define IOMUXC_GPR_GPR_ARCACHE_PCIE2_EN_MASK (0x100U)
26811#define IOMUXC_GPR_GPR_ARCACHE_PCIE2_EN_SHIFT (8U)
26812/*! ARCACHE_PCIE2_EN
26813 * 0b0..PCIE Primary AXI Master Port ARCACHE[1] driven by PCIE
26814 * 0b1..PCIE Primary AXI Master Port ARCACHE[1] driven to constant value specified by the ARCACHE_PCIE2 bit
26815 */
26816#define IOMUXC_GPR_GPR_ARCACHE_PCIE2_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_PCIE2_EN_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_PCIE2_EN_MASK)
26817#define IOMUXC_GPR_GPR_CSI2_1_CONT_CLK_MODE_MASK (0x100U)
26818#define IOMUXC_GPR_GPR_CSI2_1_CONT_CLK_MODE_SHIFT (8U)
26819#define IOMUXC_GPR_GPR_CSI2_1_CONT_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_CONT_CLK_MODE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_CONT_CLK_MODE_MASK)
26820#define IOMUXC_GPR_GPR_CSI2_2_CONT_CLK_MODE_MASK (0x100U)
26821#define IOMUXC_GPR_GPR_CSI2_2_CONT_CLK_MODE_SHIFT (8U)
26822#define IOMUXC_GPR_GPR_CSI2_2_CONT_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_CONT_CLK_MODE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_CONT_CLK_MODE_MASK)
26823#define IOMUXC_GPR_GPR_PCIE1_APP_CLK_PM_EN_MASK (0x100U)
26824#define IOMUXC_GPR_GPR_PCIE1_APP_CLK_PM_EN_SHIFT (8U)
26825#define IOMUXC_GPR_GPR_PCIE1_APP_CLK_PM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_APP_CLK_PM_EN_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_APP_CLK_PM_EN_MASK)
26826#define IOMUXC_GPR_GPR_PCIE2_APP_CLK_PM_EN_MASK (0x100U)
26827#define IOMUXC_GPR_GPR_PCIE2_APP_CLK_PM_EN_SHIFT (8U)
26828#define IOMUXC_GPR_GPR_PCIE2_APP_CLK_PM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_APP_CLK_PM_EN_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_APP_CLK_PM_EN_MASK)
26829#define IOMUXC_GPR_GPR_PCIE2_CTRL_DEVICE_TYPE_MASK (0xF00U)
26830#define IOMUXC_GPR_GPR_PCIE2_CTRL_DEVICE_TYPE_SHIFT (8U)
26831/*! PCIE2_CTRL_DEVICE_TYPE
26832 * 0b0000..PCI Express endpoint
26833 * 0b0001..Legacy PCI Express endpoint
26834 * 0b0100..Root port of PCI Express root complex
26835 */
26836#define IOMUXC_GPR_GPR_PCIE2_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_CTRL_DEVICE_TYPE_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_CTRL_DEVICE_TYPE_MASK)
26837#define IOMUXC_GPR_GPR_AWCACHE_PCIE2_EN_MASK (0x200U)
26838#define IOMUXC_GPR_GPR_AWCACHE_PCIE2_EN_SHIFT (9U)
26839/*! AWCACHE_PCIE2_EN
26840 * 0b0..PCIE Primary AXI Master Port AWCACHE[1] driven by PCIE
26841 * 0b1..PXP Primary AXI Master Port AWCACHE[1] driven to constant value specified by the AWCACHE_PCIE2 bit
26842 */
26843#define IOMUXC_GPR_GPR_AWCACHE_PCIE2_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_AWCACHE_PCIE2_EN_SHIFT)) & IOMUXC_GPR_GPR_AWCACHE_PCIE2_EN_MASK)
26844#define IOMUXC_GPR_GPR_CSI2_1_AUTO_PD_EN_MASK (0x200U)
26845#define IOMUXC_GPR_GPR_CSI2_1_AUTO_PD_EN_SHIFT (9U)
26846#define IOMUXC_GPR_GPR_CSI2_1_AUTO_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_AUTO_PD_EN_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_AUTO_PD_EN_MASK)
26847#define IOMUXC_GPR_GPR_CSI2_2_AUTO_PD_EN_MASK (0x200U)
26848#define IOMUXC_GPR_GPR_CSI2_2_AUTO_PD_EN_SHIFT (9U)
26849#define IOMUXC_GPR_GPR_CSI2_2_AUTO_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_AUTO_PD_EN_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_AUTO_PD_EN_MASK)
26850#define IOMUXC_GPR_GPR_PCIE1_REF_USE_PAD_MASK (0x200U)
26851#define IOMUXC_GPR_GPR_PCIE1_REF_USE_PAD_SHIFT (9U)
26852#define IOMUXC_GPR_GPR_PCIE1_REF_USE_PAD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_REF_USE_PAD_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_REF_USE_PAD_MASK)
26853#define IOMUXC_GPR_GPR_PCIE2_REF_USE_PAD_MASK (0x200U)
26854#define IOMUXC_GPR_GPR_PCIE2_REF_USE_PAD_SHIFT (9U)
26855#define IOMUXC_GPR_GPR_PCIE2_REF_USE_PAD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_REF_USE_PAD_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_REF_USE_PAD_MASK)
26856#define IOMUXC_GPR_GPR_ARCACHE_PCIE1_EN_MASK (0x400U)
26857#define IOMUXC_GPR_GPR_ARCACHE_PCIE1_EN_SHIFT (10U)
26858/*! ARCACHE_PCIE1_EN
26859 * 0b0..PCIe AXI Master Port ARCACHE[1] driven by PCIe
26860 * 0b1..PCIe AXI Master Port ARCACHE[1] driven to constant value specified by the ARCACHE_PXP1 bit
26861 */
26862#define IOMUXC_GPR_GPR_ARCACHE_PCIE1_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_PCIE1_EN_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_PCIE1_EN_MASK)
26863#define IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_ERR_CNT_MASK (0xFFC00U)
26864#define IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_ERR_CNT_SHIFT (10U)
26865#define IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_ERR_CNT_MASK)
26866#define IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_ERR_CNT_MASK (0xFFC00U)
26867#define IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_ERR_CNT_SHIFT (10U)
26868#define IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_ERR_CNT_MASK)
26869#define IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_ERR_CNT_MASK (0xFFC00U)
26870#define IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_ERR_CNT_SHIFT (10U)
26871#define IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_ERR_CNT_MASK)
26872#define IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_ERR_CNT_MASK (0xFFC00U)
26873#define IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_ERR_CNT_SHIFT (10U)
26874#define IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_ERR_CNT_MASK)
26875#define IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_MASK (0x400U)
26876#define IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_SHIFT (10U)
26877#define IOMUXC_GPR_GPR_CSI2_1_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_MASK)
26878#define IOMUXC_GPR_GPR_CSI2_1_HSEL_MASK (0x400U)
26879#define IOMUXC_GPR_GPR_CSI2_1_HSEL_SHIFT (10U)
26880#define IOMUXC_GPR_GPR_CSI2_1_HSEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_HSEL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_HSEL_MASK)
26881#define IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_ERR_CNT_MASK (0xFFC00U)
26882#define IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_ERR_CNT_SHIFT (10U)
26883#define IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_ERR_CNT_MASK)
26884#define IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_ERR_CNT_MASK (0xFFC00U)
26885#define IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_ERR_CNT_SHIFT (10U)
26886#define IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_ERR_CNT_MASK)
26887#define IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_ERR_CNT_MASK (0xFFC00U)
26888#define IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_ERR_CNT_SHIFT (10U)
26889#define IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_ERR_CNT_MASK)
26890#define IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_ERR_CNT_MASK (0xFFC00U)
26891#define IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_ERR_CNT_SHIFT (10U)
26892#define IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_ERR_CNT_MASK)
26893#define IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_MASK (0x400U)
26894#define IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_SHIFT (10U)
26895#define IOMUXC_GPR_GPR_CSI2_2_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_MASK)
26896#define IOMUXC_GPR_GPR_CSI2_2_HSEL_MASK (0x400U)
26897#define IOMUXC_GPR_GPR_CSI2_2_HSEL_SHIFT (10U)
26898#define IOMUXC_GPR_GPR_CSI2_2_HSEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_HSEL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_HSEL_MASK)
26899#define IOMUXC_GPR_GPR_DSI_D0_INT_LB_ERR_CNT_MASK (0xFFC00U)
26900#define IOMUXC_GPR_GPR_DSI_D0_INT_LB_ERR_CNT_SHIFT (10U)
26901#define IOMUXC_GPR_GPR_DSI_D0_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D0_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D0_INT_LB_ERR_CNT_MASK)
26902#define IOMUXC_GPR_GPR_DSI_D1_INT_LB_ERR_CNT_MASK (0xFFC00U)
26903#define IOMUXC_GPR_GPR_DSI_D1_INT_LB_ERR_CNT_SHIFT (10U)
26904#define IOMUXC_GPR_GPR_DSI_D1_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D1_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D1_INT_LB_ERR_CNT_MASK)
26905#define IOMUXC_GPR_GPR_DSI_D2_INT_LB_ERR_CNT_MASK (0xFFC00U)
26906#define IOMUXC_GPR_GPR_DSI_D2_INT_LB_ERR_CNT_SHIFT (10U)
26907#define IOMUXC_GPR_GPR_DSI_D2_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D2_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D2_INT_LB_ERR_CNT_MASK)
26908#define IOMUXC_GPR_GPR_DSI_D3_INT_LB_ERR_CNT_MASK (0xFFC00U)
26909#define IOMUXC_GPR_GPR_DSI_D3_INT_LB_ERR_CNT_SHIFT (10U)
26910#define IOMUXC_GPR_GPR_DSI_D3_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D3_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D3_INT_LB_ERR_CNT_MASK)
26911#define IOMUXC_GPR_GPR_DSI_ECC_ERR_MASK (0x400U)
26912#define IOMUXC_GPR_GPR_DSI_ECC_ERR_SHIFT (10U)
26913#define IOMUXC_GPR_GPR_DSI_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_ECC_ERR_SHIFT)) & IOMUXC_GPR_GPR_DSI_ECC_ERR_MASK)
26914#define IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_MASK (0x400U)
26915#define IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_SHIFT (10U)
26916/*! OCRAM_S_TZ_EN
26917 * 0b0..The TrustZone feature is disabled. Entire State Retention OCRAM space is available for all access types (secure/non-secure/user/supervisor).
26918 * 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter.
26919 */
26920#define IOMUXC_GPR_GPR_OCRAM_S_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_MASK)
26921#define IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_EN_MASK (0x400U)
26922#define IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_EN_SHIFT (10U)
26923#define IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_EN_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_EN_MASK)
26924#define IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_EN_MASK (0x400U)
26925#define IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_EN_SHIFT (10U)
26926#define IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_EN_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_EN_MASK)
26927#define IOMUXC_GPR_GPR_AWCACHE_PCIE1_EN_MASK (0x800U)
26928#define IOMUXC_GPR_GPR_AWCACHE_PCIE1_EN_SHIFT (11U)
26929/*! AWCACHE_PCIE1_EN
26930 * 0b0..PCIe AXI Master Port AWCACHE[1] driven by PCIe
26931 * 0b1..PCIe AXI Master Port AWCACHE[1] driven to constant value specified by the AWCACHE_PCIE1 bit
26932 */
26933#define IOMUXC_GPR_GPR_AWCACHE_PCIE1_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_AWCACHE_PCIE1_EN_SHIFT)) & IOMUXC_GPR_GPR_AWCACHE_PCIE1_EN_MASK)
26934#define IOMUXC_GPR_GPR_CSI2_1_PD_RX_MASK (0x800U)
26935#define IOMUXC_GPR_GPR_CSI2_1_PD_RX_SHIFT (11U)
26936#define IOMUXC_GPR_GPR_CSI2_1_PD_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_PD_RX_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_PD_RX_MASK)
26937#define IOMUXC_GPR_GPR_CSI2_1_ULPS_MARK_ACTIVE_MASK (0xF800U)
26938#define IOMUXC_GPR_GPR_CSI2_1_ULPS_MARK_ACTIVE_SHIFT (11U)
26939#define IOMUXC_GPR_GPR_CSI2_1_ULPS_MARK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ULPS_MARK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ULPS_MARK_ACTIVE_MASK)
26940#define IOMUXC_GPR_GPR_CSI2_2_PD_RX_MASK (0x800U)
26941#define IOMUXC_GPR_GPR_CSI2_2_PD_RX_SHIFT (11U)
26942#define IOMUXC_GPR_GPR_CSI2_2_PD_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_PD_RX_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_PD_RX_MASK)
26943#define IOMUXC_GPR_GPR_CSI2_2_ULPS_MARK_ACTIVE_MASK (0xF800U)
26944#define IOMUXC_GPR_GPR_CSI2_2_ULPS_MARK_ACTIVE_SHIFT (11U)
26945#define IOMUXC_GPR_GPR_CSI2_2_ULPS_MARK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ULPS_MARK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ULPS_MARK_ACTIVE_MASK)
26946#define IOMUXC_GPR_GPR_DSI_HOST_UNDERRUN_ERR_MASK (0x800U)
26947#define IOMUXC_GPR_GPR_DSI_HOST_UNDERRUN_ERR_SHIFT (11U)
26948#define IOMUXC_GPR_GPR_DSI_HOST_UNDERRUN_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_HOST_UNDERRUN_ERR_SHIFT)) & IOMUXC_GPR_GPR_DSI_HOST_UNDERRUN_ERR_MASK)
26949#define IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_MASK (0x3800U)
26950#define IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_SHIFT (11U)
26951#define IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_MASK)
26952#define IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_MASK (0x800U)
26953#define IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_SHIFT (11U)
26954#define IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_MASK)
26955#define IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_MASK (0x800U)
26956#define IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_SHIFT (11U)
26957#define IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_MASK)
26958#define IOMUXC_GPR_GPR_ARCACHE_LCDIF_EN_MASK (0x1000U)
26959#define IOMUXC_GPR_GPR_ARCACHE_LCDIF_EN_SHIFT (12U)
26960/*! ARCACHE_LCDIF_EN
26961 * 0b0..LCDIF AXI Master Port ARCACHE[1] driven by LCDIF
26962 * 0b1..LCDIF AXI Master Port ARCACHE[1] driven to constant value specified by the ARCACHE_LCDIF bit
26963 */
26964#define IOMUXC_GPR_GPR_ARCACHE_LCDIF_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_LCDIF_EN_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_LCDIF_EN_MASK)
26965#define IOMUXC_GPR_GPR_CSI2_1_VID_INTFC_ENB_MASK (0x1000U)
26966#define IOMUXC_GPR_GPR_CSI2_1_VID_INTFC_ENB_SHIFT (12U)
26967#define IOMUXC_GPR_GPR_CSI2_1_VID_INTFC_ENB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_VID_INTFC_ENB_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_VID_INTFC_ENB_MASK)
26968#define IOMUXC_GPR_GPR_CSI2_2_VID_INTFC_ENB_MASK (0x1000U)
26969#define IOMUXC_GPR_GPR_CSI2_2_VID_INTFC_ENB_SHIFT (12U)
26970#define IOMUXC_GPR_GPR_CSI2_2_VID_INTFC_ENB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_VID_INTFC_ENB_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_VID_INTFC_ENB_MASK)
26971#define IOMUXC_GPR_GPR_DSI_TRIGGER_ACK_MASK (0x1000U)
26972#define IOMUXC_GPR_GPR_DSI_TRIGGER_ACK_SHIFT (12U)
26973#define IOMUXC_GPR_GPR_DSI_TRIGGER_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_TRIGGER_ACK_SHIFT)) & IOMUXC_GPR_GPR_DSI_TRIGGER_ACK_MASK)
26974#define IOMUXC_GPR_GPR_DSI_TRIGGER_SEND_MASK (0x3000U)
26975#define IOMUXC_GPR_GPR_DSI_TRIGGER_SEND_SHIFT (12U)
26976#define IOMUXC_GPR_GPR_DSI_TRIGGER_SEND(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_TRIGGER_SEND_SHIFT)) & IOMUXC_GPR_GPR_DSI_TRIGGER_SEND_MASK)
26977#define IOMUXC_GPR_GPR_IRQ_MASK (0x1000U)
26978#define IOMUXC_GPR_GPR_IRQ_SHIFT (12U)
26979#define IOMUXC_GPR_GPR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_IRQ_SHIFT)) & IOMUXC_GPR_GPR_IRQ_MASK)
26980#define IOMUXC_GPR_GPR_PCIE1_CTRL_DEVICE_TYPE_MASK (0xF000U)
26981#define IOMUXC_GPR_GPR_PCIE1_CTRL_DEVICE_TYPE_SHIFT (12U)
26982/*! PCIE1_CTRL_DEVICE_TYPE
26983 * 0b0000..PCI Express endpoint
26984 * 0b0001..Legacy PCI Express endpoint
26985 * 0b0100..Root port of PCI Express root complex
26986 */
26987#define IOMUXC_GPR_GPR_PCIE1_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_CTRL_DEVICE_TYPE_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_CTRL_DEVICE_TYPE_MASK)
26988#define IOMUXC_GPR_GPR_PCIE1_VREG_BYPASS_MASK (0x1000U)
26989#define IOMUXC_GPR_GPR_PCIE1_VREG_BYPASS_SHIFT (12U)
26990#define IOMUXC_GPR_GPR_PCIE1_VREG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_VREG_BYPASS_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_VREG_BYPASS_MASK)
26991#define IOMUXC_GPR_GPR_PCIE2_VREG_BYPASS_MASK (0x1000U)
26992#define IOMUXC_GPR_GPR_PCIE2_VREG_BYPASS_SHIFT (12U)
26993#define IOMUXC_GPR_GPR_PCIE2_VREG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_VREG_BYPASS_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_VREG_BYPASS_MASK)
26994#define IOMUXC_GPR_GPR_ARCACHE_PCIE2_MASK (0x2000U)
26995#define IOMUXC_GPR_GPR_ARCACHE_PCIE2_SHIFT (13U)
26996/*! ARCACHE_PCIE2
26997 * 0b0..Drive PCIe AXI Master Port ARCACHE[1] to 0
26998 * 0b1..Drive PCIe AXI Master Port ARCACHE[1] to 1
26999 */
27000#define IOMUXC_GPR_GPR_ARCACHE_PCIE2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_PCIE2_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_PCIE2_MASK)
27001#define IOMUXC_GPR_GPR_CSI2_1_RX_ENABLE_MASK (0x2000U)
27002#define IOMUXC_GPR_GPR_CSI2_1_RX_ENABLE_SHIFT (13U)
27003#define IOMUXC_GPR_GPR_CSI2_1_RX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_RX_ENABLE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_RX_ENABLE_MASK)
27004#define IOMUXC_GPR_GPR_CSI2_2_RX_ENABLE_MASK (0x2000U)
27005#define IOMUXC_GPR_GPR_CSI2_2_RX_ENABLE_SHIFT (13U)
27006#define IOMUXC_GPR_GPR_CSI2_2_RX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_RX_ENABLE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_RX_ENABLE_MASK)
27007#define IOMUXC_GPR_GPR_DSI_LP_RX_TIMEOUT_MASK (0x2000U)
27008#define IOMUXC_GPR_GPR_DSI_LP_RX_TIMEOUT_SHIFT (13U)
27009#define IOMUXC_GPR_GPR_DSI_LP_RX_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_LP_RX_TIMEOUT_SHIFT)) & IOMUXC_GPR_GPR_DSI_LP_RX_TIMEOUT_MASK)
27010#define IOMUXC_GPR_GPR_ENET1_TX_CLK_SEL_MASK (0x2000U)
27011#define IOMUXC_GPR_GPR_ENET1_TX_CLK_SEL_SHIFT (13U)
27012/*! ENET1_TX_CLK_SEL
27013 * 0b0..Gets ENET1 TX reference clk. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function.
27014 * 0b1..Gets ENET1 TX reference clk from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller
27015 */
27016#define IOMUXC_GPR_GPR_ENET1_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ENET1_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR_ENET1_TX_CLK_SEL_MASK)
27017#define IOMUXC_GPR_GPR_PCIE1_PHY_TX_VBOOST_LVL_MASK (0xE000U)
27018#define IOMUXC_GPR_GPR_PCIE1_PHY_TX_VBOOST_LVL_SHIFT (13U)
27019#define IOMUXC_GPR_GPR_PCIE1_PHY_TX_VBOOST_LVL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PHY_TX_VBOOST_LVL_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PHY_TX_VBOOST_LVL_MASK)
27020#define IOMUXC_GPR_GPR_PCIE2_PHY_TX_VBOOST_LVL_MASK (0xE000U)
27021#define IOMUXC_GPR_GPR_PCIE2_PHY_TX_VBOOST_LVL_SHIFT (13U)
27022#define IOMUXC_GPR_GPR_PCIE2_PHY_TX_VBOOST_LVL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PHY_TX_VBOOST_LVL_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PHY_TX_VBOOST_LVL_MASK)
27023#define IOMUXC_GPR_GPR_AWCACHE_PCIE2_MASK (0x4000U)
27024#define IOMUXC_GPR_GPR_AWCACHE_PCIE2_SHIFT (14U)
27025/*! AWCACHE_PCIE2
27026 * 0b0..Drive PCIe AXI Master Port AWCACHE[1] to 0
27027 * 0b1..Drive PCIe AXI Master Port AWCACHE[1] to 1
27028 */
27029#define IOMUXC_GPR_GPR_AWCACHE_PCIE2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_AWCACHE_PCIE2_SHIFT)) & IOMUXC_GPR_GPR_AWCACHE_PCIE2_MASK)
27030#define IOMUXC_GPR_GPR_DSI_HS_TX_TIMEOUT_MASK (0x4000U)
27031#define IOMUXC_GPR_GPR_DSI_HS_TX_TIMEOUT_SHIFT (14U)
27032#define IOMUXC_GPR_GPR_DSI_HS_TX_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_HS_TX_TIMEOUT_SHIFT)) & IOMUXC_GPR_GPR_DSI_HS_TX_TIMEOUT_MASK)
27033#define IOMUXC_GPR_GPR_DSI_TRIGGER_REQ_MASK (0x4000U)
27034#define IOMUXC_GPR_GPR_DSI_TRIGGER_REQ_SHIFT (14U)
27035#define IOMUXC_GPR_GPR_DSI_TRIGGER_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_TRIGGER_REQ_SHIFT)) & IOMUXC_GPR_GPR_DSI_TRIGGER_REQ_MASK)
27036#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_6DB_MASK (0xFC000U)
27037#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_6DB_SHIFT (14U)
27038#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_6DB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_6DB_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_6DB_MASK)
27039#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_6DB_MASK (0xFC000U)
27040#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_6DB_SHIFT (14U)
27041#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_6DB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_6DB_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_6DB_MASK)
27042#define IOMUXC_GPR_GPR_DDSI_DPHY_TURNAROUND_MASK (0x8000U)
27043#define IOMUXC_GPR_GPR_DDSI_DPHY_TURNAROUND_SHIFT (15U)
27044#define IOMUXC_GPR_GPR_DDSI_DPHY_TURNAROUND(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DDSI_DPHY_TURNAROUND_SHIFT)) & IOMUXC_GPR_GPR_DDSI_DPHY_TURNAROUND_MASK)
27045#define IOMUXC_GPR_GPR_DSI_HOST_BTA_TIMEOUT_MASK (0x8000U)
27046#define IOMUXC_GPR_GPR_DSI_HOST_BTA_TIMEOUT_SHIFT (15U)
27047#define IOMUXC_GPR_GPR_DSI_HOST_BTA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_HOST_BTA_TIMEOUT_SHIFT)) & IOMUXC_GPR_GPR_DSI_HOST_BTA_TIMEOUT_MASK)
27048#define IOMUXC_GPR_GPR_GPR_ANAMIX_IPT_MODE_MASK (0x8000U)
27049#define IOMUXC_GPR_GPR_GPR_ANAMIX_IPT_MODE_SHIFT (15U)
27050#define IOMUXC_GPR_GPR_GPR_ANAMIX_IPT_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_ANAMIX_IPT_MODE_SHIFT)) & IOMUXC_GPR_GPR_GPR_ANAMIX_IPT_MODE_MASK)
27051#define IOMUXC_GPR_GPR_CPU_STANDBYWFI_MASK (0xF0000U)
27052#define IOMUXC_GPR_GPR_CPU_STANDBYWFI_SHIFT (16U)
27053#define IOMUXC_GPR_GPR_CPU_STANDBYWFI(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CPU_STANDBYWFI_SHIFT)) & IOMUXC_GPR_GPR_CPU_STANDBYWFI_MASK)
27054#define IOMUXC_GPR_GPR_CSI2_1_RX_DPHY_RDY_MASK (0x10000U)
27055#define IOMUXC_GPR_GPR_CSI2_1_RX_DPHY_RDY_SHIFT (16U)
27056#define IOMUXC_GPR_GPR_CSI2_1_RX_DPHY_RDY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_RX_DPHY_RDY_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_RX_DPHY_RDY_MASK)
27057#define IOMUXC_GPR_GPR_CSI2_2_RX_DPHY_RDY_MASK (0x10000U)
27058#define IOMUXC_GPR_GPR_CSI2_2_RX_DPHY_RDY_SHIFT (16U)
27059#define IOMUXC_GPR_GPR_CSI2_2_RX_DPHY_RDY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_RX_DPHY_RDY_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_RX_DPHY_RDY_MASK)
27060#define IOMUXC_GPR_GPR_DSI_DPHY_DIRECTION_MASK (0x10000U)
27061#define IOMUXC_GPR_GPR_DSI_DPHY_DIRECTION_SHIFT (16U)
27062#define IOMUXC_GPR_GPR_DSI_DPHY_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_DPHY_DIRECTION_SHIFT)) & IOMUXC_GPR_GPR_DSI_DPHY_DIRECTION_MASK)
27063#define IOMUXC_GPR_GPR_OCRAM_TZ_EN_LOCK_MASK (0x10000U)
27064#define IOMUXC_GPR_GPR_OCRAM_TZ_EN_LOCK_SHIFT (16U)
27065#define IOMUXC_GPR_GPR_OCRAM_TZ_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_TZ_EN_LOCK_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_TZ_EN_LOCK_MASK)
27066#define IOMUXC_GPR_GPR_PCIE1_PHY_TX0_TERM_OFFSET_MASK (0x1F0000U)
27067#define IOMUXC_GPR_GPR_PCIE1_PHY_TX0_TERM_OFFSET_SHIFT (16U)
27068#define IOMUXC_GPR_GPR_PCIE1_PHY_TX0_TERM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PHY_TX0_TERM_OFFSET_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PHY_TX0_TERM_OFFSET_MASK)
27069#define IOMUXC_GPR_GPR_PCIE2_PHY_TX0_TERM_OFFSET_MASK (0x1F0000U)
27070#define IOMUXC_GPR_GPR_PCIE2_PHY_TX0_TERM_OFFSET_SHIFT (16U)
27071#define IOMUXC_GPR_GPR_PCIE2_PHY_TX0_TERM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PHY_TX0_TERM_OFFSET_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PHY_TX0_TERM_OFFSET_MASK)
27072#define IOMUXC_GPR_GPR_RDATA_WAIT_EN_PDG_MASK (0x10000U)
27073#define IOMUXC_GPR_GPR_RDATA_WAIT_EN_PDG_SHIFT (16U)
27074/*! RDATA_WAIT_EN_PDG
27075 * 0b0..read data wait state control configuration valid
27076 * 0b1..read data wait state control bit changed
27077 */
27078#define IOMUXC_GPR_GPR_RDATA_WAIT_EN_PDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_RDATA_WAIT_EN_PDG_SHIFT)) & IOMUXC_GPR_GPR_RDATA_WAIT_EN_PDG_MASK)
27079#define IOMUXC_GPR_GPR_SDMA1_IPG_STOP_ACK_MASK (0x10000U)
27080#define IOMUXC_GPR_GPR_SDMA1_IPG_STOP_ACK_SHIFT (16U)
27081/*! SDMA1_IPG_STOP_ACK
27082 * 0b0..stop acknowledge is not asserted
27083 * 0b1..stop acknowledge is asserted, peripheral is in STOP mode
27084 */
27085#define IOMUXC_GPR_GPR_SDMA1_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SDMA1_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SDMA1_IPG_STOP_ACK_MASK)
27086#define IOMUXC_GPR_GPR_TZASC_EN_LOCK_MASK (0x10000U)
27087#define IOMUXC_GPR_GPR_TZASC_EN_LOCK_SHIFT (16U)
27088#define IOMUXC_GPR_GPR_TZASC_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_TZASC_EN_LOCK_SHIFT)) & IOMUXC_GPR_GPR_TZASC_EN_LOCK_MASK)
27089#define IOMUXC_GPR_GPR_CSI2_1_CRC_ERR_MASK (0x20000U)
27090#define IOMUXC_GPR_GPR_CSI2_1_CRC_ERR_SHIFT (17U)
27091#define IOMUXC_GPR_GPR_CSI2_1_CRC_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_CRC_ERR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_CRC_ERR_MASK)
27092#define IOMUXC_GPR_GPR_CSI2_2_CRC_ERR_MASK (0x20000U)
27093#define IOMUXC_GPR_GPR_CSI2_2_CRC_ERR_SHIFT (17U)
27094#define IOMUXC_GPR_GPR_CSI2_2_CRC_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_CRC_ERR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_CRC_ERR_MASK)
27095#define IOMUXC_GPR_GPR_DSI_CRC_ERR_MASK (0x20000U)
27096#define IOMUXC_GPR_GPR_DSI_CRC_ERR_SHIFT (17U)
27097#define IOMUXC_GPR_GPR_DSI_CRC_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_CRC_ERR_SHIFT)) & IOMUXC_GPR_GPR_DSI_CRC_ERR_MASK)
27098#define IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_LOCK_MASK (0x3E0000U)
27099#define IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_LOCK_SHIFT (17U)
27100#define IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_LOCK_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_LOCK_MASK)
27101#define IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_MASK (0x1E0000U)
27102#define IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT (17U)
27103#define IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_MASK)
27104#define IOMUXC_GPR_GPR_RADDR_PIPE_EN_PDG_MASK (0x20000U)
27105#define IOMUXC_GPR_GPR_RADDR_PIPE_EN_PDG_SHIFT (17U)
27106/*! RADDR_PIPE_EN_PDG
27107 * 0b0..read address pipeline enable configuration valid
27108 * 0b1..read address pipeline enable bit changed
27109 */
27110#define IOMUXC_GPR_GPR_RADDR_PIPE_EN_PDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_RADDR_PIPE_EN_PDG_SHIFT)) & IOMUXC_GPR_GPR_RADDR_PIPE_EN_PDG_MASK)
27111#define IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_LOCK_MASK (0x20000U)
27112#define IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_LOCK_SHIFT (17U)
27113#define IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_LOCK_SHIFT)) & IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_LOCK_MASK)
27114#define IOMUXC_GPR_GPR_CSI2_1_ULPS_ACTIVE_MASK (0x7C0000U)
27115#define IOMUXC_GPR_GPR_CSI2_1_ULPS_ACTIVE_SHIFT (18U)
27116#define IOMUXC_GPR_GPR_CSI2_1_ULPS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ULPS_ACTIVE_MASK)
27117#define IOMUXC_GPR_GPR_CSI2_2_ULPS_ACTIVE_MASK (0x7C0000U)
27118#define IOMUXC_GPR_GPR_CSI2_2_ULPS_ACTIVE_SHIFT (18U)
27119#define IOMUXC_GPR_GPR_CSI2_2_ULPS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ULPS_ACTIVE_MASK)
27120#define IOMUXC_GPR_GPR_DSI_CALOUT_MASK (0xC0000U)
27121#define IOMUXC_GPR_GPR_DSI_CALOUT_SHIFT (18U)
27122#define IOMUXC_GPR_GPR_DSI_CALOUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_CALOUT_SHIFT)) & IOMUXC_GPR_GPR_DSI_CALOUT_MASK)
27123#define IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_LOCK_MASK (0x40000U)
27124#define IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_LOCK_SHIFT (18U)
27125#define IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_LOCK_SHIFT)) & IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_LOCK_MASK)
27126#define IOMUXC_GPR_GPR_WDATA_PIPE_EN_PDG_MASK (0x40000U)
27127#define IOMUXC_GPR_GPR_WDATA_PIPE_EN_PDG_SHIFT (18U)
27128/*! WDATA_PIPE_EN_PDG
27129 * 0b0..write data pipeline enable configuration valid
27130 * 0b1..write data pipeline enable bit changed
27131 */
27132#define IOMUXC_GPR_GPR_WDATA_PIPE_EN_PDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WDATA_PIPE_EN_PDG_SHIFT)) & IOMUXC_GPR_GPR_WDATA_PIPE_EN_PDG_MASK)
27133#define IOMUXC_GPR_GPR_ENET1_IPG_STOP_ACK_MASK (0x80000U)
27134#define IOMUXC_GPR_GPR_ENET1_IPG_STOP_ACK_SHIFT (19U)
27135/*! ENET1_IPG_STOP_ACK
27136 * 0b0..stop acknowledge is not asserted
27137 * 0b1..stop acknowledge is asserted, peripheral is in STOP mode
27138 */
27139#define IOMUXC_GPR_GPR_ENET1_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ENET1_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_ENET1_IPG_STOP_ACK_MASK)
27140#define IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_LOCK_MASK (0x80000U)
27141#define IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_LOCK_SHIFT (19U)
27142#define IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_LOCK_SHIFT)) & IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_LOCK_MASK)
27143#define IOMUXC_GPR_GPR_WADDR_PIPE_EN_PNDG_MASK (0x80000U)
27144#define IOMUXC_GPR_GPR_WADDR_PIPE_EN_PNDG_SHIFT (19U)
27145/*! WADDR_PIPE_EN_PNDG
27146 * 0b0..write address pipeline enable configuration valid
27147 * 0b1..write address pipeline enable bit changed
27148 */
27149#define IOMUXC_GPR_GPR_WADDR_PIPE_EN_PNDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WADDR_PIPE_EN_PNDG_SHIFT)) & IOMUXC_GPR_GPR_WADDR_PIPE_EN_PNDG_MASK)
27150#define IOMUXC_GPR_GPR_CPU_STANDBYWFE_MASK (0xF00000U)
27151#define IOMUXC_GPR_GPR_CPU_STANDBYWFE_SHIFT (20U)
27152#define IOMUXC_GPR_GPR_CPU_STANDBYWFE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CPU_STANDBYWFE_SHIFT)) & IOMUXC_GPR_GPR_CPU_STANDBYWFE_MASK)
27153#define IOMUXC_GPR_GPR_CSI2_1_D0_LB_ACTIVE_MASK (0x100000U)
27154#define IOMUXC_GPR_GPR_CSI2_1_D0_LB_ACTIVE_SHIFT (20U)
27155#define IOMUXC_GPR_GPR_CSI2_1_D0_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D0_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D0_LB_ACTIVE_MASK)
27156#define IOMUXC_GPR_GPR_CSI2_1_D1_LB_ACTIVE_MASK (0x100000U)
27157#define IOMUXC_GPR_GPR_CSI2_1_D1_LB_ACTIVE_SHIFT (20U)
27158#define IOMUXC_GPR_GPR_CSI2_1_D1_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D1_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D1_LB_ACTIVE_MASK)
27159#define IOMUXC_GPR_GPR_CSI2_1_D2_LB_ACTIVE_MASK (0x100000U)
27160#define IOMUXC_GPR_GPR_CSI2_1_D2_LB_ACTIVE_SHIFT (20U)
27161#define IOMUXC_GPR_GPR_CSI2_1_D2_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D2_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D2_LB_ACTIVE_MASK)
27162#define IOMUXC_GPR_GPR_CSI2_1_D3_LB_ACTIVE_MASK (0x100000U)
27163#define IOMUXC_GPR_GPR_CSI2_1_D3_LB_ACTIVE_SHIFT (20U)
27164#define IOMUXC_GPR_GPR_CSI2_1_D3_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D3_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D3_LB_ACTIVE_MASK)
27165#define IOMUXC_GPR_GPR_CSI2_2_D0_LB_ACTIVE_MASK (0x100000U)
27166#define IOMUXC_GPR_GPR_CSI2_2_D0_LB_ACTIVE_SHIFT (20U)
27167#define IOMUXC_GPR_GPR_CSI2_2_D0_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D0_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D0_LB_ACTIVE_MASK)
27168#define IOMUXC_GPR_GPR_CSI2_2_D1_LB_ACTIVE_MASK (0x100000U)
27169#define IOMUXC_GPR_GPR_CSI2_2_D1_LB_ACTIVE_SHIFT (20U)
27170#define IOMUXC_GPR_GPR_CSI2_2_D1_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D1_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D1_LB_ACTIVE_MASK)
27171#define IOMUXC_GPR_GPR_CSI2_2_D2_LB_ACTIVE_MASK (0x100000U)
27172#define IOMUXC_GPR_GPR_CSI2_2_D2_LB_ACTIVE_SHIFT (20U)
27173#define IOMUXC_GPR_GPR_CSI2_2_D2_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D2_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D2_LB_ACTIVE_MASK)
27174#define IOMUXC_GPR_GPR_CSI2_2_D3_LB_ACTIVE_MASK (0x100000U)
27175#define IOMUXC_GPR_GPR_CSI2_2_D3_LB_ACTIVE_SHIFT (20U)
27176#define IOMUXC_GPR_GPR_CSI2_2_D3_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D3_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D3_LB_ACTIVE_MASK)
27177#define IOMUXC_GPR_GPR_DSI_CALCOMPL_MASK (0x100000U)
27178#define IOMUXC_GPR_GPR_DSI_CALCOMPL_SHIFT (20U)
27179#define IOMUXC_GPR_GPR_DSI_CALCOMPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_CALCOMPL_SHIFT)) & IOMUXC_GPR_GPR_DSI_CALCOMPL_MASK)
27180#define IOMUXC_GPR_GPR_DSI_D0_LB_ACTIVE_MASK (0x100000U)
27181#define IOMUXC_GPR_GPR_DSI_D0_LB_ACTIVE_SHIFT (20U)
27182#define IOMUXC_GPR_GPR_DSI_D0_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D0_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_DSI_D0_LB_ACTIVE_MASK)
27183#define IOMUXC_GPR_GPR_DSI_D1_LB_ACTIVE_MASK (0x100000U)
27184#define IOMUXC_GPR_GPR_DSI_D1_LB_ACTIVE_SHIFT (20U)
27185#define IOMUXC_GPR_GPR_DSI_D1_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D1_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_DSI_D1_LB_ACTIVE_MASK)
27186#define IOMUXC_GPR_GPR_DSI_D2_LB_ACTIVE_MASK (0x100000U)
27187#define IOMUXC_GPR_GPR_DSI_D2_LB_ACTIVE_SHIFT (20U)
27188#define IOMUXC_GPR_GPR_DSI_D2_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D2_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_DSI_D2_LB_ACTIVE_MASK)
27189#define IOMUXC_GPR_GPR_DSI_D3_LB_ACTIVE_MASK (0x100000U)
27190#define IOMUXC_GPR_GPR_DSI_D3_LB_ACTIVE_SHIFT (20U)
27191#define IOMUXC_GPR_GPR_DSI_D3_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D3_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_DSI_D3_LB_ACTIVE_MASK)
27192#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3F00000U)
27193#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT (20U)
27194#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB_MASK)
27195#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3F00000U)
27196#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT (20U)
27197#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB_MASK)
27198#define IOMUXC_GPR_GPR_SDMA2_IPG_STOP_ACK_MASK (0x100000U)
27199#define IOMUXC_GPR_GPR_SDMA2_IPG_STOP_ACK_SHIFT (20U)
27200/*! SDMA2_IPG_STOP_ACK
27201 * 0b0..stop acknowledge is not asserted
27202 * 0b1..stop acknowledge is asserted, peripheral is in STOP mode
27203 */
27204#define IOMUXC_GPR_GPR_SDMA2_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SDMA2_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SDMA2_IPG_STOP_ACK_MASK)
27205#define IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_PNDG_MASK (0x100000U)
27206#define IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_PNDG_SHIFT (20U)
27207/*! S_RDATA_WAIT_EN_PNDG
27208 * 0b0..read data wait state control configuration valid
27209 * 0b1..read data wait state control bit changed
27210 */
27211#define IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_PNDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_PNDG_SHIFT)) & IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_PNDG_MASK)
27212#define IOMUXC_GPR_GPR_WDOG3_MASK_MASK (0x100000U)
27213#define IOMUXC_GPR_GPR_WDOG3_MASK_SHIFT (20U)
27214/*! WDOG3_MASK
27215 * 0b0..WDOG3 Timeout behaves normally
27216 * 0b1..WDOG3 Timeout is masked
27217 */
27218#define IOMUXC_GPR_GPR_WDOG3_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WDOG3_MASK_SHIFT)) & IOMUXC_GPR_GPR_WDOG3_MASK_MASK)
27219#define IOMUXC_GPR_GPR_DSI_ULPS_ACTIVE_MASK (0x3E00000U)
27220#define IOMUXC_GPR_GPR_DSI_ULPS_ACTIVE_SHIFT (21U)
27221#define IOMUXC_GPR_GPR_DSI_ULPS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_DSI_ULPS_ACTIVE_MASK)
27222#define IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_MASK (0x600000U)
27223#define IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_SHIFT (21U)
27224#define IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_MASK)
27225#define IOMUXC_GPR_GPR_PCIE1_PHY_RX0_EQ_MASK (0xE00000U)
27226#define IOMUXC_GPR_GPR_PCIE1_PHY_RX0_EQ_SHIFT (21U)
27227#define IOMUXC_GPR_GPR_PCIE1_PHY_RX0_EQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PHY_RX0_EQ_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PHY_RX0_EQ_MASK)
27228#define IOMUXC_GPR_GPR_PCIE2_PHY_RX0_EQ_MASK (0xE00000U)
27229#define IOMUXC_GPR_GPR_PCIE2_PHY_RX0_EQ_SHIFT (21U)
27230#define IOMUXC_GPR_GPR_PCIE2_PHY_RX0_EQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PHY_RX0_EQ_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PHY_RX0_EQ_MASK)
27231#define IOMUXC_GPR_GPR_SAI1_IPG_STOP_ACK_MASK (0x200000U)
27232#define IOMUXC_GPR_GPR_SAI1_IPG_STOP_ACK_SHIFT (21U)
27233/*! SAI1_IPG_STOP_ACK
27234 * 0b0..stop acknowledge is not asserted
27235 * 0b1..stop acknowledge is asserted, peripheral is in STOP mode
27236 */
27237#define IOMUXC_GPR_GPR_SAI1_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SAI1_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SAI1_IPG_STOP_ACK_MASK)
27238#define IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_PNDG_MASK (0x200000U)
27239#define IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_PNDG_SHIFT (21U)
27240/*! S_RADDR_PIPE_EN_PNDG
27241 * 0b0..read address pipeline enable configuration valid
27242 * 0b1..read address pipeline enable bit changed
27243 */
27244#define IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_PNDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_PNDG_SHIFT)) & IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_PNDG_MASK)
27245#define IOMUXC_GPR_GPR_SAI2_IPG_STOP_ACK_MASK (0x400000U)
27246#define IOMUXC_GPR_GPR_SAI2_IPG_STOP_ACK_SHIFT (22U)
27247/*! SAI2_IPG_STOP_ACK
27248 * 0b0..stop acknowledge is not asserted
27249 * 0b1..stop acknowledge is asserted, peripheral is in STOP mode
27250 */
27251#define IOMUXC_GPR_GPR_SAI2_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SAI2_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SAI2_IPG_STOP_ACK_MASK)
27252#define IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_PNDG_MASK (0x400000U)
27253#define IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_PNDG_SHIFT (22U)
27254/*! S_WDATA_PIPE_EN_PNDG
27255 * 0b0..write data pipeline enable configuration valid
27256 * 0b1..write data pipeline enable bit changed
27257 */
27258#define IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_PNDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_PNDG_SHIFT)) & IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_PNDG_MASK)
27259#define IOMUXC_GPR_GPR_CSI2_1_ERR_FIFO_WR_OVFL_MASK (0x800000U)
27260#define IOMUXC_GPR_GPR_CSI2_1_ERR_FIFO_WR_OVFL_SHIFT (23U)
27261#define IOMUXC_GPR_GPR_CSI2_1_ERR_FIFO_WR_OVFL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ERR_FIFO_WR_OVFL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ERR_FIFO_WR_OVFL_MASK)
27262#define IOMUXC_GPR_GPR_CSI2_2_ERR_FIFO_WR_OVFL_MASK (0x800000U)
27263#define IOMUXC_GPR_GPR_CSI2_2_ERR_FIFO_WR_OVFL_SHIFT (23U)
27264#define IOMUXC_GPR_GPR_CSI2_2_ERR_FIFO_WR_OVFL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ERR_FIFO_WR_OVFL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ERR_FIFO_WR_OVFL_MASK)
27265#define IOMUXC_GPR_GPR_SAI3_IPG_STOP_ACK_MASK (0x800000U)
27266#define IOMUXC_GPR_GPR_SAI3_IPG_STOP_ACK_SHIFT (23U)
27267/*! SAI3_IPG_STOP_ACK
27268 * 0b0..stop acknowledge is not asserted
27269 * 0b1..stop acknowledge is asserted, peripheral is in STOP mode
27270 */
27271#define IOMUXC_GPR_GPR_SAI3_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SAI3_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SAI3_IPG_STOP_ACK_MASK)
27272#define IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_PNDG_MASK (0x800000U)
27273#define IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_PNDG_SHIFT (23U)
27274/*! S_WADDR_PIPE_EN_PNDG
27275 * 0b0..write address pipeline enable configuration valid
27276 * 0b1..write address pipeline enable bit changed
27277 */
27278#define IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_PNDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_PNDG_SHIFT)) & IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_PNDG_MASK)
27279#define IOMUXC_GPR_GPR_TZASC1_SECURE_BOOT_LOCK_MASK (0x800000U)
27280#define IOMUXC_GPR_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT (23U)
27281/*! TZASC1_SECURE_BOOT_LOCK
27282 * 0b0..Secure boot lock is disabled
27283 * 0b1..Secure boot lock is enabled
27284 */
27285#define IOMUXC_GPR_GPR_TZASC1_SECURE_BOOT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT)) & IOMUXC_GPR_GPR_TZASC1_SECURE_BOOT_LOCK_MASK)
27286#define IOMUXC_GPR_GPR_CSI2_1_ERR_SEND_LEVEL_MASK (0x1000000U)
27287#define IOMUXC_GPR_GPR_CSI2_1_ERR_SEND_LEVEL_SHIFT (24U)
27288#define IOMUXC_GPR_GPR_CSI2_1_ERR_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ERR_SEND_LEVEL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ERR_SEND_LEVEL_MASK)
27289#define IOMUXC_GPR_GPR_CSI2_2_ERR_SEND_LEVEL_MASK (0x1000000U)
27290#define IOMUXC_GPR_GPR_CSI2_2_ERR_SEND_LEVEL_SHIFT (24U)
27291#define IOMUXC_GPR_GPR_CSI2_2_ERR_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ERR_SEND_LEVEL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ERR_SEND_LEVEL_MASK)
27292#define IOMUXC_GPR_GPR_PCIE1_PHY_LOS_LEVEL_MASK (0x1F000000U)
27293#define IOMUXC_GPR_GPR_PCIE1_PHY_LOS_LEVEL_SHIFT (24U)
27294#define IOMUXC_GPR_GPR_PCIE1_PHY_LOS_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PHY_LOS_LEVEL_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PHY_LOS_LEVEL_MASK)
27295#define IOMUXC_GPR_GPR_PCIE2_PHY_LOS_LEVEL_MASK (0x1F000000U)
27296#define IOMUXC_GPR_GPR_PCIE2_PHY_LOS_LEVEL_SHIFT (24U)
27297#define IOMUXC_GPR_GPR_PCIE2_PHY_LOS_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PHY_LOS_LEVEL_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PHY_LOS_LEVEL_MASK)
27298#define IOMUXC_GPR_GPR_SAI4_IPG_STOP_ACK_MASK (0x1000000U)
27299#define IOMUXC_GPR_GPR_SAI4_IPG_STOP_ACK_SHIFT (24U)
27300/*! SAI4_IPG_STOP_ACK
27301 * 0b0..stop acknowledge is not asserted
27302 * 0b1..stop acknowledge is asserted, peripheral is in STOP mode
27303 */
27304#define IOMUXC_GPR_GPR_SAI4_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SAI4_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SAI4_IPG_STOP_ACK_MASK)
27305#define IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_STATUS_BUS_SELECT_MASK (0x1E000000U)
27306#define IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT (25U)
27307#define IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_STATUS_BUS_SELECT_MASK)
27308#define IOMUXC_GPR_GPR_SAI5_IPG_STOP_ACK_MASK (0x2000000U)
27309#define IOMUXC_GPR_GPR_SAI5_IPG_STOP_ACK_SHIFT (25U)
27310/*! SAI5_IPG_STOP_ACK
27311 * 0b0..stop acknowledge is not asserted
27312 * 0b1..stop acknowledge is asserted, peripheral is in STOP mode
27313 */
27314#define IOMUXC_GPR_GPR_SAI5_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SAI5_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SAI5_IPG_STOP_ACK_MASK)
27315#define IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_LOCK_MASK (0x4000000U)
27316#define IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_LOCK_SHIFT (26U)
27317#define IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_LOCK_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_LOCK_MASK)
27318#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN1_MASK (0xFC000000U)
27319#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN1_SHIFT (26U)
27320#define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN1_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN1_MASK)
27321#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN1_MASK (0xFC000000U)
27322#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN1_SHIFT (26U)
27323#define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN1_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN1_MASK)
27324#define IOMUXC_GPR_GPR_SAI6_IPG_STOP_ACK_MASK (0x4000000U)
27325#define IOMUXC_GPR_GPR_SAI6_IPG_STOP_ACK_SHIFT (26U)
27326/*! SAI6_IPG_STOP_ACK
27327 * 0b0..stop acknowledge is not asserted
27328 * 0b1..stop acknowledge is asserted, peripheral is in STOP mode
27329 */
27330#define IOMUXC_GPR_GPR_SAI6_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SAI6_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SAI6_IPG_STOP_ACK_MASK)
27331#define IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_LOCK_MASK (0x38000000U)
27332#define IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_LOCK_SHIFT (27U)
27333#define IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_LOCK_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_LOCK_MASK)
27334#define IOMUXC_GPR_GPR_DBG_ACK_MASK (0xF0000000U)
27335#define IOMUXC_GPR_GPR_DBG_ACK_SHIFT (28U)
27336#define IOMUXC_GPR_GPR_DBG_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DBG_ACK_SHIFT)) & IOMUXC_GPR_GPR_DBG_ACK_MASK)
27337#define IOMUXC_GPR_GPR_PCIE1_PHY_LOS_BIAS_MASK (0xE0000000U)
27338#define IOMUXC_GPR_GPR_PCIE1_PHY_LOS_BIAS_SHIFT (29U)
27339#define IOMUXC_GPR_GPR_PCIE1_PHY_LOS_BIAS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PHY_LOS_BIAS_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PHY_LOS_BIAS_MASK)
27340#define IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_CTRL_BUS_MASK (0x60000000U)
27341#define IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_CTRL_BUS_SHIFT (29U)
27342#define IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_CTRL_BUS_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_CTRL_BUS_MASK)
27343#define IOMUXC_GPR_GPR_PCIE2_PHY_LOS_BIAS_MASK (0xE0000000U)
27344#define IOMUXC_GPR_GPR_PCIE2_PHY_LOS_BIAS_SHIFT (29U)
27345#define IOMUXC_GPR_GPR_PCIE2_PHY_LOS_BIAS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PHY_LOS_BIAS_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PHY_LOS_BIAS_MASK)
27346#define IOMUXC_GPR_GPR_PCIE_DIAG_BUS_SEL_MASK (0x80000000U)
27347#define IOMUXC_GPR_GPR_PCIE_DIAG_BUS_SEL_SHIFT (31U)
27348#define IOMUXC_GPR_GPR_PCIE_DIAG_BUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE_DIAG_BUS_SEL_SHIFT)) & IOMUXC_GPR_GPR_PCIE_DIAG_BUS_SEL_MASK)
27349/*! @} */
27350
27351/* The count of IOMUXC_GPR_GPR */
27352#define IOMUXC_GPR_GPR_COUNT (48U)
27353
27354
27355/*!
27356 * @}
27357 */ /* end of group IOMUXC_GPR_Register_Masks */
27358
27359
27360/* IOMUXC_GPR - Peripheral instance base addresses */
27361/** Peripheral IOMUXC_GPR base address */
27362#define IOMUXC_GPR_BASE (0x30340000u)
27363/** Peripheral IOMUXC_GPR base pointer */
27364#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
27365/** Array initializer of IOMUXC_GPR peripheral base addresses */
27366#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE }
27367/** Array initializer of IOMUXC_GPR peripheral base pointers */
27368#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR }
27369
27370/*!
27371 * @}
27372 */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */
27373
27374
27375/* ----------------------------------------------------------------------------
27376 -- IRQ_STEER Peripheral Access Layer
27377 ---------------------------------------------------------------------------- */
27378
27379/*!
27380 * @addtogroup IRQ_STEER_Peripheral_Access_Layer IRQ_STEER Peripheral Access Layer
27381 * @{
27382 */
27383
27384/** IRQ_STEER - Register Layout Typedef */
27385typedef struct {
27386 __IO uint32_t CHANNCTL; /**< Channel n Control Register, offset: 0x0 */
27387 __IO uint32_t CHN_MASK[16]; /**< Channel n Interrupt Mask Register, array offset: 0x4, array step: 0x4 */
27388 __IO uint32_t CHN_SET[16]; /**< Channel n Interrupt Set Register, array offset: 0x44, array step: 0x4 */
27389 __I uint32_t CHN_STATUS[16]; /**< Channel n Interrupt Status Register, array offset: 0x84, array step: 0x4 */
27390 __IO uint32_t CHN_MINTDIS; /**< Channel n Master Interrupt Disable Register, offset: 0xC4 */
27391 __I uint32_t CHN_MSTRSTAT; /**< Channel n Master Status Register, offset: 0xC8 */
27392} IRQ_STEER_Type;
27393
27394/* ----------------------------------------------------------------------------
27395 -- IRQ_STEER Register Masks
27396 ---------------------------------------------------------------------------- */
27397
27398/*!
27399 * @addtogroup IRQ_STEER_Register_Masks IRQ_STEER Register Masks
27400 * @{
27401 */
27402
27403/*! @name CHANNCTL - Channel n Control Register */
27404/*! @{ */
27405#define IRQ_STEER_CHANNCTL_CH0_MASK (0x1U)
27406#define IRQ_STEER_CHANNCTL_CH0_SHIFT (0U)
27407/*! CH0 - Channel 0 control
27408 * 0b0..Disable channel 0
27409 * 0b1..Enable channel 0
27410 */
27411#define IRQ_STEER_CHANNCTL_CH0(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHANNCTL_CH0_SHIFT)) & IRQ_STEER_CHANNCTL_CH0_MASK)
27412#define IRQ_STEER_CHANNCTL_CH1_MASK (0x2U)
27413#define IRQ_STEER_CHANNCTL_CH1_SHIFT (1U)
27414/*! CH1 - Channel 1 control
27415 * 0b0..Disable channel 1
27416 * 0b1..Enable channel 1
27417 */
27418#define IRQ_STEER_CHANNCTL_CH1(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHANNCTL_CH1_SHIFT)) & IRQ_STEER_CHANNCTL_CH1_MASK)
27419#define IRQ_STEER_CHANNCTL_CH2_MASK (0x4U)
27420#define IRQ_STEER_CHANNCTL_CH2_SHIFT (2U)
27421/*! CH2 - Channel 2 control
27422 * 0b0..Disable channel 2
27423 * 0b1..Enable channel 2
27424 */
27425#define IRQ_STEER_CHANNCTL_CH2(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHANNCTL_CH2_SHIFT)) & IRQ_STEER_CHANNCTL_CH2_MASK)
27426#define IRQ_STEER_CHANNCTL_CH3_MASK (0x8U)
27427#define IRQ_STEER_CHANNCTL_CH3_SHIFT (3U)
27428/*! CH3 - Channel 3 control
27429 * 0b0..Disable channel 3
27430 * 0b1..Enable channel 3
27431 */
27432#define IRQ_STEER_CHANNCTL_CH3(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHANNCTL_CH3_SHIFT)) & IRQ_STEER_CHANNCTL_CH3_MASK)
27433#define IRQ_STEER_CHANNCTL_CH4_MASK (0x10U)
27434#define IRQ_STEER_CHANNCTL_CH4_SHIFT (4U)
27435/*! CH4 - Channel 4 control
27436 * 0b0..Disable channel 4
27437 * 0b1..Enable channel 4
27438 */
27439#define IRQ_STEER_CHANNCTL_CH4(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHANNCTL_CH4_SHIFT)) & IRQ_STEER_CHANNCTL_CH4_MASK)
27440/*! @} */
27441
27442/*! @name CHN_MASK - Channel n Interrupt Mask Register */
27443/*! @{ */
27444#define IRQ_STEER_CHN_MASK_MASKFLD_MASK (0xFFFFFFFFU)
27445#define IRQ_STEER_CHN_MASK_MASKFLD_SHIFT (0U)
27446/*! MASKFLD - Mask bits
27447 * 0b00000000000000000000000000000000..Mask interrupt
27448 * 0b00000000000000000000000000000001..Do not mask interrupt
27449 */
27450#define IRQ_STEER_CHN_MASK_MASKFLD(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHN_MASK_MASKFLD_SHIFT)) & IRQ_STEER_CHN_MASK_MASKFLD_MASK)
27451/*! @} */
27452
27453/* The count of IRQ_STEER_CHN_MASK */
27454#define IRQ_STEER_CHN_MASK_COUNT (16U)
27455
27456/*! @name CHN_SET - Channel n Interrupt Set Register */
27457/*! @{ */
27458#define IRQ_STEER_CHN_SET_FORCEFLD_MASK (0xFFFFFFFFU)
27459#define IRQ_STEER_CHN_SET_FORCEFLD_SHIFT (0U)
27460/*! FORCEFLD - Brief bitfield description.
27461 * 0b00000000000000000000000000000000..Normal operation
27462 * 0b00000000000000000000000000000001..Force interrupt
27463 */
27464#define IRQ_STEER_CHN_SET_FORCEFLD(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHN_SET_FORCEFLD_SHIFT)) & IRQ_STEER_CHN_SET_FORCEFLD_MASK)
27465/*! @} */
27466
27467/* The count of IRQ_STEER_CHN_SET */
27468#define IRQ_STEER_CHN_SET_COUNT (16U)
27469
27470/*! @name CHN_STATUS - Channel n Interrupt Status Register */
27471/*! @{ */
27472#define IRQ_STEER_CHN_STATUS_STATUS_MASK (0xFFFFFFFFU)
27473#define IRQ_STEER_CHN_STATUS_STATUS_SHIFT (0U)
27474/*! STATUS - Status of an interrupt
27475 * 0b00000000000000000000000000000000..Interrupt is not set.
27476 * 0b00000000000000000000000000000001..Interrupt is set.
27477 */
27478#define IRQ_STEER_CHN_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHN_STATUS_STATUS_SHIFT)) & IRQ_STEER_CHN_STATUS_STATUS_MASK)
27479/*! @} */
27480
27481/* The count of IRQ_STEER_CHN_STATUS */
27482#define IRQ_STEER_CHN_STATUS_COUNT (16U)
27483
27484/*! @name CHN_MINTDIS - Channel n Master Interrupt Disable Register */
27485/*! @{ */
27486#define IRQ_STEER_CHN_MINTDIS_DISABLE_MASK (0xFFU)
27487#define IRQ_STEER_CHN_MINTDIS_DISABLE_SHIFT (0U)
27488/*! DISABLE - Each bit of this field disables the corresponding interrupts in table above.
27489 * 0b00000000..Enable interrupts
27490 * 0b00000001..Disable interrupts
27491 */
27492#define IRQ_STEER_CHN_MINTDIS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHN_MINTDIS_DISABLE_SHIFT)) & IRQ_STEER_CHN_MINTDIS_DISABLE_MASK)
27493/*! @} */
27494
27495/*! @name CHN_MSTRSTAT - Channel n Master Status Register */
27496/*! @{ */
27497#define IRQ_STEER_CHN_MSTRSTAT_STATUS_MASK (0x1U)
27498#define IRQ_STEER_CHN_MSTRSTAT_STATUS_SHIFT (0U)
27499/*! STATUS - Status of all interrupts
27500 * 0b0..No interrupts are asserted.
27501 * 0b1..At least one interrupt is asserted.
27502 */
27503#define IRQ_STEER_CHN_MSTRSTAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHN_MSTRSTAT_STATUS_SHIFT)) & IRQ_STEER_CHN_MSTRSTAT_STATUS_MASK)
27504/*! @} */
27505
27506
27507/*!
27508 * @}
27509 */ /* end of group IRQ_STEER_Register_Masks */
27510
27511
27512/* IRQ_STEER - Peripheral instance base addresses */
27513/** Peripheral IRQ_STEER base address */
27514#define IRQ_STEER_BASE (0x32E2D000u)
27515/** Peripheral IRQ_STEER base pointer */
27516#define IRQ_STEER ((IRQ_STEER_Type *)IRQ_STEER_BASE)
27517/** Array initializer of IRQ_STEER peripheral base addresses */
27518#define IRQ_STEER_BASE_ADDRS { IRQ_STEER_BASE }
27519/** Array initializer of IRQ_STEER peripheral base pointers */
27520#define IRQ_STEER_BASE_PTRS { IRQ_STEER }
27521
27522/*!
27523 * @}
27524 */ /* end of group IRQ_STEER_Peripheral_Access_Layer */
27525
27526
27527/* ----------------------------------------------------------------------------
27528 -- LCDIF Peripheral Access Layer
27529 ---------------------------------------------------------------------------- */
27530
27531/*!
27532 * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer
27533 * @{
27534 */
27535
27536/** LCDIF - Register Layout Typedef */
27537typedef struct {
27538 __IO uint32_t CTRL; /**< LCDIF General Control Register, offset: 0x0 */
27539 __IO uint32_t CTRL_SET; /**< LCDIF General Control Register, offset: 0x4 */
27540 __IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 */
27541 __IO uint32_t CTRL_TOG; /**< LCDIF General Control Register, offset: 0xC */
27542 __IO uint32_t CTRL1; /**< LCDIF General Control1 Register, offset: 0x10 */
27543 __IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x14 */
27544 __IO uint32_t CTRL1_CLR; /**< LCDIF General Control1 Register, offset: 0x18 */
27545 __IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1C */
27546 __IO uint32_t CTRL2; /**< LCDIF General Control2 Register, offset: 0x20 */
27547 __IO uint32_t CTRL2_SET; /**< LCDIF General Control2 Register, offset: 0x24 */
27548 __IO uint32_t CTRL2_CLR; /**< LCDIF General Control2 Register, offset: 0x28 */
27549 __IO uint32_t CTRL2_TOG; /**< LCDIF General Control2 Register, offset: 0x2C */
27550 __IO uint32_t TRANSFER_COUNT; /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */
27551 uint8_t RESERVED_0[12];
27552 __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */
27553 uint8_t RESERVED_1[12];
27554 __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */
27555 uint8_t RESERVED_2[12];
27556 __IO uint32_t TIMING; /**< LCD Interface Timing Register, offset: 0x60 */
27557 uint8_t RESERVED_3[12];
27558 __IO uint32_t VDCTRL0; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */
27559 __IO uint32_t VDCTRL0_SET; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */
27560 __IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */
27561 __IO uint32_t VDCTRL0_TOG; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */
27562 __IO uint32_t VDCTRL1; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */
27563 uint8_t RESERVED_4[12];
27564 __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */
27565 uint8_t RESERVED_5[12];
27566 __IO uint32_t VDCTRL3; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */
27567 uint8_t RESERVED_6[12];
27568 __IO uint32_t VDCTRL4; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */
27569 uint8_t RESERVED_7[12];
27570 __IO uint32_t DVICTRL0; /**< Digital Video Interface Control0 Register, offset: 0xC0 */
27571 uint8_t RESERVED_8[12];
27572 __IO uint32_t DVICTRL1; /**< Digital Video Interface Control1 Register, offset: 0xD0 */
27573 uint8_t RESERVED_9[12];
27574 __IO uint32_t DVICTRL2; /**< Digital Video Interface Control2 Register, offset: 0xE0 */
27575 uint8_t RESERVED_10[12];
27576 __IO uint32_t DVICTRL3; /**< Digital Video Interface Control3 Register, offset: 0xF0 */
27577 uint8_t RESERVED_11[12];
27578 __IO uint32_t DVICTRL4; /**< Digital Video Interface Control4 Register, offset: 0x100 */
27579 uint8_t RESERVED_12[12];
27580 __IO uint32_t CSC_COEFF0; /**< RGB to YCbCr 4:2:2 CSC Coefficient0 Register, offset: 0x110 */
27581 uint8_t RESERVED_13[12];
27582 __IO uint32_t CSC_COEFF1; /**< RGB to YCbCr 4:2:2 CSC Coefficient1 Register, offset: 0x120 */
27583 uint8_t RESERVED_14[12];
27584 __IO uint32_t CSC_COEFF2; /**< RGB to YCbCr 4:2:2 CSC Coefficent2 Register, offset: 0x130 */
27585 uint8_t RESERVED_15[12];
27586 __IO uint32_t CSC_COEFF3; /**< RGB to YCbCr 4:2:2 CSC Coefficient3 Register, offset: 0x140 */
27587 uint8_t RESERVED_16[12];
27588 __IO uint32_t CSC_COEFF4; /**< RGB to YCbCr 4:2:2 CSC Coefficient4 Register, offset: 0x150 */
27589 uint8_t RESERVED_17[12];
27590 __IO uint32_t CSC_OFFSET; /**< RGB to YCbCr 4:2:2 CSC Offset Register, offset: 0x160 */
27591 uint8_t RESERVED_18[12];
27592 __IO uint32_t CSC_LIMIT; /**< RGB to YCbCr 4:2:2 CSC Limit Register, offset: 0x170 */
27593 uint8_t RESERVED_19[12];
27594 __IO uint32_t DATA; /**< LCD Interface Data Register, offset: 0x180 */
27595 uint8_t RESERVED_20[12];
27596 __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */
27597 uint8_t RESERVED_21[12];
27598 __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */
27599 uint8_t RESERVED_22[12];
27600 __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */
27601 uint8_t RESERVED_23[76];
27602 __IO uint32_t THRES; /**< LCDIF Threshold Register, offset: 0x200 */
27603 uint8_t RESERVED_24[12];
27604 __IO uint32_t AS_CTRL; /**< LCDIF AS Buffer Control Register, offset: 0x210 */
27605 uint8_t RESERVED_25[12];
27606 __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x220 */
27607 uint8_t RESERVED_26[12];
27608 __IO uint32_t AS_NEXT_BUF; /**< , offset: 0x230 */
27609 uint8_t RESERVED_27[12];
27610 __IO uint32_t AS_CLRKEYLOW; /**< LCDIF Overlay Color Key Low, offset: 0x240 */
27611 uint8_t RESERVED_28[12];
27612 __IO uint32_t AS_CLRKEYHIGH; /**< LCDIF Overlay Color Key High, offset: 0x250 */
27613 uint8_t RESERVED_29[12];
27614 __IO uint32_t SYNC_DELAY; /**< LCD working insync mode with CSI for VSYNC delay, offset: 0x260 */
27615} LCDIF_Type;
27616
27617/* ----------------------------------------------------------------------------
27618 -- LCDIF Register Masks
27619 ---------------------------------------------------------------------------- */
27620
27621/*!
27622 * @addtogroup LCDIF_Register_Masks LCDIF Register Masks
27623 * @{
27624 */
27625
27626/*! @name CTRL - LCDIF General Control Register */
27627/*! @{ */
27628#define LCDIF_CTRL_RUN_MASK (0x1U)
27629#define LCDIF_CTRL_RUN_SHIFT (0U)
27630#define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)
27631#define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U)
27632#define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U)
27633/*! DATA_FORMAT_24_BIT
27634 * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
27635 * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.
27636 */
27637#define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)
27638#define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U)
27639#define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U)
27640/*! DATA_FORMAT_18_BIT
27641 * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
27642 * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
27643 */
27644#define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)
27645#define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U)
27646#define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U)
27647#define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)
27648#define LCDIF_CTRL_RSRVD0_MASK (0x10U)
27649#define LCDIF_CTRL_RSRVD0_SHIFT (4U)
27650#define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)
27651#define LCDIF_CTRL_MASTER_MASK (0x20U)
27652#define LCDIF_CTRL_MASTER_SHIFT (5U)
27653#define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)
27654#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
27655#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
27656#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)
27657#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK (0x80U)
27658#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT (7U)
27659#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK)
27660#define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U)
27661#define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U)
27662/*! WORD_LENGTH
27663 * 0b00..Input data is 16 bits per pixel.
27664 * 0b01..Input data is 8 bits wide.
27665 * 0b10..Input data is 18 bits per pixel.
27666 * 0b11..Input data is 24 bits per pixel.
27667 */
27668#define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)
27669#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U)
27670#define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U)
27671/*! LCD_DATABUS_WIDTH
27672 * 0b00..16-bit data bus mode.
27673 * 0b01..8-bit data bus mode.
27674 * 0b10..18-bit data bus mode.
27675 * 0b11..24-bit data bus mode.
27676 */
27677#define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)
27678#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U)
27679#define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U)
27680/*! CSC_DATA_SWIZZLE
27681 * 0b00..No byte swapping.(Little endian)
27682 * 0b00..Little Endian byte ordering (same as NO_SWAP).
27683 * 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
27684 * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
27685 * 0b10..Swap half-words.
27686 * 0b11..Swap bytes within each half-word.
27687 */
27688#define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)
27689#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U)
27690#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U)
27691/*! INPUT_DATA_SWIZZLE
27692 * 0b00..No byte swapping.(Little endian)
27693 * 0b00..Little Endian byte ordering (same as NO_SWAP).
27694 * 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
27695 * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
27696 * 0b10..Swap half-words.
27697 * 0b11..Swap bytes within each half-word.
27698 */
27699#define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)
27700#define LCDIF_CTRL_DATA_SELECT_MASK (0x10000U)
27701#define LCDIF_CTRL_DATA_SELECT_SHIFT (16U)
27702/*! DATA_SELECT
27703 * 0b0..Command Mode. LCD_RS signal is Low.
27704 * 0b1..Data Mode. LCD_RS signal is High.
27705 */
27706#define LCDIF_CTRL_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SELECT_SHIFT)) & LCDIF_CTRL_DATA_SELECT_MASK)
27707#define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U)
27708#define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U)
27709#define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)
27710#define LCDIF_CTRL_VSYNC_MODE_MASK (0x40000U)
27711#define LCDIF_CTRL_VSYNC_MODE_SHIFT (18U)
27712#define LCDIF_CTRL_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_VSYNC_MODE_MASK)
27713#define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U)
27714#define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U)
27715#define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)
27716#define LCDIF_CTRL_DVI_MODE_MASK (0x100000U)
27717#define LCDIF_CTRL_DVI_MODE_SHIFT (20U)
27718#define LCDIF_CTRL_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DVI_MODE_SHIFT)) & LCDIF_CTRL_DVI_MODE_MASK)
27719#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U)
27720#define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U)
27721#define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)
27722#define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U)
27723#define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U)
27724/*! DATA_SHIFT_DIR
27725 * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
27726 * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
27727 */
27728#define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)
27729#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U)
27730#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT (27U)
27731#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK)
27732#define LCDIF_CTRL_READ_WRITEB_MASK (0x10000000U)
27733#define LCDIF_CTRL_READ_WRITEB_SHIFT (28U)
27734#define LCDIF_CTRL_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_READ_WRITEB_SHIFT)) & LCDIF_CTRL_READ_WRITEB_MASK)
27735#define LCDIF_CTRL_YCBCR422_INPUT_MASK (0x20000000U)
27736#define LCDIF_CTRL_YCBCR422_INPUT_SHIFT (29U)
27737#define LCDIF_CTRL_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_YCBCR422_INPUT_MASK)
27738#define LCDIF_CTRL_CLKGATE_MASK (0x40000000U)
27739#define LCDIF_CTRL_CLKGATE_SHIFT (30U)
27740#define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)
27741#define LCDIF_CTRL_SFTRST_MASK (0x80000000U)
27742#define LCDIF_CTRL_SFTRST_SHIFT (31U)
27743#define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)
27744/*! @} */
27745
27746/*! @name CTRL_SET - LCDIF General Control Register */
27747/*! @{ */
27748#define LCDIF_CTRL_SET_RUN_MASK (0x1U)
27749#define LCDIF_CTRL_SET_RUN_SHIFT (0U)
27750#define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)
27751#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U)
27752#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U)
27753/*! DATA_FORMAT_24_BIT
27754 * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
27755 * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.
27756 */
27757#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)
27758#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U)
27759#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U)
27760/*! DATA_FORMAT_18_BIT
27761 * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
27762 * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
27763 */
27764#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)
27765#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U)
27766#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U)
27767#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)
27768#define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U)
27769#define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U)
27770#define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)
27771#define LCDIF_CTRL_SET_MASTER_MASK (0x20U)
27772#define LCDIF_CTRL_SET_MASTER_SHIFT (5U)
27773#define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)
27774#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
27775#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
27776#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)
27777#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK (0x80U)
27778#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT (7U)
27779#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK)
27780#define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U)
27781#define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U)
27782/*! WORD_LENGTH
27783 * 0b00..Input data is 16 bits per pixel.
27784 * 0b01..Input data is 8 bits wide.
27785 * 0b10..Input data is 18 bits per pixel.
27786 * 0b11..Input data is 24 bits per pixel.
27787 */
27788#define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)
27789#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U)
27790#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U)
27791/*! LCD_DATABUS_WIDTH
27792 * 0b00..16-bit data bus mode.
27793 * 0b01..8-bit data bus mode.
27794 * 0b10..18-bit data bus mode.
27795 * 0b11..24-bit data bus mode.
27796 */
27797#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)
27798#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U)
27799#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U)
27800/*! CSC_DATA_SWIZZLE
27801 * 0b00..No byte swapping.(Little endian)
27802 * 0b00..Little Endian byte ordering (same as NO_SWAP).
27803 * 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
27804 * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
27805 * 0b10..Swap half-words.
27806 * 0b11..Swap bytes within each half-word.
27807 */
27808#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)
27809#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U)
27810#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U)
27811/*! INPUT_DATA_SWIZZLE
27812 * 0b00..No byte swapping.(Little endian)
27813 * 0b00..Little Endian byte ordering (same as NO_SWAP).
27814 * 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
27815 * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
27816 * 0b10..Swap half-words.
27817 * 0b11..Swap bytes within each half-word.
27818 */
27819#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)
27820#define LCDIF_CTRL_SET_DATA_SELECT_MASK (0x10000U)
27821#define LCDIF_CTRL_SET_DATA_SELECT_SHIFT (16U)
27822/*! DATA_SELECT
27823 * 0b0..Command Mode. LCD_RS signal is Low.
27824 * 0b1..Data Mode. LCD_RS signal is High.
27825 */
27826#define LCDIF_CTRL_SET_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SELECT_SHIFT)) & LCDIF_CTRL_SET_DATA_SELECT_MASK)
27827#define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U)
27828#define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U)
27829#define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)
27830#define LCDIF_CTRL_SET_VSYNC_MODE_MASK (0x40000U)
27831#define LCDIF_CTRL_SET_VSYNC_MODE_SHIFT (18U)
27832#define LCDIF_CTRL_SET_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_SET_VSYNC_MODE_MASK)
27833#define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U)
27834#define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U)
27835#define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)
27836#define LCDIF_CTRL_SET_DVI_MODE_MASK (0x100000U)
27837#define LCDIF_CTRL_SET_DVI_MODE_SHIFT (20U)
27838#define LCDIF_CTRL_SET_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DVI_MODE_SHIFT)) & LCDIF_CTRL_SET_DVI_MODE_MASK)
27839#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U)
27840#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U)
27841#define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)
27842#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U)
27843#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U)
27844/*! DATA_SHIFT_DIR
27845 * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
27846 * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
27847 */
27848#define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)
27849#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U)
27850#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT (27U)
27851#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK)
27852#define LCDIF_CTRL_SET_READ_WRITEB_MASK (0x10000000U)
27853#define LCDIF_CTRL_SET_READ_WRITEB_SHIFT (28U)
27854#define LCDIF_CTRL_SET_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_READ_WRITEB_SHIFT)) & LCDIF_CTRL_SET_READ_WRITEB_MASK)
27855#define LCDIF_CTRL_SET_YCBCR422_INPUT_MASK (0x20000000U)
27856#define LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT (29U)
27857#define LCDIF_CTRL_SET_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_SET_YCBCR422_INPUT_MASK)
27858#define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U)
27859#define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U)
27860#define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)
27861#define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U)
27862#define LCDIF_CTRL_SET_SFTRST_SHIFT (31U)
27863#define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)
27864/*! @} */
27865
27866/*! @name CTRL_CLR - LCDIF General Control Register */
27867/*! @{ */
27868#define LCDIF_CTRL_CLR_RUN_MASK (0x1U)
27869#define LCDIF_CTRL_CLR_RUN_SHIFT (0U)
27870#define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)
27871#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U)
27872#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U)
27873/*! DATA_FORMAT_24_BIT
27874 * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
27875 * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.
27876 */
27877#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)
27878#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U)
27879#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U)
27880/*! DATA_FORMAT_18_BIT
27881 * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
27882 * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
27883 */
27884#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)
27885#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U)
27886#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U)
27887#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)
27888#define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U)
27889#define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U)
27890#define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)
27891#define LCDIF_CTRL_CLR_MASTER_MASK (0x20U)
27892#define LCDIF_CTRL_CLR_MASTER_SHIFT (5U)
27893#define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)
27894#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
27895#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
27896#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)
27897#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK (0x80U)
27898#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT (7U)
27899#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK)
27900#define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U)
27901#define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U)
27902/*! WORD_LENGTH
27903 * 0b00..Input data is 16 bits per pixel.
27904 * 0b01..Input data is 8 bits wide.
27905 * 0b10..Input data is 18 bits per pixel.
27906 * 0b11..Input data is 24 bits per pixel.
27907 */
27908#define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)
27909#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U)
27910#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U)
27911/*! LCD_DATABUS_WIDTH
27912 * 0b00..16-bit data bus mode.
27913 * 0b01..8-bit data bus mode.
27914 * 0b10..18-bit data bus mode.
27915 * 0b11..24-bit data bus mode.
27916 */
27917#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)
27918#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U)
27919#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U)
27920/*! CSC_DATA_SWIZZLE
27921 * 0b00..No byte swapping.(Little endian)
27922 * 0b00..Little Endian byte ordering (same as NO_SWAP).
27923 * 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
27924 * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
27925 * 0b10..Swap half-words.
27926 * 0b11..Swap bytes within each half-word.
27927 */
27928#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)
27929#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U)
27930#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U)
27931/*! INPUT_DATA_SWIZZLE
27932 * 0b00..No byte swapping.(Little endian)
27933 * 0b00..Little Endian byte ordering (same as NO_SWAP).
27934 * 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
27935 * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
27936 * 0b10..Swap half-words.
27937 * 0b11..Swap bytes within each half-word.
27938 */
27939#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)
27940#define LCDIF_CTRL_CLR_DATA_SELECT_MASK (0x10000U)
27941#define LCDIF_CTRL_CLR_DATA_SELECT_SHIFT (16U)
27942/*! DATA_SELECT
27943 * 0b0..Command Mode. LCD_RS signal is Low.
27944 * 0b1..Data Mode. LCD_RS signal is High.
27945 */
27946#define LCDIF_CTRL_CLR_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SELECT_SHIFT)) & LCDIF_CTRL_CLR_DATA_SELECT_MASK)
27947#define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U)
27948#define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U)
27949#define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)
27950#define LCDIF_CTRL_CLR_VSYNC_MODE_MASK (0x40000U)
27951#define LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT (18U)
27952#define LCDIF_CTRL_CLR_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_CLR_VSYNC_MODE_MASK)
27953#define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U)
27954#define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U)
27955#define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)
27956#define LCDIF_CTRL_CLR_DVI_MODE_MASK (0x100000U)
27957#define LCDIF_CTRL_CLR_DVI_MODE_SHIFT (20U)
27958#define LCDIF_CTRL_CLR_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DVI_MODE_SHIFT)) & LCDIF_CTRL_CLR_DVI_MODE_MASK)
27959#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U)
27960#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U)
27961#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)
27962#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U)
27963#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U)
27964/*! DATA_SHIFT_DIR
27965 * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
27966 * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
27967 */
27968#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)
27969#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U)
27970#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT (27U)
27971#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK)
27972#define LCDIF_CTRL_CLR_READ_WRITEB_MASK (0x10000000U)
27973#define LCDIF_CTRL_CLR_READ_WRITEB_SHIFT (28U)
27974#define LCDIF_CTRL_CLR_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_READ_WRITEB_SHIFT)) & LCDIF_CTRL_CLR_READ_WRITEB_MASK)
27975#define LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK (0x20000000U)
27976#define LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT (29U)
27977#define LCDIF_CTRL_CLR_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK)
27978#define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U)
27979#define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U)
27980#define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)
27981#define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U)
27982#define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U)
27983#define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)
27984/*! @} */
27985
27986/*! @name CTRL_TOG - LCDIF General Control Register */
27987/*! @{ */
27988#define LCDIF_CTRL_TOG_RUN_MASK (0x1U)
27989#define LCDIF_CTRL_TOG_RUN_SHIFT (0U)
27990#define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)
27991#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U)
27992#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U)
27993/*! DATA_FORMAT_24_BIT
27994 * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
27995 * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped.
27996 */
27997#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)
27998#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U)
27999#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U)
28000/*! DATA_FORMAT_18_BIT
28001 * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
28002 * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
28003 */
28004#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)
28005#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U)
28006#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U)
28007#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)
28008#define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U)
28009#define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U)
28010#define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)
28011#define LCDIF_CTRL_TOG_MASTER_MASK (0x20U)
28012#define LCDIF_CTRL_TOG_MASTER_SHIFT (5U)
28013#define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)
28014#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
28015#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
28016#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)
28017#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK (0x80U)
28018#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT (7U)
28019#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK)
28020#define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U)
28021#define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U)
28022/*! WORD_LENGTH
28023 * 0b00..Input data is 16 bits per pixel.
28024 * 0b01..Input data is 8 bits wide.
28025 * 0b10..Input data is 18 bits per pixel.
28026 * 0b11..Input data is 24 bits per pixel.
28027 */
28028#define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)
28029#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U)
28030#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U)
28031/*! LCD_DATABUS_WIDTH
28032 * 0b00..16-bit data bus mode.
28033 * 0b01..8-bit data bus mode.
28034 * 0b10..18-bit data bus mode.
28035 * 0b11..24-bit data bus mode.
28036 */
28037#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)
28038#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U)
28039#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U)
28040/*! CSC_DATA_SWIZZLE
28041 * 0b00..No byte swapping.(Little endian)
28042 * 0b00..Little Endian byte ordering (same as NO_SWAP).
28043 * 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
28044 * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
28045 * 0b10..Swap half-words.
28046 * 0b11..Swap bytes within each half-word.
28047 */
28048#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)
28049#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U)
28050#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U)
28051/*! INPUT_DATA_SWIZZLE
28052 * 0b00..No byte swapping.(Little endian)
28053 * 0b00..Little Endian byte ordering (same as NO_SWAP).
28054 * 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
28055 * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
28056 * 0b10..Swap half-words.
28057 * 0b11..Swap bytes within each half-word.
28058 */
28059#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)
28060#define LCDIF_CTRL_TOG_DATA_SELECT_MASK (0x10000U)
28061#define LCDIF_CTRL_TOG_DATA_SELECT_SHIFT (16U)
28062/*! DATA_SELECT
28063 * 0b0..Command Mode. LCD_RS signal is Low.
28064 * 0b1..Data Mode. LCD_RS signal is High.
28065 */
28066#define LCDIF_CTRL_TOG_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SELECT_SHIFT)) & LCDIF_CTRL_TOG_DATA_SELECT_MASK)
28067#define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U)
28068#define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U)
28069#define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)
28070#define LCDIF_CTRL_TOG_VSYNC_MODE_MASK (0x40000U)
28071#define LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT (18U)
28072#define LCDIF_CTRL_TOG_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_TOG_VSYNC_MODE_MASK)
28073#define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U)
28074#define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U)
28075#define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)
28076#define LCDIF_CTRL_TOG_DVI_MODE_MASK (0x100000U)
28077#define LCDIF_CTRL_TOG_DVI_MODE_SHIFT (20U)
28078#define LCDIF_CTRL_TOG_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DVI_MODE_SHIFT)) & LCDIF_CTRL_TOG_DVI_MODE_MASK)
28079#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U)
28080#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U)
28081#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)
28082#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U)
28083#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U)
28084/*! DATA_SHIFT_DIR
28085 * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
28086 * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
28087 */
28088#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)
28089#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U)
28090#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT (27U)
28091#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK)
28092#define LCDIF_CTRL_TOG_READ_WRITEB_MASK (0x10000000U)
28093#define LCDIF_CTRL_TOG_READ_WRITEB_SHIFT (28U)
28094#define LCDIF_CTRL_TOG_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_READ_WRITEB_SHIFT)) & LCDIF_CTRL_TOG_READ_WRITEB_MASK)
28095#define LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK (0x20000000U)
28096#define LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT (29U)
28097#define LCDIF_CTRL_TOG_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK)
28098#define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U)
28099#define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U)
28100#define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)
28101#define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U)
28102#define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U)
28103#define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)
28104/*! @} */
28105
28106/*! @name CTRL1 - LCDIF General Control1 Register */
28107/*! @{ */
28108#define LCDIF_CTRL1_RESET_MASK (0x1U)
28109#define LCDIF_CTRL1_RESET_SHIFT (0U)
28110/*! RESET
28111 * 0b0..LCD_RESET output signal is low.
28112 * 0b1..LCD_RESET output signal is high.
28113 */
28114#define LCDIF_CTRL1_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RESET_SHIFT)) & LCDIF_CTRL1_RESET_MASK)
28115#define LCDIF_CTRL1_MODE86_MASK (0x2U)
28116#define LCDIF_CTRL1_MODE86_SHIFT (1U)
28117/*! MODE86
28118 * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively.
28119 * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively.
28120 */
28121#define LCDIF_CTRL1_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_MODE86_SHIFT)) & LCDIF_CTRL1_MODE86_MASK)
28122#define LCDIF_CTRL1_BUSY_ENABLE_MASK (0x4U)
28123#define LCDIF_CTRL1_BUSY_ENABLE_SHIFT (2U)
28124/*! BUSY_ENABLE
28125 * 0b0..The busy signal from the LCD controller will be ignored.
28126 * 0b1..Enable the use of the busy signal from the LCD controller.
28127 */
28128#define LCDIF_CTRL1_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_BUSY_ENABLE_MASK)
28129#define LCDIF_CTRL1_RSRVD0_MASK (0xF8U)
28130#define LCDIF_CTRL1_RSRVD0_SHIFT (3U)
28131#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)
28132#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U)
28133#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U)
28134/*! VSYNC_EDGE_IRQ
28135 * 0b0..No Interrupt Request Pending.
28136 * 0b1..Interrupt Request Pending.
28137 */
28138#define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
28139#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U)
28140#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U)
28141/*! CUR_FRAME_DONE_IRQ
28142 * 0b0..No Interrupt Request Pending.
28143 * 0b1..Interrupt Request Pending.
28144 */
28145#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)
28146#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U)
28147#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U)
28148/*! UNDERFLOW_IRQ
28149 * 0b0..No Interrupt Request Pending.
28150 * 0b1..Interrupt Request Pending.
28151 */
28152#define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)
28153#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U)
28154#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U)
28155/*! OVERFLOW_IRQ
28156 * 0b0..No Interrupt Request Pending.
28157 * 0b1..Interrupt Request Pending.
28158 */
28159#define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)
28160#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
28161#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
28162#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)
28163#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
28164#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
28165#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)
28166#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U)
28167#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U)
28168#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)
28169#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U)
28170#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U)
28171#define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)
28172#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U)
28173#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U)
28174#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
28175#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
28176#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
28177#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)
28178#define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U)
28179#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U)
28180#define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)
28181#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
28182#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
28183#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)
28184#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U)
28185#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U)
28186#define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)
28187#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
28188#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U)
28189#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)
28190#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U)
28191#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U)
28192/*! BM_ERROR_IRQ
28193 * 0b0..No Interrupt Request Pending.
28194 * 0b1..Interrupt Request Pending.
28195 */
28196#define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)
28197#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U)
28198#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U)
28199#define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)
28200#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK (0x8000000U)
28201#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT (27U)
28202#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK)
28203/*! @} */
28204
28205/*! @name CTRL1_SET - LCDIF General Control1 Register */
28206/*! @{ */
28207#define LCDIF_CTRL1_SET_RESET_MASK (0x1U)
28208#define LCDIF_CTRL1_SET_RESET_SHIFT (0U)
28209/*! RESET
28210 * 0b0..LCD_RESET output signal is low.
28211 * 0b1..LCD_RESET output signal is high.
28212 */
28213#define LCDIF_CTRL1_SET_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RESET_SHIFT)) & LCDIF_CTRL1_SET_RESET_MASK)
28214#define LCDIF_CTRL1_SET_MODE86_MASK (0x2U)
28215#define LCDIF_CTRL1_SET_MODE86_SHIFT (1U)
28216/*! MODE86
28217 * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively.
28218 * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively.
28219 */
28220#define LCDIF_CTRL1_SET_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_MODE86_SHIFT)) & LCDIF_CTRL1_SET_MODE86_MASK)
28221#define LCDIF_CTRL1_SET_BUSY_ENABLE_MASK (0x4U)
28222#define LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT (2U)
28223/*! BUSY_ENABLE
28224 * 0b0..The busy signal from the LCD controller will be ignored.
28225 * 0b1..Enable the use of the busy signal from the LCD controller.
28226 */
28227#define LCDIF_CTRL1_SET_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_SET_BUSY_ENABLE_MASK)
28228#define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U)
28229#define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U)
28230#define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)
28231#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U)
28232#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U)
28233/*! VSYNC_EDGE_IRQ
28234 * 0b0..No Interrupt Request Pending.
28235 * 0b1..Interrupt Request Pending.
28236 */
28237#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)
28238#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U)
28239#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)
28240/*! CUR_FRAME_DONE_IRQ
28241 * 0b0..No Interrupt Request Pending.
28242 * 0b1..Interrupt Request Pending.
28243 */
28244#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)
28245#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U)
28246#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U)
28247/*! UNDERFLOW_IRQ
28248 * 0b0..No Interrupt Request Pending.
28249 * 0b1..Interrupt Request Pending.
28250 */
28251#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)
28252#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U)
28253#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U)
28254/*! OVERFLOW_IRQ
28255 * 0b0..No Interrupt Request Pending.
28256 * 0b1..Interrupt Request Pending.
28257 */
28258#define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)
28259#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
28260#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
28261#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)
28262#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
28263#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
28264#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)
28265#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U)
28266#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U)
28267#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)
28268#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U)
28269#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U)
28270#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)
28271#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)
28272#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)
28273#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)
28274#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
28275#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
28276#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)
28277#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U)
28278#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U)
28279#define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)
28280#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
28281#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
28282#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)
28283#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U)
28284#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U)
28285#define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)
28286#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
28287#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)
28288#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)
28289#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U)
28290#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U)
28291/*! BM_ERROR_IRQ
28292 * 0b0..No Interrupt Request Pending.
28293 * 0b1..Interrupt Request Pending.
28294 */
28295#define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)
28296#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U)
28297#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U)
28298#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)
28299#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK (0x8000000U)
28300#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT (27U)
28301#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK)
28302/*! @} */
28303
28304/*! @name CTRL1_CLR - LCDIF General Control1 Register */
28305/*! @{ */
28306#define LCDIF_CTRL1_CLR_RESET_MASK (0x1U)
28307#define LCDIF_CTRL1_CLR_RESET_SHIFT (0U)
28308/*! RESET
28309 * 0b0..LCD_RESET output signal is low.
28310 * 0b1..LCD_RESET output signal is high.
28311 */
28312#define LCDIF_CTRL1_CLR_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RESET_SHIFT)) & LCDIF_CTRL1_CLR_RESET_MASK)
28313#define LCDIF_CTRL1_CLR_MODE86_MASK (0x2U)
28314#define LCDIF_CTRL1_CLR_MODE86_SHIFT (1U)
28315/*! MODE86
28316 * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively.
28317 * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively.
28318 */
28319#define LCDIF_CTRL1_CLR_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_MODE86_SHIFT)) & LCDIF_CTRL1_CLR_MODE86_MASK)
28320#define LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK (0x4U)
28321#define LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT (2U)
28322/*! BUSY_ENABLE
28323 * 0b0..The busy signal from the LCD controller will be ignored.
28324 * 0b1..Enable the use of the busy signal from the LCD controller.
28325 */
28326#define LCDIF_CTRL1_CLR_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK)
28327#define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U)
28328#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U)
28329#define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
28330#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U)
28331#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U)
28332/*! VSYNC_EDGE_IRQ
28333 * 0b0..No Interrupt Request Pending.
28334 * 0b1..Interrupt Request Pending.
28335 */
28336#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)
28337#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U)
28338#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)
28339/*! CUR_FRAME_DONE_IRQ
28340 * 0b0..No Interrupt Request Pending.
28341 * 0b1..Interrupt Request Pending.
28342 */
28343#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)
28344#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U)
28345#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U)
28346/*! UNDERFLOW_IRQ
28347 * 0b0..No Interrupt Request Pending.
28348 * 0b1..Interrupt Request Pending.
28349 */
28350#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)
28351#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U)
28352#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U)
28353/*! OVERFLOW_IRQ
28354 * 0b0..No Interrupt Request Pending.
28355 * 0b1..Interrupt Request Pending.
28356 */
28357#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)
28358#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
28359#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
28360#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)
28361#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
28362#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
28363#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)
28364#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U)
28365#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U)
28366#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)
28367#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U)
28368#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U)
28369#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)
28370#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)
28371#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)
28372#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)
28373#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
28374#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
28375#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)
28376#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U)
28377#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U)
28378#define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)
28379#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
28380#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
28381#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)
28382#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U)
28383#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U)
28384#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)
28385#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
28386#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)
28387#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)
28388#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U)
28389#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U)
28390/*! BM_ERROR_IRQ
28391 * 0b0..No Interrupt Request Pending.
28392 * 0b1..Interrupt Request Pending.
28393 */
28394#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)
28395#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U)
28396#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U)
28397#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)
28398#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK (0x8000000U)
28399#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT (27U)
28400#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK)
28401/*! @} */
28402
28403/*! @name CTRL1_TOG - LCDIF General Control1 Register */
28404/*! @{ */
28405#define LCDIF_CTRL1_TOG_RESET_MASK (0x1U)
28406#define LCDIF_CTRL1_TOG_RESET_SHIFT (0U)
28407/*! RESET
28408 * 0b0..LCD_RESET output signal is low.
28409 * 0b1..LCD_RESET output signal is high.
28410 */
28411#define LCDIF_CTRL1_TOG_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RESET_SHIFT)) & LCDIF_CTRL1_TOG_RESET_MASK)
28412#define LCDIF_CTRL1_TOG_MODE86_MASK (0x2U)
28413#define LCDIF_CTRL1_TOG_MODE86_SHIFT (1U)
28414/*! MODE86
28415 * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively.
28416 * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively.
28417 */
28418#define LCDIF_CTRL1_TOG_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_MODE86_SHIFT)) & LCDIF_CTRL1_TOG_MODE86_MASK)
28419#define LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK (0x4U)
28420#define LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT (2U)
28421/*! BUSY_ENABLE
28422 * 0b0..The busy signal from the LCD controller will be ignored.
28423 * 0b1..Enable the use of the busy signal from the LCD controller.
28424 */
28425#define LCDIF_CTRL1_TOG_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK)
28426#define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U)
28427#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U)
28428#define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)
28429#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U)
28430#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U)
28431/*! VSYNC_EDGE_IRQ
28432 * 0b0..No Interrupt Request Pending.
28433 * 0b1..Interrupt Request Pending.
28434 */
28435#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)
28436#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U)
28437#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)
28438/*! CUR_FRAME_DONE_IRQ
28439 * 0b0..No Interrupt Request Pending.
28440 * 0b1..Interrupt Request Pending.
28441 */
28442#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)
28443#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U)
28444#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U)
28445/*! UNDERFLOW_IRQ
28446 * 0b0..No Interrupt Request Pending.
28447 * 0b1..Interrupt Request Pending.
28448 */
28449#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)
28450#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U)
28451#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U)
28452/*! OVERFLOW_IRQ
28453 * 0b0..No Interrupt Request Pending.
28454 * 0b1..Interrupt Request Pending.
28455 */
28456#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)
28457#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
28458#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
28459#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)
28460#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
28461#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
28462#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)
28463#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U)
28464#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U)
28465#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)
28466#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U)
28467#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U)
28468#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)
28469#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)
28470#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)
28471#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)
28472#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
28473#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
28474#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)
28475#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U)
28476#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U)
28477#define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)
28478#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
28479#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
28480#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)
28481#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U)
28482#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U)
28483#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)
28484#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
28485#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)
28486#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)
28487#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U)
28488#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U)
28489/*! BM_ERROR_IRQ
28490 * 0b0..No Interrupt Request Pending.
28491 * 0b1..Interrupt Request Pending.
28492 */
28493#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)
28494#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U)
28495#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U)
28496#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)
28497#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK (0x8000000U)
28498#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT (27U)
28499#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK)
28500/*! @} */
28501
28502/*! @name CTRL2 - LCDIF General Control2 Register */
28503/*! @{ */
28504#define LCDIF_CTRL2_RSRVD0_MASK (0x1U)
28505#define LCDIF_CTRL2_RSRVD0_SHIFT (0U)
28506#define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)
28507#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0xEU)
28508#define LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT (1U)
28509#define LCDIF_CTRL2_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK)
28510#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U)
28511#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U)
28512#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
28513#define LCDIF_CTRL2_RSRVD1_MASK (0x80U)
28514#define LCDIF_CTRL2_RSRVD1_SHIFT (7U)
28515#define LCDIF_CTRL2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD1_SHIFT)) & LCDIF_CTRL2_RSRVD1_MASK)
28516#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK (0x100U)
28517#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT (8U)
28518#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK)
28519#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U)
28520#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U)
28521#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK)
28522#define LCDIF_CTRL2_READ_PACK_DIR_MASK (0x400U)
28523#define LCDIF_CTRL2_READ_PACK_DIR_SHIFT (10U)
28524#define LCDIF_CTRL2_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_READ_PACK_DIR_MASK)
28525#define LCDIF_CTRL2_RSRVD2_MASK (0x800U)
28526#define LCDIF_CTRL2_RSRVD2_SHIFT (11U)
28527#define LCDIF_CTRL2_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD2_SHIFT)) & LCDIF_CTRL2_RSRVD2_MASK)
28528#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U)
28529#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U)
28530/*! EVEN_LINE_PATTERN
28531 * 0b000..RGB
28532 * 0b001..RBG
28533 * 0b010..GBR
28534 * 0b011..GRB
28535 * 0b100..BRG
28536 * 0b101..BGR
28537 */
28538#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)
28539#define LCDIF_CTRL2_RSRVD3_MASK (0x8000U)
28540#define LCDIF_CTRL2_RSRVD3_SHIFT (15U)
28541#define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)
28542#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U)
28543#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U)
28544/*! ODD_LINE_PATTERN
28545 * 0b000..RGB
28546 * 0b001..RBG
28547 * 0b010..GBR
28548 * 0b011..GRB
28549 * 0b100..BRG
28550 * 0b101..BGR
28551 */
28552#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)
28553#define LCDIF_CTRL2_RSRVD4_MASK (0x80000U)
28554#define LCDIF_CTRL2_RSRVD4_SHIFT (19U)
28555#define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)
28556#define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U)
28557#define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U)
28558#define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)
28559#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U)
28560#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U)
28561/*! OUTSTANDING_REQS
28562 * 0b000..REQ_1
28563 * 0b001..REQ_2
28564 * 0b010..REQ_4
28565 * 0b011..REQ_8
28566 * 0b100..REQ_16
28567 */
28568#define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)
28569#define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U)
28570#define LCDIF_CTRL2_RSRVD5_SHIFT (24U)
28571#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)
28572/*! @} */
28573
28574/*! @name CTRL2_SET - LCDIF General Control2 Register */
28575/*! @{ */
28576#define LCDIF_CTRL2_SET_RSRVD0_MASK (0x1U)
28577#define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U)
28578#define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)
28579#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK (0xEU)
28580#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT (1U)
28581#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK)
28582#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U)
28583#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U)
28584#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
28585#define LCDIF_CTRL2_SET_RSRVD1_MASK (0x80U)
28586#define LCDIF_CTRL2_SET_RSRVD1_SHIFT (7U)
28587#define LCDIF_CTRL2_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD1_SHIFT)) & LCDIF_CTRL2_SET_RSRVD1_MASK)
28588#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK (0x100U)
28589#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT (8U)
28590#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK)
28591#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U)
28592#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U)
28593#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK)
28594#define LCDIF_CTRL2_SET_READ_PACK_DIR_MASK (0x400U)
28595#define LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT (10U)
28596#define LCDIF_CTRL2_SET_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_SET_READ_PACK_DIR_MASK)
28597#define LCDIF_CTRL2_SET_RSRVD2_MASK (0x800U)
28598#define LCDIF_CTRL2_SET_RSRVD2_SHIFT (11U)
28599#define LCDIF_CTRL2_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD2_SHIFT)) & LCDIF_CTRL2_SET_RSRVD2_MASK)
28600#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U)
28601#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U)
28602/*! EVEN_LINE_PATTERN
28603 * 0b000..RGB
28604 * 0b001..RBG
28605 * 0b010..GBR
28606 * 0b011..GRB
28607 * 0b100..BRG
28608 * 0b101..BGR
28609 */
28610#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)
28611#define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U)
28612#define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U)
28613#define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)
28614#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U)
28615#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U)
28616/*! ODD_LINE_PATTERN
28617 * 0b000..RGB
28618 * 0b001..RBG
28619 * 0b010..GBR
28620 * 0b011..GRB
28621 * 0b100..BRG
28622 * 0b101..BGR
28623 */
28624#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)
28625#define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U)
28626#define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U)
28627#define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)
28628#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U)
28629#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U)
28630#define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)
28631#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U)
28632#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U)
28633/*! OUTSTANDING_REQS
28634 * 0b000..REQ_1
28635 * 0b001..REQ_2
28636 * 0b010..REQ_4
28637 * 0b011..REQ_8
28638 * 0b100..REQ_16
28639 */
28640#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)
28641#define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U)
28642#define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U)
28643#define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)
28644/*! @} */
28645
28646/*! @name CTRL2_CLR - LCDIF General Control2 Register */
28647/*! @{ */
28648#define LCDIF_CTRL2_CLR_RSRVD0_MASK (0x1U)
28649#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U)
28650#define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)
28651#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK (0xEU)
28652#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT (1U)
28653#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK)
28654#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U)
28655#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U)
28656#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
28657#define LCDIF_CTRL2_CLR_RSRVD1_MASK (0x80U)
28658#define LCDIF_CTRL2_CLR_RSRVD1_SHIFT (7U)
28659#define LCDIF_CTRL2_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD1_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD1_MASK)
28660#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK (0x100U)
28661#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT (8U)
28662#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK)
28663#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U)
28664#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U)
28665#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK)
28666#define LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK (0x400U)
28667#define LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT (10U)
28668#define LCDIF_CTRL2_CLR_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK)
28669#define LCDIF_CTRL2_CLR_RSRVD2_MASK (0x800U)
28670#define LCDIF_CTRL2_CLR_RSRVD2_SHIFT (11U)
28671#define LCDIF_CTRL2_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD2_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD2_MASK)
28672#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U)
28673#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U)
28674/*! EVEN_LINE_PATTERN
28675 * 0b000..RGB
28676 * 0b001..RBG
28677 * 0b010..GBR
28678 * 0b011..GRB
28679 * 0b100..BRG
28680 * 0b101..BGR
28681 */
28682#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)
28683#define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U)
28684#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U)
28685#define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)
28686#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U)
28687#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U)
28688/*! ODD_LINE_PATTERN
28689 * 0b000..RGB
28690 * 0b001..RBG
28691 * 0b010..GBR
28692 * 0b011..GRB
28693 * 0b100..BRG
28694 * 0b101..BGR
28695 */
28696#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)
28697#define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U)
28698#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U)
28699#define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)
28700#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U)
28701#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U)
28702#define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)
28703#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U)
28704#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U)
28705/*! OUTSTANDING_REQS
28706 * 0b000..REQ_1
28707 * 0b001..REQ_2
28708 * 0b010..REQ_4
28709 * 0b011..REQ_8
28710 * 0b100..REQ_16
28711 */
28712#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)
28713#define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U)
28714#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U)
28715#define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)
28716/*! @} */
28717
28718/*! @name CTRL2_TOG - LCDIF General Control2 Register */
28719/*! @{ */
28720#define LCDIF_CTRL2_TOG_RSRVD0_MASK (0x1U)
28721#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U)
28722#define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)
28723#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK (0xEU)
28724#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT (1U)
28725#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK)
28726#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U)
28727#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U)
28728#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
28729#define LCDIF_CTRL2_TOG_RSRVD1_MASK (0x80U)
28730#define LCDIF_CTRL2_TOG_RSRVD1_SHIFT (7U)
28731#define LCDIF_CTRL2_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD1_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD1_MASK)
28732#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK (0x100U)
28733#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT (8U)
28734#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK)
28735#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U)
28736#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U)
28737#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK)
28738#define LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK (0x400U)
28739#define LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT (10U)
28740#define LCDIF_CTRL2_TOG_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK)
28741#define LCDIF_CTRL2_TOG_RSRVD2_MASK (0x800U)
28742#define LCDIF_CTRL2_TOG_RSRVD2_SHIFT (11U)
28743#define LCDIF_CTRL2_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD2_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD2_MASK)
28744#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U)
28745#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U)
28746/*! EVEN_LINE_PATTERN
28747 * 0b000..RGB
28748 * 0b001..RBG
28749 * 0b010..GBR
28750 * 0b011..GRB
28751 * 0b100..BRG
28752 * 0b101..BGR
28753 */
28754#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)
28755#define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U)
28756#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U)
28757#define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)
28758#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U)
28759#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U)
28760/*! ODD_LINE_PATTERN
28761 * 0b000..RGB
28762 * 0b001..RBG
28763 * 0b010..GBR
28764 * 0b011..GRB
28765 * 0b100..BRG
28766 * 0b101..BGR
28767 */
28768#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)
28769#define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U)
28770#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U)
28771#define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)
28772#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U)
28773#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U)
28774#define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)
28775#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U)
28776#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U)
28777/*! OUTSTANDING_REQS
28778 * 0b000..REQ_1
28779 * 0b001..REQ_2
28780 * 0b010..REQ_4
28781 * 0b011..REQ_8
28782 * 0b100..REQ_16
28783 */
28784#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)
28785#define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U)
28786#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U)
28787#define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
28788/*! @} */
28789
28790/*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */
28791/*! @{ */
28792#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU)
28793#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U)
28794#define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
28795#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U)
28796#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U)
28797#define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
28798/*! @} */
28799
28800/*! @name CUR_BUF - LCD Interface Current Buffer Address Register */
28801/*! @{ */
28802#define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU)
28803#define LCDIF_CUR_BUF_ADDR_SHIFT (0U)
28804#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)
28805/*! @} */
28806
28807/*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */
28808/*! @{ */
28809#define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU)
28810#define LCDIF_NEXT_BUF_ADDR_SHIFT (0U)
28811#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)
28812/*! @} */
28813
28814/*! @name TIMING - LCD Interface Timing Register */
28815/*! @{ */
28816#define LCDIF_TIMING_DATA_SETUP_MASK (0xFFU)
28817#define LCDIF_TIMING_DATA_SETUP_SHIFT (0U)
28818#define LCDIF_TIMING_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_SETUP_SHIFT)) & LCDIF_TIMING_DATA_SETUP_MASK)
28819#define LCDIF_TIMING_DATA_HOLD_MASK (0xFF00U)
28820#define LCDIF_TIMING_DATA_HOLD_SHIFT (8U)
28821#define LCDIF_TIMING_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_HOLD_SHIFT)) & LCDIF_TIMING_DATA_HOLD_MASK)
28822#define LCDIF_TIMING_CMD_SETUP_MASK (0xFF0000U)
28823#define LCDIF_TIMING_CMD_SETUP_SHIFT (16U)
28824#define LCDIF_TIMING_CMD_SETUP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_SETUP_SHIFT)) & LCDIF_TIMING_CMD_SETUP_MASK)
28825#define LCDIF_TIMING_CMD_HOLD_MASK (0xFF000000U)
28826#define LCDIF_TIMING_CMD_HOLD_SHIFT (24U)
28827#define LCDIF_TIMING_CMD_HOLD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_HOLD_SHIFT)) & LCDIF_TIMING_CMD_HOLD_MASK)
28828/*! @} */
28829
28830/*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
28831/*! @{ */
28832#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
28833#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U)
28834#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
28835#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U)
28836#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U)
28837#define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)
28838#define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U)
28839#define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U)
28840#define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)
28841#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
28842#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
28843#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)
28844#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U)
28845#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U)
28846#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)
28847#define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U)
28848#define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U)
28849#define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)
28850#define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U)
28851#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U)
28852#define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)
28853#define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U)
28854#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U)
28855#define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)
28856#define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U)
28857#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U)
28858#define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)
28859#define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U)
28860#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U)
28861#define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)
28862#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U)
28863#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U)
28864#define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)
28865#define LCDIF_VDCTRL0_VSYNC_OEB_MASK (0x20000000U)
28866#define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT (29U)
28867/*! VSYNC_OEB
28868 * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
28869 * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
28870 */
28871#define LCDIF_VDCTRL0_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK)
28872#define LCDIF_VDCTRL0_RSRVD2_MASK (0xC0000000U)
28873#define LCDIF_VDCTRL0_RSRVD2_SHIFT (30U)
28874#define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)
28875/*! @} */
28876
28877/*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
28878/*! @{ */
28879#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
28880#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)
28881#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)
28882#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U)
28883#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U)
28884#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)
28885#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U)
28886#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U)
28887#define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)
28888#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
28889#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
28890#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)
28891#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)
28892#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)
28893#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)
28894#define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U)
28895#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U)
28896#define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)
28897#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U)
28898#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U)
28899#define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)
28900#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U)
28901#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U)
28902#define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)
28903#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U)
28904#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U)
28905#define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)
28906#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U)
28907#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U)
28908#define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)
28909#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U)
28910#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U)
28911#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)
28912#define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK (0x20000000U)
28913#define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT (29U)
28914/*! VSYNC_OEB
28915 * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
28916 * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
28917 */
28918#define LCDIF_VDCTRL0_SET_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK)
28919#define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xC0000000U)
28920#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (30U)
28921#define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)
28922/*! @} */
28923
28924/*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
28925/*! @{ */
28926#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
28927#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)
28928#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)
28929#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U)
28930#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U)
28931#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)
28932#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U)
28933#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U)
28934#define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)
28935#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
28936#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
28937#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)
28938#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)
28939#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)
28940#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)
28941#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U)
28942#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U)
28943#define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)
28944#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U)
28945#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U)
28946#define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)
28947#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U)
28948#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U)
28949#define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)
28950#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U)
28951#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U)
28952#define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)
28953#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U)
28954#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U)
28955#define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)
28956#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U)
28957#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U)
28958#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)
28959#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK (0x20000000U)
28960#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT (29U)
28961/*! VSYNC_OEB
28962 * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
28963 * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
28964 */
28965#define LCDIF_VDCTRL0_CLR_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK)
28966#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xC0000000U)
28967#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (30U)
28968#define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)
28969/*! @} */
28970
28971/*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
28972/*! @{ */
28973#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
28974#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)
28975#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)
28976#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U)
28977#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U)
28978#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)
28979#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U)
28980#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U)
28981#define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)
28982#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
28983#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
28984#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)
28985#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)
28986#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)
28987#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)
28988#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U)
28989#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U)
28990#define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)
28991#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U)
28992#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U)
28993#define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)
28994#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U)
28995#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U)
28996#define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)
28997#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U)
28998#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U)
28999#define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)
29000#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U)
29001#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U)
29002#define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)
29003#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U)
29004#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U)
29005#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)
29006#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK (0x20000000U)
29007#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT (29U)
29008/*! VSYNC_OEB
29009 * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
29010 * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
29011 */
29012#define LCDIF_VDCTRL0_TOG_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK)
29013#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xC0000000U)
29014#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (30U)
29015#define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)
29016/*! @} */
29017
29018/*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */
29019/*! @{ */
29020#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU)
29021#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U)
29022#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
29023/*! @} */
29024
29025/*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */
29026/*! @{ */
29027#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU)
29028#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U)
29029#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
29030#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U)
29031#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U)
29032#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
29033/*! @} */
29034
29035/*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */
29036/*! @{ */
29037#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU)
29038#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U)
29039#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
29040#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U)
29041#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U)
29042#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
29043#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U)
29044#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U)
29045#define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)
29046#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U)
29047#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U)
29048#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)
29049#define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U)
29050#define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U)
29051#define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
29052/*! @} */
29053
29054/*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */
29055/*! @{ */
29056#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)
29057#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)
29058#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
29059#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U)
29060#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U)
29061#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)
29062#define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U)
29063#define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U)
29064#define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)
29065#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U)
29066#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U)
29067#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
29068/*! @} */
29069
29070/*! @name DVICTRL0 - Digital Video Interface Control0 Register */
29071/*! @{ */
29072#define LCDIF_DVICTRL0_H_BLANKING_CNT_MASK (0xFFFU)
29073#define LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT (0U)
29074#define LCDIF_DVICTRL0_H_BLANKING_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT)) & LCDIF_DVICTRL0_H_BLANKING_CNT_MASK)
29075#define LCDIF_DVICTRL0_RSRVD0_MASK (0xF000U)
29076#define LCDIF_DVICTRL0_RSRVD0_SHIFT (12U)
29077#define LCDIF_DVICTRL0_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD0_SHIFT)) & LCDIF_DVICTRL0_RSRVD0_MASK)
29078#define LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK (0xFFF0000U)
29079#define LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT (16U)
29080#define LCDIF_DVICTRL0_H_ACTIVE_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT)) & LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK)
29081#define LCDIF_DVICTRL0_RSRVD1_MASK (0xF0000000U)
29082#define LCDIF_DVICTRL0_RSRVD1_SHIFT (28U)
29083#define LCDIF_DVICTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD1_SHIFT)) & LCDIF_DVICTRL0_RSRVD1_MASK)
29084/*! @} */
29085
29086/*! @name DVICTRL1 - Digital Video Interface Control1 Register */
29087/*! @{ */
29088#define LCDIF_DVICTRL1_F2_START_LINE_MASK (0x3FFU)
29089#define LCDIF_DVICTRL1_F2_START_LINE_SHIFT (0U)
29090#define LCDIF_DVICTRL1_F2_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F2_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F2_START_LINE_MASK)
29091#define LCDIF_DVICTRL1_F1_END_LINE_MASK (0xFFC00U)
29092#define LCDIF_DVICTRL1_F1_END_LINE_SHIFT (10U)
29093#define LCDIF_DVICTRL1_F1_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_END_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_END_LINE_MASK)
29094#define LCDIF_DVICTRL1_F1_START_LINE_MASK (0x3FF00000U)
29095#define LCDIF_DVICTRL1_F1_START_LINE_SHIFT (20U)
29096#define LCDIF_DVICTRL1_F1_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_START_LINE_MASK)
29097#define LCDIF_DVICTRL1_RSRVD0_MASK (0xC0000000U)
29098#define LCDIF_DVICTRL1_RSRVD0_SHIFT (30U)
29099#define LCDIF_DVICTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_RSRVD0_SHIFT)) & LCDIF_DVICTRL1_RSRVD0_MASK)
29100/*! @} */
29101
29102/*! @name DVICTRL2 - Digital Video Interface Control2 Register */
29103/*! @{ */
29104#define LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK (0x3FFU)
29105#define LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT (0U)
29106#define LCDIF_DVICTRL2_V1_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK)
29107#define LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK (0xFFC00U)
29108#define LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT (10U)
29109#define LCDIF_DVICTRL2_V1_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK)
29110#define LCDIF_DVICTRL2_F2_END_LINE_MASK (0x3FF00000U)
29111#define LCDIF_DVICTRL2_F2_END_LINE_SHIFT (20U)
29112#define LCDIF_DVICTRL2_F2_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_F2_END_LINE_SHIFT)) & LCDIF_DVICTRL2_F2_END_LINE_MASK)
29113#define LCDIF_DVICTRL2_RSRVD0_MASK (0xC0000000U)
29114#define LCDIF_DVICTRL2_RSRVD0_SHIFT (30U)
29115#define LCDIF_DVICTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_RSRVD0_SHIFT)) & LCDIF_DVICTRL2_RSRVD0_MASK)
29116/*! @} */
29117
29118/*! @name DVICTRL3 - Digital Video Interface Control3 Register */
29119/*! @{ */
29120#define LCDIF_DVICTRL3_V_LINES_CNT_MASK (0x3FFU)
29121#define LCDIF_DVICTRL3_V_LINES_CNT_SHIFT (0U)
29122#define LCDIF_DVICTRL3_V_LINES_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V_LINES_CNT_SHIFT)) & LCDIF_DVICTRL3_V_LINES_CNT_MASK)
29123#define LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK (0xFFC00U)
29124#define LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT (10U)
29125#define LCDIF_DVICTRL3_V2_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK)
29126#define LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK (0x3FF00000U)
29127#define LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT (20U)
29128#define LCDIF_DVICTRL3_V2_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK)
29129#define LCDIF_DVICTRL3_RSRVD0_MASK (0xC0000000U)
29130#define LCDIF_DVICTRL3_RSRVD0_SHIFT (30U)
29131#define LCDIF_DVICTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_RSRVD0_SHIFT)) & LCDIF_DVICTRL3_RSRVD0_MASK)
29132/*! @} */
29133
29134/*! @name DVICTRL4 - Digital Video Interface Control4 Register */
29135/*! @{ */
29136#define LCDIF_DVICTRL4_H_FILL_CNT_MASK (0xFFU)
29137#define LCDIF_DVICTRL4_H_FILL_CNT_SHIFT (0U)
29138#define LCDIF_DVICTRL4_H_FILL_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_H_FILL_CNT_SHIFT)) & LCDIF_DVICTRL4_H_FILL_CNT_MASK)
29139#define LCDIF_DVICTRL4_CR_FILL_VALUE_MASK (0xFF00U)
29140#define LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT (8U)
29141#define LCDIF_DVICTRL4_CR_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CR_FILL_VALUE_MASK)
29142#define LCDIF_DVICTRL4_CB_FILL_VALUE_MASK (0xFF0000U)
29143#define LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT (16U)
29144#define LCDIF_DVICTRL4_CB_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CB_FILL_VALUE_MASK)
29145#define LCDIF_DVICTRL4_Y_FILL_VALUE_MASK (0xFF000000U)
29146#define LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT (24U)
29147#define LCDIF_DVICTRL4_Y_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_Y_FILL_VALUE_MASK)
29148/*! @} */
29149
29150/*! @name CSC_COEFF0 - RGB to YCbCr 4:2:2 CSC Coefficient0 Register */
29151/*! @{ */
29152#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK (0x3U)
29153#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT (0U)
29154/*! CSC_SUBSAMPLE_FILTER
29155 * 0b00..No filtering, simply keep every chroma value for samples numbered 2n and discard chroma values associated with all samples numbered 2n+1.
29156 * 0b01..Reserved
29157 * 0b10..Chroma samples numbered 2n and 2n+1 are averaged (weights 1/2, 1/2) and that chroma value replaces the two chroma values at 2n and 2n+1. This chroma now exists horizontally halfway between the two luma samples.
29158 * 0b11..Chroma samples numbered 2n-1, 2n, and 2n+1 are averaged (weights 1/4, 1/2, 1/4) and that chroma value exists at the same site as the luma sample numbered 2n and the chroma samples at 2n+1 are discarded.
29159 */
29160#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT)) & LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK)
29161#define LCDIF_CSC_COEFF0_RSRVD0_MASK (0xFFFCU)
29162#define LCDIF_CSC_COEFF0_RSRVD0_SHIFT (2U)
29163#define LCDIF_CSC_COEFF0_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD0_MASK)
29164#define LCDIF_CSC_COEFF0_C0_MASK (0x3FF0000U)
29165#define LCDIF_CSC_COEFF0_C0_SHIFT (16U)
29166#define LCDIF_CSC_COEFF0_C0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_C0_SHIFT)) & LCDIF_CSC_COEFF0_C0_MASK)
29167#define LCDIF_CSC_COEFF0_RSRVD1_MASK (0xFC000000U)
29168#define LCDIF_CSC_COEFF0_RSRVD1_SHIFT (26U)
29169#define LCDIF_CSC_COEFF0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD1_MASK)
29170/*! @} */
29171
29172/*! @name CSC_COEFF1 - RGB to YCbCr 4:2:2 CSC Coefficient1 Register */
29173/*! @{ */
29174#define LCDIF_CSC_COEFF1_C1_MASK (0x3FFU)
29175#define LCDIF_CSC_COEFF1_C1_SHIFT (0U)
29176#define LCDIF_CSC_COEFF1_C1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C1_SHIFT)) & LCDIF_CSC_COEFF1_C1_MASK)
29177#define LCDIF_CSC_COEFF1_RSRVD0_MASK (0xFC00U)
29178#define LCDIF_CSC_COEFF1_RSRVD0_SHIFT (10U)
29179#define LCDIF_CSC_COEFF1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD0_MASK)
29180#define LCDIF_CSC_COEFF1_C2_MASK (0x3FF0000U)
29181#define LCDIF_CSC_COEFF1_C2_SHIFT (16U)
29182#define LCDIF_CSC_COEFF1_C2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C2_SHIFT)) & LCDIF_CSC_COEFF1_C2_MASK)
29183#define LCDIF_CSC_COEFF1_RSRVD1_MASK (0xFC000000U)
29184#define LCDIF_CSC_COEFF1_RSRVD1_SHIFT (26U)
29185#define LCDIF_CSC_COEFF1_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD1_MASK)
29186/*! @} */
29187
29188/*! @name CSC_COEFF2 - RGB to YCbCr 4:2:2 CSC Coefficent2 Register */
29189/*! @{ */
29190#define LCDIF_CSC_COEFF2_C3_MASK (0x3FFU)
29191#define LCDIF_CSC_COEFF2_C3_SHIFT (0U)
29192#define LCDIF_CSC_COEFF2_C3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C3_SHIFT)) & LCDIF_CSC_COEFF2_C3_MASK)
29193#define LCDIF_CSC_COEFF2_RSRVD0_MASK (0xFC00U)
29194#define LCDIF_CSC_COEFF2_RSRVD0_SHIFT (10U)
29195#define LCDIF_CSC_COEFF2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD0_MASK)
29196#define LCDIF_CSC_COEFF2_C4_MASK (0x3FF0000U)
29197#define LCDIF_CSC_COEFF2_C4_SHIFT (16U)
29198#define LCDIF_CSC_COEFF2_C4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C4_SHIFT)) & LCDIF_CSC_COEFF2_C4_MASK)
29199#define LCDIF_CSC_COEFF2_RSRVD1_MASK (0xFC000000U)
29200#define LCDIF_CSC_COEFF2_RSRVD1_SHIFT (26U)
29201#define LCDIF_CSC_COEFF2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD1_MASK)
29202/*! @} */
29203
29204/*! @name CSC_COEFF3 - RGB to YCbCr 4:2:2 CSC Coefficient3 Register */
29205/*! @{ */
29206#define LCDIF_CSC_COEFF3_C5_MASK (0x3FFU)
29207#define LCDIF_CSC_COEFF3_C5_SHIFT (0U)
29208#define LCDIF_CSC_COEFF3_C5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C5_SHIFT)) & LCDIF_CSC_COEFF3_C5_MASK)
29209#define LCDIF_CSC_COEFF3_RSRVD0_MASK (0xFC00U)
29210#define LCDIF_CSC_COEFF3_RSRVD0_SHIFT (10U)
29211#define LCDIF_CSC_COEFF3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD0_MASK)
29212#define LCDIF_CSC_COEFF3_C6_MASK (0x3FF0000U)
29213#define LCDIF_CSC_COEFF3_C6_SHIFT (16U)
29214#define LCDIF_CSC_COEFF3_C6(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C6_SHIFT)) & LCDIF_CSC_COEFF3_C6_MASK)
29215#define LCDIF_CSC_COEFF3_RSRVD1_MASK (0xFC000000U)
29216#define LCDIF_CSC_COEFF3_RSRVD1_SHIFT (26U)
29217#define LCDIF_CSC_COEFF3_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD1_MASK)
29218/*! @} */
29219
29220/*! @name CSC_COEFF4 - RGB to YCbCr 4:2:2 CSC Coefficient4 Register */
29221/*! @{ */
29222#define LCDIF_CSC_COEFF4_C7_MASK (0x3FFU)
29223#define LCDIF_CSC_COEFF4_C7_SHIFT (0U)
29224#define LCDIF_CSC_COEFF4_C7(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C7_SHIFT)) & LCDIF_CSC_COEFF4_C7_MASK)
29225#define LCDIF_CSC_COEFF4_RSRVD0_MASK (0xFC00U)
29226#define LCDIF_CSC_COEFF4_RSRVD0_SHIFT (10U)
29227#define LCDIF_CSC_COEFF4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD0_MASK)
29228#define LCDIF_CSC_COEFF4_C8_MASK (0x3FF0000U)
29229#define LCDIF_CSC_COEFF4_C8_SHIFT (16U)
29230#define LCDIF_CSC_COEFF4_C8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C8_SHIFT)) & LCDIF_CSC_COEFF4_C8_MASK)
29231#define LCDIF_CSC_COEFF4_RSRVD1_MASK (0xFC000000U)
29232#define LCDIF_CSC_COEFF4_RSRVD1_SHIFT (26U)
29233#define LCDIF_CSC_COEFF4_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD1_MASK)
29234/*! @} */
29235
29236/*! @name CSC_OFFSET - RGB to YCbCr 4:2:2 CSC Offset Register */
29237/*! @{ */
29238#define LCDIF_CSC_OFFSET_Y_OFFSET_MASK (0x1FFU)
29239#define LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT (0U)
29240#define LCDIF_CSC_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_Y_OFFSET_MASK)
29241#define LCDIF_CSC_OFFSET_RSRVD0_MASK (0xFE00U)
29242#define LCDIF_CSC_OFFSET_RSRVD0_SHIFT (9U)
29243#define LCDIF_CSC_OFFSET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD0_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD0_MASK)
29244#define LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK (0x1FF0000U)
29245#define LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT (16U)
29246#define LCDIF_CSC_OFFSET_CBCR_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK)
29247#define LCDIF_CSC_OFFSET_RSRVD1_MASK (0xFE000000U)
29248#define LCDIF_CSC_OFFSET_RSRVD1_SHIFT (25U)
29249#define LCDIF_CSC_OFFSET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD1_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD1_MASK)
29250/*! @} */
29251
29252/*! @name CSC_LIMIT - RGB to YCbCr 4:2:2 CSC Limit Register */
29253/*! @{ */
29254#define LCDIF_CSC_LIMIT_Y_MAX_MASK (0xFFU)
29255#define LCDIF_CSC_LIMIT_Y_MAX_SHIFT (0U)
29256#define LCDIF_CSC_LIMIT_Y_MAX(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MAX_SHIFT)) & LCDIF_CSC_LIMIT_Y_MAX_MASK)
29257#define LCDIF_CSC_LIMIT_Y_MIN_MASK (0xFF00U)
29258#define LCDIF_CSC_LIMIT_Y_MIN_SHIFT (8U)
29259#define LCDIF_CSC_LIMIT_Y_MIN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MIN_SHIFT)) & LCDIF_CSC_LIMIT_Y_MIN_MASK)
29260#define LCDIF_CSC_LIMIT_CBCR_MAX_MASK (0xFF0000U)
29261#define LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT (16U)
29262#define LCDIF_CSC_LIMIT_CBCR_MAX(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MAX_MASK)
29263#define LCDIF_CSC_LIMIT_CBCR_MIN_MASK (0xFF000000U)
29264#define LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT (24U)
29265#define LCDIF_CSC_LIMIT_CBCR_MIN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MIN_MASK)
29266/*! @} */
29267
29268/*! @name DATA - LCD Interface Data Register */
29269/*! @{ */
29270#define LCDIF_DATA_DATA_ZERO_MASK (0xFFU)
29271#define LCDIF_DATA_DATA_ZERO_SHIFT (0U)
29272#define LCDIF_DATA_DATA_ZERO(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ZERO_SHIFT)) & LCDIF_DATA_DATA_ZERO_MASK)
29273#define LCDIF_DATA_DATA_ONE_MASK (0xFF00U)
29274#define LCDIF_DATA_DATA_ONE_SHIFT (8U)
29275#define LCDIF_DATA_DATA_ONE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ONE_SHIFT)) & LCDIF_DATA_DATA_ONE_MASK)
29276#define LCDIF_DATA_DATA_TWO_MASK (0xFF0000U)
29277#define LCDIF_DATA_DATA_TWO_SHIFT (16U)
29278#define LCDIF_DATA_DATA_TWO(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_TWO_SHIFT)) & LCDIF_DATA_DATA_TWO_MASK)
29279#define LCDIF_DATA_DATA_THREE_MASK (0xFF000000U)
29280#define LCDIF_DATA_DATA_THREE_SHIFT (24U)
29281#define LCDIF_DATA_DATA_THREE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_THREE_SHIFT)) & LCDIF_DATA_DATA_THREE_MASK)
29282/*! @} */
29283
29284/*! @name BM_ERROR_STAT - Bus Master Error Status Register */
29285/*! @{ */
29286#define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU)
29287#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U)
29288#define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)
29289/*! @} */
29290
29291/*! @name CRC_STAT - CRC Status Register */
29292/*! @{ */
29293#define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU)
29294#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U)
29295#define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)
29296/*! @} */
29297
29298/*! @name STAT - LCD Interface Status Register */
29299/*! @{ */
29300#define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU)
29301#define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U)
29302#define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)
29303#define LCDIF_STAT_RSRVD0_MASK (0xFFFE00U)
29304#define LCDIF_STAT_RSRVD0_SHIFT (9U)
29305#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)
29306#define LCDIF_STAT_DVI_CURRENT_FIELD_MASK (0x1000000U)
29307#define LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT (24U)
29308#define LCDIF_STAT_DVI_CURRENT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT)) & LCDIF_STAT_DVI_CURRENT_FIELD_MASK)
29309#define LCDIF_STAT_BUSY_MASK (0x2000000U)
29310#define LCDIF_STAT_BUSY_SHIFT (25U)
29311#define LCDIF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_BUSY_SHIFT)) & LCDIF_STAT_BUSY_MASK)
29312#define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U)
29313#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U)
29314#define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)
29315#define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U)
29316#define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U)
29317#define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)
29318#define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U)
29319#define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U)
29320#define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)
29321#define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U)
29322#define LCDIF_STAT_LFIFO_FULL_SHIFT (29U)
29323#define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)
29324#define LCDIF_STAT_PRESENT_MASK (0x80000000U)
29325#define LCDIF_STAT_PRESENT_SHIFT (31U)
29326#define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)
29327/*! @} */
29328
29329/*! @name THRES - LCDIF Threshold Register */
29330/*! @{ */
29331#define LCDIF_THRES_PANIC_MASK (0x1FFU)
29332#define LCDIF_THRES_PANIC_SHIFT (0U)
29333#define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK)
29334#define LCDIF_THRES_RSRVD1_MASK (0xFE00U)
29335#define LCDIF_THRES_RSRVD1_SHIFT (9U)
29336#define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK)
29337#define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U)
29338#define LCDIF_THRES_FASTCLOCK_SHIFT (16U)
29339#define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK)
29340#define LCDIF_THRES_RSRVD2_MASK (0xFE000000U)
29341#define LCDIF_THRES_RSRVD2_SHIFT (25U)
29342#define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK)
29343/*! @} */
29344
29345/*! @name AS_CTRL - LCDIF AS Buffer Control Register */
29346/*! @{ */
29347#define LCDIF_AS_CTRL_AS_ENABLE_MASK (0x1U)
29348#define LCDIF_AS_CTRL_AS_ENABLE_SHIFT (0U)
29349#define LCDIF_AS_CTRL_AS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_AS_ENABLE_SHIFT)) & LCDIF_AS_CTRL_AS_ENABLE_MASK)
29350#define LCDIF_AS_CTRL_ALPHA_CTRL_MASK (0x6U)
29351#define LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT (1U)
29352#define LCDIF_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT)) & LCDIF_AS_CTRL_ALPHA_CTRL_MASK)
29353#define LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U)
29354#define LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U)
29355#define LCDIF_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK)
29356#define LCDIF_AS_CTRL_FORMAT_MASK (0xF0U)
29357#define LCDIF_AS_CTRL_FORMAT_SHIFT (4U)
29358#define LCDIF_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_FORMAT_SHIFT)) & LCDIF_AS_CTRL_FORMAT_MASK)
29359#define LCDIF_AS_CTRL_ALPHA_MASK (0xFF00U)
29360#define LCDIF_AS_CTRL_ALPHA_SHIFT (8U)
29361#define LCDIF_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_SHIFT)) & LCDIF_AS_CTRL_ALPHA_MASK)
29362#define LCDIF_AS_CTRL_ROP_MASK (0xF0000U)
29363#define LCDIF_AS_CTRL_ROP_SHIFT (16U)
29364#define LCDIF_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ROP_SHIFT)) & LCDIF_AS_CTRL_ROP_MASK)
29365#define LCDIF_AS_CTRL_ALPHA_INVERT_MASK (0x100000U)
29366#define LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT (20U)
29367#define LCDIF_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT)) & LCDIF_AS_CTRL_ALPHA_INVERT_MASK)
29368#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK (0x600000U)
29369#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT (21U)
29370#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK)
29371#define LCDIF_AS_CTRL_PS_DISABLE_MASK (0x800000U)
29372#define LCDIF_AS_CTRL_PS_DISABLE_SHIFT (23U)
29373#define LCDIF_AS_CTRL_PS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_PS_DISABLE_SHIFT)) & LCDIF_AS_CTRL_PS_DISABLE_MASK)
29374#define LCDIF_AS_CTRL_RVDS1_MASK (0x7000000U)
29375#define LCDIF_AS_CTRL_RVDS1_SHIFT (24U)
29376#define LCDIF_AS_CTRL_RVDS1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_RVDS1_SHIFT)) & LCDIF_AS_CTRL_RVDS1_MASK)
29377#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK (0x8000000U)
29378#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT (27U)
29379#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK)
29380#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK (0x10000000U)
29381#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT (28U)
29382#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK)
29383#define LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK (0x20000000U)
29384#define LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT (29U)
29385#define LCDIF_AS_CTRL_CSI_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK)
29386#define LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK (0x40000000U)
29387#define LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT (30U)
29388#define LCDIF_AS_CTRL_CSI_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK)
29389#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK (0x80000000U)
29390#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT (31U)
29391#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK)
29392/*! @} */
29393
29394/*! @name AS_BUF - Alpha Surface Buffer Pointer */
29395/*! @{ */
29396#define LCDIF_AS_BUF_ADDR_MASK (0xFFFFFFFFU)
29397#define LCDIF_AS_BUF_ADDR_SHIFT (0U)
29398#define LCDIF_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_BUF_ADDR_SHIFT)) & LCDIF_AS_BUF_ADDR_MASK)
29399/*! @} */
29400
29401/*! @name AS_NEXT_BUF - */
29402/*! @{ */
29403#define LCDIF_AS_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU)
29404#define LCDIF_AS_NEXT_BUF_ADDR_SHIFT (0U)
29405#define LCDIF_AS_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_NEXT_BUF_ADDR_SHIFT)) & LCDIF_AS_NEXT_BUF_ADDR_MASK)
29406/*! @} */
29407
29408/*! @name AS_CLRKEYLOW - LCDIF Overlay Color Key Low */
29409/*! @{ */
29410#define LCDIF_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)
29411#define LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT (0U)
29412#define LCDIF_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYLOW_PIXEL_MASK)
29413#define LCDIF_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U)
29414#define LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT (24U)
29415#define LCDIF_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYLOW_RSVD1_MASK)
29416/*! @} */
29417
29418/*! @name AS_CLRKEYHIGH - LCDIF Overlay Color Key High */
29419/*! @{ */
29420#define LCDIF_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)
29421#define LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT (0U)
29422#define LCDIF_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYHIGH_PIXEL_MASK)
29423#define LCDIF_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U)
29424#define LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT (24U)
29425#define LCDIF_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYHIGH_RSVD1_MASK)
29426/*! @} */
29427
29428/*! @name SYNC_DELAY - LCD working insync mode with CSI for VSYNC delay */
29429/*! @{ */
29430#define LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK (0xFFFFU)
29431#define LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT (0U)
29432#define LCDIF_SYNC_DELAY_H_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK)
29433#define LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK (0xFFFF0000U)
29434#define LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT (16U)
29435#define LCDIF_SYNC_DELAY_V_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK)
29436/*! @} */
29437
29438
29439/*!
29440 * @}
29441 */ /* end of group LCDIF_Register_Masks */
29442
29443
29444/* LCDIF - Peripheral instance base addresses */
29445/** Peripheral LCDIF base address */
29446#define LCDIF_BASE (0x30320000u)
29447/** Peripheral LCDIF base pointer */
29448#define LCDIF ((LCDIF_Type *)LCDIF_BASE)
29449/** Array initializer of LCDIF peripheral base addresses */
29450#define LCDIF_BASE_ADDRS { LCDIF_BASE }
29451/** Array initializer of LCDIF peripheral base pointers */
29452#define LCDIF_BASE_PTRS { LCDIF }
29453
29454/*!
29455 * @}
29456 */ /* end of group LCDIF_Peripheral_Access_Layer */
29457
29458
29459/* ----------------------------------------------------------------------------
29460 -- LMEM Peripheral Access Layer
29461 ---------------------------------------------------------------------------- */
29462
29463/*!
29464 * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer
29465 * @{
29466 */
29467
29468/** LMEM - Register Layout Typedef */
29469typedef struct {
29470 __IO uint32_t PCCCR; /**< Cache control register, offset: 0x0 */
29471 __IO uint32_t PCCLCR; /**< Cache line control register, offset: 0x4 */
29472 __IO uint32_t PCCSAR; /**< Cache search address register, offset: 0x8 */
29473 __IO uint32_t PCCCVR; /**< Cache read/write value register, offset: 0xC */
29474 uint8_t RESERVED_0[2032];
29475 __IO uint32_t PSCCR; /**< Cache control register, offset: 0x800 */
29476 __IO uint32_t PSCLCR; /**< Cache line control register, offset: 0x804 */
29477 __IO uint32_t PSCSAR; /**< Cache search address register, offset: 0x808 */
29478 __IO uint32_t PSCCVR; /**< Cache read/write value register, offset: 0x80C */
29479} LMEM_Type;
29480
29481/* ----------------------------------------------------------------------------
29482 -- LMEM Register Masks
29483 ---------------------------------------------------------------------------- */
29484
29485/*!
29486 * @addtogroup LMEM_Register_Masks LMEM Register Masks
29487 * @{
29488 */
29489
29490/*! @name PCCCR - Cache control register */
29491/*! @{ */
29492#define LMEM_PCCCR_ENCACHE_MASK (0x1U)
29493#define LMEM_PCCCR_ENCACHE_SHIFT (0U)
29494/*! ENCACHE - Cache enable
29495 * 0b0..Cache disabled
29496 * 0b1..Cache enabled
29497 */
29498#define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)
29499#define LMEM_PCCCR_ENWRBUF_MASK (0x2U)
29500#define LMEM_PCCCR_ENWRBUF_SHIFT (1U)
29501/*! ENWRBUF - Enable Write Buffer
29502 * 0b0..Write buffer disabled
29503 * 0b1..Write buffer enabled
29504 */
29505#define LMEM_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)
29506#define LMEM_PCCCR_PCCR2_MASK (0x4U)
29507#define LMEM_PCCCR_PCCR2_SHIFT (2U)
29508#define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK)
29509#define LMEM_PCCCR_PCCR3_MASK (0x8U)
29510#define LMEM_PCCCR_PCCR3_SHIFT (3U)
29511#define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK)
29512#define LMEM_PCCCR_INVW0_MASK (0x1000000U)
29513#define LMEM_PCCCR_INVW0_SHIFT (24U)
29514/*! INVW0 - Invalidate Way 0
29515 * 0b0..No operation
29516 * 0b1..When setting the GO bit, invalidate all lines in way 0.
29517 */
29518#define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)
29519#define LMEM_PCCCR_PUSHW0_MASK (0x2000000U)
29520#define LMEM_PCCCR_PUSHW0_SHIFT (25U)
29521/*! PUSHW0 - Push Way 0
29522 * 0b0..No operation
29523 * 0b1..When setting the GO bit, push all modified lines in way 0
29524 */
29525#define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)
29526#define LMEM_PCCCR_INVW1_MASK (0x4000000U)
29527#define LMEM_PCCCR_INVW1_SHIFT (26U)
29528/*! INVW1 - Invalidate Way 1
29529 * 0b0..No operation
29530 * 0b1..When setting the GO bit, invalidate all lines in way 1
29531 */
29532#define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)
29533#define LMEM_PCCCR_PUSHW1_MASK (0x8000000U)
29534#define LMEM_PCCCR_PUSHW1_SHIFT (27U)
29535/*! PUSHW1 - Push Way 1
29536 * 0b0..No operation
29537 * 0b1..When setting the GO bit, push all modified lines in way 1
29538 */
29539#define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)
29540#define LMEM_PCCCR_GO_MASK (0x80000000U)
29541#define LMEM_PCCCR_GO_SHIFT (31U)
29542/*! GO - Initiate Cache Command
29543 * 0b0..Write: no effect. Read: no cache command active.
29544 * 0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.
29545 */
29546#define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)
29547/*! @} */
29548
29549/*! @name PCCLCR - Cache line control register */
29550/*! @{ */
29551#define LMEM_PCCLCR_LGO_MASK (0x1U)
29552#define LMEM_PCCLCR_LGO_SHIFT (0U)
29553/*! LGO - Initiate Cache Line Command
29554 * 0b0..Write: no effect. Read: no line command active.
29555 * 0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.
29556 */
29557#define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)
29558#define LMEM_PCCLCR_CACHEADDR_MASK (0x1FFCU)
29559#define LMEM_PCCLCR_CACHEADDR_SHIFT (2U)
29560#define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK)
29561#define LMEM_PCCLCR_WSEL_MASK (0x4000U)
29562#define LMEM_PCCLCR_WSEL_SHIFT (14U)
29563/*! WSEL - Way select
29564 * 0b0..Way 0
29565 * 0b1..Way 1
29566 */
29567#define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)
29568#define LMEM_PCCLCR_TDSEL_MASK (0x10000U)
29569#define LMEM_PCCLCR_TDSEL_SHIFT (16U)
29570/*! TDSEL - Tag/Data Select
29571 * 0b0..Data
29572 * 0b1..Tag
29573 */
29574#define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)
29575#define LMEM_PCCLCR_LCIVB_MASK (0x100000U)
29576#define LMEM_PCCLCR_LCIVB_SHIFT (20U)
29577#define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK)
29578#define LMEM_PCCLCR_LCIMB_MASK (0x200000U)
29579#define LMEM_PCCLCR_LCIMB_SHIFT (21U)
29580#define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK)
29581#define LMEM_PCCLCR_LCWAY_MASK (0x400000U)
29582#define LMEM_PCCLCR_LCWAY_SHIFT (22U)
29583#define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK)
29584#define LMEM_PCCLCR_LCMD_MASK (0x3000000U)
29585#define LMEM_PCCLCR_LCMD_SHIFT (24U)
29586/*! LCMD - Line Command
29587 * 0b00..Search and read or write
29588 * 0b01..Invalidate
29589 * 0b10..Push
29590 * 0b11..Clear
29591 */
29592#define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)
29593#define LMEM_PCCLCR_LADSEL_MASK (0x4000000U)
29594#define LMEM_PCCLCR_LADSEL_SHIFT (26U)
29595/*! LADSEL - Line Address Select
29596 * 0b0..Cache address
29597 * 0b1..Physical address
29598 */
29599#define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)
29600#define LMEM_PCCLCR_LACC_MASK (0x8000000U)
29601#define LMEM_PCCLCR_LACC_SHIFT (27U)
29602/*! LACC - Line access type
29603 * 0b0..Read
29604 * 0b1..Write
29605 */
29606#define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)
29607/*! @} */
29608
29609/*! @name PCCSAR - Cache search address register */
29610/*! @{ */
29611#define LMEM_PCCSAR_LGO_MASK (0x1U)
29612#define LMEM_PCCSAR_LGO_SHIFT (0U)
29613/*! LGO - Initiate Cache Line Command
29614 * 0b0..Write: no effect. Read: no line command active.
29615 * 0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
29616 */
29617#define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)
29618#define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU)
29619#define LMEM_PCCSAR_PHYADDR_SHIFT (2U)
29620#define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
29621/*! @} */
29622
29623/*! @name PCCCVR - Cache read/write value register */
29624/*! @{ */
29625#define LMEM_PCCCVR_DATA_MASK (0xFFFFFFFFU)
29626#define LMEM_PCCCVR_DATA_SHIFT (0U)
29627#define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK)
29628/*! @} */
29629
29630/*! @name PSCCR - Cache control register */
29631/*! @{ */
29632#define LMEM_PSCCR_ENCACHE_MASK (0x1U)
29633#define LMEM_PSCCR_ENCACHE_SHIFT (0U)
29634/*! ENCACHE - Cache enable
29635 * 0b0..Cache disabled
29636 * 0b1..Cache enabled
29637 */
29638#define LMEM_PSCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENCACHE_SHIFT)) & LMEM_PSCCR_ENCACHE_MASK)
29639#define LMEM_PSCCR_ENWRBUF_MASK (0x2U)
29640#define LMEM_PSCCR_ENWRBUF_SHIFT (1U)
29641/*! ENWRBUF - Enable Write Buffer
29642 * 0b0..Write buffer disabled
29643 * 0b1..Write buffer enabled
29644 */
29645#define LMEM_PSCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENWRBUF_SHIFT)) & LMEM_PSCCR_ENWRBUF_MASK)
29646#define LMEM_PSCCR_INVW0_MASK (0x1000000U)
29647#define LMEM_PSCCR_INVW0_SHIFT (24U)
29648/*! INVW0 - Invalidate Way 0
29649 * 0b0..No operation
29650 * 0b1..When setting the GO bit, invalidate all lines in way 0.
29651 */
29652#define LMEM_PSCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW0_SHIFT)) & LMEM_PSCCR_INVW0_MASK)
29653#define LMEM_PSCCR_PUSHW0_MASK (0x2000000U)
29654#define LMEM_PSCCR_PUSHW0_SHIFT (25U)
29655/*! PUSHW0 - Push Way 0
29656 * 0b0..No operation
29657 * 0b1..When setting the GO bit, push all modified lines in way 0
29658 */
29659#define LMEM_PSCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW0_SHIFT)) & LMEM_PSCCR_PUSHW0_MASK)
29660#define LMEM_PSCCR_INVW1_MASK (0x4000000U)
29661#define LMEM_PSCCR_INVW1_SHIFT (26U)
29662/*! INVW1 - Invalidate Way 1
29663 * 0b0..No operation
29664 * 0b1..When setting the GO bit, invalidate all lines in way 1
29665 */
29666#define LMEM_PSCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW1_SHIFT)) & LMEM_PSCCR_INVW1_MASK)
29667#define LMEM_PSCCR_PUSHW1_MASK (0x8000000U)
29668#define LMEM_PSCCR_PUSHW1_SHIFT (27U)
29669/*! PUSHW1 - Push Way 1
29670 * 0b0..No operation
29671 * 0b1..When setting the GO bit, push all modified lines in way 1
29672 */
29673#define LMEM_PSCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW1_SHIFT)) & LMEM_PSCCR_PUSHW1_MASK)
29674#define LMEM_PSCCR_GO_MASK (0x80000000U)
29675#define LMEM_PSCCR_GO_SHIFT (31U)
29676/*! GO - Initiate Cache Command
29677 * 0b0..Write: no effect. Read: no cache command active.
29678 * 0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.
29679 */
29680#define LMEM_PSCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_GO_SHIFT)) & LMEM_PSCCR_GO_MASK)
29681/*! @} */
29682
29683/*! @name PSCLCR - Cache line control register */
29684/*! @{ */
29685#define LMEM_PSCLCR_LGO_MASK (0x1U)
29686#define LMEM_PSCLCR_LGO_SHIFT (0U)
29687/*! LGO - Initiate Cache Line Command
29688 * 0b0..Write: no effect. Read: no line command active.
29689 * 0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.
29690 */
29691#define LMEM_PSCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LGO_SHIFT)) & LMEM_PSCLCR_LGO_MASK)
29692#define LMEM_PSCLCR_CACHEADDR_MASK (0x1FFCU)
29693#define LMEM_PSCLCR_CACHEADDR_SHIFT (2U)
29694#define LMEM_PSCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_CACHEADDR_SHIFT)) & LMEM_PSCLCR_CACHEADDR_MASK)
29695#define LMEM_PSCLCR_WSEL_MASK (0x4000U)
29696#define LMEM_PSCLCR_WSEL_SHIFT (14U)
29697/*! WSEL - Way select
29698 * 0b0..Way 0
29699 * 0b1..Way 1
29700 */
29701#define LMEM_PSCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_WSEL_SHIFT)) & LMEM_PSCLCR_WSEL_MASK)
29702#define LMEM_PSCLCR_TDSEL_MASK (0x10000U)
29703#define LMEM_PSCLCR_TDSEL_SHIFT (16U)
29704/*! TDSEL - Tag/Data Select
29705 * 0b0..Data
29706 * 0b1..Tag
29707 */
29708#define LMEM_PSCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_TDSEL_SHIFT)) & LMEM_PSCLCR_TDSEL_MASK)
29709#define LMEM_PSCLCR_LCIVB_MASK (0x100000U)
29710#define LMEM_PSCLCR_LCIVB_SHIFT (20U)
29711#define LMEM_PSCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIVB_SHIFT)) & LMEM_PSCLCR_LCIVB_MASK)
29712#define LMEM_PSCLCR_LCIMB_MASK (0x200000U)
29713#define LMEM_PSCLCR_LCIMB_SHIFT (21U)
29714#define LMEM_PSCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIMB_SHIFT)) & LMEM_PSCLCR_LCIMB_MASK)
29715#define LMEM_PSCLCR_LCWAY_MASK (0x400000U)
29716#define LMEM_PSCLCR_LCWAY_SHIFT (22U)
29717#define LMEM_PSCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCWAY_SHIFT)) & LMEM_PSCLCR_LCWAY_MASK)
29718#define LMEM_PSCLCR_LCMD_MASK (0x3000000U)
29719#define LMEM_PSCLCR_LCMD_SHIFT (24U)
29720/*! LCMD - Line Command
29721 * 0b00..Search and read or write
29722 * 0b01..Invalidate
29723 * 0b10..Push
29724 * 0b11..Clear
29725 */
29726#define LMEM_PSCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCMD_SHIFT)) & LMEM_PSCLCR_LCMD_MASK)
29727#define LMEM_PSCLCR_LADSEL_MASK (0x4000000U)
29728#define LMEM_PSCLCR_LADSEL_SHIFT (26U)
29729/*! LADSEL - Line Address Select
29730 * 0b0..Cache address
29731 * 0b1..Physical address
29732 */
29733#define LMEM_PSCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LADSEL_SHIFT)) & LMEM_PSCLCR_LADSEL_MASK)
29734#define LMEM_PSCLCR_LACC_MASK (0x8000000U)
29735#define LMEM_PSCLCR_LACC_SHIFT (27U)
29736/*! LACC - Line access type
29737 * 0b0..Read
29738 * 0b1..Write
29739 */
29740#define LMEM_PSCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LACC_SHIFT)) & LMEM_PSCLCR_LACC_MASK)
29741/*! @} */
29742
29743/*! @name PSCSAR - Cache search address register */
29744/*! @{ */
29745#define LMEM_PSCSAR_LGO_MASK (0x1U)
29746#define LMEM_PSCSAR_LGO_SHIFT (0U)
29747/*! LGO - Initiate Cache Line Command
29748 * 0b0..Write: no effect. Read: no line command active.
29749 * 0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
29750 */
29751#define LMEM_PSCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_LGO_SHIFT)) & LMEM_PSCSAR_LGO_MASK)
29752#define LMEM_PSCSAR_PHYADDR_MASK (0xFFFFFFFCU)
29753#define LMEM_PSCSAR_PHYADDR_SHIFT (2U)
29754#define LMEM_PSCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_PHYADDR_SHIFT)) & LMEM_PSCSAR_PHYADDR_MASK)
29755/*! @} */
29756
29757/*! @name PSCCVR - Cache read/write value register */
29758/*! @{ */
29759#define LMEM_PSCCVR_DATA_MASK (0xFFFFFFFFU)
29760#define LMEM_PSCCVR_DATA_SHIFT (0U)
29761#define LMEM_PSCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCVR_DATA_SHIFT)) & LMEM_PSCCVR_DATA_MASK)
29762/*! @} */
29763
29764
29765/*!
29766 * @}
29767 */ /* end of group LMEM_Register_Masks */
29768
29769
29770/* LMEM - Peripheral instance base addresses */
29771/** Peripheral LMEM base address */
29772#define LMEM_BASE (0xE0082000u)
29773/** Peripheral LMEM base pointer */
29774#define LMEM ((LMEM_Type *)LMEM_BASE)
29775/** Array initializer of LMEM peripheral base addresses */
29776#define LMEM_BASE_ADDRS { LMEM_BASE }
29777/** Array initializer of LMEM peripheral base pointers */
29778#define LMEM_BASE_PTRS { LMEM }
29779
29780/*!
29781 * @}
29782 */ /* end of group LMEM_Peripheral_Access_Layer */
29783
29784
29785/* ----------------------------------------------------------------------------
29786 -- LUT_LD Peripheral Access Layer
29787 ---------------------------------------------------------------------------- */
29788
29789/*!
29790 * @addtogroup LUT_LD_Peripheral_Access_Layer LUT_LD Peripheral Access Layer
29791 * @{
29792 */
29793
29794/** LUT_LD - Register Layout Typedef */
29795typedef struct {
29796 struct { /* offset: 0x0 */
29797 __IO uint32_t RW; /**< Control/Status register for LUT Loader., offset: 0x0 */
29798 __IO uint32_t SET; /**< Control/Status register for LUT Loader., offset: 0x4 */
29799 __IO uint32_t CLR; /**< Control/Status register for LUT Loader., offset: 0x8 */
29800 __IO uint32_t TOG; /**< Control/Status register for LUT Loader., offset: 0xC */
29801 } CTRL_STATUS;
29802 __IO uint32_t BASE_ADDR; /**< Address for data fetch., offset: 0x10 */
29803} LUT_LD_Type;
29804
29805/* ----------------------------------------------------------------------------
29806 -- LUT_LD Register Masks
29807 ---------------------------------------------------------------------------- */
29808
29809/*!
29810 * @addtogroup LUT_LD_Register_Masks LUT_LD Register Masks
29811 * @{
29812 */
29813
29814/*! @name CTRL_STATUS - Control/Status register for LUT Loader. */
29815/*! @{ */
29816#define LUT_LD_CTRL_STATUS_ENABLE_MASK (0x1U)
29817#define LUT_LD_CTRL_STATUS_ENABLE_SHIFT (0U)
29818#define LUT_LD_CTRL_STATUS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LUT_LD_CTRL_STATUS_ENABLE_SHIFT)) & LUT_LD_CTRL_STATUS_ENABLE_MASK)
29819#define LUT_LD_CTRL_STATUS_BYTES_PER_REQ_MASK (0x2U)
29820#define LUT_LD_CTRL_STATUS_BYTES_PER_REQ_SHIFT (1U)
29821#define LUT_LD_CTRL_STATUS_BYTES_PER_REQ(x) (((uint32_t)(((uint32_t)(x)) << LUT_LD_CTRL_STATUS_BYTES_PER_REQ_SHIFT)) & LUT_LD_CTRL_STATUS_BYTES_PER_REQ_MASK)
29822#define LUT_LD_CTRL_STATUS_RD_ERR_EN_MASK (0x100U)
29823#define LUT_LD_CTRL_STATUS_RD_ERR_EN_SHIFT (8U)
29824#define LUT_LD_CTRL_STATUS_RD_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << LUT_LD_CTRL_STATUS_RD_ERR_EN_SHIFT)) & LUT_LD_CTRL_STATUS_RD_ERR_EN_MASK)
29825#define LUT_LD_CTRL_STATUS_RD_ERR_MASK (0x10000U)
29826#define LUT_LD_CTRL_STATUS_RD_ERR_SHIFT (16U)
29827#define LUT_LD_CTRL_STATUS_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << LUT_LD_CTRL_STATUS_RD_ERR_SHIFT)) & LUT_LD_CTRL_STATUS_RD_ERR_MASK)
29828/*! @} */
29829
29830/*! @name BASE_ADDR - Address for data fetch. */
29831/*! @{ */
29832#define LUT_LD_BASE_ADDR_BASE_ADDR_MASK (0xFFFFFFFFU)
29833#define LUT_LD_BASE_ADDR_BASE_ADDR_SHIFT (0U)
29834#define LUT_LD_BASE_ADDR_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LUT_LD_BASE_ADDR_BASE_ADDR_SHIFT)) & LUT_LD_BASE_ADDR_BASE_ADDR_MASK)
29835/*! @} */
29836
29837
29838/*!
29839 * @}
29840 */ /* end of group LUT_LD_Register_Masks */
29841
29842
29843/* LUT_LD - Peripheral instance base addresses */
29844/** Peripheral DCSS__LUT_LD base address */
29845#define DCSS__LUT_LD_BASE (0x32E24000u)
29846/** Peripheral DCSS__LUT_LD base pointer */
29847#define DCSS__LUT_LD ((LUT_LD_Type *)DCSS__LUT_LD_BASE)
29848/** Array initializer of LUT_LD peripheral base addresses */
29849#define LUT_LD_BASE_ADDRS { DCSS__LUT_LD_BASE }
29850/** Array initializer of LUT_LD peripheral base pointers */
29851#define LUT_LD_BASE_PTRS { DCSS__LUT_LD }
29852
29853/*!
29854 * @}
29855 */ /* end of group LUT_LD_Peripheral_Access_Layer */
29856
29857
29858/* ----------------------------------------------------------------------------
29859 -- MCM Peripheral Access Layer
29860 ---------------------------------------------------------------------------- */
29861
29862/*!
29863 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
29864 * @{
29865 */
29866
29867/** MCM - Register Layout Typedef */
29868typedef struct {
29869 uint8_t RESERVED_0[8];
29870 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
29871 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
29872 uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */
29873 uint8_t RESERVED_1[16];
29874 __I uint32_t FADR; /**< Fault address register, offset: 0x20 */
29875 __I uint32_t FATR; /**< Fault attributes register, offset: 0x24 */
29876 __I uint32_t FDR; /**< Fault data register, offset: 0x28 */
29877} MCM_Type;
29878
29879/* ----------------------------------------------------------------------------
29880 -- MCM Register Masks
29881 ---------------------------------------------------------------------------- */
29882
29883/*!
29884 * @addtogroup MCM_Register_Masks MCM Register Masks
29885 * @{
29886 */
29887
29888/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
29889/*! @{ */
29890#define MCM_PLASC_ASC_MASK (0xFFU)
29891#define MCM_PLASC_ASC_SHIFT (0U)
29892/*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
29893 * 0b00000000..A bus slave connection to AXBS input port n is absent
29894 * 0b00000001..A bus slave connection to AXBS input port n is present
29895 */
29896#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
29897/*! @} */
29898
29899/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
29900/*! @{ */
29901#define MCM_PLAMC_AMC_MASK (0xFFU)
29902#define MCM_PLAMC_AMC_SHIFT (0U)
29903/*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
29904 * 0b00000000..A bus master connection to AXBS input port n is absent
29905 * 0b00000001..A bus master connection to AXBS input port n is present
29906 */
29907#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
29908/*! @} */
29909
29910/*! @name FADR - Fault address register */
29911/*! @{ */
29912#define MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU)
29913#define MCM_FADR_ADDRESS_SHIFT (0U)
29914#define MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK)
29915/*! @} */
29916
29917/*! @name FATR - Fault attributes register */
29918/*! @{ */
29919#define MCM_FATR_BEDA_MASK (0x1U)
29920#define MCM_FATR_BEDA_SHIFT (0U)
29921/*! BEDA - Bus error access type
29922 * 0b0..Instruction
29923 * 0b1..Data
29924 */
29925#define MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)
29926#define MCM_FATR_BEMD_MASK (0x2U)
29927#define MCM_FATR_BEMD_SHIFT (1U)
29928/*! BEMD - Bus error privilege level
29929 * 0b0..User mode
29930 * 0b1..Supervisor/privileged mode
29931 */
29932#define MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)
29933#define MCM_FATR_BESZ_MASK (0x30U)
29934#define MCM_FATR_BESZ_SHIFT (4U)
29935/*! BESZ - Bus error size
29936 * 0b00..8-bit access
29937 * 0b01..16-bit access
29938 * 0b10..32-bit access
29939 * 0b11..Reserved
29940 */
29941#define MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)
29942#define MCM_FATR_BEWT_MASK (0x80U)
29943#define MCM_FATR_BEWT_SHIFT (7U)
29944/*! BEWT - Bus error write
29945 * 0b0..Read access
29946 * 0b1..Write access
29947 */
29948#define MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)
29949#define MCM_FATR_BEMN_MASK (0xF00U)
29950#define MCM_FATR_BEMN_SHIFT (8U)
29951#define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK)
29952#define MCM_FATR_BEOVR_MASK (0x80000000U)
29953#define MCM_FATR_BEOVR_SHIFT (31U)
29954/*! BEOVR - Bus error overrun
29955 * 0b0..No bus error overrun
29956 * 0b1..Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error.
29957 */
29958#define MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)
29959/*! @} */
29960
29961/*! @name FDR - Fault data register */
29962/*! @{ */
29963#define MCM_FDR_DATA_MASK (0xFFFFFFFFU)
29964#define MCM_FDR_DATA_SHIFT (0U)
29965#define MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK)
29966/*! @} */
29967
29968
29969/*!
29970 * @}
29971 */ /* end of group MCM_Register_Masks */
29972
29973
29974/* MCM - Peripheral instance base addresses */
29975/** Peripheral MCM base address */
29976#define MCM_BASE (0xE0080000u)
29977/** Peripheral MCM base pointer */
29978#define MCM ((MCM_Type *)MCM_BASE)
29979/** Array initializer of MCM peripheral base addresses */
29980#define MCM_BASE_ADDRS { MCM_BASE }
29981/** Array initializer of MCM peripheral base pointers */
29982#define MCM_BASE_PTRS { MCM }
29983
29984/*!
29985 * @}
29986 */ /* end of group MCM_Peripheral_Access_Layer */
29987
29988
29989/* ----------------------------------------------------------------------------
29990 -- MED_DC_SCALER Peripheral Access Layer
29991 ---------------------------------------------------------------------------- */
29992
29993/*!
29994 * @addtogroup MED_DC_SCALER_Peripheral_Access_Layer MED_DC_SCALER Peripheral Access Layer
29995 * @{
29996 */
29997
29998/** MED_DC_SCALER - Register Layout Typedef */
29999typedef struct {
30000 __IO uint32_t SCALE_CTRL; /**< Scale Control Register, offset: 0x0 */
30001 __IO uint32_t SCALE_OFIFO_CTRL; /**< Scale Output FIFO Control Register, offset: 0x4 */
30002 __IO uint32_t SCALE_SRC_DATA_CTRL; /**< Scale Source Data Control Register, offset: 0x8 */
30003 __IO uint32_t SCALE_BIT_DEPTH; /**< Scale Bit Depth Control Register, offset: 0xC */
30004 __IO uint32_t SCALE_SRC_FORMAT; /**< Scale Source Format Control Register, offset: 0x10 */
30005 __IO uint32_t SCALE_DST_FORMAT; /**< Scale Destination Format Control Register, offset: 0x14 */
30006 __IO uint32_t SCALE_SRC_LUMA_RES; /**< Scale Source Luma Resolution Register, offset: 0x18 */
30007 __IO uint32_t SCALE_SRC_CHROMA_RES; /**< Scale Source Chroma Resolution Register, offset: 0x1C */
30008 __IO uint32_t SCALE_DST_LUMA_RES; /**< Scale Destination Luma Resolution Register, offset: 0x20 */
30009 __IO uint32_t SCALE_DST_CHROMA_RES; /**< Scale Destination Chroma Resolution Register, offset: 0x24 */
30010 uint8_t RESERVED_0[32];
30011 __IO uint32_t SCALE_V_LUMA_START; /**< Scale Vertical Luma Start Register, offset: 0x48 */
30012 __IO uint32_t SCALE_V_LUMA_INC; /**< Scale Vertical Luma Increment Register, offset: 0x4C */
30013 __IO uint32_t SCALE_H_LUMA_START; /**< Scale Horizontal Luma Start Register, offset: 0x50 */
30014 __IO uint32_t SCALE_H_LUMA_INC; /**< Scale Horizontal Luma Increment Register, offset: 0x54 */
30015 __IO uint32_t SCALE_V_CHROMA_START; /**< Scale Vertical Chroma Start Register, offset: 0x58 */
30016 __IO uint32_t SCALE_V_CHROMA_INC; /**< Scale Vertical Chroma Increment Register, offset: 0x5C */
30017 __IO uint32_t SCALE_H_CHROMA_START; /**< Scale Horizontal Chroma Start Register, offset: 0x60 */
30018 __IO uint32_t SCALE_H_CHROMA_INC; /**< Scale Horizontal Chroma Increment Register, offset: 0x64 */
30019 uint8_t RESERVED_1[24];
30020 __IO uint32_t SCALE_COEF_ARRAY; /**< Scale Coefficient Memory Array, offset: 0x80 */
30021} MED_DC_SCALER_Type;
30022
30023/* ----------------------------------------------------------------------------
30024 -- MED_DC_SCALER Register Masks
30025 ---------------------------------------------------------------------------- */
30026
30027/*!
30028 * @addtogroup MED_DC_SCALER_Register_Masks MED_DC_SCALER Register Masks
30029 * @{
30030 */
30031
30032/*! @name SCALE_CTRL - Scale Control Register */
30033/*! @{ */
30034#define MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALER_MASK (0x1U)
30035#define MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALER_SHIFT (0U)
30036#define MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALER(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALER_SHIFT)) & MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALER_MASK)
30037#define MED_DC_SCALER_SCALE_CTRL_ENABLE_REPEAT_MASK (0x10U)
30038#define MED_DC_SCALER_SCALE_CTRL_ENABLE_REPEAT_SHIFT (4U)
30039#define MED_DC_SCALER_SCALE_CTRL_ENABLE_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_CTRL_ENABLE_REPEAT_SHIFT)) & MED_DC_SCALER_SCALE_CTRL_ENABLE_REPEAT_MASK)
30040#define MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALE2MEM_MASK (0x100U)
30041#define MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALE2MEM_SHIFT (8U)
30042#define MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALE2MEM(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALE2MEM_SHIFT)) & MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALE2MEM_MASK)
30043#define MED_DC_SCALER_SCALE_CTRL_ENABLE_MEM2OFIFO_MASK (0x1000U)
30044#define MED_DC_SCALER_SCALE_CTRL_ENABLE_MEM2OFIFO_SHIFT (12U)
30045#define MED_DC_SCALER_SCALE_CTRL_ENABLE_MEM2OFIFO(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_CTRL_ENABLE_MEM2OFIFO_SHIFT)) & MED_DC_SCALER_SCALE_CTRL_ENABLE_MEM2OFIFO_MASK)
30046/*! @} */
30047
30048/*! @name SCALE_OFIFO_CTRL - Scale Output FIFO Control Register */
30049/*! @{ */
30050#define MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_LOW_THRESH_MASK (0x3FFU)
30051#define MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_LOW_THRESH_SHIFT (0U)
30052#define MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_LOW_THRESH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_LOW_THRESH_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_LOW_THRESH_MASK)
30053#define MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_HIGH_THRESH_MASK (0x3FF0000U)
30054#define MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_HIGH_THRESH_SHIFT (16U)
30055#define MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_HIGH_THRESH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_HIGH_THRESH_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_HIGH_THRESH_MASK)
30056#define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_UNDERRUN_DETECT_MASK (0x4000000U)
30057#define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_UNDERRUN_DETECT_SHIFT (26U)
30058#define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_UNDERRUN_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_UNDERRUN_DETECT_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_UNDERRUN_DETECT_MASK)
30059#define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_LOW_THRESH_DETECT_MASK (0x8000000U)
30060#define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_LOW_THRESH_DETECT_SHIFT (27U)
30061#define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_LOW_THRESH_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_LOW_THRESH_DETECT_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_LOW_THRESH_DETECT_MASK)
30062#define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_HIGH_THRESH_DETECT_MASK (0x10000000U)
30063#define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_HIGH_THRESH_DETECT_SHIFT (28U)
30064#define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_HIGH_THRESH_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_HIGH_THRESH_DETECT_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_HIGH_THRESH_DETECT_MASK)
30065#define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_UNDERRUN_DETECT_MASK (0x20000000U)
30066#define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_UNDERRUN_DETECT_SHIFT (29U)
30067#define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_UNDERRUN_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_UNDERRUN_DETECT_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_UNDERRUN_DETECT_MASK)
30068#define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_LOW_THRESH_DETECT_MASK (0x40000000U)
30069#define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_LOW_THRESH_DETECT_SHIFT (30U)
30070#define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_LOW_THRESH_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_LOW_THRESH_DETECT_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_LOW_THRESH_DETECT_MASK)
30071#define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_HIGH_THRESH_DETECT_MASK (0x80000000U)
30072#define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_HIGH_THRESH_DETECT_SHIFT (31U)
30073#define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_HIGH_THRESH_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_HIGH_THRESH_DETECT_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_HIGH_THRESH_DETECT_MASK)
30074/*! @} */
30075
30076/*! @name SCALE_SRC_DATA_CTRL - Scale Source Data Control Register */
30077/*! @{ */
30078#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_SRC_SELECT_MASK (0x1U)
30079#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_SRC_SELECT_SHIFT (0U)
30080#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_SRC_SELECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_DATA_CTRL_SRC_SELECT_SHIFT)) & MED_DC_SCALER_SCALE_SRC_DATA_CTRL_SRC_SELECT_MASK)
30081#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_RTRAM_LINES_PER_BANK_MASK (0x2U)
30082#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_RTRAM_LINES_PER_BANK_SHIFT (1U)
30083#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_RTRAM_LINES_PER_BANK(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_DATA_CTRL_RTRAM_LINES_PER_BANK_SHIFT)) & MED_DC_SCALER_SCALE_SRC_DATA_CTRL_RTRAM_LINES_PER_BANK_MASK)
30084#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_Y_UV_BYTE_SWAP_MASK (0x10U)
30085#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_Y_UV_BYTE_SWAP_SHIFT (4U)
30086#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_Y_UV_BYTE_SWAP(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_DATA_CTRL_Y_UV_BYTE_SWAP_SHIFT)) & MED_DC_SCALER_SCALE_SRC_DATA_CTRL_Y_UV_BYTE_SWAP_MASK)
30087#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_A2R10G10B10_FORMAT_MASK (0xF00U)
30088#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_A2R10G10B10_FORMAT_SHIFT (8U)
30089#define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_A2R10G10B10_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_DATA_CTRL_A2R10G10B10_FORMAT_SHIFT)) & MED_DC_SCALER_SCALE_SRC_DATA_CTRL_A2R10G10B10_FORMAT_MASK)
30090/*! @} */
30091
30092/*! @name SCALE_BIT_DEPTH - Scale Bit Depth Control Register */
30093/*! @{ */
30094#define MED_DC_SCALER_SCALE_BIT_DEPTH_LUMA_BIT_DEPTH_MASK (0x3U)
30095#define MED_DC_SCALER_SCALE_BIT_DEPTH_LUMA_BIT_DEPTH_SHIFT (0U)
30096#define MED_DC_SCALER_SCALE_BIT_DEPTH_LUMA_BIT_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_BIT_DEPTH_LUMA_BIT_DEPTH_SHIFT)) & MED_DC_SCALER_SCALE_BIT_DEPTH_LUMA_BIT_DEPTH_MASK)
30097#define MED_DC_SCALER_SCALE_BIT_DEPTH_CHROMA_BIT_DEPTH_MASK (0x30U)
30098#define MED_DC_SCALER_SCALE_BIT_DEPTH_CHROMA_BIT_DEPTH_SHIFT (4U)
30099#define MED_DC_SCALER_SCALE_BIT_DEPTH_CHROMA_BIT_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_BIT_DEPTH_CHROMA_BIT_DEPTH_SHIFT)) & MED_DC_SCALER_SCALE_BIT_DEPTH_CHROMA_BIT_DEPTH_MASK)
30100/*! @} */
30101
30102/*! @name SCALE_SRC_FORMAT - Scale Source Format Control Register */
30103/*! @{ */
30104#define MED_DC_SCALER_SCALE_SRC_FORMAT_SRC_FORMAT_MASK (0x3U)
30105#define MED_DC_SCALER_SCALE_SRC_FORMAT_SRC_FORMAT_SHIFT (0U)
30106#define MED_DC_SCALER_SCALE_SRC_FORMAT_SRC_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_FORMAT_SRC_FORMAT_SHIFT)) & MED_DC_SCALER_SCALE_SRC_FORMAT_SRC_FORMAT_MASK)
30107/*! @} */
30108
30109/*! @name SCALE_DST_FORMAT - Scale Destination Format Control Register */
30110/*! @{ */
30111#define MED_DC_SCALER_SCALE_DST_FORMAT_DST_FORMAT_MASK (0x3U)
30112#define MED_DC_SCALER_SCALE_DST_FORMAT_DST_FORMAT_SHIFT (0U)
30113#define MED_DC_SCALER_SCALE_DST_FORMAT_DST_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_DST_FORMAT_DST_FORMAT_SHIFT)) & MED_DC_SCALER_SCALE_DST_FORMAT_DST_FORMAT_MASK)
30114/*! @} */
30115
30116/*! @name SCALE_SRC_LUMA_RES - Scale Source Luma Resolution Register */
30117/*! @{ */
30118#define MED_DC_SCALER_SCALE_SRC_LUMA_RES_WIDTH_MASK (0xFFFU)
30119#define MED_DC_SCALER_SCALE_SRC_LUMA_RES_WIDTH_SHIFT (0U)
30120#define MED_DC_SCALER_SCALE_SRC_LUMA_RES_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_LUMA_RES_WIDTH_SHIFT)) & MED_DC_SCALER_SCALE_SRC_LUMA_RES_WIDTH_MASK)
30121#define MED_DC_SCALER_SCALE_SRC_LUMA_RES_HEIGHT_MASK (0xFFF0000U)
30122#define MED_DC_SCALER_SCALE_SRC_LUMA_RES_HEIGHT_SHIFT (16U)
30123#define MED_DC_SCALER_SCALE_SRC_LUMA_RES_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_LUMA_RES_HEIGHT_SHIFT)) & MED_DC_SCALER_SCALE_SRC_LUMA_RES_HEIGHT_MASK)
30124/*! @} */
30125
30126/*! @name SCALE_SRC_CHROMA_RES - Scale Source Chroma Resolution Register */
30127/*! @{ */
30128#define MED_DC_SCALER_SCALE_SRC_CHROMA_RES_WIDTH_MASK (0xFFFU)
30129#define MED_DC_SCALER_SCALE_SRC_CHROMA_RES_WIDTH_SHIFT (0U)
30130#define MED_DC_SCALER_SCALE_SRC_CHROMA_RES_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_CHROMA_RES_WIDTH_SHIFT)) & MED_DC_SCALER_SCALE_SRC_CHROMA_RES_WIDTH_MASK)
30131#define MED_DC_SCALER_SCALE_SRC_CHROMA_RES_HEIGHT_MASK (0xFFF0000U)
30132#define MED_DC_SCALER_SCALE_SRC_CHROMA_RES_HEIGHT_SHIFT (16U)
30133#define MED_DC_SCALER_SCALE_SRC_CHROMA_RES_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_CHROMA_RES_HEIGHT_SHIFT)) & MED_DC_SCALER_SCALE_SRC_CHROMA_RES_HEIGHT_MASK)
30134/*! @} */
30135
30136/*! @name SCALE_DST_LUMA_RES - Scale Destination Luma Resolution Register */
30137/*! @{ */
30138#define MED_DC_SCALER_SCALE_DST_LUMA_RES_WIDTH_MASK (0xFFFU)
30139#define MED_DC_SCALER_SCALE_DST_LUMA_RES_WIDTH_SHIFT (0U)
30140#define MED_DC_SCALER_SCALE_DST_LUMA_RES_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_DST_LUMA_RES_WIDTH_SHIFT)) & MED_DC_SCALER_SCALE_DST_LUMA_RES_WIDTH_MASK)
30141#define MED_DC_SCALER_SCALE_DST_LUMA_RES_HEIGHT_MASK (0xFFF0000U)
30142#define MED_DC_SCALER_SCALE_DST_LUMA_RES_HEIGHT_SHIFT (16U)
30143#define MED_DC_SCALER_SCALE_DST_LUMA_RES_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_DST_LUMA_RES_HEIGHT_SHIFT)) & MED_DC_SCALER_SCALE_DST_LUMA_RES_HEIGHT_MASK)
30144/*! @} */
30145
30146/*! @name SCALE_DST_CHROMA_RES - Scale Destination Chroma Resolution Register */
30147/*! @{ */
30148#define MED_DC_SCALER_SCALE_DST_CHROMA_RES_WIDTH_MASK (0xFFFU)
30149#define MED_DC_SCALER_SCALE_DST_CHROMA_RES_WIDTH_SHIFT (0U)
30150#define MED_DC_SCALER_SCALE_DST_CHROMA_RES_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_DST_CHROMA_RES_WIDTH_SHIFT)) & MED_DC_SCALER_SCALE_DST_CHROMA_RES_WIDTH_MASK)
30151/*! @} */
30152
30153/*! @name SCALE_V_LUMA_START - Scale Vertical Luma Start Register */
30154/*! @{ */
30155#define MED_DC_SCALER_SCALE_V_LUMA_START_V_START_MASK (0x3FFFFFFU)
30156#define MED_DC_SCALER_SCALE_V_LUMA_START_V_START_SHIFT (0U)
30157#define MED_DC_SCALER_SCALE_V_LUMA_START_V_START(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_V_LUMA_START_V_START_SHIFT)) & MED_DC_SCALER_SCALE_V_LUMA_START_V_START_MASK)
30158/*! @} */
30159
30160/*! @name SCALE_V_LUMA_INC - Scale Vertical Luma Increment Register */
30161/*! @{ */
30162#define MED_DC_SCALER_SCALE_V_LUMA_INC_V_INC_MASK (0xFFFFFU)
30163#define MED_DC_SCALER_SCALE_V_LUMA_INC_V_INC_SHIFT (0U)
30164#define MED_DC_SCALER_SCALE_V_LUMA_INC_V_INC(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_V_LUMA_INC_V_INC_SHIFT)) & MED_DC_SCALER_SCALE_V_LUMA_INC_V_INC_MASK)
30165/*! @} */
30166
30167/*! @name SCALE_H_LUMA_START - Scale Horizontal Luma Start Register */
30168/*! @{ */
30169#define MED_DC_SCALER_SCALE_H_LUMA_START_H_START_MASK (0x3FFFFFFU)
30170#define MED_DC_SCALER_SCALE_H_LUMA_START_H_START_SHIFT (0U)
30171#define MED_DC_SCALER_SCALE_H_LUMA_START_H_START(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_H_LUMA_START_H_START_SHIFT)) & MED_DC_SCALER_SCALE_H_LUMA_START_H_START_MASK)
30172/*! @} */
30173
30174/*! @name SCALE_H_LUMA_INC - Scale Horizontal Luma Increment Register */
30175/*! @{ */
30176#define MED_DC_SCALER_SCALE_H_LUMA_INC_H_INC_MASK (0xFFFFFU)
30177#define MED_DC_SCALER_SCALE_H_LUMA_INC_H_INC_SHIFT (0U)
30178#define MED_DC_SCALER_SCALE_H_LUMA_INC_H_INC(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_H_LUMA_INC_H_INC_SHIFT)) & MED_DC_SCALER_SCALE_H_LUMA_INC_H_INC_MASK)
30179/*! @} */
30180
30181/*! @name SCALE_V_CHROMA_START - Scale Vertical Chroma Start Register */
30182/*! @{ */
30183#define MED_DC_SCALER_SCALE_V_CHROMA_START_V_START_MASK (0x3FFFFFFU)
30184#define MED_DC_SCALER_SCALE_V_CHROMA_START_V_START_SHIFT (0U)
30185#define MED_DC_SCALER_SCALE_V_CHROMA_START_V_START(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_V_CHROMA_START_V_START_SHIFT)) & MED_DC_SCALER_SCALE_V_CHROMA_START_V_START_MASK)
30186/*! @} */
30187
30188/*! @name SCALE_V_CHROMA_INC - Scale Vertical Chroma Increment Register */
30189/*! @{ */
30190#define MED_DC_SCALER_SCALE_V_CHROMA_INC_V_INC_MASK (0xFFFFFU)
30191#define MED_DC_SCALER_SCALE_V_CHROMA_INC_V_INC_SHIFT (0U)
30192#define MED_DC_SCALER_SCALE_V_CHROMA_INC_V_INC(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_V_CHROMA_INC_V_INC_SHIFT)) & MED_DC_SCALER_SCALE_V_CHROMA_INC_V_INC_MASK)
30193/*! @} */
30194
30195/*! @name SCALE_H_CHROMA_START - Scale Horizontal Chroma Start Register */
30196/*! @{ */
30197#define MED_DC_SCALER_SCALE_H_CHROMA_START_H_START_MASK (0x3FFFFFFU)
30198#define MED_DC_SCALER_SCALE_H_CHROMA_START_H_START_SHIFT (0U)
30199#define MED_DC_SCALER_SCALE_H_CHROMA_START_H_START(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_H_CHROMA_START_H_START_SHIFT)) & MED_DC_SCALER_SCALE_H_CHROMA_START_H_START_MASK)
30200/*! @} */
30201
30202/*! @name SCALE_H_CHROMA_INC - Scale Horizontal Chroma Increment Register */
30203/*! @{ */
30204#define MED_DC_SCALER_SCALE_H_CHROMA_INC_H_INC_MASK (0xFFFFFU)
30205#define MED_DC_SCALER_SCALE_H_CHROMA_INC_H_INC_SHIFT (0U)
30206#define MED_DC_SCALER_SCALE_H_CHROMA_INC_H_INC(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_H_CHROMA_INC_H_INC_SHIFT)) & MED_DC_SCALER_SCALE_H_CHROMA_INC_H_INC_MASK)
30207/*! @} */
30208
30209/*! @name SCALE_COEF_ARRAY - Scale Coefficient Memory Array */
30210/*! @{ */
30211#define MED_DC_SCALER_SCALE_COEF_ARRAY_COEF_MASK (0xFFFU)
30212#define MED_DC_SCALER_SCALE_COEF_ARRAY_COEF_SHIFT (0U)
30213#define MED_DC_SCALER_SCALE_COEF_ARRAY_COEF(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_COEF_ARRAY_COEF_SHIFT)) & MED_DC_SCALER_SCALE_COEF_ARRAY_COEF_MASK)
30214/*! @} */
30215
30216
30217/*!
30218 * @}
30219 */ /* end of group MED_DC_SCALER_Register_Masks */
30220
30221
30222/* MED_DC_SCALER - Peripheral instance base addresses */
30223/** Peripheral DCSS__MED_DC_SCALER base address */
30224#define DCSS__MED_DC_SCALER_BASE (0x32E1C000u)
30225/** Peripheral DCSS__MED_DC_SCALER base pointer */
30226#define DCSS__MED_DC_SCALER ((MED_DC_SCALER_Type *)DCSS__MED_DC_SCALER_BASE)
30227/** Array initializer of MED_DC_SCALER peripheral base addresses */
30228#define MED_DC_SCALER_BASE_ADDRS { DCSS__MED_DC_SCALER_BASE }
30229/** Array initializer of MED_DC_SCALER peripheral base pointers */
30230#define MED_DC_SCALER_BASE_PTRS { DCSS__MED_DC_SCALER }
30231
30232/*!
30233 * @}
30234 */ /* end of group MED_DC_SCALER_Peripheral_Access_Layer */
30235
30236
30237/* ----------------------------------------------------------------------------
30238 -- MED_HDR10 Peripheral Access Layer
30239 ---------------------------------------------------------------------------- */
30240
30241/*!
30242 * @addtogroup MED_HDR10_Peripheral_Access_Layer MED_HDR10 Peripheral Access Layer
30243 * @{
30244 */
30245
30246/** MED_HDR10 - Register Layout Typedef */
30247typedef struct {
30248 __IO uint32_t PIPE1_A0_LUT; /**< A0 component Look-Up-Table. (LUT), offset: 0x0 */
30249 uint8_t RESERVED_0[4092];
30250 __IO uint32_t PIPE1_A1_LUT; /**< A1 component Look-Up-Table. (LUT), offset: 0x1000 */
30251 uint8_t RESERVED_1[4092];
30252 __IO uint32_t PIPE1_A2_LUT; /**< A2 component Look-Up-Table. (LUT), offset: 0x2000 */
30253 uint8_t RESERVED_2[4092];
30254 __IO uint32_t HDR_PIPE1_CSCA_CONTROL_REG; /**< Pipe1 Colorspace Converter A control., offset: 0x3000 */
30255 __IO uint32_t HDR_PIPE1_CSCA_H00; /**< Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient, offset: 0x3004 */
30256 __IO uint32_t HDR_PIPE1_CSCA_H10; /**< Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient, offset: 0x3008 */
30257 __IO uint32_t HDR_PIPE1_CSCA_H20; /**< Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient, offset: 0x300C */
30258 __IO uint32_t HDR_PIPE1_CSCA_H01; /**< Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient, offset: 0x3010 */
30259 __IO uint32_t HDR_PIPE1_CSCA_H11; /**< Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient, offset: 0x3014 */
30260 __IO uint32_t HDR_PIPE1_CSCA_H21; /**< Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient, offset: 0x3018 */
30261 __IO uint32_t HDR_PIPE1_CSCA_H02; /**< Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient, offset: 0x301C */
30262 __IO uint32_t HDR_PIPE1_CSCA_H12; /**< Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient, offset: 0x3020 */
30263 __IO uint32_t HDR_PIPE1_CSCA_H22; /**< Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient, offset: 0x3024 */
30264 __IO uint32_t HDR_PIPE1_CSCA_IO_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset, offset: 0x3028 */
30265 __IO uint32_t HDR_PIPE1_CSCA_IO_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset, offset: 0x302C */
30266 __IO uint32_t HDR_PIPE1_CSCA_IO_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset, offset: 0x3030 */
30267 __IO uint32_t HDR_PIPE1_CSCA_IO_MIN_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 clip min., offset: 0x3034 */
30268 __IO uint32_t HDR_PIPE1_CSCA_IO_MIN_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 clip min., offset: 0x3038 */
30269 __IO uint32_t HDR_PIPE1_CSCA_IO_MIN_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 clip min., offset: 0x303C */
30270 __IO uint32_t HDR_PIPE1_CSCA_IO_MAX_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 clip max value., offset: 0x3040 */
30271 __IO uint32_t HDR_PIPE1_CSCA_IO_MAX_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 clip max value., offset: 0x3044 */
30272 __IO uint32_t HDR_PIPE1_CSCA_IO_MAX_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 clip max value., offset: 0x3048 */
30273 __IO uint32_t HDR_PIPE1_CSCA_NORM; /**< Pipe1 Colorspace Converter A (CSCA) normalization factor, offset: 0x304C */
30274 __IO uint32_t HDR_PIPE1_CSCA_OO_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 0, offset: 0x3050 */
30275 __IO uint32_t HDR_PIPE1_CSCA_OO_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 1, offset: 0x3054 */
30276 __IO uint32_t HDR_PIPE1_CSCA_OO_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 2, offset: 0x3058 */
30277 __IO uint32_t HDR_PIPE1_CSCA_OMIN_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0, offset: 0x305C */
30278 __IO uint32_t HDR_PIPE1_CSCA_OMIN_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1, offset: 0x3060 */
30279 __IO uint32_t HDR_PIPE1_CSCA_OMIN_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2, offset: 0x3064 */
30280 __IO uint32_t HDR_PIPE1_CSCA_OMAX_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0, offset: 0x3068 */
30281 __IO uint32_t HDR_PIPE1_CSCA_OMAX_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1, offset: 0x306C */
30282 __IO uint32_t HDR_PIPE1_CSCA_OMAX_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2, offset: 0x3070 */
30283 uint32_t HDR_PIPE1_ENTRY_29; /**< PIPE1: NOT USED, offset: 0x3074 */
30284 uint8_t RESERVED_3[8];
30285 __IO uint32_t HDR_PIPE1_LUT_CONTROL_REG; /**< Pipe1 LUT control register, offset: 0x3080 */
30286 uint8_t RESERVED_4[1916];
30287 __IO uint32_t HDR_PIPE1_CSCB_CONTROL_REG; /**< Pipe1 Colorspace Converter B control., offset: 0x3800 */
30288 __IO uint32_t HDR_PIPE1_CSCB_H00; /**< Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient, offset: 0x3804 */
30289 __IO uint32_t HDR_PIPE1_CSCB_H10; /**< Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient, offset: 0x3808 */
30290 __IO uint32_t HDR_PIPE1_CSCB_H20; /**< Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient, offset: 0x380C */
30291 __IO uint32_t HDR_PIPE1_CSCB_H01; /**< Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient, offset: 0x3810 */
30292 __IO uint32_t HDR_PIPE1_CSCB_H11; /**< Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient, offset: 0x3814 */
30293 __IO uint32_t HDR_PIPE1_CSCB_H21; /**< Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient, offset: 0x3818 */
30294 __IO uint32_t HDR_PIPE1_CSCB_H02; /**< Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient, offset: 0x381C */
30295 __IO uint32_t HDR_PIPE1_CSCB_H12; /**< Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient, offset: 0x3820 */
30296 __IO uint32_t HDR_PIPE1_CSCB_H22; /**< Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient, offset: 0x3824 */
30297 __IO uint32_t HDR_PIPE1_CSCB_IO_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset, offset: 0x3828 */
30298 __IO uint32_t HDR_PIPE1_CSCB_IO_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset, offset: 0x382C */
30299 __IO uint32_t HDR_PIPE1_CSCB_IO_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset, offset: 0x3830 */
30300 __IO uint32_t HDR_PIPE1_CSCB_IO_MIN_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 clip min., offset: 0x3834 */
30301 __IO uint32_t HDR_PIPE1_CSCB_IO_MIN_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 clip min., offset: 0x3838 */
30302 __IO uint32_t HDR_PIPE1_CSCB_IO_MIN_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 clip min., offset: 0x383C */
30303 __IO uint32_t HDR_PIPE1_CSCB_IO_MAX_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 clip max value., offset: 0x3840 */
30304 __IO uint32_t HDR_PIPE1_CSCB_IO_MAX_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 clip max value., offset: 0x3844 */
30305 __IO uint32_t HDR_PIPE1_CSCB_IO_MAX_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 clip max value., offset: 0x3848 */
30306 __IO uint32_t HDR_PIPE1_CSCB_NORM; /**< Pipe1 Colorspace Converter B (CSCB) normalization factor, offset: 0x384C */
30307 __IO uint32_t HDR_PIPE1_CSCB_OO_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 0, offset: 0x3850 */
30308 __IO uint32_t HDR_PIPE1_CSCB_OO_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 1, offset: 0x3854 */
30309 __IO uint32_t HDR_PIPE1_CSCB_OO_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 2, offset: 0x3858 */
30310 __IO uint32_t HDR_PIPE1_CSCB_OMIN_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0, offset: 0x385C */
30311 __IO uint32_t HDR_PIPE1_CSCB_OMIN_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1, offset: 0x3860 */
30312 __IO uint32_t HDR_PIPE1_CSCB_OMIN_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2, offset: 0x3864 */
30313 __IO uint32_t HDR_PIPE1_CSCB_OMAX_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0, offset: 0x3868 */
30314 __IO uint32_t HDR_PIPE1_CSCB_OMAX_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1, offset: 0x386C */
30315 __IO uint32_t HDR_PIPE1_CSCB_OMAX_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2, offset: 0x3870 */
30316 __IO uint32_t HDR_PIPE1_FL2FX; /**< Pipe1 floating point to fixed point control, offset: 0x3874 */
30317 uint32_t HDR_PIPE1_ENTRY_30; /**< PIPE1: NOT USED, offset: 0x3878 */
30318 uint8_t RESERVED_5[1924];
30319 __IO uint32_t PIPE2_A0_LUT; /**< A0 component Look-Up-Table. (LUT), offset: 0x4000 */
30320 uint8_t RESERVED_6[4092];
30321 __IO uint32_t PIPE2_A1_LUT; /**< A1 component Look-Up-Table. (LUT), offset: 0x5000 */
30322 uint8_t RESERVED_7[4092];
30323 __IO uint32_t PIPE2_A2_LUT; /**< A2 component Look-Up-Table. (LUT), offset: 0x6000 */
30324 uint8_t RESERVED_8[4092];
30325 __IO uint32_t HDR_PIPE2_CSCA_CONTROL_REG; /**< Pipe1 Colorspace Converter A control., offset: 0x7000 */
30326 __IO uint32_t HDR_PIPE2_CSCA_H00; /**< Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient, offset: 0x7004 */
30327 __IO uint32_t HDR_PIPE2_CSCA_H10; /**< Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient, offset: 0x7008 */
30328 __IO uint32_t HDR_PIPE2_CSCA_H20; /**< Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient, offset: 0x700C */
30329 __IO uint32_t HDR_PIPE2_CSCA_H01; /**< Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient, offset: 0x7010 */
30330 __IO uint32_t HDR_PIPE2_CSCA_H11; /**< Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient, offset: 0x7014 */
30331 __IO uint32_t HDR_PIPE2_CSCA_H21; /**< Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient, offset: 0x7018 */
30332 __IO uint32_t HDR_PIPE2_CSCA_H02; /**< Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient, offset: 0x701C */
30333 __IO uint32_t HDR_PIPE2_CSCA_H12; /**< Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient, offset: 0x7020 */
30334 __IO uint32_t HDR_PIPE2_CSCA_H22; /**< Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient, offset: 0x7024 */
30335 __IO uint32_t HDR_PIPE2_CSCA_IO_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset, offset: 0x7028 */
30336 __IO uint32_t HDR_PIPE2_CSCA_IO_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset, offset: 0x702C */
30337 __IO uint32_t HDR_PIPE2_CSCA_IO_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset, offset: 0x7030 */
30338 __IO uint32_t HDR_PIPE2_CSCA_IO_MIN_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 clip min., offset: 0x7034 */
30339 __IO uint32_t HDR_PIPE2_CSCA_IO_MIN_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 clip min., offset: 0x7038 */
30340 __IO uint32_t HDR_PIPE2_CSCA_IO_MIN_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 clip min., offset: 0x703C */
30341 __IO uint32_t HDR_PIPE2_CSCA_IO_MAX_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 clip max value., offset: 0x7040 */
30342 __IO uint32_t HDR_PIPE2_CSCA_IO_MAX_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 clip max value., offset: 0x7044 */
30343 __IO uint32_t HDR_PIPE2_CSCA_IO_MAX_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 clip max value., offset: 0x7048 */
30344 __IO uint32_t HDR_PIPE2_CSCA_NORM; /**< Pipe1 Colorspace Converter A (CSCA) normalization factor, offset: 0x704C */
30345 __IO uint32_t HDR_PIPE2_CSCA_OO_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 0, offset: 0x7050 */
30346 __IO uint32_t HDR_PIPE2_CSCA_OO_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 1, offset: 0x7054 */
30347 __IO uint32_t HDR_PIPE2_CSCA_OO_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 2, offset: 0x7058 */
30348 __IO uint32_t HDR_PIPE2_CSCA_OMIN_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0, offset: 0x705C */
30349 __IO uint32_t HDR_PIPE2_CSCA_OMIN_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1, offset: 0x7060 */
30350 __IO uint32_t HDR_PIPE2_CSCA_OMIN_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2, offset: 0x7064 */
30351 __IO uint32_t HDR_PIPE2_CSCA_OMAX_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0, offset: 0x7068 */
30352 __IO uint32_t HDR_PIPE2_CSCA_OMAX_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1, offset: 0x706C */
30353 __IO uint32_t HDR_PIPE2_CSCA_OMAX_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2, offset: 0x7070 */
30354 uint32_t HDR_PIPE2_ENTRY_29; /**< PIPE2: NOT USED, offset: 0x7074 */
30355 uint8_t RESERVED_9[8];
30356 __IO uint32_t HDR_PIPE2_LUT_CONTROL_REG; /**< Pipe1 LUT control register, offset: 0x7080 */
30357 uint8_t RESERVED_10[1916];
30358 __IO uint32_t HDR_PIPE2_CSCB_CONTROL_REG; /**< Pipe1 Colorspace Converter B control., offset: 0x7800 */
30359 __IO uint32_t HDR_PIPE2_CSCB_H00; /**< Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient, offset: 0x7804 */
30360 __IO uint32_t HDR_PIPE2_CSCB_H10; /**< Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient, offset: 0x7808 */
30361 __IO uint32_t HDR_PIPE2_CSCB_H20; /**< Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient, offset: 0x780C */
30362 __IO uint32_t HDR_PIPE2_CSCB_H01; /**< Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient, offset: 0x7810 */
30363 __IO uint32_t HDR_PIPE2_CSCB_H11; /**< Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient, offset: 0x7814 */
30364 __IO uint32_t HDR_PIPE2_CSCB_H21; /**< Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient, offset: 0x7818 */
30365 __IO uint32_t HDR_PIPE2_CSCB_H02; /**< Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient, offset: 0x781C */
30366 __IO uint32_t HDR_PIPE2_CSCB_H12; /**< Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient, offset: 0x7820 */
30367 __IO uint32_t HDR_PIPE2_CSCB_H22; /**< Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient, offset: 0x7824 */
30368 __IO uint32_t HDR_PIPE2_CSCB_IO_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset, offset: 0x7828 */
30369 __IO uint32_t HDR_PIPE2_CSCB_IO_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset, offset: 0x782C */
30370 __IO uint32_t HDR_PIPE2_CSCB_IO_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset, offset: 0x7830 */
30371 __IO uint32_t HDR_PIPE2_CSCB_IO_MIN_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 clip min., offset: 0x7834 */
30372 __IO uint32_t HDR_PIPE2_CSCB_IO_MIN_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 clip min., offset: 0x7838 */
30373 __IO uint32_t HDR_PIPE2_CSCB_IO_MIN_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 clip min., offset: 0x783C */
30374 __IO uint32_t HDR_PIPE2_CSCB_IO_MAX_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 clip max value., offset: 0x7840 */
30375 __IO uint32_t HDR_PIPE2_CSCB_IO_MAX_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 clip max value., offset: 0x7844 */
30376 __IO uint32_t HDR_PIPE2_CSCB_IO_MAX_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 clip max value., offset: 0x7848 */
30377 __IO uint32_t HDR_PIPE2_CSCB_NORM; /**< Pipe1 Colorspace Converter B (CSCB) normalization factor, offset: 0x784C */
30378 __IO uint32_t HDR_PIPE2_CSCB_OO_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 0, offset: 0x7850 */
30379 __IO uint32_t HDR_PIPE2_CSCB_OO_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 1, offset: 0x7854 */
30380 __IO uint32_t HDR_PIPE2_CSCB_OO_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 2, offset: 0x7858 */
30381 __IO uint32_t HDR_PIPE2_CSCB_OMIN_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0, offset: 0x785C */
30382 __IO uint32_t HDR_PIPE2_CSCB_OMIN_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1, offset: 0x7860 */
30383 __IO uint32_t HDR_PIPE2_CSCB_OMIN_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2, offset: 0x7864 */
30384 __IO uint32_t HDR_PIPE2_CSCB_OMAX_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0, offset: 0x7868 */
30385 __IO uint32_t HDR_PIPE2_CSCB_OMAX_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1, offset: 0x786C */
30386 __IO uint32_t HDR_PIPE2_CSCB_OMAX_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2, offset: 0x7870 */
30387 __IO uint32_t HDR_PIPE2_FL2FX; /**< Pipe1 floating point to fixed point control, offset: 0x7874 */
30388 uint32_t HDR_PIPE2_ENTRY_30; /**< PIPE2: NOT USED, offset: 0x7878 */
30389 uint8_t RESERVED_11[1924];
30390 __IO uint32_t PIPE3_A0_LUT; /**< A0 component Look-Up-Table. (LUT), offset: 0x8000 */
30391 uint8_t RESERVED_12[4092];
30392 __IO uint32_t PIPE3_A1_LUT; /**< A1 component Look-Up-Table. (LUT), offset: 0x9000 */
30393 uint8_t RESERVED_13[4092];
30394 __IO uint32_t PIPE3_A2_LUT; /**< A2 component Look-Up-Table. (LUT), offset: 0xA000 */
30395 uint8_t RESERVED_14[4092];
30396 __IO uint32_t HDR_PIPE3_CSCA_CONTROL_REG; /**< Pipe1 Colorspace Converter A control., offset: 0xB000 */
30397 __IO uint32_t HDR_PIPE3_CSCA_H00; /**< Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient, offset: 0xB004 */
30398 __IO uint32_t HDR_PIPE3_CSCA_H10; /**< Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient, offset: 0xB008 */
30399 __IO uint32_t HDR_PIPE3_CSCA_H20; /**< Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient, offset: 0xB00C */
30400 __IO uint32_t HDR_PIPE3_CSCA_H01; /**< Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient, offset: 0xB010 */
30401 __IO uint32_t HDR_PIPE3_CSCA_H11; /**< Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient, offset: 0xB014 */
30402 __IO uint32_t HDR_PIPE3_CSCA_H21; /**< Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient, offset: 0xB018 */
30403 __IO uint32_t HDR_PIPE3_CSCA_H02; /**< Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient, offset: 0xB01C */
30404 __IO uint32_t HDR_PIPE3_CSCA_H12; /**< Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient, offset: 0xB020 */
30405 __IO uint32_t HDR_PIPE3_CSCA_H22; /**< Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient, offset: 0xB024 */
30406 __IO uint32_t HDR_PIPE3_CSCA_IO_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset, offset: 0xB028 */
30407 __IO uint32_t HDR_PIPE3_CSCA_IO_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset, offset: 0xB02C */
30408 __IO uint32_t HDR_PIPE3_CSCA_IO_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset, offset: 0xB030 */
30409 __IO uint32_t HDR_PIPE3_CSCA_IO_MIN_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 clip min., offset: 0xB034 */
30410 __IO uint32_t HDR_PIPE3_CSCA_IO_MIN_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 clip min., offset: 0xB038 */
30411 __IO uint32_t HDR_PIPE3_CSCA_IO_MIN_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 clip min., offset: 0xB03C */
30412 __IO uint32_t HDR_PIPE3_CSCA_IO_MAX_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 clip max value., offset: 0xB040 */
30413 __IO uint32_t HDR_PIPE3_CSCA_IO_MAX_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 clip max value., offset: 0xB044 */
30414 __IO uint32_t HDR_PIPE3_CSCA_IO_MAX_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 clip max value., offset: 0xB048 */
30415 __IO uint32_t HDR_PIPE3_CSCA_NORM; /**< Pipe1 Colorspace Converter A (CSCA) normalization factor, offset: 0xB04C */
30416 __IO uint32_t HDR_PIPE3_CSCA_OO_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 0, offset: 0xB050 */
30417 __IO uint32_t HDR_PIPE3_CSCA_OO_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 1, offset: 0xB054 */
30418 __IO uint32_t HDR_PIPE3_CSCA_OO_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 2, offset: 0xB058 */
30419 __IO uint32_t HDR_PIPE3_CSCA_OMIN_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0, offset: 0xB05C */
30420 __IO uint32_t HDR_PIPE3_CSCA_OMIN_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1, offset: 0xB060 */
30421 __IO uint32_t HDR_PIPE3_CSCA_OMIN_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2, offset: 0xB064 */
30422 __IO uint32_t HDR_PIPE3_CSCA_OMAX_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0, offset: 0xB068 */
30423 __IO uint32_t HDR_PIPE3_CSCA_OMAX_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1, offset: 0xB06C */
30424 __IO uint32_t HDR_PIPE3_CSCA_OMAX_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2, offset: 0xB070 */
30425 uint32_t HDR_PIPE3_ENTRY_29; /**< PIPE3: NOT USED, offset: 0xB074 */
30426 uint8_t RESERVED_15[8];
30427 __IO uint32_t HDR_PIPE3_LUT_CONTROL_REG; /**< Pipe1 LUT control register, offset: 0xB080 */
30428 uint8_t RESERVED_16[1916];
30429 __IO uint32_t HDR_PIPE3_CSCB_CONTROL_REG; /**< Pipe1 Colorspace Converter B control., offset: 0xB800 */
30430 __IO uint32_t HDR_PIPE3_CSCB_H00; /**< Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient, offset: 0xB804 */
30431 __IO uint32_t HDR_PIPE3_CSCB_H10; /**< Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient, offset: 0xB808 */
30432 __IO uint32_t HDR_PIPE3_CSCB_H20; /**< Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient, offset: 0xB80C */
30433 __IO uint32_t HDR_PIPE3_CSCB_H01; /**< Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient, offset: 0xB810 */
30434 __IO uint32_t HDR_PIPE3_CSCB_H11; /**< Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient, offset: 0xB814 */
30435 __IO uint32_t HDR_PIPE3_CSCB_H21; /**< Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient, offset: 0xB818 */
30436 __IO uint32_t HDR_PIPE3_CSCB_H02; /**< Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient, offset: 0xB81C */
30437 __IO uint32_t HDR_PIPE3_CSCB_H12; /**< Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient, offset: 0xB820 */
30438 __IO uint32_t HDR_PIPE3_CSCB_H22; /**< Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient, offset: 0xB824 */
30439 __IO uint32_t HDR_PIPE3_CSCB_IO_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset, offset: 0xB828 */
30440 __IO uint32_t HDR_PIPE3_CSCB_IO_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset, offset: 0xB82C */
30441 __IO uint32_t HDR_PIPE3_CSCB_IO_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset, offset: 0xB830 */
30442 __IO uint32_t HDR_PIPE3_CSCB_IO_MIN_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 clip min., offset: 0xB834 */
30443 __IO uint32_t HDR_PIPE3_CSCB_IO_MIN_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 clip min., offset: 0xB838 */
30444 __IO uint32_t HDR_PIPE3_CSCB_IO_MIN_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 clip min., offset: 0xB83C */
30445 __IO uint32_t HDR_PIPE3_CSCB_IO_MAX_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 clip max value., offset: 0xB840 */
30446 __IO uint32_t HDR_PIPE3_CSCB_IO_MAX_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 clip max value., offset: 0xB844 */
30447 __IO uint32_t HDR_PIPE3_CSCB_IO_MAX_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 clip max value., offset: 0xB848 */
30448 __IO uint32_t HDR_PIPE3_CSCB_NORM; /**< Pipe1 Colorspace Converter B (CSCB) normalization factor, offset: 0xB84C */
30449 __IO uint32_t HDR_PIPE3_CSCB_OO_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 0, offset: 0xB850 */
30450 __IO uint32_t HDR_PIPE3_CSCB_OO_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 1, offset: 0xB854 */
30451 __IO uint32_t HDR_PIPE3_CSCB_OO_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 2, offset: 0xB858 */
30452 __IO uint32_t HDR_PIPE3_CSCB_OMIN_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0, offset: 0xB85C */
30453 __IO uint32_t HDR_PIPE3_CSCB_OMIN_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1, offset: 0xB860 */
30454 __IO uint32_t HDR_PIPE3_CSCB_OMIN_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2, offset: 0xB864 */
30455 __IO uint32_t HDR_PIPE3_CSCB_OMAX_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0, offset: 0xB868 */
30456 __IO uint32_t HDR_PIPE3_CSCB_OMAX_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1, offset: 0xB86C */
30457 __IO uint32_t HDR_PIPE3_CSCB_OMAX_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2, offset: 0xB870 */
30458 __IO uint32_t HDR_PIPE3_FL2FX; /**< Pipe1 floating point to fixed point control, offset: 0xB874 */
30459 uint32_t HDR_PIPE3_ENTRY_30; /**< PIPE3: NOT USED, offset: 0xB878 */
30460 uint8_t RESERVED_17[1924];
30461 __IO uint32_t OPIPE_A0_TABLE; /**< A0 component Linear-to-Non-linear conversion table, offset: 0xC000 */
30462 uint8_t RESERVED_18[4092];
30463 __IO uint32_t OPIPE_A1_TABLE; /**< A1 component Linear-to-Non-linear conversion table, offset: 0xD000 */
30464 uint8_t RESERVED_19[4092];
30465 __IO uint32_t OPIPE_A2_TABLE; /**< A2 component Linear-to-Non-linear conversion table, offset: 0xE000 */
30466 uint8_t RESERVED_20[4092];
30467 __IO uint32_t HDR_OPIPE_CSC_CONTROL_REG; /**< HDR output stage Colorspace Converter (CSCO) control., offset: 0xF000 */
30468 __IO uint32_t HDR_OPIPE_CSC_H00; /**< Pipe1 Colorspace Converter (CSC) h(0,0) matrix coefficient, offset: 0xF004 */
30469 __IO uint32_t HDR_OPIPE_CSC_H10; /**< Pipe1 Colorspace Converter (CSC) h(1,0) matrix coefficient, offset: 0xF008 */
30470 __IO uint32_t HDR_OPIPE_CSC_H20; /**< HDR OUTPUT Colorspace Converter (CSCO) h(2,0) matrix coefficient, offset: 0xF00C */
30471 __IO uint32_t HDR_OPIPE_CSC_H01; /**< HDR OUTPUT pipe Colorspace Converter (CSCO) h(0,1) matrix coefficient, offset: 0xF010 */
30472 __IO uint32_t HDR_OPIPE_CSC_H11; /**< HDR OUTPUT pipe Colorspace Converter (CSCO) h(1,1) matrix coefficient, offset: 0xF014 */
30473 __IO uint32_t HDR_OPIPE_CSC_H21; /**< HDR_output pipe Colorspace Converter (CSCO) h(2,1) matrix coefficient, offset: 0xF018 */
30474 __IO uint32_t HDR_OPIPE_CSC_H02; /**< HDR OUTPUT pipe Colorspace Converter (CSCO) h(0,2) matrix coefficient, offset: 0xF01C */
30475 __IO uint32_t HDR_OPIPE_CSC_H12; /**< HDR OUPUT pipe Colorspace Converter (CSCO) h(1,2) matrix coefficient, offset: 0xF020 */
30476 __IO uint32_t HDR_; /**< HDR OUPUT pipe Colorspace Converter (CSCO) h(2,2) matrix coefficient, offset: 0xF024 */
30477 __IO uint32_t HDR_OPIPE_CSC_IO_0; /**< HDR OUTPUT pipe Colorspace Converter (CSCO) component 0 pre-offset, offset: 0xF028 */
30478 __IO uint32_t HDR_OPIPE_CSC_IO_1; /**< HDR OUPTUT pipe Colorspace Converter (CSCO) component 1 pre-offset, offset: 0xF02C */
30479 __IO uint32_t HDR_OPIPE_CSC_IO_2; /**< HDR OUPUT pipe: Colorspace Converter (CSCO) component 2 pre-offset, offset: 0xF030 */
30480 __IO uint32_t HDR_OPIPE_CSC_MIN_0; /**< HDR OUPTU pipe Colorspace Converter (CSCO) component 0 clip min., offset: 0xF034 */
30481 __IO uint32_t HDR_OPIPE_CSC_MIN_1; /**< HDR OUPUT pipe Colorspace Converter (CSCO) component 1 clip min., offset: 0xF038 */
30482 __IO uint32_t HDR_OPIPE_CSC_MIN_2; /**< HDR OUPTU pipe Colorspace Converter (CSCO) component 2 clip min., offset: 0xF03C */
30483 __IO uint32_t HDR_OPIPE_CSC_MAX_0; /**< HDR OUPTUT pipe Colorspace Converter O (CSC) component 0 clip max value., offset: 0xF040 */
30484 __IO uint32_t HDR_OPIPE_CSC_MAX_1; /**< HDR OUTPUT pipe Colorspace Converter (CSCO) component 1 clip max value., offset: 0xF044 */
30485 __IO uint32_t HDR_OPIPE_CSC_MAX_2; /**< HDR OUTPUT pipe Colorspace Converter (CSCO) component 2 clip max value., offset: 0xF048 */
30486 __IO uint32_t HDR_OPIPE_CSC_NORM; /**< HDR OUPUT pipe Colorspace Converter (CSCO) normalization factor, offset: 0xF04C */
30487 __IO uint32_t HDR_OPIPE_CSC_OO_0; /**< HDR OUPTUT pipe Colorspace Converter (CSC): Post offset component 0, offset: 0xF050 */
30488 __IO uint32_t HDR_OPIPE_CSC_OO_1; /**< HDR OUTPUT pipe Colorspace Converter (CSC): Post offset component 1, offset: 0xF054 */
30489 __IO uint32_t HDR_OPIPE_CSC_OO_2; /**< HDR OUPTUT pipe Colorspace Converter (CSC): Post offset component 2, offset: 0xF058 */
30490 __IO uint32_t HDR_OPIPE_CSC_OMIN_0; /**< HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 0, offset: 0xF05C */
30491 __IO uint32_t HDR_OPIPE_CSC_OMIN_1; /**< HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 1, offset: 0xF060 */
30492 __IO uint32_t HDR_OPIPE_CSC_OMIN_2; /**< HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 2, offset: 0xF064 */
30493 __IO uint32_t HDR_OPIPE_CSC_OMAX_0; /**< HDR OUPTUT pipe Colorspace Converter (CSC): Post offset max clip value for component 0, offset: 0xF068 */
30494 __IO uint32_t HDR_OPIPE_CSC_OMAX_1; /**< HDR OUTPUT pipe Colorspace Converter (CSC): Post offset max clip value for component 1, offset: 0xF06C */
30495 __IO uint32_t HDR_OPIPE_CSC_OMAX_2; /**< HDR OUTPUT pipe Colorspace Converter (CSC): Post offset max clip value for component 2, offset: 0xF070 */
30496 uint8_t RESERVED_21[2048];
30497 __IO uint32_t HDR_OPIPE_2NL_CONTROL_REG; /**< HDR OUTPUT -TO NON LINEAR pipeline control, offset: 0xF874 */
30498} MED_HDR10_Type;
30499
30500/* ----------------------------------------------------------------------------
30501 -- MED_HDR10 Register Masks
30502 ---------------------------------------------------------------------------- */
30503
30504/*!
30505 * @addtogroup MED_HDR10_Register_Masks MED_HDR10 Register Masks
30506 * @{
30507 */
30508
30509/*! @name PIPE1_A0_LUT - A0 component Look-Up-Table. (LUT) */
30510/*! @{ */
30511#define MED_HDR10_PIPE1_A0_LUT_PIPE1_A0_LUT_MASK (0x3FFFU)
30512#define MED_HDR10_PIPE1_A0_LUT_PIPE1_A0_LUT_SHIFT (0U)
30513#define MED_HDR10_PIPE1_A0_LUT_PIPE1_A0_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE1_A0_LUT_PIPE1_A0_LUT_SHIFT)) & MED_HDR10_PIPE1_A0_LUT_PIPE1_A0_LUT_MASK)
30514/*! @} */
30515
30516/*! @name PIPE1_A1_LUT - A1 component Look-Up-Table. (LUT) */
30517/*! @{ */
30518#define MED_HDR10_PIPE1_A1_LUT_PIPE1_A1_LUT_MASK (0x3FFFU)
30519#define MED_HDR10_PIPE1_A1_LUT_PIPE1_A1_LUT_SHIFT (0U)
30520#define MED_HDR10_PIPE1_A1_LUT_PIPE1_A1_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE1_A1_LUT_PIPE1_A1_LUT_SHIFT)) & MED_HDR10_PIPE1_A1_LUT_PIPE1_A1_LUT_MASK)
30521/*! @} */
30522
30523/*! @name PIPE1_A2_LUT - A2 component Look-Up-Table. (LUT) */
30524/*! @{ */
30525#define MED_HDR10_PIPE1_A2_LUT_PIPE1_A2_LUT_MASK (0x3FFFU)
30526#define MED_HDR10_PIPE1_A2_LUT_PIPE1_A2_LUT_SHIFT (0U)
30527#define MED_HDR10_PIPE1_A2_LUT_PIPE1_A2_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE1_A2_LUT_PIPE1_A2_LUT_SHIFT)) & MED_HDR10_PIPE1_A2_LUT_PIPE1_A2_LUT_MASK)
30528/*! @} */
30529
30530/*! @name HDR_PIPE1_CSCA_CONTROL_REG - Pipe1 Colorspace Converter A control. */
30531/*! @{ */
30532#define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_MASK (0x1U)
30533#define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_SHIFT (0U)
30534#define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_MASK)
30535#define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U)
30536#define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U)
30537#define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK)
30538#define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_BYPASS_MASK (0x8000U)
30539#define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_BYPASS_SHIFT (15U)
30540#define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_BYPASS_MASK)
30541/*! @} */
30542
30543/*! @name HDR_PIPE1_CSCA_H00 - Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient */
30544/*! @{ */
30545#define MED_HDR10_HDR_PIPE1_CSCA_H00_H00_MASK (0xFFFFU)
30546#define MED_HDR10_HDR_PIPE1_CSCA_H00_H00_SHIFT (0U)
30547#define MED_HDR10_HDR_PIPE1_CSCA_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H00_H00_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H00_H00_MASK)
30548/*! @} */
30549
30550/*! @name HDR_PIPE1_CSCA_H10 - Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient */
30551/*! @{ */
30552#define MED_HDR10_HDR_PIPE1_CSCA_H10_H10_MASK (0xFFFFU)
30553#define MED_HDR10_HDR_PIPE1_CSCA_H10_H10_SHIFT (0U)
30554#define MED_HDR10_HDR_PIPE1_CSCA_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H10_H10_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H10_H10_MASK)
30555/*! @} */
30556
30557/*! @name HDR_PIPE1_CSCA_H20 - Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient */
30558/*! @{ */
30559#define MED_HDR10_HDR_PIPE1_CSCA_H20_H20_MASK (0xFFFFU)
30560#define MED_HDR10_HDR_PIPE1_CSCA_H20_H20_SHIFT (0U)
30561#define MED_HDR10_HDR_PIPE1_CSCA_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H20_H20_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H20_H20_MASK)
30562/*! @} */
30563
30564/*! @name HDR_PIPE1_CSCA_H01 - Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient */
30565/*! @{ */
30566#define MED_HDR10_HDR_PIPE1_CSCA_H01_H01_MASK (0xFFFFU)
30567#define MED_HDR10_HDR_PIPE1_CSCA_H01_H01_SHIFT (0U)
30568#define MED_HDR10_HDR_PIPE1_CSCA_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H01_H01_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H01_H01_MASK)
30569/*! @} */
30570
30571/*! @name HDR_PIPE1_CSCA_H11 - Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient */
30572/*! @{ */
30573#define MED_HDR10_HDR_PIPE1_CSCA_H11_H11_MASK (0xFFFFU)
30574#define MED_HDR10_HDR_PIPE1_CSCA_H11_H11_SHIFT (0U)
30575#define MED_HDR10_HDR_PIPE1_CSCA_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H11_H11_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H11_H11_MASK)
30576/*! @} */
30577
30578/*! @name HDR_PIPE1_CSCA_H21 - Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient */
30579/*! @{ */
30580#define MED_HDR10_HDR_PIPE1_CSCA_H21_H21_MASK (0xFFFFU)
30581#define MED_HDR10_HDR_PIPE1_CSCA_H21_H21_SHIFT (0U)
30582#define MED_HDR10_HDR_PIPE1_CSCA_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H21_H21_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H21_H21_MASK)
30583/*! @} */
30584
30585/*! @name HDR_PIPE1_CSCA_H02 - Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient */
30586/*! @{ */
30587#define MED_HDR10_HDR_PIPE1_CSCA_H02_H02_MASK (0xFFFFU)
30588#define MED_HDR10_HDR_PIPE1_CSCA_H02_H02_SHIFT (0U)
30589#define MED_HDR10_HDR_PIPE1_CSCA_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H02_H02_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H02_H02_MASK)
30590/*! @} */
30591
30592/*! @name HDR_PIPE1_CSCA_H12 - Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient */
30593/*! @{ */
30594#define MED_HDR10_HDR_PIPE1_CSCA_H12_H12_MASK (0xFFFFU)
30595#define MED_HDR10_HDR_PIPE1_CSCA_H12_H12_SHIFT (0U)
30596#define MED_HDR10_HDR_PIPE1_CSCA_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H12_H12_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H12_H12_MASK)
30597/*! @} */
30598
30599/*! @name HDR_PIPE1_CSCA_H22 - Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient */
30600/*! @{ */
30601#define MED_HDR10_HDR_PIPE1_CSCA_H22_H22_MASK (0xFFFFU)
30602#define MED_HDR10_HDR_PIPE1_CSCA_H22_H22_SHIFT (0U)
30603#define MED_HDR10_HDR_PIPE1_CSCA_H22_H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H22_H22_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H22_H22_MASK)
30604/*! @} */
30605
30606/*! @name HDR_PIPE1_CSCA_IO_0 - Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset */
30607/*! @{ */
30608#define MED_HDR10_HDR_PIPE1_CSCA_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFU)
30609#define MED_HDR10_HDR_PIPE1_CSCA_IO_0_COMPO_PRE_OFFSET_SHIFT (0U)
30610#define MED_HDR10_HDR_PIPE1_CSCA_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_0_COMPO_PRE_OFFSET_MASK)
30611/*! @} */
30612
30613/*! @name HDR_PIPE1_CSCA_IO_1 - Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset */
30614/*! @{ */
30615#define MED_HDR10_HDR_PIPE1_CSCA_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFU)
30616#define MED_HDR10_HDR_PIPE1_CSCA_IO_1_COMP1_PRE_OFFSET_SHIFT (0U)
30617#define MED_HDR10_HDR_PIPE1_CSCA_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_1_COMP1_PRE_OFFSET_MASK)
30618/*! @} */
30619
30620/*! @name HDR_PIPE1_CSCA_IO_2 - Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset */
30621/*! @{ */
30622#define MED_HDR10_HDR_PIPE1_CSCA_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFU)
30623#define MED_HDR10_HDR_PIPE1_CSCA_IO_2_COMP2_PRE_OFFSET_SHIFT (0U)
30624#define MED_HDR10_HDR_PIPE1_CSCA_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_2_COMP2_PRE_OFFSET_MASK)
30625/*! @} */
30626
30627/*! @name HDR_PIPE1_CSCA_IO_MIN_0 - Pipe1 Colorspace Converter A (CSCA) component 0 clip min. */
30628/*! @{ */
30629#define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFU)
30630#define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_0_COMP0_CLIP_MIN_SHIFT (0U)
30631#define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_0_COMP0_CLIP_MIN_MASK)
30632/*! @} */
30633
30634/*! @name HDR_PIPE1_CSCA_IO_MIN_1 - Pipe1 Colorspace Converter A (CSCA) component 1 clip min. */
30635/*! @{ */
30636#define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFU)
30637#define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_1_COMP1_CLIP_MIN_SHIFT (0U)
30638#define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_1_COMP1_CLIP_MIN_MASK)
30639/*! @} */
30640
30641/*! @name HDR_PIPE1_CSCA_IO_MIN_2 - Pipe1 Colorspace Converter A (CSCA) component 2 clip min. */
30642/*! @{ */
30643#define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFU)
30644#define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_2_COMP2_CLIP_MIN_SHIFT (0U)
30645#define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_2_COMP2_CLIP_MIN_MASK)
30646/*! @} */
30647
30648/*! @name HDR_PIPE1_CSCA_IO_MAX_0 - Pipe1 Colorspace Converter A (CSCA) component 0 clip max value. */
30649/*! @{ */
30650#define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFU)
30651#define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_0_COMP0_CLIP_MAX_SHIFT (0U)
30652#define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_0_COMP0_CLIP_MAX_MASK)
30653/*! @} */
30654
30655/*! @name HDR_PIPE1_CSCA_IO_MAX_1 - Pipe1 Colorspace Converter A (CSCA) component 1 clip max value. */
30656/*! @{ */
30657#define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFU)
30658#define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_1_COMP1_CLIP_MAX_SHIFT (0U)
30659#define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_1_COMP1_CLIP_MAX_MASK)
30660/*! @} */
30661
30662/*! @name HDR_PIPE1_CSCA_IO_MAX_2 - Pipe1 Colorspace Converter A (CSCA) component 2 clip max value. */
30663/*! @{ */
30664#define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFU)
30665#define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_2_COMP2_CLIP_MAX_SHIFT (0U)
30666#define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_2_COMP2_CLIP_MAX_MASK)
30667/*! @} */
30668
30669/*! @name HDR_PIPE1_CSCA_NORM - Pipe1 Colorspace Converter A (CSCA) normalization factor */
30670/*! @{ */
30671#define MED_HDR10_HDR_PIPE1_CSCA_NORM_CSCA_NORM_MASK (0x1FU)
30672#define MED_HDR10_HDR_PIPE1_CSCA_NORM_CSCA_NORM_SHIFT (0U)
30673#define MED_HDR10_HDR_PIPE1_CSCA_NORM_CSCA_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_NORM_CSCA_NORM_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_NORM_CSCA_NORM_MASK)
30674/*! @} */
30675
30676/*! @name HDR_PIPE1_CSCA_OO_0 - Pipe1 Colorspace Converter A (CSCA): Post offset component 0 */
30677/*! @{ */
30678#define MED_HDR10_HDR_PIPE1_CSCA_OO_0_CSCA_OO_0_MASK (0xFFFFFFFU)
30679#define MED_HDR10_HDR_PIPE1_CSCA_OO_0_CSCA_OO_0_SHIFT (0U)
30680#define MED_HDR10_HDR_PIPE1_CSCA_OO_0_CSCA_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OO_0_CSCA_OO_0_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OO_0_CSCA_OO_0_MASK)
30681/*! @} */
30682
30683/*! @name HDR_PIPE1_CSCA_OO_1 - Pipe1 Colorspace Converter A (CSCA): Post offset component 1 */
30684/*! @{ */
30685#define MED_HDR10_HDR_PIPE1_CSCA_OO_1_CSCA_OO_1_MASK (0xFFFFFFFU)
30686#define MED_HDR10_HDR_PIPE1_CSCA_OO_1_CSCA_OO_1_SHIFT (0U)
30687#define MED_HDR10_HDR_PIPE1_CSCA_OO_1_CSCA_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OO_1_CSCA_OO_1_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OO_1_CSCA_OO_1_MASK)
30688/*! @} */
30689
30690/*! @name HDR_PIPE1_CSCA_OO_2 - Pipe1 Colorspace Converter A (CSCA): Post offset component 2 */
30691/*! @{ */
30692#define MED_HDR10_HDR_PIPE1_CSCA_OO_2_CSCA_OO_2_MASK (0xFFFFFFFU)
30693#define MED_HDR10_HDR_PIPE1_CSCA_OO_2_CSCA_OO_2_SHIFT (0U)
30694#define MED_HDR10_HDR_PIPE1_CSCA_OO_2_CSCA_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OO_2_CSCA_OO_2_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OO_2_CSCA_OO_2_MASK)
30695/*! @} */
30696
30697/*! @name HDR_PIPE1_CSCA_OMIN_0 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0 */
30698/*! @{ */
30699#define MED_HDR10_HDR_PIPE1_CSCA_OMIN_0_POST_OFF_MIN_MASK (0x3FFU)
30700#define MED_HDR10_HDR_PIPE1_CSCA_OMIN_0_POST_OFF_MIN_SHIFT (0U)
30701#define MED_HDR10_HDR_PIPE1_CSCA_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OMIN_0_POST_OFF_MIN_MASK)
30702/*! @} */
30703
30704/*! @name HDR_PIPE1_CSCA_OMIN_1 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1 */
30705/*! @{ */
30706#define MED_HDR10_HDR_PIPE1_CSCA_OMIN_1_POST_OFF_MIN_MASK (0x3FFU)
30707#define MED_HDR10_HDR_PIPE1_CSCA_OMIN_1_POST_OFF_MIN_SHIFT (0U)
30708#define MED_HDR10_HDR_PIPE1_CSCA_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OMIN_1_POST_OFF_MIN_MASK)
30709/*! @} */
30710
30711/*! @name HDR_PIPE1_CSCA_OMIN_2 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2 */
30712/*! @{ */
30713#define MED_HDR10_HDR_PIPE1_CSCA_OMIN_2_POST_OFF_MIN_MASK (0x3FFU)
30714#define MED_HDR10_HDR_PIPE1_CSCA_OMIN_2_POST_OFF_MIN_SHIFT (0U)
30715#define MED_HDR10_HDR_PIPE1_CSCA_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OMIN_2_POST_OFF_MIN_MASK)
30716/*! @} */
30717
30718/*! @name HDR_PIPE1_CSCA_OMAX_0 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0 */
30719/*! @{ */
30720#define MED_HDR10_HDR_PIPE1_CSCA_OMAX_0_POST_OFF_MAX_MASK (0x3FFU)
30721#define MED_HDR10_HDR_PIPE1_CSCA_OMAX_0_POST_OFF_MAX_SHIFT (0U)
30722#define MED_HDR10_HDR_PIPE1_CSCA_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OMAX_0_POST_OFF_MAX_MASK)
30723/*! @} */
30724
30725/*! @name HDR_PIPE1_CSCA_OMAX_1 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1 */
30726/*! @{ */
30727#define MED_HDR10_HDR_PIPE1_CSCA_OMAX_1_POST_OFF_MAX_MASK (0x3FFU)
30728#define MED_HDR10_HDR_PIPE1_CSCA_OMAX_1_POST_OFF_MAX_SHIFT (0U)
30729#define MED_HDR10_HDR_PIPE1_CSCA_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OMAX_1_POST_OFF_MAX_MASK)
30730/*! @} */
30731
30732/*! @name HDR_PIPE1_CSCA_OMAX_2 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2 */
30733/*! @{ */
30734#define MED_HDR10_HDR_PIPE1_CSCA_OMAX_2_POST_OFF_MAX_MASK (0x3FFU)
30735#define MED_HDR10_HDR_PIPE1_CSCA_OMAX_2_POST_OFF_MAX_SHIFT (0U)
30736#define MED_HDR10_HDR_PIPE1_CSCA_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OMAX_2_POST_OFF_MAX_MASK)
30737/*! @} */
30738
30739/*! @name HDR_PIPE1_LUT_CONTROL_REG - Pipe1 LUT control register */
30740/*! @{ */
30741#define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_MASK (0x1U)
30742#define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_SHIFT (0U)
30743#define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_MASK)
30744#define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U)
30745#define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U)
30746#define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK)
30747#define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_BYPASS_MASK (0x8000U)
30748#define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_BYPASS_SHIFT (15U)
30749#define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_BYPASS_MASK)
30750/*! @} */
30751
30752/*! @name HDR_PIPE1_CSCB_CONTROL_REG - Pipe1 Colorspace Converter B control. */
30753/*! @{ */
30754#define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_MASK (0x1U)
30755#define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_SHIFT (0U)
30756#define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_MASK)
30757#define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U)
30758#define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U)
30759#define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK)
30760#define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_BYPASS_MASK (0x8000U)
30761#define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_BYPASS_SHIFT (15U)
30762#define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_BYPASS_MASK)
30763/*! @} */
30764
30765/*! @name HDR_PIPE1_CSCB_H00 - Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient */
30766/*! @{ */
30767#define MED_HDR10_HDR_PIPE1_CSCB_H00_H00_MASK (0xFFFFU)
30768#define MED_HDR10_HDR_PIPE1_CSCB_H00_H00_SHIFT (0U)
30769#define MED_HDR10_HDR_PIPE1_CSCB_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H00_H00_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H00_H00_MASK)
30770/*! @} */
30771
30772/*! @name HDR_PIPE1_CSCB_H10 - Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient */
30773/*! @{ */
30774#define MED_HDR10_HDR_PIPE1_CSCB_H10_H10_MASK (0xFFFFU)
30775#define MED_HDR10_HDR_PIPE1_CSCB_H10_H10_SHIFT (0U)
30776#define MED_HDR10_HDR_PIPE1_CSCB_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H10_H10_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H10_H10_MASK)
30777/*! @} */
30778
30779/*! @name HDR_PIPE1_CSCB_H20 - Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient */
30780/*! @{ */
30781#define MED_HDR10_HDR_PIPE1_CSCB_H20_H20_MASK (0xFFFFU)
30782#define MED_HDR10_HDR_PIPE1_CSCB_H20_H20_SHIFT (0U)
30783#define MED_HDR10_HDR_PIPE1_CSCB_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H20_H20_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H20_H20_MASK)
30784/*! @} */
30785
30786/*! @name HDR_PIPE1_CSCB_H01 - Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient */
30787/*! @{ */
30788#define MED_HDR10_HDR_PIPE1_CSCB_H01_H01_MASK (0xFFFFU)
30789#define MED_HDR10_HDR_PIPE1_CSCB_H01_H01_SHIFT (0U)
30790#define MED_HDR10_HDR_PIPE1_CSCB_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H01_H01_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H01_H01_MASK)
30791/*! @} */
30792
30793/*! @name HDR_PIPE1_CSCB_H11 - Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient */
30794/*! @{ */
30795#define MED_HDR10_HDR_PIPE1_CSCB_H11_H11_MASK (0xFFFFU)
30796#define MED_HDR10_HDR_PIPE1_CSCB_H11_H11_SHIFT (0U)
30797#define MED_HDR10_HDR_PIPE1_CSCB_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H11_H11_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H11_H11_MASK)
30798/*! @} */
30799
30800/*! @name HDR_PIPE1_CSCB_H21 - Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient */
30801/*! @{ */
30802#define MED_HDR10_HDR_PIPE1_CSCB_H21_H21_MASK (0xFFFFU)
30803#define MED_HDR10_HDR_PIPE1_CSCB_H21_H21_SHIFT (0U)
30804#define MED_HDR10_HDR_PIPE1_CSCB_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H21_H21_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H21_H21_MASK)
30805/*! @} */
30806
30807/*! @name HDR_PIPE1_CSCB_H02 - Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient */
30808/*! @{ */
30809#define MED_HDR10_HDR_PIPE1_CSCB_H02_H02_MASK (0xFFFFU)
30810#define MED_HDR10_HDR_PIPE1_CSCB_H02_H02_SHIFT (0U)
30811#define MED_HDR10_HDR_PIPE1_CSCB_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H02_H02_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H02_H02_MASK)
30812/*! @} */
30813
30814/*! @name HDR_PIPE1_CSCB_H12 - Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient */
30815/*! @{ */
30816#define MED_HDR10_HDR_PIPE1_CSCB_H12_H12_MASK (0xFFFFU)
30817#define MED_HDR10_HDR_PIPE1_CSCB_H12_H12_SHIFT (0U)
30818#define MED_HDR10_HDR_PIPE1_CSCB_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H12_H12_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H12_H12_MASK)
30819/*! @} */
30820
30821/*! @name HDR_PIPE1_CSCB_H22 - Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient */
30822/*! @{ */
30823#define MED_HDR10_HDR_PIPE1_CSCB_H22_H22_MASK (0xFFFFU)
30824#define MED_HDR10_HDR_PIPE1_CSCB_H22_H22_SHIFT (0U)
30825#define MED_HDR10_HDR_PIPE1_CSCB_H22_H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H22_H22_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H22_H22_MASK)
30826/*! @} */
30827
30828/*! @name HDR_PIPE1_CSCB_IO_0 - Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset */
30829/*! @{ */
30830#define MED_HDR10_HDR_PIPE1_CSCB_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFFU)
30831#define MED_HDR10_HDR_PIPE1_CSCB_IO_0_COMPO_PRE_OFFSET_SHIFT (0U)
30832#define MED_HDR10_HDR_PIPE1_CSCB_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_0_COMPO_PRE_OFFSET_MASK)
30833/*! @} */
30834
30835/*! @name HDR_PIPE1_CSCB_IO_1 - Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset */
30836/*! @{ */
30837#define MED_HDR10_HDR_PIPE1_CSCB_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFFU)
30838#define MED_HDR10_HDR_PIPE1_CSCB_IO_1_COMP1_PRE_OFFSET_SHIFT (0U)
30839#define MED_HDR10_HDR_PIPE1_CSCB_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_1_COMP1_PRE_OFFSET_MASK)
30840/*! @} */
30841
30842/*! @name HDR_PIPE1_CSCB_IO_2 - Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset */
30843/*! @{ */
30844#define MED_HDR10_HDR_PIPE1_CSCB_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFFU)
30845#define MED_HDR10_HDR_PIPE1_CSCB_IO_2_COMP2_PRE_OFFSET_SHIFT (0U)
30846#define MED_HDR10_HDR_PIPE1_CSCB_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_2_COMP2_PRE_OFFSET_MASK)
30847/*! @} */
30848
30849/*! @name HDR_PIPE1_CSCB_IO_MIN_0 - Pipe1 Colorspace Converter B (CSCB) component 0 clip min. */
30850/*! @{ */
30851#define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFFU)
30852#define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_0_COMP0_CLIP_MIN_SHIFT (0U)
30853#define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_0_COMP0_CLIP_MIN_MASK)
30854/*! @} */
30855
30856/*! @name HDR_PIPE1_CSCB_IO_MIN_1 - Pipe1 Colorspace Converter B (CSCB) component 1 clip min. */
30857/*! @{ */
30858#define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFFU)
30859#define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_1_COMP1_CLIP_MIN_SHIFT (0U)
30860#define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_1_COMP1_CLIP_MIN_MASK)
30861/*! @} */
30862
30863/*! @name HDR_PIPE1_CSCB_IO_MIN_2 - Pipe1 Colorspace Converter B (CSCB) component 2 clip min. */
30864/*! @{ */
30865#define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFFU)
30866#define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_2_COMP2_CLIP_MIN_SHIFT (0U)
30867#define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_2_COMP2_CLIP_MIN_MASK)
30868/*! @} */
30869
30870/*! @name HDR_PIPE1_CSCB_IO_MAX_0 - Pipe1 Colorspace Converter B (CSCB) component 0 clip max value. */
30871/*! @{ */
30872#define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFFU)
30873#define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_0_COMP0_CLIP_MAX_SHIFT (0U)
30874#define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_0_COMP0_CLIP_MAX_MASK)
30875/*! @} */
30876
30877/*! @name HDR_PIPE1_CSCB_IO_MAX_1 - Pipe1 Colorspace Converter B (CSCB) component 1 clip max value. */
30878/*! @{ */
30879#define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFFU)
30880#define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_1_COMP1_CLIP_MAX_SHIFT (0U)
30881#define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_1_COMP1_CLIP_MAX_MASK)
30882/*! @} */
30883
30884/*! @name HDR_PIPE1_CSCB_IO_MAX_2 - Pipe1 Colorspace Converter B (CSCB) component 2 clip max value. */
30885/*! @{ */
30886#define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFFU)
30887#define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_2_COMP2_CLIP_MAX_SHIFT (0U)
30888#define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_2_COMP2_CLIP_MAX_MASK)
30889/*! @} */
30890
30891/*! @name HDR_PIPE1_CSCB_NORM - Pipe1 Colorspace Converter B (CSCB) normalization factor */
30892/*! @{ */
30893#define MED_HDR10_HDR_PIPE1_CSCB_NORM_CSCB_NORM_MASK (0x1FU)
30894#define MED_HDR10_HDR_PIPE1_CSCB_NORM_CSCB_NORM_SHIFT (0U)
30895#define MED_HDR10_HDR_PIPE1_CSCB_NORM_CSCB_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_NORM_CSCB_NORM_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_NORM_CSCB_NORM_MASK)
30896/*! @} */
30897
30898/*! @name HDR_PIPE1_CSCB_OO_0 - Pipe1 Colorspace Converter B (CSCB): Post offset component 0 */
30899/*! @{ */
30900#define MED_HDR10_HDR_PIPE1_CSCB_OO_0_CSCB_OO_0_MASK (0x1FFFFFFFU)
30901#define MED_HDR10_HDR_PIPE1_CSCB_OO_0_CSCB_OO_0_SHIFT (0U)
30902#define MED_HDR10_HDR_PIPE1_CSCB_OO_0_CSCB_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OO_0_CSCB_OO_0_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OO_0_CSCB_OO_0_MASK)
30903/*! @} */
30904
30905/*! @name HDR_PIPE1_CSCB_OO_1 - Pipe1 Colorspace Converter B (CSCB): Post offset component 1 */
30906/*! @{ */
30907#define MED_HDR10_HDR_PIPE1_CSCB_OO_1_CSCB_OO_1_MASK (0x1FFFFFFFU)
30908#define MED_HDR10_HDR_PIPE1_CSCB_OO_1_CSCB_OO_1_SHIFT (0U)
30909#define MED_HDR10_HDR_PIPE1_CSCB_OO_1_CSCB_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OO_1_CSCB_OO_1_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OO_1_CSCB_OO_1_MASK)
30910/*! @} */
30911
30912/*! @name HDR_PIPE1_CSCB_OO_2 - Pipe1 Colorspace Converter B (CSCB): Post offset component 2 */
30913/*! @{ */
30914#define MED_HDR10_HDR_PIPE1_CSCB_OO_2_CSCB_OO_2_MASK (0x1FFFFFFFU)
30915#define MED_HDR10_HDR_PIPE1_CSCB_OO_2_CSCB_OO_2_SHIFT (0U)
30916#define MED_HDR10_HDR_PIPE1_CSCB_OO_2_CSCB_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OO_2_CSCB_OO_2_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OO_2_CSCB_OO_2_MASK)
30917/*! @} */
30918
30919/*! @name HDR_PIPE1_CSCB_OMIN_0 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0 */
30920/*! @{ */
30921#define MED_HDR10_HDR_PIPE1_CSCB_OMIN_0_POST_OFF_MIN_MASK (0xFFFFFFFU)
30922#define MED_HDR10_HDR_PIPE1_CSCB_OMIN_0_POST_OFF_MIN_SHIFT (0U)
30923#define MED_HDR10_HDR_PIPE1_CSCB_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OMIN_0_POST_OFF_MIN_MASK)
30924/*! @} */
30925
30926/*! @name HDR_PIPE1_CSCB_OMIN_1 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1 */
30927/*! @{ */
30928#define MED_HDR10_HDR_PIPE1_CSCB_OMIN_1_POST_OFF_MIN_MASK (0xFFFFFFFU)
30929#define MED_HDR10_HDR_PIPE1_CSCB_OMIN_1_POST_OFF_MIN_SHIFT (0U)
30930#define MED_HDR10_HDR_PIPE1_CSCB_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OMIN_1_POST_OFF_MIN_MASK)
30931/*! @} */
30932
30933/*! @name HDR_PIPE1_CSCB_OMIN_2 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2 */
30934/*! @{ */
30935#define MED_HDR10_HDR_PIPE1_CSCB_OMIN_2_POST_OFF_MIN_MASK (0xFFFFFFFU)
30936#define MED_HDR10_HDR_PIPE1_CSCB_OMIN_2_POST_OFF_MIN_SHIFT (0U)
30937#define MED_HDR10_HDR_PIPE1_CSCB_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OMIN_2_POST_OFF_MIN_MASK)
30938/*! @} */
30939
30940/*! @name HDR_PIPE1_CSCB_OMAX_0 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0 */
30941/*! @{ */
30942#define MED_HDR10_HDR_PIPE1_CSCB_OMAX_0_POST_OFF_MAX_MASK (0xFFFFFFFU)
30943#define MED_HDR10_HDR_PIPE1_CSCB_OMAX_0_POST_OFF_MAX_SHIFT (0U)
30944#define MED_HDR10_HDR_PIPE1_CSCB_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OMAX_0_POST_OFF_MAX_MASK)
30945/*! @} */
30946
30947/*! @name HDR_PIPE1_CSCB_OMAX_1 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1 */
30948/*! @{ */
30949#define MED_HDR10_HDR_PIPE1_CSCB_OMAX_1_POST_OFF_MAX_MASK (0x3FFU)
30950#define MED_HDR10_HDR_PIPE1_CSCB_OMAX_1_POST_OFF_MAX_SHIFT (0U)
30951#define MED_HDR10_HDR_PIPE1_CSCB_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OMAX_1_POST_OFF_MAX_MASK)
30952/*! @} */
30953
30954/*! @name HDR_PIPE1_CSCB_OMAX_2 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2 */
30955/*! @{ */
30956#define MED_HDR10_HDR_PIPE1_CSCB_OMAX_2_POST_OFF_MAX_MASK (0xFFFFFFFU)
30957#define MED_HDR10_HDR_PIPE1_CSCB_OMAX_2_POST_OFF_MAX_SHIFT (0U)
30958#define MED_HDR10_HDR_PIPE1_CSCB_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OMAX_2_POST_OFF_MAX_MASK)
30959/*! @} */
30960
30961/*! @name HDR_PIPE1_FL2FX - Pipe1 floating point to fixed point control */
30962/*! @{ */
30963#define MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_MASK (0x1U)
30964#define MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_SHIFT (0U)
30965#define MED_HDR10_HDR_PIPE1_FL2FX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_MASK)
30966#define MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_FOR_ALL_PELS_MASK (0x2U)
30967#define MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_FOR_ALL_PELS_SHIFT (1U)
30968#define MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_FOR_ALL_PELS_MASK)
30969/*! @} */
30970
30971/*! @name PIPE2_A0_LUT - A0 component Look-Up-Table. (LUT) */
30972/*! @{ */
30973#define MED_HDR10_PIPE2_A0_LUT_PIPE2_A0_LUT_MASK (0x3FFFU)
30974#define MED_HDR10_PIPE2_A0_LUT_PIPE2_A0_LUT_SHIFT (0U)
30975#define MED_HDR10_PIPE2_A0_LUT_PIPE2_A0_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE2_A0_LUT_PIPE2_A0_LUT_SHIFT)) & MED_HDR10_PIPE2_A0_LUT_PIPE2_A0_LUT_MASK)
30976/*! @} */
30977
30978/*! @name PIPE2_A1_LUT - A1 component Look-Up-Table. (LUT) */
30979/*! @{ */
30980#define MED_HDR10_PIPE2_A1_LUT_PIPE2_A1_LUT_MASK (0x3FFFU)
30981#define MED_HDR10_PIPE2_A1_LUT_PIPE2_A1_LUT_SHIFT (0U)
30982#define MED_HDR10_PIPE2_A1_LUT_PIPE2_A1_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE2_A1_LUT_PIPE2_A1_LUT_SHIFT)) & MED_HDR10_PIPE2_A1_LUT_PIPE2_A1_LUT_MASK)
30983/*! @} */
30984
30985/*! @name PIPE2_A2_LUT - A2 component Look-Up-Table. (LUT) */
30986/*! @{ */
30987#define MED_HDR10_PIPE2_A2_LUT_PIPE2_A2_LUT_MASK (0x3FFFU)
30988#define MED_HDR10_PIPE2_A2_LUT_PIPE2_A2_LUT_SHIFT (0U)
30989#define MED_HDR10_PIPE2_A2_LUT_PIPE2_A2_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE2_A2_LUT_PIPE2_A2_LUT_SHIFT)) & MED_HDR10_PIPE2_A2_LUT_PIPE2_A2_LUT_MASK)
30990/*! @} */
30991
30992/*! @name HDR_PIPE2_CSCA_CONTROL_REG - Pipe1 Colorspace Converter A control. */
30993/*! @{ */
30994#define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_MASK (0x1U)
30995#define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_SHIFT (0U)
30996#define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_MASK)
30997#define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U)
30998#define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U)
30999#define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK)
31000#define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_BYPASS_MASK (0x8000U)
31001#define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_BYPASS_SHIFT (15U)
31002#define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_BYPASS_MASK)
31003/*! @} */
31004
31005/*! @name HDR_PIPE2_CSCA_H00 - Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient */
31006/*! @{ */
31007#define MED_HDR10_HDR_PIPE2_CSCA_H00_H00_MASK (0xFFFFU)
31008#define MED_HDR10_HDR_PIPE2_CSCA_H00_H00_SHIFT (0U)
31009#define MED_HDR10_HDR_PIPE2_CSCA_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H00_H00_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H00_H00_MASK)
31010/*! @} */
31011
31012/*! @name HDR_PIPE2_CSCA_H10 - Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient */
31013/*! @{ */
31014#define MED_HDR10_HDR_PIPE2_CSCA_H10_H10_MASK (0xFFFFU)
31015#define MED_HDR10_HDR_PIPE2_CSCA_H10_H10_SHIFT (0U)
31016#define MED_HDR10_HDR_PIPE2_CSCA_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H10_H10_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H10_H10_MASK)
31017/*! @} */
31018
31019/*! @name HDR_PIPE2_CSCA_H20 - Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient */
31020/*! @{ */
31021#define MED_HDR10_HDR_PIPE2_CSCA_H20_H20_MASK (0xFFFFU)
31022#define MED_HDR10_HDR_PIPE2_CSCA_H20_H20_SHIFT (0U)
31023#define MED_HDR10_HDR_PIPE2_CSCA_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H20_H20_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H20_H20_MASK)
31024/*! @} */
31025
31026/*! @name HDR_PIPE2_CSCA_H01 - Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient */
31027/*! @{ */
31028#define MED_HDR10_HDR_PIPE2_CSCA_H01_H01_MASK (0xFFFFU)
31029#define MED_HDR10_HDR_PIPE2_CSCA_H01_H01_SHIFT (0U)
31030#define MED_HDR10_HDR_PIPE2_CSCA_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H01_H01_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H01_H01_MASK)
31031/*! @} */
31032
31033/*! @name HDR_PIPE2_CSCA_H11 - Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient */
31034/*! @{ */
31035#define MED_HDR10_HDR_PIPE2_CSCA_H11_H11_MASK (0xFFFFU)
31036#define MED_HDR10_HDR_PIPE2_CSCA_H11_H11_SHIFT (0U)
31037#define MED_HDR10_HDR_PIPE2_CSCA_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H11_H11_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H11_H11_MASK)
31038/*! @} */
31039
31040/*! @name HDR_PIPE2_CSCA_H21 - Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient */
31041/*! @{ */
31042#define MED_HDR10_HDR_PIPE2_CSCA_H21_H21_MASK (0xFFFFU)
31043#define MED_HDR10_HDR_PIPE2_CSCA_H21_H21_SHIFT (0U)
31044#define MED_HDR10_HDR_PIPE2_CSCA_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H21_H21_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H21_H21_MASK)
31045/*! @} */
31046
31047/*! @name HDR_PIPE2_CSCA_H02 - Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient */
31048/*! @{ */
31049#define MED_HDR10_HDR_PIPE2_CSCA_H02_H02_MASK (0xFFFFU)
31050#define MED_HDR10_HDR_PIPE2_CSCA_H02_H02_SHIFT (0U)
31051#define MED_HDR10_HDR_PIPE2_CSCA_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H02_H02_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H02_H02_MASK)
31052/*! @} */
31053
31054/*! @name HDR_PIPE2_CSCA_H12 - Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient */
31055/*! @{ */
31056#define MED_HDR10_HDR_PIPE2_CSCA_H12_H12_MASK (0xFFFFU)
31057#define MED_HDR10_HDR_PIPE2_CSCA_H12_H12_SHIFT (0U)
31058#define MED_HDR10_HDR_PIPE2_CSCA_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H12_H12_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H12_H12_MASK)
31059/*! @} */
31060
31061/*! @name HDR_PIPE2_CSCA_H22 - Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient */
31062/*! @{ */
31063#define MED_HDR10_HDR_PIPE2_CSCA_H22_H22_MASK (0xFFFFU)
31064#define MED_HDR10_HDR_PIPE2_CSCA_H22_H22_SHIFT (0U)
31065#define MED_HDR10_HDR_PIPE2_CSCA_H22_H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H22_H22_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H22_H22_MASK)
31066/*! @} */
31067
31068/*! @name HDR_PIPE2_CSCA_IO_0 - Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset */
31069/*! @{ */
31070#define MED_HDR10_HDR_PIPE2_CSCA_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFU)
31071#define MED_HDR10_HDR_PIPE2_CSCA_IO_0_COMPO_PRE_OFFSET_SHIFT (0U)
31072#define MED_HDR10_HDR_PIPE2_CSCA_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_0_COMPO_PRE_OFFSET_MASK)
31073/*! @} */
31074
31075/*! @name HDR_PIPE2_CSCA_IO_1 - Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset */
31076/*! @{ */
31077#define MED_HDR10_HDR_PIPE2_CSCA_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFU)
31078#define MED_HDR10_HDR_PIPE2_CSCA_IO_1_COMP1_PRE_OFFSET_SHIFT (0U)
31079#define MED_HDR10_HDR_PIPE2_CSCA_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_1_COMP1_PRE_OFFSET_MASK)
31080/*! @} */
31081
31082/*! @name HDR_PIPE2_CSCA_IO_2 - Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset */
31083/*! @{ */
31084#define MED_HDR10_HDR_PIPE2_CSCA_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFU)
31085#define MED_HDR10_HDR_PIPE2_CSCA_IO_2_COMP2_PRE_OFFSET_SHIFT (0U)
31086#define MED_HDR10_HDR_PIPE2_CSCA_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_2_COMP2_PRE_OFFSET_MASK)
31087/*! @} */
31088
31089/*! @name HDR_PIPE2_CSCA_IO_MIN_0 - Pipe1 Colorspace Converter A (CSCA) component 0 clip min. */
31090/*! @{ */
31091#define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFU)
31092#define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_0_COMP0_CLIP_MIN_SHIFT (0U)
31093#define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_0_COMP0_CLIP_MIN_MASK)
31094/*! @} */
31095
31096/*! @name HDR_PIPE2_CSCA_IO_MIN_1 - Pipe1 Colorspace Converter A (CSCA) component 1 clip min. */
31097/*! @{ */
31098#define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFU)
31099#define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_1_COMP1_CLIP_MIN_SHIFT (0U)
31100#define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_1_COMP1_CLIP_MIN_MASK)
31101/*! @} */
31102
31103/*! @name HDR_PIPE2_CSCA_IO_MIN_2 - Pipe1 Colorspace Converter A (CSCA) component 2 clip min. */
31104/*! @{ */
31105#define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFU)
31106#define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_2_COMP2_CLIP_MIN_SHIFT (0U)
31107#define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_2_COMP2_CLIP_MIN_MASK)
31108/*! @} */
31109
31110/*! @name HDR_PIPE2_CSCA_IO_MAX_0 - Pipe1 Colorspace Converter A (CSCA) component 0 clip max value. */
31111/*! @{ */
31112#define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFU)
31113#define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_0_COMP0_CLIP_MAX_SHIFT (0U)
31114#define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_0_COMP0_CLIP_MAX_MASK)
31115/*! @} */
31116
31117/*! @name HDR_PIPE2_CSCA_IO_MAX_1 - Pipe1 Colorspace Converter A (CSCA) component 1 clip max value. */
31118/*! @{ */
31119#define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFU)
31120#define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_1_COMP1_CLIP_MAX_SHIFT (0U)
31121#define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_1_COMP1_CLIP_MAX_MASK)
31122/*! @} */
31123
31124/*! @name HDR_PIPE2_CSCA_IO_MAX_2 - Pipe1 Colorspace Converter A (CSCA) component 2 clip max value. */
31125/*! @{ */
31126#define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFU)
31127#define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_2_COMP2_CLIP_MAX_SHIFT (0U)
31128#define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_2_COMP2_CLIP_MAX_MASK)
31129/*! @} */
31130
31131/*! @name HDR_PIPE2_CSCA_NORM - Pipe1 Colorspace Converter A (CSCA) normalization factor */
31132/*! @{ */
31133#define MED_HDR10_HDR_PIPE2_CSCA_NORM_CSCA_NORM_MASK (0x1FU)
31134#define MED_HDR10_HDR_PIPE2_CSCA_NORM_CSCA_NORM_SHIFT (0U)
31135#define MED_HDR10_HDR_PIPE2_CSCA_NORM_CSCA_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_NORM_CSCA_NORM_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_NORM_CSCA_NORM_MASK)
31136/*! @} */
31137
31138/*! @name HDR_PIPE2_CSCA_OO_0 - Pipe1 Colorspace Converter A (CSCA): Post offset component 0 */
31139/*! @{ */
31140#define MED_HDR10_HDR_PIPE2_CSCA_OO_0_CSCA_OO_0_MASK (0xFFFFFFFU)
31141#define MED_HDR10_HDR_PIPE2_CSCA_OO_0_CSCA_OO_0_SHIFT (0U)
31142#define MED_HDR10_HDR_PIPE2_CSCA_OO_0_CSCA_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OO_0_CSCA_OO_0_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OO_0_CSCA_OO_0_MASK)
31143/*! @} */
31144
31145/*! @name HDR_PIPE2_CSCA_OO_1 - Pipe1 Colorspace Converter A (CSCA): Post offset component 1 */
31146/*! @{ */
31147#define MED_HDR10_HDR_PIPE2_CSCA_OO_1_CSCA_OO_1_MASK (0xFFFFFFFU)
31148#define MED_HDR10_HDR_PIPE2_CSCA_OO_1_CSCA_OO_1_SHIFT (0U)
31149#define MED_HDR10_HDR_PIPE2_CSCA_OO_1_CSCA_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OO_1_CSCA_OO_1_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OO_1_CSCA_OO_1_MASK)
31150/*! @} */
31151
31152/*! @name HDR_PIPE2_CSCA_OO_2 - Pipe1 Colorspace Converter A (CSCA): Post offset component 2 */
31153/*! @{ */
31154#define MED_HDR10_HDR_PIPE2_CSCA_OO_2_CSCA_OO_2_MASK (0xFFFFFFFU)
31155#define MED_HDR10_HDR_PIPE2_CSCA_OO_2_CSCA_OO_2_SHIFT (0U)
31156#define MED_HDR10_HDR_PIPE2_CSCA_OO_2_CSCA_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OO_2_CSCA_OO_2_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OO_2_CSCA_OO_2_MASK)
31157/*! @} */
31158
31159/*! @name HDR_PIPE2_CSCA_OMIN_0 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0 */
31160/*! @{ */
31161#define MED_HDR10_HDR_PIPE2_CSCA_OMIN_0_POST_OFF_MIN_MASK (0x3FFU)
31162#define MED_HDR10_HDR_PIPE2_CSCA_OMIN_0_POST_OFF_MIN_SHIFT (0U)
31163#define MED_HDR10_HDR_PIPE2_CSCA_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OMIN_0_POST_OFF_MIN_MASK)
31164/*! @} */
31165
31166/*! @name HDR_PIPE2_CSCA_OMIN_1 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1 */
31167/*! @{ */
31168#define MED_HDR10_HDR_PIPE2_CSCA_OMIN_1_POST_OFF_MIN_MASK (0x3FFU)
31169#define MED_HDR10_HDR_PIPE2_CSCA_OMIN_1_POST_OFF_MIN_SHIFT (0U)
31170#define MED_HDR10_HDR_PIPE2_CSCA_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OMIN_1_POST_OFF_MIN_MASK)
31171/*! @} */
31172
31173/*! @name HDR_PIPE2_CSCA_OMIN_2 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2 */
31174/*! @{ */
31175#define MED_HDR10_HDR_PIPE2_CSCA_OMIN_2_POST_OFF_MIN_MASK (0x3FFU)
31176#define MED_HDR10_HDR_PIPE2_CSCA_OMIN_2_POST_OFF_MIN_SHIFT (0U)
31177#define MED_HDR10_HDR_PIPE2_CSCA_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OMIN_2_POST_OFF_MIN_MASK)
31178/*! @} */
31179
31180/*! @name HDR_PIPE2_CSCA_OMAX_0 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0 */
31181/*! @{ */
31182#define MED_HDR10_HDR_PIPE2_CSCA_OMAX_0_POST_OFF_MAX_MASK (0x3FFU)
31183#define MED_HDR10_HDR_PIPE2_CSCA_OMAX_0_POST_OFF_MAX_SHIFT (0U)
31184#define MED_HDR10_HDR_PIPE2_CSCA_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OMAX_0_POST_OFF_MAX_MASK)
31185/*! @} */
31186
31187/*! @name HDR_PIPE2_CSCA_OMAX_1 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1 */
31188/*! @{ */
31189#define MED_HDR10_HDR_PIPE2_CSCA_OMAX_1_POST_OFF_MAX_MASK (0x3FFU)
31190#define MED_HDR10_HDR_PIPE2_CSCA_OMAX_1_POST_OFF_MAX_SHIFT (0U)
31191#define MED_HDR10_HDR_PIPE2_CSCA_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OMAX_1_POST_OFF_MAX_MASK)
31192/*! @} */
31193
31194/*! @name HDR_PIPE2_CSCA_OMAX_2 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2 */
31195/*! @{ */
31196#define MED_HDR10_HDR_PIPE2_CSCA_OMAX_2_POST_OFF_MAX_MASK (0x3FFU)
31197#define MED_HDR10_HDR_PIPE2_CSCA_OMAX_2_POST_OFF_MAX_SHIFT (0U)
31198#define MED_HDR10_HDR_PIPE2_CSCA_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OMAX_2_POST_OFF_MAX_MASK)
31199/*! @} */
31200
31201/*! @name HDR_PIPE2_LUT_CONTROL_REG - Pipe1 LUT control register */
31202/*! @{ */
31203#define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_MASK (0x1U)
31204#define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_SHIFT (0U)
31205#define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_MASK)
31206#define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U)
31207#define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U)
31208#define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK)
31209#define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_BYPASS_MASK (0x8000U)
31210#define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_BYPASS_SHIFT (15U)
31211#define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_BYPASS_MASK)
31212/*! @} */
31213
31214/*! @name HDR_PIPE2_CSCB_CONTROL_REG - Pipe1 Colorspace Converter B control. */
31215/*! @{ */
31216#define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_MASK (0x1U)
31217#define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_SHIFT (0U)
31218#define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_MASK)
31219#define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U)
31220#define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U)
31221#define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK)
31222#define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_BYPASS_MASK (0x8000U)
31223#define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_BYPASS_SHIFT (15U)
31224#define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_BYPASS_MASK)
31225/*! @} */
31226
31227/*! @name HDR_PIPE2_CSCB_H00 - Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient */
31228/*! @{ */
31229#define MED_HDR10_HDR_PIPE2_CSCB_H00_H00_MASK (0xFFFFU)
31230#define MED_HDR10_HDR_PIPE2_CSCB_H00_H00_SHIFT (0U)
31231#define MED_HDR10_HDR_PIPE2_CSCB_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H00_H00_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H00_H00_MASK)
31232/*! @} */
31233
31234/*! @name HDR_PIPE2_CSCB_H10 - Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient */
31235/*! @{ */
31236#define MED_HDR10_HDR_PIPE2_CSCB_H10_H10_MASK (0xFFFFU)
31237#define MED_HDR10_HDR_PIPE2_CSCB_H10_H10_SHIFT (0U)
31238#define MED_HDR10_HDR_PIPE2_CSCB_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H10_H10_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H10_H10_MASK)
31239/*! @} */
31240
31241/*! @name HDR_PIPE2_CSCB_H20 - Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient */
31242/*! @{ */
31243#define MED_HDR10_HDR_PIPE2_CSCB_H20_H20_MASK (0xFFFFU)
31244#define MED_HDR10_HDR_PIPE2_CSCB_H20_H20_SHIFT (0U)
31245#define MED_HDR10_HDR_PIPE2_CSCB_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H20_H20_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H20_H20_MASK)
31246/*! @} */
31247
31248/*! @name HDR_PIPE2_CSCB_H01 - Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient */
31249/*! @{ */
31250#define MED_HDR10_HDR_PIPE2_CSCB_H01_H01_MASK (0xFFFFU)
31251#define MED_HDR10_HDR_PIPE2_CSCB_H01_H01_SHIFT (0U)
31252#define MED_HDR10_HDR_PIPE2_CSCB_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H01_H01_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H01_H01_MASK)
31253/*! @} */
31254
31255/*! @name HDR_PIPE2_CSCB_H11 - Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient */
31256/*! @{ */
31257#define MED_HDR10_HDR_PIPE2_CSCB_H11_H11_MASK (0xFFFFU)
31258#define MED_HDR10_HDR_PIPE2_CSCB_H11_H11_SHIFT (0U)
31259#define MED_HDR10_HDR_PIPE2_CSCB_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H11_H11_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H11_H11_MASK)
31260/*! @} */
31261
31262/*! @name HDR_PIPE2_CSCB_H21 - Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient */
31263/*! @{ */
31264#define MED_HDR10_HDR_PIPE2_CSCB_H21_H21_MASK (0xFFFFU)
31265#define MED_HDR10_HDR_PIPE2_CSCB_H21_H21_SHIFT (0U)
31266#define MED_HDR10_HDR_PIPE2_CSCB_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H21_H21_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H21_H21_MASK)
31267/*! @} */
31268
31269/*! @name HDR_PIPE2_CSCB_H02 - Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient */
31270/*! @{ */
31271#define MED_HDR10_HDR_PIPE2_CSCB_H02_H02_MASK (0xFFFFU)
31272#define MED_HDR10_HDR_PIPE2_CSCB_H02_H02_SHIFT (0U)
31273#define MED_HDR10_HDR_PIPE2_CSCB_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H02_H02_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H02_H02_MASK)
31274/*! @} */
31275
31276/*! @name HDR_PIPE2_CSCB_H12 - Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient */
31277/*! @{ */
31278#define MED_HDR10_HDR_PIPE2_CSCB_H12_H12_MASK (0xFFFFU)
31279#define MED_HDR10_HDR_PIPE2_CSCB_H12_H12_SHIFT (0U)
31280#define MED_HDR10_HDR_PIPE2_CSCB_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H12_H12_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H12_H12_MASK)
31281/*! @} */
31282
31283/*! @name HDR_PIPE2_CSCB_H22 - Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient */
31284/*! @{ */
31285#define MED_HDR10_HDR_PIPE2_CSCB_H22_H22_MASK (0xFFFFU)
31286#define MED_HDR10_HDR_PIPE2_CSCB_H22_H22_SHIFT (0U)
31287#define MED_HDR10_HDR_PIPE2_CSCB_H22_H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H22_H22_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H22_H22_MASK)
31288/*! @} */
31289
31290/*! @name HDR_PIPE2_CSCB_IO_0 - Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset */
31291/*! @{ */
31292#define MED_HDR10_HDR_PIPE2_CSCB_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFFU)
31293#define MED_HDR10_HDR_PIPE2_CSCB_IO_0_COMPO_PRE_OFFSET_SHIFT (0U)
31294#define MED_HDR10_HDR_PIPE2_CSCB_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_0_COMPO_PRE_OFFSET_MASK)
31295/*! @} */
31296
31297/*! @name HDR_PIPE2_CSCB_IO_1 - Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset */
31298/*! @{ */
31299#define MED_HDR10_HDR_PIPE2_CSCB_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFFU)
31300#define MED_HDR10_HDR_PIPE2_CSCB_IO_1_COMP1_PRE_OFFSET_SHIFT (0U)
31301#define MED_HDR10_HDR_PIPE2_CSCB_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_1_COMP1_PRE_OFFSET_MASK)
31302/*! @} */
31303
31304/*! @name HDR_PIPE2_CSCB_IO_2 - Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset */
31305/*! @{ */
31306#define MED_HDR10_HDR_PIPE2_CSCB_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFFU)
31307#define MED_HDR10_HDR_PIPE2_CSCB_IO_2_COMP2_PRE_OFFSET_SHIFT (0U)
31308#define MED_HDR10_HDR_PIPE2_CSCB_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_2_COMP2_PRE_OFFSET_MASK)
31309/*! @} */
31310
31311/*! @name HDR_PIPE2_CSCB_IO_MIN_0 - Pipe1 Colorspace Converter B (CSCB) component 0 clip min. */
31312/*! @{ */
31313#define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFFU)
31314#define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_0_COMP0_CLIP_MIN_SHIFT (0U)
31315#define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_0_COMP0_CLIP_MIN_MASK)
31316/*! @} */
31317
31318/*! @name HDR_PIPE2_CSCB_IO_MIN_1 - Pipe1 Colorspace Converter B (CSCB) component 1 clip min. */
31319/*! @{ */
31320#define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFFU)
31321#define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_1_COMP1_CLIP_MIN_SHIFT (0U)
31322#define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_1_COMP1_CLIP_MIN_MASK)
31323/*! @} */
31324
31325/*! @name HDR_PIPE2_CSCB_IO_MIN_2 - Pipe1 Colorspace Converter B (CSCB) component 2 clip min. */
31326/*! @{ */
31327#define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFFU)
31328#define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_2_COMP2_CLIP_MIN_SHIFT (0U)
31329#define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_2_COMP2_CLIP_MIN_MASK)
31330/*! @} */
31331
31332/*! @name HDR_PIPE2_CSCB_IO_MAX_0 - Pipe1 Colorspace Converter B (CSCB) component 0 clip max value. */
31333/*! @{ */
31334#define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFFU)
31335#define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_0_COMP0_CLIP_MAX_SHIFT (0U)
31336#define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_0_COMP0_CLIP_MAX_MASK)
31337/*! @} */
31338
31339/*! @name HDR_PIPE2_CSCB_IO_MAX_1 - Pipe1 Colorspace Converter B (CSCB) component 1 clip max value. */
31340/*! @{ */
31341#define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFFU)
31342#define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_1_COMP1_CLIP_MAX_SHIFT (0U)
31343#define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_1_COMP1_CLIP_MAX_MASK)
31344/*! @} */
31345
31346/*! @name HDR_PIPE2_CSCB_IO_MAX_2 - Pipe1 Colorspace Converter B (CSCB) component 2 clip max value. */
31347/*! @{ */
31348#define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFFU)
31349#define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_2_COMP2_CLIP_MAX_SHIFT (0U)
31350#define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_2_COMP2_CLIP_MAX_MASK)
31351/*! @} */
31352
31353/*! @name HDR_PIPE2_CSCB_NORM - Pipe1 Colorspace Converter B (CSCB) normalization factor */
31354/*! @{ */
31355#define MED_HDR10_HDR_PIPE2_CSCB_NORM_CSCB_NORM_MASK (0x1FU)
31356#define MED_HDR10_HDR_PIPE2_CSCB_NORM_CSCB_NORM_SHIFT (0U)
31357#define MED_HDR10_HDR_PIPE2_CSCB_NORM_CSCB_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_NORM_CSCB_NORM_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_NORM_CSCB_NORM_MASK)
31358/*! @} */
31359
31360/*! @name HDR_PIPE2_CSCB_OO_0 - Pipe1 Colorspace Converter B (CSCB): Post offset component 0 */
31361/*! @{ */
31362#define MED_HDR10_HDR_PIPE2_CSCB_OO_0_CSCB_OO_0_MASK (0x1FFFFFFFU)
31363#define MED_HDR10_HDR_PIPE2_CSCB_OO_0_CSCB_OO_0_SHIFT (0U)
31364#define MED_HDR10_HDR_PIPE2_CSCB_OO_0_CSCB_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OO_0_CSCB_OO_0_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OO_0_CSCB_OO_0_MASK)
31365/*! @} */
31366
31367/*! @name HDR_PIPE2_CSCB_OO_1 - Pipe1 Colorspace Converter B (CSCB): Post offset component 1 */
31368/*! @{ */
31369#define MED_HDR10_HDR_PIPE2_CSCB_OO_1_CSCB_OO_1_MASK (0x1FFFFFFFU)
31370#define MED_HDR10_HDR_PIPE2_CSCB_OO_1_CSCB_OO_1_SHIFT (0U)
31371#define MED_HDR10_HDR_PIPE2_CSCB_OO_1_CSCB_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OO_1_CSCB_OO_1_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OO_1_CSCB_OO_1_MASK)
31372/*! @} */
31373
31374/*! @name HDR_PIPE2_CSCB_OO_2 - Pipe1 Colorspace Converter B (CSCB): Post offset component 2 */
31375/*! @{ */
31376#define MED_HDR10_HDR_PIPE2_CSCB_OO_2_CSCB_OO_2_MASK (0x1FFFFFFFU)
31377#define MED_HDR10_HDR_PIPE2_CSCB_OO_2_CSCB_OO_2_SHIFT (0U)
31378#define MED_HDR10_HDR_PIPE2_CSCB_OO_2_CSCB_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OO_2_CSCB_OO_2_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OO_2_CSCB_OO_2_MASK)
31379/*! @} */
31380
31381/*! @name HDR_PIPE2_CSCB_OMIN_0 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0 */
31382/*! @{ */
31383#define MED_HDR10_HDR_PIPE2_CSCB_OMIN_0_POST_OFF_MIN_MASK (0xFFFFFFFU)
31384#define MED_HDR10_HDR_PIPE2_CSCB_OMIN_0_POST_OFF_MIN_SHIFT (0U)
31385#define MED_HDR10_HDR_PIPE2_CSCB_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OMIN_0_POST_OFF_MIN_MASK)
31386/*! @} */
31387
31388/*! @name HDR_PIPE2_CSCB_OMIN_1 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1 */
31389/*! @{ */
31390#define MED_HDR10_HDR_PIPE2_CSCB_OMIN_1_POST_OFF_MIN_MASK (0xFFFFFFFU)
31391#define MED_HDR10_HDR_PIPE2_CSCB_OMIN_1_POST_OFF_MIN_SHIFT (0U)
31392#define MED_HDR10_HDR_PIPE2_CSCB_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OMIN_1_POST_OFF_MIN_MASK)
31393/*! @} */
31394
31395/*! @name HDR_PIPE2_CSCB_OMIN_2 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2 */
31396/*! @{ */
31397#define MED_HDR10_HDR_PIPE2_CSCB_OMIN_2_POST_OFF_MIN_MASK (0xFFFFFFFU)
31398#define MED_HDR10_HDR_PIPE2_CSCB_OMIN_2_POST_OFF_MIN_SHIFT (0U)
31399#define MED_HDR10_HDR_PIPE2_CSCB_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OMIN_2_POST_OFF_MIN_MASK)
31400/*! @} */
31401
31402/*! @name HDR_PIPE2_CSCB_OMAX_0 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0 */
31403/*! @{ */
31404#define MED_HDR10_HDR_PIPE2_CSCB_OMAX_0_POST_OFF_MAX_MASK (0xFFFFFFFU)
31405#define MED_HDR10_HDR_PIPE2_CSCB_OMAX_0_POST_OFF_MAX_SHIFT (0U)
31406#define MED_HDR10_HDR_PIPE2_CSCB_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OMAX_0_POST_OFF_MAX_MASK)
31407/*! @} */
31408
31409/*! @name HDR_PIPE2_CSCB_OMAX_1 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1 */
31410/*! @{ */
31411#define MED_HDR10_HDR_PIPE2_CSCB_OMAX_1_POST_OFF_MAX_MASK (0x3FFU)
31412#define MED_HDR10_HDR_PIPE2_CSCB_OMAX_1_POST_OFF_MAX_SHIFT (0U)
31413#define MED_HDR10_HDR_PIPE2_CSCB_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OMAX_1_POST_OFF_MAX_MASK)
31414/*! @} */
31415
31416/*! @name HDR_PIPE2_CSCB_OMAX_2 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2 */
31417/*! @{ */
31418#define MED_HDR10_HDR_PIPE2_CSCB_OMAX_2_POST_OFF_MAX_MASK (0xFFFFFFFU)
31419#define MED_HDR10_HDR_PIPE2_CSCB_OMAX_2_POST_OFF_MAX_SHIFT (0U)
31420#define MED_HDR10_HDR_PIPE2_CSCB_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OMAX_2_POST_OFF_MAX_MASK)
31421/*! @} */
31422
31423/*! @name HDR_PIPE2_FL2FX - Pipe1 floating point to fixed point control */
31424/*! @{ */
31425#define MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_MASK (0x1U)
31426#define MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_SHIFT (0U)
31427#define MED_HDR10_HDR_PIPE2_FL2FX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_MASK)
31428#define MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_FOR_ALL_PELS_MASK (0x2U)
31429#define MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_FOR_ALL_PELS_SHIFT (1U)
31430#define MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_FOR_ALL_PELS_MASK)
31431/*! @} */
31432
31433/*! @name PIPE3_A0_LUT - A0 component Look-Up-Table. (LUT) */
31434/*! @{ */
31435#define MED_HDR10_PIPE3_A0_LUT_PIPE3_A0_LUT_MASK (0x3FFFU)
31436#define MED_HDR10_PIPE3_A0_LUT_PIPE3_A0_LUT_SHIFT (0U)
31437#define MED_HDR10_PIPE3_A0_LUT_PIPE3_A0_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE3_A0_LUT_PIPE3_A0_LUT_SHIFT)) & MED_HDR10_PIPE3_A0_LUT_PIPE3_A0_LUT_MASK)
31438/*! @} */
31439
31440/*! @name PIPE3_A1_LUT - A1 component Look-Up-Table. (LUT) */
31441/*! @{ */
31442#define MED_HDR10_PIPE3_A1_LUT_PIPE3_A1_LUT_MASK (0x3FFFU)
31443#define MED_HDR10_PIPE3_A1_LUT_PIPE3_A1_LUT_SHIFT (0U)
31444#define MED_HDR10_PIPE3_A1_LUT_PIPE3_A1_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE3_A1_LUT_PIPE3_A1_LUT_SHIFT)) & MED_HDR10_PIPE3_A1_LUT_PIPE3_A1_LUT_MASK)
31445/*! @} */
31446
31447/*! @name PIPE3_A2_LUT - A2 component Look-Up-Table. (LUT) */
31448/*! @{ */
31449#define MED_HDR10_PIPE3_A2_LUT_PIPE3_A2_LUT_MASK (0x3FFFU)
31450#define MED_HDR10_PIPE3_A2_LUT_PIPE3_A2_LUT_SHIFT (0U)
31451#define MED_HDR10_PIPE3_A2_LUT_PIPE3_A2_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE3_A2_LUT_PIPE3_A2_LUT_SHIFT)) & MED_HDR10_PIPE3_A2_LUT_PIPE3_A2_LUT_MASK)
31452/*! @} */
31453
31454/*! @name HDR_PIPE3_CSCA_CONTROL_REG - Pipe1 Colorspace Converter A control. */
31455/*! @{ */
31456#define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_MASK (0x1U)
31457#define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_SHIFT (0U)
31458#define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_MASK)
31459#define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U)
31460#define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U)
31461#define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK)
31462#define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_BYPASS_MASK (0x8000U)
31463#define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_BYPASS_SHIFT (15U)
31464#define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_BYPASS_MASK)
31465/*! @} */
31466
31467/*! @name HDR_PIPE3_CSCA_H00 - Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient */
31468/*! @{ */
31469#define MED_HDR10_HDR_PIPE3_CSCA_H00_H00_MASK (0xFFFFU)
31470#define MED_HDR10_HDR_PIPE3_CSCA_H00_H00_SHIFT (0U)
31471#define MED_HDR10_HDR_PIPE3_CSCA_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H00_H00_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H00_H00_MASK)
31472/*! @} */
31473
31474/*! @name HDR_PIPE3_CSCA_H10 - Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient */
31475/*! @{ */
31476#define MED_HDR10_HDR_PIPE3_CSCA_H10_H10_MASK (0xFFFFU)
31477#define MED_HDR10_HDR_PIPE3_CSCA_H10_H10_SHIFT (0U)
31478#define MED_HDR10_HDR_PIPE3_CSCA_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H10_H10_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H10_H10_MASK)
31479/*! @} */
31480
31481/*! @name HDR_PIPE3_CSCA_H20 - Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient */
31482/*! @{ */
31483#define MED_HDR10_HDR_PIPE3_CSCA_H20_H20_MASK (0xFFFFU)
31484#define MED_HDR10_HDR_PIPE3_CSCA_H20_H20_SHIFT (0U)
31485#define MED_HDR10_HDR_PIPE3_CSCA_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H20_H20_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H20_H20_MASK)
31486/*! @} */
31487
31488/*! @name HDR_PIPE3_CSCA_H01 - Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient */
31489/*! @{ */
31490#define MED_HDR10_HDR_PIPE3_CSCA_H01_H01_MASK (0xFFFFU)
31491#define MED_HDR10_HDR_PIPE3_CSCA_H01_H01_SHIFT (0U)
31492#define MED_HDR10_HDR_PIPE3_CSCA_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H01_H01_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H01_H01_MASK)
31493/*! @} */
31494
31495/*! @name HDR_PIPE3_CSCA_H11 - Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient */
31496/*! @{ */
31497#define MED_HDR10_HDR_PIPE3_CSCA_H11_H11_MASK (0xFFFFU)
31498#define MED_HDR10_HDR_PIPE3_CSCA_H11_H11_SHIFT (0U)
31499#define MED_HDR10_HDR_PIPE3_CSCA_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H11_H11_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H11_H11_MASK)
31500/*! @} */
31501
31502/*! @name HDR_PIPE3_CSCA_H21 - Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient */
31503/*! @{ */
31504#define MED_HDR10_HDR_PIPE3_CSCA_H21_H21_MASK (0xFFFFU)
31505#define MED_HDR10_HDR_PIPE3_CSCA_H21_H21_SHIFT (0U)
31506#define MED_HDR10_HDR_PIPE3_CSCA_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H21_H21_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H21_H21_MASK)
31507/*! @} */
31508
31509/*! @name HDR_PIPE3_CSCA_H02 - Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient */
31510/*! @{ */
31511#define MED_HDR10_HDR_PIPE3_CSCA_H02_H02_MASK (0xFFFFU)
31512#define MED_HDR10_HDR_PIPE3_CSCA_H02_H02_SHIFT (0U)
31513#define MED_HDR10_HDR_PIPE3_CSCA_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H02_H02_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H02_H02_MASK)
31514/*! @} */
31515
31516/*! @name HDR_PIPE3_CSCA_H12 - Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient */
31517/*! @{ */
31518#define MED_HDR10_HDR_PIPE3_CSCA_H12_H12_MASK (0xFFFFU)
31519#define MED_HDR10_HDR_PIPE3_CSCA_H12_H12_SHIFT (0U)
31520#define MED_HDR10_HDR_PIPE3_CSCA_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H12_H12_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H12_H12_MASK)
31521/*! @} */
31522
31523/*! @name HDR_PIPE3_CSCA_H22 - Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient */
31524/*! @{ */
31525#define MED_HDR10_HDR_PIPE3_CSCA_H22_H22_MASK (0xFFFFU)
31526#define MED_HDR10_HDR_PIPE3_CSCA_H22_H22_SHIFT (0U)
31527#define MED_HDR10_HDR_PIPE3_CSCA_H22_H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H22_H22_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H22_H22_MASK)
31528/*! @} */
31529
31530/*! @name HDR_PIPE3_CSCA_IO_0 - Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset */
31531/*! @{ */
31532#define MED_HDR10_HDR_PIPE3_CSCA_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFU)
31533#define MED_HDR10_HDR_PIPE3_CSCA_IO_0_COMPO_PRE_OFFSET_SHIFT (0U)
31534#define MED_HDR10_HDR_PIPE3_CSCA_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_0_COMPO_PRE_OFFSET_MASK)
31535/*! @} */
31536
31537/*! @name HDR_PIPE3_CSCA_IO_1 - Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset */
31538/*! @{ */
31539#define MED_HDR10_HDR_PIPE3_CSCA_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFU)
31540#define MED_HDR10_HDR_PIPE3_CSCA_IO_1_COMP1_PRE_OFFSET_SHIFT (0U)
31541#define MED_HDR10_HDR_PIPE3_CSCA_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_1_COMP1_PRE_OFFSET_MASK)
31542/*! @} */
31543
31544/*! @name HDR_PIPE3_CSCA_IO_2 - Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset */
31545/*! @{ */
31546#define MED_HDR10_HDR_PIPE3_CSCA_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFU)
31547#define MED_HDR10_HDR_PIPE3_CSCA_IO_2_COMP2_PRE_OFFSET_SHIFT (0U)
31548#define MED_HDR10_HDR_PIPE3_CSCA_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_2_COMP2_PRE_OFFSET_MASK)
31549/*! @} */
31550
31551/*! @name HDR_PIPE3_CSCA_IO_MIN_0 - Pipe1 Colorspace Converter A (CSCA) component 0 clip min. */
31552/*! @{ */
31553#define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFU)
31554#define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_0_COMP0_CLIP_MIN_SHIFT (0U)
31555#define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_0_COMP0_CLIP_MIN_MASK)
31556/*! @} */
31557
31558/*! @name HDR_PIPE3_CSCA_IO_MIN_1 - Pipe1 Colorspace Converter A (CSCA) component 1 clip min. */
31559/*! @{ */
31560#define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFU)
31561#define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_1_COMP1_CLIP_MIN_SHIFT (0U)
31562#define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_1_COMP1_CLIP_MIN_MASK)
31563/*! @} */
31564
31565/*! @name HDR_PIPE3_CSCA_IO_MIN_2 - Pipe1 Colorspace Converter A (CSCA) component 2 clip min. */
31566/*! @{ */
31567#define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFU)
31568#define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_2_COMP2_CLIP_MIN_SHIFT (0U)
31569#define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_2_COMP2_CLIP_MIN_MASK)
31570/*! @} */
31571
31572/*! @name HDR_PIPE3_CSCA_IO_MAX_0 - Pipe1 Colorspace Converter A (CSCA) component 0 clip max value. */
31573/*! @{ */
31574#define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFU)
31575#define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_0_COMP0_CLIP_MAX_SHIFT (0U)
31576#define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_0_COMP0_CLIP_MAX_MASK)
31577/*! @} */
31578
31579/*! @name HDR_PIPE3_CSCA_IO_MAX_1 - Pipe1 Colorspace Converter A (CSCA) component 1 clip max value. */
31580/*! @{ */
31581#define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFU)
31582#define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_1_COMP1_CLIP_MAX_SHIFT (0U)
31583#define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_1_COMP1_CLIP_MAX_MASK)
31584/*! @} */
31585
31586/*! @name HDR_PIPE3_CSCA_IO_MAX_2 - Pipe1 Colorspace Converter A (CSCA) component 2 clip max value. */
31587/*! @{ */
31588#define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFU)
31589#define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_2_COMP2_CLIP_MAX_SHIFT (0U)
31590#define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_2_COMP2_CLIP_MAX_MASK)
31591/*! @} */
31592
31593/*! @name HDR_PIPE3_CSCA_NORM - Pipe1 Colorspace Converter A (CSCA) normalization factor */
31594/*! @{ */
31595#define MED_HDR10_HDR_PIPE3_CSCA_NORM_CSCA_NORM_MASK (0x1FU)
31596#define MED_HDR10_HDR_PIPE3_CSCA_NORM_CSCA_NORM_SHIFT (0U)
31597#define MED_HDR10_HDR_PIPE3_CSCA_NORM_CSCA_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_NORM_CSCA_NORM_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_NORM_CSCA_NORM_MASK)
31598/*! @} */
31599
31600/*! @name HDR_PIPE3_CSCA_OO_0 - Pipe1 Colorspace Converter A (CSCA): Post offset component 0 */
31601/*! @{ */
31602#define MED_HDR10_HDR_PIPE3_CSCA_OO_0_CSCA_OO_0_MASK (0xFFFFFFFU)
31603#define MED_HDR10_HDR_PIPE3_CSCA_OO_0_CSCA_OO_0_SHIFT (0U)
31604#define MED_HDR10_HDR_PIPE3_CSCA_OO_0_CSCA_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OO_0_CSCA_OO_0_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OO_0_CSCA_OO_0_MASK)
31605/*! @} */
31606
31607/*! @name HDR_PIPE3_CSCA_OO_1 - Pipe1 Colorspace Converter A (CSCA): Post offset component 1 */
31608/*! @{ */
31609#define MED_HDR10_HDR_PIPE3_CSCA_OO_1_CSCA_OO_1_MASK (0xFFFFFFFU)
31610#define MED_HDR10_HDR_PIPE3_CSCA_OO_1_CSCA_OO_1_SHIFT (0U)
31611#define MED_HDR10_HDR_PIPE3_CSCA_OO_1_CSCA_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OO_1_CSCA_OO_1_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OO_1_CSCA_OO_1_MASK)
31612/*! @} */
31613
31614/*! @name HDR_PIPE3_CSCA_OO_2 - Pipe1 Colorspace Converter A (CSCA): Post offset component 2 */
31615/*! @{ */
31616#define MED_HDR10_HDR_PIPE3_CSCA_OO_2_CSCA_OO_2_MASK (0xFFFFFFFU)
31617#define MED_HDR10_HDR_PIPE3_CSCA_OO_2_CSCA_OO_2_SHIFT (0U)
31618#define MED_HDR10_HDR_PIPE3_CSCA_OO_2_CSCA_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OO_2_CSCA_OO_2_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OO_2_CSCA_OO_2_MASK)
31619/*! @} */
31620
31621/*! @name HDR_PIPE3_CSCA_OMIN_0 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0 */
31622/*! @{ */
31623#define MED_HDR10_HDR_PIPE3_CSCA_OMIN_0_POST_OFF_MIN_MASK (0x3FFU)
31624#define MED_HDR10_HDR_PIPE3_CSCA_OMIN_0_POST_OFF_MIN_SHIFT (0U)
31625#define MED_HDR10_HDR_PIPE3_CSCA_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OMIN_0_POST_OFF_MIN_MASK)
31626/*! @} */
31627
31628/*! @name HDR_PIPE3_CSCA_OMIN_1 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1 */
31629/*! @{ */
31630#define MED_HDR10_HDR_PIPE3_CSCA_OMIN_1_POST_OFF_MIN_MASK (0x3FFU)
31631#define MED_HDR10_HDR_PIPE3_CSCA_OMIN_1_POST_OFF_MIN_SHIFT (0U)
31632#define MED_HDR10_HDR_PIPE3_CSCA_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OMIN_1_POST_OFF_MIN_MASK)
31633/*! @} */
31634
31635/*! @name HDR_PIPE3_CSCA_OMIN_2 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2 */
31636/*! @{ */
31637#define MED_HDR10_HDR_PIPE3_CSCA_OMIN_2_POST_OFF_MIN_MASK (0x3FFU)
31638#define MED_HDR10_HDR_PIPE3_CSCA_OMIN_2_POST_OFF_MIN_SHIFT (0U)
31639#define MED_HDR10_HDR_PIPE3_CSCA_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OMIN_2_POST_OFF_MIN_MASK)
31640/*! @} */
31641
31642/*! @name HDR_PIPE3_CSCA_OMAX_0 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0 */
31643/*! @{ */
31644#define MED_HDR10_HDR_PIPE3_CSCA_OMAX_0_POST_OFF_MAX_MASK (0x3FFU)
31645#define MED_HDR10_HDR_PIPE3_CSCA_OMAX_0_POST_OFF_MAX_SHIFT (0U)
31646#define MED_HDR10_HDR_PIPE3_CSCA_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OMAX_0_POST_OFF_MAX_MASK)
31647/*! @} */
31648
31649/*! @name HDR_PIPE3_CSCA_OMAX_1 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1 */
31650/*! @{ */
31651#define MED_HDR10_HDR_PIPE3_CSCA_OMAX_1_POST_OFF_MAX_MASK (0x3FFU)
31652#define MED_HDR10_HDR_PIPE3_CSCA_OMAX_1_POST_OFF_MAX_SHIFT (0U)
31653#define MED_HDR10_HDR_PIPE3_CSCA_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OMAX_1_POST_OFF_MAX_MASK)
31654/*! @} */
31655
31656/*! @name HDR_PIPE3_CSCA_OMAX_2 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2 */
31657/*! @{ */
31658#define MED_HDR10_HDR_PIPE3_CSCA_OMAX_2_POST_OFF_MAX_MASK (0x3FFU)
31659#define MED_HDR10_HDR_PIPE3_CSCA_OMAX_2_POST_OFF_MAX_SHIFT (0U)
31660#define MED_HDR10_HDR_PIPE3_CSCA_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OMAX_2_POST_OFF_MAX_MASK)
31661/*! @} */
31662
31663/*! @name HDR_PIPE3_LUT_CONTROL_REG - Pipe1 LUT control register */
31664/*! @{ */
31665#define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_MASK (0x1U)
31666#define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_SHIFT (0U)
31667#define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_MASK)
31668#define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U)
31669#define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U)
31670#define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK)
31671#define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_BYPASS_MASK (0x8000U)
31672#define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_BYPASS_SHIFT (15U)
31673#define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_BYPASS_MASK)
31674/*! @} */
31675
31676/*! @name HDR_PIPE3_CSCB_CONTROL_REG - Pipe1 Colorspace Converter B control. */
31677/*! @{ */
31678#define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_MASK (0x1U)
31679#define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_SHIFT (0U)
31680#define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_MASK)
31681#define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U)
31682#define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U)
31683#define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK)
31684#define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_BYPASS_MASK (0x8000U)
31685#define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_BYPASS_SHIFT (15U)
31686#define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_BYPASS_MASK)
31687/*! @} */
31688
31689/*! @name HDR_PIPE3_CSCB_H00 - Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient */
31690/*! @{ */
31691#define MED_HDR10_HDR_PIPE3_CSCB_H00_H00_MASK (0xFFFFU)
31692#define MED_HDR10_HDR_PIPE3_CSCB_H00_H00_SHIFT (0U)
31693#define MED_HDR10_HDR_PIPE3_CSCB_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H00_H00_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H00_H00_MASK)
31694/*! @} */
31695
31696/*! @name HDR_PIPE3_CSCB_H10 - Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient */
31697/*! @{ */
31698#define MED_HDR10_HDR_PIPE3_CSCB_H10_H10_MASK (0xFFFFU)
31699#define MED_HDR10_HDR_PIPE3_CSCB_H10_H10_SHIFT (0U)
31700#define MED_HDR10_HDR_PIPE3_CSCB_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H10_H10_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H10_H10_MASK)
31701/*! @} */
31702
31703/*! @name HDR_PIPE3_CSCB_H20 - Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient */
31704/*! @{ */
31705#define MED_HDR10_HDR_PIPE3_CSCB_H20_H20_MASK (0xFFFFU)
31706#define MED_HDR10_HDR_PIPE3_CSCB_H20_H20_SHIFT (0U)
31707#define MED_HDR10_HDR_PIPE3_CSCB_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H20_H20_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H20_H20_MASK)
31708/*! @} */
31709
31710/*! @name HDR_PIPE3_CSCB_H01 - Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient */
31711/*! @{ */
31712#define MED_HDR10_HDR_PIPE3_CSCB_H01_H01_MASK (0xFFFFU)
31713#define MED_HDR10_HDR_PIPE3_CSCB_H01_H01_SHIFT (0U)
31714#define MED_HDR10_HDR_PIPE3_CSCB_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H01_H01_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H01_H01_MASK)
31715/*! @} */
31716
31717/*! @name HDR_PIPE3_CSCB_H11 - Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient */
31718/*! @{ */
31719#define MED_HDR10_HDR_PIPE3_CSCB_H11_H11_MASK (0xFFFFU)
31720#define MED_HDR10_HDR_PIPE3_CSCB_H11_H11_SHIFT (0U)
31721#define MED_HDR10_HDR_PIPE3_CSCB_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H11_H11_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H11_H11_MASK)
31722/*! @} */
31723
31724/*! @name HDR_PIPE3_CSCB_H21 - Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient */
31725/*! @{ */
31726#define MED_HDR10_HDR_PIPE3_CSCB_H21_H21_MASK (0xFFFFU)
31727#define MED_HDR10_HDR_PIPE3_CSCB_H21_H21_SHIFT (0U)
31728#define MED_HDR10_HDR_PIPE3_CSCB_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H21_H21_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H21_H21_MASK)
31729/*! @} */
31730
31731/*! @name HDR_PIPE3_CSCB_H02 - Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient */
31732/*! @{ */
31733#define MED_HDR10_HDR_PIPE3_CSCB_H02_H02_MASK (0xFFFFU)
31734#define MED_HDR10_HDR_PIPE3_CSCB_H02_H02_SHIFT (0U)
31735#define MED_HDR10_HDR_PIPE3_CSCB_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H02_H02_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H02_H02_MASK)
31736/*! @} */
31737
31738/*! @name HDR_PIPE3_CSCB_H12 - Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient */
31739/*! @{ */
31740#define MED_HDR10_HDR_PIPE3_CSCB_H12_H12_MASK (0xFFFFU)
31741#define MED_HDR10_HDR_PIPE3_CSCB_H12_H12_SHIFT (0U)
31742#define MED_HDR10_HDR_PIPE3_CSCB_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H12_H12_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H12_H12_MASK)
31743/*! @} */
31744
31745/*! @name HDR_PIPE3_CSCB_H22 - Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient */
31746/*! @{ */
31747#define MED_HDR10_HDR_PIPE3_CSCB_H22_H22_MASK (0xFFFFU)
31748#define MED_HDR10_HDR_PIPE3_CSCB_H22_H22_SHIFT (0U)
31749#define MED_HDR10_HDR_PIPE3_CSCB_H22_H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H22_H22_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H22_H22_MASK)
31750/*! @} */
31751
31752/*! @name HDR_PIPE3_CSCB_IO_0 - Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset */
31753/*! @{ */
31754#define MED_HDR10_HDR_PIPE3_CSCB_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFFU)
31755#define MED_HDR10_HDR_PIPE3_CSCB_IO_0_COMPO_PRE_OFFSET_SHIFT (0U)
31756#define MED_HDR10_HDR_PIPE3_CSCB_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_0_COMPO_PRE_OFFSET_MASK)
31757/*! @} */
31758
31759/*! @name HDR_PIPE3_CSCB_IO_1 - Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset */
31760/*! @{ */
31761#define MED_HDR10_HDR_PIPE3_CSCB_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFFU)
31762#define MED_HDR10_HDR_PIPE3_CSCB_IO_1_COMP1_PRE_OFFSET_SHIFT (0U)
31763#define MED_HDR10_HDR_PIPE3_CSCB_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_1_COMP1_PRE_OFFSET_MASK)
31764/*! @} */
31765
31766/*! @name HDR_PIPE3_CSCB_IO_2 - Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset */
31767/*! @{ */
31768#define MED_HDR10_HDR_PIPE3_CSCB_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFFU)
31769#define MED_HDR10_HDR_PIPE3_CSCB_IO_2_COMP2_PRE_OFFSET_SHIFT (0U)
31770#define MED_HDR10_HDR_PIPE3_CSCB_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_2_COMP2_PRE_OFFSET_MASK)
31771/*! @} */
31772
31773/*! @name HDR_PIPE3_CSCB_IO_MIN_0 - Pipe1 Colorspace Converter B (CSCB) component 0 clip min. */
31774/*! @{ */
31775#define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFFU)
31776#define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_0_COMP0_CLIP_MIN_SHIFT (0U)
31777#define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_0_COMP0_CLIP_MIN_MASK)
31778/*! @} */
31779
31780/*! @name HDR_PIPE3_CSCB_IO_MIN_1 - Pipe1 Colorspace Converter B (CSCB) component 1 clip min. */
31781/*! @{ */
31782#define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFFU)
31783#define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_1_COMP1_CLIP_MIN_SHIFT (0U)
31784#define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_1_COMP1_CLIP_MIN_MASK)
31785/*! @} */
31786
31787/*! @name HDR_PIPE3_CSCB_IO_MIN_2 - Pipe1 Colorspace Converter B (CSCB) component 2 clip min. */
31788/*! @{ */
31789#define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFFU)
31790#define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_2_COMP2_CLIP_MIN_SHIFT (0U)
31791#define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_2_COMP2_CLIP_MIN_MASK)
31792/*! @} */
31793
31794/*! @name HDR_PIPE3_CSCB_IO_MAX_0 - Pipe1 Colorspace Converter B (CSCB) component 0 clip max value. */
31795/*! @{ */
31796#define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFFU)
31797#define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_0_COMP0_CLIP_MAX_SHIFT (0U)
31798#define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_0_COMP0_CLIP_MAX_MASK)
31799/*! @} */
31800
31801/*! @name HDR_PIPE3_CSCB_IO_MAX_1 - Pipe1 Colorspace Converter B (CSCB) component 1 clip max value. */
31802/*! @{ */
31803#define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFFU)
31804#define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_1_COMP1_CLIP_MAX_SHIFT (0U)
31805#define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_1_COMP1_CLIP_MAX_MASK)
31806/*! @} */
31807
31808/*! @name HDR_PIPE3_CSCB_IO_MAX_2 - Pipe1 Colorspace Converter B (CSCB) component 2 clip max value. */
31809/*! @{ */
31810#define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFFU)
31811#define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_2_COMP2_CLIP_MAX_SHIFT (0U)
31812#define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_2_COMP2_CLIP_MAX_MASK)
31813/*! @} */
31814
31815/*! @name HDR_PIPE3_CSCB_NORM - Pipe1 Colorspace Converter B (CSCB) normalization factor */
31816/*! @{ */
31817#define MED_HDR10_HDR_PIPE3_CSCB_NORM_CSCB_NORM_MASK (0x1FU)
31818#define MED_HDR10_HDR_PIPE3_CSCB_NORM_CSCB_NORM_SHIFT (0U)
31819#define MED_HDR10_HDR_PIPE3_CSCB_NORM_CSCB_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_NORM_CSCB_NORM_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_NORM_CSCB_NORM_MASK)
31820/*! @} */
31821
31822/*! @name HDR_PIPE3_CSCB_OO_0 - Pipe1 Colorspace Converter B (CSCB): Post offset component 0 */
31823/*! @{ */
31824#define MED_HDR10_HDR_PIPE3_CSCB_OO_0_CSCB_OO_0_MASK (0x1FFFFFFFU)
31825#define MED_HDR10_HDR_PIPE3_CSCB_OO_0_CSCB_OO_0_SHIFT (0U)
31826#define MED_HDR10_HDR_PIPE3_CSCB_OO_0_CSCB_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OO_0_CSCB_OO_0_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OO_0_CSCB_OO_0_MASK)
31827/*! @} */
31828
31829/*! @name HDR_PIPE3_CSCB_OO_1 - Pipe1 Colorspace Converter B (CSCB): Post offset component 1 */
31830/*! @{ */
31831#define MED_HDR10_HDR_PIPE3_CSCB_OO_1_CSCB_OO_1_MASK (0x1FFFFFFFU)
31832#define MED_HDR10_HDR_PIPE3_CSCB_OO_1_CSCB_OO_1_SHIFT (0U)
31833#define MED_HDR10_HDR_PIPE3_CSCB_OO_1_CSCB_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OO_1_CSCB_OO_1_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OO_1_CSCB_OO_1_MASK)
31834/*! @} */
31835
31836/*! @name HDR_PIPE3_CSCB_OO_2 - Pipe1 Colorspace Converter B (CSCB): Post offset component 2 */
31837/*! @{ */
31838#define MED_HDR10_HDR_PIPE3_CSCB_OO_2_CSCB_OO_2_MASK (0x1FFFFFFFU)
31839#define MED_HDR10_HDR_PIPE3_CSCB_OO_2_CSCB_OO_2_SHIFT (0U)
31840#define MED_HDR10_HDR_PIPE3_CSCB_OO_2_CSCB_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OO_2_CSCB_OO_2_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OO_2_CSCB_OO_2_MASK)
31841/*! @} */
31842
31843/*! @name HDR_PIPE3_CSCB_OMIN_0 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0 */
31844/*! @{ */
31845#define MED_HDR10_HDR_PIPE3_CSCB_OMIN_0_POST_OFF_MIN_MASK (0xFFFFFFFU)
31846#define MED_HDR10_HDR_PIPE3_CSCB_OMIN_0_POST_OFF_MIN_SHIFT (0U)
31847#define MED_HDR10_HDR_PIPE3_CSCB_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OMIN_0_POST_OFF_MIN_MASK)
31848/*! @} */
31849
31850/*! @name HDR_PIPE3_CSCB_OMIN_1 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1 */
31851/*! @{ */
31852#define MED_HDR10_HDR_PIPE3_CSCB_OMIN_1_POST_OFF_MIN_MASK (0xFFFFFFFU)
31853#define MED_HDR10_HDR_PIPE3_CSCB_OMIN_1_POST_OFF_MIN_SHIFT (0U)
31854#define MED_HDR10_HDR_PIPE3_CSCB_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OMIN_1_POST_OFF_MIN_MASK)
31855/*! @} */
31856
31857/*! @name HDR_PIPE3_CSCB_OMIN_2 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2 */
31858/*! @{ */
31859#define MED_HDR10_HDR_PIPE3_CSCB_OMIN_2_POST_OFF_MIN_MASK (0xFFFFFFFU)
31860#define MED_HDR10_HDR_PIPE3_CSCB_OMIN_2_POST_OFF_MIN_SHIFT (0U)
31861#define MED_HDR10_HDR_PIPE3_CSCB_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OMIN_2_POST_OFF_MIN_MASK)
31862/*! @} */
31863
31864/*! @name HDR_PIPE3_CSCB_OMAX_0 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0 */
31865/*! @{ */
31866#define MED_HDR10_HDR_PIPE3_CSCB_OMAX_0_POST_OFF_MAX_MASK (0xFFFFFFFU)
31867#define MED_HDR10_HDR_PIPE3_CSCB_OMAX_0_POST_OFF_MAX_SHIFT (0U)
31868#define MED_HDR10_HDR_PIPE3_CSCB_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OMAX_0_POST_OFF_MAX_MASK)
31869/*! @} */
31870
31871/*! @name HDR_PIPE3_CSCB_OMAX_1 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1 */
31872/*! @{ */
31873#define MED_HDR10_HDR_PIPE3_CSCB_OMAX_1_POST_OFF_MAX_MASK (0x3FFU)
31874#define MED_HDR10_HDR_PIPE3_CSCB_OMAX_1_POST_OFF_MAX_SHIFT (0U)
31875#define MED_HDR10_HDR_PIPE3_CSCB_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OMAX_1_POST_OFF_MAX_MASK)
31876/*! @} */
31877
31878/*! @name HDR_PIPE3_CSCB_OMAX_2 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2 */
31879/*! @{ */
31880#define MED_HDR10_HDR_PIPE3_CSCB_OMAX_2_POST_OFF_MAX_MASK (0xFFFFFFFU)
31881#define MED_HDR10_HDR_PIPE3_CSCB_OMAX_2_POST_OFF_MAX_SHIFT (0U)
31882#define MED_HDR10_HDR_PIPE3_CSCB_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OMAX_2_POST_OFF_MAX_MASK)
31883/*! @} */
31884
31885/*! @name HDR_PIPE3_FL2FX - Pipe1 floating point to fixed point control */
31886/*! @{ */
31887#define MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_MASK (0x1U)
31888#define MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_SHIFT (0U)
31889#define MED_HDR10_HDR_PIPE3_FL2FX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_MASK)
31890#define MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_FOR_ALL_PELS_MASK (0x2U)
31891#define MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_FOR_ALL_PELS_SHIFT (1U)
31892#define MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_FOR_ALL_PELS_MASK)
31893/*! @} */
31894
31895/*! @name OPIPE_A0_TABLE - A0 component Linear-to-Non-linear conversion table */
31896/*! @{ */
31897#define MED_HDR10_OPIPE_A0_TABLE_OPIPE_A0_TABLE_MASK (0x3FFFU)
31898#define MED_HDR10_OPIPE_A0_TABLE_OPIPE_A0_TABLE_SHIFT (0U)
31899#define MED_HDR10_OPIPE_A0_TABLE_OPIPE_A0_TABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_OPIPE_A0_TABLE_OPIPE_A0_TABLE_SHIFT)) & MED_HDR10_OPIPE_A0_TABLE_OPIPE_A0_TABLE_MASK)
31900/*! @} */
31901
31902/*! @name OPIPE_A1_TABLE - A1 component Linear-to-Non-linear conversion table */
31903/*! @{ */
31904#define MED_HDR10_OPIPE_A1_TABLE_OPIPE_A1_TABLE_MASK (0x3FFFU)
31905#define MED_HDR10_OPIPE_A1_TABLE_OPIPE_A1_TABLE_SHIFT (0U)
31906#define MED_HDR10_OPIPE_A1_TABLE_OPIPE_A1_TABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_OPIPE_A1_TABLE_OPIPE_A1_TABLE_SHIFT)) & MED_HDR10_OPIPE_A1_TABLE_OPIPE_A1_TABLE_MASK)
31907/*! @} */
31908
31909/*! @name OPIPE_A2_TABLE - A2 component Linear-to-Non-linear conversion table */
31910/*! @{ */
31911#define MED_HDR10_OPIPE_A2_TABLE_OPIPE_A2_TABLE_MASK (0x3FFFU)
31912#define MED_HDR10_OPIPE_A2_TABLE_OPIPE_A2_TABLE_SHIFT (0U)
31913#define MED_HDR10_OPIPE_A2_TABLE_OPIPE_A2_TABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_OPIPE_A2_TABLE_OPIPE_A2_TABLE_SHIFT)) & MED_HDR10_OPIPE_A2_TABLE_OPIPE_A2_TABLE_MASK)
31914/*! @} */
31915
31916/*! @name HDR_OPIPE_CSC_CONTROL_REG - HDR output stage Colorspace Converter (CSCO) control. */
31917/*! @{ */
31918#define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_MASK (0x1U)
31919#define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_SHIFT (0U)
31920#define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_MASK)
31921#define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U)
31922#define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U)
31923#define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK)
31924#define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_BYPASS_MASK (0x8000U)
31925#define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_BYPASS_SHIFT (15U)
31926#define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_BYPASS_MASK)
31927/*! @} */
31928
31929/*! @name HDR_OPIPE_CSC_H00 - Pipe1 Colorspace Converter (CSC) h(0,0) matrix coefficient */
31930/*! @{ */
31931#define MED_HDR10_HDR_OPIPE_CSC_H00_H00_MASK (0xFFFFU)
31932#define MED_HDR10_HDR_OPIPE_CSC_H00_H00_SHIFT (0U)
31933#define MED_HDR10_HDR_OPIPE_CSC_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H00_H00_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H00_H00_MASK)
31934/*! @} */
31935
31936/*! @name HDR_OPIPE_CSC_H10 - Pipe1 Colorspace Converter (CSC) h(1,0) matrix coefficient */
31937/*! @{ */
31938#define MED_HDR10_HDR_OPIPE_CSC_H10_H10_MASK (0xFFFFU)
31939#define MED_HDR10_HDR_OPIPE_CSC_H10_H10_SHIFT (0U)
31940#define MED_HDR10_HDR_OPIPE_CSC_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H10_H10_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H10_H10_MASK)
31941/*! @} */
31942
31943/*! @name HDR_OPIPE_CSC_H20 - HDR OUTPUT Colorspace Converter (CSCO) h(2,0) matrix coefficient */
31944/*! @{ */
31945#define MED_HDR10_HDR_OPIPE_CSC_H20_H20_MASK (0xFFFFU)
31946#define MED_HDR10_HDR_OPIPE_CSC_H20_H20_SHIFT (0U)
31947#define MED_HDR10_HDR_OPIPE_CSC_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H20_H20_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H20_H20_MASK)
31948/*! @} */
31949
31950/*! @name HDR_OPIPE_CSC_H01 - HDR OUTPUT pipe Colorspace Converter (CSCO) h(0,1) matrix coefficient */
31951/*! @{ */
31952#define MED_HDR10_HDR_OPIPE_CSC_H01_H01_MASK (0xFFFFU)
31953#define MED_HDR10_HDR_OPIPE_CSC_H01_H01_SHIFT (0U)
31954#define MED_HDR10_HDR_OPIPE_CSC_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H01_H01_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H01_H01_MASK)
31955/*! @} */
31956
31957/*! @name HDR_OPIPE_CSC_H11 - HDR OUTPUT pipe Colorspace Converter (CSCO) h(1,1) matrix coefficient */
31958/*! @{ */
31959#define MED_HDR10_HDR_OPIPE_CSC_H11_H11_MASK (0xFFFFU)
31960#define MED_HDR10_HDR_OPIPE_CSC_H11_H11_SHIFT (0U)
31961#define MED_HDR10_HDR_OPIPE_CSC_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H11_H11_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H11_H11_MASK)
31962/*! @} */
31963
31964/*! @name HDR_OPIPE_CSC_H21 - HDR_output pipe Colorspace Converter (CSCO) h(2,1) matrix coefficient */
31965/*! @{ */
31966#define MED_HDR10_HDR_OPIPE_CSC_H21_H21_MASK (0xFFFFU)
31967#define MED_HDR10_HDR_OPIPE_CSC_H21_H21_SHIFT (0U)
31968#define MED_HDR10_HDR_OPIPE_CSC_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H21_H21_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H21_H21_MASK)
31969/*! @} */
31970
31971/*! @name HDR_OPIPE_CSC_H02 - HDR OUTPUT pipe Colorspace Converter (CSCO) h(0,2) matrix coefficient */
31972/*! @{ */
31973#define MED_HDR10_HDR_OPIPE_CSC_H02_H02_MASK (0xFFFFU)
31974#define MED_HDR10_HDR_OPIPE_CSC_H02_H02_SHIFT (0U)
31975#define MED_HDR10_HDR_OPIPE_CSC_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H02_H02_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H02_H02_MASK)
31976/*! @} */
31977
31978/*! @name HDR_OPIPE_CSC_H12 - HDR OUPUT pipe Colorspace Converter (CSCO) h(1,2) matrix coefficient */
31979/*! @{ */
31980#define MED_HDR10_HDR_OPIPE_CSC_H12_H12_MASK (0xFFFFU)
31981#define MED_HDR10_HDR_OPIPE_CSC_H12_H12_SHIFT (0U)
31982#define MED_HDR10_HDR_OPIPE_CSC_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H12_H12_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H12_H12_MASK)
31983/*! @} */
31984
31985/*! @name HDR_ - HDR OUPUT pipe Colorspace Converter (CSCO) h(2,2) matrix coefficient */
31986/*! @{ */
31987#define MED_HDR10_HDR__H22_MASK (0xFFFFU)
31988#define MED_HDR10_HDR__H22_SHIFT (0U)
31989#define MED_HDR10_HDR__H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR__H22_SHIFT)) & MED_HDR10_HDR__H22_MASK)
31990/*! @} */
31991
31992/*! @name HDR_OPIPE_CSC_IO_0 - HDR OUTPUT pipe Colorspace Converter (CSCO) component 0 pre-offset */
31993/*! @{ */
31994#define MED_HDR10_HDR_OPIPE_CSC_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFU)
31995#define MED_HDR10_HDR_OPIPE_CSC_IO_0_COMPO_PRE_OFFSET_SHIFT (0U)
31996#define MED_HDR10_HDR_OPIPE_CSC_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_IO_0_COMPO_PRE_OFFSET_MASK)
31997/*! @} */
31998
31999/*! @name HDR_OPIPE_CSC_IO_1 - HDR OUPTUT pipe Colorspace Converter (CSCO) component 1 pre-offset */
32000/*! @{ */
32001#define MED_HDR10_HDR_OPIPE_CSC_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFU)
32002#define MED_HDR10_HDR_OPIPE_CSC_IO_1_COMP1_PRE_OFFSET_SHIFT (0U)
32003#define MED_HDR10_HDR_OPIPE_CSC_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_IO_1_COMP1_PRE_OFFSET_MASK)
32004/*! @} */
32005
32006/*! @name HDR_OPIPE_CSC_IO_2 - HDR OUPUT pipe: Colorspace Converter (CSCO) component 2 pre-offset */
32007/*! @{ */
32008#define MED_HDR10_HDR_OPIPE_CSC_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFU)
32009#define MED_HDR10_HDR_OPIPE_CSC_IO_2_COMP2_PRE_OFFSET_SHIFT (0U)
32010#define MED_HDR10_HDR_OPIPE_CSC_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_IO_2_COMP2_PRE_OFFSET_MASK)
32011/*! @} */
32012
32013/*! @name HDR_OPIPE_CSC_MIN_0 - HDR OUPTU pipe Colorspace Converter (CSCO) component 0 clip min. */
32014/*! @{ */
32015#define MED_HDR10_HDR_OPIPE_CSC_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFU)
32016#define MED_HDR10_HDR_OPIPE_CSC_MIN_0_COMP0_CLIP_MIN_SHIFT (0U)
32017#define MED_HDR10_HDR_OPIPE_CSC_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_MIN_0_COMP0_CLIP_MIN_MASK)
32018/*! @} */
32019
32020/*! @name HDR_OPIPE_CSC_MIN_1 - HDR OUPUT pipe Colorspace Converter (CSCO) component 1 clip min. */
32021/*! @{ */
32022#define MED_HDR10_HDR_OPIPE_CSC_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFU)
32023#define MED_HDR10_HDR_OPIPE_CSC_MIN_1_COMP1_CLIP_MIN_SHIFT (0U)
32024#define MED_HDR10_HDR_OPIPE_CSC_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_MIN_1_COMP1_CLIP_MIN_MASK)
32025/*! @} */
32026
32027/*! @name HDR_OPIPE_CSC_MIN_2 - HDR OUPTU pipe Colorspace Converter (CSCO) component 2 clip min. */
32028/*! @{ */
32029#define MED_HDR10_HDR_OPIPE_CSC_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFU)
32030#define MED_HDR10_HDR_OPIPE_CSC_MIN_2_COMP2_CLIP_MIN_SHIFT (0U)
32031#define MED_HDR10_HDR_OPIPE_CSC_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_MIN_2_COMP2_CLIP_MIN_MASK)
32032/*! @} */
32033
32034/*! @name HDR_OPIPE_CSC_MAX_0 - HDR OUPTUT pipe Colorspace Converter O (CSC) component 0 clip max value. */
32035/*! @{ */
32036#define MED_HDR10_HDR_OPIPE_CSC_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFU)
32037#define MED_HDR10_HDR_OPIPE_CSC_MAX_0_COMP0_CLIP_MAX_SHIFT (0U)
32038#define MED_HDR10_HDR_OPIPE_CSC_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_MAX_0_COMP0_CLIP_MAX_MASK)
32039/*! @} */
32040
32041/*! @name HDR_OPIPE_CSC_MAX_1 - HDR OUTPUT pipe Colorspace Converter (CSCO) component 1 clip max value. */
32042/*! @{ */
32043#define MED_HDR10_HDR_OPIPE_CSC_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFU)
32044#define MED_HDR10_HDR_OPIPE_CSC_MAX_1_COMP1_CLIP_MAX_SHIFT (0U)
32045#define MED_HDR10_HDR_OPIPE_CSC_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_MAX_1_COMP1_CLIP_MAX_MASK)
32046/*! @} */
32047
32048/*! @name HDR_OPIPE_CSC_MAX_2 - HDR OUTPUT pipe Colorspace Converter (CSCO) component 2 clip max value. */
32049/*! @{ */
32050#define MED_HDR10_HDR_OPIPE_CSC_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFU)
32051#define MED_HDR10_HDR_OPIPE_CSC_MAX_2_COMP2_CLIP_MAX_SHIFT (0U)
32052#define MED_HDR10_HDR_OPIPE_CSC_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_MAX_2_COMP2_CLIP_MAX_MASK)
32053/*! @} */
32054
32055/*! @name HDR_OPIPE_CSC_NORM - HDR OUPUT pipe Colorspace Converter (CSCO) normalization factor */
32056/*! @{ */
32057#define MED_HDR10_HDR_OPIPE_CSC_NORM_CSC_NORM_MASK (0x1FU)
32058#define MED_HDR10_HDR_OPIPE_CSC_NORM_CSC_NORM_SHIFT (0U)
32059#define MED_HDR10_HDR_OPIPE_CSC_NORM_CSC_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_NORM_CSC_NORM_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_NORM_CSC_NORM_MASK)
32060/*! @} */
32061
32062/*! @name HDR_OPIPE_CSC_OO_0 - HDR OUPTUT pipe Colorspace Converter (CSC): Post offset component 0 */
32063/*! @{ */
32064#define MED_HDR10_HDR_OPIPE_CSC_OO_0_CSC_OO_0_MASK (0xFFFFFFFU)
32065#define MED_HDR10_HDR_OPIPE_CSC_OO_0_CSC_OO_0_SHIFT (0U)
32066#define MED_HDR10_HDR_OPIPE_CSC_OO_0_CSC_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OO_0_CSC_OO_0_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OO_0_CSC_OO_0_MASK)
32067/*! @} */
32068
32069/*! @name HDR_OPIPE_CSC_OO_1 - HDR OUTPUT pipe Colorspace Converter (CSC): Post offset component 1 */
32070/*! @{ */
32071#define MED_HDR10_HDR_OPIPE_CSC_OO_1_CSC_OO_1_MASK (0xFFFFFFFU)
32072#define MED_HDR10_HDR_OPIPE_CSC_OO_1_CSC_OO_1_SHIFT (0U)
32073#define MED_HDR10_HDR_OPIPE_CSC_OO_1_CSC_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OO_1_CSC_OO_1_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OO_1_CSC_OO_1_MASK)
32074/*! @} */
32075
32076/*! @name HDR_OPIPE_CSC_OO_2 - HDR OUPTUT pipe Colorspace Converter (CSC): Post offset component 2 */
32077/*! @{ */
32078#define MED_HDR10_HDR_OPIPE_CSC_OO_2_CSC_OO_2_MASK (0xFFFFFFFU)
32079#define MED_HDR10_HDR_OPIPE_CSC_OO_2_CSC_OO_2_SHIFT (0U)
32080#define MED_HDR10_HDR_OPIPE_CSC_OO_2_CSC_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OO_2_CSC_OO_2_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OO_2_CSC_OO_2_MASK)
32081/*! @} */
32082
32083/*! @name HDR_OPIPE_CSC_OMIN_0 - HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 0 */
32084/*! @{ */
32085#define MED_HDR10_HDR_OPIPE_CSC_OMIN_0_POST_OFF_MIN_MASK (0x3FFU)
32086#define MED_HDR10_HDR_OPIPE_CSC_OMIN_0_POST_OFF_MIN_SHIFT (0U)
32087#define MED_HDR10_HDR_OPIPE_CSC_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OMIN_0_POST_OFF_MIN_MASK)
32088/*! @} */
32089
32090/*! @name HDR_OPIPE_CSC_OMIN_1 - HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 1 */
32091/*! @{ */
32092#define MED_HDR10_HDR_OPIPE_CSC_OMIN_1_POST_OFF_MIN_MASK (0x3FFU)
32093#define MED_HDR10_HDR_OPIPE_CSC_OMIN_1_POST_OFF_MIN_SHIFT (0U)
32094#define MED_HDR10_HDR_OPIPE_CSC_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OMIN_1_POST_OFF_MIN_MASK)
32095/*! @} */
32096
32097/*! @name HDR_OPIPE_CSC_OMIN_2 - HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 2 */
32098/*! @{ */
32099#define MED_HDR10_HDR_OPIPE_CSC_OMIN_2_POST_OFF_MIN_MASK (0x3FFU)
32100#define MED_HDR10_HDR_OPIPE_CSC_OMIN_2_POST_OFF_MIN_SHIFT (0U)
32101#define MED_HDR10_HDR_OPIPE_CSC_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OMIN_2_POST_OFF_MIN_MASK)
32102/*! @} */
32103
32104/*! @name HDR_OPIPE_CSC_OMAX_0 - HDR OUPTUT pipe Colorspace Converter (CSC): Post offset max clip value for component 0 */
32105/*! @{ */
32106#define MED_HDR10_HDR_OPIPE_CSC_OMAX_0_POST_OFF_MAX_MASK (0x3FFU)
32107#define MED_HDR10_HDR_OPIPE_CSC_OMAX_0_POST_OFF_MAX_SHIFT (0U)
32108#define MED_HDR10_HDR_OPIPE_CSC_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OMAX_0_POST_OFF_MAX_MASK)
32109/*! @} */
32110
32111/*! @name HDR_OPIPE_CSC_OMAX_1 - HDR OUTPUT pipe Colorspace Converter (CSC): Post offset max clip value for component 1 */
32112/*! @{ */
32113#define MED_HDR10_HDR_OPIPE_CSC_OMAX_1_POST_OFF_MAX_MASK (0x3FFU)
32114#define MED_HDR10_HDR_OPIPE_CSC_OMAX_1_POST_OFF_MAX_SHIFT (0U)
32115#define MED_HDR10_HDR_OPIPE_CSC_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OMAX_1_POST_OFF_MAX_MASK)
32116/*! @} */
32117
32118/*! @name HDR_OPIPE_CSC_OMAX_2 - HDR OUTPUT pipe Colorspace Converter (CSC): Post offset max clip value for component 2 */
32119/*! @{ */
32120#define MED_HDR10_HDR_OPIPE_CSC_OMAX_2_POST_OFF_MAX_MASK (0x3FFU)
32121#define MED_HDR10_HDR_OPIPE_CSC_OMAX_2_POST_OFF_MAX_SHIFT (0U)
32122#define MED_HDR10_HDR_OPIPE_CSC_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OMAX_2_POST_OFF_MAX_MASK)
32123/*! @} */
32124
32125/*! @name HDR_OPIPE_2NL_CONTROL_REG - HDR OUTPUT -TO NON LINEAR pipeline control */
32126/*! @{ */
32127#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_PASS_THRU_MASK (0x1U)
32128#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_PASS_THRU_SHIFT (0U)
32129#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_PASS_THRU(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_PASS_THRU_SHIFT)) & MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_PASS_THRU_MASK)
32130#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_DISABLE_FIXED_TO_FLOAT_MASK (0x2U)
32131#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_DISABLE_FIXED_TO_FLOAT_SHIFT (1U)
32132#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_DISABLE_FIXED_TO_FLOAT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_DISABLE_FIXED_TO_FLOAT_SHIFT)) & MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_DISABLE_FIXED_TO_FLOAT_MASK)
32133#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_LTNL_ENABLE_FOR_ALL_PELS_MASK (0x4U)
32134#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_LTNL_ENABLE_FOR_ALL_PELS_SHIFT (2U)
32135#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_LTNL_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_LTNL_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_LTNL_ENABLE_FOR_ALL_PELS_MASK)
32136#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_FIX2FLT_ENABLE_FOR_ALL_PELS_MASK (0x8U)
32137#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_FIX2FLT_ENABLE_FOR_ALL_PELS_SHIFT (3U)
32138#define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_FIX2FLT_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_FIX2FLT_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_FIX2FLT_ENABLE_FOR_ALL_PELS_MASK)
32139/*! @} */
32140
32141
32142/*!
32143 * @}
32144 */ /* end of group MED_HDR10_Register_Masks */
32145
32146
32147/* MED_HDR10 - Peripheral instance base addresses */
32148/** Peripheral DCSS__MED_HDR10 base address */
32149#define DCSS__MED_HDR10_BASE (0x32E0C000u)
32150/** Peripheral DCSS__MED_HDR10 base pointer */
32151#define DCSS__MED_HDR10 ((MED_HDR10_Type *)DCSS__MED_HDR10_BASE)
32152/** Array initializer of MED_HDR10 peripheral base addresses */
32153#define MED_HDR10_BASE_ADDRS { DCSS__MED_HDR10_BASE }
32154/** Array initializer of MED_HDR10 peripheral base pointers */
32155#define MED_HDR10_BASE_PTRS { DCSS__MED_HDR10 }
32156
32157/*!
32158 * @}
32159 */ /* end of group MED_HDR10_Peripheral_Access_Layer */
32160
32161
32162/* ----------------------------------------------------------------------------
32163 -- MIPI_CSI2RX Peripheral Access Layer
32164 ---------------------------------------------------------------------------- */
32165
32166/*!
32167 * @addtogroup MIPI_CSI2RX_Peripheral_Access_Layer MIPI_CSI2RX Peripheral Access Layer
32168 * @{
32169 */
32170
32171/** MIPI_CSI2RX - Register Layout Typedef */
32172typedef struct {
32173 __IO uint32_t CSI2RX_CFG_NUM_LANES; /**< , offset: 0x0 */
32174 __IO uint32_t CSI2RX_CFG_DISABLE_DATA_LANES; /**< , offset: 0x4 */
32175 __I uint32_t CSI2RX_BIT_ERR; /**< , offset: 0x8 */
32176 __I uint32_t CSI2RX_IRQ_STATUS; /**< , offset: 0xC */
32177 __IO uint32_t CSI2RX_IRQ_MASK; /**< , offset: 0x10 */
32178 __I uint32_t CSI2RX_ULPS_STATUS; /**< , offset: 0x14 */
32179 __I uint32_t CSI2RX_PPI_ERRSOT_HS; /**< , offset: 0x18 */
32180 __I uint32_t CSI2RX_PPI_ERRSOTSYNC_HS; /**< , offset: 0x1C */
32181 __I uint32_t CSI2RX_PPI_ERRESC; /**< , offset: 0x20 */
32182 __I uint32_t CSI2RX_PPI_ERRSYNCESC; /**< , offset: 0x24 */
32183 __I uint32_t CSI2RX_PPI_ERRCONTROL; /**< , offset: 0x28 */
32184 __IO uint32_t CSI2RX_CFG_DISABLE_PAYLOAD_0; /**< , offset: 0x2C */
32185 __IO uint32_t CSI2RX_CFG_DISABLE_PAYLOAD_1; /**< , offset: 0x30 */
32186} MIPI_CSI2RX_Type;
32187
32188/* ----------------------------------------------------------------------------
32189 -- MIPI_CSI2RX Register Masks
32190 ---------------------------------------------------------------------------- */
32191
32192/*!
32193 * @addtogroup MIPI_CSI2RX_Register_Masks MIPI_CSI2RX Register Masks
32194 * @{
32195 */
32196
32197/*! @name CSI2RX_CFG_NUM_LANES - */
32198/*! @{ */
32199#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK (0x3U)
32200#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_SHIFT (0U)
32201/*! csi2rx_cfg_num_lanes - Sets the number of active lanes that are to be used for receiving data.
32202 * 0b00..1 Lane
32203 * 0b01..2 Lane
32204 * 0b10..3 Lane
32205 * 0b11..4 Lane
32206 */
32207#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK)
32208/*! @} */
32209
32210/*! @name CSI2RX_CFG_DISABLE_DATA_LANES - */
32211/*! @{ */
32212#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_MASK (0xFU)
32213#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_SHIFT (0U)
32214/*! csi2rx_cfg_disable_data_lanes - Setting bits to a '1' value causes the DPHY Enable signal to deassert.
32215 * 0b0001..Data Lane 0
32216 * 0b0010..Data Lane 1
32217 * 0b0100..Data Lane 2
32218 * 0b1000..Data Lane 3
32219 */
32220#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_MASK)
32221/*! @} */
32222
32223/*! @name CSI2RX_BIT_ERR - */
32224/*! @{ */
32225#define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_MASK (0x3FFU)
32226#define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_SHIFT (0U)
32227#define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_SHIFT)) & MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_MASK)
32228/*! @} */
32229
32230/*! @name CSI2RX_IRQ_STATUS - */
32231/*! @{ */
32232#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_MASK (0x1FFU)
32233#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_SHIFT (0U)
32234#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_MASK)
32235/*! @} */
32236
32237/*! @name CSI2RX_IRQ_MASK - */
32238/*! @{ */
32239#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK (0x1FFU)
32240#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_SHIFT (0U)
32241#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK)
32242/*! @} */
32243
32244/*! @name CSI2RX_ULPS_STATUS - */
32245/*! @{ */
32246#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_MASK (0x3FFU)
32247#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_SHIFT (0U)
32248#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_SHIFT)) & MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_MASK)
32249/*! @} */
32250
32251/*! @name CSI2RX_PPI_ERRSOT_HS - */
32252/*! @{ */
32253#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_MASK (0xFU)
32254#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_SHIFT (0U)
32255#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_MASK)
32256/*! @} */
32257
32258/*! @name CSI2RX_PPI_ERRSOTSYNC_HS - */
32259/*! @{ */
32260#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_MASK (0xFU)
32261#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_SHIFT (0U)
32262#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_MASK)
32263/*! @} */
32264
32265/*! @name CSI2RX_PPI_ERRESC - */
32266/*! @{ */
32267#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_MASK (0xFU)
32268#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_SHIFT (0U)
32269#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_MASK)
32270/*! @} */
32271
32272/*! @name CSI2RX_PPI_ERRSYNCESC - */
32273/*! @{ */
32274#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_MASK (0xFU)
32275#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_SHIFT (0U)
32276#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_MASK)
32277/*! @} */
32278
32279/*! @name CSI2RX_PPI_ERRCONTROL - */
32280/*! @{ */
32281#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_MASK (0xFU)
32282#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_SHIFT (0U)
32283#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_MASK)
32284/*! @} */
32285
32286/*! @name CSI2RX_CFG_DISABLE_PAYLOAD_0 - */
32287/*! @{ */
32288#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_null_MASK (0x1U)
32289#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_null_SHIFT (0U)
32290#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_null(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_null_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_null_MASK)
32291#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_blank_MASK (0x2U)
32292#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_blank_SHIFT (1U)
32293#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_blank(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_blank_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_blank_MASK)
32294#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_embedded_MASK (0x4U)
32295#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_embedded_SHIFT (2U)
32296#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_embedded(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_embedded_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_embedded_MASK)
32297#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_legacy_yuv_8_MASK (0x400U)
32298#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_legacy_yuv_8_SHIFT (10U)
32299#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_legacy_yuv_8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_legacy_yuv_8_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_legacy_yuv_8_MASK)
32300#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_8_MASK (0x4000U)
32301#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_8_SHIFT (14U)
32302#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_8_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_8_MASK)
32303#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_10_MASK (0x8000U)
32304#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_10_SHIFT (15U)
32305#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_10_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_10_MASK)
32306#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb444_MASK (0x10000U)
32307#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb444_SHIFT (16U)
32308#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb444(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb444_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb444_MASK)
32309#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb555_MASK (0x20000U)
32310#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb555_SHIFT (17U)
32311#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb555(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb555_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb555_MASK)
32312#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb565_MASK (0x40000U)
32313#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb565_SHIFT (18U)
32314#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb565(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb565_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb565_MASK)
32315#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb666_MASK (0x80000U)
32316#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb666_SHIFT (19U)
32317#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb666(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb666_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb666_MASK)
32318#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb888_MASK (0x100000U)
32319#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb888_SHIFT (20U)
32320#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb888(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb888_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb888_MASK)
32321#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw6_MASK (0x1000000U)
32322#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw6_SHIFT (24U)
32323#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw6(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw6_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw6_MASK)
32324#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw7_MASK (0x2000000U)
32325#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw7_SHIFT (25U)
32326#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw7(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw7_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw7_MASK)
32327#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw8_MASK (0x4000000U)
32328#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw8_SHIFT (26U)
32329#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw8_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw8_MASK)
32330#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw10_MASK (0x8000000U)
32331#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw10_SHIFT (27U)
32332#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw10_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw10_MASK)
32333#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw12_MASK (0x10000000U)
32334#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw12_SHIFT (28U)
32335#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw12(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw12_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw12_MASK)
32336#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw14_MASK (0x20000000U)
32337#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw14_SHIFT (29U)
32338#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw14(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw14_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw14_MASK)
32339/*! @} */
32340
32341/*! @name CSI2RX_CFG_DISABLE_PAYLOAD_1 - */
32342/*! @{ */
32343#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_30_MASK (0x1U)
32344#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_30_SHIFT (0U)
32345#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_30(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_30_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_30_MASK)
32346#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_31_MASK (0x2U)
32347#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_31_SHIFT (1U)
32348#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_31_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_31_MASK)
32349#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_32_MASK (0x4U)
32350#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_32_SHIFT (2U)
32351#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_32(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_32_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_32_MASK)
32352#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_33_MASK (0x8U)
32353#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_33_SHIFT (3U)
32354#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_33(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_33_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_33_MASK)
32355#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_34_MASK (0x10U)
32356#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_34_SHIFT (4U)
32357#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_34(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_34_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_34_MASK)
32358#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_35_MASK (0x20U)
32359#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_35_SHIFT (5U)
32360#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_35(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_35_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_35_MASK)
32361#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_36_MASK (0x40U)
32362#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_36_SHIFT (6U)
32363#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_36(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_36_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_36_MASK)
32364#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_37_MASK (0x80U)
32365#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_37_SHIFT (7U)
32366#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_37(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_37_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_37_MASK)
32367#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_unsupported_MASK (0x10000U)
32368#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_unsupported_SHIFT (16U)
32369#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_unsupported(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_unsupported_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_unsupported_MASK)
32370/*! @} */
32371
32372
32373/*!
32374 * @}
32375 */ /* end of group MIPI_CSI2RX_Register_Masks */
32376
32377
32378/* MIPI_CSI2RX - Peripheral instance base addresses */
32379/** Peripheral MIPI_CSI2RX1 base address */
32380#define MIPI_CSI2RX1_BASE (0x30A70000u)
32381/** Peripheral MIPI_CSI2RX1 base pointer */
32382#define MIPI_CSI2RX1 ((MIPI_CSI2RX_Type *)MIPI_CSI2RX1_BASE)
32383/** Peripheral MIPI_CSI2RX2 base address */
32384#define MIPI_CSI2RX2_BASE (0x30B60000u)
32385/** Peripheral MIPI_CSI2RX2 base pointer */
32386#define MIPI_CSI2RX2 ((MIPI_CSI2RX_Type *)MIPI_CSI2RX2_BASE)
32387/** Array initializer of MIPI_CSI2RX peripheral base addresses */
32388#define MIPI_CSI2RX_BASE_ADDRS { 0u, MIPI_CSI2RX1_BASE, MIPI_CSI2RX2_BASE }
32389/** Array initializer of MIPI_CSI2RX peripheral base pointers */
32390#define MIPI_CSI2RX_BASE_PTRS { (MIPI_CSI2RX_Type *)0u, MIPI_CSI2RX1, MIPI_CSI2RX2 }
32391
32392/*!
32393 * @}
32394 */ /* end of group MIPI_CSI2RX_Peripheral_Access_Layer */
32395
32396
32397/* ----------------------------------------------------------------------------
32398 -- MIPI_DSI_HOST Peripheral Access Layer
32399 ---------------------------------------------------------------------------- */
32400
32401/*!
32402 * @addtogroup MIPI_DSI_HOST_Peripheral_Access_Layer MIPI_DSI_HOST Peripheral Access Layer
32403 * @{
32404 */
32405
32406/** MIPI_DSI_HOST - Register Layout Typedef */
32407typedef struct {
32408 __IO uint32_t DSI_HOST_CFG_NUM_LANES; /**< , offset: 0x0 */
32409 __IO uint32_t DSI_HOST_CFG_NONCONTINUOUS_CLK; /**< , offset: 0x4 */
32410 __IO uint32_t DSI_HOST_CFG_T_PRE; /**< , offset: 0x8 */
32411 __IO uint32_t DSI_HOST_CFG_T_POST; /**< , offset: 0xC */
32412 __IO uint32_t DSI_HOST_CFG_TX_GAP; /**< , offset: 0x10 */
32413 __IO uint32_t DSI_HOST_CFG_AUTOINSERT_EOTP; /**< , offset: 0x14 */
32414 __IO uint32_t DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP; /**< , offset: 0x18 */
32415 __IO uint32_t DSI_HOST_CFG_HTX_TO_COUNT; /**< , offset: 0x1C */
32416 __IO uint32_t DSI_HOST_CFG_LRX_H_TO_COUNT; /**< , offset: 0x20 */
32417 __IO uint32_t DSI_HOST_CFG_BTA_H_TO_COUNT; /**< , offset: 0x24 */
32418 __IO uint32_t DSI_HOST_CFG_TWAKEUP; /**< , offset: 0x28 */
32419 __I uint32_t DSI_HOST_CFG_STATUS_OUT; /**< , offset: 0x2C */
32420 __I uint32_t DSI_HOST_RX_ERROR_STATUS; /**< , offset: 0x30 */
32421} MIPI_DSI_HOST_Type;
32422
32423/* ----------------------------------------------------------------------------
32424 -- MIPI_DSI_HOST Register Masks
32425 ---------------------------------------------------------------------------- */
32426
32427/*!
32428 * @addtogroup MIPI_DSI_HOST_Register_Masks MIPI_DSI_HOST Register Masks
32429 * @{
32430 */
32431
32432/*! @name DSI_HOST_CFG_NUM_LANES - */
32433/*! @{ */
32434#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK (0x3U)
32435#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT (0U)
32436#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK)
32437/*! @} */
32438
32439/*! @name DSI_HOST_CFG_NONCONTINUOUS_CLK - */
32440/*! @{ */
32441#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK (0x1U)
32442#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT (0U)
32443#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK)
32444/*! @} */
32445
32446/*! @name DSI_HOST_CFG_T_PRE - */
32447/*! @{ */
32448#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK (0x7FU)
32449#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT (0U)
32450#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK)
32451/*! @} */
32452
32453/*! @name DSI_HOST_CFG_T_POST - */
32454/*! @{ */
32455#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK (0x7FU)
32456#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT (0U)
32457#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK)
32458/*! @} */
32459
32460/*! @name DSI_HOST_CFG_TX_GAP - */
32461/*! @{ */
32462#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_MASK (0x7FU)
32463#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_SHIFT (0U)
32464#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_MASK)
32465/*! @} */
32466
32467/*! @name DSI_HOST_CFG_AUTOINSERT_EOTP - */
32468/*! @{ */
32469#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK (0x1U)
32470#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT (0U)
32471#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK)
32472/*! @} */
32473
32474/*! @name DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP - */
32475/*! @{ */
32476#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK (0xFFU)
32477#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT (0U)
32478#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK)
32479/*! @} */
32480
32481/*! @name DSI_HOST_CFG_HTX_TO_COUNT - */
32482/*! @{ */
32483#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK (0xFFFFFFU)
32484#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT (0U)
32485#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK)
32486/*! @} */
32487
32488/*! @name DSI_HOST_CFG_LRX_H_TO_COUNT - */
32489/*! @{ */
32490#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK (0xFFFFFFU)
32491#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT (0U)
32492#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK)
32493/*! @} */
32494
32495/*! @name DSI_HOST_CFG_BTA_H_TO_COUNT - */
32496/*! @{ */
32497#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK (0xFFFFFFU)
32498#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT (0U)
32499#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK)
32500/*! @} */
32501
32502/*! @name DSI_HOST_CFG_TWAKEUP - */
32503/*! @{ */
32504#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_MASK (0x7FFFFU)
32505#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_SHIFT (0U)
32506#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_MASK)
32507/*! @} */
32508
32509/*! @name DSI_HOST_CFG_STATUS_OUT - */
32510/*! @{ */
32511#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR_MASK (0x1U)
32512#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR_SHIFT (0U)
32513#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR_MASK)
32514#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR_MASK (0x2U)
32515#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR_SHIFT (1U)
32516#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR_MASK)
32517#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR_MASK (0x4U)
32518#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR_SHIFT (2U)
32519#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR_MASK)
32520#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR_MASK (0x8U)
32521#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR_SHIFT (3U)
32522#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR_MASK)
32523#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR_MASK (0x10U)
32524#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR_SHIFT (4U)
32525#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR_MASK)
32526#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR_MASK (0x20U)
32527#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR_SHIFT (5U)
32528#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR_MASK)
32529#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR_MASK (0x40U)
32530#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR_SHIFT (6U)
32531#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR_MASK)
32532#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT_MASK (0x80U)
32533#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT_SHIFT (7U)
32534#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT_MASK)
32535#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT_MASK (0x100U)
32536#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT_SHIFT (8U)
32537#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT_MASK)
32538#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT_MASK (0x200U)
32539#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT_SHIFT (9U)
32540#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT_MASK)
32541#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR_MASK (0x400U)
32542#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR_SHIFT (10U)
32543#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR_MASK)
32544/*! @} */
32545
32546/*! @name DSI_HOST_RX_ERROR_STATUS - */
32547/*! @{ */
32548#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK (0x7FFU)
32549#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT (0U)
32550#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK)
32551/*! @} */
32552
32553
32554/*!
32555 * @}
32556 */ /* end of group MIPI_DSI_HOST_Register_Masks */
32557
32558
32559/* MIPI_DSI_HOST - Peripheral instance base addresses */
32560/** Peripheral MIPI_DSI_HOST base address */
32561#define MIPI_DSI_HOST_BASE (0x30A10000u)
32562/** Peripheral MIPI_DSI_HOST base pointer */
32563#define MIPI_DSI_HOST ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE)
32564/** Array initializer of MIPI_DSI_HOST peripheral base addresses */
32565#define MIPI_DSI_HOST_BASE_ADDRS { MIPI_DSI_HOST_BASE }
32566/** Array initializer of MIPI_DSI_HOST peripheral base pointers */
32567#define MIPI_DSI_HOST_BASE_PTRS { MIPI_DSI_HOST }
32568
32569/*!
32570 * @}
32571 */ /* end of group MIPI_DSI_HOST_Peripheral_Access_Layer */
32572
32573
32574/* ----------------------------------------------------------------------------
32575 -- MIPI_DSI_HOST_APB_PKT_IF Peripheral Access Layer
32576 ---------------------------------------------------------------------------- */
32577
32578/*!
32579 * @addtogroup MIPI_DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer MIPI_DSI_HOST_APB_PKT_IF Peripheral Access Layer
32580 * @{
32581 */
32582
32583/** MIPI_DSI_HOST_APB_PKT_IF - Register Layout Typedef */
32584typedef struct {
32585 __IO uint32_t DSI_HOST_TX_PAYLOAD; /**< , offset: 0x0 */
32586 __IO uint32_t DSI_HOST_PKT_CONTROL; /**< , offset: 0x4 */
32587 __IO uint32_t DSI_HOST_SEND_PACKET; /**< , offset: 0x8 */
32588 __I uint32_t DSI_HOST_PKT_STATUS; /**< , offset: 0xC */
32589 __I uint32_t DSI_HOST_PKT_FIFO_WR_LEVEL; /**< , offset: 0x10 */
32590 __I uint32_t DSI_HOST_PKT_FIFO_RD_LEVEL; /**< , offset: 0x14 */
32591 __I uint32_t DSI_HOST_PKT_RX_PAYLOAD; /**< , offset: 0x18 */
32592 __I uint32_t DSI_HOST_PKT_RX_PKT_HEADER; /**< , offset: 0x1C */
32593 __I uint32_t DSI_HOST_IRQ_STATUS; /**< , offset: 0x20 */
32594 __I uint32_t DSI_HOST_IRQ_STATUS2; /**< , offset: 0x24 */
32595 __IO uint32_t DSI_HOST_IRQ_MASK; /**< , offset: 0x28 */
32596 __IO uint32_t DSI_HOST_IRQ_MASK2; /**< , offset: 0x2C */
32597} MIPI_DSI_HOST_APB_PKT_IF_Type;
32598
32599/* ----------------------------------------------------------------------------
32600 -- MIPI_DSI_HOST_APB_PKT_IF Register Masks
32601 ---------------------------------------------------------------------------- */
32602
32603/*!
32604 * @addtogroup MIPI_DSI_HOST_APB_PKT_IF_Register_Masks MIPI_DSI_HOST_APB_PKT_IF Register Masks
32605 * @{
32606 */
32607
32608/*! @name DSI_HOST_TX_PAYLOAD - */
32609/*! @{ */
32610#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK (0xFFFFFFFFU)
32611#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT (0U)
32612#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK)
32613/*! @} */
32614
32615/*! @name DSI_HOST_PKT_CONTROL - */
32616/*! @{ */
32617#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK (0x7FFFFFFU)
32618#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT (0U)
32619#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK)
32620/*! @} */
32621
32622/*! @name DSI_HOST_SEND_PACKET - */
32623/*! @{ */
32624#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK (0x1U)
32625#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT (0U)
32626#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK)
32627/*! @} */
32628
32629/*! @name DSI_HOST_PKT_STATUS - */
32630/*! @{ */
32631#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK (0x1FFU)
32632#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT (0U)
32633#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK)
32634/*! @} */
32635
32636/*! @name DSI_HOST_PKT_FIFO_WR_LEVEL - */
32637/*! @{ */
32638#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK (0xFFFFU)
32639#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT (0U)
32640#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK)
32641/*! @} */
32642
32643/*! @name DSI_HOST_PKT_FIFO_RD_LEVEL - */
32644/*! @{ */
32645#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK (0xFFFFU)
32646#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT (0U)
32647#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK)
32648/*! @} */
32649
32650/*! @name DSI_HOST_PKT_RX_PAYLOAD - */
32651/*! @{ */
32652#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK (0xFFFFFFFFU)
32653#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT (0U)
32654#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK)
32655/*! @} */
32656
32657/*! @name DSI_HOST_PKT_RX_PKT_HEADER - */
32658/*! @{ */
32659#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK (0xFFFFFFU)
32660#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT (0U)
32661#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK)
32662/*! @} */
32663
32664/*! @name DSI_HOST_IRQ_STATUS - */
32665/*! @{ */
32666#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK (0xFFFFFFFFU)
32667#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT (0U)
32668#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK)
32669/*! @} */
32670
32671/*! @name DSI_HOST_IRQ_STATUS2 - */
32672/*! @{ */
32673#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK (0x7U)
32674#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT (0U)
32675#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK)
32676/*! @} */
32677
32678/*! @name DSI_HOST_IRQ_MASK - */
32679/*! @{ */
32680#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK (0xFFFFFFFFU)
32681#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT (0U)
32682#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK)
32683/*! @} */
32684
32685/*! @name DSI_HOST_IRQ_MASK2 - */
32686/*! @{ */
32687#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK (0x7U)
32688#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT (0U)
32689#define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK)
32690/*! @} */
32691
32692
32693/*!
32694 * @}
32695 */ /* end of group MIPI_DSI_HOST_APB_PKT_IF_Register_Masks */
32696
32697
32698/* MIPI_DSI_HOST_APB_PKT_IF - Peripheral instance base addresses */
32699/** Peripheral MIPI_DSI_HOST_APB_PKT_IF base address */
32700#define MIPI_DSI_HOST_APB_PKT_IF_BASE (0x30A10280u)
32701/** Peripheral MIPI_DSI_HOST_APB_PKT_IF base pointer */
32702#define MIPI_DSI_HOST_APB_PKT_IF ((MIPI_DSI_HOST_APB_PKT_IF_Type *)MIPI_DSI_HOST_APB_PKT_IF_BASE)
32703/** Array initializer of MIPI_DSI_HOST_APB_PKT_IF peripheral base addresses */
32704#define MIPI_DSI_HOST_APB_PKT_IF_BASE_ADDRS { MIPI_DSI_HOST_APB_PKT_IF_BASE }
32705/** Array initializer of MIPI_DSI_HOST_APB_PKT_IF peripheral base pointers */
32706#define MIPI_DSI_HOST_APB_PKT_IF_BASE_PTRS { MIPI_DSI_HOST_APB_PKT_IF }
32707
32708/*!
32709 * @}
32710 */ /* end of group MIPI_DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer */
32711
32712
32713/* ----------------------------------------------------------------------------
32714 -- MIPI_DSI_HOST_DPI_INTFC Peripheral Access Layer
32715 ---------------------------------------------------------------------------- */
32716
32717/*!
32718 * @addtogroup MIPI_DSI_HOST_DPI_INTFC_Peripheral_Access_Layer MIPI_DSI_HOST_DPI_INTFC Peripheral Access Layer
32719 * @{
32720 */
32721
32722/** MIPI_DSI_HOST_DPI_INTFC - Register Layout Typedef */
32723typedef struct {
32724 __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE; /**< , offset: 0x0 */
32725 __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL; /**< , offset: 0x4 */
32726 __IO uint32_t DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING; /**< , offset: 0x8 */
32727 __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FORMAT; /**< , offset: 0xC */
32728 __IO uint32_t DSI_HOST_CFG_DPI_VSYNC_POLARITY; /**< , offset: 0x10 */
32729 __IO uint32_t DSI_HOST_CFG_DPI_HSYNC_POLARITY; /**< , offset: 0x14 */
32730 __IO uint32_t DSI_HOST_CFG_DPI_VIDEO_MODE; /**< , offset: 0x18 */
32731 __IO uint32_t DSI_HOST_CFG_DPI_HFP; /**< , offset: 0x1C */
32732 __IO uint32_t DSI_HOST_CFG_DPI_HBP; /**< , offset: 0x20 */
32733 __IO uint32_t DSI_HOST_CFG_DPI_HSA; /**< , offset: 0x24 */
32734 __IO uint32_t DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS; /**< , offset: 0x28 */
32735 __IO uint32_t DSI_HOST_CFG_DPI_VBP; /**< , offset: 0x2C */
32736 __IO uint32_t DSI_HOST_CFG_DPI_VFP; /**< , offset: 0x30 */
32737 __IO uint32_t DSI_HOST_CFG_DPI_BLLP_MODE; /**< , offset: 0x34 */
32738 __IO uint32_t DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP; /**< , offset: 0x38 */
32739 __IO uint32_t DSI_HOST_CFG_DPI_VACTIVE; /**< , offset: 0x3C */
32740 __IO uint32_t DSI_HOST_CFG_DPI_VC; /**< , offset: 0x40 */
32741} MIPI_DSI_HOST_DPI_INTFC_Type;
32742
32743/* ----------------------------------------------------------------------------
32744 -- MIPI_DSI_HOST_DPI_INTFC Register Masks
32745 ---------------------------------------------------------------------------- */
32746
32747/*!
32748 * @addtogroup MIPI_DSI_HOST_DPI_INTFC_Register_Masks MIPI_DSI_HOST_DPI_INTFC Register Masks
32749 * @{
32750 */
32751
32752/*! @name DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE - */
32753/*! @{ */
32754#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK (0xFFFFU)
32755#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT (0U)
32756#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK)
32757/*! @} */
32758
32759/*! @name DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL - */
32760/*! @{ */
32761#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK (0xFFFFU)
32762#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT (0U)
32763#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK)
32764/*! @} */
32765
32766/*! @name DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING - */
32767/*! @{ */
32768#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK (0x7U)
32769#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT (0U)
32770#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK)
32771/*! @} */
32772
32773/*! @name DSI_HOST_CFG_DPI_PIXEL_FORMAT - */
32774/*! @{ */
32775#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK (0x3U)
32776#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT (0U)
32777#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK)
32778/*! @} */
32779
32780/*! @name DSI_HOST_CFG_DPI_VSYNC_POLARITY - */
32781/*! @{ */
32782#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK (0x1U)
32783#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT (0U)
32784#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK)
32785/*! @} */
32786
32787/*! @name DSI_HOST_CFG_DPI_HSYNC_POLARITY - */
32788/*! @{ */
32789#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK (0x1U)
32790#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT (0U)
32791#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK)
32792/*! @} */
32793
32794/*! @name DSI_HOST_CFG_DPI_VIDEO_MODE - */
32795/*! @{ */
32796#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK (0x3U)
32797#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT (0U)
32798#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK)
32799/*! @} */
32800
32801/*! @name DSI_HOST_CFG_DPI_HFP - */
32802/*! @{ */
32803#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK (0xFFFFU)
32804#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT (0U)
32805#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK)
32806/*! @} */
32807
32808/*! @name DSI_HOST_CFG_DPI_HBP - */
32809/*! @{ */
32810#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK (0xFFFFU)
32811#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT (0U)
32812#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK)
32813/*! @} */
32814
32815/*! @name DSI_HOST_CFG_DPI_HSA - */
32816/*! @{ */
32817#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK (0xFFFFU)
32818#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT (0U)
32819#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK)
32820/*! @} */
32821
32822/*! @name DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS - */
32823/*! @{ */
32824#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK (0x1U)
32825#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT (0U)
32826#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK)
32827/*! @} */
32828
32829/*! @name DSI_HOST_CFG_DPI_VBP - */
32830/*! @{ */
32831#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK (0xFFU)
32832#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT (0U)
32833#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK)
32834/*! @} */
32835
32836/*! @name DSI_HOST_CFG_DPI_VFP - */
32837/*! @{ */
32838#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK (0xFFU)
32839#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT (0U)
32840#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK)
32841/*! @} */
32842
32843/*! @name DSI_HOST_CFG_DPI_BLLP_MODE - */
32844/*! @{ */
32845#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK (0x1U)
32846#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT (0U)
32847#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK)
32848/*! @} */
32849
32850/*! @name DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP - */
32851/*! @{ */
32852#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK (0x1U)
32853#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT (0U)
32854#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK)
32855/*! @} */
32856
32857/*! @name DSI_HOST_CFG_DPI_VACTIVE - */
32858/*! @{ */
32859#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK (0x3FFFU)
32860#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT (0U)
32861#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK)
32862/*! @} */
32863
32864/*! @name DSI_HOST_CFG_DPI_VC - */
32865/*! @{ */
32866#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK (0x3U)
32867#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT (0U)
32868#define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK)
32869/*! @} */
32870
32871
32872/*!
32873 * @}
32874 */ /* end of group MIPI_DSI_HOST_DPI_INTFC_Register_Masks */
32875
32876
32877/* MIPI_DSI_HOST_DPI_INTFC - Peripheral instance base addresses */
32878/** Peripheral MIPI_DSI_HOST_DPI_INTFC base address */
32879#define MIPI_DSI_HOST_DPI_INTFC_BASE (0x30A10200u)
32880/** Peripheral MIPI_DSI_HOST_DPI_INTFC base pointer */
32881#define MIPI_DSI_HOST_DPI_INTFC ((MIPI_DSI_HOST_DPI_INTFC_Type *)MIPI_DSI_HOST_DPI_INTFC_BASE)
32882/** Array initializer of MIPI_DSI_HOST_DPI_INTFC peripheral base addresses */
32883#define MIPI_DSI_HOST_DPI_INTFC_BASE_ADDRS { MIPI_DSI_HOST_DPI_INTFC_BASE }
32884/** Array initializer of MIPI_DSI_HOST_DPI_INTFC peripheral base pointers */
32885#define MIPI_DSI_HOST_DPI_INTFC_BASE_PTRS { MIPI_DSI_HOST_DPI_INTFC }
32886
32887/*!
32888 * @}
32889 */ /* end of group MIPI_DSI_HOST_DPI_INTFC_Peripheral_Access_Layer */
32890
32891
32892/* ----------------------------------------------------------------------------
32893 -- MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC Peripheral Access Layer
32894 ---------------------------------------------------------------------------- */
32895
32896/*!
32897 * @addtogroup MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Peripheral_Access_Layer MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC Peripheral Access Layer
32898 * @{
32899 */
32900
32901/** MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC - Register Layout Typedef */
32902typedef struct {
32903 __IO uint32_t DPHY_PD_DPHY; /**< , offset: 0x0 */
32904 __IO uint32_t DPHY_M_PRG_HS_PREPARE; /**< , offset: 0x4 */
32905 __IO uint32_t DPHY_MC_PRG_HS_PREPARE; /**< , offset: 0x8 */
32906 __IO uint32_t DPHY_M_PRG_HS_ZERO; /**< , offset: 0xC */
32907 __IO uint32_t DPHY_MC_PRG_HS_ZERO; /**< , offset: 0x10 */
32908 __IO uint32_t DPHY_M_PRG_HS_TRAIL; /**< , offset: 0x14 */
32909 __IO uint32_t DPHY_MC_PRG_HS_TRAIL; /**< , offset: 0x18 */
32910 __IO uint32_t DPHY_PD_PLL; /**< , offset: 0x1C */
32911 __IO uint32_t DPHY_TST; /**< , offset: 0x20 */
32912 __IO uint32_t DPHY_CN; /**< , offset: 0x24 */
32913 __IO uint32_t DPHY_CM; /**< , offset: 0x28 */
32914 __IO uint32_t DPHY_CO; /**< , offset: 0x2C */
32915 __I uint32_t DPHY_LOCK; /**< , offset: 0x30 */
32916 __IO uint32_t DPHY_LOCK_BYP; /**< , offset: 0x34 */
32917 __IO uint32_t DPHY_RTERM_SEL; /**< , offset: 0x38 */
32918 __IO uint32_t DPHY_AUTO_PD_EN; /**< , offset: 0x3C */
32919 __IO uint32_t DPHY_RXLPRP; /**< , offset: 0x40 */
32920 __IO uint32_t DPHY_RXCDRP; /**< , offset: 0x44 */
32921} MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Type;
32922
32923/* ----------------------------------------------------------------------------
32924 -- MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC Register Masks
32925 ---------------------------------------------------------------------------- */
32926
32927/*!
32928 * @addtogroup MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Register_Masks MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC Register Masks
32929 * @{
32930 */
32931
32932/*! @name DPHY_PD_DPHY - */
32933/*! @{ */
32934#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy_MASK (0x1U)
32935#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy_SHIFT (0U)
32936#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy_MASK)
32937/*! @} */
32938
32939/*! @name DPHY_M_PRG_HS_PREPARE - */
32940/*! @{ */
32941#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK (0x3U)
32942#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT (0U)
32943/*! dphy_m_prg_hs_prepare - DPHY m_PRG_HS_PREPARE input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
32944 * 0b00..1
32945 * 0b01..1.5
32946 * 0b10..2
32947 * 0b11..2.5
32948 */
32949#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK)
32950/*! @} */
32951
32952/*! @name DPHY_MC_PRG_HS_PREPARE - */
32953/*! @{ */
32954#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK (0x1U)
32955#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT (0U)
32956/*! dphy_mc_prg_hs_prepare - DPHY mc_PRG_HS_PREPARE input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
32957 * 0b0..1
32958 * 0b1..1.5
32959 */
32960#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK)
32961/*! @} */
32962
32963/*! @name DPHY_M_PRG_HS_ZERO - */
32964/*! @{ */
32965#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK (0x1FU)
32966#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT (0U)
32967/*! dphy_m_prg_hs_zero - DPHY m_PRG_HS_ZERO input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
32968 * 0b00000..0
32969 * 0b00001..1
32970 * 0b00010..2
32971 * 0b00011..3
32972 * 0b00100..4
32973 * 0b00101..5
32974 * 0b00110..6
32975 * 0b00111..7
32976 * 0b01000..8
32977 * 0b01001..9
32978 * 0b01010..10
32979 * 0b01011..11
32980 * 0b01100..12
32981 * 0b01101..13
32982 * 0b01110..14
32983 * 0b01111..15
32984 * 0b10000..16
32985 * 0b10001..17
32986 * 0b10010..18
32987 * 0b10011..19
32988 * 0b10100..20
32989 * 0b10101..21
32990 * 0b10110..22
32991 * 0b10111..23
32992 * 0b11000..24
32993 * 0b11001..25
32994 * 0b11010..26
32995 * 0b11011..27
32996 * 0b11100..28
32997 * 0b11101..29
32998 * 0b11110..30
32999 * 0b11111..31
33000 */
33001#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK)
33002/*! @} */
33003
33004/*! @name DPHY_MC_PRG_HS_ZERO - */
33005/*! @{ */
33006#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK (0x3FU)
33007#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT (0U)
33008/*! dphy_mc_prg_hs_zero - DPHY mc_PRG_HS_ZERO input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
33009 * 0b100000..32
33010 * 0b100001..33
33011 * 0b100010..34
33012 * 0b100011..35
33013 * 0b100100..36
33014 * 0b100101..37
33015 * 0b100110..38
33016 * 0b100111..39
33017 * 0b101000..40
33018 * 0b101001..41
33019 * 0b101010..42
33020 * 0b101011..43
33021 * 0b101100..44
33022 * 0b101101..45
33023 * 0b101110..46
33024 * 0b101111..47
33025 * 0b110000..48
33026 * 0b110001..49
33027 * 0b110010..50
33028 * 0b110011..51
33029 * 0b110100..52
33030 * 0b110101..53
33031 * 0b110110..54
33032 * 0b110111..55
33033 * 0b111000..56
33034 * 0b111001..57
33035 * 0b111010..58
33036 * 0b111011..59
33037 * 0b111100..60
33038 * 0b111101..61
33039 * 0b111110..62
33040 * 0b111111..63
33041 */
33042#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK)
33043/*! @} */
33044
33045/*! @name DPHY_M_PRG_HS_TRAIL - */
33046/*! @{ */
33047#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK (0xFU)
33048#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT (0U)
33049/*! dphy_m_prg_hs_trail - DPHY m_PRG_HS_TRAIL input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
33050 * 0b0000..0
33051 * 0b0001..1
33052 * 0b0010..2
33053 * 0b0011..3
33054 * 0b0100..4
33055 * 0b0101..5
33056 * 0b0110..6
33057 * 0b0111..7
33058 * 0b1000..8
33059 * 0b1001..9
33060 * 0b1010..10
33061 * 0b1011..11
33062 * 0b1100..12
33063 * 0b1101..13
33064 * 0b1110..14
33065 * 0b1111..15
33066 */
33067#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK)
33068/*! @} */
33069
33070/*! @name DPHY_MC_PRG_HS_TRAIL - */
33071/*! @{ */
33072#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK (0xFU)
33073#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT (0U)
33074/*! dphy_mc_prg_hs_trail - DPHY mc_PRG_HS_TRAIL input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section.
33075 * 0b0000..0
33076 * 0b0001..1
33077 * 0b0010..2
33078 * 0b0011..3
33079 * 0b0100..4
33080 * 0b0101..5
33081 * 0b0110..6
33082 * 0b0111..7
33083 * 0b1000..8
33084 * 0b1001..9
33085 * 0b1010..10
33086 * 0b1011..11
33087 * 0b1100..12
33088 * 0b1101..13
33089 * 0b1110..14
33090 * 0b1111..15
33091 */
33092#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK)
33093/*! @} */
33094
33095/*! @name DPHY_PD_PLL - */
33096/*! @{ */
33097#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD_MASK (0x1U)
33098#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD_SHIFT (0U)
33099#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD_MASK)
33100/*! @} */
33101
33102/*! @name DPHY_TST - */
33103/*! @{ */
33104#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST_MASK (0x3FU)
33105#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST_SHIFT (0U)
33106#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST_MASK)
33107/*! @} */
33108
33109/*! @name DPHY_CN - */
33110/*! @{ */
33111#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN_MASK (0x1FU)
33112#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN_SHIFT (0U)
33113/*! CN
33114 * 0b11111..Divide by 1
33115 * 0b00000..Divide by 2
33116 * 0b10000..Divide by 3
33117 * 0b11000..Divide by 4
33118 * 0b11100..Divide by 5
33119 * 0b01110..Divide by 6
33120 * 0b00111..Divide by 7
33121 * 0b10011..Divide by 8
33122 * 0b01001..Divide by 9
33123 * 0b00100..Divide by 10
33124 * 0b00010..Divide by 11
33125 * 0b10001..Divide by 12
33126 * 0b01000..Divide by 13
33127 * 0b10100..Divide by 14
33128 * 0b01010..Divide by 15
33129 * 0b10101..Divide by 16
33130 * 0b11010..Divide by 17
33131 * 0b11101..Divide by 18
33132 * 0b11110..Divide by 19
33133 * 0b01111..Divide by 20
33134 * 0b10111..Divide by 21
33135 * 0b11011..Divide by 22
33136 * 0b01101..Divide by 23
33137 * 0b10110..Divide by 24
33138 * 0b01011..Divide by 25
33139 * 0b00101..Divide by 26
33140 * 0b10010..Divide by 27
33141 * 0b11001..Divide by 28
33142 * 0b01100..Divide by 29
33143 * 0b00110..Divide by 30
33144 * 0b00011..Divide by 31
33145 * 0b00001..Divide by 32
33146 */
33147#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN_MASK)
33148/*! @} */
33149
33150/*! @name DPHY_CM - */
33151/*! @{ */
33152#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM_MASK (0xFFU)
33153#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM_SHIFT (0U)
33154/*! CM
33155 * 0b111x0000..Divide by 16
33156 * 0b111x1111..Divide by 31
33157 * 0b11000000..Divide by 32
33158 * 0b11011111..Divide by 63
33159 * 0b10000000..Divide by 64
33160 * 0b10111111..Divide by 127
33161 * 0b00000000..Divide by 128
33162 * 0b01111111..Divide by 255
33163 */
33164#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM_MASK)
33165/*! @} */
33166
33167/*! @name DPHY_CO - */
33168/*! @{ */
33169#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO_MASK (0x3U)
33170#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO_SHIFT (0U)
33171/*! CO
33172 * 0b00..Divide by 1
33173 * 0b01..Divide by 2
33174 * 0b10..Divide by 4
33175 * 0b11..Divide by 8
33176 */
33177#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO_MASK)
33178/*! @} */
33179
33180/*! @name DPHY_LOCK - */
33181/*! @{ */
33182#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK_MASK (0x1U)
33183#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK_SHIFT (0U)
33184#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK_MASK)
33185/*! @} */
33186
33187/*! @name DPHY_LOCK_BYP - */
33188/*! @{ */
33189#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp_MASK (0x1U)
33190#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp_SHIFT (0U)
33191#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp_MASK)
33192/*! @} */
33193
33194/*! @name DPHY_RTERM_SEL - */
33195/*! @{ */
33196#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel_MASK (0x1U)
33197#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel_SHIFT (0U)
33198#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel_MASK)
33199/*! @} */
33200
33201/*! @name DPHY_AUTO_PD_EN - */
33202/*! @{ */
33203#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK (0x1U)
33204#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT (0U)
33205#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK)
33206/*! @} */
33207
33208/*! @name DPHY_RXLPRP - */
33209/*! @{ */
33210#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp_MASK (0x3U)
33211#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp_SHIFT (0U)
33212#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp_MASK)
33213/*! @} */
33214
33215/*! @name DPHY_RXCDRP - */
33216/*! @{ */
33217#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp_MASK (0x3U)
33218#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp_SHIFT (0U)
33219#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp_MASK)
33220/*! @} */
33221
33222
33223/*!
33224 * @}
33225 */ /* end of group MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Register_Masks */
33226
33227
33228/* MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC - Peripheral instance base addresses */
33229/** Peripheral MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC base address */
33230#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_BASE (0x30A10300u)
33231/** Peripheral MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC base pointer */
33232#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC ((MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Type *)MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_BASE)
33233/** Array initializer of MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC peripheral base
33234 * addresses */
33235#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_BASE_ADDRS { MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_BASE }
33236/** Array initializer of MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC peripheral base
33237 * pointers */
33238#define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_BASE_PTRS { MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC }
33239
33240/*!
33241 * @}
33242 */ /* end of group MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Peripheral_Access_Layer */
33243
33244/*!
33245 * @brief Power mode on the other side definition.
33246 */
33247typedef enum _mu_power_mode
33248{
33249 kMU_PowerModeRun = 0x00U, /*!< Run mode. */
33250 kMU_PowerModeWait = 0x01U, /*!< WAIT mode. */
33251 kMU_PowerModeStop = 0x03U, /*!< STOP mode. */
33252} mu_power_mode_t;
33253
33254
33255/* ----------------------------------------------------------------------------
33256 -- MU Peripheral Access Layer
33257 ---------------------------------------------------------------------------- */
33258
33259/*!
33260 * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
33261 * @{
33262 */
33263
33264/** MU - Register Layout Typedef */
33265typedef struct {
33266 __IO uint32_t TR[4]; /**< Processor B Transmit Register 0..Processor B Transmit Register 3, array offset: 0x0, array step: 0x4 */
33267 __I uint32_t RR[4]; /**< Processor B Receive Register 0..Processor B Receive Register 3, array offset: 0x10, array step: 0x4 */
33268 __IO uint32_t SR; /**< Processor B Status Register, offset: 0x20 */
33269 __IO uint32_t CR; /**< Processor B Control Register, offset: 0x24 */
33270} MU_Type;
33271
33272/* ----------------------------------------------------------------------------
33273 -- MU Register Masks
33274 ---------------------------------------------------------------------------- */
33275
33276/*!
33277 * @addtogroup MU_Register_Masks MU Register Masks
33278 * @{
33279 */
33280
33281/*! @name TR - Processor B Transmit Register 0..Processor B Transmit Register 3 */
33282/*! @{ */
33283#define MU_TR_BTR0_MASK (0xFFFFFFFFU)
33284#define MU_TR_BTR0_SHIFT (0U)
33285#define MU_TR_BTR0(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR0_SHIFT)) & MU_TR_BTR0_MASK)
33286#define MU_TR_BTR1_MASK (0xFFFFFFFFU)
33287#define MU_TR_BTR1_SHIFT (0U)
33288#define MU_TR_BTR1(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR1_SHIFT)) & MU_TR_BTR1_MASK)
33289#define MU_TR_BTR2_MASK (0xFFFFFFFFU)
33290#define MU_TR_BTR2_SHIFT (0U)
33291#define MU_TR_BTR2(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
33292#define MU_TR_BTR3_MASK (0xFFFFFFFFU)
33293#define MU_TR_BTR3_SHIFT (0U)
33294#define MU_TR_BTR3(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR3_SHIFT)) & MU_TR_BTR3_MASK)
33295/*! @} */
33296
33297/* The count of MU_TR */
33298#define MU_TR_COUNT (4U)
33299
33300/*! @name RR - Processor B Receive Register 0..Processor B Receive Register 3 */
33301/*! @{ */
33302#define MU_RR_BRR0_MASK (0xFFFFFFFFU)
33303#define MU_RR_BRR0_SHIFT (0U)
33304#define MU_RR_BRR0(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR0_SHIFT)) & MU_RR_BRR0_MASK)
33305#define MU_RR_BRR1_MASK (0xFFFFFFFFU)
33306#define MU_RR_BRR1_SHIFT (0U)
33307#define MU_RR_BRR1(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR1_SHIFT)) & MU_RR_BRR1_MASK)
33308#define MU_RR_BRR2_MASK (0xFFFFFFFFU)
33309#define MU_RR_BRR2_SHIFT (0U)
33310#define MU_RR_BRR2(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR2_SHIFT)) & MU_RR_BRR2_MASK)
33311#define MU_RR_BRR3_MASK (0xFFFFFFFFU)
33312#define MU_RR_BRR3_SHIFT (0U)
33313#define MU_RR_BRR3(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR3_SHIFT)) & MU_RR_BRR3_MASK)
33314/*! @} */
33315
33316/* The count of MU_RR */
33317#define MU_RR_COUNT (4U)
33318
33319/*! @name SR - Processor B Status Register */
33320/*! @{ */
33321#define MU_SR_Fn_MASK (0x7U)
33322#define MU_SR_Fn_SHIFT (0U)
33323/*! Fn
33324 * 0b000..ABFn bit in ACR register is written 0 (default).
33325 * 0b001..ABFn bit in ACR register is written 1.
33326 */
33327#define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)
33328#define MU_SR_EP_MASK (0x10U)
33329#define MU_SR_EP_SHIFT (4U)
33330/*! EP
33331 * 0b0..The Processor B-side event is not pending (default).
33332 * 0b1..The Processor B-side event is pending.
33333 */
33334#define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)
33335#define MU_SR_APM_MASK (0x60U)
33336#define MU_SR_APM_SHIFT (5U)
33337/*! APM
33338 * 0b00..The System is in Run Mode.
33339 * 0b01..The System is in WAIT Mode.
33340 * 0b10..Reserved.
33341 * 0b11..The System is in STOP Mode.
33342 */
33343#define MU_SR_APM(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_APM_SHIFT)) & MU_SR_APM_MASK)
33344#define MU_SR_ARS_MASK (0x80U)
33345#define MU_SR_ARS_SHIFT (7U)
33346/*! ARS
33347 * 0b0..The Processor A or the Processor A-side of the MU is not in reset.
33348 * 0b1..The Processor A or the Processor A-side of the MU is in reset.
33349 */
33350#define MU_SR_ARS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_ARS_SHIFT)) & MU_SR_ARS_MASK)
33351#define MU_SR_FUP_MASK (0x100U)
33352#define MU_SR_FUP_SHIFT (8U)
33353/*! FUP
33354 * 0b0..No flags updated, initiated by the Processor B, in progress (default)
33355 * 0b1..Processor B initiated flags update, processing
33356 */
33357#define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)
33358#define MU_SR_TEn_MASK (0xF00000U)
33359#define MU_SR_TEn_SHIFT (20U)
33360/*! TEn
33361 * 0b0000..BTRn register is not empty.
33362 * 0b0001..BTRn register is empty (default).
33363 */
33364#define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)
33365#define MU_SR_RFn_MASK (0xF000000U)
33366#define MU_SR_RFn_SHIFT (24U)
33367/*! RFn
33368 * 0b0000..BRRn register is not full (default).
33369 * 0b0001..BRRn register has received data from ATRn register and is ready to be read by the Processor B.
33370 */
33371#define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)
33372#define MU_SR_GIPn_MASK (0xF0000000U)
33373#define MU_SR_GIPn_SHIFT (28U)
33374/*! GIPn
33375 * 0b0000..Processor B general purpose interrupt n is not pending. (default)
33376 * 0b0001..Processor B general purpose interrupt n is pending.
33377 */
33378#define MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)
33379/*! @} */
33380
33381/*! @name CR - Processor B Control Register */
33382/*! @{ */
33383#define MU_CR_BAFn_MASK (0x7U)
33384#define MU_CR_BAFn_SHIFT (0U)
33385/*! BAFn
33386 * 0b000..Clears the Fn bit in the ASR register.
33387 * 0b001..Sets the Fn bit in the ASR register.
33388 */
33389#define MU_CR_BAFn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_BAFn_SHIFT)) & MU_CR_BAFn_MASK)
33390#define MU_CR_HRM_MASK (0x10U)
33391#define MU_CR_HRM_SHIFT (4U)
33392/*! HRM
33393 * 0b0..BHR bit in ACR is not masked, enables the hardware reset to the Processor B (default after hardware reset).
33394 * 0b1..BHR bit in ACR is masked, disables the hardware reset request to the Processor B.
33395 */
33396#define MU_CR_HRM(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_HRM_SHIFT)) & MU_CR_HRM_MASK)
33397#define MU_CR_GIRn_MASK (0xF0000U)
33398#define MU_CR_GIRn_SHIFT (16U)
33399/*! GIRn
33400 * 0b0000..Processor B General Interrupt n is not requested to the Processor A (default).
33401 * 0b0001..Processor B General Interrupt n is requested to the Processor A.
33402 */
33403#define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
33404#define MU_CR_TIEn_MASK (0xF00000U)
33405#define MU_CR_TIEn_SHIFT (20U)
33406/*! TIEn
33407 * 0b0000..Disables Processor B Transmit Interrupt n. (default)
33408 * 0b0001..Enables Processor B Transmit Interrupt n.
33409 */
33410#define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)
33411#define MU_CR_RIEn_MASK (0xF000000U)
33412#define MU_CR_RIEn_SHIFT (24U)
33413/*! RIEn
33414 * 0b0000..Disables Processor B Receive Interrupt n. (default)
33415 * 0b0001..Enables Processor B Receive Interrupt n.
33416 */
33417#define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)
33418#define MU_CR_GIEn_MASK (0xF0000000U)
33419#define MU_CR_GIEn_SHIFT (28U)
33420/*! GIEn
33421 * 0b0000..Disables Processor B General Interrupt n. (default)
33422 * 0b0001..Enables Processor B General Interrupt n.
33423 */
33424#define MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)
33425/*! @} */
33426
33427
33428/*!
33429 * @}
33430 */ /* end of group MU_Register_Masks */
33431
33432
33433/* MU - Peripheral instance base addresses */
33434/** Peripheral MUB base address */
33435#define MUB_BASE (0x30AB0000u)
33436/** Peripheral MUB base pointer */
33437#define MUB ((MU_Type *)MUB_BASE)
33438/** Array initializer of MU peripheral base addresses */
33439#define MU_BASE_ADDRS { MUB_BASE }
33440/** Array initializer of MU peripheral base pointers */
33441#define MU_BASE_PTRS { MUB }
33442/** Interrupt vectors for the MU peripheral type */
33443#define MU_IRQS { MU_M4_IRQn }
33444/* Backward compatibility */
33445#define MU_SR_PM_MASK MU_SR_APM_MASK
33446#define MU_SR_PM_SHIFT MU_SR_APM_SHIFT
33447#define MU_SR_PM(x) MU_SR_APM(x)
33448#define MU_SR_RS_MASK MU_SR_ARS_MASK
33449#define MU_SR_RS_SHIFT MU_SR_ARS_SHIFT
33450#define MU_SR_RS(x) MU_SR_ARS(x)
33451#define MU_CR_Fn_MASK MU_CR_BAFn_MASK
33452#define MU_CR_Fn_SHIFT MU_CR_BAFn_SHIFT
33453#define MU_CR_Fn(x) MU_CR_BAFn(x)
33454
33455
33456/*!
33457 * @}
33458 */ /* end of group MU_Peripheral_Access_Layer */
33459
33460
33461/* ----------------------------------------------------------------------------
33462 -- OCOTP Peripheral Access Layer
33463 ---------------------------------------------------------------------------- */
33464
33465/*!
33466 * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
33467 * @{
33468 */
33469
33470/** OCOTP - Register Layout Typedef */
33471typedef struct {
33472 __IO uint32_t CTRL; /**< OTP Controller Control Register, offset: 0x0 */
33473 __IO uint32_t CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */
33474 __IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */
33475 __IO uint32_t CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */
33476 __IO uint32_t TIMING; /**< OTP Controller Timing Register, offset: 0x10 */
33477 uint8_t RESERVED_0[12];
33478 __IO uint32_t DATA; /**< OTP Controller Write Data Register, offset: 0x20 */
33479 uint8_t RESERVED_1[12];
33480 __IO uint32_t READ_CTRL; /**< OTP Controller Write Data Register, offset: 0x30 */
33481 uint8_t RESERVED_2[12];
33482 __IO uint32_t READ_FUSE_DATA; /**< OTP Controller Read Data Register, offset: 0x40 */
33483 uint8_t RESERVED_3[12];
33484 __IO uint32_t SW_STICKY; /**< Sticky bit Register, offset: 0x50 */
33485 uint8_t RESERVED_4[12];
33486 __IO uint32_t SCS; /**< Software Controllable Signals Register, offset: 0x60 */
33487 __IO uint32_t SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */
33488 __IO uint32_t SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */
33489 __IO uint32_t SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */
33490 uint8_t RESERVED_5[32];
33491 __I uint32_t VERSION; /**< OTP Controller Version Register, offset: 0x90 */
33492 uint8_t RESERVED_6[876];
33493 __I uint32_t LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */
33494 uint8_t RESERVED_7[12];
33495 __IO uint32_t TESTER0; /**< Value of OTP Bank0 Word1 (Tester Info.), offset: 0x410 */
33496 uint8_t RESERVED_8[12];
33497 __IO uint32_t TESTER1; /**< Value of OTP Bank0 Word2 (tester Info.), offset: 0x420 */
33498 uint8_t RESERVED_9[12];
33499 __IO uint32_t TESTER2; /**< Value of OTP Bank0 Word3 (Tester Info.), offset: 0x430 */
33500 uint8_t RESERVED_10[12];
33501 __IO uint32_t TESTER3; /**< Value of OTP Bank1 Word0 (Tester Info.), offset: 0x440 */
33502 uint8_t RESERVED_11[12];
33503 __IO uint32_t TESTER4; /**< Value of OTP Bank1 Word1 (Tester Info.), offset: 0x450 */
33504 uint8_t RESERVED_12[12];
33505 __IO uint32_t TESTER5; /**< Value of OTP Bank1 Word2 (Tester Info.), offset: 0x460 */
33506 uint8_t RESERVED_13[12];
33507 __IO uint32_t BOOT_CFG0; /**< Value of OTP Bank1 Word3 (Boot Configuration Info.), offset: 0x470 */
33508 uint8_t RESERVED_14[12];
33509 __IO uint32_t BOOT_CFG1; /**< Value of OTP Bank2 Word0 (Boot Configuration Info.), offset: 0x480 */
33510 uint8_t RESERVED_15[12];
33511 __IO uint32_t BOOT_CFG2; /**< Value of OTP Bank2 Word1 (Boot Configuration Info.), offset: 0x490 */
33512 uint8_t RESERVED_16[12];
33513 __IO uint32_t BOOT_CFG3; /**< Value of OTP Bank2 Word2 (Boot Configuration Info.), offset: 0x4A0 */
33514 uint8_t RESERVED_17[12];
33515 __IO uint32_t BOOT_CFG4; /**< Value of OTP Bank2 Word3 (BOOT Configuration Info.), offset: 0x4B0 */
33516 uint8_t RESERVED_18[12];
33517 __IO uint32_t MEM_TRIM0; /**< Value of OTP Bank3 Word0 (Memory Related Info.), offset: 0x4C0 */
33518 uint8_t RESERVED_19[12];
33519 __IO uint32_t MEM_TRIM1; /**< Value of OTP Bank3 Word1 (Memory Related Info.), offset: 0x4D0 */
33520 uint8_t RESERVED_20[12];
33521 __IO uint32_t ANA0; /**< Value of OTP Bank3 Word2 (Analog Info.), offset: 0x4E0 */
33522 uint8_t RESERVED_21[12];
33523 __IO uint32_t ANA1; /**< Value of OTP Bank3 Word3 (Analog Info.), offset: 0x4F0 */
33524 uint8_t RESERVED_22[140];
33525 __IO uint32_t SRK0; /**< Shadow Register for OTP Bank6 Word0 (SRK Hash), offset: 0x580 */
33526 uint8_t RESERVED_23[12];
33527 __IO uint32_t SRK1; /**< Shadow Register for OTP Bank6 Word1 (SRK Hash), offset: 0x590 */
33528 uint8_t RESERVED_24[12];
33529 __IO uint32_t SRK2; /**< Shadow Register for OTP Bank6 Word2 (SRK Hash), offset: 0x5A0 */
33530 uint8_t RESERVED_25[12];
33531 __IO uint32_t SRK3; /**< Shadow Register for OTP Bank6 Word3 (SRK Hash), offset: 0x5B0 */
33532 uint8_t RESERVED_26[12];
33533 __IO uint32_t SRK4; /**< Shadow Register for OTP Bank7 Word0 (SRK Hash), offset: 0x5C0 */
33534 uint8_t RESERVED_27[12];
33535 __IO uint32_t SRK5; /**< Shadow Register for OTP Bank7 Word1 (SRK Hash), offset: 0x5D0 */
33536 uint8_t RESERVED_28[12];
33537 __IO uint32_t SRK6; /**< Shadow Register for OTP Bank7 Word2 (SRK Hash), offset: 0x5E0 */
33538 uint8_t RESERVED_29[12];
33539 __IO uint32_t SRK7; /**< Shadow Register for OTP Bank7 Word3 (SRK Hash), offset: 0x5F0 */
33540 uint8_t RESERVED_30[12];
33541 __IO uint32_t SJC_RESP0; /**< Value of OTP Bank8 Word0 (Secure JTAG Response Field), offset: 0x600 */
33542 uint8_t RESERVED_31[12];
33543 __IO uint32_t SJC_RESP1; /**< Value of OTP Bank8 Word1 (Secure JTAG Response Field), offset: 0x610 */
33544 uint8_t RESERVED_32[12];
33545 __IO uint32_t USB_ID; /**< Value of OTP Bank8 Word2 (USB ID info), offset: 0x620 */
33546 uint8_t RESERVED_33[12];
33547 __IO uint32_t FIELD_RETURN; /**< Value of OTP Bank5 Word6 (Field Return), offset: 0x630 */
33548 uint8_t RESERVED_34[12];
33549 __IO uint32_t MAC_ADDR0; /**< Value of OTP Bank9 Word0 (MAC Address), offset: 0x640 */
33550 uint8_t RESERVED_35[12];
33551 __IO uint32_t MAC_ADDR1; /**< Value of OTP Bank9 Word1 (MAC Address), offset: 0x650 */
33552 uint8_t RESERVED_36[12];
33553 __IO uint32_t MAC_ADDR2; /**< Value of OTP Bank9 Word2 (MAC Address), offset: 0x660 */
33554 uint8_t RESERVED_37[12];
33555 __IO uint32_t SRK_REVOKE; /**< Value of OTP Bank9 Word3 (SRK Revoke), offset: 0x670 */
33556 uint8_t RESERVED_38[12];
33557 __IO uint32_t MAU_KEY0; /**< Shadow Register for OTP Bank10 Word0 (MAU Key), offset: 0x680 */
33558 uint8_t RESERVED_39[12];
33559 __IO uint32_t MAU_KEY1; /**< Shadow Register for OTP Bank10 Word1 (MAU Key), offset: 0x690 */
33560 uint8_t RESERVED_40[12];
33561 __IO uint32_t MAU_KEY2; /**< Shadow Register for OTP Bank10 Word2 (MAU Key), offset: 0x6A0 */
33562 uint8_t RESERVED_41[12];
33563 __IO uint32_t MAU_KEY3; /**< Shadow Register for OTP Bank10 Word3 (MAU Key), offset: 0x6B0 */
33564 uint8_t RESERVED_42[12];
33565 __IO uint32_t MAU_KEY4; /**< Shadow Register for OTP Bank11 Word0 (MAU Key), offset: 0x6C0 */
33566 uint8_t RESERVED_43[12];
33567 __IO uint32_t MAU_KEY5; /**< Shadow Register for OTP Bank11 Word1 (MAU Key), offset: 0x6D0 */
33568 uint8_t RESERVED_44[12];
33569 __IO uint32_t MAU_KEY6; /**< Shadow Register for OTP Bank11 Word2 (MAU Key), offset: 0x6E0 */
33570 uint8_t RESERVED_45[12];
33571 __IO uint32_t MAU_KEY7; /**< Shadow Register for OTP Bank11 Word3 (MAU Key), offset: 0x6F0 */
33572 uint8_t RESERVED_46[140];
33573 __IO uint32_t GP10; /**< Value of OTP Bank14 Word0 (), offset: 0x780 */
33574 uint8_t RESERVED_47[12];
33575 __IO uint32_t GP11; /**< Value of OTP Bank14 Word1 (), offset: 0x790 */
33576 uint8_t RESERVED_48[12];
33577 __IO uint32_t GP20; /**< Value of OTP Bank14 Word2 (), offset: 0x7A0 */
33578 uint8_t RESERVED_49[12];
33579 __IO uint32_t GP21; /**< Value of OTP Bank14 Word3 (), offset: 0x7B0 */
33580 uint8_t RESERVED_50[12];
33581 __IO uint32_t GP_CRC0; /**< Value of OTP Bank15 Word0 (CRC Key), offset: 0x7C0 */
33582 uint8_t RESERVED_51[12];
33583 __IO uint32_t GP_CRC1; /**< Value of OTP Bank15 Word1 (CRC Key), offset: 0x7D0 */
33584 uint8_t RESERVED_52[12];
33585 __IO uint32_t GP_CRC2; /**< Value of OTP Bank15 Word2 (CRC Key), offset: 0x7E0 */
33586 uint8_t RESERVED_53[12];
33587 __IO uint32_t GROUP_MASK; /**< Value of OTP Bank15 Word3 (CRC Key), offset: 0x7F0 */
33588 uint8_t RESERVED_54[12];
33589 __IO uint32_t HDMI_FW_SRK0; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x800 */
33590 uint8_t RESERVED_55[12];
33591 __IO uint32_t HDMI_FW_SRK1; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0x810 */
33592 uint8_t RESERVED_56[12];
33593 __IO uint32_t HDMI_FW_SRK2; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x820 */
33594 uint8_t RESERVED_57[12];
33595 __IO uint32_t HDMI_FW_SRK3; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x830 */
33596 uint8_t RESERVED_58[12];
33597 __IO uint32_t HDMI_FW_SRK4; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x840 */
33598 uint8_t RESERVED_59[12];
33599 __IO uint32_t HDMI_FW_SRK5; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x850 */
33600 uint8_t RESERVED_60[12];
33601 __IO uint32_t HDMI_FW_SRK6; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x860 */
33602 uint8_t RESERVED_61[12];
33603 __IO uint32_t HDMI_FW_SRK7; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x870 */
33604 uint8_t RESERVED_62[12];
33605 __IO uint32_t HDMI_KMEK0; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x880 */
33606 uint8_t RESERVED_63[12];
33607 __IO uint32_t HDMI_KMEK1; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x890 */
33608 uint8_t RESERVED_64[12];
33609 __IO uint32_t HDMI_KMEK2; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x8A0 */
33610 uint8_t RESERVED_65[12];
33611 __IO uint32_t HDMI_KMEK3; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x8B0 */
33612 uint8_t RESERVED_66[76];
33613 __IO uint32_t HDCP_TX_CONS0; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x900 */
33614 uint8_t RESERVED_67[12];
33615 __IO uint32_t HDCP_TX_CONS1; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0x910 */
33616 uint8_t RESERVED_68[12];
33617 __IO uint32_t HDCP_TX_CONS2; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x920 */
33618 uint8_t RESERVED_69[12];
33619 __IO uint32_t HDCP_TX_CONS3; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x930 */
33620 uint8_t RESERVED_70[12];
33621 __IO uint32_t HDCP_TX_CERT0; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x940 */
33622 uint8_t RESERVED_71[12];
33623 __IO uint32_t HDCP_TX_CERT1; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x950 */
33624 uint8_t RESERVED_72[12];
33625 __IO uint32_t HDCP_TX_CERT2; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x960 */
33626 uint8_t RESERVED_73[12];
33627 __IO uint32_t HDCP_TX_CERT3; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x970 */
33628 uint8_t RESERVED_74[12];
33629 __IO uint32_t HDCP_TX_CERT4; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x980 */
33630 uint8_t RESERVED_75[12];
33631 __IO uint32_t HDCP_TX_CERT5; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x990 */
33632 uint8_t RESERVED_76[12];
33633 __IO uint32_t HDCP_TX_CERT6; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x9A0 */
33634 uint8_t RESERVED_77[12];
33635 __IO uint32_t HDCP_TX_CERT7; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x9B0 */
33636 uint8_t RESERVED_78[12];
33637 __IO uint32_t HDCP_TX_CERT8; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x9C0 */
33638 uint8_t RESERVED_79[12];
33639 __IO uint32_t HDCP_TX_CERT9; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x9D0 */
33640 uint8_t RESERVED_80[12];
33641 __IO uint32_t HDCP_TX_CERT10; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x9E0 */
33642 uint8_t RESERVED_81[12];
33643 __IO uint32_t HDCP_TX_CERT11; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x9F0 */
33644 uint8_t RESERVED_82[12];
33645 __IO uint32_t HDCP_TX_CERT12; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA00 */
33646 uint8_t RESERVED_83[12];
33647 __IO uint32_t HDCP_TX_CERT13; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0xA10 */
33648 uint8_t RESERVED_84[12];
33649 __IO uint32_t HDCP_TX_CERT14; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA20 */
33650 uint8_t RESERVED_85[12];
33651 __IO uint32_t HDCP_TX_CERT15; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA30 */
33652 uint8_t RESERVED_86[12];
33653 __IO uint32_t HDCP_TX_CERT16; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xA40 */
33654 uint8_t RESERVED_87[12];
33655 __IO uint32_t HDCP_TX_CERT17; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xA50 */
33656 uint8_t RESERVED_88[12];
33657 __IO uint32_t HDCP_TX_CERT18; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA60 */
33658 uint8_t RESERVED_89[12];
33659 __IO uint32_t HDCP_TX_CERT19; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA70 */
33660 uint8_t RESERVED_90[12];
33661 __IO uint32_t HDCP_TX_CERT20; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA80 */
33662 uint8_t RESERVED_91[12];
33663 __IO uint32_t HDCP_TX_CERT21; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA90 */
33664 uint8_t RESERVED_92[12];
33665 __IO uint32_t HDCP_TX_CERT22; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xAA0 */
33666 uint8_t RESERVED_93[12];
33667 __IO uint32_t HDCP_TX_CERT23; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xAB0 */
33668 uint8_t RESERVED_94[12];
33669 __IO uint32_t HDCP_TX_CERT24; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xAC0 */
33670 uint8_t RESERVED_95[12];
33671 __IO uint32_t HDCP_TX_CERT25; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xAD0 */
33672 uint8_t RESERVED_96[12];
33673 __IO uint32_t HDCP_TX_CERT26; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xAE0 */
33674 uint8_t RESERVED_97[12];
33675 __IO uint32_t HDCP_TX_CERT27; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xAF0 */
33676 uint8_t RESERVED_98[12];
33677 __IO uint32_t HDCP_TX_CERT28; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB00 */
33678 uint8_t RESERVED_99[12];
33679 __IO uint32_t HDCP_TX_CERT29; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0xB10 */
33680 uint8_t RESERVED_100[12];
33681 __IO uint32_t HDCP_TX_CERT30; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB20 */
33682 uint8_t RESERVED_101[12];
33683 __IO uint32_t HDCP_TX_CERT31; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB30 */
33684 uint8_t RESERVED_102[12];
33685 __IO uint32_t HDCP_TX_CERT32; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xB40 */
33686 uint8_t RESERVED_103[12];
33687 __IO uint32_t HDCP_TX_CERT33; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xB50 */
33688 uint8_t RESERVED_104[12];
33689 __IO uint32_t HDCP_TX_CERT34; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB60 */
33690 uint8_t RESERVED_105[12];
33691 __IO uint32_t HDCP_TX_CERT35; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB70 */
33692 uint8_t RESERVED_106[12];
33693 __IO uint32_t HDCP_TX_CERT36; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB80 */
33694 uint8_t RESERVED_107[12];
33695 __IO uint32_t HDCP_TX_CERT37; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB90 */
33696 uint8_t RESERVED_108[12];
33697 __IO uint32_t HDCP_TX_CERT38; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xBA0 */
33698 uint8_t RESERVED_109[12];
33699 __IO uint32_t HDCP_TX_CERT39; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xBB0 */
33700 uint8_t RESERVED_110[12];
33701 __IO uint32_t HDCP_TX_CERT40; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xBC0 */
33702 uint8_t RESERVED_111[12];
33703 __IO uint32_t HDCP_TX_CERT41; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xBD0 */
33704 uint8_t RESERVED_112[12];
33705 __IO uint32_t HDCP_TX_CERT42; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xBE0 */
33706 uint8_t RESERVED_113[12];
33707 __IO uint32_t HDCP_TX_CERT43; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xBF0 */
33708 uint8_t RESERVED_114[12];
33709 __IO uint32_t HDCP_TX_CERT44; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC00 */
33710 uint8_t RESERVED_115[12];
33711 __IO uint32_t HDCP_TX_CERT45; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0xC10 */
33712 uint8_t RESERVED_116[12];
33713 __IO uint32_t HDCP_TX_CERT46; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC20 */
33714 uint8_t RESERVED_117[12];
33715 __IO uint32_t HDCP_TX_CERT47; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC30 */
33716 uint8_t RESERVED_118[12];
33717 __IO uint32_t HDCP_TX_CERT48; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xC40 */
33718 uint8_t RESERVED_119[12];
33719 __IO uint32_t HDCP_TX_CERT49; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xC50 */
33720 uint8_t RESERVED_120[12];
33721 __IO uint32_t HDCP_TX_CERT50; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC60 */
33722 uint8_t RESERVED_121[12];
33723 __IO uint32_t HDCP_TX_CERT51; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC70 */
33724 uint8_t RESERVED_122[12];
33725 __IO uint32_t HDCP_TX_CERT52; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC80 */
33726 uint8_t RESERVED_123[12];
33727 __IO uint32_t HDCP_TX_CERT53; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC90 */
33728 uint8_t RESERVED_124[12];
33729 __IO uint32_t HDCP_TX_CERT54; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xCA0 */
33730 uint8_t RESERVED_125[12];
33731 __IO uint32_t HDCP_TX_CERT55; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xCB0 */
33732 uint8_t RESERVED_126[12];
33733 __IO uint32_t HDCP_TX_CERT56; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xCC0 */
33734 uint8_t RESERVED_127[12];
33735 __IO uint32_t HDCP_TX_CERT57; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xCD0 */
33736 uint8_t RESERVED_128[12];
33737 __IO uint32_t HDCP_TX_CERT58; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xCE0 */
33738 uint8_t RESERVED_129[12];
33739 __IO uint32_t HDCP_TX_CERT59; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xCF0 */
33740 uint8_t RESERVED_130[12];
33741 __IO uint32_t HDCP_TX_CERT60; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD00 */
33742 uint8_t RESERVED_131[12];
33743 __IO uint32_t HDCP_TX_CERT61; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0xD10 */
33744 uint8_t RESERVED_132[12];
33745 __IO uint32_t HDCP_TX_CERT62; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD20 */
33746 uint8_t RESERVED_133[12];
33747 __IO uint32_t HDCP_TX_CERT63; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD30 */
33748 uint8_t RESERVED_134[12];
33749 __IO uint32_t HDCP_TX_CERT64; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xD40 */
33750 uint8_t RESERVED_135[12];
33751 __IO uint32_t HDCP_TX_CERT65; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xD50 */
33752 uint8_t RESERVED_136[12];
33753 __IO uint32_t HDCP_TX_CERT66; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD60 */
33754 uint8_t RESERVED_137[12];
33755 __IO uint32_t HDCP_TX_CERT67; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD70 */
33756 uint8_t RESERVED_138[12];
33757 __IO uint32_t HDCP_TX_CERT68; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD80 */
33758 uint8_t RESERVED_139[12];
33759 __IO uint32_t HDCP_TX_CERT69; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD90 */
33760 uint8_t RESERVED_140[12];
33761 __IO uint32_t HDCP_TX_CERT70; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xDA0 */
33762 uint8_t RESERVED_141[12];
33763 __IO uint32_t HDCP_TX_CERT71; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xDB0 */
33764 uint8_t RESERVED_142[12];
33765 __IO uint32_t HDCP_TX_CERT72; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xDC0 */
33766 uint8_t RESERVED_143[12];
33767 __IO uint32_t HDCP_TX_CERT73; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xDD0 */
33768 uint8_t RESERVED_144[12];
33769 __IO uint32_t HDCP_TX_CERT74; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xDE0 */
33770 uint8_t RESERVED_145[12];
33771 __IO uint32_t HDCP_TX_CERT75; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xDF0 */
33772 uint8_t RESERVED_146[12];
33773 __IO uint32_t HDCP_TX_CERT76; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE00 */
33774 uint8_t RESERVED_147[12];
33775 __IO uint32_t HDCP_TX_CERT77; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0xE10 */
33776 uint8_t RESERVED_148[12];
33777 __IO uint32_t HDCP_TX_CERT78; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE20 */
33778 uint8_t RESERVED_149[12];
33779 __IO uint32_t HDCP_TX_CERT79; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE30 */
33780 uint8_t RESERVED_150[12];
33781 __IO uint32_t HDCP_TX_CERT80; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xE40 */
33782 uint8_t RESERVED_151[12];
33783 __IO uint32_t HDCP_TX_CERT81; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xE50 */
33784 uint8_t RESERVED_152[12];
33785 __IO uint32_t HDCP_TX_CERT82; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE60 */
33786 uint8_t RESERVED_153[12];
33787 __IO uint32_t HDCP_TX_CERT83; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE70 */
33788 uint8_t RESERVED_154[12];
33789 __IO uint32_t HDCP_TX_CERT84; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE80 */
33790 uint8_t RESERVED_155[12];
33791 __IO uint32_t HDCP_TX_CERT85; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE90 */
33792 uint8_t RESERVED_156[12];
33793 __IO uint32_t HDCP_TX_CERT86; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xEA0 */
33794 uint8_t RESERVED_157[12];
33795 __IO uint32_t HDCP_TX_CERT87; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xEB0 */
33796 uint8_t RESERVED_158[12];
33797 __IO uint32_t HDCP_TX_CERT88; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xEC0 */
33798 uint8_t RESERVED_159[12];
33799 __IO uint32_t HDCP_TX_CERT89; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xED0 */
33800 uint8_t RESERVED_160[12];
33801 __IO uint32_t HDCP_TX_CERT90; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xEE0 */
33802 uint8_t RESERVED_161[12];
33803 __IO uint32_t HDCP_TX_CERT91; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xEF0 */
33804 uint8_t RESERVED_162[12];
33805 __IO uint32_t HDCP_TX_CERT92; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF00 */
33806 uint8_t RESERVED_163[12];
33807 __IO uint32_t HDCP_TX_CERT93; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0xF10 */
33808 uint8_t RESERVED_164[12];
33809 __IO uint32_t HDCP_TX_CERT94; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF20 */
33810 uint8_t RESERVED_165[12];
33811 __IO uint32_t HDCP_TX_CERT95; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF30 */
33812 uint8_t RESERVED_166[12];
33813 __IO uint32_t HDCP_KEY0; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xF40 */
33814 uint8_t RESERVED_167[12];
33815 __IO uint32_t HDCP_KEY1; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xF50 */
33816 uint8_t RESERVED_168[12];
33817 __IO uint32_t HDCP_KEY2; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF60 */
33818 uint8_t RESERVED_169[12];
33819 __IO uint32_t HDCP_KEY3; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF70 */
33820 uint8_t RESERVED_170[12];
33821 __IO uint32_t HDCP_KEY4; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF80 */
33822 uint8_t RESERVED_171[12];
33823 __IO uint32_t HDCP_KEY5; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF90 */
33824 uint8_t RESERVED_172[12];
33825 __IO uint32_t HDCP_KEY6; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xFA0 */
33826 uint8_t RESERVED_173[12];
33827 __IO uint32_t HDCP_KEY7; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xFB0 */
33828 uint8_t RESERVED_174[12];
33829 __IO uint32_t HDCP_KEY8; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xFC0 */
33830 uint8_t RESERVED_175[12];
33831 __IO uint32_t HDCP_KEY9; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xFD0 */
33832 uint8_t RESERVED_176[12];
33833 __IO uint32_t HDCP_KEY10; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xFE0 */
33834 uint8_t RESERVED_177[12];
33835 __IO uint32_t HDCP_KEY11; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xFF0 */
33836 uint8_t RESERVED_178[12];
33837 __IO uint32_t HDCP_KEY12; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1000 */
33838 uint8_t RESERVED_179[12];
33839 __IO uint32_t HDCP_KEY13; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0x1010 */
33840 uint8_t RESERVED_180[12];
33841 __IO uint32_t HDCP_KEY14; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1020 */
33842 uint8_t RESERVED_181[12];
33843 __IO uint32_t HDCP_KEY15; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1030 */
33844 uint8_t RESERVED_182[12];
33845 __IO uint32_t HDCP_KEY16; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x1040 */
33846 uint8_t RESERVED_183[12];
33847 __IO uint32_t HDCP_KEY17; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x1050 */
33848 uint8_t RESERVED_184[12];
33849 __IO uint32_t HDCP_KEY18; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1060 */
33850 uint8_t RESERVED_185[12];
33851 __IO uint32_t HDCP_KEY19; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1070 */
33852 uint8_t RESERVED_186[12];
33853 __IO uint32_t HDCP_KEY20; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1080 */
33854 uint8_t RESERVED_187[12];
33855 __IO uint32_t HDCP_KEY21; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1090 */
33856 uint8_t RESERVED_188[12];
33857 __IO uint32_t HDCP_KEY22; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x10A0 */
33858 uint8_t RESERVED_189[12];
33859 __IO uint32_t HDCP_KEY23; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x10B0 */
33860 uint8_t RESERVED_190[12];
33861 __IO uint32_t HDCP_KEY24; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x10C0 */
33862 uint8_t RESERVED_191[12];
33863 __IO uint32_t HDCP_KEY25; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x10D0 */
33864 uint8_t RESERVED_192[12];
33865 __IO uint32_t HDCP_KEY26; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x10E0 */
33866 uint8_t RESERVED_193[12];
33867 __IO uint32_t HDCP_KEY27; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x10F0 */
33868 uint8_t RESERVED_194[12];
33869 __IO uint32_t HDCP_KEY28; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1100 */
33870 uint8_t RESERVED_195[12];
33871 __IO uint32_t HDCP_KEY29; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0x1110 */
33872 uint8_t RESERVED_196[12];
33873 __IO uint32_t HDCP_KEY30; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1120 */
33874 uint8_t RESERVED_197[12];
33875 __IO uint32_t HDCP_KEY31; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1130 */
33876 uint8_t RESERVED_198[12];
33877 __IO uint32_t HDCP_KEY32; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x1140 */
33878 uint8_t RESERVED_199[12];
33879 __IO uint32_t HDCP_KEY33; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x1150 */
33880 uint8_t RESERVED_200[12];
33881 __IO uint32_t HDCP_KEY34; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1160 */
33882 uint8_t RESERVED_201[12];
33883 __IO uint32_t HDCP_KEY35; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1170 */
33884 uint8_t RESERVED_202[12];
33885 __IO uint32_t HDCP_KEY36; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1180 */
33886 uint8_t RESERVED_203[12];
33887 __IO uint32_t HDCP_KEY37; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1190 */
33888 uint8_t RESERVED_204[12];
33889 __IO uint32_t HDCP_KEY38; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x11A0 */
33890 uint8_t RESERVED_205[12];
33891 __IO uint32_t HDCP_KEY39; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x11B0 */
33892 uint8_t RESERVED_206[12];
33893 __IO uint32_t HDCP_KEY40; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x11C0 */
33894 uint8_t RESERVED_207[12];
33895 __IO uint32_t HDCP_KEY41; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x11D0 */
33896 uint8_t RESERVED_208[12];
33897 __IO uint32_t HDCP_KEY42; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x11E0 */
33898 uint8_t RESERVED_209[12];
33899 __IO uint32_t HDCP_KEY43; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x11F0 */
33900 uint8_t RESERVED_210[12];
33901 __IO uint32_t HDCP_KEY44; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1200 */
33902 uint8_t RESERVED_211[12];
33903 __IO uint32_t HDCP_KEY45; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0x1210 */
33904 uint8_t RESERVED_212[12];
33905 __IO uint32_t HDCP_KEY46; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1220 */
33906 uint8_t RESERVED_213[12];
33907 __IO uint32_t HDCP_KEY47; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1230 */
33908 uint8_t RESERVED_214[12];
33909 __IO uint32_t HDCP_KEY48; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x1240 */
33910 uint8_t RESERVED_215[12];
33911 __IO uint32_t HDCP_KEY49; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x1250 */
33912 uint8_t RESERVED_216[12];
33913 __IO uint32_t HDCP_KEY50; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1260 */
33914 uint8_t RESERVED_217[12];
33915 __IO uint32_t HDCP_KEY51; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1270 */
33916 uint8_t RESERVED_218[12];
33917 __IO uint32_t HDCP_KEY52; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1280 */
33918 uint8_t RESERVED_219[12];
33919 __IO uint32_t HDCP_KEY53; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1290 */
33920 uint8_t RESERVED_220[12];
33921 __IO uint32_t HDCP_KEY54; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x12A0 */
33922 uint8_t RESERVED_221[12];
33923 __IO uint32_t HDCP_KEY55; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x12B0 */
33924 uint8_t RESERVED_222[12];
33925 __IO uint32_t HDCP_KEY56; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x12C0 */
33926 uint8_t RESERVED_223[12];
33927 __IO uint32_t HDCP_KEY57; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x12D0 */
33928 uint8_t RESERVED_224[12];
33929 __IO uint32_t HDCP_KEY58; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x12E0 */
33930 uint8_t RESERVED_225[12];
33931 __IO uint32_t HDCP_KEY59; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x12F0 */
33932 uint8_t RESERVED_226[12];
33933 __IO uint32_t HDCP_KEY60; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1300 */
33934 uint8_t RESERVED_227[12];
33935 __IO uint32_t HDCP_KEY61; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0x1310 */
33936 uint8_t RESERVED_228[12];
33937 __IO uint32_t HDCP_KEY62; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1320 */
33938 uint8_t RESERVED_229[12];
33939 __IO uint32_t HDCP_KEY63; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1330 */
33940 uint8_t RESERVED_230[12];
33941 __IO uint32_t HDCP_KEY64; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x1340 */
33942 uint8_t RESERVED_231[12];
33943 __IO uint32_t HDCP_KEY65; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x1350 */
33944 uint8_t RESERVED_232[12];
33945 __IO uint32_t HDCP_KEY66; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1360 */
33946 uint8_t RESERVED_233[12];
33947 __IO uint32_t HDCP_KEY67; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1370 */
33948 uint8_t RESERVED_234[12];
33949 __IO uint32_t HDCP_KEY68; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1380 */
33950 uint8_t RESERVED_235[12];
33951 __IO uint32_t HDCP_KEY69; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1390 */
33952 uint8_t RESERVED_236[12];
33953 __IO uint32_t HDCP_KEY70; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x13A0 */
33954 uint8_t RESERVED_237[12];
33955 __IO uint32_t HDCP_KEY71; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x13B0 */
33956} OCOTP_Type;
33957
33958/* ----------------------------------------------------------------------------
33959 -- OCOTP Register Masks
33960 ---------------------------------------------------------------------------- */
33961
33962/*!
33963 * @addtogroup OCOTP_Register_Masks OCOTP Register Masks
33964 * @{
33965 */
33966
33967/*! @name CTRL - OTP Controller Control Register */
33968/*! @{ */
33969#define OCOTP_CTRL_ADDR_MASK (0xFFU)
33970#define OCOTP_CTRL_ADDR_SHIFT (0U)
33971#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)
33972#define OCOTP_CTRL_BUSY_MASK (0x100U)
33973#define OCOTP_CTRL_BUSY_SHIFT (8U)
33974#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)
33975#define OCOTP_CTRL_ERROR_MASK (0x200U)
33976#define OCOTP_CTRL_ERROR_SHIFT (9U)
33977#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)
33978#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U)
33979#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U)
33980#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)
33981#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)
33982#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U)
33983#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)
33984/*! @} */
33985
33986/*! @name CTRL_SET - OTP Controller Control Register */
33987/*! @{ */
33988#define OCOTP_CTRL_SET_ADDR_MASK (0xFFU)
33989#define OCOTP_CTRL_SET_ADDR_SHIFT (0U)
33990#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)
33991#define OCOTP_CTRL_SET_BUSY_MASK (0x100U)
33992#define OCOTP_CTRL_SET_BUSY_SHIFT (8U)
33993#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)
33994#define OCOTP_CTRL_SET_ERROR_MASK (0x200U)
33995#define OCOTP_CTRL_SET_ERROR_SHIFT (9U)
33996#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)
33997#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U)
33998#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U)
33999#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)
34000#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U)
34001#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U)
34002#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)
34003/*! @} */
34004
34005/*! @name CTRL_CLR - OTP Controller Control Register */
34006/*! @{ */
34007#define OCOTP_CTRL_CLR_ADDR_MASK (0xFFU)
34008#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U)
34009#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)
34010#define OCOTP_CTRL_CLR_BUSY_MASK (0x100U)
34011#define OCOTP_CTRL_CLR_BUSY_SHIFT (8U)
34012#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)
34013#define OCOTP_CTRL_CLR_ERROR_MASK (0x200U)
34014#define OCOTP_CTRL_CLR_ERROR_SHIFT (9U)
34015#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)
34016#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U)
34017#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U)
34018#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)
34019#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U)
34020#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U)
34021#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
34022/*! @} */
34023
34024/*! @name CTRL_TOG - OTP Controller Control Register */
34025/*! @{ */
34026#define OCOTP_CTRL_TOG_ADDR_MASK (0xFFU)
34027#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U)
34028#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)
34029#define OCOTP_CTRL_TOG_BUSY_MASK (0x100U)
34030#define OCOTP_CTRL_TOG_BUSY_SHIFT (8U)
34031#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)
34032#define OCOTP_CTRL_TOG_ERROR_MASK (0x200U)
34033#define OCOTP_CTRL_TOG_ERROR_SHIFT (9U)
34034#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)
34035#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U)
34036#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U)
34037#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)
34038#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U)
34039#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U)
34040#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
34041/*! @} */
34042
34043/*! @name TIMING - OTP Controller Timing Register */
34044/*! @{ */
34045#define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU)
34046#define OCOTP_TIMING_STROBE_PROG_SHIFT (0U)
34047#define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK)
34048#define OCOTP_TIMING_RELAX_MASK (0xF000U)
34049#define OCOTP_TIMING_RELAX_SHIFT (12U)
34050#define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK)
34051#define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U)
34052#define OCOTP_TIMING_STROBE_READ_SHIFT (16U)
34053#define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK)
34054#define OCOTP_TIMING_WAIT_MASK (0xFC00000U)
34055#define OCOTP_TIMING_WAIT_SHIFT (22U)
34056#define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK)
34057#define OCOTP_TIMING_RSRVD0_MASK (0xF0000000U)
34058#define OCOTP_TIMING_RSRVD0_SHIFT (28U)
34059#define OCOTP_TIMING_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RSRVD0_SHIFT)) & OCOTP_TIMING_RSRVD0_MASK)
34060/*! @} */
34061
34062/*! @name DATA - OTP Controller Write Data Register */
34063/*! @{ */
34064#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU)
34065#define OCOTP_DATA_DATA_SHIFT (0U)
34066#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)
34067/*! @} */
34068
34069/*! @name READ_CTRL - OTP Controller Write Data Register */
34070/*! @{ */
34071#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U)
34072#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)
34073#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)
34074#define OCOTP_READ_CTRL_RSVD0_MASK (0xFFFFFFFEU)
34075#define OCOTP_READ_CTRL_RSVD0_SHIFT (1U)
34076#define OCOTP_READ_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_RSVD0_SHIFT)) & OCOTP_READ_CTRL_RSVD0_MASK)
34077/*! @} */
34078
34079/*! @name READ_FUSE_DATA - OTP Controller Read Data Register */
34080/*! @{ */
34081#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU)
34082#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)
34083#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)
34084/*! @} */
34085
34086/*! @name SW_STICKY - Sticky bit Register */
34087/*! @{ */
34088#define OCOTP_SW_STICKY_RSVD0_MASK (0x1U)
34089#define OCOTP_SW_STICKY_RSVD0_SHIFT (0U)
34090#define OCOTP_SW_STICKY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_RSVD0_SHIFT)) & OCOTP_SW_STICKY_RSVD0_MASK)
34091#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U)
34092#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U)
34093#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK)
34094#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U)
34095#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U)
34096#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK)
34097#define OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U)
34098#define OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U)
34099#define OCOTP_SW_STICKY_BLOCK_ROM_PART(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK)
34100#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U)
34101#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U)
34102#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK)
34103#define OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_MASK (0x20U)
34104#define OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_SHIFT (5U)
34105#define OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_SHIFT)) & OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_MASK)
34106#define OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_MASK (0x40U)
34107#define OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_SHIFT (6U)
34108#define OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_SHIFT)) & OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_MASK)
34109#define OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_MASK (0x80U)
34110#define OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_SHIFT (7U)
34111#define OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_SHIFT)) & OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_MASK)
34112#define OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_MASK (0x100U)
34113#define OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_SHIFT (8U)
34114#define OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_SHIFT)) & OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_MASK)
34115#define OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_MASK (0x200U)
34116#define OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_SHIFT (9U)
34117#define OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_SHIFT)) & OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_MASK)
34118#define OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_MASK (0x400U)
34119#define OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_SHIFT (10U)
34120#define OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_SHIFT)) & OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_MASK)
34121#define OCOTP_SW_STICKY_RSVD1_MASK (0xFFFFF800U)
34122#define OCOTP_SW_STICKY_RSVD1_SHIFT (11U)
34123#define OCOTP_SW_STICKY_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_RSVD1_SHIFT)) & OCOTP_SW_STICKY_RSVD1_MASK)
34124/*! @} */
34125
34126/*! @name SCS - Software Controllable Signals Register */
34127/*! @{ */
34128#define OCOTP_SCS_HAB_JDE_MASK (0x1U)
34129#define OCOTP_SCS_HAB_JDE_SHIFT (0U)
34130#define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK)
34131#define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU)
34132#define OCOTP_SCS_SPARE_SHIFT (1U)
34133#define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK)
34134#define OCOTP_SCS_LOCK_MASK (0x80000000U)
34135#define OCOTP_SCS_LOCK_SHIFT (31U)
34136#define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK)
34137/*! @} */
34138
34139/*! @name SCS_SET - Software Controllable Signals Register */
34140/*! @{ */
34141#define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U)
34142#define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U)
34143#define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK)
34144#define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU)
34145#define OCOTP_SCS_SET_SPARE_SHIFT (1U)
34146#define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK)
34147#define OCOTP_SCS_SET_LOCK_MASK (0x80000000U)
34148#define OCOTP_SCS_SET_LOCK_SHIFT (31U)
34149#define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK)
34150/*! @} */
34151
34152/*! @name SCS_CLR - Software Controllable Signals Register */
34153/*! @{ */
34154#define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U)
34155#define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U)
34156#define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK)
34157#define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU)
34158#define OCOTP_SCS_CLR_SPARE_SHIFT (1U)
34159#define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK)
34160#define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U)
34161#define OCOTP_SCS_CLR_LOCK_SHIFT (31U)
34162#define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK)
34163/*! @} */
34164
34165/*! @name SCS_TOG - Software Controllable Signals Register */
34166/*! @{ */
34167#define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U)
34168#define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U)
34169#define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK)
34170#define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU)
34171#define OCOTP_SCS_TOG_SPARE_SHIFT (1U)
34172#define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK)
34173#define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U)
34174#define OCOTP_SCS_TOG_LOCK_SHIFT (31U)
34175#define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK)
34176/*! @} */
34177
34178/*! @name VERSION - OTP Controller Version Register */
34179/*! @{ */
34180#define OCOTP_VERSION_STEP_MASK (0xFFFFU)
34181#define OCOTP_VERSION_STEP_SHIFT (0U)
34182#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK)
34183#define OCOTP_VERSION_MINOR_MASK (0xFF0000U)
34184#define OCOTP_VERSION_MINOR_SHIFT (16U)
34185#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK)
34186#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U)
34187#define OCOTP_VERSION_MAJOR_SHIFT (24U)
34188#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK)
34189/*! @} */
34190
34191/*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */
34192/*! @{ */
34193#define OCOTP_LOCK_TESTER_MASK (0x3U)
34194#define OCOTP_LOCK_TESTER_SHIFT (0U)
34195#define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK)
34196#define OCOTP_LOCK_BOOT_CFG_MASK (0xCU)
34197#define OCOTP_LOCK_BOOT_CFG_SHIFT (2U)
34198#define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK)
34199#define OCOTP_LOCK_MEM_TRIM_MASK (0x30U)
34200#define OCOTP_LOCK_MEM_TRIM_SHIFT (4U)
34201#define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK)
34202#define OCOTP_LOCK_ANALOG_MASK (0xC0U)
34203#define OCOTP_LOCK_ANALOG_SHIFT (6U)
34204#define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK)
34205#define OCOTP_LOCK_OTPMK_MASK (0x100U)
34206#define OCOTP_LOCK_OTPMK_SHIFT (8U)
34207#define OCOTP_LOCK_OTPMK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_SHIFT)) & OCOTP_LOCK_OTPMK_MASK)
34208#define OCOTP_LOCK_SRK_MASK (0x200U)
34209#define OCOTP_LOCK_SRK_SHIFT (9U)
34210#define OCOTP_LOCK_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK)
34211#define OCOTP_LOCK_SJC_RESP_MASK (0x400U)
34212#define OCOTP_LOCK_SJC_RESP_SHIFT (10U)
34213#define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK)
34214#define OCOTP_LOCK_GROUP_MASK_MASK (0x800U)
34215#define OCOTP_LOCK_GROUP_MASK_SHIFT (11U)
34216#define OCOTP_LOCK_GROUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GROUP_MASK_SHIFT)) & OCOTP_LOCK_GROUP_MASK_MASK)
34217#define OCOTP_LOCK_USB_ID_MASK (0x3000U)
34218#define OCOTP_LOCK_USB_ID_SHIFT (12U)
34219#define OCOTP_LOCK_USB_ID(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_USB_ID_SHIFT)) & OCOTP_LOCK_USB_ID_MASK)
34220#define OCOTP_LOCK_MAC_ADDR_MASK (0xC000U)
34221#define OCOTP_LOCK_MAC_ADDR_SHIFT (14U)
34222#define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK)
34223#define OCOTP_LOCK_MAU_KEY_MASK (0x10000U)
34224#define OCOTP_LOCK_MAU_KEY_SHIFT (16U)
34225#define OCOTP_LOCK_MAU_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAU_KEY_SHIFT)) & OCOTP_LOCK_MAU_KEY_MASK)
34226#define OCOTP_LOCK_ROM_PATCH_MASK (0x20000U)
34227#define OCOTP_LOCK_ROM_PATCH_SHIFT (17U)
34228#define OCOTP_LOCK_ROM_PATCH(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ROM_PATCH_SHIFT)) & OCOTP_LOCK_ROM_PATCH_MASK)
34229#define OCOTP_LOCK_GP_CRC_MASK (0xC0000U)
34230#define OCOTP_LOCK_GP_CRC_SHIFT (18U)
34231#define OCOTP_LOCK_GP_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP_CRC_SHIFT)) & OCOTP_LOCK_GP_CRC_MASK)
34232#define OCOTP_LOCK_GP1_MASK (0x300000U)
34233#define OCOTP_LOCK_GP1_SHIFT (20U)
34234#define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK)
34235#define OCOTP_LOCK_GP2_MASK (0xC00000U)
34236#define OCOTP_LOCK_GP2_SHIFT (22U)
34237#define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK)
34238#define OCOTP_LOCK_HDMI_KEY_MASK (0x3000000U)
34239#define OCOTP_LOCK_HDMI_KEY_SHIFT (24U)
34240#define OCOTP_LOCK_HDMI_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_HDMI_KEY_SHIFT)) & OCOTP_LOCK_HDMI_KEY_MASK)
34241#define OCOTP_LOCK_HDMI_CRC_MASK (0xC000000U)
34242#define OCOTP_LOCK_HDMI_CRC_SHIFT (26U)
34243#define OCOTP_LOCK_HDMI_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_HDMI_CRC_SHIFT)) & OCOTP_LOCK_HDMI_CRC_MASK)
34244#define OCOTP_LOCK_HDCP_KEY_MASK (0x30000000U)
34245#define OCOTP_LOCK_HDCP_KEY_SHIFT (28U)
34246#define OCOTP_LOCK_HDCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_HDCP_KEY_SHIFT)) & OCOTP_LOCK_HDCP_KEY_MASK)
34247#define OCOTP_LOCK_HDCP_CRC_MASK (0xC0000000U)
34248#define OCOTP_LOCK_HDCP_CRC_SHIFT (30U)
34249#define OCOTP_LOCK_HDCP_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_HDCP_CRC_SHIFT)) & OCOTP_LOCK_HDCP_CRC_MASK)
34250/*! @} */
34251
34252/*! @name TESTER0 - Value of OTP Bank0 Word1 (Tester Info.) */
34253/*! @{ */
34254#define OCOTP_TESTER0_BITS_MASK (0xFFFFFFFFU)
34255#define OCOTP_TESTER0_BITS_SHIFT (0U)
34256#define OCOTP_TESTER0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TESTER0_BITS_SHIFT)) & OCOTP_TESTER0_BITS_MASK)
34257/*! @} */
34258
34259/*! @name TESTER1 - Value of OTP Bank0 Word2 (tester Info.) */
34260/*! @{ */
34261#define OCOTP_TESTER1_BITS_MASK (0xFFFFFFFFU)
34262#define OCOTP_TESTER1_BITS_SHIFT (0U)
34263#define OCOTP_TESTER1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TESTER1_BITS_SHIFT)) & OCOTP_TESTER1_BITS_MASK)
34264/*! @} */
34265
34266/*! @name TESTER2 - Value of OTP Bank0 Word3 (Tester Info.) */
34267/*! @{ */
34268#define OCOTP_TESTER2_BITS_MASK (0xFFFFFFFFU)
34269#define OCOTP_TESTER2_BITS_SHIFT (0U)
34270#define OCOTP_TESTER2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TESTER2_BITS_SHIFT)) & OCOTP_TESTER2_BITS_MASK)
34271/*! @} */
34272
34273/*! @name TESTER3 - Value of OTP Bank1 Word0 (Tester Info.) */
34274/*! @{ */
34275#define OCOTP_TESTER3_BITS_MASK (0xFFFFFFFFU)
34276#define OCOTP_TESTER3_BITS_SHIFT (0U)
34277#define OCOTP_TESTER3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TESTER3_BITS_SHIFT)) & OCOTP_TESTER3_BITS_MASK)
34278/*! @} */
34279
34280/*! @name TESTER4 - Value of OTP Bank1 Word1 (Tester Info.) */
34281/*! @{ */
34282#define OCOTP_TESTER4_BITS_MASK (0xFFFFFFFFU)
34283#define OCOTP_TESTER4_BITS_SHIFT (0U)
34284#define OCOTP_TESTER4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TESTER4_BITS_SHIFT)) & OCOTP_TESTER4_BITS_MASK)
34285/*! @} */
34286
34287/*! @name TESTER5 - Value of OTP Bank1 Word2 (Tester Info.) */
34288/*! @{ */
34289#define OCOTP_TESTER5_BITS_MASK (0xFFFFFFFFU)
34290#define OCOTP_TESTER5_BITS_SHIFT (0U)
34291#define OCOTP_TESTER5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TESTER5_BITS_SHIFT)) & OCOTP_TESTER5_BITS_MASK)
34292/*! @} */
34293
34294/*! @name BOOT_CFG0 - Value of OTP Bank1 Word3 (Boot Configuration Info.) */
34295/*! @{ */
34296#define OCOTP_BOOT_CFG0_BITS_MASK (0xFFFFFFFFU)
34297#define OCOTP_BOOT_CFG0_BITS_SHIFT (0U)
34298#define OCOTP_BOOT_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BOOT_CFG0_BITS_SHIFT)) & OCOTP_BOOT_CFG0_BITS_MASK)
34299/*! @} */
34300
34301/*! @name BOOT_CFG1 - Value of OTP Bank2 Word0 (Boot Configuration Info.) */
34302/*! @{ */
34303#define OCOTP_BOOT_CFG1_BITS_MASK (0xFFFFFFFFU)
34304#define OCOTP_BOOT_CFG1_BITS_SHIFT (0U)
34305#define OCOTP_BOOT_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BOOT_CFG1_BITS_SHIFT)) & OCOTP_BOOT_CFG1_BITS_MASK)
34306/*! @} */
34307
34308/*! @name BOOT_CFG2 - Value of OTP Bank2 Word1 (Boot Configuration Info.) */
34309/*! @{ */
34310#define OCOTP_BOOT_CFG2_BITS_MASK (0xFFFFFFFFU)
34311#define OCOTP_BOOT_CFG2_BITS_SHIFT (0U)
34312#define OCOTP_BOOT_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BOOT_CFG2_BITS_SHIFT)) & OCOTP_BOOT_CFG2_BITS_MASK)
34313/*! @} */
34314
34315/*! @name BOOT_CFG3 - Value of OTP Bank2 Word2 (Boot Configuration Info.) */
34316/*! @{ */
34317#define OCOTP_BOOT_CFG3_BITS_MASK (0xFFFFFFFFU)
34318#define OCOTP_BOOT_CFG3_BITS_SHIFT (0U)
34319#define OCOTP_BOOT_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BOOT_CFG3_BITS_SHIFT)) & OCOTP_BOOT_CFG3_BITS_MASK)
34320/*! @} */
34321
34322/*! @name BOOT_CFG4 - Value of OTP Bank2 Word3 (BOOT Configuration Info.) */
34323/*! @{ */
34324#define OCOTP_BOOT_CFG4_BITS_MASK (0xFFFFFFFFU)
34325#define OCOTP_BOOT_CFG4_BITS_SHIFT (0U)
34326#define OCOTP_BOOT_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BOOT_CFG4_BITS_SHIFT)) & OCOTP_BOOT_CFG4_BITS_MASK)
34327/*! @} */
34328
34329/*! @name MEM_TRIM0 - Value of OTP Bank3 Word0 (Memory Related Info.) */
34330/*! @{ */
34331#define OCOTP_MEM_TRIM0_BITS_MASK (0xFFFFFFFFU)
34332#define OCOTP_MEM_TRIM0_BITS_SHIFT (0U)
34333#define OCOTP_MEM_TRIM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM_TRIM0_BITS_SHIFT)) & OCOTP_MEM_TRIM0_BITS_MASK)
34334/*! @} */
34335
34336/*! @name MEM_TRIM1 - Value of OTP Bank3 Word1 (Memory Related Info.) */
34337/*! @{ */
34338#define OCOTP_MEM_TRIM1_BITS_MASK (0xFFFFFFFFU)
34339#define OCOTP_MEM_TRIM1_BITS_SHIFT (0U)
34340#define OCOTP_MEM_TRIM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM_TRIM1_BITS_SHIFT)) & OCOTP_MEM_TRIM1_BITS_MASK)
34341/*! @} */
34342
34343/*! @name ANA0 - Value of OTP Bank3 Word2 (Analog Info.) */
34344/*! @{ */
34345#define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU)
34346#define OCOTP_ANA0_BITS_SHIFT (0U)
34347#define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK)
34348/*! @} */
34349
34350/*! @name ANA1 - Value of OTP Bank3 Word3 (Analog Info.) */
34351/*! @{ */
34352#define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU)
34353#define OCOTP_ANA1_BITS_SHIFT (0U)
34354#define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK)
34355/*! @} */
34356
34357/*! @name SRK0 - Shadow Register for OTP Bank6 Word0 (SRK Hash) */
34358/*! @{ */
34359#define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU)
34360#define OCOTP_SRK0_BITS_SHIFT (0U)
34361#define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK)
34362/*! @} */
34363
34364/*! @name SRK1 - Shadow Register for OTP Bank6 Word1 (SRK Hash) */
34365/*! @{ */
34366#define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU)
34367#define OCOTP_SRK1_BITS_SHIFT (0U)
34368#define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK)
34369/*! @} */
34370
34371/*! @name SRK2 - Shadow Register for OTP Bank6 Word2 (SRK Hash) */
34372/*! @{ */
34373#define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU)
34374#define OCOTP_SRK2_BITS_SHIFT (0U)
34375#define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK)
34376/*! @} */
34377
34378/*! @name SRK3 - Shadow Register for OTP Bank6 Word3 (SRK Hash) */
34379/*! @{ */
34380#define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU)
34381#define OCOTP_SRK3_BITS_SHIFT (0U)
34382#define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK)
34383/*! @} */
34384
34385/*! @name SRK4 - Shadow Register for OTP Bank7 Word0 (SRK Hash) */
34386/*! @{ */
34387#define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU)
34388#define OCOTP_SRK4_BITS_SHIFT (0U)
34389#define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK)
34390/*! @} */
34391
34392/*! @name SRK5 - Shadow Register for OTP Bank7 Word1 (SRK Hash) */
34393/*! @{ */
34394#define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU)
34395#define OCOTP_SRK5_BITS_SHIFT (0U)
34396#define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK)
34397/*! @} */
34398
34399/*! @name SRK6 - Shadow Register for OTP Bank7 Word2 (SRK Hash) */
34400/*! @{ */
34401#define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU)
34402#define OCOTP_SRK6_BITS_SHIFT (0U)
34403#define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK)
34404/*! @} */
34405
34406/*! @name SRK7 - Shadow Register for OTP Bank7 Word3 (SRK Hash) */
34407/*! @{ */
34408#define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU)
34409#define OCOTP_SRK7_BITS_SHIFT (0U)
34410#define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK)
34411/*! @} */
34412
34413/*! @name SJC_RESP0 - Value of OTP Bank8 Word0 (Secure JTAG Response Field) */
34414/*! @{ */
34415#define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU)
34416#define OCOTP_SJC_RESP0_BITS_SHIFT (0U)
34417#define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK)
34418/*! @} */
34419
34420/*! @name SJC_RESP1 - Value of OTP Bank8 Word1 (Secure JTAG Response Field) */
34421/*! @{ */
34422#define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU)
34423#define OCOTP_SJC_RESP1_BITS_SHIFT (0U)
34424#define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK)
34425/*! @} */
34426
34427/*! @name USB_ID - Value of OTP Bank8 Word2 (USB ID info) */
34428/*! @{ */
34429#define OCOTP_USB_ID_BITS_MASK (0xFFFFFFFFU)
34430#define OCOTP_USB_ID_BITS_SHIFT (0U)
34431#define OCOTP_USB_ID_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_USB_ID_BITS_SHIFT)) & OCOTP_USB_ID_BITS_MASK)
34432/*! @} */
34433
34434/*! @name FIELD_RETURN - Value of OTP Bank5 Word6 (Field Return) */
34435/*! @{ */
34436#define OCOTP_FIELD_RETURN_BITS_MASK (0xFFFFFFFFU)
34437#define OCOTP_FIELD_RETURN_BITS_SHIFT (0U)
34438#define OCOTP_FIELD_RETURN_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FIELD_RETURN_BITS_SHIFT)) & OCOTP_FIELD_RETURN_BITS_MASK)
34439/*! @} */
34440
34441/*! @name MAC_ADDR0 - Value of OTP Bank9 Word0 (MAC Address) */
34442/*! @{ */
34443#define OCOTP_MAC_ADDR0_BITS_MASK (0xFFFFFFFFU)
34444#define OCOTP_MAC_ADDR0_BITS_SHIFT (0U)
34445#define OCOTP_MAC_ADDR0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC_ADDR0_BITS_SHIFT)) & OCOTP_MAC_ADDR0_BITS_MASK)
34446/*! @} */
34447
34448/*! @name MAC_ADDR1 - Value of OTP Bank9 Word1 (MAC Address) */
34449/*! @{ */
34450#define OCOTP_MAC_ADDR1_BITS_MASK (0xFFFFFFFFU)
34451#define OCOTP_MAC_ADDR1_BITS_SHIFT (0U)
34452#define OCOTP_MAC_ADDR1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC_ADDR1_BITS_SHIFT)) & OCOTP_MAC_ADDR1_BITS_MASK)
34453/*! @} */
34454
34455/*! @name MAC_ADDR2 - Value of OTP Bank9 Word2 (MAC Address) */
34456/*! @{ */
34457#define OCOTP_MAC_ADDR2_BITS_MASK (0xFFFFFFFFU)
34458#define OCOTP_MAC_ADDR2_BITS_SHIFT (0U)
34459#define OCOTP_MAC_ADDR2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC_ADDR2_BITS_SHIFT)) & OCOTP_MAC_ADDR2_BITS_MASK)
34460/*! @} */
34461
34462/*! @name SRK_REVOKE - Value of OTP Bank9 Word3 (SRK Revoke) */
34463/*! @{ */
34464#define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU)
34465#define OCOTP_SRK_REVOKE_BITS_SHIFT (0U)
34466#define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK)
34467/*! @} */
34468
34469/*! @name MAU_KEY0 - Shadow Register for OTP Bank10 Word0 (MAU Key) */
34470/*! @{ */
34471#define OCOTP_MAU_KEY0_BITS_MASK (0xFFFFFFFFU)
34472#define OCOTP_MAU_KEY0_BITS_SHIFT (0U)
34473#define OCOTP_MAU_KEY0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY0_BITS_SHIFT)) & OCOTP_MAU_KEY0_BITS_MASK)
34474/*! @} */
34475
34476/*! @name MAU_KEY1 - Shadow Register for OTP Bank10 Word1 (MAU Key) */
34477/*! @{ */
34478#define OCOTP_MAU_KEY1_BITS_MASK (0xFFFFFFFFU)
34479#define OCOTP_MAU_KEY1_BITS_SHIFT (0U)
34480#define OCOTP_MAU_KEY1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY1_BITS_SHIFT)) & OCOTP_MAU_KEY1_BITS_MASK)
34481/*! @} */
34482
34483/*! @name MAU_KEY2 - Shadow Register for OTP Bank10 Word2 (MAU Key) */
34484/*! @{ */
34485#define OCOTP_MAU_KEY2_BITS_MASK (0xFFFFFFFFU)
34486#define OCOTP_MAU_KEY2_BITS_SHIFT (0U)
34487#define OCOTP_MAU_KEY2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY2_BITS_SHIFT)) & OCOTP_MAU_KEY2_BITS_MASK)
34488/*! @} */
34489
34490/*! @name MAU_KEY3 - Shadow Register for OTP Bank10 Word3 (MAU Key) */
34491/*! @{ */
34492#define OCOTP_MAU_KEY3_BITS_MASK (0xFFFFFFFFU)
34493#define OCOTP_MAU_KEY3_BITS_SHIFT (0U)
34494#define OCOTP_MAU_KEY3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY3_BITS_SHIFT)) & OCOTP_MAU_KEY3_BITS_MASK)
34495/*! @} */
34496
34497/*! @name MAU_KEY4 - Shadow Register for OTP Bank11 Word0 (MAU Key) */
34498/*! @{ */
34499#define OCOTP_MAU_KEY4_BITS_MASK (0xFFFFFFFFU)
34500#define OCOTP_MAU_KEY4_BITS_SHIFT (0U)
34501#define OCOTP_MAU_KEY4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY4_BITS_SHIFT)) & OCOTP_MAU_KEY4_BITS_MASK)
34502/*! @} */
34503
34504/*! @name MAU_KEY5 - Shadow Register for OTP Bank11 Word1 (MAU Key) */
34505/*! @{ */
34506#define OCOTP_MAU_KEY5_BITS_MASK (0xFFFFFFFFU)
34507#define OCOTP_MAU_KEY5_BITS_SHIFT (0U)
34508#define OCOTP_MAU_KEY5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY5_BITS_SHIFT)) & OCOTP_MAU_KEY5_BITS_MASK)
34509/*! @} */
34510
34511/*! @name MAU_KEY6 - Shadow Register for OTP Bank11 Word2 (MAU Key) */
34512/*! @{ */
34513#define OCOTP_MAU_KEY6_BITS_MASK (0xFFFFFFFFU)
34514#define OCOTP_MAU_KEY6_BITS_SHIFT (0U)
34515#define OCOTP_MAU_KEY6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY6_BITS_SHIFT)) & OCOTP_MAU_KEY6_BITS_MASK)
34516/*! @} */
34517
34518/*! @name MAU_KEY7 - Shadow Register for OTP Bank11 Word3 (MAU Key) */
34519/*! @{ */
34520#define OCOTP_MAU_KEY7_BITS_MASK (0xFFFFFFFFU)
34521#define OCOTP_MAU_KEY7_BITS_SHIFT (0U)
34522#define OCOTP_MAU_KEY7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY7_BITS_SHIFT)) & OCOTP_MAU_KEY7_BITS_MASK)
34523/*! @} */
34524
34525/*! @name GP10 - Value of OTP Bank14 Word0 () */
34526/*! @{ */
34527#define OCOTP_GP10_BITS_MASK (0xFFFFFFFFU)
34528#define OCOTP_GP10_BITS_SHIFT (0U)
34529#define OCOTP_GP10_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP10_BITS_SHIFT)) & OCOTP_GP10_BITS_MASK)
34530/*! @} */
34531
34532/*! @name GP11 - Value of OTP Bank14 Word1 () */
34533/*! @{ */
34534#define OCOTP_GP11_BITS_MASK (0xFFFFFFFFU)
34535#define OCOTP_GP11_BITS_SHIFT (0U)
34536#define OCOTP_GP11_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP11_BITS_SHIFT)) & OCOTP_GP11_BITS_MASK)
34537/*! @} */
34538
34539/*! @name GP20 - Value of OTP Bank14 Word2 () */
34540/*! @{ */
34541#define OCOTP_GP20_BITS_MASK (0xFFFFFFFFU)
34542#define OCOTP_GP20_BITS_SHIFT (0U)
34543#define OCOTP_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP20_BITS_SHIFT)) & OCOTP_GP20_BITS_MASK)
34544/*! @} */
34545
34546/*! @name GP21 - Value of OTP Bank14 Word3 () */
34547/*! @{ */
34548#define OCOTP_GP21_BITS_MASK (0xFFFFFFFFU)
34549#define OCOTP_GP21_BITS_SHIFT (0U)
34550#define OCOTP_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP21_BITS_SHIFT)) & OCOTP_GP21_BITS_MASK)
34551/*! @} */
34552
34553/*! @name GP_CRC0 - Value of OTP Bank15 Word0 (CRC Key) */
34554/*! @{ */
34555#define OCOTP_GP_CRC0_BITS_MASK (0xFFFFFFFFU)
34556#define OCOTP_GP_CRC0_BITS_SHIFT (0U)
34557#define OCOTP_GP_CRC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP_CRC0_BITS_SHIFT)) & OCOTP_GP_CRC0_BITS_MASK)
34558/*! @} */
34559
34560/*! @name GP_CRC1 - Value of OTP Bank15 Word1 (CRC Key) */
34561/*! @{ */
34562#define OCOTP_GP_CRC1_BITS_MASK (0xFFFFFFFFU)
34563#define OCOTP_GP_CRC1_BITS_SHIFT (0U)
34564#define OCOTP_GP_CRC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP_CRC1_BITS_SHIFT)) & OCOTP_GP_CRC1_BITS_MASK)
34565/*! @} */
34566
34567/*! @name GP_CRC2 - Value of OTP Bank15 Word2 (CRC Key) */
34568/*! @{ */
34569#define OCOTP_GP_CRC2_BITS_MASK (0xFFFFFFFFU)
34570#define OCOTP_GP_CRC2_BITS_SHIFT (0U)
34571#define OCOTP_GP_CRC2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP_CRC2_BITS_SHIFT)) & OCOTP_GP_CRC2_BITS_MASK)
34572/*! @} */
34573
34574/*! @name GROUP_MASK - Value of OTP Bank15 Word3 (CRC Key) */
34575/*! @{ */
34576#define OCOTP_GROUP_MASK_BITS_MASK (0xFFFFFFFFU)
34577#define OCOTP_GROUP_MASK_BITS_SHIFT (0U)
34578#define OCOTP_GROUP_MASK_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GROUP_MASK_BITS_SHIFT)) & OCOTP_GROUP_MASK_BITS_MASK)
34579/*! @} */
34580
34581/*! @name HDMI_FW_SRK0 - Value of OTP Bank16 Word0 (HDCP Key) */
34582/*! @{ */
34583#define OCOTP_HDMI_FW_SRK0_BITS_MASK (0xFFFFFFFFU)
34584#define OCOTP_HDMI_FW_SRK0_BITS_SHIFT (0U)
34585#define OCOTP_HDMI_FW_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK0_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK0_BITS_MASK)
34586/*! @} */
34587
34588/*! @name HDMI_FW_SRK1 - Value of OTP Bank16 Word1 (HDCP Key) */
34589/*! @{ */
34590#define OCOTP_HDMI_FW_SRK1_BITS_MASK (0xFFFFFFFFU)
34591#define OCOTP_HDMI_FW_SRK1_BITS_SHIFT (0U)
34592#define OCOTP_HDMI_FW_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK1_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK1_BITS_MASK)
34593/*! @} */
34594
34595/*! @name HDMI_FW_SRK2 - Value of OTP Bank16 Word0 (HDCP Key) */
34596/*! @{ */
34597#define OCOTP_HDMI_FW_SRK2_BITS_MASK (0xFFFFFFFFU)
34598#define OCOTP_HDMI_FW_SRK2_BITS_SHIFT (0U)
34599#define OCOTP_HDMI_FW_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK2_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK2_BITS_MASK)
34600/*! @} */
34601
34602/*! @name HDMI_FW_SRK3 - Value of OTP Bank16 Word0 (HDCP Key) */
34603/*! @{ */
34604#define OCOTP_HDMI_FW_SRK3_BITS_MASK (0xFFFFFFFFU)
34605#define OCOTP_HDMI_FW_SRK3_BITS_SHIFT (0U)
34606#define OCOTP_HDMI_FW_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK3_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK3_BITS_MASK)
34607/*! @} */
34608
34609/*! @name HDMI_FW_SRK4 - Value of OTP Bank17 Word0 (HDCP Key) */
34610/*! @{ */
34611#define OCOTP_HDMI_FW_SRK4_BITS_MASK (0xFFFFFFFFU)
34612#define OCOTP_HDMI_FW_SRK4_BITS_SHIFT (0U)
34613#define OCOTP_HDMI_FW_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK4_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK4_BITS_MASK)
34614/*! @} */
34615
34616/*! @name HDMI_FW_SRK5 - Value of OTP Bank17 Word1 (HDCP Key) */
34617/*! @{ */
34618#define OCOTP_HDMI_FW_SRK5_BITS_MASK (0xFFFFFFFFU)
34619#define OCOTP_HDMI_FW_SRK5_BITS_SHIFT (0U)
34620#define OCOTP_HDMI_FW_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK5_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK5_BITS_MASK)
34621/*! @} */
34622
34623/*! @name HDMI_FW_SRK6 - Value of OTP Bank16 Word0 (HDCP Key) */
34624/*! @{ */
34625#define OCOTP_HDMI_FW_SRK6_BITS_MASK (0xFFFFFFFFU)
34626#define OCOTP_HDMI_FW_SRK6_BITS_SHIFT (0U)
34627#define OCOTP_HDMI_FW_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK6_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK6_BITS_MASK)
34628/*! @} */
34629
34630/*! @name HDMI_FW_SRK7 - Value of OTP Bank16 Word0 (HDCP Key) */
34631/*! @{ */
34632#define OCOTP_HDMI_FW_SRK7_BITS_MASK (0xFFFFFFFFU)
34633#define OCOTP_HDMI_FW_SRK7_BITS_SHIFT (0U)
34634#define OCOTP_HDMI_FW_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK7_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK7_BITS_MASK)
34635/*! @} */
34636
34637/*! @name HDMI_KMEK0 - Value of OTP Bank16 Word0 (HDCP Key) */
34638/*! @{ */
34639#define OCOTP_HDMI_KMEK0_BITS_MASK (0xFFFFFFFFU)
34640#define OCOTP_HDMI_KMEK0_BITS_SHIFT (0U)
34641#define OCOTP_HDMI_KMEK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_KMEK0_BITS_SHIFT)) & OCOTP_HDMI_KMEK0_BITS_MASK)
34642/*! @} */
34643
34644/*! @name HDMI_KMEK1 - Value of OTP Bank16 Word0 (HDCP Key) */
34645/*! @{ */
34646#define OCOTP_HDMI_KMEK1_BITS_MASK (0xFFFFFFFFU)
34647#define OCOTP_HDMI_KMEK1_BITS_SHIFT (0U)
34648#define OCOTP_HDMI_KMEK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_KMEK1_BITS_SHIFT)) & OCOTP_HDMI_KMEK1_BITS_MASK)
34649/*! @} */
34650
34651/*! @name HDMI_KMEK2 - Value of OTP Bank16 Word0 (HDCP Key) */
34652/*! @{ */
34653#define OCOTP_HDMI_KMEK2_BITS_MASK (0xFFFFFFFFU)
34654#define OCOTP_HDMI_KMEK2_BITS_SHIFT (0U)
34655#define OCOTP_HDMI_KMEK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_KMEK2_BITS_SHIFT)) & OCOTP_HDMI_KMEK2_BITS_MASK)
34656/*! @} */
34657
34658/*! @name HDMI_KMEK3 - Value of OTP Bank16 Word0 (HDCP Key) */
34659/*! @{ */
34660#define OCOTP_HDMI_KMEK3_BITS_MASK (0xFFFFFFFFU)
34661#define OCOTP_HDMI_KMEK3_BITS_SHIFT (0U)
34662#define OCOTP_HDMI_KMEK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_KMEK3_BITS_SHIFT)) & OCOTP_HDMI_KMEK3_BITS_MASK)
34663/*! @} */
34664
34665/*! @name HDCP_TX_CONS0 - Value of OTP Bank16 Word0 (HDCP Key) */
34666/*! @{ */
34667#define OCOTP_HDCP_TX_CONS0_BITS_MASK (0xFFFFFFFFU)
34668#define OCOTP_HDCP_TX_CONS0_BITS_SHIFT (0U)
34669#define OCOTP_HDCP_TX_CONS0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CONS0_BITS_SHIFT)) & OCOTP_HDCP_TX_CONS0_BITS_MASK)
34670/*! @} */
34671
34672/*! @name HDCP_TX_CONS1 - Value of OTP Bank16 Word1 (HDCP Key) */
34673/*! @{ */
34674#define OCOTP_HDCP_TX_CONS1_BITS_MASK (0xFFFFFFFFU)
34675#define OCOTP_HDCP_TX_CONS1_BITS_SHIFT (0U)
34676#define OCOTP_HDCP_TX_CONS1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CONS1_BITS_SHIFT)) & OCOTP_HDCP_TX_CONS1_BITS_MASK)
34677/*! @} */
34678
34679/*! @name HDCP_TX_CONS2 - Value of OTP Bank16 Word0 (HDCP Key) */
34680/*! @{ */
34681#define OCOTP_HDCP_TX_CONS2_BITS_MASK (0xFFFFFFFFU)
34682#define OCOTP_HDCP_TX_CONS2_BITS_SHIFT (0U)
34683#define OCOTP_HDCP_TX_CONS2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CONS2_BITS_SHIFT)) & OCOTP_HDCP_TX_CONS2_BITS_MASK)
34684/*! @} */
34685
34686/*! @name HDCP_TX_CONS3 - Value of OTP Bank16 Word0 (HDCP Key) */
34687/*! @{ */
34688#define OCOTP_HDCP_TX_CONS3_BITS_MASK (0xFFFFFFFFU)
34689#define OCOTP_HDCP_TX_CONS3_BITS_SHIFT (0U)
34690#define OCOTP_HDCP_TX_CONS3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CONS3_BITS_SHIFT)) & OCOTP_HDCP_TX_CONS3_BITS_MASK)
34691/*! @} */
34692
34693/*! @name HDCP_TX_CERT0 - Value of OTP Bank17 Word0 (HDCP Key) */
34694/*! @{ */
34695#define OCOTP_HDCP_TX_CERT0_BITS_MASK (0xFFFFFFFFU)
34696#define OCOTP_HDCP_TX_CERT0_BITS_SHIFT (0U)
34697#define OCOTP_HDCP_TX_CERT0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT0_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT0_BITS_MASK)
34698/*! @} */
34699
34700/*! @name HDCP_TX_CERT1 - Value of OTP Bank17 Word1 (HDCP Key) */
34701/*! @{ */
34702#define OCOTP_HDCP_TX_CERT1_BITS_MASK (0xFFFFFFFFU)
34703#define OCOTP_HDCP_TX_CERT1_BITS_SHIFT (0U)
34704#define OCOTP_HDCP_TX_CERT1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT1_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT1_BITS_MASK)
34705/*! @} */
34706
34707/*! @name HDCP_TX_CERT2 - Value of OTP Bank16 Word0 (HDCP Key) */
34708/*! @{ */
34709#define OCOTP_HDCP_TX_CERT2_BITS_MASK (0xFFFFFFFFU)
34710#define OCOTP_HDCP_TX_CERT2_BITS_SHIFT (0U)
34711#define OCOTP_HDCP_TX_CERT2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT2_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT2_BITS_MASK)
34712/*! @} */
34713
34714/*! @name HDCP_TX_CERT3 - Value of OTP Bank16 Word0 (HDCP Key) */
34715/*! @{ */
34716#define OCOTP_HDCP_TX_CERT3_BITS_MASK (0xFFFFFFFFU)
34717#define OCOTP_HDCP_TX_CERT3_BITS_SHIFT (0U)
34718#define OCOTP_HDCP_TX_CERT3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT3_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT3_BITS_MASK)
34719/*! @} */
34720
34721/*! @name HDCP_TX_CERT4 - Value of OTP Bank16 Word0 (HDCP Key) */
34722/*! @{ */
34723#define OCOTP_HDCP_TX_CERT4_BITS_MASK (0xFFFFFFFFU)
34724#define OCOTP_HDCP_TX_CERT4_BITS_SHIFT (0U)
34725#define OCOTP_HDCP_TX_CERT4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT4_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT4_BITS_MASK)
34726/*! @} */
34727
34728/*! @name HDCP_TX_CERT5 - Value of OTP Bank16 Word0 (HDCP Key) */
34729/*! @{ */
34730#define OCOTP_HDCP_TX_CERT5_BITS_MASK (0xFFFFFFFFU)
34731#define OCOTP_HDCP_TX_CERT5_BITS_SHIFT (0U)
34732#define OCOTP_HDCP_TX_CERT5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT5_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT5_BITS_MASK)
34733/*! @} */
34734
34735/*! @name HDCP_TX_CERT6 - Value of OTP Bank16 Word0 (HDCP Key) */
34736/*! @{ */
34737#define OCOTP_HDCP_TX_CERT6_BITS_MASK (0xFFFFFFFFU)
34738#define OCOTP_HDCP_TX_CERT6_BITS_SHIFT (0U)
34739#define OCOTP_HDCP_TX_CERT6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT6_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT6_BITS_MASK)
34740/*! @} */
34741
34742/*! @name HDCP_TX_CERT7 - Value of OTP Bank16 Word0 (HDCP Key) */
34743/*! @{ */
34744#define OCOTP_HDCP_TX_CERT7_BITS_MASK (0xFFFFFFFFU)
34745#define OCOTP_HDCP_TX_CERT7_BITS_SHIFT (0U)
34746#define OCOTP_HDCP_TX_CERT7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT7_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT7_BITS_MASK)
34747/*! @} */
34748
34749/*! @name HDCP_TX_CERT8 - Value of OTP Bank17 Word0 (HDCP Key) */
34750/*! @{ */
34751#define OCOTP_HDCP_TX_CERT8_BITS_MASK (0xFFFFFFFFU)
34752#define OCOTP_HDCP_TX_CERT8_BITS_SHIFT (0U)
34753#define OCOTP_HDCP_TX_CERT8_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT8_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT8_BITS_MASK)
34754/*! @} */
34755
34756/*! @name HDCP_TX_CERT9 - Value of OTP Bank17 Word1 (HDCP Key) */
34757/*! @{ */
34758#define OCOTP_HDCP_TX_CERT9_BITS_MASK (0xFFFFFFFFU)
34759#define OCOTP_HDCP_TX_CERT9_BITS_SHIFT (0U)
34760#define OCOTP_HDCP_TX_CERT9_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT9_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT9_BITS_MASK)
34761/*! @} */
34762
34763/*! @name HDCP_TX_CERT10 - Value of OTP Bank16 Word0 (HDCP Key) */
34764/*! @{ */
34765#define OCOTP_HDCP_TX_CERT10_BITS_MASK (0xFFFFFFFFU)
34766#define OCOTP_HDCP_TX_CERT10_BITS_SHIFT (0U)
34767#define OCOTP_HDCP_TX_CERT10_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT10_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT10_BITS_MASK)
34768/*! @} */
34769
34770/*! @name HDCP_TX_CERT11 - Value of OTP Bank16 Word0 (HDCP Key) */
34771/*! @{ */
34772#define OCOTP_HDCP_TX_CERT11_BITS_MASK (0xFFFFFFFFU)
34773#define OCOTP_HDCP_TX_CERT11_BITS_SHIFT (0U)
34774#define OCOTP_HDCP_TX_CERT11_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT11_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT11_BITS_MASK)
34775/*! @} */
34776
34777/*! @name HDCP_TX_CERT12 - Value of OTP Bank16 Word0 (HDCP Key) */
34778/*! @{ */
34779#define OCOTP_HDCP_TX_CERT12_BITS_MASK (0xFFFFFFFFU)
34780#define OCOTP_HDCP_TX_CERT12_BITS_SHIFT (0U)
34781#define OCOTP_HDCP_TX_CERT12_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT12_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT12_BITS_MASK)
34782/*! @} */
34783
34784/*! @name HDCP_TX_CERT13 - Value of OTP Bank16 Word1 (HDCP Key) */
34785/*! @{ */
34786#define OCOTP_HDCP_TX_CERT13_BITS_MASK (0xFFFFFFFFU)
34787#define OCOTP_HDCP_TX_CERT13_BITS_SHIFT (0U)
34788#define OCOTP_HDCP_TX_CERT13_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT13_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT13_BITS_MASK)
34789/*! @} */
34790
34791/*! @name HDCP_TX_CERT14 - Value of OTP Bank16 Word0 (HDCP Key) */
34792/*! @{ */
34793#define OCOTP_HDCP_TX_CERT14_BITS_MASK (0xFFFFFFFFU)
34794#define OCOTP_HDCP_TX_CERT14_BITS_SHIFT (0U)
34795#define OCOTP_HDCP_TX_CERT14_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT14_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT14_BITS_MASK)
34796/*! @} */
34797
34798/*! @name HDCP_TX_CERT15 - Value of OTP Bank16 Word0 (HDCP Key) */
34799/*! @{ */
34800#define OCOTP_HDCP_TX_CERT15_BITS_MASK (0xFFFFFFFFU)
34801#define OCOTP_HDCP_TX_CERT15_BITS_SHIFT (0U)
34802#define OCOTP_HDCP_TX_CERT15_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT15_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT15_BITS_MASK)
34803/*! @} */
34804
34805/*! @name HDCP_TX_CERT16 - Value of OTP Bank17 Word0 (HDCP Key) */
34806/*! @{ */
34807#define OCOTP_HDCP_TX_CERT16_BITS_MASK (0xFFFFFFFFU)
34808#define OCOTP_HDCP_TX_CERT16_BITS_SHIFT (0U)
34809#define OCOTP_HDCP_TX_CERT16_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT16_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT16_BITS_MASK)
34810/*! @} */
34811
34812/*! @name HDCP_TX_CERT17 - Value of OTP Bank17 Word1 (HDCP Key) */
34813/*! @{ */
34814#define OCOTP_HDCP_TX_CERT17_BITS_MASK (0xFFFFFFFFU)
34815#define OCOTP_HDCP_TX_CERT17_BITS_SHIFT (0U)
34816#define OCOTP_HDCP_TX_CERT17_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT17_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT17_BITS_MASK)
34817/*! @} */
34818
34819/*! @name HDCP_TX_CERT18 - Value of OTP Bank16 Word0 (HDCP Key) */
34820/*! @{ */
34821#define OCOTP_HDCP_TX_CERT18_BITS_MASK (0xFFFFFFFFU)
34822#define OCOTP_HDCP_TX_CERT18_BITS_SHIFT (0U)
34823#define OCOTP_HDCP_TX_CERT18_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT18_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT18_BITS_MASK)
34824/*! @} */
34825
34826/*! @name HDCP_TX_CERT19 - Value of OTP Bank16 Word0 (HDCP Key) */
34827/*! @{ */
34828#define OCOTP_HDCP_TX_CERT19_BITS_MASK (0xFFFFFFFFU)
34829#define OCOTP_HDCP_TX_CERT19_BITS_SHIFT (0U)
34830#define OCOTP_HDCP_TX_CERT19_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT19_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT19_BITS_MASK)
34831/*! @} */
34832
34833/*! @name HDCP_TX_CERT20 - Value of OTP Bank16 Word0 (HDCP Key) */
34834/*! @{ */
34835#define OCOTP_HDCP_TX_CERT20_BITS_MASK (0xFFFFFFFFU)
34836#define OCOTP_HDCP_TX_CERT20_BITS_SHIFT (0U)
34837#define OCOTP_HDCP_TX_CERT20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT20_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT20_BITS_MASK)
34838/*! @} */
34839
34840/*! @name HDCP_TX_CERT21 - Value of OTP Bank16 Word0 (HDCP Key) */
34841/*! @{ */
34842#define OCOTP_HDCP_TX_CERT21_BITS_MASK (0xFFFFFFFFU)
34843#define OCOTP_HDCP_TX_CERT21_BITS_SHIFT (0U)
34844#define OCOTP_HDCP_TX_CERT21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT21_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT21_BITS_MASK)
34845/*! @} */
34846
34847/*! @name HDCP_TX_CERT22 - Value of OTP Bank16 Word0 (HDCP Key) */
34848/*! @{ */
34849#define OCOTP_HDCP_TX_CERT22_BITS_MASK (0xFFFFFFFFU)
34850#define OCOTP_HDCP_TX_CERT22_BITS_SHIFT (0U)
34851#define OCOTP_HDCP_TX_CERT22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT22_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT22_BITS_MASK)
34852/*! @} */
34853
34854/*! @name HDCP_TX_CERT23 - Value of OTP Bank16 Word0 (HDCP Key) */
34855/*! @{ */
34856#define OCOTP_HDCP_TX_CERT23_BITS_MASK (0xFFFFFFFFU)
34857#define OCOTP_HDCP_TX_CERT23_BITS_SHIFT (0U)
34858#define OCOTP_HDCP_TX_CERT23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT23_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT23_BITS_MASK)
34859/*! @} */
34860
34861/*! @name HDCP_TX_CERT24 - Value of OTP Bank17 Word0 (HDCP Key) */
34862/*! @{ */
34863#define OCOTP_HDCP_TX_CERT24_BITS_MASK (0xFFFFFFFFU)
34864#define OCOTP_HDCP_TX_CERT24_BITS_SHIFT (0U)
34865#define OCOTP_HDCP_TX_CERT24_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT24_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT24_BITS_MASK)
34866/*! @} */
34867
34868/*! @name HDCP_TX_CERT25 - Value of OTP Bank17 Word1 (HDCP Key) */
34869/*! @{ */
34870#define OCOTP_HDCP_TX_CERT25_BITS_MASK (0xFFFFFFFFU)
34871#define OCOTP_HDCP_TX_CERT25_BITS_SHIFT (0U)
34872#define OCOTP_HDCP_TX_CERT25_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT25_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT25_BITS_MASK)
34873/*! @} */
34874
34875/*! @name HDCP_TX_CERT26 - Value of OTP Bank16 Word0 (HDCP Key) */
34876/*! @{ */
34877#define OCOTP_HDCP_TX_CERT26_BITS_MASK (0xFFFFFFFFU)
34878#define OCOTP_HDCP_TX_CERT26_BITS_SHIFT (0U)
34879#define OCOTP_HDCP_TX_CERT26_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT26_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT26_BITS_MASK)
34880/*! @} */
34881
34882/*! @name HDCP_TX_CERT27 - Value of OTP Bank16 Word0 (HDCP Key) */
34883/*! @{ */
34884#define OCOTP_HDCP_TX_CERT27_BITS_MASK (0xFFFFFFFFU)
34885#define OCOTP_HDCP_TX_CERT27_BITS_SHIFT (0U)
34886#define OCOTP_HDCP_TX_CERT27_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT27_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT27_BITS_MASK)
34887/*! @} */
34888
34889/*! @name HDCP_TX_CERT28 - Value of OTP Bank16 Word0 (HDCP Key) */
34890/*! @{ */
34891#define OCOTP_HDCP_TX_CERT28_BITS_MASK (0xFFFFFFFFU)
34892#define OCOTP_HDCP_TX_CERT28_BITS_SHIFT (0U)
34893#define OCOTP_HDCP_TX_CERT28_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT28_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT28_BITS_MASK)
34894/*! @} */
34895
34896/*! @name HDCP_TX_CERT29 - Value of OTP Bank16 Word1 (HDCP Key) */
34897/*! @{ */
34898#define OCOTP_HDCP_TX_CERT29_BITS_MASK (0xFFFFFFFFU)
34899#define OCOTP_HDCP_TX_CERT29_BITS_SHIFT (0U)
34900#define OCOTP_HDCP_TX_CERT29_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT29_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT29_BITS_MASK)
34901/*! @} */
34902
34903/*! @name HDCP_TX_CERT30 - Value of OTP Bank16 Word0 (HDCP Key) */
34904/*! @{ */
34905#define OCOTP_HDCP_TX_CERT30_BITS_MASK (0xFFFFFFFFU)
34906#define OCOTP_HDCP_TX_CERT30_BITS_SHIFT (0U)
34907#define OCOTP_HDCP_TX_CERT30_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT30_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT30_BITS_MASK)
34908/*! @} */
34909
34910/*! @name HDCP_TX_CERT31 - Value of OTP Bank16 Word0 (HDCP Key) */
34911/*! @{ */
34912#define OCOTP_HDCP_TX_CERT31_BITS_MASK (0xFFFFFFFFU)
34913#define OCOTP_HDCP_TX_CERT31_BITS_SHIFT (0U)
34914#define OCOTP_HDCP_TX_CERT31_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT31_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT31_BITS_MASK)
34915/*! @} */
34916
34917/*! @name HDCP_TX_CERT32 - Value of OTP Bank17 Word0 (HDCP Key) */
34918/*! @{ */
34919#define OCOTP_HDCP_TX_CERT32_BITS_MASK (0xFFFFFFFFU)
34920#define OCOTP_HDCP_TX_CERT32_BITS_SHIFT (0U)
34921#define OCOTP_HDCP_TX_CERT32_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT32_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT32_BITS_MASK)
34922/*! @} */
34923
34924/*! @name HDCP_TX_CERT33 - Value of OTP Bank17 Word1 (HDCP Key) */
34925/*! @{ */
34926#define OCOTP_HDCP_TX_CERT33_BITS_MASK (0xFFFFFFFFU)
34927#define OCOTP_HDCP_TX_CERT33_BITS_SHIFT (0U)
34928#define OCOTP_HDCP_TX_CERT33_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT33_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT33_BITS_MASK)
34929/*! @} */
34930
34931/*! @name HDCP_TX_CERT34 - Value of OTP Bank16 Word0 (HDCP Key) */
34932/*! @{ */
34933#define OCOTP_HDCP_TX_CERT34_BITS_MASK (0xFFFFFFFFU)
34934#define OCOTP_HDCP_TX_CERT34_BITS_SHIFT (0U)
34935#define OCOTP_HDCP_TX_CERT34_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT34_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT34_BITS_MASK)
34936/*! @} */
34937
34938/*! @name HDCP_TX_CERT35 - Value of OTP Bank16 Word0 (HDCP Key) */
34939/*! @{ */
34940#define OCOTP_HDCP_TX_CERT35_BITS_MASK (0xFFFFFFFFU)
34941#define OCOTP_HDCP_TX_CERT35_BITS_SHIFT (0U)
34942#define OCOTP_HDCP_TX_CERT35_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT35_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT35_BITS_MASK)
34943/*! @} */
34944
34945/*! @name HDCP_TX_CERT36 - Value of OTP Bank16 Word0 (HDCP Key) */
34946/*! @{ */
34947#define OCOTP_HDCP_TX_CERT36_BITS_MASK (0xFFFFFFFFU)
34948#define OCOTP_HDCP_TX_CERT36_BITS_SHIFT (0U)
34949#define OCOTP_HDCP_TX_CERT36_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT36_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT36_BITS_MASK)
34950/*! @} */
34951
34952/*! @name HDCP_TX_CERT37 - Value of OTP Bank16 Word0 (HDCP Key) */
34953/*! @{ */
34954#define OCOTP_HDCP_TX_CERT37_BITS_MASK (0xFFFFFFFFU)
34955#define OCOTP_HDCP_TX_CERT37_BITS_SHIFT (0U)
34956#define OCOTP_HDCP_TX_CERT37_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT37_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT37_BITS_MASK)
34957/*! @} */
34958
34959/*! @name HDCP_TX_CERT38 - Value of OTP Bank16 Word0 (HDCP Key) */
34960/*! @{ */
34961#define OCOTP_HDCP_TX_CERT38_BITS_MASK (0xFFFFFFFFU)
34962#define OCOTP_HDCP_TX_CERT38_BITS_SHIFT (0U)
34963#define OCOTP_HDCP_TX_CERT38_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT38_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT38_BITS_MASK)
34964/*! @} */
34965
34966/*! @name HDCP_TX_CERT39 - Value of OTP Bank16 Word0 (HDCP Key) */
34967/*! @{ */
34968#define OCOTP_HDCP_TX_CERT39_BITS_MASK (0xFFFFFFFFU)
34969#define OCOTP_HDCP_TX_CERT39_BITS_SHIFT (0U)
34970#define OCOTP_HDCP_TX_CERT39_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT39_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT39_BITS_MASK)
34971/*! @} */
34972
34973/*! @name HDCP_TX_CERT40 - Value of OTP Bank17 Word0 (HDCP Key) */
34974/*! @{ */
34975#define OCOTP_HDCP_TX_CERT40_BITS_MASK (0xFFFFFFFFU)
34976#define OCOTP_HDCP_TX_CERT40_BITS_SHIFT (0U)
34977#define OCOTP_HDCP_TX_CERT40_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT40_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT40_BITS_MASK)
34978/*! @} */
34979
34980/*! @name HDCP_TX_CERT41 - Value of OTP Bank17 Word1 (HDCP Key) */
34981/*! @{ */
34982#define OCOTP_HDCP_TX_CERT41_BITS_MASK (0xFFFFFFFFU)
34983#define OCOTP_HDCP_TX_CERT41_BITS_SHIFT (0U)
34984#define OCOTP_HDCP_TX_CERT41_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT41_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT41_BITS_MASK)
34985/*! @} */
34986
34987/*! @name HDCP_TX_CERT42 - Value of OTP Bank16 Word0 (HDCP Key) */
34988/*! @{ */
34989#define OCOTP_HDCP_TX_CERT42_BITS_MASK (0xFFFFFFFFU)
34990#define OCOTP_HDCP_TX_CERT42_BITS_SHIFT (0U)
34991#define OCOTP_HDCP_TX_CERT42_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT42_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT42_BITS_MASK)
34992/*! @} */
34993
34994/*! @name HDCP_TX_CERT43 - Value of OTP Bank16 Word0 (HDCP Key) */
34995/*! @{ */
34996#define OCOTP_HDCP_TX_CERT43_BITS_MASK (0xFFFFFFFFU)
34997#define OCOTP_HDCP_TX_CERT43_BITS_SHIFT (0U)
34998#define OCOTP_HDCP_TX_CERT43_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT43_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT43_BITS_MASK)
34999/*! @} */
35000
35001/*! @name HDCP_TX_CERT44 - Value of OTP Bank16 Word0 (HDCP Key) */
35002/*! @{ */
35003#define OCOTP_HDCP_TX_CERT44_BITS_MASK (0xFFFFFFFFU)
35004#define OCOTP_HDCP_TX_CERT44_BITS_SHIFT (0U)
35005#define OCOTP_HDCP_TX_CERT44_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT44_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT44_BITS_MASK)
35006/*! @} */
35007
35008/*! @name HDCP_TX_CERT45 - Value of OTP Bank16 Word1 (HDCP Key) */
35009/*! @{ */
35010#define OCOTP_HDCP_TX_CERT45_BITS_MASK (0xFFFFFFFFU)
35011#define OCOTP_HDCP_TX_CERT45_BITS_SHIFT (0U)
35012#define OCOTP_HDCP_TX_CERT45_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT45_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT45_BITS_MASK)
35013/*! @} */
35014
35015/*! @name HDCP_TX_CERT46 - Value of OTP Bank16 Word0 (HDCP Key) */
35016/*! @{ */
35017#define OCOTP_HDCP_TX_CERT46_BITS_MASK (0xFFFFFFFFU)
35018#define OCOTP_HDCP_TX_CERT46_BITS_SHIFT (0U)
35019#define OCOTP_HDCP_TX_CERT46_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT46_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT46_BITS_MASK)
35020/*! @} */
35021
35022/*! @name HDCP_TX_CERT47 - Value of OTP Bank16 Word0 (HDCP Key) */
35023/*! @{ */
35024#define OCOTP_HDCP_TX_CERT47_BITS_MASK (0xFFFFFFFFU)
35025#define OCOTP_HDCP_TX_CERT47_BITS_SHIFT (0U)
35026#define OCOTP_HDCP_TX_CERT47_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT47_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT47_BITS_MASK)
35027/*! @} */
35028
35029/*! @name HDCP_TX_CERT48 - Value of OTP Bank17 Word0 (HDCP Key) */
35030/*! @{ */
35031#define OCOTP_HDCP_TX_CERT48_BITS_MASK (0xFFFFFFFFU)
35032#define OCOTP_HDCP_TX_CERT48_BITS_SHIFT (0U)
35033#define OCOTP_HDCP_TX_CERT48_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT48_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT48_BITS_MASK)
35034/*! @} */
35035
35036/*! @name HDCP_TX_CERT49 - Value of OTP Bank17 Word1 (HDCP Key) */
35037/*! @{ */
35038#define OCOTP_HDCP_TX_CERT49_BITS_MASK (0xFFFFFFFFU)
35039#define OCOTP_HDCP_TX_CERT49_BITS_SHIFT (0U)
35040#define OCOTP_HDCP_TX_CERT49_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT49_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT49_BITS_MASK)
35041/*! @} */
35042
35043/*! @name HDCP_TX_CERT50 - Value of OTP Bank16 Word0 (HDCP Key) */
35044/*! @{ */
35045#define OCOTP_HDCP_TX_CERT50_BITS_MASK (0xFFFFFFFFU)
35046#define OCOTP_HDCP_TX_CERT50_BITS_SHIFT (0U)
35047#define OCOTP_HDCP_TX_CERT50_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT50_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT50_BITS_MASK)
35048/*! @} */
35049
35050/*! @name HDCP_TX_CERT51 - Value of OTP Bank16 Word0 (HDCP Key) */
35051/*! @{ */
35052#define OCOTP_HDCP_TX_CERT51_BITS_MASK (0xFFFFFFFFU)
35053#define OCOTP_HDCP_TX_CERT51_BITS_SHIFT (0U)
35054#define OCOTP_HDCP_TX_CERT51_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT51_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT51_BITS_MASK)
35055/*! @} */
35056
35057/*! @name HDCP_TX_CERT52 - Value of OTP Bank16 Word0 (HDCP Key) */
35058/*! @{ */
35059#define OCOTP_HDCP_TX_CERT52_BITS_MASK (0xFFFFFFFFU)
35060#define OCOTP_HDCP_TX_CERT52_BITS_SHIFT (0U)
35061#define OCOTP_HDCP_TX_CERT52_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT52_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT52_BITS_MASK)
35062/*! @} */
35063
35064/*! @name HDCP_TX_CERT53 - Value of OTP Bank16 Word0 (HDCP Key) */
35065/*! @{ */
35066#define OCOTP_HDCP_TX_CERT53_BITS_MASK (0xFFFFFFFFU)
35067#define OCOTP_HDCP_TX_CERT53_BITS_SHIFT (0U)
35068#define OCOTP_HDCP_TX_CERT53_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT53_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT53_BITS_MASK)
35069/*! @} */
35070
35071/*! @name HDCP_TX_CERT54 - Value of OTP Bank16 Word0 (HDCP Key) */
35072/*! @{ */
35073#define OCOTP_HDCP_TX_CERT54_BITS_MASK (0xFFFFFFFFU)
35074#define OCOTP_HDCP_TX_CERT54_BITS_SHIFT (0U)
35075#define OCOTP_HDCP_TX_CERT54_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT54_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT54_BITS_MASK)
35076/*! @} */
35077
35078/*! @name HDCP_TX_CERT55 - Value of OTP Bank16 Word0 (HDCP Key) */
35079/*! @{ */
35080#define OCOTP_HDCP_TX_CERT55_BITS_MASK (0xFFFFFFFFU)
35081#define OCOTP_HDCP_TX_CERT55_BITS_SHIFT (0U)
35082#define OCOTP_HDCP_TX_CERT55_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT55_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT55_BITS_MASK)
35083/*! @} */
35084
35085/*! @name HDCP_TX_CERT56 - Value of OTP Bank17 Word0 (HDCP Key) */
35086/*! @{ */
35087#define OCOTP_HDCP_TX_CERT56_BITS_MASK (0xFFFFFFFFU)
35088#define OCOTP_HDCP_TX_CERT56_BITS_SHIFT (0U)
35089#define OCOTP_HDCP_TX_CERT56_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT56_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT56_BITS_MASK)
35090/*! @} */
35091
35092/*! @name HDCP_TX_CERT57 - Value of OTP Bank17 Word1 (HDCP Key) */
35093/*! @{ */
35094#define OCOTP_HDCP_TX_CERT57_BITS_MASK (0xFFFFFFFFU)
35095#define OCOTP_HDCP_TX_CERT57_BITS_SHIFT (0U)
35096#define OCOTP_HDCP_TX_CERT57_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT57_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT57_BITS_MASK)
35097/*! @} */
35098
35099/*! @name HDCP_TX_CERT58 - Value of OTP Bank16 Word0 (HDCP Key) */
35100/*! @{ */
35101#define OCOTP_HDCP_TX_CERT58_BITS_MASK (0xFFFFFFFFU)
35102#define OCOTP_HDCP_TX_CERT58_BITS_SHIFT (0U)
35103#define OCOTP_HDCP_TX_CERT58_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT58_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT58_BITS_MASK)
35104/*! @} */
35105
35106/*! @name HDCP_TX_CERT59 - Value of OTP Bank16 Word0 (HDCP Key) */
35107/*! @{ */
35108#define OCOTP_HDCP_TX_CERT59_BITS_MASK (0xFFFFFFFFU)
35109#define OCOTP_HDCP_TX_CERT59_BITS_SHIFT (0U)
35110#define OCOTP_HDCP_TX_CERT59_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT59_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT59_BITS_MASK)
35111/*! @} */
35112
35113/*! @name HDCP_TX_CERT60 - Value of OTP Bank16 Word0 (HDCP Key) */
35114/*! @{ */
35115#define OCOTP_HDCP_TX_CERT60_BITS_MASK (0xFFFFFFFFU)
35116#define OCOTP_HDCP_TX_CERT60_BITS_SHIFT (0U)
35117#define OCOTP_HDCP_TX_CERT60_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT60_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT60_BITS_MASK)
35118/*! @} */
35119
35120/*! @name HDCP_TX_CERT61 - Value of OTP Bank16 Word1 (HDCP Key) */
35121/*! @{ */
35122#define OCOTP_HDCP_TX_CERT61_BITS_MASK (0xFFFFFFFFU)
35123#define OCOTP_HDCP_TX_CERT61_BITS_SHIFT (0U)
35124#define OCOTP_HDCP_TX_CERT61_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT61_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT61_BITS_MASK)
35125/*! @} */
35126
35127/*! @name HDCP_TX_CERT62 - Value of OTP Bank16 Word0 (HDCP Key) */
35128/*! @{ */
35129#define OCOTP_HDCP_TX_CERT62_BITS_MASK (0xFFFFFFFFU)
35130#define OCOTP_HDCP_TX_CERT62_BITS_SHIFT (0U)
35131#define OCOTP_HDCP_TX_CERT62_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT62_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT62_BITS_MASK)
35132/*! @} */
35133
35134/*! @name HDCP_TX_CERT63 - Value of OTP Bank16 Word0 (HDCP Key) */
35135/*! @{ */
35136#define OCOTP_HDCP_TX_CERT63_BITS_MASK (0xFFFFFFFFU)
35137#define OCOTP_HDCP_TX_CERT63_BITS_SHIFT (0U)
35138#define OCOTP_HDCP_TX_CERT63_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT63_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT63_BITS_MASK)
35139/*! @} */
35140
35141/*! @name HDCP_TX_CERT64 - Value of OTP Bank17 Word0 (HDCP Key) */
35142/*! @{ */
35143#define OCOTP_HDCP_TX_CERT64_BITS_MASK (0xFFFFFFFFU)
35144#define OCOTP_HDCP_TX_CERT64_BITS_SHIFT (0U)
35145#define OCOTP_HDCP_TX_CERT64_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT64_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT64_BITS_MASK)
35146/*! @} */
35147
35148/*! @name HDCP_TX_CERT65 - Value of OTP Bank17 Word1 (HDCP Key) */
35149/*! @{ */
35150#define OCOTP_HDCP_TX_CERT65_BITS_MASK (0xFFFFFFFFU)
35151#define OCOTP_HDCP_TX_CERT65_BITS_SHIFT (0U)
35152#define OCOTP_HDCP_TX_CERT65_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT65_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT65_BITS_MASK)
35153/*! @} */
35154
35155/*! @name HDCP_TX_CERT66 - Value of OTP Bank16 Word0 (HDCP Key) */
35156/*! @{ */
35157#define OCOTP_HDCP_TX_CERT66_BITS_MASK (0xFFFFFFFFU)
35158#define OCOTP_HDCP_TX_CERT66_BITS_SHIFT (0U)
35159#define OCOTP_HDCP_TX_CERT66_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT66_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT66_BITS_MASK)
35160/*! @} */
35161
35162/*! @name HDCP_TX_CERT67 - Value of OTP Bank16 Word0 (HDCP Key) */
35163/*! @{ */
35164#define OCOTP_HDCP_TX_CERT67_BITS_MASK (0xFFFFFFFFU)
35165#define OCOTP_HDCP_TX_CERT67_BITS_SHIFT (0U)
35166#define OCOTP_HDCP_TX_CERT67_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT67_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT67_BITS_MASK)
35167/*! @} */
35168
35169/*! @name HDCP_TX_CERT68 - Value of OTP Bank16 Word0 (HDCP Key) */
35170/*! @{ */
35171#define OCOTP_HDCP_TX_CERT68_BITS_MASK (0xFFFFFFFFU)
35172#define OCOTP_HDCP_TX_CERT68_BITS_SHIFT (0U)
35173#define OCOTP_HDCP_TX_CERT68_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT68_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT68_BITS_MASK)
35174/*! @} */
35175
35176/*! @name HDCP_TX_CERT69 - Value of OTP Bank16 Word0 (HDCP Key) */
35177/*! @{ */
35178#define OCOTP_HDCP_TX_CERT69_BITS_MASK (0xFFFFFFFFU)
35179#define OCOTP_HDCP_TX_CERT69_BITS_SHIFT (0U)
35180#define OCOTP_HDCP_TX_CERT69_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT69_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT69_BITS_MASK)
35181/*! @} */
35182
35183/*! @name HDCP_TX_CERT70 - Value of OTP Bank16 Word0 (HDCP Key) */
35184/*! @{ */
35185#define OCOTP_HDCP_TX_CERT70_BITS_MASK (0xFFFFFFFFU)
35186#define OCOTP_HDCP_TX_CERT70_BITS_SHIFT (0U)
35187#define OCOTP_HDCP_TX_CERT70_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT70_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT70_BITS_MASK)
35188/*! @} */
35189
35190/*! @name HDCP_TX_CERT71 - Value of OTP Bank16 Word0 (HDCP Key) */
35191/*! @{ */
35192#define OCOTP_HDCP_TX_CERT71_BITS_MASK (0xFFFFFFFFU)
35193#define OCOTP_HDCP_TX_CERT71_BITS_SHIFT (0U)
35194#define OCOTP_HDCP_TX_CERT71_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT71_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT71_BITS_MASK)
35195/*! @} */
35196
35197/*! @name HDCP_TX_CERT72 - Value of OTP Bank17 Word0 (HDCP Key) */
35198/*! @{ */
35199#define OCOTP_HDCP_TX_CERT72_BITS_MASK (0xFFFFFFFFU)
35200#define OCOTP_HDCP_TX_CERT72_BITS_SHIFT (0U)
35201#define OCOTP_HDCP_TX_CERT72_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT72_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT72_BITS_MASK)
35202/*! @} */
35203
35204/*! @name HDCP_TX_CERT73 - Value of OTP Bank17 Word1 (HDCP Key) */
35205/*! @{ */
35206#define OCOTP_HDCP_TX_CERT73_BITS_MASK (0xFFFFFFFFU)
35207#define OCOTP_HDCP_TX_CERT73_BITS_SHIFT (0U)
35208#define OCOTP_HDCP_TX_CERT73_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT73_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT73_BITS_MASK)
35209/*! @} */
35210
35211/*! @name HDCP_TX_CERT74 - Value of OTP Bank16 Word0 (HDCP Key) */
35212/*! @{ */
35213#define OCOTP_HDCP_TX_CERT74_BITS_MASK (0xFFFFFFFFU)
35214#define OCOTP_HDCP_TX_CERT74_BITS_SHIFT (0U)
35215#define OCOTP_HDCP_TX_CERT74_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT74_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT74_BITS_MASK)
35216/*! @} */
35217
35218/*! @name HDCP_TX_CERT75 - Value of OTP Bank16 Word0 (HDCP Key) */
35219/*! @{ */
35220#define OCOTP_HDCP_TX_CERT75_BITS_MASK (0xFFFFFFFFU)
35221#define OCOTP_HDCP_TX_CERT75_BITS_SHIFT (0U)
35222#define OCOTP_HDCP_TX_CERT75_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT75_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT75_BITS_MASK)
35223/*! @} */
35224
35225/*! @name HDCP_TX_CERT76 - Value of OTP Bank16 Word0 (HDCP Key) */
35226/*! @{ */
35227#define OCOTP_HDCP_TX_CERT76_BITS_MASK (0xFFFFFFFFU)
35228#define OCOTP_HDCP_TX_CERT76_BITS_SHIFT (0U)
35229#define OCOTP_HDCP_TX_CERT76_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT76_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT76_BITS_MASK)
35230/*! @} */
35231
35232/*! @name HDCP_TX_CERT77 - Value of OTP Bank16 Word1 (HDCP Key) */
35233/*! @{ */
35234#define OCOTP_HDCP_TX_CERT77_BITS_MASK (0xFFFFFFFFU)
35235#define OCOTP_HDCP_TX_CERT77_BITS_SHIFT (0U)
35236#define OCOTP_HDCP_TX_CERT77_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT77_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT77_BITS_MASK)
35237/*! @} */
35238
35239/*! @name HDCP_TX_CERT78 - Value of OTP Bank16 Word0 (HDCP Key) */
35240/*! @{ */
35241#define OCOTP_HDCP_TX_CERT78_BITS_MASK (0xFFFFFFFFU)
35242#define OCOTP_HDCP_TX_CERT78_BITS_SHIFT (0U)
35243#define OCOTP_HDCP_TX_CERT78_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT78_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT78_BITS_MASK)
35244/*! @} */
35245
35246/*! @name HDCP_TX_CERT79 - Value of OTP Bank16 Word0 (HDCP Key) */
35247/*! @{ */
35248#define OCOTP_HDCP_TX_CERT79_BITS_MASK (0xFFFFFFFFU)
35249#define OCOTP_HDCP_TX_CERT79_BITS_SHIFT (0U)
35250#define OCOTP_HDCP_TX_CERT79_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT79_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT79_BITS_MASK)
35251/*! @} */
35252
35253/*! @name HDCP_TX_CERT80 - Value of OTP Bank17 Word0 (HDCP Key) */
35254/*! @{ */
35255#define OCOTP_HDCP_TX_CERT80_BITS_MASK (0xFFFFFFFFU)
35256#define OCOTP_HDCP_TX_CERT80_BITS_SHIFT (0U)
35257#define OCOTP_HDCP_TX_CERT80_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT80_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT80_BITS_MASK)
35258/*! @} */
35259
35260/*! @name HDCP_TX_CERT81 - Value of OTP Bank17 Word1 (HDCP Key) */
35261/*! @{ */
35262#define OCOTP_HDCP_TX_CERT81_BITS_MASK (0xFFFFFFFFU)
35263#define OCOTP_HDCP_TX_CERT81_BITS_SHIFT (0U)
35264#define OCOTP_HDCP_TX_CERT81_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT81_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT81_BITS_MASK)
35265/*! @} */
35266
35267/*! @name HDCP_TX_CERT82 - Value of OTP Bank16 Word0 (HDCP Key) */
35268/*! @{ */
35269#define OCOTP_HDCP_TX_CERT82_BITS_MASK (0xFFFFFFFFU)
35270#define OCOTP_HDCP_TX_CERT82_BITS_SHIFT (0U)
35271#define OCOTP_HDCP_TX_CERT82_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT82_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT82_BITS_MASK)
35272/*! @} */
35273
35274/*! @name HDCP_TX_CERT83 - Value of OTP Bank16 Word0 (HDCP Key) */
35275/*! @{ */
35276#define OCOTP_HDCP_TX_CERT83_BITS_MASK (0xFFFFFFFFU)
35277#define OCOTP_HDCP_TX_CERT83_BITS_SHIFT (0U)
35278#define OCOTP_HDCP_TX_CERT83_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT83_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT83_BITS_MASK)
35279/*! @} */
35280
35281/*! @name HDCP_TX_CERT84 - Value of OTP Bank16 Word0 (HDCP Key) */
35282/*! @{ */
35283#define OCOTP_HDCP_TX_CERT84_BITS_MASK (0xFFFFFFFFU)
35284#define OCOTP_HDCP_TX_CERT84_BITS_SHIFT (0U)
35285#define OCOTP_HDCP_TX_CERT84_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT84_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT84_BITS_MASK)
35286/*! @} */
35287
35288/*! @name HDCP_TX_CERT85 - Value of OTP Bank16 Word0 (HDCP Key) */
35289/*! @{ */
35290#define OCOTP_HDCP_TX_CERT85_BITS_MASK (0xFFFFFFFFU)
35291#define OCOTP_HDCP_TX_CERT85_BITS_SHIFT (0U)
35292#define OCOTP_HDCP_TX_CERT85_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT85_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT85_BITS_MASK)
35293/*! @} */
35294
35295/*! @name HDCP_TX_CERT86 - Value of OTP Bank16 Word0 (HDCP Key) */
35296/*! @{ */
35297#define OCOTP_HDCP_TX_CERT86_BITS_MASK (0xFFFFFFFFU)
35298#define OCOTP_HDCP_TX_CERT86_BITS_SHIFT (0U)
35299#define OCOTP_HDCP_TX_CERT86_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT86_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT86_BITS_MASK)
35300/*! @} */
35301
35302/*! @name HDCP_TX_CERT87 - Value of OTP Bank16 Word0 (HDCP Key) */
35303/*! @{ */
35304#define OCOTP_HDCP_TX_CERT87_BITS_MASK (0xFFFFFFFFU)
35305#define OCOTP_HDCP_TX_CERT87_BITS_SHIFT (0U)
35306#define OCOTP_HDCP_TX_CERT87_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT87_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT87_BITS_MASK)
35307/*! @} */
35308
35309/*! @name HDCP_TX_CERT88 - Value of OTP Bank17 Word0 (HDCP Key) */
35310/*! @{ */
35311#define OCOTP_HDCP_TX_CERT88_BITS_MASK (0xFFFFFFFFU)
35312#define OCOTP_HDCP_TX_CERT88_BITS_SHIFT (0U)
35313#define OCOTP_HDCP_TX_CERT88_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT88_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT88_BITS_MASK)
35314/*! @} */
35315
35316/*! @name HDCP_TX_CERT89 - Value of OTP Bank17 Word1 (HDCP Key) */
35317/*! @{ */
35318#define OCOTP_HDCP_TX_CERT89_BITS_MASK (0xFFFFFFFFU)
35319#define OCOTP_HDCP_TX_CERT89_BITS_SHIFT (0U)
35320#define OCOTP_HDCP_TX_CERT89_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT89_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT89_BITS_MASK)
35321/*! @} */
35322
35323/*! @name HDCP_TX_CERT90 - Value of OTP Bank16 Word0 (HDCP Key) */
35324/*! @{ */
35325#define OCOTP_HDCP_TX_CERT90_BITS_MASK (0xFFFFFFFFU)
35326#define OCOTP_HDCP_TX_CERT90_BITS_SHIFT (0U)
35327#define OCOTP_HDCP_TX_CERT90_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT90_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT90_BITS_MASK)
35328/*! @} */
35329
35330/*! @name HDCP_TX_CERT91 - Value of OTP Bank16 Word0 (HDCP Key) */
35331/*! @{ */
35332#define OCOTP_HDCP_TX_CERT91_BITS_MASK (0xFFFFFFFFU)
35333#define OCOTP_HDCP_TX_CERT91_BITS_SHIFT (0U)
35334#define OCOTP_HDCP_TX_CERT91_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT91_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT91_BITS_MASK)
35335/*! @} */
35336
35337/*! @name HDCP_TX_CERT92 - Value of OTP Bank16 Word0 (HDCP Key) */
35338/*! @{ */
35339#define OCOTP_HDCP_TX_CERT92_BITS_MASK (0xFFFFFFFFU)
35340#define OCOTP_HDCP_TX_CERT92_BITS_SHIFT (0U)
35341#define OCOTP_HDCP_TX_CERT92_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT92_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT92_BITS_MASK)
35342/*! @} */
35343
35344/*! @name HDCP_TX_CERT93 - Value of OTP Bank16 Word1 (HDCP Key) */
35345/*! @{ */
35346#define OCOTP_HDCP_TX_CERT93_BITS_MASK (0xFFFFFFFFU)
35347#define OCOTP_HDCP_TX_CERT93_BITS_SHIFT (0U)
35348#define OCOTP_HDCP_TX_CERT93_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT93_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT93_BITS_MASK)
35349/*! @} */
35350
35351/*! @name HDCP_TX_CERT94 - Value of OTP Bank16 Word0 (HDCP Key) */
35352/*! @{ */
35353#define OCOTP_HDCP_TX_CERT94_BITS_MASK (0xFFFFFFFFU)
35354#define OCOTP_HDCP_TX_CERT94_BITS_SHIFT (0U)
35355#define OCOTP_HDCP_TX_CERT94_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT94_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT94_BITS_MASK)
35356/*! @} */
35357
35358/*! @name HDCP_TX_CERT95 - Value of OTP Bank16 Word0 (HDCP Key) */
35359/*! @{ */
35360#define OCOTP_HDCP_TX_CERT95_BITS_MASK (0xFFFFFFFFU)
35361#define OCOTP_HDCP_TX_CERT95_BITS_SHIFT (0U)
35362#define OCOTP_HDCP_TX_CERT95_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT95_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT95_BITS_MASK)
35363/*! @} */
35364
35365/*! @name HDCP_KEY0 - Value of OTP Bank17 Word0 (HDCP Key) */
35366/*! @{ */
35367#define OCOTP_HDCP_KEY0_BITS_MASK (0xFFFFFFFFU)
35368#define OCOTP_HDCP_KEY0_BITS_SHIFT (0U)
35369#define OCOTP_HDCP_KEY0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY0_BITS_SHIFT)) & OCOTP_HDCP_KEY0_BITS_MASK)
35370/*! @} */
35371
35372/*! @name HDCP_KEY1 - Value of OTP Bank17 Word1 (HDCP Key) */
35373/*! @{ */
35374#define OCOTP_HDCP_KEY1_BITS_MASK (0xFFFFFFFFU)
35375#define OCOTP_HDCP_KEY1_BITS_SHIFT (0U)
35376#define OCOTP_HDCP_KEY1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY1_BITS_SHIFT)) & OCOTP_HDCP_KEY1_BITS_MASK)
35377/*! @} */
35378
35379/*! @name HDCP_KEY2 - Value of OTP Bank16 Word0 (HDCP Key) */
35380/*! @{ */
35381#define OCOTP_HDCP_KEY2_BITS_MASK (0xFFFFFFFFU)
35382#define OCOTP_HDCP_KEY2_BITS_SHIFT (0U)
35383#define OCOTP_HDCP_KEY2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY2_BITS_SHIFT)) & OCOTP_HDCP_KEY2_BITS_MASK)
35384/*! @} */
35385
35386/*! @name HDCP_KEY3 - Value of OTP Bank16 Word0 (HDCP Key) */
35387/*! @{ */
35388#define OCOTP_HDCP_KEY3_BITS_MASK (0xFFFFFFFFU)
35389#define OCOTP_HDCP_KEY3_BITS_SHIFT (0U)
35390#define OCOTP_HDCP_KEY3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY3_BITS_SHIFT)) & OCOTP_HDCP_KEY3_BITS_MASK)
35391/*! @} */
35392
35393/*! @name HDCP_KEY4 - Value of OTP Bank16 Word0 (HDCP Key) */
35394/*! @{ */
35395#define OCOTP_HDCP_KEY4_BITS_MASK (0xFFFFFFFFU)
35396#define OCOTP_HDCP_KEY4_BITS_SHIFT (0U)
35397#define OCOTP_HDCP_KEY4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY4_BITS_SHIFT)) & OCOTP_HDCP_KEY4_BITS_MASK)
35398/*! @} */
35399
35400/*! @name HDCP_KEY5 - Value of OTP Bank16 Word0 (HDCP Key) */
35401/*! @{ */
35402#define OCOTP_HDCP_KEY5_BITS_MASK (0xFFFFFFFFU)
35403#define OCOTP_HDCP_KEY5_BITS_SHIFT (0U)
35404#define OCOTP_HDCP_KEY5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY5_BITS_SHIFT)) & OCOTP_HDCP_KEY5_BITS_MASK)
35405/*! @} */
35406
35407/*! @name HDCP_KEY6 - Value of OTP Bank16 Word0 (HDCP Key) */
35408/*! @{ */
35409#define OCOTP_HDCP_KEY6_BITS_MASK (0xFFFFFFFFU)
35410#define OCOTP_HDCP_KEY6_BITS_SHIFT (0U)
35411#define OCOTP_HDCP_KEY6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY6_BITS_SHIFT)) & OCOTP_HDCP_KEY6_BITS_MASK)
35412/*! @} */
35413
35414/*! @name HDCP_KEY7 - Value of OTP Bank16 Word0 (HDCP Key) */
35415/*! @{ */
35416#define OCOTP_HDCP_KEY7_BITS_MASK (0xFFFFFFFFU)
35417#define OCOTP_HDCP_KEY7_BITS_SHIFT (0U)
35418#define OCOTP_HDCP_KEY7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY7_BITS_SHIFT)) & OCOTP_HDCP_KEY7_BITS_MASK)
35419/*! @} */
35420
35421/*! @name HDCP_KEY8 - Value of OTP Bank17 Word0 (HDCP Key) */
35422/*! @{ */
35423#define OCOTP_HDCP_KEY8_BITS_MASK (0xFFFFFFFFU)
35424#define OCOTP_HDCP_KEY8_BITS_SHIFT (0U)
35425#define OCOTP_HDCP_KEY8_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY8_BITS_SHIFT)) & OCOTP_HDCP_KEY8_BITS_MASK)
35426/*! @} */
35427
35428/*! @name HDCP_KEY9 - Value of OTP Bank17 Word1 (HDCP Key) */
35429/*! @{ */
35430#define OCOTP_HDCP_KEY9_BITS_MASK (0xFFFFFFFFU)
35431#define OCOTP_HDCP_KEY9_BITS_SHIFT (0U)
35432#define OCOTP_HDCP_KEY9_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY9_BITS_SHIFT)) & OCOTP_HDCP_KEY9_BITS_MASK)
35433/*! @} */
35434
35435/*! @name HDCP_KEY10 - Value of OTP Bank16 Word0 (HDCP Key) */
35436/*! @{ */
35437#define OCOTP_HDCP_KEY10_BITS_MASK (0xFFFFFFFFU)
35438#define OCOTP_HDCP_KEY10_BITS_SHIFT (0U)
35439#define OCOTP_HDCP_KEY10_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY10_BITS_SHIFT)) & OCOTP_HDCP_KEY10_BITS_MASK)
35440/*! @} */
35441
35442/*! @name HDCP_KEY11 - Value of OTP Bank16 Word0 (HDCP Key) */
35443/*! @{ */
35444#define OCOTP_HDCP_KEY11_BITS_MASK (0xFFFFFFFFU)
35445#define OCOTP_HDCP_KEY11_BITS_SHIFT (0U)
35446#define OCOTP_HDCP_KEY11_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY11_BITS_SHIFT)) & OCOTP_HDCP_KEY11_BITS_MASK)
35447/*! @} */
35448
35449/*! @name HDCP_KEY12 - Value of OTP Bank16 Word0 (HDCP Key) */
35450/*! @{ */
35451#define OCOTP_HDCP_KEY12_BITS_MASK (0xFFFFFFFFU)
35452#define OCOTP_HDCP_KEY12_BITS_SHIFT (0U)
35453#define OCOTP_HDCP_KEY12_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY12_BITS_SHIFT)) & OCOTP_HDCP_KEY12_BITS_MASK)
35454/*! @} */
35455
35456/*! @name HDCP_KEY13 - Value of OTP Bank16 Word1 (HDCP Key) */
35457/*! @{ */
35458#define OCOTP_HDCP_KEY13_BITS_MASK (0xFFFFFFFFU)
35459#define OCOTP_HDCP_KEY13_BITS_SHIFT (0U)
35460#define OCOTP_HDCP_KEY13_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY13_BITS_SHIFT)) & OCOTP_HDCP_KEY13_BITS_MASK)
35461/*! @} */
35462
35463/*! @name HDCP_KEY14 - Value of OTP Bank16 Word0 (HDCP Key) */
35464/*! @{ */
35465#define OCOTP_HDCP_KEY14_BITS_MASK (0xFFFFFFFFU)
35466#define OCOTP_HDCP_KEY14_BITS_SHIFT (0U)
35467#define OCOTP_HDCP_KEY14_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY14_BITS_SHIFT)) & OCOTP_HDCP_KEY14_BITS_MASK)
35468/*! @} */
35469
35470/*! @name HDCP_KEY15 - Value of OTP Bank16 Word0 (HDCP Key) */
35471/*! @{ */
35472#define OCOTP_HDCP_KEY15_BITS_MASK (0xFFFFFFFFU)
35473#define OCOTP_HDCP_KEY15_BITS_SHIFT (0U)
35474#define OCOTP_HDCP_KEY15_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY15_BITS_SHIFT)) & OCOTP_HDCP_KEY15_BITS_MASK)
35475/*! @} */
35476
35477/*! @name HDCP_KEY16 - Value of OTP Bank17 Word0 (HDCP Key) */
35478/*! @{ */
35479#define OCOTP_HDCP_KEY16_BITS_MASK (0xFFFFFFFFU)
35480#define OCOTP_HDCP_KEY16_BITS_SHIFT (0U)
35481#define OCOTP_HDCP_KEY16_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY16_BITS_SHIFT)) & OCOTP_HDCP_KEY16_BITS_MASK)
35482/*! @} */
35483
35484/*! @name HDCP_KEY17 - Value of OTP Bank17 Word1 (HDCP Key) */
35485/*! @{ */
35486#define OCOTP_HDCP_KEY17_BITS_MASK (0xFFFFFFFFU)
35487#define OCOTP_HDCP_KEY17_BITS_SHIFT (0U)
35488#define OCOTP_HDCP_KEY17_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY17_BITS_SHIFT)) & OCOTP_HDCP_KEY17_BITS_MASK)
35489/*! @} */
35490
35491/*! @name HDCP_KEY18 - Value of OTP Bank16 Word0 (HDCP Key) */
35492/*! @{ */
35493#define OCOTP_HDCP_KEY18_BITS_MASK (0xFFFFFFFFU)
35494#define OCOTP_HDCP_KEY18_BITS_SHIFT (0U)
35495#define OCOTP_HDCP_KEY18_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY18_BITS_SHIFT)) & OCOTP_HDCP_KEY18_BITS_MASK)
35496/*! @} */
35497
35498/*! @name HDCP_KEY19 - Value of OTP Bank16 Word0 (HDCP Key) */
35499/*! @{ */
35500#define OCOTP_HDCP_KEY19_BITS_MASK (0xFFFFFFFFU)
35501#define OCOTP_HDCP_KEY19_BITS_SHIFT (0U)
35502#define OCOTP_HDCP_KEY19_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY19_BITS_SHIFT)) & OCOTP_HDCP_KEY19_BITS_MASK)
35503/*! @} */
35504
35505/*! @name HDCP_KEY20 - Value of OTP Bank16 Word0 (HDCP Key) */
35506/*! @{ */
35507#define OCOTP_HDCP_KEY20_BITS_MASK (0xFFFFFFFFU)
35508#define OCOTP_HDCP_KEY20_BITS_SHIFT (0U)
35509#define OCOTP_HDCP_KEY20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY20_BITS_SHIFT)) & OCOTP_HDCP_KEY20_BITS_MASK)
35510/*! @} */
35511
35512/*! @name HDCP_KEY21 - Value of OTP Bank16 Word0 (HDCP Key) */
35513/*! @{ */
35514#define OCOTP_HDCP_KEY21_BITS_MASK (0xFFFFFFFFU)
35515#define OCOTP_HDCP_KEY21_BITS_SHIFT (0U)
35516#define OCOTP_HDCP_KEY21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY21_BITS_SHIFT)) & OCOTP_HDCP_KEY21_BITS_MASK)
35517/*! @} */
35518
35519/*! @name HDCP_KEY22 - Value of OTP Bank16 Word0 (HDCP Key) */
35520/*! @{ */
35521#define OCOTP_HDCP_KEY22_BITS_MASK (0xFFFFFFFFU)
35522#define OCOTP_HDCP_KEY22_BITS_SHIFT (0U)
35523#define OCOTP_HDCP_KEY22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY22_BITS_SHIFT)) & OCOTP_HDCP_KEY22_BITS_MASK)
35524/*! @} */
35525
35526/*! @name HDCP_KEY23 - Value of OTP Bank16 Word0 (HDCP Key) */
35527/*! @{ */
35528#define OCOTP_HDCP_KEY23_BITS_MASK (0xFFFFFFFFU)
35529#define OCOTP_HDCP_KEY23_BITS_SHIFT (0U)
35530#define OCOTP_HDCP_KEY23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY23_BITS_SHIFT)) & OCOTP_HDCP_KEY23_BITS_MASK)
35531/*! @} */
35532
35533/*! @name HDCP_KEY24 - Value of OTP Bank17 Word0 (HDCP Key) */
35534/*! @{ */
35535#define OCOTP_HDCP_KEY24_BITS_MASK (0xFFFFFFFFU)
35536#define OCOTP_HDCP_KEY24_BITS_SHIFT (0U)
35537#define OCOTP_HDCP_KEY24_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY24_BITS_SHIFT)) & OCOTP_HDCP_KEY24_BITS_MASK)
35538/*! @} */
35539
35540/*! @name HDCP_KEY25 - Value of OTP Bank17 Word1 (HDCP Key) */
35541/*! @{ */
35542#define OCOTP_HDCP_KEY25_BITS_MASK (0xFFFFFFFFU)
35543#define OCOTP_HDCP_KEY25_BITS_SHIFT (0U)
35544#define OCOTP_HDCP_KEY25_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY25_BITS_SHIFT)) & OCOTP_HDCP_KEY25_BITS_MASK)
35545/*! @} */
35546
35547/*! @name HDCP_KEY26 - Value of OTP Bank16 Word0 (HDCP Key) */
35548/*! @{ */
35549#define OCOTP_HDCP_KEY26_BITS_MASK (0xFFFFFFFFU)
35550#define OCOTP_HDCP_KEY26_BITS_SHIFT (0U)
35551#define OCOTP_HDCP_KEY26_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY26_BITS_SHIFT)) & OCOTP_HDCP_KEY26_BITS_MASK)
35552/*! @} */
35553
35554/*! @name HDCP_KEY27 - Value of OTP Bank16 Word0 (HDCP Key) */
35555/*! @{ */
35556#define OCOTP_HDCP_KEY27_BITS_MASK (0xFFFFFFFFU)
35557#define OCOTP_HDCP_KEY27_BITS_SHIFT (0U)
35558#define OCOTP_HDCP_KEY27_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY27_BITS_SHIFT)) & OCOTP_HDCP_KEY27_BITS_MASK)
35559/*! @} */
35560
35561/*! @name HDCP_KEY28 - Value of OTP Bank16 Word0 (HDCP Key) */
35562/*! @{ */
35563#define OCOTP_HDCP_KEY28_BITS_MASK (0xFFFFFFFFU)
35564#define OCOTP_HDCP_KEY28_BITS_SHIFT (0U)
35565#define OCOTP_HDCP_KEY28_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY28_BITS_SHIFT)) & OCOTP_HDCP_KEY28_BITS_MASK)
35566/*! @} */
35567
35568/*! @name HDCP_KEY29 - Value of OTP Bank16 Word1 (HDCP Key) */
35569/*! @{ */
35570#define OCOTP_HDCP_KEY29_BITS_MASK (0xFFFFFFFFU)
35571#define OCOTP_HDCP_KEY29_BITS_SHIFT (0U)
35572#define OCOTP_HDCP_KEY29_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY29_BITS_SHIFT)) & OCOTP_HDCP_KEY29_BITS_MASK)
35573/*! @} */
35574
35575/*! @name HDCP_KEY30 - Value of OTP Bank16 Word0 (HDCP Key) */
35576/*! @{ */
35577#define OCOTP_HDCP_KEY30_BITS_MASK (0xFFFFFFFFU)
35578#define OCOTP_HDCP_KEY30_BITS_SHIFT (0U)
35579#define OCOTP_HDCP_KEY30_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY30_BITS_SHIFT)) & OCOTP_HDCP_KEY30_BITS_MASK)
35580/*! @} */
35581
35582/*! @name HDCP_KEY31 - Value of OTP Bank16 Word0 (HDCP Key) */
35583/*! @{ */
35584#define OCOTP_HDCP_KEY31_BITS_MASK (0xFFFFFFFFU)
35585#define OCOTP_HDCP_KEY31_BITS_SHIFT (0U)
35586#define OCOTP_HDCP_KEY31_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY31_BITS_SHIFT)) & OCOTP_HDCP_KEY31_BITS_MASK)
35587/*! @} */
35588
35589/*! @name HDCP_KEY32 - Value of OTP Bank17 Word0 (HDCP Key) */
35590/*! @{ */
35591#define OCOTP_HDCP_KEY32_BITS_MASK (0xFFFFFFFFU)
35592#define OCOTP_HDCP_KEY32_BITS_SHIFT (0U)
35593#define OCOTP_HDCP_KEY32_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY32_BITS_SHIFT)) & OCOTP_HDCP_KEY32_BITS_MASK)
35594/*! @} */
35595
35596/*! @name HDCP_KEY33 - Value of OTP Bank17 Word1 (HDCP Key) */
35597/*! @{ */
35598#define OCOTP_HDCP_KEY33_BITS_MASK (0xFFFFFFFFU)
35599#define OCOTP_HDCP_KEY33_BITS_SHIFT (0U)
35600#define OCOTP_HDCP_KEY33_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY33_BITS_SHIFT)) & OCOTP_HDCP_KEY33_BITS_MASK)
35601/*! @} */
35602
35603/*! @name HDCP_KEY34 - Value of OTP Bank16 Word0 (HDCP Key) */
35604/*! @{ */
35605#define OCOTP_HDCP_KEY34_BITS_MASK (0xFFFFFFFFU)
35606#define OCOTP_HDCP_KEY34_BITS_SHIFT (0U)
35607#define OCOTP_HDCP_KEY34_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY34_BITS_SHIFT)) & OCOTP_HDCP_KEY34_BITS_MASK)
35608/*! @} */
35609
35610/*! @name HDCP_KEY35 - Value of OTP Bank16 Word0 (HDCP Key) */
35611/*! @{ */
35612#define OCOTP_HDCP_KEY35_BITS_MASK (0xFFFFFFFFU)
35613#define OCOTP_HDCP_KEY35_BITS_SHIFT (0U)
35614#define OCOTP_HDCP_KEY35_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY35_BITS_SHIFT)) & OCOTP_HDCP_KEY35_BITS_MASK)
35615/*! @} */
35616
35617/*! @name HDCP_KEY36 - Value of OTP Bank16 Word0 (HDCP Key) */
35618/*! @{ */
35619#define OCOTP_HDCP_KEY36_BITS_MASK (0xFFFFFFFFU)
35620#define OCOTP_HDCP_KEY36_BITS_SHIFT (0U)
35621#define OCOTP_HDCP_KEY36_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY36_BITS_SHIFT)) & OCOTP_HDCP_KEY36_BITS_MASK)
35622/*! @} */
35623
35624/*! @name HDCP_KEY37 - Value of OTP Bank16 Word0 (HDCP Key) */
35625/*! @{ */
35626#define OCOTP_HDCP_KEY37_BITS_MASK (0xFFFFFFFFU)
35627#define OCOTP_HDCP_KEY37_BITS_SHIFT (0U)
35628#define OCOTP_HDCP_KEY37_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY37_BITS_SHIFT)) & OCOTP_HDCP_KEY37_BITS_MASK)
35629/*! @} */
35630
35631/*! @name HDCP_KEY38 - Value of OTP Bank16 Word0 (HDCP Key) */
35632/*! @{ */
35633#define OCOTP_HDCP_KEY38_BITS_MASK (0xFFFFFFFFU)
35634#define OCOTP_HDCP_KEY38_BITS_SHIFT (0U)
35635#define OCOTP_HDCP_KEY38_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY38_BITS_SHIFT)) & OCOTP_HDCP_KEY38_BITS_MASK)
35636/*! @} */
35637
35638/*! @name HDCP_KEY39 - Value of OTP Bank16 Word0 (HDCP Key) */
35639/*! @{ */
35640#define OCOTP_HDCP_KEY39_BITS_MASK (0xFFFFFFFFU)
35641#define OCOTP_HDCP_KEY39_BITS_SHIFT (0U)
35642#define OCOTP_HDCP_KEY39_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY39_BITS_SHIFT)) & OCOTP_HDCP_KEY39_BITS_MASK)
35643/*! @} */
35644
35645/*! @name HDCP_KEY40 - Value of OTP Bank17 Word0 (HDCP Key) */
35646/*! @{ */
35647#define OCOTP_HDCP_KEY40_BITS_MASK (0xFFFFFFFFU)
35648#define OCOTP_HDCP_KEY40_BITS_SHIFT (0U)
35649#define OCOTP_HDCP_KEY40_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY40_BITS_SHIFT)) & OCOTP_HDCP_KEY40_BITS_MASK)
35650/*! @} */
35651
35652/*! @name HDCP_KEY41 - Value of OTP Bank17 Word1 (HDCP Key) */
35653/*! @{ */
35654#define OCOTP_HDCP_KEY41_BITS_MASK (0xFFFFFFFFU)
35655#define OCOTP_HDCP_KEY41_BITS_SHIFT (0U)
35656#define OCOTP_HDCP_KEY41_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY41_BITS_SHIFT)) & OCOTP_HDCP_KEY41_BITS_MASK)
35657/*! @} */
35658
35659/*! @name HDCP_KEY42 - Value of OTP Bank16 Word0 (HDCP Key) */
35660/*! @{ */
35661#define OCOTP_HDCP_KEY42_BITS_MASK (0xFFFFFFFFU)
35662#define OCOTP_HDCP_KEY42_BITS_SHIFT (0U)
35663#define OCOTP_HDCP_KEY42_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY42_BITS_SHIFT)) & OCOTP_HDCP_KEY42_BITS_MASK)
35664/*! @} */
35665
35666/*! @name HDCP_KEY43 - Value of OTP Bank16 Word0 (HDCP Key) */
35667/*! @{ */
35668#define OCOTP_HDCP_KEY43_BITS_MASK (0xFFFFFFFFU)
35669#define OCOTP_HDCP_KEY43_BITS_SHIFT (0U)
35670#define OCOTP_HDCP_KEY43_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY43_BITS_SHIFT)) & OCOTP_HDCP_KEY43_BITS_MASK)
35671/*! @} */
35672
35673/*! @name HDCP_KEY44 - Value of OTP Bank16 Word0 (HDCP Key) */
35674/*! @{ */
35675#define OCOTP_HDCP_KEY44_BITS_MASK (0xFFFFFFFFU)
35676#define OCOTP_HDCP_KEY44_BITS_SHIFT (0U)
35677#define OCOTP_HDCP_KEY44_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY44_BITS_SHIFT)) & OCOTP_HDCP_KEY44_BITS_MASK)
35678/*! @} */
35679
35680/*! @name HDCP_KEY45 - Value of OTP Bank16 Word1 (HDCP Key) */
35681/*! @{ */
35682#define OCOTP_HDCP_KEY45_BITS_MASK (0xFFFFFFFFU)
35683#define OCOTP_HDCP_KEY45_BITS_SHIFT (0U)
35684#define OCOTP_HDCP_KEY45_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY45_BITS_SHIFT)) & OCOTP_HDCP_KEY45_BITS_MASK)
35685/*! @} */
35686
35687/*! @name HDCP_KEY46 - Value of OTP Bank16 Word0 (HDCP Key) */
35688/*! @{ */
35689#define OCOTP_HDCP_KEY46_BITS_MASK (0xFFFFFFFFU)
35690#define OCOTP_HDCP_KEY46_BITS_SHIFT (0U)
35691#define OCOTP_HDCP_KEY46_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY46_BITS_SHIFT)) & OCOTP_HDCP_KEY46_BITS_MASK)
35692/*! @} */
35693
35694/*! @name HDCP_KEY47 - Value of OTP Bank16 Word0 (HDCP Key) */
35695/*! @{ */
35696#define OCOTP_HDCP_KEY47_BITS_MASK (0xFFFFFFFFU)
35697#define OCOTP_HDCP_KEY47_BITS_SHIFT (0U)
35698#define OCOTP_HDCP_KEY47_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY47_BITS_SHIFT)) & OCOTP_HDCP_KEY47_BITS_MASK)
35699/*! @} */
35700
35701/*! @name HDCP_KEY48 - Value of OTP Bank17 Word0 (HDCP Key) */
35702/*! @{ */
35703#define OCOTP_HDCP_KEY48_BITS_MASK (0xFFFFFFFFU)
35704#define OCOTP_HDCP_KEY48_BITS_SHIFT (0U)
35705#define OCOTP_HDCP_KEY48_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY48_BITS_SHIFT)) & OCOTP_HDCP_KEY48_BITS_MASK)
35706/*! @} */
35707
35708/*! @name HDCP_KEY49 - Value of OTP Bank17 Word1 (HDCP Key) */
35709/*! @{ */
35710#define OCOTP_HDCP_KEY49_BITS_MASK (0xFFFFFFFFU)
35711#define OCOTP_HDCP_KEY49_BITS_SHIFT (0U)
35712#define OCOTP_HDCP_KEY49_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY49_BITS_SHIFT)) & OCOTP_HDCP_KEY49_BITS_MASK)
35713/*! @} */
35714
35715/*! @name HDCP_KEY50 - Value of OTP Bank16 Word0 (HDCP Key) */
35716/*! @{ */
35717#define OCOTP_HDCP_KEY50_BITS_MASK (0xFFFFFFFFU)
35718#define OCOTP_HDCP_KEY50_BITS_SHIFT (0U)
35719#define OCOTP_HDCP_KEY50_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY50_BITS_SHIFT)) & OCOTP_HDCP_KEY50_BITS_MASK)
35720/*! @} */
35721
35722/*! @name HDCP_KEY51 - Value of OTP Bank16 Word0 (HDCP Key) */
35723/*! @{ */
35724#define OCOTP_HDCP_KEY51_BITS_MASK (0xFFFFFFFFU)
35725#define OCOTP_HDCP_KEY51_BITS_SHIFT (0U)
35726#define OCOTP_HDCP_KEY51_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY51_BITS_SHIFT)) & OCOTP_HDCP_KEY51_BITS_MASK)
35727/*! @} */
35728
35729/*! @name HDCP_KEY52 - Value of OTP Bank16 Word0 (HDCP Key) */
35730/*! @{ */
35731#define OCOTP_HDCP_KEY52_BITS_MASK (0xFFFFFFFFU)
35732#define OCOTP_HDCP_KEY52_BITS_SHIFT (0U)
35733#define OCOTP_HDCP_KEY52_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY52_BITS_SHIFT)) & OCOTP_HDCP_KEY52_BITS_MASK)
35734/*! @} */
35735
35736/*! @name HDCP_KEY53 - Value of OTP Bank16 Word0 (HDCP Key) */
35737/*! @{ */
35738#define OCOTP_HDCP_KEY53_BITS_MASK (0xFFFFFFFFU)
35739#define OCOTP_HDCP_KEY53_BITS_SHIFT (0U)
35740#define OCOTP_HDCP_KEY53_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY53_BITS_SHIFT)) & OCOTP_HDCP_KEY53_BITS_MASK)
35741/*! @} */
35742
35743/*! @name HDCP_KEY54 - Value of OTP Bank16 Word0 (HDCP Key) */
35744/*! @{ */
35745#define OCOTP_HDCP_KEY54_BITS_MASK (0xFFFFFFFFU)
35746#define OCOTP_HDCP_KEY54_BITS_SHIFT (0U)
35747#define OCOTP_HDCP_KEY54_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY54_BITS_SHIFT)) & OCOTP_HDCP_KEY54_BITS_MASK)
35748/*! @} */
35749
35750/*! @name HDCP_KEY55 - Value of OTP Bank16 Word0 (HDCP Key) */
35751/*! @{ */
35752#define OCOTP_HDCP_KEY55_BITS_MASK (0xFFFFFFFFU)
35753#define OCOTP_HDCP_KEY55_BITS_SHIFT (0U)
35754#define OCOTP_HDCP_KEY55_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY55_BITS_SHIFT)) & OCOTP_HDCP_KEY55_BITS_MASK)
35755/*! @} */
35756
35757/*! @name HDCP_KEY56 - Value of OTP Bank17 Word0 (HDCP Key) */
35758/*! @{ */
35759#define OCOTP_HDCP_KEY56_BITS_MASK (0xFFFFFFFFU)
35760#define OCOTP_HDCP_KEY56_BITS_SHIFT (0U)
35761#define OCOTP_HDCP_KEY56_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY56_BITS_SHIFT)) & OCOTP_HDCP_KEY56_BITS_MASK)
35762/*! @} */
35763
35764/*! @name HDCP_KEY57 - Value of OTP Bank17 Word1 (HDCP Key) */
35765/*! @{ */
35766#define OCOTP_HDCP_KEY57_BITS_MASK (0xFFFFFFFFU)
35767#define OCOTP_HDCP_KEY57_BITS_SHIFT (0U)
35768#define OCOTP_HDCP_KEY57_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY57_BITS_SHIFT)) & OCOTP_HDCP_KEY57_BITS_MASK)
35769/*! @} */
35770
35771/*! @name HDCP_KEY58 - Value of OTP Bank16 Word0 (HDCP Key) */
35772/*! @{ */
35773#define OCOTP_HDCP_KEY58_BITS_MASK (0xFFFFFFFFU)
35774#define OCOTP_HDCP_KEY58_BITS_SHIFT (0U)
35775#define OCOTP_HDCP_KEY58_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY58_BITS_SHIFT)) & OCOTP_HDCP_KEY58_BITS_MASK)
35776/*! @} */
35777
35778/*! @name HDCP_KEY59 - Value of OTP Bank16 Word0 (HDCP Key) */
35779/*! @{ */
35780#define OCOTP_HDCP_KEY59_BITS_MASK (0xFFFFFFFFU)
35781#define OCOTP_HDCP_KEY59_BITS_SHIFT (0U)
35782#define OCOTP_HDCP_KEY59_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY59_BITS_SHIFT)) & OCOTP_HDCP_KEY59_BITS_MASK)
35783/*! @} */
35784
35785/*! @name HDCP_KEY60 - Value of OTP Bank16 Word0 (HDCP Key) */
35786/*! @{ */
35787#define OCOTP_HDCP_KEY60_BITS_MASK (0xFFFFFFFFU)
35788#define OCOTP_HDCP_KEY60_BITS_SHIFT (0U)
35789#define OCOTP_HDCP_KEY60_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY60_BITS_SHIFT)) & OCOTP_HDCP_KEY60_BITS_MASK)
35790/*! @} */
35791
35792/*! @name HDCP_KEY61 - Value of OTP Bank16 Word1 (HDCP Key) */
35793/*! @{ */
35794#define OCOTP_HDCP_KEY61_BITS_MASK (0xFFFFFFFFU)
35795#define OCOTP_HDCP_KEY61_BITS_SHIFT (0U)
35796#define OCOTP_HDCP_KEY61_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY61_BITS_SHIFT)) & OCOTP_HDCP_KEY61_BITS_MASK)
35797/*! @} */
35798
35799/*! @name HDCP_KEY62 - Value of OTP Bank16 Word0 (HDCP Key) */
35800/*! @{ */
35801#define OCOTP_HDCP_KEY62_BITS_MASK (0xFFFFFFFFU)
35802#define OCOTP_HDCP_KEY62_BITS_SHIFT (0U)
35803#define OCOTP_HDCP_KEY62_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY62_BITS_SHIFT)) & OCOTP_HDCP_KEY62_BITS_MASK)
35804/*! @} */
35805
35806/*! @name HDCP_KEY63 - Value of OTP Bank16 Word0 (HDCP Key) */
35807/*! @{ */
35808#define OCOTP_HDCP_KEY63_BITS_MASK (0xFFFFFFFFU)
35809#define OCOTP_HDCP_KEY63_BITS_SHIFT (0U)
35810#define OCOTP_HDCP_KEY63_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY63_BITS_SHIFT)) & OCOTP_HDCP_KEY63_BITS_MASK)
35811/*! @} */
35812
35813/*! @name HDCP_KEY64 - Value of OTP Bank17 Word0 (HDCP Key) */
35814/*! @{ */
35815#define OCOTP_HDCP_KEY64_BITS_MASK (0xFFFFFFFFU)
35816#define OCOTP_HDCP_KEY64_BITS_SHIFT (0U)
35817#define OCOTP_HDCP_KEY64_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY64_BITS_SHIFT)) & OCOTP_HDCP_KEY64_BITS_MASK)
35818/*! @} */
35819
35820/*! @name HDCP_KEY65 - Value of OTP Bank17 Word1 (HDCP Key) */
35821/*! @{ */
35822#define OCOTP_HDCP_KEY65_BITS_MASK (0xFFFFFFFFU)
35823#define OCOTP_HDCP_KEY65_BITS_SHIFT (0U)
35824#define OCOTP_HDCP_KEY65_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY65_BITS_SHIFT)) & OCOTP_HDCP_KEY65_BITS_MASK)
35825/*! @} */
35826
35827/*! @name HDCP_KEY66 - Value of OTP Bank16 Word0 (HDCP Key) */
35828/*! @{ */
35829#define OCOTP_HDCP_KEY66_BITS_MASK (0xFFFFFFFFU)
35830#define OCOTP_HDCP_KEY66_BITS_SHIFT (0U)
35831#define OCOTP_HDCP_KEY66_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY66_BITS_SHIFT)) & OCOTP_HDCP_KEY66_BITS_MASK)
35832/*! @} */
35833
35834/*! @name HDCP_KEY67 - Value of OTP Bank16 Word0 (HDCP Key) */
35835/*! @{ */
35836#define OCOTP_HDCP_KEY67_BITS_MASK (0xFFFFFFFFU)
35837#define OCOTP_HDCP_KEY67_BITS_SHIFT (0U)
35838#define OCOTP_HDCP_KEY67_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY67_BITS_SHIFT)) & OCOTP_HDCP_KEY67_BITS_MASK)
35839/*! @} */
35840
35841/*! @name HDCP_KEY68 - Value of OTP Bank16 Word0 (HDCP Key) */
35842/*! @{ */
35843#define OCOTP_HDCP_KEY68_BITS_MASK (0xFFFFFFFFU)
35844#define OCOTP_HDCP_KEY68_BITS_SHIFT (0U)
35845#define OCOTP_HDCP_KEY68_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY68_BITS_SHIFT)) & OCOTP_HDCP_KEY68_BITS_MASK)
35846/*! @} */
35847
35848/*! @name HDCP_KEY69 - Value of OTP Bank16 Word0 (HDCP Key) */
35849/*! @{ */
35850#define OCOTP_HDCP_KEY69_BITS_MASK (0xFFFFFFFFU)
35851#define OCOTP_HDCP_KEY69_BITS_SHIFT (0U)
35852#define OCOTP_HDCP_KEY69_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY69_BITS_SHIFT)) & OCOTP_HDCP_KEY69_BITS_MASK)
35853/*! @} */
35854
35855/*! @name HDCP_KEY70 - Value of OTP Bank16 Word0 (HDCP Key) */
35856/*! @{ */
35857#define OCOTP_HDCP_KEY70_BITS_MASK (0xFFFFFFFFU)
35858#define OCOTP_HDCP_KEY70_BITS_SHIFT (0U)
35859#define OCOTP_HDCP_KEY70_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY70_BITS_SHIFT)) & OCOTP_HDCP_KEY70_BITS_MASK)
35860/*! @} */
35861
35862/*! @name HDCP_KEY71 - Value of OTP Bank16 Word0 (HDCP Key) */
35863/*! @{ */
35864#define OCOTP_HDCP_KEY71_BITS_MASK (0xFFFFFFFFU)
35865#define OCOTP_HDCP_KEY71_BITS_SHIFT (0U)
35866#define OCOTP_HDCP_KEY71_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY71_BITS_SHIFT)) & OCOTP_HDCP_KEY71_BITS_MASK)
35867/*! @} */
35868
35869
35870/*!
35871 * @}
35872 */ /* end of group OCOTP_Register_Masks */
35873
35874
35875/* OCOTP - Peripheral instance base addresses */
35876/** Peripheral OCOTP base address */
35877#define OCOTP_BASE (0x30350000u)
35878/** Peripheral OCOTP base pointer */
35879#define OCOTP ((OCOTP_Type *)OCOTP_BASE)
35880/** Array initializer of OCOTP peripheral base addresses */
35881#define OCOTP_BASE_ADDRS { OCOTP_BASE }
35882/** Array initializer of OCOTP peripheral base pointers */
35883#define OCOTP_BASE_PTRS { OCOTP }
35884
35885/*!
35886 * @}
35887 */ /* end of group OCOTP_Peripheral_Access_Layer */
35888
35889
35890/* ----------------------------------------------------------------------------
35891 -- PWM Peripheral Access Layer
35892 ---------------------------------------------------------------------------- */
35893
35894/*!
35895 * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
35896 * @{
35897 */
35898
35899/** PWM - Register Layout Typedef */
35900typedef struct {
35901 __IO uint32_t PWMCR; /**< PWM Control Register, offset: 0x0 */
35902 __IO uint32_t PWMSR; /**< PWM Status Register, offset: 0x4 */
35903 __IO uint32_t PWMIR; /**< PWM Interrupt Register, offset: 0x8 */
35904 __IO uint32_t PWMSAR; /**< PWM Sample Register, offset: 0xC */
35905 __IO uint32_t PWMPR; /**< PWM Period Register, offset: 0x10 */
35906 __I uint32_t PWMCNR; /**< PWM Counter Register, offset: 0x14 */
35907} PWM_Type;
35908
35909/* ----------------------------------------------------------------------------
35910 -- PWM Register Masks
35911 ---------------------------------------------------------------------------- */
35912
35913/*!
35914 * @addtogroup PWM_Register_Masks PWM Register Masks
35915 * @{
35916 */
35917
35918/*! @name PWMCR - PWM Control Register */
35919/*! @{ */
35920#define PWM_PWMCR_EN_MASK (0x1U)
35921#define PWM_PWMCR_EN_SHIFT (0U)
35922/*! EN
35923 * 0b0..PWM disabled
35924 * 0b1..PWM enabled
35925 */
35926#define PWM_PWMCR_EN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_EN_SHIFT)) & PWM_PWMCR_EN_MASK)
35927#define PWM_PWMCR_REPEAT_MASK (0x6U)
35928#define PWM_PWMCR_REPEAT_SHIFT (1U)
35929/*! REPEAT
35930 * 0b00..Use each sample once
35931 * 0b01..Use each sample twice
35932 * 0b10..Use each sample four times
35933 * 0b11..Use each sample eight times
35934 */
35935#define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_REPEAT_SHIFT)) & PWM_PWMCR_REPEAT_MASK)
35936#define PWM_PWMCR_SWR_MASK (0x8U)
35937#define PWM_PWMCR_SWR_SHIFT (3U)
35938/*! SWR
35939 * 0b0..PWM is out of reset
35940 * 0b1..PWM is undergoing reset
35941 */
35942#define PWM_PWMCR_SWR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_SWR_SHIFT)) & PWM_PWMCR_SWR_MASK)
35943#define PWM_PWMCR_PRESCALER_MASK (0xFFF0U)
35944#define PWM_PWMCR_PRESCALER_SHIFT (4U)
35945/*! PRESCALER
35946 * 0b000000000000..Divide by 1
35947 * 0b000000000001..Divide by 2
35948 * 0b111111111111..Divide by 4096
35949 */
35950#define PWM_PWMCR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_PRESCALER_SHIFT)) & PWM_PWMCR_PRESCALER_MASK)
35951#define PWM_PWMCR_CLKSRC_MASK (0x30000U)
35952#define PWM_PWMCR_CLKSRC_SHIFT (16U)
35953/*! CLKSRC
35954 * 0b00..Clock is off
35955 * 0b01..ipg_clk
35956 * 0b10..ipg_clk_highfreq
35957 * 0b11..ipg_clk_32k
35958 */
35959#define PWM_PWMCR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_CLKSRC_SHIFT)) & PWM_PWMCR_CLKSRC_MASK)
35960#define PWM_PWMCR_POUTC_MASK (0xC0000U)
35961#define PWM_PWMCR_POUTC_SHIFT (18U)
35962/*! POUTC
35963 * 0b00..Output pin is set at rollover and cleared at comparison
35964 * 0b01..Output pin is cleared at rollover and set at comparison
35965 * 0b10..PWM output is disconnected
35966 * 0b11..PWM output is disconnected
35967 */
35968#define PWM_PWMCR_POUTC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_POUTC_SHIFT)) & PWM_PWMCR_POUTC_MASK)
35969#define PWM_PWMCR_HCTR_MASK (0x100000U)
35970#define PWM_PWMCR_HCTR_SHIFT (20U)
35971/*! HCTR
35972 * 0b0..Half word swapping does not take place
35973 * 0b1..Half words from write data bus are swapped
35974 */
35975#define PWM_PWMCR_HCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_HCTR_SHIFT)) & PWM_PWMCR_HCTR_MASK)
35976#define PWM_PWMCR_BCTR_MASK (0x200000U)
35977#define PWM_PWMCR_BCTR_SHIFT (21U)
35978/*! BCTR
35979 * 0b0..byte ordering remains the same
35980 * 0b1..byte ordering is reversed
35981 */
35982#define PWM_PWMCR_BCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_BCTR_SHIFT)) & PWM_PWMCR_BCTR_MASK)
35983#define PWM_PWMCR_DBGEN_MASK (0x400000U)
35984#define PWM_PWMCR_DBGEN_SHIFT (22U)
35985/*! DBGEN
35986 * 0b0..Inactive in debug mode
35987 * 0b1..Active in debug mode
35988 */
35989#define PWM_PWMCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DBGEN_SHIFT)) & PWM_PWMCR_DBGEN_MASK)
35990#define PWM_PWMCR_WAITEN_MASK (0x800000U)
35991#define PWM_PWMCR_WAITEN_SHIFT (23U)
35992/*! WAITEN
35993 * 0b0..Inactive in wait mode
35994 * 0b1..Active in wait mode
35995 */
35996#define PWM_PWMCR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_WAITEN_SHIFT)) & PWM_PWMCR_WAITEN_MASK)
35997#define PWM_PWMCR_DOZEN_MASK (0x1000000U)
35998#define PWM_PWMCR_DOZEN_SHIFT (24U)
35999/*! DOZEN
36000 * 0b0..Inactive in doze mode
36001 * 0b1..Active in doze mode
36002 */
36003#define PWM_PWMCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DOZEN_SHIFT)) & PWM_PWMCR_DOZEN_MASK)
36004#define PWM_PWMCR_STOPEN_MASK (0x2000000U)
36005#define PWM_PWMCR_STOPEN_SHIFT (25U)
36006/*! STOPEN
36007 * 0b0..Inactive in stop mode
36008 * 0b1..Active in stop mode
36009 */
36010#define PWM_PWMCR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_STOPEN_SHIFT)) & PWM_PWMCR_STOPEN_MASK)
36011#define PWM_PWMCR_FWM_MASK (0xC000000U)
36012#define PWM_PWMCR_FWM_SHIFT (26U)
36013/*! FWM
36014 * 0b00..FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO
36015 * 0b01..FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO
36016 * 0b10..FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO
36017 * 0b11..FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO
36018 */
36019#define PWM_PWMCR_FWM(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_FWM_SHIFT)) & PWM_PWMCR_FWM_MASK)
36020/*! @} */
36021
36022/*! @name PWMSR - PWM Status Register */
36023/*! @{ */
36024#define PWM_PWMSR_FIFOAV_MASK (0x7U)
36025#define PWM_PWMSR_FIFOAV_SHIFT (0U)
36026/*! FIFOAV
36027 * 0b000..No data available
36028 * 0b001..1 word of data in FIFO
36029 * 0b010..2 words of data in FIFO
36030 * 0b011..3 words of data in FIFO
36031 * 0b100..4 words of data in FIFO
36032 * 0b101..unused
36033 * 0b110..unused
36034 * 0b111..unused
36035 */
36036#define PWM_PWMSR_FIFOAV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FIFOAV_SHIFT)) & PWM_PWMSR_FIFOAV_MASK)
36037#define PWM_PWMSR_FE_MASK (0x8U)
36038#define PWM_PWMSR_FE_SHIFT (3U)
36039/*! FE
36040 * 0b0..Data level is above water mark
36041 * 0b1..When the data level falls below the mark set by FWM field
36042 */
36043#define PWM_PWMSR_FE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FE_SHIFT)) & PWM_PWMSR_FE_MASK)
36044#define PWM_PWMSR_ROV_MASK (0x10U)
36045#define PWM_PWMSR_ROV_SHIFT (4U)
36046/*! ROV
36047 * 0b0..Roll-over event not occurred
36048 * 0b1..Roll-over event occurred
36049 */
36050#define PWM_PWMSR_ROV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_ROV_SHIFT)) & PWM_PWMSR_ROV_MASK)
36051#define PWM_PWMSR_CMP_MASK (0x20U)
36052#define PWM_PWMSR_CMP_SHIFT (5U)
36053/*! CMP
36054 * 0b0..Compare event not occurred
36055 * 0b1..Compare event occurred
36056 */
36057#define PWM_PWMSR_CMP(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_CMP_SHIFT)) & PWM_PWMSR_CMP_MASK)
36058#define PWM_PWMSR_FWE_MASK (0x40U)
36059#define PWM_PWMSR_FWE_SHIFT (6U)
36060/*! FWE
36061 * 0b0..FIFO write error not occurred
36062 * 0b1..FIFO write error occurred
36063 */
36064#define PWM_PWMSR_FWE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FWE_SHIFT)) & PWM_PWMSR_FWE_MASK)
36065/*! @} */
36066
36067/*! @name PWMIR - PWM Interrupt Register */
36068/*! @{ */
36069#define PWM_PWMIR_FIE_MASK (0x1U)
36070#define PWM_PWMIR_FIE_SHIFT (0U)
36071/*! FIE
36072 * 0b0..FIFO Empty interrupt disabled
36073 * 0b1..FIFO Empty interrupt enabled
36074 */
36075#define PWM_PWMIR_FIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_FIE_SHIFT)) & PWM_PWMIR_FIE_MASK)
36076#define PWM_PWMIR_RIE_MASK (0x2U)
36077#define PWM_PWMIR_RIE_SHIFT (1U)
36078/*! RIE
36079 * 0b0..Roll-over interrupt not enabled
36080 * 0b1..Roll-over Interrupt enabled
36081 */
36082#define PWM_PWMIR_RIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_RIE_SHIFT)) & PWM_PWMIR_RIE_MASK)
36083#define PWM_PWMIR_CIE_MASK (0x4U)
36084#define PWM_PWMIR_CIE_SHIFT (2U)
36085/*! CIE
36086 * 0b0..Compare Interrupt not enabled
36087 * 0b1..Compare Interrupt enabled
36088 */
36089#define PWM_PWMIR_CIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_CIE_SHIFT)) & PWM_PWMIR_CIE_MASK)
36090/*! @} */
36091
36092/*! @name PWMSAR - PWM Sample Register */
36093/*! @{ */
36094#define PWM_PWMSAR_SAMPLE_MASK (0xFFFFU)
36095#define PWM_PWMSAR_SAMPLE_SHIFT (0U)
36096#define PWM_PWMSAR_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSAR_SAMPLE_SHIFT)) & PWM_PWMSAR_SAMPLE_MASK)
36097/*! @} */
36098
36099/*! @name PWMPR - PWM Period Register */
36100/*! @{ */
36101#define PWM_PWMPR_PERIOD_MASK (0xFFFFU)
36102#define PWM_PWMPR_PERIOD_SHIFT (0U)
36103#define PWM_PWMPR_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMPR_PERIOD_SHIFT)) & PWM_PWMPR_PERIOD_MASK)
36104/*! @} */
36105
36106/*! @name PWMCNR - PWM Counter Register */
36107/*! @{ */
36108#define PWM_PWMCNR_COUNT_MASK (0xFFFFU)
36109#define PWM_PWMCNR_COUNT_SHIFT (0U)
36110#define PWM_PWMCNR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCNR_COUNT_SHIFT)) & PWM_PWMCNR_COUNT_MASK)
36111/*! @} */
36112
36113
36114/*!
36115 * @}
36116 */ /* end of group PWM_Register_Masks */
36117
36118
36119/* PWM - Peripheral instance base addresses */
36120/** Peripheral PWM1 base address */
36121#define PWM1_BASE (0x30660000u)
36122/** Peripheral PWM1 base pointer */
36123#define PWM1 ((PWM_Type *)PWM1_BASE)
36124/** Peripheral PWM2 base address */
36125#define PWM2_BASE (0x30670000u)
36126/** Peripheral PWM2 base pointer */
36127#define PWM2 ((PWM_Type *)PWM2_BASE)
36128/** Peripheral PWM3 base address */
36129#define PWM3_BASE (0x30680000u)
36130/** Peripheral PWM3 base pointer */
36131#define PWM3 ((PWM_Type *)PWM3_BASE)
36132/** Peripheral PWM4 base address */
36133#define PWM4_BASE (0x30690000u)
36134/** Peripheral PWM4 base pointer */
36135#define PWM4 ((PWM_Type *)PWM4_BASE)
36136/** Array initializer of PWM peripheral base addresses */
36137#define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
36138/** Array initializer of PWM peripheral base pointers */
36139#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
36140/** Interrupt vectors for the PWM peripheral type */
36141#define PWM_IRQS { NotAvail_IRQn, PWM1_IRQn, PWM2_IRQn, PWM3_IRQn, PWM4_IRQn }
36142
36143/*!
36144 * @}
36145 */ /* end of group PWM_Peripheral_Access_Layer */
36146
36147
36148/* ----------------------------------------------------------------------------
36149 -- QuadSPI Peripheral Access Layer
36150 ---------------------------------------------------------------------------- */
36151
36152/*!
36153 * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer
36154 * @{
36155 */
36156
36157/** QuadSPI - Register Layout Typedef */
36158typedef struct {
36159 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
36160 uint8_t RESERVED_0[4];
36161 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */
36162 __IO uint32_t FLSHCR; /**< Flash Configuration Register, offset: 0xC */
36163 __IO uint32_t BUF0CR; /**< Buffer0 Configuration Register, offset: 0x10 */
36164 __IO uint32_t BUF1CR; /**< Buffer1 Configuration Register, offset: 0x14 */
36165 __IO uint32_t BUF2CR; /**< Buffer2 Configuration Register, offset: 0x18 */
36166 __IO uint32_t BUF3CR; /**< Buffer3 Configuration Register, offset: 0x1C */
36167 __IO uint32_t BFGENCR; /**< Buffer Generic Configuration Register, offset: 0x20 */
36168 uint8_t RESERVED_1[12];
36169 __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */
36170 __IO uint32_t BUF1IND; /**< Buffer1 Top Index Register, offset: 0x34 */
36171 __IO uint32_t BUF2IND; /**< Buffer2 Top Index Register, offset: 0x38 */
36172 uint8_t RESERVED_2[196];
36173 __IO uint32_t SFAR; /**< Serial Flash Address Register, offset: 0x100 */
36174 uint8_t RESERVED_3[4];
36175 __IO uint32_t SMPR; /**< Sampling Register, offset: 0x108 */
36176 __I uint32_t RBSR; /**< RX Buffer Status Register, offset: 0x10C */
36177 __IO uint32_t RBCT; /**< RX Buffer Control Register, offset: 0x110 */
36178 uint8_t RESERVED_4[60];
36179 __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */
36180 __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */
36181 uint8_t RESERVED_5[4];
36182 __I uint32_t SR; /**< Status Register, offset: 0x15C */
36183 __IO uint32_t FR; /**< Flag Register, offset: 0x160 */
36184 __IO uint32_t RSER; /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */
36185 __I uint32_t SPNDST; /**< Sequence Suspend Status Register, offset: 0x168 */
36186 __IO uint32_t SPTRCLR; /**< Sequence Pointer Clear Register, offset: 0x16C */
36187 uint8_t RESERVED_6[16];
36188 __IO uint32_t SFA1AD; /**< Serial Flash A1 Top Address, offset: 0x180 */
36189 __IO uint32_t SFA2AD; /**< Serial Flash A2 Top Address, offset: 0x184 */
36190 __IO uint32_t SFB1AD; /**< Serial Flash B1Top Address, offset: 0x188 */
36191 __IO uint32_t SFB2AD; /**< Serial Flash B2Top Address, offset: 0x18C */
36192 uint8_t RESERVED_7[112];
36193 __IO uint32_t RBDR[32]; /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */
36194 uint8_t RESERVED_8[128];
36195 __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x300 */
36196 __IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x304 */
36197 uint8_t RESERVED_9[8];
36198 __IO uint32_t LUT[64]; /**< Look-up Table register, array offset: 0x310, array step: 0x4 */
36199} QuadSPI_Type;
36200
36201/* ----------------------------------------------------------------------------
36202 -- QuadSPI Register Masks
36203 ---------------------------------------------------------------------------- */
36204
36205/*!
36206 * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks
36207 * @{
36208 */
36209
36210/*! @name MCR - Module Configuration Register */
36211/*! @{ */
36212#define QuadSPI_MCR_SWRSTSD_MASK (0x1U)
36213#define QuadSPI_MCR_SWRSTSD_SHIFT (0U)
36214/*! SWRSTSD
36215 * 0b0..No action
36216 * 0b1..Serial Flash domain flops are reset. Does not reset configuration registers. It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects.
36217 */
36218#define QuadSPI_MCR_SWRSTSD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTSD_SHIFT)) & QuadSPI_MCR_SWRSTSD_MASK)
36219#define QuadSPI_MCR_SWRSTHD_MASK (0x2U)
36220#define QuadSPI_MCR_SWRSTHD_SHIFT (1U)
36221/*! SWRSTHD
36222 * 0b0..No action
36223 * 0b1..AHB domain flops are reset. Does not reset configuration registers. It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects.
36224 */
36225#define QuadSPI_MCR_SWRSTHD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
36226#define QuadSPI_MCR_END_CFG_MASK (0xCU)
36227#define QuadSPI_MCR_END_CFG_SHIFT (2U)
36228#define QuadSPI_MCR_END_CFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_END_CFG_SHIFT)) & QuadSPI_MCR_END_CFG_MASK)
36229#define QuadSPI_MCR_DQS_EN_MASK (0x40U)
36230#define QuadSPI_MCR_DQS_EN_SHIFT (6U)
36231/*! DQS_EN
36232 * 0b0..DQS disabled.
36233 * 0b1..DQS enabled- When enabled, the incoming data is sampled on both the edges of DQS input when QSPI_MCR[DDR_EN] is set, else, on only one edge when QSPI_MCR[DDR_EN] is 0. The QSPI_SMPR[DDR_SMP] values are ignored.
36234 */
36235#define QuadSPI_MCR_DQS_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_EN_SHIFT)) & QuadSPI_MCR_DQS_EN_MASK)
36236#define QuadSPI_MCR_DDR_EN_MASK (0x80U)
36237#define QuadSPI_MCR_DDR_EN_SHIFT (7U)
36238/*! DDR_EN
36239 * 0b0..2x and 4x clocks are disabled for SDR instructions only
36240 * 0b1..2x and 4x clocks are enabled supports both SDR and DDR instruction.
36241 */
36242#define QuadSPI_MCR_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DDR_EN_SHIFT)) & QuadSPI_MCR_DDR_EN_MASK)
36243#define QuadSPI_MCR_CLR_RXF_MASK (0x400U)
36244#define QuadSPI_MCR_CLR_RXF_SHIFT (10U)
36245/*! CLR_RXF
36246 * 0b0..No action.
36247 * 0b1..Read and write pointers of the RX Buffer are reset to 0. QSPI_RBSR[RDBFL] is reset to 0.
36248 */
36249#define QuadSPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_RXF_SHIFT)) & QuadSPI_MCR_CLR_RXF_MASK)
36250#define QuadSPI_MCR_CLR_TXF_MASK (0x800U)
36251#define QuadSPI_MCR_CLR_TXF_SHIFT (11U)
36252/*! CLR_TXF
36253 * 0b0..No action.
36254 * 0b1..Read and write pointers of the TX Buffer are reset to 0. QSPI_TBSR[TRCTR] is reset to 0.
36255 */
36256#define QuadSPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_TXF_SHIFT)) & QuadSPI_MCR_CLR_TXF_MASK)
36257#define QuadSPI_MCR_MDIS_MASK (0x4000U)
36258#define QuadSPI_MCR_MDIS_SHIFT (14U)
36259/*! MDIS
36260 * 0b0..Enable QuadSPI clocks.
36261 * 0b1..Allow external logic to disable QuadSPI clocks.
36262 */
36263#define QuadSPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_MDIS_SHIFT)) & QuadSPI_MCR_MDIS_MASK)
36264#define QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD_MASK (0x1000000U)
36265#define QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD_SHIFT (24U)
36266#define QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD_SHIFT)) & QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD_MASK)
36267#define QuadSPI_MCR_DQS_LOOPBACK_EN_MASK (0x2000000U)
36268#define QuadSPI_MCR_DQS_LOOPBACK_EN_SHIFT (25U)
36269#define QuadSPI_MCR_DQS_LOOPBACK_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_LOOPBACK_EN_SHIFT)) & QuadSPI_MCR_DQS_LOOPBACK_EN_MASK)
36270#define QuadSPI_MCR_DQS_PHASE_EN_MASK (0x4000000U)
36271#define QuadSPI_MCR_DQS_PHASE_EN_SHIFT (26U)
36272#define QuadSPI_MCR_DQS_PHASE_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_PHASE_EN_SHIFT)) & QuadSPI_MCR_DQS_PHASE_EN_MASK)
36273/*! @} */
36274
36275/*! @name IPCR - IP Configuration Register */
36276/*! @{ */
36277#define QuadSPI_IPCR_IDATSZ_MASK (0xFFFFU)
36278#define QuadSPI_IPCR_IDATSZ_SHIFT (0U)
36279#define QuadSPI_IPCR_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_IDATSZ_SHIFT)) & QuadSPI_IPCR_IDATSZ_MASK)
36280#define QuadSPI_IPCR_PAR_EN_MASK (0x10000U)
36281#define QuadSPI_IPCR_PAR_EN_SHIFT (16U)
36282#define QuadSPI_IPCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_PAR_EN_SHIFT)) & QuadSPI_IPCR_PAR_EN_MASK)
36283#define QuadSPI_IPCR_SEQID_MASK (0xF000000U)
36284#define QuadSPI_IPCR_SEQID_SHIFT (24U)
36285#define QuadSPI_IPCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
36286/*! @} */
36287
36288/*! @name FLSHCR - Flash Configuration Register */
36289/*! @{ */
36290#define QuadSPI_FLSHCR_TCSS_MASK (0xFU)
36291#define QuadSPI_FLSHCR_TCSS_SHIFT (0U)
36292#define QuadSPI_FLSHCR_TCSS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSS_SHIFT)) & QuadSPI_FLSHCR_TCSS_MASK)
36293#define QuadSPI_FLSHCR_TCSH_MASK (0xF00U)
36294#define QuadSPI_FLSHCR_TCSH_SHIFT (8U)
36295#define QuadSPI_FLSHCR_TCSH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSH_SHIFT)) & QuadSPI_FLSHCR_TCSH_MASK)
36296#define QuadSPI_FLSHCR_TDH_MASK (0x30000U)
36297#define QuadSPI_FLSHCR_TDH_SHIFT (16U)
36298/*! TDH
36299 * 0b00..Data aligned with the posedge of Internal reference clock of QuadSPI
36300 * 0b01..Data aligned with 2x serial flash half clock
36301 * 0b10..Reserved
36302 * 0b11..Reserved
36303 */
36304#define QuadSPI_FLSHCR_TDH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK)
36305/*! @} */
36306
36307/*! @name BUF0CR - Buffer0 Configuration Register */
36308/*! @{ */
36309#define QuadSPI_BUF0CR_MSTRID_MASK (0xFU)
36310#define QuadSPI_BUF0CR_MSTRID_SHIFT (0U)
36311#define QuadSPI_BUF0CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_MSTRID_SHIFT)) & QuadSPI_BUF0CR_MSTRID_MASK)
36312#define QuadSPI_BUF0CR_ADATSZ_MASK (0xFF00U)
36313#define QuadSPI_BUF0CR_ADATSZ_SHIFT (8U)
36314#define QuadSPI_BUF0CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_ADATSZ_SHIFT)) & QuadSPI_BUF0CR_ADATSZ_MASK)
36315#define QuadSPI_BUF0CR_HP_EN_MASK (0x80000000U)
36316#define QuadSPI_BUF0CR_HP_EN_SHIFT (31U)
36317#define QuadSPI_BUF0CR_HP_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_HP_EN_SHIFT)) & QuadSPI_BUF0CR_HP_EN_MASK)
36318/*! @} */
36319
36320/*! @name BUF1CR - Buffer1 Configuration Register */
36321/*! @{ */
36322#define QuadSPI_BUF1CR_MSTRID_MASK (0xFU)
36323#define QuadSPI_BUF1CR_MSTRID_SHIFT (0U)
36324#define QuadSPI_BUF1CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_MSTRID_SHIFT)) & QuadSPI_BUF1CR_MSTRID_MASK)
36325#define QuadSPI_BUF1CR_ADATSZ_MASK (0xFF00U)
36326#define QuadSPI_BUF1CR_ADATSZ_SHIFT (8U)
36327#define QuadSPI_BUF1CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_ADATSZ_SHIFT)) & QuadSPI_BUF1CR_ADATSZ_MASK)
36328/*! @} */
36329
36330/*! @name BUF2CR - Buffer2 Configuration Register */
36331/*! @{ */
36332#define QuadSPI_BUF2CR_MSTRID_MASK (0xFU)
36333#define QuadSPI_BUF2CR_MSTRID_SHIFT (0U)
36334#define QuadSPI_BUF2CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_MSTRID_SHIFT)) & QuadSPI_BUF2CR_MSTRID_MASK)
36335#define QuadSPI_BUF2CR_ADATSZ_MASK (0xFF00U)
36336#define QuadSPI_BUF2CR_ADATSZ_SHIFT (8U)
36337#define QuadSPI_BUF2CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_ADATSZ_SHIFT)) & QuadSPI_BUF2CR_ADATSZ_MASK)
36338/*! @} */
36339
36340/*! @name BUF3CR - Buffer3 Configuration Register */
36341/*! @{ */
36342#define QuadSPI_BUF3CR_MSTRID_MASK (0xFU)
36343#define QuadSPI_BUF3CR_MSTRID_SHIFT (0U)
36344#define QuadSPI_BUF3CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_MSTRID_SHIFT)) & QuadSPI_BUF3CR_MSTRID_MASK)
36345#define QuadSPI_BUF3CR_ADATSZ_MASK (0xFF00U)
36346#define QuadSPI_BUF3CR_ADATSZ_SHIFT (8U)
36347#define QuadSPI_BUF3CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ADATSZ_SHIFT)) & QuadSPI_BUF3CR_ADATSZ_MASK)
36348#define QuadSPI_BUF3CR_ALLMST_MASK (0x80000000U)
36349#define QuadSPI_BUF3CR_ALLMST_SHIFT (31U)
36350#define QuadSPI_BUF3CR_ALLMST(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ALLMST_SHIFT)) & QuadSPI_BUF3CR_ALLMST_MASK)
36351/*! @} */
36352
36353/*! @name BFGENCR - Buffer Generic Configuration Register */
36354/*! @{ */
36355#define QuadSPI_BFGENCR_SEQID_MASK (0xF000U)
36356#define QuadSPI_BFGENCR_SEQID_SHIFT (12U)
36357#define QuadSPI_BFGENCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_SEQID_SHIFT)) & QuadSPI_BFGENCR_SEQID_MASK)
36358#define QuadSPI_BFGENCR_PAR_EN_MASK (0x10000U)
36359#define QuadSPI_BFGENCR_PAR_EN_SHIFT (16U)
36360#define QuadSPI_BFGENCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_PAR_EN_SHIFT)) & QuadSPI_BFGENCR_PAR_EN_MASK)
36361/*! @} */
36362
36363/*! @name BUF0IND - Buffer0 Top Index Register */
36364/*! @{ */
36365#define QuadSPI_BUF0IND_TPINDX0_MASK (0xFFFFFFF8U)
36366#define QuadSPI_BUF0IND_TPINDX0_SHIFT (3U)
36367#define QuadSPI_BUF0IND_TPINDX0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0IND_TPINDX0_SHIFT)) & QuadSPI_BUF0IND_TPINDX0_MASK)
36368/*! @} */
36369
36370/*! @name BUF1IND - Buffer1 Top Index Register */
36371/*! @{ */
36372#define QuadSPI_BUF1IND_TPINDX1_MASK (0xFFFFFFF8U)
36373#define QuadSPI_BUF1IND_TPINDX1_SHIFT (3U)
36374#define QuadSPI_BUF1IND_TPINDX1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1IND_TPINDX1_SHIFT)) & QuadSPI_BUF1IND_TPINDX1_MASK)
36375/*! @} */
36376
36377/*! @name BUF2IND - Buffer2 Top Index Register */
36378/*! @{ */
36379#define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U)
36380#define QuadSPI_BUF2IND_TPINDX2_SHIFT (3U)
36381#define QuadSPI_BUF2IND_TPINDX2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
36382/*! @} */
36383
36384/*! @name SFAR - Serial Flash Address Register */
36385/*! @{ */
36386#define QuadSPI_SFAR_SFADR_MASK (0xFFFFFFFFU)
36387#define QuadSPI_SFAR_SFADR_SHIFT (0U)
36388#define QuadSPI_SFAR_SFADR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFAR_SFADR_SHIFT)) & QuadSPI_SFAR_SFADR_MASK)
36389/*! @} */
36390
36391/*! @name SMPR - Sampling Register */
36392/*! @{ */
36393#define QuadSPI_SMPR_SDRSMP_MASK (0x60U)
36394#define QuadSPI_SMPR_SDRSMP_SHIFT (5U)
36395#define QuadSPI_SMPR_SDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_SDRSMP_SHIFT)) & QuadSPI_SMPR_SDRSMP_MASK)
36396#define QuadSPI_SMPR_DDRSMP_MASK (0x70000U)
36397#define QuadSPI_SMPR_DDRSMP_SHIFT (16U)
36398#define QuadSPI_SMPR_DDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_DDRSMP_SHIFT)) & QuadSPI_SMPR_DDRSMP_MASK)
36399/*! @} */
36400
36401/*! @name RBSR - RX Buffer Status Register */
36402/*! @{ */
36403#define QuadSPI_RBSR_RDBFL_MASK (0x3F00U)
36404#define QuadSPI_RBSR_RDBFL_SHIFT (8U)
36405#define QuadSPI_RBSR_RDBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDBFL_SHIFT)) & QuadSPI_RBSR_RDBFL_MASK)
36406#define QuadSPI_RBSR_RDCTR_MASK (0xFFFF0000U)
36407#define QuadSPI_RBSR_RDCTR_SHIFT (16U)
36408#define QuadSPI_RBSR_RDCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDCTR_SHIFT)) & QuadSPI_RBSR_RDCTR_MASK)
36409/*! @} */
36410
36411/*! @name RBCT - RX Buffer Control Register */
36412/*! @{ */
36413#define QuadSPI_RBCT_WMRK_MASK (0x1FU)
36414#define QuadSPI_RBCT_WMRK_SHIFT (0U)
36415#define QuadSPI_RBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_WMRK_SHIFT)) & QuadSPI_RBCT_WMRK_MASK)
36416#define QuadSPI_RBCT_RXBRD_MASK (0x100U)
36417#define QuadSPI_RBCT_RXBRD_SHIFT (8U)
36418/*! RXBRD
36419 * 0b0..RX Buffer content is read using the AHB Bus registers QSPI_ARDB0 to QSPI_ARDB31. For details, refer to Exclusive Access to Serial Flash for AHB Commands.
36420 * 0b1..RX Buffer content is read using the IP Bus registers QSPI_RBDR0 to QSPI_RBDR31.
36421 */
36422#define QuadSPI_RBCT_RXBRD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_RXBRD_SHIFT)) & QuadSPI_RBCT_RXBRD_MASK)
36423/*! @} */
36424
36425/*! @name TBSR - TX Buffer Status Register */
36426/*! @{ */
36427#define QuadSPI_TBSR_TRBFL_MASK (0x1F00U)
36428#define QuadSPI_TBSR_TRBFL_SHIFT (8U)
36429#define QuadSPI_TBSR_TRBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRBFL_SHIFT)) & QuadSPI_TBSR_TRBFL_MASK)
36430#define QuadSPI_TBSR_TRCTR_MASK (0xFFFF0000U)
36431#define QuadSPI_TBSR_TRCTR_SHIFT (16U)
36432#define QuadSPI_TBSR_TRCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRCTR_SHIFT)) & QuadSPI_TBSR_TRCTR_MASK)
36433/*! @} */
36434
36435/*! @name TBDR - TX Buffer Data Register */
36436/*! @{ */
36437#define QuadSPI_TBDR_TXDATA_MASK (0xFFFFFFFFU)
36438#define QuadSPI_TBDR_TXDATA_SHIFT (0U)
36439#define QuadSPI_TBDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBDR_TXDATA_SHIFT)) & QuadSPI_TBDR_TXDATA_MASK)
36440/*! @} */
36441
36442/*! @name SR - Status Register */
36443/*! @{ */
36444#define QuadSPI_SR_BUSY_MASK (0x1U)
36445#define QuadSPI_SR_BUSY_SHIFT (0U)
36446#define QuadSPI_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_BUSY_SHIFT)) & QuadSPI_SR_BUSY_MASK)
36447#define QuadSPI_SR_IP_ACC_MASK (0x2U)
36448#define QuadSPI_SR_IP_ACC_SHIFT (1U)
36449#define QuadSPI_SR_IP_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_IP_ACC_SHIFT)) & QuadSPI_SR_IP_ACC_MASK)
36450#define QuadSPI_SR_AHB_ACC_MASK (0x4U)
36451#define QuadSPI_SR_AHB_ACC_SHIFT (2U)
36452#define QuadSPI_SR_AHB_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB_ACC_SHIFT)) & QuadSPI_SR_AHB_ACC_MASK)
36453#define QuadSPI_SR_AHBGNT_MASK (0x20U)
36454#define QuadSPI_SR_AHBGNT_SHIFT (5U)
36455#define QuadSPI_SR_AHBGNT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBGNT_SHIFT)) & QuadSPI_SR_AHBGNT_MASK)
36456#define QuadSPI_SR_AHBTRN_MASK (0x40U)
36457#define QuadSPI_SR_AHBTRN_SHIFT (6U)
36458#define QuadSPI_SR_AHBTRN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBTRN_SHIFT)) & QuadSPI_SR_AHBTRN_MASK)
36459#define QuadSPI_SR_AHB0NE_MASK (0x80U)
36460#define QuadSPI_SR_AHB0NE_SHIFT (7U)
36461#define QuadSPI_SR_AHB0NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
36462#define QuadSPI_SR_AHB1NE_MASK (0x100U)
36463#define QuadSPI_SR_AHB1NE_SHIFT (8U)
36464#define QuadSPI_SR_AHB1NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1NE_SHIFT)) & QuadSPI_SR_AHB1NE_MASK)
36465#define QuadSPI_SR_AHB2NE_MASK (0x200U)
36466#define QuadSPI_SR_AHB2NE_SHIFT (9U)
36467#define QuadSPI_SR_AHB2NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2NE_SHIFT)) & QuadSPI_SR_AHB2NE_MASK)
36468#define QuadSPI_SR_AHB3NE_MASK (0x400U)
36469#define QuadSPI_SR_AHB3NE_SHIFT (10U)
36470#define QuadSPI_SR_AHB3NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3NE_SHIFT)) & QuadSPI_SR_AHB3NE_MASK)
36471#define QuadSPI_SR_AHB0FUL_MASK (0x800U)
36472#define QuadSPI_SR_AHB0FUL_SHIFT (11U)
36473#define QuadSPI_SR_AHB0FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
36474#define QuadSPI_SR_AHB1FUL_MASK (0x1000U)
36475#define QuadSPI_SR_AHB1FUL_SHIFT (12U)
36476#define QuadSPI_SR_AHB1FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1FUL_SHIFT)) & QuadSPI_SR_AHB1FUL_MASK)
36477#define QuadSPI_SR_AHB2FUL_MASK (0x2000U)
36478#define QuadSPI_SR_AHB2FUL_SHIFT (13U)
36479#define QuadSPI_SR_AHB2FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2FUL_SHIFT)) & QuadSPI_SR_AHB2FUL_MASK)
36480#define QuadSPI_SR_AHB3FUL_MASK (0x4000U)
36481#define QuadSPI_SR_AHB3FUL_SHIFT (14U)
36482#define QuadSPI_SR_AHB3FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3FUL_SHIFT)) & QuadSPI_SR_AHB3FUL_MASK)
36483#define QuadSPI_SR_RXWE_MASK (0x10000U)
36484#define QuadSPI_SR_RXWE_SHIFT (16U)
36485#define QuadSPI_SR_RXWE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
36486#define QuadSPI_SR_RXFULL_MASK (0x80000U)
36487#define QuadSPI_SR_RXFULL_SHIFT (19U)
36488#define QuadSPI_SR_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
36489#define QuadSPI_SR_RXDMA_MASK (0x800000U)
36490#define QuadSPI_SR_RXDMA_SHIFT (23U)
36491#define QuadSPI_SR_RXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXDMA_SHIFT)) & QuadSPI_SR_RXDMA_MASK)
36492#define QuadSPI_SR_TXEDA_MASK (0x1000000U)
36493#define QuadSPI_SR_TXEDA_SHIFT (24U)
36494#define QuadSPI_SR_TXEDA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXEDA_SHIFT)) & QuadSPI_SR_TXEDA_MASK)
36495#define QuadSPI_SR_TXFULL_MASK (0x8000000U)
36496#define QuadSPI_SR_TXFULL_SHIFT (27U)
36497#define QuadSPI_SR_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
36498#define QuadSPI_SR_DLPSMP_MASK (0xE0000000U)
36499#define QuadSPI_SR_DLPSMP_SHIFT (29U)
36500#define QuadSPI_SR_DLPSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK)
36501/*! @} */
36502
36503/*! @name FR - Flag Register */
36504/*! @{ */
36505#define QuadSPI_FR_TFF_MASK (0x1U)
36506#define QuadSPI_FR_TFF_SHIFT (0U)
36507#define QuadSPI_FR_TFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TFF_SHIFT)) & QuadSPI_FR_TFF_MASK)
36508#define QuadSPI_FR_IPGEF_MASK (0x10U)
36509#define QuadSPI_FR_IPGEF_SHIFT (4U)
36510#define QuadSPI_FR_IPGEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPGEF_SHIFT)) & QuadSPI_FR_IPGEF_MASK)
36511#define QuadSPI_FR_IPIEF_MASK (0x40U)
36512#define QuadSPI_FR_IPIEF_SHIFT (6U)
36513#define QuadSPI_FR_IPIEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPIEF_SHIFT)) & QuadSPI_FR_IPIEF_MASK)
36514#define QuadSPI_FR_IPAEF_MASK (0x80U)
36515#define QuadSPI_FR_IPAEF_SHIFT (7U)
36516#define QuadSPI_FR_IPAEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPAEF_SHIFT)) & QuadSPI_FR_IPAEF_MASK)
36517#define QuadSPI_FR_IUEF_MASK (0x800U)
36518#define QuadSPI_FR_IUEF_SHIFT (11U)
36519#define QuadSPI_FR_IUEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IUEF_SHIFT)) & QuadSPI_FR_IUEF_MASK)
36520#define QuadSPI_FR_ABOF_MASK (0x1000U)
36521#define QuadSPI_FR_ABOF_SHIFT (12U)
36522#define QuadSPI_FR_ABOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABOF_SHIFT)) & QuadSPI_FR_ABOF_MASK)
36523#define QuadSPI_FR_ABSEF_MASK (0x8000U)
36524#define QuadSPI_FR_ABSEF_SHIFT (15U)
36525#define QuadSPI_FR_ABSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK)
36526#define QuadSPI_FR_RBDF_MASK (0x10000U)
36527#define QuadSPI_FR_RBDF_SHIFT (16U)
36528#define QuadSPI_FR_RBDF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBDF_SHIFT)) & QuadSPI_FR_RBDF_MASK)
36529#define QuadSPI_FR_RBOF_MASK (0x20000U)
36530#define QuadSPI_FR_RBOF_SHIFT (17U)
36531#define QuadSPI_FR_RBOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBOF_SHIFT)) & QuadSPI_FR_RBOF_MASK)
36532#define QuadSPI_FR_ILLINE_MASK (0x800000U)
36533#define QuadSPI_FR_ILLINE_SHIFT (23U)
36534#define QuadSPI_FR_ILLINE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
36535#define QuadSPI_FR_TBUF_MASK (0x4000000U)
36536#define QuadSPI_FR_TBUF_SHIFT (26U)
36537#define QuadSPI_FR_TBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBUF_SHIFT)) & QuadSPI_FR_TBUF_MASK)
36538#define QuadSPI_FR_TBFF_MASK (0x8000000U)
36539#define QuadSPI_FR_TBFF_SHIFT (27U)
36540#define QuadSPI_FR_TBFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBFF_SHIFT)) & QuadSPI_FR_TBFF_MASK)
36541#define QuadSPI_FR_DLPFF_MASK (0x80000000U)
36542#define QuadSPI_FR_DLPFF_SHIFT (31U)
36543#define QuadSPI_FR_DLPFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_DLPFF_SHIFT)) & QuadSPI_FR_DLPFF_MASK)
36544/*! @} */
36545
36546/*! @name RSER - Interrupt and DMA Request Select and Enable Register */
36547/*! @{ */
36548#define QuadSPI_RSER_TFIE_MASK (0x1U)
36549#define QuadSPI_RSER_TFIE_SHIFT (0U)
36550/*! TFIE
36551 * 0b0..No TFF interrupt will be generated
36552 * 0b1..TFF interrupt will be generated
36553 */
36554#define QuadSPI_RSER_TFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TFIE_SHIFT)) & QuadSPI_RSER_TFIE_MASK)
36555#define QuadSPI_RSER_IPGEIE_MASK (0x10U)
36556#define QuadSPI_RSER_IPGEIE_SHIFT (4U)
36557/*! IPGEIE
36558 * 0b0..No IPGEF interrupt will be generated
36559 * 0b1..IPGEF interrupt will be generated
36560 */
36561#define QuadSPI_RSER_IPGEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPGEIE_SHIFT)) & QuadSPI_RSER_IPGEIE_MASK)
36562#define QuadSPI_RSER_IPIEIE_MASK (0x40U)
36563#define QuadSPI_RSER_IPIEIE_SHIFT (6U)
36564/*! IPIEIE
36565 * 0b0..No IPIEF interrupt will be generated
36566 * 0b0..IPIEF interrupt will be generated
36567 */
36568#define QuadSPI_RSER_IPIEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPIEIE_SHIFT)) & QuadSPI_RSER_IPIEIE_MASK)
36569#define QuadSPI_RSER_IPAEIE_MASK (0x80U)
36570#define QuadSPI_RSER_IPAEIE_SHIFT (7U)
36571/*! IPAEIE
36572 * 0b0..No IPAEF interrupt will be generated
36573 * 0b1..IPAEF interrupt will be generated
36574 */
36575#define QuadSPI_RSER_IPAEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPAEIE_SHIFT)) & QuadSPI_RSER_IPAEIE_MASK)
36576#define QuadSPI_RSER_IUEIE_MASK (0x800U)
36577#define QuadSPI_RSER_IUEIE_SHIFT (11U)
36578/*! IUEIE
36579 * 0b0..No IUEF interrupt will be generated
36580 * 0b1..IUEF interrupt will be generated
36581 */
36582#define QuadSPI_RSER_IUEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IUEIE_SHIFT)) & QuadSPI_RSER_IUEIE_MASK)
36583#define QuadSPI_RSER_ABOIE_MASK (0x1000U)
36584#define QuadSPI_RSER_ABOIE_SHIFT (12U)
36585/*! ABOIE
36586 * 0b0..No ABOF interrupt will be generated
36587 * 0b1..ABOF interrupt will be generated
36588 */
36589#define QuadSPI_RSER_ABOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABOIE_SHIFT)) & QuadSPI_RSER_ABOIE_MASK)
36590#define QuadSPI_RSER_ABSEIE_MASK (0x8000U)
36591#define QuadSPI_RSER_ABSEIE_SHIFT (15U)
36592/*! ABSEIE
36593 * 0b0..No ABSEF interrupt will be generated
36594 * 0b1..ABSEF interrupt will be generated
36595 */
36596#define QuadSPI_RSER_ABSEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABSEIE_SHIFT)) & QuadSPI_RSER_ABSEIE_MASK)
36597#define QuadSPI_RSER_RBDIE_MASK (0x10000U)
36598#define QuadSPI_RSER_RBDIE_SHIFT (16U)
36599/*! RBDIE
36600 * 0b0..No RBDF interrupt will be generated
36601 * 0b1..RBDF Interrupt will be generated
36602 */
36603#define QuadSPI_RSER_RBDIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDIE_SHIFT)) & QuadSPI_RSER_RBDIE_MASK)
36604#define QuadSPI_RSER_RBOIE_MASK (0x20000U)
36605#define QuadSPI_RSER_RBOIE_SHIFT (17U)
36606/*! RBOIE
36607 * 0b0..No RBOF interrupt will be generated
36608 * 0b1..RBOF interrupt will be generated
36609 */
36610#define QuadSPI_RSER_RBOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBOIE_SHIFT)) & QuadSPI_RSER_RBOIE_MASK)
36611#define QuadSPI_RSER_RBDDE_MASK (0x200000U)
36612#define QuadSPI_RSER_RBDDE_SHIFT (21U)
36613/*! RBDDE
36614 * 0b0..No DMA request will be generated
36615 * 0b1..DMA request will be generated
36616 */
36617#define QuadSPI_RSER_RBDDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDDE_SHIFT)) & QuadSPI_RSER_RBDDE_MASK)
36618#define QuadSPI_RSER_ILLINIE_MASK (0x800000U)
36619#define QuadSPI_RSER_ILLINIE_SHIFT (23U)
36620/*! ILLINIE
36621 * 0b0..No ILLINE interrupt will be generated
36622 * 0b1..ILLINE interrupt will be generated
36623 */
36624#define QuadSPI_RSER_ILLINIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ILLINIE_SHIFT)) & QuadSPI_RSER_ILLINIE_MASK)
36625#define QuadSPI_RSER_TBUIE_MASK (0x4000000U)
36626#define QuadSPI_RSER_TBUIE_SHIFT (26U)
36627/*! TBUIE
36628 * 0b0..No TBUF interrupt will be generated
36629 * 0b1..TBUF interrupt will be generated
36630 */
36631#define QuadSPI_RSER_TBUIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBUIE_SHIFT)) & QuadSPI_RSER_TBUIE_MASK)
36632#define QuadSPI_RSER_TBFIE_MASK (0x8000000U)
36633#define QuadSPI_RSER_TBFIE_SHIFT (27U)
36634/*! TBFIE
36635 * 0b0..No TBFF interrupt will be generated
36636 * 0b1..TBFF interrupt will be generated
36637 */
36638#define QuadSPI_RSER_TBFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFIE_SHIFT)) & QuadSPI_RSER_TBFIE_MASK)
36639#define QuadSPI_RSER_DLPFIE_MASK (0x80000000U)
36640#define QuadSPI_RSER_DLPFIE_SHIFT (31U)
36641/*! DLPFIE
36642 * 0b0..No DLPFF interrupt will be generated
36643 * 0b1..DLPFF interrupt will be generated
36644 */
36645#define QuadSPI_RSER_DLPFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_DLPFIE_SHIFT)) & QuadSPI_RSER_DLPFIE_MASK)
36646/*! @} */
36647
36648/*! @name SPNDST - Sequence Suspend Status Register */
36649/*! @{ */
36650#define QuadSPI_SPNDST_SUSPND_MASK (0x1U)
36651#define QuadSPI_SPNDST_SUSPND_SHIFT (0U)
36652#define QuadSPI_SPNDST_SUSPND(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SUSPND_SHIFT)) & QuadSPI_SPNDST_SUSPND_MASK)
36653#define QuadSPI_SPNDST_SPDBUF_MASK (0xC0U)
36654#define QuadSPI_SPNDST_SPDBUF_SHIFT (6U)
36655#define QuadSPI_SPNDST_SPDBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SPDBUF_SHIFT)) & QuadSPI_SPNDST_SPDBUF_MASK)
36656#define QuadSPI_SPNDST_DATLFT_MASK (0xFE00U)
36657#define QuadSPI_SPNDST_DATLFT_SHIFT (9U)
36658#define QuadSPI_SPNDST_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_DATLFT_SHIFT)) & QuadSPI_SPNDST_DATLFT_MASK)
36659/*! @} */
36660
36661/*! @name SPTRCLR - Sequence Pointer Clear Register */
36662/*! @{ */
36663#define QuadSPI_SPTRCLR_BFPTRC_MASK (0x1U)
36664#define QuadSPI_SPTRCLR_BFPTRC_SHIFT (0U)
36665#define QuadSPI_SPTRCLR_BFPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_BFPTRC_SHIFT)) & QuadSPI_SPTRCLR_BFPTRC_MASK)
36666#define QuadSPI_SPTRCLR_IPPTRC_MASK (0x100U)
36667#define QuadSPI_SPTRCLR_IPPTRC_SHIFT (8U)
36668#define QuadSPI_SPTRCLR_IPPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_IPPTRC_SHIFT)) & QuadSPI_SPTRCLR_IPPTRC_MASK)
36669/*! @} */
36670
36671/*! @name SFA1AD - Serial Flash A1 Top Address */
36672/*! @{ */
36673#define QuadSPI_SFA1AD_TPADA1_MASK (0xFFFFFC00U)
36674#define QuadSPI_SFA1AD_TPADA1_SHIFT (10U)
36675#define QuadSPI_SFA1AD_TPADA1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA1AD_TPADA1_SHIFT)) & QuadSPI_SFA1AD_TPADA1_MASK)
36676/*! @} */
36677
36678/*! @name SFA2AD - Serial Flash A2 Top Address */
36679/*! @{ */
36680#define QuadSPI_SFA2AD_TPADA2_MASK (0xFFFFFC00U)
36681#define QuadSPI_SFA2AD_TPADA2_SHIFT (10U)
36682#define QuadSPI_SFA2AD_TPADA2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA2AD_TPADA2_SHIFT)) & QuadSPI_SFA2AD_TPADA2_MASK)
36683/*! @} */
36684
36685/*! @name SFB1AD - Serial Flash B1Top Address */
36686/*! @{ */
36687#define QuadSPI_SFB1AD_TPADB1_MASK (0xFFFFFC00U)
36688#define QuadSPI_SFB1AD_TPADB1_SHIFT (10U)
36689#define QuadSPI_SFB1AD_TPADB1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB1AD_TPADB1_SHIFT)) & QuadSPI_SFB1AD_TPADB1_MASK)
36690/*! @} */
36691
36692/*! @name SFB2AD - Serial Flash B2Top Address */
36693/*! @{ */
36694#define QuadSPI_SFB2AD_TPADB2_MASK (0xFFFFFC00U)
36695#define QuadSPI_SFB2AD_TPADB2_SHIFT (10U)
36696#define QuadSPI_SFB2AD_TPADB2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB2AD_TPADB2_SHIFT)) & QuadSPI_SFB2AD_TPADB2_MASK)
36697/*! @} */
36698
36699/*! @name RBDR - RX Buffer Data Register */
36700/*! @{ */
36701#define QuadSPI_RBDR_RXDATA_MASK (0xFFFFFFFFU)
36702#define QuadSPI_RBDR_RXDATA_SHIFT (0U)
36703#define QuadSPI_RBDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBDR_RXDATA_SHIFT)) & QuadSPI_RBDR_RXDATA_MASK)
36704/*! @} */
36705
36706/* The count of QuadSPI_RBDR */
36707#define QuadSPI_RBDR_COUNT (32U)
36708
36709/*! @name LUTKEY - LUT Key Register */
36710/*! @{ */
36711#define QuadSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)
36712#define QuadSPI_LUTKEY_KEY_SHIFT (0U)
36713#define QuadSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUTKEY_KEY_SHIFT)) & QuadSPI_LUTKEY_KEY_MASK)
36714/*! @} */
36715
36716/*! @name LCKCR - LUT Lock Configuration Register */
36717/*! @{ */
36718#define QuadSPI_LCKCR_LOCK_MASK (0x1U)
36719#define QuadSPI_LCKCR_LOCK_SHIFT (0U)
36720#define QuadSPI_LCKCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
36721#define QuadSPI_LCKCR_UNLOCK_MASK (0x2U)
36722#define QuadSPI_LCKCR_UNLOCK_SHIFT (1U)
36723#define QuadSPI_LCKCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_UNLOCK_SHIFT)) & QuadSPI_LCKCR_UNLOCK_MASK)
36724/*! @} */
36725
36726/*! @name LUT - Look-up Table register */
36727/*! @{ */
36728#define QuadSPI_LUT_OPRND0_MASK (0xFFU)
36729#define QuadSPI_LUT_OPRND0_SHIFT (0U)
36730#define QuadSPI_LUT_OPRND0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND0_SHIFT)) & QuadSPI_LUT_OPRND0_MASK)
36731#define QuadSPI_LUT_PAD0_MASK (0x300U)
36732#define QuadSPI_LUT_PAD0_SHIFT (8U)
36733/*! PAD0 - Pad information for INSTR0.
36734 * 0b00..1 Pad
36735 * 0b01..2 Pads
36736 * 0b10..4 Pads
36737 * 0b11..NA
36738 */
36739#define QuadSPI_LUT_PAD0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD0_SHIFT)) & QuadSPI_LUT_PAD0_MASK)
36740#define QuadSPI_LUT_INSTR0_MASK (0xFC00U)
36741#define QuadSPI_LUT_INSTR0_SHIFT (10U)
36742#define QuadSPI_LUT_INSTR0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR0_SHIFT)) & QuadSPI_LUT_INSTR0_MASK)
36743#define QuadSPI_LUT_OPRND1_MASK (0xFF0000U)
36744#define QuadSPI_LUT_OPRND1_SHIFT (16U)
36745#define QuadSPI_LUT_OPRND1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND1_SHIFT)) & QuadSPI_LUT_OPRND1_MASK)
36746#define QuadSPI_LUT_PAD1_MASK (0x3000000U)
36747#define QuadSPI_LUT_PAD1_SHIFT (24U)
36748/*! PAD1 - Pad information for INSTR1.
36749 * 0b00..1 Pad
36750 * 0b01..2 Pads
36751 * 0b10..4 Pads
36752 * 0b11..NA
36753 */
36754#define QuadSPI_LUT_PAD1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD1_SHIFT)) & QuadSPI_LUT_PAD1_MASK)
36755#define QuadSPI_LUT_INSTR1_MASK (0xFC000000U)
36756#define QuadSPI_LUT_INSTR1_SHIFT (26U)
36757#define QuadSPI_LUT_INSTR1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR1_SHIFT)) & QuadSPI_LUT_INSTR1_MASK)
36758/*! @} */
36759
36760/* The count of QuadSPI_LUT */
36761#define QuadSPI_LUT_COUNT (64U)
36762
36763
36764/*!
36765 * @}
36766 */ /* end of group QuadSPI_Register_Masks */
36767
36768
36769/* QuadSPI - Peripheral instance base addresses */
36770/** Peripheral QuadSPI base address */
36771#define QuadSPI_BASE (0x30BB0000u)
36772/** Peripheral QuadSPI base pointer */
36773#define QuadSPI ((QuadSPI_Type *)QuadSPI_BASE)
36774/** Array initializer of QuadSPI peripheral base addresses */
36775#define QuadSPI_BASE_ADDRS { QuadSPI_BASE }
36776/** Array initializer of QuadSPI peripheral base pointers */
36777#define QuadSPI_BASE_PTRS { QuadSPI }
36778/** Interrupt vectors for the QuadSPI peripheral type */
36779#define QuadSPI_IRQS { QSPI_IRQn }
36780
36781/*!
36782 * @}
36783 */ /* end of group QuadSPI_Peripheral_Access_Layer */
36784
36785
36786/* ----------------------------------------------------------------------------
36787 -- RDC Peripheral Access Layer
36788 ---------------------------------------------------------------------------- */
36789
36790/*!
36791 * @addtogroup RDC_Peripheral_Access_Layer RDC Peripheral Access Layer
36792 * @{
36793 */
36794
36795/** RDC - Register Layout Typedef */
36796typedef struct {
36797 __I uint32_t VIR; /**< Version Information, offset: 0x0 */
36798 uint8_t RESERVED_0[32];
36799 __IO uint32_t STAT; /**< Status, offset: 0x24 */
36800 __IO uint32_t INTCTRL; /**< Interrupt and Control, offset: 0x28 */
36801 __IO uint32_t INTSTAT; /**< Interrupt Status, offset: 0x2C */
36802 uint8_t RESERVED_1[464];
36803 __IO uint32_t MDA[27]; /**< Master Domain Assignment, array offset: 0x200, array step: 0x4 */
36804 uint8_t RESERVED_2[404];
36805 __IO uint32_t PDAP[118]; /**< Peripheral Domain Access Permissions, array offset: 0x400, array step: 0x4 */
36806 uint8_t RESERVED_3[552];
36807 struct { /* offset: 0x800, array step: 0x10 */
36808 __IO uint32_t MRSA; /**< Memory Region Start Address, array offset: 0x800, array step: 0x10 */
36809 __IO uint32_t MREA; /**< Memory Region End Address, array offset: 0x804, array step: 0x10 */
36810 __IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, array step: 0x10 */
36811 __IO uint32_t MRVS; /**< Memory Region Violation Status, array offset: 0x80C, array step: 0x10 */
36812 } MR[52];
36813} RDC_Type;
36814
36815/* ----------------------------------------------------------------------------
36816 -- RDC Register Masks
36817 ---------------------------------------------------------------------------- */
36818
36819/*!
36820 * @addtogroup RDC_Register_Masks RDC Register Masks
36821 * @{
36822 */
36823
36824/*! @name VIR - Version Information */
36825/*! @{ */
36826#define RDC_VIR_NDID_MASK (0xFU)
36827#define RDC_VIR_NDID_SHIFT (0U)
36828#define RDC_VIR_NDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NDID_SHIFT)) & RDC_VIR_NDID_MASK)
36829#define RDC_VIR_NMSTR_MASK (0xFF0U)
36830#define RDC_VIR_NMSTR_SHIFT (4U)
36831#define RDC_VIR_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NMSTR_SHIFT)) & RDC_VIR_NMSTR_MASK)
36832#define RDC_VIR_NPER_MASK (0xFF000U)
36833#define RDC_VIR_NPER_SHIFT (12U)
36834#define RDC_VIR_NPER(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NPER_SHIFT)) & RDC_VIR_NPER_MASK)
36835#define RDC_VIR_NRGN_MASK (0xFF00000U)
36836#define RDC_VIR_NRGN_SHIFT (20U)
36837#define RDC_VIR_NRGN(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NRGN_SHIFT)) & RDC_VIR_NRGN_MASK)
36838/*! @} */
36839
36840/*! @name STAT - Status */
36841/*! @{ */
36842#define RDC_STAT_DID_MASK (0xFU)
36843#define RDC_STAT_DID_SHIFT (0U)
36844#define RDC_STAT_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_DID_SHIFT)) & RDC_STAT_DID_MASK)
36845#define RDC_STAT_PDS_MASK (0x100U)
36846#define RDC_STAT_PDS_SHIFT (8U)
36847/*! PDS - Power Domain Status
36848 * 0b0..Power Down Domain is OFF
36849 * 0b1..Power Down Domain is ON
36850 */
36851#define RDC_STAT_PDS(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_PDS_SHIFT)) & RDC_STAT_PDS_MASK)
36852/*! @} */
36853
36854/*! @name INTCTRL - Interrupt and Control */
36855/*! @{ */
36856#define RDC_INTCTRL_RCI_EN_MASK (0x1U)
36857#define RDC_INTCTRL_RCI_EN_SHIFT (0U)
36858/*! RCI_EN - Restoration Complete Interrupt
36859 * 0b0..Interrupt Disabled
36860 * 0b1..Interrupt Enabled
36861 */
36862#define RDC_INTCTRL_RCI_EN(x) (((uint32_t)(((uint32_t)(x)) << RDC_INTCTRL_RCI_EN_SHIFT)) & RDC_INTCTRL_RCI_EN_MASK)
36863/*! @} */
36864
36865/*! @name INTSTAT - Interrupt Status */
36866/*! @{ */
36867#define RDC_INTSTAT_INT_MASK (0x1U)
36868#define RDC_INTSTAT_INT_SHIFT (0U)
36869/*! INT - Interrupt Status
36870 * 0b0..No Interrupt Pending
36871 * 0b1..Interrupt Pending
36872 */
36873#define RDC_INTSTAT_INT(x) (((uint32_t)(((uint32_t)(x)) << RDC_INTSTAT_INT_SHIFT)) & RDC_INTSTAT_INT_MASK)
36874/*! @} */
36875
36876/*! @name MDA - Master Domain Assignment */
36877/*! @{ */
36878#define RDC_MDA_DID_MASK (0x3U)
36879#define RDC_MDA_DID_SHIFT (0U)
36880/*! DID - Domain ID
36881 * 0b00..Master assigned to Processing Domain 0
36882 * 0b01..Master assigned to Processing Domain 1
36883 * 0b10..Master assigned to Processing Domain 2
36884 * 0b11..Master assigned to Processing Domain 3
36885 */
36886#define RDC_MDA_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_DID_SHIFT)) & RDC_MDA_DID_MASK)
36887#define RDC_MDA_LCK_MASK (0x80000000U)
36888#define RDC_MDA_LCK_SHIFT (31U)
36889/*! LCK
36890 * 0b0..Not Locked
36891 * 0b1..Locked
36892 */
36893#define RDC_MDA_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_LCK_SHIFT)) & RDC_MDA_LCK_MASK)
36894/*! @} */
36895
36896/* The count of RDC_MDA */
36897#define RDC_MDA_COUNT (27U)
36898
36899/*! @name PDAP - Peripheral Domain Access Permissions */
36900/*! @{ */
36901#define RDC_PDAP_D0W_MASK (0x1U)
36902#define RDC_PDAP_D0W_SHIFT (0U)
36903/*! D0W - Domain 0 Write Access
36904 * 0b0..No Write Access
36905 * 0b1..Write Access Allowed
36906 */
36907#define RDC_PDAP_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0W_SHIFT)) & RDC_PDAP_D0W_MASK)
36908#define RDC_PDAP_D0R_MASK (0x2U)
36909#define RDC_PDAP_D0R_SHIFT (1U)
36910/*! D0R - Domain 0 Read Access
36911 * 0b0..No Read Access
36912 * 0b1..Read Access Allowed
36913 */
36914#define RDC_PDAP_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0R_SHIFT)) & RDC_PDAP_D0R_MASK)
36915#define RDC_PDAP_D1W_MASK (0x4U)
36916#define RDC_PDAP_D1W_SHIFT (2U)
36917/*! D1W - Domain 1 Write Access
36918 * 0b0..No Write Access
36919 * 0b1..Write Access Allowed
36920 */
36921#define RDC_PDAP_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1W_SHIFT)) & RDC_PDAP_D1W_MASK)
36922#define RDC_PDAP_D1R_MASK (0x8U)
36923#define RDC_PDAP_D1R_SHIFT (3U)
36924/*! D1R - Domain 1 Read Access
36925 * 0b0..No Read Access
36926 * 0b1..Read Access Allowed
36927 */
36928#define RDC_PDAP_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1R_SHIFT)) & RDC_PDAP_D1R_MASK)
36929#define RDC_PDAP_D2W_MASK (0x10U)
36930#define RDC_PDAP_D2W_SHIFT (4U)
36931/*! D2W - Domain 2 Write Access
36932 * 0b0..No Write Access
36933 * 0b1..Write Access Allowed
36934 */
36935#define RDC_PDAP_D2W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D2W_SHIFT)) & RDC_PDAP_D2W_MASK)
36936#define RDC_PDAP_D2R_MASK (0x20U)
36937#define RDC_PDAP_D2R_SHIFT (5U)
36938/*! D2R - Domain 2 Read Access
36939 * 0b0..No Read Access
36940 * 0b1..Read Access Allowed
36941 */
36942#define RDC_PDAP_D2R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D2R_SHIFT)) & RDC_PDAP_D2R_MASK)
36943#define RDC_PDAP_D3W_MASK (0x40U)
36944#define RDC_PDAP_D3W_SHIFT (6U)
36945/*! D3W - Domain 3 Write Access
36946 * 0b0..No Write Access
36947 * 0b1..Write Access Allowed
36948 */
36949#define RDC_PDAP_D3W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D3W_SHIFT)) & RDC_PDAP_D3W_MASK)
36950#define RDC_PDAP_D3R_MASK (0x80U)
36951#define RDC_PDAP_D3R_SHIFT (7U)
36952/*! D3R - Domain 3 Read Access
36953 * 0b0..No Read Access
36954 * 0b1..Read Access Allowed
36955 */
36956#define RDC_PDAP_D3R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D3R_SHIFT)) & RDC_PDAP_D3R_MASK)
36957#define RDC_PDAP_SREQ_MASK (0x40000000U)
36958#define RDC_PDAP_SREQ_SHIFT (30U)
36959/*! SREQ - Semaphore Required
36960 * 0b0..Semaphores have no effect
36961 * 0b1..Semaphores are enforced
36962 */
36963#define RDC_PDAP_SREQ(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_SREQ_SHIFT)) & RDC_PDAP_SREQ_MASK)
36964#define RDC_PDAP_LCK_MASK (0x80000000U)
36965#define RDC_PDAP_LCK_SHIFT (31U)
36966/*! LCK - Peripheral Permissions Lock
36967 * 0b0..Not Locked
36968 * 0b1..Locked
36969 */
36970#define RDC_PDAP_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_LCK_SHIFT)) & RDC_PDAP_LCK_MASK)
36971/*! @} */
36972
36973/* The count of RDC_PDAP */
36974#define RDC_PDAP_COUNT (118U)
36975
36976/*! @name MRSA - Memory Region Start Address */
36977/*! @{ */
36978#define RDC_MRSA_SADR_MASK (0xFFFFFF80U)
36979#define RDC_MRSA_SADR_SHIFT (7U)
36980#define RDC_MRSA_SADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRSA_SADR_SHIFT)) & RDC_MRSA_SADR_MASK)
36981/*! @} */
36982
36983/* The count of RDC_MRSA */
36984#define RDC_MRSA_COUNT (52U)
36985
36986/*! @name MREA - Memory Region End Address */
36987/*! @{ */
36988#define RDC_MREA_EADR_MASK (0xFFFFFF80U)
36989#define RDC_MREA_EADR_SHIFT (7U)
36990#define RDC_MREA_EADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MREA_EADR_SHIFT)) & RDC_MREA_EADR_MASK)
36991/*! @} */
36992
36993/* The count of RDC_MREA */
36994#define RDC_MREA_COUNT (52U)
36995
36996/*! @name MRC - Memory Region Control */
36997/*! @{ */
36998#define RDC_MRC_D0W_MASK (0x1U)
36999#define RDC_MRC_D0W_SHIFT (0U)
37000/*! D0W - Domain 0 Write Access to Region
37001 * 0b0..Processing Domain 0 does not have Write access to the memory region
37002 * 0b1..Processing Domain 0 has Write access to the memory region
37003 */
37004#define RDC_MRC_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0W_SHIFT)) & RDC_MRC_D0W_MASK)
37005#define RDC_MRC_D0R_MASK (0x2U)
37006#define RDC_MRC_D0R_SHIFT (1U)
37007/*! D0R - Domain 0 Read Access to Region
37008 * 0b0..Processing Domain 0 does not have Read access to the memory region
37009 * 0b1..Processing Domain 0 has Read access to the memory region
37010 */
37011#define RDC_MRC_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0R_SHIFT)) & RDC_MRC_D0R_MASK)
37012#define RDC_MRC_D1W_MASK (0x4U)
37013#define RDC_MRC_D1W_SHIFT (2U)
37014/*! D1W - Domain 1 Write Access to Region
37015 * 0b0..Processing Domain 1 does not have Write access to the memory region
37016 * 0b1..Processing Domain 1 has Write access to the memory region
37017 */
37018#define RDC_MRC_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1W_SHIFT)) & RDC_MRC_D1W_MASK)
37019#define RDC_MRC_D1R_MASK (0x8U)
37020#define RDC_MRC_D1R_SHIFT (3U)
37021/*! D1R - Domain 1 Read Access to Region
37022 * 0b0..Processing Domain 1 does not have Read access to the memory region
37023 * 0b1..Processing Domain 1 has Read access to the memory region
37024 */
37025#define RDC_MRC_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1R_SHIFT)) & RDC_MRC_D1R_MASK)
37026#define RDC_MRC_D2W_MASK (0x10U)
37027#define RDC_MRC_D2W_SHIFT (4U)
37028/*! D2W - Domain 2 Write Access to Region
37029 * 0b0..Processing Domain 2 does not have Write access to the memory region
37030 * 0b1..Processing Domain 2 has Write access to the memory region
37031 */
37032#define RDC_MRC_D2W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D2W_SHIFT)) & RDC_MRC_D2W_MASK)
37033#define RDC_MRC_D2R_MASK (0x20U)
37034#define RDC_MRC_D2R_SHIFT (5U)
37035/*! D2R - Domain 2 Read Access to Region
37036 * 0b0..Processing Domain 2 does not have Read access to the memory region
37037 * 0b1..Processing Domain 2 has Read access to the memory region
37038 */
37039#define RDC_MRC_D2R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D2R_SHIFT)) & RDC_MRC_D2R_MASK)
37040#define RDC_MRC_D3W_MASK (0x40U)
37041#define RDC_MRC_D3W_SHIFT (6U)
37042/*! D3W - Domain 3 Write Access to Region
37043 * 0b0..Processing Domain 3 does not have Write access to the memory region
37044 * 0b1..Processing Domain 3 has Read access to the memory region
37045 */
37046#define RDC_MRC_D3W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D3W_SHIFT)) & RDC_MRC_D3W_MASK)
37047#define RDC_MRC_D3R_MASK (0x80U)
37048#define RDC_MRC_D3R_SHIFT (7U)
37049/*! D3R - Domain 3 Read Access to Region
37050 * 0b0..Processing Domain 3 does not have Read access to the memory region
37051 * 0b1..Processing Domain 3 has Read access to the memory region
37052 */
37053#define RDC_MRC_D3R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D3R_SHIFT)) & RDC_MRC_D3R_MASK)
37054#define RDC_MRC_ENA_MASK (0x40000000U)
37055#define RDC_MRC_ENA_SHIFT (30U)
37056/*! ENA - Region Enable
37057 * 0b0..Memory region is not defined or restricted.
37058 * 0b1..Memory boundaries, domain permissions and controls are in effect.
37059 */
37060#define RDC_MRC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_ENA_SHIFT)) & RDC_MRC_ENA_MASK)
37061#define RDC_MRC_LCK_MASK (0x80000000U)
37062#define RDC_MRC_LCK_SHIFT (31U)
37063/*! LCK - Region Lock
37064 * 0b0..No Lock. All fields in this register may be modified.
37065 * 0b1..Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
37066 */
37067#define RDC_MRC_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_LCK_SHIFT)) & RDC_MRC_LCK_MASK)
37068/*! @} */
37069
37070/* The count of RDC_MRC */
37071#define RDC_MRC_COUNT (52U)
37072
37073/*! @name MRVS - Memory Region Violation Status */
37074/*! @{ */
37075#define RDC_MRVS_VDID_MASK (0x3U)
37076#define RDC_MRVS_VDID_SHIFT (0U)
37077/*! VDID - Violating Domain ID
37078 * 0b00..Processing Domain 0
37079 * 0b01..Processing Domain 1
37080 * 0b10..Processing Domain 2
37081 * 0b11..Processing Domain 3
37082 */
37083#define RDC_MRVS_VDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VDID_SHIFT)) & RDC_MRVS_VDID_MASK)
37084#define RDC_MRVS_AD_MASK (0x10U)
37085#define RDC_MRVS_AD_SHIFT (4U)
37086#define RDC_MRVS_AD(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_AD_SHIFT)) & RDC_MRVS_AD_MASK)
37087#define RDC_MRVS_VADR_MASK (0xFFFFFFE0U)
37088#define RDC_MRVS_VADR_SHIFT (5U)
37089#define RDC_MRVS_VADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VADR_SHIFT)) & RDC_MRVS_VADR_MASK)
37090/*! @} */
37091
37092/* The count of RDC_MRVS */
37093#define RDC_MRVS_COUNT (52U)
37094
37095
37096/*!
37097 * @}
37098 */ /* end of group RDC_Register_Masks */
37099
37100
37101/* RDC - Peripheral instance base addresses */
37102/** Peripheral RDC base address */
37103#define RDC_BASE (0x303D0000u)
37104/** Peripheral RDC base pointer */
37105#define RDC ((RDC_Type *)RDC_BASE)
37106/** Array initializer of RDC peripheral base addresses */
37107#define RDC_BASE_ADDRS { RDC_BASE }
37108/** Array initializer of RDC peripheral base pointers */
37109#define RDC_BASE_PTRS { RDC }
37110/** Interrupt vectors for the RDC peripheral type */
37111#define RDC_IRQS { RDC_IRQn }
37112
37113/*!
37114 * @}
37115 */ /* end of group RDC_Peripheral_Access_Layer */
37116
37117
37118/* ----------------------------------------------------------------------------
37119 -- RDC_SEMAPHORE Peripheral Access Layer
37120 ---------------------------------------------------------------------------- */
37121
37122/*!
37123 * @addtogroup RDC_SEMAPHORE_Peripheral_Access_Layer RDC_SEMAPHORE Peripheral Access Layer
37124 * @{
37125 */
37126
37127/** RDC_SEMAPHORE - Register Layout Typedef */
37128typedef struct {
37129 __IO uint8_t GATE0; /**< Gate Register, offset: 0x0 */
37130 __IO uint8_t GATE1; /**< Gate Register, offset: 0x1 */
37131 __IO uint8_t GATE2; /**< Gate Register, offset: 0x2 */
37132 __IO uint8_t GATE3; /**< Gate Register, offset: 0x3 */
37133 __IO uint8_t GATE4; /**< Gate Register, offset: 0x4 */
37134 __IO uint8_t GATE5; /**< Gate Register, offset: 0x5 */
37135 __IO uint8_t GATE6; /**< Gate Register, offset: 0x6 */
37136 __IO uint8_t GATE7; /**< Gate Register, offset: 0x7 */
37137 __IO uint8_t GATE8; /**< Gate Register, offset: 0x8 */
37138 __IO uint8_t GATE9; /**< Gate Register, offset: 0x9 */
37139 __IO uint8_t GATE10; /**< Gate Register, offset: 0xA */
37140 __IO uint8_t GATE11; /**< Gate Register, offset: 0xB */
37141 __IO uint8_t GATE12; /**< Gate Register, offset: 0xC */
37142 __IO uint8_t GATE13; /**< Gate Register, offset: 0xD */
37143 __IO uint8_t GATE14; /**< Gate Register, offset: 0xE */
37144 __IO uint8_t GATE15; /**< Gate Register, offset: 0xF */
37145 __IO uint8_t GATE16; /**< Gate Register, offset: 0x10 */
37146 __IO uint8_t GATE17; /**< Gate Register, offset: 0x11 */
37147 __IO uint8_t GATE18; /**< Gate Register, offset: 0x12 */
37148 __IO uint8_t GATE19; /**< Gate Register, offset: 0x13 */
37149 __IO uint8_t GATE20; /**< Gate Register, offset: 0x14 */
37150 __IO uint8_t GATE21; /**< Gate Register, offset: 0x15 */
37151 __IO uint8_t GATE22; /**< Gate Register, offset: 0x16 */
37152 __IO uint8_t GATE23; /**< Gate Register, offset: 0x17 */
37153 __IO uint8_t GATE24; /**< Gate Register, offset: 0x18 */
37154 __IO uint8_t GATE25; /**< Gate Register, offset: 0x19 */
37155 __IO uint8_t GATE26; /**< Gate Register, offset: 0x1A */
37156 __IO uint8_t GATE27; /**< Gate Register, offset: 0x1B */
37157 __IO uint8_t GATE28; /**< Gate Register, offset: 0x1C */
37158 __IO uint8_t GATE29; /**< Gate Register, offset: 0x1D */
37159 __IO uint8_t GATE30; /**< Gate Register, offset: 0x1E */
37160 __IO uint8_t GATE31; /**< Gate Register, offset: 0x1F */
37161 __IO uint8_t GATE32; /**< Gate Register, offset: 0x20 */
37162 __IO uint8_t GATE33; /**< Gate Register, offset: 0x21 */
37163 __IO uint8_t GATE34; /**< Gate Register, offset: 0x22 */
37164 __IO uint8_t GATE35; /**< Gate Register, offset: 0x23 */
37165 __IO uint8_t GATE36; /**< Gate Register, offset: 0x24 */
37166 __IO uint8_t GATE37; /**< Gate Register, offset: 0x25 */
37167 __IO uint8_t GATE38; /**< Gate Register, offset: 0x26 */
37168 __IO uint8_t GATE39; /**< Gate Register, offset: 0x27 */
37169 __IO uint8_t GATE40; /**< Gate Register, offset: 0x28 */
37170 __IO uint8_t GATE41; /**< Gate Register, offset: 0x29 */
37171 __IO uint8_t GATE42; /**< Gate Register, offset: 0x2A */
37172 __IO uint8_t GATE43; /**< Gate Register, offset: 0x2B */
37173 __IO uint8_t GATE44; /**< Gate Register, offset: 0x2C */
37174 __IO uint8_t GATE45; /**< Gate Register, offset: 0x2D */
37175 __IO uint8_t GATE46; /**< Gate Register, offset: 0x2E */
37176 __IO uint8_t GATE47; /**< Gate Register, offset: 0x2F */
37177 __IO uint8_t GATE48; /**< Gate Register, offset: 0x30 */
37178 __IO uint8_t GATE49; /**< Gate Register, offset: 0x31 */
37179 __IO uint8_t GATE50; /**< Gate Register, offset: 0x32 */
37180 __IO uint8_t GATE51; /**< Gate Register, offset: 0x33 */
37181 __IO uint8_t GATE52; /**< Gate Register, offset: 0x34 */
37182 __IO uint8_t GATE53; /**< Gate Register, offset: 0x35 */
37183 __IO uint8_t GATE54; /**< Gate Register, offset: 0x36 */
37184 __IO uint8_t GATE55; /**< Gate Register, offset: 0x37 */
37185 __IO uint8_t GATE56; /**< Gate Register, offset: 0x38 */
37186 __IO uint8_t GATE57; /**< Gate Register, offset: 0x39 */
37187 __IO uint8_t GATE58; /**< Gate Register, offset: 0x3A */
37188 __IO uint8_t GATE59; /**< Gate Register, offset: 0x3B */
37189 __IO uint8_t GATE60; /**< Gate Register, offset: 0x3C */
37190 __IO uint8_t GATE61; /**< Gate Register, offset: 0x3D */
37191 __IO uint8_t GATE62; /**< Gate Register, offset: 0x3E */
37192 __IO uint8_t GATE63; /**< Gate Register, offset: 0x3F */
37193 union { /* offset: 0x40 */
37194 __IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x40 */
37195 __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */
37196 };
37197} RDC_SEMAPHORE_Type;
37198
37199/* ----------------------------------------------------------------------------
37200 -- RDC_SEMAPHORE Register Masks
37201 ---------------------------------------------------------------------------- */
37202
37203/*!
37204 * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks
37205 * @{
37206 */
37207
37208/*! @name GATE0 - Gate Register */
37209/*! @{ */
37210#define RDC_SEMAPHORE_GATE0_GTFSM_MASK (0xFU)
37211#define RDC_SEMAPHORE_GATE0_GTFSM_SHIFT (0U)
37212/*! GTFSM - Gate Finite State Machine.
37213 * 0b0000..The gate is unlocked (free).
37214 * 0b0001..The gate has been locked by processor with master_index = 0.
37215 * 0b0010..The gate has been locked by processor with master_index = 1.
37216 * 0b0011..The gate has been locked by processor with master_index = 2.
37217 * 0b0100..The gate has been locked by processor with master_index = 3.
37218 * 0b0101..The gate has been locked by processor with master_index = 4.
37219 * 0b0110..The gate has been locked by processor with master_index = 5.
37220 * 0b0111..The gate has been locked by processor with master_index = 6.
37221 * 0b1000..The gate has been locked by processor with master_index = 7.
37222 * 0b1001..The gate has been locked by processor with master_index = 8.
37223 * 0b1010..The gate has been locked by processor with master_index = 9.
37224 * 0b1011..The gate has been locked by processor with master_index = 10.
37225 * 0b1100..The gate has been locked by processor with master_index = 11.
37226 * 0b1101..The gate has been locked by processor with master_index = 12.
37227 * 0b1110..The gate has been locked by processor with master_index = 13.
37228 * 0b1111..The gate has been locked by processor with master_index = 14.
37229 */
37230#define RDC_SEMAPHORE_GATE0_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE0_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE0_GTFSM_MASK)
37231#define RDC_SEMAPHORE_GATE0_LDOM_MASK (0x30U)
37232#define RDC_SEMAPHORE_GATE0_LDOM_SHIFT (4U)
37233/*! LDOM
37234 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37235 * 0b01..The gate has been locked by domain 1.
37236 * 0b10..The gate has been locked by domain 2.
37237 * 0b11..The gate has been locked by domain 3.
37238 */
37239#define RDC_SEMAPHORE_GATE0_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE0_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE0_LDOM_MASK)
37240/*! @} */
37241
37242/*! @name GATE1 - Gate Register */
37243/*! @{ */
37244#define RDC_SEMAPHORE_GATE1_GTFSM_MASK (0xFU)
37245#define RDC_SEMAPHORE_GATE1_GTFSM_SHIFT (0U)
37246/*! GTFSM - Gate Finite State Machine.
37247 * 0b0000..The gate is unlocked (free).
37248 * 0b0001..The gate has been locked by processor with master_index = 0.
37249 * 0b0010..The gate has been locked by processor with master_index = 1.
37250 * 0b0011..The gate has been locked by processor with master_index = 2.
37251 * 0b0100..The gate has been locked by processor with master_index = 3.
37252 * 0b0101..The gate has been locked by processor with master_index = 4.
37253 * 0b0110..The gate has been locked by processor with master_index = 5.
37254 * 0b0111..The gate has been locked by processor with master_index = 6.
37255 * 0b1000..The gate has been locked by processor with master_index = 7.
37256 * 0b1001..The gate has been locked by processor with master_index = 8.
37257 * 0b1010..The gate has been locked by processor with master_index = 9.
37258 * 0b1011..The gate has been locked by processor with master_index = 10.
37259 * 0b1100..The gate has been locked by processor with master_index = 11.
37260 * 0b1101..The gate has been locked by processor with master_index = 12.
37261 * 0b1110..The gate has been locked by processor with master_index = 13.
37262 * 0b1111..The gate has been locked by processor with master_index = 14.
37263 */
37264#define RDC_SEMAPHORE_GATE1_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE1_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE1_GTFSM_MASK)
37265#define RDC_SEMAPHORE_GATE1_LDOM_MASK (0x30U)
37266#define RDC_SEMAPHORE_GATE1_LDOM_SHIFT (4U)
37267/*! LDOM
37268 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37269 * 0b01..The gate has been locked by domain 1.
37270 * 0b10..The gate has been locked by domain 2.
37271 * 0b11..The gate has been locked by domain 3.
37272 */
37273#define RDC_SEMAPHORE_GATE1_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE1_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE1_LDOM_MASK)
37274/*! @} */
37275
37276/*! @name GATE2 - Gate Register */
37277/*! @{ */
37278#define RDC_SEMAPHORE_GATE2_GTFSM_MASK (0xFU)
37279#define RDC_SEMAPHORE_GATE2_GTFSM_SHIFT (0U)
37280/*! GTFSM - Gate Finite State Machine.
37281 * 0b0000..The gate is unlocked (free).
37282 * 0b0001..The gate has been locked by processor with master_index = 0.
37283 * 0b0010..The gate has been locked by processor with master_index = 1.
37284 * 0b0011..The gate has been locked by processor with master_index = 2.
37285 * 0b0100..The gate has been locked by processor with master_index = 3.
37286 * 0b0101..The gate has been locked by processor with master_index = 4.
37287 * 0b0110..The gate has been locked by processor with master_index = 5.
37288 * 0b0111..The gate has been locked by processor with master_index = 6.
37289 * 0b1000..The gate has been locked by processor with master_index = 7.
37290 * 0b1001..The gate has been locked by processor with master_index = 8.
37291 * 0b1010..The gate has been locked by processor with master_index = 9.
37292 * 0b1011..The gate has been locked by processor with master_index = 10.
37293 * 0b1100..The gate has been locked by processor with master_index = 11.
37294 * 0b1101..The gate has been locked by processor with master_index = 12.
37295 * 0b1110..The gate has been locked by processor with master_index = 13.
37296 * 0b1111..The gate has been locked by processor with master_index = 14.
37297 */
37298#define RDC_SEMAPHORE_GATE2_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE2_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE2_GTFSM_MASK)
37299#define RDC_SEMAPHORE_GATE2_LDOM_MASK (0x30U)
37300#define RDC_SEMAPHORE_GATE2_LDOM_SHIFT (4U)
37301/*! LDOM
37302 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37303 * 0b01..The gate has been locked by domain 1.
37304 * 0b10..The gate has been locked by domain 2.
37305 * 0b11..The gate has been locked by domain 3.
37306 */
37307#define RDC_SEMAPHORE_GATE2_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE2_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE2_LDOM_MASK)
37308/*! @} */
37309
37310/*! @name GATE3 - Gate Register */
37311/*! @{ */
37312#define RDC_SEMAPHORE_GATE3_GTFSM_MASK (0xFU)
37313#define RDC_SEMAPHORE_GATE3_GTFSM_SHIFT (0U)
37314/*! GTFSM - Gate Finite State Machine.
37315 * 0b0000..The gate is unlocked (free).
37316 * 0b0001..The gate has been locked by processor with master_index = 0.
37317 * 0b0010..The gate has been locked by processor with master_index = 1.
37318 * 0b0011..The gate has been locked by processor with master_index = 2.
37319 * 0b0100..The gate has been locked by processor with master_index = 3.
37320 * 0b0101..The gate has been locked by processor with master_index = 4.
37321 * 0b0110..The gate has been locked by processor with master_index = 5.
37322 * 0b0111..The gate has been locked by processor with master_index = 6.
37323 * 0b1000..The gate has been locked by processor with master_index = 7.
37324 * 0b1001..The gate has been locked by processor with master_index = 8.
37325 * 0b1010..The gate has been locked by processor with master_index = 9.
37326 * 0b1011..The gate has been locked by processor with master_index = 10.
37327 * 0b1100..The gate has been locked by processor with master_index = 11.
37328 * 0b1101..The gate has been locked by processor with master_index = 12.
37329 * 0b1110..The gate has been locked by processor with master_index = 13.
37330 * 0b1111..The gate has been locked by processor with master_index = 14.
37331 */
37332#define RDC_SEMAPHORE_GATE3_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE3_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE3_GTFSM_MASK)
37333#define RDC_SEMAPHORE_GATE3_LDOM_MASK (0x30U)
37334#define RDC_SEMAPHORE_GATE3_LDOM_SHIFT (4U)
37335/*! LDOM
37336 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37337 * 0b01..The gate has been locked by domain 1.
37338 * 0b10..The gate has been locked by domain 2.
37339 * 0b11..The gate has been locked by domain 3.
37340 */
37341#define RDC_SEMAPHORE_GATE3_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE3_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE3_LDOM_MASK)
37342/*! @} */
37343
37344/*! @name GATE4 - Gate Register */
37345/*! @{ */
37346#define RDC_SEMAPHORE_GATE4_GTFSM_MASK (0xFU)
37347#define RDC_SEMAPHORE_GATE4_GTFSM_SHIFT (0U)
37348/*! GTFSM - Gate Finite State Machine.
37349 * 0b0000..The gate is unlocked (free).
37350 * 0b0001..The gate has been locked by processor with master_index = 0.
37351 * 0b0010..The gate has been locked by processor with master_index = 1.
37352 * 0b0011..The gate has been locked by processor with master_index = 2.
37353 * 0b0100..The gate has been locked by processor with master_index = 3.
37354 * 0b0101..The gate has been locked by processor with master_index = 4.
37355 * 0b0110..The gate has been locked by processor with master_index = 5.
37356 * 0b0111..The gate has been locked by processor with master_index = 6.
37357 * 0b1000..The gate has been locked by processor with master_index = 7.
37358 * 0b1001..The gate has been locked by processor with master_index = 8.
37359 * 0b1010..The gate has been locked by processor with master_index = 9.
37360 * 0b1011..The gate has been locked by processor with master_index = 10.
37361 * 0b1100..The gate has been locked by processor with master_index = 11.
37362 * 0b1101..The gate has been locked by processor with master_index = 12.
37363 * 0b1110..The gate has been locked by processor with master_index = 13.
37364 * 0b1111..The gate has been locked by processor with master_index = 14.
37365 */
37366#define RDC_SEMAPHORE_GATE4_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE4_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE4_GTFSM_MASK)
37367#define RDC_SEMAPHORE_GATE4_LDOM_MASK (0x30U)
37368#define RDC_SEMAPHORE_GATE4_LDOM_SHIFT (4U)
37369/*! LDOM
37370 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37371 * 0b01..The gate has been locked by domain 1.
37372 * 0b10..The gate has been locked by domain 2.
37373 * 0b11..The gate has been locked by domain 3.
37374 */
37375#define RDC_SEMAPHORE_GATE4_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE4_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE4_LDOM_MASK)
37376/*! @} */
37377
37378/*! @name GATE5 - Gate Register */
37379/*! @{ */
37380#define RDC_SEMAPHORE_GATE5_GTFSM_MASK (0xFU)
37381#define RDC_SEMAPHORE_GATE5_GTFSM_SHIFT (0U)
37382/*! GTFSM - Gate Finite State Machine.
37383 * 0b0000..The gate is unlocked (free).
37384 * 0b0001..The gate has been locked by processor with master_index = 0.
37385 * 0b0010..The gate has been locked by processor with master_index = 1.
37386 * 0b0011..The gate has been locked by processor with master_index = 2.
37387 * 0b0100..The gate has been locked by processor with master_index = 3.
37388 * 0b0101..The gate has been locked by processor with master_index = 4.
37389 * 0b0110..The gate has been locked by processor with master_index = 5.
37390 * 0b0111..The gate has been locked by processor with master_index = 6.
37391 * 0b1000..The gate has been locked by processor with master_index = 7.
37392 * 0b1001..The gate has been locked by processor with master_index = 8.
37393 * 0b1010..The gate has been locked by processor with master_index = 9.
37394 * 0b1011..The gate has been locked by processor with master_index = 10.
37395 * 0b1100..The gate has been locked by processor with master_index = 11.
37396 * 0b1101..The gate has been locked by processor with master_index = 12.
37397 * 0b1110..The gate has been locked by processor with master_index = 13.
37398 * 0b1111..The gate has been locked by processor with master_index = 14.
37399 */
37400#define RDC_SEMAPHORE_GATE5_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE5_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE5_GTFSM_MASK)
37401#define RDC_SEMAPHORE_GATE5_LDOM_MASK (0x30U)
37402#define RDC_SEMAPHORE_GATE5_LDOM_SHIFT (4U)
37403/*! LDOM
37404 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37405 * 0b01..The gate has been locked by domain 1.
37406 * 0b10..The gate has been locked by domain 2.
37407 * 0b11..The gate has been locked by domain 3.
37408 */
37409#define RDC_SEMAPHORE_GATE5_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE5_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE5_LDOM_MASK)
37410/*! @} */
37411
37412/*! @name GATE6 - Gate Register */
37413/*! @{ */
37414#define RDC_SEMAPHORE_GATE6_GTFSM_MASK (0xFU)
37415#define RDC_SEMAPHORE_GATE6_GTFSM_SHIFT (0U)
37416/*! GTFSM - Gate Finite State Machine.
37417 * 0b0000..The gate is unlocked (free).
37418 * 0b0001..The gate has been locked by processor with master_index = 0.
37419 * 0b0010..The gate has been locked by processor with master_index = 1.
37420 * 0b0011..The gate has been locked by processor with master_index = 2.
37421 * 0b0100..The gate has been locked by processor with master_index = 3.
37422 * 0b0101..The gate has been locked by processor with master_index = 4.
37423 * 0b0110..The gate has been locked by processor with master_index = 5.
37424 * 0b0111..The gate has been locked by processor with master_index = 6.
37425 * 0b1000..The gate has been locked by processor with master_index = 7.
37426 * 0b1001..The gate has been locked by processor with master_index = 8.
37427 * 0b1010..The gate has been locked by processor with master_index = 9.
37428 * 0b1011..The gate has been locked by processor with master_index = 10.
37429 * 0b1100..The gate has been locked by processor with master_index = 11.
37430 * 0b1101..The gate has been locked by processor with master_index = 12.
37431 * 0b1110..The gate has been locked by processor with master_index = 13.
37432 * 0b1111..The gate has been locked by processor with master_index = 14.
37433 */
37434#define RDC_SEMAPHORE_GATE6_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE6_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE6_GTFSM_MASK)
37435#define RDC_SEMAPHORE_GATE6_LDOM_MASK (0x30U)
37436#define RDC_SEMAPHORE_GATE6_LDOM_SHIFT (4U)
37437/*! LDOM
37438 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37439 * 0b01..The gate has been locked by domain 1.
37440 * 0b10..The gate has been locked by domain 2.
37441 * 0b11..The gate has been locked by domain 3.
37442 */
37443#define RDC_SEMAPHORE_GATE6_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE6_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE6_LDOM_MASK)
37444/*! @} */
37445
37446/*! @name GATE7 - Gate Register */
37447/*! @{ */
37448#define RDC_SEMAPHORE_GATE7_GTFSM_MASK (0xFU)
37449#define RDC_SEMAPHORE_GATE7_GTFSM_SHIFT (0U)
37450/*! GTFSM - Gate Finite State Machine.
37451 * 0b0000..The gate is unlocked (free).
37452 * 0b0001..The gate has been locked by processor with master_index = 0.
37453 * 0b0010..The gate has been locked by processor with master_index = 1.
37454 * 0b0011..The gate has been locked by processor with master_index = 2.
37455 * 0b0100..The gate has been locked by processor with master_index = 3.
37456 * 0b0101..The gate has been locked by processor with master_index = 4.
37457 * 0b0110..The gate has been locked by processor with master_index = 5.
37458 * 0b0111..The gate has been locked by processor with master_index = 6.
37459 * 0b1000..The gate has been locked by processor with master_index = 7.
37460 * 0b1001..The gate has been locked by processor with master_index = 8.
37461 * 0b1010..The gate has been locked by processor with master_index = 9.
37462 * 0b1011..The gate has been locked by processor with master_index = 10.
37463 * 0b1100..The gate has been locked by processor with master_index = 11.
37464 * 0b1101..The gate has been locked by processor with master_index = 12.
37465 * 0b1110..The gate has been locked by processor with master_index = 13.
37466 * 0b1111..The gate has been locked by processor with master_index = 14.
37467 */
37468#define RDC_SEMAPHORE_GATE7_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE7_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE7_GTFSM_MASK)
37469#define RDC_SEMAPHORE_GATE7_LDOM_MASK (0x30U)
37470#define RDC_SEMAPHORE_GATE7_LDOM_SHIFT (4U)
37471/*! LDOM
37472 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37473 * 0b01..The gate has been locked by domain 1.
37474 * 0b10..The gate has been locked by domain 2.
37475 * 0b11..The gate has been locked by domain 3.
37476 */
37477#define RDC_SEMAPHORE_GATE7_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE7_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE7_LDOM_MASK)
37478/*! @} */
37479
37480/*! @name GATE8 - Gate Register */
37481/*! @{ */
37482#define RDC_SEMAPHORE_GATE8_GTFSM_MASK (0xFU)
37483#define RDC_SEMAPHORE_GATE8_GTFSM_SHIFT (0U)
37484/*! GTFSM - Gate Finite State Machine.
37485 * 0b0000..The gate is unlocked (free).
37486 * 0b0001..The gate has been locked by processor with master_index = 0.
37487 * 0b0010..The gate has been locked by processor with master_index = 1.
37488 * 0b0011..The gate has been locked by processor with master_index = 2.
37489 * 0b0100..The gate has been locked by processor with master_index = 3.
37490 * 0b0101..The gate has been locked by processor with master_index = 4.
37491 * 0b0110..The gate has been locked by processor with master_index = 5.
37492 * 0b0111..The gate has been locked by processor with master_index = 6.
37493 * 0b1000..The gate has been locked by processor with master_index = 7.
37494 * 0b1001..The gate has been locked by processor with master_index = 8.
37495 * 0b1010..The gate has been locked by processor with master_index = 9.
37496 * 0b1011..The gate has been locked by processor with master_index = 10.
37497 * 0b1100..The gate has been locked by processor with master_index = 11.
37498 * 0b1101..The gate has been locked by processor with master_index = 12.
37499 * 0b1110..The gate has been locked by processor with master_index = 13.
37500 * 0b1111..The gate has been locked by processor with master_index = 14.
37501 */
37502#define RDC_SEMAPHORE_GATE8_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE8_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE8_GTFSM_MASK)
37503#define RDC_SEMAPHORE_GATE8_LDOM_MASK (0x30U)
37504#define RDC_SEMAPHORE_GATE8_LDOM_SHIFT (4U)
37505/*! LDOM
37506 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37507 * 0b01..The gate has been locked by domain 1.
37508 * 0b10..The gate has been locked by domain 2.
37509 * 0b11..The gate has been locked by domain 3.
37510 */
37511#define RDC_SEMAPHORE_GATE8_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE8_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE8_LDOM_MASK)
37512/*! @} */
37513
37514/*! @name GATE9 - Gate Register */
37515/*! @{ */
37516#define RDC_SEMAPHORE_GATE9_GTFSM_MASK (0xFU)
37517#define RDC_SEMAPHORE_GATE9_GTFSM_SHIFT (0U)
37518/*! GTFSM - Gate Finite State Machine.
37519 * 0b0000..The gate is unlocked (free).
37520 * 0b0001..The gate has been locked by processor with master_index = 0.
37521 * 0b0010..The gate has been locked by processor with master_index = 1.
37522 * 0b0011..The gate has been locked by processor with master_index = 2.
37523 * 0b0100..The gate has been locked by processor with master_index = 3.
37524 * 0b0101..The gate has been locked by processor with master_index = 4.
37525 * 0b0110..The gate has been locked by processor with master_index = 5.
37526 * 0b0111..The gate has been locked by processor with master_index = 6.
37527 * 0b1000..The gate has been locked by processor with master_index = 7.
37528 * 0b1001..The gate has been locked by processor with master_index = 8.
37529 * 0b1010..The gate has been locked by processor with master_index = 9.
37530 * 0b1011..The gate has been locked by processor with master_index = 10.
37531 * 0b1100..The gate has been locked by processor with master_index = 11.
37532 * 0b1101..The gate has been locked by processor with master_index = 12.
37533 * 0b1110..The gate has been locked by processor with master_index = 13.
37534 * 0b1111..The gate has been locked by processor with master_index = 14.
37535 */
37536#define RDC_SEMAPHORE_GATE9_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE9_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE9_GTFSM_MASK)
37537#define RDC_SEMAPHORE_GATE9_LDOM_MASK (0x30U)
37538#define RDC_SEMAPHORE_GATE9_LDOM_SHIFT (4U)
37539/*! LDOM
37540 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37541 * 0b01..The gate has been locked by domain 1.
37542 * 0b10..The gate has been locked by domain 2.
37543 * 0b11..The gate has been locked by domain 3.
37544 */
37545#define RDC_SEMAPHORE_GATE9_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE9_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE9_LDOM_MASK)
37546/*! @} */
37547
37548/*! @name GATE10 - Gate Register */
37549/*! @{ */
37550#define RDC_SEMAPHORE_GATE10_GTFSM_MASK (0xFU)
37551#define RDC_SEMAPHORE_GATE10_GTFSM_SHIFT (0U)
37552/*! GTFSM - Gate Finite State Machine.
37553 * 0b0000..The gate is unlocked (free).
37554 * 0b0001..The gate has been locked by processor with master_index = 0.
37555 * 0b0010..The gate has been locked by processor with master_index = 1.
37556 * 0b0011..The gate has been locked by processor with master_index = 2.
37557 * 0b0100..The gate has been locked by processor with master_index = 3.
37558 * 0b0101..The gate has been locked by processor with master_index = 4.
37559 * 0b0110..The gate has been locked by processor with master_index = 5.
37560 * 0b0111..The gate has been locked by processor with master_index = 6.
37561 * 0b1000..The gate has been locked by processor with master_index = 7.
37562 * 0b1001..The gate has been locked by processor with master_index = 8.
37563 * 0b1010..The gate has been locked by processor with master_index = 9.
37564 * 0b1011..The gate has been locked by processor with master_index = 10.
37565 * 0b1100..The gate has been locked by processor with master_index = 11.
37566 * 0b1101..The gate has been locked by processor with master_index = 12.
37567 * 0b1110..The gate has been locked by processor with master_index = 13.
37568 * 0b1111..The gate has been locked by processor with master_index = 14.
37569 */
37570#define RDC_SEMAPHORE_GATE10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE10_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE10_GTFSM_MASK)
37571#define RDC_SEMAPHORE_GATE10_LDOM_MASK (0x30U)
37572#define RDC_SEMAPHORE_GATE10_LDOM_SHIFT (4U)
37573/*! LDOM
37574 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37575 * 0b01..The gate has been locked by domain 1.
37576 * 0b10..The gate has been locked by domain 2.
37577 * 0b11..The gate has been locked by domain 3.
37578 */
37579#define RDC_SEMAPHORE_GATE10_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE10_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE10_LDOM_MASK)
37580/*! @} */
37581
37582/*! @name GATE11 - Gate Register */
37583/*! @{ */
37584#define RDC_SEMAPHORE_GATE11_GTFSM_MASK (0xFU)
37585#define RDC_SEMAPHORE_GATE11_GTFSM_SHIFT (0U)
37586/*! GTFSM - Gate Finite State Machine.
37587 * 0b0000..The gate is unlocked (free).
37588 * 0b0001..The gate has been locked by processor with master_index = 0.
37589 * 0b0010..The gate has been locked by processor with master_index = 1.
37590 * 0b0011..The gate has been locked by processor with master_index = 2.
37591 * 0b0100..The gate has been locked by processor with master_index = 3.
37592 * 0b0101..The gate has been locked by processor with master_index = 4.
37593 * 0b0110..The gate has been locked by processor with master_index = 5.
37594 * 0b0111..The gate has been locked by processor with master_index = 6.
37595 * 0b1000..The gate has been locked by processor with master_index = 7.
37596 * 0b1001..The gate has been locked by processor with master_index = 8.
37597 * 0b1010..The gate has been locked by processor with master_index = 9.
37598 * 0b1011..The gate has been locked by processor with master_index = 10.
37599 * 0b1100..The gate has been locked by processor with master_index = 11.
37600 * 0b1101..The gate has been locked by processor with master_index = 12.
37601 * 0b1110..The gate has been locked by processor with master_index = 13.
37602 * 0b1111..The gate has been locked by processor with master_index = 14.
37603 */
37604#define RDC_SEMAPHORE_GATE11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE11_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE11_GTFSM_MASK)
37605#define RDC_SEMAPHORE_GATE11_LDOM_MASK (0x30U)
37606#define RDC_SEMAPHORE_GATE11_LDOM_SHIFT (4U)
37607/*! LDOM
37608 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37609 * 0b01..The gate has been locked by domain 1.
37610 * 0b10..The gate has been locked by domain 2.
37611 * 0b11..The gate has been locked by domain 3.
37612 */
37613#define RDC_SEMAPHORE_GATE11_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE11_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE11_LDOM_MASK)
37614/*! @} */
37615
37616/*! @name GATE12 - Gate Register */
37617/*! @{ */
37618#define RDC_SEMAPHORE_GATE12_GTFSM_MASK (0xFU)
37619#define RDC_SEMAPHORE_GATE12_GTFSM_SHIFT (0U)
37620/*! GTFSM - Gate Finite State Machine.
37621 * 0b0000..The gate is unlocked (free).
37622 * 0b0001..The gate has been locked by processor with master_index = 0.
37623 * 0b0010..The gate has been locked by processor with master_index = 1.
37624 * 0b0011..The gate has been locked by processor with master_index = 2.
37625 * 0b0100..The gate has been locked by processor with master_index = 3.
37626 * 0b0101..The gate has been locked by processor with master_index = 4.
37627 * 0b0110..The gate has been locked by processor with master_index = 5.
37628 * 0b0111..The gate has been locked by processor with master_index = 6.
37629 * 0b1000..The gate has been locked by processor with master_index = 7.
37630 * 0b1001..The gate has been locked by processor with master_index = 8.
37631 * 0b1010..The gate has been locked by processor with master_index = 9.
37632 * 0b1011..The gate has been locked by processor with master_index = 10.
37633 * 0b1100..The gate has been locked by processor with master_index = 11.
37634 * 0b1101..The gate has been locked by processor with master_index = 12.
37635 * 0b1110..The gate has been locked by processor with master_index = 13.
37636 * 0b1111..The gate has been locked by processor with master_index = 14.
37637 */
37638#define RDC_SEMAPHORE_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE12_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE12_GTFSM_MASK)
37639#define RDC_SEMAPHORE_GATE12_LDOM_MASK (0x30U)
37640#define RDC_SEMAPHORE_GATE12_LDOM_SHIFT (4U)
37641/*! LDOM
37642 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37643 * 0b01..The gate has been locked by domain 1.
37644 * 0b10..The gate has been locked by domain 2.
37645 * 0b11..The gate has been locked by domain 3.
37646 */
37647#define RDC_SEMAPHORE_GATE12_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE12_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE12_LDOM_MASK)
37648/*! @} */
37649
37650/*! @name GATE13 - Gate Register */
37651/*! @{ */
37652#define RDC_SEMAPHORE_GATE13_GTFSM_MASK (0xFU)
37653#define RDC_SEMAPHORE_GATE13_GTFSM_SHIFT (0U)
37654/*! GTFSM - Gate Finite State Machine.
37655 * 0b0000..The gate is unlocked (free).
37656 * 0b0001..The gate has been locked by processor with master_index = 0.
37657 * 0b0010..The gate has been locked by processor with master_index = 1.
37658 * 0b0011..The gate has been locked by processor with master_index = 2.
37659 * 0b0100..The gate has been locked by processor with master_index = 3.
37660 * 0b0101..The gate has been locked by processor with master_index = 4.
37661 * 0b0110..The gate has been locked by processor with master_index = 5.
37662 * 0b0111..The gate has been locked by processor with master_index = 6.
37663 * 0b1000..The gate has been locked by processor with master_index = 7.
37664 * 0b1001..The gate has been locked by processor with master_index = 8.
37665 * 0b1010..The gate has been locked by processor with master_index = 9.
37666 * 0b1011..The gate has been locked by processor with master_index = 10.
37667 * 0b1100..The gate has been locked by processor with master_index = 11.
37668 * 0b1101..The gate has been locked by processor with master_index = 12.
37669 * 0b1110..The gate has been locked by processor with master_index = 13.
37670 * 0b1111..The gate has been locked by processor with master_index = 14.
37671 */
37672#define RDC_SEMAPHORE_GATE13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE13_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE13_GTFSM_MASK)
37673#define RDC_SEMAPHORE_GATE13_LDOM_MASK (0x30U)
37674#define RDC_SEMAPHORE_GATE13_LDOM_SHIFT (4U)
37675/*! LDOM
37676 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37677 * 0b01..The gate has been locked by domain 1.
37678 * 0b10..The gate has been locked by domain 2.
37679 * 0b11..The gate has been locked by domain 3.
37680 */
37681#define RDC_SEMAPHORE_GATE13_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE13_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE13_LDOM_MASK)
37682/*! @} */
37683
37684/*! @name GATE14 - Gate Register */
37685/*! @{ */
37686#define RDC_SEMAPHORE_GATE14_GTFSM_MASK (0xFU)
37687#define RDC_SEMAPHORE_GATE14_GTFSM_SHIFT (0U)
37688/*! GTFSM - Gate Finite State Machine.
37689 * 0b0000..The gate is unlocked (free).
37690 * 0b0001..The gate has been locked by processor with master_index = 0.
37691 * 0b0010..The gate has been locked by processor with master_index = 1.
37692 * 0b0011..The gate has been locked by processor with master_index = 2.
37693 * 0b0100..The gate has been locked by processor with master_index = 3.
37694 * 0b0101..The gate has been locked by processor with master_index = 4.
37695 * 0b0110..The gate has been locked by processor with master_index = 5.
37696 * 0b0111..The gate has been locked by processor with master_index = 6.
37697 * 0b1000..The gate has been locked by processor with master_index = 7.
37698 * 0b1001..The gate has been locked by processor with master_index = 8.
37699 * 0b1010..The gate has been locked by processor with master_index = 9.
37700 * 0b1011..The gate has been locked by processor with master_index = 10.
37701 * 0b1100..The gate has been locked by processor with master_index = 11.
37702 * 0b1101..The gate has been locked by processor with master_index = 12.
37703 * 0b1110..The gate has been locked by processor with master_index = 13.
37704 * 0b1111..The gate has been locked by processor with master_index = 14.
37705 */
37706#define RDC_SEMAPHORE_GATE14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE14_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE14_GTFSM_MASK)
37707#define RDC_SEMAPHORE_GATE14_LDOM_MASK (0x30U)
37708#define RDC_SEMAPHORE_GATE14_LDOM_SHIFT (4U)
37709/*! LDOM
37710 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37711 * 0b01..The gate has been locked by domain 1.
37712 * 0b10..The gate has been locked by domain 2.
37713 * 0b11..The gate has been locked by domain 3.
37714 */
37715#define RDC_SEMAPHORE_GATE14_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE14_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE14_LDOM_MASK)
37716/*! @} */
37717
37718/*! @name GATE15 - Gate Register */
37719/*! @{ */
37720#define RDC_SEMAPHORE_GATE15_GTFSM_MASK (0xFU)
37721#define RDC_SEMAPHORE_GATE15_GTFSM_SHIFT (0U)
37722/*! GTFSM - Gate Finite State Machine.
37723 * 0b0000..The gate is unlocked (free).
37724 * 0b0001..The gate has been locked by processor with master_index = 0.
37725 * 0b0010..The gate has been locked by processor with master_index = 1.
37726 * 0b0011..The gate has been locked by processor with master_index = 2.
37727 * 0b0100..The gate has been locked by processor with master_index = 3.
37728 * 0b0101..The gate has been locked by processor with master_index = 4.
37729 * 0b0110..The gate has been locked by processor with master_index = 5.
37730 * 0b0111..The gate has been locked by processor with master_index = 6.
37731 * 0b1000..The gate has been locked by processor with master_index = 7.
37732 * 0b1001..The gate has been locked by processor with master_index = 8.
37733 * 0b1010..The gate has been locked by processor with master_index = 9.
37734 * 0b1011..The gate has been locked by processor with master_index = 10.
37735 * 0b1100..The gate has been locked by processor with master_index = 11.
37736 * 0b1101..The gate has been locked by processor with master_index = 12.
37737 * 0b1110..The gate has been locked by processor with master_index = 13.
37738 * 0b1111..The gate has been locked by processor with master_index = 14.
37739 */
37740#define RDC_SEMAPHORE_GATE15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE15_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE15_GTFSM_MASK)
37741#define RDC_SEMAPHORE_GATE15_LDOM_MASK (0x30U)
37742#define RDC_SEMAPHORE_GATE15_LDOM_SHIFT (4U)
37743/*! LDOM
37744 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37745 * 0b01..The gate has been locked by domain 1.
37746 * 0b10..The gate has been locked by domain 2.
37747 * 0b11..The gate has been locked by domain 3.
37748 */
37749#define RDC_SEMAPHORE_GATE15_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE15_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE15_LDOM_MASK)
37750/*! @} */
37751
37752/*! @name GATE16 - Gate Register */
37753/*! @{ */
37754#define RDC_SEMAPHORE_GATE16_GTFSM_MASK (0xFU)
37755#define RDC_SEMAPHORE_GATE16_GTFSM_SHIFT (0U)
37756/*! GTFSM - Gate Finite State Machine.
37757 * 0b0000..The gate is unlocked (free).
37758 * 0b0001..The gate has been locked by processor with master_index = 0.
37759 * 0b0010..The gate has been locked by processor with master_index = 1.
37760 * 0b0011..The gate has been locked by processor with master_index = 2.
37761 * 0b0100..The gate has been locked by processor with master_index = 3.
37762 * 0b0101..The gate has been locked by processor with master_index = 4.
37763 * 0b0110..The gate has been locked by processor with master_index = 5.
37764 * 0b0111..The gate has been locked by processor with master_index = 6.
37765 * 0b1000..The gate has been locked by processor with master_index = 7.
37766 * 0b1001..The gate has been locked by processor with master_index = 8.
37767 * 0b1010..The gate has been locked by processor with master_index = 9.
37768 * 0b1011..The gate has been locked by processor with master_index = 10.
37769 * 0b1100..The gate has been locked by processor with master_index = 11.
37770 * 0b1101..The gate has been locked by processor with master_index = 12.
37771 * 0b1110..The gate has been locked by processor with master_index = 13.
37772 * 0b1111..The gate has been locked by processor with master_index = 14.
37773 */
37774#define RDC_SEMAPHORE_GATE16_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE16_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE16_GTFSM_MASK)
37775#define RDC_SEMAPHORE_GATE16_LDOM_MASK (0x30U)
37776#define RDC_SEMAPHORE_GATE16_LDOM_SHIFT (4U)
37777/*! LDOM
37778 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37779 * 0b01..The gate has been locked by domain 1.
37780 * 0b10..The gate has been locked by domain 2.
37781 * 0b11..The gate has been locked by domain 3.
37782 */
37783#define RDC_SEMAPHORE_GATE16_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE16_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE16_LDOM_MASK)
37784/*! @} */
37785
37786/*! @name GATE17 - Gate Register */
37787/*! @{ */
37788#define RDC_SEMAPHORE_GATE17_GTFSM_MASK (0xFU)
37789#define RDC_SEMAPHORE_GATE17_GTFSM_SHIFT (0U)
37790/*! GTFSM - Gate Finite State Machine.
37791 * 0b0000..The gate is unlocked (free).
37792 * 0b0001..The gate has been locked by processor with master_index = 0.
37793 * 0b0010..The gate has been locked by processor with master_index = 1.
37794 * 0b0011..The gate has been locked by processor with master_index = 2.
37795 * 0b0100..The gate has been locked by processor with master_index = 3.
37796 * 0b0101..The gate has been locked by processor with master_index = 4.
37797 * 0b0110..The gate has been locked by processor with master_index = 5.
37798 * 0b0111..The gate has been locked by processor with master_index = 6.
37799 * 0b1000..The gate has been locked by processor with master_index = 7.
37800 * 0b1001..The gate has been locked by processor with master_index = 8.
37801 * 0b1010..The gate has been locked by processor with master_index = 9.
37802 * 0b1011..The gate has been locked by processor with master_index = 10.
37803 * 0b1100..The gate has been locked by processor with master_index = 11.
37804 * 0b1101..The gate has been locked by processor with master_index = 12.
37805 * 0b1110..The gate has been locked by processor with master_index = 13.
37806 * 0b1111..The gate has been locked by processor with master_index = 14.
37807 */
37808#define RDC_SEMAPHORE_GATE17_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE17_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE17_GTFSM_MASK)
37809#define RDC_SEMAPHORE_GATE17_LDOM_MASK (0x30U)
37810#define RDC_SEMAPHORE_GATE17_LDOM_SHIFT (4U)
37811/*! LDOM
37812 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37813 * 0b01..The gate has been locked by domain 1.
37814 * 0b10..The gate has been locked by domain 2.
37815 * 0b11..The gate has been locked by domain 3.
37816 */
37817#define RDC_SEMAPHORE_GATE17_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE17_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE17_LDOM_MASK)
37818/*! @} */
37819
37820/*! @name GATE18 - Gate Register */
37821/*! @{ */
37822#define RDC_SEMAPHORE_GATE18_GTFSM_MASK (0xFU)
37823#define RDC_SEMAPHORE_GATE18_GTFSM_SHIFT (0U)
37824/*! GTFSM - Gate Finite State Machine.
37825 * 0b0000..The gate is unlocked (free).
37826 * 0b0001..The gate has been locked by processor with master_index = 0.
37827 * 0b0010..The gate has been locked by processor with master_index = 1.
37828 * 0b0011..The gate has been locked by processor with master_index = 2.
37829 * 0b0100..The gate has been locked by processor with master_index = 3.
37830 * 0b0101..The gate has been locked by processor with master_index = 4.
37831 * 0b0110..The gate has been locked by processor with master_index = 5.
37832 * 0b0111..The gate has been locked by processor with master_index = 6.
37833 * 0b1000..The gate has been locked by processor with master_index = 7.
37834 * 0b1001..The gate has been locked by processor with master_index = 8.
37835 * 0b1010..The gate has been locked by processor with master_index = 9.
37836 * 0b1011..The gate has been locked by processor with master_index = 10.
37837 * 0b1100..The gate has been locked by processor with master_index = 11.
37838 * 0b1101..The gate has been locked by processor with master_index = 12.
37839 * 0b1110..The gate has been locked by processor with master_index = 13.
37840 * 0b1111..The gate has been locked by processor with master_index = 14.
37841 */
37842#define RDC_SEMAPHORE_GATE18_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE18_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE18_GTFSM_MASK)
37843#define RDC_SEMAPHORE_GATE18_LDOM_MASK (0x30U)
37844#define RDC_SEMAPHORE_GATE18_LDOM_SHIFT (4U)
37845/*! LDOM
37846 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37847 * 0b01..The gate has been locked by domain 1.
37848 * 0b10..The gate has been locked by domain 2.
37849 * 0b11..The gate has been locked by domain 3.
37850 */
37851#define RDC_SEMAPHORE_GATE18_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE18_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE18_LDOM_MASK)
37852/*! @} */
37853
37854/*! @name GATE19 - Gate Register */
37855/*! @{ */
37856#define RDC_SEMAPHORE_GATE19_GTFSM_MASK (0xFU)
37857#define RDC_SEMAPHORE_GATE19_GTFSM_SHIFT (0U)
37858/*! GTFSM - Gate Finite State Machine.
37859 * 0b0000..The gate is unlocked (free).
37860 * 0b0001..The gate has been locked by processor with master_index = 0.
37861 * 0b0010..The gate has been locked by processor with master_index = 1.
37862 * 0b0011..The gate has been locked by processor with master_index = 2.
37863 * 0b0100..The gate has been locked by processor with master_index = 3.
37864 * 0b0101..The gate has been locked by processor with master_index = 4.
37865 * 0b0110..The gate has been locked by processor with master_index = 5.
37866 * 0b0111..The gate has been locked by processor with master_index = 6.
37867 * 0b1000..The gate has been locked by processor with master_index = 7.
37868 * 0b1001..The gate has been locked by processor with master_index = 8.
37869 * 0b1010..The gate has been locked by processor with master_index = 9.
37870 * 0b1011..The gate has been locked by processor with master_index = 10.
37871 * 0b1100..The gate has been locked by processor with master_index = 11.
37872 * 0b1101..The gate has been locked by processor with master_index = 12.
37873 * 0b1110..The gate has been locked by processor with master_index = 13.
37874 * 0b1111..The gate has been locked by processor with master_index = 14.
37875 */
37876#define RDC_SEMAPHORE_GATE19_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE19_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE19_GTFSM_MASK)
37877#define RDC_SEMAPHORE_GATE19_LDOM_MASK (0x30U)
37878#define RDC_SEMAPHORE_GATE19_LDOM_SHIFT (4U)
37879/*! LDOM
37880 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37881 * 0b01..The gate has been locked by domain 1.
37882 * 0b10..The gate has been locked by domain 2.
37883 * 0b11..The gate has been locked by domain 3.
37884 */
37885#define RDC_SEMAPHORE_GATE19_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE19_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE19_LDOM_MASK)
37886/*! @} */
37887
37888/*! @name GATE20 - Gate Register */
37889/*! @{ */
37890#define RDC_SEMAPHORE_GATE20_GTFSM_MASK (0xFU)
37891#define RDC_SEMAPHORE_GATE20_GTFSM_SHIFT (0U)
37892/*! GTFSM - Gate Finite State Machine.
37893 * 0b0000..The gate is unlocked (free).
37894 * 0b0001..The gate has been locked by processor with master_index = 0.
37895 * 0b0010..The gate has been locked by processor with master_index = 1.
37896 * 0b0011..The gate has been locked by processor with master_index = 2.
37897 * 0b0100..The gate has been locked by processor with master_index = 3.
37898 * 0b0101..The gate has been locked by processor with master_index = 4.
37899 * 0b0110..The gate has been locked by processor with master_index = 5.
37900 * 0b0111..The gate has been locked by processor with master_index = 6.
37901 * 0b1000..The gate has been locked by processor with master_index = 7.
37902 * 0b1001..The gate has been locked by processor with master_index = 8.
37903 * 0b1010..The gate has been locked by processor with master_index = 9.
37904 * 0b1011..The gate has been locked by processor with master_index = 10.
37905 * 0b1100..The gate has been locked by processor with master_index = 11.
37906 * 0b1101..The gate has been locked by processor with master_index = 12.
37907 * 0b1110..The gate has been locked by processor with master_index = 13.
37908 * 0b1111..The gate has been locked by processor with master_index = 14.
37909 */
37910#define RDC_SEMAPHORE_GATE20_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE20_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE20_GTFSM_MASK)
37911#define RDC_SEMAPHORE_GATE20_LDOM_MASK (0x30U)
37912#define RDC_SEMAPHORE_GATE20_LDOM_SHIFT (4U)
37913/*! LDOM
37914 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37915 * 0b01..The gate has been locked by domain 1.
37916 * 0b10..The gate has been locked by domain 2.
37917 * 0b11..The gate has been locked by domain 3.
37918 */
37919#define RDC_SEMAPHORE_GATE20_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE20_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE20_LDOM_MASK)
37920/*! @} */
37921
37922/*! @name GATE21 - Gate Register */
37923/*! @{ */
37924#define RDC_SEMAPHORE_GATE21_GTFSM_MASK (0xFU)
37925#define RDC_SEMAPHORE_GATE21_GTFSM_SHIFT (0U)
37926/*! GTFSM - Gate Finite State Machine.
37927 * 0b0000..The gate is unlocked (free).
37928 * 0b0001..The gate has been locked by processor with master_index = 0.
37929 * 0b0010..The gate has been locked by processor with master_index = 1.
37930 * 0b0011..The gate has been locked by processor with master_index = 2.
37931 * 0b0100..The gate has been locked by processor with master_index = 3.
37932 * 0b0101..The gate has been locked by processor with master_index = 4.
37933 * 0b0110..The gate has been locked by processor with master_index = 5.
37934 * 0b0111..The gate has been locked by processor with master_index = 6.
37935 * 0b1000..The gate has been locked by processor with master_index = 7.
37936 * 0b1001..The gate has been locked by processor with master_index = 8.
37937 * 0b1010..The gate has been locked by processor with master_index = 9.
37938 * 0b1011..The gate has been locked by processor with master_index = 10.
37939 * 0b1100..The gate has been locked by processor with master_index = 11.
37940 * 0b1101..The gate has been locked by processor with master_index = 12.
37941 * 0b1110..The gate has been locked by processor with master_index = 13.
37942 * 0b1111..The gate has been locked by processor with master_index = 14.
37943 */
37944#define RDC_SEMAPHORE_GATE21_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE21_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE21_GTFSM_MASK)
37945#define RDC_SEMAPHORE_GATE21_LDOM_MASK (0x30U)
37946#define RDC_SEMAPHORE_GATE21_LDOM_SHIFT (4U)
37947/*! LDOM
37948 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37949 * 0b01..The gate has been locked by domain 1.
37950 * 0b10..The gate has been locked by domain 2.
37951 * 0b11..The gate has been locked by domain 3.
37952 */
37953#define RDC_SEMAPHORE_GATE21_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE21_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE21_LDOM_MASK)
37954/*! @} */
37955
37956/*! @name GATE22 - Gate Register */
37957/*! @{ */
37958#define RDC_SEMAPHORE_GATE22_GTFSM_MASK (0xFU)
37959#define RDC_SEMAPHORE_GATE22_GTFSM_SHIFT (0U)
37960/*! GTFSM - Gate Finite State Machine.
37961 * 0b0000..The gate is unlocked (free).
37962 * 0b0001..The gate has been locked by processor with master_index = 0.
37963 * 0b0010..The gate has been locked by processor with master_index = 1.
37964 * 0b0011..The gate has been locked by processor with master_index = 2.
37965 * 0b0100..The gate has been locked by processor with master_index = 3.
37966 * 0b0101..The gate has been locked by processor with master_index = 4.
37967 * 0b0110..The gate has been locked by processor with master_index = 5.
37968 * 0b0111..The gate has been locked by processor with master_index = 6.
37969 * 0b1000..The gate has been locked by processor with master_index = 7.
37970 * 0b1001..The gate has been locked by processor with master_index = 8.
37971 * 0b1010..The gate has been locked by processor with master_index = 9.
37972 * 0b1011..The gate has been locked by processor with master_index = 10.
37973 * 0b1100..The gate has been locked by processor with master_index = 11.
37974 * 0b1101..The gate has been locked by processor with master_index = 12.
37975 * 0b1110..The gate has been locked by processor with master_index = 13.
37976 * 0b1111..The gate has been locked by processor with master_index = 14.
37977 */
37978#define RDC_SEMAPHORE_GATE22_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE22_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE22_GTFSM_MASK)
37979#define RDC_SEMAPHORE_GATE22_LDOM_MASK (0x30U)
37980#define RDC_SEMAPHORE_GATE22_LDOM_SHIFT (4U)
37981/*! LDOM
37982 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
37983 * 0b01..The gate has been locked by domain 1.
37984 * 0b10..The gate has been locked by domain 2.
37985 * 0b11..The gate has been locked by domain 3.
37986 */
37987#define RDC_SEMAPHORE_GATE22_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE22_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE22_LDOM_MASK)
37988/*! @} */
37989
37990/*! @name GATE23 - Gate Register */
37991/*! @{ */
37992#define RDC_SEMAPHORE_GATE23_GTFSM_MASK (0xFU)
37993#define RDC_SEMAPHORE_GATE23_GTFSM_SHIFT (0U)
37994/*! GTFSM - Gate Finite State Machine.
37995 * 0b0000..The gate is unlocked (free).
37996 * 0b0001..The gate has been locked by processor with master_index = 0.
37997 * 0b0010..The gate has been locked by processor with master_index = 1.
37998 * 0b0011..The gate has been locked by processor with master_index = 2.
37999 * 0b0100..The gate has been locked by processor with master_index = 3.
38000 * 0b0101..The gate has been locked by processor with master_index = 4.
38001 * 0b0110..The gate has been locked by processor with master_index = 5.
38002 * 0b0111..The gate has been locked by processor with master_index = 6.
38003 * 0b1000..The gate has been locked by processor with master_index = 7.
38004 * 0b1001..The gate has been locked by processor with master_index = 8.
38005 * 0b1010..The gate has been locked by processor with master_index = 9.
38006 * 0b1011..The gate has been locked by processor with master_index = 10.
38007 * 0b1100..The gate has been locked by processor with master_index = 11.
38008 * 0b1101..The gate has been locked by processor with master_index = 12.
38009 * 0b1110..The gate has been locked by processor with master_index = 13.
38010 * 0b1111..The gate has been locked by processor with master_index = 14.
38011 */
38012#define RDC_SEMAPHORE_GATE23_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE23_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE23_GTFSM_MASK)
38013#define RDC_SEMAPHORE_GATE23_LDOM_MASK (0x30U)
38014#define RDC_SEMAPHORE_GATE23_LDOM_SHIFT (4U)
38015/*! LDOM
38016 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38017 * 0b01..The gate has been locked by domain 1.
38018 * 0b10..The gate has been locked by domain 2.
38019 * 0b11..The gate has been locked by domain 3.
38020 */
38021#define RDC_SEMAPHORE_GATE23_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE23_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE23_LDOM_MASK)
38022/*! @} */
38023
38024/*! @name GATE24 - Gate Register */
38025/*! @{ */
38026#define RDC_SEMAPHORE_GATE24_GTFSM_MASK (0xFU)
38027#define RDC_SEMAPHORE_GATE24_GTFSM_SHIFT (0U)
38028/*! GTFSM - Gate Finite State Machine.
38029 * 0b0000..The gate is unlocked (free).
38030 * 0b0001..The gate has been locked by processor with master_index = 0.
38031 * 0b0010..The gate has been locked by processor with master_index = 1.
38032 * 0b0011..The gate has been locked by processor with master_index = 2.
38033 * 0b0100..The gate has been locked by processor with master_index = 3.
38034 * 0b0101..The gate has been locked by processor with master_index = 4.
38035 * 0b0110..The gate has been locked by processor with master_index = 5.
38036 * 0b0111..The gate has been locked by processor with master_index = 6.
38037 * 0b1000..The gate has been locked by processor with master_index = 7.
38038 * 0b1001..The gate has been locked by processor with master_index = 8.
38039 * 0b1010..The gate has been locked by processor with master_index = 9.
38040 * 0b1011..The gate has been locked by processor with master_index = 10.
38041 * 0b1100..The gate has been locked by processor with master_index = 11.
38042 * 0b1101..The gate has been locked by processor with master_index = 12.
38043 * 0b1110..The gate has been locked by processor with master_index = 13.
38044 * 0b1111..The gate has been locked by processor with master_index = 14.
38045 */
38046#define RDC_SEMAPHORE_GATE24_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE24_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE24_GTFSM_MASK)
38047#define RDC_SEMAPHORE_GATE24_LDOM_MASK (0x30U)
38048#define RDC_SEMAPHORE_GATE24_LDOM_SHIFT (4U)
38049/*! LDOM
38050 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38051 * 0b01..The gate has been locked by domain 1.
38052 * 0b10..The gate has been locked by domain 2.
38053 * 0b11..The gate has been locked by domain 3.
38054 */
38055#define RDC_SEMAPHORE_GATE24_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE24_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE24_LDOM_MASK)
38056/*! @} */
38057
38058/*! @name GATE25 - Gate Register */
38059/*! @{ */
38060#define RDC_SEMAPHORE_GATE25_GTFSM_MASK (0xFU)
38061#define RDC_SEMAPHORE_GATE25_GTFSM_SHIFT (0U)
38062/*! GTFSM - Gate Finite State Machine.
38063 * 0b0000..The gate is unlocked (free).
38064 * 0b0001..The gate has been locked by processor with master_index = 0.
38065 * 0b0010..The gate has been locked by processor with master_index = 1.
38066 * 0b0011..The gate has been locked by processor with master_index = 2.
38067 * 0b0100..The gate has been locked by processor with master_index = 3.
38068 * 0b0101..The gate has been locked by processor with master_index = 4.
38069 * 0b0110..The gate has been locked by processor with master_index = 5.
38070 * 0b0111..The gate has been locked by processor with master_index = 6.
38071 * 0b1000..The gate has been locked by processor with master_index = 7.
38072 * 0b1001..The gate has been locked by processor with master_index = 8.
38073 * 0b1010..The gate has been locked by processor with master_index = 9.
38074 * 0b1011..The gate has been locked by processor with master_index = 10.
38075 * 0b1100..The gate has been locked by processor with master_index = 11.
38076 * 0b1101..The gate has been locked by processor with master_index = 12.
38077 * 0b1110..The gate has been locked by processor with master_index = 13.
38078 * 0b1111..The gate has been locked by processor with master_index = 14.
38079 */
38080#define RDC_SEMAPHORE_GATE25_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE25_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE25_GTFSM_MASK)
38081#define RDC_SEMAPHORE_GATE25_LDOM_MASK (0x30U)
38082#define RDC_SEMAPHORE_GATE25_LDOM_SHIFT (4U)
38083/*! LDOM
38084 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38085 * 0b01..The gate has been locked by domain 1.
38086 * 0b10..The gate has been locked by domain 2.
38087 * 0b11..The gate has been locked by domain 3.
38088 */
38089#define RDC_SEMAPHORE_GATE25_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE25_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE25_LDOM_MASK)
38090/*! @} */
38091
38092/*! @name GATE26 - Gate Register */
38093/*! @{ */
38094#define RDC_SEMAPHORE_GATE26_GTFSM_MASK (0xFU)
38095#define RDC_SEMAPHORE_GATE26_GTFSM_SHIFT (0U)
38096/*! GTFSM - Gate Finite State Machine.
38097 * 0b0000..The gate is unlocked (free).
38098 * 0b0001..The gate has been locked by processor with master_index = 0.
38099 * 0b0010..The gate has been locked by processor with master_index = 1.
38100 * 0b0011..The gate has been locked by processor with master_index = 2.
38101 * 0b0100..The gate has been locked by processor with master_index = 3.
38102 * 0b0101..The gate has been locked by processor with master_index = 4.
38103 * 0b0110..The gate has been locked by processor with master_index = 5.
38104 * 0b0111..The gate has been locked by processor with master_index = 6.
38105 * 0b1000..The gate has been locked by processor with master_index = 7.
38106 * 0b1001..The gate has been locked by processor with master_index = 8.
38107 * 0b1010..The gate has been locked by processor with master_index = 9.
38108 * 0b1011..The gate has been locked by processor with master_index = 10.
38109 * 0b1100..The gate has been locked by processor with master_index = 11.
38110 * 0b1101..The gate has been locked by processor with master_index = 12.
38111 * 0b1110..The gate has been locked by processor with master_index = 13.
38112 * 0b1111..The gate has been locked by processor with master_index = 14.
38113 */
38114#define RDC_SEMAPHORE_GATE26_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE26_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE26_GTFSM_MASK)
38115#define RDC_SEMAPHORE_GATE26_LDOM_MASK (0x30U)
38116#define RDC_SEMAPHORE_GATE26_LDOM_SHIFT (4U)
38117/*! LDOM
38118 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38119 * 0b01..The gate has been locked by domain 1.
38120 * 0b10..The gate has been locked by domain 2.
38121 * 0b11..The gate has been locked by domain 3.
38122 */
38123#define RDC_SEMAPHORE_GATE26_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE26_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE26_LDOM_MASK)
38124/*! @} */
38125
38126/*! @name GATE27 - Gate Register */
38127/*! @{ */
38128#define RDC_SEMAPHORE_GATE27_GTFSM_MASK (0xFU)
38129#define RDC_SEMAPHORE_GATE27_GTFSM_SHIFT (0U)
38130/*! GTFSM - Gate Finite State Machine.
38131 * 0b0000..The gate is unlocked (free).
38132 * 0b0001..The gate has been locked by processor with master_index = 0.
38133 * 0b0010..The gate has been locked by processor with master_index = 1.
38134 * 0b0011..The gate has been locked by processor with master_index = 2.
38135 * 0b0100..The gate has been locked by processor with master_index = 3.
38136 * 0b0101..The gate has been locked by processor with master_index = 4.
38137 * 0b0110..The gate has been locked by processor with master_index = 5.
38138 * 0b0111..The gate has been locked by processor with master_index = 6.
38139 * 0b1000..The gate has been locked by processor with master_index = 7.
38140 * 0b1001..The gate has been locked by processor with master_index = 8.
38141 * 0b1010..The gate has been locked by processor with master_index = 9.
38142 * 0b1011..The gate has been locked by processor with master_index = 10.
38143 * 0b1100..The gate has been locked by processor with master_index = 11.
38144 * 0b1101..The gate has been locked by processor with master_index = 12.
38145 * 0b1110..The gate has been locked by processor with master_index = 13.
38146 * 0b1111..The gate has been locked by processor with master_index = 14.
38147 */
38148#define RDC_SEMAPHORE_GATE27_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE27_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE27_GTFSM_MASK)
38149#define RDC_SEMAPHORE_GATE27_LDOM_MASK (0x30U)
38150#define RDC_SEMAPHORE_GATE27_LDOM_SHIFT (4U)
38151/*! LDOM
38152 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38153 * 0b01..The gate has been locked by domain 1.
38154 * 0b10..The gate has been locked by domain 2.
38155 * 0b11..The gate has been locked by domain 3.
38156 */
38157#define RDC_SEMAPHORE_GATE27_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE27_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE27_LDOM_MASK)
38158/*! @} */
38159
38160/*! @name GATE28 - Gate Register */
38161/*! @{ */
38162#define RDC_SEMAPHORE_GATE28_GTFSM_MASK (0xFU)
38163#define RDC_SEMAPHORE_GATE28_GTFSM_SHIFT (0U)
38164/*! GTFSM - Gate Finite State Machine.
38165 * 0b0000..The gate is unlocked (free).
38166 * 0b0001..The gate has been locked by processor with master_index = 0.
38167 * 0b0010..The gate has been locked by processor with master_index = 1.
38168 * 0b0011..The gate has been locked by processor with master_index = 2.
38169 * 0b0100..The gate has been locked by processor with master_index = 3.
38170 * 0b0101..The gate has been locked by processor with master_index = 4.
38171 * 0b0110..The gate has been locked by processor with master_index = 5.
38172 * 0b0111..The gate has been locked by processor with master_index = 6.
38173 * 0b1000..The gate has been locked by processor with master_index = 7.
38174 * 0b1001..The gate has been locked by processor with master_index = 8.
38175 * 0b1010..The gate has been locked by processor with master_index = 9.
38176 * 0b1011..The gate has been locked by processor with master_index = 10.
38177 * 0b1100..The gate has been locked by processor with master_index = 11.
38178 * 0b1101..The gate has been locked by processor with master_index = 12.
38179 * 0b1110..The gate has been locked by processor with master_index = 13.
38180 * 0b1111..The gate has been locked by processor with master_index = 14.
38181 */
38182#define RDC_SEMAPHORE_GATE28_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE28_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE28_GTFSM_MASK)
38183#define RDC_SEMAPHORE_GATE28_LDOM_MASK (0x30U)
38184#define RDC_SEMAPHORE_GATE28_LDOM_SHIFT (4U)
38185/*! LDOM
38186 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38187 * 0b01..The gate has been locked by domain 1.
38188 * 0b10..The gate has been locked by domain 2.
38189 * 0b11..The gate has been locked by domain 3.
38190 */
38191#define RDC_SEMAPHORE_GATE28_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE28_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE28_LDOM_MASK)
38192/*! @} */
38193
38194/*! @name GATE29 - Gate Register */
38195/*! @{ */
38196#define RDC_SEMAPHORE_GATE29_GTFSM_MASK (0xFU)
38197#define RDC_SEMAPHORE_GATE29_GTFSM_SHIFT (0U)
38198/*! GTFSM - Gate Finite State Machine.
38199 * 0b0000..The gate is unlocked (free).
38200 * 0b0001..The gate has been locked by processor with master_index = 0.
38201 * 0b0010..The gate has been locked by processor with master_index = 1.
38202 * 0b0011..The gate has been locked by processor with master_index = 2.
38203 * 0b0100..The gate has been locked by processor with master_index = 3.
38204 * 0b0101..The gate has been locked by processor with master_index = 4.
38205 * 0b0110..The gate has been locked by processor with master_index = 5.
38206 * 0b0111..The gate has been locked by processor with master_index = 6.
38207 * 0b1000..The gate has been locked by processor with master_index = 7.
38208 * 0b1001..The gate has been locked by processor with master_index = 8.
38209 * 0b1010..The gate has been locked by processor with master_index = 9.
38210 * 0b1011..The gate has been locked by processor with master_index = 10.
38211 * 0b1100..The gate has been locked by processor with master_index = 11.
38212 * 0b1101..The gate has been locked by processor with master_index = 12.
38213 * 0b1110..The gate has been locked by processor with master_index = 13.
38214 * 0b1111..The gate has been locked by processor with master_index = 14.
38215 */
38216#define RDC_SEMAPHORE_GATE29_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE29_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE29_GTFSM_MASK)
38217#define RDC_SEMAPHORE_GATE29_LDOM_MASK (0x30U)
38218#define RDC_SEMAPHORE_GATE29_LDOM_SHIFT (4U)
38219/*! LDOM
38220 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38221 * 0b01..The gate has been locked by domain 1.
38222 * 0b10..The gate has been locked by domain 2.
38223 * 0b11..The gate has been locked by domain 3.
38224 */
38225#define RDC_SEMAPHORE_GATE29_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE29_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE29_LDOM_MASK)
38226/*! @} */
38227
38228/*! @name GATE30 - Gate Register */
38229/*! @{ */
38230#define RDC_SEMAPHORE_GATE30_GTFSM_MASK (0xFU)
38231#define RDC_SEMAPHORE_GATE30_GTFSM_SHIFT (0U)
38232/*! GTFSM - Gate Finite State Machine.
38233 * 0b0000..The gate is unlocked (free).
38234 * 0b0001..The gate has been locked by processor with master_index = 0.
38235 * 0b0010..The gate has been locked by processor with master_index = 1.
38236 * 0b0011..The gate has been locked by processor with master_index = 2.
38237 * 0b0100..The gate has been locked by processor with master_index = 3.
38238 * 0b0101..The gate has been locked by processor with master_index = 4.
38239 * 0b0110..The gate has been locked by processor with master_index = 5.
38240 * 0b0111..The gate has been locked by processor with master_index = 6.
38241 * 0b1000..The gate has been locked by processor with master_index = 7.
38242 * 0b1001..The gate has been locked by processor with master_index = 8.
38243 * 0b1010..The gate has been locked by processor with master_index = 9.
38244 * 0b1011..The gate has been locked by processor with master_index = 10.
38245 * 0b1100..The gate has been locked by processor with master_index = 11.
38246 * 0b1101..The gate has been locked by processor with master_index = 12.
38247 * 0b1110..The gate has been locked by processor with master_index = 13.
38248 * 0b1111..The gate has been locked by processor with master_index = 14.
38249 */
38250#define RDC_SEMAPHORE_GATE30_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE30_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE30_GTFSM_MASK)
38251#define RDC_SEMAPHORE_GATE30_LDOM_MASK (0x30U)
38252#define RDC_SEMAPHORE_GATE30_LDOM_SHIFT (4U)
38253/*! LDOM
38254 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38255 * 0b01..The gate has been locked by domain 1.
38256 * 0b10..The gate has been locked by domain 2.
38257 * 0b11..The gate has been locked by domain 3.
38258 */
38259#define RDC_SEMAPHORE_GATE30_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE30_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE30_LDOM_MASK)
38260/*! @} */
38261
38262/*! @name GATE31 - Gate Register */
38263/*! @{ */
38264#define RDC_SEMAPHORE_GATE31_GTFSM_MASK (0xFU)
38265#define RDC_SEMAPHORE_GATE31_GTFSM_SHIFT (0U)
38266/*! GTFSM - Gate Finite State Machine.
38267 * 0b0000..The gate is unlocked (free).
38268 * 0b0001..The gate has been locked by processor with master_index = 0.
38269 * 0b0010..The gate has been locked by processor with master_index = 1.
38270 * 0b0011..The gate has been locked by processor with master_index = 2.
38271 * 0b0100..The gate has been locked by processor with master_index = 3.
38272 * 0b0101..The gate has been locked by processor with master_index = 4.
38273 * 0b0110..The gate has been locked by processor with master_index = 5.
38274 * 0b0111..The gate has been locked by processor with master_index = 6.
38275 * 0b1000..The gate has been locked by processor with master_index = 7.
38276 * 0b1001..The gate has been locked by processor with master_index = 8.
38277 * 0b1010..The gate has been locked by processor with master_index = 9.
38278 * 0b1011..The gate has been locked by processor with master_index = 10.
38279 * 0b1100..The gate has been locked by processor with master_index = 11.
38280 * 0b1101..The gate has been locked by processor with master_index = 12.
38281 * 0b1110..The gate has been locked by processor with master_index = 13.
38282 * 0b1111..The gate has been locked by processor with master_index = 14.
38283 */
38284#define RDC_SEMAPHORE_GATE31_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE31_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE31_GTFSM_MASK)
38285#define RDC_SEMAPHORE_GATE31_LDOM_MASK (0x30U)
38286#define RDC_SEMAPHORE_GATE31_LDOM_SHIFT (4U)
38287/*! LDOM
38288 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38289 * 0b01..The gate has been locked by domain 1.
38290 * 0b10..The gate has been locked by domain 2.
38291 * 0b11..The gate has been locked by domain 3.
38292 */
38293#define RDC_SEMAPHORE_GATE31_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE31_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE31_LDOM_MASK)
38294/*! @} */
38295
38296/*! @name GATE32 - Gate Register */
38297/*! @{ */
38298#define RDC_SEMAPHORE_GATE32_GTFSM_MASK (0xFU)
38299#define RDC_SEMAPHORE_GATE32_GTFSM_SHIFT (0U)
38300/*! GTFSM - Gate Finite State Machine.
38301 * 0b0000..The gate is unlocked (free).
38302 * 0b0001..The gate has been locked by processor with master_index = 0.
38303 * 0b0010..The gate has been locked by processor with master_index = 1.
38304 * 0b0011..The gate has been locked by processor with master_index = 2.
38305 * 0b0100..The gate has been locked by processor with master_index = 3.
38306 * 0b0101..The gate has been locked by processor with master_index = 4.
38307 * 0b0110..The gate has been locked by processor with master_index = 5.
38308 * 0b0111..The gate has been locked by processor with master_index = 6.
38309 * 0b1000..The gate has been locked by processor with master_index = 7.
38310 * 0b1001..The gate has been locked by processor with master_index = 8.
38311 * 0b1010..The gate has been locked by processor with master_index = 9.
38312 * 0b1011..The gate has been locked by processor with master_index = 10.
38313 * 0b1100..The gate has been locked by processor with master_index = 11.
38314 * 0b1101..The gate has been locked by processor with master_index = 12.
38315 * 0b1110..The gate has been locked by processor with master_index = 13.
38316 * 0b1111..The gate has been locked by processor with master_index = 14.
38317 */
38318#define RDC_SEMAPHORE_GATE32_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE32_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE32_GTFSM_MASK)
38319#define RDC_SEMAPHORE_GATE32_LDOM_MASK (0x30U)
38320#define RDC_SEMAPHORE_GATE32_LDOM_SHIFT (4U)
38321/*! LDOM
38322 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38323 * 0b01..The gate has been locked by domain 1.
38324 * 0b10..The gate has been locked by domain 2.
38325 * 0b11..The gate has been locked by domain 3.
38326 */
38327#define RDC_SEMAPHORE_GATE32_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE32_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE32_LDOM_MASK)
38328/*! @} */
38329
38330/*! @name GATE33 - Gate Register */
38331/*! @{ */
38332#define RDC_SEMAPHORE_GATE33_GTFSM_MASK (0xFU)
38333#define RDC_SEMAPHORE_GATE33_GTFSM_SHIFT (0U)
38334/*! GTFSM - Gate Finite State Machine.
38335 * 0b0000..The gate is unlocked (free).
38336 * 0b0001..The gate has been locked by processor with master_index = 0.
38337 * 0b0010..The gate has been locked by processor with master_index = 1.
38338 * 0b0011..The gate has been locked by processor with master_index = 2.
38339 * 0b0100..The gate has been locked by processor with master_index = 3.
38340 * 0b0101..The gate has been locked by processor with master_index = 4.
38341 * 0b0110..The gate has been locked by processor with master_index = 5.
38342 * 0b0111..The gate has been locked by processor with master_index = 6.
38343 * 0b1000..The gate has been locked by processor with master_index = 7.
38344 * 0b1001..The gate has been locked by processor with master_index = 8.
38345 * 0b1010..The gate has been locked by processor with master_index = 9.
38346 * 0b1011..The gate has been locked by processor with master_index = 10.
38347 * 0b1100..The gate has been locked by processor with master_index = 11.
38348 * 0b1101..The gate has been locked by processor with master_index = 12.
38349 * 0b1110..The gate has been locked by processor with master_index = 13.
38350 * 0b1111..The gate has been locked by processor with master_index = 14.
38351 */
38352#define RDC_SEMAPHORE_GATE33_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE33_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE33_GTFSM_MASK)
38353#define RDC_SEMAPHORE_GATE33_LDOM_MASK (0x30U)
38354#define RDC_SEMAPHORE_GATE33_LDOM_SHIFT (4U)
38355/*! LDOM
38356 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38357 * 0b01..The gate has been locked by domain 1.
38358 * 0b10..The gate has been locked by domain 2.
38359 * 0b11..The gate has been locked by domain 3.
38360 */
38361#define RDC_SEMAPHORE_GATE33_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE33_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE33_LDOM_MASK)
38362/*! @} */
38363
38364/*! @name GATE34 - Gate Register */
38365/*! @{ */
38366#define RDC_SEMAPHORE_GATE34_GTFSM_MASK (0xFU)
38367#define RDC_SEMAPHORE_GATE34_GTFSM_SHIFT (0U)
38368/*! GTFSM - Gate Finite State Machine.
38369 * 0b0000..The gate is unlocked (free).
38370 * 0b0001..The gate has been locked by processor with master_index = 0.
38371 * 0b0010..The gate has been locked by processor with master_index = 1.
38372 * 0b0011..The gate has been locked by processor with master_index = 2.
38373 * 0b0100..The gate has been locked by processor with master_index = 3.
38374 * 0b0101..The gate has been locked by processor with master_index = 4.
38375 * 0b0110..The gate has been locked by processor with master_index = 5.
38376 * 0b0111..The gate has been locked by processor with master_index = 6.
38377 * 0b1000..The gate has been locked by processor with master_index = 7.
38378 * 0b1001..The gate has been locked by processor with master_index = 8.
38379 * 0b1010..The gate has been locked by processor with master_index = 9.
38380 * 0b1011..The gate has been locked by processor with master_index = 10.
38381 * 0b1100..The gate has been locked by processor with master_index = 11.
38382 * 0b1101..The gate has been locked by processor with master_index = 12.
38383 * 0b1110..The gate has been locked by processor with master_index = 13.
38384 * 0b1111..The gate has been locked by processor with master_index = 14.
38385 */
38386#define RDC_SEMAPHORE_GATE34_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE34_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE34_GTFSM_MASK)
38387#define RDC_SEMAPHORE_GATE34_LDOM_MASK (0x30U)
38388#define RDC_SEMAPHORE_GATE34_LDOM_SHIFT (4U)
38389/*! LDOM
38390 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38391 * 0b01..The gate has been locked by domain 1.
38392 * 0b10..The gate has been locked by domain 2.
38393 * 0b11..The gate has been locked by domain 3.
38394 */
38395#define RDC_SEMAPHORE_GATE34_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE34_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE34_LDOM_MASK)
38396/*! @} */
38397
38398/*! @name GATE35 - Gate Register */
38399/*! @{ */
38400#define RDC_SEMAPHORE_GATE35_GTFSM_MASK (0xFU)
38401#define RDC_SEMAPHORE_GATE35_GTFSM_SHIFT (0U)
38402/*! GTFSM - Gate Finite State Machine.
38403 * 0b0000..The gate is unlocked (free).
38404 * 0b0001..The gate has been locked by processor with master_index = 0.
38405 * 0b0010..The gate has been locked by processor with master_index = 1.
38406 * 0b0011..The gate has been locked by processor with master_index = 2.
38407 * 0b0100..The gate has been locked by processor with master_index = 3.
38408 * 0b0101..The gate has been locked by processor with master_index = 4.
38409 * 0b0110..The gate has been locked by processor with master_index = 5.
38410 * 0b0111..The gate has been locked by processor with master_index = 6.
38411 * 0b1000..The gate has been locked by processor with master_index = 7.
38412 * 0b1001..The gate has been locked by processor with master_index = 8.
38413 * 0b1010..The gate has been locked by processor with master_index = 9.
38414 * 0b1011..The gate has been locked by processor with master_index = 10.
38415 * 0b1100..The gate has been locked by processor with master_index = 11.
38416 * 0b1101..The gate has been locked by processor with master_index = 12.
38417 * 0b1110..The gate has been locked by processor with master_index = 13.
38418 * 0b1111..The gate has been locked by processor with master_index = 14.
38419 */
38420#define RDC_SEMAPHORE_GATE35_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE35_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE35_GTFSM_MASK)
38421#define RDC_SEMAPHORE_GATE35_LDOM_MASK (0x30U)
38422#define RDC_SEMAPHORE_GATE35_LDOM_SHIFT (4U)
38423/*! LDOM
38424 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38425 * 0b01..The gate has been locked by domain 1.
38426 * 0b10..The gate has been locked by domain 2.
38427 * 0b11..The gate has been locked by domain 3.
38428 */
38429#define RDC_SEMAPHORE_GATE35_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE35_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE35_LDOM_MASK)
38430/*! @} */
38431
38432/*! @name GATE36 - Gate Register */
38433/*! @{ */
38434#define RDC_SEMAPHORE_GATE36_GTFSM_MASK (0xFU)
38435#define RDC_SEMAPHORE_GATE36_GTFSM_SHIFT (0U)
38436/*! GTFSM - Gate Finite State Machine.
38437 * 0b0000..The gate is unlocked (free).
38438 * 0b0001..The gate has been locked by processor with master_index = 0.
38439 * 0b0010..The gate has been locked by processor with master_index = 1.
38440 * 0b0011..The gate has been locked by processor with master_index = 2.
38441 * 0b0100..The gate has been locked by processor with master_index = 3.
38442 * 0b0101..The gate has been locked by processor with master_index = 4.
38443 * 0b0110..The gate has been locked by processor with master_index = 5.
38444 * 0b0111..The gate has been locked by processor with master_index = 6.
38445 * 0b1000..The gate has been locked by processor with master_index = 7.
38446 * 0b1001..The gate has been locked by processor with master_index = 8.
38447 * 0b1010..The gate has been locked by processor with master_index = 9.
38448 * 0b1011..The gate has been locked by processor with master_index = 10.
38449 * 0b1100..The gate has been locked by processor with master_index = 11.
38450 * 0b1101..The gate has been locked by processor with master_index = 12.
38451 * 0b1110..The gate has been locked by processor with master_index = 13.
38452 * 0b1111..The gate has been locked by processor with master_index = 14.
38453 */
38454#define RDC_SEMAPHORE_GATE36_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE36_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE36_GTFSM_MASK)
38455#define RDC_SEMAPHORE_GATE36_LDOM_MASK (0x30U)
38456#define RDC_SEMAPHORE_GATE36_LDOM_SHIFT (4U)
38457/*! LDOM
38458 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38459 * 0b01..The gate has been locked by domain 1.
38460 * 0b10..The gate has been locked by domain 2.
38461 * 0b11..The gate has been locked by domain 3.
38462 */
38463#define RDC_SEMAPHORE_GATE36_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE36_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE36_LDOM_MASK)
38464/*! @} */
38465
38466/*! @name GATE37 - Gate Register */
38467/*! @{ */
38468#define RDC_SEMAPHORE_GATE37_GTFSM_MASK (0xFU)
38469#define RDC_SEMAPHORE_GATE37_GTFSM_SHIFT (0U)
38470/*! GTFSM - Gate Finite State Machine.
38471 * 0b0000..The gate is unlocked (free).
38472 * 0b0001..The gate has been locked by processor with master_index = 0.
38473 * 0b0010..The gate has been locked by processor with master_index = 1.
38474 * 0b0011..The gate has been locked by processor with master_index = 2.
38475 * 0b0100..The gate has been locked by processor with master_index = 3.
38476 * 0b0101..The gate has been locked by processor with master_index = 4.
38477 * 0b0110..The gate has been locked by processor with master_index = 5.
38478 * 0b0111..The gate has been locked by processor with master_index = 6.
38479 * 0b1000..The gate has been locked by processor with master_index = 7.
38480 * 0b1001..The gate has been locked by processor with master_index = 8.
38481 * 0b1010..The gate has been locked by processor with master_index = 9.
38482 * 0b1011..The gate has been locked by processor with master_index = 10.
38483 * 0b1100..The gate has been locked by processor with master_index = 11.
38484 * 0b1101..The gate has been locked by processor with master_index = 12.
38485 * 0b1110..The gate has been locked by processor with master_index = 13.
38486 * 0b1111..The gate has been locked by processor with master_index = 14.
38487 */
38488#define RDC_SEMAPHORE_GATE37_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE37_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE37_GTFSM_MASK)
38489#define RDC_SEMAPHORE_GATE37_LDOM_MASK (0x30U)
38490#define RDC_SEMAPHORE_GATE37_LDOM_SHIFT (4U)
38491/*! LDOM
38492 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38493 * 0b01..The gate has been locked by domain 1.
38494 * 0b10..The gate has been locked by domain 2.
38495 * 0b11..The gate has been locked by domain 3.
38496 */
38497#define RDC_SEMAPHORE_GATE37_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE37_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE37_LDOM_MASK)
38498/*! @} */
38499
38500/*! @name GATE38 - Gate Register */
38501/*! @{ */
38502#define RDC_SEMAPHORE_GATE38_GTFSM_MASK (0xFU)
38503#define RDC_SEMAPHORE_GATE38_GTFSM_SHIFT (0U)
38504/*! GTFSM - Gate Finite State Machine.
38505 * 0b0000..The gate is unlocked (free).
38506 * 0b0001..The gate has been locked by processor with master_index = 0.
38507 * 0b0010..The gate has been locked by processor with master_index = 1.
38508 * 0b0011..The gate has been locked by processor with master_index = 2.
38509 * 0b0100..The gate has been locked by processor with master_index = 3.
38510 * 0b0101..The gate has been locked by processor with master_index = 4.
38511 * 0b0110..The gate has been locked by processor with master_index = 5.
38512 * 0b0111..The gate has been locked by processor with master_index = 6.
38513 * 0b1000..The gate has been locked by processor with master_index = 7.
38514 * 0b1001..The gate has been locked by processor with master_index = 8.
38515 * 0b1010..The gate has been locked by processor with master_index = 9.
38516 * 0b1011..The gate has been locked by processor with master_index = 10.
38517 * 0b1100..The gate has been locked by processor with master_index = 11.
38518 * 0b1101..The gate has been locked by processor with master_index = 12.
38519 * 0b1110..The gate has been locked by processor with master_index = 13.
38520 * 0b1111..The gate has been locked by processor with master_index = 14.
38521 */
38522#define RDC_SEMAPHORE_GATE38_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE38_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE38_GTFSM_MASK)
38523#define RDC_SEMAPHORE_GATE38_LDOM_MASK (0x30U)
38524#define RDC_SEMAPHORE_GATE38_LDOM_SHIFT (4U)
38525/*! LDOM
38526 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38527 * 0b01..The gate has been locked by domain 1.
38528 * 0b10..The gate has been locked by domain 2.
38529 * 0b11..The gate has been locked by domain 3.
38530 */
38531#define RDC_SEMAPHORE_GATE38_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE38_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE38_LDOM_MASK)
38532/*! @} */
38533
38534/*! @name GATE39 - Gate Register */
38535/*! @{ */
38536#define RDC_SEMAPHORE_GATE39_GTFSM_MASK (0xFU)
38537#define RDC_SEMAPHORE_GATE39_GTFSM_SHIFT (0U)
38538/*! GTFSM - Gate Finite State Machine.
38539 * 0b0000..The gate is unlocked (free).
38540 * 0b0001..The gate has been locked by processor with master_index = 0.
38541 * 0b0010..The gate has been locked by processor with master_index = 1.
38542 * 0b0011..The gate has been locked by processor with master_index = 2.
38543 * 0b0100..The gate has been locked by processor with master_index = 3.
38544 * 0b0101..The gate has been locked by processor with master_index = 4.
38545 * 0b0110..The gate has been locked by processor with master_index = 5.
38546 * 0b0111..The gate has been locked by processor with master_index = 6.
38547 * 0b1000..The gate has been locked by processor with master_index = 7.
38548 * 0b1001..The gate has been locked by processor with master_index = 8.
38549 * 0b1010..The gate has been locked by processor with master_index = 9.
38550 * 0b1011..The gate has been locked by processor with master_index = 10.
38551 * 0b1100..The gate has been locked by processor with master_index = 11.
38552 * 0b1101..The gate has been locked by processor with master_index = 12.
38553 * 0b1110..The gate has been locked by processor with master_index = 13.
38554 * 0b1111..The gate has been locked by processor with master_index = 14.
38555 */
38556#define RDC_SEMAPHORE_GATE39_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE39_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE39_GTFSM_MASK)
38557#define RDC_SEMAPHORE_GATE39_LDOM_MASK (0x30U)
38558#define RDC_SEMAPHORE_GATE39_LDOM_SHIFT (4U)
38559/*! LDOM
38560 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38561 * 0b01..The gate has been locked by domain 1.
38562 * 0b10..The gate has been locked by domain 2.
38563 * 0b11..The gate has been locked by domain 3.
38564 */
38565#define RDC_SEMAPHORE_GATE39_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE39_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE39_LDOM_MASK)
38566/*! @} */
38567
38568/*! @name GATE40 - Gate Register */
38569/*! @{ */
38570#define RDC_SEMAPHORE_GATE40_GTFSM_MASK (0xFU)
38571#define RDC_SEMAPHORE_GATE40_GTFSM_SHIFT (0U)
38572/*! GTFSM - Gate Finite State Machine.
38573 * 0b0000..The gate is unlocked (free).
38574 * 0b0001..The gate has been locked by processor with master_index = 0.
38575 * 0b0010..The gate has been locked by processor with master_index = 1.
38576 * 0b0011..The gate has been locked by processor with master_index = 2.
38577 * 0b0100..The gate has been locked by processor with master_index = 3.
38578 * 0b0101..The gate has been locked by processor with master_index = 4.
38579 * 0b0110..The gate has been locked by processor with master_index = 5.
38580 * 0b0111..The gate has been locked by processor with master_index = 6.
38581 * 0b1000..The gate has been locked by processor with master_index = 7.
38582 * 0b1001..The gate has been locked by processor with master_index = 8.
38583 * 0b1010..The gate has been locked by processor with master_index = 9.
38584 * 0b1011..The gate has been locked by processor with master_index = 10.
38585 * 0b1100..The gate has been locked by processor with master_index = 11.
38586 * 0b1101..The gate has been locked by processor with master_index = 12.
38587 * 0b1110..The gate has been locked by processor with master_index = 13.
38588 * 0b1111..The gate has been locked by processor with master_index = 14.
38589 */
38590#define RDC_SEMAPHORE_GATE40_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE40_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE40_GTFSM_MASK)
38591#define RDC_SEMAPHORE_GATE40_LDOM_MASK (0x30U)
38592#define RDC_SEMAPHORE_GATE40_LDOM_SHIFT (4U)
38593/*! LDOM
38594 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38595 * 0b01..The gate has been locked by domain 1.
38596 * 0b10..The gate has been locked by domain 2.
38597 * 0b11..The gate has been locked by domain 3.
38598 */
38599#define RDC_SEMAPHORE_GATE40_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE40_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE40_LDOM_MASK)
38600/*! @} */
38601
38602/*! @name GATE41 - Gate Register */
38603/*! @{ */
38604#define RDC_SEMAPHORE_GATE41_GTFSM_MASK (0xFU)
38605#define RDC_SEMAPHORE_GATE41_GTFSM_SHIFT (0U)
38606/*! GTFSM - Gate Finite State Machine.
38607 * 0b0000..The gate is unlocked (free).
38608 * 0b0001..The gate has been locked by processor with master_index = 0.
38609 * 0b0010..The gate has been locked by processor with master_index = 1.
38610 * 0b0011..The gate has been locked by processor with master_index = 2.
38611 * 0b0100..The gate has been locked by processor with master_index = 3.
38612 * 0b0101..The gate has been locked by processor with master_index = 4.
38613 * 0b0110..The gate has been locked by processor with master_index = 5.
38614 * 0b0111..The gate has been locked by processor with master_index = 6.
38615 * 0b1000..The gate has been locked by processor with master_index = 7.
38616 * 0b1001..The gate has been locked by processor with master_index = 8.
38617 * 0b1010..The gate has been locked by processor with master_index = 9.
38618 * 0b1011..The gate has been locked by processor with master_index = 10.
38619 * 0b1100..The gate has been locked by processor with master_index = 11.
38620 * 0b1101..The gate has been locked by processor with master_index = 12.
38621 * 0b1110..The gate has been locked by processor with master_index = 13.
38622 * 0b1111..The gate has been locked by processor with master_index = 14.
38623 */
38624#define RDC_SEMAPHORE_GATE41_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE41_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE41_GTFSM_MASK)
38625#define RDC_SEMAPHORE_GATE41_LDOM_MASK (0x30U)
38626#define RDC_SEMAPHORE_GATE41_LDOM_SHIFT (4U)
38627/*! LDOM
38628 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38629 * 0b01..The gate has been locked by domain 1.
38630 * 0b10..The gate has been locked by domain 2.
38631 * 0b11..The gate has been locked by domain 3.
38632 */
38633#define RDC_SEMAPHORE_GATE41_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE41_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE41_LDOM_MASK)
38634/*! @} */
38635
38636/*! @name GATE42 - Gate Register */
38637/*! @{ */
38638#define RDC_SEMAPHORE_GATE42_GTFSM_MASK (0xFU)
38639#define RDC_SEMAPHORE_GATE42_GTFSM_SHIFT (0U)
38640/*! GTFSM - Gate Finite State Machine.
38641 * 0b0000..The gate is unlocked (free).
38642 * 0b0001..The gate has been locked by processor with master_index = 0.
38643 * 0b0010..The gate has been locked by processor with master_index = 1.
38644 * 0b0011..The gate has been locked by processor with master_index = 2.
38645 * 0b0100..The gate has been locked by processor with master_index = 3.
38646 * 0b0101..The gate has been locked by processor with master_index = 4.
38647 * 0b0110..The gate has been locked by processor with master_index = 5.
38648 * 0b0111..The gate has been locked by processor with master_index = 6.
38649 * 0b1000..The gate has been locked by processor with master_index = 7.
38650 * 0b1001..The gate has been locked by processor with master_index = 8.
38651 * 0b1010..The gate has been locked by processor with master_index = 9.
38652 * 0b1011..The gate has been locked by processor with master_index = 10.
38653 * 0b1100..The gate has been locked by processor with master_index = 11.
38654 * 0b1101..The gate has been locked by processor with master_index = 12.
38655 * 0b1110..The gate has been locked by processor with master_index = 13.
38656 * 0b1111..The gate has been locked by processor with master_index = 14.
38657 */
38658#define RDC_SEMAPHORE_GATE42_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE42_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE42_GTFSM_MASK)
38659#define RDC_SEMAPHORE_GATE42_LDOM_MASK (0x30U)
38660#define RDC_SEMAPHORE_GATE42_LDOM_SHIFT (4U)
38661/*! LDOM
38662 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38663 * 0b01..The gate has been locked by domain 1.
38664 * 0b10..The gate has been locked by domain 2.
38665 * 0b11..The gate has been locked by domain 3.
38666 */
38667#define RDC_SEMAPHORE_GATE42_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE42_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE42_LDOM_MASK)
38668/*! @} */
38669
38670/*! @name GATE43 - Gate Register */
38671/*! @{ */
38672#define RDC_SEMAPHORE_GATE43_GTFSM_MASK (0xFU)
38673#define RDC_SEMAPHORE_GATE43_GTFSM_SHIFT (0U)
38674/*! GTFSM - Gate Finite State Machine.
38675 * 0b0000..The gate is unlocked (free).
38676 * 0b0001..The gate has been locked by processor with master_index = 0.
38677 * 0b0010..The gate has been locked by processor with master_index = 1.
38678 * 0b0011..The gate has been locked by processor with master_index = 2.
38679 * 0b0100..The gate has been locked by processor with master_index = 3.
38680 * 0b0101..The gate has been locked by processor with master_index = 4.
38681 * 0b0110..The gate has been locked by processor with master_index = 5.
38682 * 0b0111..The gate has been locked by processor with master_index = 6.
38683 * 0b1000..The gate has been locked by processor with master_index = 7.
38684 * 0b1001..The gate has been locked by processor with master_index = 8.
38685 * 0b1010..The gate has been locked by processor with master_index = 9.
38686 * 0b1011..The gate has been locked by processor with master_index = 10.
38687 * 0b1100..The gate has been locked by processor with master_index = 11.
38688 * 0b1101..The gate has been locked by processor with master_index = 12.
38689 * 0b1110..The gate has been locked by processor with master_index = 13.
38690 * 0b1111..The gate has been locked by processor with master_index = 14.
38691 */
38692#define RDC_SEMAPHORE_GATE43_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE43_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE43_GTFSM_MASK)
38693#define RDC_SEMAPHORE_GATE43_LDOM_MASK (0x30U)
38694#define RDC_SEMAPHORE_GATE43_LDOM_SHIFT (4U)
38695/*! LDOM
38696 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38697 * 0b01..The gate has been locked by domain 1.
38698 * 0b10..The gate has been locked by domain 2.
38699 * 0b11..The gate has been locked by domain 3.
38700 */
38701#define RDC_SEMAPHORE_GATE43_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE43_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE43_LDOM_MASK)
38702/*! @} */
38703
38704/*! @name GATE44 - Gate Register */
38705/*! @{ */
38706#define RDC_SEMAPHORE_GATE44_GTFSM_MASK (0xFU)
38707#define RDC_SEMAPHORE_GATE44_GTFSM_SHIFT (0U)
38708/*! GTFSM - Gate Finite State Machine.
38709 * 0b0000..The gate is unlocked (free).
38710 * 0b0001..The gate has been locked by processor with master_index = 0.
38711 * 0b0010..The gate has been locked by processor with master_index = 1.
38712 * 0b0011..The gate has been locked by processor with master_index = 2.
38713 * 0b0100..The gate has been locked by processor with master_index = 3.
38714 * 0b0101..The gate has been locked by processor with master_index = 4.
38715 * 0b0110..The gate has been locked by processor with master_index = 5.
38716 * 0b0111..The gate has been locked by processor with master_index = 6.
38717 * 0b1000..The gate has been locked by processor with master_index = 7.
38718 * 0b1001..The gate has been locked by processor with master_index = 8.
38719 * 0b1010..The gate has been locked by processor with master_index = 9.
38720 * 0b1011..The gate has been locked by processor with master_index = 10.
38721 * 0b1100..The gate has been locked by processor with master_index = 11.
38722 * 0b1101..The gate has been locked by processor with master_index = 12.
38723 * 0b1110..The gate has been locked by processor with master_index = 13.
38724 * 0b1111..The gate has been locked by processor with master_index = 14.
38725 */
38726#define RDC_SEMAPHORE_GATE44_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE44_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE44_GTFSM_MASK)
38727#define RDC_SEMAPHORE_GATE44_LDOM_MASK (0x30U)
38728#define RDC_SEMAPHORE_GATE44_LDOM_SHIFT (4U)
38729/*! LDOM
38730 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38731 * 0b01..The gate has been locked by domain 1.
38732 * 0b10..The gate has been locked by domain 2.
38733 * 0b11..The gate has been locked by domain 3.
38734 */
38735#define RDC_SEMAPHORE_GATE44_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE44_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE44_LDOM_MASK)
38736/*! @} */
38737
38738/*! @name GATE45 - Gate Register */
38739/*! @{ */
38740#define RDC_SEMAPHORE_GATE45_GTFSM_MASK (0xFU)
38741#define RDC_SEMAPHORE_GATE45_GTFSM_SHIFT (0U)
38742/*! GTFSM - Gate Finite State Machine.
38743 * 0b0000..The gate is unlocked (free).
38744 * 0b0001..The gate has been locked by processor with master_index = 0.
38745 * 0b0010..The gate has been locked by processor with master_index = 1.
38746 * 0b0011..The gate has been locked by processor with master_index = 2.
38747 * 0b0100..The gate has been locked by processor with master_index = 3.
38748 * 0b0101..The gate has been locked by processor with master_index = 4.
38749 * 0b0110..The gate has been locked by processor with master_index = 5.
38750 * 0b0111..The gate has been locked by processor with master_index = 6.
38751 * 0b1000..The gate has been locked by processor with master_index = 7.
38752 * 0b1001..The gate has been locked by processor with master_index = 8.
38753 * 0b1010..The gate has been locked by processor with master_index = 9.
38754 * 0b1011..The gate has been locked by processor with master_index = 10.
38755 * 0b1100..The gate has been locked by processor with master_index = 11.
38756 * 0b1101..The gate has been locked by processor with master_index = 12.
38757 * 0b1110..The gate has been locked by processor with master_index = 13.
38758 * 0b1111..The gate has been locked by processor with master_index = 14.
38759 */
38760#define RDC_SEMAPHORE_GATE45_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE45_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE45_GTFSM_MASK)
38761#define RDC_SEMAPHORE_GATE45_LDOM_MASK (0x30U)
38762#define RDC_SEMAPHORE_GATE45_LDOM_SHIFT (4U)
38763/*! LDOM
38764 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38765 * 0b01..The gate has been locked by domain 1.
38766 * 0b10..The gate has been locked by domain 2.
38767 * 0b11..The gate has been locked by domain 3.
38768 */
38769#define RDC_SEMAPHORE_GATE45_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE45_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE45_LDOM_MASK)
38770/*! @} */
38771
38772/*! @name GATE46 - Gate Register */
38773/*! @{ */
38774#define RDC_SEMAPHORE_GATE46_GTFSM_MASK (0xFU)
38775#define RDC_SEMAPHORE_GATE46_GTFSM_SHIFT (0U)
38776/*! GTFSM - Gate Finite State Machine.
38777 * 0b0000..The gate is unlocked (free).
38778 * 0b0001..The gate has been locked by processor with master_index = 0.
38779 * 0b0010..The gate has been locked by processor with master_index = 1.
38780 * 0b0011..The gate has been locked by processor with master_index = 2.
38781 * 0b0100..The gate has been locked by processor with master_index = 3.
38782 * 0b0101..The gate has been locked by processor with master_index = 4.
38783 * 0b0110..The gate has been locked by processor with master_index = 5.
38784 * 0b0111..The gate has been locked by processor with master_index = 6.
38785 * 0b1000..The gate has been locked by processor with master_index = 7.
38786 * 0b1001..The gate has been locked by processor with master_index = 8.
38787 * 0b1010..The gate has been locked by processor with master_index = 9.
38788 * 0b1011..The gate has been locked by processor with master_index = 10.
38789 * 0b1100..The gate has been locked by processor with master_index = 11.
38790 * 0b1101..The gate has been locked by processor with master_index = 12.
38791 * 0b1110..The gate has been locked by processor with master_index = 13.
38792 * 0b1111..The gate has been locked by processor with master_index = 14.
38793 */
38794#define RDC_SEMAPHORE_GATE46_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE46_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE46_GTFSM_MASK)
38795#define RDC_SEMAPHORE_GATE46_LDOM_MASK (0x30U)
38796#define RDC_SEMAPHORE_GATE46_LDOM_SHIFT (4U)
38797/*! LDOM
38798 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38799 * 0b01..The gate has been locked by domain 1.
38800 * 0b10..The gate has been locked by domain 2.
38801 * 0b11..The gate has been locked by domain 3.
38802 */
38803#define RDC_SEMAPHORE_GATE46_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE46_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE46_LDOM_MASK)
38804/*! @} */
38805
38806/*! @name GATE47 - Gate Register */
38807/*! @{ */
38808#define RDC_SEMAPHORE_GATE47_GTFSM_MASK (0xFU)
38809#define RDC_SEMAPHORE_GATE47_GTFSM_SHIFT (0U)
38810/*! GTFSM - Gate Finite State Machine.
38811 * 0b0000..The gate is unlocked (free).
38812 * 0b0001..The gate has been locked by processor with master_index = 0.
38813 * 0b0010..The gate has been locked by processor with master_index = 1.
38814 * 0b0011..The gate has been locked by processor with master_index = 2.
38815 * 0b0100..The gate has been locked by processor with master_index = 3.
38816 * 0b0101..The gate has been locked by processor with master_index = 4.
38817 * 0b0110..The gate has been locked by processor with master_index = 5.
38818 * 0b0111..The gate has been locked by processor with master_index = 6.
38819 * 0b1000..The gate has been locked by processor with master_index = 7.
38820 * 0b1001..The gate has been locked by processor with master_index = 8.
38821 * 0b1010..The gate has been locked by processor with master_index = 9.
38822 * 0b1011..The gate has been locked by processor with master_index = 10.
38823 * 0b1100..The gate has been locked by processor with master_index = 11.
38824 * 0b1101..The gate has been locked by processor with master_index = 12.
38825 * 0b1110..The gate has been locked by processor with master_index = 13.
38826 * 0b1111..The gate has been locked by processor with master_index = 14.
38827 */
38828#define RDC_SEMAPHORE_GATE47_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE47_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE47_GTFSM_MASK)
38829#define RDC_SEMAPHORE_GATE47_LDOM_MASK (0x30U)
38830#define RDC_SEMAPHORE_GATE47_LDOM_SHIFT (4U)
38831/*! LDOM
38832 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38833 * 0b01..The gate has been locked by domain 1.
38834 * 0b10..The gate has been locked by domain 2.
38835 * 0b11..The gate has been locked by domain 3.
38836 */
38837#define RDC_SEMAPHORE_GATE47_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE47_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE47_LDOM_MASK)
38838/*! @} */
38839
38840/*! @name GATE48 - Gate Register */
38841/*! @{ */
38842#define RDC_SEMAPHORE_GATE48_GTFSM_MASK (0xFU)
38843#define RDC_SEMAPHORE_GATE48_GTFSM_SHIFT (0U)
38844/*! GTFSM - Gate Finite State Machine.
38845 * 0b0000..The gate is unlocked (free).
38846 * 0b0001..The gate has been locked by processor with master_index = 0.
38847 * 0b0010..The gate has been locked by processor with master_index = 1.
38848 * 0b0011..The gate has been locked by processor with master_index = 2.
38849 * 0b0100..The gate has been locked by processor with master_index = 3.
38850 * 0b0101..The gate has been locked by processor with master_index = 4.
38851 * 0b0110..The gate has been locked by processor with master_index = 5.
38852 * 0b0111..The gate has been locked by processor with master_index = 6.
38853 * 0b1000..The gate has been locked by processor with master_index = 7.
38854 * 0b1001..The gate has been locked by processor with master_index = 8.
38855 * 0b1010..The gate has been locked by processor with master_index = 9.
38856 * 0b1011..The gate has been locked by processor with master_index = 10.
38857 * 0b1100..The gate has been locked by processor with master_index = 11.
38858 * 0b1101..The gate has been locked by processor with master_index = 12.
38859 * 0b1110..The gate has been locked by processor with master_index = 13.
38860 * 0b1111..The gate has been locked by processor with master_index = 14.
38861 */
38862#define RDC_SEMAPHORE_GATE48_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE48_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE48_GTFSM_MASK)
38863#define RDC_SEMAPHORE_GATE48_LDOM_MASK (0x30U)
38864#define RDC_SEMAPHORE_GATE48_LDOM_SHIFT (4U)
38865/*! LDOM
38866 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38867 * 0b01..The gate has been locked by domain 1.
38868 * 0b10..The gate has been locked by domain 2.
38869 * 0b11..The gate has been locked by domain 3.
38870 */
38871#define RDC_SEMAPHORE_GATE48_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE48_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE48_LDOM_MASK)
38872/*! @} */
38873
38874/*! @name GATE49 - Gate Register */
38875/*! @{ */
38876#define RDC_SEMAPHORE_GATE49_GTFSM_MASK (0xFU)
38877#define RDC_SEMAPHORE_GATE49_GTFSM_SHIFT (0U)
38878/*! GTFSM - Gate Finite State Machine.
38879 * 0b0000..The gate is unlocked (free).
38880 * 0b0001..The gate has been locked by processor with master_index = 0.
38881 * 0b0010..The gate has been locked by processor with master_index = 1.
38882 * 0b0011..The gate has been locked by processor with master_index = 2.
38883 * 0b0100..The gate has been locked by processor with master_index = 3.
38884 * 0b0101..The gate has been locked by processor with master_index = 4.
38885 * 0b0110..The gate has been locked by processor with master_index = 5.
38886 * 0b0111..The gate has been locked by processor with master_index = 6.
38887 * 0b1000..The gate has been locked by processor with master_index = 7.
38888 * 0b1001..The gate has been locked by processor with master_index = 8.
38889 * 0b1010..The gate has been locked by processor with master_index = 9.
38890 * 0b1011..The gate has been locked by processor with master_index = 10.
38891 * 0b1100..The gate has been locked by processor with master_index = 11.
38892 * 0b1101..The gate has been locked by processor with master_index = 12.
38893 * 0b1110..The gate has been locked by processor with master_index = 13.
38894 * 0b1111..The gate has been locked by processor with master_index = 14.
38895 */
38896#define RDC_SEMAPHORE_GATE49_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE49_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE49_GTFSM_MASK)
38897#define RDC_SEMAPHORE_GATE49_LDOM_MASK (0x30U)
38898#define RDC_SEMAPHORE_GATE49_LDOM_SHIFT (4U)
38899/*! LDOM
38900 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38901 * 0b01..The gate has been locked by domain 1.
38902 * 0b10..The gate has been locked by domain 2.
38903 * 0b11..The gate has been locked by domain 3.
38904 */
38905#define RDC_SEMAPHORE_GATE49_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE49_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE49_LDOM_MASK)
38906/*! @} */
38907
38908/*! @name GATE50 - Gate Register */
38909/*! @{ */
38910#define RDC_SEMAPHORE_GATE50_GTFSM_MASK (0xFU)
38911#define RDC_SEMAPHORE_GATE50_GTFSM_SHIFT (0U)
38912/*! GTFSM - Gate Finite State Machine.
38913 * 0b0000..The gate is unlocked (free).
38914 * 0b0001..The gate has been locked by processor with master_index = 0.
38915 * 0b0010..The gate has been locked by processor with master_index = 1.
38916 * 0b0011..The gate has been locked by processor with master_index = 2.
38917 * 0b0100..The gate has been locked by processor with master_index = 3.
38918 * 0b0101..The gate has been locked by processor with master_index = 4.
38919 * 0b0110..The gate has been locked by processor with master_index = 5.
38920 * 0b0111..The gate has been locked by processor with master_index = 6.
38921 * 0b1000..The gate has been locked by processor with master_index = 7.
38922 * 0b1001..The gate has been locked by processor with master_index = 8.
38923 * 0b1010..The gate has been locked by processor with master_index = 9.
38924 * 0b1011..The gate has been locked by processor with master_index = 10.
38925 * 0b1100..The gate has been locked by processor with master_index = 11.
38926 * 0b1101..The gate has been locked by processor with master_index = 12.
38927 * 0b1110..The gate has been locked by processor with master_index = 13.
38928 * 0b1111..The gate has been locked by processor with master_index = 14.
38929 */
38930#define RDC_SEMAPHORE_GATE50_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE50_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE50_GTFSM_MASK)
38931#define RDC_SEMAPHORE_GATE50_LDOM_MASK (0x30U)
38932#define RDC_SEMAPHORE_GATE50_LDOM_SHIFT (4U)
38933/*! LDOM
38934 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38935 * 0b01..The gate has been locked by domain 1.
38936 * 0b10..The gate has been locked by domain 2.
38937 * 0b11..The gate has been locked by domain 3.
38938 */
38939#define RDC_SEMAPHORE_GATE50_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE50_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE50_LDOM_MASK)
38940/*! @} */
38941
38942/*! @name GATE51 - Gate Register */
38943/*! @{ */
38944#define RDC_SEMAPHORE_GATE51_GTFSM_MASK (0xFU)
38945#define RDC_SEMAPHORE_GATE51_GTFSM_SHIFT (0U)
38946/*! GTFSM - Gate Finite State Machine.
38947 * 0b0000..The gate is unlocked (free).
38948 * 0b0001..The gate has been locked by processor with master_index = 0.
38949 * 0b0010..The gate has been locked by processor with master_index = 1.
38950 * 0b0011..The gate has been locked by processor with master_index = 2.
38951 * 0b0100..The gate has been locked by processor with master_index = 3.
38952 * 0b0101..The gate has been locked by processor with master_index = 4.
38953 * 0b0110..The gate has been locked by processor with master_index = 5.
38954 * 0b0111..The gate has been locked by processor with master_index = 6.
38955 * 0b1000..The gate has been locked by processor with master_index = 7.
38956 * 0b1001..The gate has been locked by processor with master_index = 8.
38957 * 0b1010..The gate has been locked by processor with master_index = 9.
38958 * 0b1011..The gate has been locked by processor with master_index = 10.
38959 * 0b1100..The gate has been locked by processor with master_index = 11.
38960 * 0b1101..The gate has been locked by processor with master_index = 12.
38961 * 0b1110..The gate has been locked by processor with master_index = 13.
38962 * 0b1111..The gate has been locked by processor with master_index = 14.
38963 */
38964#define RDC_SEMAPHORE_GATE51_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE51_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE51_GTFSM_MASK)
38965#define RDC_SEMAPHORE_GATE51_LDOM_MASK (0x30U)
38966#define RDC_SEMAPHORE_GATE51_LDOM_SHIFT (4U)
38967/*! LDOM
38968 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
38969 * 0b01..The gate has been locked by domain 1.
38970 * 0b10..The gate has been locked by domain 2.
38971 * 0b11..The gate has been locked by domain 3.
38972 */
38973#define RDC_SEMAPHORE_GATE51_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE51_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE51_LDOM_MASK)
38974/*! @} */
38975
38976/*! @name GATE52 - Gate Register */
38977/*! @{ */
38978#define RDC_SEMAPHORE_GATE52_GTFSM_MASK (0xFU)
38979#define RDC_SEMAPHORE_GATE52_GTFSM_SHIFT (0U)
38980/*! GTFSM - Gate Finite State Machine.
38981 * 0b0000..The gate is unlocked (free).
38982 * 0b0001..The gate has been locked by processor with master_index = 0.
38983 * 0b0010..The gate has been locked by processor with master_index = 1.
38984 * 0b0011..The gate has been locked by processor with master_index = 2.
38985 * 0b0100..The gate has been locked by processor with master_index = 3.
38986 * 0b0101..The gate has been locked by processor with master_index = 4.
38987 * 0b0110..The gate has been locked by processor with master_index = 5.
38988 * 0b0111..The gate has been locked by processor with master_index = 6.
38989 * 0b1000..The gate has been locked by processor with master_index = 7.
38990 * 0b1001..The gate has been locked by processor with master_index = 8.
38991 * 0b1010..The gate has been locked by processor with master_index = 9.
38992 * 0b1011..The gate has been locked by processor with master_index = 10.
38993 * 0b1100..The gate has been locked by processor with master_index = 11.
38994 * 0b1101..The gate has been locked by processor with master_index = 12.
38995 * 0b1110..The gate has been locked by processor with master_index = 13.
38996 * 0b1111..The gate has been locked by processor with master_index = 14.
38997 */
38998#define RDC_SEMAPHORE_GATE52_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE52_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE52_GTFSM_MASK)
38999#define RDC_SEMAPHORE_GATE52_LDOM_MASK (0x30U)
39000#define RDC_SEMAPHORE_GATE52_LDOM_SHIFT (4U)
39001/*! LDOM
39002 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
39003 * 0b01..The gate has been locked by domain 1.
39004 * 0b10..The gate has been locked by domain 2.
39005 * 0b11..The gate has been locked by domain 3.
39006 */
39007#define RDC_SEMAPHORE_GATE52_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE52_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE52_LDOM_MASK)
39008/*! @} */
39009
39010/*! @name GATE53 - Gate Register */
39011/*! @{ */
39012#define RDC_SEMAPHORE_GATE53_GTFSM_MASK (0xFU)
39013#define RDC_SEMAPHORE_GATE53_GTFSM_SHIFT (0U)
39014/*! GTFSM - Gate Finite State Machine.
39015 * 0b0000..The gate is unlocked (free).
39016 * 0b0001..The gate has been locked by processor with master_index = 0.
39017 * 0b0010..The gate has been locked by processor with master_index = 1.
39018 * 0b0011..The gate has been locked by processor with master_index = 2.
39019 * 0b0100..The gate has been locked by processor with master_index = 3.
39020 * 0b0101..The gate has been locked by processor with master_index = 4.
39021 * 0b0110..The gate has been locked by processor with master_index = 5.
39022 * 0b0111..The gate has been locked by processor with master_index = 6.
39023 * 0b1000..The gate has been locked by processor with master_index = 7.
39024 * 0b1001..The gate has been locked by processor with master_index = 8.
39025 * 0b1010..The gate has been locked by processor with master_index = 9.
39026 * 0b1011..The gate has been locked by processor with master_index = 10.
39027 * 0b1100..The gate has been locked by processor with master_index = 11.
39028 * 0b1101..The gate has been locked by processor with master_index = 12.
39029 * 0b1110..The gate has been locked by processor with master_index = 13.
39030 * 0b1111..The gate has been locked by processor with master_index = 14.
39031 */
39032#define RDC_SEMAPHORE_GATE53_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE53_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE53_GTFSM_MASK)
39033#define RDC_SEMAPHORE_GATE53_LDOM_MASK (0x30U)
39034#define RDC_SEMAPHORE_GATE53_LDOM_SHIFT (4U)
39035/*! LDOM
39036 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
39037 * 0b01..The gate has been locked by domain 1.
39038 * 0b10..The gate has been locked by domain 2.
39039 * 0b11..The gate has been locked by domain 3.
39040 */
39041#define RDC_SEMAPHORE_GATE53_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE53_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE53_LDOM_MASK)
39042/*! @} */
39043
39044/*! @name GATE54 - Gate Register */
39045/*! @{ */
39046#define RDC_SEMAPHORE_GATE54_GTFSM_MASK (0xFU)
39047#define RDC_SEMAPHORE_GATE54_GTFSM_SHIFT (0U)
39048/*! GTFSM - Gate Finite State Machine.
39049 * 0b0000..The gate is unlocked (free).
39050 * 0b0001..The gate has been locked by processor with master_index = 0.
39051 * 0b0010..The gate has been locked by processor with master_index = 1.
39052 * 0b0011..The gate has been locked by processor with master_index = 2.
39053 * 0b0100..The gate has been locked by processor with master_index = 3.
39054 * 0b0101..The gate has been locked by processor with master_index = 4.
39055 * 0b0110..The gate has been locked by processor with master_index = 5.
39056 * 0b0111..The gate has been locked by processor with master_index = 6.
39057 * 0b1000..The gate has been locked by processor with master_index = 7.
39058 * 0b1001..The gate has been locked by processor with master_index = 8.
39059 * 0b1010..The gate has been locked by processor with master_index = 9.
39060 * 0b1011..The gate has been locked by processor with master_index = 10.
39061 * 0b1100..The gate has been locked by processor with master_index = 11.
39062 * 0b1101..The gate has been locked by processor with master_index = 12.
39063 * 0b1110..The gate has been locked by processor with master_index = 13.
39064 * 0b1111..The gate has been locked by processor with master_index = 14.
39065 */
39066#define RDC_SEMAPHORE_GATE54_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE54_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE54_GTFSM_MASK)
39067#define RDC_SEMAPHORE_GATE54_LDOM_MASK (0x30U)
39068#define RDC_SEMAPHORE_GATE54_LDOM_SHIFT (4U)
39069/*! LDOM
39070 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
39071 * 0b01..The gate has been locked by domain 1.
39072 * 0b10..The gate has been locked by domain 2.
39073 * 0b11..The gate has been locked by domain 3.
39074 */
39075#define RDC_SEMAPHORE_GATE54_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE54_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE54_LDOM_MASK)
39076/*! @} */
39077
39078/*! @name GATE55 - Gate Register */
39079/*! @{ */
39080#define RDC_SEMAPHORE_GATE55_GTFSM_MASK (0xFU)
39081#define RDC_SEMAPHORE_GATE55_GTFSM_SHIFT (0U)
39082/*! GTFSM - Gate Finite State Machine.
39083 * 0b0000..The gate is unlocked (free).
39084 * 0b0001..The gate has been locked by processor with master_index = 0.
39085 * 0b0010..The gate has been locked by processor with master_index = 1.
39086 * 0b0011..The gate has been locked by processor with master_index = 2.
39087 * 0b0100..The gate has been locked by processor with master_index = 3.
39088 * 0b0101..The gate has been locked by processor with master_index = 4.
39089 * 0b0110..The gate has been locked by processor with master_index = 5.
39090 * 0b0111..The gate has been locked by processor with master_index = 6.
39091 * 0b1000..The gate has been locked by processor with master_index = 7.
39092 * 0b1001..The gate has been locked by processor with master_index = 8.
39093 * 0b1010..The gate has been locked by processor with master_index = 9.
39094 * 0b1011..The gate has been locked by processor with master_index = 10.
39095 * 0b1100..The gate has been locked by processor with master_index = 11.
39096 * 0b1101..The gate has been locked by processor with master_index = 12.
39097 * 0b1110..The gate has been locked by processor with master_index = 13.
39098 * 0b1111..The gate has been locked by processor with master_index = 14.
39099 */
39100#define RDC_SEMAPHORE_GATE55_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE55_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE55_GTFSM_MASK)
39101#define RDC_SEMAPHORE_GATE55_LDOM_MASK (0x30U)
39102#define RDC_SEMAPHORE_GATE55_LDOM_SHIFT (4U)
39103/*! LDOM
39104 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
39105 * 0b01..The gate has been locked by domain 1.
39106 * 0b10..The gate has been locked by domain 2.
39107 * 0b11..The gate has been locked by domain 3.
39108 */
39109#define RDC_SEMAPHORE_GATE55_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE55_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE55_LDOM_MASK)
39110/*! @} */
39111
39112/*! @name GATE56 - Gate Register */
39113/*! @{ */
39114#define RDC_SEMAPHORE_GATE56_GTFSM_MASK (0xFU)
39115#define RDC_SEMAPHORE_GATE56_GTFSM_SHIFT (0U)
39116/*! GTFSM - Gate Finite State Machine.
39117 * 0b0000..The gate is unlocked (free).
39118 * 0b0001..The gate has been locked by processor with master_index = 0.
39119 * 0b0010..The gate has been locked by processor with master_index = 1.
39120 * 0b0011..The gate has been locked by processor with master_index = 2.
39121 * 0b0100..The gate has been locked by processor with master_index = 3.
39122 * 0b0101..The gate has been locked by processor with master_index = 4.
39123 * 0b0110..The gate has been locked by processor with master_index = 5.
39124 * 0b0111..The gate has been locked by processor with master_index = 6.
39125 * 0b1000..The gate has been locked by processor with master_index = 7.
39126 * 0b1001..The gate has been locked by processor with master_index = 8.
39127 * 0b1010..The gate has been locked by processor with master_index = 9.
39128 * 0b1011..The gate has been locked by processor with master_index = 10.
39129 * 0b1100..The gate has been locked by processor with master_index = 11.
39130 * 0b1101..The gate has been locked by processor with master_index = 12.
39131 * 0b1110..The gate has been locked by processor with master_index = 13.
39132 * 0b1111..The gate has been locked by processor with master_index = 14.
39133 */
39134#define RDC_SEMAPHORE_GATE56_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE56_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE56_GTFSM_MASK)
39135#define RDC_SEMAPHORE_GATE56_LDOM_MASK (0x30U)
39136#define RDC_SEMAPHORE_GATE56_LDOM_SHIFT (4U)
39137/*! LDOM
39138 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
39139 * 0b01..The gate has been locked by domain 1.
39140 * 0b10..The gate has been locked by domain 2.
39141 * 0b11..The gate has been locked by domain 3.
39142 */
39143#define RDC_SEMAPHORE_GATE56_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE56_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE56_LDOM_MASK)
39144/*! @} */
39145
39146/*! @name GATE57 - Gate Register */
39147/*! @{ */
39148#define RDC_SEMAPHORE_GATE57_GTFSM_MASK (0xFU)
39149#define RDC_SEMAPHORE_GATE57_GTFSM_SHIFT (0U)
39150/*! GTFSM - Gate Finite State Machine.
39151 * 0b0000..The gate is unlocked (free).
39152 * 0b0001..The gate has been locked by processor with master_index = 0.
39153 * 0b0010..The gate has been locked by processor with master_index = 1.
39154 * 0b0011..The gate has been locked by processor with master_index = 2.
39155 * 0b0100..The gate has been locked by processor with master_index = 3.
39156 * 0b0101..The gate has been locked by processor with master_index = 4.
39157 * 0b0110..The gate has been locked by processor with master_index = 5.
39158 * 0b0111..The gate has been locked by processor with master_index = 6.
39159 * 0b1000..The gate has been locked by processor with master_index = 7.
39160 * 0b1001..The gate has been locked by processor with master_index = 8.
39161 * 0b1010..The gate has been locked by processor with master_index = 9.
39162 * 0b1011..The gate has been locked by processor with master_index = 10.
39163 * 0b1100..The gate has been locked by processor with master_index = 11.
39164 * 0b1101..The gate has been locked by processor with master_index = 12.
39165 * 0b1110..The gate has been locked by processor with master_index = 13.
39166 * 0b1111..The gate has been locked by processor with master_index = 14.
39167 */
39168#define RDC_SEMAPHORE_GATE57_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE57_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE57_GTFSM_MASK)
39169#define RDC_SEMAPHORE_GATE57_LDOM_MASK (0x30U)
39170#define RDC_SEMAPHORE_GATE57_LDOM_SHIFT (4U)
39171/*! LDOM
39172 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
39173 * 0b01..The gate has been locked by domain 1.
39174 * 0b10..The gate has been locked by domain 2.
39175 * 0b11..The gate has been locked by domain 3.
39176 */
39177#define RDC_SEMAPHORE_GATE57_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE57_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE57_LDOM_MASK)
39178/*! @} */
39179
39180/*! @name GATE58 - Gate Register */
39181/*! @{ */
39182#define RDC_SEMAPHORE_GATE58_GTFSM_MASK (0xFU)
39183#define RDC_SEMAPHORE_GATE58_GTFSM_SHIFT (0U)
39184/*! GTFSM - Gate Finite State Machine.
39185 * 0b0000..The gate is unlocked (free).
39186 * 0b0001..The gate has been locked by processor with master_index = 0.
39187 * 0b0010..The gate has been locked by processor with master_index = 1.
39188 * 0b0011..The gate has been locked by processor with master_index = 2.
39189 * 0b0100..The gate has been locked by processor with master_index = 3.
39190 * 0b0101..The gate has been locked by processor with master_index = 4.
39191 * 0b0110..The gate has been locked by processor with master_index = 5.
39192 * 0b0111..The gate has been locked by processor with master_index = 6.
39193 * 0b1000..The gate has been locked by processor with master_index = 7.
39194 * 0b1001..The gate has been locked by processor with master_index = 8.
39195 * 0b1010..The gate has been locked by processor with master_index = 9.
39196 * 0b1011..The gate has been locked by processor with master_index = 10.
39197 * 0b1100..The gate has been locked by processor with master_index = 11.
39198 * 0b1101..The gate has been locked by processor with master_index = 12.
39199 * 0b1110..The gate has been locked by processor with master_index = 13.
39200 * 0b1111..The gate has been locked by processor with master_index = 14.
39201 */
39202#define RDC_SEMAPHORE_GATE58_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE58_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE58_GTFSM_MASK)
39203#define RDC_SEMAPHORE_GATE58_LDOM_MASK (0x30U)
39204#define RDC_SEMAPHORE_GATE58_LDOM_SHIFT (4U)
39205/*! LDOM
39206 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
39207 * 0b01..The gate has been locked by domain 1.
39208 * 0b10..The gate has been locked by domain 2.
39209 * 0b11..The gate has been locked by domain 3.
39210 */
39211#define RDC_SEMAPHORE_GATE58_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE58_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE58_LDOM_MASK)
39212/*! @} */
39213
39214/*! @name GATE59 - Gate Register */
39215/*! @{ */
39216#define RDC_SEMAPHORE_GATE59_GTFSM_MASK (0xFU)
39217#define RDC_SEMAPHORE_GATE59_GTFSM_SHIFT (0U)
39218/*! GTFSM - Gate Finite State Machine.
39219 * 0b0000..The gate is unlocked (free).
39220 * 0b0001..The gate has been locked by processor with master_index = 0.
39221 * 0b0010..The gate has been locked by processor with master_index = 1.
39222 * 0b0011..The gate has been locked by processor with master_index = 2.
39223 * 0b0100..The gate has been locked by processor with master_index = 3.
39224 * 0b0101..The gate has been locked by processor with master_index = 4.
39225 * 0b0110..The gate has been locked by processor with master_index = 5.
39226 * 0b0111..The gate has been locked by processor with master_index = 6.
39227 * 0b1000..The gate has been locked by processor with master_index = 7.
39228 * 0b1001..The gate has been locked by processor with master_index = 8.
39229 * 0b1010..The gate has been locked by processor with master_index = 9.
39230 * 0b1011..The gate has been locked by processor with master_index = 10.
39231 * 0b1100..The gate has been locked by processor with master_index = 11.
39232 * 0b1101..The gate has been locked by processor with master_index = 12.
39233 * 0b1110..The gate has been locked by processor with master_index = 13.
39234 * 0b1111..The gate has been locked by processor with master_index = 14.
39235 */
39236#define RDC_SEMAPHORE_GATE59_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE59_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE59_GTFSM_MASK)
39237#define RDC_SEMAPHORE_GATE59_LDOM_MASK (0x30U)
39238#define RDC_SEMAPHORE_GATE59_LDOM_SHIFT (4U)
39239/*! LDOM
39240 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
39241 * 0b01..The gate has been locked by domain 1.
39242 * 0b10..The gate has been locked by domain 2.
39243 * 0b11..The gate has been locked by domain 3.
39244 */
39245#define RDC_SEMAPHORE_GATE59_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE59_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE59_LDOM_MASK)
39246/*! @} */
39247
39248/*! @name GATE60 - Gate Register */
39249/*! @{ */
39250#define RDC_SEMAPHORE_GATE60_GTFSM_MASK (0xFU)
39251#define RDC_SEMAPHORE_GATE60_GTFSM_SHIFT (0U)
39252/*! GTFSM - Gate Finite State Machine.
39253 * 0b0000..The gate is unlocked (free).
39254 * 0b0001..The gate has been locked by processor with master_index = 0.
39255 * 0b0010..The gate has been locked by processor with master_index = 1.
39256 * 0b0011..The gate has been locked by processor with master_index = 2.
39257 * 0b0100..The gate has been locked by processor with master_index = 3.
39258 * 0b0101..The gate has been locked by processor with master_index = 4.
39259 * 0b0110..The gate has been locked by processor with master_index = 5.
39260 * 0b0111..The gate has been locked by processor with master_index = 6.
39261 * 0b1000..The gate has been locked by processor with master_index = 7.
39262 * 0b1001..The gate has been locked by processor with master_index = 8.
39263 * 0b1010..The gate has been locked by processor with master_index = 9.
39264 * 0b1011..The gate has been locked by processor with master_index = 10.
39265 * 0b1100..The gate has been locked by processor with master_index = 11.
39266 * 0b1101..The gate has been locked by processor with master_index = 12.
39267 * 0b1110..The gate has been locked by processor with master_index = 13.
39268 * 0b1111..The gate has been locked by processor with master_index = 14.
39269 */
39270#define RDC_SEMAPHORE_GATE60_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE60_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE60_GTFSM_MASK)
39271#define RDC_SEMAPHORE_GATE60_LDOM_MASK (0x30U)
39272#define RDC_SEMAPHORE_GATE60_LDOM_SHIFT (4U)
39273/*! LDOM
39274 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
39275 * 0b01..The gate has been locked by domain 1.
39276 * 0b10..The gate has been locked by domain 2.
39277 * 0b11..The gate has been locked by domain 3.
39278 */
39279#define RDC_SEMAPHORE_GATE60_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE60_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE60_LDOM_MASK)
39280/*! @} */
39281
39282/*! @name GATE61 - Gate Register */
39283/*! @{ */
39284#define RDC_SEMAPHORE_GATE61_GTFSM_MASK (0xFU)
39285#define RDC_SEMAPHORE_GATE61_GTFSM_SHIFT (0U)
39286/*! GTFSM - Gate Finite State Machine.
39287 * 0b0000..The gate is unlocked (free).
39288 * 0b0001..The gate has been locked by processor with master_index = 0.
39289 * 0b0010..The gate has been locked by processor with master_index = 1.
39290 * 0b0011..The gate has been locked by processor with master_index = 2.
39291 * 0b0100..The gate has been locked by processor with master_index = 3.
39292 * 0b0101..The gate has been locked by processor with master_index = 4.
39293 * 0b0110..The gate has been locked by processor with master_index = 5.
39294 * 0b0111..The gate has been locked by processor with master_index = 6.
39295 * 0b1000..The gate has been locked by processor with master_index = 7.
39296 * 0b1001..The gate has been locked by processor with master_index = 8.
39297 * 0b1010..The gate has been locked by processor with master_index = 9.
39298 * 0b1011..The gate has been locked by processor with master_index = 10.
39299 * 0b1100..The gate has been locked by processor with master_index = 11.
39300 * 0b1101..The gate has been locked by processor with master_index = 12.
39301 * 0b1110..The gate has been locked by processor with master_index = 13.
39302 * 0b1111..The gate has been locked by processor with master_index = 14.
39303 */
39304#define RDC_SEMAPHORE_GATE61_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE61_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE61_GTFSM_MASK)
39305#define RDC_SEMAPHORE_GATE61_LDOM_MASK (0x30U)
39306#define RDC_SEMAPHORE_GATE61_LDOM_SHIFT (4U)
39307/*! LDOM
39308 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
39309 * 0b01..The gate has been locked by domain 1.
39310 * 0b10..The gate has been locked by domain 2.
39311 * 0b11..The gate has been locked by domain 3.
39312 */
39313#define RDC_SEMAPHORE_GATE61_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE61_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE61_LDOM_MASK)
39314/*! @} */
39315
39316/*! @name GATE62 - Gate Register */
39317/*! @{ */
39318#define RDC_SEMAPHORE_GATE62_GTFSM_MASK (0xFU)
39319#define RDC_SEMAPHORE_GATE62_GTFSM_SHIFT (0U)
39320/*! GTFSM - Gate Finite State Machine.
39321 * 0b0000..The gate is unlocked (free).
39322 * 0b0001..The gate has been locked by processor with master_index = 0.
39323 * 0b0010..The gate has been locked by processor with master_index = 1.
39324 * 0b0011..The gate has been locked by processor with master_index = 2.
39325 * 0b0100..The gate has been locked by processor with master_index = 3.
39326 * 0b0101..The gate has been locked by processor with master_index = 4.
39327 * 0b0110..The gate has been locked by processor with master_index = 5.
39328 * 0b0111..The gate has been locked by processor with master_index = 6.
39329 * 0b1000..The gate has been locked by processor with master_index = 7.
39330 * 0b1001..The gate has been locked by processor with master_index = 8.
39331 * 0b1010..The gate has been locked by processor with master_index = 9.
39332 * 0b1011..The gate has been locked by processor with master_index = 10.
39333 * 0b1100..The gate has been locked by processor with master_index = 11.
39334 * 0b1101..The gate has been locked by processor with master_index = 12.
39335 * 0b1110..The gate has been locked by processor with master_index = 13.
39336 * 0b1111..The gate has been locked by processor with master_index = 14.
39337 */
39338#define RDC_SEMAPHORE_GATE62_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE62_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE62_GTFSM_MASK)
39339#define RDC_SEMAPHORE_GATE62_LDOM_MASK (0x30U)
39340#define RDC_SEMAPHORE_GATE62_LDOM_SHIFT (4U)
39341/*! LDOM
39342 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
39343 * 0b01..The gate has been locked by domain 1.
39344 * 0b10..The gate has been locked by domain 2.
39345 * 0b11..The gate has been locked by domain 3.
39346 */
39347#define RDC_SEMAPHORE_GATE62_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE62_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE62_LDOM_MASK)
39348/*! @} */
39349
39350/*! @name GATE63 - Gate Register */
39351/*! @{ */
39352#define RDC_SEMAPHORE_GATE63_GTFSM_MASK (0xFU)
39353#define RDC_SEMAPHORE_GATE63_GTFSM_SHIFT (0U)
39354/*! GTFSM - Gate Finite State Machine.
39355 * 0b0000..The gate is unlocked (free).
39356 * 0b0001..The gate has been locked by processor with master_index = 0.
39357 * 0b0010..The gate has been locked by processor with master_index = 1.
39358 * 0b0011..The gate has been locked by processor with master_index = 2.
39359 * 0b0100..The gate has been locked by processor with master_index = 3.
39360 * 0b0101..The gate has been locked by processor with master_index = 4.
39361 * 0b0110..The gate has been locked by processor with master_index = 5.
39362 * 0b0111..The gate has been locked by processor with master_index = 6.
39363 * 0b1000..The gate has been locked by processor with master_index = 7.
39364 * 0b1001..The gate has been locked by processor with master_index = 8.
39365 * 0b1010..The gate has been locked by processor with master_index = 9.
39366 * 0b1011..The gate has been locked by processor with master_index = 10.
39367 * 0b1100..The gate has been locked by processor with master_index = 11.
39368 * 0b1101..The gate has been locked by processor with master_index = 12.
39369 * 0b1110..The gate has been locked by processor with master_index = 13.
39370 * 0b1111..The gate has been locked by processor with master_index = 14.
39371 */
39372#define RDC_SEMAPHORE_GATE63_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE63_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE63_GTFSM_MASK)
39373#define RDC_SEMAPHORE_GATE63_LDOM_MASK (0x30U)
39374#define RDC_SEMAPHORE_GATE63_LDOM_SHIFT (4U)
39375/*! LDOM
39376 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
39377 * 0b01..The gate has been locked by domain 1.
39378 * 0b10..The gate has been locked by domain 2.
39379 * 0b11..The gate has been locked by domain 3.
39380 */
39381#define RDC_SEMAPHORE_GATE63_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE63_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE63_LDOM_MASK)
39382/*! @} */
39383
39384/*! @name RSTGT_R - Reset Gate Read */
39385/*! @{ */
39386#define RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK (0xFU)
39387#define RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT (0U)
39388#define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK)
39389#define RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK (0x30U)
39390#define RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT (4U)
39391/*! RSTGSM
39392 * 0b00..Idle, waiting for the first data pattern write.
39393 * 0b01..Waiting for the second data pattern write.
39394 * 0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists for only one clock cycle. Software will never be able to observe this state.
39395 * 0b11..This state encoding is never used and therefore reserved.
39396 */
39397#define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK)
39398#define RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK (0xFF00U)
39399#define RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT (8U)
39400#define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK)
39401/*! @} */
39402
39403/*! @name RSTGT_W - Reset Gate Write */
39404/*! @{ */
39405#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK (0xFFU)
39406#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT (0U)
39407#define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK)
39408#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK (0xFF00U)
39409#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT (8U)
39410#define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK)
39411/*! @} */
39412
39413
39414/*!
39415 * @}
39416 */ /* end of group RDC_SEMAPHORE_Register_Masks */
39417
39418
39419/* RDC_SEMAPHORE - Peripheral instance base addresses */
39420/** Peripheral RDC_SEMAPHORE1 base address */
39421#define RDC_SEMAPHORE1_BASE (0x303B0000u)
39422/** Peripheral RDC_SEMAPHORE1 base pointer */
39423#define RDC_SEMAPHORE1 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE1_BASE)
39424/** Peripheral RDC_SEMAPHORE2 base address */
39425#define RDC_SEMAPHORE2_BASE (0x303C0000u)
39426/** Peripheral RDC_SEMAPHORE2 base pointer */
39427#define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
39428/** Array initializer of RDC_SEMAPHORE peripheral base addresses */
39429#define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
39430/** Array initializer of RDC_SEMAPHORE peripheral base pointers */
39431#define RDC_SEMAPHORE_BASE_PTRS { (RDC_SEMAPHORE_Type *)0u, RDC_SEMAPHORE1, RDC_SEMAPHORE2 }
39432
39433/*!
39434 * @}
39435 */ /* end of group RDC_SEMAPHORE_Peripheral_Access_Layer */
39436
39437
39438/* ----------------------------------------------------------------------------
39439 -- RD_SRC Peripheral Access Layer
39440 ---------------------------------------------------------------------------- */
39441
39442/*!
39443 * @addtogroup RD_SRC_Peripheral_Access_Layer RD_SRC Peripheral Access Layer
39444 * @{
39445 */
39446
39447/** RD_SRC - Register Layout Typedef */
39448typedef struct {
39449 struct { /* offset: 0x0 */
39450 __IO uint32_t RW; /**< Control register for Read surface., offset: 0x0 */
39451 __IO uint32_t SET; /**< Control register for Read surface., offset: 0x4 */
39452 __IO uint32_t CLR; /**< Control register for Read surface., offset: 0x8 */
39453 __IO uint32_t TOG; /**< Control register for Read surface., offset: 0xC */
39454 } CTRL_STATUS;
39455 __IO uint32_t BASE_ADDR; /**< Read Surface Base address, offset: 0x10 */
39456 __IO uint32_t PITCH; /**< Read surface vertical pitch, offset: 0x14 */
39457 __IO uint32_t WIDTH; /**< Source frame buffer width, offset: 0x18 */
39458 __IO uint32_t HEIGHT; /**< Height of frame to be read, offset: 0x1C */
39459} RD_SRC_Type;
39460
39461/* ----------------------------------------------------------------------------
39462 -- RD_SRC Register Masks
39463 ---------------------------------------------------------------------------- */
39464
39465/*!
39466 * @addtogroup RD_SRC_Register_Masks RD_SRC Register Masks
39467 * @{
39468 */
39469
39470/*! @name CTRL_STATUS - Control register for Read surface. */
39471/*! @{ */
39472#define RD_SRC_CTRL_STATUS_ENABLE_MASK (0x1U)
39473#define RD_SRC_CTRL_STATUS_ENABLE_SHIFT (0U)
39474#define RD_SRC_CTRL_STATUS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_ENABLE_SHIFT)) & RD_SRC_CTRL_STATUS_ENABLE_MASK)
39475#define RD_SRC_CTRL_STATUS_BPP_MASK (0x1CU)
39476#define RD_SRC_CTRL_STATUS_BPP_SHIFT (2U)
39477#define RD_SRC_CTRL_STATUS_BPP(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_BPP_SHIFT)) & RD_SRC_CTRL_STATUS_BPP_MASK)
39478#define RD_SRC_CTRL_STATUS_T_SIZE_MASK (0x60U)
39479#define RD_SRC_CTRL_STATUS_T_SIZE_SHIFT (5U)
39480#define RD_SRC_CTRL_STATUS_T_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_T_SIZE_SHIFT)) & RD_SRC_CTRL_STATUS_T_SIZE_MASK)
39481#define RD_SRC_CTRL_STATUS_P_SIZE_MASK (0x380U)
39482#define RD_SRC_CTRL_STATUS_P_SIZE_SHIFT (7U)
39483#define RD_SRC_CTRL_STATUS_P_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_P_SIZE_SHIFT)) & RD_SRC_CTRL_STATUS_P_SIZE_MASK)
39484#define RD_SRC_CTRL_STATUS_FRAME_COMP_EN_MASK (0x4000U)
39485#define RD_SRC_CTRL_STATUS_FRAME_COMP_EN_SHIFT (14U)
39486#define RD_SRC_CTRL_STATUS_FRAME_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_FRAME_COMP_EN_SHIFT)) & RD_SRC_CTRL_STATUS_FRAME_COMP_EN_MASK)
39487#define RD_SRC_CTRL_STATUS_RD_ERR_EN_MASK (0x8000U)
39488#define RD_SRC_CTRL_STATUS_RD_ERR_EN_SHIFT (15U)
39489#define RD_SRC_CTRL_STATUS_RD_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_RD_ERR_EN_SHIFT)) & RD_SRC_CTRL_STATUS_RD_ERR_EN_MASK)
39490#define RD_SRC_CTRL_STATUS_FIFO_SIZE_MASK (0x7F0000U)
39491#define RD_SRC_CTRL_STATUS_FIFO_SIZE_SHIFT (16U)
39492#define RD_SRC_CTRL_STATUS_FIFO_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_FIFO_SIZE_SHIFT)) & RD_SRC_CTRL_STATUS_FIFO_SIZE_MASK)
39493#define RD_SRC_CTRL_STATUS_FRAME_COMP_MASK (0x40000000U)
39494#define RD_SRC_CTRL_STATUS_FRAME_COMP_SHIFT (30U)
39495#define RD_SRC_CTRL_STATUS_FRAME_COMP(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_FRAME_COMP_SHIFT)) & RD_SRC_CTRL_STATUS_FRAME_COMP_MASK)
39496#define RD_SRC_CTRL_STATUS_RD_ERR_MASK (0x80000000U)
39497#define RD_SRC_CTRL_STATUS_RD_ERR_SHIFT (31U)
39498#define RD_SRC_CTRL_STATUS_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_RD_ERR_SHIFT)) & RD_SRC_CTRL_STATUS_RD_ERR_MASK)
39499/*! @} */
39500
39501/*! @name BASE_ADDR - Read Surface Base address */
39502/*! @{ */
39503#define RD_SRC_BASE_ADDR_BASE_ADDR_MASK (0xFFFFFFFFU)
39504#define RD_SRC_BASE_ADDR_BASE_ADDR_SHIFT (0U)
39505#define RD_SRC_BASE_ADDR_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_BASE_ADDR_BASE_ADDR_SHIFT)) & RD_SRC_BASE_ADDR_BASE_ADDR_MASK)
39506/*! @} */
39507
39508/*! @name PITCH - Read surface vertical pitch */
39509/*! @{ */
39510#define RD_SRC_PITCH_PITCH_MASK (0xFFFFU)
39511#define RD_SRC_PITCH_PITCH_SHIFT (0U)
39512#define RD_SRC_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_PITCH_PITCH_SHIFT)) & RD_SRC_PITCH_PITCH_MASK)
39513/*! @} */
39514
39515/*! @name WIDTH - Source frame buffer width */
39516/*! @{ */
39517#define RD_SRC_WIDTH_WIDTH_MASK (0xFFFFU)
39518#define RD_SRC_WIDTH_WIDTH_SHIFT (0U)
39519#define RD_SRC_WIDTH_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_WIDTH_WIDTH_SHIFT)) & RD_SRC_WIDTH_WIDTH_MASK)
39520/*! @} */
39521
39522/*! @name HEIGHT - Height of frame to be read */
39523/*! @{ */
39524#define RD_SRC_HEIGHT_HEIGHT_MASK (0xFFFFU)
39525#define RD_SRC_HEIGHT_HEIGHT_SHIFT (0U)
39526#define RD_SRC_HEIGHT_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_HEIGHT_HEIGHT_SHIFT)) & RD_SRC_HEIGHT_HEIGHT_MASK)
39527/*! @} */
39528
39529
39530/*!
39531 * @}
39532 */ /* end of group RD_SRC_Register_Masks */
39533
39534
39535/* RD_SRC - Peripheral instance base addresses */
39536/** Peripheral DCSS__RD_SRC base address */
39537#define DCSS__RD_SRC_BASE (0x32E22000u)
39538/** Peripheral DCSS__RD_SRC base pointer */
39539#define DCSS__RD_SRC ((RD_SRC_Type *)DCSS__RD_SRC_BASE)
39540/** Array initializer of RD_SRC peripheral base addresses */
39541#define RD_SRC_BASE_ADDRS { DCSS__RD_SRC_BASE }
39542/** Array initializer of RD_SRC peripheral base pointers */
39543#define RD_SRC_BASE_PTRS { DCSS__RD_SRC }
39544
39545/*!
39546 * @}
39547 */ /* end of group RD_SRC_Peripheral_Access_Layer */
39548
39549
39550/* ----------------------------------------------------------------------------
39551 -- ROMC Peripheral Access Layer
39552 ---------------------------------------------------------------------------- */
39553
39554/*!
39555 * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer
39556 * @{
39557 */
39558
39559/** ROMC - Register Layout Typedef */
39560typedef struct {
39561 uint8_t RESERVED_0[212];
39562 __IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */
39563 __IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */
39564 uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */
39565 __IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */
39566 __IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */
39567 uint8_t RESERVED_1[200];
39568 __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */
39569} ROMC_Type;
39570
39571/* ----------------------------------------------------------------------------
39572 -- ROMC Register Masks
39573 ---------------------------------------------------------------------------- */
39574
39575/*!
39576 * @addtogroup ROMC_Register_Masks ROMC Register Masks
39577 * @{
39578 */
39579
39580/*! @name ROMPATCHD - ROMC Data Registers */
39581/*! @{ */
39582#define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU)
39583#define ROMC_ROMPATCHD_DATAX_SHIFT (0U)
39584#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK)
39585/*! @} */
39586
39587/* The count of ROMC_ROMPATCHD */
39588#define ROMC_ROMPATCHD_COUNT (8U)
39589
39590/*! @name ROMPATCHCNTL - ROMC Control Register */
39591/*! @{ */
39592#define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU)
39593#define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U)
39594/*! DATAFIX
39595 * 0b00000000..Address comparator triggers a opcode patch
39596 * 0b00000001..Address comparator triggers a data fix
39597 */
39598#define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK)
39599#define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U)
39600#define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U)
39601/*! DIS
39602 * 0b0..Does not affect any ROMC functions (default)
39603 * 0b1..Disable all ROMC functions: data fixing, and opcode patching
39604 */
39605#define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK)
39606/*! @} */
39607
39608/*! @name ROMPATCHENL - ROMC Enable Register Low */
39609/*! @{ */
39610#define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU)
39611#define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U)
39612/*! ENABLE
39613 * 0b0000000000000000..Address comparator disabled
39614 * 0b0000000000000001..Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address
39615 */
39616#define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK)
39617/*! @} */
39618
39619/*! @name ROMPATCHA - ROMC Address Registers */
39620/*! @{ */
39621#define ROMC_ROMPATCHA_THUMBX_MASK (0x1U)
39622#define ROMC_ROMPATCHA_THUMBX_SHIFT (0U)
39623/*! THUMBX
39624 * 0b0..Arm patch
39625 * 0b1..THUMB patch (ignore if data fix)
39626 */
39627#define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK)
39628#define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU)
39629#define ROMC_ROMPATCHA_ADDRX_SHIFT (1U)
39630#define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK)
39631/*! @} */
39632
39633/* The count of ROMC_ROMPATCHA */
39634#define ROMC_ROMPATCHA_COUNT (16U)
39635
39636/*! @name ROMPATCHSR - ROMC Status Register */
39637/*! @{ */
39638#define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU)
39639#define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U)
39640/*! SOURCE
39641 * 0b000000..Address Comparator 0 matched
39642 * 0b000001..Address Comparator 1 matched
39643 * 0b001111..Address Comparator 15 matched
39644 */
39645#define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK)
39646#define ROMC_ROMPATCHSR_SW_MASK (0x20000U)
39647#define ROMC_ROMPATCHSR_SW_SHIFT (17U)
39648/*! SW
39649 * 0b0..no event or comparator collisions
39650 * 0b1..a collision has occurred
39651 */
39652#define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK)
39653/*! @} */
39654
39655
39656/*!
39657 * @}
39658 */ /* end of group ROMC_Register_Masks */
39659
39660
39661/* ROMC - Peripheral instance base addresses */
39662/** Peripheral ROMC base address */
39663#define ROMC_BASE (0x30310000u)
39664/** Peripheral ROMC base pointer */
39665#define ROMC ((ROMC_Type *)ROMC_BASE)
39666/** Array initializer of ROMC peripheral base addresses */
39667#define ROMC_BASE_ADDRS { ROMC_BASE }
39668/** Array initializer of ROMC peripheral base pointers */
39669#define ROMC_BASE_PTRS { ROMC }
39670
39671/*!
39672 * @}
39673 */ /* end of group ROMC_Peripheral_Access_Layer */
39674
39675
39676/* ----------------------------------------------------------------------------
39677 -- SDMAARM Peripheral Access Layer
39678 ---------------------------------------------------------------------------- */
39679
39680/*!
39681 * @addtogroup SDMAARM_Peripheral_Access_Layer SDMAARM Peripheral Access Layer
39682 * @{
39683 */
39684
39685/** SDMAARM - Register Layout Typedef */
39686typedef struct {
39687 __IO uint32_t MC0PTR; /**< Arm platform Channel 0 Pointer, offset: 0x0 */
39688 __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */
39689 __IO uint32_t STOP_STAT; /**< Channel Stop/Channel Status, offset: 0x8 */
39690 __IO uint32_t HSTART; /**< Channel Start, offset: 0xC */
39691 __IO uint32_t EVTOVR; /**< Channel Event Override, offset: 0x10 */
39692 __IO uint32_t DSPOVR; /**< Channel BP Override, offset: 0x14 */
39693 __IO uint32_t HOSTOVR; /**< Channel Arm platform Override, offset: 0x18 */
39694 __IO uint32_t EVTPEND; /**< Channel Event Pending, offset: 0x1C */
39695 uint8_t RESERVED_0[4];
39696 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */
39697 __I uint32_t EVTERR; /**< DMA Request Error Register, offset: 0x28 */
39698 __IO uint32_t INTRMASK; /**< Channel Arm platform Interrupt Mask, offset: 0x2C */
39699 __I uint32_t PSW; /**< Schedule Status, offset: 0x30 */
39700 __I uint32_t EVTERRDBG; /**< DMA Request Error Register, offset: 0x34 */
39701 __IO uint32_t CONFIG; /**< Configuration Register, offset: 0x38 */
39702 __IO uint32_t SDMA_LOCK; /**< SDMA LOCK, offset: 0x3C */
39703 __IO uint32_t ONCE_ENB; /**< OnCE Enable, offset: 0x40 */
39704 __IO uint32_t ONCE_DATA; /**< OnCE Data Register, offset: 0x44 */
39705 __IO uint32_t ONCE_INSTR; /**< OnCE Instruction Register, offset: 0x48 */
39706 __I uint32_t ONCE_STAT; /**< OnCE Status Register, offset: 0x4C */
39707 __IO uint32_t ONCE_CMD; /**< OnCE Command Register, offset: 0x50 */
39708 uint8_t RESERVED_1[4];
39709 __IO uint32_t ILLINSTADDR; /**< Illegal Instruction Trap Address, offset: 0x58 */
39710 __IO uint32_t CHN0ADDR; /**< Channel 0 Boot Address, offset: 0x5C */
39711 __I uint32_t EVT_MIRROR; /**< DMA Requests, offset: 0x60 */
39712 __I uint32_t EVT_MIRROR2; /**< DMA Requests 2, offset: 0x64 */
39713 uint8_t RESERVED_2[8];
39714 __IO uint32_t XTRIG_CONF1; /**< Cross-Trigger Events Configuration Register 1, offset: 0x70 */
39715 __IO uint32_t XTRIG_CONF2; /**< Cross-Trigger Events Configuration Register 2, offset: 0x74 */
39716 uint8_t RESERVED_3[136];
39717 __IO uint32_t SDMA_CHNPRI[32]; /**< Channel Priority Registers, array offset: 0x100, array step: 0x4 */
39718 uint8_t RESERVED_4[128];
39719 __IO uint32_t CHNENBL[48]; /**< Channel Enable RAM, array offset: 0x200, array step: 0x4 */
39720} SDMAARM_Type;
39721
39722/* ----------------------------------------------------------------------------
39723 -- SDMAARM Register Masks
39724 ---------------------------------------------------------------------------- */
39725
39726/*!
39727 * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks
39728 * @{
39729 */
39730
39731/*! @name MC0PTR - Arm platform Channel 0 Pointer */
39732/*! @{ */
39733#define SDMAARM_MC0PTR_MC0PTR_MASK (0xFFFFFFFFU)
39734#define SDMAARM_MC0PTR_MC0PTR_SHIFT (0U)
39735#define SDMAARM_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_MC0PTR_MC0PTR_SHIFT)) & SDMAARM_MC0PTR_MC0PTR_MASK)
39736/*! @} */
39737
39738/*! @name INTR - Channel Interrupts */
39739/*! @{ */
39740#define SDMAARM_INTR_HI_MASK (0xFFFFFFFFU)
39741#define SDMAARM_INTR_HI_SHIFT (0U)
39742#define SDMAARM_INTR_HI(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTR_HI_SHIFT)) & SDMAARM_INTR_HI_MASK)
39743/*! @} */
39744
39745/*! @name STOP_STAT - Channel Stop/Channel Status */
39746/*! @{ */
39747#define SDMAARM_STOP_STAT_HE_MASK (0xFFFFFFFFU)
39748#define SDMAARM_STOP_STAT_HE_SHIFT (0U)
39749#define SDMAARM_STOP_STAT_HE(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_STOP_STAT_HE_SHIFT)) & SDMAARM_STOP_STAT_HE_MASK)
39750/*! @} */
39751
39752/*! @name HSTART - Channel Start */
39753/*! @{ */
39754#define SDMAARM_HSTART_HSTART_HE_MASK (0xFFFFFFFFU)
39755#define SDMAARM_HSTART_HSTART_HE_SHIFT (0U)
39756#define SDMAARM_HSTART_HSTART_HE(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_HSTART_HSTART_HE_SHIFT)) & SDMAARM_HSTART_HSTART_HE_MASK)
39757/*! @} */
39758
39759/*! @name EVTOVR - Channel Event Override */
39760/*! @{ */
39761#define SDMAARM_EVTOVR_EO_MASK (0xFFFFFFFFU)
39762#define SDMAARM_EVTOVR_EO_SHIFT (0U)
39763#define SDMAARM_EVTOVR_EO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTOVR_EO_SHIFT)) & SDMAARM_EVTOVR_EO_MASK)
39764/*! @} */
39765
39766/*! @name DSPOVR - Channel BP Override */
39767/*! @{ */
39768#define SDMAARM_DSPOVR_DO_MASK (0xFFFFFFFFU)
39769#define SDMAARM_DSPOVR_DO_SHIFT (0U)
39770/*! DO
39771 * 0b00000000000000000000000000000000..- Reserved
39772 * 0b00000000000000000000000000000001..- Reset value.
39773 */
39774#define SDMAARM_DSPOVR_DO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DSPOVR_DO_SHIFT)) & SDMAARM_DSPOVR_DO_MASK)
39775/*! @} */
39776
39777/*! @name HOSTOVR - Channel Arm platform Override */
39778/*! @{ */
39779#define SDMAARM_HOSTOVR_HO_MASK (0xFFFFFFFFU)
39780#define SDMAARM_HOSTOVR_HO_SHIFT (0U)
39781#define SDMAARM_HOSTOVR_HO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_HOSTOVR_HO_SHIFT)) & SDMAARM_HOSTOVR_HO_MASK)
39782/*! @} */
39783
39784/*! @name EVTPEND - Channel Event Pending */
39785/*! @{ */
39786#define SDMAARM_EVTPEND_EP_MASK (0xFFFFFFFFU)
39787#define SDMAARM_EVTPEND_EP_SHIFT (0U)
39788#define SDMAARM_EVTPEND_EP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTPEND_EP_SHIFT)) & SDMAARM_EVTPEND_EP_MASK)
39789/*! @} */
39790
39791/*! @name RESET - Reset Register */
39792/*! @{ */
39793#define SDMAARM_RESET_RESET_MASK (0x1U)
39794#define SDMAARM_RESET_RESET_SHIFT (0U)
39795#define SDMAARM_RESET_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESET_SHIFT)) & SDMAARM_RESET_RESET_MASK)
39796#define SDMAARM_RESET_RESCHED_MASK (0x2U)
39797#define SDMAARM_RESET_RESCHED_SHIFT (1U)
39798#define SDMAARM_RESET_RESCHED(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESCHED_SHIFT)) & SDMAARM_RESET_RESCHED_MASK)
39799/*! @} */
39800
39801/*! @name EVTERR - DMA Request Error Register */
39802/*! @{ */
39803#define SDMAARM_EVTERR_CHNERR_MASK (0xFFFFFFFFU)
39804#define SDMAARM_EVTERR_CHNERR_SHIFT (0U)
39805#define SDMAARM_EVTERR_CHNERR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERR_CHNERR_SHIFT)) & SDMAARM_EVTERR_CHNERR_MASK)
39806/*! @} */
39807
39808/*! @name INTRMASK - Channel Arm platform Interrupt Mask */
39809/*! @{ */
39810#define SDMAARM_INTRMASK_HIMASK_MASK (0xFFFFFFFFU)
39811#define SDMAARM_INTRMASK_HIMASK_SHIFT (0U)
39812#define SDMAARM_INTRMASK_HIMASK(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTRMASK_HIMASK_SHIFT)) & SDMAARM_INTRMASK_HIMASK_MASK)
39813/*! @} */
39814
39815/*! @name PSW - Schedule Status */
39816/*! @{ */
39817#define SDMAARM_PSW_CCR_MASK (0xFU)
39818#define SDMAARM_PSW_CCR_SHIFT (0U)
39819#define SDMAARM_PSW_CCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCR_SHIFT)) & SDMAARM_PSW_CCR_MASK)
39820#define SDMAARM_PSW_CCP_MASK (0xF0U)
39821#define SDMAARM_PSW_CCP_SHIFT (4U)
39822/*! CCP
39823 * 0b0000..No running channel
39824 * 0b0001..Active channel priority
39825 */
39826#define SDMAARM_PSW_CCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCP_SHIFT)) & SDMAARM_PSW_CCP_MASK)
39827#define SDMAARM_PSW_NCR_MASK (0x1F00U)
39828#define SDMAARM_PSW_NCR_SHIFT (8U)
39829#define SDMAARM_PSW_NCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCR_SHIFT)) & SDMAARM_PSW_NCR_MASK)
39830#define SDMAARM_PSW_NCP_MASK (0xE000U)
39831#define SDMAARM_PSW_NCP_SHIFT (13U)
39832/*! NCP
39833 * 0b000..No running channel
39834 * 0b001..Active channel priority
39835 */
39836#define SDMAARM_PSW_NCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCP_SHIFT)) & SDMAARM_PSW_NCP_MASK)
39837/*! @} */
39838
39839/*! @name EVTERRDBG - DMA Request Error Register */
39840/*! @{ */
39841#define SDMAARM_EVTERRDBG_CHNERR_MASK (0xFFFFFFFFU)
39842#define SDMAARM_EVTERRDBG_CHNERR_SHIFT (0U)
39843#define SDMAARM_EVTERRDBG_CHNERR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERRDBG_CHNERR_SHIFT)) & SDMAARM_EVTERRDBG_CHNERR_MASK)
39844/*! @} */
39845
39846/*! @name CONFIG - Configuration Register */
39847/*! @{ */
39848#define SDMAARM_CONFIG_CSM_MASK (0x3U)
39849#define SDMAARM_CONFIG_CSM_SHIFT (0U)
39850/*! CSM
39851 * 0b00..static
39852 * 0b01..dynamic low power
39853 * 0b10..dynamic with no loop
39854 * 0b11..dynamic
39855 */
39856#define SDMAARM_CONFIG_CSM(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_CSM_SHIFT)) & SDMAARM_CONFIG_CSM_MASK)
39857#define SDMAARM_CONFIG_ACR_MASK (0x10U)
39858#define SDMAARM_CONFIG_ACR_SHIFT (4U)
39859/*! ACR
39860 * 0b0..Arm platform DMA interface frequency equals twice core frequency
39861 * 0b1..Arm platform DMA interface frequency equals core frequency
39862 */
39863#define SDMAARM_CONFIG_ACR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_ACR_SHIFT)) & SDMAARM_CONFIG_ACR_MASK)
39864#define SDMAARM_CONFIG_RTDOBS_MASK (0x800U)
39865#define SDMAARM_CONFIG_RTDOBS_SHIFT (11U)
39866/*! RTDOBS
39867 * 0b0..RTD pins disabled
39868 * 0b1..RTD pins enabled
39869 */
39870#define SDMAARM_CONFIG_RTDOBS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_RTDOBS_SHIFT)) & SDMAARM_CONFIG_RTDOBS_MASK)
39871#define SDMAARM_CONFIG_DSPDMA_MASK (0x1000U)
39872#define SDMAARM_CONFIG_DSPDMA_SHIFT (12U)
39873/*! DSPDMA
39874 * 0b0..- Reset Value
39875 * 0b1..- Reserved
39876 */
39877#define SDMAARM_CONFIG_DSPDMA(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_DSPDMA_SHIFT)) & SDMAARM_CONFIG_DSPDMA_MASK)
39878/*! @} */
39879
39880/*! @name SDMA_LOCK - SDMA LOCK */
39881/*! @{ */
39882#define SDMAARM_SDMA_LOCK_LOCK_MASK (0x1U)
39883#define SDMAARM_SDMA_LOCK_LOCK_SHIFT (0U)
39884/*! LOCK
39885 * 0b0..LOCK disengaged.
39886 * 0b1..LOCK enabled.
39887 */
39888#define SDMAARM_SDMA_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_LOCK_SHIFT)) & SDMAARM_SDMA_LOCK_LOCK_MASK)
39889#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK (0x2U)
39890#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT (1U)
39891/*! SRESET_LOCK_CLR
39892 * 0b0..Software Reset does not clear the LOCK bit.
39893 * 0b1..Software Reset clears the LOCK bit.
39894 */
39895#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT)) & SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK)
39896/*! @} */
39897
39898/*! @name ONCE_ENB - OnCE Enable */
39899/*! @{ */
39900#define SDMAARM_ONCE_ENB_ENB_MASK (0x1U)
39901#define SDMAARM_ONCE_ENB_ENB_SHIFT (0U)
39902#define SDMAARM_ONCE_ENB_ENB(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_ENB_ENB_SHIFT)) & SDMAARM_ONCE_ENB_ENB_MASK)
39903/*! @} */
39904
39905/*! @name ONCE_DATA - OnCE Data Register */
39906/*! @{ */
39907#define SDMAARM_ONCE_DATA_DATA_MASK (0xFFFFFFFFU)
39908#define SDMAARM_ONCE_DATA_DATA_SHIFT (0U)
39909#define SDMAARM_ONCE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_DATA_DATA_SHIFT)) & SDMAARM_ONCE_DATA_DATA_MASK)
39910/*! @} */
39911
39912/*! @name ONCE_INSTR - OnCE Instruction Register */
39913/*! @{ */
39914#define SDMAARM_ONCE_INSTR_INSTR_MASK (0xFFFFU)
39915#define SDMAARM_ONCE_INSTR_INSTR_SHIFT (0U)
39916#define SDMAARM_ONCE_INSTR_INSTR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_INSTR_INSTR_SHIFT)) & SDMAARM_ONCE_INSTR_INSTR_MASK)
39917/*! @} */
39918
39919/*! @name ONCE_STAT - OnCE Status Register */
39920/*! @{ */
39921#define SDMAARM_ONCE_STAT_ECDR_MASK (0x7U)
39922#define SDMAARM_ONCE_STAT_ECDR_SHIFT (0U)
39923/*! ECDR
39924 * 0b000..1 matched addra_cond
39925 * 0b001..1 matched addrb_cond
39926 * 0b010..1 matched data_cond
39927 */
39928#define SDMAARM_ONCE_STAT_ECDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ECDR_SHIFT)) & SDMAARM_ONCE_STAT_ECDR_MASK)
39929#define SDMAARM_ONCE_STAT_MST_MASK (0x80U)
39930#define SDMAARM_ONCE_STAT_MST_SHIFT (7U)
39931/*! MST
39932 * 0b0..The JTAG interface controls the OnCE.
39933 * 0b1..The Arm platform peripheral interface controls the OnCE.
39934 */
39935#define SDMAARM_ONCE_STAT_MST(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_MST_SHIFT)) & SDMAARM_ONCE_STAT_MST_MASK)
39936#define SDMAARM_ONCE_STAT_SWB_MASK (0x100U)
39937#define SDMAARM_ONCE_STAT_SWB_SHIFT (8U)
39938#define SDMAARM_ONCE_STAT_SWB(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_SWB_SHIFT)) & SDMAARM_ONCE_STAT_SWB_MASK)
39939#define SDMAARM_ONCE_STAT_ODR_MASK (0x200U)
39940#define SDMAARM_ONCE_STAT_ODR_SHIFT (9U)
39941#define SDMAARM_ONCE_STAT_ODR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ODR_SHIFT)) & SDMAARM_ONCE_STAT_ODR_MASK)
39942#define SDMAARM_ONCE_STAT_EDR_MASK (0x400U)
39943#define SDMAARM_ONCE_STAT_EDR_SHIFT (10U)
39944#define SDMAARM_ONCE_STAT_EDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_EDR_SHIFT)) & SDMAARM_ONCE_STAT_EDR_MASK)
39945#define SDMAARM_ONCE_STAT_RCV_MASK (0x800U)
39946#define SDMAARM_ONCE_STAT_RCV_SHIFT (11U)
39947#define SDMAARM_ONCE_STAT_RCV(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_RCV_SHIFT)) & SDMAARM_ONCE_STAT_RCV_MASK)
39948#define SDMAARM_ONCE_STAT_PST_MASK (0xF000U)
39949#define SDMAARM_ONCE_STAT_PST_SHIFT (12U)
39950/*! PST
39951 * 0b0000..Program
39952 * 0b0001..Data
39953 * 0b0010..Change of Flow
39954 * 0b0011..Change of Flow in Loop
39955 * 0b0100..Debug
39956 * 0b0101..Functional Unit
39957 * 0b0110..Sleep
39958 * 0b0111..Save
39959 * 0b1000..Program in Sleep
39960 * 0b1001..Data in Sleep
39961 * 0b0010..Change of Flow in Sleep
39962 * 0b0011..Change Flow in Loop in Sleep
39963 * 0b1100..Debug in Sleep
39964 * 0b1101..Functional Unit in Sleep
39965 * 0b1110..Sleep after Reset
39966 * 0b1111..Restore
39967 */
39968#define SDMAARM_ONCE_STAT_PST(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_PST_SHIFT)) & SDMAARM_ONCE_STAT_PST_MASK)
39969/*! @} */
39970
39971/*! @name ONCE_CMD - OnCE Command Register */
39972/*! @{ */
39973#define SDMAARM_ONCE_CMD_CMD_MASK (0xFU)
39974#define SDMAARM_ONCE_CMD_CMD_SHIFT (0U)
39975/*! CMD
39976 * 0b0000..rstatus
39977 * 0b0001..dmov
39978 * 0b0010..exec_once
39979 * 0b0011..run_core
39980 * 0b0100..exec_core
39981 * 0b0101..debug_rqst
39982 * 0b0110..rbuffer
39983 */
39984#define SDMAARM_ONCE_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_CMD_CMD_SHIFT)) & SDMAARM_ONCE_CMD_CMD_MASK)
39985/*! @} */
39986
39987/*! @name ILLINSTADDR - Illegal Instruction Trap Address */
39988/*! @{ */
39989#define SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK (0x3FFFU)
39990#define SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT (0U)
39991#define SDMAARM_ILLINSTADDR_ILLINSTADDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT)) & SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK)
39992/*! @} */
39993
39994/*! @name CHN0ADDR - Channel 0 Boot Address */
39995/*! @{ */
39996#define SDMAARM_CHN0ADDR_CHN0ADDR_MASK (0x3FFFU)
39997#define SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT (0U)
39998#define SDMAARM_CHN0ADDR_CHN0ADDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT)) & SDMAARM_CHN0ADDR_CHN0ADDR_MASK)
39999#define SDMAARM_CHN0ADDR_SMSZ_MASK (0x4000U)
40000#define SDMAARM_CHN0ADDR_SMSZ_SHIFT (14U)
40001/*! SMSZ
40002 * 0b0..24 words per context
40003 * 0b1..32 words per context
40004 */
40005#define SDMAARM_CHN0ADDR_SMSZ(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_SMSZ_SHIFT)) & SDMAARM_CHN0ADDR_SMSZ_MASK)
40006/*! @} */
40007
40008/*! @name EVT_MIRROR - DMA Requests */
40009/*! @{ */
40010#define SDMAARM_EVT_MIRROR_EVENTS_MASK (0xFFFFFFFFU)
40011#define SDMAARM_EVT_MIRROR_EVENTS_SHIFT (0U)
40012/*! EVENTS
40013 * 0b00000000000000000000000000000000..DMA request event not pending
40014 * 0b00000000000000000000000000000001..DMA request event pending
40015 */
40016#define SDMAARM_EVT_MIRROR_EVENTS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR_EVENTS_MASK)
40017/*! @} */
40018
40019/*! @name EVT_MIRROR2 - DMA Requests 2 */
40020/*! @{ */
40021#define SDMAARM_EVT_MIRROR2_EVENTS_MASK (0xFFFFU)
40022#define SDMAARM_EVT_MIRROR2_EVENTS_SHIFT (0U)
40023/*! EVENTS
40024 * 0b0000000000000000..- DMA request event not pending
40025 */
40026#define SDMAARM_EVT_MIRROR2_EVENTS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR2_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR2_EVENTS_MASK)
40027/*! @} */
40028
40029/*! @name XTRIG_CONF1 - Cross-Trigger Events Configuration Register 1 */
40030/*! @{ */
40031#define SDMAARM_XTRIG_CONF1_NUM0_MASK (0x3FU)
40032#define SDMAARM_XTRIG_CONF1_NUM0_SHIFT (0U)
40033#define SDMAARM_XTRIG_CONF1_NUM0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM0_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM0_MASK)
40034#define SDMAARM_XTRIG_CONF1_CNF0_MASK (0x40U)
40035#define SDMAARM_XTRIG_CONF1_CNF0_SHIFT (6U)
40036/*! CNF0
40037 * 0b0..channel
40038 * 0b1..DMA request
40039 */
40040#define SDMAARM_XTRIG_CONF1_CNF0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF0_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF0_MASK)
40041#define SDMAARM_XTRIG_CONF1_NUM1_MASK (0x3F00U)
40042#define SDMAARM_XTRIG_CONF1_NUM1_SHIFT (8U)
40043#define SDMAARM_XTRIG_CONF1_NUM1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM1_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM1_MASK)
40044#define SDMAARM_XTRIG_CONF1_CNF1_MASK (0x4000U)
40045#define SDMAARM_XTRIG_CONF1_CNF1_SHIFT (14U)
40046/*! CNF1
40047 * 0b0..channel
40048 * 0b1..DMA request
40049 */
40050#define SDMAARM_XTRIG_CONF1_CNF1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF1_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF1_MASK)
40051#define SDMAARM_XTRIG_CONF1_NUM2_MASK (0x3F0000U)
40052#define SDMAARM_XTRIG_CONF1_NUM2_SHIFT (16U)
40053#define SDMAARM_XTRIG_CONF1_NUM2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM2_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM2_MASK)
40054#define SDMAARM_XTRIG_CONF1_CNF2_MASK (0x400000U)
40055#define SDMAARM_XTRIG_CONF1_CNF2_SHIFT (22U)
40056/*! CNF2
40057 * 0b0..channel
40058 * 0b1..DMA request
40059 */
40060#define SDMAARM_XTRIG_CONF1_CNF2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF2_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF2_MASK)
40061#define SDMAARM_XTRIG_CONF1_NUM3_MASK (0x3F000000U)
40062#define SDMAARM_XTRIG_CONF1_NUM3_SHIFT (24U)
40063#define SDMAARM_XTRIG_CONF1_NUM3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM3_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM3_MASK)
40064#define SDMAARM_XTRIG_CONF1_CNF3_MASK (0x40000000U)
40065#define SDMAARM_XTRIG_CONF1_CNF3_SHIFT (30U)
40066/*! CNF3
40067 * 0b0..channel
40068 * 0b1..DMA request
40069 */
40070#define SDMAARM_XTRIG_CONF1_CNF3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF3_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF3_MASK)
40071/*! @} */
40072
40073/*! @name XTRIG_CONF2 - Cross-Trigger Events Configuration Register 2 */
40074/*! @{ */
40075#define SDMAARM_XTRIG_CONF2_NUM4_MASK (0x3FU)
40076#define SDMAARM_XTRIG_CONF2_NUM4_SHIFT (0U)
40077#define SDMAARM_XTRIG_CONF2_NUM4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM4_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM4_MASK)
40078#define SDMAARM_XTRIG_CONF2_CNF4_MASK (0x40U)
40079#define SDMAARM_XTRIG_CONF2_CNF4_SHIFT (6U)
40080/*! CNF4
40081 * 0b0..channel
40082 * 0b1..DMA request
40083 */
40084#define SDMAARM_XTRIG_CONF2_CNF4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF4_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF4_MASK)
40085#define SDMAARM_XTRIG_CONF2_NUM5_MASK (0x3F00U)
40086#define SDMAARM_XTRIG_CONF2_NUM5_SHIFT (8U)
40087#define SDMAARM_XTRIG_CONF2_NUM5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM5_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM5_MASK)
40088#define SDMAARM_XTRIG_CONF2_CNF5_MASK (0x4000U)
40089#define SDMAARM_XTRIG_CONF2_CNF5_SHIFT (14U)
40090/*! CNF5
40091 * 0b0..channel
40092 * 0b1..DMA request
40093 */
40094#define SDMAARM_XTRIG_CONF2_CNF5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF5_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF5_MASK)
40095#define SDMAARM_XTRIG_CONF2_NUM6_MASK (0x3F0000U)
40096#define SDMAARM_XTRIG_CONF2_NUM6_SHIFT (16U)
40097#define SDMAARM_XTRIG_CONF2_NUM6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM6_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM6_MASK)
40098#define SDMAARM_XTRIG_CONF2_CNF6_MASK (0x400000U)
40099#define SDMAARM_XTRIG_CONF2_CNF6_SHIFT (22U)
40100/*! CNF6
40101 * 0b0..channel
40102 * 0b1..DMA request
40103 */
40104#define SDMAARM_XTRIG_CONF2_CNF6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF6_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF6_MASK)
40105#define SDMAARM_XTRIG_CONF2_NUM7_MASK (0x3F000000U)
40106#define SDMAARM_XTRIG_CONF2_NUM7_SHIFT (24U)
40107#define SDMAARM_XTRIG_CONF2_NUM7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM7_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM7_MASK)
40108#define SDMAARM_XTRIG_CONF2_CNF7_MASK (0x40000000U)
40109#define SDMAARM_XTRIG_CONF2_CNF7_SHIFT (30U)
40110/*! CNF7
40111 * 0b0..channel
40112 * 0b1..DMA request
40113 */
40114#define SDMAARM_XTRIG_CONF2_CNF7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF7_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF7_MASK)
40115/*! @} */
40116
40117/*! @name SDMA_CHNPRI - Channel Priority Registers */
40118/*! @{ */
40119#define SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK (0x7U)
40120#define SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT (0U)
40121#define SDMAARM_SDMA_CHNPRI_CHNPRIn(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT)) & SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK)
40122/*! @} */
40123
40124/* The count of SDMAARM_SDMA_CHNPRI */
40125#define SDMAARM_SDMA_CHNPRI_COUNT (32U)
40126
40127/*! @name CHNENBL - Channel Enable RAM */
40128/*! @{ */
40129#define SDMAARM_CHNENBL_ENBLn_MASK (0xFFFFFFFFU)
40130#define SDMAARM_CHNENBL_ENBLn_SHIFT (0U)
40131#define SDMAARM_CHNENBL_ENBLn(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHNENBL_ENBLn_SHIFT)) & SDMAARM_CHNENBL_ENBLn_MASK)
40132/*! @} */
40133
40134/* The count of SDMAARM_CHNENBL */
40135#define SDMAARM_CHNENBL_COUNT (48U)
40136
40137
40138/*!
40139 * @}
40140 */ /* end of group SDMAARM_Register_Masks */
40141
40142
40143/* SDMAARM - Peripheral instance base addresses */
40144/** Peripheral SDMAARM1 base address */
40145#define SDMAARM1_BASE (0x30BD0000u)
40146/** Peripheral SDMAARM1 base pointer */
40147#define SDMAARM1 ((SDMAARM_Type *)SDMAARM1_BASE)
40148/** Peripheral SDMAARM2 base address */
40149#define SDMAARM2_BASE (0x302C0000u)
40150/** Peripheral SDMAARM2 base pointer */
40151#define SDMAARM2 ((SDMAARM_Type *)SDMAARM2_BASE)
40152/** Array initializer of SDMAARM peripheral base addresses */
40153#define SDMAARM_BASE_ADDRS { 0u, SDMAARM1_BASE, SDMAARM2_BASE }
40154/** Array initializer of SDMAARM peripheral base pointers */
40155#define SDMAARM_BASE_PTRS { (SDMAARM_Type *)0u, SDMAARM1, SDMAARM2 }
40156/** Interrupt vectors for the SDMAARM peripheral type */
40157#define SDMAARM_IRQS { NotAvail_IRQn, SDMA1_IRQn, SDMA2_IRQn }
40158
40159/*!
40160 * @}
40161 */ /* end of group SDMAARM_Peripheral_Access_Layer */
40162
40163
40164/* ----------------------------------------------------------------------------
40165 -- SEMA4 Peripheral Access Layer
40166 ---------------------------------------------------------------------------- */
40167
40168/*!
40169 * @addtogroup SEMA4_Peripheral_Access_Layer SEMA4 Peripheral Access Layer
40170 * @{
40171 */
40172
40173/** SEMA4 - Register Layout Typedef */
40174typedef struct {
40175 __IO uint8_t Gate00; /**< Semaphores Gate 0 Register, offset: 0x0 */
40176 __IO uint8_t Gate01; /**< Semaphores Gate 1 Register, offset: 0x1 */
40177 __IO uint8_t Gate02; /**< Semaphores Gate 2 Register, offset: 0x2 */
40178 __IO uint8_t Gate03; /**< Semaphores Gate 3 Register, offset: 0x3 */
40179 __IO uint8_t Gate04; /**< Semaphores Gate 4 Register, offset: 0x4 */
40180 __IO uint8_t Gate05; /**< Semaphores Gate 5 Register, offset: 0x5 */
40181 __IO uint8_t Gate06; /**< Semaphores Gate 6 Register, offset: 0x6 */
40182 __IO uint8_t Gate07; /**< Semaphores Gate 7 Register, offset: 0x7 */
40183 __IO uint8_t Gate08; /**< Semaphores Gate 8 Register, offset: 0x8 */
40184 __IO uint8_t Gate09; /**< Semaphores Gate 9 Register, offset: 0x9 */
40185 __IO uint8_t Gate10; /**< Semaphores Gate 10 Register, offset: 0xA */
40186 __IO uint8_t Gate11; /**< Semaphores Gate 11 Register, offset: 0xB */
40187 __IO uint8_t Gate12; /**< Semaphores Gate 12 Register, offset: 0xC */
40188 __IO uint8_t Gate13; /**< Semaphores Gate 13 Register, offset: 0xD */
40189 __IO uint8_t Gate14; /**< Semaphores Gate 14 Register, offset: 0xE */
40190 __IO uint8_t Gate15; /**< Semaphores Gate 15 Register, offset: 0xF */
40191 uint8_t RESERVED_0[48];
40192 struct { /* offset: 0x40, array step: 0x8 */
40193 __IO uint16_t CPINE; /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */
40194 uint8_t RESERVED_0[6];
40195 } CPINE[2];
40196 uint8_t RESERVED_1[48];
40197 struct { /* offset: 0x80, array step: 0x8 */
40198 __I uint16_t CPNTF; /**< Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8 */
40199 uint8_t RESERVED_0[6];
40200 } CPNTF[2];
40201 uint8_t RESERVED_2[112];
40202 __IO uint16_t RSTGT; /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */
40203 uint8_t RESERVED_3[2];
40204 __IO uint16_t RSTNTF; /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */
40205} SEMA4_Type;
40206
40207/* ----------------------------------------------------------------------------
40208 -- SEMA4 Register Masks
40209 ---------------------------------------------------------------------------- */
40210
40211/*!
40212 * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks
40213 * @{
40214 */
40215
40216/*! @name Gate00 - Semaphores Gate 0 Register */
40217/*! @{ */
40218#define SEMA4_Gate00_GTFSM_MASK (0x3U)
40219#define SEMA4_Gate00_GTFSM_SHIFT (0U)
40220/*! GTFSM - Gate Finite State Machine.
40221 * 0b00..The gate is unlocked (free).
40222 * 0b01..The gate has been locked by processor 0.
40223 * 0b10..The gate has been locked by processor 1.
40224 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine.
40225 */
40226#define SEMA4_Gate00_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate00_GTFSM_SHIFT)) & SEMA4_Gate00_GTFSM_MASK)
40227/*! @} */
40228
40229/*! @name Gate01 - Semaphores Gate 1 Register */
40230/*! @{ */
40231#define SEMA4_Gate01_GTFSM_MASK (0x3U)
40232#define SEMA4_Gate01_GTFSM_SHIFT (0U)
40233/*! GTFSM - Gate Finite State Machine.
40234 * 0b00..The gate is unlocked (free).
40235 * 0b01..The gate has been locked by processor 0.
40236 * 0b10..The gate has been locked by processor 1.
40237 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine.
40238 */
40239#define SEMA4_Gate01_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate01_GTFSM_SHIFT)) & SEMA4_Gate01_GTFSM_MASK)
40240/*! @} */
40241
40242/*! @name Gate02 - Semaphores Gate 2 Register */
40243/*! @{ */
40244#define SEMA4_Gate02_GTFSM_MASK (0x3U)
40245#define SEMA4_Gate02_GTFSM_SHIFT (0U)
40246/*! GTFSM - Gate Finite State Machine.
40247 * 0b00..The gate is unlocked (free).
40248 * 0b01..The gate has been locked by processor 0.
40249 * 0b10..The gate has been locked by processor 1.
40250 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine.
40251 */
40252#define SEMA4_Gate02_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate02_GTFSM_SHIFT)) & SEMA4_Gate02_GTFSM_MASK)
40253/*! @} */
40254
40255/*! @name Gate03 - Semaphores Gate 3 Register */
40256/*! @{ */
40257#define SEMA4_Gate03_GTFSM_MASK (0x3U)
40258#define SEMA4_Gate03_GTFSM_SHIFT (0U)
40259/*! GTFSM - Gate Finite State Machine.
40260 * 0b00..The gate is unlocked (free).
40261 * 0b01..The gate has been locked by processor 0.
40262 * 0b10..The gate has been locked by processor 1.
40263 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine.
40264 */
40265#define SEMA4_Gate03_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate03_GTFSM_SHIFT)) & SEMA4_Gate03_GTFSM_MASK)
40266/*! @} */
40267
40268/*! @name Gate04 - Semaphores Gate 4 Register */
40269/*! @{ */
40270#define SEMA4_Gate04_GTFSM_MASK (0x3U)
40271#define SEMA4_Gate04_GTFSM_SHIFT (0U)
40272/*! GTFSM - Gate Finite State Machine.
40273 * 0b00..The gate is unlocked (free).
40274 * 0b01..The gate has been locked by processor 0.
40275 * 0b10..The gate has been locked by processor 1.
40276 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine.
40277 */
40278#define SEMA4_Gate04_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate04_GTFSM_SHIFT)) & SEMA4_Gate04_GTFSM_MASK)
40279/*! @} */
40280
40281/*! @name Gate05 - Semaphores Gate 5 Register */
40282/*! @{ */
40283#define SEMA4_Gate05_GTFSM_MASK (0x3U)
40284#define SEMA4_Gate05_GTFSM_SHIFT (0U)
40285/*! GTFSM - Gate Finite State Machine.
40286 * 0b00..The gate is unlocked (free).
40287 * 0b01..The gate has been locked by processor 0.
40288 * 0b10..The gate has been locked by processor 1.
40289 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine.
40290 */
40291#define SEMA4_Gate05_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate05_GTFSM_SHIFT)) & SEMA4_Gate05_GTFSM_MASK)
40292/*! @} */
40293
40294/*! @name Gate06 - Semaphores Gate 6 Register */
40295/*! @{ */
40296#define SEMA4_Gate06_GTFSM_MASK (0x3U)
40297#define SEMA4_Gate06_GTFSM_SHIFT (0U)
40298/*! GTFSM - Gate Finite State Machine.
40299 * 0b00..The gate is unlocked (free).
40300 * 0b01..The gate has been locked by processor 0.
40301 * 0b10..The gate has been locked by processor 1.
40302 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine.
40303 */
40304#define SEMA4_Gate06_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate06_GTFSM_SHIFT)) & SEMA4_Gate06_GTFSM_MASK)
40305/*! @} */
40306
40307/*! @name Gate07 - Semaphores Gate 7 Register */
40308/*! @{ */
40309#define SEMA4_Gate07_GTFSM_MASK (0x3U)
40310#define SEMA4_Gate07_GTFSM_SHIFT (0U)
40311/*! GTFSM - Gate Finite State Machine.
40312 * 0b00..The gate is unlocked (free).
40313 * 0b01..The gate has been locked by processor 0.
40314 * 0b10..The gate has been locked by processor 1.
40315 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine.
40316 */
40317#define SEMA4_Gate07_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate07_GTFSM_SHIFT)) & SEMA4_Gate07_GTFSM_MASK)
40318/*! @} */
40319
40320/*! @name Gate08 - Semaphores Gate 8 Register */
40321/*! @{ */
40322#define SEMA4_Gate08_GTFSM_MASK (0x3U)
40323#define SEMA4_Gate08_GTFSM_SHIFT (0U)
40324/*! GTFSM - Gate Finite State Machine.
40325 * 0b00..The gate is unlocked (free).
40326 * 0b01..The gate has been locked by processor 0.
40327 * 0b10..The gate has been locked by processor 1.
40328 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine.
40329 */
40330#define SEMA4_Gate08_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate08_GTFSM_SHIFT)) & SEMA4_Gate08_GTFSM_MASK)
40331/*! @} */
40332
40333/*! @name Gate09 - Semaphores Gate 9 Register */
40334/*! @{ */
40335#define SEMA4_Gate09_GTFSM_MASK (0x3U)
40336#define SEMA4_Gate09_GTFSM_SHIFT (0U)
40337/*! GTFSM - Gate Finite State Machine.
40338 * 0b00..The gate is unlocked (free).
40339 * 0b01..The gate has been locked by processor 0.
40340 * 0b10..The gate has been locked by processor 1.
40341 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine.
40342 */
40343#define SEMA4_Gate09_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate09_GTFSM_SHIFT)) & SEMA4_Gate09_GTFSM_MASK)
40344/*! @} */
40345
40346/*! @name Gate10 - Semaphores Gate 10 Register */
40347/*! @{ */
40348#define SEMA4_Gate10_GTFSM_MASK (0x3U)
40349#define SEMA4_Gate10_GTFSM_SHIFT (0U)
40350/*! GTFSM - Gate Finite State Machine.
40351 * 0b00..The gate is unlocked (free).
40352 * 0b01..The gate has been locked by processor 0.
40353 * 0b10..The gate has been locked by processor 1.
40354 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine.
40355 */
40356#define SEMA4_Gate10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate10_GTFSM_SHIFT)) & SEMA4_Gate10_GTFSM_MASK)
40357/*! @} */
40358
40359/*! @name Gate11 - Semaphores Gate 11 Register */
40360/*! @{ */
40361#define SEMA4_Gate11_GTFSM_MASK (0x3U)
40362#define SEMA4_Gate11_GTFSM_SHIFT (0U)
40363/*! GTFSM - Gate Finite State Machine.
40364 * 0b00..The gate is unlocked (free).
40365 * 0b01..The gate has been locked by processor 0.
40366 * 0b10..The gate has been locked by processor 1.
40367 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine.
40368 */
40369#define SEMA4_Gate11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate11_GTFSM_SHIFT)) & SEMA4_Gate11_GTFSM_MASK)
40370/*! @} */
40371
40372/*! @name Gate12 - Semaphores Gate 12 Register */
40373/*! @{ */
40374#define SEMA4_Gate12_GTFSM_MASK (0x3U)
40375#define SEMA4_Gate12_GTFSM_SHIFT (0U)
40376/*! GTFSM - Gate Finite State Machine.
40377 * 0b00..The gate is unlocked (free).
40378 * 0b01..The gate has been locked by processor 0.
40379 * 0b10..The gate has been locked by processor 1.
40380 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine.
40381 */
40382#define SEMA4_Gate12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate12_GTFSM_SHIFT)) & SEMA4_Gate12_GTFSM_MASK)
40383/*! @} */
40384
40385/*! @name Gate13 - Semaphores Gate 13 Register */
40386/*! @{ */
40387#define SEMA4_Gate13_GTFSM_MASK (0x3U)
40388#define SEMA4_Gate13_GTFSM_SHIFT (0U)
40389/*! GTFSM - Gate Finite State Machine.
40390 * 0b00..The gate is unlocked (free).
40391 * 0b01..The gate has been locked by processor 0.
40392 * 0b10..The gate has been locked by processor 1.
40393 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine.
40394 */
40395#define SEMA4_Gate13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate13_GTFSM_SHIFT)) & SEMA4_Gate13_GTFSM_MASK)
40396/*! @} */
40397
40398/*! @name Gate14 - Semaphores Gate 14 Register */
40399/*! @{ */
40400#define SEMA4_Gate14_GTFSM_MASK (0x3U)
40401#define SEMA4_Gate14_GTFSM_SHIFT (0U)
40402/*! GTFSM - Gate Finite State Machine.
40403 * 0b00..The gate is unlocked (free).
40404 * 0b01..The gate has been locked by processor 0.
40405 * 0b10..The gate has been locked by processor 1.
40406 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine.
40407 */
40408#define SEMA4_Gate14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate14_GTFSM_SHIFT)) & SEMA4_Gate14_GTFSM_MASK)
40409/*! @} */
40410
40411/*! @name Gate15 - Semaphores Gate 15 Register */
40412/*! @{ */
40413#define SEMA4_Gate15_GTFSM_MASK (0x3U)
40414#define SEMA4_Gate15_GTFSM_SHIFT (0U)
40415/*! GTFSM - Gate Finite State Machine.
40416 * 0b00..The gate is unlocked (free).
40417 * 0b01..The gate has been locked by processor 0.
40418 * 0b10..The gate has been locked by processor 1.
40419 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine.
40420 */
40421#define SEMA4_Gate15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate15_GTFSM_SHIFT)) & SEMA4_Gate15_GTFSM_MASK)
40422/*! @} */
40423
40424/*! @name CPINE - Semaphores Processor n IRQ Notification Enable */
40425/*! @{ */
40426#define SEMA4_CPINE_INE7_MASK (0x1U)
40427#define SEMA4_CPINE_INE7_SHIFT (0U)
40428/*! INE7 - Interrupt Request Notification Enable 7. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 7.
40429 * 0b0..The generation of the notification interrupt is disabled.
40430 * 0b1..The generation of the notification interrupt is enabled.
40431 */
40432#define SEMA4_CPINE_INE7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_SHIFT)) & SEMA4_CPINE_INE7_MASK)
40433#define SEMA4_CPINE_INE6_MASK (0x2U)
40434#define SEMA4_CPINE_INE6_SHIFT (1U)
40435/*! INE6 - Interrupt Request Notification Enable 6. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 6.
40436 * 0b0..The generation of the notification interrupt is disabled.
40437 * 0b1..The generation of the notification interrupt is enabled.
40438 */
40439#define SEMA4_CPINE_INE6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_SHIFT)) & SEMA4_CPINE_INE6_MASK)
40440#define SEMA4_CPINE_INE5_MASK (0x4U)
40441#define SEMA4_CPINE_INE5_SHIFT (2U)
40442/*! INE5 - Interrupt Request Notification Enable 5. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 5.
40443 * 0b0..The generation of the notification interrupt is disabled.
40444 * 0b1..The generation of the notification interrupt is enabled.
40445 */
40446#define SEMA4_CPINE_INE5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_SHIFT)) & SEMA4_CPINE_INE5_MASK)
40447#define SEMA4_CPINE_INE4_MASK (0x8U)
40448#define SEMA4_CPINE_INE4_SHIFT (3U)
40449/*! INE4 - Interrupt Request Notification Enable 4. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 4.
40450 * 0b0..The generation of the notification interrupt is disabled.
40451 * 0b1..The generation of the notification interrupt is enabled.
40452 */
40453#define SEMA4_CPINE_INE4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_SHIFT)) & SEMA4_CPINE_INE4_MASK)
40454#define SEMA4_CPINE_INE3_MASK (0x10U)
40455#define SEMA4_CPINE_INE3_SHIFT (4U)
40456/*! INE3
40457 * 0b0..The generation of the notification interrupt is disabled.
40458 * 0b1..The generation of the notification interrupt is enabled.
40459 */
40460#define SEMA4_CPINE_INE3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_SHIFT)) & SEMA4_CPINE_INE3_MASK)
40461#define SEMA4_CPINE_INE2_MASK (0x20U)
40462#define SEMA4_CPINE_INE2_SHIFT (5U)
40463/*! INE2
40464 * 0b0..The generation of the notification interrupt is disabled.
40465 * 0b1..The generation of the notification interrupt is enabled.
40466 */
40467#define SEMA4_CPINE_INE2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_SHIFT)) & SEMA4_CPINE_INE2_MASK)
40468#define SEMA4_CPINE_INE1_MASK (0x40U)
40469#define SEMA4_CPINE_INE1_SHIFT (6U)
40470/*! INE1
40471 * 0b0..The generation of the notification interrupt is disabled.
40472 * 0b1..The generation of the notification interrupt is enabled.
40473 */
40474#define SEMA4_CPINE_INE1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_SHIFT)) & SEMA4_CPINE_INE1_MASK)
40475#define SEMA4_CPINE_INE0_MASK (0x80U)
40476#define SEMA4_CPINE_INE0_SHIFT (7U)
40477/*! INE0
40478 * 0b0..The generation of the notification interrupt is disabled.
40479 * 0b1..The generation of the notification interrupt is enabled.
40480 */
40481#define SEMA4_CPINE_INE0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_SHIFT)) & SEMA4_CPINE_INE0_MASK)
40482#define SEMA4_CPINE_INE15_MASK (0x100U)
40483#define SEMA4_CPINE_INE15_SHIFT (8U)
40484/*! INE15 - Interrupt Request Notification Enable 15. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 15.
40485 * 0b0..The generation of the notification interrupt is disabled.
40486 * 0b1..The generation of the notification interrupt is enabled.
40487 */
40488#define SEMA4_CPINE_INE15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_SHIFT)) & SEMA4_CPINE_INE15_MASK)
40489#define SEMA4_CPINE_INE14_MASK (0x200U)
40490#define SEMA4_CPINE_INE14_SHIFT (9U)
40491/*! INE14 - Interrupt Request Notification Enable 14. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 14.
40492 * 0b0..The generation of the notification interrupt is disabled.
40493 * 0b1..The generation of the notification interrupt is enabled.
40494 */
40495#define SEMA4_CPINE_INE14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_SHIFT)) & SEMA4_CPINE_INE14_MASK)
40496#define SEMA4_CPINE_INE13_MASK (0x400U)
40497#define SEMA4_CPINE_INE13_SHIFT (10U)
40498/*! INE13 - Interrupt Request Notification Enable 13. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 13.
40499 * 0b0..The generation of the notification interrupt is disabled.
40500 * 0b1..The generation of the notification interrupt is enabled.
40501 */
40502#define SEMA4_CPINE_INE13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_SHIFT)) & SEMA4_CPINE_INE13_MASK)
40503#define SEMA4_CPINE_INE12_MASK (0x800U)
40504#define SEMA4_CPINE_INE12_SHIFT (11U)
40505/*! INE12 - Interrupt Request Notification Enable 12. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 12.
40506 * 0b0..The generation of the notification interrupt is disabled.
40507 * 0b1..The generation of the notification interrupt is enabled.
40508 */
40509#define SEMA4_CPINE_INE12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_SHIFT)) & SEMA4_CPINE_INE12_MASK)
40510#define SEMA4_CPINE_INE11_MASK (0x1000U)
40511#define SEMA4_CPINE_INE11_SHIFT (12U)
40512/*! INE11 - Interrupt Request Notification Enable 11. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 11.
40513 * 0b0..The generation of the notification interrupt is disabled.
40514 * 0b1..The generation of the notification interrupt is enabled.
40515 */
40516#define SEMA4_CPINE_INE11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_SHIFT)) & SEMA4_CPINE_INE11_MASK)
40517#define SEMA4_CPINE_INE10_MASK (0x2000U)
40518#define SEMA4_CPINE_INE10_SHIFT (13U)
40519/*! INE10 - Interrupt Request Notification Enable 10. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 10.
40520 * 0b0..The generation of the notification interrupt is disabled.
40521 * 0b1..The generation of the notification interrupt is enabled.
40522 */
40523#define SEMA4_CPINE_INE10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_SHIFT)) & SEMA4_CPINE_INE10_MASK)
40524#define SEMA4_CPINE_INE9_MASK (0x4000U)
40525#define SEMA4_CPINE_INE9_SHIFT (14U)
40526/*! INE9 - Interrupt Request Notification Enable 9. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 9.
40527 * 0b0..The generation of the notification interrupt is disabled.
40528 * 0b1..The generation of the notification interrupt is enabled.
40529 */
40530#define SEMA4_CPINE_INE9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_SHIFT)) & SEMA4_CPINE_INE9_MASK)
40531#define SEMA4_CPINE_INE8_MASK (0x8000U)
40532#define SEMA4_CPINE_INE8_SHIFT (15U)
40533/*! INE8 - Interrupt Request Notification Enable 8. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 8.
40534 * 0b0..The generation of the notification interrupt is disabled.
40535 * 0b1..The generation of the notification interrupt is enabled.
40536 */
40537#define SEMA4_CPINE_INE8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_SHIFT)) & SEMA4_CPINE_INE8_MASK)
40538/*! @} */
40539
40540/* The count of SEMA4_CPINE */
40541#define SEMA4_CPINE_COUNT (2U)
40542
40543/*! @name CPNTF - Semaphores Processor n IRQ Notification */
40544/*! @{ */
40545#define SEMA4_CPNTF_GN7_MASK (0x1U)
40546#define SEMA4_CPNTF_GN7_SHIFT (0U)
40547#define SEMA4_CPNTF_GN7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN7_SHIFT)) & SEMA4_CPNTF_GN7_MASK)
40548#define SEMA4_CPNTF_GN6_MASK (0x2U)
40549#define SEMA4_CPNTF_GN6_SHIFT (1U)
40550#define SEMA4_CPNTF_GN6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN6_SHIFT)) & SEMA4_CPNTF_GN6_MASK)
40551#define SEMA4_CPNTF_GN5_MASK (0x4U)
40552#define SEMA4_CPNTF_GN5_SHIFT (2U)
40553#define SEMA4_CPNTF_GN5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN5_SHIFT)) & SEMA4_CPNTF_GN5_MASK)
40554#define SEMA4_CPNTF_GN4_MASK (0x8U)
40555#define SEMA4_CPNTF_GN4_SHIFT (3U)
40556#define SEMA4_CPNTF_GN4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN4_SHIFT)) & SEMA4_CPNTF_GN4_MASK)
40557#define SEMA4_CPNTF_GN3_MASK (0x10U)
40558#define SEMA4_CPNTF_GN3_SHIFT (4U)
40559#define SEMA4_CPNTF_GN3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN3_SHIFT)) & SEMA4_CPNTF_GN3_MASK)
40560#define SEMA4_CPNTF_GN2_MASK (0x20U)
40561#define SEMA4_CPNTF_GN2_SHIFT (5U)
40562#define SEMA4_CPNTF_GN2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN2_SHIFT)) & SEMA4_CPNTF_GN2_MASK)
40563#define SEMA4_CPNTF_GN1_MASK (0x40U)
40564#define SEMA4_CPNTF_GN1_SHIFT (6U)
40565#define SEMA4_CPNTF_GN1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN1_SHIFT)) & SEMA4_CPNTF_GN1_MASK)
40566#define SEMA4_CPNTF_GN0_MASK (0x80U)
40567#define SEMA4_CPNTF_GN0_SHIFT (7U)
40568#define SEMA4_CPNTF_GN0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN0_SHIFT)) & SEMA4_CPNTF_GN0_MASK)
40569#define SEMA4_CPNTF_GN15_MASK (0x100U)
40570#define SEMA4_CPNTF_GN15_SHIFT (8U)
40571#define SEMA4_CPNTF_GN15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN15_SHIFT)) & SEMA4_CPNTF_GN15_MASK)
40572#define SEMA4_CPNTF_GN14_MASK (0x200U)
40573#define SEMA4_CPNTF_GN14_SHIFT (9U)
40574#define SEMA4_CPNTF_GN14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN14_SHIFT)) & SEMA4_CPNTF_GN14_MASK)
40575#define SEMA4_CPNTF_GN13_MASK (0x400U)
40576#define SEMA4_CPNTF_GN13_SHIFT (10U)
40577#define SEMA4_CPNTF_GN13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN13_SHIFT)) & SEMA4_CPNTF_GN13_MASK)
40578#define SEMA4_CPNTF_GN12_MASK (0x800U)
40579#define SEMA4_CPNTF_GN12_SHIFT (11U)
40580#define SEMA4_CPNTF_GN12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN12_SHIFT)) & SEMA4_CPNTF_GN12_MASK)
40581#define SEMA4_CPNTF_GN11_MASK (0x1000U)
40582#define SEMA4_CPNTF_GN11_SHIFT (12U)
40583#define SEMA4_CPNTF_GN11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN11_SHIFT)) & SEMA4_CPNTF_GN11_MASK)
40584#define SEMA4_CPNTF_GN10_MASK (0x2000U)
40585#define SEMA4_CPNTF_GN10_SHIFT (13U)
40586#define SEMA4_CPNTF_GN10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN10_SHIFT)) & SEMA4_CPNTF_GN10_MASK)
40587#define SEMA4_CPNTF_GN9_MASK (0x4000U)
40588#define SEMA4_CPNTF_GN9_SHIFT (14U)
40589#define SEMA4_CPNTF_GN9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN9_SHIFT)) & SEMA4_CPNTF_GN9_MASK)
40590#define SEMA4_CPNTF_GN8_MASK (0x8000U)
40591#define SEMA4_CPNTF_GN8_SHIFT (15U)
40592#define SEMA4_CPNTF_GN8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN8_SHIFT)) & SEMA4_CPNTF_GN8_MASK)
40593/*! @} */
40594
40595/* The count of SEMA4_CPNTF */
40596#define SEMA4_CPNTF_COUNT (2U)
40597
40598/*! @name RSTGT - Semaphores (Secure) Reset Gate n */
40599/*! @{ */
40600#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK (0xFFU)
40601#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT (0U)
40602#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT)) & SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK)
40603#define SEMA4_RSTGT_RSTGTN_MASK (0xFF00U)
40604#define SEMA4_RSTGT_RSTGTN_SHIFT (8U)
40605#define SEMA4_RSTGT_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGTN_SHIFT)) & SEMA4_RSTGT_RSTGTN_MASK)
40606/*! @} */
40607
40608/*! @name RSTNTF - Semaphores (Secure) Reset IRQ Notification */
40609/*! @{ */
40610#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK (0xFFU)
40611#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT (0U)
40612#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT)) & SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK)
40613#define SEMA4_RSTNTF_RSTNTN_MASK (0xFF00U)
40614#define SEMA4_RSTNTF_RSTNTN_SHIFT (8U)
40615#define SEMA4_RSTNTF_RSTNTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNTN_SHIFT)) & SEMA4_RSTNTF_RSTNTN_MASK)
40616/*! @} */
40617
40618
40619/*!
40620 * @}
40621 */ /* end of group SEMA4_Register_Masks */
40622
40623
40624/* SEMA4 - Peripheral instance base addresses */
40625/** Peripheral SEMA4 base address */
40626#define SEMA4_BASE (0x30AC0000u)
40627/** Peripheral SEMA4 base pointer */
40628#define SEMA4 ((SEMA4_Type *)SEMA4_BASE)
40629/** Array initializer of SEMA4 peripheral base addresses */
40630#define SEMA4_BASE_ADDRS { SEMA4_BASE }
40631/** Array initializer of SEMA4 peripheral base pointers */
40632#define SEMA4_BASE_PTRS { SEMA4 }
40633
40634/*!
40635 * @}
40636 */ /* end of group SEMA4_Peripheral_Access_Layer */
40637
40638
40639/* ----------------------------------------------------------------------------
40640 -- SNVS Peripheral Access Layer
40641 ---------------------------------------------------------------------------- */
40642
40643/*!
40644 * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer
40645 * @{
40646 */
40647
40648/** SNVS - Register Layout Typedef */
40649typedef struct {
40650 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */
40651 __IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */
40652 __IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */
40653 __IO uint32_t HPSICR; /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */
40654 __IO uint32_t HPSVCR; /**< SNVS_HP Security Violation Control Register, offset: 0x10 */
40655 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */
40656 __IO uint32_t HPSVSR; /**< SNVS_HP Security Violation Status Register, offset: 0x18 */
40657 __IO uint32_t HPHACIVR; /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */
40658 __I uint32_t HPHACR; /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */
40659 __IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */
40660 __IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */
40661 __IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */
40662 __IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */
40663 __IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */
40664 __IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */
40665 __IO uint32_t LPMKCR; /**< SNVS_LP Master Key Control Register, offset: 0x3C */
40666 __IO uint32_t LPSVCR; /**< SNVS_LP Security Violation Control Register, offset: 0x40 */
40667 uint8_t RESERVED_0[4];
40668 __IO uint32_t LPSECR; /**< SNVS_LP Security Events Configuration Register, offset: 0x48 */
40669 __IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */
40670 __IO uint32_t LPSRTCMR; /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */
40671 __IO uint32_t LPSRTCLR; /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */
40672 __IO uint32_t LPTAR; /**< SNVS_LP Time Alarm Register, offset: 0x58 */
40673 __I uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */
40674 __I uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */
40675 __IO uint32_t LPPGDR; /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */
40676 __IO uint32_t LPGPR0_LEGACY_ALIAS; /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */
40677 __IO uint32_t LPZMKR[8]; /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */
40678 uint8_t RESERVED_1[4];
40679 __IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */
40680 uint8_t RESERVED_2[96];
40681 __IO uint32_t LPGPR[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x100, array step: 0x4 */
40682 uint8_t RESERVED_3[2792];
40683 __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */
40684 __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */
40685} SNVS_Type;
40686
40687/* ----------------------------------------------------------------------------
40688 -- SNVS Register Masks
40689 ---------------------------------------------------------------------------- */
40690
40691/*!
40692 * @addtogroup SNVS_Register_Masks SNVS Register Masks
40693 * @{
40694 */
40695
40696/*! @name HPLR - SNVS_HP Lock Register */
40697/*! @{ */
40698#define SNVS_HPLR_ZMK_WSL_MASK (0x1U)
40699#define SNVS_HPLR_ZMK_WSL_SHIFT (0U)
40700/*! ZMK_WSL
40701 * 0b0..Write access is allowed
40702 * 0b1..Write access is not allowed
40703 */
40704#define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
40705#define SNVS_HPLR_ZMK_RSL_MASK (0x2U)
40706#define SNVS_HPLR_ZMK_RSL_SHIFT (1U)
40707/*! ZMK_RSL
40708 * 0b0..Read access is allowed (only in software Programming mode)
40709 * 0b1..Read access is not allowed
40710 */
40711#define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
40712#define SNVS_HPLR_SRTC_SL_MASK (0x4U)
40713#define SNVS_HPLR_SRTC_SL_SHIFT (2U)
40714/*! SRTC_SL
40715 * 0b0..Write access is allowed
40716 * 0b1..Write access is not allowed
40717 */
40718#define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
40719#define SNVS_HPLR_LPCALB_SL_MASK (0x8U)
40720#define SNVS_HPLR_LPCALB_SL_SHIFT (3U)
40721/*! LPCALB_SL
40722 * 0b0..Write access is allowed
40723 * 0b1..Write access is not allowed
40724 */
40725#define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
40726#define SNVS_HPLR_MC_SL_MASK (0x10U)
40727#define SNVS_HPLR_MC_SL_SHIFT (4U)
40728/*! MC_SL
40729 * 0b0..Write access (increment) is allowed
40730 * 0b1..Write access (increment) is not allowed
40731 */
40732#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
40733#define SNVS_HPLR_GPR_SL_MASK (0x20U)
40734#define SNVS_HPLR_GPR_SL_SHIFT (5U)
40735/*! GPR_SL
40736 * 0b0..Write access is allowed
40737 * 0b1..Write access is not allowed
40738 */
40739#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
40740#define SNVS_HPLR_LPSVCR_SL_MASK (0x40U)
40741#define SNVS_HPLR_LPSVCR_SL_SHIFT (6U)
40742/*! LPSVCR_SL
40743 * 0b0..Write access is allowed
40744 * 0b1..Write access is not allowed
40745 */
40746#define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
40747#define SNVS_HPLR_LPSECR_SL_MASK (0x100U)
40748#define SNVS_HPLR_LPSECR_SL_SHIFT (8U)
40749/*! LPSECR_SL
40750 * 0b0..Write access is allowed
40751 * 0b1..Write access is not allowed
40752 */
40753#define SNVS_HPLR_LPSECR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSECR_SL_SHIFT)) & SNVS_HPLR_LPSECR_SL_MASK)
40754#define SNVS_HPLR_MKS_SL_MASK (0x200U)
40755#define SNVS_HPLR_MKS_SL_SHIFT (9U)
40756/*! MKS_SL
40757 * 0b0..Write access is allowed
40758 * 0b1..Write access is not allowed
40759 */
40760#define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
40761#define SNVS_HPLR_HPSVCR_L_MASK (0x10000U)
40762#define SNVS_HPLR_HPSVCR_L_SHIFT (16U)
40763/*! HPSVCR_L
40764 * 0b0..Write access is allowed
40765 * 0b1..Write access is not allowed
40766 */
40767#define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
40768#define SNVS_HPLR_HPSICR_L_MASK (0x20000U)
40769#define SNVS_HPLR_HPSICR_L_SHIFT (17U)
40770/*! HPSICR_L
40771 * 0b0..Write access is allowed
40772 * 0b1..Write access is not allowed
40773 */
40774#define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
40775#define SNVS_HPLR_HAC_L_MASK (0x40000U)
40776#define SNVS_HPLR_HAC_L_SHIFT (18U)
40777/*! HAC_L
40778 * 0b0..Write access is allowed
40779 * 0b1..Write access is not allowed
40780 */
40781#define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
40782/*! @} */
40783
40784/*! @name HPCOMR - SNVS_HP Command Register */
40785/*! @{ */
40786#define SNVS_HPCOMR_SSM_ST_MASK (0x1U)
40787#define SNVS_HPCOMR_SSM_ST_SHIFT (0U)
40788#define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
40789#define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U)
40790#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U)
40791/*! SSM_ST_DIS
40792 * 0b0..Secure to Trusted State transition is enabled
40793 * 0b1..Secure to Trusted State transition is disabled
40794 */
40795#define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
40796#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U)
40797#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U)
40798/*! SSM_SFNS_DIS
40799 * 0b0..Soft Fail to Non-Secure State transition is enabled
40800 * 0b1..Soft Fail to Non-Secure State transition is disabled
40801 */
40802#define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
40803#define SNVS_HPCOMR_LP_SWR_MASK (0x10U)
40804#define SNVS_HPCOMR_LP_SWR_SHIFT (4U)
40805/*! LP_SWR
40806 * 0b0..No Action
40807 * 0b1..Reset LP section
40808 */
40809#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
40810#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)
40811#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)
40812/*! LP_SWR_DIS
40813 * 0b0..LP software reset is enabled
40814 * 0b1..LP software reset is disabled
40815 */
40816#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
40817#define SNVS_HPCOMR_SW_SV_MASK (0x100U)
40818#define SNVS_HPCOMR_SW_SV_SHIFT (8U)
40819#define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)
40820#define SNVS_HPCOMR_SW_FSV_MASK (0x200U)
40821#define SNVS_HPCOMR_SW_FSV_SHIFT (9U)
40822#define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)
40823#define SNVS_HPCOMR_SW_LPSV_MASK (0x400U)
40824#define SNVS_HPCOMR_SW_LPSV_SHIFT (10U)
40825#define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
40826#define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U)
40827#define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U)
40828/*! PROG_ZMK
40829 * 0b0..No Action
40830 * 0b1..Activate hardware key programming mechanism
40831 */
40832#define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
40833#define SNVS_HPCOMR_MKS_EN_MASK (0x2000U)
40834#define SNVS_HPCOMR_MKS_EN_SHIFT (13U)
40835#define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
40836#define SNVS_HPCOMR_HAC_EN_MASK (0x10000U)
40837#define SNVS_HPCOMR_HAC_EN_SHIFT (16U)
40838/*! HAC_EN
40839 * 0b0..High Assurance Counter is disabled
40840 * 0b1..High Assurance Counter is enabled
40841 */
40842#define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
40843#define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U)
40844#define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U)
40845/*! HAC_LOAD
40846 * 0b0..No Action
40847 * 0b1..Load the HAC
40848 */
40849#define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
40850#define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U)
40851#define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U)
40852/*! HAC_CLEAR
40853 * 0b0..No Action
40854 * 0b1..Clear the HAC
40855 */
40856#define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
40857#define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U)
40858#define SNVS_HPCOMR_HAC_STOP_SHIFT (19U)
40859#define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)
40860#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)
40861#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)
40862#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
40863/*! @} */
40864
40865/*! @name HPCR - SNVS_HP Control Register */
40866/*! @{ */
40867#define SNVS_HPCR_RTC_EN_MASK (0x1U)
40868#define SNVS_HPCR_RTC_EN_SHIFT (0U)
40869/*! RTC_EN
40870 * 0b0..RTC is disabled
40871 * 0b1..RTC is enabled
40872 */
40873#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
40874#define SNVS_HPCR_HPTA_EN_MASK (0x2U)
40875#define SNVS_HPCR_HPTA_EN_SHIFT (1U)
40876/*! HPTA_EN
40877 * 0b0..HP Time Alarm Interrupt is disabled
40878 * 0b1..HP Time Alarm Interrupt is enabled
40879 */
40880#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
40881#define SNVS_HPCR_DIS_PI_MASK (0x4U)
40882#define SNVS_HPCR_DIS_PI_SHIFT (2U)
40883/*! DIS_PI
40884 * 0b0..Periodic interrupt will trigger a functional interrupt
40885 * 0b1..Disable periodic interrupt in the function interrupt
40886 */
40887#define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
40888#define SNVS_HPCR_PI_EN_MASK (0x8U)
40889#define SNVS_HPCR_PI_EN_SHIFT (3U)
40890/*! PI_EN
40891 * 0b0..HP Periodic Interrupt is disabled
40892 * 0b1..HP Periodic Interrupt is enabled
40893 */
40894#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
40895#define SNVS_HPCR_PI_FREQ_MASK (0xF0U)
40896#define SNVS_HPCR_PI_FREQ_SHIFT (4U)
40897/*! PI_FREQ
40898 * 0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt
40899 * 0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt
40900 * 0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt
40901 * 0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt
40902 * 0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt
40903 * 0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt
40904 * 0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt
40905 * 0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt
40906 * 0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt
40907 * 0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt
40908 * 0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt
40909 * 0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt
40910 * 0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt
40911 * 0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt
40912 * 0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt
40913 * 0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt
40914 */
40915#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
40916#define SNVS_HPCR_HPCALB_EN_MASK (0x100U)
40917#define SNVS_HPCR_HPCALB_EN_SHIFT (8U)
40918/*! HPCALB_EN
40919 * 0b0..HP Timer calibration disabled
40920 * 0b1..HP Timer calibration enabled
40921 */
40922#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
40923#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)
40924#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U)
40925/*! HPCALB_VAL
40926 * 0b00000..+0 counts per each 32768 ticks of the counter
40927 * 0b00001..+1 counts per each 32768 ticks of the counter
40928 * 0b00010..+2 counts per each 32768 ticks of the counter
40929 * 0b01111..+15 counts per each 32768 ticks of the counter
40930 * 0b10000..-16 counts per each 32768 ticks of the counter
40931 * 0b10001..-15 counts per each 32768 ticks of the counter
40932 * 0b11110..-2 counts per each 32768 ticks of the counter
40933 * 0b11111..-1 counts per each 32768 ticks of the counter
40934 */
40935#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
40936#define SNVS_HPCR_HP_TS_MASK (0x10000U)
40937#define SNVS_HPCR_HP_TS_SHIFT (16U)
40938/*! HP_TS
40939 * 0b0..No Action
40940 * 0b1..Synchronize the HP Time Counter to the LP Time Counter
40941 */
40942#define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
40943#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)
40944#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U)
40945#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
40946#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U)
40947#define SNVS_HPCR_BTN_MASK_SHIFT (27U)
40948#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
40949/*! @} */
40950
40951/*! @name HPSICR - SNVS_HP Security Interrupt Control Register */
40952/*! @{ */
40953#define SNVS_HPSICR_SV0_EN_MASK (0x1U)
40954#define SNVS_HPSICR_SV0_EN_SHIFT (0U)
40955/*! SV0_EN
40956 * 0b0..Security Violation 0 Interrupt is Disabled
40957 * 0b1..Security Violation 0 Interrupt is Enabled
40958 */
40959#define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)
40960#define SNVS_HPSICR_SV1_EN_MASK (0x2U)
40961#define SNVS_HPSICR_SV1_EN_SHIFT (1U)
40962/*! SV1_EN
40963 * 0b0..Security Violation 1 Interrupt is Disabled
40964 * 0b1..Security Violation 1 Interrupt is Enabled
40965 */
40966#define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)
40967#define SNVS_HPSICR_SV2_EN_MASK (0x4U)
40968#define SNVS_HPSICR_SV2_EN_SHIFT (2U)
40969/*! SV2_EN
40970 * 0b0..Security Violation 2 Interrupt is Disabled
40971 * 0b1..Security Violation 2 Interrupt is Enabled
40972 */
40973#define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)
40974#define SNVS_HPSICR_SV3_EN_MASK (0x8U)
40975#define SNVS_HPSICR_SV3_EN_SHIFT (3U)
40976/*! SV3_EN
40977 * 0b0..Security Violation 3 Interrupt is Disabled
40978 * 0b1..Security Violation 3 Interrupt is Enabled
40979 */
40980#define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)
40981#define SNVS_HPSICR_SV4_EN_MASK (0x10U)
40982#define SNVS_HPSICR_SV4_EN_SHIFT (4U)
40983/*! SV4_EN
40984 * 0b0..Security Violation 4 Interrupt is Disabled
40985 * 0b1..Security Violation 4 Interrupt is Enabled
40986 */
40987#define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)
40988#define SNVS_HPSICR_SV5_EN_MASK (0x20U)
40989#define SNVS_HPSICR_SV5_EN_SHIFT (5U)
40990/*! SV5_EN
40991 * 0b0..Security Violation 5 Interrupt is Disabled
40992 * 0b1..Security Violation 5 Interrupt is Enabled
40993 */
40994#define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)
40995#define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U)
40996#define SNVS_HPSICR_LPSVI_EN_SHIFT (31U)
40997/*! LPSVI_EN
40998 * 0b0..LP Security Violation Interrupt is Disabled
40999 * 0b1..LP Security Violation Interrupt is Enabled
41000 */
41001#define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
41002/*! @} */
41003
41004/*! @name HPSVCR - SNVS_HP Security Violation Control Register */
41005/*! @{ */
41006#define SNVS_HPSVCR_SV0_CFG_MASK (0x1U)
41007#define SNVS_HPSVCR_SV0_CFG_SHIFT (0U)
41008/*! SV0_CFG
41009 * 0b0..Security Violation 0 is a non-fatal violation
41010 * 0b1..Security Violation 0 is a fatal violation
41011 */
41012#define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)
41013#define SNVS_HPSVCR_SV1_CFG_MASK (0x2U)
41014#define SNVS_HPSVCR_SV1_CFG_SHIFT (1U)
41015/*! SV1_CFG
41016 * 0b0..Security Violation 1 is a non-fatal violation
41017 * 0b1..Security Violation 1 is a fatal violation
41018 */
41019#define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)
41020#define SNVS_HPSVCR_SV2_CFG_MASK (0x4U)
41021#define SNVS_HPSVCR_SV2_CFG_SHIFT (2U)
41022/*! SV2_CFG
41023 * 0b0..Security Violation 2 is a non-fatal violation
41024 * 0b1..Security Violation 2 is a fatal violation
41025 */
41026#define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)
41027#define SNVS_HPSVCR_SV3_CFG_MASK (0x8U)
41028#define SNVS_HPSVCR_SV3_CFG_SHIFT (3U)
41029/*! SV3_CFG
41030 * 0b0..Security Violation 3 is a non-fatal violation
41031 * 0b1..Security Violation 3 is a fatal violation
41032 */
41033#define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)
41034#define SNVS_HPSVCR_SV4_CFG_MASK (0x10U)
41035#define SNVS_HPSVCR_SV4_CFG_SHIFT (4U)
41036/*! SV4_CFG
41037 * 0b0..Security Violation 4 is a non-fatal violation
41038 * 0b1..Security Violation 4 is a fatal violation
41039 */
41040#define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)
41041#define SNVS_HPSVCR_SV5_CFG_MASK (0x60U)
41042#define SNVS_HPSVCR_SV5_CFG_SHIFT (5U)
41043/*! SV5_CFG
41044 * 0b00..Security Violation 5 is disabled
41045 * 0b01..Security Violation 5 is a non-fatal violation
41046 * 0b1x..Security Violation 5 is a fatal violation
41047 */
41048#define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)
41049#define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U)
41050#define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U)
41051/*! LPSV_CFG
41052 * 0b00..LP security violation is disabled
41053 * 0b01..LP security violation is a non-fatal violation
41054 * 0b1x..LP security violation is a fatal violation
41055 */
41056#define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
41057/*! @} */
41058
41059/*! @name HPSR - SNVS_HP Status Register */
41060/*! @{ */
41061#define SNVS_HPSR_HPTA_MASK (0x1U)
41062#define SNVS_HPSR_HPTA_SHIFT (0U)
41063/*! HPTA
41064 * 0b0..No time alarm interrupt occurred.
41065 * 0b1..A time alarm interrupt occurred.
41066 */
41067#define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
41068#define SNVS_HPSR_PI_MASK (0x2U)
41069#define SNVS_HPSR_PI_SHIFT (1U)
41070/*! PI
41071 * 0b0..No periodic interrupt occurred.
41072 * 0b1..A periodic interrupt occurred.
41073 */
41074#define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
41075#define SNVS_HPSR_LPDIS_MASK (0x10U)
41076#define SNVS_HPSR_LPDIS_SHIFT (4U)
41077#define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
41078#define SNVS_HPSR_BTN_MASK (0x40U)
41079#define SNVS_HPSR_BTN_SHIFT (6U)
41080#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
41081#define SNVS_HPSR_BI_MASK (0x80U)
41082#define SNVS_HPSR_BI_SHIFT (7U)
41083#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
41084#define SNVS_HPSR_SSM_STATE_MASK (0xF00U)
41085#define SNVS_HPSR_SSM_STATE_SHIFT (8U)
41086/*! SSM_STATE
41087 * 0b0000..Init
41088 * 0b0001..Hard Fail
41089 * 0b0011..Soft Fail
41090 * 0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle)
41091 * 0b1001..Check
41092 * 0b1011..Non-Secure
41093 * 0b1101..Trusted
41094 * 0b1111..Secure
41095 */
41096#define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
41097#define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U)
41098#define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U)
41099/*! SECURITY_CONFIG
41100 * 0b0000, 0b1000..FAB configuration
41101 * 0b0001, 0b0010, 0b0011..OPEN configuration
41102 * 0b1010, 0b1001, 0b1011..CLOSED configuration
41103 * 0bx1xx..FIELD RETURN configuration
41104 */
41105#define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK)
41106#define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U)
41107#define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U)
41108#define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)
41109#define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U)
41110#define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U)
41111/*! OTPMK_ZERO
41112 * 0b0..The OTPMK is not zero.
41113 * 0b1..The OTPMK is zero.
41114 */
41115#define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
41116#define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U)
41117#define SNVS_HPSR_ZMK_ZERO_SHIFT (31U)
41118/*! ZMK_ZERO
41119 * 0b0..The ZMK is not zero.
41120 * 0b1..The ZMK is zero.
41121 */
41122#define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
41123/*! @} */
41124
41125/*! @name HPSVSR - SNVS_HP Security Violation Status Register */
41126/*! @{ */
41127#define SNVS_HPSVSR_SV0_MASK (0x1U)
41128#define SNVS_HPSVSR_SV0_SHIFT (0U)
41129/*! SV0
41130 * 0b0..No Security Violation 0 security violation was detected.
41131 * 0b1..Security Violation 0 security violation was detected.
41132 */
41133#define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)
41134#define SNVS_HPSVSR_SV1_MASK (0x2U)
41135#define SNVS_HPSVSR_SV1_SHIFT (1U)
41136/*! SV1
41137 * 0b0..No Security Violation 1 security violation was detected.
41138 * 0b1..Security Violation 1 security violation was detected.
41139 */
41140#define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)
41141#define SNVS_HPSVSR_SV2_MASK (0x4U)
41142#define SNVS_HPSVSR_SV2_SHIFT (2U)
41143/*! SV2
41144 * 0b0..No Security Violation 2 security violation was detected.
41145 * 0b1..Security Violation 2 security violation was detected.
41146 */
41147#define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)
41148#define SNVS_HPSVSR_SV3_MASK (0x8U)
41149#define SNVS_HPSVSR_SV3_SHIFT (3U)
41150/*! SV3
41151 * 0b0..No Security Violation 3 security violation was detected.
41152 * 0b1..Security Violation 3 security violation was detected.
41153 */
41154#define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)
41155#define SNVS_HPSVSR_SV4_MASK (0x10U)
41156#define SNVS_HPSVSR_SV4_SHIFT (4U)
41157/*! SV4
41158 * 0b0..No Security Violation 4 security violation was detected.
41159 * 0b1..Security Violation 4 security violation was detected.
41160 */
41161#define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)
41162#define SNVS_HPSVSR_SV5_MASK (0x20U)
41163#define SNVS_HPSVSR_SV5_SHIFT (5U)
41164/*! SV5
41165 * 0b0..No Security Violation 5 security violation was detected.
41166 * 0b1..Security Violation 5 security violation was detected.
41167 */
41168#define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
41169#define SNVS_HPSVSR_SW_SV_MASK (0x2000U)
41170#define SNVS_HPSVSR_SW_SV_SHIFT (13U)
41171#define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)
41172#define SNVS_HPSVSR_SW_FSV_MASK (0x4000U)
41173#define SNVS_HPSVSR_SW_FSV_SHIFT (14U)
41174#define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)
41175#define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U)
41176#define SNVS_HPSVSR_SW_LPSV_SHIFT (15U)
41177#define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)
41178#define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U)
41179#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U)
41180#define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
41181#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U)
41182#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U)
41183/*! ZMK_ECC_FAIL
41184 * 0b0..ZMK ECC Failure was not detected.
41185 * 0b1..ZMK ECC Failure was detected.
41186 */
41187#define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
41188#define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U)
41189#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U)
41190#define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)
41191/*! @} */
41192
41193/*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */
41194/*! @{ */
41195#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU)
41196#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U)
41197#define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
41198/*! @} */
41199
41200/*! @name HPHACR - SNVS_HP High Assurance Counter Register */
41201/*! @{ */
41202#define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU)
41203#define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U)
41204#define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)
41205/*! @} */
41206
41207/*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */
41208/*! @{ */
41209#define SNVS_HPRTCMR_RTC_MASK (0x7FFFU)
41210#define SNVS_HPRTCMR_RTC_SHIFT (0U)
41211#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
41212/*! @} */
41213
41214/*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */
41215/*! @{ */
41216#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)
41217#define SNVS_HPRTCLR_RTC_SHIFT (0U)
41218#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
41219/*! @} */
41220
41221/*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */
41222/*! @{ */
41223#define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)
41224#define SNVS_HPTAMR_HPTA_MS_SHIFT (0U)
41225#define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
41226/*! @} */
41227
41228/*! @name HPTALR - SNVS_HP Time Alarm LSB Register */
41229/*! @{ */
41230#define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)
41231#define SNVS_HPTALR_HPTA_LS_SHIFT (0U)
41232#define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
41233/*! @} */
41234
41235/*! @name LPLR - SNVS_LP Lock Register */
41236/*! @{ */
41237#define SNVS_LPLR_ZMK_WHL_MASK (0x1U)
41238#define SNVS_LPLR_ZMK_WHL_SHIFT (0U)
41239/*! ZMK_WHL
41240 * 0b0..Write access is allowed.
41241 * 0b1..Write access is not allowed.
41242 */
41243#define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
41244#define SNVS_LPLR_ZMK_RHL_MASK (0x2U)
41245#define SNVS_LPLR_ZMK_RHL_SHIFT (1U)
41246/*! ZMK_RHL
41247 * 0b0..Read access is allowed (only in software programming mode).
41248 * 0b1..Read access is not allowed.
41249 */
41250#define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
41251#define SNVS_LPLR_SRTC_HL_MASK (0x4U)
41252#define SNVS_LPLR_SRTC_HL_SHIFT (2U)
41253/*! SRTC_HL
41254 * 0b0..Write access is allowed.
41255 * 0b1..Write access is not allowed.
41256 */
41257#define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
41258#define SNVS_LPLR_LPCALB_HL_MASK (0x8U)
41259#define SNVS_LPLR_LPCALB_HL_SHIFT (3U)
41260/*! LPCALB_HL
41261 * 0b0..Write access is allowed.
41262 * 0b1..Write access is not allowed.
41263 */
41264#define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
41265#define SNVS_LPLR_MC_HL_MASK (0x10U)
41266#define SNVS_LPLR_MC_HL_SHIFT (4U)
41267/*! MC_HL
41268 * 0b0..Write access (increment) is allowed.
41269 * 0b1..Write access (increment) is not allowed.
41270 */
41271#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
41272#define SNVS_LPLR_GPR_HL_MASK (0x20U)
41273#define SNVS_LPLR_GPR_HL_SHIFT (5U)
41274/*! GPR_HL
41275 * 0b0..Write access is allowed.
41276 * 0b1..Write access is not allowed.
41277 */
41278#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
41279#define SNVS_LPLR_LPSVCR_HL_MASK (0x40U)
41280#define SNVS_LPLR_LPSVCR_HL_SHIFT (6U)
41281/*! LPSVCR_HL
41282 * 0b0..Write access is allowed.
41283 * 0b1..Write access is not allowed.
41284 */
41285#define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
41286#define SNVS_LPLR_LPSECR_HL_MASK (0x100U)
41287#define SNVS_LPLR_LPSECR_HL_SHIFT (8U)
41288/*! LPSECR_HL
41289 * 0b0..Write access is allowed.
41290 * 0b1..Write access is not allowed.
41291 */
41292#define SNVS_LPLR_LPSECR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSECR_HL_SHIFT)) & SNVS_LPLR_LPSECR_HL_MASK)
41293#define SNVS_LPLR_MKS_HL_MASK (0x200U)
41294#define SNVS_LPLR_MKS_HL_SHIFT (9U)
41295/*! MKS_HL
41296 * 0b0..Write access is allowed.
41297 * 0b1..Write access is not allowed.
41298 */
41299#define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
41300/*! @} */
41301
41302/*! @name LPCR - SNVS_LP Control Register */
41303/*! @{ */
41304#define SNVS_LPCR_SRTC_ENV_MASK (0x1U)
41305#define SNVS_LPCR_SRTC_ENV_SHIFT (0U)
41306/*! SRTC_ENV
41307 * 0b0..SRTC is disabled or invalid.
41308 * 0b1..SRTC is enabled and valid.
41309 */
41310#define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
41311#define SNVS_LPCR_LPTA_EN_MASK (0x2U)
41312#define SNVS_LPCR_LPTA_EN_SHIFT (1U)
41313/*! LPTA_EN
41314 * 0b0..LP time alarm interrupt is disabled.
41315 * 0b1..LP time alarm interrupt is enabled.
41316 */
41317#define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
41318#define SNVS_LPCR_MC_ENV_MASK (0x4U)
41319#define SNVS_LPCR_MC_ENV_SHIFT (2U)
41320/*! MC_ENV
41321 * 0b0..MC is disabled or invalid.
41322 * 0b1..MC is enabled and valid.
41323 */
41324#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
41325#define SNVS_LPCR_LPWUI_EN_MASK (0x8U)
41326#define SNVS_LPCR_LPWUI_EN_SHIFT (3U)
41327#define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
41328#define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U)
41329#define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U)
41330/*! SRTC_INV_EN
41331 * 0b0..SRTC stays valid in the case of security violation.
41332 * 0b1..SRTC is invalidated in the case of security violation.
41333 */
41334#define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
41335#define SNVS_LPCR_DP_EN_MASK (0x20U)
41336#define SNVS_LPCR_DP_EN_SHIFT (5U)
41337/*! DP_EN
41338 * 0b0..Smart PMIC enabled.
41339 * 0b1..Dumb PMIC enabled.
41340 */
41341#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
41342#define SNVS_LPCR_TOP_MASK (0x40U)
41343#define SNVS_LPCR_TOP_SHIFT (6U)
41344/*! TOP
41345 * 0b0..Leave system power on.
41346 * 0b1..Turn off system power.
41347 */
41348#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
41349#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U)
41350#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U)
41351#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK)
41352#define SNVS_LPCR_LPCALB_EN_MASK (0x100U)
41353#define SNVS_LPCR_LPCALB_EN_SHIFT (8U)
41354/*! LPCALB_EN
41355 * 0b0..SRTC Time calibration is disabled.
41356 * 0b1..SRTC Time calibration is enabled.
41357 */
41358#define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
41359#define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U)
41360#define SNVS_LPCR_LPCALB_VAL_SHIFT (10U)
41361/*! LPCALB_VAL
41362 * 0b00000..+0 counts per each 32768 ticks of the counter clock
41363 * 0b00001..+1 counts per each 32768 ticks of the counter clock
41364 * 0b00010..+2 counts per each 32768 ticks of the counter clock
41365 * 0b01111..+15 counts per each 32768 ticks of the counter clock
41366 * 0b10000..-16 counts per each 32768 ticks of the counter clock
41367 * 0b10001..-15 counts per each 32768 ticks of the counter clock
41368 * 0b11110..-2 counts per each 32768 ticks of the counter clock
41369 * 0b11111..-1 counts per each 32768 ticks of the counter clock
41370 */
41371#define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
41372#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)
41373#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)
41374#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
41375#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)
41376#define SNVS_LPCR_DEBOUNCE_SHIFT (18U)
41377#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
41378#define SNVS_LPCR_ON_TIME_MASK (0x300000U)
41379#define SNVS_LPCR_ON_TIME_SHIFT (20U)
41380#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
41381#define SNVS_LPCR_PK_EN_MASK (0x400000U)
41382#define SNVS_LPCR_PK_EN_SHIFT (22U)
41383#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
41384#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)
41385#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)
41386#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
41387#define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U)
41388#define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U)
41389#define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)
41390/*! @} */
41391
41392/*! @name LPMKCR - SNVS_LP Master Key Control Register */
41393/*! @{ */
41394#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U)
41395#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U)
41396/*! MASTER_KEY_SEL
41397 * 0b0x..Select one time programmable master key.
41398 */
41399#define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
41400#define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U)
41401#define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U)
41402/*! ZMK_HWP
41403 * 0b0..ZMK is in the software programming mode.
41404 * 0b1..ZMK is in the hardware programming mode.
41405 */
41406#define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
41407#define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U)
41408#define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U)
41409/*! ZMK_VAL
41410 * 0b0..ZMK is not valid.
41411 * 0b1..ZMK is valid.
41412 */
41413#define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
41414#define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U)
41415#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U)
41416/*! ZMK_ECC_EN
41417 * 0b0..ZMK ECC check is disabled.
41418 * 0b1..ZMK ECC check is enabled.
41419 */
41420#define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
41421#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U)
41422#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U)
41423#define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
41424/*! @} */
41425
41426/*! @name LPSVCR - SNVS_LP Security Violation Control Register */
41427/*! @{ */
41428#define SNVS_LPSVCR_SV0_EN_MASK (0x1U)
41429#define SNVS_LPSVCR_SV0_EN_SHIFT (0U)
41430/*! SV0_EN
41431 * 0b0..Security Violation 0 is disabled in the LP domain.
41432 * 0b1..Security Violation 0 is enabled in the LP domain.
41433 */
41434#define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)
41435#define SNVS_LPSVCR_SV1_EN_MASK (0x2U)
41436#define SNVS_LPSVCR_SV1_EN_SHIFT (1U)
41437/*! SV1_EN
41438 * 0b0..Security Violation 1 is disabled in the LP domain.
41439 * 0b1..Security Violation 1 is enabled in the LP domain.
41440 */
41441#define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)
41442#define SNVS_LPSVCR_SV2_EN_MASK (0x4U)
41443#define SNVS_LPSVCR_SV2_EN_SHIFT (2U)
41444/*! SV2_EN
41445 * 0b0..Security Violation 2 is disabled in the LP domain.
41446 * 0b1..Security Violation 2 is enabled in the LP domain.
41447 */
41448#define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)
41449#define SNVS_LPSVCR_SV3_EN_MASK (0x8U)
41450#define SNVS_LPSVCR_SV3_EN_SHIFT (3U)
41451/*! SV3_EN
41452 * 0b0..Security Violation 3 is disabled in the LP domain.
41453 * 0b1..Security Violation 3 is enabled in the LP domain.
41454 */
41455#define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)
41456#define SNVS_LPSVCR_SV4_EN_MASK (0x10U)
41457#define SNVS_LPSVCR_SV4_EN_SHIFT (4U)
41458/*! SV4_EN
41459 * 0b0..Security Violation 4 is disabled in the LP domain.
41460 * 0b1..Security Violation 4 is enabled in the LP domain.
41461 */
41462#define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)
41463#define SNVS_LPSVCR_SV5_EN_MASK (0x20U)
41464#define SNVS_LPSVCR_SV5_EN_SHIFT (5U)
41465/*! SV5_EN
41466 * 0b0..Security Violation 5 is disabled in the LP domain.
41467 * 0b1..Security Violation 5 is enabled in the LP domain.
41468 */
41469#define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)
41470/*! @} */
41471
41472/*! @name LPSECR - SNVS_LP Security Events Configuration Register */
41473/*! @{ */
41474#define SNVS_LPSECR_SRTCR_EN_MASK (0x2U)
41475#define SNVS_LPSECR_SRTCR_EN_SHIFT (1U)
41476/*! SRTCR_EN
41477 * 0b0..SRTC rollover is disabled.
41478 * 0b1..SRTC rollover is enabled.
41479 */
41480#define SNVS_LPSECR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_SRTCR_EN_SHIFT)) & SNVS_LPSECR_SRTCR_EN_MASK)
41481#define SNVS_LPSECR_MCR_EN_MASK (0x4U)
41482#define SNVS_LPSECR_MCR_EN_SHIFT (2U)
41483/*! MCR_EN
41484 * 0b0..MC rollover is disabled.
41485 * 0b1..MC rollover is enabled.
41486 */
41487#define SNVS_LPSECR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_MCR_EN_SHIFT)) & SNVS_LPSECR_MCR_EN_MASK)
41488#define SNVS_LPSECR_PFD_OBSERV_MASK (0x4000U)
41489#define SNVS_LPSECR_PFD_OBSERV_SHIFT (14U)
41490#define SNVS_LPSECR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_PFD_OBSERV_SHIFT)) & SNVS_LPSECR_PFD_OBSERV_MASK)
41491#define SNVS_LPSECR_POR_OBSERV_MASK (0x8000U)
41492#define SNVS_LPSECR_POR_OBSERV_SHIFT (15U)
41493#define SNVS_LPSECR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_POR_OBSERV_SHIFT)) & SNVS_LPSECR_POR_OBSERV_MASK)
41494#define SNVS_LPSECR_LTDC_MASK (0x70000U)
41495#define SNVS_LPSECR_LTDC_SHIFT (16U)
41496#define SNVS_LPSECR_LTDC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_LTDC_SHIFT)) & SNVS_LPSECR_LTDC_MASK)
41497#define SNVS_LPSECR_HTDC_MASK (0x700000U)
41498#define SNVS_LPSECR_HTDC_SHIFT (20U)
41499#define SNVS_LPSECR_HTDC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_HTDC_SHIFT)) & SNVS_LPSECR_HTDC_MASK)
41500#define SNVS_LPSECR_VRC_MASK (0x7000000U)
41501#define SNVS_LPSECR_VRC_SHIFT (24U)
41502#define SNVS_LPSECR_VRC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_VRC_SHIFT)) & SNVS_LPSECR_VRC_MASK)
41503#define SNVS_LPSECR_OSCB_MASK (0x10000000U)
41504#define SNVS_LPSECR_OSCB_SHIFT (28U)
41505/*! OSCB
41506 * 0b0..Normal SRTC clock oscillator not bypassed.
41507 * 0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source.
41508 */
41509#define SNVS_LPSECR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_OSCB_SHIFT)) & SNVS_LPSECR_OSCB_MASK)
41510/*! @} */
41511
41512/*! @name LPSR - SNVS_LP Status Register */
41513/*! @{ */
41514#define SNVS_LPSR_LPTA_MASK (0x1U)
41515#define SNVS_LPSR_LPTA_SHIFT (0U)
41516/*! LPTA
41517 * 0b0..No time alarm interrupt occurred.
41518 * 0b1..A time alarm interrupt occurred.
41519 */
41520#define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
41521#define SNVS_LPSR_SRTCR_MASK (0x2U)
41522#define SNVS_LPSR_SRTCR_SHIFT (1U)
41523/*! SRTCR
41524 * 0b0..SRTC has not reached its maximum value.
41525 * 0b1..SRTC has reached its maximum value.
41526 */
41527#define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
41528#define SNVS_LPSR_MCR_MASK (0x4U)
41529#define SNVS_LPSR_MCR_SHIFT (2U)
41530/*! MCR
41531 * 0b0..MC has not reached its maximum value.
41532 * 0b1..MC has reached its maximum value.
41533 */
41534#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
41535#define SNVS_LPSR_PGD_MASK (0x8U)
41536#define SNVS_LPSR_PGD_SHIFT (3U)
41537#define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK)
41538#define SNVS_LPSR_ESVD_MASK (0x10000U)
41539#define SNVS_LPSR_ESVD_SHIFT (16U)
41540/*! ESVD
41541 * 0b0..No external security violation.
41542 * 0b1..External security violation is detected.
41543 */
41544#define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
41545#define SNVS_LPSR_EO_MASK (0x20000U)
41546#define SNVS_LPSR_EO_SHIFT (17U)
41547/*! EO
41548 * 0b0..Emergency off was not detected.
41549 * 0b1..Emergency off was detected.
41550 */
41551#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
41552#define SNVS_LPSR_SPO_MASK (0x40000U)
41553#define SNVS_LPSR_SPO_SHIFT (18U)
41554/*! SPO
41555 * 0b0..Set Power Off was not detected.
41556 * 0b1..Set Power Off was detected.
41557 */
41558#define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK)
41559#define SNVS_LPSR_LPNS_MASK (0x40000000U)
41560#define SNVS_LPSR_LPNS_SHIFT (30U)
41561/*! LPNS
41562 * 0b0..LP section was not programmed in the non-secure state.
41563 * 0b1..LP section was programmed in the non-secure state.
41564 */
41565#define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
41566#define SNVS_LPSR_LPS_MASK (0x80000000U)
41567#define SNVS_LPSR_LPS_SHIFT (31U)
41568/*! LPS
41569 * 0b0..LP section was not programmed in secure or trusted state.
41570 * 0b1..LP section was programmed in secure or trusted state.
41571 */
41572#define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
41573/*! @} */
41574
41575/*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */
41576/*! @{ */
41577#define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU)
41578#define SNVS_LPSRTCMR_SRTC_SHIFT (0U)
41579#define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)
41580/*! @} */
41581
41582/*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */
41583/*! @{ */
41584#define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU)
41585#define SNVS_LPSRTCLR_SRTC_SHIFT (0U)
41586#define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)
41587/*! @} */
41588
41589/*! @name LPTAR - SNVS_LP Time Alarm Register */
41590/*! @{ */
41591#define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU)
41592#define SNVS_LPTAR_LPTA_SHIFT (0U)
41593#define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)
41594/*! @} */
41595
41596/*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */
41597/*! @{ */
41598#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)
41599#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)
41600#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
41601#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)
41602#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)
41603#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
41604/*! @} */
41605
41606/*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */
41607/*! @{ */
41608#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)
41609#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)
41610#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
41611/*! @} */
41612
41613/*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */
41614/*! @{ */
41615#define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU)
41616#define SNVS_LPPGDR_PGD_SHIFT (0U)
41617#define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK)
41618/*! @} */
41619
41620/*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */
41621/*! @{ */
41622#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)
41623#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)
41624#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
41625/*! @} */
41626
41627/*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */
41628/*! @{ */
41629#define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU)
41630#define SNVS_LPZMKR_ZMK_SHIFT (0U)
41631#define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)
41632/*! @} */
41633
41634/* The count of SNVS_LPZMKR */
41635#define SNVS_LPZMKR_COUNT (8U)
41636
41637/*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */
41638/*! @{ */
41639#define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)
41640#define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)
41641#define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
41642/*! @} */
41643
41644/* The count of SNVS_LPGPR_ALIAS */
41645#define SNVS_LPGPR_ALIAS_COUNT (4U)
41646
41647/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 3 */
41648/*! @{ */
41649#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)
41650#define SNVS_LPGPR_GPR_SHIFT (0U)
41651#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
41652/*! @} */
41653
41654/* The count of SNVS_LPGPR */
41655#define SNVS_LPGPR_COUNT (4U)
41656
41657/*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */
41658/*! @{ */
41659#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)
41660#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U)
41661#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
41662#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)
41663#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)
41664#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
41665#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)
41666#define SNVS_HPVIDR1_IP_ID_SHIFT (16U)
41667#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
41668/*! @} */
41669
41670/*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */
41671/*! @{ */
41672#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU)
41673#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U)
41674#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)
41675#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)
41676#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U)
41677#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
41678#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U)
41679#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U)
41680#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)
41681#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)
41682#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U)
41683#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)
41684/*! @} */
41685
41686
41687/*!
41688 * @}
41689 */ /* end of group SNVS_Register_Masks */
41690
41691
41692/* SNVS - Peripheral instance base addresses */
41693/** Peripheral SNVS base address */
41694#define SNVS_BASE (0x30370000u)
41695/** Peripheral SNVS base pointer */
41696#define SNVS ((SNVS_Type *)SNVS_BASE)
41697/** Array initializer of SNVS peripheral base addresses */
41698#define SNVS_BASE_ADDRS { SNVS_BASE }
41699/** Array initializer of SNVS peripheral base pointers */
41700#define SNVS_BASE_PTRS { SNVS }
41701/** Interrupt vectors for the SNVS peripheral type */
41702#define SNVS_IRQS { SNVS_IRQn }
41703#define SNVS_CONSOLIDATED_IRQS { SNVS_Consolidated_IRQn }
41704#define SNVS_SECURITY_IRQS { SNVS_Security_IRQn }
41705
41706/*!
41707 * @}
41708 */ /* end of group SNVS_Peripheral_Access_Layer */
41709
41710
41711/* ----------------------------------------------------------------------------
41712 -- SPBA Peripheral Access Layer
41713 ---------------------------------------------------------------------------- */
41714
41715/*!
41716 * @addtogroup SPBA_Peripheral_Access_Layer SPBA Peripheral Access Layer
41717 * @{
41718 */
41719
41720/** SPBA - Register Layout Typedef */
41721typedef struct {
41722 __IO uint32_t PRR[32]; /**< Peripheral Rights Register, array offset: 0x0, array step: 0x4 */
41723} SPBA_Type;
41724
41725/* ----------------------------------------------------------------------------
41726 -- SPBA Register Masks
41727 ---------------------------------------------------------------------------- */
41728
41729/*!
41730 * @addtogroup SPBA_Register_Masks SPBA Register Masks
41731 * @{
41732 */
41733
41734/*! @name PRR - Peripheral Rights Register */
41735/*! @{ */
41736#define SPBA_PRR_RARA_MASK (0x1U)
41737#define SPBA_PRR_RARA_SHIFT (0U)
41738/*! RARA
41739 * 0b0..Access to peripheral is not allowed.
41740 * 0b1..Access to peripheral is granted.
41741 */
41742#define SPBA_PRR_RARA(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARA_SHIFT)) & SPBA_PRR_RARA_MASK)
41743#define SPBA_PRR_RARB_MASK (0x2U)
41744#define SPBA_PRR_RARB_SHIFT (1U)
41745/*! RARB
41746 * 0b0..Access to peripheral is not allowed.
41747 * 0b1..Access to peripheral is granted.
41748 */
41749#define SPBA_PRR_RARB(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARB_SHIFT)) & SPBA_PRR_RARB_MASK)
41750#define SPBA_PRR_RARC_MASK (0x4U)
41751#define SPBA_PRR_RARC_SHIFT (2U)
41752/*! RARC
41753 * 0b0..Access to peripheral is not allowed.
41754 * 0b1..Access to peripheral is granted.
41755 */
41756#define SPBA_PRR_RARC(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARC_SHIFT)) & SPBA_PRR_RARC_MASK)
41757#define SPBA_PRR_ROI_MASK (0x30000U)
41758#define SPBA_PRR_ROI_SHIFT (16U)
41759/*! ROI
41760 * 0b00..Unowned resource.
41761 * 0b01..The resource is owned by master A port.
41762 * 0b10..The resource is owned by master B port.
41763 * 0b11..The resource is owned by master C port.
41764 */
41765#define SPBA_PRR_ROI(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_ROI_SHIFT)) & SPBA_PRR_ROI_MASK)
41766#define SPBA_PRR_RMO_MASK (0xC0000000U)
41767#define SPBA_PRR_RMO_SHIFT (30U)
41768/*! RMO
41769 * 0b00..The resource is unowned.
41770 * 0b01..Reserved.
41771 * 0b10..The resource is owned by another master.
41772 * 0b11..The resource is owned by the requesting master.
41773 */
41774#define SPBA_PRR_RMO(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RMO_SHIFT)) & SPBA_PRR_RMO_MASK)
41775/*! @} */
41776
41777/* The count of SPBA_PRR */
41778#define SPBA_PRR_COUNT (32U)
41779
41780
41781/*!
41782 * @}
41783 */ /* end of group SPBA_Register_Masks */
41784
41785
41786/* SPBA - Peripheral instance base addresses */
41787/** Peripheral SPBA1 base address */
41788#define SPBA1_BASE (0x308F0000u)
41789/** Peripheral SPBA1 base pointer */
41790#define SPBA1 ((SPBA_Type *)SPBA1_BASE)
41791/** Peripheral SPBA2 base address */
41792#define SPBA2_BASE (0x300F0000u)
41793/** Peripheral SPBA2 base pointer */
41794#define SPBA2 ((SPBA_Type *)SPBA2_BASE)
41795/** Array initializer of SPBA peripheral base addresses */
41796#define SPBA_BASE_ADDRS { 0u, SPBA1_BASE, SPBA2_BASE }
41797/** Array initializer of SPBA peripheral base pointers */
41798#define SPBA_BASE_PTRS { (SPBA_Type *)0u, SPBA1, SPBA2 }
41799
41800/*!
41801 * @}
41802 */ /* end of group SPBA_Peripheral_Access_Layer */
41803
41804
41805/* ----------------------------------------------------------------------------
41806 -- SPDIF Peripheral Access Layer
41807 ---------------------------------------------------------------------------- */
41808
41809/*!
41810 * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer
41811 * @{
41812 */
41813
41814/** SPDIF - Register Layout Typedef */
41815typedef struct {
41816 __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */
41817 __IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */
41818 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */
41819 __IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */
41820 union { /* offset: 0x10 */
41821 __O uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */
41822 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */
41823 };
41824 __I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */
41825 __I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */
41826 __I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */
41827 __I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */
41828 __I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */
41829 __I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */
41830 __O uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */
41831 __O uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */
41832 __IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */
41833 __IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */
41834 uint8_t RESERVED_0[8];
41835 __I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */
41836 uint8_t RESERVED_1[8];
41837 __IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */
41838} SPDIF_Type;
41839
41840/* ----------------------------------------------------------------------------
41841 -- SPDIF Register Masks
41842 ---------------------------------------------------------------------------- */
41843
41844/*!
41845 * @addtogroup SPDIF_Register_Masks SPDIF Register Masks
41846 * @{
41847 */
41848
41849/*! @name SCR - SPDIF Configuration Register */
41850/*! @{ */
41851#define SPDIF_SCR_USRC_SEL_MASK (0x3U)
41852#define SPDIF_SCR_USRC_SEL_SHIFT (0U)
41853/*! USrc_Sel
41854 * 0b00..No embedded U channel
41855 * 0b01..U channel from SPDIF receive block (CD mode)
41856 * 0b10..Reserved
41857 * 0b11..U channel from on chip transmitter
41858 */
41859#define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
41860#define SPDIF_SCR_TXSEL_MASK (0x1CU)
41861#define SPDIF_SCR_TXSEL_SHIFT (2U)
41862/*! TxSel
41863 * 0b000..Off and output 0
41864 * 0b001..Feed-through SPDIFIN
41865 * 0b101..Tx Normal operation
41866 */
41867#define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
41868#define SPDIF_SCR_VALCTRL_MASK (0x20U)
41869#define SPDIF_SCR_VALCTRL_SHIFT (5U)
41870/*! ValCtrl
41871 * 0b0..Outgoing Validity always set
41872 * 0b1..Outgoing Validity always clear
41873 */
41874#define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
41875#define SPDIF_SCR_DMA_TX_EN_MASK (0x100U)
41876#define SPDIF_SCR_DMA_TX_EN_SHIFT (8U)
41877#define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)
41878#define SPDIF_SCR_DMA_RX_EN_MASK (0x200U)
41879#define SPDIF_SCR_DMA_RX_EN_SHIFT (9U)
41880#define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
41881#define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U)
41882#define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U)
41883/*! TxFIFO_Ctrl
41884 * 0b00..Send out digital zero on SPDIF Tx
41885 * 0b01..Tx Normal operation
41886 * 0b10..Reset to 1 sample remaining
41887 * 0b11..Reserved
41888 */
41889#define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
41890#define SPDIF_SCR_SOFT_RESET_MASK (0x1000U)
41891#define SPDIF_SCR_SOFT_RESET_SHIFT (12U)
41892#define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)
41893#define SPDIF_SCR_LOW_POWER_MASK (0x2000U)
41894#define SPDIF_SCR_LOW_POWER_SHIFT (13U)
41895#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
41896#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U)
41897#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U)
41898/*! TxFIFOEmpty_Sel
41899 * 0b00..Empty interrupt if 0 sample in Tx left and right FIFOs
41900 * 0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs
41901 * 0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs
41902 * 0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs
41903 */
41904#define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
41905#define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U)
41906#define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U)
41907/*! TxAutoSync
41908 * 0b0..Tx FIFO auto sync off
41909 * 0b1..Tx FIFO auto sync on
41910 */
41911#define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
41912#define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U)
41913#define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U)
41914/*! RxAutoSync
41915 * 0b0..Rx FIFO auto sync off
41916 * 0b1..RxFIFO auto sync on
41917 */
41918#define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
41919#define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U)
41920#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U)
41921/*! RxFIFOFull_Sel
41922 * 0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs
41923 * 0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs
41924 * 0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs
41925 * 0b11..Full interrupt if at least 16 sample in Rx left and right FIFO
41926 */
41927#define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
41928#define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U)
41929#define SPDIF_SCR_RXFIFO_RST_SHIFT (21U)
41930/*! RxFIFO_Rst
41931 * 0b0..Normal operation
41932 * 0b1..Reset register to 1 sample remaining
41933 */
41934#define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
41935#define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U)
41936#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U)
41937/*! RxFIFO_Off_On
41938 * 0b0..SPDIF Rx FIFO is on
41939 * 0b1..SPDIF Rx FIFO is off. Does not accept data from interface
41940 */
41941#define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
41942#define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U)
41943#define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U)
41944/*! RxFIFO_Ctrl
41945 * 0b0..Normal operation
41946 * 0b1..Always read zero from Rx data register
41947 */
41948#define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
41949/*! @} */
41950
41951/*! @name SRCD - CDText Control Register */
41952/*! @{ */
41953#define SPDIF_SRCD_USYNCMODE_MASK (0x2U)
41954#define SPDIF_SRCD_USYNCMODE_SHIFT (1U)
41955/*! USyncMode
41956 * 0b0..Non-CD data
41957 * 0b1..CD user channel subcode
41958 */
41959#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
41960/*! @} */
41961
41962/*! @name SRPC - PhaseConfig Register */
41963/*! @{ */
41964#define SPDIF_SRPC_GAINSEL_MASK (0x38U)
41965#define SPDIF_SRPC_GAINSEL_SHIFT (3U)
41966/*! GainSel
41967 * 0b000..24*(2**10)
41968 * 0b001..16*(2**10)
41969 * 0b010..12*(2**10)
41970 * 0b011..8*(2**10)
41971 * 0b100..6*(2**10)
41972 * 0b101..4*(2**10)
41973 * 0b110..3*(2**10)
41974 */
41975#define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
41976#define SPDIF_SRPC_LOCK_MASK (0x40U)
41977#define SPDIF_SRPC_LOCK_SHIFT (6U)
41978#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
41979#define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U)
41980#define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U)
41981/*! ClkSrc_Sel
41982 * 0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)
41983 * 0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)
41984 * 0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK
41985 * 0b0101..REF_CLK_32K (XTALOSC)
41986 * 0b0110..tx_clk (SPDIF0_CLK_ROOT)
41987 * 0b1000..SPDIF_EXT_CLK
41988 */
41989#define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
41990/*! @} */
41991
41992/*! @name SIE - InterruptEn Register */
41993/*! @{ */
41994#define SPDIF_SIE_RXFIFOFUL_MASK (0x1U)
41995#define SPDIF_SIE_RXFIFOFUL_SHIFT (0U)
41996#define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)
41997#define SPDIF_SIE_TXEM_MASK (0x2U)
41998#define SPDIF_SIE_TXEM_SHIFT (1U)
41999#define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)
42000#define SPDIF_SIE_LOCKLOSS_MASK (0x4U)
42001#define SPDIF_SIE_LOCKLOSS_SHIFT (2U)
42002#define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)
42003#define SPDIF_SIE_RXFIFORESYN_MASK (0x8U)
42004#define SPDIF_SIE_RXFIFORESYN_SHIFT (3U)
42005#define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)
42006#define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U)
42007#define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U)
42008#define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)
42009#define SPDIF_SIE_UQERR_MASK (0x20U)
42010#define SPDIF_SIE_UQERR_SHIFT (5U)
42011#define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)
42012#define SPDIF_SIE_UQSYNC_MASK (0x40U)
42013#define SPDIF_SIE_UQSYNC_SHIFT (6U)
42014#define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)
42015#define SPDIF_SIE_QRXOV_MASK (0x80U)
42016#define SPDIF_SIE_QRXOV_SHIFT (7U)
42017#define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)
42018#define SPDIF_SIE_QRXFUL_MASK (0x100U)
42019#define SPDIF_SIE_QRXFUL_SHIFT (8U)
42020#define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)
42021#define SPDIF_SIE_URXOV_MASK (0x200U)
42022#define SPDIF_SIE_URXOV_SHIFT (9U)
42023#define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)
42024#define SPDIF_SIE_URXFUL_MASK (0x400U)
42025#define SPDIF_SIE_URXFUL_SHIFT (10U)
42026#define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)
42027#define SPDIF_SIE_BITERR_MASK (0x4000U)
42028#define SPDIF_SIE_BITERR_SHIFT (14U)
42029#define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)
42030#define SPDIF_SIE_SYMERR_MASK (0x8000U)
42031#define SPDIF_SIE_SYMERR_SHIFT (15U)
42032#define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)
42033#define SPDIF_SIE_VALNOGOOD_MASK (0x10000U)
42034#define SPDIF_SIE_VALNOGOOD_SHIFT (16U)
42035#define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)
42036#define SPDIF_SIE_CNEW_MASK (0x20000U)
42037#define SPDIF_SIE_CNEW_SHIFT (17U)
42038#define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)
42039#define SPDIF_SIE_TXRESYN_MASK (0x40000U)
42040#define SPDIF_SIE_TXRESYN_SHIFT (18U)
42041#define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)
42042#define SPDIF_SIE_TXUNOV_MASK (0x80000U)
42043#define SPDIF_SIE_TXUNOV_SHIFT (19U)
42044#define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)
42045#define SPDIF_SIE_LOCK_MASK (0x100000U)
42046#define SPDIF_SIE_LOCK_SHIFT (20U)
42047#define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
42048/*! @} */
42049
42050/*! @name SIC - InterruptClear Register */
42051/*! @{ */
42052#define SPDIF_SIC_LOCKLOSS_MASK (0x4U)
42053#define SPDIF_SIC_LOCKLOSS_SHIFT (2U)
42054#define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)
42055#define SPDIF_SIC_RXFIFORESYN_MASK (0x8U)
42056#define SPDIF_SIC_RXFIFORESYN_SHIFT (3U)
42057#define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)
42058#define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U)
42059#define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U)
42060#define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)
42061#define SPDIF_SIC_UQERR_MASK (0x20U)
42062#define SPDIF_SIC_UQERR_SHIFT (5U)
42063#define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)
42064#define SPDIF_SIC_UQSYNC_MASK (0x40U)
42065#define SPDIF_SIC_UQSYNC_SHIFT (6U)
42066#define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)
42067#define SPDIF_SIC_QRXOV_MASK (0x80U)
42068#define SPDIF_SIC_QRXOV_SHIFT (7U)
42069#define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)
42070#define SPDIF_SIC_URXOV_MASK (0x200U)
42071#define SPDIF_SIC_URXOV_SHIFT (9U)
42072#define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)
42073#define SPDIF_SIC_BITERR_MASK (0x4000U)
42074#define SPDIF_SIC_BITERR_SHIFT (14U)
42075#define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)
42076#define SPDIF_SIC_SYMERR_MASK (0x8000U)
42077#define SPDIF_SIC_SYMERR_SHIFT (15U)
42078#define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)
42079#define SPDIF_SIC_VALNOGOOD_MASK (0x10000U)
42080#define SPDIF_SIC_VALNOGOOD_SHIFT (16U)
42081#define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)
42082#define SPDIF_SIC_CNEW_MASK (0x20000U)
42083#define SPDIF_SIC_CNEW_SHIFT (17U)
42084#define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)
42085#define SPDIF_SIC_TXRESYN_MASK (0x40000U)
42086#define SPDIF_SIC_TXRESYN_SHIFT (18U)
42087#define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)
42088#define SPDIF_SIC_TXUNOV_MASK (0x80000U)
42089#define SPDIF_SIC_TXUNOV_SHIFT (19U)
42090#define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)
42091#define SPDIF_SIC_LOCK_MASK (0x100000U)
42092#define SPDIF_SIC_LOCK_SHIFT (20U)
42093#define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)
42094/*! @} */
42095
42096/*! @name SIS - InterruptStat Register */
42097/*! @{ */
42098#define SPDIF_SIS_RXFIFOFUL_MASK (0x1U)
42099#define SPDIF_SIS_RXFIFOFUL_SHIFT (0U)
42100#define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)
42101#define SPDIF_SIS_TXEM_MASK (0x2U)
42102#define SPDIF_SIS_TXEM_SHIFT (1U)
42103#define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)
42104#define SPDIF_SIS_LOCKLOSS_MASK (0x4U)
42105#define SPDIF_SIS_LOCKLOSS_SHIFT (2U)
42106#define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)
42107#define SPDIF_SIS_RXFIFORESYN_MASK (0x8U)
42108#define SPDIF_SIS_RXFIFORESYN_SHIFT (3U)
42109#define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)
42110#define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U)
42111#define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U)
42112#define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)
42113#define SPDIF_SIS_UQERR_MASK (0x20U)
42114#define SPDIF_SIS_UQERR_SHIFT (5U)
42115#define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)
42116#define SPDIF_SIS_UQSYNC_MASK (0x40U)
42117#define SPDIF_SIS_UQSYNC_SHIFT (6U)
42118#define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)
42119#define SPDIF_SIS_QRXOV_MASK (0x80U)
42120#define SPDIF_SIS_QRXOV_SHIFT (7U)
42121#define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)
42122#define SPDIF_SIS_QRXFUL_MASK (0x100U)
42123#define SPDIF_SIS_QRXFUL_SHIFT (8U)
42124#define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)
42125#define SPDIF_SIS_URXOV_MASK (0x200U)
42126#define SPDIF_SIS_URXOV_SHIFT (9U)
42127#define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)
42128#define SPDIF_SIS_URXFUL_MASK (0x400U)
42129#define SPDIF_SIS_URXFUL_SHIFT (10U)
42130#define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)
42131#define SPDIF_SIS_BITERR_MASK (0x4000U)
42132#define SPDIF_SIS_BITERR_SHIFT (14U)
42133#define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)
42134#define SPDIF_SIS_SYMERR_MASK (0x8000U)
42135#define SPDIF_SIS_SYMERR_SHIFT (15U)
42136#define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)
42137#define SPDIF_SIS_VALNOGOOD_MASK (0x10000U)
42138#define SPDIF_SIS_VALNOGOOD_SHIFT (16U)
42139#define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)
42140#define SPDIF_SIS_CNEW_MASK (0x20000U)
42141#define SPDIF_SIS_CNEW_SHIFT (17U)
42142#define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)
42143#define SPDIF_SIS_TXRESYN_MASK (0x40000U)
42144#define SPDIF_SIS_TXRESYN_SHIFT (18U)
42145#define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)
42146#define SPDIF_SIS_TXUNOV_MASK (0x80000U)
42147#define SPDIF_SIS_TXUNOV_SHIFT (19U)
42148#define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)
42149#define SPDIF_SIS_LOCK_MASK (0x100000U)
42150#define SPDIF_SIS_LOCK_SHIFT (20U)
42151#define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
42152/*! @} */
42153
42154/*! @name SRL - SPDIFRxLeft Register */
42155/*! @{ */
42156#define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU)
42157#define SPDIF_SRL_RXDATALEFT_SHIFT (0U)
42158#define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
42159/*! @} */
42160
42161/*! @name SRR - SPDIFRxRight Register */
42162/*! @{ */
42163#define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU)
42164#define SPDIF_SRR_RXDATARIGHT_SHIFT (0U)
42165#define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
42166/*! @} */
42167
42168/*! @name SRCSH - SPDIFRxCChannel_h Register */
42169/*! @{ */
42170#define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU)
42171#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U)
42172#define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
42173/*! @} */
42174
42175/*! @name SRCSL - SPDIFRxCChannel_l Register */
42176/*! @{ */
42177#define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU)
42178#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U)
42179#define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
42180/*! @} */
42181
42182/*! @name SRU - UchannelRx Register */
42183/*! @{ */
42184#define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU)
42185#define SPDIF_SRU_RXUCHANNEL_SHIFT (0U)
42186#define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
42187/*! @} */
42188
42189/*! @name SRQ - QchannelRx Register */
42190/*! @{ */
42191#define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU)
42192#define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U)
42193#define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
42194/*! @} */
42195
42196/*! @name STL - SPDIFTxLeft Register */
42197/*! @{ */
42198#define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU)
42199#define SPDIF_STL_TXDATALEFT_SHIFT (0U)
42200#define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
42201/*! @} */
42202
42203/*! @name STR - SPDIFTxRight Register */
42204/*! @{ */
42205#define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU)
42206#define SPDIF_STR_TXDATARIGHT_SHIFT (0U)
42207#define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
42208/*! @} */
42209
42210/*! @name STCSCH - SPDIFTxCChannelCons_h Register */
42211/*! @{ */
42212#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU)
42213#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U)
42214#define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
42215/*! @} */
42216
42217/*! @name STCSCL - SPDIFTxCChannelCons_l Register */
42218/*! @{ */
42219#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU)
42220#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U)
42221#define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
42222/*! @} */
42223
42224/*! @name SRFM - FreqMeas Register */
42225/*! @{ */
42226#define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU)
42227#define SPDIF_SRFM_FREQMEAS_SHIFT (0U)
42228#define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
42229/*! @} */
42230
42231/*! @name STC - SPDIFTxClk Register */
42232/*! @{ */
42233#define SPDIF_STC_TXCLK_DF_MASK (0x7FU)
42234#define SPDIF_STC_TXCLK_DF_SHIFT (0U)
42235/*! TxClk_DF
42236 * 0b0000000..divider factor is 1
42237 * 0b0000001..divider factor is 2
42238 * 0b1111111..divider factor is 128
42239 */
42240#define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
42241#define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U)
42242#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U)
42243/*! tx_all_clk_en
42244 * 0b0..disable transfer clock.
42245 * 0b1..enable transfer clock.
42246 */
42247#define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
42248#define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U)
42249#define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U)
42250/*! TxClk_Source
42251 * 0b000..REF_CLK_32K input (XTALOSC 32 kHz clock)
42252 * 0b001..tx_clk input (from SPDIF0_CLK_ROOT. See CCM.)
42253 * 0b011..SPDIF_EXT_CLK, from pads
42254 * 0b101..ipg_clk input (frequency divided)
42255 */
42256#define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
42257#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U)
42258#define SPDIF_STC_SYSCLK_DF_SHIFT (11U)
42259/*! SYSCLK_DF
42260 * 0b000000000..no clock signal
42261 * 0b000000001..divider factor is 2
42262 * 0b111111111..divider factor is 512
42263 */
42264#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)
42265/*! @} */
42266
42267
42268/*!
42269 * @}
42270 */ /* end of group SPDIF_Register_Masks */
42271
42272
42273/* SPDIF - Peripheral instance base addresses */
42274/** Peripheral SPDIF1 base address */
42275#define SPDIF1_BASE (0x30810000u)
42276/** Peripheral SPDIF1 base pointer */
42277#define SPDIF1 ((SPDIF_Type *)SPDIF1_BASE)
42278/** Peripheral SPDIF2 base address */
42279#define SPDIF2_BASE (0x308A0000u)
42280/** Peripheral SPDIF2 base pointer */
42281#define SPDIF2 ((SPDIF_Type *)SPDIF2_BASE)
42282/** Array initializer of SPDIF peripheral base addresses */
42283#define SPDIF_BASE_ADDRS { 0u, SPDIF1_BASE, SPDIF2_BASE }
42284/** Array initializer of SPDIF peripheral base pointers */
42285#define SPDIF_BASE_PTRS { (SPDIF_Type *)0u, SPDIF1, SPDIF2 }
42286/** Interrupt vectors for the SPDIF peripheral type */
42287#define SPDIF_IRQS { NotAvail_IRQn, SPDIF1_IRQn, SPDIF2_IRQn }
42288
42289/*!
42290 * @}
42291 */ /* end of group SPDIF_Peripheral_Access_Layer */
42292
42293
42294/* ----------------------------------------------------------------------------
42295 -- SRC Peripheral Access Layer
42296 ---------------------------------------------------------------------------- */
42297
42298/*!
42299 * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer
42300 * @{
42301 */
42302
42303/** SRC - Register Layout Typedef */
42304typedef struct {
42305 __IO uint32_t SCR; /**< SRC Reset Control Register, offset: 0x0 */
42306 __IO uint32_t A53RCR0; /**< A53 Reset Control Register, offset: 0x4 */
42307 __IO uint32_t A53RCR1; /**< A53 Reset Control Register, offset: 0x8 */
42308 __IO uint32_t M4RCR; /**< M4 Reset Control Register, offset: 0xC */
42309 uint8_t RESERVED_0[16];
42310 __IO uint32_t USBOPHY1_RCR; /**< USB OTG PHY1 Reset Control Register, offset: 0x20 */
42311 __IO uint32_t USBOPHY2_RCR; /**< USB OTG PHY2 Reset Control Register, offset: 0x24 */
42312 __IO uint32_t MIPIPHY_RCR; /**< MIPI PHY Reset Control Register, offset: 0x28 */
42313 __IO uint32_t PCIEPHY_RCR; /**< PCIE PHY Reset Control Register, offset: 0x2C */
42314 __IO uint32_t HDMI_RCR; /**< HDMI Reset Control Register, offset: 0x30 */
42315 __IO uint32_t DISP_RCR; /**< DISP Reset Control Register, offset: 0x34 */
42316 uint8_t RESERVED_1[8];
42317 __IO uint32_t GPU_RCR; /**< GPU Reset Control Register, offset: 0x40 */
42318 __IO uint32_t VPU_RCR; /**< VPU Reset Control Register, offset: 0x44 */
42319 __IO uint32_t PCIE2_RCR; /**< PCIE2 Reset Control Register, offset: 0x48 */
42320 __IO uint32_t MIPIPHY1_RCR; /**< MIPI CSI1 PHY Reset Control Register, offset: 0x4C */
42321 __IO uint32_t MIPIPHY2_RCR; /**< MIPI CSI2 PHY Reset Control Register, offset: 0x50 */
42322 uint8_t RESERVED_2[4];
42323 __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x58 */
42324 __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x5C */
42325 uint8_t RESERVED_3[8];
42326 __I uint32_t SISR; /**< SRC Interrupt Status Register, offset: 0x68 */
42327 __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */
42328 __IO uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x70 */
42329 __IO uint32_t GPR[10]; /**< SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x74, array step: 0x4 */
42330 uint8_t RESERVED_4[3940];
42331 __IO uint32_t DDRC_RCR; /**< SRC DDR Controller Reset Control Register, offset: 0x1000 */
42332 __IO uint32_t DDRC2_RCR; /**< SRC DDRC2 Controller Reset Control Register, offset: 0x1004 */
42333} SRC_Type;
42334
42335/* ----------------------------------------------------------------------------
42336 -- SRC Register Masks
42337 ---------------------------------------------------------------------------- */
42338
42339/*!
42340 * @addtogroup SRC_Register_Masks SRC Register Masks
42341 * @{
42342 */
42343
42344/*! @name SCR - SRC Reset Control Register */
42345/*! @{ */
42346#define SRC_SCR_MASK_TEMPSENSE_RESET_MASK (0xF0U)
42347#define SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT (4U)
42348/*! MASK_TEMPSENSE_RESET
42349 * 0b0101..tempsense_reset is masked
42350 * 0b1010..tempsense_reset is not masked
42351 */
42352#define SRC_SCR_MASK_TEMPSENSE_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT)) & SRC_SCR_MASK_TEMPSENSE_RESET_MASK)
42353#define SRC_SCR_DOMAIN0_MASK (0x1000000U)
42354#define SRC_SCR_DOMAIN0_SHIFT (24U)
42355/*! DOMAIN0
42356 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
42357 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
42358 */
42359#define SRC_SCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN0_SHIFT)) & SRC_SCR_DOMAIN0_MASK)
42360#define SRC_SCR_DOMAIN1_MASK (0x2000000U)
42361#define SRC_SCR_DOMAIN1_SHIFT (25U)
42362/*! DOMAIN1
42363 * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register.
42364 * 0b1..This register is assigned to domain1. The master from domain3 can write to this register
42365 */
42366#define SRC_SCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN1_SHIFT)) & SRC_SCR_DOMAIN1_MASK)
42367#define SRC_SCR_DOMAIN2_MASK (0x4000000U)
42368#define SRC_SCR_DOMAIN2_SHIFT (26U)
42369/*! DOMAIN2
42370 * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register.
42371 * 0b1..This register is assigned to domain2. The master from domain3 can write to this register
42372 */
42373#define SRC_SCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN2_SHIFT)) & SRC_SCR_DOMAIN2_MASK)
42374#define SRC_SCR_DOMAIN3_MASK (0x8000000U)
42375#define SRC_SCR_DOMAIN3_SHIFT (27U)
42376/*! DOMAIN3
42377 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
42378 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
42379 */
42380#define SRC_SCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN3_SHIFT)) & SRC_SCR_DOMAIN3_MASK)
42381#define SRC_SCR_LOCK_MASK (0x40000000U)
42382#define SRC_SCR_LOCK_SHIFT (30U)
42383/*! LOCK
42384 * 0b0..[31] and [27:24] bits can be modified
42385 * 0b1..[31] and [27:24] bits cannot be modified
42386 */
42387#define SRC_SCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_LOCK_SHIFT)) & SRC_SCR_LOCK_MASK)
42388#define SRC_SCR_DOM_EN_MASK (0x80000000U)
42389#define SRC_SCR_DOM_EN_SHIFT (31U)
42390/*! DOM_EN
42391 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
42392 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
42393 */
42394#define SRC_SCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOM_EN_SHIFT)) & SRC_SCR_DOM_EN_MASK)
42395/*! @} */
42396
42397/*! @name A53RCR0 - A53 Reset Control Register */
42398/*! @{ */
42399#define SRC_A53RCR0_A53_CORE_POR_RESET0_MASK (0x1U)
42400#define SRC_A53RCR0_A53_CORE_POR_RESET0_SHIFT (0U)
42401/*! A53_CORE_POR_RESET0
42402 * 0b0..do not assert core0 reset
42403 * 0b1..assert core0 reset
42404 */
42405#define SRC_A53RCR0_A53_CORE_POR_RESET0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET0_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET0_MASK)
42406#define SRC_A53RCR0_A53_CORE_POR_RESET1_MASK (0x2U)
42407#define SRC_A53RCR0_A53_CORE_POR_RESET1_SHIFT (1U)
42408/*! A53_CORE_POR_RESET1
42409 * 0b0..do not assert core1 reset
42410 * 0b1..assert core1 reset
42411 */
42412#define SRC_A53RCR0_A53_CORE_POR_RESET1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET1_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET1_MASK)
42413#define SRC_A53RCR0_A53_CORE_POR_RESET2_MASK (0x4U)
42414#define SRC_A53RCR0_A53_CORE_POR_RESET2_SHIFT (2U)
42415/*! A53_CORE_POR_RESET2
42416 * 0b0..do not assert core2 reset
42417 * 0b1..assert core2 reset
42418 */
42419#define SRC_A53RCR0_A53_CORE_POR_RESET2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET2_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET2_MASK)
42420#define SRC_A53RCR0_A53_CORE_POR_RESET3_MASK (0x8U)
42421#define SRC_A53RCR0_A53_CORE_POR_RESET3_SHIFT (3U)
42422/*! A53_CORE_POR_RESET3
42423 * 0b0..do not assert core3 reset
42424 * 0b1..assert core3 reset
42425 */
42426#define SRC_A53RCR0_A53_CORE_POR_RESET3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET3_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET3_MASK)
42427#define SRC_A53RCR0_A53_CORE_RESET0_MASK (0x10U)
42428#define SRC_A53RCR0_A53_CORE_RESET0_SHIFT (4U)
42429/*! A53_CORE_RESET0
42430 * 0b0..do not assert core0 reset
42431 * 0b1..assert core0 reset
42432 */
42433#define SRC_A53RCR0_A53_CORE_RESET0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET0_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET0_MASK)
42434#define SRC_A53RCR0_A53_CORE_RESET1_MASK (0x20U)
42435#define SRC_A53RCR0_A53_CORE_RESET1_SHIFT (5U)
42436/*! A53_CORE_RESET1
42437 * 0b0..do not assert core1 reset
42438 * 0b1..assert core1 reset
42439 */
42440#define SRC_A53RCR0_A53_CORE_RESET1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET1_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET1_MASK)
42441#define SRC_A53RCR0_A53_CORE_RESET2_MASK (0x40U)
42442#define SRC_A53RCR0_A53_CORE_RESET2_SHIFT (6U)
42443/*! A53_CORE_RESET2
42444 * 0b0..do not assert core2 reset
42445 * 0b1..assert core2 reset
42446 */
42447#define SRC_A53RCR0_A53_CORE_RESET2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET2_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET2_MASK)
42448#define SRC_A53RCR0_A53_CORE_RESET3_MASK (0x80U)
42449#define SRC_A53RCR0_A53_CORE_RESET3_SHIFT (7U)
42450/*! A53_CORE_RESET3
42451 * 0b0..do not assert core3 reset
42452 * 0b1..assert core3 reset
42453 */
42454#define SRC_A53RCR0_A53_CORE_RESET3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET3_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET3_MASK)
42455#define SRC_A53RCR0_A53_DBG_RESET0_MASK (0x100U)
42456#define SRC_A53RCR0_A53_DBG_RESET0_SHIFT (8U)
42457/*! A53_DBG_RESET0
42458 * 0b0..do not assert core0 debug reset
42459 * 0b1..assert core0 debug reset
42460 */
42461#define SRC_A53RCR0_A53_DBG_RESET0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET0_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET0_MASK)
42462#define SRC_A53RCR0_A53_DBG_RESET1_MASK (0x200U)
42463#define SRC_A53RCR0_A53_DBG_RESET1_SHIFT (9U)
42464/*! A53_DBG_RESET1
42465 * 0b0..do not assert core1 debug reset
42466 * 0b1..assert core1 debug reset
42467 */
42468#define SRC_A53RCR0_A53_DBG_RESET1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET1_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET1_MASK)
42469#define SRC_A53RCR0_A53_DBG_RESET2_MASK (0x400U)
42470#define SRC_A53RCR0_A53_DBG_RESET2_SHIFT (10U)
42471/*! A53_DBG_RESET2
42472 * 0b0..do not assert core2 debug reset
42473 * 0b1..assert core2 debug reset
42474 */
42475#define SRC_A53RCR0_A53_DBG_RESET2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET2_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET2_MASK)
42476#define SRC_A53RCR0_A53_DBG_RESET3_MASK (0x800U)
42477#define SRC_A53RCR0_A53_DBG_RESET3_SHIFT (11U)
42478/*! A53_DBG_RESET3
42479 * 0b0..do not assert core3 debug reset
42480 * 0b1..assert core3 debug reset
42481 */
42482#define SRC_A53RCR0_A53_DBG_RESET3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET3_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET3_MASK)
42483#define SRC_A53RCR0_A53_ETM_RESET0_MASK (0x1000U)
42484#define SRC_A53RCR0_A53_ETM_RESET0_SHIFT (12U)
42485/*! A53_ETM_RESET0
42486 * 0b0..do not assert core0 ETM reset
42487 * 0b1..assert core0 ETM reset
42488 */
42489#define SRC_A53RCR0_A53_ETM_RESET0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET0_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET0_MASK)
42490#define SRC_A53RCR0_A53_ETM_RESET1_MASK (0x2000U)
42491#define SRC_A53RCR0_A53_ETM_RESET1_SHIFT (13U)
42492/*! A53_ETM_RESET1
42493 * 0b0..do not assert core1 ETM reset
42494 * 0b1..assert core1 ETM reset
42495 */
42496#define SRC_A53RCR0_A53_ETM_RESET1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET1_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET1_MASK)
42497#define SRC_A53RCR0_A53_ETM_RESET2_MASK (0x4000U)
42498#define SRC_A53RCR0_A53_ETM_RESET2_SHIFT (14U)
42499/*! A53_ETM_RESET2
42500 * 0b0..do not assert core2 ETM reset
42501 * 0b1..assert core2 ETM reset
42502 */
42503#define SRC_A53RCR0_A53_ETM_RESET2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET2_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET2_MASK)
42504#define SRC_A53RCR0_A53_ETM_RESET3_MASK (0x8000U)
42505#define SRC_A53RCR0_A53_ETM_RESET3_SHIFT (15U)
42506/*! A53_ETM_RESET3
42507 * 0b0..do not assert core3 ETM reset
42508 * 0b1..assert core3 ETM reset
42509 */
42510#define SRC_A53RCR0_A53_ETM_RESET3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET3_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET3_MASK)
42511#define SRC_A53RCR0_MASK_WDOG1_RST_MASK (0xF0000U)
42512#define SRC_A53RCR0_MASK_WDOG1_RST_SHIFT (16U)
42513/*! MASK_WDOG1_RST
42514 * 0b0101..wdog1_rst_b is masked
42515 * 0b1010..wdog1_rst_b is not masked
42516 */
42517#define SRC_A53RCR0_MASK_WDOG1_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_MASK_WDOG1_RST_SHIFT)) & SRC_A53RCR0_MASK_WDOG1_RST_MASK)
42518#define SRC_A53RCR0_A53_SOC_DBG_RESET_MASK (0x100000U)
42519#define SRC_A53RCR0_A53_SOC_DBG_RESET_SHIFT (20U)
42520/*! A53_SOC_DBG_RESET
42521 * 0b0..do not assert system level debug reset
42522 * 0b1..assert system level debug reset
42523 */
42524#define SRC_A53RCR0_A53_SOC_DBG_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_SOC_DBG_RESET_SHIFT)) & SRC_A53RCR0_A53_SOC_DBG_RESET_MASK)
42525#define SRC_A53RCR0_A53_L2RESET_MASK (0x200000U)
42526#define SRC_A53RCR0_A53_L2RESET_SHIFT (21U)
42527/*! A53_L2RESET
42528 * 0b0..do not assert SCU reset
42529 * 0b1..assert SCU reset
42530 */
42531#define SRC_A53RCR0_A53_L2RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_L2RESET_SHIFT)) & SRC_A53RCR0_A53_L2RESET_MASK)
42532#define SRC_A53RCR0_DOMAIN0_MASK (0x1000000U)
42533#define SRC_A53RCR0_DOMAIN0_SHIFT (24U)
42534/*! DOMAIN0
42535 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
42536 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
42537 */
42538#define SRC_A53RCR0_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN0_SHIFT)) & SRC_A53RCR0_DOMAIN0_MASK)
42539#define SRC_A53RCR0_DOMAIN1_MASK (0x2000000U)
42540#define SRC_A53RCR0_DOMAIN1_SHIFT (25U)
42541/*! DOMAIN1
42542 * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register.
42543 * 0b1..This register is assigned to domain1. The master from domain3 can write to this register
42544 */
42545#define SRC_A53RCR0_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN1_SHIFT)) & SRC_A53RCR0_DOMAIN1_MASK)
42546#define SRC_A53RCR0_DOMAIN2_MASK (0x4000000U)
42547#define SRC_A53RCR0_DOMAIN2_SHIFT (26U)
42548/*! DOMAIN2
42549 * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register.
42550 * 0b1..This register is assigned to domain2. The master from domain3 can write to this register
42551 */
42552#define SRC_A53RCR0_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN2_SHIFT)) & SRC_A53RCR0_DOMAIN2_MASK)
42553#define SRC_A53RCR0_DOMAIN3_MASK (0x8000000U)
42554#define SRC_A53RCR0_DOMAIN3_SHIFT (27U)
42555/*! DOMAIN3
42556 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
42557 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
42558 */
42559#define SRC_A53RCR0_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN3_SHIFT)) & SRC_A53RCR0_DOMAIN3_MASK)
42560#define SRC_A53RCR0_LOCK_MASK (0x40000000U)
42561#define SRC_A53RCR0_LOCK_SHIFT (30U)
42562/*! LOCK
42563 * 0b0..[31] and [27:24] bits can be modified
42564 * 0b1..[31] and [27:24] bits cannot be modified
42565 */
42566#define SRC_A53RCR0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_LOCK_SHIFT)) & SRC_A53RCR0_LOCK_MASK)
42567#define SRC_A53RCR0_DOM_EN_MASK (0x80000000U)
42568#define SRC_A53RCR0_DOM_EN_SHIFT (31U)
42569/*! DOM_EN
42570 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
42571 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
42572 */
42573#define SRC_A53RCR0_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOM_EN_SHIFT)) & SRC_A53RCR0_DOM_EN_MASK)
42574/*! @} */
42575
42576/*! @name A53RCR1 - A53 Reset Control Register */
42577/*! @{ */
42578#define SRC_A53RCR1_A53_CORE0_ENABLE_MASK (0x1U)
42579#define SRC_A53RCR1_A53_CORE0_ENABLE_SHIFT (0U)
42580#define SRC_A53RCR1_A53_CORE0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE0_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE0_ENABLE_MASK)
42581#define SRC_A53RCR1_A53_CORE1_ENABLE_MASK (0x2U)
42582#define SRC_A53RCR1_A53_CORE1_ENABLE_SHIFT (1U)
42583/*! A53_CORE1_ENABLE
42584 * 0b0..core1 is disabled
42585 * 0b1..core1 is enabled
42586 */
42587#define SRC_A53RCR1_A53_CORE1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE1_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE1_ENABLE_MASK)
42588#define SRC_A53RCR1_A53_CORE2_ENABLE_MASK (0x4U)
42589#define SRC_A53RCR1_A53_CORE2_ENABLE_SHIFT (2U)
42590/*! A53_CORE2_ENABLE
42591 * 0b0..core2 is disabled
42592 * 0b1..core2 is enabled
42593 */
42594#define SRC_A53RCR1_A53_CORE2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE2_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE2_ENABLE_MASK)
42595#define SRC_A53RCR1_A53_CORE3_ENABLE_MASK (0x8U)
42596#define SRC_A53RCR1_A53_CORE3_ENABLE_SHIFT (3U)
42597/*! A53_CORE3_ENABLE
42598 * 0b0..core3 is disabled
42599 * 0b1..core3 is enabled
42600 */
42601#define SRC_A53RCR1_A53_CORE3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE3_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE3_ENABLE_MASK)
42602#define SRC_A53RCR1_A53_RST_SLOW_MASK (0x70U)
42603#define SRC_A53RCR1_A53_RST_SLOW_SHIFT (4U)
42604#define SRC_A53RCR1_A53_RST_SLOW(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_RST_SLOW_SHIFT)) & SRC_A53RCR1_A53_RST_SLOW_MASK)
42605#define SRC_A53RCR1_DOMAIN0_MASK (0x1000000U)
42606#define SRC_A53RCR1_DOMAIN0_SHIFT (24U)
42607/*! DOMAIN0
42608 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
42609 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
42610 */
42611#define SRC_A53RCR1_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN0_SHIFT)) & SRC_A53RCR1_DOMAIN0_MASK)
42612#define SRC_A53RCR1_DOMAIN1_MASK (0x2000000U)
42613#define SRC_A53RCR1_DOMAIN1_SHIFT (25U)
42614/*! DOMAIN1
42615 * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register.
42616 * 0b1..This register is assigned to domain1. The master from domain3 can write to this register
42617 */
42618#define SRC_A53RCR1_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN1_SHIFT)) & SRC_A53RCR1_DOMAIN1_MASK)
42619#define SRC_A53RCR1_DOMAIN2_MASK (0x4000000U)
42620#define SRC_A53RCR1_DOMAIN2_SHIFT (26U)
42621/*! DOMAIN2
42622 * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register.
42623 * 0b1..This register is assigned to domain2. The master from domain3 can write to this register
42624 */
42625#define SRC_A53RCR1_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN2_SHIFT)) & SRC_A53RCR1_DOMAIN2_MASK)
42626#define SRC_A53RCR1_DOMAIN3_MASK (0x8000000U)
42627#define SRC_A53RCR1_DOMAIN3_SHIFT (27U)
42628/*! DOMAIN3
42629 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
42630 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
42631 */
42632#define SRC_A53RCR1_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN3_SHIFT)) & SRC_A53RCR1_DOMAIN3_MASK)
42633#define SRC_A53RCR1_LOCK_MASK (0x40000000U)
42634#define SRC_A53RCR1_LOCK_SHIFT (30U)
42635/*! LOCK
42636 * 0b0..[31] and [27:24] bits can be modified
42637 * 0b1..[31] and [27:24] bits cannot be modified
42638 */
42639#define SRC_A53RCR1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_LOCK_SHIFT)) & SRC_A53RCR1_LOCK_MASK)
42640#define SRC_A53RCR1_DOM_EN_MASK (0x80000000U)
42641#define SRC_A53RCR1_DOM_EN_SHIFT (31U)
42642/*! DOM_EN
42643 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
42644 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
42645 */
42646#define SRC_A53RCR1_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOM_EN_SHIFT)) & SRC_A53RCR1_DOM_EN_MASK)
42647/*! @} */
42648
42649/*! @name M4RCR - M4 Reset Control Register */
42650/*! @{ */
42651#define SRC_M4RCR_SW_M4C_NON_SCLR_RST_MASK (0x1U)
42652#define SRC_M4RCR_SW_M4C_NON_SCLR_RST_SHIFT (0U)
42653/*! SW_M4C_NON_SCLR_RST
42654 * 0b0..do not assert M4 core reset
42655 * 0b1..assert M4 core reset
42656 */
42657#define SRC_M4RCR_SW_M4C_NON_SCLR_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_SW_M4C_NON_SCLR_RST_SHIFT)) & SRC_M4RCR_SW_M4C_NON_SCLR_RST_MASK)
42658#define SRC_M4RCR_SW_M4C_RST_MASK (0x2U)
42659#define SRC_M4RCR_SW_M4C_RST_SHIFT (1U)
42660/*! SW_M4C_RST
42661 * 0b0..do not assert M4 core reset
42662 * 0b1..assert M4 core reset
42663 */
42664#define SRC_M4RCR_SW_M4C_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_SW_M4C_RST_SHIFT)) & SRC_M4RCR_SW_M4C_RST_MASK)
42665#define SRC_M4RCR_SW_M4P_RST_MASK (0x4U)
42666#define SRC_M4RCR_SW_M4P_RST_SHIFT (2U)
42667/*! SW_M4P_RST
42668 * 0b0..do not assert M4 platform reset
42669 * 0b1..assert M4 platform reset
42670 */
42671#define SRC_M4RCR_SW_M4P_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_SW_M4P_RST_SHIFT)) & SRC_M4RCR_SW_M4P_RST_MASK)
42672#define SRC_M4RCR_ENABLE_M4_MASK (0x8U)
42673#define SRC_M4RCR_ENABLE_M4_SHIFT (3U)
42674/*! ENABLE_M4
42675 * 0b0..M4 is disabled
42676 * 0b1..M4 is enabled
42677 */
42678#define SRC_M4RCR_ENABLE_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_ENABLE_M4_SHIFT)) & SRC_M4RCR_ENABLE_M4_MASK)
42679#define SRC_M4RCR_MASK_WDOG3_RST_MASK (0xF0U)
42680#define SRC_M4RCR_MASK_WDOG3_RST_SHIFT (4U)
42681/*! MASK_WDOG3_RST
42682 * 0b0101..wdog3_rst_b is masked
42683 * 0b1010..wdog3_rst_b is not masked
42684 */
42685#define SRC_M4RCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_MASK_WDOG3_RST_SHIFT)) & SRC_M4RCR_MASK_WDOG3_RST_MASK)
42686#define SRC_M4RCR_WDOG3_RST_OPTION_M4_MASK (0x100U)
42687#define SRC_M4RCR_WDOG3_RST_OPTION_M4_SHIFT (8U)
42688/*! WDOG3_RST_OPTION_M4
42689 * 0b0..wdgo3_rst_b Reset M4 core only
42690 * 0b1..Reset both M4 core and platform
42691 */
42692#define SRC_M4RCR_WDOG3_RST_OPTION_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_WDOG3_RST_OPTION_M4_SHIFT)) & SRC_M4RCR_WDOG3_RST_OPTION_M4_MASK)
42693#define SRC_M4RCR_WDOG3_RST_OPTION_MASK (0x200U)
42694#define SRC_M4RCR_WDOG3_RST_OPTION_SHIFT (9U)
42695/*! WDOG3_RST_OPTION
42696 * 0b0..Wdog3_rst_b asserts M4 reset
42697 * 0b1..Wdog3_rst_b asserts global reset
42698 */
42699#define SRC_M4RCR_WDOG3_RST_OPTION(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_WDOG3_RST_OPTION_SHIFT)) & SRC_M4RCR_WDOG3_RST_OPTION_MASK)
42700#define SRC_M4RCR_DOMAIN0_MASK (0x1000000U)
42701#define SRC_M4RCR_DOMAIN0_SHIFT (24U)
42702/*! DOMAIN0
42703 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
42704 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
42705 */
42706#define SRC_M4RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_DOMAIN0_SHIFT)) & SRC_M4RCR_DOMAIN0_MASK)
42707#define SRC_M4RCR_DOMAIN1_MASK (0x2000000U)
42708#define SRC_M4RCR_DOMAIN1_SHIFT (25U)
42709/*! DOMAIN1
42710 * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register.
42711 * 0b1..This register is assigned to domain1. The master from domain3 can write to this register
42712 */
42713#define SRC_M4RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_DOMAIN1_SHIFT)) & SRC_M4RCR_DOMAIN1_MASK)
42714#define SRC_M4RCR_DOMAIN2_MASK (0x4000000U)
42715#define SRC_M4RCR_DOMAIN2_SHIFT (26U)
42716/*! DOMAIN2
42717 * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register.
42718 * 0b1..This register is assigned to domain2. The master from domain3 can write to this register
42719 */
42720#define SRC_M4RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_DOMAIN2_SHIFT)) & SRC_M4RCR_DOMAIN2_MASK)
42721#define SRC_M4RCR_DOMAIN3_MASK (0x8000000U)
42722#define SRC_M4RCR_DOMAIN3_SHIFT (27U)
42723/*! DOMAIN3
42724 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
42725 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
42726 */
42727#define SRC_M4RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_DOMAIN3_SHIFT)) & SRC_M4RCR_DOMAIN3_MASK)
42728#define SRC_M4RCR_LOCK_MASK (0x40000000U)
42729#define SRC_M4RCR_LOCK_SHIFT (30U)
42730/*! LOCK
42731 * 0b0..[31] and [27:24] bits can be modified
42732 * 0b1..[31] and [27:24] bits cannot be modified
42733 */
42734#define SRC_M4RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_LOCK_SHIFT)) & SRC_M4RCR_LOCK_MASK)
42735#define SRC_M4RCR_DOM_EN_MASK (0x80000000U)
42736#define SRC_M4RCR_DOM_EN_SHIFT (31U)
42737/*! DOM_EN
42738 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
42739 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
42740 */
42741#define SRC_M4RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_DOM_EN_SHIFT)) & SRC_M4RCR_DOM_EN_MASK)
42742/*! @} */
42743
42744/*! @name USBOPHY1_RCR - USB OTG PHY1 Reset Control Register */
42745/*! @{ */
42746#define SRC_USBOPHY1_RCR_OTG1_PHY_RESET_MASK (0x1U)
42747#define SRC_USBOPHY1_RCR_OTG1_PHY_RESET_SHIFT (0U)
42748/*! OTG1_PHY_RESET
42749 * 0b0..Don't reset USB OTG1 PHY
42750 * 0b1..Reset USB OTG1 PHY
42751 */
42752#define SRC_USBOPHY1_RCR_OTG1_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_OTG1_PHY_RESET_SHIFT)) & SRC_USBOPHY1_RCR_OTG1_PHY_RESET_MASK)
42753#define SRC_USBOPHY1_RCR_DOMAIN0_MASK (0x1000000U)
42754#define SRC_USBOPHY1_RCR_DOMAIN0_SHIFT (24U)
42755/*! DOMAIN0
42756 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
42757 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
42758 */
42759#define SRC_USBOPHY1_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN0_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN0_MASK)
42760#define SRC_USBOPHY1_RCR_DOMAIN1_MASK (0x2000000U)
42761#define SRC_USBOPHY1_RCR_DOMAIN1_SHIFT (25U)
42762/*! DOMAIN1
42763 * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register.
42764 * 0b1..This register is assigned to domain1. The master from domain3 can write to this register
42765 */
42766#define SRC_USBOPHY1_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN1_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN1_MASK)
42767#define SRC_USBOPHY1_RCR_DOMAIN2_MASK (0x4000000U)
42768#define SRC_USBOPHY1_RCR_DOMAIN2_SHIFT (26U)
42769/*! DOMAIN2
42770 * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register.
42771 * 0b1..This register is assigned to domain2. The master from domain3 can write to this register
42772 */
42773#define SRC_USBOPHY1_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN2_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN2_MASK)
42774#define SRC_USBOPHY1_RCR_DOMAIN3_MASK (0x8000000U)
42775#define SRC_USBOPHY1_RCR_DOMAIN3_SHIFT (27U)
42776/*! DOMAIN3
42777 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
42778 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
42779 */
42780#define SRC_USBOPHY1_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN3_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN3_MASK)
42781#define SRC_USBOPHY1_RCR_LOCK_MASK (0x40000000U)
42782#define SRC_USBOPHY1_RCR_LOCK_SHIFT (30U)
42783/*! LOCK
42784 * 0b0..[31] and [27:24] bits can be modified
42785 * 0b1..[31] and [27:24] bits cannot be modified
42786 */
42787#define SRC_USBOPHY1_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_LOCK_SHIFT)) & SRC_USBOPHY1_RCR_LOCK_MASK)
42788#define SRC_USBOPHY1_RCR_DOM_EN_MASK (0x80000000U)
42789#define SRC_USBOPHY1_RCR_DOM_EN_SHIFT (31U)
42790/*! DOM_EN
42791 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
42792 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
42793 */
42794#define SRC_USBOPHY1_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOM_EN_SHIFT)) & SRC_USBOPHY1_RCR_DOM_EN_MASK)
42795/*! @} */
42796
42797/*! @name USBOPHY2_RCR - USB OTG PHY2 Reset Control Register */
42798/*! @{ */
42799#define SRC_USBOPHY2_RCR_OTG2_PHY_RESET_MASK (0x1U)
42800#define SRC_USBOPHY2_RCR_OTG2_PHY_RESET_SHIFT (0U)
42801/*! OTG2_PHY_RESET
42802 * 0b0..Don't reset USB OTG2 PHY
42803 * 0b1..Reset USB OTG2 PHY
42804 */
42805#define SRC_USBOPHY2_RCR_OTG2_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_OTG2_PHY_RESET_SHIFT)) & SRC_USBOPHY2_RCR_OTG2_PHY_RESET_MASK)
42806#define SRC_USBOPHY2_RCR_DOMAIN0_MASK (0x1000000U)
42807#define SRC_USBOPHY2_RCR_DOMAIN0_SHIFT (24U)
42808/*! DOMAIN0
42809 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
42810 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
42811 */
42812#define SRC_USBOPHY2_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_DOMAIN0_SHIFT)) & SRC_USBOPHY2_RCR_DOMAIN0_MASK)
42813#define SRC_USBOPHY2_RCR_DOMAIN1_MASK (0x2000000U)
42814#define SRC_USBOPHY2_RCR_DOMAIN1_SHIFT (25U)
42815/*! DOMAIN1
42816 * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register.
42817 * 0b1..This register is assigned to domain1. The master from domain3 can write to this register
42818 */
42819#define SRC_USBOPHY2_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_DOMAIN1_SHIFT)) & SRC_USBOPHY2_RCR_DOMAIN1_MASK)
42820#define SRC_USBOPHY2_RCR_DOMAIN2_MASK (0x4000000U)
42821#define SRC_USBOPHY2_RCR_DOMAIN2_SHIFT (26U)
42822/*! DOMAIN2
42823 * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register.
42824 * 0b1..This register is assigned to domain2. The master from domain3 can write to this register
42825 */
42826#define SRC_USBOPHY2_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_DOMAIN2_SHIFT)) & SRC_USBOPHY2_RCR_DOMAIN2_MASK)
42827#define SRC_USBOPHY2_RCR_DOMAIN3_MASK (0x8000000U)
42828#define SRC_USBOPHY2_RCR_DOMAIN3_SHIFT (27U)
42829/*! DOMAIN3
42830 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
42831 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
42832 */
42833#define SRC_USBOPHY2_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_DOMAIN3_SHIFT)) & SRC_USBOPHY2_RCR_DOMAIN3_MASK)
42834#define SRC_USBOPHY2_RCR_LOCK_MASK (0x40000000U)
42835#define SRC_USBOPHY2_RCR_LOCK_SHIFT (30U)
42836/*! LOCK
42837 * 0b0..[31] and [27:24] bits can be modified
42838 * 0b1..[31] and [27:24] bits cannot be modified
42839 */
42840#define SRC_USBOPHY2_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_LOCK_SHIFT)) & SRC_USBOPHY2_RCR_LOCK_MASK)
42841#define SRC_USBOPHY2_RCR_DOM_EN_MASK (0x80000000U)
42842#define SRC_USBOPHY2_RCR_DOM_EN_SHIFT (31U)
42843/*! DOM_EN
42844 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
42845 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
42846 */
42847#define SRC_USBOPHY2_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_DOM_EN_SHIFT)) & SRC_USBOPHY2_RCR_DOM_EN_MASK)
42848/*! @} */
42849
42850/*! @name MIPIPHY_RCR - MIPI PHY Reset Control Register */
42851/*! @{ */
42852#define SRC_MIPIPHY_RCR_MIPI_DSI_RESET_BYTE_N_MASK (0x2U)
42853#define SRC_MIPIPHY_RCR_MIPI_DSI_RESET_BYTE_N_SHIFT (1U)
42854/*! MIPI_DSI_RESET_BYTE_N
42855 * 0b0..Reset
42856 * 0b1..Don't reset
42857 */
42858#define SRC_MIPIPHY_RCR_MIPI_DSI_RESET_BYTE_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_MIPI_DSI_RESET_BYTE_N_SHIFT)) & SRC_MIPIPHY_RCR_MIPI_DSI_RESET_BYTE_N_MASK)
42859#define SRC_MIPIPHY_RCR_MIPI_DSI_RESET_N_MASK (0x4U)
42860#define SRC_MIPIPHY_RCR_MIPI_DSI_RESET_N_SHIFT (2U)
42861/*! MIPI_DSI_RESET_N
42862 * 0b0..Reset
42863 * 0b1..Don't reset
42864 */
42865#define SRC_MIPIPHY_RCR_MIPI_DSI_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_MIPI_DSI_RESET_N_SHIFT)) & SRC_MIPIPHY_RCR_MIPI_DSI_RESET_N_MASK)
42866#define SRC_MIPIPHY_RCR_MIPI_DIS_DPI_RESET_N_MASK (0x8U)
42867#define SRC_MIPIPHY_RCR_MIPI_DIS_DPI_RESET_N_SHIFT (3U)
42868/*! MIPI_DIS_DPI_RESET_N
42869 * 0b0..Reset
42870 * 0b1..Don't reset
42871 */
42872#define SRC_MIPIPHY_RCR_MIPI_DIS_DPI_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_MIPI_DIS_DPI_RESET_N_SHIFT)) & SRC_MIPIPHY_RCR_MIPI_DIS_DPI_RESET_N_MASK)
42873#define SRC_MIPIPHY_RCR_MIPI_DIS_ESC_RESET_N_MASK (0x10U)
42874#define SRC_MIPIPHY_RCR_MIPI_DIS_ESC_RESET_N_SHIFT (4U)
42875/*! MIPI_DIS_ESC_RESET_N
42876 * 0b0..Reset
42877 * 0b1..Don't reset
42878 */
42879#define SRC_MIPIPHY_RCR_MIPI_DIS_ESC_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_MIPI_DIS_ESC_RESET_N_SHIFT)) & SRC_MIPIPHY_RCR_MIPI_DIS_ESC_RESET_N_MASK)
42880#define SRC_MIPIPHY_RCR_MIPI_DIS_PCLK_RESET_N_MASK (0x20U)
42881#define SRC_MIPIPHY_RCR_MIPI_DIS_PCLK_RESET_N_SHIFT (5U)
42882/*! MIPI_DIS_PCLK_RESET_N
42883 * 0b0..Reset
42884 * 0b1..Don't reset
42885 */
42886#define SRC_MIPIPHY_RCR_MIPI_DIS_PCLK_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_MIPI_DIS_PCLK_RESET_N_SHIFT)) & SRC_MIPIPHY_RCR_MIPI_DIS_PCLK_RESET_N_MASK)
42887#define SRC_MIPIPHY_RCR_DOMAIN0_MASK (0x1000000U)
42888#define SRC_MIPIPHY_RCR_DOMAIN0_SHIFT (24U)
42889/*! DOMAIN0
42890 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
42891 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
42892 */
42893#define SRC_MIPIPHY_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN0_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN0_MASK)
42894#define SRC_MIPIPHY_RCR_DOMAIN1_MASK (0x2000000U)
42895#define SRC_MIPIPHY_RCR_DOMAIN1_SHIFT (25U)
42896/*! DOMAIN1
42897 * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register.
42898 * 0b1..This register is assigned to domain1. The master from domain3 can write to this register
42899 */
42900#define SRC_MIPIPHY_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN1_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN1_MASK)
42901#define SRC_MIPIPHY_RCR_DOMAIN2_MASK (0x4000000U)
42902#define SRC_MIPIPHY_RCR_DOMAIN2_SHIFT (26U)
42903/*! DOMAIN2
42904 * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register.
42905 * 0b1..This register is assigned to domain2. The master from domain3 can write to this register
42906 */
42907#define SRC_MIPIPHY_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN2_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN2_MASK)
42908#define SRC_MIPIPHY_RCR_DOMAIN3_MASK (0x8000000U)
42909#define SRC_MIPIPHY_RCR_DOMAIN3_SHIFT (27U)
42910/*! DOMAIN3
42911 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
42912 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
42913 */
42914#define SRC_MIPIPHY_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN3_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN3_MASK)
42915#define SRC_MIPIPHY_RCR_LOCK_MASK (0x40000000U)
42916#define SRC_MIPIPHY_RCR_LOCK_SHIFT (30U)
42917/*! LOCK
42918 * 0b0..[31] and [27:24] bits can be modified
42919 * 0b1..[31] and [27:24] bits cannot be modified
42920 */
42921#define SRC_MIPIPHY_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_LOCK_SHIFT)) & SRC_MIPIPHY_RCR_LOCK_MASK)
42922#define SRC_MIPIPHY_RCR_DOM_EN_MASK (0x80000000U)
42923#define SRC_MIPIPHY_RCR_DOM_EN_SHIFT (31U)
42924/*! DOM_EN
42925 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
42926 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
42927 */
42928#define SRC_MIPIPHY_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOM_EN_SHIFT)) & SRC_MIPIPHY_RCR_DOM_EN_MASK)
42929/*! @} */
42930
42931/*! @name PCIEPHY_RCR - PCIE PHY Reset Control Register */
42932/*! @{ */
42933#define SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_N_MASK (0x1U)
42934#define SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_N_SHIFT (0U)
42935#define SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_N_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_N_MASK)
42936#define SRC_PCIEPHY_RCR_PCIEPHY_G_RST_MASK (0x2U)
42937#define SRC_PCIEPHY_RCR_PCIEPHY_G_RST_SHIFT (1U)
42938#define SRC_PCIEPHY_RCR_PCIEPHY_G_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIEPHY_G_RST_SHIFT)) & SRC_PCIEPHY_RCR_PCIEPHY_G_RST_MASK)
42939#define SRC_PCIEPHY_RCR_PCIEPHY_BTN_MASK (0x4U)
42940#define SRC_PCIEPHY_RCR_PCIEPHY_BTN_SHIFT (2U)
42941#define SRC_PCIEPHY_RCR_PCIEPHY_BTN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIEPHY_BTN_SHIFT)) & SRC_PCIEPHY_RCR_PCIEPHY_BTN_MASK)
42942#define SRC_PCIEPHY_RCR_PCIEPHY_PERST_MASK (0x8U)
42943#define SRC_PCIEPHY_RCR_PCIEPHY_PERST_SHIFT (3U)
42944#define SRC_PCIEPHY_RCR_PCIEPHY_PERST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIEPHY_PERST_SHIFT)) & SRC_PCIEPHY_RCR_PCIEPHY_PERST_MASK)
42945#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_MASK (0x10U)
42946#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_SHIFT (4U)
42947#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_MASK)
42948#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_MASK (0x20U)
42949#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_SHIFT (5U)
42950#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_MASK)
42951#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_MASK (0x40U)
42952#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_SHIFT (6U)
42953#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_MASK)
42954#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_MASK (0x80U)
42955#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_SHIFT (7U)
42956#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_MASK)
42957#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_MASK (0x100U)
42958#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_SHIFT (8U)
42959#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_MASK)
42960#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_MASK (0x200U)
42961#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_SHIFT (9U)
42962#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_MASK)
42963#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_MASK (0x400U)
42964#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_SHIFT (10U)
42965#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_MASK)
42966#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_MASK (0x800U)
42967#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_SHIFT (11U)
42968#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_MASK)
42969#define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_MASK (0x1000U)
42970#define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_SHIFT (12U)
42971#define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_MASK)
42972#define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_MASK (0x4000U)
42973#define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_SHIFT (14U)
42974#define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_MASK)
42975#define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_MASK (0x8000U)
42976#define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_SHIFT (15U)
42977#define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_MASK)
42978#define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_MASK (0x10000U)
42979#define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_SHIFT (16U)
42980#define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_MASK)
42981#define SRC_PCIEPHY_RCR_DOMAIN0_MASK (0x1000000U)
42982#define SRC_PCIEPHY_RCR_DOMAIN0_SHIFT (24U)
42983/*! DOMAIN0
42984 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
42985 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
42986 */
42987#define SRC_PCIEPHY_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN0_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN0_MASK)
42988#define SRC_PCIEPHY_RCR_DOMAIN1_MASK (0x2000000U)
42989#define SRC_PCIEPHY_RCR_DOMAIN1_SHIFT (25U)
42990/*! DOMAIN1
42991 * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register.
42992 * 0b1..This register is assigned to domain1. The master from domain3 can write to this register
42993 */
42994#define SRC_PCIEPHY_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN1_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN1_MASK)
42995#define SRC_PCIEPHY_RCR_DOMAIN2_MASK (0x4000000U)
42996#define SRC_PCIEPHY_RCR_DOMAIN2_SHIFT (26U)
42997/*! DOMAIN2
42998 * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register.
42999 * 0b1..This register is assigned to domain2. The master from domain3 can write to this register
43000 */
43001#define SRC_PCIEPHY_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN2_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN2_MASK)
43002#define SRC_PCIEPHY_RCR_DOMAIN3_MASK (0x8000000U)
43003#define SRC_PCIEPHY_RCR_DOMAIN3_SHIFT (27U)
43004/*! DOMAIN3
43005 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
43006 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
43007 */
43008#define SRC_PCIEPHY_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN3_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN3_MASK)
43009#define SRC_PCIEPHY_RCR_LOCK_MASK (0x40000000U)
43010#define SRC_PCIEPHY_RCR_LOCK_SHIFT (30U)
43011/*! LOCK
43012 * 0b0..[31] and [27:24] bits can be modified
43013 * 0b1..[31] and [27:24] bits cannot be modified
43014 */
43015#define SRC_PCIEPHY_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_LOCK_SHIFT)) & SRC_PCIEPHY_RCR_LOCK_MASK)
43016#define SRC_PCIEPHY_RCR_DOM_EN_MASK (0x80000000U)
43017#define SRC_PCIEPHY_RCR_DOM_EN_SHIFT (31U)
43018/*! DOM_EN
43019 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
43020 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
43021 */
43022#define SRC_PCIEPHY_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOM_EN_SHIFT)) & SRC_PCIEPHY_RCR_DOM_EN_MASK)
43023/*! @} */
43024
43025/*! @name HDMI_RCR - HDMI Reset Control Register */
43026/*! @{ */
43027#define SRC_HDMI_RCR_HDMI_PHY_APB_RESET_MASK (0x1U)
43028#define SRC_HDMI_RCR_HDMI_PHY_APB_RESET_SHIFT (0U)
43029#define SRC_HDMI_RCR_HDMI_PHY_APB_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_HDMI_PHY_APB_RESET_SHIFT)) & SRC_HDMI_RCR_HDMI_PHY_APB_RESET_MASK)
43030#define SRC_HDMI_RCR_DOMAIN0_MASK (0x1000000U)
43031#define SRC_HDMI_RCR_DOMAIN0_SHIFT (24U)
43032/*! DOMAIN0
43033 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
43034 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
43035 */
43036#define SRC_HDMI_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN0_SHIFT)) & SRC_HDMI_RCR_DOMAIN0_MASK)
43037#define SRC_HDMI_RCR_DOMAIN1_MASK (0x2000000U)
43038#define SRC_HDMI_RCR_DOMAIN1_SHIFT (25U)
43039/*! DOMAIN1
43040 * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register.
43041 * 0b1..This register is assigned to domain1. The master from domain3 can write to this register
43042 */
43043#define SRC_HDMI_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN1_SHIFT)) & SRC_HDMI_RCR_DOMAIN1_MASK)
43044#define SRC_HDMI_RCR_DOMAIN2_MASK (0x4000000U)
43045#define SRC_HDMI_RCR_DOMAIN2_SHIFT (26U)
43046/*! DOMAIN2
43047 * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register.
43048 * 0b1..This register is assigned to domain2. The master from domain3 can write to this register
43049 */
43050#define SRC_HDMI_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN2_SHIFT)) & SRC_HDMI_RCR_DOMAIN2_MASK)
43051#define SRC_HDMI_RCR_DOMAIN3_MASK (0x8000000U)
43052#define SRC_HDMI_RCR_DOMAIN3_SHIFT (27U)
43053/*! DOMAIN3
43054 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
43055 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
43056 */
43057#define SRC_HDMI_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN3_SHIFT)) & SRC_HDMI_RCR_DOMAIN3_MASK)
43058#define SRC_HDMI_RCR_LOCK_MASK (0x40000000U)
43059#define SRC_HDMI_RCR_LOCK_SHIFT (30U)
43060/*! LOCK
43061 * 0b0..[31] and [27:24] bits can be modified
43062 * 0b1..[31] and [27:24] bits cannot be modified
43063 */
43064#define SRC_HDMI_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_LOCK_SHIFT)) & SRC_HDMI_RCR_LOCK_MASK)
43065#define SRC_HDMI_RCR_DOM_EN_MASK (0x80000000U)
43066#define SRC_HDMI_RCR_DOM_EN_SHIFT (31U)
43067/*! DOM_EN
43068 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
43069 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
43070 */
43071#define SRC_HDMI_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOM_EN_SHIFT)) & SRC_HDMI_RCR_DOM_EN_MASK)
43072/*! @} */
43073
43074/*! @name DISP_RCR - DISP Reset Control Register */
43075/*! @{ */
43076#define SRC_DISP_RCR_DISP_RESET_MASK (0x1U)
43077#define SRC_DISP_RCR_DISP_RESET_SHIFT (0U)
43078/*! DISP_RESET
43079 * 0b0..Don't reset dispmix
43080 * 0b1..Reset dispmix
43081 */
43082#define SRC_DISP_RCR_DISP_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DISP_RESET_SHIFT)) & SRC_DISP_RCR_DISP_RESET_MASK)
43083#define SRC_DISP_RCR_DOMAIN0_MASK (0x1000000U)
43084#define SRC_DISP_RCR_DOMAIN0_SHIFT (24U)
43085/*! DOMAIN0
43086 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
43087 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
43088 */
43089#define SRC_DISP_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN0_SHIFT)) & SRC_DISP_RCR_DOMAIN0_MASK)
43090#define SRC_DISP_RCR_DOMAIN1_MASK (0x2000000U)
43091#define SRC_DISP_RCR_DOMAIN1_SHIFT (25U)
43092/*! DOMAIN1
43093 * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register.
43094 * 0b1..This register is assigned to domain1. The master from domain3 can write to this register
43095 */
43096#define SRC_DISP_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN1_SHIFT)) & SRC_DISP_RCR_DOMAIN1_MASK)
43097#define SRC_DISP_RCR_DOMAIN2_MASK (0x4000000U)
43098#define SRC_DISP_RCR_DOMAIN2_SHIFT (26U)
43099/*! DOMAIN2
43100 * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register.
43101 * 0b1..This register is assigned to domain2. The master from domain3 can write to this register
43102 */
43103#define SRC_DISP_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN2_SHIFT)) & SRC_DISP_RCR_DOMAIN2_MASK)
43104#define SRC_DISP_RCR_DOMAIN3_MASK (0x8000000U)
43105#define SRC_DISP_RCR_DOMAIN3_SHIFT (27U)
43106/*! DOMAIN3
43107 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
43108 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
43109 */
43110#define SRC_DISP_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN3_SHIFT)) & SRC_DISP_RCR_DOMAIN3_MASK)
43111#define SRC_DISP_RCR_LOCK_MASK (0x40000000U)
43112#define SRC_DISP_RCR_LOCK_SHIFT (30U)
43113/*! LOCK
43114 * 0b0..[31] and [27:24] bits can be modified
43115 * 0b1..[31] and [27:24] bits cannot be modified
43116 */
43117#define SRC_DISP_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_LOCK_SHIFT)) & SRC_DISP_RCR_LOCK_MASK)
43118#define SRC_DISP_RCR_DOM_EN_MASK (0x80000000U)
43119#define SRC_DISP_RCR_DOM_EN_SHIFT (31U)
43120/*! DOM_EN
43121 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
43122 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
43123 */
43124#define SRC_DISP_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOM_EN_SHIFT)) & SRC_DISP_RCR_DOM_EN_MASK)
43125/*! @} */
43126
43127/*! @name GPU_RCR - GPU Reset Control Register */
43128/*! @{ */
43129#define SRC_GPU_RCR_GPU_RESET_MASK (0x1U)
43130#define SRC_GPU_RCR_GPU_RESET_SHIFT (0U)
43131#define SRC_GPU_RCR_GPU_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_GPU_RESET_SHIFT)) & SRC_GPU_RCR_GPU_RESET_MASK)
43132#define SRC_GPU_RCR_DOMAIN0_MASK (0x1000000U)
43133#define SRC_GPU_RCR_DOMAIN0_SHIFT (24U)
43134/*! DOMAIN0
43135 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
43136 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
43137 */
43138#define SRC_GPU_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN0_SHIFT)) & SRC_GPU_RCR_DOMAIN0_MASK)
43139#define SRC_GPU_RCR_DOMAIN1_MASK (0x2000000U)
43140#define SRC_GPU_RCR_DOMAIN1_SHIFT (25U)
43141/*! DOMAIN1
43142 * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register.
43143 * 0b1..This register is assigned to domain1. The master from domain3 can write to this register
43144 */
43145#define SRC_GPU_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN1_SHIFT)) & SRC_GPU_RCR_DOMAIN1_MASK)
43146#define SRC_GPU_RCR_DOMAIN2_MASK (0x4000000U)
43147#define SRC_GPU_RCR_DOMAIN2_SHIFT (26U)
43148/*! DOMAIN2
43149 * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register.
43150 * 0b1..This register is assigned to domain2. The master from domain3 can write to this register
43151 */
43152#define SRC_GPU_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN2_SHIFT)) & SRC_GPU_RCR_DOMAIN2_MASK)
43153#define SRC_GPU_RCR_DOMAIN3_MASK (0x8000000U)
43154#define SRC_GPU_RCR_DOMAIN3_SHIFT (27U)
43155/*! DOMAIN3
43156 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
43157 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
43158 */
43159#define SRC_GPU_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN3_SHIFT)) & SRC_GPU_RCR_DOMAIN3_MASK)
43160#define SRC_GPU_RCR_LOCK_MASK (0x40000000U)
43161#define SRC_GPU_RCR_LOCK_SHIFT (30U)
43162/*! LOCK
43163 * 0b0..[31] and [27:24] bits can be modified
43164 * 0b1..[31] and [27:24] bits cannot be modified
43165 */
43166#define SRC_GPU_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_LOCK_SHIFT)) & SRC_GPU_RCR_LOCK_MASK)
43167#define SRC_GPU_RCR_DOM_EN_MASK (0x80000000U)
43168#define SRC_GPU_RCR_DOM_EN_SHIFT (31U)
43169/*! DOM_EN
43170 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
43171 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
43172 */
43173#define SRC_GPU_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOM_EN_SHIFT)) & SRC_GPU_RCR_DOM_EN_MASK)
43174/*! @} */
43175
43176/*! @name VPU_RCR - VPU Reset Control Register */
43177/*! @{ */
43178#define SRC_VPU_RCR_VPU_RESET_MASK (0x1U)
43179#define SRC_VPU_RCR_VPU_RESET_SHIFT (0U)
43180#define SRC_VPU_RCR_VPU_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_VPU_RESET_SHIFT)) & SRC_VPU_RCR_VPU_RESET_MASK)
43181#define SRC_VPU_RCR_DOMAIN0_MASK (0x1000000U)
43182#define SRC_VPU_RCR_DOMAIN0_SHIFT (24U)
43183/*! DOMAIN0
43184 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
43185 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
43186 */
43187#define SRC_VPU_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN0_SHIFT)) & SRC_VPU_RCR_DOMAIN0_MASK)
43188#define SRC_VPU_RCR_DOMAIN1_MASK (0x2000000U)
43189#define SRC_VPU_RCR_DOMAIN1_SHIFT (25U)
43190/*! DOMAIN1
43191 * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register.
43192 * 0b1..This register is assigned to domain1. The master from domain3 can write to this register
43193 */
43194#define SRC_VPU_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN1_SHIFT)) & SRC_VPU_RCR_DOMAIN1_MASK)
43195#define SRC_VPU_RCR_DOMAIN2_MASK (0x4000000U)
43196#define SRC_VPU_RCR_DOMAIN2_SHIFT (26U)
43197/*! DOMAIN2
43198 * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register.
43199 * 0b1..This register is assigned to domain2. The master from domain3 can write to this register
43200 */
43201#define SRC_VPU_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN2_SHIFT)) & SRC_VPU_RCR_DOMAIN2_MASK)
43202#define SRC_VPU_RCR_DOMAIN3_MASK (0x8000000U)
43203#define SRC_VPU_RCR_DOMAIN3_SHIFT (27U)
43204/*! DOMAIN3
43205 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
43206 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
43207 */
43208#define SRC_VPU_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN3_SHIFT)) & SRC_VPU_RCR_DOMAIN3_MASK)
43209#define SRC_VPU_RCR_LOCK_MASK (0x40000000U)
43210#define SRC_VPU_RCR_LOCK_SHIFT (30U)
43211/*! LOCK
43212 * 0b0..[31] and [27:24] bits can be modified
43213 * 0b1..[31] and [27:24] bits cannot be modified
43214 */
43215#define SRC_VPU_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_LOCK_SHIFT)) & SRC_VPU_RCR_LOCK_MASK)
43216#define SRC_VPU_RCR_DOM_EN_MASK (0x80000000U)
43217#define SRC_VPU_RCR_DOM_EN_SHIFT (31U)
43218/*! DOM_EN
43219 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
43220 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
43221 */
43222#define SRC_VPU_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOM_EN_SHIFT)) & SRC_VPU_RCR_DOM_EN_MASK)
43223/*! @} */
43224
43225/*! @name PCIE2_RCR - PCIE2 Reset Control Register */
43226/*! @{ */
43227#define SRC_PCIE2_RCR_PCIE_PHY_POWER_ON_RESET_N_MASK (0x1U)
43228#define SRC_PCIE2_RCR_PCIE_PHY_POWER_ON_RESET_N_SHIFT (0U)
43229#define SRC_PCIE2_RCR_PCIE_PHY_POWER_ON_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_PHY_POWER_ON_RESET_N_SHIFT)) & SRC_PCIE2_RCR_PCIE_PHY_POWER_ON_RESET_N_MASK)
43230#define SRC_PCIE2_RCR_PCIE_G_RST_MASK (0x2U)
43231#define SRC_PCIE2_RCR_PCIE_G_RST_SHIFT (1U)
43232#define SRC_PCIE2_RCR_PCIE_G_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_G_RST_SHIFT)) & SRC_PCIE2_RCR_PCIE_G_RST_MASK)
43233#define SRC_PCIE2_RCR_PCIE_BTN_MASK (0x4U)
43234#define SRC_PCIE2_RCR_PCIE_BTN_SHIFT (2U)
43235#define SRC_PCIE2_RCR_PCIE_BTN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_BTN_SHIFT)) & SRC_PCIE2_RCR_PCIE_BTN_MASK)
43236#define SRC_PCIE2_RCR_PCIE_PERST_MASK (0x8U)
43237#define SRC_PCIE2_RCR_PCIE_PERST_SHIFT (3U)
43238#define SRC_PCIE2_RCR_PCIE_PERST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_PERST_SHIFT)) & SRC_PCIE2_RCR_PCIE_PERST_MASK)
43239#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_CLK_REQ_MASK (0x10U)
43240#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_CLK_REQ_SHIFT (4U)
43241#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_CLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_CLK_REQ_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_CLK_REQ_MASK)
43242#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_RST_MASK (0x20U)
43243#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_RST_SHIFT (5U)
43244#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_RST_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_RST_MASK)
43245#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_EN_MASK (0x40U)
43246#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_EN_SHIFT (6U)
43247#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_EN_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_EN_MASK)
43248#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_READY_MASK (0x80U)
43249#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_READY_SHIFT (7U)
43250#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_READY(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_READY_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_READY_MASK)
43251#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_ENTER_MASK (0x100U)
43252#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_ENTER_SHIFT (8U)
43253#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_ENTER(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_ENTER_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_ENTER_MASK)
43254#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_EXIT_MASK (0x200U)
43255#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_EXIT_SHIFT (9U)
43256#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_EXIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_EXIT_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_EXIT_MASK)
43257#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_PME_MASK (0x400U)
43258#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_PME_SHIFT (10U)
43259#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_PME(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_PME_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_PME_MASK)
43260#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_TURNOFF_MASK (0x800U)
43261#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_TURNOFF_SHIFT (11U)
43262#define SRC_PCIE2_RCR_PCIE_CTRL_APPS_TURNOFF(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_TURNOFF_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_TURNOFF_MASK)
43263#define SRC_PCIE2_RCR_PCIE_CTRL_CFG_L1_AUX_MASK (0x1000U)
43264#define SRC_PCIE2_RCR_PCIE_CTRL_CFG_L1_AUX_SHIFT (12U)
43265#define SRC_PCIE2_RCR_PCIE_CTRL_CFG_L1_AUX(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_CFG_L1_AUX_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_CFG_L1_AUX_MASK)
43266#define SRC_PCIE2_RCR_PCIE_CTRL_SYS_INT_MASK (0x4000U)
43267#define SRC_PCIE2_RCR_PCIE_CTRL_SYS_INT_SHIFT (14U)
43268#define SRC_PCIE2_RCR_PCIE_CTRL_SYS_INT(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_SYS_INT_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_SYS_INT_MASK)
43269#define SRC_PCIE2_RCR_PCIE_CTRL_APP_UNLOCK_MSG_MASK (0x8000U)
43270#define SRC_PCIE2_RCR_PCIE_CTRL_APP_UNLOCK_MSG_SHIFT (15U)
43271#define SRC_PCIE2_RCR_PCIE_CTRL_APP_UNLOCK_MSG(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APP_UNLOCK_MSG_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APP_UNLOCK_MSG_MASK)
43272#define SRC_PCIE2_RCR_PCIE_CTRL_APP_XFER_PENDING_MASK (0x10000U)
43273#define SRC_PCIE2_RCR_PCIE_CTRL_APP_XFER_PENDING_SHIFT (16U)
43274#define SRC_PCIE2_RCR_PCIE_CTRL_APP_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APP_XFER_PENDING_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APP_XFER_PENDING_MASK)
43275#define SRC_PCIE2_RCR_DOMAIN0_MASK (0x1000000U)
43276#define SRC_PCIE2_RCR_DOMAIN0_SHIFT (24U)
43277/*! DOMAIN0
43278 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
43279 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
43280 */
43281#define SRC_PCIE2_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_DOMAIN0_SHIFT)) & SRC_PCIE2_RCR_DOMAIN0_MASK)
43282#define SRC_PCIE2_RCR_DOMAIN1_MASK (0x2000000U)
43283#define SRC_PCIE2_RCR_DOMAIN1_SHIFT (25U)
43284/*! DOMAIN1
43285 * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register.
43286 * 0b1..This register is assigned to domain1. The master from domain3 can write to this register
43287 */
43288#define SRC_PCIE2_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_DOMAIN1_SHIFT)) & SRC_PCIE2_RCR_DOMAIN1_MASK)
43289#define SRC_PCIE2_RCR_DOMAIN2_MASK (0x4000000U)
43290#define SRC_PCIE2_RCR_DOMAIN2_SHIFT (26U)
43291/*! DOMAIN2
43292 * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register.
43293 * 0b1..This register is assigned to domain2. The master from domain3 can write to this register
43294 */
43295#define SRC_PCIE2_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_DOMAIN2_SHIFT)) & SRC_PCIE2_RCR_DOMAIN2_MASK)
43296#define SRC_PCIE2_RCR_DOMAIN3_MASK (0x8000000U)
43297#define SRC_PCIE2_RCR_DOMAIN3_SHIFT (27U)
43298/*! DOMAIN3
43299 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
43300 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
43301 */
43302#define SRC_PCIE2_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_DOMAIN3_SHIFT)) & SRC_PCIE2_RCR_DOMAIN3_MASK)
43303#define SRC_PCIE2_RCR_LOCK_MASK (0x40000000U)
43304#define SRC_PCIE2_RCR_LOCK_SHIFT (30U)
43305/*! LOCK
43306 * 0b0..[31] and [27:24] bits can be modified
43307 * 0b1..[31] and [27:24] bits cannot be modified
43308 */
43309#define SRC_PCIE2_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_LOCK_SHIFT)) & SRC_PCIE2_RCR_LOCK_MASK)
43310#define SRC_PCIE2_RCR_DOM_EN_MASK (0x80000000U)
43311#define SRC_PCIE2_RCR_DOM_EN_SHIFT (31U)
43312/*! DOM_EN
43313 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
43314 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
43315 */
43316#define SRC_PCIE2_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_DOM_EN_SHIFT)) & SRC_PCIE2_RCR_DOM_EN_MASK)
43317/*! @} */
43318
43319/*! @name MIPIPHY1_RCR - MIPI CSI1 PHY Reset Control Register */
43320/*! @{ */
43321#define SRC_MIPIPHY1_RCR_MIPI_CSI1_CORE_RESET_MASK (0x1U)
43322#define SRC_MIPIPHY1_RCR_MIPI_CSI1_CORE_RESET_SHIFT (0U)
43323#define SRC_MIPIPHY1_RCR_MIPI_CSI1_CORE_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_MIPI_CSI1_CORE_RESET_SHIFT)) & SRC_MIPIPHY1_RCR_MIPI_CSI1_CORE_RESET_MASK)
43324#define SRC_MIPIPHY1_RCR_MIPI_CSI1_PHY_REF_RESET_MASK (0x2U)
43325#define SRC_MIPIPHY1_RCR_MIPI_CSI1_PHY_REF_RESET_SHIFT (1U)
43326#define SRC_MIPIPHY1_RCR_MIPI_CSI1_PHY_REF_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_MIPI_CSI1_PHY_REF_RESET_SHIFT)) & SRC_MIPIPHY1_RCR_MIPI_CSI1_PHY_REF_RESET_MASK)
43327#define SRC_MIPIPHY1_RCR_MIPI_CSI1_ESC_RESET_MASK (0x4U)
43328#define SRC_MIPIPHY1_RCR_MIPI_CSI1_ESC_RESET_SHIFT (2U)
43329#define SRC_MIPIPHY1_RCR_MIPI_CSI1_ESC_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_MIPI_CSI1_ESC_RESET_SHIFT)) & SRC_MIPIPHY1_RCR_MIPI_CSI1_ESC_RESET_MASK)
43330#define SRC_MIPIPHY1_RCR_DOMAIN0_MASK (0x1000000U)
43331#define SRC_MIPIPHY1_RCR_DOMAIN0_SHIFT (24U)
43332/*! DOMAIN0
43333 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
43334 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
43335 */
43336#define SRC_MIPIPHY1_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN0_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN0_MASK)
43337#define SRC_MIPIPHY1_RCR_DOMAIN1_MASK (0x2000000U)
43338#define SRC_MIPIPHY1_RCR_DOMAIN1_SHIFT (25U)
43339/*! DOMAIN1
43340 * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register.
43341 * 0b1..This register is assigned to domain1. The master from domain3 can write to this register
43342 */
43343#define SRC_MIPIPHY1_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN1_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN1_MASK)
43344#define SRC_MIPIPHY1_RCR_DOMAIN2_MASK (0x4000000U)
43345#define SRC_MIPIPHY1_RCR_DOMAIN2_SHIFT (26U)
43346/*! DOMAIN2
43347 * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register.
43348 * 0b1..This register is assigned to domain2. The master from domain3 can write to this register
43349 */
43350#define SRC_MIPIPHY1_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN2_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN2_MASK)
43351#define SRC_MIPIPHY1_RCR_DOMAIN3_MASK (0x8000000U)
43352#define SRC_MIPIPHY1_RCR_DOMAIN3_SHIFT (27U)
43353/*! DOMAIN3
43354 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
43355 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
43356 */
43357#define SRC_MIPIPHY1_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN3_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN3_MASK)
43358#define SRC_MIPIPHY1_RCR_LOCK_MASK (0x40000000U)
43359#define SRC_MIPIPHY1_RCR_LOCK_SHIFT (30U)
43360/*! LOCK
43361 * 0b0..[31] and [27:24] bits can be modified
43362 * 0b1..[31] and [27:24] bits cannot be modified
43363 */
43364#define SRC_MIPIPHY1_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_LOCK_SHIFT)) & SRC_MIPIPHY1_RCR_LOCK_MASK)
43365#define SRC_MIPIPHY1_RCR_DOM_EN_MASK (0x80000000U)
43366#define SRC_MIPIPHY1_RCR_DOM_EN_SHIFT (31U)
43367/*! DOM_EN
43368 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
43369 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
43370 */
43371#define SRC_MIPIPHY1_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOM_EN_SHIFT)) & SRC_MIPIPHY1_RCR_DOM_EN_MASK)
43372/*! @} */
43373
43374/*! @name MIPIPHY2_RCR - MIPI CSI2 PHY Reset Control Register */
43375/*! @{ */
43376#define SRC_MIPIPHY2_RCR_MIPI_CSI2_CORE_RESET_MASK (0x1U)
43377#define SRC_MIPIPHY2_RCR_MIPI_CSI2_CORE_RESET_SHIFT (0U)
43378#define SRC_MIPIPHY2_RCR_MIPI_CSI2_CORE_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_MIPI_CSI2_CORE_RESET_SHIFT)) & SRC_MIPIPHY2_RCR_MIPI_CSI2_CORE_RESET_MASK)
43379#define SRC_MIPIPHY2_RCR_MIPI_CSI2_PHY_REF_RESET_MASK (0x2U)
43380#define SRC_MIPIPHY2_RCR_MIPI_CSI2_PHY_REF_RESET_SHIFT (1U)
43381#define SRC_MIPIPHY2_RCR_MIPI_CSI2_PHY_REF_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_MIPI_CSI2_PHY_REF_RESET_SHIFT)) & SRC_MIPIPHY2_RCR_MIPI_CSI2_PHY_REF_RESET_MASK)
43382#define SRC_MIPIPHY2_RCR_MIPI_CSI2_ESC_RESET_MASK (0x4U)
43383#define SRC_MIPIPHY2_RCR_MIPI_CSI2_ESC_RESET_SHIFT (2U)
43384#define SRC_MIPIPHY2_RCR_MIPI_CSI2_ESC_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_MIPI_CSI2_ESC_RESET_SHIFT)) & SRC_MIPIPHY2_RCR_MIPI_CSI2_ESC_RESET_MASK)
43385#define SRC_MIPIPHY2_RCR_DOMAIN0_MASK (0x1000000U)
43386#define SRC_MIPIPHY2_RCR_DOMAIN0_SHIFT (24U)
43387/*! DOMAIN0
43388 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
43389 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
43390 */
43391#define SRC_MIPIPHY2_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN0_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN0_MASK)
43392#define SRC_MIPIPHY2_RCR_DOMAIN1_MASK (0x2000000U)
43393#define SRC_MIPIPHY2_RCR_DOMAIN1_SHIFT (25U)
43394/*! DOMAIN1
43395 * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register.
43396 * 0b1..This register is assigned to domain1. The master from domain3 can write to this register
43397 */
43398#define SRC_MIPIPHY2_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN1_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN1_MASK)
43399#define SRC_MIPIPHY2_RCR_DOMAIN2_MASK (0x4000000U)
43400#define SRC_MIPIPHY2_RCR_DOMAIN2_SHIFT (26U)
43401/*! DOMAIN2
43402 * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register.
43403 * 0b1..This register is assigned to domain2. The master from domain3 can write to this register
43404 */
43405#define SRC_MIPIPHY2_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN2_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN2_MASK)
43406#define SRC_MIPIPHY2_RCR_DOMAIN3_MASK (0x8000000U)
43407#define SRC_MIPIPHY2_RCR_DOMAIN3_SHIFT (27U)
43408/*! DOMAIN3
43409 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
43410 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
43411 */
43412#define SRC_MIPIPHY2_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN3_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN3_MASK)
43413#define SRC_MIPIPHY2_RCR_LOCK_MASK (0x40000000U)
43414#define SRC_MIPIPHY2_RCR_LOCK_SHIFT (30U)
43415/*! LOCK
43416 * 0b0..[31] and [27:24] bits can be modified
43417 * 0b1..[31] and [27:24] bits cannot be modified
43418 */
43419#define SRC_MIPIPHY2_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_LOCK_SHIFT)) & SRC_MIPIPHY2_RCR_LOCK_MASK)
43420#define SRC_MIPIPHY2_RCR_DOM_EN_MASK (0x80000000U)
43421#define SRC_MIPIPHY2_RCR_DOM_EN_SHIFT (31U)
43422/*! DOM_EN
43423 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
43424 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
43425 */
43426#define SRC_MIPIPHY2_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOM_EN_SHIFT)) & SRC_MIPIPHY2_RCR_DOM_EN_MASK)
43427/*! @} */
43428
43429/*! @name SBMR1 - SRC Boot Mode Register 1 */
43430/*! @{ */
43431#define SRC_SBMR1_BOOT_CFG_MASK (0xFFFFFFFFU)
43432#define SRC_SBMR1_BOOT_CFG_SHIFT (0U)
43433#define SRC_SBMR1_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG_SHIFT)) & SRC_SBMR1_BOOT_CFG_MASK)
43434/*! @} */
43435
43436/*! @name SRSR - SRC Reset Status Register */
43437/*! @{ */
43438#define SRC_SRSR_CSU_RESET_B_MASK (0x4U)
43439#define SRC_SRSR_CSU_RESET_B_SHIFT (2U)
43440/*! csu_reset_b
43441 * 0b0..Reset is not a result of the csu_reset_b event.
43442 * 0b1..Reset is a result of the csu_reset_b event.
43443 */
43444#define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)
43445#define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U)
43446#define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U)
43447/*! ipp_user_reset_b
43448 * 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
43449 * 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
43450 */
43451#define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)
43452#define SRC_SRSR_WDOG1_RST_B_MASK (0x10U)
43453#define SRC_SRSR_WDOG1_RST_B_SHIFT (4U)
43454/*! wdog1_rst_b
43455 * 0b0..Reset is not a result of the watchdog1 time-out event.
43456 * 0b1..Reset is a result of the watchdog1 time-out event.
43457 */
43458#define SRC_SRSR_WDOG1_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG1_RST_B_SHIFT)) & SRC_SRSR_WDOG1_RST_B_MASK)
43459#define SRC_SRSR_JTAG_RST_B_MASK (0x20U)
43460#define SRC_SRSR_JTAG_RST_B_SHIFT (5U)
43461/*! jtag_rst_b
43462 * 0b0..Reset is not a result of HIGH-Z reset from JTAG.
43463 * 0b1..Reset is a result of HIGH-Z reset from JTAG.
43464 */
43465#define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)
43466#define SRC_SRSR_JTAG_SW_RST_MASK (0x40U)
43467#define SRC_SRSR_JTAG_SW_RST_SHIFT (6U)
43468/*! jtag_sw_rst
43469 * 0b0..Reset is not a result of software reset from JTAG.
43470 * 0b1..Reset is a result of software reset from JTAG.
43471 */
43472#define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)
43473#define SRC_SRSR_WDOG3_RST_B_MASK (0x80U)
43474#define SRC_SRSR_WDOG3_RST_B_SHIFT (7U)
43475/*! wdog3_rst_b
43476 * 0b0..Reset is not a result of the watchdog3 time-out event.
43477 * 0b1..Reset is a result of the watchdog3 time-out event.
43478 */
43479#define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)
43480#define SRC_SRSR_WDOG4_RST_B_MASK (0x100U)
43481#define SRC_SRSR_WDOG4_RST_B_SHIFT (8U)
43482/*! wdog4_rst_b
43483 * 0b0..Reset is not a result of the watchdog4 time-out event.
43484 * 0b1..Reset is a result of the watchdog4 time-out event.
43485 */
43486#define SRC_SRSR_WDOG4_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_SHIFT)) & SRC_SRSR_WDOG4_RST_B_MASK)
43487#define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x200U)
43488#define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (9U)
43489/*! tempsense_rst_b
43490 * 0b0..Reset is not a result of software reset from Temperature Sensor.
43491 * 0b1..Reset is a result of software reset from Temperature Sensor.
43492 */
43493#define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)
43494/*! @} */
43495
43496/*! @name SISR - SRC Interrupt Status Register */
43497/*! @{ */
43498#define SRC_SISR_HSICPHY_PASSED_RESET_MASK (0x2U)
43499#define SRC_SISR_HSICPHY_PASSED_RESET_SHIFT (1U)
43500/*! HSICPHY_PASSED_RESET
43501 * 0b0..Interrupt generated not due to HSIC PHY passed reset
43502 * 0b1..Interrupt generated due to HSIC PHY passed reset
43503 */
43504#define SRC_SISR_HSICPHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_HSICPHY_PASSED_RESET_SHIFT)) & SRC_SISR_HSICPHY_PASSED_RESET_MASK)
43505#define SRC_SISR_OTGPHY1_PASSED_RESET_MASK (0x4U)
43506#define SRC_SISR_OTGPHY1_PASSED_RESET_SHIFT (2U)
43507/*! OTGPHY1_PASSED_RESET
43508 * 0b0..Interrupt generated not due to OTG PHY1 passed reset
43509 * 0b1..Interrupt generated due to OTG PHY1 passed reset
43510 */
43511#define SRC_SISR_OTGPHY1_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_OTGPHY1_PASSED_RESET_SHIFT)) & SRC_SISR_OTGPHY1_PASSED_RESET_MASK)
43512#define SRC_SISR_OTGPHY2_PASSED_RESET_MASK (0x8U)
43513#define SRC_SISR_OTGPHY2_PASSED_RESET_SHIFT (3U)
43514/*! OTGPHY2_PASSED_RESET
43515 * 0b0..Interrupt generated not due to OTG PHY2 passed reset
43516 * 0b1..Interrupt generated due to OTG PHY2 passed reset
43517 */
43518#define SRC_SISR_OTGPHY2_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_OTGPHY2_PASSED_RESET_SHIFT)) & SRC_SISR_OTGPHY2_PASSED_RESET_MASK)
43519#define SRC_SISR_MIPIPHY_PASSED_RESET_MASK (0x10U)
43520#define SRC_SISR_MIPIPHY_PASSED_RESET_SHIFT (4U)
43521/*! MIPIPHY_PASSED_RESET
43522 * 0b0..Interrupt generated not due to MIPI PHY passed reset
43523 * 0b1..Interrupt generated due to MIPI PHY passed reset
43524 */
43525#define SRC_SISR_MIPIPHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_MIPIPHY_PASSED_RESET_SHIFT)) & SRC_SISR_MIPIPHY_PASSED_RESET_MASK)
43526#define SRC_SISR_PCIE1_PHY_PASSED_RESET_MASK (0x20U)
43527#define SRC_SISR_PCIE1_PHY_PASSED_RESET_SHIFT (5U)
43528/*! PCIE1_PHY_PASSED_RESET
43529 * 0b0..Interrupt generated not due to PCIE1 PHY passed reset
43530 * 0b1..Interrupt generated due to PCIE1 PHY passed reset
43531 */
43532#define SRC_SISR_PCIE1_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_PCIE1_PHY_PASSED_RESET_SHIFT)) & SRC_SISR_PCIE1_PHY_PASSED_RESET_MASK)
43533#define SRC_SISR_HDMI_PASSED_RESET_MASK (0x40U)
43534#define SRC_SISR_HDMI_PASSED_RESET_SHIFT (6U)
43535/*! HDMI_PASSED_RESET
43536 * 0b0..Interrupt generated not due to HDMI passed reset
43537 * 0b1..Interrupt generated due to HDMI passed reset
43538 */
43539#define SRC_SISR_HDMI_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_HDMI_PASSED_RESET_SHIFT)) & SRC_SISR_HDMI_PASSED_RESET_MASK)
43540#define SRC_SISR_DISPLAY_PASSED_RESET_MASK (0x80U)
43541#define SRC_SISR_DISPLAY_PASSED_RESET_SHIFT (7U)
43542/*! DISPLAY_PASSED_RESET
43543 * 0b0..Interrupt generated not due to DISPLAY passed reset
43544 * 0b1..Interrupt generated due to DISPLAY passed reset
43545 */
43546#define SRC_SISR_DISPLAY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_DISPLAY_PASSED_RESET_SHIFT)) & SRC_SISR_DISPLAY_PASSED_RESET_MASK)
43547#define SRC_SISR_M4C_PASSED_RESET_MASK (0x100U)
43548#define SRC_SISR_M4C_PASSED_RESET_SHIFT (8U)
43549/*! M4C_PASSED_RESET
43550 * 0b0..interrupt generated not due to m4 core reset
43551 * 0b1..interrupt generated due to m4 core reset
43552 */
43553#define SRC_SISR_M4C_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_M4C_PASSED_RESET_SHIFT)) & SRC_SISR_M4C_PASSED_RESET_MASK)
43554#define SRC_SISR_M4P_PASSED_RESET_MASK (0x200U)
43555#define SRC_SISR_M4P_PASSED_RESET_SHIFT (9U)
43556/*! M4P_PASSED_RESET
43557 * 0b0..interrupt generated not due to m4 platform reset
43558 * 0b1..interrupt generated due to m4 platform reset
43559 */
43560#define SRC_SISR_M4P_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_M4P_PASSED_RESET_SHIFT)) & SRC_SISR_M4P_PASSED_RESET_MASK)
43561#define SRC_SISR_GPU_PASSED_RESET_MASK (0x400U)
43562#define SRC_SISR_GPU_PASSED_RESET_SHIFT (10U)
43563/*! GPU_PASSED_RESET
43564 * 0b0..interrupt generated not due to GPU reset
43565 * 0b1..interrupt generated due to GPU reset
43566 */
43567#define SRC_SISR_GPU_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_GPU_PASSED_RESET_SHIFT)) & SRC_SISR_GPU_PASSED_RESET_MASK)
43568#define SRC_SISR_VPU_PASSED_RESET_MASK (0x800U)
43569#define SRC_SISR_VPU_PASSED_RESET_SHIFT (11U)
43570/*! VPU_PASSED_RESET
43571 * 0b0..interrupt generated not due to VPU reset
43572 * 0b1..interrupt generated due to VPU reset
43573 */
43574#define SRC_SISR_VPU_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_VPU_PASSED_RESET_SHIFT)) & SRC_SISR_VPU_PASSED_RESET_MASK)
43575#define SRC_SISR_PCIE2_PHY_PASSED_RESET_MASK (0x1000U)
43576#define SRC_SISR_PCIE2_PHY_PASSED_RESET_SHIFT (12U)
43577/*! PCIE2_PHY_PASSED_RESET
43578 * 0b0..interrupt generated not due to PCIE2 PHY reset
43579 * 0b1..interrupt generated due to PCIE2 PHY reset
43580 */
43581#define SRC_SISR_PCIE2_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_PCIE2_PHY_PASSED_RESET_SHIFT)) & SRC_SISR_PCIE2_PHY_PASSED_RESET_MASK)
43582#define SRC_SISR_MIPI_CSI1_PHY_PASSED_RESET_MASK (0x2000U)
43583#define SRC_SISR_MIPI_CSI1_PHY_PASSED_RESET_SHIFT (13U)
43584/*! MIPI_CSI1_PHY_PASSED_RESET
43585 * 0b0..interrupt generated not due to MIPI CSI1 PHY reset
43586 * 0b1..interrupt generated due to MIPI CSI1 PHY reset
43587 */
43588#define SRC_SISR_MIPI_CSI1_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_MIPI_CSI1_PHY_PASSED_RESET_SHIFT)) & SRC_SISR_MIPI_CSI1_PHY_PASSED_RESET_MASK)
43589#define SRC_SISR_MIPI_CSI2_PHY_PASSED_RESET_MASK (0x4000U)
43590#define SRC_SISR_MIPI_CSI2_PHY_PASSED_RESET_SHIFT (14U)
43591/*! MIPI_CSI2_PHY_PASSED_RESET
43592 * 0b0..interrupt generated not due to MIPI CSI2 PHY reset
43593 * 0b1..interrupt generated due to MIPI CSI2 PHY reset
43594 */
43595#define SRC_SISR_MIPI_CSI2_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_MIPI_CSI2_PHY_PASSED_RESET_SHIFT)) & SRC_SISR_MIPI_CSI2_PHY_PASSED_RESET_MASK)
43596/*! @} */
43597
43598/*! @name SIMR - SRC Interrupt Mask Register */
43599/*! @{ */
43600#define SRC_SIMR_MASK_HSICPHY_PASSED_RESET_MASK (0x2U)
43601#define SRC_SIMR_MASK_HSICPHY_PASSED_RESET_SHIFT (1U)
43602/*! MASK_HSICPHY_PASSED_RESET
43603 * 0b0..do not mask interrupt due to HSIC PHY passed reset - interrupt will be created
43604 * 0b1..mask interrupt due to HSIC PHY passed reset
43605 */
43606#define SRC_SIMR_MASK_HSICPHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_HSICPHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_HSICPHY_PASSED_RESET_MASK)
43607#define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_MASK (0x4U)
43608#define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_SHIFT (2U)
43609/*! MASK_OTGPHY1_PASSED_RESET
43610 * 0b0..do not mask interrupt due to OTG PHY1 passed reset - interrupt will be created
43611 * 0b1..mask interrupt due to OTG PHY1 passed reset
43612 */
43613#define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_MASK)
43614#define SRC_SIMR_MASK_OTGPHY2_PASSED_RESET_MASK (0x8U)
43615#define SRC_SIMR_MASK_OTGPHY2_PASSED_RESET_SHIFT (3U)
43616/*! MASK_OTGPHY2_PASSED_RESET
43617 * 0b0..do not mask interrupt due to OTG PHY2 passed reset - interrupt will be created
43618 * 0b1..mask interrupt due to OTG PHY2 passed reset
43619 */
43620#define SRC_SIMR_MASK_OTGPHY2_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_OTGPHY2_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_OTGPHY2_PASSED_RESET_MASK)
43621#define SRC_SIMR_MASK_MIPIPHY_PASSED_RESET_MASK (0x10U)
43622#define SRC_SIMR_MASK_MIPIPHY_PASSED_RESET_SHIFT (4U)
43623/*! MASK_MIPIPHY_PASSED_RESET
43624 * 0b0..do not mask interrupt due to MIPI PHY passed reset - interrupt will be created
43625 * 0b1..mask interrupt due to MIPI PHY passed reset
43626 */
43627#define SRC_SIMR_MASK_MIPIPHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_MIPIPHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_MIPIPHY_PASSED_RESET_MASK)
43628#define SRC_SIMR_MASK_PCIE1_PHY_PASSED_RESET_MASK (0x20U)
43629#define SRC_SIMR_MASK_PCIE1_PHY_PASSED_RESET_SHIFT (5U)
43630/*! MASK_PCIE1_PHY_PASSED_RESET
43631 * 0b0..do not mask interrupt due to PCIE1 PHY passed reset - interrupt will be created
43632 * 0b1..mask interrupt due to PCIE1 PHY passed reset
43633 */
43634#define SRC_SIMR_MASK_PCIE1_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_PCIE1_PHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_PCIE1_PHY_PASSED_RESET_MASK)
43635#define SRC_SIMR_MASK_HDMI_PASSED_RESET_MASK (0x40U)
43636#define SRC_SIMR_MASK_HDMI_PASSED_RESET_SHIFT (6U)
43637/*! MASK_HDMI_PASSED_RESET
43638 * 0b0..do not mask interrupt due to HDMI passed reset - interrupt will be created
43639 * 0b1..mask interrupt due to HDMI passed reset
43640 */
43641#define SRC_SIMR_MASK_HDMI_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_HDMI_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_HDMI_PASSED_RESET_MASK)
43642#define SRC_SIMR_MASK_DISPLAY_PASSED_RESET_MASK (0x80U)
43643#define SRC_SIMR_MASK_DISPLAY_PASSED_RESET_SHIFT (7U)
43644/*! MASK_DISPLAY_PASSED_RESET
43645 * 0b0..do not mask interrupt due to HDMI passed reset - interrupt will be created
43646 * 0b1..mask interrupt due to HDMI passed reset
43647 */
43648#define SRC_SIMR_MASK_DISPLAY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_DISPLAY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_DISPLAY_PASSED_RESET_MASK)
43649#define SRC_SIMR_MASK_M4C_PASSED_RESET_MASK (0x100U)
43650#define SRC_SIMR_MASK_M4C_PASSED_RESET_SHIFT (8U)
43651/*! MASK_M4C_PASSED_RESET
43652 * 0b0..do not mask interrupt due to m4 core passed reset - interrupt will be created
43653 * 0b1..mask interrupt due to m4 core passed reset
43654 */
43655#define SRC_SIMR_MASK_M4C_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_M4C_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_M4C_PASSED_RESET_MASK)
43656#define SRC_SIMR_MASK_M4P_PASSED_RESET_MASK (0x200U)
43657#define SRC_SIMR_MASK_M4P_PASSED_RESET_SHIFT (9U)
43658/*! MASK_M4P_PASSED_RESET
43659 * 0b0..do not mask interrupt due to m4 platform passed reset - interrupt will be created
43660 * 0b1..mask interrupt due to m4platform passed reset
43661 */
43662#define SRC_SIMR_MASK_M4P_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_M4P_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_M4P_PASSED_RESET_MASK)
43663#define SRC_SIMR_MASK_GPU_PASSED_RESET_MASK (0x400U)
43664#define SRC_SIMR_MASK_GPU_PASSED_RESET_SHIFT (10U)
43665/*! MASK_GPU_PASSED_RESET
43666 * 0b0..do not mask interrupt due to GPU passed reset - interrupt will be created
43667 * 0b1..mask interrupt due to GPU passed reset
43668 */
43669#define SRC_SIMR_MASK_GPU_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_GPU_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_GPU_PASSED_RESET_MASK)
43670#define SRC_SIMR_MASK_VPU_PASSED_RESET_MASK (0x800U)
43671#define SRC_SIMR_MASK_VPU_PASSED_RESET_SHIFT (11U)
43672/*! MASK_VPU_PASSED_RESET
43673 * 0b0..do not mask interrupt due to VPU passed reset - interrupt will be created
43674 * 0b1..mask interrupt due to VPU passed reset
43675 */
43676#define SRC_SIMR_MASK_VPU_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_VPU_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_VPU_PASSED_RESET_MASK)
43677#define SRC_SIMR_MASK_PCIE2_PHY_PASSED_RESET_MASK (0x1000U)
43678#define SRC_SIMR_MASK_PCIE2_PHY_PASSED_RESET_SHIFT (12U)
43679/*! MASK_PCIE2_PHY_PASSED_RESET
43680 * 0b0..do not mask interrupt due to PCIE2 PHY passed reset - interrupt will be created
43681 * 0b1..mask interrupt due to PCIE2 PHY passed reset
43682 */
43683#define SRC_SIMR_MASK_PCIE2_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_PCIE2_PHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_PCIE2_PHY_PASSED_RESET_MASK)
43684#define SRC_SIMR_MASK_MIPI_CSI1_PHY_PASSED_RESET_MASK (0x2000U)
43685#define SRC_SIMR_MASK_MIPI_CSI1_PHY_PASSED_RESET_SHIFT (13U)
43686/*! MASK_MIPI_CSI1_PHY_PASSED_RESET
43687 * 0b0..do not mask interrupt due to MIPI CSI1 PHY passed reset - interrupt will be created
43688 * 0b1..mask interrupt due to MIPI CSI1 PHY passed reset
43689 */
43690#define SRC_SIMR_MASK_MIPI_CSI1_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_MIPI_CSI1_PHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_MIPI_CSI1_PHY_PASSED_RESET_MASK)
43691#define SRC_SIMR_MASK_MIPI_CSI2_PHY_PASSED_RESET_MASK (0x4000U)
43692#define SRC_SIMR_MASK_MIPI_CSI2_PHY_PASSED_RESET_SHIFT (14U)
43693/*! MASK_MIPI_CSI2_PHY_PASSED_RESET
43694 * 0b0..do not mask interrupt due to MIPI CSI2 PHY passed reset - interrupt will be created
43695 * 0b1..mask interrupt due to MIPI CSI2 PHY passed reset
43696 */
43697#define SRC_SIMR_MASK_MIPI_CSI2_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_MIPI_CSI2_PHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_MIPI_CSI2_PHY_PASSED_RESET_MASK)
43698/*! @} */
43699
43700/*! @name SBMR2 - SRC Boot Mode Register 2 */
43701/*! @{ */
43702#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U)
43703#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U)
43704#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
43705#define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U)
43706#define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U)
43707#define SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK)
43708#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)
43709#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)
43710#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
43711#define SRC_SBMR2_FUSE_FORCE_COLD_BOOT_MASK (0x20U)
43712#define SRC_SBMR2_FUSE_FORCE_COLD_BOOT_SHIFT (5U)
43713#define SRC_SBMR2_FUSE_FORCE_COLD_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_FUSE_FORCE_COLD_BOOT_SHIFT)) & SRC_SBMR2_FUSE_FORCE_COLD_BOOT_MASK)
43714#define SRC_SBMR2_BMOD_MASK (0x3000000U)
43715#define SRC_SBMR2_BMOD_SHIFT (24U)
43716#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)
43717/*! @} */
43718
43719/*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */
43720/*! @{ */
43721#define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU)
43722#define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U)
43723#define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK)
43724#define SRC_GPR_PERSISTENT_ARG1_MASK (0xFFFFFFFFU)
43725#define SRC_GPR_PERSISTENT_ARG1_SHIFT (0U)
43726#define SRC_GPR_PERSISTENT_ARG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG1_SHIFT)) & SRC_GPR_PERSISTENT_ARG1_MASK)
43727#define SRC_GPR_PERSISTENT_ARG2_MASK (0xFFFFFFFFU)
43728#define SRC_GPR_PERSISTENT_ARG2_SHIFT (0U)
43729#define SRC_GPR_PERSISTENT_ARG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG2_SHIFT)) & SRC_GPR_PERSISTENT_ARG2_MASK)
43730#define SRC_GPR_PERSISTENT_ARG3_MASK (0xFFFFFFFFU)
43731#define SRC_GPR_PERSISTENT_ARG3_SHIFT (0U)
43732#define SRC_GPR_PERSISTENT_ARG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG3_SHIFT)) & SRC_GPR_PERSISTENT_ARG3_MASK)
43733#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU)
43734#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U)
43735#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK)
43736#define SRC_GPR_PERSISTENT_ENTRY1_MASK (0xFFFFFFFFU)
43737#define SRC_GPR_PERSISTENT_ENTRY1_SHIFT (0U)
43738#define SRC_GPR_PERSISTENT_ENTRY1(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY1_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY1_MASK)
43739#define SRC_GPR_PERSISTENT_ENTRY2_MASK (0xFFFFFFFFU)
43740#define SRC_GPR_PERSISTENT_ENTRY2_SHIFT (0U)
43741#define SRC_GPR_PERSISTENT_ENTRY2(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY2_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY2_MASK)
43742#define SRC_GPR_PERSISTENT_ENTRY3_MASK (0xFFFFFFFFU)
43743#define SRC_GPR_PERSISTENT_ENTRY3_SHIFT (0U)
43744#define SRC_GPR_PERSISTENT_ENTRY3(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY3_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY3_MASK)
43745/*! @} */
43746
43747/* The count of SRC_GPR */
43748#define SRC_GPR_COUNT (10U)
43749
43750/*! @name DDRC_RCR - SRC DDR Controller Reset Control Register */
43751/*! @{ */
43752#define SRC_DDRC_RCR_DDRC1_PRST_MASK (0x1U)
43753#define SRC_DDRC_RCR_DDRC1_PRST_SHIFT (0U)
43754/*! DDRC1_PRST
43755 * 0b0..De-ssert DDR Controller preset and DDR PHY reset reset
43756 * 0b1..Assert DDR Controller preset and DDR PHY reset
43757 */
43758#define SRC_DDRC_RCR_DDRC1_PRST(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PRST_SHIFT)) & SRC_DDRC_RCR_DDRC1_PRST_MASK)
43759#define SRC_DDRC_RCR_DDRC1_CORE_RST_MASK (0x2U)
43760#define SRC_DDRC_RCR_DDRC1_CORE_RST_SHIFT (1U)
43761/*! DDRC1_CORE_RST
43762 * 0b0..De-ssert DDR controller aresetn and core_ddrc_rstn
43763 * 0b1..Assert DDR Controller preset and DDR PHY reset
43764 */
43765#define SRC_DDRC_RCR_DDRC1_CORE_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_CORE_RST_SHIFT)) & SRC_DDRC_RCR_DDRC1_CORE_RST_MASK)
43766#define SRC_DDRC_RCR_DDRC1_PHY_RESET_MASK (0x4U)
43767#define SRC_DDRC_RCR_DDRC1_PHY_RESET_SHIFT (2U)
43768/*! DDRC1_PHY_RESET
43769 * 0b0..De-ssert DDR controller
43770 * 0b1..Assert DDR Controller
43771 */
43772#define SRC_DDRC_RCR_DDRC1_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PHY_RESET_SHIFT)) & SRC_DDRC_RCR_DDRC1_PHY_RESET_MASK)
43773#define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_MASK (0x8U)
43774#define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_SHIFT (3U)
43775/*! DDRC1_PHY_PWROKIN
43776 * 0b0..De-ssert DDR controller
43777 * 0b1..Assert DDR Controller
43778 */
43779#define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_SHIFT)) & SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_MASK)
43780#define SRC_DDRC_RCR_DOMAIN0_MASK (0x1000000U)
43781#define SRC_DDRC_RCR_DOMAIN0_SHIFT (24U)
43782/*! DOMAIN0
43783 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
43784 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
43785 */
43786#define SRC_DDRC_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN0_SHIFT)) & SRC_DDRC_RCR_DOMAIN0_MASK)
43787#define SRC_DDRC_RCR_DOMAIN1_MASK (0x2000000U)
43788#define SRC_DDRC_RCR_DOMAIN1_SHIFT (25U)
43789/*! DOMAIN1
43790 * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register.
43791 * 0b1..This register is assigned to domain1. The master from domain3 can write to this register
43792 */
43793#define SRC_DDRC_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN1_SHIFT)) & SRC_DDRC_RCR_DOMAIN1_MASK)
43794#define SRC_DDRC_RCR_DOMAIN2_MASK (0x4000000U)
43795#define SRC_DDRC_RCR_DOMAIN2_SHIFT (26U)
43796/*! DOMAIN2
43797 * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register.
43798 * 0b1..This register is assigned to domain2. The master from domain3 can write to this register
43799 */
43800#define SRC_DDRC_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN2_SHIFT)) & SRC_DDRC_RCR_DOMAIN2_MASK)
43801#define SRC_DDRC_RCR_DOMAIN3_MASK (0x8000000U)
43802#define SRC_DDRC_RCR_DOMAIN3_SHIFT (27U)
43803/*! DOMAIN3
43804 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
43805 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
43806 */
43807#define SRC_DDRC_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN3_SHIFT)) & SRC_DDRC_RCR_DOMAIN3_MASK)
43808#define SRC_DDRC_RCR_LOCK_MASK (0x40000000U)
43809#define SRC_DDRC_RCR_LOCK_SHIFT (30U)
43810/*! LOCK
43811 * 0b0..[31] and [27:24] bits can be modified
43812 * 0b1..[31] and [27:24] bits cannot be modified
43813 */
43814#define SRC_DDRC_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_LOCK_SHIFT)) & SRC_DDRC_RCR_LOCK_MASK)
43815#define SRC_DDRC_RCR_DOM_EN_MASK (0x80000000U)
43816#define SRC_DDRC_RCR_DOM_EN_SHIFT (31U)
43817/*! DOM_EN
43818 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
43819 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
43820 */
43821#define SRC_DDRC_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOM_EN_SHIFT)) & SRC_DDRC_RCR_DOM_EN_MASK)
43822/*! @} */
43823
43824/*! @name DDRC2_RCR - SRC DDRC2 Controller Reset Control Register */
43825/*! @{ */
43826#define SRC_DDRC2_RCR_DDRC2_PRST_MASK (0x1U)
43827#define SRC_DDRC2_RCR_DDRC2_PRST_SHIFT (0U)
43828/*! DDRC2_PRST
43829 * 0b0..De-ssert DDRC2 Controller preset and DDR PHY reset reset
43830 * 0b1..Assert DDRC2 Controller preset and DDR PHY reset
43831 */
43832#define SRC_DDRC2_RCR_DDRC2_PRST(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DDRC2_PRST_SHIFT)) & SRC_DDRC2_RCR_DDRC2_PRST_MASK)
43833#define SRC_DDRC2_RCR_DDRC2_CORE_RST_MASK (0x2U)
43834#define SRC_DDRC2_RCR_DDRC2_CORE_RST_SHIFT (1U)
43835/*! DDRC2_CORE_RST
43836 * 0b0..De-ssert DDR controller aresetn and core_ddrc_rstn
43837 * 0b1..Assert DDR Controller preset and DDR PHY reset
43838 */
43839#define SRC_DDRC2_RCR_DDRC2_CORE_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DDRC2_CORE_RST_SHIFT)) & SRC_DDRC2_RCR_DDRC2_CORE_RST_MASK)
43840#define SRC_DDRC2_RCR_DDRC1_PHY_RESET_MASK (0x4U)
43841#define SRC_DDRC2_RCR_DDRC1_PHY_RESET_SHIFT (2U)
43842/*! DDRC1_PHY_RESET
43843 * 0b0..De-ssert DDR controller
43844 * 0b1..Assert DDR Controller
43845 */
43846#define SRC_DDRC2_RCR_DDRC1_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DDRC1_PHY_RESET_SHIFT)) & SRC_DDRC2_RCR_DDRC1_PHY_RESET_MASK)
43847#define SRC_DDRC2_RCR_DDRC1_PHY_PWROKIN_MASK (0x8U)
43848#define SRC_DDRC2_RCR_DDRC1_PHY_PWROKIN_SHIFT (3U)
43849/*! DDRC1_PHY_PWROKIN
43850 * 0b0..De-ssert DDR controller
43851 * 0b1..Assert DDR Controller
43852 */
43853#define SRC_DDRC2_RCR_DDRC1_PHY_PWROKIN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DDRC1_PHY_PWROKIN_SHIFT)) & SRC_DDRC2_RCR_DDRC1_PHY_PWROKIN_MASK)
43854#define SRC_DDRC2_RCR_DOMAIN0_MASK (0x1000000U)
43855#define SRC_DDRC2_RCR_DOMAIN0_SHIFT (24U)
43856/*! DOMAIN0
43857 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
43858 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
43859 */
43860#define SRC_DDRC2_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DOMAIN0_SHIFT)) & SRC_DDRC2_RCR_DOMAIN0_MASK)
43861#define SRC_DDRC2_RCR_DOMAIN1_MASK (0x2000000U)
43862#define SRC_DDRC2_RCR_DOMAIN1_SHIFT (25U)
43863/*! DOMAIN1
43864 * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register.
43865 * 0b1..This register is assigned to domain1. The master from domain3 can write to this register
43866 */
43867#define SRC_DDRC2_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DOMAIN1_SHIFT)) & SRC_DDRC2_RCR_DOMAIN1_MASK)
43868#define SRC_DDRC2_RCR_DOMAIN2_MASK (0x4000000U)
43869#define SRC_DDRC2_RCR_DOMAIN2_SHIFT (26U)
43870/*! DOMAIN2
43871 * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register.
43872 * 0b1..This register is assigned to domain2. The master from domain3 can write to this register
43873 */
43874#define SRC_DDRC2_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DOMAIN2_SHIFT)) & SRC_DDRC2_RCR_DOMAIN2_MASK)
43875#define SRC_DDRC2_RCR_DOMAIN3_MASK (0x8000000U)
43876#define SRC_DDRC2_RCR_DOMAIN3_SHIFT (27U)
43877/*! DOMAIN3
43878 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
43879 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
43880 */
43881#define SRC_DDRC2_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DOMAIN3_SHIFT)) & SRC_DDRC2_RCR_DOMAIN3_MASK)
43882#define SRC_DDRC2_RCR_LOCK_MASK (0x40000000U)
43883#define SRC_DDRC2_RCR_LOCK_SHIFT (30U)
43884/*! LOCK
43885 * 0b0..[31] and [27:24] bits can be modified
43886 * 0b1..[31] and [27:24] bits cannot be modified
43887 */
43888#define SRC_DDRC2_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_LOCK_SHIFT)) & SRC_DDRC2_RCR_LOCK_MASK)
43889#define SRC_DDRC2_RCR_DOM_EN_MASK (0x80000000U)
43890#define SRC_DDRC2_RCR_DOM_EN_SHIFT (31U)
43891/*! DOM_EN
43892 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
43893 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area.
43894 */
43895#define SRC_DDRC2_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DOM_EN_SHIFT)) & SRC_DDRC2_RCR_DOM_EN_MASK)
43896/*! @} */
43897
43898
43899/*!
43900 * @}
43901 */ /* end of group SRC_Register_Masks */
43902
43903
43904/* SRC - Peripheral instance base addresses */
43905/** Peripheral SRC base address */
43906#define SRC_BASE (0x30390000u)
43907/** Peripheral SRC base pointer */
43908#define SRC ((SRC_Type *)SRC_BASE)
43909/** Array initializer of SRC peripheral base addresses */
43910#define SRC_BASE_ADDRS { SRC_BASE }
43911/** Array initializer of SRC peripheral base pointers */
43912#define SRC_BASE_PTRS { SRC }
43913/** Interrupt vectors for the SRC peripheral type */
43914#define SRC_IRQS { SRC_IRQn }
43915#define SRC_COMBINED_IRQS { SRC_Combined_IRQn }
43916
43917/*!
43918 * @}
43919 */ /* end of group SRC_Peripheral_Access_Layer */
43920
43921
43922/* ----------------------------------------------------------------------------
43923 -- SUBSAM Peripheral Access Layer
43924 ---------------------------------------------------------------------------- */
43925
43926/*!
43927 * @addtogroup SUBSAM_Peripheral_Access_Layer SUBSAM Peripheral Access Layer
43928 * @{
43929 */
43930
43931/** SUBSAM - Register Layout Typedef */
43932typedef struct {
43933 struct { /* offset: 0x0 */
43934 __IO uint32_t RW; /**< , offset: 0x0 */
43935 __IO uint32_t SET; /**< , offset: 0x4 */
43936 __IO uint32_t CLR; /**< , offset: 0x8 */
43937 __IO uint32_t TOG; /**< , offset: 0xC */
43938 } SS_SYS_CTRL;
43939 struct { /* offset: 0x10 */
43940 __IO uint32_t RW; /**< , offset: 0x10 */
43941 __IO uint32_t SET; /**< , offset: 0x14 */
43942 __IO uint32_t CLR; /**< , offset: 0x18 */
43943 __IO uint32_t TOG; /**< , offset: 0x1C */
43944 } SS_DISPLAY;
43945 struct { /* offset: 0x20 */
43946 __IO uint32_t RW; /**< , offset: 0x20 */
43947 __IO uint32_t SET; /**< , offset: 0x24 */
43948 __IO uint32_t CLR; /**< , offset: 0x28 */
43949 __IO uint32_t TOG; /**< , offset: 0x2C */
43950 } SS_HSYNC;
43951 struct { /* offset: 0x30 */
43952 __IO uint32_t RW; /**< , offset: 0x30 */
43953 __IO uint32_t SET; /**< , offset: 0x34 */
43954 __IO uint32_t CLR; /**< , offset: 0x38 */
43955 __IO uint32_t TOG; /**< , offset: 0x3C */
43956 } SS_VSYNC;
43957 struct { /* offset: 0x40 */
43958 __IO uint32_t RW; /**< , offset: 0x40 */
43959 __IO uint32_t SET; /**< , offset: 0x44 */
43960 __IO uint32_t CLR; /**< , offset: 0x48 */
43961 __IO uint32_t TOG; /**< , offset: 0x4C */
43962 } SS_DE_ULC;
43963 struct { /* offset: 0x50 */
43964 __IO uint32_t RW; /**< , offset: 0x50 */
43965 __IO uint32_t SET; /**< , offset: 0x54 */
43966 __IO uint32_t CLR; /**< , offset: 0x58 */
43967 __IO uint32_t TOG; /**< , offset: 0x5C */
43968 } SS_DE_LRC;
43969 struct { /* offset: 0x60 */
43970 __IO uint32_t RW; /**< , offset: 0x60 */
43971 __IO uint32_t SET; /**< , offset: 0x64 */
43972 __IO uint32_t CLR; /**< , offset: 0x68 */
43973 __IO uint32_t TOG; /**< , offset: 0x6C */
43974 } SS_MODE;
43975 struct { /* offset: 0x70 */
43976 __IO uint32_t RW; /**< , offset: 0x70 */
43977 __IO uint32_t SET; /**< , offset: 0x74 */
43978 __IO uint32_t CLR; /**< , offset: 0x78 */
43979 __IO uint32_t TOG; /**< , offset: 0x7C */
43980 } SS_COEFF;
43981 struct { /* offset: 0x80 */
43982 __IO uint32_t RW; /**< , offset: 0x80 */
43983 __IO uint32_t SET; /**< , offset: 0x84 */
43984 __IO uint32_t CLR; /**< , offset: 0x88 */
43985 __IO uint32_t TOG; /**< , offset: 0x8C */
43986 } SS_CLIP_CB;
43987 struct { /* offset: 0x90 */
43988 __IO uint32_t RW; /**< , offset: 0x90 */
43989 __IO uint32_t SET; /**< , offset: 0x94 */
43990 __IO uint32_t CLR; /**< , offset: 0x98 */
43991 __IO uint32_t TOG; /**< , offset: 0x9C */
43992 } SS_CLIP_CR;
43993 struct { /* offset: 0xA0 */
43994 __IO uint32_t RW; /**< , offset: 0xA0 */
43995 __IO uint32_t SET; /**< , offset: 0xA4 */
43996 __IO uint32_t CLR; /**< , offset: 0xA8 */
43997 __IO uint32_t TOG; /**< , offset: 0xAC */
43998 } SS_INTER_MODE;
43999 __IO uint32_t SS_CHKSUM_CTRL; /**< , offset: 0xB0 */
44000 __IO uint32_t SS_CHKSUM_START; /**< , offset: 0xB4 */
44001 __IO uint32_t SS_CHKSUM_END; /**< , offset: 0xB8 */
44002 __I uint32_t SS_CHKSUM_DATA_LOW; /**< , offset: 0xBC */
44003 __IO uint32_t SS_CHKSUM_DATA_HIGH; /**< , offset: 0xC0 */
44004} SUBSAM_Type;
44005
44006/* ----------------------------------------------------------------------------
44007 -- SUBSAM Register Masks
44008 ---------------------------------------------------------------------------- */
44009
44010/*!
44011 * @addtogroup SUBSAM_Register_Masks SUBSAM Register Masks
44012 * @{
44013 */
44014
44015/*! @name SS_SYS_CTRL - */
44016/*! @{ */
44017#define SUBSAM_SS_SYS_CTRL_RUN_EN_MASK (0x1U)
44018#define SUBSAM_SS_SYS_CTRL_RUN_EN_SHIFT (0U)
44019#define SUBSAM_SS_SYS_CTRL_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_SYS_CTRL_RUN_EN_SHIFT)) & SUBSAM_SS_SYS_CTRL_RUN_EN_MASK)
44020/*! @} */
44021
44022/*! @name SS_DISPLAY - */
44023/*! @{ */
44024#define SUBSAM_SS_DISPLAY_LRC_X_MASK (0x1FFFU)
44025#define SUBSAM_SS_DISPLAY_LRC_X_SHIFT (0U)
44026#define SUBSAM_SS_DISPLAY_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DISPLAY_LRC_X_SHIFT)) & SUBSAM_SS_DISPLAY_LRC_X_MASK)
44027#define SUBSAM_SS_DISPLAY_LRC_Y_MASK (0x1FFF0000U)
44028#define SUBSAM_SS_DISPLAY_LRC_Y_SHIFT (16U)
44029#define SUBSAM_SS_DISPLAY_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DISPLAY_LRC_Y_SHIFT)) & SUBSAM_SS_DISPLAY_LRC_Y_MASK)
44030/*! @} */
44031
44032/*! @name SS_HSYNC - */
44033/*! @{ */
44034#define SUBSAM_SS_HSYNC_START_MASK (0x1FFFU)
44035#define SUBSAM_SS_HSYNC_START_SHIFT (0U)
44036#define SUBSAM_SS_HSYNC_START(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_HSYNC_START_SHIFT)) & SUBSAM_SS_HSYNC_START_MASK)
44037#define SUBSAM_SS_HSYNC_END_MASK (0x1FFF0000U)
44038#define SUBSAM_SS_HSYNC_END_SHIFT (16U)
44039#define SUBSAM_SS_HSYNC_END(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_HSYNC_END_SHIFT)) & SUBSAM_SS_HSYNC_END_MASK)
44040#define SUBSAM_SS_HSYNC_POL_MASK (0x80000000U)
44041#define SUBSAM_SS_HSYNC_POL_SHIFT (31U)
44042#define SUBSAM_SS_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_HSYNC_POL_SHIFT)) & SUBSAM_SS_HSYNC_POL_MASK)
44043/*! @} */
44044
44045/*! @name SS_VSYNC - */
44046/*! @{ */
44047#define SUBSAM_SS_VSYNC_START_MASK (0x1FFFU)
44048#define SUBSAM_SS_VSYNC_START_SHIFT (0U)
44049#define SUBSAM_SS_VSYNC_START(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_VSYNC_START_SHIFT)) & SUBSAM_SS_VSYNC_START_MASK)
44050#define SUBSAM_SS_VSYNC_END_MASK (0x1FFF0000U)
44051#define SUBSAM_SS_VSYNC_END_SHIFT (16U)
44052#define SUBSAM_SS_VSYNC_END(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_VSYNC_END_SHIFT)) & SUBSAM_SS_VSYNC_END_MASK)
44053#define SUBSAM_SS_VSYNC_POL_MASK (0x80000000U)
44054#define SUBSAM_SS_VSYNC_POL_SHIFT (31U)
44055#define SUBSAM_SS_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_VSYNC_POL_SHIFT)) & SUBSAM_SS_VSYNC_POL_MASK)
44056/*! @} */
44057
44058/*! @name SS_DE_ULC - */
44059/*! @{ */
44060#define SUBSAM_SS_DE_ULC_ULC_X_MASK (0x1FFFU)
44061#define SUBSAM_SS_DE_ULC_ULC_X_SHIFT (0U)
44062#define SUBSAM_SS_DE_ULC_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DE_ULC_ULC_X_SHIFT)) & SUBSAM_SS_DE_ULC_ULC_X_MASK)
44063#define SUBSAM_SS_DE_ULC_ULC_Y_MASK (0x1FFF0000U)
44064#define SUBSAM_SS_DE_ULC_ULC_Y_SHIFT (16U)
44065#define SUBSAM_SS_DE_ULC_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DE_ULC_ULC_Y_SHIFT)) & SUBSAM_SS_DE_ULC_ULC_Y_MASK)
44066#define SUBSAM_SS_DE_ULC_POL_MASK (0x80000000U)
44067#define SUBSAM_SS_DE_ULC_POL_SHIFT (31U)
44068#define SUBSAM_SS_DE_ULC_POL(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DE_ULC_POL_SHIFT)) & SUBSAM_SS_DE_ULC_POL_MASK)
44069/*! @} */
44070
44071/*! @name SS_DE_LRC - */
44072/*! @{ */
44073#define SUBSAM_SS_DE_LRC_LRC_X_MASK (0x1FFFU)
44074#define SUBSAM_SS_DE_LRC_LRC_X_SHIFT (0U)
44075#define SUBSAM_SS_DE_LRC_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DE_LRC_LRC_X_SHIFT)) & SUBSAM_SS_DE_LRC_LRC_X_MASK)
44076#define SUBSAM_SS_DE_LRC_LRC_Y_MASK (0x1FFF0000U)
44077#define SUBSAM_SS_DE_LRC_LRC_Y_SHIFT (16U)
44078#define SUBSAM_SS_DE_LRC_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DE_LRC_LRC_Y_SHIFT)) & SUBSAM_SS_DE_LRC_LRC_Y_MASK)
44079/*! @} */
44080
44081/*! @name SS_MODE - */
44082/*! @{ */
44083#define SUBSAM_SS_MODE_PIPE_MODE_MASK (0x3U)
44084#define SUBSAM_SS_MODE_PIPE_MODE_SHIFT (0U)
44085#define SUBSAM_SS_MODE_PIPE_MODE(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_PIPE_MODE_SHIFT)) & SUBSAM_SS_MODE_PIPE_MODE_MASK)
44086#define SUBSAM_SS_MODE_COMP_SEL0_OUT_MASK (0x300U)
44087#define SUBSAM_SS_MODE_COMP_SEL0_OUT_SHIFT (8U)
44088#define SUBSAM_SS_MODE_COMP_SEL0_OUT(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_COMP_SEL0_OUT_SHIFT)) & SUBSAM_SS_MODE_COMP_SEL0_OUT_MASK)
44089#define SUBSAM_SS_MODE_COMP_SEL1_OUT_MASK (0xC00U)
44090#define SUBSAM_SS_MODE_COMP_SEL1_OUT_SHIFT (10U)
44091#define SUBSAM_SS_MODE_COMP_SEL1_OUT(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_COMP_SEL1_OUT_SHIFT)) & SUBSAM_SS_MODE_COMP_SEL1_OUT_MASK)
44092#define SUBSAM_SS_MODE_COMP_SEL2_OUT_MASK (0x3000U)
44093#define SUBSAM_SS_MODE_COMP_SEL2_OUT_SHIFT (12U)
44094#define SUBSAM_SS_MODE_COMP_SEL2_OUT(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_COMP_SEL2_OUT_SHIFT)) & SUBSAM_SS_MODE_COMP_SEL2_OUT_MASK)
44095#define SUBSAM_SS_MODE_COMP_SEL0_IN_MASK (0x30000U)
44096#define SUBSAM_SS_MODE_COMP_SEL0_IN_SHIFT (16U)
44097#define SUBSAM_SS_MODE_COMP_SEL0_IN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_COMP_SEL0_IN_SHIFT)) & SUBSAM_SS_MODE_COMP_SEL0_IN_MASK)
44098#define SUBSAM_SS_MODE_COMP_SEL1_IN_MASK (0xC0000U)
44099#define SUBSAM_SS_MODE_COMP_SEL1_IN_SHIFT (18U)
44100#define SUBSAM_SS_MODE_COMP_SEL1_IN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_COMP_SEL1_IN_SHIFT)) & SUBSAM_SS_MODE_COMP_SEL1_IN_MASK)
44101#define SUBSAM_SS_MODE_COMP_SEL2_IN_MASK (0x300000U)
44102#define SUBSAM_SS_MODE_COMP_SEL2_IN_SHIFT (20U)
44103#define SUBSAM_SS_MODE_COMP_SEL2_IN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_COMP_SEL2_IN_SHIFT)) & SUBSAM_SS_MODE_COMP_SEL2_IN_MASK)
44104/*! @} */
44105
44106/*! @name SS_COEFF - */
44107/*! @{ */
44108#define SUBSAM_SS_COEFF_HORIZ_A_MASK (0xFU)
44109#define SUBSAM_SS_COEFF_HORIZ_A_SHIFT (0U)
44110#define SUBSAM_SS_COEFF_HORIZ_A(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_HORIZ_A_SHIFT)) & SUBSAM_SS_COEFF_HORIZ_A_MASK)
44111#define SUBSAM_SS_COEFF_HORIZ_B_MASK (0xF0U)
44112#define SUBSAM_SS_COEFF_HORIZ_B_SHIFT (4U)
44113#define SUBSAM_SS_COEFF_HORIZ_B(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_HORIZ_B_SHIFT)) & SUBSAM_SS_COEFF_HORIZ_B_MASK)
44114#define SUBSAM_SS_COEFF_HORIZ_C_MASK (0xF00U)
44115#define SUBSAM_SS_COEFF_HORIZ_C_SHIFT (8U)
44116#define SUBSAM_SS_COEFF_HORIZ_C(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_HORIZ_C_SHIFT)) & SUBSAM_SS_COEFF_HORIZ_C_MASK)
44117#define SUBSAM_SS_COEFF_HORIZ_NORM_MASK (0x7000U)
44118#define SUBSAM_SS_COEFF_HORIZ_NORM_SHIFT (12U)
44119#define SUBSAM_SS_COEFF_HORIZ_NORM(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_HORIZ_NORM_SHIFT)) & SUBSAM_SS_COEFF_HORIZ_NORM_MASK)
44120#define SUBSAM_SS_COEFF_VERT_A_MASK (0xF0000U)
44121#define SUBSAM_SS_COEFF_VERT_A_SHIFT (16U)
44122#define SUBSAM_SS_COEFF_VERT_A(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_VERT_A_SHIFT)) & SUBSAM_SS_COEFF_VERT_A_MASK)
44123#define SUBSAM_SS_COEFF_VERT_B_MASK (0xF00000U)
44124#define SUBSAM_SS_COEFF_VERT_B_SHIFT (20U)
44125#define SUBSAM_SS_COEFF_VERT_B(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_VERT_B_SHIFT)) & SUBSAM_SS_COEFF_VERT_B_MASK)
44126#define SUBSAM_SS_COEFF_VERT_C_MASK (0xF000000U)
44127#define SUBSAM_SS_COEFF_VERT_C_SHIFT (24U)
44128#define SUBSAM_SS_COEFF_VERT_C(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_VERT_C_SHIFT)) & SUBSAM_SS_COEFF_VERT_C_MASK)
44129#define SUBSAM_SS_COEFF_VERT_NORM_MASK (0x70000000U)
44130#define SUBSAM_SS_COEFF_VERT_NORM_SHIFT (28U)
44131#define SUBSAM_SS_COEFF_VERT_NORM(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_VERT_NORM_SHIFT)) & SUBSAM_SS_COEFF_VERT_NORM_MASK)
44132/*! @} */
44133
44134/*! @name SS_CLIP_CB - */
44135/*! @{ */
44136#define SUBSAM_SS_CLIP_CB_MIN_MASK (0xFFFU)
44137#define SUBSAM_SS_CLIP_CB_MIN_SHIFT (0U)
44138#define SUBSAM_SS_CLIP_CB_MIN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CLIP_CB_MIN_SHIFT)) & SUBSAM_SS_CLIP_CB_MIN_MASK)
44139#define SUBSAM_SS_CLIP_CB_MAX_MASK (0xFFF0000U)
44140#define SUBSAM_SS_CLIP_CB_MAX_SHIFT (16U)
44141#define SUBSAM_SS_CLIP_CB_MAX(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CLIP_CB_MAX_SHIFT)) & SUBSAM_SS_CLIP_CB_MAX_MASK)
44142/*! @} */
44143
44144/*! @name SS_CLIP_CR - */
44145/*! @{ */
44146#define SUBSAM_SS_CLIP_CR_MIN_MASK (0xFFFU)
44147#define SUBSAM_SS_CLIP_CR_MIN_SHIFT (0U)
44148#define SUBSAM_SS_CLIP_CR_MIN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CLIP_CR_MIN_SHIFT)) & SUBSAM_SS_CLIP_CR_MIN_MASK)
44149#define SUBSAM_SS_CLIP_CR_MAX_MASK (0xFFF0000U)
44150#define SUBSAM_SS_CLIP_CR_MAX_SHIFT (16U)
44151#define SUBSAM_SS_CLIP_CR_MAX(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CLIP_CR_MAX_SHIFT)) & SUBSAM_SS_CLIP_CR_MAX_MASK)
44152/*! @} */
44153
44154/*! @name SS_INTER_MODE - */
44155/*! @{ */
44156#define SUBSAM_SS_INTER_MODE_INT_EN_MASK (0x1U)
44157#define SUBSAM_SS_INTER_MODE_INT_EN_SHIFT (0U)
44158#define SUBSAM_SS_INTER_MODE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_INTER_MODE_INT_EN_SHIFT)) & SUBSAM_SS_INTER_MODE_INT_EN_MASK)
44159#define SUBSAM_SS_INTER_MODE_VSYNC_SHIFT_MASK (0x2U)
44160#define SUBSAM_SS_INTER_MODE_VSYNC_SHIFT_SHIFT (1U)
44161#define SUBSAM_SS_INTER_MODE_VSYNC_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_INTER_MODE_VSYNC_SHIFT_SHIFT)) & SUBSAM_SS_INTER_MODE_VSYNC_SHIFT_MASK)
44162/*! @} */
44163
44164/*! @name SS_CHKSUM_CTRL - */
44165/*! @{ */
44166#define SUBSAM_SS_CHKSUM_CTRL_CHKSUM_EN_MASK (0x1U)
44167#define SUBSAM_SS_CHKSUM_CTRL_CHKSUM_EN_SHIFT (0U)
44168/*! CHKSUM_EN
44169 * 0b0..Checksum is disabled.
44170 * 0b1..Checksum is enabled.
44171 */
44172#define SUBSAM_SS_CHKSUM_CTRL_CHKSUM_EN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_CTRL_CHKSUM_EN_SHIFT)) & SUBSAM_SS_CHKSUM_CTRL_CHKSUM_EN_MASK)
44173#define SUBSAM_SS_CHKSUM_CTRL_NUM_FRAMES_MASK (0xF0U)
44174#define SUBSAM_SS_CHKSUM_CTRL_NUM_FRAMES_SHIFT (4U)
44175/*! NUM_FRAMES
44176 * 0b0000..Continuous mode. Output a checksum after each start trigger to end trigger process.
44177 * 0b0001..Accumulate the cheksum over one complete frame.
44178 * 0b0010..Accumulate the cheksum over two complete frames.
44179 * 0b0011-0b1111..Accumulate the cheksum over NUM_FRAMES complete frames.
44180 */
44181#define SUBSAM_SS_CHKSUM_CTRL_NUM_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_CTRL_NUM_FRAMES_SHIFT)) & SUBSAM_SS_CHKSUM_CTRL_NUM_FRAMES_MASK)
44182/*! @} */
44183
44184/*! @name SS_CHKSUM_START - */
44185/*! @{ */
44186#define SUBSAM_SS_CHKSUM_START_VCOUNT_START_MASK (0x1FFFU)
44187#define SUBSAM_SS_CHKSUM_START_VCOUNT_START_SHIFT (0U)
44188#define SUBSAM_SS_CHKSUM_START_VCOUNT_START(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_START_VCOUNT_START_SHIFT)) & SUBSAM_SS_CHKSUM_START_VCOUNT_START_MASK)
44189#define SUBSAM_SS_CHKSUM_START_HCOUNT_START_MASK (0x1FFF0000U)
44190#define SUBSAM_SS_CHKSUM_START_HCOUNT_START_SHIFT (16U)
44191#define SUBSAM_SS_CHKSUM_START_HCOUNT_START(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_START_HCOUNT_START_SHIFT)) & SUBSAM_SS_CHKSUM_START_HCOUNT_START_MASK)
44192/*! @} */
44193
44194/*! @name SS_CHKSUM_END - */
44195/*! @{ */
44196#define SUBSAM_SS_CHKSUM_END_VCOUNT_END_MASK (0x1FFFU)
44197#define SUBSAM_SS_CHKSUM_END_VCOUNT_END_SHIFT (0U)
44198#define SUBSAM_SS_CHKSUM_END_VCOUNT_END(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_END_VCOUNT_END_SHIFT)) & SUBSAM_SS_CHKSUM_END_VCOUNT_END_MASK)
44199#define SUBSAM_SS_CHKSUM_END_HCOUNT_END_MASK (0x1FFF0000U)
44200#define SUBSAM_SS_CHKSUM_END_HCOUNT_END_SHIFT (16U)
44201#define SUBSAM_SS_CHKSUM_END_HCOUNT_END(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_END_HCOUNT_END_SHIFT)) & SUBSAM_SS_CHKSUM_END_HCOUNT_END_MASK)
44202/*! @} */
44203
44204/*! @name SS_CHKSUM_DATA_LOW - */
44205/*! @{ */
44206#define SUBSAM_SS_CHKSUM_DATA_LOW_CHKSUM_RESULT_MASK (0xFFFFFFFFU)
44207#define SUBSAM_SS_CHKSUM_DATA_LOW_CHKSUM_RESULT_SHIFT (0U)
44208#define SUBSAM_SS_CHKSUM_DATA_LOW_CHKSUM_RESULT(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_DATA_LOW_CHKSUM_RESULT_SHIFT)) & SUBSAM_SS_CHKSUM_DATA_LOW_CHKSUM_RESULT_MASK)
44209/*! @} */
44210
44211/*! @name SS_CHKSUM_DATA_HIGH - */
44212/*! @{ */
44213#define SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_RESULT_MASK (0x3FFU)
44214#define SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_RESULT_SHIFT (0U)
44215#define SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_RESULT(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_RESULT_SHIFT)) & SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_RESULT_MASK)
44216#define SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_VLD_MASK (0x80000000U)
44217#define SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_VLD_SHIFT (31U)
44218#define SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_VLD(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_VLD_SHIFT)) & SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_VLD_MASK)
44219/*! @} */
44220
44221
44222/*!
44223 * @}
44224 */ /* end of group SUBSAM_Register_Masks */
44225
44226
44227/* SUBSAM - Peripheral instance base addresses */
44228/** Peripheral DCSS__SUBSAM base address */
44229#define DCSS__SUBSAM_BASE (0x32E1B000u)
44230/** Peripheral DCSS__SUBSAM base pointer */
44231#define DCSS__SUBSAM ((SUBSAM_Type *)DCSS__SUBSAM_BASE)
44232/** Array initializer of SUBSAM peripheral base addresses */
44233#define SUBSAM_BASE_ADDRS { DCSS__SUBSAM_BASE }
44234/** Array initializer of SUBSAM peripheral base pointers */
44235#define SUBSAM_BASE_PTRS { DCSS__SUBSAM }
44236
44237/*!
44238 * @}
44239 */ /* end of group SUBSAM_Peripheral_Access_Layer */
44240
44241
44242/* ----------------------------------------------------------------------------
44243 -- TMU Peripheral Access Layer
44244 ---------------------------------------------------------------------------- */
44245
44246/*!
44247 * @addtogroup TMU_Peripheral_Access_Layer TMU Peripheral Access Layer
44248 * @{
44249 */
44250
44251/** TMU - Register Layout Typedef */
44252typedef struct {
44253 __IO uint32_t TMR; /**< TMU Mode register, offset: 0x0 */
44254 __I uint32_t TSR; /**< TMU Status register, offset: 0x4 */
44255 __IO uint32_t TMTMIR; /**< TMU Monitor Temperature Measurement Interval register, offset: 0x8 */
44256 uint8_t RESERVED_0[20];
44257 __IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x20 */
44258 __IO uint32_t TIDR; /**< TMU Interrupt Detect register, offset: 0x24 */
44259 __IO uint32_t TISCR; /**< TMU Interrupt Site Capture register, offset: 0x28 */
44260 __IO uint32_t TICSCR; /**< TMU Interrupt Critical Site Capture register, offset: 0x2C */
44261 uint8_t RESERVED_1[16];
44262 __I uint32_t TMHTCRH; /**< TMU Monitor High Temperature Capture register, offset: 0x40 */
44263 __I uint32_t TMHTCRL; /**< TMU Monitor Low Temperature Capture register, offset: 0x44 */
44264 uint8_t RESERVED_2[8];
44265 __IO uint32_t TMHTITR; /**< TMU Monitor High Temperature Immediate Threshold register, offset: 0x50 */
44266 __IO uint32_t TMHTATR; /**< TMU Monitor High Temperature Average threshold register, offset: 0x54 */
44267 __IO uint32_t TMHTACTR; /**< TMU Monitor High Temperature Average Critical Threshold register, offset: 0x58 */
44268 uint8_t RESERVED_3[36];
44269 __IO uint32_t TTCFGR; /**< TMU Temperature Configuration register, offset: 0x80 */
44270 __IO uint32_t TSCFGR; /**< TMU Sensor Configuration register, offset: 0x84 */
44271 uint8_t RESERVED_4[120];
44272 struct { /* offset: 0x100, array step: 0x10 */
44273 __I uint32_t TRITSR; /**< TMU Report Immediate Temperature Site register n, array offset: 0x100, array step: 0x10 */
44274 __I uint32_t TRATSR; /**< TMU Report Average Temperature Site register n, array offset: 0x104, array step: 0x10 */
44275 uint8_t RESERVED_0[8];
44276 } TRTSR[16];
44277 uint8_t RESERVED_5[2552];
44278 __I uint32_t IPBRR0; /**< IP Block Revision register 0, offset: 0xBF8 */
44279 uint8_t RESERVED_6[788];
44280 __IO uint32_t TTRCR[4]; /**< TMU Temperature Range n Control register, array offset: 0xF10, array step: 0x4 */
44281} TMU_Type;
44282
44283/* ----------------------------------------------------------------------------
44284 -- TMU Register Masks
44285 ---------------------------------------------------------------------------- */
44286
44287/*!
44288 * @addtogroup TMU_Register_Masks TMU Register Masks
44289 * @{
44290 */
44291
44292/*! @name TMR - TMU Mode register */
44293/*! @{ */
44294#define TMU_TMR_MSITE_MASK (0xFFFFU)
44295#define TMU_TMR_MSITE_SHIFT (0U)
44296#define TMU_TMR_MSITE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMR_MSITE_SHIFT)) & TMU_TMR_MSITE_MASK)
44297#define TMU_TMR_ALPF_MASK (0xC000000U)
44298#define TMU_TMR_ALPF_SHIFT (26U)
44299/*! ALPF
44300 * 0b00..1.0
44301 * 0b01..0.5
44302 * 0b10..0.25
44303 * 0b11..0.125
44304 */
44305#define TMU_TMR_ALPF(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMR_ALPF_SHIFT)) & TMU_TMR_ALPF_MASK)
44306#define TMU_TMR_ME_MASK (0x80000000U)
44307#define TMU_TMR_ME_SHIFT (31U)
44308/*! ME
44309 * 0b0..No monitoring. Power saving mode.
44310 * 0b1..Monitoring of sites as defined by MSITE.
44311 */
44312#define TMU_TMR_ME(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMR_ME_SHIFT)) & TMU_TMR_ME_MASK)
44313/*! @} */
44314
44315/*! @name TSR - TMU Status register */
44316/*! @{ */
44317#define TMU_TSR_ORH_MASK (0x10000000U)
44318#define TMU_TSR_ORH_SHIFT (28U)
44319#define TMU_TSR_ORH(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_ORH_SHIFT)) & TMU_TSR_ORH_MASK)
44320#define TMU_TSR_ORL_MASK (0x20000000U)
44321#define TMU_TSR_ORL_SHIFT (29U)
44322#define TMU_TSR_ORL(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_ORL_SHIFT)) & TMU_TSR_ORL_MASK)
44323#define TMU_TSR_MIE_MASK (0x40000000U)
44324#define TMU_TSR_MIE_SHIFT (30U)
44325/*! MIE
44326 * 0b0..Monitoring interval not exceeded.
44327 * 0b1..Monitoring interval exceeded. The time required to perform measurement of all monitored sites has exceeded the monitoring interval as defined by TMTMIR.
44328 */
44329#define TMU_TSR_MIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_MIE_SHIFT)) & TMU_TSR_MIE_MASK)
44330/*! @} */
44331
44332/*! @name TMTMIR - TMU Monitor Temperature Measurement Interval register */
44333/*! @{ */
44334#define TMU_TMTMIR_TMI_MASK (0xFU)
44335#define TMU_TMTMIR_TMI_SHIFT (0U)
44336#define TMU_TMTMIR_TMI(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMTMIR_TMI_SHIFT)) & TMU_TMTMIR_TMI_MASK)
44337/*! @} */
44338
44339/*! @name TIER - TMU Interrupt Enable register */
44340/*! @{ */
44341#define TMU_TIER_ATCTEIE_MASK (0x20000000U)
44342#define TMU_TIER_ATCTEIE_SHIFT (29U)
44343/*! ATCTEIE
44344 * 0b0..Disabled.
44345 * 0b1..Interrupt enabled. Generate an interrupt if TIDR[ATCTE] is set.
44346 */
44347#define TMU_TIER_ATCTEIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ATCTEIE_SHIFT)) & TMU_TIER_ATCTEIE_MASK)
44348#define TMU_TIER_ATTEIE_MASK (0x40000000U)
44349#define TMU_TIER_ATTEIE_SHIFT (30U)
44350/*! ATTEIE
44351 * 0b0..Disabled.
44352 * 0b1..Interrupt enabled. Generate an interrupt if TIDR[ATTE] is set.
44353 */
44354#define TMU_TIER_ATTEIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ATTEIE_SHIFT)) & TMU_TIER_ATTEIE_MASK)
44355#define TMU_TIER_ITTEIE_MASK (0x80000000U)
44356#define TMU_TIER_ITTEIE_SHIFT (31U)
44357/*! ITTEIE
44358 * 0b0..Disabled.
44359 * 0b1..Interrupt enabled. Generate an interrupt if TIDR[ITTE] is set.
44360 */
44361#define TMU_TIER_ITTEIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ITTEIE_SHIFT)) & TMU_TIER_ITTEIE_MASK)
44362/*! @} */
44363
44364/*! @name TIDR - TMU Interrupt Detect register */
44365/*! @{ */
44366#define TMU_TIDR_ATCTE_MASK (0x20000000U)
44367#define TMU_TIDR_ATCTE_SHIFT (29U)
44368/*! ATCTE
44369 * 0b0..No threshold exceeded.
44370 * 0b1..Average temperature critical threshold, as defined by TMHTACTR, has been exceeded by one or more monitored sites. The sites which has exceeded the threshold are captured in TICSCR[CASITE].
44371 */
44372#define TMU_TIDR_ATCTE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ATCTE_SHIFT)) & TMU_TIDR_ATCTE_MASK)
44373#define TMU_TIDR_ATTE_MASK (0x40000000U)
44374#define TMU_TIDR_ATTE_SHIFT (30U)
44375/*! ATTE
44376 * 0b0..No threshold exceeded.
44377 * 0b1..Average temperature threshold, as defined by TMHTATR, has been exceeded by one or more monitored sites. The sites which has exceeded the threshold are captured in TISCR[ASITE].
44378 */
44379#define TMU_TIDR_ATTE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ATTE_SHIFT)) & TMU_TIDR_ATTE_MASK)
44380#define TMU_TIDR_ITTE_MASK (0x80000000U)
44381#define TMU_TIDR_ITTE_SHIFT (31U)
44382/*! ITTE
44383 * 0b0..No threshold exceeded.
44384 * 0b1..Immediate temperature threshold, as defined by TMHTITR, has been exceeded by one or more monitored sites. This includes an out-of-range measured temperature above 125degree C. The sites which has exceeded the threshold are captured in TISCR[ISITE].
44385 */
44386#define TMU_TIDR_ITTE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ITTE_SHIFT)) & TMU_TIDR_ITTE_MASK)
44387/*! @} */
44388
44389/*! @name TISCR - TMU Interrupt Site Capture register */
44390/*! @{ */
44391#define TMU_TISCR_ASITE_MASK (0xFFFFU)
44392#define TMU_TISCR_ASITE_SHIFT (0U)
44393#define TMU_TISCR_ASITE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TISCR_ASITE_SHIFT)) & TMU_TISCR_ASITE_MASK)
44394#define TMU_TISCR_ISITE_MASK (0xFFFF0000U)
44395#define TMU_TISCR_ISITE_SHIFT (16U)
44396#define TMU_TISCR_ISITE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TISCR_ISITE_SHIFT)) & TMU_TISCR_ISITE_MASK)
44397/*! @} */
44398
44399/*! @name TICSCR - TMU Interrupt Critical Site Capture register */
44400/*! @{ */
44401#define TMU_TICSCR_CASITE_MASK (0xFFFFU)
44402#define TMU_TICSCR_CASITE_SHIFT (0U)
44403#define TMU_TICSCR_CASITE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TICSCR_CASITE_SHIFT)) & TMU_TICSCR_CASITE_MASK)
44404/*! @} */
44405
44406/*! @name TMHTCRH - TMU Monitor High Temperature Capture register */
44407/*! @{ */
44408#define TMU_TMHTCRH_TEMP_MASK (0xFFU)
44409#define TMU_TMHTCRH_TEMP_SHIFT (0U)
44410#define TMU_TMHTCRH_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTCRH_TEMP_SHIFT)) & TMU_TMHTCRH_TEMP_MASK)
44411#define TMU_TMHTCRH_V_MASK (0x80000000U)
44412#define TMU_TMHTCRH_V_SHIFT (31U)
44413/*! V
44414 * 0b0..Temperature reading is not valid due to no measured temperature within the sensor range of 0-125 degree C for an enabled monitored site.
44415 * 0b1..Temperature reading is valid.
44416 */
44417#define TMU_TMHTCRH_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTCRH_V_SHIFT)) & TMU_TMHTCRH_V_MASK)
44418/*! @} */
44419
44420/*! @name TMHTCRL - TMU Monitor Low Temperature Capture register */
44421/*! @{ */
44422#define TMU_TMHTCRL_TEMP_MASK (0xFFU)
44423#define TMU_TMHTCRL_TEMP_SHIFT (0U)
44424#define TMU_TMHTCRL_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTCRL_TEMP_SHIFT)) & TMU_TMHTCRL_TEMP_MASK)
44425#define TMU_TMHTCRL_V_MASK (0x80000000U)
44426#define TMU_TMHTCRL_V_SHIFT (31U)
44427/*! V
44428 * 0b0..Temperature reading is not valid due to no measured temperature within the sensor range of 0-125 degree C for an enabled monitored site.
44429 * 0b1..Temperature reading is valid.
44430 */
44431#define TMU_TMHTCRL_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTCRL_V_SHIFT)) & TMU_TMHTCRL_V_MASK)
44432/*! @} */
44433
44434/*! @name TMHTITR - TMU Monitor High Temperature Immediate Threshold register */
44435/*! @{ */
44436#define TMU_TMHTITR_TEMP_MASK (0xFFU)
44437#define TMU_TMHTITR_TEMP_SHIFT (0U)
44438#define TMU_TMHTITR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_TEMP_SHIFT)) & TMU_TMHTITR_TEMP_MASK)
44439#define TMU_TMHTITR_EN_MASK (0x80000000U)
44440#define TMU_TMHTITR_EN_SHIFT (31U)
44441/*! EN
44442 * 0b0..Disabled.
44443 * 0b1..Threshold enabled.
44444 */
44445#define TMU_TMHTITR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_EN_SHIFT)) & TMU_TMHTITR_EN_MASK)
44446/*! @} */
44447
44448/*! @name TMHTATR - TMU Monitor High Temperature Average threshold register */
44449/*! @{ */
44450#define TMU_TMHTATR_TEMP_MASK (0xFFU)
44451#define TMU_TMHTATR_TEMP_SHIFT (0U)
44452#define TMU_TMHTATR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_TEMP_SHIFT)) & TMU_TMHTATR_TEMP_MASK)
44453#define TMU_TMHTATR_EN_MASK (0x80000000U)
44454#define TMU_TMHTATR_EN_SHIFT (31U)
44455/*! EN
44456 * 0b0..Disabled.
44457 * 0b1..Threshold enabled.
44458 */
44459#define TMU_TMHTATR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_EN_SHIFT)) & TMU_TMHTATR_EN_MASK)
44460/*! @} */
44461
44462/*! @name TMHTACTR - TMU Monitor High Temperature Average Critical Threshold register */
44463/*! @{ */
44464#define TMU_TMHTACTR_TEMP_MASK (0xFFU)
44465#define TMU_TMHTACTR_TEMP_SHIFT (0U)
44466#define TMU_TMHTACTR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_TEMP_SHIFT)) & TMU_TMHTACTR_TEMP_MASK)
44467#define TMU_TMHTACTR_EN_MASK (0x80000000U)
44468#define TMU_TMHTACTR_EN_SHIFT (31U)
44469/*! EN
44470 * 0b0..Disabled.
44471 * 0b1..Threshold enabled.
44472 */
44473#define TMU_TMHTACTR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_EN_SHIFT)) & TMU_TMHTACTR_EN_MASK)
44474/*! @} */
44475
44476/*! @name TTCFGR - TMU Temperature Configuration register */
44477/*! @{ */
44478#define TMU_TTCFGR_DATA_MASK (0xFFFFFFFFU)
44479#define TMU_TTCFGR_DATA_SHIFT (0U)
44480#define TMU_TTCFGR_DATA(x) (((uint32_t)(((uint32_t)(x)) << TMU_TTCFGR_DATA_SHIFT)) & TMU_TTCFGR_DATA_MASK)
44481/*! @} */
44482
44483/*! @name TSCFGR - TMU Sensor Configuration register */
44484/*! @{ */
44485#define TMU_TSCFGR_DATA_MASK (0xFFFFFFFFU)
44486#define TMU_TSCFGR_DATA_SHIFT (0U)
44487#define TMU_TSCFGR_DATA(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSCFGR_DATA_SHIFT)) & TMU_TSCFGR_DATA_MASK)
44488/*! @} */
44489
44490/*! @name TRITSR - TMU Report Immediate Temperature Site register n */
44491/*! @{ */
44492#define TMU_TRITSR_TEMP_MASK (0xFFU)
44493#define TMU_TRITSR_TEMP_SHIFT (0U)
44494#define TMU_TRITSR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_TEMP_SHIFT)) & TMU_TRITSR_TEMP_MASK)
44495#define TMU_TRITSR_V_MASK (0x80000000U)
44496#define TMU_TRITSR_V_SHIFT (31U)
44497/*! V
44498 * 0b0..Not valid. Temperature out of sensor range or first measurement still pending.
44499 * 0b1..Valid.
44500 */
44501#define TMU_TRITSR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_V_SHIFT)) & TMU_TRITSR_V_MASK)
44502/*! @} */
44503
44504/* The count of TMU_TRITSR */
44505#define TMU_TRITSR_COUNT (16U)
44506
44507/*! @name TRATSR - TMU Report Average Temperature Site register n */
44508/*! @{ */
44509#define TMU_TRATSR_TEMP_MASK (0xFFU)
44510#define TMU_TRATSR_TEMP_SHIFT (0U)
44511#define TMU_TRATSR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_TEMP_SHIFT)) & TMU_TRATSR_TEMP_MASK)
44512#define TMU_TRATSR_V_MASK (0x80000000U)
44513#define TMU_TRATSR_V_SHIFT (31U)
44514/*! V
44515 * 0b0..Not valid. Temperature out of sensor range or first measurement still pending.
44516 * 0b1..Valid.
44517 */
44518#define TMU_TRATSR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_V_SHIFT)) & TMU_TRATSR_V_MASK)
44519/*! @} */
44520
44521/* The count of TMU_TRATSR */
44522#define TMU_TRATSR_COUNT (16U)
44523
44524/*! @name IPBRR0 - IP Block Revision register 0 */
44525/*! @{ */
44526#define TMU_IPBRR0_IP_MN_MASK (0xFFU)
44527#define TMU_IPBRR0_IP_MN_SHIFT (0U)
44528#define TMU_IPBRR0_IP_MN(x) (((uint32_t)(((uint32_t)(x)) << TMU_IPBRR0_IP_MN_SHIFT)) & TMU_IPBRR0_IP_MN_MASK)
44529#define TMU_IPBRR0_IP_MJ_MASK (0xFF00U)
44530#define TMU_IPBRR0_IP_MJ_SHIFT (8U)
44531#define TMU_IPBRR0_IP_MJ(x) (((uint32_t)(((uint32_t)(x)) << TMU_IPBRR0_IP_MJ_SHIFT)) & TMU_IPBRR0_IP_MJ_MASK)
44532#define TMU_IPBRR0_IP_ID_MASK (0xFFFF0000U)
44533#define TMU_IPBRR0_IP_ID_SHIFT (16U)
44534#define TMU_IPBRR0_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TMU_IPBRR0_IP_ID_SHIFT)) & TMU_IPBRR0_IP_ID_MASK)
44535/*! @} */
44536
44537/*! @name TTRCR - TMU Temperature Range n Control register */
44538/*! @{ */
44539#define TMU_TTRCR_TEMP_MASK (0xFFU)
44540#define TMU_TTRCR_TEMP_SHIFT (0U)
44541#define TMU_TTRCR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TTRCR_TEMP_SHIFT)) & TMU_TTRCR_TEMP_MASK)
44542#define TMU_TTRCR_CAL_PTS_MASK (0xF0000U)
44543#define TMU_TTRCR_CAL_PTS_SHIFT (16U)
44544#define TMU_TTRCR_CAL_PTS(x) (((uint32_t)(((uint32_t)(x)) << TMU_TTRCR_CAL_PTS_SHIFT)) & TMU_TTRCR_CAL_PTS_MASK)
44545/*! @} */
44546
44547/* The count of TMU_TTRCR */
44548#define TMU_TTRCR_COUNT (4U)
44549
44550
44551/*!
44552 * @}
44553 */ /* end of group TMU_Register_Masks */
44554
44555
44556/* TMU - Peripheral instance base addresses */
44557/** Peripheral TMU base address */
44558#define TMU_BASE (0x30260000u)
44559/** Peripheral TMU base pointer */
44560#define TMU ((TMU_Type *)TMU_BASE)
44561/** Array initializer of TMU peripheral base addresses */
44562#define TMU_BASE_ADDRS { TMU_BASE }
44563/** Array initializer of TMU peripheral base pointers */
44564#define TMU_BASE_PTRS { TMU }
44565
44566/*!
44567 * @}
44568 */ /* end of group TMU_Peripheral_Access_Layer */
44569
44570
44571/* ----------------------------------------------------------------------------
44572 -- UART Peripheral Access Layer
44573 ---------------------------------------------------------------------------- */
44574
44575/*!
44576 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
44577 * @{
44578 */
44579
44580/** UART - Register Layout Typedef */
44581typedef struct {
44582 __I uint32_t URXD; /**< UART Receiver Register, offset: 0x0 */
44583 uint8_t RESERVED_0[60];
44584 __O uint32_t UTXD; /**< UART Transmitter Register, offset: 0x40 */
44585 uint8_t RESERVED_1[60];
44586 __IO uint32_t UCR1; /**< UART Control Register 1, offset: 0x80 */
44587 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */
44588 __IO uint32_t UCR3; /**< UART Control Register 3, offset: 0x88 */
44589 __IO uint32_t UCR4; /**< UART Control Register 4, offset: 0x8C */
44590 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */
44591 __IO uint32_t USR1; /**< UART Status Register 1, offset: 0x94 */
44592 __IO uint32_t USR2; /**< UART Status Register 2, offset: 0x98 */
44593 __IO uint32_t UESC; /**< UART Escape Character Register, offset: 0x9C */
44594 __IO uint32_t UTIM; /**< UART Escape Timer Register, offset: 0xA0 */
44595 __IO uint32_t UBIR; /**< UART BRM Incremental Register, offset: 0xA4 */
44596 __IO uint32_t UBMR; /**< UART BRM Modulator Register, offset: 0xA8 */
44597 __I uint32_t UBRC; /**< UART Baud Rate Count Register, offset: 0xAC */
44598 __IO uint32_t ONEMS; /**< UART One Millisecond Register, offset: 0xB0 */
44599 __IO uint32_t UTS; /**< UART Test Register, offset: 0xB4 */
44600 __IO uint32_t UMCR; /**< UART RS-485 Mode Control Register, offset: 0xB8 */
44601} UART_Type;
44602
44603/* ----------------------------------------------------------------------------
44604 -- UART Register Masks
44605 ---------------------------------------------------------------------------- */
44606
44607/*!
44608 * @addtogroup UART_Register_Masks UART Register Masks
44609 * @{
44610 */
44611
44612/*! @name URXD - UART Receiver Register */
44613/*! @{ */
44614#define UART_URXD_RX_DATA_MASK (0xFFU)
44615#define UART_URXD_RX_DATA_SHIFT (0U)
44616#define UART_URXD_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_RX_DATA_SHIFT)) & UART_URXD_RX_DATA_MASK)
44617#define UART_URXD_PRERR_MASK (0x400U)
44618#define UART_URXD_PRERR_SHIFT (10U)
44619/*! PRERR
44620 * 0b0..= No parity error was detected for data in the RX_DATA field
44621 * 0b1..= A parity error was detected for data in the RX_DATA field
44622 */
44623#define UART_URXD_PRERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_PRERR_SHIFT)) & UART_URXD_PRERR_MASK)
44624#define UART_URXD_BRK_MASK (0x800U)
44625#define UART_URXD_BRK_SHIFT (11U)
44626/*! BRK
44627 * 0b0..The current character is not a BREAK character
44628 * 0b1..The current character is a BREAK character
44629 */
44630#define UART_URXD_BRK(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_BRK_SHIFT)) & UART_URXD_BRK_MASK)
44631#define UART_URXD_FRMERR_MASK (0x1000U)
44632#define UART_URXD_FRMERR_SHIFT (12U)
44633/*! FRMERR
44634 * 0b0..The current character has no framing error
44635 * 0b1..The current character has a framing error
44636 */
44637#define UART_URXD_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_FRMERR_SHIFT)) & UART_URXD_FRMERR_MASK)
44638#define UART_URXD_OVRRUN_MASK (0x2000U)
44639#define UART_URXD_OVRRUN_SHIFT (13U)
44640/*! OVRRUN
44641 * 0b0..No RxFIFO overrun was detected
44642 * 0b1..A RxFIFO overrun was detected
44643 */
44644#define UART_URXD_OVRRUN(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_OVRRUN_SHIFT)) & UART_URXD_OVRRUN_MASK)
44645#define UART_URXD_ERR_MASK (0x4000U)
44646#define UART_URXD_ERR_SHIFT (14U)
44647/*! ERR
44648 * 0b0..No error status was detected
44649 * 0b1..An error status was detected
44650 */
44651#define UART_URXD_ERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_ERR_SHIFT)) & UART_URXD_ERR_MASK)
44652#define UART_URXD_CHARRDY_MASK (0x8000U)
44653#define UART_URXD_CHARRDY_SHIFT (15U)
44654/*! CHARRDY
44655 * 0b0..Character in RX_DATA field and associated flags are invalid.
44656 * 0b1..Character in RX_DATA field and associated flags valid and ready for reading.
44657 */
44658#define UART_URXD_CHARRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_CHARRDY_SHIFT)) & UART_URXD_CHARRDY_MASK)
44659/*! @} */
44660
44661/*! @name UTXD - UART Transmitter Register */
44662/*! @{ */
44663#define UART_UTXD_TX_DATA_MASK (0xFFU)
44664#define UART_UTXD_TX_DATA_SHIFT (0U)
44665#define UART_UTXD_TX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_UTXD_TX_DATA_SHIFT)) & UART_UTXD_TX_DATA_MASK)
44666/*! @} */
44667
44668/*! @name UCR1 - UART Control Register 1 */
44669/*! @{ */
44670#define UART_UCR1_UARTEN_MASK (0x1U)
44671#define UART_UCR1_UARTEN_SHIFT (0U)
44672/*! UARTEN
44673 * 0b0..Disable the UART
44674 * 0b1..Enable the UART
44675 */
44676#define UART_UCR1_UARTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_UARTEN_SHIFT)) & UART_UCR1_UARTEN_MASK)
44677#define UART_UCR1_DOZE_MASK (0x2U)
44678#define UART_UCR1_DOZE_SHIFT (1U)
44679/*! DOZE
44680 * 0b0..The UART is enabled when in DOZE state
44681 * 0b1..The UART is disabled when in DOZE state
44682 */
44683#define UART_UCR1_DOZE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_DOZE_SHIFT)) & UART_UCR1_DOZE_MASK)
44684#define UART_UCR1_ATDMAEN_MASK (0x4U)
44685#define UART_UCR1_ATDMAEN_SHIFT (2U)
44686/*! ATDMAEN
44687 * 0b0..Disable AGTIM DMA request
44688 * 0b1..Enable AGTIM DMA request
44689 */
44690#define UART_UCR1_ATDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ATDMAEN_SHIFT)) & UART_UCR1_ATDMAEN_MASK)
44691#define UART_UCR1_TXDMAEN_MASK (0x8U)
44692#define UART_UCR1_TXDMAEN_SHIFT (3U)
44693/*! TXDMAEN
44694 * 0b0..Disable transmit DMA request
44695 * 0b1..Enable transmit DMA request
44696 */
44697#define UART_UCR1_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXDMAEN_SHIFT)) & UART_UCR1_TXDMAEN_MASK)
44698#define UART_UCR1_SNDBRK_MASK (0x10U)
44699#define UART_UCR1_SNDBRK_SHIFT (4U)
44700/*! SNDBRK
44701 * 0b0..Do not send a BREAK character
44702 * 0b1..Send a BREAK character (continuous 0s)
44703 */
44704#define UART_UCR1_SNDBRK(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_SNDBRK_SHIFT)) & UART_UCR1_SNDBRK_MASK)
44705#define UART_UCR1_RTSDEN_MASK (0x20U)
44706#define UART_UCR1_RTSDEN_SHIFT (5U)
44707/*! RTSDEN
44708 * 0b0..Disable RTSD interrupt
44709 * 0b1..Enable RTSD interrupt
44710 */
44711#define UART_UCR1_RTSDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RTSDEN_SHIFT)) & UART_UCR1_RTSDEN_MASK)
44712#define UART_UCR1_TXMPTYEN_MASK (0x40U)
44713#define UART_UCR1_TXMPTYEN_SHIFT (6U)
44714/*! TXMPTYEN
44715 * 0b0..Disable the transmitter FIFO empty interrupt
44716 * 0b1..Enable the transmitter FIFO empty interrupt
44717 */
44718#define UART_UCR1_TXMPTYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXMPTYEN_SHIFT)) & UART_UCR1_TXMPTYEN_MASK)
44719#define UART_UCR1_IREN_MASK (0x80U)
44720#define UART_UCR1_IREN_SHIFT (7U)
44721/*! IREN
44722 * 0b0..Disable the IR interface
44723 * 0b1..Enable the IR interface
44724 */
44725#define UART_UCR1_IREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IREN_SHIFT)) & UART_UCR1_IREN_MASK)
44726#define UART_UCR1_RXDMAEN_MASK (0x100U)
44727#define UART_UCR1_RXDMAEN_SHIFT (8U)
44728/*! RXDMAEN
44729 * 0b0..Disable DMA request
44730 * 0b1..Enable DMA request
44731 */
44732#define UART_UCR1_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RXDMAEN_SHIFT)) & UART_UCR1_RXDMAEN_MASK)
44733#define UART_UCR1_RRDYEN_MASK (0x200U)
44734#define UART_UCR1_RRDYEN_SHIFT (9U)
44735/*! RRDYEN
44736 * 0b0..Disables the RRDY interrupt
44737 * 0b1..Enables the RRDY interrupt
44738 */
44739#define UART_UCR1_RRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RRDYEN_SHIFT)) & UART_UCR1_RRDYEN_MASK)
44740#define UART_UCR1_ICD_MASK (0xC00U)
44741#define UART_UCR1_ICD_SHIFT (10U)
44742/*! ICD
44743 * 0b00..Idle for more than 4 frames
44744 * 0b01..Idle for more than 8 frames
44745 * 0b10..Idle for more than 16 frames
44746 * 0b11..Idle for more than 32 frames
44747 */
44748#define UART_UCR1_ICD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ICD_SHIFT)) & UART_UCR1_ICD_MASK)
44749#define UART_UCR1_IDEN_MASK (0x1000U)
44750#define UART_UCR1_IDEN_SHIFT (12U)
44751/*! IDEN
44752 * 0b0..Disable the IDLE interrupt
44753 * 0b1..Enable the IDLE interrupt
44754 */
44755#define UART_UCR1_IDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IDEN_SHIFT)) & UART_UCR1_IDEN_MASK)
44756#define UART_UCR1_TRDYEN_MASK (0x2000U)
44757#define UART_UCR1_TRDYEN_SHIFT (13U)
44758/*! TRDYEN
44759 * 0b0..Disable the transmitter ready interrupt
44760 * 0b1..Enable the transmitter ready interrupt
44761 */
44762#define UART_UCR1_TRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TRDYEN_SHIFT)) & UART_UCR1_TRDYEN_MASK)
44763#define UART_UCR1_ADBR_MASK (0x4000U)
44764#define UART_UCR1_ADBR_SHIFT (14U)
44765/*! ADBR
44766 * 0b0..Disable automatic detection of baud rate
44767 * 0b1..Enable automatic detection of baud rate
44768 */
44769#define UART_UCR1_ADBR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADBR_SHIFT)) & UART_UCR1_ADBR_MASK)
44770#define UART_UCR1_ADEN_MASK (0x8000U)
44771#define UART_UCR1_ADEN_SHIFT (15U)
44772/*! ADEN
44773 * 0b0..Disable the automatic baud rate detection interrupt
44774 * 0b1..Enable the automatic baud rate detection interrupt
44775 */
44776#define UART_UCR1_ADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADEN_SHIFT)) & UART_UCR1_ADEN_MASK)
44777/*! @} */
44778
44779/*! @name UCR2 - UART Control Register 2 */
44780/*! @{ */
44781#define UART_UCR2_SRST_MASK (0x1U)
44782#define UART_UCR2_SRST_SHIFT (0U)
44783/*! SRST
44784 * 0b0..Reset the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3].
44785 * 0b1..No reset
44786 */
44787#define UART_UCR2_SRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_SRST_SHIFT)) & UART_UCR2_SRST_MASK)
44788#define UART_UCR2_RXEN_MASK (0x2U)
44789#define UART_UCR2_RXEN_SHIFT (1U)
44790/*! RXEN
44791 * 0b0..Disable the receiver
44792 * 0b1..Enable the receiver
44793 */
44794#define UART_UCR2_RXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RXEN_SHIFT)) & UART_UCR2_RXEN_MASK)
44795#define UART_UCR2_TXEN_MASK (0x4U)
44796#define UART_UCR2_TXEN_SHIFT (2U)
44797/*! TXEN
44798 * 0b0..Disable the transmitter
44799 * 0b1..Enable the transmitter
44800 */
44801#define UART_UCR2_TXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_TXEN_SHIFT)) & UART_UCR2_TXEN_MASK)
44802#define UART_UCR2_ATEN_MASK (0x8U)
44803#define UART_UCR2_ATEN_SHIFT (3U)
44804/*! ATEN
44805 * 0b0..AGTIM interrupt disabled
44806 * 0b1..AGTIM interrupt enabled
44807 */
44808#define UART_UCR2_ATEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ATEN_SHIFT)) & UART_UCR2_ATEN_MASK)
44809#define UART_UCR2_RTSEN_MASK (0x10U)
44810#define UART_UCR2_RTSEN_SHIFT (4U)
44811/*! RTSEN
44812 * 0b0..Disable request to send interrupt
44813 * 0b1..Enable request to send interrupt
44814 */
44815#define UART_UCR2_RTSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTSEN_SHIFT)) & UART_UCR2_RTSEN_MASK)
44816#define UART_UCR2_WS_MASK (0x20U)
44817#define UART_UCR2_WS_SHIFT (5U)
44818/*! WS
44819 * 0b0..7-bit transmit and receive character length (not including START, STOP or PARITY bits)
44820 * 0b1..8-bit transmit and receive character length (not including START, STOP or PARITY bits)
44821 */
44822#define UART_UCR2_WS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_WS_SHIFT)) & UART_UCR2_WS_MASK)
44823#define UART_UCR2_STPB_MASK (0x40U)
44824#define UART_UCR2_STPB_SHIFT (6U)
44825/*! STPB
44826 * 0b0..The transmitter sends 1 stop bit. The receiver expects 1 or more stop bits.
44827 * 0b1..The transmitter sends 2 stop bits. The receiver expects 2 or more stop bits.
44828 */
44829#define UART_UCR2_STPB(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_STPB_SHIFT)) & UART_UCR2_STPB_MASK)
44830#define UART_UCR2_PROE_MASK (0x80U)
44831#define UART_UCR2_PROE_SHIFT (7U)
44832/*! PROE
44833 * 0b0..Even parity
44834 * 0b1..Odd parity
44835 */
44836#define UART_UCR2_PROE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PROE_SHIFT)) & UART_UCR2_PROE_MASK)
44837#define UART_UCR2_PREN_MASK (0x100U)
44838#define UART_UCR2_PREN_SHIFT (8U)
44839/*! PREN
44840 * 0b0..Disable parity generator and checker
44841 * 0b1..Enable parity generator and checker
44842 */
44843#define UART_UCR2_PREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PREN_SHIFT)) & UART_UCR2_PREN_MASK)
44844#define UART_UCR2_RTEC_MASK (0x600U)
44845#define UART_UCR2_RTEC_SHIFT (9U)
44846/*! RTEC
44847 * 0b00..Trigger interrupt on a rising edge
44848 * 0b01..Trigger interrupt on a falling edge
44849 * 0b1x..Trigger interrupt on any edge
44850 */
44851#define UART_UCR2_RTEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTEC_SHIFT)) & UART_UCR2_RTEC_MASK)
44852#define UART_UCR2_ESCEN_MASK (0x800U)
44853#define UART_UCR2_ESCEN_SHIFT (11U)
44854/*! ESCEN
44855 * 0b0..Disable escape sequence detection
44856 * 0b1..Enable escape sequence detection
44857 */
44858#define UART_UCR2_ESCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCEN_SHIFT)) & UART_UCR2_ESCEN_MASK)
44859#define UART_UCR2_CTS_MASK (0x1000U)
44860#define UART_UCR2_CTS_SHIFT (12U)
44861/*! CTS
44862 * 0b0..The CTS_B pin is high (inactive)
44863 * 0b1..The CTS_B pin is low (active)
44864 */
44865#define UART_UCR2_CTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTS_SHIFT)) & UART_UCR2_CTS_MASK)
44866#define UART_UCR2_CTSC_MASK (0x2000U)
44867#define UART_UCR2_CTSC_SHIFT (13U)
44868/*! CTSC
44869 * 0b0..The CTS_B pin is controlled by the CTS bit
44870 * 0b1..The CTS_B pin is controlled by the receiver
44871 */
44872#define UART_UCR2_CTSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTSC_SHIFT)) & UART_UCR2_CTSC_MASK)
44873#define UART_UCR2_IRTS_MASK (0x4000U)
44874#define UART_UCR2_IRTS_SHIFT (14U)
44875/*! IRTS
44876 * 0b0..Transmit only when the RTS pin is asserted
44877 * 0b1..Ignore the RTS pin
44878 */
44879#define UART_UCR2_IRTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_IRTS_SHIFT)) & UART_UCR2_IRTS_MASK)
44880#define UART_UCR2_ESCI_MASK (0x8000U)
44881#define UART_UCR2_ESCI_SHIFT (15U)
44882/*! ESCI
44883 * 0b0..Disable the escape sequence interrupt
44884 * 0b1..Enable the escape sequence interrupt
44885 */
44886#define UART_UCR2_ESCI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCI_SHIFT)) & UART_UCR2_ESCI_MASK)
44887/*! @} */
44888
44889/*! @name UCR3 - UART Control Register 3 */
44890/*! @{ */
44891#define UART_UCR3_ACIEN_MASK (0x1U)
44892#define UART_UCR3_ACIEN_SHIFT (0U)
44893/*! ACIEN
44894 * 0b0..ACST interrupt disabled
44895 * 0b1..ACST interrupt enabled
44896 */
44897#define UART_UCR3_ACIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ACIEN_SHIFT)) & UART_UCR3_ACIEN_MASK)
44898#define UART_UCR3_INVT_MASK (0x2U)
44899#define UART_UCR3_INVT_SHIFT (1U)
44900/*! INVT
44901 * 0b0..TXD is not inverted
44902 * 0b1..TXD is inverted
44903 * 0b0..TXD Active low transmission
44904 * 0b1..TXD Active high transmission
44905 */
44906#define UART_UCR3_INVT(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_INVT_SHIFT)) & UART_UCR3_INVT_MASK)
44907#define UART_UCR3_RXDMUXSEL_MASK (0x4U)
44908#define UART_UCR3_RXDMUXSEL_SHIFT (2U)
44909#define UART_UCR3_RXDMUXSEL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDMUXSEL_SHIFT)) & UART_UCR3_RXDMUXSEL_MASK)
44910#define UART_UCR3_DTRDEN_MASK (0x8U)
44911#define UART_UCR3_DTRDEN_SHIFT (3U)
44912#define UART_UCR3_DTRDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTRDEN_SHIFT)) & UART_UCR3_DTRDEN_MASK)
44913#define UART_UCR3_AWAKEN_MASK (0x10U)
44914#define UART_UCR3_AWAKEN_SHIFT (4U)
44915/*! AWAKEN
44916 * 0b0..Disable the AWAKE interrupt
44917 * 0b1..Enable the AWAKE interrupt
44918 */
44919#define UART_UCR3_AWAKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AWAKEN_SHIFT)) & UART_UCR3_AWAKEN_MASK)
44920#define UART_UCR3_AIRINTEN_MASK (0x20U)
44921#define UART_UCR3_AIRINTEN_SHIFT (5U)
44922/*! AIRINTEN
44923 * 0b0..Disable the AIRINT interrupt
44924 * 0b1..Enable the AIRINT interrupt
44925 */
44926#define UART_UCR3_AIRINTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AIRINTEN_SHIFT)) & UART_UCR3_AIRINTEN_MASK)
44927#define UART_UCR3_RXDSEN_MASK (0x40U)
44928#define UART_UCR3_RXDSEN_SHIFT (6U)
44929/*! RXDSEN
44930 * 0b0..Disable the RXDS interrupt
44931 * 0b1..Enable the RXDS interrupt
44932 */
44933#define UART_UCR3_RXDSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDSEN_SHIFT)) & UART_UCR3_RXDSEN_MASK)
44934#define UART_UCR3_ADNIMP_MASK (0x80U)
44935#define UART_UCR3_ADNIMP_SHIFT (7U)
44936/*! ADNIMP
44937 * 0b0..Autobaud detection new features selected
44938 * 0b1..Keep old autobaud detection mechanism
44939 */
44940#define UART_UCR3_ADNIMP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ADNIMP_SHIFT)) & UART_UCR3_ADNIMP_MASK)
44941#define UART_UCR3_RI_MASK (0x100U)
44942#define UART_UCR3_RI_SHIFT (8U)
44943#define UART_UCR3_RI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RI_SHIFT)) & UART_UCR3_RI_MASK)
44944#define UART_UCR3_DCD_MASK (0x200U)
44945#define UART_UCR3_DCD_SHIFT (9U)
44946#define UART_UCR3_DCD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DCD_SHIFT)) & UART_UCR3_DCD_MASK)
44947#define UART_UCR3_DSR_MASK (0x400U)
44948#define UART_UCR3_DSR_SHIFT (10U)
44949#define UART_UCR3_DSR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DSR_SHIFT)) & UART_UCR3_DSR_MASK)
44950#define UART_UCR3_FRAERREN_MASK (0x800U)
44951#define UART_UCR3_FRAERREN_SHIFT (11U)
44952/*! FRAERREN
44953 * 0b0..Disable the frame error interrupt
44954 * 0b1..Enable the frame error interrupt
44955 */
44956#define UART_UCR3_FRAERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_FRAERREN_SHIFT)) & UART_UCR3_FRAERREN_MASK)
44957#define UART_UCR3_PARERREN_MASK (0x1000U)
44958#define UART_UCR3_PARERREN_SHIFT (12U)
44959/*! PARERREN
44960 * 0b0..Disable the parity error interrupt
44961 * 0b1..Enable the parity error interrupt
44962 */
44963#define UART_UCR3_PARERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_PARERREN_SHIFT)) & UART_UCR3_PARERREN_MASK)
44964#define UART_UCR3_DTREN_MASK (0x2000U)
44965#define UART_UCR3_DTREN_SHIFT (13U)
44966#define UART_UCR3_DTREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTREN_SHIFT)) & UART_UCR3_DTREN_MASK)
44967#define UART_UCR3_DPEC_MASK (0xC000U)
44968#define UART_UCR3_DPEC_SHIFT (14U)
44969#define UART_UCR3_DPEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DPEC_SHIFT)) & UART_UCR3_DPEC_MASK)
44970/*! @} */
44971
44972/*! @name UCR4 - UART Control Register 4 */
44973/*! @{ */
44974#define UART_UCR4_DREN_MASK (0x1U)
44975#define UART_UCR4_DREN_SHIFT (0U)
44976/*! DREN
44977 * 0b0..Disable RDR interrupt
44978 * 0b1..Enable RDR interrupt
44979 */
44980#define UART_UCR4_DREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_DREN_SHIFT)) & UART_UCR4_DREN_MASK)
44981#define UART_UCR4_OREN_MASK (0x2U)
44982#define UART_UCR4_OREN_SHIFT (1U)
44983/*! OREN
44984 * 0b0..Disable ORE interrupt
44985 * 0b1..Enable ORE interrupt
44986 */
44987#define UART_UCR4_OREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_OREN_SHIFT)) & UART_UCR4_OREN_MASK)
44988#define UART_UCR4_BKEN_MASK (0x4U)
44989#define UART_UCR4_BKEN_SHIFT (2U)
44990/*! BKEN
44991 * 0b0..Disable the BRCD interrupt
44992 * 0b1..Enable the BRCD interrupt
44993 */
44994#define UART_UCR4_BKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_BKEN_SHIFT)) & UART_UCR4_BKEN_MASK)
44995#define UART_UCR4_TCEN_MASK (0x8U)
44996#define UART_UCR4_TCEN_SHIFT (3U)
44997/*! TCEN
44998 * 0b0..Disable TXDC interrupt
44999 * 0b1..Enable TXDC interrupt
45000 */
45001#define UART_UCR4_TCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_TCEN_SHIFT)) & UART_UCR4_TCEN_MASK)
45002#define UART_UCR4_LPBYP_MASK (0x10U)
45003#define UART_UCR4_LPBYP_SHIFT (4U)
45004/*! LPBYP
45005 * 0b0..Low power features enabled
45006 * 0b1..Low power features disabled
45007 */
45008#define UART_UCR4_LPBYP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_LPBYP_SHIFT)) & UART_UCR4_LPBYP_MASK)
45009#define UART_UCR4_IRSC_MASK (0x20U)
45010#define UART_UCR4_IRSC_SHIFT (5U)
45011/*! IRSC
45012 * 0b0..The vote logic uses the sampling clock (16x baud rate) for normal operation
45013 * 0b1..The vote logic uses the UART reference clock
45014 */
45015#define UART_UCR4_IRSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IRSC_SHIFT)) & UART_UCR4_IRSC_MASK)
45016#define UART_UCR4_IDDMAEN_MASK (0x40U)
45017#define UART_UCR4_IDDMAEN_SHIFT (6U)
45018/*! IDDMAEN
45019 * 0b0..DMA IDLE interrupt disabled
45020 * 0b1..DMA IDLE interrupt enabled
45021 */
45022#define UART_UCR4_IDDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IDDMAEN_SHIFT)) & UART_UCR4_IDDMAEN_MASK)
45023#define UART_UCR4_WKEN_MASK (0x80U)
45024#define UART_UCR4_WKEN_SHIFT (7U)
45025/*! WKEN
45026 * 0b0..Disable the WAKE interrupt
45027 * 0b1..Enable the WAKE interrupt
45028 */
45029#define UART_UCR4_WKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_WKEN_SHIFT)) & UART_UCR4_WKEN_MASK)
45030#define UART_UCR4_ENIRI_MASK (0x100U)
45031#define UART_UCR4_ENIRI_SHIFT (8U)
45032/*! ENIRI
45033 * 0b0..Serial infrared Interrupt disabled
45034 * 0b1..Serial infrared Interrupt enabled
45035 */
45036#define UART_UCR4_ENIRI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_ENIRI_SHIFT)) & UART_UCR4_ENIRI_MASK)
45037#define UART_UCR4_INVR_MASK (0x200U)
45038#define UART_UCR4_INVR_SHIFT (9U)
45039/*! INVR
45040 * 0b0..RXD input is not inverted
45041 * 0b1..RXD input is inverted
45042 * 0b0..RXD active low detection
45043 * 0b1..RXD active high detection
45044 */
45045#define UART_UCR4_INVR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_INVR_SHIFT)) & UART_UCR4_INVR_MASK)
45046#define UART_UCR4_CTSTL_MASK (0xFC00U)
45047#define UART_UCR4_CTSTL_SHIFT (10U)
45048/*! CTSTL
45049 * 0b000000..0 characters received
45050 * 0b000001..1 characters in the RxFIFO
45051 * 0b100000..32 characters in the RxFIFO (maximum)
45052 */
45053#define UART_UCR4_CTSTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_CTSTL_SHIFT)) & UART_UCR4_CTSTL_MASK)
45054/*! @} */
45055
45056/*! @name UFCR - UART FIFO Control Register */
45057/*! @{ */
45058#define UART_UFCR_RXTL_MASK (0x3FU)
45059#define UART_UFCR_RXTL_SHIFT (0U)
45060/*! RXTL
45061 * 0b000000..0 characters received
45062 * 0b000001..RxFIFO has 1 character
45063 * 0b011111..RxFIFO has 31 characters
45064 * 0b100000..RxFIFO has 32 characters (maximum)
45065 */
45066#define UART_UFCR_RXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RXTL_SHIFT)) & UART_UFCR_RXTL_MASK)
45067#define UART_UFCR_DCEDTE_MASK (0x40U)
45068#define UART_UFCR_DCEDTE_SHIFT (6U)
45069/*! DCEDTE
45070 * 0b0..DCE mode selected
45071 * 0b1..DTE mode selected
45072 */
45073#define UART_UFCR_DCEDTE(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_DCEDTE_SHIFT)) & UART_UFCR_DCEDTE_MASK)
45074#define UART_UFCR_RFDIV_MASK (0x380U)
45075#define UART_UFCR_RFDIV_SHIFT (7U)
45076/*! RFDIV
45077 * 0b000..Divide input clock by 6
45078 * 0b001..Divide input clock by 5
45079 * 0b010..Divide input clock by 4
45080 * 0b011..Divide input clock by 3
45081 * 0b100..Divide input clock by 2
45082 * 0b101..Divide input clock by 1
45083 * 0b110..Divide input clock by 7
45084 * 0b111..Reserved
45085 */
45086#define UART_UFCR_RFDIV(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RFDIV_SHIFT)) & UART_UFCR_RFDIV_MASK)
45087#define UART_UFCR_TXTL_MASK (0xFC00U)
45088#define UART_UFCR_TXTL_SHIFT (10U)
45089/*! TXTL
45090 * 0b000000..Reserved
45091 * 0b000001..Reserved
45092 * 0b000010..TxFIFO has 2 or fewer characters
45093 * 0b011111..TxFIFO has 31 or fewer characters
45094 * 0b100000..TxFIFO has 32 characters (maximum)
45095 */
45096#define UART_UFCR_TXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_TXTL_SHIFT)) & UART_UFCR_TXTL_MASK)
45097/*! @} */
45098
45099/*! @name USR1 - UART Status Register 1 */
45100/*! @{ */
45101#define UART_USR1_SAD_MASK (0x8U)
45102#define UART_USR1_SAD_SHIFT (3U)
45103/*! SAD
45104 * 0b0..No slave address detected
45105 * 0b1..Slave address detected
45106 */
45107#define UART_USR1_SAD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_SAD_SHIFT)) & UART_USR1_SAD_MASK)
45108#define UART_USR1_AWAKE_MASK (0x10U)
45109#define UART_USR1_AWAKE_SHIFT (4U)
45110/*! AWAKE
45111 * 0b0..No falling edge was detected on the RXD Serial pin
45112 * 0b1..A falling edge was detected on the RXD Serial pin
45113 */
45114#define UART_USR1_AWAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AWAKE_SHIFT)) & UART_USR1_AWAKE_MASK)
45115#define UART_USR1_AIRINT_MASK (0x20U)
45116#define UART_USR1_AIRINT_SHIFT (5U)
45117/*! AIRINT
45118 * 0b0..No pulse was detected on the RXD IrDA pin
45119 * 0b1..A pulse was detected on the RXD IrDA pin
45120 */
45121#define UART_USR1_AIRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AIRINT_SHIFT)) & UART_USR1_AIRINT_MASK)
45122#define UART_USR1_RXDS_MASK (0x40U)
45123#define UART_USR1_RXDS_SHIFT (6U)
45124/*! RXDS
45125 * 0b0..Receive in progress
45126 * 0b1..Receiver is IDLE
45127 */
45128#define UART_USR1_RXDS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RXDS_SHIFT)) & UART_USR1_RXDS_MASK)
45129#define UART_USR1_DTRD_MASK (0x80U)
45130#define UART_USR1_DTRD_SHIFT (7U)
45131#define UART_USR1_DTRD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_DTRD_SHIFT)) & UART_USR1_DTRD_MASK)
45132#define UART_USR1_AGTIM_MASK (0x100U)
45133#define UART_USR1_AGTIM_SHIFT (8U)
45134/*! AGTIM
45135 * 0b0..AGTIM is not active
45136 * 0b1..AGTIM is active (write 1 to clear)
45137 */
45138#define UART_USR1_AGTIM(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AGTIM_SHIFT)) & UART_USR1_AGTIM_MASK)
45139#define UART_USR1_RRDY_MASK (0x200U)
45140#define UART_USR1_RRDY_SHIFT (9U)
45141/*! RRDY
45142 * 0b0..No character ready
45143 * 0b1..Character(s) ready (interrupt posted)
45144 */
45145#define UART_USR1_RRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RRDY_SHIFT)) & UART_USR1_RRDY_MASK)
45146#define UART_USR1_FRAMERR_MASK (0x400U)
45147#define UART_USR1_FRAMERR_SHIFT (10U)
45148/*! FRAMERR
45149 * 0b0..No frame error detected
45150 * 0b1..Frame error detected (write 1 to clear)
45151 */
45152#define UART_USR1_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_FRAMERR_SHIFT)) & UART_USR1_FRAMERR_MASK)
45153#define UART_USR1_ESCF_MASK (0x800U)
45154#define UART_USR1_ESCF_SHIFT (11U)
45155/*! ESCF
45156 * 0b0..No escape sequence detected
45157 * 0b1..Escape sequence detected (write 1 to clear).
45158 */
45159#define UART_USR1_ESCF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_ESCF_SHIFT)) & UART_USR1_ESCF_MASK)
45160#define UART_USR1_RTSD_MASK (0x1000U)
45161#define UART_USR1_RTSD_SHIFT (12U)
45162/*! RTSD
45163 * 0b0..RTS_B pin did not change state since last cleared
45164 * 0b1..RTS_B pin changed state (write 1 to clear)
45165 */
45166#define UART_USR1_RTSD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSD_SHIFT)) & UART_USR1_RTSD_MASK)
45167#define UART_USR1_TRDY_MASK (0x2000U)
45168#define UART_USR1_TRDY_SHIFT (13U)
45169/*! TRDY
45170 * 0b0..The transmitter does not require data
45171 * 0b1..The transmitter requires data (interrupt posted)
45172 */
45173#define UART_USR1_TRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_TRDY_SHIFT)) & UART_USR1_TRDY_MASK)
45174#define UART_USR1_RTSS_MASK (0x4000U)
45175#define UART_USR1_RTSS_SHIFT (14U)
45176/*! RTSS
45177 * 0b0..The RTS_B module input is high (inactive)
45178 * 0b1..The RTS_B module input is low (active)
45179 */
45180#define UART_USR1_RTSS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSS_SHIFT)) & UART_USR1_RTSS_MASK)
45181#define UART_USR1_PARITYERR_MASK (0x8000U)
45182#define UART_USR1_PARITYERR_SHIFT (15U)
45183/*! PARITYERR
45184 * 0b0..No parity error detected
45185 * 0b1..Parity error detected (write 1 to clear)
45186 */
45187#define UART_USR1_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_PARITYERR_SHIFT)) & UART_USR1_PARITYERR_MASK)
45188/*! @} */
45189
45190/*! @name USR2 - UART Status Register 2 */
45191/*! @{ */
45192#define UART_USR2_RDR_MASK (0x1U)
45193#define UART_USR2_RDR_SHIFT (0U)
45194/*! RDR
45195 * 0b0..No receive data ready
45196 * 0b1..Receive data ready
45197 */
45198#define UART_USR2_RDR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RDR_SHIFT)) & UART_USR2_RDR_MASK)
45199#define UART_USR2_ORE_MASK (0x2U)
45200#define UART_USR2_ORE_SHIFT (1U)
45201/*! ORE
45202 * 0b0..No overrun error
45203 * 0b1..Overrun error (write 1 to clear)
45204 */
45205#define UART_USR2_ORE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ORE_SHIFT)) & UART_USR2_ORE_MASK)
45206#define UART_USR2_BRCD_MASK (0x4U)
45207#define UART_USR2_BRCD_SHIFT (2U)
45208/*! BRCD
45209 * 0b0..No BREAK condition was detected
45210 * 0b1..A BREAK condition was detected (write 1 to clear)
45211 */
45212#define UART_USR2_BRCD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_BRCD_SHIFT)) & UART_USR2_BRCD_MASK)
45213#define UART_USR2_TXDC_MASK (0x8U)
45214#define UART_USR2_TXDC_SHIFT (3U)
45215/*! TXDC
45216 * 0b0..Transmit is incomplete
45217 * 0b1..Transmit is complete
45218 */
45219#define UART_USR2_TXDC(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXDC_SHIFT)) & UART_USR2_TXDC_MASK)
45220#define UART_USR2_RTSF_MASK (0x10U)
45221#define UART_USR2_RTSF_SHIFT (4U)
45222/*! RTSF
45223 * 0b0..Programmed edge not detected on RTS_B
45224 * 0b1..Programmed edge detected on RTS_B (write 1 to clear)
45225 */
45226#define UART_USR2_RTSF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RTSF_SHIFT)) & UART_USR2_RTSF_MASK)
45227#define UART_USR2_DCDIN_MASK (0x20U)
45228#define UART_USR2_DCDIN_SHIFT (5U)
45229#define UART_USR2_DCDIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDIN_SHIFT)) & UART_USR2_DCDIN_MASK)
45230#define UART_USR2_DCDDELT_MASK (0x40U)
45231#define UART_USR2_DCDDELT_SHIFT (6U)
45232#define UART_USR2_DCDDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDDELT_SHIFT)) & UART_USR2_DCDDELT_MASK)
45233#define UART_USR2_WAKE_MASK (0x80U)
45234#define UART_USR2_WAKE_SHIFT (7U)
45235/*! WAKE
45236 * 0b0..start bit not detected
45237 * 0b1..start bit detected (write 1 to clear)
45238 */
45239#define UART_USR2_WAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_WAKE_SHIFT)) & UART_USR2_WAKE_MASK)
45240#define UART_USR2_IRINT_MASK (0x100U)
45241#define UART_USR2_IRINT_SHIFT (8U)
45242/*! IRINT
45243 * 0b0..no edge detected
45244 * 0b1..valid edge detected (write 1 to clear)
45245 */
45246#define UART_USR2_IRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IRINT_SHIFT)) & UART_USR2_IRINT_MASK)
45247#define UART_USR2_RIIN_MASK (0x200U)
45248#define UART_USR2_RIIN_SHIFT (9U)
45249#define UART_USR2_RIIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIIN_SHIFT)) & UART_USR2_RIIN_MASK)
45250#define UART_USR2_RIDELT_MASK (0x400U)
45251#define UART_USR2_RIDELT_SHIFT (10U)
45252#define UART_USR2_RIDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIDELT_SHIFT)) & UART_USR2_RIDELT_MASK)
45253#define UART_USR2_ACST_MASK (0x800U)
45254#define UART_USR2_ACST_SHIFT (11U)
45255/*! ACST
45256 * 0b0..Measurement of bit length not finished (in autobaud)
45257 * 0b1..Measurement of bit length finished (in autobaud). (write 1 to clear)
45258 */
45259#define UART_USR2_ACST(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ACST_SHIFT)) & UART_USR2_ACST_MASK)
45260#define UART_USR2_IDLE_MASK (0x1000U)
45261#define UART_USR2_IDLE_SHIFT (12U)
45262/*! IDLE
45263 * 0b0..No idle condition detected
45264 * 0b1..Idle condition detected (write 1 to clear)
45265 */
45266#define UART_USR2_IDLE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IDLE_SHIFT)) & UART_USR2_IDLE_MASK)
45267#define UART_USR2_DTRF_MASK (0x2000U)
45268#define UART_USR2_DTRF_SHIFT (13U)
45269#define UART_USR2_DTRF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DTRF_SHIFT)) & UART_USR2_DTRF_MASK)
45270#define UART_USR2_TXFE_MASK (0x4000U)
45271#define UART_USR2_TXFE_SHIFT (14U)
45272/*! TXFE
45273 * 0b0..The transmit buffer (TxFIFO) is not empty
45274 * 0b1..The transmit buffer (TxFIFO) is empty
45275 */
45276#define UART_USR2_TXFE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXFE_SHIFT)) & UART_USR2_TXFE_MASK)
45277#define UART_USR2_ADET_MASK (0x8000U)
45278#define UART_USR2_ADET_SHIFT (15U)
45279/*! ADET
45280 * 0b0..ASCII "A" or "a" was not received
45281 * 0b1..ASCII "A" or "a" was received (write 1 to clear)
45282 */
45283#define UART_USR2_ADET(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ADET_SHIFT)) & UART_USR2_ADET_MASK)
45284/*! @} */
45285
45286/*! @name UESC - UART Escape Character Register */
45287/*! @{ */
45288#define UART_UESC_ESC_CHAR_MASK (0xFFU)
45289#define UART_UESC_ESC_CHAR_SHIFT (0U)
45290#define UART_UESC_ESC_CHAR(x) (((uint32_t)(((uint32_t)(x)) << UART_UESC_ESC_CHAR_SHIFT)) & UART_UESC_ESC_CHAR_MASK)
45291/*! @} */
45292
45293/*! @name UTIM - UART Escape Timer Register */
45294/*! @{ */
45295#define UART_UTIM_TIM_MASK (0xFFFU)
45296#define UART_UTIM_TIM_SHIFT (0U)
45297#define UART_UTIM_TIM(x) (((uint32_t)(((uint32_t)(x)) << UART_UTIM_TIM_SHIFT)) & UART_UTIM_TIM_MASK)
45298/*! @} */
45299
45300/*! @name UBIR - UART BRM Incremental Register */
45301/*! @{ */
45302#define UART_UBIR_INC_MASK (0xFFFFU)
45303#define UART_UBIR_INC_SHIFT (0U)
45304#define UART_UBIR_INC(x) (((uint32_t)(((uint32_t)(x)) << UART_UBIR_INC_SHIFT)) & UART_UBIR_INC_MASK)
45305/*! @} */
45306
45307/*! @name UBMR - UART BRM Modulator Register */
45308/*! @{ */
45309#define UART_UBMR_MOD_MASK (0xFFFFU)
45310#define UART_UBMR_MOD_SHIFT (0U)
45311#define UART_UBMR_MOD(x) (((uint32_t)(((uint32_t)(x)) << UART_UBMR_MOD_SHIFT)) & UART_UBMR_MOD_MASK)
45312/*! @} */
45313
45314/*! @name UBRC - UART Baud Rate Count Register */
45315/*! @{ */
45316#define UART_UBRC_BCNT_MASK (0xFFFFU)
45317#define UART_UBRC_BCNT_SHIFT (0U)
45318#define UART_UBRC_BCNT(x) (((uint32_t)(((uint32_t)(x)) << UART_UBRC_BCNT_SHIFT)) & UART_UBRC_BCNT_MASK)
45319/*! @} */
45320
45321/*! @name ONEMS - UART One Millisecond Register */
45322/*! @{ */
45323#define UART_ONEMS_ONEMS_MASK (0xFFFFFFU)
45324#define UART_ONEMS_ONEMS_SHIFT (0U)
45325#define UART_ONEMS_ONEMS(x) (((uint32_t)(((uint32_t)(x)) << UART_ONEMS_ONEMS_SHIFT)) & UART_ONEMS_ONEMS_MASK)
45326/*! @} */
45327
45328/*! @name UTS - UART Test Register */
45329/*! @{ */
45330#define UART_UTS_SOFTRST_MASK (0x1U)
45331#define UART_UTS_SOFTRST_SHIFT (0U)
45332/*! SOFTRST
45333 * 0b0..Software reset inactive
45334 * 0b1..Software reset active
45335 */
45336#define UART_UTS_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_SOFTRST_SHIFT)) & UART_UTS_SOFTRST_MASK)
45337#define UART_UTS_RXFULL_MASK (0x8U)
45338#define UART_UTS_RXFULL_SHIFT (3U)
45339/*! RXFULL
45340 * 0b0..The RxFIFO is not full
45341 * 0b1..The RxFIFO is full
45342 */
45343#define UART_UTS_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXFULL_SHIFT)) & UART_UTS_RXFULL_MASK)
45344#define UART_UTS_TXFULL_MASK (0x10U)
45345#define UART_UTS_TXFULL_SHIFT (4U)
45346/*! TXFULL
45347 * 0b0..The TxFIFO is not full
45348 * 0b1..The TxFIFO is full
45349 */
45350#define UART_UTS_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXFULL_SHIFT)) & UART_UTS_TXFULL_MASK)
45351#define UART_UTS_RXEMPTY_MASK (0x20U)
45352#define UART_UTS_RXEMPTY_SHIFT (5U)
45353/*! RXEMPTY
45354 * 0b0..The RxFIFO is not empty
45355 * 0b1..The RxFIFO is empty
45356 */
45357#define UART_UTS_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXEMPTY_SHIFT)) & UART_UTS_RXEMPTY_MASK)
45358#define UART_UTS_TXEMPTY_MASK (0x40U)
45359#define UART_UTS_TXEMPTY_SHIFT (6U)
45360/*! TXEMPTY
45361 * 0b0..The TxFIFO is not empty
45362 * 0b1..The TxFIFO is empty
45363 */
45364#define UART_UTS_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXEMPTY_SHIFT)) & UART_UTS_TXEMPTY_MASK)
45365#define UART_UTS_RXDBG_MASK (0x200U)
45366#define UART_UTS_RXDBG_SHIFT (9U)
45367/*! RXDBG
45368 * 0b0..rx fifo read pointer does not increment
45369 * 0b1..rx_fifo read pointer increments as normal
45370 */
45371#define UART_UTS_RXDBG(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXDBG_SHIFT)) & UART_UTS_RXDBG_MASK)
45372#define UART_UTS_LOOPIR_MASK (0x400U)
45373#define UART_UTS_LOOPIR_SHIFT (10U)
45374/*! LOOPIR
45375 * 0b0..No IR loop
45376 * 0b1..Connect IR transmitter to IR receiver
45377 */
45378#define UART_UTS_LOOPIR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOPIR_SHIFT)) & UART_UTS_LOOPIR_MASK)
45379#define UART_UTS_DBGEN_MASK (0x800U)
45380#define UART_UTS_DBGEN_SHIFT (11U)
45381/*! DBGEN
45382 * 0b0..UART will go into debug mode when debug_req is HIGH
45383 * 0b1..UART will not go into debug mode even if debug_req is HIGH
45384 */
45385#define UART_UTS_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_DBGEN_SHIFT)) & UART_UTS_DBGEN_MASK)
45386#define UART_UTS_LOOP_MASK (0x1000U)
45387#define UART_UTS_LOOP_SHIFT (12U)
45388/*! LOOP
45389 * 0b0..Normal receiver operation
45390 * 0b1..Internally connect the transmitter output to the receiver input
45391 */
45392#define UART_UTS_LOOP(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOP_SHIFT)) & UART_UTS_LOOP_MASK)
45393#define UART_UTS_FRCPERR_MASK (0x2000U)
45394#define UART_UTS_FRCPERR_SHIFT (13U)
45395/*! FRCPERR
45396 * 0b0..Generate normal parity
45397 * 0b1..Generate inverted parity (error)
45398 */
45399#define UART_UTS_FRCPERR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_FRCPERR_SHIFT)) & UART_UTS_FRCPERR_MASK)
45400/*! @} */
45401
45402/*! @name UMCR - UART RS-485 Mode Control Register */
45403/*! @{ */
45404#define UART_UMCR_MDEN_MASK (0x1U)
45405#define UART_UMCR_MDEN_SHIFT (0U)
45406/*! MDEN
45407 * 0b0..Normal RS-232 or IrDA mode, see for detail.
45408 * 0b1..Enable RS-485 mode, see for detail
45409 */
45410#define UART_UMCR_MDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_MDEN_SHIFT)) & UART_UMCR_MDEN_MASK)
45411#define UART_UMCR_SLAM_MASK (0x2U)
45412#define UART_UMCR_SLAM_SHIFT (1U)
45413/*! SLAM
45414 * 0b0..Select Normal Address Detect mode
45415 * 0b1..Select Automatic Address Detect mode
45416 */
45417#define UART_UMCR_SLAM(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLAM_SHIFT)) & UART_UMCR_SLAM_MASK)
45418#define UART_UMCR_TXB8_MASK (0x4U)
45419#define UART_UMCR_TXB8_SHIFT (2U)
45420/*! TXB8
45421 * 0b0..0 will be transmitted as the RS485 9th data bit
45422 * 0b1..1 will be transmitted as the RS485 9th data bit
45423 */
45424#define UART_UMCR_TXB8(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_TXB8_SHIFT)) & UART_UMCR_TXB8_MASK)
45425#define UART_UMCR_SADEN_MASK (0x8U)
45426#define UART_UMCR_SADEN_SHIFT (3U)
45427/*! SADEN
45428 * 0b0..Disable RS-485 Slave Address Detected Interrupt
45429 * 0b1..Enable RS-485 Slave Address Detected Interrupt
45430 */
45431#define UART_UMCR_SADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SADEN_SHIFT)) & UART_UMCR_SADEN_MASK)
45432#define UART_UMCR_SLADDR_MASK (0xFF00U)
45433#define UART_UMCR_SLADDR_SHIFT (8U)
45434#define UART_UMCR_SLADDR(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLADDR_SHIFT)) & UART_UMCR_SLADDR_MASK)
45435/*! @} */
45436
45437
45438/*!
45439 * @}
45440 */ /* end of group UART_Register_Masks */
45441
45442
45443/* UART - Peripheral instance base addresses */
45444/** Peripheral UART1 base address */
45445#define UART1_BASE (0x30860000u)
45446/** Peripheral UART1 base pointer */
45447#define UART1 ((UART_Type *)UART1_BASE)
45448/** Peripheral UART2 base address */
45449#define UART2_BASE (0x30890000u)
45450/** Peripheral UART2 base pointer */
45451#define UART2 ((UART_Type *)UART2_BASE)
45452/** Peripheral UART3 base address */
45453#define UART3_BASE (0x30880000u)
45454/** Peripheral UART3 base pointer */
45455#define UART3 ((UART_Type *)UART3_BASE)
45456/** Peripheral UART4 base address */
45457#define UART4_BASE (0x30A60000u)
45458/** Peripheral UART4 base pointer */
45459#define UART4 ((UART_Type *)UART4_BASE)
45460/** Array initializer of UART peripheral base addresses */
45461#define UART_BASE_ADDRS { 0u, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE }
45462/** Array initializer of UART peripheral base pointers */
45463#define UART_BASE_PTRS { (UART_Type *)0u, UART1, UART2, UART3, UART4 }
45464/** Interrupt vectors for the UART peripheral type */
45465#define UART_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn, UART3_IRQn, UART4_IRQn }
45466
45467/*!
45468 * @}
45469 */ /* end of group UART_Peripheral_Access_Layer */
45470
45471
45472/* ----------------------------------------------------------------------------
45473 -- USDHC Peripheral Access Layer
45474 ---------------------------------------------------------------------------- */
45475
45476/*!
45477 * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
45478 * @{
45479 */
45480
45481/** USDHC - Register Layout Typedef */
45482typedef struct {
45483 __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */
45484 __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */
45485 __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */
45486 __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */
45487 __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */
45488 __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */
45489 __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */
45490 __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */
45491 __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */
45492 __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */
45493 __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */
45494 __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */
45495 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */
45496 __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */
45497 __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */
45498 __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */
45499 __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */
45500 __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */
45501 __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */
45502 uint8_t RESERVED_0[4];
45503 __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */
45504 __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */
45505 __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */
45506 uint8_t RESERVED_1[4];
45507 __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */
45508 __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */
45509 __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */
45510 uint8_t RESERVED_2[4];
45511 __IO uint32_t STROBE_DLL_CTRL; /**< Strobe DLL Control, offset: 0x70 */
45512 __I uint32_t STROBE_DLL_STATUS; /**< Strobe DLL Status, offset: 0x74 */
45513 uint8_t RESERVED_3[72];
45514 __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */
45515 __IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */
45516 __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */
45517 __IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */
45518} USDHC_Type;
45519
45520/* ----------------------------------------------------------------------------
45521 -- USDHC Register Masks
45522 ---------------------------------------------------------------------------- */
45523
45524/*!
45525 * @addtogroup USDHC_Register_Masks USDHC Register Masks
45526 * @{
45527 */
45528
45529/*! @name DS_ADDR - DMA System Address */
45530/*! @{ */
45531#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFCU)
45532#define USDHC_DS_ADDR_DS_ADDR_SHIFT (2U)
45533#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
45534/*! @} */
45535
45536/*! @name BLK_ATT - Block Attributes */
45537/*! @{ */
45538#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)
45539#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)
45540/*! BLKSIZE
45541 * 0b0000000001000..4096 Bytes
45542 * 0b0001100100000..2048 Bytes
45543 * 0b0000011001000..512 Bytes
45544 * 0b0000000000100..4 Bytes
45545 * 0b0000000000011..3 Bytes
45546 * 0b0000000000010..2 Bytes
45547 * 0b0000000000001..1 Byte
45548 * 0b0000000000000..No data transfer
45549 */
45550#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
45551#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)
45552#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U)
45553/*! BLKCNT
45554 * 0b0000000000000010..2 blocks
45555 * 0b0000000000000001..1 block
45556 * 0b0000000000000000..Stop Count
45557 */
45558#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
45559/*! @} */
45560
45561/*! @name CMD_ARG - Command Argument */
45562/*! @{ */
45563#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)
45564#define USDHC_CMD_ARG_CMDARG_SHIFT (0U)
45565#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
45566/*! @} */
45567
45568/*! @name CMD_XFR_TYP - Command Transfer Type */
45569/*! @{ */
45570#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)
45571#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)
45572/*! RSPTYP - Response Type Select
45573 * 0b00..No Response
45574 * 0b01..Response Length 136
45575 * 0b10..Response Length 48
45576 * 0b11..Response Length 48, check Busy after response
45577 */
45578#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
45579#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)
45580#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)
45581/*! CCCEN - Command CRC Check Enable
45582 * 0b1..Enable
45583 * 0b0..Disable
45584 */
45585#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
45586#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)
45587#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)
45588/*! CICEN - Command Index Check Enable
45589 * 0b1..Enable
45590 * 0b0..Disable
45591 */
45592#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
45593#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)
45594#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)
45595/*! DPSEL - Data Present Select
45596 * 0b1..Data Present
45597 * 0b0..No Data Present
45598 */
45599#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
45600#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)
45601#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)
45602/*! CMDTYP - Command Type
45603 * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
45604 * 0b10..Resume CMD52 for writing Function Select in CCCR
45605 * 0b01..Suspend CMD52 for writing Bus Suspend in CCCR
45606 * 0b00..Normal Other commands
45607 */
45608#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
45609#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)
45610#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)
45611#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
45612/*! @} */
45613
45614/*! @name CMD_RSP0 - Command Response0 */
45615/*! @{ */
45616#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)
45617#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)
45618#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
45619/*! @} */
45620
45621/*! @name CMD_RSP1 - Command Response1 */
45622/*! @{ */
45623#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)
45624#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)
45625#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
45626/*! @} */
45627
45628/*! @name CMD_RSP2 - Command Response2 */
45629/*! @{ */
45630#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)
45631#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)
45632#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
45633/*! @} */
45634
45635/*! @name CMD_RSP3 - Command Response3 */
45636/*! @{ */
45637#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)
45638#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)
45639#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
45640/*! @} */
45641
45642/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
45643/*! @{ */
45644#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)
45645#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)
45646#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
45647/*! @} */
45648
45649/*! @name PRES_STATE - Present State */
45650/*! @{ */
45651#define USDHC_PRES_STATE_CIHB_MASK (0x1U)
45652#define USDHC_PRES_STATE_CIHB_SHIFT (0U)
45653/*! CIHB - Command Inhibit (CMD)
45654 * 0b1..Cannot issue command
45655 * 0b0..Can issue command using only CMD line
45656 */
45657#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
45658#define USDHC_PRES_STATE_CDIHB_MASK (0x2U)
45659#define USDHC_PRES_STATE_CDIHB_SHIFT (1U)
45660/*! CDIHB - Command Inhibit (DATA)
45661 * 0b1..Cannot issue command which uses the DATA line
45662 * 0b0..Can issue command which uses the DATA line
45663 */
45664#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
45665#define USDHC_PRES_STATE_DLA_MASK (0x4U)
45666#define USDHC_PRES_STATE_DLA_SHIFT (2U)
45667/*! DLA - Data Line Active
45668 * 0b1..DATA Line Active
45669 * 0b0..DATA Line Inactive
45670 */
45671#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
45672#define USDHC_PRES_STATE_SDSTB_MASK (0x8U)
45673#define USDHC_PRES_STATE_SDSTB_SHIFT (3U)
45674/*! SDSTB - SD Clock Stable
45675 * 0b1..Clock is stable.
45676 * 0b0..Clock is changing frequency and not stable.
45677 */
45678#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
45679#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U)
45680#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U)
45681/*! IPGOFF - IPG_CLK Gated Off Internally
45682 * 0b1..IPG_CLK is gated off.
45683 * 0b0..IPG_CLK is active.
45684 */
45685#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
45686#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U)
45687#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U)
45688/*! HCKOFF - HCLK Gated Off Internally
45689 * 0b1..HCLK is gated off.
45690 * 0b0..HCLK is active.
45691 */
45692#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
45693#define USDHC_PRES_STATE_PEROFF_MASK (0x40U)
45694#define USDHC_PRES_STATE_PEROFF_SHIFT (6U)
45695/*! PEROFF - IPG_PERCLK Gated Off Internally
45696 * 0b1..IPG_PERCLK is gated off.
45697 * 0b0..IPG_PERCLK is active.
45698 */
45699#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
45700#define USDHC_PRES_STATE_SDOFF_MASK (0x80U)
45701#define USDHC_PRES_STATE_SDOFF_SHIFT (7U)
45702/*! SDOFF - SD Clock Gated Off Internally
45703 * 0b1..SD Clock is gated off.
45704 * 0b0..SD Clock is active.
45705 */
45706#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
45707#define USDHC_PRES_STATE_WTA_MASK (0x100U)
45708#define USDHC_PRES_STATE_WTA_SHIFT (8U)
45709/*! WTA - Write Transfer Active
45710 * 0b1..Transferring data
45711 * 0b0..No valid data
45712 */
45713#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
45714#define USDHC_PRES_STATE_RTA_MASK (0x200U)
45715#define USDHC_PRES_STATE_RTA_SHIFT (9U)
45716/*! RTA - Read Transfer Active
45717 * 0b1..Transferring data
45718 * 0b0..No valid data
45719 */
45720#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
45721#define USDHC_PRES_STATE_BWEN_MASK (0x400U)
45722#define USDHC_PRES_STATE_BWEN_SHIFT (10U)
45723/*! BWEN - Buffer Write Enable
45724 * 0b1..Write enable
45725 * 0b0..Write disable
45726 */
45727#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
45728#define USDHC_PRES_STATE_BREN_MASK (0x800U)
45729#define USDHC_PRES_STATE_BREN_SHIFT (11U)
45730/*! BREN - Buffer Read Enable
45731 * 0b1..Read enable
45732 * 0b0..Read disable
45733 */
45734#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
45735#define USDHC_PRES_STATE_RTR_MASK (0x1000U)
45736#define USDHC_PRES_STATE_RTR_SHIFT (12U)
45737/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode)
45738 * 0b1..Sampling clock needs re-tuning
45739 * 0b0..Fixed or well tuned sampling clock
45740 */
45741#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
45742#define USDHC_PRES_STATE_TSCD_MASK (0x8000U)
45743#define USDHC_PRES_STATE_TSCD_SHIFT (15U)
45744/*! TSCD - Tape Select Change Done
45745 * 0b1..Delay cell select change is finished.
45746 * 0b0..Delay cell select change is not finished.
45747 */
45748#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
45749#define USDHC_PRES_STATE_CINST_MASK (0x10000U)
45750#define USDHC_PRES_STATE_CINST_SHIFT (16U)
45751/*! CINST - Card Inserted
45752 * 0b1..Card Inserted
45753 * 0b0..Power on Reset or No Card
45754 */
45755#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
45756#define USDHC_PRES_STATE_CDPL_MASK (0x40000U)
45757#define USDHC_PRES_STATE_CDPL_SHIFT (18U)
45758/*! CDPL - Card Detect Pin Level
45759 * 0b1..Card present (CD_B = 0)
45760 * 0b0..No card present (CD_B = 1)
45761 */
45762#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
45763#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U)
45764#define USDHC_PRES_STATE_WPSPL_SHIFT (19U)
45765/*! WPSPL - Write Protect Switch Pin Level
45766 * 0b1..Write enabled (WP = 0)
45767 * 0b0..Write protected (WP = 1)
45768 */
45769#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
45770#define USDHC_PRES_STATE_CLSL_MASK (0x800000U)
45771#define USDHC_PRES_STATE_CLSL_SHIFT (23U)
45772#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
45773#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)
45774#define USDHC_PRES_STATE_DLSL_SHIFT (24U)
45775#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
45776/*! @} */
45777
45778/*! @name PROT_CTRL - Protocol Control */
45779/*! @{ */
45780#define USDHC_PROT_CTRL_LCTL_MASK (0x1U)
45781#define USDHC_PROT_CTRL_LCTL_SHIFT (0U)
45782/*! LCTL - LED Control
45783 * 0b1..LED on
45784 * 0b0..LED off
45785 */
45786#define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)
45787#define USDHC_PROT_CTRL_DTW_MASK (0x6U)
45788#define USDHC_PROT_CTRL_DTW_SHIFT (1U)
45789/*! DTW - Data Transfer Width
45790 * 0b10..8-bit mode
45791 * 0b01..4-bit mode
45792 * 0b00..1-bit mode
45793 * 0b11..Reserved
45794 */
45795#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
45796#define USDHC_PROT_CTRL_D3CD_MASK (0x8U)
45797#define USDHC_PROT_CTRL_D3CD_SHIFT (3U)
45798/*! D3CD - DATA3 as Card Detection Pin
45799 * 0b1..DATA3 as Card Detection Pin
45800 * 0b0..DATA3 does not monitor Card Insertion
45801 */
45802#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
45803#define USDHC_PROT_CTRL_EMODE_MASK (0x30U)
45804#define USDHC_PROT_CTRL_EMODE_SHIFT (4U)
45805/*! EMODE - Endian Mode
45806 * 0b00..Big Endian Mode
45807 * 0b01..Half Word Big Endian Mode
45808 * 0b10..Little Endian Mode
45809 * 0b11..Reserved
45810 */
45811#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
45812#define USDHC_PROT_CTRL_CDTL_MASK (0x40U)
45813#define USDHC_PROT_CTRL_CDTL_SHIFT (6U)
45814/*! CDTL - Card Detect Test Level
45815 * 0b1..Card Detect Test Level is 1, card inserted
45816 * 0b0..Card Detect Test Level is 0, no card inserted
45817 */
45818#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
45819#define USDHC_PROT_CTRL_CDSS_MASK (0x80U)
45820#define USDHC_PROT_CTRL_CDSS_SHIFT (7U)
45821/*! CDSS - Card Detect Signal Selection
45822 * 0b1..Card Detection Test Level is selected (for test purpose).
45823 * 0b0..Card Detection Level is selected (for normal purpose).
45824 */
45825#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
45826#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U)
45827#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U)
45828/*! DMASEL - DMA Select
45829 * 0b00..No DMA or Simple DMA is selected
45830 * 0b01..ADMA1 is selected
45831 * 0b10..ADMA2 is selected
45832 * 0b11..reserved
45833 */
45834#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
45835#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)
45836#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)
45837/*! SABGREQ - Stop At Block Gap Request
45838 * 0b1..Stop
45839 * 0b0..Transfer
45840 */
45841#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
45842#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U)
45843#define USDHC_PROT_CTRL_CREQ_SHIFT (17U)
45844/*! CREQ - Continue Request
45845 * 0b1..Restart
45846 * 0b0..No effect
45847 */
45848#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
45849#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)
45850#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U)
45851/*! RWCTL - Read Wait Control
45852 * 0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set
45853 * 0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set
45854 */
45855#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
45856#define USDHC_PROT_CTRL_IABG_MASK (0x80000U)
45857#define USDHC_PROT_CTRL_IABG_SHIFT (19U)
45858/*! IABG - Interrupt At Block Gap
45859 * 0b1..Enabled
45860 * 0b0..Disabled
45861 */
45862#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
45863#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)
45864#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)
45865#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
45866#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)
45867#define USDHC_PROT_CTRL_WECINT_SHIFT (24U)
45868/*! WECINT - Wakeup Event Enable On Card Interrupt
45869 * 0b1..Enable
45870 * 0b0..Disable
45871 */
45872#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
45873#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)
45874#define USDHC_PROT_CTRL_WECINS_SHIFT (25U)
45875/*! WECINS - Wakeup Event Enable On SD Card Insertion
45876 * 0b1..Enable
45877 * 0b0..Disable
45878 */
45879#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
45880#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)
45881#define USDHC_PROT_CTRL_WECRM_SHIFT (26U)
45882/*! WECRM - Wakeup Event Enable On SD Card Removal
45883 * 0b1..Enable
45884 * 0b0..Disable
45885 */
45886#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
45887#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U)
45888#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U)
45889/*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
45890 * 0bxx1..Burst length is enabled for INCR
45891 * 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16
45892 * 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
45893 */
45894#define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)
45895#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)
45896#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)
45897/*! NON_EXACT_BLK_RD
45898 * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
45899 * 0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read.
45900 */
45901#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
45902/*! @} */
45903
45904/*! @name SYS_CTRL - System Control */
45905/*! @{ */
45906#define USDHC_SYS_CTRL_DVS_MASK (0xF0U)
45907#define USDHC_SYS_CTRL_DVS_SHIFT (4U)
45908/*! DVS - Divisor
45909 * 0b0000..Divide-by-1
45910 * 0b0001..Divide-by-2
45911 * 0b1110..Divide-by-15
45912 * 0b1111..Divide-by-16
45913 */
45914#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
45915#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)
45916#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)
45917#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
45918#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)
45919#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U)
45920/*! DTOCV - Data Timeout Counter Value
45921 * 0b1111..SDCLK x 2 29
45922 * 0b1110..SDCLK x 2 28
45923 * 0b0001..SDCLK x 2 15
45924 * 0b0000..SDCLK x 2 14
45925 */
45926#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
45927#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)
45928#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)
45929#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
45930#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)
45931#define USDHC_SYS_CTRL_RSTA_SHIFT (24U)
45932/*! RSTA - Software Reset For ALL
45933 * 0b1..Reset
45934 * 0b0..No Reset
45935 */
45936#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
45937#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)
45938#define USDHC_SYS_CTRL_RSTC_SHIFT (25U)
45939/*! RSTC - Software Reset For CMD Line
45940 * 0b1..Reset
45941 * 0b0..No Reset
45942 */
45943#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
45944#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)
45945#define USDHC_SYS_CTRL_RSTD_SHIFT (26U)
45946/*! RSTD - Software Reset For DATA Line
45947 * 0b1..Reset
45948 * 0b0..No Reset
45949 */
45950#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
45951#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U)
45952#define USDHC_SYS_CTRL_INITA_SHIFT (27U)
45953#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
45954#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)
45955#define USDHC_SYS_CTRL_RSTT_SHIFT (28U)
45956#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
45957/*! @} */
45958
45959/*! @name INT_STATUS - Interrupt Status */
45960/*! @{ */
45961#define USDHC_INT_STATUS_CC_MASK (0x1U)
45962#define USDHC_INT_STATUS_CC_SHIFT (0U)
45963/*! CC - Command Complete
45964 * 0b1..Command complete
45965 * 0b0..Command not complete
45966 */
45967#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
45968#define USDHC_INT_STATUS_TC_MASK (0x2U)
45969#define USDHC_INT_STATUS_TC_SHIFT (1U)
45970/*! TC - Transfer Complete
45971 * 0b1..Transfer complete
45972 * 0b0..Transfer not complete
45973 */
45974#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
45975#define USDHC_INT_STATUS_BGE_MASK (0x4U)
45976#define USDHC_INT_STATUS_BGE_SHIFT (2U)
45977/*! BGE - Block Gap Event
45978 * 0b1..Transaction stopped at block gap
45979 * 0b0..No block gap event
45980 */
45981#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
45982#define USDHC_INT_STATUS_DINT_MASK (0x8U)
45983#define USDHC_INT_STATUS_DINT_SHIFT (3U)
45984/*! DINT - DMA Interrupt
45985 * 0b1..DMA Interrupt is generated
45986 * 0b0..No DMA Interrupt
45987 */
45988#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
45989#define USDHC_INT_STATUS_BWR_MASK (0x10U)
45990#define USDHC_INT_STATUS_BWR_SHIFT (4U)
45991/*! BWR - Buffer Write Ready
45992 * 0b1..Ready to write buffer:
45993 * 0b0..Not ready to write buffer
45994 */
45995#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
45996#define USDHC_INT_STATUS_BRR_MASK (0x20U)
45997#define USDHC_INT_STATUS_BRR_SHIFT (5U)
45998/*! BRR - Buffer Read Ready
45999 * 0b1..Ready to read buffer
46000 * 0b0..Not ready to read buffer
46001 */
46002#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
46003#define USDHC_INT_STATUS_CINS_MASK (0x40U)
46004#define USDHC_INT_STATUS_CINS_SHIFT (6U)
46005/*! CINS - Card Insertion
46006 * 0b1..Card inserted
46007 * 0b0..Card state unstable or removed
46008 */
46009#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
46010#define USDHC_INT_STATUS_CRM_MASK (0x80U)
46011#define USDHC_INT_STATUS_CRM_SHIFT (7U)
46012/*! CRM - Card Removal
46013 * 0b1..Card removed
46014 * 0b0..Card state unstable or inserted
46015 */
46016#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
46017#define USDHC_INT_STATUS_CINT_MASK (0x100U)
46018#define USDHC_INT_STATUS_CINT_SHIFT (8U)
46019/*! CINT - Card Interrupt
46020 * 0b1..Generate Card Interrupt
46021 * 0b0..No Card Interrupt
46022 */
46023#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
46024#define USDHC_INT_STATUS_RTE_MASK (0x1000U)
46025#define USDHC_INT_STATUS_RTE_SHIFT (12U)
46026/*! RTE - Re-Tuning Event: (only for SD3.0 SDR104 mode)
46027 * 0b1..Re-Tuning should be performed
46028 * 0b0..Re-Tuning is not required
46029 */
46030#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
46031#define USDHC_INT_STATUS_TP_MASK (0x4000U)
46032#define USDHC_INT_STATUS_TP_SHIFT (14U)
46033#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
46034#define USDHC_INT_STATUS_CTOE_MASK (0x10000U)
46035#define USDHC_INT_STATUS_CTOE_SHIFT (16U)
46036/*! CTOE - Command Timeout Error
46037 * 0b1..Time out
46038 * 0b0..No Error
46039 */
46040#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
46041#define USDHC_INT_STATUS_CCE_MASK (0x20000U)
46042#define USDHC_INT_STATUS_CCE_SHIFT (17U)
46043/*! CCE - Command CRC Error
46044 * 0b1..CRC Error Generated.
46045 * 0b0..No Error
46046 */
46047#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
46048#define USDHC_INT_STATUS_CEBE_MASK (0x40000U)
46049#define USDHC_INT_STATUS_CEBE_SHIFT (18U)
46050/*! CEBE - Command End Bit Error
46051 * 0b1..End Bit Error Generated
46052 * 0b0..No Error
46053 */
46054#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
46055#define USDHC_INT_STATUS_CIE_MASK (0x80000U)
46056#define USDHC_INT_STATUS_CIE_SHIFT (19U)
46057/*! CIE - Command Index Error
46058 * 0b1..Error
46059 * 0b0..No Error
46060 */
46061#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
46062#define USDHC_INT_STATUS_DTOE_MASK (0x100000U)
46063#define USDHC_INT_STATUS_DTOE_SHIFT (20U)
46064/*! DTOE - Data Timeout Error
46065 * 0b1..Time out
46066 * 0b0..No Error
46067 */
46068#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
46069#define USDHC_INT_STATUS_DCE_MASK (0x200000U)
46070#define USDHC_INT_STATUS_DCE_SHIFT (21U)
46071/*! DCE - Data CRC Error
46072 * 0b1..Error
46073 * 0b0..No Error
46074 */
46075#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
46076#define USDHC_INT_STATUS_DEBE_MASK (0x400000U)
46077#define USDHC_INT_STATUS_DEBE_SHIFT (22U)
46078/*! DEBE - Data End Bit Error
46079 * 0b1..Error
46080 * 0b0..No Error
46081 */
46082#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
46083#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U)
46084#define USDHC_INT_STATUS_AC12E_SHIFT (24U)
46085/*! AC12E - Auto CMD12 Error
46086 * 0b1..Error
46087 * 0b0..No Error
46088 */
46089#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
46090#define USDHC_INT_STATUS_TNE_MASK (0x4000000U)
46091#define USDHC_INT_STATUS_TNE_SHIFT (26U)
46092#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
46093#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U)
46094#define USDHC_INT_STATUS_DMAE_SHIFT (28U)
46095/*! DMAE - DMA Error
46096 * 0b1..Error
46097 * 0b0..No Error
46098 */
46099#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
46100/*! @} */
46101
46102/*! @name INT_STATUS_EN - Interrupt Status Enable */
46103/*! @{ */
46104#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)
46105#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)
46106/*! CCSEN - Command Complete Status Enable
46107 * 0b1..Enabled
46108 * 0b0..Masked
46109 */
46110#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
46111#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)
46112#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)
46113/*! TCSEN - Transfer Complete Status Enable
46114 * 0b1..Enabled
46115 * 0b0..Masked
46116 */
46117#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
46118#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)
46119#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)
46120/*! BGESEN - Block Gap Event Status Enable
46121 * 0b1..Enabled
46122 * 0b0..Masked
46123 */
46124#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
46125#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)
46126#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)
46127/*! DINTSEN - DMA Interrupt Status Enable
46128 * 0b1..Enabled
46129 * 0b0..Masked
46130 */
46131#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
46132#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)
46133#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)
46134/*! BWRSEN - Buffer Write Ready Status Enable
46135 * 0b1..Enabled
46136 * 0b0..Masked
46137 */
46138#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
46139#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)
46140#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)
46141/*! BRRSEN - Buffer Read Ready Status Enable
46142 * 0b1..Enabled
46143 * 0b0..Masked
46144 */
46145#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
46146#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)
46147#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)
46148/*! CINSSEN - Card Insertion Status Enable
46149 * 0b1..Enabled
46150 * 0b0..Masked
46151 */
46152#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
46153#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)
46154#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)
46155/*! CRMSEN - Card Removal Status Enable
46156 * 0b1..Enabled
46157 * 0b0..Masked
46158 */
46159#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
46160#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)
46161#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)
46162/*! CINTSEN - Card Interrupt Status Enable
46163 * 0b1..Enabled
46164 * 0b0..Masked
46165 */
46166#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
46167#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)
46168#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)
46169/*! RTESEN - Re-Tuning Event Status Enable
46170 * 0b1..Enabled
46171 * 0b0..Masked
46172 */
46173#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
46174#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)
46175#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)
46176/*! TPSEN - Tuning Pass Status Enable
46177 * 0b1..Enabled
46178 * 0b0..Masked
46179 */
46180#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
46181#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)
46182#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)
46183/*! CTOESEN - Command Timeout Error Status Enable
46184 * 0b1..Enabled
46185 * 0b0..Masked
46186 */
46187#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
46188#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)
46189#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)
46190/*! CCESEN - Command CRC Error Status Enable
46191 * 0b1..Enabled
46192 * 0b0..Masked
46193 */
46194#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
46195#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)
46196#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)
46197/*! CEBESEN - Command End Bit Error Status Enable
46198 * 0b1..Enabled
46199 * 0b0..Masked
46200 */
46201#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
46202#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)
46203#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)
46204/*! CIESEN - Command Index Error Status Enable
46205 * 0b1..Enabled
46206 * 0b0..Masked
46207 */
46208#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
46209#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)
46210#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)
46211/*! DTOESEN - Data Timeout Error Status Enable
46212 * 0b1..Enabled
46213 * 0b0..Masked
46214 */
46215#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
46216#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)
46217#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)
46218/*! DCESEN - Data CRC Error Status Enable
46219 * 0b1..Enabled
46220 * 0b0..Masked
46221 */
46222#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
46223#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)
46224#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)
46225/*! DEBESEN - Data End Bit Error Status Enable
46226 * 0b1..Enabled
46227 * 0b0..Masked
46228 */
46229#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
46230#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)
46231#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)
46232/*! AC12ESEN - Auto CMD12 Error Status Enable
46233 * 0b1..Enabled
46234 * 0b0..Masked
46235 */
46236#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
46237#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)
46238#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)
46239/*! TNESEN - Tuning Error Status Enable
46240 * 0b1..Enabled
46241 * 0b0..Masked
46242 */
46243#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
46244#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)
46245#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)
46246/*! DMAESEN - DMA Error Status Enable
46247 * 0b1..Enabled
46248 * 0b0..Masked
46249 */
46250#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
46251/*! @} */
46252
46253/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
46254/*! @{ */
46255#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)
46256#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)
46257/*! CCIEN - Command Complete Interrupt Enable
46258 * 0b1..Enabled
46259 * 0b0..Masked
46260 */
46261#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
46262#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)
46263#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)
46264/*! TCIEN - Transfer Complete Interrupt Enable
46265 * 0b1..Enabled
46266 * 0b0..Masked
46267 */
46268#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
46269#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)
46270#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)
46271/*! BGEIEN - Block Gap Event Interrupt Enable
46272 * 0b1..Enabled
46273 * 0b0..Masked
46274 */
46275#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
46276#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)
46277#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)
46278/*! DINTIEN - DMA Interrupt Enable
46279 * 0b1..Enabled
46280 * 0b0..Masked
46281 */
46282#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
46283#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)
46284#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)
46285/*! BWRIEN - Buffer Write Ready Interrupt Enable
46286 * 0b1..Enabled
46287 * 0b0..Masked
46288 */
46289#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
46290#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)
46291#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)
46292/*! BRRIEN - Buffer Read Ready Interrupt Enable
46293 * 0b1..Enabled
46294 * 0b0..Masked
46295 */
46296#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
46297#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)
46298#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)
46299/*! CINSIEN - Card Insertion Interrupt Enable
46300 * 0b1..Enabled
46301 * 0b0..Masked
46302 */
46303#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
46304#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)
46305#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)
46306/*! CRMIEN - Card Removal Interrupt Enable
46307 * 0b1..Enabled
46308 * 0b0..Masked
46309 */
46310#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
46311#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)
46312#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)
46313/*! CINTIEN - Card Interrupt Interrupt Enable
46314 * 0b1..Enabled
46315 * 0b0..Masked
46316 */
46317#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
46318#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)
46319#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)
46320/*! RTEIEN - Re-Tuning Event Interrupt Enable
46321 * 0b1..Enabled
46322 * 0b0..Masked
46323 */
46324#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
46325#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)
46326#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)
46327/*! TPIEN - Tuning Pass Interrupt Enable
46328 * 0b1..Enabled
46329 * 0b0..Masked
46330 */
46331#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
46332#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)
46333#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)
46334/*! CTOEIEN - Command Timeout Error Interrupt Enable
46335 * 0b1..Enabled
46336 * 0b0..Masked
46337 */
46338#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
46339#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)
46340#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)
46341/*! CCEIEN - Command CRC Error Interrupt Enable
46342 * 0b1..Enabled
46343 * 0b0..Masked
46344 */
46345#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
46346#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)
46347#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)
46348/*! CEBEIEN - Command End Bit Error Interrupt Enable
46349 * 0b1..Enabled
46350 * 0b0..Masked
46351 */
46352#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
46353#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)
46354#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)
46355/*! CIEIEN - Command Index Error Interrupt Enable
46356 * 0b1..Enabled
46357 * 0b0..Masked
46358 */
46359#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
46360#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)
46361#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)
46362/*! DTOEIEN - Data Timeout Error Interrupt Enable
46363 * 0b1..Enabled
46364 * 0b0..Masked
46365 */
46366#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
46367#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)
46368#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)
46369/*! DCEIEN - Data CRC Error Interrupt Enable
46370 * 0b1..Enabled
46371 * 0b0..Masked
46372 */
46373#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
46374#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)
46375#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)
46376/*! DEBEIEN - Data End Bit Error Interrupt Enable
46377 * 0b1..Enabled
46378 * 0b0..Masked
46379 */
46380#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
46381#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)
46382#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)
46383/*! AC12EIEN - Auto CMD12 Error Interrupt Enable
46384 * 0b1..Enabled
46385 * 0b0..Masked
46386 */
46387#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
46388#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)
46389#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)
46390/*! TNEIEN - Tuning Error Interrupt Enable
46391 * 0b1..Enabled
46392 * 0b0..Masked
46393 */
46394#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
46395#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)
46396#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)
46397/*! DMAEIEN - DMA Error Interrupt Enable
46398 * 0b1..Enable
46399 * 0b0..Masked
46400 */
46401#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
46402/*! @} */
46403
46404/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
46405/*! @{ */
46406#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)
46407#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)
46408/*! AC12NE - Auto CMD12 Not Executed
46409 * 0b1..Not executed
46410 * 0b0..Executed
46411 */
46412#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
46413#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)
46414#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
46415/*! AC12TOE - Auto CMD12 / 23 Timeout Error
46416 * 0b1..Time out
46417 * 0b0..No error
46418 */
46419#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
46420#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)
46421#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
46422/*! AC12EBE - Auto CMD12 / 23 End Bit Error
46423 * 0b1..End Bit Error Generated
46424 * 0b0..No error
46425 */
46426#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
46427#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)
46428#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)
46429/*! AC12CE - Auto CMD12 / 23 CRC Error
46430 * 0b1..CRC Error Met in Auto CMD12/23 Response
46431 * 0b0..No CRC error
46432 */
46433#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
46434#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)
46435#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)
46436/*! AC12IE - Auto CMD12 / 23 Index Error
46437 * 0b1..Error, the CMD index in response is not CMD12/23
46438 * 0b0..No error
46439 */
46440#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
46441#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
46442#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
46443/*! CNIBAC12E - Command Not Issued By Auto CMD12 Error
46444 * 0b1..Not Issued
46445 * 0b0..No error
46446 */
46447#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
46448#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
46449#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
46450#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
46451#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
46452#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
46453/*! SMP_CLK_SEL - Sample Clock Select
46454 * 0b1..Tuned clock is used to sample data
46455 * 0b0..Fixed clock is used to sample data
46456 */
46457#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
46458/*! @} */
46459
46460/*! @name HOST_CTRL_CAP - Host Controller Capabilities */
46461/*! @{ */
46462#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)
46463#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)
46464#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
46465#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)
46466#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
46467#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
46468#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)
46469#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)
46470#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
46471#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)
46472#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)
46473#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)
46474#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
46475#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
46476/*! USE_TUNING_SDR50 - Use Tuning for SDR50
46477 * 0b1..SDR50 requires tuning
46478 * 0b0..SDR does not require tuning
46479 */
46480#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
46481#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U)
46482#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U)
46483/*! RETUNING_MODE - Retuning Mode
46484 * 0b00..Mode 1
46485 * 0b01..Mode 2
46486 * 0b10..Mode 3
46487 * 0b11..Reserved
46488 */
46489#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)
46490#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)
46491#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)
46492/*! MBL - Max Block Length
46493 * 0b000..512 bytes
46494 * 0b001..1024 bytes
46495 * 0b010..2048 bytes
46496 * 0b011..4096 bytes
46497 */
46498#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
46499#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)
46500#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)
46501/*! ADMAS - ADMA Support
46502 * 0b1..Advanced DMA Supported
46503 * 0b0..Advanced DMA Not supported
46504 */
46505#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
46506#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)
46507#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)
46508/*! HSS - High Speed Support
46509 * 0b1..High Speed Supported
46510 * 0b0..High Speed Not Supported
46511 */
46512#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
46513#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)
46514#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)
46515/*! DMAS - DMA Support
46516 * 0b1..DMA Supported
46517 * 0b0..DMA not supported
46518 */
46519#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
46520#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)
46521#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)
46522/*! SRS - Suspend / Resume Support
46523 * 0b1..Supported
46524 * 0b0..Not supported
46525 */
46526#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
46527#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)
46528#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)
46529/*! VS33 - Voltage Support 3.3V
46530 * 0b1..3.3V supported
46531 * 0b0..3.3V not supported
46532 */
46533#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
46534#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)
46535#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)
46536/*! VS30 - Voltage Support 3.0 V
46537 * 0b1..3.0V supported
46538 * 0b0..3.0V not supported
46539 */
46540#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
46541#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)
46542#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)
46543/*! VS18 - Voltage Support 1.8 V
46544 * 0b1..1.8V supported
46545 * 0b0..1.8V not supported
46546 */
46547#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
46548/*! @} */
46549
46550/*! @name WTMK_LVL - Watermark Level */
46551/*! @{ */
46552#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)
46553#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U)
46554#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
46555#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U)
46556#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U)
46557#define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)
46558#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)
46559#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U)
46560#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
46561#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U)
46562#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U)
46563#define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)
46564/*! @} */
46565
46566/*! @name MIX_CTRL - Mixer Control */
46567/*! @{ */
46568#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U)
46569#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U)
46570/*! DMAEN - DMA Enable
46571 * 0b1..Enable
46572 * 0b0..Disable
46573 */
46574#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
46575#define USDHC_MIX_CTRL_BCEN_MASK (0x2U)
46576#define USDHC_MIX_CTRL_BCEN_SHIFT (1U)
46577/*! BCEN - Block Count Enable
46578 * 0b1..Enable
46579 * 0b0..Disable
46580 */
46581#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
46582#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U)
46583#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U)
46584/*! AC12EN - Auto CMD12 Enable
46585 * 0b1..Enable
46586 * 0b0..Disable
46587 */
46588#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
46589#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)
46590#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)
46591#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
46592#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)
46593#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)
46594/*! DTDSEL - Data Transfer Direction Select
46595 * 0b1..Read (Card to Host)
46596 * 0b0..Write (Host to Card)
46597 */
46598#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
46599#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)
46600#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)
46601/*! MSBSEL - Multi / Single Block Select
46602 * 0b1..Multiple Blocks
46603 * 0b0..Single Block
46604 */
46605#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
46606#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)
46607#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)
46608#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
46609#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U)
46610#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U)
46611#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
46612#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)
46613#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)
46614/*! EXE_TUNE - Execute Tuning: (Only used for SD3.0, SDR104 mode)
46615 * 0b1..Execute Tuning
46616 * 0b0..Not Tuned or Tuning Completed
46617 */
46618#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
46619#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)
46620#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)
46621/*! SMP_CLK_SEL
46622 * 0b1..Tuned clock is used to sample data / cmd
46623 * 0b0..Fixed clock is used to sample data / cmd
46624 */
46625#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
46626#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)
46627#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)
46628/*! AUTO_TUNE_EN - Auto Tuning Enable (Only used for SD3.0, SDR104 mode)
46629 * 0b1..Enable auto tuning
46630 * 0b0..Disable auto tuning
46631 */
46632#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
46633#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)
46634#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)
46635/*! FBCLK_SEL - Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode)
46636 * 0b1..Feedback clock comes from the ipp_card_clk_out
46637 * 0b0..Feedback clock comes from the loopback CLK
46638 */
46639#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
46640#define USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U)
46641#define USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U)
46642#define USDHC_MIX_CTRL_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)
46643/*! @} */
46644
46645/*! @name FORCE_EVENT - Force Event */
46646/*! @{ */
46647#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)
46648#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)
46649#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
46650#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)
46651#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)
46652#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
46653#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)
46654#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)
46655#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
46656#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)
46657#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)
46658#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
46659#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)
46660#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)
46661#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
46662#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)
46663#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)
46664#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
46665#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)
46666#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)
46667#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
46668#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)
46669#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)
46670#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
46671#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)
46672#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)
46673#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
46674#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)
46675#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)
46676#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
46677#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)
46678#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)
46679#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
46680#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)
46681#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)
46682#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
46683#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)
46684#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)
46685#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
46686#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)
46687#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)
46688#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
46689#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)
46690#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)
46691#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
46692#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)
46693#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)
46694#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
46695#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)
46696#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)
46697#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
46698/*! @} */
46699
46700/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */
46701/*! @{ */
46702#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)
46703#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)
46704#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
46705#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)
46706#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)
46707/*! ADMALME - ADMA Length Mismatch Error
46708 * 0b1..Error
46709 * 0b0..No Error
46710 */
46711#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
46712#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)
46713#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)
46714/*! ADMADCE - ADMA Descritor Error
46715 * 0b1..Error
46716 * 0b0..No Error
46717 */
46718#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
46719/*! @} */
46720
46721/*! @name ADMA_SYS_ADDR - ADMA System Address */
46722/*! @{ */
46723#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)
46724#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)
46725#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
46726/*! @} */
46727
46728/*! @name DLL_CTRL - DLL (Delay Line) Control */
46729/*! @{ */
46730#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)
46731#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)
46732#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
46733#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)
46734#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)
46735#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
46736#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
46737#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
46738#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
46739#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
46740#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
46741#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
46742#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
46743#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
46744#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
46745#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
46746#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
46747#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
46748#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
46749#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
46750#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
46751#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
46752#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
46753#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
46754#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
46755#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
46756#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
46757#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
46758#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
46759#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
46760/*! @} */
46761
46762/*! @name DLL_STATUS - DLL Status */
46763/*! @{ */
46764#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)
46765#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)
46766#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
46767#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)
46768#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)
46769#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
46770#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)
46771#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)
46772#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
46773#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)
46774#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)
46775#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
46776/*! @} */
46777
46778/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
46779/*! @{ */
46780#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
46781#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
46782#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
46783#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
46784#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
46785#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
46786#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
46787#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
46788#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
46789#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)
46790#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
46791#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
46792#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
46793#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
46794#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
46795#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
46796#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
46797#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
46798#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
46799#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
46800#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
46801#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)
46802#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
46803#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
46804/*! @} */
46805
46806/*! @name STROBE_DLL_CTRL - Strobe DLL Control */
46807/*! @{ */
46808#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U)
46809#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U)
46810#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)
46811#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U)
46812#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U)
46813#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)
46814#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
46815#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
46816#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)
46817#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x38U)
46818#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
46819#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)
46820#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK (0x40U)
46821#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT (6U)
46822#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK)
46823#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK (0x80U)
46824#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT (7U)
46825#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK)
46826#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
46827#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
46828#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)
46829#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
46830#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
46831#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
46832#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
46833#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
46834#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)
46835#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
46836#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
46837#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)
46838/*! @} */
46839
46840/*! @name STROBE_DLL_STATUS - Strobe DLL Status */
46841/*! @{ */
46842#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U)
46843#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U)
46844#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)
46845#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U)
46846#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U)
46847#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)
46848#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU)
46849#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U)
46850#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)
46851#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U)
46852#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U)
46853#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)
46854/*! @} */
46855
46856/*! @name VEND_SPEC - Vendor Specific Register */
46857/*! @{ */
46858#define USDHC_VEND_SPEC_EXT_DMA_EN_MASK (0x1U)
46859#define USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT (0U)
46860/*! EXT_DMA_EN - External DMA Request Enable
46861 * 0b0..In any scenario, uSDHC does not send out external DMA request.
46862 * 0b1..When internal DMA is not active, the external DMA request will be sent out.
46863 */
46864#define USDHC_VEND_SPEC_EXT_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT)) & USDHC_VEND_SPEC_EXT_DMA_EN_MASK)
46865#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U)
46866#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U)
46867/*! VSELECT - Voltage Selection
46868 * 0b1..Change the voltage to low voltage range, around 1.8 V
46869 * 0b0..Change the voltage to high voltage range, around 3.0 V
46870 */
46871#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
46872#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)
46873#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)
46874/*! CONFLICT_CHK_EN - Conflict check enable.
46875 * 0b0..Conflict check disable
46876 * 0b1..Conflict check enable
46877 */
46878#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
46879#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)
46880#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
46881/*! AC12_WR_CHKBUSY_EN
46882 * 0b0..Do not check busy after auto CMD12 for write data packet
46883 * 0b1..Check busy after auto CMD12 for write data packet
46884 */
46885#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
46886#define USDHC_VEND_SPEC_DAT3_CD_POL_MASK (0x10U)
46887#define USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT (4U)
46888/*! DAT3_CD_POL
46889 * 0b0..Card detected when DATA3 is high.
46890 * 0b1..Card detected when DATA3 is low.
46891 */
46892#define USDHC_VEND_SPEC_DAT3_CD_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT)) & USDHC_VEND_SPEC_DAT3_CD_POL_MASK)
46893#define USDHC_VEND_SPEC_CD_POL_MASK (0x20U)
46894#define USDHC_VEND_SPEC_CD_POL_SHIFT (5U)
46895/*! CD_POL
46896 * 0b0..CD_B pin is low active.
46897 * 0b1..CD_B pin is high active.
46898 */
46899#define USDHC_VEND_SPEC_CD_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CD_POL_SHIFT)) & USDHC_VEND_SPEC_CD_POL_MASK)
46900#define USDHC_VEND_SPEC_WP_POL_MASK (0x40U)
46901#define USDHC_VEND_SPEC_WP_POL_SHIFT (6U)
46902/*! WP_POL
46903 * 0b0..WP pin is high active.
46904 * 0b1..WP pin is low active.
46905 */
46906#define USDHC_VEND_SPEC_WP_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_WP_POL_SHIFT)) & USDHC_VEND_SPEC_WP_POL_MASK)
46907#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK (0x80U)
46908#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT (7U)
46909/*! CLKONJ_IN_ABORT
46910 * 0b0..The CLK output is active when sending abort command while data is transmitting even if the internal FIFO is full (for read) or empty (for write).
46911 * 0b1..The CLK output is inactive when sending abort command while data is transmitting if the internal FIFO is full (for read) or empty (for write).
46912 */
46913#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT)) & USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK)
46914#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)
46915#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)
46916/*! FRC_SDCLK_ON
46917 * 0b0..CLK active or inactive is fully controlled by the hardware.
46918 * 0b1..Force CLK active.
46919 */
46920#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
46921#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK (0x800U)
46922#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT (11U)
46923/*! IPG_CLK_SOFT_EN - IPG_CLK Software Enable
46924 * 0b0..Gate off the IPG_CLK
46925 * 0b1..Enable the IPG_CLK
46926 */
46927#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK)
46928#define USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK (0x1000U)
46929#define USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT (12U)
46930/*! HCLK_SOFT_EN - AHB Clock Software Enable
46931 * 0b0..Gate off the AHB clock.
46932 * 0b1..Enable the AHB clock.
46933 */
46934#define USDHC_VEND_SPEC_HCLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK)
46935#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK (0x2000U)
46936#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT (13U)
46937/*! IPG_PERCLK_SOFT_EN - IPG_PERCLK Software Enable
46938 * 0b0..Gate off the IPG_PERCLK
46939 * 0b1..Enable the IPG_PERCLK
46940 */
46941#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK)
46942#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK (0x4000U)
46943#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT (14U)
46944/*! CARD_CLK_SOFT_EN - Card Clock Software Enable
46945 * 0b0..Gate off the sd_clk
46946 * 0b1..Enable the sd_clk
46947 */
46948#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK)
46949#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)
46950#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)
46951/*! CRC_CHK_DIS - CRC Check Disable
46952 * 0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet
46953 * 0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet
46954 */
46955#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
46956#define USDHC_VEND_SPEC_INT_ST_VAL_MASK (0xFF0000U)
46957#define USDHC_VEND_SPEC_INT_ST_VAL_SHIFT (16U)
46958#define USDHC_VEND_SPEC_INT_ST_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_INT_ST_VAL_SHIFT)) & USDHC_VEND_SPEC_INT_ST_VAL_MASK)
46959#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)
46960#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)
46961/*! CMD_BYTE_EN
46962 * 0b0..Disable
46963 * 0b1..Enable
46964 */
46965#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
46966/*! @} */
46967
46968/*! @name MMC_BOOT - MMC Boot Register */
46969/*! @{ */
46970#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)
46971#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)
46972/*! DTOCV_ACK
46973 * 0b0000..SDCLK x 2^13
46974 * 0b0001..SDCLK x 2^14
46975 * 0b0010..SDCLK x 2^15
46976 * 0b0011..SDCLK x 2^16
46977 * 0b0100..SDCLK x 2^17
46978 * 0b0101..SDCLK x 2^18
46979 * 0b0110..SDCLK x 2^19
46980 * 0b0111..SDCLK x 2^20
46981 * 0b1110..SDCLK x 2^27
46982 * 0b1111..SDCLK x 2^28
46983 */
46984#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
46985#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)
46986#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)
46987/*! BOOT_ACK
46988 * 0b0..No ack
46989 * 0b1..Ack
46990 */
46991#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
46992#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)
46993#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)
46994/*! BOOT_MODE
46995 * 0b0..Normal boot
46996 * 0b1..Alternative boot
46997 */
46998#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
46999#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)
47000#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)
47001/*! BOOT_EN
47002 * 0b0..Fast boot disable
47003 * 0b1..Fast boot enable
47004 */
47005#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
47006#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)
47007#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)
47008#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
47009#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)
47010#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)
47011/*! DISABLE_TIME_OUT - Disable Time Out
47012 * 0b0..Enable time out
47013 * 0b1..Disable time out
47014 */
47015#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
47016#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)
47017#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)
47018#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
47019/*! @} */
47020
47021/*! @name VEND_SPEC2 - Vendor Specific 2 Register */
47022/*! @{ */
47023#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK (0x1U)
47024#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT (0U)
47025/*! SDR104_TIMING_DIS
47026 * 0b0..The timeout counter for Ncr changes to 80, Ncrc changes to 21.
47027 * 0b1..The timeout counter for Ncr changes to 72, Ncrc changes to 15.
47028 */
47029#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK)
47030#define USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK (0x2U)
47031#define USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT (1U)
47032/*! SDR104_OE_DIS
47033 * 0b0..Drive the CMD_OE / DATA_OE for one more clock cycle after the end bit.
47034 * 0b1..Stop to drive the CMD_OE / DATA_OE at once after driving the end bit.
47035 */
47036#define USDHC_VEND_SPEC2_SDR104_OE_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK)
47037#define USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK (0x4U)
47038#define USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT (2U)
47039/*! SDR104_NSD_DIS
47040 * 0b0..Enable the interrupt window 9 cycles later after the end of the I/O abort command (or CMD12) is sent.
47041 * 0b1..Enable the interrupt window 5 cycles later after the end of the I/O abort command (or CMD12) is sent.
47042 */
47043#define USDHC_VEND_SPEC2_SDR104_NSD_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK)
47044#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)
47045#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)
47046/*! CARD_INT_D3_TEST - Card Interrupt Detection Test
47047 * 0b0..Check the card interrupt only when DATA3 is high.
47048 * 0b1..Check the card interrupt by ignoring the status of DATA3.
47049 */
47050#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
47051#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)
47052#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)
47053/*! TUNING_8bit_EN
47054 * 0b0..Tuning circuit only checks the DATA[3:0].
47055 * 0b1..Tuning circuit only checks the DATA0.
47056 */
47057#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
47058#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)
47059#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)
47060#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
47061#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)
47062#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)
47063/*! TUNING_CMD_EN
47064 * 0b0..Auto tuning circuit does not check the CMD line.
47065 * 0b1..Auto tuning circuit checks the CMD line.
47066 */
47067#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
47068#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK (0x80U)
47069#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT (7U)
47070/*! CARD_INT_AUTO_CLR_DIS
47071 * 0b0..Card interrupt status bit (CINT) can be cleared when Card Interrupt status enable bit is 0.
47072 * 0b1..Card interrupt status bit (CINT) can only be cleared by writting a 1 to CINT bit.
47073 */
47074#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK)
47075#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U)
47076#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U)
47077#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)
47078#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U)
47079#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U)
47080#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)
47081/*! @} */
47082
47083/*! @name TUNING_CTRL - Tuning Control Register */
47084/*! @{ */
47085#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU)
47086#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
47087#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
47088#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)
47089#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)
47090#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
47091#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)
47092#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)
47093#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
47094#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)
47095#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)
47096#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
47097#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)
47098#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)
47099#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
47100/*! @} */
47101
47102
47103/*!
47104 * @}
47105 */ /* end of group USDHC_Register_Masks */
47106
47107
47108/* USDHC - Peripheral instance base addresses */
47109/** Peripheral uSDHC1 base address */
47110#define uSDHC1_BASE (0x30B40000u)
47111/** Peripheral uSDHC1 base pointer */
47112#define uSDHC1 ((USDHC_Type *)uSDHC1_BASE)
47113/** Peripheral uSDHC2 base address */
47114#define uSDHC2_BASE (0x30B50000u)
47115/** Peripheral uSDHC2 base pointer */
47116#define uSDHC2 ((USDHC_Type *)uSDHC2_BASE)
47117/** Array initializer of USDHC peripheral base addresses */
47118#define USDHC_BASE_ADDRS { 0u, uSDHC1_BASE, uSDHC2_BASE }
47119/** Array initializer of USDHC peripheral base pointers */
47120#define USDHC_BASE_PTRS { (USDHC_Type *)0u, uSDHC1, uSDHC2 }
47121/** Interrupt vectors for the USDHC peripheral type */
47122#define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }
47123
47124/*!
47125 * @}
47126 */ /* end of group USDHC_Peripheral_Access_Layer */
47127
47128
47129/* ----------------------------------------------------------------------------
47130 -- WDOG Peripheral Access Layer
47131 ---------------------------------------------------------------------------- */
47132
47133/*!
47134 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
47135 * @{
47136 */
47137
47138/** WDOG - Register Layout Typedef */
47139typedef struct {
47140 __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */
47141 __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */
47142 __I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */
47143 __IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */
47144 __IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */
47145} WDOG_Type;
47146
47147/* ----------------------------------------------------------------------------
47148 -- WDOG Register Masks
47149 ---------------------------------------------------------------------------- */
47150
47151/*!
47152 * @addtogroup WDOG_Register_Masks WDOG Register Masks
47153 * @{
47154 */
47155
47156/*! @name WCR - Watchdog Control Register */
47157/*! @{ */
47158#define WDOG_WCR_WDZST_MASK (0x1U)
47159#define WDOG_WCR_WDZST_SHIFT (0U)
47160/*! WDZST
47161 * 0b0..Continue timer operation (Default).
47162 * 0b1..Suspend the watchdog timer.
47163 */
47164#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
47165#define WDOG_WCR_WDBG_MASK (0x2U)
47166#define WDOG_WCR_WDBG_SHIFT (1U)
47167/*! WDBG
47168 * 0b0..Continue WDOG timer operation (Default).
47169 * 0b1..Suspend the watchdog timer.
47170 */
47171#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
47172#define WDOG_WCR_WDE_MASK (0x4U)
47173#define WDOG_WCR_WDE_SHIFT (2U)
47174/*! WDE
47175 * 0b0..Disable the Watchdog (Default).
47176 * 0b1..Enable the Watchdog.
47177 */
47178#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
47179#define WDOG_WCR_WDT_MASK (0x8U)
47180#define WDOG_WCR_WDT_SHIFT (3U)
47181/*! WDT
47182 * 0b0..No effect on WDOG_B (Default).
47183 * 0b1..Assert WDOG_B upon a Watchdog Time-out event.
47184 */
47185#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
47186#define WDOG_WCR_SRS_MASK (0x10U)
47187#define WDOG_WCR_SRS_SHIFT (4U)
47188/*! SRS
47189 * 0b0..Assert system reset signal.
47190 * 0b1..No effect on the system (Default).
47191 */
47192#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
47193#define WDOG_WCR_WDA_MASK (0x20U)
47194#define WDOG_WCR_WDA_SHIFT (5U)
47195/*! WDA
47196 * 0b0..Assert WDOG_B output.
47197 * 0b1..No effect on system (Default).
47198 */
47199#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
47200#define WDOG_WCR_SRE_MASK (0x40U)
47201#define WDOG_WCR_SRE_SHIFT (6U)
47202/*! SRE - Software Reset Extension. Required to be set to 1 when used in conjunction with the Software Reset Signal (SRS).
47203 * 0b0..Reserved
47204 * 0b1..This bit must be set to 1.
47205 */
47206#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
47207#define WDOG_WCR_WDW_MASK (0x80U)
47208#define WDOG_WCR_WDW_SHIFT (7U)
47209/*! WDW
47210 * 0b0..Continue WDOG timer operation (Default).
47211 * 0b1..Suspend WDOG timer operation.
47212 */
47213#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
47214#define WDOG_WCR_WT_MASK (0xFF00U)
47215#define WDOG_WCR_WT_SHIFT (8U)
47216/*! WT
47217 * 0b00000000..- 0.5 Seconds (Default).
47218 * 0b00000001..- 1.0 Seconds.
47219 * 0b00000010..- 1.5 Seconds.
47220 * 0b00000011..- 2.0 Seconds.
47221 * 0b11111111..- 128 Seconds.
47222 */
47223#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
47224/*! @} */
47225
47226/*! @name WSR - Watchdog Service Register */
47227/*! @{ */
47228#define WDOG_WSR_WSR_MASK (0xFFFFU)
47229#define WDOG_WSR_WSR_SHIFT (0U)
47230/*! WSR
47231 * 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR).
47232 * 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR).
47233 */
47234#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
47235/*! @} */
47236
47237/*! @name WRSR - Watchdog Reset Status Register */
47238/*! @{ */
47239#define WDOG_WRSR_SFTW_MASK (0x1U)
47240#define WDOG_WRSR_SFTW_SHIFT (0U)
47241/*! SFTW
47242 * 0b0..Reset is not the result of a software reset.
47243 * 0b1..Reset is the result of a software reset.
47244 */
47245#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
47246#define WDOG_WRSR_TOUT_MASK (0x2U)
47247#define WDOG_WRSR_TOUT_SHIFT (1U)
47248/*! TOUT
47249 * 0b0..Reset is not the result of a WDOG timeout.
47250 * 0b1..Reset is the result of a WDOG timeout.
47251 */
47252#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
47253#define WDOG_WRSR_POR_MASK (0x10U)
47254#define WDOG_WRSR_POR_SHIFT (4U)
47255/*! POR
47256 * 0b0..Reset is not the result of a power on reset.
47257 * 0b1..Reset is the result of a power on reset.
47258 */
47259#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
47260/*! @} */
47261
47262/*! @name WICR - Watchdog Interrupt Control Register */
47263/*! @{ */
47264#define WDOG_WICR_WICT_MASK (0xFFU)
47265#define WDOG_WICR_WICT_SHIFT (0U)
47266/*! WICT
47267 * 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds.
47268 * 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds.
47269 * 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default).
47270 * 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
47271 */
47272#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
47273#define WDOG_WICR_WTIS_MASK (0x4000U)
47274#define WDOG_WICR_WTIS_SHIFT (14U)
47275/*! WTIS
47276 * 0b0..No interrupt has occurred (Default).
47277 * 0b1..Interrupt has occurred
47278 */
47279#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
47280#define WDOG_WICR_WIE_MASK (0x8000U)
47281#define WDOG_WICR_WIE_SHIFT (15U)
47282/*! WIE
47283 * 0b0..Disable Interrupt (Default).
47284 * 0b1..Enable Interrupt.
47285 */
47286#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
47287/*! @} */
47288
47289/*! @name WMCR - Watchdog Miscellaneous Control Register */
47290/*! @{ */
47291#define WDOG_WMCR_PDE_MASK (0x1U)
47292#define WDOG_WMCR_PDE_SHIFT (0U)
47293/*! PDE
47294 * 0b0..Power Down Counter of WDOG is disabled.
47295 * 0b1..Power Down Counter of WDOG is enabled (Default).
47296 */
47297#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)
47298/*! @} */
47299
47300
47301/*!
47302 * @}
47303 */ /* end of group WDOG_Register_Masks */
47304
47305
47306/* WDOG - Peripheral instance base addresses */
47307/** Peripheral WDOG1 base address */
47308#define WDOG1_BASE (0x30280000u)
47309/** Peripheral WDOG1 base pointer */
47310#define WDOG1 ((WDOG_Type *)WDOG1_BASE)
47311/** Peripheral WDOG2 base address */
47312#define WDOG2_BASE (0x30290000u)
47313/** Peripheral WDOG2 base pointer */
47314#define WDOG2 ((WDOG_Type *)WDOG2_BASE)
47315/** Peripheral WDOG3 base address */
47316#define WDOG3_BASE (0x302A0000u)
47317/** Peripheral WDOG3 base pointer */
47318#define WDOG3 ((WDOG_Type *)WDOG3_BASE)
47319/** Array initializer of WDOG peripheral base addresses */
47320#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE, WDOG3_BASE }
47321/** Array initializer of WDOG peripheral base pointers */
47322#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2, WDOG3 }
47323/** Interrupt vectors for the WDOG peripheral type */
47324#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn, WDOG3_IRQn }
47325
47326/*!
47327 * @}
47328 */ /* end of group WDOG_Peripheral_Access_Layer */
47329
47330
47331/* ----------------------------------------------------------------------------
47332 -- WR_SCL Peripheral Access Layer
47333 ---------------------------------------------------------------------------- */
47334
47335/*!
47336 * @addtogroup WR_SCL_Peripheral_Access_Layer WR_SCL Peripheral Access Layer
47337 * @{
47338 */
47339
47340/** WR_SCL - Register Layout Typedef */
47341typedef struct {
47342 struct { /* offset: 0x0 */
47343 __IO uint32_t RW; /**< Control register for Context Loader., offset: 0x0 */
47344 __IO uint32_t SET; /**< Control register for Context Loader., offset: 0x4 */
47345 __IO uint32_t CLR; /**< Control register for Context Loader., offset: 0x8 */
47346 __IO uint32_t TOG; /**< Control register for Context Loader., offset: 0xC */
47347 } CTRL_STATUS;
47348 __IO uint32_t BASE_ADDR; /**< Holds the base address, offset: 0x10 */
47349 __IO uint32_t PITCH; /**< Pitch, offset: 0x14 */
47350} WR_SCL_Type;
47351
47352/* ----------------------------------------------------------------------------
47353 -- WR_SCL Register Masks
47354 ---------------------------------------------------------------------------- */
47355
47356/*!
47357 * @addtogroup WR_SCL_Register_Masks WR_SCL Register Masks
47358 * @{
47359 */
47360
47361/*! @name CTRL_STATUS - Control register for Context Loader. */
47362/*! @{ */
47363#define WR_SCL_CTRL_STATUS_ENABLE_MASK (0x1U)
47364#define WR_SCL_CTRL_STATUS_ENABLE_SHIFT (0U)
47365#define WR_SCL_CTRL_STATUS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_ENABLE_SHIFT)) & WR_SCL_CTRL_STATUS_ENABLE_MASK)
47366#define WR_SCL_CTRL_STATUS_REPEAT_MASK (0x2U)
47367#define WR_SCL_CTRL_STATUS_REPEAT_SHIFT (1U)
47368#define WR_SCL_CTRL_STATUS_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_REPEAT_SHIFT)) & WR_SCL_CTRL_STATUS_REPEAT_MASK)
47369#define WR_SCL_CTRL_STATUS_BPP_MASK (0x1CU)
47370#define WR_SCL_CTRL_STATUS_BPP_SHIFT (2U)
47371#define WR_SCL_CTRL_STATUS_BPP(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_BPP_SHIFT)) & WR_SCL_CTRL_STATUS_BPP_MASK)
47372#define WR_SCL_CTRL_STATUS_T_SIZE_MASK (0x60U)
47373#define WR_SCL_CTRL_STATUS_T_SIZE_SHIFT (5U)
47374#define WR_SCL_CTRL_STATUS_T_SIZE(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_T_SIZE_SHIFT)) & WR_SCL_CTRL_STATUS_T_SIZE_MASK)
47375#define WR_SCL_CTRL_STATUS_P_SIZE_MASK (0x380U)
47376#define WR_SCL_CTRL_STATUS_P_SIZE_SHIFT (7U)
47377#define WR_SCL_CTRL_STATUS_P_SIZE(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_P_SIZE_SHIFT)) & WR_SCL_CTRL_STATUS_P_SIZE_MASK)
47378#define WR_SCL_CTRL_STATUS_P_FREQ_MASK (0x3FC00U)
47379#define WR_SCL_CTRL_STATUS_P_FREQ_SHIFT (10U)
47380#define WR_SCL_CTRL_STATUS_P_FREQ(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_P_FREQ_SHIFT)) & WR_SCL_CTRL_STATUS_P_FREQ_MASK)
47381#define WR_SCL_CTRL_STATUS_FIFO_SIZE_MASK (0x1FC0000U)
47382#define WR_SCL_CTRL_STATUS_FIFO_SIZE_SHIFT (18U)
47383#define WR_SCL_CTRL_STATUS_FIFO_SIZE(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_FIFO_SIZE_SHIFT)) & WR_SCL_CTRL_STATUS_FIFO_SIZE_MASK)
47384#define WR_SCL_CTRL_STATUS_FRAME_COMP_EN_MASK (0x10000000U)
47385#define WR_SCL_CTRL_STATUS_FRAME_COMP_EN_SHIFT (28U)
47386#define WR_SCL_CTRL_STATUS_FRAME_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_FRAME_COMP_EN_SHIFT)) & WR_SCL_CTRL_STATUS_FRAME_COMP_EN_MASK)
47387#define WR_SCL_CTRL_STATUS_FRAME_COMP_MASK (0x20000000U)
47388#define WR_SCL_CTRL_STATUS_FRAME_COMP_SHIFT (29U)
47389#define WR_SCL_CTRL_STATUS_FRAME_COMP(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_FRAME_COMP_SHIFT)) & WR_SCL_CTRL_STATUS_FRAME_COMP_MASK)
47390#define WR_SCL_CTRL_STATUS_WR_ERR_EN_MASK (0x40000000U)
47391#define WR_SCL_CTRL_STATUS_WR_ERR_EN_SHIFT (30U)
47392#define WR_SCL_CTRL_STATUS_WR_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_WR_ERR_EN_SHIFT)) & WR_SCL_CTRL_STATUS_WR_ERR_EN_MASK)
47393#define WR_SCL_CTRL_STATUS_WR_ERR_MASK (0x80000000U)
47394#define WR_SCL_CTRL_STATUS_WR_ERR_SHIFT (31U)
47395#define WR_SCL_CTRL_STATUS_WR_ERR(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_WR_ERR_SHIFT)) & WR_SCL_CTRL_STATUS_WR_ERR_MASK)
47396/*! @} */
47397
47398/*! @name BASE_ADDR - Holds the base address */
47399/*! @{ */
47400#define WR_SCL_BASE_ADDR_BASE_ADDR_MASK (0xFFFFFFFFU)
47401#define WR_SCL_BASE_ADDR_BASE_ADDR_SHIFT (0U)
47402#define WR_SCL_BASE_ADDR_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_BASE_ADDR_BASE_ADDR_SHIFT)) & WR_SCL_BASE_ADDR_BASE_ADDR_MASK)
47403/*! @} */
47404
47405/*! @name PITCH - Pitch */
47406/*! @{ */
47407#define WR_SCL_PITCH_PITCH_MASK (0xFFFFU)
47408#define WR_SCL_PITCH_PITCH_SHIFT (0U)
47409#define WR_SCL_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_PITCH_PITCH_SHIFT)) & WR_SCL_PITCH_PITCH_MASK)
47410/*! @} */
47411
47412
47413/*!
47414 * @}
47415 */ /* end of group WR_SCL_Register_Masks */
47416
47417
47418/* WR_SCL - Peripheral instance base addresses */
47419/** Peripheral DCSS__WR_SCL base address */
47420#define DCSS__WR_SCL_BASE (0x32E21000u)
47421/** Peripheral DCSS__WR_SCL base pointer */
47422#define DCSS__WR_SCL ((WR_SCL_Type *)DCSS__WR_SCL_BASE)
47423/** Array initializer of WR_SCL peripheral base addresses */
47424#define WR_SCL_BASE_ADDRS { DCSS__WR_SCL_BASE }
47425/** Array initializer of WR_SCL peripheral base pointers */
47426#define WR_SCL_BASE_PTRS { DCSS__WR_SCL }
47427
47428/*!
47429 * @}
47430 */ /* end of group WR_SCL_Peripheral_Access_Layer */
47431
47432
47433/* ----------------------------------------------------------------------------
47434 -- XTALOSC Peripheral Access Layer
47435 ---------------------------------------------------------------------------- */
47436
47437/*!
47438 * @addtogroup XTALOSC_Peripheral_Access_Layer XTALOSC Peripheral Access Layer
47439 * @{
47440 */
47441
47442/** XTALOSC - Register Layout Typedef */
47443typedef struct {
47444 __IO uint32_t OSC25M_CTL_CFG; /**< 25M Oscillator Control Configuration Register, offset: 0x0 */
47445 __IO uint32_t OSC25M_TEST_CFG; /**< 25M Oscillator Test Configuration Register, offset: 0x4 */
47446 uint8_t RESERVED_0[32760];
47447 __IO uint32_t OSC27M_CTL_CFG; /**< 27M Oscillator Control Configuration Register, offset: 0x8000 */
47448 __IO uint32_t OSC27M_TEST_CFG; /**< 27M Oscillator Test Configuration Register, offset: 0x8004 */
47449} XTALOSC_Type;
47450
47451/* ----------------------------------------------------------------------------
47452 -- XTALOSC Register Masks
47453 ---------------------------------------------------------------------------- */
47454
47455/*!
47456 * @addtogroup XTALOSC_Register_Masks XTALOSC Register Masks
47457 * @{
47458 */
47459
47460/*! @name OSC25M_CTL_CFG - 25M Oscillator Control Configuration Register */
47461/*! @{ */
47462#define XTALOSC_OSC25M_CTL_CFG_OSC_ALC_CTL_MASK (0x4U)
47463#define XTALOSC_OSC25M_CTL_CFG_OSC_ALC_CTL_SHIFT (2U)
47464/*! OSC_ALC_CTL
47465 * 0b0..Enable automatic level controller
47466 * 0b1..Disable automatic level controller
47467 */
47468#define XTALOSC_OSC25M_CTL_CFG_OSC_ALC_CTL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_ALC_CTL_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_ALC_CTL_MASK)
47469#define XTALOSC_OSC25M_CTL_CFG_OSC_HYST_CTL_MASK (0x8U)
47470#define XTALOSC_OSC25M_CTL_CFG_OSC_HYST_CTL_SHIFT (3U)
47471/*! OSC_HYST_CTL
47472 * 0b0..Enable hysteresis control
47473 * 0b1..Disable hysteresis control
47474 */
47475#define XTALOSC_OSC25M_CTL_CFG_OSC_HYST_CTL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_HYST_CTL_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_HYST_CTL_MASK)
47476#define XTALOSC_OSC25M_CTL_CFG_OSC_GM_SEL_MASK (0x70U)
47477#define XTALOSC_OSC25M_CTL_CFG_OSC_GM_SEL_SHIFT (4U)
47478#define XTALOSC_OSC25M_CTL_CFG_OSC_GM_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_GM_SEL_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_GM_SEL_MASK)
47479#define XTALOSC_OSC25M_CTL_CFG_OSC_INT_STU_MASK (0x80U)
47480#define XTALOSC_OSC25M_CTL_CFG_OSC_INT_STU_SHIFT (7U)
47481/*! OSC_INT_STU
47482 * 0b0..No oscillator clock interrupt occurred
47483 * 0b1..Oscillator clock interrupt pending
47484 */
47485#define XTALOSC_OSC25M_CTL_CFG_OSC_INT_STU(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_INT_STU_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_INT_STU_MASK)
47486#define XTALOSC_OSC25M_CTL_CFG_OSC_DIV_MASK (0x1F00U)
47487#define XTALOSC_OSC25M_CTL_CFG_OSC_DIV_SHIFT (8U)
47488#define XTALOSC_OSC25M_CTL_CFG_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_DIV_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_DIV_MASK)
47489#define XTALOSC_OSC25M_CTL_CFG_OSC_OK_BYPASS_MASK (0x2000U)
47490#define XTALOSC_OSC25M_CTL_CFG_OSC_OK_BYPASS_SHIFT (13U)
47491#define XTALOSC_OSC25M_CTL_CFG_OSC_OK_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_OK_BYPASS_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_OK_BYPASS_MASK)
47492#define XTALOSC_OSC25M_CTL_CFG_OSC_INT_MASK_MASK (0x8000U)
47493#define XTALOSC_OSC25M_CTL_CFG_OSC_INT_MASK_SHIFT (15U)
47494/*! OSC_INT_MASK
47495 * 0b0..Crystal oscillator clock interrupt is masked
47496 * 0b1..Crystal oscillator clock interrupt is enabled
47497 */
47498#define XTALOSC_OSC25M_CTL_CFG_OSC_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_INT_MASK_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_INT_MASK_MASK)
47499#define XTALOSC_OSC25M_CTL_CFG_OSC_EOCV_MASK (0xFF0000U)
47500#define XTALOSC_OSC25M_CTL_CFG_OSC_EOCV_SHIFT (16U)
47501#define XTALOSC_OSC25M_CTL_CFG_OSC_EOCV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_EOCV_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_EOCV_MASK)
47502#define XTALOSC_OSC25M_CTL_CFG_OSC_GM_TST_SEL_MASK (0x40000000U)
47503#define XTALOSC_OSC25M_CTL_CFG_OSC_GM_TST_SEL_SHIFT (30U)
47504/*! OSC_GM_TST_SEL
47505 * 0b0..Normal run mode
47506 * 0b1..Enable test mode measurement of GM
47507 */
47508#define XTALOSC_OSC25M_CTL_CFG_OSC_GM_TST_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_GM_TST_SEL_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_GM_TST_SEL_MASK)
47509#define XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS_MASK (0x80000000U)
47510#define XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS_SHIFT (31U)
47511/*! OSC_BYPSS
47512 * 0b0..Oscillator output is used as root clock.
47513 * 0b1..EXTAL is used as root clock
47514 */
47515#define XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS_MASK)
47516/*! @} */
47517
47518/*! @name OSC25M_TEST_CFG - 25M Oscillator Test Configuration Register */
47519/*! @{ */
47520#define XTALOSC_OSC25M_TEST_CFG_XOSC_TESTEN_MASK (0x80000000U)
47521#define XTALOSC_OSC25M_TEST_CFG_XOSC_TESTEN_SHIFT (31U)
47522#define XTALOSC_OSC25M_TEST_CFG_XOSC_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_TEST_CFG_XOSC_TESTEN_SHIFT)) & XTALOSC_OSC25M_TEST_CFG_XOSC_TESTEN_MASK)
47523/*! @} */
47524
47525/*! @name OSC27M_CTL_CFG - 27M Oscillator Control Configuration Register */
47526/*! @{ */
47527#define XTALOSC_OSC27M_CTL_CFG_OSC_ALC_CTL_MASK (0x4U)
47528#define XTALOSC_OSC27M_CTL_CFG_OSC_ALC_CTL_SHIFT (2U)
47529/*! OSC_ALC_CTL
47530 * 0b0..Enable automatic level controller
47531 * 0b1..Disable automatic level controller
47532 */
47533#define XTALOSC_OSC27M_CTL_CFG_OSC_ALC_CTL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_ALC_CTL_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_ALC_CTL_MASK)
47534#define XTALOSC_OSC27M_CTL_CFG_OSC_HYST_CTL_MASK (0x8U)
47535#define XTALOSC_OSC27M_CTL_CFG_OSC_HYST_CTL_SHIFT (3U)
47536/*! OSC_HYST_CTL
47537 * 0b0..Enable hysteresis control
47538 * 0b1..Disable hysteresis control
47539 */
47540#define XTALOSC_OSC27M_CTL_CFG_OSC_HYST_CTL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_HYST_CTL_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_HYST_CTL_MASK)
47541#define XTALOSC_OSC27M_CTL_CFG_OSC_GM_SEL_MASK (0x70U)
47542#define XTALOSC_OSC27M_CTL_CFG_OSC_GM_SEL_SHIFT (4U)
47543#define XTALOSC_OSC27M_CTL_CFG_OSC_GM_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_GM_SEL_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_GM_SEL_MASK)
47544#define XTALOSC_OSC27M_CTL_CFG_OSC_INT_STU_MASK (0x80U)
47545#define XTALOSC_OSC27M_CTL_CFG_OSC_INT_STU_SHIFT (7U)
47546/*! OSC_INT_STU
47547 * 0b0..No oscillator clock interrupt occurred
47548 * 0b1..Oscillator clock interrupt pending
47549 */
47550#define XTALOSC_OSC27M_CTL_CFG_OSC_INT_STU(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_INT_STU_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_INT_STU_MASK)
47551#define XTALOSC_OSC27M_CTL_CFG_OSC_DIV_MASK (0x1F00U)
47552#define XTALOSC_OSC27M_CTL_CFG_OSC_DIV_SHIFT (8U)
47553#define XTALOSC_OSC27M_CTL_CFG_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_DIV_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_DIV_MASK)
47554#define XTALOSC_OSC27M_CTL_CFG_OSC_OK_BYPASS_MASK (0x2000U)
47555#define XTALOSC_OSC27M_CTL_CFG_OSC_OK_BYPASS_SHIFT (13U)
47556#define XTALOSC_OSC27M_CTL_CFG_OSC_OK_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_OK_BYPASS_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_OK_BYPASS_MASK)
47557#define XTALOSC_OSC27M_CTL_CFG_OSC_INT_MASK_MASK (0x8000U)
47558#define XTALOSC_OSC27M_CTL_CFG_OSC_INT_MASK_SHIFT (15U)
47559/*! OSC_INT_MASK
47560 * 0b0..Crystal oscillator clock interrupt is masked
47561 * 0b1..Crystal oscillator clock interrupt is enabled
47562 */
47563#define XTALOSC_OSC27M_CTL_CFG_OSC_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_INT_MASK_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_INT_MASK_MASK)
47564#define XTALOSC_OSC27M_CTL_CFG_OSC_EOCV_MASK (0xFF0000U)
47565#define XTALOSC_OSC27M_CTL_CFG_OSC_EOCV_SHIFT (16U)
47566#define XTALOSC_OSC27M_CTL_CFG_OSC_EOCV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_EOCV_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_EOCV_MASK)
47567#define XTALOSC_OSC27M_CTL_CFG_OSC_GM_TST_SEL_MASK (0x40000000U)
47568#define XTALOSC_OSC27M_CTL_CFG_OSC_GM_TST_SEL_SHIFT (30U)
47569/*! OSC_GM_TST_SEL
47570 * 0b0..Normal run mode
47571 * 0b1..Enable test mode measurement of GM
47572 */
47573#define XTALOSC_OSC27M_CTL_CFG_OSC_GM_TST_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_GM_TST_SEL_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_GM_TST_SEL_MASK)
47574#define XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS_MASK (0x80000000U)
47575#define XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS_SHIFT (31U)
47576/*! OSC_BYPSS
47577 * 0b0..Oscillator output is used as root clock.
47578 * 0b1..EXTAL is used as root clock
47579 */
47580#define XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS_MASK)
47581/*! @} */
47582
47583/*! @name OSC27M_TEST_CFG - 27M Oscillator Test Configuration Register */
47584/*! @{ */
47585#define XTALOSC_OSC27M_TEST_CFG_XOSC_TESTEN_MASK (0x80000000U)
47586#define XTALOSC_OSC27M_TEST_CFG_XOSC_TESTEN_SHIFT (31U)
47587#define XTALOSC_OSC27M_TEST_CFG_XOSC_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_TEST_CFG_XOSC_TESTEN_SHIFT)) & XTALOSC_OSC27M_TEST_CFG_XOSC_TESTEN_MASK)
47588/*! @} */
47589
47590
47591/*!
47592 * @}
47593 */ /* end of group XTALOSC_Register_Masks */
47594
47595
47596/* XTALOSC - Peripheral instance base addresses */
47597/** Peripheral XTALOSC base address */
47598#define XTALOSC_BASE (0x30270000u)
47599/** Peripheral XTALOSC base pointer */
47600#define XTALOSC ((XTALOSC_Type *)XTALOSC_BASE)
47601/** Array initializer of XTALOSC peripheral base addresses */
47602#define XTALOSC_BASE_ADDRS { XTALOSC_BASE }
47603/** Array initializer of XTALOSC peripheral base pointers */
47604#define XTALOSC_BASE_PTRS { XTALOSC }
47605
47606/*!
47607 * @}
47608 */ /* end of group XTALOSC_Peripheral_Access_Layer */
47609
47610
47611/*
47612** End of section using anonymous unions
47613*/
47614
47615#if defined(__ARMCC_VERSION)
47616 #if (__ARMCC_VERSION >= 6010050)
47617 #pragma clang diagnostic pop
47618 #else
47619 #pragma pop
47620 #endif
47621#elif defined(__GNUC__)
47622 /* leave anonymous unions enabled */
47623#elif defined(__IAR_SYSTEMS_ICC__)
47624 #pragma language=default
47625#else
47626 #error Not supported compiler type
47627#endif
47628
47629/*!
47630 * @}
47631 */ /* end of group Peripheral_access_layer */
47632
47633
47634/* ----------------------------------------------------------------------------
47635 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
47636 ---------------------------------------------------------------------------- */
47637
47638/*!
47639 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
47640 * @{
47641 */
47642
47643#if defined(__ARMCC_VERSION)
47644 #if (__ARMCC_VERSION >= 6010050)
47645 #pragma clang system_header
47646 #endif
47647#elif defined(__IAR_SYSTEMS_ICC__)
47648 #pragma system_include
47649#endif
47650
47651/**
47652 * @brief Mask and left-shift a bit field value for use in a register bit range.
47653 * @param field Name of the register bit field.
47654 * @param value Value of the bit field.
47655 * @return Masked and shifted value.
47656 */
47657#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
47658/**
47659 * @brief Mask and right-shift a register value to extract a bit field value.
47660 * @param field Name of the register bit field.
47661 * @param value Value of the register.
47662 * @return Masked and shifted bit field value.
47663 */
47664#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
47665
47666/*!
47667 * @}
47668 */ /* end of group Bit_Field_Generic_Macros */
47669
47670
47671/* ----------------------------------------------------------------------------
47672 -- SDK Compatibility
47673 ---------------------------------------------------------------------------- */
47674
47675/*!
47676 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
47677 * @{
47678 */
47679
47680/* No SDK compatibility issues. */
47681
47682/*!
47683 * @}
47684 */ /* end of group SDK_Compatibility_Symbols */
47685
47686
47687#endif /* _MIMX8MD7_CM4_H_ */
47688
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/MIMX8MD7_cm4_features.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/MIMX8MD7_cm4_features.h
new file mode 100644
index 000000000..9fdfdcf83
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/MIMX8MD7_cm4_features.h
@@ -0,0 +1,388 @@
1/*
2** ###################################################################
3** Version: rev. 4.0, 2018-01-26
4** Build: b200922
5**
6** Abstract:
7** Chip specific module features.
8**
9** Copyright 2016 Freescale Semiconductor, Inc.
10** Copyright 2016-2020 NXP
11** All rights reserved.
12**
13** SPDX-License-Identifier: BSD-3-Clause
14**
15** http: www.nxp.com
16** mail: [email protected]
17**
18** Revisions:
19** - rev. 1.0 (2016-06-02)
20** Initial version.
21** - rev. 2.0 (2017-04-27)
22** Rev.B Header EAR1
23** - rev. 3.0 (2017-07-19)
24** Rev.C Header EAR2
25** - rev. 4.0 (2018-01-26)
26** Rev.D Header RFP
27**
28** ###################################################################
29*/
30
31#ifndef _MIMX8MD7_cm4_FEATURES_H_
32#define _MIMX8MD7_cm4_FEATURES_H_
33
34/* SOC module features */
35
36/* @brief AIPSTZ availability on the SoC. */
37#define FSL_FEATURE_SOC_AIPSTZ_COUNT (4)
38/* @brief APBH availability on the SoC. */
39#define FSL_FEATURE_SOC_APBH_COUNT (1)
40/* @brief BCH availability on the SoC. */
41#define FSL_FEATURE_SOC_BCH_COUNT (1)
42/* @brief CCM availability on the SoC. */
43#define FSL_FEATURE_SOC_CCM_COUNT (1)
44/* @brief CCM_ANALOG availability on the SoC. */
45#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
46/* @brief DDRC availability on the SoC. */
47#define FSL_FEATURE_SOC_DDRC_COUNT (1)
48/* @brief ECSPI availability on the SoC. */
49#define FSL_FEATURE_SOC_ECSPI_COUNT (3)
50/* @brief ENET availability on the SoC. */
51#define FSL_FEATURE_SOC_ENET_COUNT (1)
52/* @brief GPC availability on the SoC. */
53#define FSL_FEATURE_SOC_GPC_COUNT (1)
54/* @brief GPC_PGC availability on the SoC. */
55#define FSL_FEATURE_SOC_GPC_PGC_COUNT (1)
56/* @brief GPMI availability on the SoC. */
57#define FSL_FEATURE_SOC_GPMI_COUNT (1)
58/* @brief GPT availability on the SoC. */
59#define FSL_FEATURE_SOC_GPT_COUNT (6)
60/* @brief I2S availability on the SoC. */
61#define FSL_FEATURE_SOC_I2S_COUNT (6)
62/* @brief IGPIO availability on the SoC. */
63#define FSL_FEATURE_SOC_IGPIO_COUNT (5)
64/* @brief II2C availability on the SoC. */
65#define FSL_FEATURE_SOC_II2C_COUNT (4)
66/* @brief IOMUXC availability on the SoC. */
67#define FSL_FEATURE_SOC_IOMUXC_COUNT (1)
68/* @brief IOMUXC_GPR availability on the SoC. */
69#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1)
70/* @brief IPWM availability on the SoC. */
71#define FSL_FEATURE_SOC_IPWM_COUNT (4)
72/* @brief IRQSTEER availability on the SoC. */
73#define FSL_FEATURE_SOC_IRQSTEER_COUNT (1)
74/* @brief IUART availability on the SoC. */
75#define FSL_FEATURE_SOC_IUART_COUNT (4)
76/* @brief LCDIF availability on the SoC. */
77#define FSL_FEATURE_SOC_LCDIF_COUNT (1)
78/* @brief LMEM availability on the SoC. */
79#define FSL_FEATURE_SOC_LMEM_COUNT (1)
80/* @brief MCM availability on the SoC. */
81#define FSL_FEATURE_SOC_MCM_COUNT (1)
82/* @brief MIPI_CSI2RX availability on the SoC. */
83#define FSL_FEATURE_SOC_MIPI_CSI2RX_COUNT (2)
84/* @brief MIPI_DSI_HOST availability on the SoC. */
85#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (1)
86/* @brief MU availability on the SoC. */
87#define FSL_FEATURE_SOC_MU_COUNT (1)
88/* @brief OCOTP availability on the SoC. */
89#define FSL_FEATURE_SOC_OCOTP_COUNT (1)
90/* @brief QuadSPI availability on the SoC. */
91#define FSL_FEATURE_SOC_QuadSPI_COUNT (1)
92/* @brief RDC availability on the SoC. */
93#define FSL_FEATURE_SOC_RDC_COUNT (1)
94/* @brief RDC_SEMAPHORE availability on the SoC. */
95#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (2)
96/* @brief ROMC availability on the SoC. */
97#define FSL_FEATURE_SOC_ROMC_COUNT (1)
98/* @brief SEMA4 availability on the SoC. */
99#define FSL_FEATURE_SOC_SEMA4_COUNT (1)
100/* @brief SNVS availability on the SoC. */
101#define FSL_FEATURE_SOC_SNVS_COUNT (1)
102/* @brief SPBA availability on the SoC. */
103#define FSL_FEATURE_SOC_SPBA_COUNT (2)
104/* @brief SPDIF availability on the SoC. */
105#define FSL_FEATURE_SOC_SPDIF_COUNT (2)
106/* @brief SRC availability on the SoC. */
107#define FSL_FEATURE_SOC_SRC_COUNT (1)
108/* @brief USDHC availability on the SoC. */
109#define FSL_FEATURE_SOC_USDHC_COUNT (2)
110/* @brief WDOG availability on the SoC. */
111#define FSL_FEATURE_SOC_WDOG_COUNT (3)
112/* @brief XTALOSC availability on the SoC. */
113#define FSL_FEATURE_SOC_XTALOSC_COUNT (1)
114
115/* CCM module features */
116
117/* @brief Is affected by errata with ID 50235 (Incorrect clock setting for CAN affects by LPUART clock gate). */
118#define FSL_FEATURE_CCM_HAS_ERRATA_50235 (0)
119
120/* ECSPI module features */
121
122/* @brief ECSPI Tx FIFO Size. */
123#define FSL_FEATURE_ECSPI_TX_FIFO_SIZEn(x) (64)
124
125/* ENET module features */
126
127/* @brief Support Interrupt Coalesce */
128#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1)
129/* @brief Queue Size. */
130#define FSL_FEATURE_ENET_QUEUE (3)
131/* @brief Has AVB Support. */
132#define FSL_FEATURE_ENET_HAS_AVB (1)
133/* @brief Has Timer Pulse Width control. */
134#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (0)
135/* @brief Has Extend MDIO Support. */
136#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1)
137/* @brief Has Additional 1588 Timer Channel Interrupt. */
138#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (1)
139/* @brief Support Interrupt Coalesce for each instance */
140#define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (0)
141/* @brief Queue Size for each instance. */
142#define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (3)
143/* @brief Has AVB Support for each instance. */
144#define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) (1)
145/* @brief Has Timer Pulse Width control for each instance. */
146#define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) (0)
147/* @brief Has Extend MDIO Support for each instance. */
148#define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (1)
149/* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */
150#define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1)
151/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */
152#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1)
153
154/* GPC module features */
155
156/* @brief Has PGC MF. */
157#define FSL_FEATURE_GPC_HAS_PGC_MF (1)
158
159/* IGPIO module features */
160
161/* @brief Has data register set DR_SET. */
162#define FSL_FEATURE_IGPIO_HAS_DR_SET (0)
163/* @brief Has data register clear DR_CLEAR. */
164#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (0)
165/* @brief Has data register toggle DR_TOGGLE. */
166#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (0)
167
168/* SAI module features */
169
170/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
171#define FSL_FEATURE_SAI_FIFO_COUNT (128)
172/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
173#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \
174 (((x) == I2S1) ? (8) : \
175 (((x) == I2S2) ? (1) : \
176 (((x) == I2S3) ? (1) : \
177 (((x) == I2S4) ? (1) : \
178 (((x) == I2S5) ? (1) : \
179 (((x) == I2S6) ? (1) : (-1)))))))
180/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
181#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
182/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
183#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
184/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
185#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
186/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
187#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
188/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
189#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
190/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
191#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
192/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
193#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
194/* @brief Interrupt source number */
195#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1)
196/* @brief Has register of MCR. */
197#define FSL_FEATURE_SAI_HAS_MCR (0)
198/* @brief Has bit field MICS of the MCR register. */
199#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1)
200/* @brief Has register of MDR */
201#define FSL_FEATURE_SAI_HAS_MDR (0)
202/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
203#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0)
204/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */
205#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0)
206/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */
207#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1)
208/* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */
209#define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1)
210
211/* LMEM module features */
212
213/* @brief Has process identifier support. */
214#define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (1)
215/* @brief Support instruction cache demote. */
216#define FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE (1)
217/* @brief Has no NONCACHEABLE section. */
218#define FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION (0)
219/* @brief L1 ICACHE line size in byte. */
220#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32)
221/* @brief L1 DCACHE line size in byte. */
222#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32)
223
224/* MEMORY module features */
225
226/* @brief Memory map has offset between subsystems. */
227#define FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET (1)
228
229/* MU module features */
230
231/* @brief MU side for current core */
232#define FSL_FEATURE_MU_SIDE_B (1)
233/* @brief MU Has register CCR */
234#define FSL_FEATURE_MU_HAS_CCR (0)
235/* @brief MU Has register SR[RS], BSR[ARS] */
236#define FSL_FEATURE_MU_HAS_SR_RS (1)
237/* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */
238#define FSL_FEATURE_MU_HAS_RESET_INT (0)
239/* @brief MU Has register SR[MURIP] */
240#define FSL_FEATURE_MU_HAS_SR_MURIP (0)
241/* @brief MU Has register SR[HRIP] */
242#define FSL_FEATURE_MU_HAS_SR_HRIP (0)
243/* @brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */
244#define FSL_FEATURE_MU_NO_CLKE (1)
245/* @brief MU does not support NMI, CR[NMI]. */
246#define FSL_FEATURE_MU_NO_NMI (1)
247/* @brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */
248#define FSL_FEATURE_MU_NO_RSTH (1)
249/* @brief MU does not supports MU reset, CR[MUR]. */
250#define FSL_FEATURE_MU_NO_MUR (1)
251/* @brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */
252#define FSL_FEATURE_MU_NO_HR (1)
253/* @brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */
254#define FSL_FEATURE_MU_HAS_HRM (1)
255/* @brief MU does not support check the other core power mode. SR[PM]. */
256#define FSL_FEATURE_MU_NO_PM (1)
257/* @brief MU supports reset assert interrupt. CR[RAIE] or BCR[RAIE]. */
258#define FSL_FEATURE_MU_HAS_RESET_ASSERT_INT (0)
259/* @brief MU supports reset de-assert interrupt. CR[RDIE] or BCR[RDIE]. */
260#define FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT (0)
261
262/* interrupt module features */
263
264/* @brief Lowest interrupt request number. */
265#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
266/* @brief Highest interrupt request number. */
267#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105)
268
269/* QSPI module features */
270
271/* @brief QSPI lookup table depth. */
272#define FSL_FEATURE_QSPI_LUT_DEPTH (64)
273/* @brief QSPI Tx FIFO depth. */
274#define FSL_FEATURE_QSPI_TXFIFO_DEPTH (16)
275/* @brief QSPI Rx FIFO depth. */
276#define FSL_FEATURE_QSPI_RXFIFO_DEPTH (16)
277/* @brief QSPI AHB buffer count. */
278#define FSL_FEATURE_QSPI_AHB_BUFFER_COUNT (4)
279/* @brief QSPI has command usage error flag. */
280#define FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR (1)
281/* @brief QSPI support parallel mode. */
282#define FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE (1)
283/* @brief QSPI support dual die. */
284#define FSL_FEATURE_QSPI_SUPPORT_DUAL_DIE (1)
285/* @brief there is no SCLKCFG bit in MCR register. */
286#define FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL (1)
287/* @brief there is no AITEF bit in FR register. */
288#define FSL_FEATURE_QSPI_HAS_NO_AITEF (1)
289/* @brief there is no AIBSEF bit in FR register. */
290#define FSL_FEATURE_QSPI_HAS_NO_AIBSEF (1)
291/* @brief there is no TXDMA and TXWA bit in SR register. */
292#define FSL_FEATURE_QSPI_HAS_NO_TXDMA (1)
293/* @brief there is no SFACR register. */
294#define FSL_FEATURE_QSPI_HAS_NO_SFACR (1)
295/* @brief there is no TDH bit in FLSHCR register. */
296#define FSL_FEATURE_QSPI_HAS_NO_TDH (0)
297/* @brief QSPI AHB buffer size in byte. */
298#define FSL_FEATURE_QSPI_AHB_BUFFER_SIZE (1024U)
299/* @brief QSPI AMBA base address. */
300#define FSL_FEATURE_QSPI_AMBA_BASE (0xC0000000U)
301/* @brief QSPI AHB buffer ARDB base address. */
302#define FSL_FEATURE_QSPI_ARDB_BASE (0x34000000U)
303/* @brief QSPI has no SOCCR register. */
304#define FSL_FEATURE_QSPI_HAS_NO_SOCCR_REG (1)
305
306/* SDMA module features */
307
308/* @brief SDMA module channel number. */
309#define FSL_FEATURE_SDMA_MODULE_CHANNEL (32)
310/* @brief SDMA module event number. */
311#define FSL_FEATURE_SDMA_EVENT_NUM (48)
312/* @brief SDMA ROM memory to memory script start address. */
313#define FSL_FEATURE_SDMA_M2M_ADDR (644)
314/* @brief SDMA ROM peripheral to memory script start address. */
315#define FSL_FEATURE_SDMA_P2M_ADDR (685)
316/* @brief SDMA ROM memory to peripheral script start address. */
317#define FSL_FEATURE_SDMA_M2P_ADDR (749)
318/* @brief SDMA ROM uart to memory script start address. */
319#define FSL_FEATURE_SDMA_UART2M_ADDR (819)
320/* @brief SDMA ROM peripheral on SPBA to memory script start address. */
321#define FSL_FEATURE_SDMA_SHP2M_ADDR (893)
322/* @brief SDMA ROM memory to peripheral on SPBA script start address. */
323#define FSL_FEATURE_SDMA_M2SHP_ADDR (962)
324/* @brief SDMA ROM UART on SPBA to memory script start address. */
325#define FSL_FEATURE_SDMA_UARTSH2M_ADDR (1034)
326/* @brief SDMA ROM SPDIF to memory script start address. */
327#define FSL_FEATURE_SDMA_SPDIF2M_ADDR (1102)
328/* @brief SDMA ROM memory to SPDIF script start address. */
329#define FSL_FEATURE_SDMA_M2SPDIF_ADDR (1136)
330
331/* SEMA4 module features */
332
333/* @brief Gate counts */
334#define FSL_FEATURE_SEMA4_GATE_COUNT (16)
335
336/* SNVS module features */
337
338/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */
339#define FSL_FEATURE_SNVS_HAS_SRTC (1)
340
341/* SPBA module features */
342
343/* @brief SPBA module start address. */
344#define FSL_FEATURE_SPBA_STARTn(x) \
345 (((x) == SPBA1) ? (0x30800000) : \
346 (((x) == SPBA2) ? (0x30000000) : (-1)))
347/* @brief SPBA module end address. */
348#define FSL_FEATURE_SPBA_ENDn(x) \
349 (((x) == SPBA1) ? (0x308FFFFF) : \
350 (((x) == SPBA2) ? (0x300FFFFF) : (-1)))
351
352/* SysTick module features */
353
354/* @brief Systick has external reference clock. */
355#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
356/* @brief Systick external reference clock is core clock divided by this value. */
357#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
358
359/* IUART module features */
360
361/* @brief UART Transmit/Receive FIFO Size */
362#define FSL_FEATURE_IUART_FIFO_SIZEn(x) (32)
363/* @brief UART RX MUXed input selected option */
364#define FSL_FEATURE_IUART_RXDMUXSEL (1)
365
366/* USDHC module features */
367
368/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
369#define FSL_FEATURE_USDHC_HAS_EXT_DMA (1)
370/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */
371#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1)
372/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */
373#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1)
374/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
375#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1)
376/* @brief USDHC has reset control */
377#define FSL_FEATURE_USDHC_HAS_RESET (0)
378/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */
379#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0)
380/* @brief If USDHC instance support 8 bit width */
381#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1)
382/* @brief If USDHC instance support HS400 mode */
383#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0)
384/* @brief If USDHC instance support 1v8 signal */
385#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1)
386
387#endif /* _MIMX8MD7_cm4_FEATURES_H_ */
388
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/drivers/driver_reset.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/drivers/driver_reset.cmake
new file mode 100644
index 000000000..989530f6f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/drivers/driver_reset.cmake
@@ -0,0 +1,14 @@
1if(NOT DRIVER_RESET_INCLUDED)
2
3 set(DRIVER_RESET_INCLUDED true CACHE BOOL "driver_reset component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 )
7
8 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
9 ${CMAKE_CURRENT_LIST_DIR}/.
10 )
11
12
13
14endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/drivers/fsl_clock.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/drivers/fsl_clock.c
new file mode 100644
index 000000000..d7c8b735c
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/drivers/fsl_clock.c
@@ -0,0 +1,967 @@
1/*
2 * Copyright 2017 - 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7#include "fsl_common.h"
8#include "fsl_clock.h"
9
10/*******************************************************************************
11 * Definitions
12 ******************************************************************************/
13/* Component ID definition, used by tools. */
14#ifndef FSL_COMPONENT_ID
15#define FSL_COMPONENT_ID "platform.drivers.clock"
16#endif
17/*! @brief SSCG PLL FLITER range value */
18#define SSCG_PLL1_FILTER_RANGE (35000000U)
19/*******************************************************************************
20 * Prototypes
21 ******************************************************************************/
22
23/*******************************************************************************
24 * Variables
25 ******************************************************************************/
26
27/*******************************************************************************
28 * Code
29 ******************************************************************************/
30/*!
31 * brief Gets the clock frequency for a specific clock name.
32 *
33 * This function checks the current clock configurations and then calculates
34 * the clock frequency for a specific clock name defined in clock_name_t.
35 *
36 * param clockName Clock names defined in clock_name_t
37 * return Clock frequency value in hertz
38 */
39uint32_t CLOCK_GetFreq(clock_name_t clockName)
40{
41 uint32_t freq;
42
43 switch (clockName)
44 {
45 case kCLOCK_CoreM4Clk:
46 freq = CLOCK_GetCoreM4Freq();
47 break;
48 case kCLOCK_AxiClk:
49 freq = CLOCK_GetAxiFreq();
50 break;
51 case kCLOCK_AhbClk:
52 freq = CLOCK_GetAhbFreq();
53 break;
54 case kCLOCK_IpgClk:
55 freq = CLOCK_GetAhbFreq();
56 break;
57 default:
58 freq = 0U;
59 break;
60 }
61 return freq;
62}
63
64/*!
65 * brief Get the CCM Cortex M4 core frequency.
66 *
67 * return Clock frequency; If the clock is invalid, returns 0.
68 */
69uint32_t CLOCK_GetCoreM4Freq(void)
70{
71 uint32_t freq;
72 uint32_t pre = CLOCK_GetRootPreDivider(kCLOCK_RootM4);
73 uint32_t post = CLOCK_GetRootPostDivider(kCLOCK_RootM4);
74
75 switch (CLOCK_GetRootMux(kCLOCK_RootM4))
76 {
77 case (uint32_t)kCLOCK_M4RootmuxOsc25m:
78 freq = OSC25M_CLK_FREQ;
79 break;
80 case (uint32_t)kCLOCK_M4RootmuxSysPll2Div5:
81 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 5U;
82 break;
83 case (uint32_t)kCLOCK_M4RootmuxSysPll2Div4:
84 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 4U;
85 break;
86 case (uint32_t)kCLOCK_M4RootmuxSysPll1Div3:
87 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / 3U;
88 break;
89 case (uint32_t)kCLOCK_M4RootmuxSysPll1:
90 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl);
91 break;
92 case (uint32_t)kCLOCK_M4RootmuxAudioPll1:
93 freq = CLOCK_GetPllFreq(kCLOCK_AudioPll1Ctrl);
94 break;
95 case (uint32_t)kCLOCK_M4RootmuxVideoPll1:
96 freq = CLOCK_GetPllFreq(kCLOCK_VideoPll1Ctrl);
97 break;
98 case (uint32_t)kCLOCK_M4RootmuxSysPll3:
99 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll3Ctrl);
100 break;
101 default:
102 freq = 0U;
103 break;
104 }
105
106 return freq / pre / post;
107}
108
109/*!
110 * brief Get the CCM Axi bus frequency.
111 *
112 * return Clock frequency; If the clock is invalid, returns 0.
113 */
114uint32_t CLOCK_GetAxiFreq(void)
115{
116 uint32_t freq;
117 uint32_t pre = CLOCK_GetRootPreDivider(kCLOCK_RootAxi);
118 uint32_t post = CLOCK_GetRootPostDivider(kCLOCK_RootAxi);
119
120 switch (CLOCK_GetRootMux(kCLOCK_RootAxi))
121 {
122 case (uint32_t)kCLOCK_AxiRootmuxOsc25m:
123 freq = OSC25M_CLK_FREQ;
124 break;
125 case (uint32_t)kCLOCK_AxiRootmuxSysPll2Div3:
126 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 3U;
127 break;
128 case (uint32_t)kCLOCK_AxiRootmuxSysPll2Div4:
129 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 4U;
130 break;
131 case (uint32_t)kCLOCK_AxiRootmuxSysPll2:
132 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl);
133 break;
134 case (uint32_t)kCLOCK_AxiRootmuxAudioPll1:
135 freq = CLOCK_GetPllFreq(kCLOCK_AudioPll1Ctrl);
136 break;
137 case (uint32_t)kCLOCK_AxiRootmuxVideoPll1:
138 freq = CLOCK_GetPllFreq(kCLOCK_VideoPll1Ctrl);
139 break;
140 case (uint32_t)kCLOCK_AxiRootmuxSysPll1Div8:
141 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / 8U;
142 break;
143 case (uint32_t)kCLOCK_AxiRootmuxSysPll1:
144 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl);
145 break;
146 default:
147 freq = 0U;
148 break;
149 }
150
151 return freq / pre / post;
152}
153
154/*!
155 * brief Get the CCM Ahb bus frequency.
156 *
157 * return Clock frequency; If the clock is invalid, returns 0.
158 */
159uint32_t CLOCK_GetAhbFreq(void)
160{
161 uint32_t freq;
162 uint32_t pre = CLOCK_GetRootPreDivider(kCLOCK_RootAhb);
163 uint32_t post = CLOCK_GetRootPostDivider(kCLOCK_RootAhb);
164
165 switch (CLOCK_GetRootMux(kCLOCK_RootAhb))
166 {
167 case (uint32_t)kCLOCK_AhbRootmuxOsc25m:
168 freq = OSC25M_CLK_FREQ;
169 break;
170 case (uint32_t)kCLOCK_AhbRootmuxSysPll1Div6:
171 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / 6U;
172 break;
173 case (uint32_t)kCLOCK_AhbRootmuxSysPll1Div2:
174 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / 2U;
175 break;
176 case (uint32_t)kCLOCK_AhbRootmuxSysPll1:
177 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl);
178 break;
179 case (uint32_t)kCLOCK_AhbRootmuxSysPll2Div8:
180 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 8U;
181 break;
182 case (uint32_t)kCLOCK_AhbRootmuxSysPll3:
183 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll3Ctrl);
184 break;
185 case (uint32_t)kCLOCK_AhbRootmuxAudioPll1:
186 freq = CLOCK_GetPllFreq(kCLOCK_AudioPll1Ctrl);
187 break;
188 case (uint32_t)kCLOCK_AhbRootmuxVideoPll1:
189 freq = CLOCK_GetPllFreq(kCLOCK_VideoPll1Ctrl);
190 break;
191 default:
192 freq = 0U;
193 break;
194 }
195
196 return freq / pre / post;
197}
198
199/*!
200 * brief Gets PLL reference clock frequency.
201 *
202 * param type fractional pll type.
203
204 * return Clock frequency
205 */
206uint32_t CLOCK_GetPllRefClkFreq(clock_pll_ctrl_t ctrl)
207{
208 uint32_t refClkFreq = 0U;
209 uint8_t clkSel = 0U;
210
211 if (ctrl <= kCLOCK_ArmPllCtrl)
212 {
213 clkSel = (uint8_t)CCM_BIT_FIELD_EXTRACTION(CCM_ANALOG_TUPLE_REG(CCM_ANALOG, ctrl),
214 CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_MASK,
215 CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT);
216 }
217 else
218 {
219 clkSel = (uint8_t)(CCM_ANALOG_TUPLE_REG(CCM_ANALOG, ctrl) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_MASK);
220 }
221
222 switch (clkSel)
223 {
224 case (uint8_t)kANALOG_PllRefOsc25M:
225 refClkFreq = OSC25M_CLK_FREQ /
226 (CCM_BIT_FIELD_EXTRACTION(XTALOSC->OSC25M_CTL_CFG, XTALOSC_OSC25M_CTL_CFG_OSC_DIV_MASK,
227 XTALOSC_OSC25M_CTL_CFG_OSC_DIV_SHIFT) +
228 1U);
229 break;
230
231 case (uint8_t)kANALOG_PllRefOsc27M:
232 refClkFreq = OSC27M_CLK_FREQ /
233 (CCM_BIT_FIELD_EXTRACTION(XTALOSC->OSC27M_CTL_CFG, XTALOSC_OSC27M_CTL_CFG_OSC_DIV_MASK,
234 XTALOSC_OSC27M_CTL_CFG_OSC_DIV_SHIFT) +
235 1U);
236 break;
237
238 case (uint8_t)kANALOG_PllRefOscHdmiPhy27M:
239 refClkFreq = HDMI_PHY_27M_FREQ;
240 break;
241
242 case (uint8_t)kANALOG_PllRefClkPN:
243 refClkFreq = CLKPN_FREQ;
244 break;
245 default:
246 refClkFreq = 0U;
247 break;
248 }
249
250 return refClkFreq;
251}
252
253/*!
254 * brief Gets PLL clock frequency.
255 *
256 * param type fractional pll type.
257
258 * return Clock frequency
259 */
260uint32_t CLOCK_GetPllFreq(clock_pll_ctrl_t pll)
261{
262 uint32_t pllFreq = 0U;
263 uint32_t pllRefFreq = 0U;
264 bool sscgPll1Bypass = false;
265 bool sscgPll2Bypass = false;
266 bool fracPllBypass = false;
267
268 pllRefFreq = CLOCK_GetPllRefClkFreq(pll);
269
270 switch (pll)
271 {
272 /* SSCG PLL frequency */
273 case kCLOCK_SystemPll1Ctrl:
274 sscgPll1Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll1InternalPll1BypassCtrl);
275 sscgPll2Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll1InternalPll2BypassCtrl);
276 break;
277 case kCLOCK_SystemPll2Ctrl:
278 sscgPll1Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll2InternalPll1BypassCtrl);
279 sscgPll2Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll2InternalPll2BypassCtrl);
280 break;
281 case kCLOCK_SystemPll3Ctrl:
282 sscgPll1Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll3InternalPll1BypassCtrl);
283 sscgPll2Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll3InternalPll2BypassCtrl);
284 break;
285 case kCLOCK_VideoPll2Ctrl:
286 sscgPll1Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_VideoPll2InternalPll1BypassCtrl);
287 sscgPll2Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_VideoPll2InternalPll2BypassCtrl);
288 break;
289 case kCLOCK_DramPllCtrl:
290 sscgPll1Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_DramPllInternalPll1BypassCtrl);
291 sscgPll2Bypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_DramPllInternalPll2BypassCtrl);
292 break;
293 case kCLOCK_AudioPll1Ctrl:
294 fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_AudioPll1BypassCtrl);
295 break;
296 case kCLOCK_AudioPll2Ctrl:
297 fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_AudioPll2BypassCtrl);
298 break;
299 case kCLOCK_VideoPll1Ctrl:
300 fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_VideoPll1BypassCtrl);
301 break;
302 case kCLOCK_GpuPllCtrl:
303 fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_GpuPLLPwrBypassCtrl);
304 break;
305 case kCLOCK_VpuPllCtrl:
306 fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_VpuPllPwrBypassCtrl);
307 break;
308 case kCLOCK_ArmPllCtrl:
309 fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_ArmPllPwrBypassCtrl);
310 break;
311 default:
312 fracPllBypass = false;
313 break;
314 }
315 if (pll <= kCLOCK_ArmPllCtrl)
316 {
317 if (fracPllBypass)
318 {
319 pllFreq = pllRefFreq;
320 }
321 else
322 {
323 pllFreq = CLOCK_GetFracPllFreq(CCM_ANALOG, pll, pllRefFreq);
324 }
325 }
326 else
327 {
328 if (sscgPll2Bypass)
329 {
330 /* if PLL2 is bypass, return reference clock directly */
331 pllFreq = pllRefFreq;
332 }
333 else
334 {
335 pllFreq = CLOCK_GetSSCGPllFreq(CCM_ANALOG, pll, pllRefFreq, sscgPll1Bypass);
336 }
337 }
338
339 return pllFreq;
340}
341
342/*!
343 * brief Initializes the ANALOG ARM PLL.
344 *
345 * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration).
346 *
347 * note This function can't detect whether the Arm PLL has been enabled and
348 * used by some IPs.
349 */
350void CLOCK_InitArmPll(const ccm_analog_frac_pll_config_t *config)
351{
352 assert(config != NULL);
353
354 /* Disable PLL bypass */
355 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_ArmPllPwrBypassCtrl, false);
356 /* Fractional pll configuration */
357 CLOCK_InitFracPll(CCM_ANALOG, config, kCLOCK_ArmPllCtrl);
358 /* Enable and power up PLL clock. */
359 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_ArmPllClke);
360
361 /* Wait for PLL to be locked. */
362 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_ArmPllCtrl))
363 {
364 }
365}
366
367/*!
368 * brief De-initialize the ARM PLL.
369 */
370void CLOCK_DeinitArmPll(void)
371{
372 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_ArmPllCtrl);
373}
374
375/*!
376 * brief Initializes the ANALOG AUDIO PLL1.
377 *
378 * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration).
379 *
380 * note This function can't detect whether the AUDIO PLL has been enabled and
381 * used by some IPs.
382 */
383void CLOCK_InitAudioPll1(const ccm_analog_frac_pll_config_t *config)
384{
385 assert(config != NULL);
386
387 /* Disable PLL bypass */
388 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_AudioPll1BypassCtrl, false);
389 /* Fractional pll configuration */
390 CLOCK_InitFracPll(CCM_ANALOG, config, kCLOCK_AudioPll1Ctrl);
391 /* Enable and power up PLL clock. */
392 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_AudioPll1Clke);
393
394 /* Wait for PLL to be locked. */
395 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_AudioPll1Ctrl))
396 {
397 }
398}
399
400/*!
401 * brief De-initialize the Audio PLL1.
402 */
403void CLOCK_DeinitAudioPll1(void)
404{
405 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_AudioPll1Ctrl);
406}
407
408/*!
409 * brief Initializes the ANALOG AUDIO PLL2.
410 *
411 * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration).
412 *
413 * note This function can't detect whether the AUDIO PLL has been enabled and
414 * used by some IPs.
415 */
416void CLOCK_InitAudioPll2(const ccm_analog_frac_pll_config_t *config)
417{
418 assert(config != NULL);
419
420 /* Disable PLL bypass */
421 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_AudioPll2BypassCtrl, false);
422 /* Fractional pll configuration */
423 CLOCK_InitFracPll(CCM_ANALOG, config, kCLOCK_AudioPll2Ctrl);
424 /* Enable and power up PLL clock. */
425 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_AudioPll2Clke);
426
427 /* Wait for PLL to be locked. */
428 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_AudioPll2Ctrl))
429 {
430 }
431}
432
433/*!
434 * brief De-initialize the Audio PLL2.
435 */
436void CLOCK_DeinitAudioPll2(void)
437{
438 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_AudioPll2Ctrl);
439}
440
441/*!
442 * brief Initializes the ANALOG VIDEO PLL1.
443 *
444 * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration).
445 *
446 */
447void CLOCK_InitVideoPll1(const ccm_analog_frac_pll_config_t *config)
448{
449 assert(config != NULL);
450
451 /* Disable PLL bypass */
452 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_VideoPll1BypassCtrl, false);
453 /* Fractional pll configuration */
454 CLOCK_InitFracPll(CCM_ANALOG, config, kCLOCK_VideoPll1Ctrl);
455 /* Enable and power up PLL clock. */
456 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_VideoPll1Clke);
457
458 /* Wait for PLL to be locked. */
459 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_VideoPll1Ctrl))
460 {
461 }
462}
463
464/*!
465 * brief De-initialize the Video PLL1.
466 */
467void CLOCK_DeinitVideoPll1(void)
468{
469 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_VideoPll1Ctrl);
470}
471
472/*!
473 * brief Initializes the ANALOG SYS PLL1.
474 *
475 * param config Pointer to the configuration structure(see ref ccm_analog_sscg_pll_config_t enumeration).
476 *
477 * note This function can't detect whether the SYS PLL has been enabled and
478 * used by some IPs.
479 */
480void CLOCK_InitSysPll1(const ccm_analog_sscg_pll_config_t *config)
481{
482 assert(config != NULL);
483
484 /* SSCG PLL configuration */
485 CLOCK_InitSSCGPll(CCM_ANALOG, config, kCLOCK_SystemPll1Ctrl);
486 /* Disable PLL bypass */
487 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll1InternalPll1BypassCtrl, false);
488 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll1InternalPll2BypassCtrl, false);
489 /* Enable and power up PLL clock. */
490 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_SystemPll1Clke);
491
492 /* Wait for PLL to be locked. */
493 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_SystemPll1Ctrl))
494 {
495 }
496}
497
498/*!
499 * brief De-initialize the System PLL1.
500 */
501void CLOCK_DeinitSysPll1(void)
502{
503 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_SystemPll1Ctrl);
504}
505
506/*!
507 * brief Initializes the ANALOG SYS PLL2.
508 *
509 * param config Pointer to the configuration structure(see ref ccm_analog_sscg_pll_config_t enumeration).
510 *
511 * note This function can't detect whether the SYS PLL has been enabled and
512 * used by some IPs.
513 */
514void CLOCK_InitSysPll2(const ccm_analog_sscg_pll_config_t *config)
515{
516 assert(config != NULL);
517
518 /* SSCG PLL configuration */
519 CLOCK_InitSSCGPll(CCM_ANALOG, config, kCLOCK_SystemPll2Ctrl);
520 /* Disable PLL bypass */
521 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll2InternalPll1BypassCtrl, false);
522 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll2InternalPll2BypassCtrl, false);
523 /* Enable and power up PLL clock. */
524 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_SystemPll2Clke);
525
526 /* Wait for PLL to be locked. */
527 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_SystemPll2Ctrl))
528 {
529 }
530}
531
532/*!
533 * brief De-initialize the System PLL2.
534 */
535void CLOCK_DeinitSysPll2(void)
536{
537 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_SystemPll2Ctrl);
538}
539
540/*!
541 * brief Initializes the ANALOG SYS PLL3.
542 *
543 * param config Pointer to the configuration structure(see ref ccm_analog_sscg_pll_config_t enumeration).
544 *
545 * note This function can't detect whether the SYS PLL has been enabled and
546 * used by some IPs.
547 */
548void CLOCK_InitSysPll3(const ccm_analog_sscg_pll_config_t *config)
549{
550 assert(config != NULL);
551
552 /* SSCG PLL configuration */
553 CLOCK_InitSSCGPll(CCM_ANALOG, config, kCLOCK_SystemPll3Ctrl);
554 /* Disable PLL bypass */
555 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll3InternalPll1BypassCtrl, false);
556 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll3InternalPll2BypassCtrl, false);
557 /* Enable and power up PLL clock. */
558 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_SystemPll3Clke);
559
560 /* Wait for PLL to be locked. */
561 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_SystemPll3Ctrl))
562 {
563 }
564}
565
566/*!
567 * brief De-initialize the System PLL3.
568 */
569void CLOCK_DeinitSysPll3(void)
570{
571 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_SystemPll3Ctrl);
572}
573
574/*!
575 * brief Initializes the ANALOG DDR PLL.
576 *
577 * param config Pointer to the configuration structure(see ref ccm_analog_sscg_pll_config_t enumeration).
578 *
579 * note This function can't detect whether the DDR PLL has been enabled and
580 * used by some IPs.
581 */
582void CLOCK_InitDramPll(const ccm_analog_sscg_pll_config_t *config)
583{
584 assert(config != NULL);
585
586 /* init SSCG pll */
587 CLOCK_InitSSCGPll(CCM_ANALOG, config, kCLOCK_DramPllCtrl);
588 /* Disable PLL bypass */
589 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_DramPllInternalPll1BypassCtrl, false);
590 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_DramPllInternalPll2BypassCtrl, false);
591 /* Enable and power up PLL clock. */
592 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_DramPllClke);
593
594 /* make sure DDR is release from reset, DDR1 should be assigned to special domain first */
595 /* trigger the DDR1 power up */
596 GPC->PU_PGC_SW_PUP_REQ |= GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_MASK;
597 /* release DDR1 from reset status */
598 SRC->DDRC2_RCR = (SRC->DDRC2_RCR & (~(SRC_DDRC2_RCR_DDRC1_PHY_PWROKIN_MASK | SRC_DDRC2_RCR_DDRC1_PHY_RESET_MASK |
599 SRC_DDRC2_RCR_DDRC2_CORE_RST_MASK | SRC_DDRC2_RCR_DDRC2_PRST_MASK))) |
600 SRC_DDRC2_RCR_DOM_EN_MASK | SRC_DDRC2_RCR_DOMAIN3_MASK | SRC_DDRC2_RCR_DOMAIN2_MASK |
601 SRC_DDRC2_RCR_DOMAIN1_MASK | SRC_DDRC2_RCR_DOMAIN0_MASK;
602
603 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_DramPllCtrl))
604 {
605 }
606}
607
608/*!
609 * brief De-initialize the Dram PLL.
610 */
611void CLOCK_DeinitDramPll(void)
612{
613 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_DramPllCtrl);
614}
615
616/*!
617 * brief Initializes the ANALOG VIDEO PLL2.
618 *
619 * param config Pointer to the configuration structure(see ref ccm_analog_sscg_pll_config_t enumeration).
620 *
621 * note This function can't detect whether the VIDEO PLL has been enabled and
622 * used by some IPs.
623 */
624void CLOCK_InitVideoPll2(const ccm_analog_sscg_pll_config_t *config)
625{
626 assert(config != NULL);
627
628 /* init SSCG pll */
629 CLOCK_InitSSCGPll(CCM_ANALOG, config, kCLOCK_VideoPll2Ctrl);
630
631 /* Disable PLL bypass */
632 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_VideoPll2InternalPll1BypassCtrl, false);
633 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_VideoPll2InternalPll2BypassCtrl, false);
634 /* Enable and power up PLL clock. */
635 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_VideoPll2Clke);
636
637 /* Wait for PLL to be locked. */
638 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_VideoPll2Ctrl))
639 {
640 }
641}
642
643/*!
644 * brief De-initialize the Video PLL2.
645 */
646void CLOCK_DeinitVideoPll2(void)
647{
648 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_VideoPll2Ctrl);
649}
650
651/*!
652 * brief Initializes the ANALOG Fractional PLL.
653 *
654 * param base CCM ANALOG base address.
655 * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration).
656 * param type fractional pll type.
657 *
658 */
659void CLOCK_InitFracPll(CCM_ANALOG_Type *base, const ccm_analog_frac_pll_config_t *config, clock_pll_ctrl_t type)
660{
661 assert(config != NULL);
662 assert((config->refDiv != 0U) && (config->outDiv != 0U));
663 assert((config->outDiv % 2U) == 0U);
664 assert(type <= kCLOCK_ArmPllCtrl);
665
666 uint32_t fracCfg0 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) | CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_MASK;
667 uint32_t fracCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 4U);
668
669 /* power down the fractional PLL first */
670 CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) = fracCfg0;
671
672 CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) =
673 (fracCfg0 &
674 (~(CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK | CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK |
675 CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_MASK | CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL_MASK))) |
676 (CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL((uint32_t)(config->outDiv) / 2U - 1U)) |
677 (CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL((uint32_t)(config->refDiv) - 1U)) |
678 CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL(config->refSel);
679
680 CCM_ANALOG_TUPLE_REG_OFF(base, type, 4U) =
681 (fracCfg1 &
682 (~(CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK | CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK))) |
683 CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL(config->intDiv) |
684 CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL(config->fractionDiv);
685
686 /* NEW_DIV_VAL */
687 CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) |= CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL_MASK;
688
689 /* power up the fractional pll */
690 CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) &= ~CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_MASK;
691
692 /* need to check NEW_DIV_ACK */
693 while ((CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_ACK_MASK) == 0U)
694 {
695 }
696}
697
698/*!
699 * brief Gets the ANALOG Fractional PLL clock frequency.
700 *
701 * param base CCM_ANALOG base pointer.
702 * param type fractional pll type.
703 * param fractional pll reference clock frequency
704 *
705 * return Clock frequency
706 */
707uint32_t CLOCK_GetFracPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq)
708{
709 assert(type <= kCLOCK_ArmPllCtrl);
710
711 uint32_t fracCfg0 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U);
712 uint32_t fracCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 4U);
713 uint64_t fracClk = 0U;
714
715 uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK,
716 CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_SHIFT);
717 uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK,
718 CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT);
719 uint32_t fracDiv = CCM_BIT_FIELD_EXTRACTION(fracCfg1, CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK,
720 CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_SHIFT);
721 uint8_t intDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg1, CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK,
722 CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_SHIFT);
723
724 refClkFreq /= (uint32_t)refDiv + 1UL;
725 fracClk = (uint64_t)refClkFreq * 8U * (1U + intDiv) + (((uint64_t)refClkFreq * 8U * fracDiv) >> 24U);
726
727 return (uint32_t)(fracClk / (((uint64_t)outDiv + 1U) * 2U));
728}
729
730/*!
731 * brief Initializes the ANALOG SSCG PLL.
732 *
733 * param base CCM ANALOG base address
734 * param config Pointer to the configuration structure(see ref ccm_analog_sscg_pll_config_t enumeration).
735 * param type sscg pll type
736 *
737 */
738void CLOCK_InitSSCGPll(CCM_ANALOG_Type *base, const ccm_analog_sscg_pll_config_t *config, clock_pll_ctrl_t type)
739{
740 assert(config != NULL);
741 assert(config->refDiv1 != 0U);
742 assert(config->refDiv2 != 0U);
743 assert(config->outDiv != 0U);
744 assert(config->loopDivider1 != 0U);
745 assert(config->loopDivider2 != 0U);
746 assert(type >= kCLOCK_SystemPll1Ctrl);
747
748 uint32_t sscgCfg0 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) | CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_MASK;
749 uint32_t sscgCfg2 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 8U);
750 uint32_t pll1Filter = 0U;
751
752 /* power down the SSCG PLL first */
753 CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) = sscgCfg0;
754
755 /* pll mux configuration */
756 CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) =
757 (sscgCfg0 & (~CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_MASK)) | config->refSel;
758
759 /* reserve CFG1, spread spectrum */
760
761 /* match the PLL1 input clock range with PLL filter range */
762 if ((CLOCK_GetPllRefClkFreq(type) / (config->refDiv1)) > SSCG_PLL1_FILTER_RANGE)
763 {
764 pll1Filter = 1U;
765 }
766 /* divider configuration */
767 CCM_ANALOG_TUPLE_REG_OFF(base, type, 8U) =
768 (sscgCfg2 &
769 (~(CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_MASK | CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_MASK |
770 CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_MASK | CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK |
771 CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_MASK))) |
772 CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL((uint32_t)(config->outDiv) - 1U) |
773 CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2(config->loopDivider2 - 1U) |
774 CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1(config->loopDivider1 - 1U) |
775 CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2((uint32_t)(config->refDiv2) - 1U) |
776 CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1((uint32_t)(config->refDiv1) - 1U) | pll1Filter;
777
778 /* power up the SSCG PLL */
779 CCM_ANALOG_TUPLE_REG_OFF(base, type, 0U) &= ~CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_MASK;
780}
781
782/*!
783 * brief Get the ANALOG SSCG PLL clock frequency.
784 *
785 * param base CCM ANALOG base address.
786 * param type sscg pll type
787 * param pll1Bypass pll1 bypass flag
788 *
789 * return Clock frequency
790 */
791uint32_t CLOCK_GetSSCGPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq, bool pll1Bypass)
792{
793 assert(type >= kCLOCK_SystemPll1Ctrl);
794
795 uint32_t sscgCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 4U);
796 uint32_t sscgCfg2 = CCM_ANALOG_TUPLE_REG_OFF(base, type, 8U);
797 uint64_t pll2InputClock = 0U;
798
799 uint8_t refDiv1 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_MASK,
800 CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_SHIFT) +
801 1U;
802 uint8_t refDiv2 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK,
803 CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_SHIFT) +
804 1U;
805 uint8_t divf1 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_MASK,
806 CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_SHIFT) +
807 1U;
808 uint8_t divf2 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_MASK,
809 CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_SHIFT) +
810 1U;
811 uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_MASK,
812 CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT) +
813 1U;
814
815 refClkFreq /= refDiv1;
816
817 if (pll1Bypass)
818 {
819 pll2InputClock = refClkFreq;
820 }
821 else if ((sscgCfg1 & CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE_MASK) != 0U)
822 {
823 pll2InputClock = (uint64_t)refClkFreq * 8U * divf1 / refDiv2;
824 }
825 else
826 {
827 pll2InputClock = (uint64_t)refClkFreq * 2U * divf1 / refDiv2;
828 }
829
830 return (uint32_t)(pll2InputClock * divf2 / outDiv);
831}
832
833/*!
834 * brief Set root clock divider
835 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
836 *
837 * param ccmRootClk Root control (see ref clock_root_control_t enumeration)
838 * param pre Pre divider value (1-8)
839 * param post Post divider value (1-64)
840 */
841void CLOCK_SetRootDivider(clock_root_control_t ccmRootClk, uint32_t pre, uint32_t post)
842{
843 assert((pre <= 8U) && (pre != 0U));
844 assert((post <= 64U) && (post != 0U));
845
846 CCM_REG(ccmRootClk) = (CCM_REG(ccmRootClk) & (~(CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_POST_PODF_MASK))) |
847 CCM_TARGET_ROOT_PRE_PODF(pre - 1U) | CCM_TARGET_ROOT_POST_PODF(post - 1U);
848}
849
850/*!
851 * brief Update clock root in one step, for dynamical clock switching
852 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
853 *
854 * param ccmRootClk Root control (see ref clock_root_control_t enumeration)
855 * param root mux value (see ref _ccm_rootmux_xxx enumeration)
856 * param pre Pre divider value (0-7, divider=n+1)
857 * param post Post divider value (0-63, divider=n+1)
858 */
859void CLOCK_UpdateRoot(clock_root_control_t ccmRootClk, uint32_t mux, uint32_t pre, uint32_t post)
860{
861 assert((pre <= 8U) && (pre != 0U));
862 assert((post <= 64U) && (post != 0U));
863
864 CCM_REG(ccmRootClk) =
865 (CCM_REG(ccmRootClk) &
866 (~(CCM_TARGET_ROOT_MUX_MASK | CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_POST_PODF_MASK))) |
867 CCM_TARGET_ROOT_MUX(mux) | CCM_TARGET_ROOT_PRE_PODF(pre - 1U) | CCM_TARGET_ROOT_POST_PODF(post - 1U);
868}
869
870/*!
871 * brief OSC25M init
872 *
873 * param config osc configuration
874 */
875void CLOCK_InitOSC25M(const osc_config_t *config)
876{
877 assert(config != NULL);
878 assert(config->oscDiv != 0U);
879
880 XTALOSC->OSC25M_CTL_CFG =
881 (XTALOSC->OSC25M_CTL_CFG & (~(XTALOSC_OSC25M_CTL_CFG_OSC_DIV_MASK | XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS_MASK))) |
882 XTALOSC_OSC25M_CTL_CFG_OSC_DIV((uint32_t)(config->oscDiv) - 1U) |
883 XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS(config->oscMode);
884
885 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_OSC25MClke);
886}
887
888/*!
889 * brief OSC25M deinit
890 *
891 */
892void CLOCK_DeinitOSC25M(void)
893{
894 CLOCK_DisableAnalogClock(CCM_ANALOG, kCLOCK_OSC25MClke);
895}
896
897/*!
898 * brief OSC27M init
899 *
900 */
901void CLOCK_InitOSC27M(const osc_config_t *config)
902{
903 assert(config != NULL);
904 assert(config->oscDiv != 0U);
905
906 XTALOSC->OSC27M_CTL_CFG =
907 (XTALOSC->OSC27M_CTL_CFG & (~(XTALOSC_OSC27M_CTL_CFG_OSC_DIV_MASK | XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS_MASK))) |
908 XTALOSC_OSC27M_CTL_CFG_OSC_DIV((uint32_t)(config->oscDiv) - 1U) |
909 XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS(config->oscMode);
910
911 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_OSC27MClke);
912}
913
914/*!
915 * brief OSC27M deinit
916 *
917 * param config osc configuration
918 */
919void CLOCK_DeinitOSC27M(void)
920{
921 CLOCK_DisableAnalogClock(CCM_ANALOG, kCLOCK_OSC27MClke);
922}
923
924/*!
925 * brief Enable CCGR clock gate and root clock gate for each module
926 * User should set specific gate for each module according to the description
927 * of the table of system clocks, gating and override in CCM chapter of
928 * reference manual. Take care of that one module may need to set more than
929 * one clock gate.
930 *
931 * param ccmGate Gate control for each module (see ref clock_ip_name_t enumeration).
932 */
933void CLOCK_EnableClock(clock_ip_name_t ccmGate)
934{
935 uint32_t ccgr = CCM_TUPLE_CCGR(ccmGate);
936 uint32_t rootClk = CCM_TUPLE_ROOT(ccmGate);
937
938 CCM_REG_SET(ccgr) = (uint32_t)kCLOCK_ClockNeededAll;
939 /* if root clock is 0xFFFFU, then skip enable root clock */
940 if (rootClk != 0xFFFFU)
941 {
942 CCM_REG_SET(rootClk) = CCM_TARGET_ROOT_SET_ENABLE_MASK;
943 }
944}
945
946/*!
947 * brief Disable CCGR clock gate for the each module
948 * User should set specific gate for each module according to the description
949 * of the table of system clocks, gating and override in CCM chapter of
950 * reference manual. Take care of that one module may need to set more than
951 * one clock gate.
952 *
953 * param ccmGate Gate control for each module (see ref clock_ip_name_t enumeration).
954 */
955void CLOCK_DisableClock(clock_ip_name_t ccmGate)
956{
957 uint32_t ccgr = CCM_TUPLE_CCGR(ccmGate);
958 uint32_t rootClk = CCM_TUPLE_ROOT(ccmGate);
959
960 CCM_REG(ccgr) = (uint32_t)kCLOCK_ClockNotNeeded;
961
962 /* if root clock is 0xFFFFU, then skip disable root clock */
963 if (rootClk != 0xFFFFU)
964 {
965 CCM_REG_CLR(rootClk) = CCM_TARGET_ROOT_CLR_ENABLE_MASK;
966 }
967}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/drivers/fsl_clock.h
new file mode 100644
index 000000000..4deb75ae3
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/drivers/fsl_clock.h
@@ -0,0 +1,1349 @@
1/*
2 * Copyright 2017 - 2020, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_device_registers.h"
12#include <stdint.h>
13#include <stdbool.h>
14#include <stddef.h>
15#include <assert.h>
16
17/*!
18 * @addtogroup clock
19 * @{
20 */
21
22/*******************************************************************************
23 * Definitions
24 ******************************************************************************/
25
26/*! @name Driver version */
27/*@{*/
28/*! @brief CLOCK driver version 2.3.2. */
29#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
30/*@}*/
31
32/* Definition for delay API in clock driver, users can redefine it to the real application. */
33#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
34#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (400000000UL)
35#endif
36
37/*!
38 * @brief XTAL 25M clock frequency.
39 */
40#define OSC25M_CLK_FREQ 25000000U
41
42/*!
43 * @brief XTAL 27M clock frequency.
44 */
45#define OSC27M_CLK_FREQ 27000000U
46
47/*!
48 * @brief HDMI PHY 27M clock frequency.
49 */
50#define HDMI_PHY_27M_FREQ 27000000U
51
52/*!
53 * @brief clock1PN frequency.
54 */
55#define CLKPN_FREQ 0U
56
57/*! @brief Clock ip name array for ECSPI. */
58#define ECSPI_CLOCKS \
59 { \
60 kCLOCK_IpInvalid, kCLOCK_Ecspi1, kCLOCK_Ecspi2, kCLOCK_Ecspi3, \
61 }
62
63/*! @brief Clock ip name array for GPIO. */
64#define GPIO_CLOCKS \
65 { \
66 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5, \
67 }
68
69/*! @brief Clock ip name array for GPT. */
70#define GPT_CLOCKS \
71 { \
72 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6, \
73 }
74
75/*! @brief Clock ip name array for I2C. */
76#define I2C_CLOCKS \
77 { \
78 kCLOCK_IpInvalid, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, kCLOCK_I2c4, \
79 }
80
81/*! @brief Clock ip name array for IOMUX. */
82#define IOMUX_CLOCKS \
83 { \
84 kCLOCK_Iomux, \
85 }
86
87/*! @brief Clock ip name array for IPMUX. */
88#define IPMUX_CLOCKS \
89 { \
90 kCLOCK_Ipmux1, kCLOCK_Ipmux2, kCLOCK_Ipmux3, kCLOCK_Ipmux4, \
91 }
92
93/*! @brief Clock ip name array for PWM. */
94#define PWM_CLOCKS \
95 { \
96 kCLOCK_IpInvalid, kCLOCK_Pwm1, kCLOCK_Pwm2, kCLOCK_Pwm3, kCLOCK_Pwm4, \
97 }
98
99/*! @brief Clock ip name array for RDC. */
100#define RDC_CLOCKS \
101 { \
102 kCLOCK_Rdc, \
103 }
104
105/*! @brief Clock ip name array for SAI. */
106#define SAI_CLOCKS \
107 { \
108 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_Sai4, kCLOCK_Sai5, kCLOCK_Sai6, \
109 }
110
111/*! @brief Clock ip name array for RDC SEMA42. */
112#define RDC_SEMA42_CLOCKS \
113 { \
114 kCLOCK_IpInvalid, kCLOCK_Sema42_1, kCLOCK_Sema42_2 \
115 }
116
117/*! @brief Clock ip name array for UART. */
118#define UART_CLOCKS \
119 { \
120 kCLOCK_IpInvalid, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, \
121 }
122
123/*! @brief Clock ip name array for USDHC. */
124#define USDHC_CLOCKS \
125 { \
126 kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
127 }
128
129/*! @brief Clock ip name array for WDOG. */
130#define WDOG_CLOCKS \
131 { \
132 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3 \
133 }
134
135/*! @brief Clock ip name array for TEMPSENSOR. */
136#define TMU_CLOCKS \
137 { \
138 kCLOCK_TempSensor, \
139 }
140
141/*! @brief Clock ip name array for SDMA. */
142#define SDMA_CLOCKS \
143 { \
144 kCLOCK_Sdma1, kCLOCK_Sdma2 \
145 }
146
147/*! @brief Clock ip name array for MU. */
148#define MU_CLOCKS \
149 { \
150 kCLOCK_Mu \
151 }
152
153/*! @brief Clock ip name array for QSPI. */
154#define QSPI_CLOCKS \
155 { \
156 kCLOCK_Qspi \
157 }
158
159/*!
160 * @brief CCM reg macros to extract corresponding registers bit field.
161 */
162#define CCM_BIT_FIELD_EXTRACTION(val, mask, shift) (((val) & (mask)) >> (shift))
163
164/*!
165 * @brief CCM reg macros to map corresponding registers.
166 */
167#define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uint32_t)(root) + (off))))
168#define CCM_REG(root) CCM_REG_OFF(root, 0U)
169#define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
170#define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
171
172/*!
173 * @brief CCM Analog registers offset.
174 */
175#define AUDIO_PLL1_CFG0_OFFSET 0x00
176#define AUDIO_PLL2_CFG0_OFFSET 0x08
177#define VIDEO_PLL1_CFG0_OFFSET 0x10
178#define GPU_PLL_CFG0_OFFSET 0x18
179#define VPU_PLL_CFG0_OFFSET 0x20
180#define ARM_PLL_CFG0_OFFSET 0x28
181#define SYS_PLL1_CFG0_OFFSET 0x30
182#define SYS_PLL2_CFG0_OFFSET 0x3C
183#define SYS_PLL3_CFG0_OFFSET 0x48
184#define VIDEO_PLL2_CFG0_OFFSET 0x54
185#define DRAM_PLL_CFG0_OFFSET 0x60
186#define OSC_MISC_CFG_OFFSET 0x70
187
188/*!
189 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
190 */
191#define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFFU) << 16U) | (shift))
192#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)(tuple)) & 0x1FU)
193#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
194 (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFFU) + (off))))
195#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
196
197/*!
198 * @brief CCM CCGR and root tuple
199 */
200#define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root))
201#define CCM_TUPLE_CCGR(tuple) ((uint32_t)(&(CCM)->CCGR[(uint32_t)(tuple) >> 16U].CCGR))
202#define CCM_TUPLE_ROOT(tuple) ((uint32_t)(&(CCM)->ROOT[(uint32_t)(tuple)&0xFFFFU].TARGET_ROOT))
203
204/*! @brief Clock name used to get clock frequency. */
205typedef enum _clock_name
206{
207 kCLOCK_CoreM4Clk, /*!< ARM M4 Core clock */
208
209 kCLOCK_AxiClk, /*!< Main AXI bus clock. */
210 kCLOCK_AhbClk, /*!< AHB bus clock. */
211 kCLOCK_IpgClk, /*!< IPG bus clock. */
212
213 /* -------------------------------- Other clock --------------------------*/
214} clock_name_t;
215
216#define kCLOCK_CoreSysClk kCLOCK_CoreM4Clk /*!< For compatible with other platforms without CCM. */
217#define CLOCK_GetCoreSysClkFreq CLOCK_GetCoreM4Freq /*!< For compatible with other platforms without CCM. */
218
219/*! @brief CCM CCGR gate control. */
220typedef enum _clock_ip_name
221{
222 kCLOCK_IpInvalid = -1,
223
224 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
225
226 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
227
228 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
229 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
230 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
231
232 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
233 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
234 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
235 kCLOCK_Gpio4 = CCM_TUPLE(14U, 33U), /*!< GPIO4 Clock Gate.*/
236 kCLOCK_Gpio5 = CCM_TUPLE(15U, 33U), /*!< GPIO5 Clock Gate.*/
237
238 kCLOCK_Gpt1 = CCM_TUPLE(16U, 107U), /*!< GPT1 Clock Gate.*/
239 kCLOCK_Gpt2 = CCM_TUPLE(17U, 108U), /*!< GPT2 Clock Gate.*/
240 kCLOCK_Gpt3 = CCM_TUPLE(18U, 109U), /*!< GPT3 Clock Gate.*/
241 kCLOCK_Gpt4 = CCM_TUPLE(19U, 110U), /*!< GPT4 Clock Gate.*/
242 kCLOCK_Gpt5 = CCM_TUPLE(20U, 111U), /*!< GPT5 Clock Gate.*/
243 kCLOCK_Gpt6 = CCM_TUPLE(21U, 112U), /*!< GPT6 Clock Gate.*/
244
245 kCLOCK_I2c1 = CCM_TUPLE(23U, 90U), /*!< I2C1 Clock Gate.*/
246 kCLOCK_I2c2 = CCM_TUPLE(24U, 91U), /*!< I2C2 Clock Gate.*/
247 kCLOCK_I2c3 = CCM_TUPLE(25U, 92U), /*!< I2C3 Clock Gate.*/
248 kCLOCK_I2c4 = CCM_TUPLE(26U, 93U), /*!< I2C4 Clock Gate.*/
249
250 kCLOCK_Iomux = CCM_TUPLE(27U, 33U), /*!< IOMUX Clock Gate.*/
251 kCLOCK_Ipmux1 = CCM_TUPLE(28U, 33U), /*!< IPMUX1 Clock Gate.*/
252 kCLOCK_Ipmux2 = CCM_TUPLE(29U, 33U), /*!< IPMUX2 Clock Gate.*/
253 kCLOCK_Ipmux3 = CCM_TUPLE(30U, 33U), /*!< IPMUX3 Clock Gate.*/
254 kCLOCK_Ipmux4 = CCM_TUPLE(31U, 33U), /*!< IPMUX4 Clock Gate.*/
255
256 kCLOCK_M4 = CCM_TUPLE(32U, 1U), /*!< M4 Clock Gate.*/
257
258 kCLOCK_Mu = CCM_TUPLE(33U, 33U), /*!< MU Clock Gate.*/
259
260 kCLOCK_Ocram = CCM_TUPLE(35U, 16U), /*!< OCRAM Clock Gate.*/
261 kCLOCK_OcramS = CCM_TUPLE(36U, 32U), /*!< OCRAM S Clock Gate.*/
262
263 kCLOCK_Pwm1 = CCM_TUPLE(40U, 103U), /*!< PWM1 Clock Gate.*/
264 kCLOCK_Pwm2 = CCM_TUPLE(41U, 104U), /*!< PWM2 Clock Gate.*/
265 kCLOCK_Pwm3 = CCM_TUPLE(42U, 105U), /*!< PWM3 Clock Gate.*/
266 kCLOCK_Pwm4 = CCM_TUPLE(43U, 106U), /*!< PWM4 Clock Gate.*/
267
268 kCLOCK_Qspi = CCM_TUPLE(47U, 87U), /*!< QSPI Clock Gate.*/
269
270 kCLOCK_Rdc = CCM_TUPLE(49U, 33U), /*!< RDC Clock Gate.*/
271
272 kCLOCK_Sai1 = CCM_TUPLE(51U, 75U), /*!< SAI1 Clock Gate.*/
273 kCLOCK_Sai2 = CCM_TUPLE(52U, 76U), /*!< SAI2 Clock Gate.*/
274 kCLOCK_Sai3 = CCM_TUPLE(53U, 77U), /*!< SAI3 Clock Gate.*/
275 kCLOCK_Sai4 = CCM_TUPLE(54U, 78U), /*!< SAI4 Clock Gate.*/
276 kCLOCK_Sai5 = CCM_TUPLE(55U, 79U), /*!< SAI5 Clock Gate.*/
277 kCLOCK_Sai6 = CCM_TUPLE(56U, 80U), /*!< SAI6 Clock Gate.*/
278
279 kCLOCK_Sdma1 = CCM_TUPLE(58U, 33U), /*!< SDMA1 Clock Gate.*/
280 kCLOCK_Sdma2 = CCM_TUPLE(59U, 35U), /*!< SDMA2 Clock Gate.*/
281
282 kCLOCK_Sec_Debug = CCM_TUPLE(60U, 33U), /*!< SEC_DEBUG Clock Gate.*/
283
284 kCLOCK_Sema42_1 = CCM_TUPLE(61U, 33U), /*!< RDC SEMA42 Clock Gate.*/
285 kCLOCK_Sema42_2 = CCM_TUPLE(62U, 33U), /*!< RDC SEMA42 Clock Gate.*/
286
287 kCLOCK_Sim_display = CCM_TUPLE(63U, 16U), /*!< SIM_Display Clock Gate.*/
288 kCLOCK_Sim_m = CCM_TUPLE(65U, 32U), /*!< SIM_M Clock Gate.*/
289 kCLOCK_Sim_main = CCM_TUPLE(66U, 16U), /*!< SIM_MAIN Clock Gate.*/
290 kCLOCK_Sim_s = CCM_TUPLE(67U, 32U), /*!< SIM_S Clock Gate.*/
291 kCLOCK_Sim_wakeup = CCM_TUPLE(68U, 32U), /*!< SIM_WAKEUP Clock Gate.*/
292
293 kCLOCK_Uart1 = CCM_TUPLE(73U, 94U), /*!< UART1 Clock Gate.*/
294 kCLOCK_Uart2 = CCM_TUPLE(74U, 95U), /*!< UART2 Clock Gate.*/
295 kCLOCK_Uart3 = CCM_TUPLE(75U, 96U), /*!< UART3 Clock Gate.*/
296 kCLOCK_Uart4 = CCM_TUPLE(76U, 97U), /*!< UART4 Clock Gate.*/
297
298 kCLOCK_Wdog1 = CCM_TUPLE(83U, 114U), /*!< WDOG1 Clock Gate.*/
299 kCLOCK_Wdog2 = CCM_TUPLE(84U, 114U), /*!< WDOG2 Clock Gate.*/
300 kCLOCK_Wdog3 = CCM_TUPLE(85U, 114U), /*!< WDOG3 Clock Gate.*/
301
302 kCLOCK_TempSensor = CCM_TUPLE(98U, 0xFFFF), /*!< TempSensor Clock Gate.*/
303
304} clock_ip_name_t;
305
306/*! @brief ccm root name used to get clock frequency. */
307typedef enum _clock_root_control
308{
309 kCLOCK_RootM4 = (uint32_t)(&(CCM)->ROOT[1].TARGET_ROOT), /*!< ARM Cortex-M4 Clock control name.*/
310 kCLOCK_RootAxi = (uint32_t)(&(CCM)->ROOT[16].TARGET_ROOT), /*!< AXI Clock control name.*/
311 kCLOCK_RootNoc = (uint32_t)(&(CCM)->ROOT[26].TARGET_ROOT), /*!< NOC Clock control name.*/
312 kCLOCK_RootAhb = (uint32_t)(&(CCM)->ROOT[32].TARGET_ROOT), /*!< AHB Clock control name.*/
313 kCLOCK_RootIpg = (uint32_t)(&(CCM)->ROOT[33].TARGET_ROOT), /*!< IPG Clock control name.*/
314 kCLOCK_RootDramAlt = (uint32_t)(&(CCM)->ROOT[64].TARGET_ROOT), /*!< DRAM ALT Clock control name.*/
315
316 kCLOCK_RootSai1 = (uint32_t)(&(CCM)->ROOT[75].TARGET_ROOT), /*!< SAI1 Clock control name.*/
317 kCLOCK_RootSai2 = (uint32_t)(&(CCM)->ROOT[76].TARGET_ROOT), /*!< SAI2 Clock control name.*/
318 kCLOCK_RootSai3 = (uint32_t)(&(CCM)->ROOT[77].TARGET_ROOT), /*!< SAI3 Clock control name.*/
319 kCLOCK_RootSai4 = (uint32_t)(&(CCM)->ROOT[78].TARGET_ROOT), /*!< SAI4 Clock control name.*/
320 kCLOCK_RootSai5 = (uint32_t)(&(CCM)->ROOT[79].TARGET_ROOT), /*!< SAI5 Clock control name.*/
321 kCLOCK_RootSai6 = (uint32_t)(&(CCM)->ROOT[80].TARGET_ROOT), /*!< SAI6 Clock control name.*/
322
323 kCLOCK_RootQspi = (uint32_t)(&(CCM)->ROOT[87].TARGET_ROOT), /*!< QSPI Clock control name.*/
324
325 kCLOCK_RootI2c1 = (uint32_t)(&(CCM)->ROOT[90].TARGET_ROOT), /*!< I2C1 Clock control name.*/
326 kCLOCK_RootI2c2 = (uint32_t)(&(CCM)->ROOT[91].TARGET_ROOT), /*!< I2C2 Clock control name.*/
327 kCLOCK_RootI2c3 = (uint32_t)(&(CCM)->ROOT[92].TARGET_ROOT), /*!< I2C3 Clock control name.*/
328 kCLOCK_RootI2c4 = (uint32_t)(&(CCM)->ROOT[93].TARGET_ROOT), /*!< I2C4 Clock control name.*/
329
330 kCLOCK_RootUart1 = (uint32_t)(&(CCM)->ROOT[94].TARGET_ROOT), /*!< UART1 Clock control name.*/
331 kCLOCK_RootUart2 = (uint32_t)(&(CCM)->ROOT[95].TARGET_ROOT), /*!< UART2 Clock control name.*/
332 kCLOCK_RootUart3 = (uint32_t)(&(CCM)->ROOT[96].TARGET_ROOT), /*!< UART3 Clock control name.*/
333 kCLOCK_RootUart4 = (uint32_t)(&(CCM)->ROOT[97].TARGET_ROOT), /*!< UART4 Clock control name.*/
334
335 kCLOCK_RootEcspi1 = (uint32_t)(&(CCM)->ROOT[101].TARGET_ROOT), /*!< ECSPI1 Clock control name.*/
336 kCLOCK_RootEcspi2 = (uint32_t)(&(CCM)->ROOT[102].TARGET_ROOT), /*!< ECSPI2 Clock control name.*/
337 kCLOCK_RootEcspi3 = (uint32_t)(&(CCM)->ROOT[131].TARGET_ROOT), /*!< ECSPI3 Clock control name.*/
338
339 kCLOCK_RootPwm1 = (uint32_t)(&(CCM)->ROOT[103].TARGET_ROOT), /*!< PWM1 Clock control name.*/
340 kCLOCK_RootPwm2 = (uint32_t)(&(CCM)->ROOT[104].TARGET_ROOT), /*!< PWM2 Clock control name.*/
341 kCLOCK_RootPwm3 = (uint32_t)(&(CCM)->ROOT[105].TARGET_ROOT), /*!< PWM3 Clock control name.*/
342 kCLOCK_RootPwm4 = (uint32_t)(&(CCM)->ROOT[106].TARGET_ROOT), /*!< PWM4 Clock control name.*/
343
344 kCLOCK_RootGpt1 = (uint32_t)(&(CCM)->ROOT[107].TARGET_ROOT), /*!< GPT1 Clock control name.*/
345 kCLOCK_RootGpt2 = (uint32_t)(&(CCM)->ROOT[108].TARGET_ROOT), /*!< GPT2 Clock control name.*/
346 kCLOCK_RootGpt3 = (uint32_t)(&(CCM)->ROOT[109].TARGET_ROOT), /*!< GPT3 Clock control name.*/
347 kCLOCK_RootGpt4 = (uint32_t)(&(CCM)->ROOT[110].TARGET_ROOT), /*!< GPT4 Clock control name.*/
348 kCLOCK_RootGpt5 = (uint32_t)(&(CCM)->ROOT[111].TARGET_ROOT), /*!< GPT5 Clock control name.*/
349 kCLOCK_RootGpt6 = (uint32_t)(&(CCM)->ROOT[112].TARGET_ROOT), /*!< GPT6 Clock control name.*/
350
351 kCLOCK_RootWdog = (uint32_t)(&(CCM)->ROOT[114].TARGET_ROOT), /*!< WDOG Clock control name.*/
352} clock_root_control_t;
353
354/*! @brief Root clock select enumeration for ARM Cortex-M4 core. */
355typedef enum _clock_rootmux_m4_clk_sel
356{
357 kCLOCK_M4RootmuxOsc25m = 0U, /*!< ARM Cortex-M4 Clock from OSC 25M.*/
358 kCLOCK_M4RootmuxSysPll2Div5 = 1U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL2 divided by 5.*/
359 kCLOCK_M4RootmuxSysPll2Div4 = 2U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL2 divided by 4.*/
360 kCLOCK_M4RootmuxSysPll1Div3 = 3U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL1 divided by 3.*/
361 kCLOCK_M4RootmuxSysPll1 = 4U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL1.*/
362 kCLOCK_M4RootmuxAudioPll1 = 5U, /*!< ARM Cortex-M4 Clock from AUDIO PLL1.*/
363 kCLOCK_M4RootmuxVideoPll1 = 6U, /*!< ARM Cortex-M4 Clock from VIDEO PLL1.*/
364 kCLOCK_M4RootmuxSysPll3 = 7U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL3.*/
365} clock_rootmux_m4_clk_sel_t;
366
367/*! @brief Root clock select enumeration for AXI bus. */
368typedef enum _clock_rootmux_axi_clk_sel
369{
370 kCLOCK_AxiRootmuxOsc25m = 0U, /*!< ARM AXI Clock from OSC 25M.*/
371 kCLOCK_AxiRootmuxSysPll2Div3 = 1U, /*!< ARM AXI Clock from SYSTEM PLL2 divided by 3.*/
372 kCLOCK_AxiRootmuxSysPll1 = 2U, /*!< ARM AXI Clock from SYSTEM PLL1.*/
373 kCLOCK_AxiRootmuxSysPll2Div4 = 3U, /*!< ARM AXI Clock from SYSTEM PLL2 divided by 4.*/
374 kCLOCK_AxiRootmuxSysPll2 = 4U, /*!< ARM AXI Clock from SYSTEM PLL2.*/
375 kCLOCK_AxiRootmuxAudioPll1 = 5U, /*!< ARM AXI Clock from AUDIO PLL1.*/
376 kCLOCK_AxiRootmuxVideoPll1 = 6U, /*!< ARM AXI Clock from VIDEO PLL1.*/
377 kCLOCK_AxiRootmuxSysPll1Div8 = 7U, /*!< ARM AXI Clock from SYSTEM PLL1 divided by 8.*/
378} clock_rootmux_axi_clk_sel_t;
379
380/*! @brief Root clock select enumeration for AHB bus. */
381typedef enum _clock_rootmux_ahb_clk_sel
382{
383 kCLOCK_AhbRootmuxOsc25m = 0U, /*!< ARM AHB Clock from OSC 25M.*/
384 kCLOCK_AhbRootmuxSysPll1Div6 = 1U, /*!< ARM AHB Clock from SYSTEM PLL1 divided by 6.*/
385 kCLOCK_AhbRootmuxSysPll1 = 2U, /*!< ARM AHB Clock from SYSTEM PLL1.*/
386 kCLOCK_AhbRootmuxSysPll1Div2 = 3U, /*!< ARM AHB Clock from SYSTEM PLL1 divided by 2.*/
387 kCLOCK_AhbRootmuxSysPll2Div8 = 4U, /*!< ARM AHB Clock from SYSTEM PLL2 divided by 8.*/
388 kCLOCK_AhbRootmuxSysPll3 = 5U, /*!< ARM AHB Clock from SYSTEM PLL3.*/
389 kCLOCK_AhbRootmuxAudioPll1 = 6U, /*!< ARM AHB Clock from AUDIO PLL1.*/
390 kCLOCK_AhbRootmuxVideoPll1 = 7U, /*!< ARM AHB Clock from VIDEO PLL1.*/
391} clock_rootmux_ahb_clk_sel_t;
392
393/*! @brief Root clock select enumeration for QSPI peripheral. */
394typedef enum _clock_rootmux_qspi_clk_sel
395{
396 kCLOCK_QspiRootmuxOsc25m = 0U, /*!< ARM QSPI Clock from OSC 25M.*/
397 kCLOCK_QspiRootmuxSysPll1Div2 = 1U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 2.*/
398 kCLOCK_QspiRootmuxSysPll1 = 2U, /*!< ARM QSPI Clock from SYSTEM PLL1.*/
399 kCLOCK_QspiRootmuxSysPll2Div2 = 3U, /*!< ARM QSPI Clock from SYSTEM PLL2 divided by 2.*/
400 kCLOCK_QspiRootmuxAudioPll2 = 4, /*!< ARM QSPI Clock from AUDIO PLL2.*/
401 kCLOCK_QspiRootmuxSysPll1Div3 = 5U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 3 */
402 kCLOCK_QspiRootmuxSysPll3 = 6U, /*!< ARM QSPI Clock from SYSTEM PLL3.*/
403 kCLOCK_QspiRootmuxSysPll1Div8 = 7U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 8.*/
404} clock_rootmux_qspi_clk_sel_t;
405
406/*! @brief Root clock select enumeration for ECSPI peripheral. */
407typedef enum _clock_rootmux_ecspi_clk_sel
408{
409 kCLOCK_EcspiRootmuxOsc25m = 0U, /*!< ECSPI Clock from OSC 25M.*/
410 kCLOCK_EcspiRootmuxSysPll2Div5 = 1U, /*!< ECSPI Clock from SYSTEM PLL2 divided by 5.*/
411 kCLOCK_EcspiRootmuxSysPll1Div20 = 2U, /*!< ECSPI Clock from SYSTEM PLL1 divided by 20.*/
412 kCLOCK_EcspiRootmuxSysPll1Div5 = 3U, /*!< ECSPI Clock from SYSTEM PLL1 divided by 5.*/
413 kCLOCK_EcspiRootmuxSysPll1 = 4U, /*!< ECSPI Clock from SYSTEM PLL1.*/
414 kCLOCK_EcspiRootmuxSysPll3 = 5U, /*!< ECSPI Clock from SYSTEM PLL3.*/
415 kCLOCK_EcspiRootmuxSysPll2Div4 = 6U, /*!< ECSPI Clock from SYSTEM PLL2 divided by 4.*/
416 kCLOCK_EcspiRootmuxAudioPll2 = 7U, /*!< ECSPI Clock from AUDIO PLL2.*/
417} clock_rootmux_ecspi_clk_sel_t;
418
419/*! @brief Root clock select enumeration for I2C peripheral. */
420typedef enum _clock_rootmux_i2c_clk_sel
421{
422 kCLOCK_I2cRootmuxOsc25m = 0U, /*!< I2C Clock from OSC 25M.*/
423 kCLOCK_I2cRootmuxSysPll1Div5 = 1U, /*!< I2C Clock from SYSTEM PLL1 divided by 5.*/
424 kCLOCK_I2cRootmuxSysPll2Div20 = 2U, /*!< I2C Clock from SYSTEM PLL2 divided by 20.*/
425 kCLOCK_I2cRootmuxSysPll3 = 3U, /*!< I2C Clock from SYSTEM PLL3 .*/
426 kCLOCK_I2cRootmuxAudioPll1 = 4U, /*!< I2C Clock from AUDIO PLL1.*/
427 kCLOCK_I2cRootmuxVideoPll1 = 5U, /*!< I2C Clock from VIDEO PLL1.*/
428 kCLOCK_I2cRootmuxAudioPll2 = 6U, /*!< I2C Clock from AUDIO PLL2.*/
429 kCLOCK_I2cRootmuxSysPll1Div6 = 7U, /*!< I2C Clock from SYSTEM PLL1 divided by 6.*/
430} clock_rootmux_i2c_clk_sel_t;
431
432/*! @brief Root clock select enumeration for UART peripheral. */
433typedef enum _clock_rootmux_uart_clk_sel
434{
435 kCLOCK_UartRootmuxOsc25m = 0U, /*!< UART Clock from OSC 25M.*/
436 kCLOCK_UartRootmuxSysPll1Div10 = 1U, /*!< UART Clock from SYSTEM PLL1 divided by 10.*/
437 kCLOCK_UartRootmuxSysPll2Div5 = 2U, /*!< UART Clock from SYSTEM PLL2 divided by 5.*/
438 kCLOCK_UartRootmuxSysPll2Div10 = 3U, /*!< UART Clock from SYSTEM PLL2 divided by 10.*/
439 kCLOCK_UartRootmuxSysPll3 = 4U, /*!< UART Clock from SYSTEM PLL3.*/
440 kCLOCK_UartRootmuxExtClk2 = 5U, /*!< UART Clock from External Clock 2.*/
441 kCLOCK_UartRootmuxExtClk34 = 6U, /*!< UART Clock from External Clock 3, External Clock 4.*/
442 kCLOCK_UartRootmuxAudioPll2 = 7U, /*!< UART Clock from Audio PLL2.*/
443} clock_rootmux_uart_clk_sel_t;
444
445/*! @brief Root clock select enumeration for GPT peripheral. */
446typedef enum _clock_rootmux_gpt
447{
448 kCLOCK_GptRootmuxOsc25m = 0U, /*!< GPT Clock from OSC 25M.*/
449 kCLOCK_GptRootmuxSystemPll2Div10 = 1U, /*!< GPT Clock from SYSTEM PLL2 divided by 10.*/
450 kCLOCK_GptRootmuxSysPll1Div2 = 2U, /*!< GPT Clock from SYSTEM PLL1 divided by 2.*/
451 kCLOCK_GptRootmuxSysPll1Div20 = 3U, /*!< GPT Clock from SYSTEM PLL1 divided by 20.*/
452 kCLOCK_GptRootmuxVideoPll1 = 4U, /*!< GPT Clock from VIDEO PLL1.*/
453 kCLOCK_GptRootmuxSystemPll1Div10 = 5U, /*!< GPT Clock from SYSTEM PLL1 divided by 10.*/
454 kCLOCK_GptRootmuxAudioPll1 = 6U, /*!< GPT Clock from AUDIO PLL1.*/
455 kCLOCK_GptRootmuxExtClk123 = 7U, /*!< GPT Clock from External Clock1, External Clock2, External Clock3.*/
456} clock_rootmux_gpt_t;
457
458/*! @brief Root clock select enumeration for WDOG peripheral. */
459typedef enum _clock_rootmux_wdog_clk_sel
460{
461 kCLOCK_WdogRootmuxOsc25m = 0U, /*!< WDOG Clock from OSC 25M.*/
462 kCLOCK_WdogRootmuxSysPll1Div6 = 1U, /*!< WDOG Clock from SYSTEM PLL1 divided by 6.*/
463 kCLOCK_WdogRootmuxSysPll1Div5 = 2U, /*!< WDOG Clock from SYSTEM PLL1 divided by 5.*/
464 kCLOCK_WdogRootmuxVpuPll = 3U, /*!< WDOG Clock from VPU DLL.*/
465 kCLOCK_WdogRootmuxSystemPll2Div8 = 4U, /*!< WDOG Clock from SYSTEM PLL2 divided by 8.*/
466 kCLOCK_WdogRootmuxSystemPll3 = 5U, /*!< WDOG Clock from SYSTEM PLL3.*/
467 kCLOCK_WdogRootmuxSystemPll1Div10 = 6U, /*!< WDOG Clock from SYSTEM PLL1 divided by 10.*/
468 kCLOCK_WdogRootmuxSystemPll2Div6 = 7U, /*!< WDOG Clock from SYSTEM PLL2 divided by 6.*/
469} clock_rootmux_wdog_clk_sel_t;
470
471/*! @brief Root clock select enumeration for PWM peripheral. */
472typedef enum _clock_rootmux_pwm_clk_sel
473{
474 kCLOCK_PwmRootmuxOsc25m = 0U, /*!< PWM Clock from OSC 25M.*/
475 kCLOCK_PwmRootmuxSysPll2Div10 = 1U, /*!< PWM Clock from SYSTEM PLL2 divided by 10.*/
476 kCLOCK_PwmRootmuxSysPll1Div5 = 2U, /*!< PWM Clock from SYSTEM PLL1 divided by 5.*/
477 kCLOCK_PwmRootmuxSysPll1Div20 = 3U, /*!< PWM Clock from SYSTEM PLL1 divided by 20.*/
478 kCLOCK_PwmRootmuxSystemPll3 = 4U, /*!< PWM Clock from SYSTEM PLL3.*/
479 kCLOCK_PwmRootmuxExtClk12 = 5U, /*!< PWM Clock from External Clock1, External Clock2.*/
480 kCLOCK_PwmRootmuxSystemPll1Div10 = 6U, /*!< PWM Clock from SYSTEM PLL1 divided by 10.*/
481 kCLOCK_PwmRootmuxVideoPll1 = 7U, /*!< PWM Clock from VIDEO PLL1.*/
482} clock_rootmux_Pwm_clk_sel_t;
483
484/*! @brief Root clock select enumeration for SAI peripheral. */
485typedef enum _clock_rootmux_sai_clk_sel
486{
487 kCLOCK_SaiRootmuxOsc25m = 0U, /*!< SAI Clock from OSC 25M.*/
488 kCLOCK_SaiRootmuxAudioPll1 = 1U, /*!< SAI Clock from AUDIO PLL1.*/
489 kCLOCK_SaiRootmuxAudioPll2 = 2U, /*!< SAI Clock from AUDIO PLL2.*/
490 kCLOCK_SaiRootmuxVideoPll1 = 3U, /*!< SAI Clock from VIDEO PLL1.*/
491 kCLOCK_SaiRootmuxSysPll1Div6 = 4U, /*!< SAI Clock from SYSTEM PLL1 divided by 6.*/
492 kCLOCK_SaiRootmuxOsc27m = 5U, /*!< SAI Clock from OSC 27M.*/
493 kCLOCK_SaiRootmuxExtClk123 = 6U, /*!< SAI Clock from External Clock1, External Clock2, External Clock3.*/
494 kCLOCK_SaiRootmuxExtClk234 = 7U, /*!< SAI Clock from External Clock2, External Clock3, External Clock4.*/
495} clock_rootmux_sai_clk_sel_t;
496
497/*! @brief Root clock select enumeration for NOC CLK. */
498typedef enum _clock_rootmux_noc_clk_sel
499{
500 kCLOCK_NocRootmuxOsc25m = 0U, /*!< NOC Clock from OSC 25M.*/
501 kCLOCK_NocRootmuxSysPll1 = 1U, /*!< NOC Clock from SYSTEM PLL1.*/
502 kCLOCK_NocRootmuxSysPll3 = 2U, /*!< NOC Clock from SYSTEM PLL3.*/
503 kCLOCK_NocRootmuxSysPll2 = 3U, /*!< NOC Clock from SYSTEM PLL2.*/
504 kCLOCK_NocRootmuxSysPll2Div2 = 4U, /*!< NOC Clock from SYSTEM PLL2 divided by 2.*/
505 kCLOCK_NocRootmuxAudioPll1 = 5U, /*!< NOC Clock from AUDIO PLL1.*/
506 kCLOCK_NocRootmuxVideoPll1 = 6U, /*!< NOC Clock from VIDEO PLL1.*/
507 kCLOCK_NocRootmuxAudioPll2 = 7U, /*!< NOC Clock from AUDIO PLL2.*/
508
509} clock_rootmux_noc_clk_sel_t;
510
511/*! @brief CCM PLL gate control. */
512typedef enum _clock_pll_gate
513{
514 kCLOCK_ArmPllGate = (uint32_t)(&(CCM)->PLL_CTRL[12].PLL_CTRL), /*!< ARM PLL Gate.*/
515
516 kCLOCK_GpuPllGate = (uint32_t)(&(CCM)->PLL_CTRL[13].PLL_CTRL), /*!< GPU PLL Gate.*/
517 kCLOCK_VpuPllGate = (uint32_t)(&(CCM)->PLL_CTRL[14].PLL_CTRL), /*!< VPU PLL Gate.*/
518 kCLOCK_DramPllGate = (uint32_t)(&(CCM)->PLL_CTRL[15].PLL_CTRL), /*!< DRAM PLL1 Gate.*/
519
520 kCLOCK_SysPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[16].PLL_CTRL), /*!< SYSTEM PLL1 Gate.*/
521 kCLOCK_SysPll1Div2Gate = (uint32_t)(&(CCM)->PLL_CTRL[17].PLL_CTRL), /*!< SYSTEM PLL1 Div2 Gate.*/
522 kCLOCK_SysPll1Div3Gate = (uint32_t)(&(CCM)->PLL_CTRL[18].PLL_CTRL), /*!< SYSTEM PLL1 Div3 Gate.*/
523 kCLOCK_SysPll1Div4Gate = (uint32_t)(&(CCM)->PLL_CTRL[19].PLL_CTRL), /*!< SYSTEM PLL1 Div4 Gate.*/
524 kCLOCK_SysPll1Div5Gate = (uint32_t)(&(CCM)->PLL_CTRL[20].PLL_CTRL), /*!< SYSTEM PLL1 Div5 Gate.*/
525 kCLOCK_SysPll1Div6Gate = (uint32_t)(&(CCM)->PLL_CTRL[21].PLL_CTRL), /*!< SYSTEM PLL1 Div6 Gate.*/
526 kCLOCK_SysPll1Div8Gate = (uint32_t)(&(CCM)->PLL_CTRL[22].PLL_CTRL), /*!< SYSTEM PLL1 Div8 Gate.*/
527 kCLOCK_SysPll1Div10Gate = (uint32_t)(&(CCM)->PLL_CTRL[23].PLL_CTRL), /*!< SYSTEM PLL1 Div10 Gate.*/
528 kCLOCK_SysPll1Div20Gate = (uint32_t)(&(CCM)->PLL_CTRL[24].PLL_CTRL), /*!< SYSTEM PLL1 Div20 Gate.*/
529
530 kCLOCK_SysPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[25].PLL_CTRL), /*!< SYSTEM PLL2 Gate.*/
531 kCLOCK_SysPll2Div2Gate = (uint32_t)(&(CCM)->PLL_CTRL[26].PLL_CTRL), /*!< SYSTEM PLL2 Div2 Gate.*/
532 kCLOCK_SysPll2Div3Gate = (uint32_t)(&(CCM)->PLL_CTRL[27].PLL_CTRL), /*!< SYSTEM PLL2 Div3 Gate.*/
533 kCLOCK_SysPll2Div4Gate = (uint32_t)(&(CCM)->PLL_CTRL[28].PLL_CTRL), /*!< SYSTEM PLL2 Div4 Gate.*/
534 kCLOCK_SysPll2Div5Gate = (uint32_t)(&(CCM)->PLL_CTRL[29].PLL_CTRL), /*!< SYSTEM PLL2 Div5 Gate.*/
535 kCLOCK_SysPll2Div6Gate = (uint32_t)(&(CCM)->PLL_CTRL[30].PLL_CTRL), /*!< SYSTEM PLL2 Div6 Gate.*/
536 kCLOCK_SysPll2Div8Gate = (uint32_t)(&(CCM)->PLL_CTRL[31].PLL_CTRL), /*!< SYSTEM PLL2 Div8 Gate.*/
537 kCLOCK_SysPll2Div10Gate = (uint32_t)(&(CCM)->PLL_CTRL[32].PLL_CTRL), /*!< SYSTEM PLL2 Div10 Gate.*/
538 kCLOCK_SysPll2Div20Gate = (uint32_t)(&(CCM)->PLL_CTRL[33].PLL_CTRL), /*!< SYSTEM PLL2 Div20 Gate.*/
539
540 kCLOCK_SysPll3Gate = (uint32_t)(&(CCM)->PLL_CTRL[34].PLL_CTRL), /*!< SYSTEM PLL3 Gate.*/
541
542 kCLOCK_AudioPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[35].PLL_CTRL), /*!< AUDIO PLL1 Gate.*/
543 kCLOCK_AudioPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[36].PLL_CTRL), /*!< AUDIO PLL2 Gate.*/
544 kCLOCK_VideoPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[37].PLL_CTRL), /*!< VIDEO PLL1 Gate.*/
545 kCLOCK_VideoPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[38].PLL_CTRL), /*!< VIDEO PLL2 Gate.*/
546} clock_pll_gate_t;
547
548/*! @brief CCM gate control value. */
549typedef enum _clock_gate_value
550{
551 kCLOCK_ClockNotNeeded = 0x0U, /*!< Clock always disabled.*/
552 kCLOCK_ClockNeededRun = 0x1111U, /*!< Clock enabled when CPU is running.*/
553 kCLOCK_ClockNeededRunWait = 0x2222U, /*!< Clock enabled when CPU is running or in WAIT mode.*/
554 kCLOCK_ClockNeededAll = 0x3333U, /*!< Clock always enabled.*/
555} clock_gate_value_t;
556
557/*!
558 * @brief PLL control names for PLL bypass.
559 *
560 * These constants define the PLL control names for PLL bypass.\n
561 * - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
562 * - 16:20: bypass bit shift.
563 */
564typedef enum _clock_pll_bypass_ctrl
565{
566 kCLOCK_AudioPll1BypassCtrl = CCM_ANALOG_TUPLE(
567 AUDIO_PLL1_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Audio PLL1 bypass Control.*/
568 kCLOCK_AudioPll2BypassCtrl = CCM_ANALOG_TUPLE(
569 AUDIO_PLL2_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Audio PLL2 bypass Control.*/
570 kCLOCK_VideoPll1BypassCtrl = CCM_ANALOG_TUPLE(
571 VIDEO_PLL1_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Video Pll1 bypass Control.*/
572 kCLOCK_GpuPLLPwrBypassCtrl = CCM_ANALOG_TUPLE(
573 GPU_PLL_CFG0_OFFSET, CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Gpu PLL bypass Control.*/
574 kCLOCK_VpuPllPwrBypassCtrl = CCM_ANALOG_TUPLE(
575 VPU_PLL_CFG0_OFFSET, CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Vpu PLL bypass Control.*/
576 kCLOCK_ArmPllPwrBypassCtrl = CCM_ANALOG_TUPLE(
577 ARM_PLL_CFG0_OFFSET, CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Arm PLL bypass Control.*/
578
579 kCLOCK_SysPll1InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
580 SYS_PLL1_CFG0_OFFSET,
581 CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM System PLL1 internal pll1 bypass Control.*/
582 kCLOCK_SysPll1InternalPll2BypassCtrl = CCM_ANALOG_TUPLE(
583 SYS_PLL1_CFG0_OFFSET,
584 CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM System PLL1 internal pll2 bypass Control.*/
585
586 kCLOCK_SysPll2InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
587 SYS_PLL2_CFG0_OFFSET,
588 CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM Analog System PLL1 internal pll1 bypass Control.*/
589 kCLOCK_SysPll2InternalPll2BypassCtrl = CCM_ANALOG_TUPLE(
590 SYS_PLL2_CFG0_OFFSET,
591 CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM Analog VIDEO System PLL1 internal pll1 bypass Control.*/
592
593 kCLOCK_SysPll3InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
594 SYS_PLL3_CFG0_OFFSET, CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM Analog VIDEO PLL bypass Control.*/
595 kCLOCK_SysPll3InternalPll2BypassCtrl = CCM_ANALOG_TUPLE(
596 SYS_PLL3_CFG0_OFFSET, CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM Analog VIDEO PLL bypass Control.*/
597
598 kCLOCK_VideoPll2InternalPll1BypassCtrl =
599 CCM_ANALOG_TUPLE(VIDEO_PLL2_CFG0_OFFSET,
600 CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM Analog 480M PLL bypass Control.*/
601 kCLOCK_VideoPll2InternalPll2BypassCtrl =
602 CCM_ANALOG_TUPLE(VIDEO_PLL2_CFG0_OFFSET,
603 CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM Analog 480M PLL bypass Control.*/
604
605 kCLOCK_DramPllInternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
606 DRAM_PLL_CFG0_OFFSET, CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM Analog 480M PLL bypass Control.*/
607 kCLOCK_DramPllInternalPll2BypassCtrl = CCM_ANALOG_TUPLE(
608 DRAM_PLL_CFG0_OFFSET, CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM Analog 480M PLL bypass Control.*/
609} clock_pll_bypass_ctrl_t;
610
611/*!
612 * @brief PLL clock names for clock enable/disable settings.
613 *
614 * These constants define the PLL clock names for PLL clock enable/disable operations.\n
615 * - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
616 * - 16:20: Clock enable bit shift.
617 */
618typedef enum _ccm_analog_pll_clke
619{
620 kCLOCK_AudioPll1Clke =
621 CCM_ANALOG_TUPLE(AUDIO_PLL1_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_SHIFT), /*!< Audio pll1 clke */
622 kCLOCK_AudioPll2Clke =
623 CCM_ANALOG_TUPLE(AUDIO_PLL2_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_SHIFT), /*!< Audio pll2 clke */
624 kCLOCK_VideoPll1Clke =
625 CCM_ANALOG_TUPLE(VIDEO_PLL1_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_SHIFT), /*!< Video pll1 clke */
626 kCLOCK_GpuPllClke =
627 CCM_ANALOG_TUPLE(GPU_PLL_CFG0_OFFSET, CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_SHIFT), /*!< Gpu pll clke */
628 kCLOCK_VpuPllClke =
629 CCM_ANALOG_TUPLE(VPU_PLL_CFG0_OFFSET, CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_SHIFT), /*!< Vpu pll clke */
630 kCLOCK_ArmPllClke =
631 CCM_ANALOG_TUPLE(ARM_PLL_CFG0_OFFSET, CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_SHIFT), /*!< Arm pll clke */
632
633 kCLOCK_SystemPll1Clke =
634 CCM_ANALOG_TUPLE(SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_SHIFT), /*!< System pll1 clke */
635 kCLOCK_SystemPll1Div2Clke = CCM_ANALOG_TUPLE(
636 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE_SHIFT), /*!< System pll1 Div2 clke */
637 kCLOCK_SystemPll1Div3Clke = CCM_ANALOG_TUPLE(
638 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE_SHIFT), /*!< System pll1 Div3 clke */
639 kCLOCK_SystemPll1Div4Clke = CCM_ANALOG_TUPLE(
640 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE_SHIFT), /*!< System pll1 Div4 clke */
641 kCLOCK_SystemPll1Div5Clke = CCM_ANALOG_TUPLE(
642 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE_SHIFT), /*!< System pll1 Div5 clke */
643 kCLOCK_SystemPll1Div6Clke = CCM_ANALOG_TUPLE(
644 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE_SHIFT), /*!< System pll1 Div6 clke */
645 kCLOCK_SystemPll1Div8Clke = CCM_ANALOG_TUPLE(
646 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE_SHIFT), /*!< System pll1 Div8 clke */
647 kCLOCK_SystemPll1Div10Clke = CCM_ANALOG_TUPLE(
648 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE_SHIFT), /*!< System pll1 Div10 clke */
649 kCLOCK_SystemPll1Div20Clke = CCM_ANALOG_TUPLE(
650 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE_SHIFT), /*!< System pll1 Div20 clke */
651
652 kCLOCK_SystemPll2Clke =
653 CCM_ANALOG_TUPLE(SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_SHIFT), /*!< System pll2 clke */
654 kCLOCK_SystemPll2Div2Clke = CCM_ANALOG_TUPLE(
655 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE_SHIFT), /*!< System pll2 Div2 clke */
656 kCLOCK_SystemPll2Div3Clke = CCM_ANALOG_TUPLE(
657 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE_SHIFT), /*!< System pll2 Div3 clke */
658 kCLOCK_SystemPll2Div4Clke = CCM_ANALOG_TUPLE(
659 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE_SHIFT), /*!< System pll2 Div4 clke */
660 kCLOCK_SystemPll2Div5Clke = CCM_ANALOG_TUPLE(
661 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE_SHIFT), /*!< System pll2 Div5 clke */
662 kCLOCK_SystemPll2Div6Clke = CCM_ANALOG_TUPLE(
663 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE_SHIFT), /*!< System pll2 Div6 clke */
664 kCLOCK_SystemPll2Div8Clke = CCM_ANALOG_TUPLE(
665 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE_SHIFT), /*!< System pll2 Div8 clke */
666 kCLOCK_SystemPll2Div10Clke = CCM_ANALOG_TUPLE(
667 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE_SHIFT), /*!< System pll2 Div10 clke */
668 kCLOCK_SystemPll2Div20Clke = CCM_ANALOG_TUPLE(
669 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE_SHIFT), /*!< System pll2 Div20 clke */
670
671 kCLOCK_SystemPll3Clke =
672 CCM_ANALOG_TUPLE(SYS_PLL3_CFG0_OFFSET, CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_SHIFT), /*!< System pll3 clke */
673 kCLOCK_VideoPll2Clke =
674 CCM_ANALOG_TUPLE(VIDEO_PLL2_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_SHIFT), /*!< Video pll2 clke */
675 kCLOCK_DramPllClke =
676 CCM_ANALOG_TUPLE(DRAM_PLL_CFG0_OFFSET, CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_SHIFT), /*!< Dram pll clke */
677 kCLOCK_OSC25MClke =
678 CCM_ANALOG_TUPLE(OSC_MISC_CFG_OFFSET, CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_SHIFT), /*!< OSC25M clke */
679 kCLOCK_OSC27MClke =
680 CCM_ANALOG_TUPLE(OSC_MISC_CFG_OFFSET, CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_SHIFT), /*!< OSC27M clke */
681
682} clock_pll_clke_t;
683
684/*!
685 * @brief ANALOG Power down override control.
686 */
687typedef enum _clock_pll_ctrl
688{
689 kCLOCK_AudioPll1Ctrl = CCM_ANALOG_TUPLE(AUDIO_PLL1_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_SHIFT),
690 kCLOCK_AudioPll2Ctrl = CCM_ANALOG_TUPLE(AUDIO_PLL2_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_SHIFT),
691 kCLOCK_VideoPll1Ctrl = CCM_ANALOG_TUPLE(VIDEO_PLL1_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_SHIFT),
692 kCLOCK_GpuPllCtrl = CCM_ANALOG_TUPLE(GPU_PLL_CFG0_OFFSET, CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_SHIFT),
693 kCLOCK_VpuPllCtrl = CCM_ANALOG_TUPLE(VPU_PLL_CFG0_OFFSET, CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_SHIFT),
694 kCLOCK_ArmPllCtrl = CCM_ANALOG_TUPLE(ARM_PLL_CFG0_OFFSET, CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_SHIFT),
695
696 kCLOCK_SystemPll1Ctrl = CCM_ANALOG_TUPLE(SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_SHIFT),
697 kCLOCK_SystemPll2Ctrl = CCM_ANALOG_TUPLE(SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_SHIFT),
698 kCLOCK_SystemPll3Ctrl = CCM_ANALOG_TUPLE(SYS_PLL3_CFG0_OFFSET, CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_SHIFT),
699 kCLOCK_VideoPll2Ctrl = CCM_ANALOG_TUPLE(VIDEO_PLL2_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_SHIFT),
700 kCLOCK_DramPllCtrl = CCM_ANALOG_TUPLE(DRAM_PLL_CFG0_OFFSET, CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_SHIFT),
701
702} clock_pll_ctrl_t;
703
704/*! @brief OSC work mode. */
705enum _osc_mode
706{
707 kOSC_OscMode = 0U, /*!< OSC oscillator mode */
708 kOSC_ExtMode = 1U, /*!< OSC external mode */
709};
710
711/*! @brief OSC 32K input select. */
712typedef enum _osc32_src
713{
714 kOSC32_Src25MDiv800 = 0U, /*!< source from 25M divide 800 */
715 kOSC32_SrcRTC, /*!< source from RTC */
716} osc32_src_t;
717
718/*! @brief PLL reference clock select. */
719enum _ccm_analog_pll_ref_clk
720{
721 kANALOG_PllRefOsc25M = 0U, /*!< reference OSC 25M */
722 kANALOG_PllRefOsc27M = 1U, /*!< reference OSC 27M */
723 kANALOG_PllRefOscHdmiPhy27M = 2U, /*!< reference HDMI PHY 27M */
724 kANALOG_PllRefClkPN = 3U, /*!< reference CLK_P_N */
725};
726
727/*!
728 * @brief OSC configuration structure.
729 */
730typedef struct _osc_config
731{
732 uint8_t oscMode; /*!< ext or osc mode */
733 uint8_t oscDiv; /*!< osc divider */
734} osc_config_t;
735
736/*!
737 * @brief Fractional-N PLL configuration.
738 * Note: all the dividers in this configuration structure are the actually divider, software will map it to register
739 * value
740 */
741typedef struct _ccm_analog_frac_pll_config
742{
743 uint8_t refSel; /*!< pll reference clock sel */
744
745 uint8_t refDiv; /*!< A 6bit divider to make sure the REF must be within the range 10MHZ~300MHZ */
746
747 uint32_t fractionDiv; /*!< Inlcude fraction divider(divider:1:2^24) output clock
748 range is 2000MHZ-4000MHZ */
749 uint8_t intDiv; /*and integer divide(divider: 1:32)*/
750 uint8_t outDiv; /*!< output clock divide, output clock range is 30MHZ to 2000MHZ, must be a even value */
751
752} ccm_analog_frac_pll_config_t;
753
754/*!
755 * @brief SSCG PLL configuration.
756 * Note: all the dividers in this configuration structure are the actually divider, software will map it to register
757 * value
758 */
759typedef struct _ccm_analog_sscg_pll_config
760{
761 uint8_t refSel; /*!< pll reference clock sel */
762
763 uint8_t refDiv1; /*!< A 3bit divider to make sure the REF must be within the range 25MHZ~235MHZ ,post_divide REF
764 must be within the range 25MHZ~54MHZ */
765 uint8_t refDiv2; /*!< A 6bit divider to make sure the post_divide REF must be within the range 54MHZ~75MHZ */
766
767 uint32_t loopDivider1; /*!< A 6bit internal PLL1 feedback clock divider, output clock range must be within the range
768 1600MHZ-2400MHZ */
769 uint32_t loopDivider2; /*!< A 6bit internal PLL2 feedback clock divider, output clock range must be within the range
770 1200MHZ-2400MHZ */
771
772 uint8_t outDiv; /*!< A 6bit output clock divide, output clock range is 20MHZ to 1200MHZ */
773
774} ccm_analog_sscg_pll_config_t;
775
776/*******************************************************************************
777 * API
778 ******************************************************************************/
779
780#if defined(__cplusplus)
781extern "C" {
782#endif
783
784/*!
785 * @name CCM Root Clock Setting
786 * @{
787 */
788
789/*!
790 * @brief Set clock root mux.
791 * User maybe need to set more than one mux ROOT according to the clock tree
792 * description in the reference manual.
793 *
794 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration).
795 * @param mux Root mux value (see _ccm_rootmux_xxx enumeration).
796 */
797static inline void CLOCK_SetRootMux(clock_root_control_t rootClk, uint32_t mux)
798{
799 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux);
800}
801
802/*!
803 * @brief Get clock root mux.
804 * In order to get the clock source of root, user maybe need to get more than one
805 * ROOT's mux value to obtain the final clock source of root.
806 *
807 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration).
808 * @return Root mux value (see _ccm_rootmux_xxx enumeration).
809 */
810static inline uint32_t CLOCK_GetRootMux(clock_root_control_t rootClk)
811{
812 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT;
813}
814
815/*!
816 * @brief Enable clock root
817 *
818 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration)
819 */
820static inline void CLOCK_EnableRoot(clock_root_control_t rootClk)
821{
822 CCM_REG_SET(rootClk) = CCM_TARGET_ROOT_SET_ENABLE_MASK;
823}
824
825/*!
826 * @brief Disable clock root
827 *
828 * @param rootClk Root control (see @ref clock_root_control_t enumeration)
829 */
830static inline void CLOCK_DisableRoot(clock_root_control_t rootClk)
831{
832 CCM_REG_CLR(rootClk) = CCM_TARGET_ROOT_CLR_ENABLE_MASK;
833}
834
835/*!
836 * @brief Check whether clock root is enabled
837 *
838 * @param rootClk Root control (see @ref clock_root_control_t enumeration)
839 * @return CCM root enabled or not.
840 * - true: Clock root is enabled.
841 * - false: Clock root is disabled.
842 */
843static inline bool CLOCK_IsRootEnabled(clock_root_control_t rootClk)
844{
845 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK);
846}
847
848/*!
849 * @brief Update clock root in one step, for dynamical clock switching
850 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
851 *
852 * @param ccmRootClk Root control (see @ref clock_root_control_t enumeration)
853 * @param mux root mux value (see _ccm_rootmux_xxx enumeration)
854 * @param pre Pre divider value (0-7, divider=n+1)
855 * @param post Post divider value (0-63, divider=n+1)
856 */
857void CLOCK_UpdateRoot(clock_root_control_t ccmRootClk, uint32_t mux, uint32_t pre, uint32_t post);
858
859/*!
860 * @brief Set root clock divider
861 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
862 *
863 * @param ccmRootClk Root control (see @ref clock_root_control_t enumeration)
864 * @param pre Pre divider value (1-8)
865 * @param post Post divider value (1-64)
866 */
867void CLOCK_SetRootDivider(clock_root_control_t ccmRootClk, uint32_t pre, uint32_t post);
868
869/*!
870 * @brief Get clock root PRE_PODF.
871 * In order to get the clock source of root, user maybe need to get more than one
872 * ROOT's mux value to obtain the final clock source of root.
873 *
874 * @param rootClk Root clock name (see @ref clock_root_control_t enumeration).
875 * @return Root Pre divider value.
876 */
877static inline uint32_t CLOCK_GetRootPreDivider(clock_root_control_t rootClk)
878{
879 return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U;
880}
881
882/*!
883 * @brief Get clock root POST_PODF.
884 * In order to get the clock source of root, user maybe need to get more than one
885 * ROOT's mux value to obtain the final clock source of root.
886 *
887 * @param rootClk Root clock name (see @ref clock_root_control_t enumeration).
888 * @return Root Post divider value.
889 */
890static inline uint32_t CLOCK_GetRootPostDivider(clock_root_control_t rootClk)
891{
892 return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + 1U;
893}
894
895/*!
896 * @name OSC setting
897 * @{
898 */
899/*!
900 * @brief OSC25M init
901 *
902 * @param config osc configuration.
903 */
904void CLOCK_InitOSC25M(const osc_config_t *config);
905
906/*!
907 * @brief OSC25M deinit
908 *
909 */
910void CLOCK_DeinitOSC25M(void);
911
912/*!
913 * @brief OSC27M init
914 * @param config osc configuration.
915 *
916 */
917void CLOCK_InitOSC27M(const osc_config_t *config);
918
919/*!
920 * @brief OSC27M deinit
921 *
922 */
923void CLOCK_DeinitOSC27M(void);
924
925/*!
926 * @brief switch 32KHZ OSC input
927 * @param sel OSC32 input clock select
928 */
929static inline void CLOCK_SwitchOSC32Src(osc32_src_t sel)
930{
931 CCM_ANALOG->OSC_MISC_CFG = (CCM_ANALOG->OSC_MISC_CFG & (~CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK)) | (uint32_t)sel;
932}
933
934/*!
935 * @name CCM Gate Control
936 * @{
937 */
938
939/*!
940 * @brief Set PLL or CCGR gate control
941 *
942 * @param ccmGate Gate control (see @ref clock_pll_gate_t and @ref clock_ip_name_t enumeration)
943 * @param control Gate control value (see @ref clock_gate_value_t)
944 */
945static inline void CLOCK_ControlGate(uint32_t ccmGate, clock_gate_value_t control)
946{
947 CCM_REG(ccmGate) = (uint32_t)control;
948}
949
950/*!
951 * @brief Enable CCGR clock gate and root clock gate for each module
952 * User should set specific gate for each module according to the description
953 * of the table of system clocks, gating and override in CCM chapter of
954 * reference manual. Take care of that one module may need to set more than
955 * one clock gate.
956 *
957 * @param ccmGate Gate control for each module (see @ref clock_ip_name_t enumeration).
958 */
959void CLOCK_EnableClock(clock_ip_name_t ccmGate);
960
961/*!
962 * @brief Disable CCGR clock gate for the each module
963 * User should set specific gate for each module according to the description
964 * of the table of system clocks, gating and override in CCM chapter of
965 * reference manual. Take care of that one module may need to set more than
966 * one clock gate.
967 *
968 * @param ccmGate Gate control for each module (see @ref clock_ip_name_t enumeration).
969 */
970void CLOCK_DisableClock(clock_ip_name_t ccmGate);
971
972/*!
973 * @name CCM Analog PLL Operatoin Functions
974 * @{
975 */
976
977/*!
978 * @brief Power up PLL
979 *
980 * @param base CCM_ANALOG base pointer.
981 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
982 */
983static inline void CLOCK_PowerUpPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
984{
985 CCM_ANALOG_TUPLE_REG(base, pllControl) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
986}
987
988/*!
989 * @brief Power down PLL
990 *
991 * @param base CCM_ANALOG base pointer.
992 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
993 */
994static inline void CLOCK_PowerDownPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
995{
996 CCM_ANALOG_TUPLE_REG(base, pllControl) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl);
997}
998
999/*!
1000 * @brief PLL bypass setting
1001 *
1002 * @param base CCM_ANALOG base pointer.
1003 * @param pllControl PLL control name (see ccm_analog_pll_control_t enumeration)
1004 * @param bypass Bypass the PLL.
1005 * - true: Bypass the PLL.
1006 * - false: Do not bypass the PLL.
1007 */
1008static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl, bool bypass)
1009{
1010 if (bypass)
1011 {
1012 CCM_ANALOG_TUPLE_REG(base, pllControl) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl);
1013 }
1014 else
1015 {
1016 CCM_ANALOG_TUPLE_REG(base, pllControl) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
1017 }
1018}
1019
1020/*!
1021 * @brief Check if PLL is bypassed
1022 *
1023 * @param base CCM_ANALOG base pointer.
1024 * @param pllControl PLL control name (see ccm_analog_pll_control_t enumeration)
1025 * @return PLL bypass status.
1026 * - true: The PLL is bypassed.
1027 * - false: The PLL is not bypassed.
1028 */
1029static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl)
1030{
1031 return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl)));
1032}
1033
1034/*!
1035 * @brief Check if PLL clock is locked
1036 *
1037 * @param base CCM_ANALOG base pointer.
1038 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
1039 * @return PLL lock status.
1040 * - true: The PLL clock is locked.
1041 * - false: The PLL clock is not locked.
1042 */
1043static inline bool CLOCK_IsPllLocked(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
1044{
1045 return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_MASK);
1046}
1047
1048/*!
1049 * @brief Enable PLL clock
1050 *
1051 * @param base CCM_ANALOG base pointer.
1052 * @param pllClock PLL clock name (see ccm_analog_pll_clock_t enumeration)
1053 */
1054static inline void CLOCK_EnableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
1055{
1056 CCM_ANALOG_TUPLE_REG(base, pllClock) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllClock);
1057}
1058
1059/*!
1060 * @brief Disable PLL clock
1061 *
1062 * @param base CCM_ANALOG base pointer.
1063 * @param pllClock PLL clock name (see ccm_analog_pll_clock_t enumeration)
1064 */
1065static inline void CLOCK_DisableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
1066{
1067 CCM_ANALOG_TUPLE_REG(base, pllClock) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllClock));
1068}
1069
1070/*!
1071 * @brief Override PLL clock output enable
1072 *
1073 * @param base CCM_ANALOG base pointer.
1074 * @param ovClock PLL clock name (see @ref clock_pll_clke_t enumeration)
1075 * @param override Override the PLL.
1076 * - true: Override the PLL clke, CCM will handle it.
1077 * - false: Do not override the PLL clke.
1078 */
1079static inline void CLOCK_OverrideAnalogClke(CCM_ANALOG_Type *base, clock_pll_clke_t ovClock, bool override)
1080{
1081 if (override)
1082 {
1083 CCM_ANALOG_TUPLE_REG(base, ovClock) |= 1UL << (CCM_ANALOG_TUPLE_SHIFT(ovClock) - 1UL);
1084 }
1085 else
1086 {
1087 CCM_ANALOG_TUPLE_REG(base, ovClock) &= ~(1UL << (CCM_ANALOG_TUPLE_SHIFT(ovClock) - 1UL));
1088 }
1089}
1090
1091/*!
1092 * @brief Override PLL power down
1093 *
1094 * @param base CCM_ANALOG base pointer.
1095 * @param pdClock PLL clock name (see @ref clock_pll_ctrl_t enumeration)
1096 * @param override Override the PLL.
1097 * - true: Override the PLL clke, CCM will handle it.
1098 * - false: Do not override the PLL clke.
1099 */
1100static inline void CLOCK_OverridePllPd(CCM_ANALOG_Type *base, clock_pll_ctrl_t pdClock, bool override)
1101{
1102 if (override)
1103 {
1104 CCM_ANALOG_TUPLE_REG(base, pdClock) |= 1UL << (CCM_ANALOG_TUPLE_SHIFT(pdClock) - 1UL);
1105 }
1106 else
1107 {
1108 CCM_ANALOG_TUPLE_REG(base, pdClock) &= ~(1UL << (CCM_ANALOG_TUPLE_SHIFT(pdClock) - 1UL));
1109 }
1110}
1111
1112/*!
1113 * @brief Initializes the ANALOG ARM PLL.
1114 *
1115 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1116 *
1117 * @note This function can't detect whether the Arm PLL has been enabled and
1118 * used by some IPs.
1119 */
1120void CLOCK_InitArmPll(const ccm_analog_frac_pll_config_t *config);
1121
1122/*!
1123 * @brief De-initialize the ARM PLL.
1124 */
1125void CLOCK_DeinitArmPll(void);
1126
1127/*!
1128 * @brief Initializes the ANALOG SYS PLL1.
1129 *
1130 * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration).
1131 *
1132 * @note This function can't detect whether the SYS PLL has been enabled and
1133 * used by some IPs.
1134 */
1135void CLOCK_InitSysPll1(const ccm_analog_sscg_pll_config_t *config);
1136
1137/*!
1138 * @brief De-initialize the System PLL1.
1139 */
1140void CLOCK_DeinitSysPll1(void);
1141
1142/*!
1143 * @brief Initializes the ANALOG SYS PLL2.
1144 *
1145 * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration).
1146 *
1147 * @note This function can't detect whether the SYS PLL has been enabled and
1148 * used by some IPs.
1149 */
1150void CLOCK_InitSysPll2(const ccm_analog_sscg_pll_config_t *config);
1151
1152/*!
1153 * @brief De-initialize the System PLL2.
1154 */
1155void CLOCK_DeinitSysPll2(void);
1156
1157/*!
1158 * @brief Initializes the ANALOG SYS PLL3.
1159 *
1160 * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration).
1161 *
1162 * @note This function can't detect whether the SYS PLL has been enabled and
1163 * used by some IPs.
1164 */
1165void CLOCK_InitSysPll3(const ccm_analog_sscg_pll_config_t *config);
1166
1167/*!
1168 * @brief De-initialize the System PLL3.
1169 */
1170void CLOCK_DeinitSysPll3(void);
1171
1172/*!
1173 * @brief Initializes the ANALOG DDR PLL.
1174 *
1175 * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration).
1176 *
1177 * @note This function can't detect whether the DDR PLL has been enabled and
1178 * used by some IPs.
1179 */
1180void CLOCK_InitDramPll(const ccm_analog_sscg_pll_config_t *config);
1181
1182/*!
1183 * @brief De-initialize the Dram PLL.
1184 */
1185void CLOCK_DeinitDramPll(void);
1186
1187/*!
1188 * @brief Initializes the ANALOG AUDIO PLL1.
1189 *
1190 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1191 *
1192 * @note This function can't detect whether the AUDIO PLL has been enabled and
1193 * used by some IPs.
1194 */
1195void CLOCK_InitAudioPll1(const ccm_analog_frac_pll_config_t *config);
1196
1197/*!
1198 * @brief De-initialize the Audio PLL1.
1199 */
1200void CLOCK_DeinitAudioPll1(void);
1201
1202/*!
1203 * @brief Initializes the ANALOG AUDIO PLL2.
1204 *
1205 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1206 *
1207 * @note This function can't detect whether the AUDIO PLL has been enabled and
1208 * used by some IPs.
1209 */
1210void CLOCK_InitAudioPll2(const ccm_analog_frac_pll_config_t *config);
1211
1212/*!
1213 * @brief De-initialize the Audio PLL2.
1214 */
1215void CLOCK_DeinitAudioPll2(void);
1216
1217/*!
1218 * @brief Initializes the ANALOG VIDEO PLL1.
1219 *
1220 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1221 *
1222 */
1223void CLOCK_InitVideoPll1(const ccm_analog_frac_pll_config_t *config);
1224
1225/*!
1226 * @brief De-initialize the Video PLL1.
1227 */
1228void CLOCK_DeinitVideoPll1(void);
1229
1230/*!
1231 * @brief Initializes the ANALOG VIDEO PLL2.
1232 *
1233 * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration).
1234 *
1235 * @note This function can't detect whether the VIDEO PLL has been enabled and
1236 * used by some IPs.
1237 */
1238void CLOCK_InitVideoPll2(const ccm_analog_sscg_pll_config_t *config);
1239
1240/*!
1241 * @brief De-initialize the Video PLL2.
1242 */
1243void CLOCK_DeinitVideoPll2(void);
1244
1245/*!
1246 * @brief Initializes the ANALOG SSCG PLL.
1247 *
1248 * @param base CCM ANALOG base address
1249 * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration).
1250 * @param type sscg pll type
1251 *
1252 */
1253void CLOCK_InitSSCGPll(CCM_ANALOG_Type *base, const ccm_analog_sscg_pll_config_t *config, clock_pll_ctrl_t type);
1254
1255/*!
1256 * @brief Get the ANALOG SSCG PLL clock frequency.
1257 *
1258 * @param base CCM ANALOG base address.
1259 * @param type sscg pll type
1260 * @param refClkFreq reference clock frequency
1261 * @param pll1Bypass pll1 bypass flag
1262 *
1263 * @return Clock frequency
1264 */
1265uint32_t CLOCK_GetSSCGPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq, bool pll1Bypass);
1266
1267/*!
1268 * @brief Initializes the ANALOG Fractional PLL.
1269 *
1270 * @param base CCM ANALOG base address.
1271 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1272 * @param type fractional pll type.
1273 *
1274 */
1275void CLOCK_InitFracPll(CCM_ANALOG_Type *base, const ccm_analog_frac_pll_config_t *config, clock_pll_ctrl_t type);
1276
1277/*!
1278 * @brief Gets the ANALOG Fractional PLL clock frequency.
1279 *
1280 * @param base CCM_ANALOG base pointer.
1281 * @param type fractional pll type.
1282 * @param refClkFreq reference clock frequency
1283 *
1284 * @return Clock frequency
1285 */
1286uint32_t CLOCK_GetFracPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq);
1287
1288/*!
1289 * @brief Gets PLL clock frequency.
1290 *
1291 * @param pll fractional pll type.
1292
1293 * @return Clock frequency
1294 */
1295uint32_t CLOCK_GetPllFreq(clock_pll_ctrl_t pll);
1296
1297/*!
1298 * @brief Gets PLL reference clock frequency.
1299 *
1300 * @param ctrl fractional pll type.
1301
1302 * @return Clock frequency
1303 */
1304uint32_t CLOCK_GetPllRefClkFreq(clock_pll_ctrl_t ctrl);
1305
1306/*!
1307 * @name CCM Get frequency
1308 * @{
1309 */
1310
1311/*!
1312 * @brief Gets the clock frequency for a specific clock name.
1313 *
1314 * This function checks the current clock configurations and then calculates
1315 * the clock frequency for a specific clock name defined in clock_name_t.
1316 *
1317 * @param clockName Clock names defined in clock_name_t
1318 * @return Clock frequency value in hertz
1319 */
1320uint32_t CLOCK_GetFreq(clock_name_t clockName);
1321
1322/*!
1323 * @brief Get the CCM Cortex M4 core frequency.
1324 *
1325 * @return Clock frequency; If the clock is invalid, returns 0.
1326 */
1327uint32_t CLOCK_GetCoreM4Freq(void);
1328
1329/*!
1330 * @brief Get the CCM Axi bus frequency.
1331 *
1332 * @return Clock frequency; If the clock is invalid, returns 0.
1333 */
1334uint32_t CLOCK_GetAxiFreq(void);
1335
1336/*!
1337 * @brief Get the CCM Ahb bus frequency.
1338 *
1339 * @return Clock frequency; If the clock is invalid, returns 0.
1340 */
1341uint32_t CLOCK_GetAhbFreq(void);
1342
1343/* @} */
1344
1345#if defined(__cplusplus)
1346}
1347#endif
1348/* @} */
1349#endif
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/drivers/fsl_iomuxc.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/drivers/fsl_iomuxc.h
new file mode 100644
index 000000000..c668299a3
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/drivers/fsl_iomuxc.h
@@ -0,0 +1,606 @@
1/*
2 * Copyright 2016 Freescale Semiconductor, Inc.
3 * Copyright 2016-2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8#ifndef _FSL_IOMUXC_H_
9#define _FSL_IOMUXC_H_
10
11#include "fsl_common.h"
12
13/*!
14 * @addtogroup iomuxc_driver
15 * @{
16 */
17
18/*! @file */
19
20/*******************************************************************************
21 * Definitions
22 ******************************************************************************/
23/* Component ID definition, used by tools. */
24#ifndef FSL_COMPONENT_ID
25#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
26#endif
27
28/*! @name Driver version */
29/*@{*/
30/*! @brief IOMUXC driver version 2.0.1. */
31#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
32/*@}*/
33
34/*!
35 * @name Pin function ID
36 * The pin function ID is a tuple of \<muxRegister muxMode inputRegister inputDaisy configRegister\>
37 *
38 * @{
39 */
40#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
41#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
42#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
43#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
44#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
45#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
46#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
47#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
48#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
49#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
50#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
51#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
52#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
53#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
54#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
55#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
56#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
57#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
58#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
59#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
60#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
61#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
62#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
63#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
64#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
65#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
66#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
67#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
68#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
69#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
70#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
71#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
72#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
73#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
74#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
75#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
76#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
77#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
78#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
79#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
80#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
81#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
82#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
83#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
84#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
85#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
86#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
87#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
88#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
89#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
90#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
91#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
92#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
93#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
94#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
95#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
96#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
97#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
98#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
99#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
100#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
101#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
102#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
103#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
104#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
105#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
106#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
107#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
108#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
109#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
110#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
111#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
112#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
113#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
114#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
115#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
116#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
117#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
118#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
119#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
120#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
121#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
122#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
123#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
124#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
125#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
126#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
127#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
128#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
129#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
130#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
131#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
132#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
133#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
134#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
135#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
136#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
137#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
138#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
139#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
140#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
141#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
142#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
143#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
144#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
145#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
146#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
147#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
148#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
149#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
150#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
151#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
152#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
153#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
154#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
155#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
156#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
157#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
158#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
159#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
160#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
161#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
162#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
163#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
164#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
165#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
166#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
167#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
168#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
169#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
170#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
171#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
172#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
173#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
174#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
175#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
176#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
177#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
178#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
179#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
180#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
181#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
182#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
183#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
184#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
185#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
186#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
187#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
188#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
189#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
190#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
191#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
192#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
193#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
194#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
195#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
196#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
197#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
198#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
199#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
200#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
201#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
202#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
203#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
204#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
205#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
206#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
207#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
208#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
209#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
210#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
211#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
212#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
213#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
214#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
215#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
216#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
217#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
218#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
219#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
220#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
221#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
222#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
223#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
224#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
225#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
226#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
227#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
228#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
229#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
230#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
231#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
232#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
233#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
234#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
235#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
236#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
237#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
238#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
239#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
240#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
241#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
242#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
243#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
244#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
245#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
246#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
247#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
248#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
249#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
250#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
251#define IOMUXC_SAI5_MCLK_SAI4_MCLK 0x30330158, 0x2, 0x00000000, 0x0, 0x303303C0
252#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
253#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
254#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
255#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
256#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
257#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
258#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
259#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
260#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
261#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
262#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
263#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
264#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
265#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
266#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
267#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
268#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
269#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
270#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
271#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
272#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
273#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
274#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
275#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
276#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
277#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
278#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
279#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
280#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
281#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
282#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
283#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
284#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
285#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
286#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
287#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
288#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
289#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
290#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
291#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
292#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
293#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
294#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
295#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
296#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
297#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
298#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
299#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
300#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
301#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
302#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
303#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
304#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
305#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
306#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
307#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
308#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
309#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
310#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
311#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
312#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
313#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
314#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
315#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
316#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
317#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
318#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
319#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
320#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
321#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
322#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
323#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
324#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
325#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
326#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
327#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
328#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
329#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
330#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
331#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
332#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
333#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
334#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
335#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
336#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
337#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
338#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
339#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
340#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
341#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
342#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
343#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
344#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
345#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
346#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
347#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
348#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
349#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
350#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
351#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
352#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
353#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
354#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
355#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
356#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
357#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
358#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
359#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
360#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
361#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
362#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
363#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
364#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
365#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
366#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
367#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
368#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
369#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
370#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
371#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
372#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
373#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
374#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
375#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
376#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
377#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
378#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
379#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
380#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
381#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
382#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
383#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
384#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
385#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
386#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
387#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
388#define IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
389#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
390#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
391#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
392#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
393#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
394#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
395#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
396#define IOMUXC_SAI3_TXFS_GPT1_CLK 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
397#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
398#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
399#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
400#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
401#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
402#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
403#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
404#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
405#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
406#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
407#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
408#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
409#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
410#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
411#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
412#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
413#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
414#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
415#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
416#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
417#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
418#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
419#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
420#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
421#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
422#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
423#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
424#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
425#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
426#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
427#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
428#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
429#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
430#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
431#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
432#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
433#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
434#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
435#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
436#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
437#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
438#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
439#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
440#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
441#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
442#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
443#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
444#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
445#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
446#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
447#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
448#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
449#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
450#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
451#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
452#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
453#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
454#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
455#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
456#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
457#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
458#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
459#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
460#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
461#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
462#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
463#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
464#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
465#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
466#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
467#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
468#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
469#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
470#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
471#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
472#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
473#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
474#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
475#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
476#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
477#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
478#define IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x30330230, 0x2, 0x30330528, 0x0, 0x30330498
479#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
480#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
481#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
482#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
483#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
484#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
485#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
486#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
487#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
488#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
489#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
490#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
491#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
492#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
493#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
494#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
495#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
496#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
497#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
498#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
499#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
500#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
501#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
502#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
503#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
504#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
505#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
506#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
507#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
508#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
509#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
510#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
511#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
512#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
513#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
514#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
515#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
516#define IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x30330250, 0x2, 0x30330528, 0x1, 0x303304B8
517#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
518#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
519#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
520#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
521#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
522#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
523#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
524#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
525#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
526#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
527#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
528
529/*@}*/
530
531#if defined(__cplusplus)
532extern "C" {
533#endif /*__cplusplus */
534
535/*! @name Configuration */
536/*@{*/
537
538/*!
539 * @brief Sets the IOMUXC pin mux mode.
540 * @note The first five parameters can be filled with the pin function ID macros.
541 *
542 * This is an example to set the I2C4_SDA as the pwm1_OUT:
543 * @code
544 * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
545 * @endcode
546 *
547 *
548 * @param muxRegister The pin mux register_
549 * @param muxMode The pin mux mode_
550 * @param inputRegister The select input register_
551 * @param inputDaisy The input daisy_
552 * @param configRegister The config register_
553 * @param inputOnfield The pad->module input inversion_
554 */
555static inline void IOMUXC_SetPinMux(uint32_t muxRegister,
556 uint32_t muxMode,
557 uint32_t inputRegister,
558 uint32_t inputDaisy,
559 uint32_t configRegister,
560 uint32_t inputOnfield)
561{
562 *((volatile uint32_t *)muxRegister) =
563 IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
564
565 if (inputRegister)
566 {
567 *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
568 }
569}
570/*!
571 * @brief Sets the IOMUXC pin configuration.
572 * @note The previous five parameters can be filled with the pin function ID macros.
573 *
574 * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
575 * @code
576 * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
577 * @endcode
578 *
579 * @param muxRegister The pin mux register_
580 * @param muxMode The pin mux mode_
581 * @param inputRegister The select input register_
582 * @param inputDaisy The input daisy_
583 * @param configRegister The config register_
584 * @param configValue The pin config value_
585 */
586static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
587 uint32_t muxMode,
588 uint32_t inputRegister,
589 uint32_t inputDaisy,
590 uint32_t configRegister,
591 uint32_t configValue)
592{
593 if (configRegister)
594 {
595 *((volatile uint32_t *)configRegister) = configValue;
596 }
597}
598/*@}*/
599
600#if defined(__cplusplus)
601}
602#endif /*__cplusplus */
603
604/*! @}*/
605
606#endif /* _FSL_IOMUXC_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/fsl_device_registers.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/fsl_device_registers.h
new file mode 100644
index 000000000..952dc46fa
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/fsl_device_registers.h
@@ -0,0 +1,38 @@
1/*
2 * Copyright 2014-2016 Freescale Semiconductor, Inc.
3 * Copyright 2016-2018 NXP
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 */
8
9#ifndef __FSL_DEVICE_REGISTERS_H__
10#define __FSL_DEVICE_REGISTERS_H__
11
12/*
13 * Include the cpu specific register header files.
14 *
15 * The CPU macro should be declared in the project or makefile.
16 */
17#if (defined(CPU_MIMX8MD7CVAHZ) || defined(CPU_MIMX8MD7DVAJZ))
18
19#define MIMX8MD7_cm4_SERIES
20
21/* Add global project definitions */
22#if defined(CMSIS_RTE_PROJECT)
23#include "RTE_Components.h"
24#endif
25/* CMSIS-style register definitions */
26#include "MIMX8MD7_cm4.h"
27/* CPU specific feature definitions */
28#include "MIMX8MD7_cm4_features.h"
29
30#else
31 #error "No valid CPU defined!"
32#endif
33
34#endif /* __FSL_DEVICE_REGISTERS_H__ */
35
36/*******************************************************************************
37 * EOF
38 ******************************************************************************/
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/MIMX8MD7xxxHZ_cm4_ddr_ram.ld b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/MIMX8MD7xxxHZ_cm4_ddr_ram.ld
new file mode 100644
index 000000000..405cc76a6
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/MIMX8MD7xxxHZ_cm4_ddr_ram.ld
@@ -0,0 +1,226 @@
1/*
2** ###################################################################
3** Processor: MIMX8MD7CVAHZ
4** Compiler: GNU C Compiler
5** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018
6** Version: rev. 4.0, 2018-01-26
7** Build: b200331
8**
9** Abstract:
10** Linker file for the GNU C Compiler
11**
12** Copyright 2016 Freescale Semiconductor, Inc.
13** Copyright 2016-2020 NXP
14** All rights reserved.
15**
16** SPDX-License-Identifier: BSD-3-Clause
17**
18** http: www.nxp.com
19** mail: [email protected]
20**
21** ###################################################################
22*/
23
24/* Entry Point */
25ENTRY(Reset_Handler)
26
27HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
28STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
29
30/* Specify the memory areas */
31MEMORY
32{
33 m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240
34 m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0
35 m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000
36 m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000
37}
38
39/* Define output sections */
40SECTIONS
41{
42/* The startup code goes first into internal RAM */
43 .interrupts :
44 {
45 __VECTOR_TABLE = .;
46 __Vectors = .;
47 . = ALIGN(4);
48 KEEP(*(.isr_vector)) /* Startup code */
49 . = ALIGN(4);
50 } > m_interrupts
51
52 .resource_table :
53 {
54 . = ALIGN(8);
55 KEEP(*(.resource_table)) /* Resource table */
56 . = ALIGN(8);
57 } > m_text
58
59 /* The program code and other data goes into internal RAM */
60 .text :
61 {
62 . = ALIGN(4);
63 *(.text) /* .text sections (code) */
64 *(.text*) /* .text* sections (code) */
65 *(.rodata) /* .rodata sections (constants, strings, etc.) */
66 *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
67 *(.glue_7) /* glue arm to thumb code */
68 *(.glue_7t) /* glue thumb to arm code */
69 *(.eh_frame)
70 KEEP (*(.init))
71 KEEP (*(.fini))
72 . = ALIGN(4);
73 } > m_text
74
75 .ARM.extab :
76 {
77 *(.ARM.extab* .gnu.linkonce.armextab.*)
78 } > m_text
79
80 .ARM :
81 {
82 __exidx_start = .;
83 *(.ARM.exidx*)
84 __exidx_end = .;
85 } > m_text
86
87 .ctors :
88 {
89 __CTOR_LIST__ = .;
90 /* gcc uses crtbegin.o to find the start of
91 the constructors, so we make sure it is
92 first. Because this is a wildcard, it
93 doesn't matter if the user does not
94 actually link against crtbegin.o; the
95 linker won't look for a file to match a
96 wildcard. The wildcard also means that it
97 doesn't matter which directory crtbegin.o
98 is in. */
99 KEEP (*crtbegin.o(.ctors))
100 KEEP (*crtbegin?.o(.ctors))
101 /* We don't want to include the .ctor section from
102 from the crtend.o file until after the sorted ctors.
103 The .ctor section from the crtend file contains the
104 end of ctors marker and it must be last */
105 KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
106 KEEP (*(SORT(.ctors.*)))
107 KEEP (*(.ctors))
108 __CTOR_END__ = .;
109 } > m_text
110
111 .dtors :
112 {
113 __DTOR_LIST__ = .;
114 KEEP (*crtbegin.o(.dtors))
115 KEEP (*crtbegin?.o(.dtors))
116 KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
117 KEEP (*(SORT(.dtors.*)))
118 KEEP (*(.dtors))
119 __DTOR_END__ = .;
120 } > m_text
121
122 .preinit_array :
123 {
124 PROVIDE_HIDDEN (__preinit_array_start = .);
125 KEEP (*(.preinit_array*))
126 PROVIDE_HIDDEN (__preinit_array_end = .);
127 } > m_text
128
129 .init_array :
130 {
131 PROVIDE_HIDDEN (__init_array_start = .);
132 KEEP (*(SORT(.init_array.*)))
133 KEEP (*(.init_array*))
134 PROVIDE_HIDDEN (__init_array_end = .);
135 } > m_text
136
137 .fini_array :
138 {
139 PROVIDE_HIDDEN (__fini_array_start = .);
140 KEEP (*(SORT(.fini_array.*)))
141 KEEP (*(.fini_array*))
142 PROVIDE_HIDDEN (__fini_array_end = .);
143 } > m_text
144
145 __etext = .; /* define a global symbol at end of code */
146 __DATA_ROM = .; /* Symbol is used by startup for data initialization */
147
148 .data : AT(__DATA_ROM)
149 {
150 . = ALIGN(4);
151 __DATA_RAM = .;
152 __data_start__ = .; /* create a global symbol at data start */
153 *(.data) /* .data sections */
154 *(.data*) /* .data* sections */
155 KEEP(*(.jcr*))
156 . = ALIGN(4);
157 __data_end__ = .; /* define a global symbol at data end */
158 } > m_data
159
160 __CACHE_REGION_START = ORIGIN(m_interrupts);
161 __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
162
163 __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
164
165 .ncache.init : AT(__NDATA_ROM)
166 {
167 __noncachedata_start__ = .; /* create a global symbol at ncache data start */
168 *(NonCacheable.init)
169 . = ALIGN(4);
170 __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
171 } > m_data2
172
173 . = __noncachedata_init_end__;
174 .ncache :
175 {
176 *(NonCacheable)
177 . = ALIGN(4);
178 __noncachedata_end__ = .; /* define a global symbol at ncache data end */
179 } > m_data2
180
181 __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
182 text_end = ORIGIN(m_text) + LENGTH(m_text);
183 ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
184
185 /* Uninitialized data section */
186 .bss :
187 {
188 /* This is used by the startup in order to initialize the .bss section */
189 . = ALIGN(4);
190 __START_BSS = .;
191 __bss_start__ = .;
192 *(.bss)
193 *(.bss*)
194 *(COMMON)
195 . = ALIGN(4);
196 __bss_end__ = .;
197 __END_BSS = .;
198 } > m_data
199
200 .heap :
201 {
202 . = ALIGN(8);
203 __end__ = .;
204 PROVIDE(end = .);
205 __HeapBase = .;
206 . += HEAP_SIZE;
207 __HeapLimit = .;
208 __heap_limit = .; /* Add for _sbrk */
209 } > m_data
210
211 .stack :
212 {
213 . = ALIGN(8);
214 . += STACK_SIZE;
215 } > m_data
216
217 /* Initializes stack on the end of block */
218 __StackTop = ORIGIN(m_data) + LENGTH(m_data);
219 __StackLimit = __StackTop - STACK_SIZE;
220 PROVIDE(__stack = __StackTop);
221
222 .ARM.attributes 0 : { *(.ARM.attributes) }
223
224 ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
225}
226
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/MIMX8MD7xxxHZ_cm4_ram.ld b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/MIMX8MD7xxxHZ_cm4_ram.ld
new file mode 100644
index 000000000..b7a5e9769
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/MIMX8MD7xxxHZ_cm4_ram.ld
@@ -0,0 +1,225 @@
1/*
2** ###################################################################
3** Processor: MIMX8MD7CVAHZ
4** Compiler: GNU C Compiler
5** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018
6** Version: rev. 4.0, 2018-01-26
7** Build: b200331
8**
9** Abstract:
10** Linker file for the GNU C Compiler
11**
12** Copyright 2016 Freescale Semiconductor, Inc.
13** Copyright 2016-2020 NXP
14** All rights reserved.
15**
16** SPDX-License-Identifier: BSD-3-Clause
17**
18** http: www.nxp.com
19** mail: [email protected]
20**
21** ###################################################################
22*/
23
24/* Entry Point */
25ENTRY(Reset_Handler)
26
27HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
28STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
29
30/* Specify the memory areas */
31MEMORY
32{
33 m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
34 m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
35 m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
36 m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000
37}
38
39/* Define output sections */
40SECTIONS
41{
42/* The startup code goes first into internal RAM */
43 .interrupts :
44 {
45 __VECTOR_TABLE = .;
46 __Vectors = .;
47 . = ALIGN(4);
48 KEEP(*(.isr_vector)) /* Startup code */
49 . = ALIGN(4);
50 } > m_interrupts
51
52 .resource_table :
53 {
54 . = ALIGN(8);
55 KEEP(*(.resource_table)) /* Resource table */
56 . = ALIGN(8);
57 } > m_text
58
59 /* The program code and other data goes into internal RAM */
60 .text :
61 {
62 . = ALIGN(4);
63 *(.text) /* .text sections (code) */
64 *(.text*) /* .text* sections (code) */
65 *(.rodata) /* .rodata sections (constants, strings, etc.) */
66 *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
67 *(.glue_7) /* glue arm to thumb code */
68 *(.glue_7t) /* glue thumb to arm code */
69 *(.eh_frame)
70 KEEP (*(.init))
71 KEEP (*(.fini))
72 . = ALIGN(4);
73 } > m_text
74
75 .ARM.extab :
76 {
77 *(.ARM.extab* .gnu.linkonce.armextab.*)
78 } > m_text
79
80 .ARM :
81 {
82 __exidx_start = .;
83 *(.ARM.exidx*)
84 __exidx_end = .;
85 } > m_text
86
87 .ctors :
88 {
89 __CTOR_LIST__ = .;
90 /* gcc uses crtbegin.o to find the start of
91 the constructors, so we make sure it is
92 first. Because this is a wildcard, it
93 doesn't matter if the user does not
94 actually link against crtbegin.o; the
95 linker won't look for a file to match a
96 wildcard. The wildcard also means that it
97 doesn't matter which directory crtbegin.o
98 is in. */
99 KEEP (*crtbegin.o(.ctors))
100 KEEP (*crtbegin?.o(.ctors))
101 /* We don't want to include the .ctor section from
102 from the crtend.o file until after the sorted ctors.
103 The .ctor section from the crtend file contains the
104 end of ctors marker and it must be last */
105 KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
106 KEEP (*(SORT(.ctors.*)))
107 KEEP (*(.ctors))
108 __CTOR_END__ = .;
109 } > m_text
110
111 .dtors :
112 {
113 __DTOR_LIST__ = .;
114 KEEP (*crtbegin.o(.dtors))
115 KEEP (*crtbegin?.o(.dtors))
116 KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
117 KEEP (*(SORT(.dtors.*)))
118 KEEP (*(.dtors))
119 __DTOR_END__ = .;
120 } > m_text
121
122 .preinit_array :
123 {
124 PROVIDE_HIDDEN (__preinit_array_start = .);
125 KEEP (*(.preinit_array*))
126 PROVIDE_HIDDEN (__preinit_array_end = .);
127 } > m_text
128
129 .init_array :
130 {
131 PROVIDE_HIDDEN (__init_array_start = .);
132 KEEP (*(SORT(.init_array.*)))
133 KEEP (*(.init_array*))
134 PROVIDE_HIDDEN (__init_array_end = .);
135 } > m_text
136
137 .fini_array :
138 {
139 PROVIDE_HIDDEN (__fini_array_start = .);
140 KEEP (*(SORT(.fini_array.*)))
141 KEEP (*(.fini_array*))
142 PROVIDE_HIDDEN (__fini_array_end = .);
143 } > m_text
144
145 __etext = .; /* define a global symbol at end of code */
146 __DATA_ROM = .; /* Symbol is used by startup for data initialization */
147
148 .data : AT(__DATA_ROM)
149 {
150 . = ALIGN(4);
151 __DATA_RAM = .;
152 __data_start__ = .; /* create a global symbol at data start */
153 *(.data) /* .data sections */
154 *(.data*) /* .data* sections */
155 KEEP(*(.jcr*))
156 . = ALIGN(4);
157 __data_end__ = .; /* define a global symbol at data end */
158 } > m_data
159
160 __CACHE_REGION_START = ORIGIN(m_interrupts);
161 __CACHE_REGION_SIZE = 0;
162 __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
163
164 .ncache.init : AT(__NDATA_ROM)
165 {
166 __noncachedata_start__ = .; /* create a global symbol at ncache data start */
167 *(NonCacheable.init)
168 . = ALIGN(4);
169 __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
170 } > m_data2
171
172 . = __noncachedata_init_end__;
173 .ncache :
174 {
175 *(NonCacheable)
176 . = ALIGN(4);
177 __noncachedata_end__ = .; /* define a global symbol at ncache data end */
178 } > m_data2
179
180 __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
181 text_end = ORIGIN(m_text) + LENGTH(m_text);
182 ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
183
184 /* Uninitialized data section */
185 .bss :
186 {
187 /* This is used by the startup in order to initialize the .bss section */
188 . = ALIGN(4);
189 __START_BSS = .;
190 __bss_start__ = .;
191 *(.bss)
192 *(.bss*)
193 *(COMMON)
194 . = ALIGN(4);
195 __bss_end__ = .;
196 __END_BSS = .;
197 } > m_data
198
199 .heap :
200 {
201 . = ALIGN(8);
202 __end__ = .;
203 PROVIDE(end = .);
204 __HeapBase = .;
205 . += HEAP_SIZE;
206 __HeapLimit = .;
207 __heap_limit = .; /* Add for _sbrk */
208 } > m_data
209
210 .stack :
211 {
212 . = ALIGN(8);
213 . += STACK_SIZE;
214 } > m_data
215
216 /* Initializes stack on the end of block */
217 __StackTop = ORIGIN(m_data) + LENGTH(m_data);
218 __StackLimit = __StackTop - STACK_SIZE;
219 PROVIDE(__stack = __StackTop);
220
221 .ARM.attributes 0 : { *(.ARM.attributes) }
222
223 ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
224}
225
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/MIMX8MD7xxxJZ_cm4_ddr_ram.ld b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/MIMX8MD7xxxJZ_cm4_ddr_ram.ld
new file mode 100644
index 000000000..d5525e22a
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/MIMX8MD7xxxJZ_cm4_ddr_ram.ld
@@ -0,0 +1,226 @@
1/*
2** ###################################################################
3** Processor: MIMX8MD7DVAJZ
4** Compiler: GNU C Compiler
5** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018
6** Version: rev. 4.0, 2018-01-26
7** Build: b200331
8**
9** Abstract:
10** Linker file for the GNU C Compiler
11**
12** Copyright 2016 Freescale Semiconductor, Inc.
13** Copyright 2016-2020 NXP
14** All rights reserved.
15**
16** SPDX-License-Identifier: BSD-3-Clause
17**
18** http: www.nxp.com
19** mail: [email protected]
20**
21** ###################################################################
22*/
23
24/* Entry Point */
25ENTRY(Reset_Handler)
26
27HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
28STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
29
30/* Specify the memory areas */
31MEMORY
32{
33 m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000240
34 m_text (RX) : ORIGIN = 0x80000240, LENGTH = 0x001FFDC0
35 m_data (RW) : ORIGIN = 0x80200000, LENGTH = 0x00200000
36 m_data2 (RW) : ORIGIN = 0x80400000, LENGTH = 0x00C00000
37}
38
39/* Define output sections */
40SECTIONS
41{
42/* The startup code goes first into internal RAM */
43 .interrupts :
44 {
45 __VECTOR_TABLE = .;
46 __Vectors = .;
47 . = ALIGN(4);
48 KEEP(*(.isr_vector)) /* Startup code */
49 . = ALIGN(4);
50 } > m_interrupts
51
52 .resource_table :
53 {
54 . = ALIGN(8);
55 KEEP(*(.resource_table)) /* Resource table */
56 . = ALIGN(8);
57 } > m_text
58
59 /* The program code and other data goes into internal RAM */
60 .text :
61 {
62 . = ALIGN(4);
63 *(.text) /* .text sections (code) */
64 *(.text*) /* .text* sections (code) */
65 *(.rodata) /* .rodata sections (constants, strings, etc.) */
66 *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
67 *(.glue_7) /* glue arm to thumb code */
68 *(.glue_7t) /* glue thumb to arm code */
69 *(.eh_frame)
70 KEEP (*(.init))
71 KEEP (*(.fini))
72 . = ALIGN(4);
73 } > m_text
74
75 .ARM.extab :
76 {
77 *(.ARM.extab* .gnu.linkonce.armextab.*)
78 } > m_text
79
80 .ARM :
81 {
82 __exidx_start = .;
83 *(.ARM.exidx*)
84 __exidx_end = .;
85 } > m_text
86
87 .ctors :
88 {
89 __CTOR_LIST__ = .;
90 /* gcc uses crtbegin.o to find the start of
91 the constructors, so we make sure it is
92 first. Because this is a wildcard, it
93 doesn't matter if the user does not
94 actually link against crtbegin.o; the
95 linker won't look for a file to match a
96 wildcard. The wildcard also means that it
97 doesn't matter which directory crtbegin.o
98 is in. */
99 KEEP (*crtbegin.o(.ctors))
100 KEEP (*crtbegin?.o(.ctors))
101 /* We don't want to include the .ctor section from
102 from the crtend.o file until after the sorted ctors.
103 The .ctor section from the crtend file contains the
104 end of ctors marker and it must be last */
105 KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
106 KEEP (*(SORT(.ctors.*)))
107 KEEP (*(.ctors))
108 __CTOR_END__ = .;
109 } > m_text
110
111 .dtors :
112 {
113 __DTOR_LIST__ = .;
114 KEEP (*crtbegin.o(.dtors))
115 KEEP (*crtbegin?.o(.dtors))
116 KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
117 KEEP (*(SORT(.dtors.*)))
118 KEEP (*(.dtors))
119 __DTOR_END__ = .;
120 } > m_text
121
122 .preinit_array :
123 {
124 PROVIDE_HIDDEN (__preinit_array_start = .);
125 KEEP (*(.preinit_array*))
126 PROVIDE_HIDDEN (__preinit_array_end = .);
127 } > m_text
128
129 .init_array :
130 {
131 PROVIDE_HIDDEN (__init_array_start = .);
132 KEEP (*(SORT(.init_array.*)))
133 KEEP (*(.init_array*))
134 PROVIDE_HIDDEN (__init_array_end = .);
135 } > m_text
136
137 .fini_array :
138 {
139 PROVIDE_HIDDEN (__fini_array_start = .);
140 KEEP (*(SORT(.fini_array.*)))
141 KEEP (*(.fini_array*))
142 PROVIDE_HIDDEN (__fini_array_end = .);
143 } > m_text
144
145 __etext = .; /* define a global symbol at end of code */
146 __DATA_ROM = .; /* Symbol is used by startup for data initialization */
147
148 .data : AT(__DATA_ROM)
149 {
150 . = ALIGN(4);
151 __DATA_RAM = .;
152 __data_start__ = .; /* create a global symbol at data start */
153 *(.data) /* .data sections */
154 *(.data*) /* .data* sections */
155 KEEP(*(.jcr*))
156 . = ALIGN(4);
157 __data_end__ = .; /* define a global symbol at data end */
158 } > m_data
159
160 __CACHE_REGION_START = ORIGIN(m_interrupts);
161 __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
162
163 __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
164
165 .ncache.init : AT(__NDATA_ROM)
166 {
167 __noncachedata_start__ = .; /* create a global symbol at ncache data start */
168 *(NonCacheable.init)
169 . = ALIGN(4);
170 __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
171 } > m_data2
172
173 . = __noncachedata_init_end__;
174 .ncache :
175 {
176 *(NonCacheable)
177 . = ALIGN(4);
178 __noncachedata_end__ = .; /* define a global symbol at ncache data end */
179 } > m_data2
180
181 __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
182 text_end = ORIGIN(m_text) + LENGTH(m_text);
183 ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
184
185 /* Uninitialized data section */
186 .bss :
187 {
188 /* This is used by the startup in order to initialize the .bss section */
189 . = ALIGN(4);
190 __START_BSS = .;
191 __bss_start__ = .;
192 *(.bss)
193 *(.bss*)
194 *(COMMON)
195 . = ALIGN(4);
196 __bss_end__ = .;
197 __END_BSS = .;
198 } > m_data
199
200 .heap :
201 {
202 . = ALIGN(8);
203 __end__ = .;
204 PROVIDE(end = .);
205 __HeapBase = .;
206 . += HEAP_SIZE;
207 __HeapLimit = .;
208 __heap_limit = .; /* Add for _sbrk */
209 } > m_data
210
211 .stack :
212 {
213 . = ALIGN(8);
214 . += STACK_SIZE;
215 } > m_data
216
217 /* Initializes stack on the end of block */
218 __StackTop = ORIGIN(m_data) + LENGTH(m_data);
219 __StackLimit = __StackTop - STACK_SIZE;
220 PROVIDE(__stack = __StackTop);
221
222 .ARM.attributes 0 : { *(.ARM.attributes) }
223
224 ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
225}
226
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/MIMX8MD7xxxJZ_cm4_ram.ld b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/MIMX8MD7xxxJZ_cm4_ram.ld
new file mode 100644
index 000000000..1dfc3be9f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/MIMX8MD7xxxJZ_cm4_ram.ld
@@ -0,0 +1,225 @@
1/*
2** ###################################################################
3** Processor: MIMX8MD7DVAJZ
4** Compiler: GNU C Compiler
5** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018
6** Version: rev. 4.0, 2018-01-26
7** Build: b200331
8**
9** Abstract:
10** Linker file for the GNU C Compiler
11**
12** Copyright 2016 Freescale Semiconductor, Inc.
13** Copyright 2016-2020 NXP
14** All rights reserved.
15**
16** SPDX-License-Identifier: BSD-3-Clause
17**
18** http: www.nxp.com
19** mail: [email protected]
20**
21** ###################################################################
22*/
23
24/* Entry Point */
25ENTRY(Reset_Handler)
26
27HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
28STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
29
30/* Specify the memory areas */
31MEMORY
32{
33 m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
34 m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
35 m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
36 m_data2 (RW) : ORIGIN = 0x80000000, LENGTH = 0x01000000
37}
38
39/* Define output sections */
40SECTIONS
41{
42/* The startup code goes first into internal RAM */
43 .interrupts :
44 {
45 __VECTOR_TABLE = .;
46 __Vectors = .;
47 . = ALIGN(4);
48 KEEP(*(.isr_vector)) /* Startup code */
49 . = ALIGN(4);
50 } > m_interrupts
51
52 .resource_table :
53 {
54 . = ALIGN(8);
55 KEEP(*(.resource_table)) /* Resource table */
56 . = ALIGN(8);
57 } > m_text
58
59 /* The program code and other data goes into internal RAM */
60 .text :
61 {
62 . = ALIGN(4);
63 *(.text) /* .text sections (code) */
64 *(.text*) /* .text* sections (code) */
65 *(.rodata) /* .rodata sections (constants, strings, etc.) */
66 *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
67 *(.glue_7) /* glue arm to thumb code */
68 *(.glue_7t) /* glue thumb to arm code */
69 *(.eh_frame)
70 KEEP (*(.init))
71 KEEP (*(.fini))
72 . = ALIGN(4);
73 } > m_text
74
75 .ARM.extab :
76 {
77 *(.ARM.extab* .gnu.linkonce.armextab.*)
78 } > m_text
79
80 .ARM :
81 {
82 __exidx_start = .;
83 *(.ARM.exidx*)
84 __exidx_end = .;
85 } > m_text
86
87 .ctors :
88 {
89 __CTOR_LIST__ = .;
90 /* gcc uses crtbegin.o to find the start of
91 the constructors, so we make sure it is
92 first. Because this is a wildcard, it
93 doesn't matter if the user does not
94 actually link against crtbegin.o; the
95 linker won't look for a file to match a
96 wildcard. The wildcard also means that it
97 doesn't matter which directory crtbegin.o
98 is in. */
99 KEEP (*crtbegin.o(.ctors))
100 KEEP (*crtbegin?.o(.ctors))
101 /* We don't want to include the .ctor section from
102 from the crtend.o file until after the sorted ctors.
103 The .ctor section from the crtend file contains the
104 end of ctors marker and it must be last */
105 KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
106 KEEP (*(SORT(.ctors.*)))
107 KEEP (*(.ctors))
108 __CTOR_END__ = .;
109 } > m_text
110
111 .dtors :
112 {
113 __DTOR_LIST__ = .;
114 KEEP (*crtbegin.o(.dtors))
115 KEEP (*crtbegin?.o(.dtors))
116 KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
117 KEEP (*(SORT(.dtors.*)))
118 KEEP (*(.dtors))
119 __DTOR_END__ = .;
120 } > m_text
121
122 .preinit_array :
123 {
124 PROVIDE_HIDDEN (__preinit_array_start = .);
125 KEEP (*(.preinit_array*))
126 PROVIDE_HIDDEN (__preinit_array_end = .);
127 } > m_text
128
129 .init_array :
130 {
131 PROVIDE_HIDDEN (__init_array_start = .);
132 KEEP (*(SORT(.init_array.*)))
133 KEEP (*(.init_array*))
134 PROVIDE_HIDDEN (__init_array_end = .);
135 } > m_text
136
137 .fini_array :
138 {
139 PROVIDE_HIDDEN (__fini_array_start = .);
140 KEEP (*(SORT(.fini_array.*)))
141 KEEP (*(.fini_array*))
142 PROVIDE_HIDDEN (__fini_array_end = .);
143 } > m_text
144
145 __etext = .; /* define a global symbol at end of code */
146 __DATA_ROM = .; /* Symbol is used by startup for data initialization */
147
148 .data : AT(__DATA_ROM)
149 {
150 . = ALIGN(4);
151 __DATA_RAM = .;
152 __data_start__ = .; /* create a global symbol at data start */
153 *(.data) /* .data sections */
154 *(.data*) /* .data* sections */
155 KEEP(*(.jcr*))
156 . = ALIGN(4);
157 __data_end__ = .; /* define a global symbol at data end */
158 } > m_data
159
160 __CACHE_REGION_START = ORIGIN(m_interrupts);
161 __CACHE_REGION_SIZE = 0;
162 __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
163
164 .ncache.init : AT(__NDATA_ROM)
165 {
166 __noncachedata_start__ = .; /* create a global symbol at ncache data start */
167 *(NonCacheable.init)
168 . = ALIGN(4);
169 __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
170 } > m_data2
171
172 . = __noncachedata_init_end__;
173 .ncache :
174 {
175 *(NonCacheable)
176 . = ALIGN(4);
177 __noncachedata_end__ = .; /* define a global symbol at ncache data end */
178 } > m_data2
179
180 __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
181 text_end = ORIGIN(m_text) + LENGTH(m_text);
182 ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
183
184 /* Uninitialized data section */
185 .bss :
186 {
187 /* This is used by the startup in order to initialize the .bss section */
188 . = ALIGN(4);
189 __START_BSS = .;
190 __bss_start__ = .;
191 *(.bss)
192 *(.bss*)
193 *(COMMON)
194 . = ALIGN(4);
195 __bss_end__ = .;
196 __END_BSS = .;
197 } > m_data
198
199 .heap :
200 {
201 . = ALIGN(8);
202 __end__ = .;
203 PROVIDE(end = .);
204 __HeapBase = .;
205 . += HEAP_SIZE;
206 __HeapLimit = .;
207 __heap_limit = .; /* Add for _sbrk */
208 } > m_data
209
210 .stack :
211 {
212 . = ALIGN(8);
213 . += STACK_SIZE;
214 } > m_data
215
216 /* Initializes stack on the end of block */
217 __StackTop = ORIGIN(m_data) + LENGTH(m_data);
218 __StackLimit = __StackTop - STACK_SIZE;
219 PROVIDE(__stack = __StackTop);
220
221 .ARM.attributes 0 : { *(.ARM.attributes) }
222
223 ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
224}
225
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/startup_MIMX8MD7_cm4.S b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/startup_MIMX8MD7_cm4.S
new file mode 100644
index 000000000..d1836ae5a
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/gcc/startup_MIMX8MD7_cm4.S
@@ -0,0 +1,754 @@
1/* ------------------------------------------------------------------------- */
2/* @file: startup_MIMX8MD7_cm4.s */
3/* @purpose: CMSIS Cortex-M4 Core Device Startup File */
4/* MIMX8MD7_cm4 */
5/* @version: 4.0 */
6/* @date: 2018-1-26 */
7/* @build: b190124 */
8/* ------------------------------------------------------------------------- */
9/* */
10/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
11/* Copyright 2016-2019 NXP */
12/* All rights reserved. */
13/* */
14/* SPDX-License-Identifier: BSD-3-Clause */
15/*****************************************************************************/
16/* Version: GCC for ARM Embedded Processors */
17/*****************************************************************************/
18 .syntax unified
19 .arch armv7-m
20
21 .section .isr_vector, "a"
22 .align 2
23 .globl __isr_vector
24__isr_vector:
25 .long __StackTop /* Top of Stack */
26 .long Reset_Handler /* Reset Handler */
27 .long NMI_Handler /* NMI Handler*/
28 .long HardFault_Handler /* Hard Fault Handler*/
29 .long MemManage_Handler /* MPU Fault Handler*/
30 .long BusFault_Handler /* Bus Fault Handler*/
31 .long UsageFault_Handler /* Usage Fault Handler*/
32 .long 0 /* Reserved*/
33 .long 0 /* Reserved*/
34 .long 0 /* Reserved*/
35 .long 0 /* Reserved*/
36 .long SVC_Handler /* SVCall Handler*/
37 .long DebugMon_Handler /* Debug Monitor Handler*/
38 .long 0 /* Reserved*/
39 .long PendSV_Handler /* PendSV Handler*/
40 .long SysTick_Handler /* SysTick Handler*/
41
42 /* External Interrupts*/
43 .long GPR_IRQ_IRQHandler /* GPR Interrupt. Used to notify cores on exception condition while boot.*/
44 .long DAP_IRQHandler /* DAP Interrupt*/
45 .long SDMA1_IRQHandler /* AND of all 48 SDMA interrupts (events) from all the channels*/
46 .long GPU_IRQHandler /* GPU Interrupt*/
47 .long SNVS_IRQHandler /* ON-OFF button press shorter than 5 seconds (pulse event)*/
48 .long LCDIF_IRQHandler /* LCDIF Sync Interrupt*/
49 .long SPDIF1_IRQHandler /* SPDIF1 Interrupt*/
50 .long H264_IRQHandler /* h264 Decoder Interrupt*/
51 .long VPUDMA_IRQHandler /* VPU DMA Interrupt*/
52 .long QOS_IRQHandler /* QOS interrupt*/
53 .long WDOG3_IRQHandler /* Watchdog Timer reset*/
54 .long HS_CP1_IRQHandler /* HS Interrupt Request*/
55 .long APBHDMA_IRQHandler /* GPMI operation channel 0-3 description complete interrupt*/
56 .long SPDIF2_IRQHandler /* SPDIF2 Interrupt*/
57 .long BCH_IRQHandler /* BCH operation complete interrupt*/
58 .long GPMI_IRQHandler /* GPMI operation TIMEOUT ERROR interrupt*/
59 .long HDMI_IRQ0_IRQHandler /* HDMI Interrupt 0*/
60 .long HDMI_IRQ1_IRQHandler /* HDMI Interrupt 1*/
61 .long HDMI_IRQ2_IRQHandler /* HDMI Interrupt 2*/
62 .long SNVS_Consolidated_IRQHandler /* SRTC Consolidated Interrupt. Non TZ.*/
63 .long SNVS_Security_IRQHandler /* SRTC Security Interrupt. TZ.*/
64 .long CSU_IRQHandler /* CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted.*/
65 .long USDHC1_IRQHandler /* uSDHC1 Enhanced SDHC Interrupt Request*/
66 .long USDHC2_IRQHandler /* uSDHC2 Enhanced SDHC Interrupt Request*/
67 .long DDC_IRQHandler /* DC8000 Display Controller IRQ*/
68 .long DTRC_IRQHandler /* DTRC interrupt*/
69 .long UART1_IRQHandler /* UART-1 ORed interrupt*/
70 .long UART2_IRQHandler /* UART-2 ORed interrupt*/
71 .long UART3_IRQHandler /* UART-3 ORed interrupt*/
72 .long UART4_IRQHandler /* UART-4 ORed interrupt*/
73 .long VP9_IRQHandler /* VP9 Decoder interrupt*/
74 .long ECSPI1_IRQHandler /* ECSPI1 interrupt request line to the core.*/
75 .long ECSPI2_IRQHandler /* ECSPI2 interrupt request line to the core.*/
76 .long ECSPI3_IRQHandler /* ECSPI3 interrupt request line to the core.*/
77 .long MIPI_DSI_IRQHandler /* DSI Interrupt*/
78 .long I2C1_IRQHandler /* I2C-1 Interrupt*/
79 .long I2C2_IRQHandler /* I2C-2 Interrupt*/
80 .long I2C3_IRQHandler /* I2C-3 Interrupt*/
81 .long I2C4_IRQHandler /* I2C-4 Interrupt*/
82 .long RDC_IRQHandler /* RDC interrupt*/
83 .long USB1_IRQHandler /* USB1 Interrupt*/
84 .long USB2_IRQHandler /* USB1 Interrupt*/
85 .long CSI1_IRQHandler /* CSI1 interrupt*/
86 .long CSI2_IRQHandler /* CSI2 interrupt*/
87 .long MIPI_CSI1_IRQHandler /* MIPI-CSI-1 Interrupt*/
88 .long MIPI_CSI2_IRQHandler /* MIPI-CSI-2 Interrupt*/
89 .long GPT6_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/
90 .long SCTR_IRQ0_IRQHandler /* ISO7816IP Interrupt 0*/
91 .long SCTR_IRQ1_IRQHandler /* ISO7816IP Interrupt 1*/
92 .long TEMPMON_IRQHandler /* TempSensor (Temperature alarm).*/
93 .long I2S3_IRQHandler /* SAI3 Receive / Transmit Interrupt*/
94 .long GPT5_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/
95 .long GPT4_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/
96 .long GPT3_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/
97 .long GPT2_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/
98 .long GPT1_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/
99 .long GPIO1_INT7_IRQHandler /* Active HIGH Interrupt from INT7 from GPIO*/
100 .long GPIO1_INT6_IRQHandler /* Active HIGH Interrupt from INT6 from GPIO*/
101 .long GPIO1_INT5_IRQHandler /* Active HIGH Interrupt from INT5 from GPIO*/
102 .long GPIO1_INT4_IRQHandler /* Active HIGH Interrupt from INT4 from GPIO*/
103 .long GPIO1_INT3_IRQHandler /* Active HIGH Interrupt from INT3 from GPIO*/
104 .long GPIO1_INT2_IRQHandler /* Active HIGH Interrupt from INT2 from GPIO*/
105 .long GPIO1_INT1_IRQHandler /* Active HIGH Interrupt from INT1 from GPIO*/
106 .long GPIO1_INT0_IRQHandler /* Active HIGH Interrupt from INT0 from GPIO*/
107 .long GPIO1_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO1 signal 0 throughout 15*/
108 .long GPIO1_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO1 signal 16 throughout 31*/
109 .long GPIO2_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO2 signal 0 throughout 15*/
110 .long GPIO2_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO2 signal 16 throughout 31*/
111 .long GPIO3_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO3 signal 0 throughout 15*/
112 .long GPIO3_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO3 signal 16 throughout 31*/
113 .long GPIO4_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO4 signal 0 throughout 15*/
114 .long GPIO4_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO4 signal 16 throughout 31*/
115 .long GPIO5_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO5 signal 0 throughout 15*/
116 .long GPIO5_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO5 signal 16 throughout 31*/
117 .long PCIE_CTRL2_IRQ0_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/
118 .long PCIE_CTRL2_IRQ1_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/
119 .long PCIE_CTRL2_IRQ2_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/
120 .long PCIE_CTRL2_IRQ3_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/
121 .long WDOG1_IRQHandler /* Watchdog Timer reset*/
122 .long WDOG2_IRQHandler /* Watchdog Timer reset*/
123 .long PCIE_CTRL2_IRQHandler /* Channels [63:32] interrupts requests*/
124 .long PWM1_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/
125 .long PWM2_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/
126 .long PWM3_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/
127 .long PWM4_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/
128 .long CCM_IRQ1_IRQHandler /* CCM, Interrupt Request 1*/
129 .long CCM_IRQ2_IRQHandler /* CCM, Interrupt Request 2*/
130 .long GPC_IRQHandler /* GPC Interrupt Request 1*/
131 .long MU_A53_IRQHandler /* Interrupt to A53*/
132 .long SRC_IRQHandler /* SRC interrupt request*/
133 .long I2S56_IRQHandler /* SAI5/6 Receive / Transmit Interrupt*/
134 .long RTIC_IRQHandler /* RTIC Interrupt*/
135 .long CPU_PerformanceUnit_IRQHandler /* Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n]*/
136 .long CPU_CTI_Trigger_IRQHandler /* CTI trigger outputs (internal: nCTIIRQ[n]*/
137 .long SRC_Combined_IRQHandler /* Combined CPU wdog interrupts (4x) out of SRC.*/
138 .long I2S1_IRQHandler /* SAI1 Receive / Transmit Interrupt*/
139 .long I2S2_IRQHandler /* SAI2 Receive / Transmit Interrupt*/
140 .long MU_M4_IRQHandler /* Interrupt to M4*/
141 .long DDR_PerformanceMonitor_IRQHandler /* ddr Interrupt for performance monitor*/
142 .long DDR_IRQHandler /* ddr Interrupt*/
143 .long I2S4_IRQHandler /* SAI4 Receive / Transmit Interrupt*/
144 .long CPU_Error_AXI_IRQHandler /* CPU Error indicator for AXI transaction with a write response error condition*/
145 .long CPU_Error_L2RAM_IRQHandler /* CPU Error indicator for L2 RAM double-bit ECC error*/
146 .long SDMA2_IRQHandler /* AND of all 48 SDMA interrupts (events) from all the channels*/
147 .long Reserved120_IRQHandler /* Reserved*/
148 .long CAAM_IRQ0_IRQHandler /* CAAM interrupt queue for JQ*/
149 .long CAAM_IRQ1_IRQHandler /* CAAM interrupt queue for JQ*/
150 .long QSPI_IRQHandler /* QSPI Interrupt*/
151 .long TZASC_IRQHandler /* TZASC (PL380) interrupt*/
152 .long Reserved125_IRQHandler /* Reserved*/
153 .long Reserved126_IRQHandler /* Reserved*/
154 .long Reserved127_IRQHandler /* Reserved*/
155 .long PERFMON1_IRQHandler /* General Interrupt*/
156 .long PERFMON2_IRQHandler /* General Interrupt*/
157 .long CAAM_IRQ2_IRQHandler /* CAAM interrupt queue for JQ*/
158 .long CAAM_ERROR_IRQHandler /* Recoverable error interrupt*/
159 .long HS_CP0_IRQHandler /* HS Interrupt Request*/
160 .long HEVC_IRQHandler /* HEVC interrupt*/
161 .long ENET_MAC0_Rx_Tx_Done1_IRQHandler /* MAC 0 Receive / Trasmit Frame / Buffer Done*/
162 .long ENET_MAC0_Rx_Tx_Done2_IRQHandler /* MAC 0 Receive / Trasmit Frame / Buffer Done*/
163 .long ENET_IRQHandler /* MAC 0 IRQ*/
164 .long ENET_1588_IRQHandler /* MAC 0 1588 Timer Interrupt - synchronous*/
165 .long PCIE_CTRL1_IRQ0_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/
166 .long PCIE_CTRL1_IRQ1_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/
167 .long PCIE_CTRL1_IRQ2_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/
168 .long PCIE_CTRL1_IRQ3_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/
169 .long Reserved142_IRQHandler /* Reserved*/
170 .long PCIE_CTRL1_IRQHandler /* Channels [63:32] interrupts requests*/
171
172 .size __isr_vector, . - __isr_vector
173
174 .text
175 .thumb
176
177/* Reset Handler */
178
179 .thumb_func
180 .align 2
181 .globl Reset_Handler
182 .weak Reset_Handler
183 .type Reset_Handler, %function
184Reset_Handler:
185 cpsid i /* Mask interrupts */
186 .equ VTOR, 0xE000ED08
187 ldr r0, =VTOR
188 ldr r1, =__isr_vector
189 str r1, [r0]
190 ldr r2, [r1]
191 msr msp, r2
192#ifndef __NO_SYSTEM_INIT
193 ldr r0,=SystemInit
194 blx r0
195#endif
196/* Loop to copy data from read only memory to RAM. The ranges
197 * of copy from/to are specified by following symbols evaluated in
198 * linker script.
199 * __etext: End of code section, i.e., begin of data sections to copy from.
200 * __data_start__/__data_end__: RAM address range that data should be
201 * __noncachedata_start__/__noncachedata_end__ : none cachable region
202 * copied to. Both must be aligned to 4 bytes boundary. */
203
204 ldr r1, =__etext
205 ldr r2, =__data_start__
206 ldr r3, =__data_end__
207
208#ifdef __PERFORMANCE_IMPLEMENTATION
209/* Here are two copies of loop implementations. First one favors performance
210 * and the second one favors code size. Default uses the second one.
211 * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
212 subs r3, r2
213 ble .LC1
214.LC0:
215 subs r3, #4
216 ldr r0, [r1, r3]
217 str r0, [r2, r3]
218 bgt .LC0
219.LC1:
220#else /* code size implemenation */
221.LC0:
222 cmp r2, r3
223 ittt lt
224 ldrlt r0, [r1], #4
225 strlt r0, [r2], #4
226 blt .LC0
227#endif
228#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
229 ldr r2, =__noncachedata_start__
230 ldr r3, =__noncachedata_init_end__
231#ifdef __PERFORMANCE_IMPLEMENTATION
232/* Here are two copies of loop implementations. First one favors performance
233 * and the second one favors code size. Default uses the second one.
234 * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
235 subs r3, r2
236 ble .LC3
237.LC2:
238 subs r3, #4
239 ldr r0, [r1, r3]
240 str r0, [r2, r3]
241 bgt .LC2
242.LC3:
243#else /* code size implemenation */
244.LC2:
245 cmp r2, r3
246 ittt lt
247 ldrlt r0, [r1], #4
248 strlt r0, [r2], #4
249 blt .LC2
250#endif
251/* zero inited ncache section initialization */
252 ldr r3, =__noncachedata_end__
253 movs r0,0
254.LC4:
255 cmp r2,r3
256 itt lt
257 strlt r0,[r2],#4
258 blt .LC4
259#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */
260
261#ifdef __STARTUP_CLEAR_BSS
262/* This part of work usually is done in C library startup code. Otherwise,
263 * define this macro to enable it in this startup.
264 *
265 * Loop to zero out BSS section, which uses following symbols
266 * in linker script:
267 * __bss_start__: start of BSS section. Must align to 4
268 * __bss_end__: end of BSS section. Must align to 4
269 */
270 ldr r1, =__bss_start__
271 ldr r2, =__bss_end__
272
273 movs r0, 0
274.LC5:
275 cmp r1, r2
276 itt lt
277 strlt r0, [r1], #4
278 blt .LC5
279#endif /* __STARTUP_CLEAR_BSS */
280
281 cpsie i /* Unmask interrupts */
282#ifndef __START
283#define __START _start
284#endif
285#ifndef __ATOLLIC__
286 ldr r0,=__START
287 blx r0
288#else
289 ldr r0,=__libc_init_array
290 blx r0
291 ldr r0,=main
292 bx r0
293#endif
294 .pool
295 .size Reset_Handler, . - Reset_Handler
296
297 .align 1
298 .thumb_func
299 .weak DefaultISR
300 .type DefaultISR, %function
301DefaultISR:
302 b DefaultISR
303 .size DefaultISR, . - DefaultISR
304
305 .align 1
306 .thumb_func
307 .weak NMI_Handler
308 .type NMI_Handler, %function
309NMI_Handler:
310 ldr r0,=NMI_Handler
311 bx r0
312 .size NMI_Handler, . - NMI_Handler
313
314 .align 1
315 .thumb_func
316 .weak HardFault_Handler
317 .type HardFault_Handler, %function
318HardFault_Handler:
319 ldr r0,=HardFault_Handler
320 bx r0
321 .size HardFault_Handler, . - HardFault_Handler
322
323 .align 1
324 .thumb_func
325 .weak SVC_Handler
326 .type SVC_Handler, %function
327SVC_Handler:
328 ldr r0,=SVC_Handler
329 bx r0
330 .size SVC_Handler, . - SVC_Handler
331
332 .align 1
333 .thumb_func
334 .weak PendSV_Handler
335 .type PendSV_Handler, %function
336PendSV_Handler:
337 ldr r0,=PendSV_Handler
338 bx r0
339 .size PendSV_Handler, . - PendSV_Handler
340
341 .align 1
342 .thumb_func
343 .weak SysTick_Handler
344 .type SysTick_Handler, %function
345SysTick_Handler:
346 ldr r0,=SysTick_Handler
347 bx r0
348 .size SysTick_Handler, . - SysTick_Handler
349
350 .align 1
351 .thumb_func
352 .weak SDMA1_IRQHandler
353 .type SDMA1_IRQHandler, %function
354SDMA1_IRQHandler:
355 ldr r0,=SDMA1_DriverIRQHandler
356 bx r0
357 .size SDMA1_IRQHandler, . - SDMA1_IRQHandler
358
359 .align 1
360 .thumb_func
361 .weak SPDIF1_IRQHandler
362 .type SPDIF1_IRQHandler, %function
363SPDIF1_IRQHandler:
364 ldr r0,=SPDIF1_DriverIRQHandler
365 bx r0
366 .size SPDIF1_IRQHandler, . - SPDIF1_IRQHandler
367
368 .align 1
369 .thumb_func
370 .weak VPUDMA_IRQHandler
371 .type VPUDMA_IRQHandler, %function
372VPUDMA_IRQHandler:
373 ldr r0,=VPUDMA_DriverIRQHandler
374 bx r0
375 .size VPUDMA_IRQHandler, . - VPUDMA_IRQHandler
376
377 .align 1
378 .thumb_func
379 .weak APBHDMA_IRQHandler
380 .type APBHDMA_IRQHandler, %function
381APBHDMA_IRQHandler:
382 ldr r0,=APBHDMA_DriverIRQHandler
383 bx r0
384 .size APBHDMA_IRQHandler, . - APBHDMA_IRQHandler
385
386 .align 1
387 .thumb_func
388 .weak SPDIF2_IRQHandler
389 .type SPDIF2_IRQHandler, %function
390SPDIF2_IRQHandler:
391 ldr r0,=SPDIF2_DriverIRQHandler
392 bx r0
393 .size SPDIF2_IRQHandler, . - SPDIF2_IRQHandler
394
395 .align 1
396 .thumb_func
397 .weak USDHC1_IRQHandler
398 .type USDHC1_IRQHandler, %function
399USDHC1_IRQHandler:
400 ldr r0,=USDHC1_DriverIRQHandler
401 bx r0
402 .size USDHC1_IRQHandler, . - USDHC1_IRQHandler
403
404 .align 1
405 .thumb_func
406 .weak USDHC2_IRQHandler
407 .type USDHC2_IRQHandler, %function
408USDHC2_IRQHandler:
409 ldr r0,=USDHC2_DriverIRQHandler
410 bx r0
411 .size USDHC2_IRQHandler, . - USDHC2_IRQHandler
412
413 .align 1
414 .thumb_func
415 .weak UART1_IRQHandler
416 .type UART1_IRQHandler, %function
417UART1_IRQHandler:
418 ldr r0,=UART1_DriverIRQHandler
419 bx r0
420 .size UART1_IRQHandler, . - UART1_IRQHandler
421
422 .align 1
423 .thumb_func
424 .weak UART2_IRQHandler
425 .type UART2_IRQHandler, %function
426UART2_IRQHandler:
427 ldr r0,=UART2_DriverIRQHandler
428 bx r0
429 .size UART2_IRQHandler, . - UART2_IRQHandler
430
431 .align 1
432 .thumb_func
433 .weak UART3_IRQHandler
434 .type UART3_IRQHandler, %function
435UART3_IRQHandler:
436 ldr r0,=UART3_DriverIRQHandler
437 bx r0
438 .size UART3_IRQHandler, . - UART3_IRQHandler
439
440 .align 1
441 .thumb_func
442 .weak UART4_IRQHandler
443 .type UART4_IRQHandler, %function
444UART4_IRQHandler:
445 ldr r0,=UART4_DriverIRQHandler
446 bx r0
447 .size UART4_IRQHandler, . - UART4_IRQHandler
448
449 .align 1
450 .thumb_func
451 .weak ECSPI1_IRQHandler
452 .type ECSPI1_IRQHandler, %function
453ECSPI1_IRQHandler:
454 ldr r0,=ECSPI1_DriverIRQHandler
455 bx r0
456 .size ECSPI1_IRQHandler, . - ECSPI1_IRQHandler
457
458 .align 1
459 .thumb_func
460 .weak ECSPI2_IRQHandler
461 .type ECSPI2_IRQHandler, %function
462ECSPI2_IRQHandler:
463 ldr r0,=ECSPI2_DriverIRQHandler
464 bx r0
465 .size ECSPI2_IRQHandler, . - ECSPI2_IRQHandler
466
467 .align 1
468 .thumb_func
469 .weak ECSPI3_IRQHandler
470 .type ECSPI3_IRQHandler, %function
471ECSPI3_IRQHandler:
472 ldr r0,=ECSPI3_DriverIRQHandler
473 bx r0
474 .size ECSPI3_IRQHandler, . - ECSPI3_IRQHandler
475
476 .align 1
477 .thumb_func
478 .weak I2C1_IRQHandler
479 .type I2C1_IRQHandler, %function
480I2C1_IRQHandler:
481 ldr r0,=I2C1_DriverIRQHandler
482 bx r0
483 .size I2C1_IRQHandler, . - I2C1_IRQHandler
484
485 .align 1
486 .thumb_func
487 .weak I2C2_IRQHandler
488 .type I2C2_IRQHandler, %function
489I2C2_IRQHandler:
490 ldr r0,=I2C2_DriverIRQHandler
491 bx r0
492 .size I2C2_IRQHandler, . - I2C2_IRQHandler
493
494 .align 1
495 .thumb_func
496 .weak I2C3_IRQHandler
497 .type I2C3_IRQHandler, %function
498I2C3_IRQHandler:
499 ldr r0,=I2C3_DriverIRQHandler
500 bx r0
501 .size I2C3_IRQHandler, . - I2C3_IRQHandler
502
503 .align 1
504 .thumb_func
505 .weak I2C4_IRQHandler
506 .type I2C4_IRQHandler, %function
507I2C4_IRQHandler:
508 ldr r0,=I2C4_DriverIRQHandler
509 bx r0
510 .size I2C4_IRQHandler, . - I2C4_IRQHandler
511
512 .align 1
513 .thumb_func
514 .weak I2S3_IRQHandler
515 .type I2S3_IRQHandler, %function
516I2S3_IRQHandler:
517 ldr r0,=I2S3_DriverIRQHandler
518 bx r0
519 .size I2S3_IRQHandler, . - I2S3_IRQHandler
520
521 .align 1
522 .thumb_func
523 .weak I2S56_IRQHandler
524 .type I2S56_IRQHandler, %function
525I2S56_IRQHandler:
526 ldr r0,=I2S56_DriverIRQHandler
527 bx r0
528 .size I2S56_IRQHandler, . - I2S56_IRQHandler
529
530 .align 1
531 .thumb_func
532 .weak I2S1_IRQHandler
533 .type I2S1_IRQHandler, %function
534I2S1_IRQHandler:
535 ldr r0,=I2S1_DriverIRQHandler
536 bx r0
537 .size I2S1_IRQHandler, . - I2S1_IRQHandler
538
539 .align 1
540 .thumb_func
541 .weak I2S2_IRQHandler
542 .type I2S2_IRQHandler, %function
543I2S2_IRQHandler:
544 ldr r0,=I2S2_DriverIRQHandler
545 bx r0
546 .size I2S2_IRQHandler, . - I2S2_IRQHandler
547
548 .align 1
549 .thumb_func
550 .weak I2S4_IRQHandler
551 .type I2S4_IRQHandler, %function
552I2S4_IRQHandler:
553 ldr r0,=I2S4_DriverIRQHandler
554 bx r0
555 .size I2S4_IRQHandler, . - I2S4_IRQHandler
556
557 .align 1
558 .thumb_func
559 .weak SDMA2_IRQHandler
560 .type SDMA2_IRQHandler, %function
561SDMA2_IRQHandler:
562 ldr r0,=SDMA2_DriverIRQHandler
563 bx r0
564 .size SDMA2_IRQHandler, . - SDMA2_IRQHandler
565
566 .align 1
567 .thumb_func
568 .weak QSPI_IRQHandler
569 .type QSPI_IRQHandler, %function
570QSPI_IRQHandler:
571 ldr r0,=QSPI_DriverIRQHandler
572 bx r0
573 .size QSPI_IRQHandler, . - QSPI_IRQHandler
574
575 .align 1
576 .thumb_func
577 .weak ENET_MAC0_Rx_Tx_Done1_IRQHandler
578 .type ENET_MAC0_Rx_Tx_Done1_IRQHandler, %function
579ENET_MAC0_Rx_Tx_Done1_IRQHandler:
580 ldr r0,=ENET_MAC0_Rx_Tx_Done1_DriverIRQHandler
581 bx r0
582 .size ENET_MAC0_Rx_Tx_Done1_IRQHandler, . - ENET_MAC0_Rx_Tx_Done1_IRQHandler
583
584 .align 1
585 .thumb_func
586 .weak ENET_MAC0_Rx_Tx_Done2_IRQHandler
587 .type ENET_MAC0_Rx_Tx_Done2_IRQHandler, %function
588ENET_MAC0_Rx_Tx_Done2_IRQHandler:
589 ldr r0,=ENET_MAC0_Rx_Tx_Done2_DriverIRQHandler
590 bx r0
591 .size ENET_MAC0_Rx_Tx_Done2_IRQHandler, . - ENET_MAC0_Rx_Tx_Done2_IRQHandler
592
593 .align 1
594 .thumb_func
595 .weak ENET_IRQHandler
596 .type ENET_IRQHandler, %function
597ENET_IRQHandler:
598 ldr r0,=ENET_DriverIRQHandler
599 bx r0
600 .size ENET_IRQHandler, . - ENET_IRQHandler
601
602 .align 1
603 .thumb_func
604 .weak ENET_1588_IRQHandler
605 .type ENET_1588_IRQHandler, %function
606ENET_1588_IRQHandler:
607 ldr r0,=ENET_1588_DriverIRQHandler
608 bx r0
609 .size ENET_1588_IRQHandler, . - ENET_1588_IRQHandler
610
611
612/* Macro to define default handlers. Default handler
613 * will be weak symbol and just dead loops. They can be
614 * overwritten by other handlers */
615 .macro def_irq_handler handler_name
616 .weak \handler_name
617 .set \handler_name, DefaultISR
618 .endm
619
620/* Exception Handlers */
621 def_irq_handler MemManage_Handler
622 def_irq_handler BusFault_Handler
623 def_irq_handler UsageFault_Handler
624 def_irq_handler DebugMon_Handler
625 def_irq_handler GPR_IRQ_IRQHandler
626 def_irq_handler DAP_IRQHandler
627 def_irq_handler SDMA1_DriverIRQHandler
628 def_irq_handler GPU_IRQHandler
629 def_irq_handler SNVS_IRQHandler
630 def_irq_handler LCDIF_IRQHandler
631 def_irq_handler SPDIF1_DriverIRQHandler
632 def_irq_handler H264_IRQHandler
633 def_irq_handler VPUDMA_DriverIRQHandler
634 def_irq_handler QOS_IRQHandler
635 def_irq_handler WDOG3_IRQHandler
636 def_irq_handler HS_CP1_IRQHandler
637 def_irq_handler APBHDMA_DriverIRQHandler
638 def_irq_handler SPDIF2_DriverIRQHandler
639 def_irq_handler BCH_IRQHandler
640 def_irq_handler GPMI_IRQHandler
641 def_irq_handler HDMI_IRQ0_IRQHandler
642 def_irq_handler HDMI_IRQ1_IRQHandler
643 def_irq_handler HDMI_IRQ2_IRQHandler
644 def_irq_handler SNVS_Consolidated_IRQHandler
645 def_irq_handler SNVS_Security_IRQHandler
646 def_irq_handler CSU_IRQHandler
647 def_irq_handler USDHC1_DriverIRQHandler
648 def_irq_handler USDHC2_DriverIRQHandler
649 def_irq_handler DDC_IRQHandler
650 def_irq_handler DTRC_IRQHandler
651 def_irq_handler UART1_DriverIRQHandler
652 def_irq_handler UART2_DriverIRQHandler
653 def_irq_handler UART3_DriverIRQHandler
654 def_irq_handler UART4_DriverIRQHandler
655 def_irq_handler VP9_IRQHandler
656 def_irq_handler ECSPI1_DriverIRQHandler
657 def_irq_handler ECSPI2_DriverIRQHandler
658 def_irq_handler ECSPI3_DriverIRQHandler
659 def_irq_handler MIPI_DSI_IRQHandler
660 def_irq_handler I2C1_DriverIRQHandler
661 def_irq_handler I2C2_DriverIRQHandler
662 def_irq_handler I2C3_DriverIRQHandler
663 def_irq_handler I2C4_DriverIRQHandler
664 def_irq_handler RDC_IRQHandler
665 def_irq_handler USB1_IRQHandler
666 def_irq_handler USB2_IRQHandler
667 def_irq_handler CSI1_IRQHandler
668 def_irq_handler CSI2_IRQHandler
669 def_irq_handler MIPI_CSI1_IRQHandler
670 def_irq_handler MIPI_CSI2_IRQHandler
671 def_irq_handler GPT6_IRQHandler
672 def_irq_handler SCTR_IRQ0_IRQHandler
673 def_irq_handler SCTR_IRQ1_IRQHandler
674 def_irq_handler TEMPMON_IRQHandler
675 def_irq_handler I2S3_DriverIRQHandler
676 def_irq_handler GPT5_IRQHandler
677 def_irq_handler GPT4_IRQHandler
678 def_irq_handler GPT3_IRQHandler
679 def_irq_handler GPT2_IRQHandler
680 def_irq_handler GPT1_IRQHandler
681 def_irq_handler GPIO1_INT7_IRQHandler
682 def_irq_handler GPIO1_INT6_IRQHandler
683 def_irq_handler GPIO1_INT5_IRQHandler
684 def_irq_handler GPIO1_INT4_IRQHandler
685 def_irq_handler GPIO1_INT3_IRQHandler
686 def_irq_handler GPIO1_INT2_IRQHandler
687 def_irq_handler GPIO1_INT1_IRQHandler
688 def_irq_handler GPIO1_INT0_IRQHandler
689 def_irq_handler GPIO1_Combined_0_15_IRQHandler
690 def_irq_handler GPIO1_Combined_16_31_IRQHandler
691 def_irq_handler GPIO2_Combined_0_15_IRQHandler
692 def_irq_handler GPIO2_Combined_16_31_IRQHandler
693 def_irq_handler GPIO3_Combined_0_15_IRQHandler
694 def_irq_handler GPIO3_Combined_16_31_IRQHandler
695 def_irq_handler GPIO4_Combined_0_15_IRQHandler
696 def_irq_handler GPIO4_Combined_16_31_IRQHandler
697 def_irq_handler GPIO5_Combined_0_15_IRQHandler
698 def_irq_handler GPIO5_Combined_16_31_IRQHandler
699 def_irq_handler PCIE_CTRL2_IRQ0_IRQHandler
700 def_irq_handler PCIE_CTRL2_IRQ1_IRQHandler
701 def_irq_handler PCIE_CTRL2_IRQ2_IRQHandler
702 def_irq_handler PCIE_CTRL2_IRQ3_IRQHandler
703 def_irq_handler WDOG1_IRQHandler
704 def_irq_handler WDOG2_IRQHandler
705 def_irq_handler PCIE_CTRL2_IRQHandler
706 def_irq_handler PWM1_IRQHandler
707 def_irq_handler PWM2_IRQHandler
708 def_irq_handler PWM3_IRQHandler
709 def_irq_handler PWM4_IRQHandler
710 def_irq_handler CCM_IRQ1_IRQHandler
711 def_irq_handler CCM_IRQ2_IRQHandler
712 def_irq_handler GPC_IRQHandler
713 def_irq_handler MU_A53_IRQHandler
714 def_irq_handler SRC_IRQHandler
715 def_irq_handler I2S56_DriverIRQHandler
716 def_irq_handler RTIC_IRQHandler
717 def_irq_handler CPU_PerformanceUnit_IRQHandler
718 def_irq_handler CPU_CTI_Trigger_IRQHandler
719 def_irq_handler SRC_Combined_IRQHandler
720 def_irq_handler I2S1_DriverIRQHandler
721 def_irq_handler I2S2_DriverIRQHandler
722 def_irq_handler MU_M4_IRQHandler
723 def_irq_handler DDR_PerformanceMonitor_IRQHandler
724 def_irq_handler DDR_IRQHandler
725 def_irq_handler I2S4_DriverIRQHandler
726 def_irq_handler CPU_Error_AXI_IRQHandler
727 def_irq_handler CPU_Error_L2RAM_IRQHandler
728 def_irq_handler SDMA2_DriverIRQHandler
729 def_irq_handler Reserved120_IRQHandler
730 def_irq_handler CAAM_IRQ0_IRQHandler
731 def_irq_handler CAAM_IRQ1_IRQHandler
732 def_irq_handler QSPI_DriverIRQHandler
733 def_irq_handler TZASC_IRQHandler
734 def_irq_handler Reserved125_IRQHandler
735 def_irq_handler Reserved126_IRQHandler
736 def_irq_handler Reserved127_IRQHandler
737 def_irq_handler PERFMON1_IRQHandler
738 def_irq_handler PERFMON2_IRQHandler
739 def_irq_handler CAAM_IRQ2_IRQHandler
740 def_irq_handler CAAM_ERROR_IRQHandler
741 def_irq_handler HS_CP0_IRQHandler
742 def_irq_handler HEVC_IRQHandler
743 def_irq_handler ENET_MAC0_Rx_Tx_Done1_DriverIRQHandler
744 def_irq_handler ENET_MAC0_Rx_Tx_Done2_DriverIRQHandler
745 def_irq_handler ENET_DriverIRQHandler
746 def_irq_handler ENET_1588_DriverIRQHandler
747 def_irq_handler PCIE_CTRL1_IRQ0_IRQHandler
748 def_irq_handler PCIE_CTRL1_IRQ1_IRQHandler
749 def_irq_handler PCIE_CTRL1_IRQ2_IRQHandler
750 def_irq_handler PCIE_CTRL1_IRQ3_IRQHandler
751 def_irq_handler Reserved142_IRQHandler
752 def_irq_handler PCIE_CTRL1_IRQHandler
753
754 .end
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/mcuxpresso/startup_MIMX8MD7_cm4.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/mcuxpresso/startup_MIMX8MD7_cm4.c
new file mode 100644
index 000000000..e2c9e1c3e
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/mcuxpresso/startup_MIMX8MD7_cm4.c
@@ -0,0 +1,822 @@
1//*****************************************************************************
2// MIMX8MSCALE_M4 startup code for use with MCUXpresso IDE
3//
4// Version : 160922
5//*****************************************************************************
6//
7// Copyright 2016, NXP
8// All rights reserved.
9//
10// Software that is described herein is for illustrative purposes only
11// which provides customers with programming information regarding the
12// LPC products. This software is supplied "AS IS" without any warranties of
13// any kind, and NXP Semiconductors and its licensor disclaim any and
14// all warranties, express or implied, including all implied warranties of
15// merchantability, fitness for a particular purpose and non-infringement of
16// intellectual property rights. NXP Semiconductors assumes no responsibility
17// or liability for the use of the software, conveys no license or rights under any
18// patent, copyright, mask work right, or any other intellectual property rights in
19// or to any products. NXP Semiconductors reserves the right to make changes
20// in the software without notification. NXP Semiconductors also makes no
21// representation or warranty that such application will be suitable for the
22// specified use without further testing or modification.
23//
24// Permission to use, copy, modify, and distribute this software and its
25// documentation is hereby granted, under NXP Semiconductors' and its
26// licensor's relevant copyrights in the software, without fee, provided that it
27// is used in conjunction with NXP Semiconductors microcontrollers. This
28// copyright, permission, and disclaimer notice must appear in all copies of
29// this code.
30//*****************************************************************************
31
32#if defined (DEBUG)
33#pragma GCC push_options
34#pragma GCC optimize ("Og")
35#endif // (DEBUG)
36
37#if defined (__cplusplus)
38#ifdef __REDLIB__
39#error Redlib does not support C++
40#else
41//*****************************************************************************
42//
43// The entry point for the C++ library startup
44//
45//*****************************************************************************
46extern "C" {
47 extern void __libc_init_array(void);
48}
49#endif
50#endif
51
52#define WEAK __attribute__ ((weak))
53#define WEAK_AV __attribute__ ((weak, section(".after_vectors")))
54#define ALIAS(f) __attribute__ ((weak, alias (#f)))
55
56//*****************************************************************************
57#if defined (__cplusplus)
58extern "C" {
59#endif
60
61//*****************************************************************************
62// Declaration of external SystemInit function
63//*****************************************************************************
64#if defined (__USE_CMSIS)
65extern void SystemInit(void);
66#endif // (__USE_CMSIS)
67
68//*****************************************************************************
69// Forward declaration of the core exception handlers.
70// When the application defines a handler (with the same name), this will
71// automatically take precedence over these weak definitions
72//*****************************************************************************
73 void ResetISR(void);
74WEAK void NMI_Handler(void);
75WEAK void HardFault_Handler(void);
76WEAK void MemManage_Handler(void);
77WEAK void BusFault_Handler(void);
78WEAK void UsageFault_Handler(void);
79WEAK void SVC_Handler(void);
80WEAK void DebugMon_Handler(void);
81WEAK void PendSV_Handler(void);
82WEAK void SysTick_Handler(void);
83WEAK void IntDefaultHandler(void);
84//*****************************************************************************
85// Forward declaration of the application IRQ handlers. When the application
86// defines a handler (with the same name), this will automatically take
87// precedence over weak definitions below
88//*****************************************************************************
89WEAK void CTI0_IRQHandler(void);
90WEAK void DMA0_0_4_IRQHandler(void);
91WEAK void DMA0_1_5_IRQHandler(void);
92WEAK void DMA0_2_6_IRQHandler(void);
93WEAK void DMA0_3_7_IRQHandler(void);
94WEAK void DMA0_8_12_IRQHandler(void);
95WEAK void DMA0_9_13_IRQHandler(void);
96WEAK void DMA0_10_14_IRQHandler(void);
97WEAK void DMA0_11_15_IRQHandler(void);
98WEAK void DMA0_16_20_IRQHandler(void);
99WEAK void DMA0_17_21_IRQHandler(void);
100WEAK void DMA0_18_22_IRQHandler(void);
101WEAK void DMA0_19_23_IRQHandler(void);
102WEAK void DMA0_24_28_IRQHandler(void);
103WEAK void DMA0_25_29_IRQHandler(void);
104WEAK void DMA0_26_30_IRQHandler(void);
105WEAK void DMA0_27_31_IRQHandler(void);
106WEAK void DMA0_Error_IRQHandler(void);
107WEAK void MCM0_IRQHandler(void);
108WEAK void EWM_IRQHandler(void);
109WEAK void LLWU0_IRQHandler(void);
110WEAK void SIM_IRQHandler(void);
111WEAK void MU_A_IRQHandler(void);
112WEAK void Reserved39_IRQHandler(void);
113WEAK void Software1_IRQHandler(void);
114WEAK void Software2_IRQHandler(void);
115WEAK void WDOG0_IRQHandler(void);
116WEAK void SCG0_IRQHandler(void);
117WEAK void QSPI_IRQHandler(void);
118WEAK void LTC_IRQHandler(void);
119WEAK void Reserved46_IRQHandler(void);
120WEAK void SNVS_IRQHandler(void);
121WEAK void TRNG0_IRQHandler(void);
122WEAK void LPIT0_IRQHandler(void);
123WEAK void PMC0_IRQHandler(void);
124WEAK void CMC0_IRQHandler(void);
125WEAK void LPTMR0_IRQHandler(void);
126WEAK void LPTMR1_IRQHandler(void);
127WEAK void TPM0_IRQHandler(void);
128WEAK void TPM1_IRQHandler(void);
129WEAK void TPM2_IRQHandler(void);
130WEAK void TPM3_IRQHandler(void);
131WEAK void FLEXIO0_IRQHandler(void);
132WEAK void LPI2C0_IRQHandler(void);
133WEAK void LPI2C1_IRQHandler(void);
134WEAK void LPI2C2_IRQHandler(void);
135WEAK void LPI2C3_IRQHandler(void);
136WEAK void SAI0_IRQHandler(void);
137WEAK void SAI1_IRQHandler(void);
138WEAK void LPSPI0_IRQHandler(void);
139WEAK void LPSPI1_IRQHandler(void);
140WEAK void LPUART0_IRQHandler(void);
141WEAK void LPUART1_IRQHandler(void);
142WEAK void LPUART2_IRQHandler(void);
143WEAK void LPUART3_IRQHandler(void);
144WEAK void DPM_IRQHandler(void);
145WEAK void PCTLA_IRQHandler(void);
146WEAK void PCTLB_IRQHandler(void);
147WEAK void ADC0_IRQHandler(void);
148WEAK void ADC1_IRQHandler(void);
149WEAK void CMP0_IRQHandler(void);
150WEAK void CMP1_IRQHandler(void);
151WEAK void DAC0_IRQHandler(void);
152WEAK void DAC1_IRQHandler(void);
153WEAK void WDOG1_IRQHandler(void);
154WEAK void USB0_IRQHandler(void);
155WEAK void USB1_IRQHandler(void);
156WEAK void Reserved83_IRQHandler(void);
157WEAK void WDOG2_IRQHandler(void);
158WEAK void USBPHY_IRQHandler(void);
159WEAK void CMC1_IRQHandler(void);
160
161//*****************************************************************************
162// Forward declaration of the driver IRQ handlers. These are aliased
163// to the IntDefaultHandler, which is a 'forever' loop. When the driver
164// defines a handler (with the same name), this will automatically take
165// precedence over these weak definitions
166//*****************************************************************************
167void CTI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
168void DMA0_0_4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
169void DMA0_1_5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
170void DMA0_2_6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
171void DMA0_3_7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
172void DMA0_8_12_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
173void DMA0_9_13_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
174void DMA0_10_14_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
175void DMA0_11_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
176void DMA0_16_20_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
177void DMA0_17_21_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
178void DMA0_18_22_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
179void DMA0_19_23_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
180void DMA0_24_28_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
181void DMA0_25_29_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
182void DMA0_26_30_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
183void DMA0_27_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
184void DMA0_Error_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
185void MCM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
186void EWM_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
187void LLWU0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
188void SIM_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
189void MU_A_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
190void Reserved39_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
191void Software1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
192void Software2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
193void WDOG0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
194void SCG0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
195void QSPI_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
196void LTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
197void Reserved46_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
198void SNVS_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
199void TRNG0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
200void LPIT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
201void PMC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
202void CMC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
203void LPTMR0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
204void LPTMR1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
205void TPM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
206void TPM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
207void TPM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
208void TPM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
209void FLEXIO0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
210void LPI2C0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
211void LPI2C1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
212void LPI2C2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
213void LPI2C3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
214void SAI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
215void SAI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
216void LPSPI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
217void LPSPI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
218void LPUART0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
219void LPUART1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
220void LPUART2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
221void LPUART3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
222void DPM_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
223void PCTLA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
224void PCTLB_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
225void ADC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
226void ADC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
227void CMP0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
228void CMP1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
229void DAC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
230void DAC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
231void WDOG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
232void USB0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
233void USB1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
234void Reserved83_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
235void WDOG2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
236void USBPHY_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
237void CMC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
238
239//*****************************************************************************
240// The entry point for the application.
241// __main() is the entry point for Redlib based applications
242// main() is the entry point for Newlib based applications
243//*****************************************************************************
244#if defined (__REDLIB__)
245extern void __main(void);
246#endif
247extern int main(void);
248
249//*****************************************************************************
250// External declaration for the pointer to the stack top from the Linker Script
251//*****************************************************************************
252extern void _vStackTop(void);
253
254//*****************************************************************************
255#if defined (__cplusplus)
256} // extern "C"
257#endif
258
259//*****************************************************************************
260// The vector table.
261// This relies on the linker script to place at correct location in memory.
262//*****************************************************************************
263extern void (* const g_pfnVectors[])(void);
264__attribute__ ((section(".isr_vector")))
265void (* const g_pfnVectors[])(void) = {
266 &_vStackTop, // The initial stack pointer
267 ResetISR, // The reset handler
268 NMI_Handler, //NMI Handler
269 HardFault_Handler, //Hard Fault Handler
270 MemManage_Handler, //MPU Fault Handler
271 BusFault_Handler, //Bus Fault Handler
272 UsageFault_Handler, //Usage Fault Handler
273 0, //Reserved
274 0, //Reserved
275 0, //Reserved
276 0, //Reserved
277 SVC_Handler, //SVCall Handler
278 DebugMon_Handler, //Debug Monitor Handler
279 0, //Reserved
280 PendSV_Handler, //PendSV Handler
281 SysTick_Handler, //SysTick Handler
282 //External Interrupts
283 CTI0_IRQHandler, //Cross Trigger Interface for CM4
284 DMA0_0_4_IRQHandler, //DMA Channel 0, 4 Transfer Complete
285 DMA0_1_5_IRQHandler, //DMA Channel 1, 5 Transfer Complete
286 DMA0_2_6_IRQHandler, //DMA Channel 2, 6 Transfer Complete
287 DMA0_3_7_IRQHandler, //DMA Channel 3, 7 Transfer Complete
288 DMA0_8_12_IRQHandler, //DMA Channel 8, 12 Transfer Complete
289 DMA0_9_13_IRQHandler, //DMA Channel 9, 13 Transfer Complete
290 DMA0_10_14_IRQHandler, //DMA Channel 10, 14 Transfer Complete
291 DMA0_11_15_IRQHandler, //DMA Channel 11, 15 Transfer Complete
292 DMA0_16_20_IRQHandler, //DMA Channel 16, 20 Transfer Complete
293 DMA0_17_21_IRQHandler, //DMA Channel 17, 21 Transfer Complete
294 DMA0_18_22_IRQHandler, //DMA Channel 18, 22 Transfer Complete
295 DMA0_19_23_IRQHandler, //DMA Channel 19, 23 Transfer Complete
296 DMA0_24_28_IRQHandler, //DMA Channel 24, 28 Transfer Complete
297 DMA0_25_29_IRQHandler, //DMA Channel 25, 29 Transfer Complete
298 DMA0_26_30_IRQHandler, //DMA Channel 26, 30 Transfer Complete
299 DMA0_27_31_IRQHandler, //DMA Channel 27, 31 Transfer Complete
300 DMA0_Error_IRQHandler, //DMA Error Interrupt - All Channels
301 MCM0_IRQHandler, //MCM Interrupt
302 EWM_IRQHandler, //External Watchdog Monitor Interrupt
303 LLWU0_IRQHandler, //Low Leakage Wake Up
304 SIM_IRQHandler, //System Integation Module
305 MU_A_IRQHandler, //Messaging Unit - Side A
306 Reserved39_IRQHandler, //Secured JTAG Controller
307 Software1_IRQHandler, //Software Interrupt
308 Software2_IRQHandler, //Software Interrupt
309 WDOG0_IRQHandler, //Watchdog Interrupt
310 SCG0_IRQHandler, //System Clock Generator for M4 domain
311 QSPI_IRQHandler, //Quad Serial Peripheral Interface
312 LTC_IRQHandler, //Low Power Trusted Cryptography
313 Reserved46_IRQHandler, //Reserved
314 SNVS_IRQHandler, //Secure Non-Volatile Storage Consolidated Interrupt
315 TRNG0_IRQHandler, //Random Number Generator
316 LPIT0_IRQHandler, //Low Power Periodic Interrupt Timer
317 PMC0_IRQHandler, //Power Management Control interrupts for M4 domain
318 CMC0_IRQHandler, //Core Mode Controller interrupts for M4 domain
319 LPTMR0_IRQHandler, //Low Power Timer
320 LPTMR1_IRQHandler, //Low Power Timer
321 TPM0_IRQHandler, //Timer PWM module
322 TPM1_IRQHandler, //Timer PWM module
323 TPM2_IRQHandler, //Timer PWM module
324 TPM3_IRQHandler, //Timer PWM module
325 FLEXIO0_IRQHandler, //Flexible IO
326 LPI2C0_IRQHandler, //Inter-integrated circuit 0
327 LPI2C1_IRQHandler, //Inter-integrated circuit 1
328 LPI2C2_IRQHandler, //Inter-integrated circuit 2
329 LPI2C3_IRQHandler, //Inter-integrated circuit 3
330 SAI0_IRQHandler, //Serial Audio Interface
331 SAI1_IRQHandler, //Serial Audio Interface 1
332 LPSPI0_IRQHandler, //Low Power Serial Peripheral Interface
333 LPSPI1_IRQHandler, //Low Power Serial Peripheral Interface
334 LPUART0_IRQHandler, //Low Power UART
335 LPUART1_IRQHandler, //Low Power UART
336 LPUART2_IRQHandler, //Low Power UART
337 LPUART3_IRQHandler, //Low Power UART
338 DPM_IRQHandler, //Dynamic Process Monitor
339 PCTLA_IRQHandler, //Port A pin interrupt
340 PCTLB_IRQHandler, //Port B pin interrupt
341 ADC0_IRQHandler, //Analog to Digital Convertor
342 ADC1_IRQHandler, //Analog to Digital Convertor
343 CMP0_IRQHandler, //Comparator
344 CMP1_IRQHandler, //Comparator
345 DAC0_IRQHandler, //Digital to Analog Convertor
346 DAC1_IRQHandler, //Digital to Analog Convertor
347 WDOG1_IRQHandler, //Watchdog Interrupt from A7 subsystem
348 USB0_IRQHandler, //USB 0 Interrupt from A7 subsystem
349 USB1_IRQHandler, //USB 1 Interrupt from A7 subsystem
350 Reserved83_IRQHandler, //
351 WDOG2_IRQHandler, //Watchdog Interrupt from A7 subsystem
352 USBPHY_IRQHandler, //USB PHY (used in conjunction with USBOTG0)
353 CMC1_IRQHandler, //A7 resets
354}; /* End of g_pfnVectors */
355
356//*****************************************************************************
357// Functions to carry out the initialization of RW and BSS data sections. These
358// are written as separate functions rather than being inlined within the
359// ResetISR() function in order to cope with MCUs with multiple banks of
360// memory.
361//*****************************************************************************
362__attribute__ ((section(".after_vectors.init_data")))
363void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
364 unsigned int *pulDest = (unsigned int*) start;
365 unsigned int *pulSrc = (unsigned int*) romstart;
366 unsigned int loop;
367 for (loop = 0; loop < len; loop = loop + 4)
368 *pulDest++ = *pulSrc++;
369}
370
371__attribute__ ((section(".after_vectors.init_bss")))
372void bss_init(unsigned int start, unsigned int len) {
373 unsigned int *pulDest = (unsigned int*) start;
374 unsigned int loop;
375 for (loop = 0; loop < len; loop = loop + 4)
376 *pulDest++ = 0;
377}
378
379//*****************************************************************************
380// The following symbols are constructs generated by the linker, indicating
381// the location of various points in the "Global Section Table". This table is
382// created by the linker via the Code Red managed linker script mechanism. It
383// contains the load address, execution address and length of each RW data
384// section and the execution and length of each BSS (zero initialized) section.
385//*****************************************************************************
386extern unsigned int __data_section_table;
387extern unsigned int __data_section_table_end;
388extern unsigned int __bss_section_table;
389extern unsigned int __bss_section_table_end;
390
391//*****************************************************************************
392// Reset entry point for your code.
393// Sets up a simple runtime environment and initializes the C/C++
394// library.
395//*****************************************************************************
396__attribute__ ((section(".after_vectors.reset")))
397void
398ResetISR(void) {
399 // Disable interrupts
400 __asm volatile ("cpsid i");
401
402#if defined (__USE_CMSIS)
403// If __USE_CMSIS defined, then call CMSIS SystemInit code
404 SystemInit();
405#endif // (__USE_CMSIS)
406
407 //
408 // Copy the data sections from flash to SRAM.
409 //
410 unsigned int LoadAddr, ExeAddr, SectionLen;
411 unsigned int *SectionTableAddr;
412
413 // Load base address of Global Section Table
414 SectionTableAddr = &__data_section_table;
415
416 // Copy the data sections from flash to SRAM.
417 while (SectionTableAddr < &__data_section_table_end) {
418 LoadAddr = *SectionTableAddr++;
419 ExeAddr = *SectionTableAddr++;
420 SectionLen = *SectionTableAddr++;
421 data_init(LoadAddr, ExeAddr, SectionLen);
422 }
423
424 // At this point, SectionTableAddr = &__bss_section_table;
425 // Zero fill the bss segment
426 while (SectionTableAddr < &__bss_section_table_end) {
427 ExeAddr = *SectionTableAddr++;
428 SectionLen = *SectionTableAddr++;
429 bss_init(ExeAddr, SectionLen);
430 }
431
432#if !defined (__USE_CMSIS)
433// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
434// will enable the FPU
435#if defined (__VFP_FP__) && !defined (__SOFTFP__)
436 //
437 // Code to enable the Cortex-M4 FPU only included
438 // if appropriate build options have been selected.
439 // Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
440 //
441 // Read CPACR (located at address 0xE000ED88)
442 // Set bits 20-23 to enable CP10 and CP11 coprocessors
443 // Write back the modified value to the CPACR
444 asm volatile ("LDR.W R0, =0xE000ED88\n\t"
445 "LDR R1, [R0]\n\t"
446 "ORR R1, R1, #(0xF << 20)\n\t"
447 "STR R1, [R0]");
448#endif // (__VFP_FP__) && !(__SOFTFP__)
449#endif // (__USE_CMSIS)
450
451#if !defined (__USE_CMSIS)
452// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
453// will setup the VTOR register
454
455 // Check to see if we are running the code from a non-zero
456 // address (eg RAM, external flash), in which case we need
457 // to modify the VTOR register to tell the CPU that the
458 // vector table is located at a non-0x0 address.
459 unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
460 if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
461 *pSCB_VTOR = (unsigned int)g_pfnVectors;
462 }
463#endif // (__USE_CMSIS)
464
465#if defined (__cplusplus)
466 //
467 // Call C++ library initialisation
468 //
469 __libc_init_array();
470#endif
471
472
473 // Reenable interrupts
474 __asm volatile ("cpsie i");
475
476#if defined (__REDLIB__)
477 // Call the Redlib library, which in turn calls main()
478 __main() ;
479#else
480 main();
481#endif
482
483 //
484 // main() shouldn't return, but if it does, we'll just enter an infinite loop
485 //
486 while (1) {
487 ;
488 }
489}
490
491//*****************************************************************************
492// Default core exception handlers. Override the ones here by defining your own
493// handler routines in your application code.
494//*****************************************************************************
495WEAK void NMI_Handler(void) //NMI Handler
496{ while(1) {}
497}
498
499WEAK void HardFault_Handler(void) //Hard Fault Handler
500{ while(1) {}
501}
502
503WEAK void MemManage_Handler(void) //MPU Fault Handler
504{ while(1) {}
505}
506
507WEAK void BusFault_Handler(void) //Bus Fault Handler
508{ while(1) {}
509}
510
511WEAK void UsageFault_Handler(void) //Usage Fault Handler
512{ while(1) {}
513}
514
515WEAK void SVC_Handler(void) //SVCall Handler
516{ while(1) {}
517}
518
519WEAK void DebugMon_Handler(void) //Debug Monitor Handler
520{ while(1) {}
521}
522
523WEAK void PendSV_Handler(void) //PendSV Handler
524{ while(1) {}
525}
526
527WEAK void SysTick_Handler(void) //SysTick Handler
528{ while(1) {}
529}
530
531//*****************************************************************************
532// Processor ends up here if an unexpected interrupt occurs or a specific
533// handler is not present in the application code.
534//*****************************************************************************
535WEAK_AV void IntDefaultHandler(void)
536{ while(1) {}
537}
538
539//*****************************************************************************
540// Default application exception handlers. Override the ones here by defining
541// your own handler routines in your application code. These routines call
542// driver exception handlers or IntDefaultHandler() if no driver exception
543// handler is included.
544//*****************************************************************************
545WEAK void CTI0_IRQHandler(void) //Cross Trigger Interface for CM4
546{ CTI0_DriverIRQHandler();
547}
548
549WEAK void DMA0_0_4_IRQHandler(void) //DMA Channel 0, 4 Transfer Complete
550{ DMA0_0_4_DriverIRQHandler();
551}
552
553WEAK void DMA0_1_5_IRQHandler(void) //DMA Channel 1, 5 Transfer Complete
554{ DMA0_1_5_DriverIRQHandler();
555}
556
557WEAK void DMA0_2_6_IRQHandler(void) //DMA Channel 2, 6 Transfer Complete
558{ DMA0_2_6_DriverIRQHandler();
559}
560
561WEAK void DMA0_3_7_IRQHandler(void) //DMA Channel 3, 7 Transfer Complete
562{ DMA0_3_7_DriverIRQHandler();
563}
564
565WEAK void DMA0_8_12_IRQHandler(void) //DMA Channel 8, 12 Transfer Complete
566{ DMA0_8_12_DriverIRQHandler();
567}
568
569WEAK void DMA0_9_13_IRQHandler(void) //DMA Channel 9, 13 Transfer Complete
570{ DMA0_9_13_DriverIRQHandler();
571}
572
573WEAK void DMA0_10_14_IRQHandler(void) //DMA Channel 10, 14 Transfer Complete
574{ DMA0_10_14_DriverIRQHandler();
575}
576
577WEAK void DMA0_11_15_IRQHandler(void) //DMA Channel 11, 15 Transfer Complete
578{ DMA0_11_15_DriverIRQHandler();
579}
580
581WEAK void DMA0_16_20_IRQHandler(void) //DMA Channel 16, 20 Transfer Complete
582{ DMA0_16_20_DriverIRQHandler();
583}
584
585WEAK void DMA0_17_21_IRQHandler(void) //DMA Channel 17, 21 Transfer Complete
586{ DMA0_17_21_DriverIRQHandler();
587}
588
589WEAK void DMA0_18_22_IRQHandler(void) //DMA Channel 18, 22 Transfer Complete
590{ DMA0_18_22_DriverIRQHandler();
591}
592
593WEAK void DMA0_19_23_IRQHandler(void) //DMA Channel 19, 23 Transfer Complete
594{ DMA0_19_23_DriverIRQHandler();
595}
596
597WEAK void DMA0_24_28_IRQHandler(void) //DMA Channel 24, 28 Transfer Complete
598{ DMA0_24_28_DriverIRQHandler();
599}
600
601WEAK void DMA0_25_29_IRQHandler(void) //DMA Channel 25, 29 Transfer Complete
602{ DMA0_25_29_DriverIRQHandler();
603}
604
605WEAK void DMA0_26_30_IRQHandler(void) //DMA Channel 26, 30 Transfer Complete
606{ DMA0_26_30_DriverIRQHandler();
607}
608
609WEAK void DMA0_27_31_IRQHandler(void) //DMA Channel 27, 31 Transfer Complete
610{ DMA0_27_31_DriverIRQHandler();
611}
612
613WEAK void DMA0_Error_IRQHandler(void) //DMA Error Interrupt - All Channels
614{ DMA0_Error_DriverIRQHandler();
615}
616
617WEAK void MCM0_IRQHandler(void) //MCM Interrupt
618{ MCM0_DriverIRQHandler();
619}
620
621WEAK void EWM_IRQHandler(void) //External Watchdog Monitor Interrupt
622{ EWM_DriverIRQHandler();
623}
624
625WEAK void LLWU0_IRQHandler(void) //Low Leakage Wake Up
626{ LLWU0_DriverIRQHandler();
627}
628
629WEAK void SIM_IRQHandler(void) //System Integation Module
630{ SIM_DriverIRQHandler();
631}
632
633WEAK void MU_A_IRQHandler(void) //Messaging Unit - Side A
634{ MU_A_DriverIRQHandler();
635}
636
637WEAK void Software1_IRQHandler(void) //Software Interrupt
638{ Software1_DriverIRQHandler();
639}
640
641WEAK void Software2_IRQHandler(void) //Software Interrupt
642{ Software2_DriverIRQHandler();
643}
644
645WEAK void WDOG0_IRQHandler(void) //Watchdog Interrupt
646{ WDOG0_DriverIRQHandler();
647}
648
649WEAK void SCG0_IRQHandler(void) //System Clock Generator for M4 domain
650{ SCG0_DriverIRQHandler();
651}
652
653WEAK void QSPI_IRQHandler(void) //Quad Serial Peripheral Interface
654{ QSPI_DriverIRQHandler();
655}
656
657WEAK void LTC_IRQHandler(void) //Low Power Trusted Cryptography
658{ LTC_DriverIRQHandler();
659}
660
661WEAK void SNVS_IRQHandler(void) //Secure Non-Volatile Storage Consolidated Interrupt
662{ SNVS_DriverIRQHandler();
663}
664
665WEAK void TRNG0_IRQHandler(void) //Random Number Generator
666{ TRNG0_DriverIRQHandler();
667}
668
669WEAK void LPIT0_IRQHandler(void) //Low Power Periodic Interrupt Timer
670{ LPIT0_DriverIRQHandler();
671}
672
673WEAK void PMC0_IRQHandler(void) //Power Management Control interrupts for M4 domain
674{ PMC0_DriverIRQHandler();
675}
676
677WEAK void CMC0_IRQHandler(void) //Core Mode Controller interrupts for M4 domain
678{ CMC0_DriverIRQHandler();
679}
680
681WEAK void LPTMR0_IRQHandler(void) //Low Power Timer
682{ LPTMR0_DriverIRQHandler();
683}
684
685WEAK void LPTMR1_IRQHandler(void) //Low Power Timer
686{ LPTMR1_DriverIRQHandler();
687}
688
689WEAK void TPM0_IRQHandler(void) //Timer PWM module
690{ TPM0_DriverIRQHandler();
691}
692
693WEAK void TPM1_IRQHandler(void) //Timer PWM module
694{ TPM1_DriverIRQHandler();
695}
696
697WEAK void TPM2_IRQHandler(void) //Timer PWM module
698{ TPM2_DriverIRQHandler();
699}
700
701WEAK void TPM3_IRQHandler(void) //Timer PWM module
702{ TPM3_DriverIRQHandler();
703}
704
705WEAK void FLEXIO0_IRQHandler(void) //Flexible IO
706{ FLEXIO0_DriverIRQHandler();
707}
708
709WEAK void LPI2C0_IRQHandler(void) //Inter-integrated circuit 0
710{ LPI2C0_DriverIRQHandler();
711}
712
713WEAK void LPI2C1_IRQHandler(void) //Inter-integrated circuit 1
714{ LPI2C1_DriverIRQHandler();
715}
716
717WEAK void LPI2C2_IRQHandler(void) //Inter-integrated circuit 2
718{ LPI2C2_DriverIRQHandler();
719}
720
721WEAK void LPI2C3_IRQHandler(void) //Inter-integrated circuit 3
722{ LPI2C3_DriverIRQHandler();
723}
724
725WEAK void SAI0_IRQHandler(void) //Serial Audio Interface
726{ SAI0_DriverIRQHandler();
727}
728
729WEAK void SAI1_IRQHandler(void) //Serial Audio Interface 1
730{ SAI1_DriverIRQHandler();
731}
732
733WEAK void LPSPI0_IRQHandler(void) //Low Power Serial Peripheral Interface
734{ LPSPI0_DriverIRQHandler();
735}
736
737WEAK void LPSPI1_IRQHandler(void) //Low Power Serial Peripheral Interface
738{ LPSPI1_DriverIRQHandler();
739}
740
741WEAK void LPUART0_IRQHandler(void) //Low Power UART
742{ LPUART0_DriverIRQHandler();
743}
744
745WEAK void LPUART1_IRQHandler(void) //Low Power UART
746{ LPUART1_DriverIRQHandler();
747}
748
749WEAK void LPUART2_IRQHandler(void) //Low Power UART
750{ LPUART2_DriverIRQHandler();
751}
752
753WEAK void LPUART3_IRQHandler(void) //Low Power UART
754{ LPUART3_DriverIRQHandler();
755}
756
757WEAK void DPM_IRQHandler(void) //Dynamic Process Monitor
758{ DPM_DriverIRQHandler();
759}
760
761WEAK void PCTLA_IRQHandler(void) //Port A pin interrupt
762{ PCTLA_DriverIRQHandler();
763}
764
765WEAK void PCTLB_IRQHandler(void) //Port B pin interrupt
766{ PCTLB_DriverIRQHandler();
767}
768
769WEAK void ADC0_IRQHandler(void) //Analog to Digital Convertor
770{ ADC0_DriverIRQHandler();
771}
772
773WEAK void ADC1_IRQHandler(void) //Analog to Digital Convertor
774{ ADC1_DriverIRQHandler();
775}
776
777WEAK void CMP0_IRQHandler(void) //Comparator
778{ CMP0_DriverIRQHandler();
779}
780
781WEAK void CMP1_IRQHandler(void) //Comparator
782{ CMP1_DriverIRQHandler();
783}
784
785WEAK void DAC0_IRQHandler(void) //Digital to Analog Convertor
786{ DAC0_DriverIRQHandler();
787}
788
789WEAK void DAC1_IRQHandler(void) //Digital to Analog Convertor
790{ DAC1_DriverIRQHandler();
791}
792
793WEAK void WDOG1_IRQHandler(void) //Watchdog Interrupt from A7 subsystem
794{ WDOG1_DriverIRQHandler();
795}
796
797WEAK void USB0_IRQHandler(void) //USB 0 Interrupt from A7 subsystem
798{ USB0_DriverIRQHandler();
799}
800
801WEAK void USB1_IRQHandler(void) //USB 1 Interrupt from A7 subsystem
802{ USB1_DriverIRQHandler();
803}
804
805WEAK void WDOG2_IRQHandler(void) //Watchdog Interrupt from A7 subsystem
806{ WDOG2_DriverIRQHandler();
807}
808
809WEAK void USBPHY_IRQHandler(void) //USB PHY (used in conjunction with USBOTG0)
810{ USBPHY_DriverIRQHandler();
811}
812
813WEAK void CMC1_IRQHandler(void) //A7 resets
814{ CMC1_DriverIRQHandler();
815}
816
817//*****************************************************************************
818
819#if defined (DEBUG)
820#pragma GCC pop_options
821#endif // (DEBUG)
822 \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/mcuxpresso/startup_MIMX8MD7_cm4.cpp b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/mcuxpresso/startup_MIMX8MD7_cm4.cpp
new file mode 100644
index 000000000..67153b072
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/mcuxpresso/startup_MIMX8MD7_cm4.cpp
@@ -0,0 +1,821 @@
1//*****************************************************************************
2// MIMX8MSCALE_M4 startup code for use with MCUXpresso IDE
3//
4// Version : 160922
5//*****************************************************************************
6//
7// Copyright 2016, NXP
8// All rights reserved.
9//
10// Software that is described herein is for illustrative purposes only
11// which provides customers with programming information regarding the
12// LPC products. This software is supplied "AS IS" without any warranties of
13// any kind, and NXP Semiconductors and its licensor disclaim any and
14// all warranties, express or implied, including all implied warranties of
15// merchantability, fitness for a particular purpose and non-infringement of
16// intellectual property rights. NXP Semiconductors assumes no responsibility
17// or liability for the use of the software, conveys no license or rights under any
18// patent, copyright, mask work right, or any other intellectual property rights in
19// or to any products. NXP Semiconductors reserves the right to make changes
20// in the software without notification. NXP Semiconductors also makes no
21// representation or warranty that such application will be suitable for the
22// specified use without further testing or modification.
23//
24// Permission to use, copy, modify, and distribute this software and its
25// documentation is hereby granted, under NXP Semiconductors' and its
26// licensor's relevant copyrights in the software, without fee, provided that it
27// is used in conjunction with NXP Semiconductors microcontrollers. This
28// copyright, permission, and disclaimer notice must appear in all copies of
29// this code.
30//*****************************************************************************
31
32#if defined (DEBUG)
33#pragma GCC push_options
34#pragma GCC optimize ("Og")
35#endif // (DEBUG)
36
37#if defined (__cplusplus)
38#ifdef __REDLIB__
39#error Redlib does not support C++
40#else
41//*****************************************************************************
42//
43// The entry point for the C++ library startup
44//
45//*****************************************************************************
46extern "C" {
47 extern void __libc_init_array(void);
48}
49#endif
50#endif
51
52#define WEAK __attribute__ ((weak))
53#define WEAK_AV __attribute__ ((weak, section(".after_vectors")))
54#define ALIAS(f) __attribute__ ((weak, alias (#f)))
55
56//*****************************************************************************
57#if defined (__cplusplus)
58extern "C" {
59#endif
60
61//*****************************************************************************
62// Declaration of external SystemInit function
63//*****************************************************************************
64#if defined (__USE_CMSIS)
65extern void SystemInit(void);
66#endif // (__USE_CMSIS)
67
68//*****************************************************************************
69// Forward declaration of the core exception handlers.
70// When the application defines a handler (with the same name), this will
71// automatically take precedence over these weak definitions
72//*****************************************************************************
73 void ResetISR(void);
74WEAK void NMI_Handler(void);
75WEAK void HardFault_Handler(void);
76WEAK void MemManage_Handler(void);
77WEAK void BusFault_Handler(void);
78WEAK void UsageFault_Handler(void);
79WEAK void SVC_Handler(void);
80WEAK void DebugMon_Handler(void);
81WEAK void PendSV_Handler(void);
82WEAK void SysTick_Handler(void);
83WEAK void IntDefaultHandler(void);
84//*****************************************************************************
85// Forward declaration of the application IRQ handlers. When the application
86// defines a handler (with the same name), this will automatically take
87// precedence over weak definitions below
88//*****************************************************************************
89WEAK void CTI0_IRQHandler(void);
90WEAK void DMA0_0_4_IRQHandler(void);
91WEAK void DMA0_1_5_IRQHandler(void);
92WEAK void DMA0_2_6_IRQHandler(void);
93WEAK void DMA0_3_7_IRQHandler(void);
94WEAK void DMA0_8_12_IRQHandler(void);
95WEAK void DMA0_9_13_IRQHandler(void);
96WEAK void DMA0_10_14_IRQHandler(void);
97WEAK void DMA0_11_15_IRQHandler(void);
98WEAK void DMA0_16_20_IRQHandler(void);
99WEAK void DMA0_17_21_IRQHandler(void);
100WEAK void DMA0_18_22_IRQHandler(void);
101WEAK void DMA0_19_23_IRQHandler(void);
102WEAK void DMA0_24_28_IRQHandler(void);
103WEAK void DMA0_25_29_IRQHandler(void);
104WEAK void DMA0_26_30_IRQHandler(void);
105WEAK void DMA0_27_31_IRQHandler(void);
106WEAK void DMA0_Error_IRQHandler(void);
107WEAK void MCM0_IRQHandler(void);
108WEAK void EWM_IRQHandler(void);
109WEAK void LLWU0_IRQHandler(void);
110WEAK void SIM_IRQHandler(void);
111WEAK void MU_A_IRQHandler(void);
112WEAK void Reserved39_IRQHandler(void);
113WEAK void Software1_IRQHandler(void);
114WEAK void Software2_IRQHandler(void);
115WEAK void WDOG0_IRQHandler(void);
116WEAK void SCG0_IRQHandler(void);
117WEAK void QSPI_IRQHandler(void);
118WEAK void LTC_IRQHandler(void);
119WEAK void Reserved46_IRQHandler(void);
120WEAK void SNVS_IRQHandler(void);
121WEAK void TRNG0_IRQHandler(void);
122WEAK void LPIT0_IRQHandler(void);
123WEAK void PMC0_IRQHandler(void);
124WEAK void CMC0_IRQHandler(void);
125WEAK void LPTMR0_IRQHandler(void);
126WEAK void LPTMR1_IRQHandler(void);
127WEAK void TPM0_IRQHandler(void);
128WEAK void TPM1_IRQHandler(void);
129WEAK void TPM2_IRQHandler(void);
130WEAK void TPM3_IRQHandler(void);
131WEAK void FLEXIO0_IRQHandler(void);
132WEAK void LPI2C0_IRQHandler(void);
133WEAK void LPI2C1_IRQHandler(void);
134WEAK void LPI2C2_IRQHandler(void);
135WEAK void LPI2C3_IRQHandler(void);
136WEAK void SAI0_IRQHandler(void);
137WEAK void SAI1_IRQHandler(void);
138WEAK void LPSPI0_IRQHandler(void);
139WEAK void LPSPI1_IRQHandler(void);
140WEAK void LPUART0_IRQHandler(void);
141WEAK void LPUART1_IRQHandler(void);
142WEAK void LPUART2_IRQHandler(void);
143WEAK void LPUART3_IRQHandler(void);
144WEAK void DPM_IRQHandler(void);
145WEAK void PCTLA_IRQHandler(void);
146WEAK void PCTLB_IRQHandler(void);
147WEAK void ADC0_IRQHandler(void);
148WEAK void ADC1_IRQHandler(void);
149WEAK void CMP0_IRQHandler(void);
150WEAK void CMP1_IRQHandler(void);
151WEAK void DAC0_IRQHandler(void);
152WEAK void DAC1_IRQHandler(void);
153WEAK void WDOG1_IRQHandler(void);
154WEAK void USB0_IRQHandler(void);
155WEAK void USB1_IRQHandler(void);
156WEAK void Reserved83_IRQHandler(void);
157WEAK void WDOG2_IRQHandler(void);
158WEAK void USBPHY_IRQHandler(void);
159WEAK void CMC1_IRQHandler(void);
160
161//*****************************************************************************
162// Forward declaration of the driver IRQ handlers. These are aliased
163// to the IntDefaultHandler, which is a 'forever' loop. When the driver
164// defines a handler (with the same name), this will automatically take
165// precedence over these weak definitions
166//*****************************************************************************
167void CTI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
168void DMA0_0_4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
169void DMA0_1_5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
170void DMA0_2_6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
171void DMA0_3_7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
172void DMA0_8_12_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
173void DMA0_9_13_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
174void DMA0_10_14_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
175void DMA0_11_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
176void DMA0_16_20_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
177void DMA0_17_21_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
178void DMA0_18_22_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
179void DMA0_19_23_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
180void DMA0_24_28_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
181void DMA0_25_29_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
182void DMA0_26_30_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
183void DMA0_27_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
184void DMA0_Error_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
185void MCM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
186void EWM_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
187void LLWU0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
188void SIM_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
189void MU_A_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
190void Reserved39_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
191void Software1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
192void Software2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
193void WDOG0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
194void SCG0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
195void QSPI_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
196void LTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
197void Reserved46_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
198void SNVS_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
199void TRNG0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
200void LPIT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
201void PMC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
202void CMC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
203void LPTMR0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
204void LPTMR1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
205void TPM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
206void TPM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
207void TPM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
208void TPM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
209void FLEXIO0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
210void LPI2C0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
211void LPI2C1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
212void LPI2C2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
213void LPI2C3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
214void SAI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
215void SAI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
216void LPSPI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
217void LPSPI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
218void LPUART0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
219void LPUART1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
220void LPUART2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
221void LPUART3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
222void DPM_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
223void PCTLA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
224void PCTLB_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
225void ADC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
226void ADC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
227void CMP0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
228void CMP1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
229void DAC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
230void DAC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
231void WDOG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
232void USB0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
233void USB1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
234void Reserved83_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
235void WDOG2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
236void USBPHY_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
237void CMC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
238
239//*****************************************************************************
240// The entry point for the application.
241// __main() is the entry point for Redlib based applications
242// main() is the entry point for Newlib based applications
243//*****************************************************************************
244#if defined (__REDLIB__)
245extern void __main(void);
246#endif
247extern int main(void);
248
249//*****************************************************************************
250// External declaration for the pointer to the stack top from the Linker Script
251//*****************************************************************************
252extern void _vStackTop(void);
253
254//*****************************************************************************
255#if defined (__cplusplus)
256} // extern "C"
257#endif
258
259//*****************************************************************************
260// The vector table.
261// This relies on the linker script to place at correct location in memory.
262//*****************************************************************************
263extern void (* const g_pfnVectors[])(void);
264__attribute__ ((section(".isr_vector")))
265void (* const g_pfnVectors[])(void) = {
266 &_vStackTop, // The initial stack pointer
267 ResetISR, // The reset handler
268 NMI_Handler, //NMI Handler
269 HardFault_Handler, //Hard Fault Handler
270 MemManage_Handler, //MPU Fault Handler
271 BusFault_Handler, //Bus Fault Handler
272 UsageFault_Handler, //Usage Fault Handler
273 0, //Reserved
274 0, //Reserved
275 0, //Reserved
276 0, //Reserved
277 SVC_Handler, //SVCall Handler
278 DebugMon_Handler, //Debug Monitor Handler
279 0, //Reserved
280 PendSV_Handler, //PendSV Handler
281 SysTick_Handler, //SysTick Handler
282 //External Interrupts
283 CTI0_IRQHandler, //Cross Trigger Interface for CM4
284 DMA0_0_4_IRQHandler, //DMA Channel 0, 4 Transfer Complete
285 DMA0_1_5_IRQHandler, //DMA Channel 1, 5 Transfer Complete
286 DMA0_2_6_IRQHandler, //DMA Channel 2, 6 Transfer Complete
287 DMA0_3_7_IRQHandler, //DMA Channel 3, 7 Transfer Complete
288 DMA0_8_12_IRQHandler, //DMA Channel 8, 12 Transfer Complete
289 DMA0_9_13_IRQHandler, //DMA Channel 9, 13 Transfer Complete
290 DMA0_10_14_IRQHandler, //DMA Channel 10, 14 Transfer Complete
291 DMA0_11_15_IRQHandler, //DMA Channel 11, 15 Transfer Complete
292 DMA0_16_20_IRQHandler, //DMA Channel 16, 20 Transfer Complete
293 DMA0_17_21_IRQHandler, //DMA Channel 17, 21 Transfer Complete
294 DMA0_18_22_IRQHandler, //DMA Channel 18, 22 Transfer Complete
295 DMA0_19_23_IRQHandler, //DMA Channel 19, 23 Transfer Complete
296 DMA0_24_28_IRQHandler, //DMA Channel 24, 28 Transfer Complete
297 DMA0_25_29_IRQHandler, //DMA Channel 25, 29 Transfer Complete
298 DMA0_26_30_IRQHandler, //DMA Channel 26, 30 Transfer Complete
299 DMA0_27_31_IRQHandler, //DMA Channel 27, 31 Transfer Complete
300 DMA0_Error_IRQHandler, //DMA Error Interrupt - All Channels
301 MCM0_IRQHandler, //MCM Interrupt
302 EWM_IRQHandler, //External Watchdog Monitor Interrupt
303 LLWU0_IRQHandler, //Low Leakage Wake Up
304 SIM_IRQHandler, //System Integation Module
305 MU_A_IRQHandler, //Messaging Unit - Side A
306 Reserved39_IRQHandler, //Secured JTAG Controller
307 Software1_IRQHandler, //Software Interrupt
308 Software2_IRQHandler, //Software Interrupt
309 WDOG0_IRQHandler, //Watchdog Interrupt
310 SCG0_IRQHandler, //System Clock Generator for M4 domain
311 QSPI_IRQHandler, //Quad Serial Peripheral Interface
312 LTC_IRQHandler, //Low Power Trusted Cryptography
313 Reserved46_IRQHandler, //Reserved
314 SNVS_IRQHandler, //Secure Non-Volatile Storage Consolidated Interrupt
315 TRNG0_IRQHandler, //Random Number Generator
316 LPIT0_IRQHandler, //Low Power Periodic Interrupt Timer
317 PMC0_IRQHandler, //Power Management Control interrupts for M4 domain
318 CMC0_IRQHandler, //Core Mode Controller interrupts for M4 domain
319 LPTMR0_IRQHandler, //Low Power Timer
320 LPTMR1_IRQHandler, //Low Power Timer
321 TPM0_IRQHandler, //Timer PWM module
322 TPM1_IRQHandler, //Timer PWM module
323 TPM2_IRQHandler, //Timer PWM module
324 TPM3_IRQHandler, //Timer PWM module
325 FLEXIO0_IRQHandler, //Flexible IO
326 LPI2C0_IRQHandler, //Inter-integrated circuit 0
327 LPI2C1_IRQHandler, //Inter-integrated circuit 1
328 LPI2C2_IRQHandler, //Inter-integrated circuit 2
329 LPI2C3_IRQHandler, //Inter-integrated circuit 3
330 SAI0_IRQHandler, //Serial Audio Interface
331 SAI1_IRQHandler, //Serial Audio Interface 1
332 LPSPI0_IRQHandler, //Low Power Serial Peripheral Interface
333 LPSPI1_IRQHandler, //Low Power Serial Peripheral Interface
334 LPUART0_IRQHandler, //Low Power UART
335 LPUART1_IRQHandler, //Low Power UART
336 LPUART2_IRQHandler, //Low Power UART
337 LPUART3_IRQHandler, //Low Power UART
338 DPM_IRQHandler, //Dynamic Process Monitor
339 PCTLA_IRQHandler, //Port A pin interrupt
340 PCTLB_IRQHandler, //Port B pin interrupt
341 ADC0_IRQHandler, //Analog to Digital Convertor
342 ADC1_IRQHandler, //Analog to Digital Convertor
343 CMP0_IRQHandler, //Comparator
344 CMP1_IRQHandler, //Comparator
345 DAC0_IRQHandler, //Digital to Analog Convertor
346 DAC1_IRQHandler, //Digital to Analog Convertor
347 WDOG1_IRQHandler, //Watchdog Interrupt from A7 subsystem
348 USB0_IRQHandler, //USB 0 Interrupt from A7 subsystem
349 USB1_IRQHandler, //USB 1 Interrupt from A7 subsystem
350 Reserved83_IRQHandler, //
351 WDOG2_IRQHandler, //Watchdog Interrupt from A7 subsystem
352 USBPHY_IRQHandler, //USB PHY (used in conjunction with USBOTG0)
353 CMC1_IRQHandler, //A7 resets
354}; /* End of g_pfnVectors */
355
356//*****************************************************************************
357// Functions to carry out the initialization of RW and BSS data sections. These
358// are written as separate functions rather than being inlined within the
359// ResetISR() function in order to cope with MCUs with multiple banks of
360// memory.
361//*****************************************************************************
362__attribute__ ((section(".after_vectors.init_data")))
363void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
364 unsigned int *pulDest = (unsigned int*) start;
365 unsigned int *pulSrc = (unsigned int*) romstart;
366 unsigned int loop;
367 for (loop = 0; loop < len; loop = loop + 4)
368 *pulDest++ = *pulSrc++;
369}
370
371__attribute__ ((section(".after_vectors.init_bss")))
372void bss_init(unsigned int start, unsigned int len) {
373 unsigned int *pulDest = (unsigned int*) start;
374 unsigned int loop;
375 for (loop = 0; loop < len; loop = loop + 4)
376 *pulDest++ = 0;
377}
378
379//*****************************************************************************
380// The following symbols are constructs generated by the linker, indicating
381// the location of various points in the "Global Section Table". This table is
382// created by the linker via the Code Red managed linker script mechanism. It
383// contains the load address, execution address and length of each RW data
384// section and the execution and length of each BSS (zero initialized) section.
385//*****************************************************************************
386extern unsigned int __data_section_table;
387extern unsigned int __data_section_table_end;
388extern unsigned int __bss_section_table;
389extern unsigned int __bss_section_table_end;
390
391//*****************************************************************************
392// Reset entry point for your code.
393// Sets up a simple runtime environment and initializes the C/C++
394// library.
395//*****************************************************************************
396__attribute__ ((section(".after_vectors.reset")))
397void ResetISR(void) {
398 // Disable interrupts
399 __asm volatile ("cpsid i");
400
401#if defined (__USE_CMSIS)
402// If __USE_CMSIS defined, then call CMSIS SystemInit code
403 SystemInit();
404#endif // (__USE_CMSIS)
405
406 //
407 // Copy the data sections from flash to SRAM.
408 //
409 unsigned int LoadAddr, ExeAddr, SectionLen;
410 unsigned int *SectionTableAddr;
411
412 // Load base address of Global Section Table
413 SectionTableAddr = &__data_section_table;
414
415 // Copy the data sections from flash to SRAM.
416 while (SectionTableAddr < &__data_section_table_end) {
417 LoadAddr = *SectionTableAddr++;
418 ExeAddr = *SectionTableAddr++;
419 SectionLen = *SectionTableAddr++;
420 data_init(LoadAddr, ExeAddr, SectionLen);
421 }
422
423 // At this point, SectionTableAddr = &__bss_section_table;
424 // Zero fill the bss segment
425 while (SectionTableAddr < &__bss_section_table_end) {
426 ExeAddr = *SectionTableAddr++;
427 SectionLen = *SectionTableAddr++;
428 bss_init(ExeAddr, SectionLen);
429 }
430
431#if !defined (__USE_CMSIS)
432// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
433// will enable the FPU
434#if defined (__VFP_FP__) && !defined (__SOFTFP__)
435 //
436 // Code to enable the Cortex-M4 FPU only included
437 // if appropriate build options have been selected.
438 // Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
439 //
440 // Read CPACR (located at address 0xE000ED88)
441 // Set bits 20-23 to enable CP10 and CP11 coprocessors
442 // Write back the modified value to the CPACR
443 asm volatile ("LDR.W R0, =0xE000ED88\n\t"
444 "LDR R1, [R0]\n\t"
445 "ORR R1, R1, #(0xF << 20)\n\t"
446 "STR R1, [R0]");
447#endif // (__VFP_FP__) && !(__SOFTFP__)
448#endif // (__USE_CMSIS)
449
450#if !defined (__USE_CMSIS)
451// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
452// will setup the VTOR register
453
454 // Check to see if we are running the code from a non-zero
455 // address (eg RAM, external flash), in which case we need
456 // to modify the VTOR register to tell the CPU that the
457 // vector table is located at a non-0x0 address.
458 unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
459 if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
460 *pSCB_VTOR = (unsigned int)g_pfnVectors;
461 }
462#endif // (__USE_CMSIS)
463
464#if defined (__cplusplus)
465 //
466 // Call C++ library initialisation
467 //
468 __libc_init_array();
469#endif
470
471
472 // Reenable interrupts
473 __asm volatile ("cpsie i");
474
475#if defined (__REDLIB__)
476 // Call the Redlib library, which in turn calls main()
477 __main() ;
478#else
479 main();
480#endif
481
482 //
483 // main() shouldn't return, but if it does, we'll just enter an infinite loop
484 //
485 while (1) {
486 ;
487 }
488}
489
490//*****************************************************************************
491// Default core exception handlers. Override the ones here by defining your own
492// handler routines in your application code.
493//*****************************************************************************
494WEAK void NMI_Handler(void) //NMI Handler
495{ while(1) {}
496}
497
498WEAK void HardFault_Handler(void) //Hard Fault Handler
499{ while(1) {}
500}
501
502WEAK void MemManage_Handler(void) //MPU Fault Handler
503{ while(1) {}
504}
505
506WEAK void BusFault_Handler(void) //Bus Fault Handler
507{ while(1) {}
508}
509
510WEAK void UsageFault_Handler(void) //Usage Fault Handler
511{ while(1) {}
512}
513
514WEAK void SVC_Handler(void) //SVCall Handler
515{ while(1) {}
516}
517
518WEAK void DebugMon_Handler(void) //Debug Monitor Handler
519{ while(1) {}
520}
521
522WEAK void PendSV_Handler(void) //PendSV Handler
523{ while(1) {}
524}
525
526WEAK void SysTick_Handler(void) //SysTick Handler
527{ while(1) {}
528}
529
530//*****************************************************************************
531// Processor ends up here if an unexpected interrupt occurs or a specific
532// handler is not present in the application code.
533//*****************************************************************************
534WEAK_AV void IntDefaultHandler(void)
535{ while(1) {}
536}
537
538//*****************************************************************************
539// Default application exception handlers. Override the ones here by defining
540// your own handler routines in your application code. These routines call
541// driver exception handlers or IntDefaultHandler() if no driver exception
542// handler is included.
543//*****************************************************************************
544WEAK void CTI0_IRQHandler(void) //Cross Trigger Interface for CM4
545{ CTI0_DriverIRQHandler();
546}
547
548WEAK void DMA0_0_4_IRQHandler(void) //DMA Channel 0, 4 Transfer Complete
549{ DMA0_0_4_DriverIRQHandler();
550}
551
552WEAK void DMA0_1_5_IRQHandler(void) //DMA Channel 1, 5 Transfer Complete
553{ DMA0_1_5_DriverIRQHandler();
554}
555
556WEAK void DMA0_2_6_IRQHandler(void) //DMA Channel 2, 6 Transfer Complete
557{ DMA0_2_6_DriverIRQHandler();
558}
559
560WEAK void DMA0_3_7_IRQHandler(void) //DMA Channel 3, 7 Transfer Complete
561{ DMA0_3_7_DriverIRQHandler();
562}
563
564WEAK void DMA0_8_12_IRQHandler(void) //DMA Channel 8, 12 Transfer Complete
565{ DMA0_8_12_DriverIRQHandler();
566}
567
568WEAK void DMA0_9_13_IRQHandler(void) //DMA Channel 9, 13 Transfer Complete
569{ DMA0_9_13_DriverIRQHandler();
570}
571
572WEAK void DMA0_10_14_IRQHandler(void) //DMA Channel 10, 14 Transfer Complete
573{ DMA0_10_14_DriverIRQHandler();
574}
575
576WEAK void DMA0_11_15_IRQHandler(void) //DMA Channel 11, 15 Transfer Complete
577{ DMA0_11_15_DriverIRQHandler();
578}
579
580WEAK void DMA0_16_20_IRQHandler(void) //DMA Channel 16, 20 Transfer Complete
581{ DMA0_16_20_DriverIRQHandler();
582}
583
584WEAK void DMA0_17_21_IRQHandler(void) //DMA Channel 17, 21 Transfer Complete
585{ DMA0_17_21_DriverIRQHandler();
586}
587
588WEAK void DMA0_18_22_IRQHandler(void) //DMA Channel 18, 22 Transfer Complete
589{ DMA0_18_22_DriverIRQHandler();
590}
591
592WEAK void DMA0_19_23_IRQHandler(void) //DMA Channel 19, 23 Transfer Complete
593{ DMA0_19_23_DriverIRQHandler();
594}
595
596WEAK void DMA0_24_28_IRQHandler(void) //DMA Channel 24, 28 Transfer Complete
597{ DMA0_24_28_DriverIRQHandler();
598}
599
600WEAK void DMA0_25_29_IRQHandler(void) //DMA Channel 25, 29 Transfer Complete
601{ DMA0_25_29_DriverIRQHandler();
602}
603
604WEAK void DMA0_26_30_IRQHandler(void) //DMA Channel 26, 30 Transfer Complete
605{ DMA0_26_30_DriverIRQHandler();
606}
607
608WEAK void DMA0_27_31_IRQHandler(void) //DMA Channel 27, 31 Transfer Complete
609{ DMA0_27_31_DriverIRQHandler();
610}
611
612WEAK void DMA0_Error_IRQHandler(void) //DMA Error Interrupt - All Channels
613{ DMA0_Error_DriverIRQHandler();
614}
615
616WEAK void MCM0_IRQHandler(void) //MCM Interrupt
617{ MCM0_DriverIRQHandler();
618}
619
620WEAK void EWM_IRQHandler(void) //External Watchdog Monitor Interrupt
621{ EWM_DriverIRQHandler();
622}
623
624WEAK void LLWU0_IRQHandler(void) //Low Leakage Wake Up
625{ LLWU0_DriverIRQHandler();
626}
627
628WEAK void SIM_IRQHandler(void) //System Integation Module
629{ SIM_DriverIRQHandler();
630}
631
632WEAK void MU_A_IRQHandler(void) //Messaging Unit - Side A
633{ MU_A_DriverIRQHandler();
634}
635
636WEAK void Software1_IRQHandler(void) //Software Interrupt
637{ Software1_DriverIRQHandler();
638}
639
640WEAK void Software2_IRQHandler(void) //Software Interrupt
641{ Software2_DriverIRQHandler();
642}
643
644WEAK void WDOG0_IRQHandler(void) //Watchdog Interrupt
645{ WDOG0_DriverIRQHandler();
646}
647
648WEAK void SCG0_IRQHandler(void) //System Clock Generator for M4 domain
649{ SCG0_DriverIRQHandler();
650}
651
652WEAK void QSPI_IRQHandler(void) //Quad Serial Peripheral Interface
653{ QSPI_DriverIRQHandler();
654}
655
656WEAK void LTC_IRQHandler(void) //Low Power Trusted Cryptography
657{ LTC_DriverIRQHandler();
658}
659
660WEAK void SNVS_IRQHandler(void) //Secure Non-Volatile Storage Consolidated Interrupt
661{ SNVS_DriverIRQHandler();
662}
663
664WEAK void TRNG0_IRQHandler(void) //Random Number Generator
665{ TRNG0_DriverIRQHandler();
666}
667
668WEAK void LPIT0_IRQHandler(void) //Low Power Periodic Interrupt Timer
669{ LPIT0_DriverIRQHandler();
670}
671
672WEAK void PMC0_IRQHandler(void) //Power Management Control interrupts for M4 domain
673{ PMC0_DriverIRQHandler();
674}
675
676WEAK void CMC0_IRQHandler(void) //Core Mode Controller interrupts for M4 domain
677{ CMC0_DriverIRQHandler();
678}
679
680WEAK void LPTMR0_IRQHandler(void) //Low Power Timer
681{ LPTMR0_DriverIRQHandler();
682}
683
684WEAK void LPTMR1_IRQHandler(void) //Low Power Timer
685{ LPTMR1_DriverIRQHandler();
686}
687
688WEAK void TPM0_IRQHandler(void) //Timer PWM module
689{ TPM0_DriverIRQHandler();
690}
691
692WEAK void TPM1_IRQHandler(void) //Timer PWM module
693{ TPM1_DriverIRQHandler();
694}
695
696WEAK void TPM2_IRQHandler(void) //Timer PWM module
697{ TPM2_DriverIRQHandler();
698}
699
700WEAK void TPM3_IRQHandler(void) //Timer PWM module
701{ TPM3_DriverIRQHandler();
702}
703
704WEAK void FLEXIO0_IRQHandler(void) //Flexible IO
705{ FLEXIO0_DriverIRQHandler();
706}
707
708WEAK void LPI2C0_IRQHandler(void) //Inter-integrated circuit 0
709{ LPI2C0_DriverIRQHandler();
710}
711
712WEAK void LPI2C1_IRQHandler(void) //Inter-integrated circuit 1
713{ LPI2C1_DriverIRQHandler();
714}
715
716WEAK void LPI2C2_IRQHandler(void) //Inter-integrated circuit 2
717{ LPI2C2_DriverIRQHandler();
718}
719
720WEAK void LPI2C3_IRQHandler(void) //Inter-integrated circuit 3
721{ LPI2C3_DriverIRQHandler();
722}
723
724WEAK void SAI0_IRQHandler(void) //Serial Audio Interface
725{ SAI0_DriverIRQHandler();
726}
727
728WEAK void SAI1_IRQHandler(void) //Serial Audio Interface 1
729{ SAI1_DriverIRQHandler();
730}
731
732WEAK void LPSPI0_IRQHandler(void) //Low Power Serial Peripheral Interface
733{ LPSPI0_DriverIRQHandler();
734}
735
736WEAK void LPSPI1_IRQHandler(void) //Low Power Serial Peripheral Interface
737{ LPSPI1_DriverIRQHandler();
738}
739
740WEAK void LPUART0_IRQHandler(void) //Low Power UART
741{ LPUART0_DriverIRQHandler();
742}
743
744WEAK void LPUART1_IRQHandler(void) //Low Power UART
745{ LPUART1_DriverIRQHandler();
746}
747
748WEAK void LPUART2_IRQHandler(void) //Low Power UART
749{ LPUART2_DriverIRQHandler();
750}
751
752WEAK void LPUART3_IRQHandler(void) //Low Power UART
753{ LPUART3_DriverIRQHandler();
754}
755
756WEAK void DPM_IRQHandler(void) //Dynamic Process Monitor
757{ DPM_DriverIRQHandler();
758}
759
760WEAK void PCTLA_IRQHandler(void) //Port A pin interrupt
761{ PCTLA_DriverIRQHandler();
762}
763
764WEAK void PCTLB_IRQHandler(void) //Port B pin interrupt
765{ PCTLB_DriverIRQHandler();
766}
767
768WEAK void ADC0_IRQHandler(void) //Analog to Digital Convertor
769{ ADC0_DriverIRQHandler();
770}
771
772WEAK void ADC1_IRQHandler(void) //Analog to Digital Convertor
773{ ADC1_DriverIRQHandler();
774}
775
776WEAK void CMP0_IRQHandler(void) //Comparator
777{ CMP0_DriverIRQHandler();
778}
779
780WEAK void CMP1_IRQHandler(void) //Comparator
781{ CMP1_DriverIRQHandler();
782}
783
784WEAK void DAC0_IRQHandler(void) //Digital to Analog Convertor
785{ DAC0_DriverIRQHandler();
786}
787
788WEAK void DAC1_IRQHandler(void) //Digital to Analog Convertor
789{ DAC1_DriverIRQHandler();
790}
791
792WEAK void WDOG1_IRQHandler(void) //Watchdog Interrupt from A7 subsystem
793{ WDOG1_DriverIRQHandler();
794}
795
796WEAK void USB0_IRQHandler(void) //USB 0 Interrupt from A7 subsystem
797{ USB0_DriverIRQHandler();
798}
799
800WEAK void USB1_IRQHandler(void) //USB 1 Interrupt from A7 subsystem
801{ USB1_DriverIRQHandler();
802}
803
804WEAK void WDOG2_IRQHandler(void) //Watchdog Interrupt from A7 subsystem
805{ WDOG2_DriverIRQHandler();
806}
807
808WEAK void USBPHY_IRQHandler(void) //USB PHY (used in conjunction with USBOTG0)
809{ USBPHY_DriverIRQHandler();
810}
811
812WEAK void CMC1_IRQHandler(void) //A7 resets
813{ CMC1_DriverIRQHandler();
814}
815
816//*****************************************************************************
817
818#if defined (DEBUG)
819#pragma GCC pop_options
820#endif // (DEBUG)
821
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/board.c
new file mode 100644
index 000000000..cfe975c19
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/board.c
@@ -0,0 +1,179 @@
1/*
2 * Copyright 2017 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "fsl_debug_console.h"
10#include "fsl_rdc.h"
11#include "fsl_iomuxc.h"
12#include "pin_mux.h"
13#include "board.h"
14#include "fsl_clock.h"
15/*******************************************************************************
16 * Variables
17 ******************************************************************************/
18
19/*******************************************************************************
20 * Code
21 ******************************************************************************/
22/* Initialize debug console. */
23void BOARD_InitDebugConsole(void)
24{
25 uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
26 CLOCK_EnableClock(kCLOCK_Uart2);
27 DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, DEBUG_CONSOLE_DEVICE_TYPE_IUART,
28 uartClkSrcFreq);
29}
30/* Initialize MPU, configure non-cacheable memory */
31void BOARD_InitMemory(void)
32{
33#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
34 extern uint32_t Load$$LR$$LR_cache_region$$Base[];
35 extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
36 uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
37 uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
38#else
39 extern uint32_t __CACHE_REGION_START[];
40 extern uint32_t __CACHE_REGION_SIZE[];
41 uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
42 uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
43#endif
44 uint32_t i = 0;
45 /* Make sure outstanding transfers are done. */
46 __DMB();
47 /* Disable the MPU. */
48 MPU->CTRL = 0;
49
50 /*
51 * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
52 * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
53 * change the default memory attributes.
54 * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
55 * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
56 * 0x27FFFFFF) to use the
57 * background memory attributes.
58 */
59
60 /* Select Region 0 and set its base address to the M4 code bus start address. */
61 MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
62
63 /* Region 0 setting:
64 * 1) Disable Instruction Access;
65 * 2) AP = 011b, full access;
66 * 3) Non-shared device;
67 * 4) Region Not Shared;
68 * 5) Sub-Region 0,1 Disabled;
69 * 6) MPU Protection Region size = 512M byte;
70 * 7) Enable Region 0.
71 */
72 MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
73 (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
74
75 /*
76 * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
77 * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
78 * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
79 * region size,
80 * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
81 * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
82 * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
83 * needs.
84 */
85
86 /* Select Region 1 and set its base address to the DDR start address. */
87 MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
88
89 /* Region 1 setting:
90 * 1) Enable Instruction Access;
91 * 2) AP = 011b, full access;
92 * 3) Shared Device;
93 * 4) MPU Protection Region size = 1024M byte;
94 * 5) Enable Region 1.
95 */
96 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
97
98 /* Select Region 2 and set its base address to the DDR start address. */
99 MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
100
101 /* Region 2 setting:
102 * 1) Enable Instruction Access;
103 * 2) AP = 011b, full access;
104 * 3) Shared Device;
105 * 4) MPU Protection Region size = 1024M byte;
106 * 5) Enable Region 2.
107 */
108 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
109
110 while ((size >> i) > 0x1U)
111 {
112 i++;
113 }
114
115 /* If run on DDR, configure text and data section to be cacheable */
116 if (i != 0)
117 {
118 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
119 assert((size & (size - 1)) == 0);
120 assert(!(cacheStart % size));
121 assert(size == (uint32_t)(1 << i));
122 assert(i >= 5);
123
124 /* Select Region 3 and set its base address to the cache able region start address. */
125 MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
126
127 /* Region 3 setting:
128 * 1) Enable Instruction Access;
129 * 2) AP = 011b, full access;
130 * 3) Outer and inner Cacheable, write and read allocate;
131 * 4) Region Not Shared;
132 * 5) All Sub-Region Enabled;
133 * 6) MPU Protection Region size get from linker file;
134 * 7) Enable Region 3.
135 */
136 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
137 (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
138 }
139
140 /* Enable Privileged default memory map and the MPU. */
141 MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
142 /* Memory barriers to ensure subsequence data & instruction
143 * transfers using updated MPU settings.
144 */
145 __DSB();
146 __ISB();
147}
148
149void BOARD_RdcInit(void)
150{
151 /* Move M4 core to specific RDC domain 1 */
152 rdc_domain_assignment_t assignment = {0};
153
154 assignment.domainId = BOARD_DOMAIN_ID;
155 RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
156 /*
157 * The M4 core is running at domain 1, enable clock gate for Iomux and Gpio to run at domain 1.
158 */
159 CLOCK_EnableClock(kCLOCK_Gpio1);
160 CLOCK_EnableClock(kCLOCK_Gpio2);
161 CLOCK_EnableClock(kCLOCK_Gpio3);
162 CLOCK_EnableClock(kCLOCK_Gpio4);
163 CLOCK_EnableClock(kCLOCK_Gpio5);
164
165 CLOCK_EnableClock(kCLOCK_Iomux0);
166 CLOCK_EnableClock(kCLOCK_Iomux1);
167 CLOCK_EnableClock(kCLOCK_Iomux2);
168 CLOCK_EnableClock(kCLOCK_Iomux3);
169 CLOCK_EnableClock(kCLOCK_Iomux4);
170 /*
171 * The M4 core is running at domain 1, enable the PLL clock sources to domain 1.
172 */
173 CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enabel SysPLL1 to Domain 1 */
174 CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable SysPLL2 to Domain 1 */
175 CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable SysPLL3 to Domain 1 */
176 CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable AudioPLL1 to Domain 1 */
177 CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable AudioPLL2 to Domain 1 */
178 CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable VideoPLL1 to Domain 1 */
179}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/board.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/board.h
new file mode 100644
index 000000000..4a442bd06
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/board.h
@@ -0,0 +1,46 @@
1/*
2 * Copyright 2017 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _BOARD_H_
9#define _BOARD_H_
10#include "clock_config.h"
11#include "fsl_clock.h"
12/*******************************************************************************
13 * Definitions
14 ******************************************************************************/
15/*! @brief The board name */
16#define BOARD_NAME "MIMX8MQ-EVK"
17#define MANUFACTURER_NAME "NXP"
18#define BOARD_DOMAIN_ID (1)
19/* The UART to use for debug messages. */
20#define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_UART
21#define BOARD_DEBUG_UART_BAUDRATE 115200u
22#define BOARD_DEBUG_UART_BASEADDR UART2_BASE
23#define BOARD_DEBUG_UART_INSTANCE 2U
24#define BOARD_DEBUG_UART_CLK_FREQ \
25 CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \
26 (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10
27#define BOARD_UART_IRQ UART2_IRQn
28#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler
29
30#if defined(__cplusplus)
31extern "C" {
32#endif /* __cplusplus */
33
34/*******************************************************************************
35 * API
36 ******************************************************************************/
37
38void BOARD_InitDebugConsole(void);
39void BOARD_InitMemory(void);
40void BOARD_RdcInit(void);
41
42#if defined(__cplusplus)
43}
44#endif /* __cplusplus */
45
46#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/clock_config.c
new file mode 100644
index 000000000..ef4a40577
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/clock_config.c
@@ -0,0 +1,145 @@
1/*
2 * Copyright 2017 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "clock_config.h"
10
11/*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14
15/* OSC 27M configuration */
16const osc_config_t g_osc27MConfig = {
17 .oscMode = kOSC_OscMode, .oscDiv = 1U,
18};
19
20/* OSC 25M configuration */
21const osc_config_t g_osc25MConfig = {
22 .oscMode = kOSC_OscMode, .oscDiv = 1U,
23};
24
25/* AUDIO PLL1 configuration */
26const ccm_analog_frac_pll_config_t g_audioPll1Config = {
27 .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */
28 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
29 .fractionDiv = 0U,
30 .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */
31 .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */
32};
33
34/* AUDIO PLL2 configuration */
35const ccm_analog_frac_pll_config_t g_audioPll2Config = {
36 .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */
37 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
38 .fractionDiv = 0U,
39 .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */
40 .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */
41};
42
43/* VIDEO PLL1 configuration */
44const ccm_analog_frac_pll_config_t g_videoPll1Config = {
45 .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */
46 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
47 .fractionDiv = 0U,
48 .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */
49 .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */
50};
51
52/* SYSTEM PLL1 configuration */
53const ccm_analog_sscg_pll_config_t g_sysPll1Config = {
54 .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */
55 .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */
56 .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */
57 .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */
58 .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */
59 .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */
60};
61
62/* SYSTEM PLL2 configuration */
63const ccm_analog_sscg_pll_config_t g_sysPll2Config = {
64 .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */
65 .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */
66 .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */
67 .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */
68 .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */
69 .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */
70};
71
72/* SYSTEM PLL3 configuration */
73const ccm_analog_sscg_pll_config_t g_sysPll3Config = {
74 .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */
75 .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */
76 .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */
77 .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */
78 .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */
79 .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */
80};
81
82/*******************************************************************************
83 * Variables
84 ******************************************************************************/
85
86/*******************************************************************************
87 * Code
88 ******************************************************************************/
89void BOARD_BootClockRUN(void)
90{
91 /* OSC configuration */
92 CLOCK_InitOSC25M(&g_osc25MConfig);
93 CLOCK_InitOSC27M(&g_osc27MConfig);
94
95 /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
96 * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
97 * would also do configuration on the SYSTEM PLL1 to 800Mhz and SYSTEM PLL2 to 1000Mhz by U-Boot.*/
98
99 /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */
100 CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m);
101 CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m);
102 /* switch AXI M4 root to 25M first in order to configure the SYSTEM PLL2. */
103 CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m);
104 CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc25m);
105
106 CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
107 CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
108 CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */
109
110 CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */
111 CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */
112 CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */
113
114 CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */
115 CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
116
117 CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
118 CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
119
120 CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U);
121 CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */
122
123 CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
124 CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
125
126 CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
127
128 /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
129 * enters the low power status.*/
130 // CLOCK_EnableClock(kCLOCK_Sim_m);
131 // CLOCK_EnableClock(kCLOCK_Sim_main);
132 // CLOCK_EnableClock(kCLOCK_Sim_s);
133 // CLOCK_EnableClock(kCLOCK_Sim_wakeup);
134 // CLOCK_EnableClock(kCLOCK_Debug);
135 // CLOCK_EnableClock(kCLOCK_Dram);
136 // CLOCK_EnableClock(kCLOCK_Sec_Debug);
137
138 /* Disable unused PLL */
139 CLOCK_DeinitSysPll3();
140 CLOCK_DeinitVideoPll1();
141 CLOCK_DeinitAudioPll1();
142 CLOCK_DeinitAudioPll2();
143 /* Update core clock */
144 SystemCoreClockUpdate();
145}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/clock_config.h
new file mode 100644
index 000000000..84bbbed41
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/clock_config.h
@@ -0,0 +1,27 @@
1/*
2 * Copyright 2017 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7#ifndef _CLOCK_CONFIG_H_
8#define _CLOCK_CONFIG_H_
9
10/*******************************************************************************
11 * Definitions
12 ******************************************************************************/
13
14/*******************************************************************************
15 * API
16 ******************************************************************************/
17#if defined(__cplusplus)
18extern "C" {
19#endif /* __cplusplus*/
20
21void BOARD_BootClockRUN(void);
22
23#if defined(__cplusplus)
24}
25#endif /* __cplusplus*/
26
27#endif /* _CLOCK_CONFIG_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/peripherals.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/peripherals.c
new file mode 100644
index 000000000..ead892540
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/peripherals.c
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2019 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
9!!GlobalInfo
10product: Peripherals v1.0
11 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
12
13/*******************************************************************************
14 * Included files
15 ******************************************************************************/
16#include "peripherals.h"
17
18/*******************************************************************************
19 * BOARD_InitBootPeripherals function
20 ******************************************************************************/
21void BOARD_InitBootPeripherals(void)
22{
23}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/peripherals.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/peripherals.h
new file mode 100644
index 000000000..92e132099
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/peripherals.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2019 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _PERIPHERALS_H_
9#define _PERIPHERALS_H_
10
11#if defined(__cplusplus)
12extern "C" {
13#endif /*_cplusplus. */
14 /*******************************************************************************
15 * BOARD_InitBootPeripherals function
16 ******************************************************************************/
17void BOARD_InitBootPeripherals(void);
18
19#if defined(__cplusplus)
20}
21#endif /*_cplusplus. */
22
23#endif /* _PERIPHERALS_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/pin_mux.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/pin_mux.c
new file mode 100644
index 000000000..48e0d18ef
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/pin_mux.c
@@ -0,0 +1,57 @@
1/*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13/*
14 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
15!!GlobalInfo
16product: Pins v5.0
17processor: MIMX8MD7xxxJZ
18mcu_data: ksdk2_0
19processor_version: 0.0.12
20 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
21 */
22
23#include "fsl_common.h"
24#include "fsl_iomuxc.h"
25#include "pin_mux.h"
26
27/* FUNCTION ************************************************************************************************************
28 *
29 * Function Name : BOARD_InitBootPins
30 * Description : Calls initialization functions.
31 *
32 * END ****************************************************************************************************************/
33void BOARD_InitBootPins(void)
34{
35 BOARD_InitPins();
36}
37
38/*
39 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
40BOARD_InitPins:
41- options: {callFromInitBoot: 'true', coreID: a53_0}
42- pin_list: []
43 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
44 */
45
46/* FUNCTION ************************************************************************************************************
47 *
48 * Function Name : BOARD_InitPins
49 * Description : Configures pin routing and optionally pin electrical features.
50 *
51 * END ****************************************************************************************************************/
52void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-A53[a53_0] */
53}
54
55/***********************************************************************************************************************
56 * EOF
57 **********************************************************************************************************************/
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/pin_mux.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/pin_mux.h
new file mode 100644
index 000000000..018d54f57
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/pin_mux.h
@@ -0,0 +1,54 @@
1/*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _PIN_MUX_H_
9#define _PIN_MUX_H_
10
11#include "board.h"
12
13/***********************************************************************************************************************
14 * Definitions
15 **********************************************************************************************************************/
16
17/*!
18 * @addtogroup pin_mux
19 * @{
20 */
21
22/***********************************************************************************************************************
23 * API
24 **********************************************************************************************************************/
25
26#if defined(__cplusplus)
27extern "C" {
28#endif
29
30
31/*!
32 * @brief Calls initialization functions.
33 *
34 */
35void BOARD_InitBootPins(void);
36
37/*!
38 * @brief Configures pin routing and optionally pin electrical features.
39 *
40 */
41void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-A53[a53_0] */
42
43#if defined(__cplusplus)
44}
45#endif
46
47/*!
48 * @}
49 */
50#endif /* _PIN_MUX_H_ */
51
52/***********************************************************************************************************************
53 * EOF
54 **********************************************************************************************************************/
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/system_MIMX8MD7_cm4.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/system_MIMX8MD7_cm4.c
new file mode 100644
index 000000000..45405bbb9
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/system_MIMX8MD7_cm4.c
@@ -0,0 +1,269 @@
1/*
2** ###################################################################
3** Processors: MIMX8MD7CVAHZ
4** MIMX8MD7DVAJZ
5**
6** Compilers: Keil ARM C/C++ Compiler
7** GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9**
10** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018
11** Version: rev. 4.0, 2018-01-26
12** Build: b180903
13**
14** Abstract:
15** Provides a system configuration function and a global variable that
16** contains the system frequency. It configures the device and initializes
17** the oscillator (PLL) that is part of the microcontroller device.
18**
19** Copyright 2016 Freescale Semiconductor, Inc.
20** Copyright 2016-2018 NXP
21** All rights reserved.
22**
23** SPDX-License-Identifier: BSD-3-Clause
24**
25** http: www.nxp.com
26** mail: [email protected]
27**
28** Revisions:
29** - rev. 1.0 (2017-01-10)
30** Initial version.
31** - rev. 2.0 (2017-04-27)
32** Rev.B Header EAR1
33** - rev. 3.0 (2017-07-19)
34** Rev.C Header EAR2
35** - rev. 4.0 (2018-01-26)
36** Rev.D Header RFP
37**
38** ###################################################################
39*/
40
41/*!
42 * @file MIMX8MD7_cm4
43 * @version 4.0
44 * @date 2018-01-26
45 * @brief Device specific configuration file for MIMX8MD7_cm4 (implementation
46 * file)
47 *
48 * Provides a system configuration function and a global variable that contains
49 * the system frequency. It configures the device and initializes the oscillator
50 * (PLL) that is part of the microcontroller device.
51 */
52
53#include <stdint.h>
54#include "fsl_device_registers.h"
55
56/*!
57 * @brief CCM reg macros to extract corresponding registers bit field.
58 */
59#define CCM_BIT_FIELD_VAL(val, mask, shift) (((val)&mask) >> shift)
60
61/*!
62 * @brief CCM reg macros to get corresponding registers values.
63 */
64#define CCM_ANALOG_REG_VAL(base, off) (*((volatile uint32_t *)((uint32_t)(base) + (off))))
65
66/*******************************************************************************
67 * Prototypes
68 ******************************************************************************/
69uint32_t GetFracPllFreq(const volatile uint32_t *base);
70uint32_t GetSSCGPllFreq(const volatile uint32_t *base);
71
72uint32_t GetFracPllFreq(const volatile uint32_t *base)
73{
74 uint32_t fracCfg0 = CCM_ANALOG_REG_VAL(base, 0U);
75 uint32_t fracCfg1 = CCM_ANALOG_REG_VAL(base, 4U);
76 uint32_t refClkFreq = 0U;
77 uint64_t fracClk = 0U;
78
79 uint8_t refSel = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_MASK,
80 CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT);
81 uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK,
82 CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_SHIFT);
83 uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK,
84 CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT);
85 uint32_t fracDiv = CCM_BIT_FIELD_VAL(fracCfg1, CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK,
86 CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_SHIFT);
87 uint8_t intDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg1, CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK,
88 CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_SHIFT);
89
90 if (refSel == 0U) /* OSC 25M Clock */
91 {
92 refClkFreq = CPU_XTAL_SOSC_CLK_25MHZ;
93 }
94 else if ((refSel == 1U) || /* OSC 27M Clock */
95 (refSel == 2U)) /* HDMI_PYH 27M Clock */
96 {
97 refClkFreq = CPU_XTAL_SOSC_CLK_27MHZ;
98 }
99 else
100 {
101 refClkFreq = CLK_P_N_FREQ; /* CLK_P_N Clock, please note that the value is 0hz by default, it could be set at
102 system_MIMX8MQx_cm4.h :88 */
103 }
104 refClkFreq /= (uint32_t)refDiv + 1U;
105 fracClk = (uint64_t)refClkFreq * 8U * (1U + intDiv) + (((uint64_t)refClkFreq * 8U * fracDiv) >> 24U);
106
107 return (uint32_t)(fracClk / (((uint64_t)outDiv + 1U) * 2U));
108}
109
110uint32_t GetSSCGPllFreq(const volatile uint32_t *base)
111{
112 uint32_t sscgCfg0 = CCM_ANALOG_REG_VAL(base, 0U);
113 uint32_t sscgCfg1 = CCM_ANALOG_REG_VAL(base, 4U);
114 uint32_t sscgCfg2 = CCM_ANALOG_REG_VAL(base, 8U);
115 uint32_t refClkFreq = 0U;
116 uint64_t pll2InputClock = 0U;
117
118 uint8_t pll1Bypass = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg0, CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_MASK,
119 CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_SHIFT);
120 uint8_t refSel = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg0, CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_MASK,
121 CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT);
122 uint8_t refDiv1 = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_MASK,
123 CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_SHIFT) +
124 1U;
125 uint8_t refDiv2 = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK,
126 CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_SHIFT) +
127 1U;
128 uint8_t divf1 = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_MASK,
129 CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_SHIFT) +
130 1U;
131 uint8_t divf2 = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_MASK,
132 CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_SHIFT) +
133 1U;
134 uint8_t outDiv = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_MASK,
135 CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT) +
136 1U;
137
138 if (refSel == 0U) /* OSC 25M Clock */
139 {
140 refClkFreq = CPU_XTAL_SOSC_CLK_25MHZ;
141 }
142 else if ((refSel == 1U) || /* OSC 27M Clock */
143 (refSel == 2U)) /* HDMI_PYH 27M Clock */
144 {
145 refClkFreq = CPU_XTAL_SOSC_CLK_27MHZ;
146 }
147 else
148 {
149 refClkFreq = CLK_P_N_FREQ; /* CLK_P_N Clock, please note that the value is 0hz by default, it could be set at
150 system_MIMX8MQx_cm4.h :88 */
151 }
152
153 refClkFreq /= refDiv1;
154
155 if (pll1Bypass != 0U)
156 {
157 pll2InputClock = refClkFreq;
158 }
159 else if ((sscgCfg1 & CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE_MASK) != 0U)
160 {
161 pll2InputClock = (uint64_t)refClkFreq * 8U * divf1 / refDiv2;
162 }
163 else
164 {
165 pll2InputClock = (uint64_t)refClkFreq * 2U * divf1 / refDiv2;
166 }
167
168 return (uint32_t)(pll2InputClock * divf2 / outDiv);
169}
170
171/* ----------------------------------------------------------------------------
172 -- Core clock
173 ---------------------------------------------------------------------------- */
174
175uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
176
177/* ----------------------------------------------------------------------------
178 -- SystemInit()
179 ---------------------------------------------------------------------------- */
180
181void SystemInit(void)
182{
183#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
184 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
185#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
186
187 /* Initialize Cache */
188 /* Enable Code Bus Cache */
189 /* set command to invalidate all ways, and write GO bit to initiate command */
190 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
191 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK;
192 /* Wait until the command completes */
193 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U)
194 {
195 }
196 /* Enable cache, enable write buffer */
197 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);
198
199 /* Enable System Bus Cache */
200 /* set command to invalidate all ways, and write GO bit to initiate command */
201 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK;
202 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK;
203 /* Wait until the command completes */
204 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U)
205 {
206 }
207 /* Enable cache, enable write buffer */
208 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK);
209
210 __ISB();
211 __DSB();
212
213 SystemInitHook();
214}
215
216/* ----------------------------------------------------------------------------
217 -- SystemCoreClockUpdate()
218 ---------------------------------------------------------------------------- */
219
220void SystemCoreClockUpdate(void)
221{
222 volatile uint32_t *M4_ClockRoot = (volatile uint32_t *)(&(CCM)->ROOT[1].TARGET_ROOT);
223 uint32_t pre = ((*M4_ClockRoot & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U;
224 uint32_t post = ((*M4_ClockRoot & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + 1U;
225
226 uint32_t freq = 0U;
227
228 switch ((*M4_ClockRoot & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT)
229 {
230 case 0U: /* OSC 25M Clock */
231 freq = CPU_XTAL_SOSC_CLK_25MHZ;
232 break;
233 case 1U: /* System PLL2 DIV5 */
234 freq = GetSSCGPllFreq(&(CCM_ANALOG->SYS_PLL2_CFG0)) / 5U; /* Get System PLL2 DIV5 freq */
235 break;
236 case 2U: /* System PLL2 DIV4 */
237 freq = GetSSCGPllFreq(&(CCM_ANALOG->SYS_PLL2_CFG0)) / 4U; /* Get System PLL2 DIV4 freq */
238 break;
239 case 3U: /* System PLL1 DIV3 */
240 freq = GetSSCGPllFreq(&(CCM_ANALOG->SYS_PLL1_CFG0)) / 3U; /* Get System PLL1 DIV3 freq */
241 break;
242 case 4U: /* System PLL1 */
243 freq = GetSSCGPllFreq(&(CCM_ANALOG->SYS_PLL1_CFG0)); /* Get System PLL1 freq */
244 break;
245 case 5U: /* AUDIO PLL1 */
246 freq = GetFracPllFreq(&(CCM_ANALOG->AUDIO_PLL1_CFG0)); /* Get AUDIO PLL1 freq */
247 break;
248 case 6U: /* VIDEO PLL1 */
249 freq = GetFracPllFreq(&(CCM_ANALOG->VIDEO_PLL1_CFG0)); /* Get VIDEO PLL1 freq */
250 break;
251 case 7U: /* System PLL3 */
252 freq = GetSSCGPllFreq(&(CCM_ANALOG->SYS_PLL3_CFG0)); /* Get System PLL3 freq */
253 break;
254 default:
255 freq = CPU_XTAL_SOSC_CLK_25MHZ;
256 break;
257 }
258
259 SystemCoreClock = freq / pre / post;
260}
261
262/* ----------------------------------------------------------------------------
263 -- SystemInitHook()
264 ---------------------------------------------------------------------------- */
265
266__attribute__((weak)) void SystemInitHook(void)
267{
268 /* Void implementation of the weak function. */
269}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/system_MIMX8MD7_cm4.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/system_MIMX8MD7_cm4.h
new file mode 100644
index 000000000..94fdc2289
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/system_MIMX8MD7_cm4.h
@@ -0,0 +1,119 @@
1/*
2** ###################################################################
3** Processors: MIMX8MD7CVAHZ
4** MIMX8MD7DVAJZ
5**
6** Compilers: Keil ARM C/C++ Compiler
7** GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9**
10** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018
11** Version: rev. 4.0, 2018-01-26
12** Build: b180903
13**
14** Abstract:
15** Provides a system configuration function and a global variable that
16** contains the system frequency. It configures the device and initializes
17** the oscillator (PLL) that is part of the microcontroller device.
18**
19** Copyright 2016 Freescale Semiconductor, Inc.
20** Copyright 2016-2018 NXP
21** All rights reserved.
22**
23** SPDX-License-Identifier: BSD-3-Clause
24**
25** http: www.nxp.com
26** mail: [email protected]
27**
28** Revisions:
29** - rev. 1.0 (2017-01-10)
30** Initial version.
31** - rev. 2.0 (2017-04-27)
32** Rev.B Header EAR1
33** - rev. 3.0 (2017-07-19)
34** Rev.C Header EAR2
35** - rev. 4.0 (2018-01-26)
36** Rev.D Header RFP
37**
38** ###################################################################
39*/
40
41/*!
42 * @file MIMX8MD7_cm4
43 * @version 4.0
44 * @date 2018-01-26
45 * @brief Device specific configuration file for MIMX8MD7_cm4 (header file)
46 *
47 * Provides a system configuration function and a global variable that contains
48 * the system frequency. It configures the device and initializes the oscillator
49 * (PLL) that is part of the microcontroller device.
50 */
51
52#ifndef _SYSTEM_MIMX8MD7_cm4_H_
53#define _SYSTEM_MIMX8MD7_cm4_H_ /**< Symbol preventing repeated inclusion */
54
55#ifdef __cplusplus
56extern "C" {
57#endif
58
59#include <stdint.h>
60
61
62/* i.MX8MQ Definitions */
63#ifndef DISABLE_WDOG
64 #define DISABLE_WDOG 1
65#endif
66/* Define clock source values */
67#define CLK_P_N_FREQ 0u /* The value could be changeD according to the actual usage */
68#define CPU_XTAL_SOSC_CLK_25MHZ 25000000u /* Value of the external System Oscillator Clock(SOSC) frequency in Hz */
69#define CPU_XTAL_SOSC_CLK_27MHZ 27000000u /* Value of the external System Oscillator Clock(SOSC) frequency in Hz */
70#define CPU_HDMI_PHY_CLK_27MHZ 27000000u /* Value of the HDMI PHY 27M clock frequency in Hz*/
71#define DEFAULT_SYSTEM_CLOCK 266666666u /* Default System clock value */
72
73
74/**
75 * @brief System clock frequency (core clock)
76 *
77 * The system clock frequency supplied to the SysTick timer and the processor
78 * core clock. This variable can be used by the user application to setup the
79 * SysTick timer or configure other parameters. It may also be used by debugger to
80 * query the frequency of the debug timer or configure the trace clock speed
81 * SystemCoreClock is initialized with a correct predefined value.
82 */
83extern uint32_t SystemCoreClock;
84
85/**
86 * @brief Setup the microcontroller system.
87 *
88 * Typically this function configures the oscillator (PLL) that is part of the
89 * microcontroller device. For systems with variable clock speed it also updates
90 * the variable SystemCoreClock. SystemInit is called from startup_device file.
91 */
92void SystemInit (void);
93
94/**
95 * @brief Updates the SystemCoreClock variable.
96 *
97 * It must be called whenever the core clock is changed during program
98 * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
99 * the current core clock.
100 */
101void SystemCoreClockUpdate (void);
102
103/**
104 * @brief SystemInit function hook.
105 *
106 * This weak function allows to call specific initialization code during the
107 * SystemInit() execution.This can be used when an application specific code needs
108 * to be called as close to the reset entry as possible (for example the Multicore
109 * Manager MCMGR_EarlyInit() function call).
110 * NOTE: No global r/w variables can be used in this hook function because the
111 * initialization of these variables happens after this function.
112 */
113void SystemInitHook (void);
114
115#ifdef __cplusplus
116}
117#endif
118
119#endif /* _SYSTEM_MIMX8MD7_cm4_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/template/RTE_Device.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/template/RTE_Device.h
new file mode 100644
index 000000000..fbbbace1d
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/template/RTE_Device.h
@@ -0,0 +1,48 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _RTE_DEVICE_H
10#define _RTE_DEVICE_H
11
12#include "pin_mux.h"
13
14/* UART select, UART1-UART4 */
15/* User needs to provide the implementation of UARTX_GetFreq/UARTX_InitPins/UARTX_DeinitPins for the enabled UART
16 * instance. */
17#define RTE_USART1 0
18#define RTE_USART1_DMA_EN 0
19#define RTE_USART2 0
20#define RTE_USART2_DMA_EN 0
21#define RTE_USART3 0
22#define RTE_USART3_DMA_EN 0
23#define RTE_USART4 0
24#define RTE_USART4_DMA_EN 0
25
26/* I2C select, I2C1 - I2C4. */
27/* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance.
28 */
29#define RTE_I2C1 0
30#define RTE_I2C1_DMA_EN 0
31#define RTE_I2C2 0
32#define RTE_I2C2_DMA_EN 0
33#define RTE_I2C3 0
34#define RTE_I2C3_DMA_EN 0
35#define RTE_I2C4 0
36#define RTE_I2C4_DMA_EN 0
37
38/* SPI select, ECSPI1 - ECSPI3. */
39/* User needs to provide the implementation of ECSPIX_GetFreq/ECSPIX_InitPins/ECSPIX_DeinitPins for the enabled ECSPI
40 * instance. */
41#define RTE_SPI0 0
42#define RTE_SPI0_DMA_EN 0
43#define RTE_SPI1 0
44#define RTE_SPI1_DMA_EN 0
45#define RTE_SPI2 0
46#define RTE_SPI2_DMA_EN 0
47
48#endif /* _RTE_DEVICE_H */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 05:23:14 +0100