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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/board.c179
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/board.h46
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/clock_config.c145
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/clock_config.h27
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/peripherals.c23
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/peripherals.h23
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/pin_mux.c57
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/pin_mux.h54
8 files changed, 554 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/board.c
new file mode 100644
index 000000000..cfe975c19
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/board.c
@@ -0,0 +1,179 @@
1/*
2 * Copyright 2017 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "fsl_debug_console.h"
10#include "fsl_rdc.h"
11#include "fsl_iomuxc.h"
12#include "pin_mux.h"
13#include "board.h"
14#include "fsl_clock.h"
15/*******************************************************************************
16 * Variables
17 ******************************************************************************/
18
19/*******************************************************************************
20 * Code
21 ******************************************************************************/
22/* Initialize debug console. */
23void BOARD_InitDebugConsole(void)
24{
25 uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
26 CLOCK_EnableClock(kCLOCK_Uart2);
27 DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, DEBUG_CONSOLE_DEVICE_TYPE_IUART,
28 uartClkSrcFreq);
29}
30/* Initialize MPU, configure non-cacheable memory */
31void BOARD_InitMemory(void)
32{
33#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
34 extern uint32_t Load$$LR$$LR_cache_region$$Base[];
35 extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
36 uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
37 uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
38#else
39 extern uint32_t __CACHE_REGION_START[];
40 extern uint32_t __CACHE_REGION_SIZE[];
41 uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
42 uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
43#endif
44 uint32_t i = 0;
45 /* Make sure outstanding transfers are done. */
46 __DMB();
47 /* Disable the MPU. */
48 MPU->CTRL = 0;
49
50 /*
51 * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
52 * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
53 * change the default memory attributes.
54 * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
55 * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
56 * 0x27FFFFFF) to use the
57 * background memory attributes.
58 */
59
60 /* Select Region 0 and set its base address to the M4 code bus start address. */
61 MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
62
63 /* Region 0 setting:
64 * 1) Disable Instruction Access;
65 * 2) AP = 011b, full access;
66 * 3) Non-shared device;
67 * 4) Region Not Shared;
68 * 5) Sub-Region 0,1 Disabled;
69 * 6) MPU Protection Region size = 512M byte;
70 * 7) Enable Region 0.
71 */
72 MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
73 (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
74
75 /*
76 * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
77 * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
78 * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
79 * region size,
80 * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
81 * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
82 * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
83 * needs.
84 */
85
86 /* Select Region 1 and set its base address to the DDR start address. */
87 MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
88
89 /* Region 1 setting:
90 * 1) Enable Instruction Access;
91 * 2) AP = 011b, full access;
92 * 3) Shared Device;
93 * 4) MPU Protection Region size = 1024M byte;
94 * 5) Enable Region 1.
95 */
96 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
97
98 /* Select Region 2 and set its base address to the DDR start address. */
99 MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
100
101 /* Region 2 setting:
102 * 1) Enable Instruction Access;
103 * 2) AP = 011b, full access;
104 * 3) Shared Device;
105 * 4) MPU Protection Region size = 1024M byte;
106 * 5) Enable Region 2.
107 */
108 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
109
110 while ((size >> i) > 0x1U)
111 {
112 i++;
113 }
114
115 /* If run on DDR, configure text and data section to be cacheable */
116 if (i != 0)
117 {
118 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
119 assert((size & (size - 1)) == 0);
120 assert(!(cacheStart % size));
121 assert(size == (uint32_t)(1 << i));
122 assert(i >= 5);
123
124 /* Select Region 3 and set its base address to the cache able region start address. */
125 MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
126
127 /* Region 3 setting:
128 * 1) Enable Instruction Access;
129 * 2) AP = 011b, full access;
130 * 3) Outer and inner Cacheable, write and read allocate;
131 * 4) Region Not Shared;
132 * 5) All Sub-Region Enabled;
133 * 6) MPU Protection Region size get from linker file;
134 * 7) Enable Region 3.
135 */
136 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
137 (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
138 }
139
140 /* Enable Privileged default memory map and the MPU. */
141 MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
142 /* Memory barriers to ensure subsequence data & instruction
143 * transfers using updated MPU settings.
144 */
145 __DSB();
146 __ISB();
147}
148
149void BOARD_RdcInit(void)
150{
151 /* Move M4 core to specific RDC domain 1 */
152 rdc_domain_assignment_t assignment = {0};
153
154 assignment.domainId = BOARD_DOMAIN_ID;
155 RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
156 /*
157 * The M4 core is running at domain 1, enable clock gate for Iomux and Gpio to run at domain 1.
158 */
159 CLOCK_EnableClock(kCLOCK_Gpio1);
160 CLOCK_EnableClock(kCLOCK_Gpio2);
161 CLOCK_EnableClock(kCLOCK_Gpio3);
162 CLOCK_EnableClock(kCLOCK_Gpio4);
163 CLOCK_EnableClock(kCLOCK_Gpio5);
164
165 CLOCK_EnableClock(kCLOCK_Iomux0);
166 CLOCK_EnableClock(kCLOCK_Iomux1);
167 CLOCK_EnableClock(kCLOCK_Iomux2);
168 CLOCK_EnableClock(kCLOCK_Iomux3);
169 CLOCK_EnableClock(kCLOCK_Iomux4);
170 /*
171 * The M4 core is running at domain 1, enable the PLL clock sources to domain 1.
172 */
173 CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enabel SysPLL1 to Domain 1 */
174 CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable SysPLL2 to Domain 1 */
175 CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable SysPLL3 to Domain 1 */
176 CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable AudioPLL1 to Domain 1 */
177 CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable AudioPLL2 to Domain 1 */
178 CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable VideoPLL1 to Domain 1 */
179}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/board.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/board.h
new file mode 100644
index 000000000..4a442bd06
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/board.h
@@ -0,0 +1,46 @@
1/*
2 * Copyright 2017 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _BOARD_H_
9#define _BOARD_H_
10#include "clock_config.h"
11#include "fsl_clock.h"
12/*******************************************************************************
13 * Definitions
14 ******************************************************************************/
15/*! @brief The board name */
16#define BOARD_NAME "MIMX8MQ-EVK"
17#define MANUFACTURER_NAME "NXP"
18#define BOARD_DOMAIN_ID (1)
19/* The UART to use for debug messages. */
20#define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_UART
21#define BOARD_DEBUG_UART_BAUDRATE 115200u
22#define BOARD_DEBUG_UART_BASEADDR UART2_BASE
23#define BOARD_DEBUG_UART_INSTANCE 2U
24#define BOARD_DEBUG_UART_CLK_FREQ \
25 CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) / \
26 (CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) / 10
27#define BOARD_UART_IRQ UART2_IRQn
28#define BOARD_UART_IRQ_HANDLER UART2_IRQHandler
29
30#if defined(__cplusplus)
31extern "C" {
32#endif /* __cplusplus */
33
34/*******************************************************************************
35 * API
36 ******************************************************************************/
37
38void BOARD_InitDebugConsole(void);
39void BOARD_InitMemory(void);
40void BOARD_RdcInit(void);
41
42#if defined(__cplusplus)
43}
44#endif /* __cplusplus */
45
46#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/clock_config.c
new file mode 100644
index 000000000..ef4a40577
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/clock_config.c
@@ -0,0 +1,145 @@
1/*
2 * Copyright 2017 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "clock_config.h"
10
11/*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14
15/* OSC 27M configuration */
16const osc_config_t g_osc27MConfig = {
17 .oscMode = kOSC_OscMode, .oscDiv = 1U,
18};
19
20/* OSC 25M configuration */
21const osc_config_t g_osc25MConfig = {
22 .oscMode = kOSC_OscMode, .oscDiv = 1U,
23};
24
25/* AUDIO PLL1 configuration */
26const ccm_analog_frac_pll_config_t g_audioPll1Config = {
27 .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */
28 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
29 .fractionDiv = 0U,
30 .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */
31 .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */
32};
33
34/* AUDIO PLL2 configuration */
35const ccm_analog_frac_pll_config_t g_audioPll2Config = {
36 .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */
37 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
38 .fractionDiv = 0U,
39 .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */
40 .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */
41};
42
43/* VIDEO PLL1 configuration */
44const ccm_analog_frac_pll_config_t g_videoPll1Config = {
45 .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */
46 .refDiv = 5U, /*!< PLL input = 25 / 5 = 5M */
47 .fractionDiv = 0U,
48 .intDiv = 64U, /*!< Integer and fractional Divider output = 5 * (1 + 64) * 8 = 2600MHZ */
49 .outDiv = 4U, /*!< Pll out frequency = 2600 / 4 = 650MHZ */
50};
51
52/* SYSTEM PLL1 configuration */
53const ccm_analog_sscg_pll_config_t g_sysPll1Config = {
54 .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */
55 .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */
56 .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */
57 .refDiv2 = 24U, /*!< PLL2 input = 1600 / 24 = 66.66MHZ */
58 .loopDivider2 = 12U, /*!< PLL2 output = 12 * 66.66 * 2 = 1600MHZ */
59 .outDiv = 1U, /*!< PLL output = 1600 / 2 / 1 = 800MHZ */
60};
61
62/* SYSTEM PLL2 configuration */
63const ccm_analog_sscg_pll_config_t g_sysPll2Config = {
64 .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */
65 .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */
66 .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */
67 .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */
68 .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */
69 .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */
70};
71
72/* SYSTEM PLL3 configuration */
73const ccm_analog_sscg_pll_config_t g_sysPll3Config = {
74 .refSel = kANALOG_PllRefOsc25M, /*!< PLL reference OSC25M */
75 .refDiv1 = 1U, /*!< PLL1 input = 25 / 1 = 25MHZ */
76 .loopDivider1 = 32U, /*!< PLL1 output = 25 * 32 * 2 = 1600MHZ */
77 .refDiv2 = 16U, /*!< PLL2 input = 1600 / 16 = 100MHZ */
78 .loopDivider2 = 10U, /*!< PLL2 output = 10 * 100 * 2 = 2000MHZ */
79 .outDiv = 1U, /*!< PLL output = 2000 / 2 / 1 = 1000MHZ */
80};
81
82/*******************************************************************************
83 * Variables
84 ******************************************************************************/
85
86/*******************************************************************************
87 * Code
88 ******************************************************************************/
89void BOARD_BootClockRUN(void)
90{
91 /* OSC configuration */
92 CLOCK_InitOSC25M(&g_osc25MConfig);
93 CLOCK_InitOSC27M(&g_osc27MConfig);
94
95 /* The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
96 * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
97 * would also do configuration on the SYSTEM PLL1 to 800Mhz and SYSTEM PLL2 to 1000Mhz by U-Boot.*/
98
99 /* switch AHB NOC root to 25M first in order to configure the SYSTEM PLL1. */
100 CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc25m);
101 CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc25m);
102 /* switch AXI M4 root to 25M first in order to configure the SYSTEM PLL2. */
103 CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc25m);
104 CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc25m);
105
106 CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
107 CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
108 CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 1000MHZ */
109
110 CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 650MHZ */
111 CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 650MHZ */
112 CLOCK_InitVideoPll1(&g_videoPll1Config); /* init VIDEO PLL1 run at 650MHZ */
113
114 CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3); /* switch cortex-m4 to SYSTEM PLL1 DIV3 */
115 CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
116
117 CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
118 CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
119
120 CLOCK_SetRootDivider(kCLOCK_RootAxi, 3U, 1U);
121 CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 = 266MHZ */
122
123 CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
124 CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
125
126 CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
127
128 /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
129 * enters the low power status.*/
130 // CLOCK_EnableClock(kCLOCK_Sim_m);
131 // CLOCK_EnableClock(kCLOCK_Sim_main);
132 // CLOCK_EnableClock(kCLOCK_Sim_s);
133 // CLOCK_EnableClock(kCLOCK_Sim_wakeup);
134 // CLOCK_EnableClock(kCLOCK_Debug);
135 // CLOCK_EnableClock(kCLOCK_Dram);
136 // CLOCK_EnableClock(kCLOCK_Sec_Debug);
137
138 /* Disable unused PLL */
139 CLOCK_DeinitSysPll3();
140 CLOCK_DeinitVideoPll1();
141 CLOCK_DeinitAudioPll1();
142 CLOCK_DeinitAudioPll2();
143 /* Update core clock */
144 SystemCoreClockUpdate();
145}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/clock_config.h
new file mode 100644
index 000000000..84bbbed41
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/clock_config.h
@@ -0,0 +1,27 @@
1/*
2 * Copyright 2017 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7#ifndef _CLOCK_CONFIG_H_
8#define _CLOCK_CONFIG_H_
9
10/*******************************************************************************
11 * Definitions
12 ******************************************************************************/
13
14/*******************************************************************************
15 * API
16 ******************************************************************************/
17#if defined(__cplusplus)
18extern "C" {
19#endif /* __cplusplus*/
20
21void BOARD_BootClockRUN(void);
22
23#if defined(__cplusplus)
24}
25#endif /* __cplusplus*/
26
27#endif /* _CLOCK_CONFIG_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/peripherals.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/peripherals.c
new file mode 100644
index 000000000..ead892540
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/peripherals.c
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2019 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
9!!GlobalInfo
10product: Peripherals v1.0
11 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
12
13/*******************************************************************************
14 * Included files
15 ******************************************************************************/
16#include "peripherals.h"
17
18/*******************************************************************************
19 * BOARD_InitBootPeripherals function
20 ******************************************************************************/
21void BOARD_InitBootPeripherals(void)
22{
23}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/peripherals.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/peripherals.h
new file mode 100644
index 000000000..92e132099
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/peripherals.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2019 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _PERIPHERALS_H_
9#define _PERIPHERALS_H_
10
11#if defined(__cplusplus)
12extern "C" {
13#endif /*_cplusplus. */
14 /*******************************************************************************
15 * BOARD_InitBootPeripherals function
16 ******************************************************************************/
17void BOARD_InitBootPeripherals(void);
18
19#if defined(__cplusplus)
20}
21#endif /*_cplusplus. */
22
23#endif /* _PERIPHERALS_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/pin_mux.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/pin_mux.c
new file mode 100644
index 000000000..48e0d18ef
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/pin_mux.c
@@ -0,0 +1,57 @@
1/*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13/*
14 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
15!!GlobalInfo
16product: Pins v5.0
17processor: MIMX8MD7xxxJZ
18mcu_data: ksdk2_0
19processor_version: 0.0.12
20 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
21 */
22
23#include "fsl_common.h"
24#include "fsl_iomuxc.h"
25#include "pin_mux.h"
26
27/* FUNCTION ************************************************************************************************************
28 *
29 * Function Name : BOARD_InitBootPins
30 * Description : Calls initialization functions.
31 *
32 * END ****************************************************************************************************************/
33void BOARD_InitBootPins(void)
34{
35 BOARD_InitPins();
36}
37
38/*
39 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
40BOARD_InitPins:
41- options: {callFromInitBoot: 'true', coreID: a53_0}
42- pin_list: []
43 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
44 */
45
46/* FUNCTION ************************************************************************************************************
47 *
48 * Function Name : BOARD_InitPins
49 * Description : Configures pin routing and optionally pin electrical features.
50 *
51 * END ****************************************************************************************************************/
52void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-A53[a53_0] */
53}
54
55/***********************************************************************************************************************
56 * EOF
57 **********************************************************************************************************************/
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/pin_mux.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/pin_mux.h
new file mode 100644
index 000000000..018d54f57
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MD7/project_template/pin_mux.h
@@ -0,0 +1,54 @@
1/*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _PIN_MUX_H_
9#define _PIN_MUX_H_
10
11#include "board.h"
12
13/***********************************************************************************************************************
14 * Definitions
15 **********************************************************************************************************************/
16
17/*!
18 * @addtogroup pin_mux
19 * @{
20 */
21
22/***********************************************************************************************************************
23 * API
24 **********************************************************************************************************************/
25
26#if defined(__cplusplus)
27extern "C" {
28#endif
29
30
31/*!
32 * @brief Calls initialization functions.
33 *
34 */
35void BOARD_InitBootPins(void);
36
37/*!
38 * @brief Configures pin routing and optionally pin electrical features.
39 *
40 */
41void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-A53[a53_0] */
42
43#if defined(__cplusplus)
44}
45#endif
46
47/*!
48 * @}
49 */
50#endif /* _PIN_MUX_H_ */
51
52/***********************************************************************************************************************
53 * EOF
54 **********************************************************************************************************************/
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 01:10:01 +0100