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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/MIMX8MM2_cm4.h65947
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/MIMX8MM2_cm4_features.h355
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/drivers/driver_reset.cmake14
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/drivers/fsl_clock.c792
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/drivers/fsl_clock.h1260
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/drivers/fsl_iomuxc.h656
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/drivers/fsl_memory.h130
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/fsl_device_registers.h35
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/gcc/MIMX8MM2xxxxx_cm4_ddr_ram.ld228
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/gcc/MIMX8MM2xxxxx_cm4_flash.ld228
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/gcc/MIMX8MM2xxxxx_cm4_ram.ld227
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/gcc/startup_MIMX8MM2_cm4.S751
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/mcuxpresso/startup_MIMX8MM2_cm4.c822
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/mcuxpresso/startup_MIMX8MM2_cm4.cpp821
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/project_template/board.c180
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/project_template/board.h48
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/project_template/clock_config.c119
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/project_template/clock_config.h27
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/project_template/peripherals.c24
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/project_template/peripherals.h24
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/project_template/pin_mux.c69
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/project_template/pin_mux.h56
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/system_MIMX8MM2_cm4.c245
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/system_MIMX8MM2_cm4.h117
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/template/RTE_Device.h48
25 files changed, 73223 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/MIMX8MM2_cm4.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/MIMX8MM2_cm4.h
new file mode 100644
index 000000000..8127cbdd8
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/MIMX8MM2_cm4.h
@@ -0,0 +1,65947 @@
1/*
2** ###################################################################
3** Processors: MIMX8MM2CVTKZ
4** MIMX8MM2DVTLZ
5**
6** Compilers: GNU C Compiler
7** IAR ANSI C/C++ Compiler for ARM
8** Keil ARM C/C++ Compiler
9**
10** Reference manual: MX8MMRM, Rev. 0, 02/2019
11** Version: rev. 4.0, 2019-02-18
12** Build: b190228
13**
14** Abstract:
15** CMSIS Peripheral Access Layer for MIMX8MM2_cm4
16**
17** Copyright 1997-2016 Freescale Semiconductor, Inc.
18** Copyright 2016-2019 NXP
19** All rights reserved.
20**
21** SPDX-License-Identifier: BSD-3-Clause
22**
23** http: www.nxp.com
24** mail: [email protected]
25**
26** Revisions:
27** - rev. 1.0 (2018-03-26)
28** Initial version.
29** - rev. 2.0 (2018-07-20)
30** Rev.A Header EAR
31** - rev. 3.0 (2018-10-24)
32** Rev.B Header PRC
33** - rev. 4.0 (2019-02-18)
34** Rev.0 Header RFP
35**
36** ###################################################################
37*/
38
39/*!
40 * @file MIMX8MM2_cm4.h
41 * @version 4.0
42 * @date 2019-02-18
43 * @brief CMSIS Peripheral Access Layer for MIMX8MM2_cm4
44 *
45 * CMSIS Peripheral Access Layer for MIMX8MM2_cm4
46 */
47
48#ifndef _MIMX8MM2_CM4_H_
49#define _MIMX8MM2_CM4_H_ /**< Symbol preventing repeated inclusion */
50
51/** Memory map major version (memory maps with equal major version number are
52 * compatible) */
53#define MCU_MEM_MAP_VERSION 0x0400U
54/** Memory map minor version */
55#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
56
57
58/* ----------------------------------------------------------------------------
59 -- Interrupt vector numbers
60 ---------------------------------------------------------------------------- */
61
62/*!
63 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
64 * @{
65 */
66
67/** Interrupt Number Definitions */
68#define NUMBER_OF_INT_VECTORS 144 /**< Number of interrupts in the Vector table */
69
70typedef enum IRQn {
71 /* Auxiliary constants */
72 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
73
74 /* Core interrupts */
75 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
76 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
77 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
78 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
79 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
80 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
81 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
82 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
83 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
84
85 /* Device specific interrupts */
86 GPR_IRQ_IRQn = 0, /**< GPR Interrupt. Used to notify cores on exception condition while boot. */
87 DAP_IRQn = 1, /**< DAP Interrupt */
88 SDMA1_IRQn = 2, /**< AND of all 48 SDMA1 interrupts (events) from all the channels */
89 GPU3D_IRQn = 3, /**< GPU3D Interrupt */
90 SNVS_IRQn = 4, /**< ON-OFF button press shorter than 5 seconds (pulse event) */
91 LCDIF_IRQn = 5, /**< LCDIF Interrupt */
92 SPDIF1_IRQn = 6, /**< SPDIF1 RZX/TX Interrupt */
93 VPU_G1_IRQn = 7, /**< VPU G1 Decoder Interrupt */
94 VPU_G2_IRQn = 8, /**< VPU G2 Decoder Interrupt */
95 QOS_IRQn = 9, /**< QOS interrupt */
96 WDOG3_IRQn = 10, /**< Watchdog Timer reset */
97 HS_CP1_IRQn = 11, /**< HS Interrupt Request */
98 APBHDMA_IRQn = 12, /**< GPMI operation channel 0-3 description complete interrupt */
99 Reserved29_IRQn = 13, /**< Reserved */
100 BCH_IRQn = 14, /**< BCH operation complete interrupt */
101 GPMI_IRQn = 15, /**< GPMI operation TIMEOUT ERROR interrupt */
102 CSI1_IRQn = 16, /**< CSI Interrupt */
103 MIPI_CSI1_IRQn = 17, /**< MIPI CSI Interrupt */
104 MIPI_DSI_IRQn = 18, /**< MIPI DSI Interrupt */
105 SNVS_Consolidated_IRQn = 19, /**< SRTC Consolidated Interrupt. Non TZ. */
106 SNVS_Security_IRQn = 20, /**< SRTC Security Interrupt. TZ. */
107 CSU_IRQn = 21, /**< CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted. */
108 USDHC1_IRQn = 22, /**< uSDHC1 Enhanced SDHC Interrupt Request */
109 USDHC2_IRQn = 23, /**< uSDHC2 Enhanced SDHC Interrupt Request */
110 USDHC3_IRQn = 24, /**< uSDHC3 Enhanced SDHC Interrupt Request */
111 GPU2D_IRQn = 25, /**< GPU2D Interrupt */
112 UART1_IRQn = 26, /**< UART-1 ORed interrupt */
113 UART2_IRQn = 27, /**< UART-2 ORed interrupt */
114 UART3_IRQn = 28, /**< UART-3 ORed interrupt */
115 UART4_IRQn = 29, /**< UART-4 ORed interrupt */
116 VPU_H1_IRQn = 30, /**< VPU H1 Encoder Interrupt */
117 ECSPI1_IRQn = 31, /**< ECSPI1 interrupt request line to the core. */
118 ECSPI2_IRQn = 32, /**< ECSPI2 interrupt request line to the core. */
119 ECSPI3_IRQn = 33, /**< ECSPI3 interrupt request line to the core. */
120 SDMA3_IRQn = 34, /**< AND of all 48 SDMA3 interrupts (events) from all the channels */
121 I2C1_IRQn = 35, /**< I2C-1 Interrupt */
122 I2C2_IRQn = 36, /**< I2C-2 Interrupt */
123 I2C3_IRQn = 37, /**< I2C-3 Interrupt */
124 I2C4_IRQn = 38, /**< I2C-4 Interrupt */
125 RDC_IRQn = 39, /**< RDC interrupt */
126 USB1_IRQn = 40, /**< USB1 Interrupt */
127 USB2_IRQn = 41, /**< USB1 Interrupt */
128 Reserved58_IRQn = 42, /**< Reserved interrupt */
129 Reserved59_IRQn = 43, /**< Reserved interrupt */
130 PDM_HWVAD_EVENT_IRQn = 44, /**< Digital Microphone interface voice activity detector event interrupt */
131 PDM_HWVAD_ERROR_IRQn = 45, /**< Digital Microphone interface voice activity detector error interrupt */
132 GPT6_IRQn = 46, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
133 SCTR_IRQ0_IRQn = 47, /**< System Counter Interrupt 0 */
134 SCTR_IRQ1_IRQn = 48, /**< System Counter Interrupt 1 */
135 TEMPMON_LOW_IRQn = 49, /**< TempSensor (Temperature low alarm). */
136 I2S3_IRQn = 50, /**< SAI3 Receive / Transmit Interrupt */
137 GPT5_IRQn = 51, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
138 GPT4_IRQn = 52, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
139 GPT3_IRQn = 53, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
140 GPT2_IRQn = 54, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
141 GPT1_IRQn = 55, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
142 GPIO1_INT7_IRQn = 56, /**< Active HIGH Interrupt from INT7 from GPIO */
143 GPIO1_INT6_IRQn = 57, /**< Active HIGH Interrupt from INT6 from GPIO */
144 GPIO1_INT5_IRQn = 58, /**< Active HIGH Interrupt from INT5 from GPIO */
145 GPIO1_INT4_IRQn = 59, /**< Active HIGH Interrupt from INT4 from GPIO */
146 GPIO1_INT3_IRQn = 60, /**< Active HIGH Interrupt from INT3 from GPIO */
147 GPIO1_INT2_IRQn = 61, /**< Active HIGH Interrupt from INT2 from GPIO */
148 GPIO1_INT1_IRQn = 62, /**< Active HIGH Interrupt from INT1 from GPIO */
149 GPIO1_INT0_IRQn = 63, /**< Active HIGH Interrupt from INT0 from GPIO */
150 GPIO1_Combined_0_15_IRQn = 64, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
151 GPIO1_Combined_16_31_IRQn = 65, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
152 GPIO2_Combined_0_15_IRQn = 66, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
153 GPIO2_Combined_16_31_IRQn = 67, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
154 GPIO3_Combined_0_15_IRQn = 68, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
155 GPIO3_Combined_16_31_IRQn = 69, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
156 GPIO4_Combined_0_15_IRQn = 70, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */
157 GPIO4_Combined_16_31_IRQn = 71, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */
158 GPIO5_Combined_0_15_IRQn = 72, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
159 GPIO5_Combined_16_31_IRQn = 73, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
160 Reserved90_IRQn = 74, /**< Reserved interrupt */
161 Reserved91_IRQn = 75, /**< Reserved interrupt */
162 Reserved92_IRQn = 76, /**< Reserved interrupt */
163 Reserved93_IRQn = 77, /**< Reserved interrupt */
164 WDOG1_IRQn = 78, /**< Watchdog Timer reset */
165 WDOG2_IRQn = 79, /**< Watchdog Timer reset */
166 Reserved96_IRQn = 80, /**< Reserved interrupt */
167 PWM1_IRQn = 81, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
168 PWM2_IRQn = 82, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
169 PWM3_IRQn = 83, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
170 PWM4_IRQn = 84, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
171 CCM_IRQ1_IRQn = 85, /**< CCM Interrupt Request 1 */
172 CCM_IRQ2_IRQn = 86, /**< CCM Interrupt Request 2 */
173 GPC_IRQn = 87, /**< GPC Interrupt Request 1 */
174 MU_A53_IRQn = 88, /**< Interrupt to A53 */
175 SRC_IRQn = 89, /**< SRC interrupt request */
176 I2S56_IRQn = 90, /**< SAI5/6 Receive / Transmit Interrupt */
177 RTIC_IRQn = 91, /**< RTIC Interrupt */
178 CPU_PerformanceUnit_IRQn = 92, /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n] */
179 CPU_CTI_Trigger_IRQn = 93, /**< CTI trigger outputs (internal: nCTIIRQ[n] */
180 SRC_Combined_IRQn = 94, /**< Combined CPU wdog interrupts (4x) out of SRC. */
181 I2S1_IRQn = 95, /**< SAI1 Receive / Transmit Interrupt */
182 I2S2_IRQn = 96, /**< SAI2 Receive / Transmit Interrupt */
183 MU_M4_IRQn = 97, /**< Interrupt to M4 */
184 DDR_PerformanceMonitor_IRQn = 98, /**< ddr Interrupt for performance monitor */
185 DDR_IRQn = 99, /**< ddr Interrupt */
186 Reserved116_IRQn = 100, /**< Reserved interrupt */
187 CPU_Error_AXI_IRQn = 101, /**< CPU Error indicator for AXI transaction with a write response error condition */
188 CPU_Error_L2RAM_IRQn = 102, /**< CPU Error indicator for L2 RAM double-bit ECC error */
189 SDMA2_IRQn = 103, /**< AND of all 48 SDMA2 interrupts (events) from all the channels */
190 SJC_IRQn = 104, /**< Interrupt triggered by SJC register */
191 CAAM_IRQ0_IRQn = 105, /**< CAAM interrupt queue for JQ */
192 CAAM_IRQ1_IRQn = 106, /**< CAAM interrupt queue for JQ */
193 QSPI_IRQn = 107, /**< QSPI Interrupt */
194 TZASC_IRQn = 108, /**< TZASC (PL380) interrupt */
195 PDM_EVENT_IRQn = 109, /**< Digital Microphone interface interrupt */
196 PDM_ERROR_IRQn = 110, /**< Digital Microphone interface error interrupt */
197 Reserved127_IRQn = 111, /**< Reserved interrupt */
198 PERFMON1_IRQn = 112, /**< General Interrupt */
199 PERFMON2_IRQn = 113, /**< General Interrupt */
200 CAAM_IRQ2_IRQn = 114, /**< CAAM interrupt queue for JQ */
201 CAAM_ERROR_IRQn = 115, /**< Recoverable error interrupt */
202 HS_CP0_IRQn = 116, /**< HS Interrupt Request */
203 Reserved133_IRQn = 117, /**< Reserved interrupt */
204 ENET_MAC0_Rx_Tx_Done1_IRQn = 118, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */
205 ENET_MAC0_Rx_Tx_Done2_IRQn = 119, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */
206 ENET_IRQn = 120, /**< MAC 0 IRQ */
207 ENET_1588_IRQn = 121, /**< MAC 0 1588 Timer Interrupt - synchronous */
208 PCIE_CTRL1_IRQ0_IRQn = 122, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
209 PCIE_CTRL1_IRQ1_IRQn = 123, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
210 PCIE_CTRL1_IRQ2_IRQn = 124, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
211 PCIE_CTRL1_IRQ3_IRQn = 125, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
212 Reserved142_IRQn = 126, /**< Reserved */
213 PCIE_CTRL1_IRQn = 127 /**< Channels [63:32] interrupts requests */
214} IRQn_Type;
215
216/*!
217 * @}
218 */ /* end of group Interrupt_vector_numbers */
219
220
221/* ----------------------------------------------------------------------------
222 -- Cortex M4 Core Configuration
223 ---------------------------------------------------------------------------- */
224
225/*!
226 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
227 * @{
228 */
229
230#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
231#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
232#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
233#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
234
235#include "core_cm4.h" /* Core Peripheral Access Layer */
236#include "system_MIMX8MM2_cm4.h" /* Device specific configuration file */
237
238/*!
239 * @}
240 */ /* end of group Cortex_Core_Configuration */
241
242
243/* ----------------------------------------------------------------------------
244 -- Mapping Information
245 ---------------------------------------------------------------------------- */
246
247/*!
248 * @addtogroup Mapping_Information Mapping Information
249 * @{
250 */
251
252/** Mapping Information */
253/*!
254 * @addtogroup iomuxc_pads
255 * @{ */
256
257/*******************************************************************************
258 * Definitions
259*******************************************************************************/
260
261/*!
262 * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
263 *
264 * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
265 */
266typedef enum _iomuxc_sw_mux_ctl_pad
267{
268 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
269 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
270 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
271 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
272 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
273 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
274 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
275 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
276 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
277 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
278 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
279 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
280 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
281 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
282 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
283 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
284 kIOMUXC_SW_MUX_CTL_PAD_ENET_MDC = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */
285 kIOMUXC_SW_MUX_CTL_PAD_ENET_MDIO = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */
286 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD3 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */
287 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD2 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */
288 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD1 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */
289 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD0 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */
290 kIOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */
291 kIOMUXC_SW_MUX_CTL_PAD_ENET_TXC = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */
292 kIOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */
293 kIOMUXC_SW_MUX_CTL_PAD_ENET_RXC = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */
294 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD0 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */
295 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD1 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */
296 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD2 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */
297 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD3 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */
298 kIOMUXC_SW_MUX_CTL_PAD_SD1_CLK = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */
299 kIOMUXC_SW_MUX_CTL_PAD_SD1_CMD = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */
300 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */
301 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */
302 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */
303 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */
304 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA4 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */
305 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA5 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */
306 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA6 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */
307 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA7 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */
308 kIOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */
309 kIOMUXC_SW_MUX_CTL_PAD_SD1_STROBE = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */
310 kIOMUXC_SW_MUX_CTL_PAD_SD2_CD_B = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */
311 kIOMUXC_SW_MUX_CTL_PAD_SD2_CLK = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */
312 kIOMUXC_SW_MUX_CTL_PAD_SD2_CMD = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */
313 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */
314 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */
315 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */
316 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */
317 kIOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */
318 kIOMUXC_SW_MUX_CTL_PAD_SD2_WP = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */
319 kIOMUXC_SW_MUX_CTL_PAD_NAND_ALE = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */
320 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */
321 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */
322 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */
323 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */
324 kIOMUXC_SW_MUX_CTL_PAD_NAND_CLE = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */
325 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */
326 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */
327 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */
328 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */
329 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */
330 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */
331 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */
332 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */
333 kIOMUXC_SW_MUX_CTL_PAD_NAND_DQS = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */
334 kIOMUXC_SW_MUX_CTL_PAD_NAND_RE_B = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */
335 kIOMUXC_SW_MUX_CTL_PAD_NAND_READY_B = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */
336 kIOMUXC_SW_MUX_CTL_PAD_NAND_WE_B = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */
337 kIOMUXC_SW_MUX_CTL_PAD_NAND_WP_B = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */
338 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */
339 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXC = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */
340 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */
341 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */
342 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */
343 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */
344 kIOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */
345 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXFS = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */
346 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXC = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */
347 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD0 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */
348 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD1 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */
349 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD2 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */
350 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD3 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */
351 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD4 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */
352 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD5 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */
353 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD6 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */
354 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD7 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */
355 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXFS = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */
356 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXC = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */
357 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD0 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */
358 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD1 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */
359 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD2 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */
360 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD3 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */
361 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD4 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */
362 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD5 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */
363 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD6 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */
364 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD7 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */
365 kIOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */
366 kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */
367 kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXC = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */
368 kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */
369 kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */
370 kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXC = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */
371 kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */
372 kIOMUXC_SW_MUX_CTL_PAD_SAI2_MCLK = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */
373 kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */
374 kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXC = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */
375 kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXD = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */
376 kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */
377 kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXC = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */
378 kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXD = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */
379 kIOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */
380 kIOMUXC_SW_MUX_CTL_PAD_SPDIF_TX = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */
381 kIOMUXC_SW_MUX_CTL_PAD_SPDIF_RX = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */
382 kIOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */
383 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */
384 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */
385 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */
386 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */
387 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */
388 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */
389 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */
390 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */
391 kIOMUXC_SW_MUX_CTL_PAD_I2C1_SCL = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */
392 kIOMUXC_SW_MUX_CTL_PAD_I2C1_SDA = 124U, /**< IOMUXC SW_MUX_CTL_PAD index */
393 kIOMUXC_SW_MUX_CTL_PAD_I2C2_SCL = 125U, /**< IOMUXC SW_MUX_CTL_PAD index */
394 kIOMUXC_SW_MUX_CTL_PAD_I2C2_SDA = 126U, /**< IOMUXC SW_MUX_CTL_PAD index */
395 kIOMUXC_SW_MUX_CTL_PAD_I2C3_SCL = 127U, /**< IOMUXC SW_MUX_CTL_PAD index */
396 kIOMUXC_SW_MUX_CTL_PAD_I2C3_SDA = 128U, /**< IOMUXC SW_MUX_CTL_PAD index */
397 kIOMUXC_SW_MUX_CTL_PAD_I2C4_SCL = 129U, /**< IOMUXC SW_MUX_CTL_PAD index */
398 kIOMUXC_SW_MUX_CTL_PAD_I2C4_SDA = 130U, /**< IOMUXC SW_MUX_CTL_PAD index */
399 kIOMUXC_SW_MUX_CTL_PAD_UART1_RXD = 131U, /**< IOMUXC SW_MUX_CTL_PAD index */
400 kIOMUXC_SW_MUX_CTL_PAD_UART1_TXD = 132U, /**< IOMUXC SW_MUX_CTL_PAD index */
401 kIOMUXC_SW_MUX_CTL_PAD_UART2_RXD = 133U, /**< IOMUXC SW_MUX_CTL_PAD index */
402 kIOMUXC_SW_MUX_CTL_PAD_UART2_TXD = 134U, /**< IOMUXC SW_MUX_CTL_PAD index */
403 kIOMUXC_SW_MUX_CTL_PAD_UART3_RXD = 135U, /**< IOMUXC SW_MUX_CTL_PAD index */
404 kIOMUXC_SW_MUX_CTL_PAD_UART3_TXD = 136U, /**< IOMUXC SW_MUX_CTL_PAD index */
405 kIOMUXC_SW_MUX_CTL_PAD_UART4_RXD = 137U, /**< IOMUXC SW_MUX_CTL_PAD index */
406 kIOMUXC_SW_MUX_CTL_PAD_UART4_TXD = 138U, /**< IOMUXC SW_MUX_CTL_PAD index */
407} iomuxc_sw_mux_ctl_pad_t;
408
409/*!
410 * @addtogroup iomuxc_pads
411 * @{ */
412
413/*******************************************************************************
414 * Definitions
415*******************************************************************************/
416
417/*!
418 * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
419 *
420 * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
421 */
422typedef enum _iomuxc_sw_pad_ctl_pad
423{
424 kIOMUXC_SW_PAD_CTL_PAD_TEST_MODE = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
425 kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
426 kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
427 kIOMUXC_SW_PAD_CTL_PAD_JTAG_MOD = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
428 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
429 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDI = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
430 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TMS = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */
431 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TCK = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */
432 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDO = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */
433 kIOMUXC_SW_PAD_CTL_PAD_RTC = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */
434 kIOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */
435 kIOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */
436 kIOMUXC_SW_PAD_CTL_PAD_ONOFF = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */
437 kIOMUXC_SW_PAD_CTL_PAD_POR_B = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */
438 kIOMUXC_SW_PAD_CTL_PAD_RTC_RESET_B = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */
439 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
440 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */
441 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */
442 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */
443 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */
444 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */
445 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */
446 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */
447 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */
448 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */
449 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */
450 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */
451 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */
452 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */
453 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */
454 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */
455 kIOMUXC_SW_PAD_CTL_PAD_ENET_MDC = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */
456 kIOMUXC_SW_PAD_CTL_PAD_ENET_MDIO = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */
457 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD3 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */
458 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD2 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */
459 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD1 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */
460 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD0 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */
461 kIOMUXC_SW_PAD_CTL_PAD_ENET_TX_CTL = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */
462 kIOMUXC_SW_PAD_CTL_PAD_ENET_TXC = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */
463 kIOMUXC_SW_PAD_CTL_PAD_ENET_RX_CTL = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */
464 kIOMUXC_SW_PAD_CTL_PAD_ENET_RXC = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */
465 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD0 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */
466 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD1 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */
467 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD2 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */
468 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD3 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */
469 kIOMUXC_SW_PAD_CTL_PAD_SD1_CLK = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */
470 kIOMUXC_SW_PAD_CTL_PAD_SD1_CMD = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */
471 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */
472 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */
473 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */
474 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */
475 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA4 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */
476 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA5 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */
477 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA6 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */
478 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA7 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */
479 kIOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */
480 kIOMUXC_SW_PAD_CTL_PAD_SD1_STROBE = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */
481 kIOMUXC_SW_PAD_CTL_PAD_SD2_CD_B = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */
482 kIOMUXC_SW_PAD_CTL_PAD_SD2_CLK = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */
483 kIOMUXC_SW_PAD_CTL_PAD_SD2_CMD = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */
484 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */
485 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */
486 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */
487 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */
488 kIOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */
489 kIOMUXC_SW_PAD_CTL_PAD_SD2_WP = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */
490 kIOMUXC_SW_PAD_CTL_PAD_NAND_ALE = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */
491 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */
492 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */
493 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE2_B = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */
494 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE3_B = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */
495 kIOMUXC_SW_PAD_CTL_PAD_NAND_CLE = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */
496 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */
497 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */
498 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */
499 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */
500 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */
501 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */
502 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */
503 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */
504 kIOMUXC_SW_PAD_CTL_PAD_NAND_DQS = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */
505 kIOMUXC_SW_PAD_CTL_PAD_NAND_RE_B = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */
506 kIOMUXC_SW_PAD_CTL_PAD_NAND_READY_B = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */
507 kIOMUXC_SW_PAD_CTL_PAD_NAND_WE_B = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */
508 kIOMUXC_SW_PAD_CTL_PAD_NAND_WP_B = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */
509 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXFS = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */
510 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXC = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */
511 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD0 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */
512 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD1 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */
513 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD2 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */
514 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD3 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */
515 kIOMUXC_SW_PAD_CTL_PAD_SAI5_MCLK = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */
516 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXFS = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */
517 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXC = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */
518 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD0 = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */
519 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD1 = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */
520 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD2 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */
521 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD3 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */
522 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD4 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */
523 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD5 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */
524 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD6 = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */
525 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD7 = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */
526 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXFS = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */
527 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXC = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */
528 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD0 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */
529 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD1 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */
530 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD2 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */
531 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD3 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */
532 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD4 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */
533 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD5 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */
534 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD6 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */
535 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD7 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */
536 kIOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK = 112U, /**< IOMUXC SW_PAD_CTL_PAD index */
537 kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXFS = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */
538 kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXC = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */
539 kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXD0 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */
540 kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXFS = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */
541 kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXC = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */
542 kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXD0 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */
543 kIOMUXC_SW_PAD_CTL_PAD_SAI2_MCLK = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */
544 kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXFS = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */
545 kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXC = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */
546 kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXD = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */
547 kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXFS = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */
548 kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXC = 124U, /**< IOMUXC SW_PAD_CTL_PAD index */
549 kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXD = 125U, /**< IOMUXC SW_PAD_CTL_PAD index */
550 kIOMUXC_SW_PAD_CTL_PAD_SAI3_MCLK = 126U, /**< IOMUXC SW_PAD_CTL_PAD index */
551 kIOMUXC_SW_PAD_CTL_PAD_SPDIF_TX = 127U, /**< IOMUXC SW_PAD_CTL_PAD index */
552 kIOMUXC_SW_PAD_CTL_PAD_SPDIF_RX = 128U, /**< IOMUXC SW_PAD_CTL_PAD index */
553 kIOMUXC_SW_PAD_CTL_PAD_SPDIF_EXT_CLK = 129U, /**< IOMUXC SW_PAD_CTL_PAD index */
554 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK = 130U, /**< IOMUXC SW_PAD_CTL_PAD index */
555 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI = 131U, /**< IOMUXC SW_PAD_CTL_PAD index */
556 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO = 132U, /**< IOMUXC SW_PAD_CTL_PAD index */
557 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0 = 133U, /**< IOMUXC SW_PAD_CTL_PAD index */
558 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK = 134U, /**< IOMUXC SW_PAD_CTL_PAD index */
559 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI = 135U, /**< IOMUXC SW_PAD_CTL_PAD index */
560 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO = 136U, /**< IOMUXC SW_PAD_CTL_PAD index */
561 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0 = 137U, /**< IOMUXC SW_PAD_CTL_PAD index */
562 kIOMUXC_SW_PAD_CTL_PAD_I2C1_SCL = 138U, /**< IOMUXC SW_PAD_CTL_PAD index */
563 kIOMUXC_SW_PAD_CTL_PAD_I2C1_SDA = 139U, /**< IOMUXC SW_PAD_CTL_PAD index */
564 kIOMUXC_SW_PAD_CTL_PAD_I2C2_SCL = 140U, /**< IOMUXC SW_PAD_CTL_PAD index */
565 kIOMUXC_SW_PAD_CTL_PAD_I2C2_SDA = 141U, /**< IOMUXC SW_PAD_CTL_PAD index */
566 kIOMUXC_SW_PAD_CTL_PAD_I2C3_SCL = 142U, /**< IOMUXC SW_PAD_CTL_PAD index */
567 kIOMUXC_SW_PAD_CTL_PAD_I2C3_SDA = 143U, /**< IOMUXC SW_PAD_CTL_PAD index */
568 kIOMUXC_SW_PAD_CTL_PAD_I2C4_SCL = 144U, /**< IOMUXC SW_PAD_CTL_PAD index */
569 kIOMUXC_SW_PAD_CTL_PAD_I2C4_SDA = 145U, /**< IOMUXC SW_PAD_CTL_PAD index */
570 kIOMUXC_SW_PAD_CTL_PAD_UART1_RXD = 146U, /**< IOMUXC SW_PAD_CTL_PAD index */
571 kIOMUXC_SW_PAD_CTL_PAD_UART1_TXD = 147U, /**< IOMUXC SW_PAD_CTL_PAD index */
572 kIOMUXC_SW_PAD_CTL_PAD_UART2_RXD = 148U, /**< IOMUXC SW_PAD_CTL_PAD index */
573 kIOMUXC_SW_PAD_CTL_PAD_UART2_TXD = 149U, /**< IOMUXC SW_PAD_CTL_PAD index */
574 kIOMUXC_SW_PAD_CTL_PAD_UART3_RXD = 150U, /**< IOMUXC SW_PAD_CTL_PAD index */
575 kIOMUXC_SW_PAD_CTL_PAD_UART3_TXD = 151U, /**< IOMUXC SW_PAD_CTL_PAD index */
576 kIOMUXC_SW_PAD_CTL_PAD_UART4_RXD = 152U, /**< IOMUXC SW_PAD_CTL_PAD index */
577 kIOMUXC_SW_PAD_CTL_PAD_UART4_TXD = 153U, /**< IOMUXC SW_PAD_CTL_PAD index */
578} iomuxc_sw_pad_ctl_pad_t;
579
580/* @} */
581
582/*!
583 * @brief Enumeration for the IOMUXC select input
584 *
585 * Defines the enumeration for the IOMUXC select input collections.
586 */
587typedef enum _iomuxc_select_input
588{
589 kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 0U, /**< IOMUXC select input index */
590 kIOMUXC_ENET1_MDIO_SELECT_INPUT = 1U, /**< IOMUXC select input index */
591 kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 2U, /**< IOMUXC select input index */
592 kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 3U, /**< IOMUXC select input index */
593 kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 4U, /**< IOMUXC select input index */
594 kIOMUXC_SAI5_RX_BCLK_SELECT_INPUT = 5U, /**< IOMUXC select input index */
595 kIOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 = 6U, /**< IOMUXC select input index */
596 kIOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 = 7U, /**< IOMUXC select input index */
597 kIOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 = 8U, /**< IOMUXC select input index */
598 kIOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 = 9U, /**< IOMUXC select input index */
599 kIOMUXC_SAI5_RX_SYNC_SELECT_INPUT = 10U, /**< IOMUXC select input index */
600 kIOMUXC_SAI5_TX_BCLK_SELECT_INPUT = 11U, /**< IOMUXC select input index */
601 kIOMUXC_SAI5_TX_SYNC_SELECT_INPUT = 12U, /**< IOMUXC select input index */
602 kIOMUXC_UART1_RTS_B_SELECT_INPUT = 13U, /**< IOMUXC select input index */
603 kIOMUXC_UART1_RXD_SELECT_INPUT = 14U, /**< IOMUXC select input index */
604 kIOMUXC_UART2_RTS_B_SELECT_INPUT = 15U, /**< IOMUXC select input index */
605 kIOMUXC_UART2_RXD_SELECT_INPUT = 16U, /**< IOMUXC select input index */
606 kIOMUXC_UART3_RTS_B_SELECT_INPUT = 17U, /**< IOMUXC select input index */
607 kIOMUXC_UART3_RXD_SELECT_INPUT = 18U, /**< IOMUXC select input index */
608 kIOMUXC_UART4_RTS_B_SELECT_INPUT = 19U, /**< IOMUXC select input index */
609 kIOMUXC_UART4_RXD_SELECT_INPUT = 20U, /**< IOMUXC select input index */
610 kIOMUXC_SAI6_RX_BCLK_SELECT_INPUT = 21U, /**< IOMUXC select input index */
611 kIOMUXC_SAI6_RX_DATA_SELECT_INPUT_0 = 22U, /**< IOMUXC select input index */
612 kIOMUXC_SAI6_RX_SYNC_SELECT_INPUT = 23U, /**< IOMUXC select input index */
613 kIOMUXC_SAI6_TX_BCLK_SELECT_INPUT = 24U, /**< IOMUXC select input index */
614 kIOMUXC_SAI6_TX_SYNC_SELECT_INPUT = 25U, /**< IOMUXC select input index */
615 kIOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT = 26U, /**< IOMUXC select input index */
616 kIOMUXC_SAI5_MCLK_SELECT_INPUT = 28U, /**< IOMUXC select input index */
617 kIOMUXC_SAI6_MCLK_SELECT_INPUT = 29U, /**< IOMUXC select input index */
618 kIOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 = 30U, /**< IOMUXC select input index */
619 kIOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 = 31U, /**< IOMUXC select input index */
620 kIOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 = 32U, /**< IOMUXC select input index */
621 kIOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 = 33U, /**< IOMUXC select input index */
622 kIOMUXC_USDHC3_CD_B_SELECT_INPUT = 34U, /**< IOMUXC select input index */
623 kIOMUXC_USDHC3_WP_SELECT_INPUT = 35U, /**< IOMUXC select input index */
624} iomuxc_select_input_t;
625
626/*!
627 * @addtogroup rdc_mapping
628 * @{
629 */
630
631/*******************************************************************************
632 * Definitions
633 ******************************************************************************/
634
635/*!
636 * @brief Structure for the RDC mapping
637 *
638 * Defines the structure for the RDC resource collections.
639 */
640
641typedef enum _rdc_master
642{
643 kRDC_Master_A53 = 0U, /**< ARM Cortex-A53 RDC Master */
644 kRDC_Master_M4 = 1U, /**< ARM Cortex-M4 RDC Master */
645 kRDC_Master_PCIE_CTRL1 = 2U, /**< PCIE CTRL1 RDC Master */
646 kRDC_Master_SDMA3_PERIPH = 3U, /**< SDMA3 PERIPHERAL RDC Master */
647 kRDC_Master_VPU = 4U, /**< VPU RDC Master */
648 kRDC_Master_LCDIF = 5U, /**< LCDIF RDC Master */
649 kRDC_Master_CSI = 6U, /**< CSI PORT RDC Master */
650 kRDC_Master_SDMA3_BURST = 7U, /**< SDMA3 BURST RDC Master */
651 kRDC_Master_Coresight = 8U, /**< CORESIGHT RDC Master */
652 kRDC_Master_DAP = 9U, /**< DAP RDC Master */
653 kRDC_Master_CAAM = 10U, /**< CAAM RDC Master */
654 kRDC_Master_SDMA1_PERIPH = 11U, /**< SDMA1 PERIPHERAL RDC Master */
655 kRDC_Master_SDMA1_BURST = 12U, /**< SDMA1 BURST RDC Master */
656 kRDC_Master_APBHDMA = 13U, /**< APBH DMA RDC Master */
657 kRDC_Master_RAWNAND = 14U, /**< RAW NAND RDC Master */
658 kRDC_Master_USDHC1 = 15U, /**< USDHC1 RDC Master */
659 kRDC_Master_USDHC2 = 16U, /**< USDHC2 RDC Master */
660 kRDC_Master_USDHC3 = 17U, /**< USDHC3 RDC Master */
661 kRDC_Master_GPU = 18U, /**< GPU RDC Master */
662 kRDC_Master_USB1 = 19U, /**< USB1 RDC Master */
663 kRDC_Master_USB2 = 20U, /**< USB2 RDC Master */
664 kRDC_Master_TESTPORT = 21U, /**< TESTPORT RDC Master */
665 kRDC_Master_ENET1TX = 22U, /**< ENET1 TX RDC Master */
666 kRDC_Master_ENET1RX = 23U, /**< ENET1 RX RDC Master */
667 kRDC_Master_SDMA2_PERIPH = 24U, /**< SDMA2 PERIPH RDC Master */
668 kRDC_Master_SDMA2_BURST = 24U, /**< SDMA2 BURST RDC Master */
669 kRDC_Master_SDMA2_SPBA2 = 24U, /**< SDMA2 to SPBA2 RDC Master */
670 kRDC_Master_SDMA3_SPBA2 = 25U, /**< SDMA3 to SPBA2 RDC Master */
671 kRDC_Master_SDMA1_SPBA1 = 26U, /**< SDMA1 to SPBA1 RDC Master */
672} rdc_master_t;
673
674typedef enum _rdc_mem
675{
676 kRDC_Mem_MRC0_0 = 0U, /**< MMDC/DRAM. Region resolution 4KB. */
677 kRDC_Mem_MRC0_1 = 1U,
678 kRDC_Mem_MRC0_2 = 2U,
679 kRDC_Mem_MRC0_3 = 3U,
680 kRDC_Mem_MRC0_4 = 4U,
681 kRDC_Mem_MRC0_5 = 5U,
682 kRDC_Mem_MRC0_6 = 6U,
683 kRDC_Mem_MRC0_7 = 7U,
684 kRDC_Mem_MRC1_0 = 8U, /**< QSPI. Region resolution 4KB. */
685 kRDC_Mem_MRC1_1 = 9U,
686 kRDC_Mem_MRC1_2 = 10U,
687 kRDC_Mem_MRC1_3 = 11U,
688 kRDC_Mem_MRC1_4 = 12U,
689 kRDC_Mem_MRC1_5 = 13U,
690 kRDC_Mem_MRC1_6 = 14U,
691 kRDC_Mem_MRC1_7 = 15U,
692 kRDC_Mem_MRC2_0 = 16U, /**< PCIE1. Region resolution 4KB. */
693 kRDC_Mem_MRC2_1 = 17U,
694 kRDC_Mem_MRC2_2 = 18U,
695 kRDC_Mem_MRC2_3 = 19U,
696 kRDC_Mem_MRC2_4 = 20U,
697 kRDC_Mem_MRC2_5 = 21U,
698 kRDC_Mem_MRC2_6 = 22U,
699 kRDC_Mem_MRC2_7 = 23U,
700 kRDC_Mem_MRC3_0 = 24U, /**< OCRAM. Region resolution 128B. */
701 kRDC_Mem_MRC3_1 = 25U,
702 kRDC_Mem_MRC3_2 = 26U,
703 kRDC_Mem_MRC3_3 = 27U,
704 kRDC_Mem_MRC3_4 = 28U,
705 kRDC_Mem_MRC4_0 = 29U, /**< OCRAM_S. Region resolution 128B. */
706 kRDC_Mem_MRC4_1 = 30U,
707 kRDC_Mem_MRC4_2 = 31U,
708 kRDC_Mem_MRC4_3 = 32U,
709 kRDC_Mem_MRC4_4 = 33U,
710 kRDC_Mem_MRC5_0 = 34U, /**< TCM. Region resolution 128B. */
711 kRDC_Mem_MRC5_1 = 35U,
712 kRDC_Mem_MRC5_2 = 36U,
713 kRDC_Mem_MRC5_3 = 37U,
714 kRDC_Mem_MRC5_4 = 38U,
715 kRDC_Mem_MRC6_0 = 39U, /**< GIC. Region resolution 4KB. */
716 kRDC_Mem_MRC6_1 = 40U,
717 kRDC_Mem_MRC6_2 = 41U,
718 kRDC_Mem_MRC6_3 = 42U,
719 kRDC_Mem_MRC7_0 = 43U, /**< GPU. Region resolution 4KB. */
720 kRDC_Mem_MRC7_1 = 44U,
721 kRDC_Mem_MRC7_2 = 45U,
722 kRDC_Mem_MRC7_3 = 46U,
723 kRDC_Mem_MRC8_4 = 47U,
724 kRDC_Mem_MRC8_5 = 48U,
725 kRDC_Mem_MRC8_6 = 49U,
726 kRDC_Mem_MRC8_7 = 50U,
727 kRDC_Mem_MRC9_0 = 51U, /**< VPU(Decoder). Region resolution 4KB. */
728 kRDC_Mem_MRC9_1 = 52U,
729 kRDC_Mem_MRC9_2 = 53U,
730 kRDC_Mem_MRC9_3 = 54U,
731 kRDC_Mem_MRC10_0 = 55U, /**< DEBUG(DAP). Region resolution 4KB. */
732 kRDC_Mem_MRC10_1 = 56U,
733 kRDC_Mem_MRC10_2 = 57U,
734 kRDC_Mem_MRC10_3 = 58U,
735 kRDC_Mem_MRC11_0 = 59U, /**< DDRC(REG). Region resolution 4KB. */
736 kRDC_Mem_MRC11_1 = 60U,
737 kRDC_Mem_MRC11_2 = 61U,
738 kRDC_Mem_MRC11_3 = 62U,
739 kRDC_Mem_MRC11_4 = 63U,
740} rdc_mem_t;
741
742typedef enum _rdc_periph
743{
744 kRDC_Periph_GPIO1 = 0U, /**< GPIO1 RDC Peripheral */
745 kRDC_Periph_GPIO2 = 1U, /**< GPIO2 RDC Peripheral */
746 kRDC_Periph_GPIO3 = 2U, /**< GPIO3 RDC Peripheral */
747 kRDC_Periph_GPIO4 = 3U, /**< GPIO4 RDC Peripheral */
748 kRDC_Periph_GPIO5 = 4U, /**< GPIO5 RDC Peripheral */
749 kRDC_Periph_ANA_TSENSOR = 6U, /**< ANA_TSENSOR RDC Peripheral */
750 kRDC_Periph_ANA_OSC = 7U, /**< ANA_OSC RDC Peripheral */
751 kRDC_Periph_WDOG1 = 8U, /**< WDOG1 RDC Peripheral */
752 kRDC_Periph_WDOG2 = 9U, /**< WDOG2 RDC Peripheral */
753 kRDC_Periph_WDOG3 = 10U, /**< WDOG3 RDC Peripheral */
754 kRDC_Periph_SDMA3 = 11U, /**< SDMA3 RDC Peripheral */
755 kRDC_Periph_SDMA2 = 12U, /**< SDMA2 RDC Peripheral */
756 kRDC_Periph_GPT1 = 13U, /**< GPT1 RDC Peripheral */
757 kRDC_Periph_GPT2 = 14U, /**< GPT2 RDC Peripheral */
758 kRDC_Periph_GPT3 = 15U, /**< GPT3 RDC Peripheral */
759 kRDC_Periph_ROMCP = 17U, /**< ROMCP RDC Peripheral */
760 kRDC_Periph_IOMUXC = 19U, /**< IOMUXC RDC Peripheral */
761 kRDC_Periph_IOMUXC_GPR = 20U, /**< IOMUXC_GPR RDC Peripheral */
762 kRDC_Periph_OCOTP_CTRL = 21U, /**< OCOTP_CTRL RDC Peripheral */
763 kRDC_Periph_ANA_PLL = 22U, /**< ANA_PLL RDC Peripheral */
764 kRDC_Periph_SNVS_HP = 23U, /**< SNVS_HP GPR RDC Peripheral */
765 kRDC_Periph_CCM = 24U, /**< CCM RDC Peripheral */
766 kRDC_Periph_SRC = 25U, /**< SRC RDC Peripheral */
767 kRDC_Periph_GPC = 26U, /**< GPC RDC Peripheral */
768 kRDC_Periph_SEMAPHORE1 = 27U, /**< SEMAPHORE1 RDC Peripheral */
769 kRDC_Periph_SEMAPHORE2 = 28U, /**< SEMAPHORE2 RDC Peripheral */
770 kRDC_Periph_RDC = 29U, /**< RDC RDC Peripheral */
771 kRDC_Periph_CSU = 30U, /**< CSU RDC Peripheral */
772 kRDC_Periph_LCDIF = 32U, /**< LCDIF RDC Peripheral */
773 kRDC_Periph_MIPI_DSI = 33U, /**< MIPI_DSI RDC Peripheral */
774 kRDC_Periph_CSI = 34U, /**< CSI RDC Peripheral */
775 kRDC_Periph_MIPI_CSI = 35U, /**< MIPI_CSI RDC Peripheral */
776 kRDC_Periph_USB1 = 36U, /**< USB1 RDC Peripheral */
777 kRDC_Periph_PWM1 = 38U, /**< PWM1 RDC Peripheral */
778 kRDC_Periph_PWM2 = 39U, /**< PWM2 RDC Peripheral */
779 kRDC_Periph_PWM3 = 40U, /**< PWM3 RDC Peripheral */
780 kRDC_Periph_PWM4 = 41U, /**< PWM4 RDC Peripheral */
781 kRDC_Periph_SYS_COUNTER_RD = 42U, /**< System counter read RDC Peripheral */
782 kRDC_Periph_SYS_COUNTER_CMP = 43U, /**< System counter compare RDC Peripheral */
783 kRDC_Periph_SYS_COUNTER_CTRL = 44U, /**< System counter control RDC Peripheral */
784 kRDC_Periph_GPT6 = 46U, /**< GPT6 RDC Peripheral */
785 kRDC_Periph_GPT5 = 47U, /**< GPT5 RDC Peripheral */
786 kRDC_Periph_GPT4 = 48U, /**< GPT4 RDC Peripheral */
787 kRDC_Periph_TZASC = 56U, /**< TZASC RDC Peripheral */
788 kRDC_Periph_USB2 = 59U, /**< USB2 RDC Peripheral */
789 kRDC_Periph_PERFMON1 = 60U, /**< PERFMON1 RDC Peripheral */
790 kRDC_Periph_PERFMON2 = 61U, /**< PERFMON2 RDC Peripheral */
791 kRDC_Periph_PLATFORM_CTRL = 62U, /**< PLATFORM_CTRL RDC Peripheral */
792 kRDC_Periph_QOSC = 63U, /**< QOSC RDC Peripheral */
793 kRDC_Periph_I2C1 = 66U, /**< I2C1 RDC Peripheral */
794 kRDC_Periph_I2C2 = 67U, /**< I2C2 RDC Peripheral */
795 kRDC_Periph_I2C3 = 68U, /**< I2C3 RDC Peripheral */
796 kRDC_Periph_I2C4 = 69U, /**< I2C4 RDC Peripheral */
797 kRDC_Periph_UART4 = 70U, /**< UART4 RDC Peripheral */
798 kRDC_Periph_MU_A = 74U, /**< MU_A RDC Peripheral */
799 kRDC_Periph_MU_B = 75U, /**< MU_B RDC Peripheral */
800 kRDC_Periph_SEMAPHORE_HS = 76U, /**< SEMAPHORE_HS RDC Peripheral */
801 kRDC_Periph_SAI1 = 78U, /**< SAI1 RDC Peripheral */
802 kRDC_Periph_SAI2_ACCESS = 79U, /**< SAI2 RDC Peripheral Access Control */
803 kRDC_Periph_SAI3_ACCESS = 80U, /**< SAI3 RDC Peripheral Access Control */
804 kRDC_Periph_SAI6_LPM = 80U, /**< SAI6 RDC Low Power Mode Control */
805 kRDC_Periph_SAI5_LPM = 81U, /**< SAI5 RDC Low Power Mode Control */
806 kRDC_Periph_SAI5_ACCESS = 82U, /**< SAI5 RDC Peripheral Access Control */
807 kRDC_Periph_SAI6_ACCESS = 83U, /**< SAI6 RDC Peripheral Access Control */
808 kRDC_Periph_USDHC1 = 84U, /**< USDHC1 RDC Peripheral */
809 kRDC_Periph_USDHC2 = 85U, /**< USDHC2 RDC Peripheral */
810 kRDC_Periph_USDHC3 = 86U, /**< USDHC3 RDC Peripheral */
811 kRDC_Periph_PCIE_PHY1 = 88U, /**< PCIE_PHY1 RDC Peripheral */
812 kRDC_Periph_SPBA2 = 90U, /**< SPBA2 RDC Peripheral */
813 kRDC_Periph_QSPI = 91U, /**< QSPI RDC Peripheral */
814 kRDC_Periph_SDMA1 = 93U, /**< SDMA1 RDC Peripheral */
815 kRDC_Periph_ENET1 = 94U, /**< ENET1 RDC Peripheral */
816 kRDC_Periph_SPDIF1 = 97U, /**< SPDIF1 RDC Peripheral */
817 kRDC_Periph_ECSPI1 = 98U, /**< ECSPI1 RDC Peripheral */
818 kRDC_Periph_ECSPI2 = 99U, /**< ECSPI2 RDC Peripheral */
819 kRDC_Periph_ECSPI3 = 100U, /**< ECSPI3 RDC Peripheral */
820 kRDC_Periph_MICFIL = 101U, /**< MICFIL RDC Peripheral */
821 kRDC_Periph_UART1 = 102U, /**< UART1 RDC Peripheral */
822 kRDC_Periph_UART3 = 104U, /**< UART3 RDC Peripheral */
823 kRDC_Periph_UART2 = 105U, /**< UART2 RDC Peripheral */
824 kRDC_Periph_SPDIF2 = 106U, /**< SPDIF2 RDC Peripheral */
825 kRDC_Periph_SAI2_LPM = 107U, /**< SAI2 RDC Low Power Mode Control */
826 kRDC_Periph_SAI3_LPM = 108U, /**< SAI3 RDC Low Power Mode Control */
827 kRDC_Periph_SPBA1 = 111U, /**< SPBA1 RDC Peripheral */
828 kRDC_Periph_CAAM = 114U, /**< CAAM RDC Peripheral */
829} rdc_periph_t;
830
831/* @} */
832
833
834/*!
835 * @}
836 */ /* end of group Mapping_Information */
837
838
839/* ----------------------------------------------------------------------------
840 -- Device Peripheral Access Layer
841 ---------------------------------------------------------------------------- */
842
843/*!
844 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
845 * @{
846 */
847
848
849/*
850** Start of section using anonymous unions
851*/
852
853#if defined(__ARMCC_VERSION)
854 #if (__ARMCC_VERSION >= 6010050)
855 #pragma clang diagnostic push
856 #else
857 #pragma push
858 #pragma anon_unions
859 #endif
860#elif defined(__GNUC__)
861 /* anonymous unions are enabled by default */
862#elif defined(__IAR_SYSTEMS_ICC__)
863 #pragma language=extended
864#else
865 #error Not supported compiler type
866#endif
867
868/* ----------------------------------------------------------------------------
869 -- AIPSTZ Peripheral Access Layer
870 ---------------------------------------------------------------------------- */
871
872/*!
873 * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
874 * @{
875 */
876
877/** AIPSTZ - Register Layout Typedef */
878typedef struct {
879 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */
880 uint8_t RESERVED_0[60];
881 __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */
882 __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */
883 __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */
884 __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */
885 __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */
886} AIPSTZ_Type;
887
888/* ----------------------------------------------------------------------------
889 -- AIPSTZ Register Masks
890 ---------------------------------------------------------------------------- */
891
892/*!
893 * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
894 * @{
895 */
896
897/*! @name MPR - Master Priviledge Registers */
898/*! @{ */
899#define AIPSTZ_MPR_MPROT5_MASK (0xF00U)
900#define AIPSTZ_MPR_MPROT5_SHIFT (8U)
901/*! MPROT5
902 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
903 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
904 * 0bxx0x..This master is not trusted for write accesses.
905 * 0bxx1x..This master is trusted for write accesses.
906 * 0bx0xx..This master is not trusted for read accesses.
907 * 0bx1xx..This master is trusted for read accesses.
908 * 0b1xxx..Write accesses from this master are allowed to be buffered
909 */
910#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
911#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
912#define AIPSTZ_MPR_MPROT3_SHIFT (16U)
913/*! MPROT3
914 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
915 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
916 * 0bxx0x..This master is not trusted for write accesses.
917 * 0bxx1x..This master is trusted for write accesses.
918 * 0bx0xx..This master is not trusted for read accesses.
919 * 0bx1xx..This master is trusted for read accesses.
920 * 0b1xxx..Write accesses from this master are allowed to be buffered
921 */
922#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
923#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
924#define AIPSTZ_MPR_MPROT2_SHIFT (20U)
925/*! MPROT2
926 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
927 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
928 * 0bxx0x..This master is not trusted for write accesses.
929 * 0bxx1x..This master is trusted for write accesses.
930 * 0bx0xx..This master is not trusted for read accesses.
931 * 0bx1xx..This master is trusted for read accesses.
932 * 0b1xxx..Write accesses from this master are allowed to be buffered
933 */
934#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
935#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
936#define AIPSTZ_MPR_MPROT1_SHIFT (24U)
937/*! MPROT1
938 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
939 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
940 * 0bxx0x..This master is not trusted for write accesses.
941 * 0bxx1x..This master is trusted for write accesses.
942 * 0bx0xx..This master is not trusted for read accesses.
943 * 0bx1xx..This master is trusted for read accesses.
944 * 0b1xxx..Write accesses from this master are allowed to be buffered
945 */
946#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
947#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
948#define AIPSTZ_MPR_MPROT0_SHIFT (28U)
949/*! MPROT0
950 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
951 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
952 * 0bxx0x..This master is not trusted for write accesses.
953 * 0bxx1x..This master is trusted for write accesses.
954 * 0bx0xx..This master is not trusted for read accesses.
955 * 0bx1xx..This master is trusted for read accesses.
956 * 0b1xxx..Write accesses from this master are allowed to be buffered
957 */
958#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
959/*! @} */
960
961/*! @name OPACR - Off-Platform Peripheral Access Control Registers */
962/*! @{ */
963#define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
964#define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
965/*! OPAC7
966 * 0bxxx0..Accesses from an untrusted master are allowed.
967 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
968 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
969 * 0bxx0x..This peripheral allows write accesses.
970 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
971 * error response and no peripheral access is initiated on the IPS bus.
972 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
973 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
974 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
975 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
976 * on the IPS bus.
977 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
978 */
979#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
980#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
981#define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
982/*! OPAC6
983 * 0bxxx0..Accesses from an untrusted master are allowed.
984 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
985 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
986 * 0bxx0x..This peripheral allows write accesses.
987 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
988 * error response and no peripheral access is initiated on the IPS bus.
989 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
990 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
991 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
992 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
993 * on the IPS bus.
994 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
995 */
996#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
997#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
998#define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
999/*! OPAC5
1000 * 0bxxx0..Accesses from an untrusted master are allowed.
1001 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1002 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1003 * 0bxx0x..This peripheral allows write accesses.
1004 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1005 * error response and no peripheral access is initiated on the IPS bus.
1006 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1007 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1008 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1009 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1010 * on the IPS bus.
1011 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1012 */
1013#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
1014#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
1015#define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
1016/*! OPAC4
1017 * 0bxxx0..Accesses from an untrusted master are allowed.
1018 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1019 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1020 * 0bxx0x..This peripheral allows write accesses.
1021 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1022 * error response and no peripheral access is initiated on the IPS bus.
1023 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1024 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1025 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1026 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1027 * on the IPS bus.
1028 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1029 */
1030#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
1031#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
1032#define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
1033/*! OPAC3
1034 * 0bxxx0..Accesses from an untrusted master are allowed.
1035 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1036 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1037 * 0bxx0x..This peripheral allows write accesses.
1038 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1039 * error response and no peripheral access is initiated on the IPS bus.
1040 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1041 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1042 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1043 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1044 * on the IPS bus.
1045 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1046 */
1047#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
1048#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
1049#define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
1050/*! OPAC2
1051 * 0bxxx0..Accesses from an untrusted master are allowed.
1052 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1053 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1054 * 0bxx0x..This peripheral allows write accesses.
1055 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1056 * error response and no peripheral access is initiated on the IPS bus.
1057 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1058 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1059 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1060 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1061 * on the IPS bus.
1062 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1063 */
1064#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
1065#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
1066#define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
1067/*! OPAC1
1068 * 0bxxx0..Accesses from an untrusted master are allowed.
1069 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1070 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1071 * 0bxx0x..This peripheral allows write accesses.
1072 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1073 * error response and no peripheral access is initiated on the IPS bus.
1074 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1075 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1076 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1077 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1078 * on the IPS bus.
1079 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1080 */
1081#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
1082#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
1083#define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
1084/*! OPAC0
1085 * 0bxxx0..Accesses from an untrusted master are allowed.
1086 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1087 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1088 * 0bxx0x..This peripheral allows write accesses.
1089 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1090 * error response and no peripheral access is initiated on the IPS bus.
1091 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1092 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1093 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1094 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1095 * on the IPS bus.
1096 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1097 */
1098#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
1099/*! @} */
1100
1101/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */
1102/*! @{ */
1103#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
1104#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
1105/*! OPAC15
1106 * 0bxxx0..Accesses from an untrusted master are allowed.
1107 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1108 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1109 * 0bxx0x..This peripheral allows write accesses.
1110 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1111 * error response and no peripheral access is initiated on the IPS bus.
1112 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1113 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1114 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1115 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1116 * on the IPS bus.
1117 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1118 */
1119#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
1120#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
1121#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
1122/*! OPAC14
1123 * 0bxxx0..Accesses from an untrusted master are allowed.
1124 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1125 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1126 * 0bxx0x..This peripheral allows write accesses.
1127 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1128 * error response and no peripheral access is initiated on the IPS bus.
1129 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1130 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1131 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1132 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1133 * on the IPS bus.
1134 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1135 */
1136#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
1137#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
1138#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
1139/*! OPAC13
1140 * 0bxxx0..Accesses from an untrusted master are allowed.
1141 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1142 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1143 * 0bxx0x..This peripheral allows write accesses.
1144 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1145 * error response and no peripheral access is initiated on the IPS bus.
1146 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1147 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1148 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1149 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1150 * on the IPS bus.
1151 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1152 */
1153#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
1154#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
1155#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
1156/*! OPAC12
1157 * 0bxxx0..Accesses from an untrusted master are allowed.
1158 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1159 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1160 * 0bxx0x..This peripheral allows write accesses.
1161 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1162 * error response and no peripheral access is initiated on the IPS bus.
1163 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1164 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1165 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1166 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1167 * on the IPS bus.
1168 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1169 */
1170#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
1171#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
1172#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
1173/*! OPAC11
1174 * 0bxxx0..Accesses from an untrusted master are allowed.
1175 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1176 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1177 * 0bxx0x..This peripheral allows write accesses.
1178 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1179 * error response and no peripheral access is initiated on the IPS bus.
1180 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1181 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1182 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1183 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1184 * on the IPS bus.
1185 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1186 */
1187#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
1188#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
1189#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
1190/*! OPAC10
1191 * 0bxxx0..Accesses from an untrusted master are allowed.
1192 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1193 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1194 * 0bxx0x..This peripheral allows write accesses.
1195 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1196 * error response and no peripheral access is initiated on the IPS bus.
1197 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1198 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1199 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1200 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1201 * on the IPS bus.
1202 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1203 */
1204#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
1205#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
1206#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
1207/*! OPAC9
1208 * 0bxxx0..Accesses from an untrusted master are allowed.
1209 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1210 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1211 * 0bxx0x..This peripheral allows write accesses.
1212 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1213 * error response and no peripheral access is initiated on the IPS bus.
1214 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1215 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1216 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1217 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1218 * on the IPS bus.
1219 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1220 */
1221#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
1222#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
1223#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
1224/*! OPAC8
1225 * 0bxxx0..Accesses from an untrusted master are allowed.
1226 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1227 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1228 * 0bxx0x..This peripheral allows write accesses.
1229 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1230 * error response and no peripheral access is initiated on the IPS bus.
1231 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1232 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1233 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1234 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1235 * on the IPS bus.
1236 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1237 */
1238#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
1239/*! @} */
1240
1241/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */
1242/*! @{ */
1243#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
1244#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
1245/*! OPAC23
1246 * 0bxxx0..Accesses from an untrusted master are allowed.
1247 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1248 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1249 * 0bxx0x..This peripheral allows write accesses.
1250 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1251 * error response and no peripheral access is initiated on the IPS bus.
1252 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1253 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1254 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1255 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1256 * on the IPS bus.
1257 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1258 */
1259#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
1260#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
1261#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
1262/*! OPAC22
1263 * 0bxxx0..Accesses from an untrusted master are allowed.
1264 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1265 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1266 * 0bxx0x..This peripheral allows write accesses.
1267 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1268 * error response and no peripheral access is initiated on the IPS bus.
1269 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1270 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1271 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1272 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1273 * on the IPS bus.
1274 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1275 */
1276#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
1277#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
1278#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
1279/*! OPAC21
1280 * 0bxxx0..Accesses from an untrusted master are allowed.
1281 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1282 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1283 * 0bxx0x..This peripheral allows write accesses.
1284 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1285 * error response and no peripheral access is initiated on the IPS bus.
1286 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1287 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1288 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1289 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1290 * on the IPS bus.
1291 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1292 */
1293#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
1294#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
1295#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
1296/*! OPAC20
1297 * 0bxxx0..Accesses from an untrusted master are allowed.
1298 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1299 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1300 * 0bxx0x..This peripheral allows write accesses.
1301 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1302 * error response and no peripheral access is initiated on the IPS bus.
1303 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1304 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1305 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1306 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1307 * on the IPS bus.
1308 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1309 */
1310#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
1311#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
1312#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
1313/*! OPAC19
1314 * 0bxxx0..Accesses from an untrusted master are allowed.
1315 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1316 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1317 * 0bxx0x..This peripheral allows write accesses.
1318 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1319 * error response and no peripheral access is initiated on the IPS bus.
1320 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1321 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1322 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1323 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1324 * on the IPS bus.
1325 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1326 */
1327#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
1328#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
1329#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
1330/*! OPAC18
1331 * 0bxxx0..Accesses from an untrusted master are allowed.
1332 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1333 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1334 * 0bxx0x..This peripheral allows write accesses.
1335 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1336 * error response and no peripheral access is initiated on the IPS bus.
1337 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1338 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1339 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1340 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1341 * on the IPS bus.
1342 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1343 */
1344#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
1345#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
1346#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
1347/*! OPAC17
1348 * 0bxxx0..Accesses from an untrusted master are allowed.
1349 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1350 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1351 * 0bxx0x..This peripheral allows write accesses.
1352 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1353 * error response and no peripheral access is initiated on the IPS bus.
1354 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1355 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1356 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1357 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1358 * on the IPS bus.
1359 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1360 */
1361#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
1362#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
1363#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
1364/*! OPAC16
1365 * 0bxxx0..Accesses from an untrusted master are allowed.
1366 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1367 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1368 * 0bxx0x..This peripheral allows write accesses.
1369 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1370 * error response and no peripheral access is initiated on the IPS bus.
1371 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1372 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1373 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1374 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1375 * on the IPS bus.
1376 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1377 */
1378#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
1379/*! @} */
1380
1381/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */
1382/*! @{ */
1383#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
1384#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
1385/*! OPAC31
1386 * 0bxxx0..Accesses from an untrusted master are allowed.
1387 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1388 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1389 * 0bxx0x..This peripheral allows write accesses.
1390 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1391 * error response and no peripheral access is initiated on the IPS bus.
1392 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1393 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1394 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1395 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1396 * on the IPS bus.
1397 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1398 */
1399#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
1400#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
1401#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
1402/*! OPAC30
1403 * 0bxxx0..Accesses from an untrusted master are allowed.
1404 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1405 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1406 * 0bxx0x..This peripheral allows write accesses.
1407 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1408 * error response and no peripheral access is initiated on the IPS bus.
1409 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1410 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1411 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1412 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1413 * on the IPS bus.
1414 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1415 */
1416#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
1417#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
1418#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
1419/*! OPAC29
1420 * 0bxxx0..Accesses from an untrusted master are allowed.
1421 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1422 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1423 * 0bxx0x..This peripheral allows write accesses.
1424 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1425 * error response and no peripheral access is initiated on the IPS bus.
1426 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1427 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1428 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1429 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1430 * on the IPS bus.
1431 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1432 */
1433#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
1434#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
1435#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
1436/*! OPAC28
1437 * 0bxxx0..Accesses from an untrusted master are allowed.
1438 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1439 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1440 * 0bxx0x..This peripheral allows write accesses.
1441 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1442 * error response and no peripheral access is initiated on the IPS bus.
1443 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1444 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1445 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1446 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1447 * on the IPS bus.
1448 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1449 */
1450#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
1451#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
1452#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
1453/*! OPAC27
1454 * 0bxxx0..Accesses from an untrusted master are allowed.
1455 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1456 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1457 * 0bxx0x..This peripheral allows write accesses.
1458 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1459 * error response and no peripheral access is initiated on the IPS bus.
1460 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1461 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1462 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1463 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1464 * on the IPS bus.
1465 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1466 */
1467#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
1468#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
1469#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
1470/*! OPAC26
1471 * 0bxxx0..Accesses from an untrusted master are allowed.
1472 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1473 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1474 * 0bxx0x..This peripheral allows write accesses.
1475 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1476 * error response and no peripheral access is initiated on the IPS bus.
1477 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1478 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1479 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1480 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1481 * on the IPS bus.
1482 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1483 */
1484#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
1485#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
1486#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
1487/*! OPAC25
1488 * 0bxxx0..Accesses from an untrusted master are allowed.
1489 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1490 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1491 * 0bxx0x..This peripheral allows write accesses.
1492 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1493 * error response and no peripheral access is initiated on the IPS bus.
1494 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1495 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1496 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1497 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1498 * on the IPS bus.
1499 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1500 */
1501#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
1502#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
1503#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
1504/*! OPAC24
1505 * 0bxxx0..Accesses from an untrusted master are allowed.
1506 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1507 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1508 * 0bxx0x..This peripheral allows write accesses.
1509 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1510 * error response and no peripheral access is initiated on the IPS bus.
1511 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1512 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1513 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1514 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1515 * on the IPS bus.
1516 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1517 */
1518#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
1519/*! @} */
1520
1521/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */
1522/*! @{ */
1523#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
1524#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
1525/*! OPAC33
1526 * 0bxxx0..Accesses from an untrusted master are allowed.
1527 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1528 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1529 * 0bxx0x..This peripheral allows write accesses.
1530 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1531 * error response and no peripheral access is initiated on the IPS bus.
1532 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1533 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1534 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1535 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1536 * on the IPS bus.
1537 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1538 */
1539#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
1540#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
1541#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
1542/*! OPAC32
1543 * 0bxxx0..Accesses from an untrusted master are allowed.
1544 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1545 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1546 * 0bxx0x..This peripheral allows write accesses.
1547 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1548 * error response and no peripheral access is initiated on the IPS bus.
1549 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1550 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1551 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1552 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1553 * on the IPS bus.
1554 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1555 */
1556#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
1557/*! @} */
1558
1559
1560/*!
1561 * @}
1562 */ /* end of group AIPSTZ_Register_Masks */
1563
1564
1565/* AIPSTZ - Peripheral instance base addresses */
1566/** Peripheral AIPSTZ base address */
1567#define AIPSTZ_BASE (0x30000000u)
1568/** Peripheral AIPSTZ base pointer */
1569#define AIPSTZ ((AIPSTZ_Type *)AIPSTZ_BASE)
1570/** Array initializer of AIPSTZ peripheral base addresses */
1571#define AIPSTZ_BASE_ADDRS { AIPSTZ_BASE }
1572/** Array initializer of AIPSTZ peripheral base pointers */
1573#define AIPSTZ_BASE_PTRS { AIPSTZ }
1574
1575/*!
1576 * @}
1577 */ /* end of group AIPSTZ_Peripheral_Access_Layer */
1578
1579
1580/* ----------------------------------------------------------------------------
1581 -- APBH Peripheral Access Layer
1582 ---------------------------------------------------------------------------- */
1583
1584/*!
1585 * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer
1586 * @{
1587 */
1588
1589/** APBH - Register Layout Typedef */
1590typedef struct {
1591 __IO uint32_t CTRL0; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */
1592 __IO uint32_t CTRL0_SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */
1593 __IO uint32_t CTRL0_CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */
1594 __IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */
1595 __IO uint32_t CTRL1; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */
1596 __IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */
1597 __IO uint32_t CTRL1_CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */
1598 __IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */
1599 __IO uint32_t CTRL2; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */
1600 __IO uint32_t CTRL2_SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */
1601 __IO uint32_t CTRL2_CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */
1602 __IO uint32_t CTRL2_TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */
1603 __IO uint32_t CHANNEL_CTRL; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */
1604 __IO uint32_t CHANNEL_CTRL_SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */
1605 __IO uint32_t CHANNEL_CTRL_CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */
1606 __IO uint32_t CHANNEL_CTRL_TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */
1607 uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */
1608 uint8_t RESERVED_0[12];
1609 __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */
1610 uint8_t RESERVED_1[12];
1611 __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */
1612 uint8_t RESERVED_2[156];
1613 struct { /* offset: 0x100, array step: 0x70 */
1614 __I uint32_t CH_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, array offset: 0x100, array step: 0x70 */
1615 uint8_t RESERVED_0[12];
1616 __IO uint32_t CH_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, array offset: 0x110, array step: 0x70 */
1617 uint8_t RESERVED_1[12];
1618 __I uint32_t CH_CMD; /**< APBH DMA Channel n Command Register, array offset: 0x120, array step: 0x70 */
1619 uint8_t RESERVED_2[12];
1620 __I uint32_t CH_BAR; /**< APBH DMA Channel n Buffer Address Register, array offset: 0x130, array step: 0x70 */
1621 uint8_t RESERVED_3[12];
1622 __IO uint32_t CH_SEMA; /**< APBH DMA Channel n Semaphore Register, array offset: 0x140, array step: 0x70 */
1623 uint8_t RESERVED_4[12];
1624 __I uint32_t CH_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x150, array step: 0x70 */
1625 uint8_t RESERVED_5[12];
1626 __I uint32_t CH_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */
1627 uint8_t RESERVED_6[12];
1628 } CH_CFGn[16];
1629 __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */
1630} APBH_Type;
1631
1632/* ----------------------------------------------------------------------------
1633 -- APBH Register Masks
1634 ---------------------------------------------------------------------------- */
1635
1636/*!
1637 * @addtogroup APBH_Register_Masks APBH Register Masks
1638 * @{
1639 */
1640
1641/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */
1642/*! @{ */
1643#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU)
1644#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U)
1645/*! CLKGATE_CHANNEL
1646 * 0b0000000000000001..NAND0
1647 * 0b0000000000000010..NAND1
1648 * 0b0000000000000100..NAND2
1649 * 0b0000000000001000..NAND3
1650 * 0b0000000000010000..NAND4
1651 * 0b0000000000100000..NAND5
1652 * 0b0000000001000000..NAND6
1653 * 0b0000000010000000..NAND7
1654 * 0b0000000100000000..SSP
1655 */
1656#define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK)
1657#define APBH_CTRL0_RSVD0_MASK (0xFFF0000U)
1658#define APBH_CTRL0_RSVD0_SHIFT (16U)
1659#define APBH_CTRL0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_RSVD0_SHIFT)) & APBH_CTRL0_RSVD0_MASK)
1660#define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U)
1661#define APBH_CTRL0_APB_BURST_EN_SHIFT (28U)
1662#define APBH_CTRL0_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK)
1663#define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U)
1664#define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U)
1665#define APBH_CTRL0_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK)
1666#define APBH_CTRL0_CLKGATE_MASK (0x40000000U)
1667#define APBH_CTRL0_CLKGATE_SHIFT (30U)
1668#define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK)
1669#define APBH_CTRL0_SFTRST_MASK (0x80000000U)
1670#define APBH_CTRL0_SFTRST_SHIFT (31U)
1671#define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK)
1672/*! @} */
1673
1674/*! @name CTRL0_SET - AHB to APBH Bridge Control and Status Register 0 */
1675/*! @{ */
1676#define APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK (0xFFFFU)
1677#define APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT (0U)
1678/*! CLKGATE_CHANNEL
1679 * 0b0000000000000001..NAND0
1680 * 0b0000000000000010..NAND1
1681 * 0b0000000000000100..NAND2
1682 * 0b0000000000001000..NAND3
1683 * 0b0000000000010000..NAND4
1684 * 0b0000000000100000..NAND5
1685 * 0b0000000001000000..NAND6
1686 * 0b0000000010000000..NAND7
1687 * 0b0000000100000000..SSP
1688 */
1689#define APBH_CTRL0_SET_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK)
1690#define APBH_CTRL0_SET_RSVD0_MASK (0xFFF0000U)
1691#define APBH_CTRL0_SET_RSVD0_SHIFT (16U)
1692#define APBH_CTRL0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_RSVD0_SHIFT)) & APBH_CTRL0_SET_RSVD0_MASK)
1693#define APBH_CTRL0_SET_APB_BURST_EN_MASK (0x10000000U)
1694#define APBH_CTRL0_SET_APB_BURST_EN_SHIFT (28U)
1695#define APBH_CTRL0_SET_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_APB_BURST_EN_SHIFT)) & APBH_CTRL0_SET_APB_BURST_EN_MASK)
1696#define APBH_CTRL0_SET_AHB_BURST8_EN_MASK (0x20000000U)
1697#define APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT (29U)
1698#define APBH_CTRL0_SET_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_SET_AHB_BURST8_EN_MASK)
1699#define APBH_CTRL0_SET_CLKGATE_MASK (0x40000000U)
1700#define APBH_CTRL0_SET_CLKGATE_SHIFT (30U)
1701#define APBH_CTRL0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_SHIFT)) & APBH_CTRL0_SET_CLKGATE_MASK)
1702#define APBH_CTRL0_SET_SFTRST_MASK (0x80000000U)
1703#define APBH_CTRL0_SET_SFTRST_SHIFT (31U)
1704#define APBH_CTRL0_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_SFTRST_SHIFT)) & APBH_CTRL0_SET_SFTRST_MASK)
1705/*! @} */
1706
1707/*! @name CTRL0_CLR - AHB to APBH Bridge Control and Status Register 0 */
1708/*! @{ */
1709#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK (0xFFFFU)
1710#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT (0U)
1711/*! CLKGATE_CHANNEL
1712 * 0b0000000000000001..NAND0
1713 * 0b0000000000000010..NAND1
1714 * 0b0000000000000100..NAND2
1715 * 0b0000000000001000..NAND3
1716 * 0b0000000000010000..NAND4
1717 * 0b0000000000100000..NAND5
1718 * 0b0000000001000000..NAND6
1719 * 0b0000000010000000..NAND7
1720 * 0b0000000100000000..SSP
1721 */
1722#define APBH_CTRL0_CLR_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK)
1723#define APBH_CTRL0_CLR_RSVD0_MASK (0xFFF0000U)
1724#define APBH_CTRL0_CLR_RSVD0_SHIFT (16U)
1725#define APBH_CTRL0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_RSVD0_SHIFT)) & APBH_CTRL0_CLR_RSVD0_MASK)
1726#define APBH_CTRL0_CLR_APB_BURST_EN_MASK (0x10000000U)
1727#define APBH_CTRL0_CLR_APB_BURST_EN_SHIFT (28U)
1728#define APBH_CTRL0_CLR_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_APB_BURST_EN_SHIFT)) & APBH_CTRL0_CLR_APB_BURST_EN_MASK)
1729#define APBH_CTRL0_CLR_AHB_BURST8_EN_MASK (0x20000000U)
1730#define APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT (29U)
1731#define APBH_CTRL0_CLR_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_CLR_AHB_BURST8_EN_MASK)
1732#define APBH_CTRL0_CLR_CLKGATE_MASK (0x40000000U)
1733#define APBH_CTRL0_CLR_CLKGATE_SHIFT (30U)
1734#define APBH_CTRL0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_MASK)
1735#define APBH_CTRL0_CLR_SFTRST_MASK (0x80000000U)
1736#define APBH_CTRL0_CLR_SFTRST_SHIFT (31U)
1737#define APBH_CTRL0_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_SFTRST_SHIFT)) & APBH_CTRL0_CLR_SFTRST_MASK)
1738/*! @} */
1739
1740/*! @name CTRL0_TOG - AHB to APBH Bridge Control and Status Register 0 */
1741/*! @{ */
1742#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK (0xFFFFU)
1743#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT (0U)
1744/*! CLKGATE_CHANNEL
1745 * 0b0000000000000001..NAND0
1746 * 0b0000000000000010..NAND1
1747 * 0b0000000000000100..NAND2
1748 * 0b0000000000001000..NAND3
1749 * 0b0000000000010000..NAND4
1750 * 0b0000000000100000..NAND5
1751 * 0b0000000001000000..NAND6
1752 * 0b0000000010000000..NAND7
1753 * 0b0000000100000000..SSP
1754 */
1755#define APBH_CTRL0_TOG_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK)
1756#define APBH_CTRL0_TOG_RSVD0_MASK (0xFFF0000U)
1757#define APBH_CTRL0_TOG_RSVD0_SHIFT (16U)
1758#define APBH_CTRL0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_RSVD0_SHIFT)) & APBH_CTRL0_TOG_RSVD0_MASK)
1759#define APBH_CTRL0_TOG_APB_BURST_EN_MASK (0x10000000U)
1760#define APBH_CTRL0_TOG_APB_BURST_EN_SHIFT (28U)
1761#define APBH_CTRL0_TOG_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_APB_BURST_EN_SHIFT)) & APBH_CTRL0_TOG_APB_BURST_EN_MASK)
1762#define APBH_CTRL0_TOG_AHB_BURST8_EN_MASK (0x20000000U)
1763#define APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT (29U)
1764#define APBH_CTRL0_TOG_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_TOG_AHB_BURST8_EN_MASK)
1765#define APBH_CTRL0_TOG_CLKGATE_MASK (0x40000000U)
1766#define APBH_CTRL0_TOG_CLKGATE_SHIFT (30U)
1767#define APBH_CTRL0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_MASK)
1768#define APBH_CTRL0_TOG_SFTRST_MASK (0x80000000U)
1769#define APBH_CTRL0_TOG_SFTRST_SHIFT (31U)
1770#define APBH_CTRL0_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_SFTRST_SHIFT)) & APBH_CTRL0_TOG_SFTRST_MASK)
1771/*! @} */
1772
1773/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */
1774/*! @{ */
1775#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1776#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1777#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK)
1778#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1779#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1780#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK)
1781#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1782#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1783#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK)
1784#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1785#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1786#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK)
1787#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1788#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1789#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK)
1790#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1791#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1792#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK)
1793#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1794#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1795#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK)
1796#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1797#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1798#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK)
1799#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1800#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1801#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK)
1802#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1803#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1804#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK)
1805#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1806#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1807#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK)
1808#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1809#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1810#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK)
1811#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1812#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1813#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK)
1814#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1815#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1816#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK)
1817#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1818#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1819#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK)
1820#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1821#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1822#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK)
1823#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1824#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
1825#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK)
1826#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
1827#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
1828#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK)
1829#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
1830#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
1831#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK)
1832#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
1833#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
1834#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK)
1835#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
1836#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
1837#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK)
1838#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
1839#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
1840#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK)
1841#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
1842#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
1843#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK)
1844#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
1845#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
1846#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK)
1847#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
1848#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
1849#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK)
1850#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
1851#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
1852#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK)
1853#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
1854#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
1855#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
1856#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
1857#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
1858#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK)
1859#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
1860#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
1861#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK)
1862#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
1863#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
1864#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK)
1865#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
1866#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
1867#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK)
1868#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
1869#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
1870#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK)
1871/*! @} */
1872
1873/*! @name CTRL1_SET - AHB to APBH Bridge Control and Status Register 1 */
1874/*! @{ */
1875#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1876#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1877#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK)
1878#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1879#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1880#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK)
1881#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1882#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1883#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK)
1884#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1885#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1886#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK)
1887#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1888#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1889#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK)
1890#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1891#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1892#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK)
1893#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1894#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1895#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK)
1896#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1897#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1898#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK)
1899#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1900#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1901#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK)
1902#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1903#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1904#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK)
1905#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1906#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1907#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK)
1908#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1909#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1910#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK)
1911#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1912#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1913#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK)
1914#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1915#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1916#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK)
1917#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1918#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1919#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK)
1920#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1921#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1922#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK)
1923#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1924#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
1925#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK)
1926#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
1927#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
1928#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK)
1929#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
1930#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
1931#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK)
1932#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
1933#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
1934#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK)
1935#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
1936#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
1937#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK)
1938#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
1939#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
1940#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK)
1941#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
1942#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
1943#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK)
1944#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
1945#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
1946#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK)
1947#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
1948#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
1949#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK)
1950#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
1951#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
1952#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK)
1953#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
1954#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
1955#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK)
1956#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
1957#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
1958#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK)
1959#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
1960#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
1961#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK)
1962#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
1963#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
1964#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK)
1965#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
1966#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
1967#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK)
1968#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
1969#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
1970#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK)
1971/*! @} */
1972
1973/*! @name CTRL1_CLR - AHB to APBH Bridge Control and Status Register 1 */
1974/*! @{ */
1975#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1976#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1977#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK)
1978#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1979#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1980#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK)
1981#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1982#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1983#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK)
1984#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1985#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1986#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK)
1987#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1988#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1989#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK)
1990#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1991#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1992#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK)
1993#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1994#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1995#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK)
1996#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1997#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1998#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK)
1999#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK (0x100U)
2000#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT (8U)
2001#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK)
2002#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK (0x200U)
2003#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT (9U)
2004#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK)
2005#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK (0x400U)
2006#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT (10U)
2007#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK)
2008#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK (0x800U)
2009#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT (11U)
2010#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK)
2011#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
2012#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT (12U)
2013#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK)
2014#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
2015#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT (13U)
2016#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK)
2017#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
2018#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT (14U)
2019#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK)
2020#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
2021#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT (15U)
2022#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK)
2023#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
2024#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
2025#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK)
2026#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
2027#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
2028#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK)
2029#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
2030#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
2031#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK)
2032#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
2033#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
2034#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK)
2035#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
2036#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
2037#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK)
2038#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
2039#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
2040#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK)
2041#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
2042#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
2043#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK)
2044#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
2045#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
2046#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK)
2047#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
2048#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
2049#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK)
2050#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
2051#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
2052#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK)
2053#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
2054#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
2055#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK)
2056#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
2057#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
2058#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK)
2059#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
2060#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
2061#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK)
2062#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
2063#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
2064#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK)
2065#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
2066#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
2067#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK)
2068#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
2069#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
2070#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK)
2071/*! @} */
2072
2073/*! @name CTRL1_TOG - AHB to APBH Bridge Control and Status Register 1 */
2074/*! @{ */
2075#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK (0x1U)
2076#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT (0U)
2077#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK)
2078#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK (0x2U)
2079#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT (1U)
2080#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK)
2081#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK (0x4U)
2082#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT (2U)
2083#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK)
2084#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK (0x8U)
2085#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT (3U)
2086#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK)
2087#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK (0x10U)
2088#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT (4U)
2089#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK)
2090#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK (0x20U)
2091#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT (5U)
2092#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK)
2093#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK (0x40U)
2094#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT (6U)
2095#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK)
2096#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK (0x80U)
2097#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT (7U)
2098#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK)
2099#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK (0x100U)
2100#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT (8U)
2101#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK)
2102#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK (0x200U)
2103#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT (9U)
2104#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK)
2105#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK (0x400U)
2106#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT (10U)
2107#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK)
2108#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK (0x800U)
2109#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT (11U)
2110#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK)
2111#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
2112#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT (12U)
2113#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK)
2114#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
2115#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT (13U)
2116#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK)
2117#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
2118#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT (14U)
2119#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK)
2120#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
2121#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT (15U)
2122#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK)
2123#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
2124#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
2125#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK)
2126#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
2127#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
2128#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK)
2129#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
2130#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
2131#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK)
2132#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
2133#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
2134#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK)
2135#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
2136#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
2137#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK)
2138#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
2139#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
2140#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK)
2141#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
2142#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
2143#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK)
2144#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
2145#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
2146#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK)
2147#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
2148#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
2149#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK)
2150#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
2151#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
2152#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK)
2153#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
2154#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
2155#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK)
2156#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
2157#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
2158#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK)
2159#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
2160#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
2161#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK)
2162#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
2163#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
2164#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK)
2165#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
2166#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
2167#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK)
2168#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
2169#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
2170#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK)
2171/*! @} */
2172
2173/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */
2174/*! @{ */
2175#define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U)
2176#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U)
2177#define APBH_CTRL2_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK)
2178#define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U)
2179#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U)
2180#define APBH_CTRL2_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK)
2181#define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U)
2182#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U)
2183#define APBH_CTRL2_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK)
2184#define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U)
2185#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U)
2186#define APBH_CTRL2_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK)
2187#define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U)
2188#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U)
2189#define APBH_CTRL2_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK)
2190#define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U)
2191#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U)
2192#define APBH_CTRL2_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK)
2193#define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U)
2194#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U)
2195#define APBH_CTRL2_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK)
2196#define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U)
2197#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U)
2198#define APBH_CTRL2_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK)
2199#define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U)
2200#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U)
2201#define APBH_CTRL2_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK)
2202#define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U)
2203#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U)
2204#define APBH_CTRL2_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK)
2205#define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U)
2206#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U)
2207#define APBH_CTRL2_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK)
2208#define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U)
2209#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U)
2210#define APBH_CTRL2_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK)
2211#define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U)
2212#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U)
2213#define APBH_CTRL2_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK)
2214#define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U)
2215#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U)
2216#define APBH_CTRL2_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK)
2217#define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U)
2218#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U)
2219#define APBH_CTRL2_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK)
2220#define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U)
2221#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U)
2222#define APBH_CTRL2_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK)
2223#define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U)
2224#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U)
2225/*! CH0_ERROR_STATUS
2226 * 0b0..An early termination from the device causes error IRQ.
2227 * 0b1..An AHB bus error causes error IRQ.
2228 */
2229#define APBH_CTRL2_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK)
2230#define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U)
2231#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U)
2232/*! CH1_ERROR_STATUS
2233 * 0b0..An early termination from the device causes error IRQ.
2234 * 0b1..An AHB bus error causes error IRQ.
2235 */
2236#define APBH_CTRL2_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK)
2237#define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U)
2238#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U)
2239/*! CH2_ERROR_STATUS
2240 * 0b0..An early termination from the device causes error IRQ.
2241 * 0b1..An AHB bus error causes error IRQ.
2242 */
2243#define APBH_CTRL2_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK)
2244#define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U)
2245#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U)
2246/*! CH3_ERROR_STATUS
2247 * 0b0..An early termination from the device causes error IRQ.
2248 * 0b1..An AHB bus error causes error IRQ.
2249 */
2250#define APBH_CTRL2_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK)
2251#define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U)
2252#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U)
2253/*! CH4_ERROR_STATUS
2254 * 0b0..An early termination from the device causes error IRQ.
2255 * 0b1..An AHB bus error causes error IRQ.
2256 */
2257#define APBH_CTRL2_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK)
2258#define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U)
2259#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U)
2260/*! CH5_ERROR_STATUS
2261 * 0b0..An early termination from the device causes error IRQ.
2262 * 0b1..An AHB bus error causes error IRQ.
2263 */
2264#define APBH_CTRL2_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK)
2265#define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U)
2266#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U)
2267/*! CH6_ERROR_STATUS
2268 * 0b0..An early termination from the device causes error IRQ.
2269 * 0b1..An AHB bus error causes error IRQ.
2270 */
2271#define APBH_CTRL2_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK)
2272#define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U)
2273#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U)
2274/*! CH7_ERROR_STATUS
2275 * 0b0..An early termination from the device causes error IRQ.
2276 * 0b1..An AHB bus error causes error IRQ.
2277 */
2278#define APBH_CTRL2_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK)
2279#define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U)
2280#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U)
2281/*! CH8_ERROR_STATUS
2282 * 0b0..An early termination from the device causes error IRQ.
2283 * 0b1..An AHB bus error causes error IRQ.
2284 */
2285#define APBH_CTRL2_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK)
2286#define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U)
2287#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U)
2288/*! CH9_ERROR_STATUS
2289 * 0b0..An early termination from the device causes error IRQ.
2290 * 0b1..An AHB bus error causes error IRQ.
2291 */
2292#define APBH_CTRL2_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK)
2293#define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U)
2294#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U)
2295/*! CH10_ERROR_STATUS
2296 * 0b0..An early termination from the device causes error IRQ.
2297 * 0b1..An AHB bus error causes error IRQ.
2298 */
2299#define APBH_CTRL2_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK)
2300#define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U)
2301#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U)
2302/*! CH11_ERROR_STATUS
2303 * 0b0..An early termination from the device causes error IRQ.
2304 * 0b1..An AHB bus error causes error IRQ.
2305 */
2306#define APBH_CTRL2_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK)
2307#define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U)
2308#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U)
2309/*! CH12_ERROR_STATUS
2310 * 0b0..An early termination from the device causes error IRQ.
2311 * 0b1..An AHB bus error causes error IRQ.
2312 */
2313#define APBH_CTRL2_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK)
2314#define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U)
2315#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U)
2316/*! CH13_ERROR_STATUS
2317 * 0b0..An early termination from the device causes error IRQ.
2318 * 0b1..An AHB bus error causes error IRQ.
2319 */
2320#define APBH_CTRL2_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK)
2321#define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U)
2322#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U)
2323/*! CH14_ERROR_STATUS
2324 * 0b0..An early termination from the device causes error IRQ.
2325 * 0b1..An AHB bus error causes error IRQ.
2326 */
2327#define APBH_CTRL2_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK)
2328#define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U)
2329#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U)
2330/*! CH15_ERROR_STATUS
2331 * 0b0..An early termination from the device causes error IRQ.
2332 * 0b1..An AHB bus error causes error IRQ.
2333 */
2334#define APBH_CTRL2_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK)
2335/*! @} */
2336
2337/*! @name CTRL2_SET - AHB to APBH Bridge Control and Status Register 2 */
2338/*! @{ */
2339#define APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK (0x1U)
2340#define APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT (0U)
2341#define APBH_CTRL2_SET_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK)
2342#define APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK (0x2U)
2343#define APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT (1U)
2344#define APBH_CTRL2_SET_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK)
2345#define APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK (0x4U)
2346#define APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT (2U)
2347#define APBH_CTRL2_SET_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK)
2348#define APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK (0x8U)
2349#define APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT (3U)
2350#define APBH_CTRL2_SET_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK)
2351#define APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK (0x10U)
2352#define APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT (4U)
2353#define APBH_CTRL2_SET_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK)
2354#define APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK (0x20U)
2355#define APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT (5U)
2356#define APBH_CTRL2_SET_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK)
2357#define APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK (0x40U)
2358#define APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT (6U)
2359#define APBH_CTRL2_SET_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK)
2360#define APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK (0x80U)
2361#define APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT (7U)
2362#define APBH_CTRL2_SET_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK)
2363#define APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK (0x100U)
2364#define APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT (8U)
2365#define APBH_CTRL2_SET_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK)
2366#define APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK (0x200U)
2367#define APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT (9U)
2368#define APBH_CTRL2_SET_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK)
2369#define APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK (0x400U)
2370#define APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT (10U)
2371#define APBH_CTRL2_SET_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK)
2372#define APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK (0x800U)
2373#define APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT (11U)
2374#define APBH_CTRL2_SET_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK)
2375#define APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK (0x1000U)
2376#define APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT (12U)
2377#define APBH_CTRL2_SET_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK)
2378#define APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK (0x2000U)
2379#define APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT (13U)
2380#define APBH_CTRL2_SET_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK)
2381#define APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK (0x4000U)
2382#define APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT (14U)
2383#define APBH_CTRL2_SET_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK)
2384#define APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK (0x8000U)
2385#define APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT (15U)
2386#define APBH_CTRL2_SET_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK)
2387#define APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK (0x10000U)
2388#define APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT (16U)
2389/*! CH0_ERROR_STATUS
2390 * 0b0..An early termination from the device causes error IRQ.
2391 * 0b1..An AHB bus error causes error IRQ.
2392 */
2393#define APBH_CTRL2_SET_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK)
2394#define APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK (0x20000U)
2395#define APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT (17U)
2396/*! CH1_ERROR_STATUS
2397 * 0b0..An early termination from the device causes error IRQ.
2398 * 0b1..An AHB bus error causes error IRQ.
2399 */
2400#define APBH_CTRL2_SET_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK)
2401#define APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK (0x40000U)
2402#define APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT (18U)
2403/*! CH2_ERROR_STATUS
2404 * 0b0..An early termination from the device causes error IRQ.
2405 * 0b1..An AHB bus error causes error IRQ.
2406 */
2407#define APBH_CTRL2_SET_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK)
2408#define APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK (0x80000U)
2409#define APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT (19U)
2410/*! CH3_ERROR_STATUS
2411 * 0b0..An early termination from the device causes error IRQ.
2412 * 0b1..An AHB bus error causes error IRQ.
2413 */
2414#define APBH_CTRL2_SET_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK)
2415#define APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK (0x100000U)
2416#define APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT (20U)
2417/*! CH4_ERROR_STATUS
2418 * 0b0..An early termination from the device causes error IRQ.
2419 * 0b1..An AHB bus error causes error IRQ.
2420 */
2421#define APBH_CTRL2_SET_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK)
2422#define APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK (0x200000U)
2423#define APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT (21U)
2424/*! CH5_ERROR_STATUS
2425 * 0b0..An early termination from the device causes error IRQ.
2426 * 0b1..An AHB bus error causes error IRQ.
2427 */
2428#define APBH_CTRL2_SET_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK)
2429#define APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK (0x400000U)
2430#define APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT (22U)
2431/*! CH6_ERROR_STATUS
2432 * 0b0..An early termination from the device causes error IRQ.
2433 * 0b1..An AHB bus error causes error IRQ.
2434 */
2435#define APBH_CTRL2_SET_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK)
2436#define APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK (0x800000U)
2437#define APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT (23U)
2438/*! CH7_ERROR_STATUS
2439 * 0b0..An early termination from the device causes error IRQ.
2440 * 0b1..An AHB bus error causes error IRQ.
2441 */
2442#define APBH_CTRL2_SET_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK)
2443#define APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK (0x1000000U)
2444#define APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT (24U)
2445/*! CH8_ERROR_STATUS
2446 * 0b0..An early termination from the device causes error IRQ.
2447 * 0b1..An AHB bus error causes error IRQ.
2448 */
2449#define APBH_CTRL2_SET_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK)
2450#define APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK (0x2000000U)
2451#define APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT (25U)
2452/*! CH9_ERROR_STATUS
2453 * 0b0..An early termination from the device causes error IRQ.
2454 * 0b1..An AHB bus error causes error IRQ.
2455 */
2456#define APBH_CTRL2_SET_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK)
2457#define APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK (0x4000000U)
2458#define APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT (26U)
2459/*! CH10_ERROR_STATUS
2460 * 0b0..An early termination from the device causes error IRQ.
2461 * 0b1..An AHB bus error causes error IRQ.
2462 */
2463#define APBH_CTRL2_SET_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK)
2464#define APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK (0x8000000U)
2465#define APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT (27U)
2466/*! CH11_ERROR_STATUS
2467 * 0b0..An early termination from the device causes error IRQ.
2468 * 0b1..An AHB bus error causes error IRQ.
2469 */
2470#define APBH_CTRL2_SET_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK)
2471#define APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK (0x10000000U)
2472#define APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT (28U)
2473/*! CH12_ERROR_STATUS
2474 * 0b0..An early termination from the device causes error IRQ.
2475 * 0b1..An AHB bus error causes error IRQ.
2476 */
2477#define APBH_CTRL2_SET_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK)
2478#define APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK (0x20000000U)
2479#define APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT (29U)
2480/*! CH13_ERROR_STATUS
2481 * 0b0..An early termination from the device causes error IRQ.
2482 * 0b1..An AHB bus error causes error IRQ.
2483 */
2484#define APBH_CTRL2_SET_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK)
2485#define APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK (0x40000000U)
2486#define APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT (30U)
2487/*! CH14_ERROR_STATUS
2488 * 0b0..An early termination from the device causes error IRQ.
2489 * 0b1..An AHB bus error causes error IRQ.
2490 */
2491#define APBH_CTRL2_SET_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK)
2492#define APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK (0x80000000U)
2493#define APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT (31U)
2494/*! CH15_ERROR_STATUS
2495 * 0b0..An early termination from the device causes error IRQ.
2496 * 0b1..An AHB bus error causes error IRQ.
2497 */
2498#define APBH_CTRL2_SET_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK)
2499/*! @} */
2500
2501/*! @name CTRL2_CLR - AHB to APBH Bridge Control and Status Register 2 */
2502/*! @{ */
2503#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK (0x1U)
2504#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT (0U)
2505#define APBH_CTRL2_CLR_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK)
2506#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK (0x2U)
2507#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT (1U)
2508#define APBH_CTRL2_CLR_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK)
2509#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK (0x4U)
2510#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT (2U)
2511#define APBH_CTRL2_CLR_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK)
2512#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK (0x8U)
2513#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT (3U)
2514#define APBH_CTRL2_CLR_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK)
2515#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK (0x10U)
2516#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT (4U)
2517#define APBH_CTRL2_CLR_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK)
2518#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK (0x20U)
2519#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT (5U)
2520#define APBH_CTRL2_CLR_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK)
2521#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK (0x40U)
2522#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT (6U)
2523#define APBH_CTRL2_CLR_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK)
2524#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK (0x80U)
2525#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT (7U)
2526#define APBH_CTRL2_CLR_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK)
2527#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK (0x100U)
2528#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT (8U)
2529#define APBH_CTRL2_CLR_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK)
2530#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK (0x200U)
2531#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT (9U)
2532#define APBH_CTRL2_CLR_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK)
2533#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK (0x400U)
2534#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT (10U)
2535#define APBH_CTRL2_CLR_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK)
2536#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK (0x800U)
2537#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT (11U)
2538#define APBH_CTRL2_CLR_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK)
2539#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK (0x1000U)
2540#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT (12U)
2541#define APBH_CTRL2_CLR_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK)
2542#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK (0x2000U)
2543#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT (13U)
2544#define APBH_CTRL2_CLR_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK)
2545#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK (0x4000U)
2546#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT (14U)
2547#define APBH_CTRL2_CLR_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK)
2548#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK (0x8000U)
2549#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT (15U)
2550#define APBH_CTRL2_CLR_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK)
2551#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK (0x10000U)
2552#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT (16U)
2553/*! CH0_ERROR_STATUS
2554 * 0b0..An early termination from the device causes error IRQ.
2555 * 0b1..An AHB bus error causes error IRQ.
2556 */
2557#define APBH_CTRL2_CLR_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK)
2558#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK (0x20000U)
2559#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT (17U)
2560/*! CH1_ERROR_STATUS
2561 * 0b0..An early termination from the device causes error IRQ.
2562 * 0b1..An AHB bus error causes error IRQ.
2563 */
2564#define APBH_CTRL2_CLR_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK)
2565#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK (0x40000U)
2566#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT (18U)
2567/*! CH2_ERROR_STATUS
2568 * 0b0..An early termination from the device causes error IRQ.
2569 * 0b1..An AHB bus error causes error IRQ.
2570 */
2571#define APBH_CTRL2_CLR_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK)
2572#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK (0x80000U)
2573#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT (19U)
2574/*! CH3_ERROR_STATUS
2575 * 0b0..An early termination from the device causes error IRQ.
2576 * 0b1..An AHB bus error causes error IRQ.
2577 */
2578#define APBH_CTRL2_CLR_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK)
2579#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK (0x100000U)
2580#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT (20U)
2581/*! CH4_ERROR_STATUS
2582 * 0b0..An early termination from the device causes error IRQ.
2583 * 0b1..An AHB bus error causes error IRQ.
2584 */
2585#define APBH_CTRL2_CLR_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK)
2586#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK (0x200000U)
2587#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT (21U)
2588/*! CH5_ERROR_STATUS
2589 * 0b0..An early termination from the device causes error IRQ.
2590 * 0b1..An AHB bus error causes error IRQ.
2591 */
2592#define APBH_CTRL2_CLR_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK)
2593#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK (0x400000U)
2594#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT (22U)
2595/*! CH6_ERROR_STATUS
2596 * 0b0..An early termination from the device causes error IRQ.
2597 * 0b1..An AHB bus error causes error IRQ.
2598 */
2599#define APBH_CTRL2_CLR_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK)
2600#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK (0x800000U)
2601#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT (23U)
2602/*! CH7_ERROR_STATUS
2603 * 0b0..An early termination from the device causes error IRQ.
2604 * 0b1..An AHB bus error causes error IRQ.
2605 */
2606#define APBH_CTRL2_CLR_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK)
2607#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK (0x1000000U)
2608#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT (24U)
2609/*! CH8_ERROR_STATUS
2610 * 0b0..An early termination from the device causes error IRQ.
2611 * 0b1..An AHB bus error causes error IRQ.
2612 */
2613#define APBH_CTRL2_CLR_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK)
2614#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK (0x2000000U)
2615#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT (25U)
2616/*! CH9_ERROR_STATUS
2617 * 0b0..An early termination from the device causes error IRQ.
2618 * 0b1..An AHB bus error causes error IRQ.
2619 */
2620#define APBH_CTRL2_CLR_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK)
2621#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK (0x4000000U)
2622#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT (26U)
2623/*! CH10_ERROR_STATUS
2624 * 0b0..An early termination from the device causes error IRQ.
2625 * 0b1..An AHB bus error causes error IRQ.
2626 */
2627#define APBH_CTRL2_CLR_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK)
2628#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK (0x8000000U)
2629#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT (27U)
2630/*! CH11_ERROR_STATUS
2631 * 0b0..An early termination from the device causes error IRQ.
2632 * 0b1..An AHB bus error causes error IRQ.
2633 */
2634#define APBH_CTRL2_CLR_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK)
2635#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK (0x10000000U)
2636#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT (28U)
2637/*! CH12_ERROR_STATUS
2638 * 0b0..An early termination from the device causes error IRQ.
2639 * 0b1..An AHB bus error causes error IRQ.
2640 */
2641#define APBH_CTRL2_CLR_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK)
2642#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK (0x20000000U)
2643#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT (29U)
2644/*! CH13_ERROR_STATUS
2645 * 0b0..An early termination from the device causes error IRQ.
2646 * 0b1..An AHB bus error causes error IRQ.
2647 */
2648#define APBH_CTRL2_CLR_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK)
2649#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK (0x40000000U)
2650#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT (30U)
2651/*! CH14_ERROR_STATUS
2652 * 0b0..An early termination from the device causes error IRQ.
2653 * 0b1..An AHB bus error causes error IRQ.
2654 */
2655#define APBH_CTRL2_CLR_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK)
2656#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK (0x80000000U)
2657#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT (31U)
2658/*! CH15_ERROR_STATUS
2659 * 0b0..An early termination from the device causes error IRQ.
2660 * 0b1..An AHB bus error causes error IRQ.
2661 */
2662#define APBH_CTRL2_CLR_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK)
2663/*! @} */
2664
2665/*! @name CTRL2_TOG - AHB to APBH Bridge Control and Status Register 2 */
2666/*! @{ */
2667#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK (0x1U)
2668#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT (0U)
2669#define APBH_CTRL2_TOG_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK)
2670#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK (0x2U)
2671#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT (1U)
2672#define APBH_CTRL2_TOG_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK)
2673#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK (0x4U)
2674#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT (2U)
2675#define APBH_CTRL2_TOG_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK)
2676#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK (0x8U)
2677#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT (3U)
2678#define APBH_CTRL2_TOG_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK)
2679#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK (0x10U)
2680#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT (4U)
2681#define APBH_CTRL2_TOG_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK)
2682#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK (0x20U)
2683#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT (5U)
2684#define APBH_CTRL2_TOG_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK)
2685#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK (0x40U)
2686#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT (6U)
2687#define APBH_CTRL2_TOG_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK)
2688#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK (0x80U)
2689#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT (7U)
2690#define APBH_CTRL2_TOG_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK)
2691#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK (0x100U)
2692#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT (8U)
2693#define APBH_CTRL2_TOG_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK)
2694#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK (0x200U)
2695#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT (9U)
2696#define APBH_CTRL2_TOG_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK)
2697#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK (0x400U)
2698#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT (10U)
2699#define APBH_CTRL2_TOG_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK)
2700#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK (0x800U)
2701#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT (11U)
2702#define APBH_CTRL2_TOG_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK)
2703#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK (0x1000U)
2704#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT (12U)
2705#define APBH_CTRL2_TOG_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK)
2706#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK (0x2000U)
2707#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT (13U)
2708#define APBH_CTRL2_TOG_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK)
2709#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK (0x4000U)
2710#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT (14U)
2711#define APBH_CTRL2_TOG_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK)
2712#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK (0x8000U)
2713#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT (15U)
2714#define APBH_CTRL2_TOG_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK)
2715#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK (0x10000U)
2716#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT (16U)
2717/*! CH0_ERROR_STATUS
2718 * 0b0..An early termination from the device causes error IRQ.
2719 * 0b1..An AHB bus error causes error IRQ.
2720 */
2721#define APBH_CTRL2_TOG_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK)
2722#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK (0x20000U)
2723#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT (17U)
2724/*! CH1_ERROR_STATUS
2725 * 0b0..An early termination from the device causes error IRQ.
2726 * 0b1..An AHB bus error causes error IRQ.
2727 */
2728#define APBH_CTRL2_TOG_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK)
2729#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK (0x40000U)
2730#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT (18U)
2731/*! CH2_ERROR_STATUS
2732 * 0b0..An early termination from the device causes error IRQ.
2733 * 0b1..An AHB bus error causes error IRQ.
2734 */
2735#define APBH_CTRL2_TOG_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK)
2736#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK (0x80000U)
2737#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT (19U)
2738/*! CH3_ERROR_STATUS
2739 * 0b0..An early termination from the device causes error IRQ.
2740 * 0b1..An AHB bus error causes error IRQ.
2741 */
2742#define APBH_CTRL2_TOG_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK)
2743#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK (0x100000U)
2744#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT (20U)
2745/*! CH4_ERROR_STATUS
2746 * 0b0..An early termination from the device causes error IRQ.
2747 * 0b1..An AHB bus error causes error IRQ.
2748 */
2749#define APBH_CTRL2_TOG_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK)
2750#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK (0x200000U)
2751#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT (21U)
2752/*! CH5_ERROR_STATUS
2753 * 0b0..An early termination from the device causes error IRQ.
2754 * 0b1..An AHB bus error causes error IRQ.
2755 */
2756#define APBH_CTRL2_TOG_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK)
2757#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK (0x400000U)
2758#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT (22U)
2759/*! CH6_ERROR_STATUS
2760 * 0b0..An early termination from the device causes error IRQ.
2761 * 0b1..An AHB bus error causes error IRQ.
2762 */
2763#define APBH_CTRL2_TOG_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK)
2764#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK (0x800000U)
2765#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT (23U)
2766/*! CH7_ERROR_STATUS
2767 * 0b0..An early termination from the device causes error IRQ.
2768 * 0b1..An AHB bus error causes error IRQ.
2769 */
2770#define APBH_CTRL2_TOG_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK)
2771#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK (0x1000000U)
2772#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT (24U)
2773/*! CH8_ERROR_STATUS
2774 * 0b0..An early termination from the device causes error IRQ.
2775 * 0b1..An AHB bus error causes error IRQ.
2776 */
2777#define APBH_CTRL2_TOG_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK)
2778#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK (0x2000000U)
2779#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT (25U)
2780/*! CH9_ERROR_STATUS
2781 * 0b0..An early termination from the device causes error IRQ.
2782 * 0b1..An AHB bus error causes error IRQ.
2783 */
2784#define APBH_CTRL2_TOG_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK)
2785#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK (0x4000000U)
2786#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT (26U)
2787/*! CH10_ERROR_STATUS
2788 * 0b0..An early termination from the device causes error IRQ.
2789 * 0b1..An AHB bus error causes error IRQ.
2790 */
2791#define APBH_CTRL2_TOG_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK)
2792#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK (0x8000000U)
2793#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT (27U)
2794/*! CH11_ERROR_STATUS
2795 * 0b0..An early termination from the device causes error IRQ.
2796 * 0b1..An AHB bus error causes error IRQ.
2797 */
2798#define APBH_CTRL2_TOG_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK)
2799#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK (0x10000000U)
2800#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT (28U)
2801/*! CH12_ERROR_STATUS
2802 * 0b0..An early termination from the device causes error IRQ.
2803 * 0b1..An AHB bus error causes error IRQ.
2804 */
2805#define APBH_CTRL2_TOG_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK)
2806#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK (0x20000000U)
2807#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT (29U)
2808/*! CH13_ERROR_STATUS
2809 * 0b0..An early termination from the device causes error IRQ.
2810 * 0b1..An AHB bus error causes error IRQ.
2811 */
2812#define APBH_CTRL2_TOG_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK)
2813#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK (0x40000000U)
2814#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT (30U)
2815/*! CH14_ERROR_STATUS
2816 * 0b0..An early termination from the device causes error IRQ.
2817 * 0b1..An AHB bus error causes error IRQ.
2818 */
2819#define APBH_CTRL2_TOG_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK)
2820#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK (0x80000000U)
2821#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT (31U)
2822/*! CH15_ERROR_STATUS
2823 * 0b0..An early termination from the device causes error IRQ.
2824 * 0b1..An AHB bus error causes error IRQ.
2825 */
2826#define APBH_CTRL2_TOG_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK)
2827/*! @} */
2828
2829/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */
2830/*! @{ */
2831#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU)
2832#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U)
2833/*! FREEZE_CHANNEL
2834 * 0b0000000000000001..NAND0
2835 * 0b0000000000000010..NAND1
2836 * 0b0000000000000100..NAND2
2837 * 0b0000000000001000..NAND3
2838 * 0b0000000000010000..NAND4
2839 * 0b0000000000100000..NAND5
2840 * 0b0000000001000000..NAND6
2841 * 0b0000000010000000..NAND7
2842 * 0b0000000100000000..SSP
2843 */
2844#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK)
2845#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U)
2846#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U)
2847/*! RESET_CHANNEL
2848 * 0b0000000000000001..NAND0
2849 * 0b0000000000000010..NAND1
2850 * 0b0000000000000100..NAND2
2851 * 0b0000000000001000..NAND3
2852 * 0b0000000000010000..NAND4
2853 * 0b0000000000100000..NAND5
2854 * 0b0000000001000000..NAND6
2855 * 0b0000000010000000..NAND7
2856 * 0b0000000100000000..SSP
2857 */
2858#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK)
2859/*! @} */
2860
2861/*! @name CHANNEL_CTRL_SET - AHB to APBH Bridge Channel Register */
2862/*! @{ */
2863#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK (0xFFFFU)
2864#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT (0U)
2865/*! FREEZE_CHANNEL
2866 * 0b0000000000000001..NAND0
2867 * 0b0000000000000010..NAND1
2868 * 0b0000000000000100..NAND2
2869 * 0b0000000000001000..NAND3
2870 * 0b0000000000010000..NAND4
2871 * 0b0000000000100000..NAND5
2872 * 0b0000000001000000..NAND6
2873 * 0b0000000010000000..NAND7
2874 * 0b0000000100000000..SSP
2875 */
2876#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK)
2877#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK (0xFFFF0000U)
2878#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT (16U)
2879/*! RESET_CHANNEL
2880 * 0b0000000000000001..NAND0
2881 * 0b0000000000000010..NAND1
2882 * 0b0000000000000100..NAND2
2883 * 0b0000000000001000..NAND3
2884 * 0b0000000000010000..NAND4
2885 * 0b0000000000100000..NAND5
2886 * 0b0000000001000000..NAND6
2887 * 0b0000000010000000..NAND7
2888 * 0b0000000100000000..SSP
2889 */
2890#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK)
2891/*! @} */
2892
2893/*! @name CHANNEL_CTRL_CLR - AHB to APBH Bridge Channel Register */
2894/*! @{ */
2895#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK (0xFFFFU)
2896#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT (0U)
2897/*! FREEZE_CHANNEL
2898 * 0b0000000000000001..NAND0
2899 * 0b0000000000000010..NAND1
2900 * 0b0000000000000100..NAND2
2901 * 0b0000000000001000..NAND3
2902 * 0b0000000000010000..NAND4
2903 * 0b0000000000100000..NAND5
2904 * 0b0000000001000000..NAND6
2905 * 0b0000000010000000..NAND7
2906 * 0b0000000100000000..SSP
2907 */
2908#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK)
2909#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK (0xFFFF0000U)
2910#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT (16U)
2911/*! RESET_CHANNEL
2912 * 0b0000000000000001..NAND0
2913 * 0b0000000000000010..NAND1
2914 * 0b0000000000000100..NAND2
2915 * 0b0000000000001000..NAND3
2916 * 0b0000000000010000..NAND4
2917 * 0b0000000000100000..NAND5
2918 * 0b0000000001000000..NAND6
2919 * 0b0000000010000000..NAND7
2920 * 0b0000000100000000..SSP
2921 */
2922#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK)
2923/*! @} */
2924
2925/*! @name CHANNEL_CTRL_TOG - AHB to APBH Bridge Channel Register */
2926/*! @{ */
2927#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK (0xFFFFU)
2928#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT (0U)
2929/*! FREEZE_CHANNEL
2930 * 0b0000000000000001..NAND0
2931 * 0b0000000000000010..NAND1
2932 * 0b0000000000000100..NAND2
2933 * 0b0000000000001000..NAND3
2934 * 0b0000000000010000..NAND4
2935 * 0b0000000000100000..NAND5
2936 * 0b0000000001000000..NAND6
2937 * 0b0000000010000000..NAND7
2938 * 0b0000000100000000..SSP
2939 */
2940#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK)
2941#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK (0xFFFF0000U)
2942#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT (16U)
2943/*! RESET_CHANNEL
2944 * 0b0000000000000001..NAND0
2945 * 0b0000000000000010..NAND1
2946 * 0b0000000000000100..NAND2
2947 * 0b0000000000001000..NAND3
2948 * 0b0000000000010000..NAND4
2949 * 0b0000000000100000..NAND5
2950 * 0b0000000001000000..NAND6
2951 * 0b0000000010000000..NAND7
2952 * 0b0000000100000000..SSP
2953 */
2954#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK)
2955/*! @} */
2956
2957/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */
2958/*! @{ */
2959#define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U)
2960#define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U)
2961#define APBH_DMA_BURST_SIZE_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK)
2962#define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU)
2963#define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U)
2964#define APBH_DMA_BURST_SIZE_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK)
2965#define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U)
2966#define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U)
2967#define APBH_DMA_BURST_SIZE_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK)
2968#define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U)
2969#define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U)
2970#define APBH_DMA_BURST_SIZE_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK)
2971#define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U)
2972#define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U)
2973#define APBH_DMA_BURST_SIZE_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK)
2974#define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U)
2975#define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U)
2976#define APBH_DMA_BURST_SIZE_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK)
2977#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U)
2978#define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U)
2979#define APBH_DMA_BURST_SIZE_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK)
2980#define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U)
2981#define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U)
2982#define APBH_DMA_BURST_SIZE_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK)
2983#define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U)
2984#define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U)
2985/*! CH8
2986 * 0b00..BURST0
2987 * 0b01..BURST4
2988 * 0b10..BURST8
2989 */
2990#define APBH_DMA_BURST_SIZE_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK)
2991/*! @} */
2992
2993/*! @name DEBUG - AHB to APBH DMA Debug Register */
2994/*! @{ */
2995#define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U)
2996#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U)
2997#define APBH_DEBUG_GPMI_ONE_FIFO(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK)
2998/*! @} */
2999
3000/*! @name CH_CURCMDAR - APBH DMA Channel n Current Command Address Register */
3001/*! @{ */
3002#define APBH_CH_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3003#define APBH_CH_CURCMDAR_CMD_ADDR_SHIFT (0U)
3004#define APBH_CH_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_CURCMDAR_CMD_ADDR_MASK)
3005/*! @} */
3006
3007/* The count of APBH_CH_CURCMDAR */
3008#define APBH_CH_CURCMDAR_COUNT (16U)
3009
3010/*! @name CH_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
3011/*! @{ */
3012#define APBH_CH_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3013#define APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT (0U)
3014#define APBH_CH_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_NXTCMDAR_CMD_ADDR_MASK)
3015/*! @} */
3016
3017/* The count of APBH_CH_NXTCMDAR */
3018#define APBH_CH_NXTCMDAR_COUNT (16U)
3019
3020/*! @name CH_CMD - APBH DMA Channel n Command Register */
3021/*! @{ */
3022#define APBH_CH_CMD_COMMAND_MASK (0x3U)
3023#define APBH_CH_CMD_COMMAND_SHIFT (0U)
3024/*! COMMAND
3025 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
3026 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
3027 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
3028 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained
3029 * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain
3030 * pointer if the peripheral sense line is false.
3031 */
3032#define APBH_CH_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_COMMAND_SHIFT)) & APBH_CH_CMD_COMMAND_MASK)
3033#define APBH_CH_CMD_CHAIN_MASK (0x4U)
3034#define APBH_CH_CMD_CHAIN_SHIFT (2U)
3035#define APBH_CH_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CHAIN_SHIFT)) & APBH_CH_CMD_CHAIN_MASK)
3036#define APBH_CH_CMD_IRQONCMPLT_MASK (0x8U)
3037#define APBH_CH_CMD_IRQONCMPLT_SHIFT (3U)
3038#define APBH_CH_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_IRQONCMPLT_SHIFT)) & APBH_CH_CMD_IRQONCMPLT_MASK)
3039#define APBH_CH_CMD_NANDLOCK_MASK (0x10U)
3040#define APBH_CH_CMD_NANDLOCK_SHIFT (4U)
3041#define APBH_CH_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDLOCK_SHIFT)) & APBH_CH_CMD_NANDLOCK_MASK)
3042#define APBH_CH_CMD_NANDWAIT4READY_MASK (0x20U)
3043#define APBH_CH_CMD_NANDWAIT4READY_SHIFT (5U)
3044#define APBH_CH_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH_CMD_NANDWAIT4READY_MASK)
3045#define APBH_CH_CMD_SEMAPHORE_MASK (0x40U)
3046#define APBH_CH_CMD_SEMAPHORE_SHIFT (6U)
3047#define APBH_CH_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_SEMAPHORE_SHIFT)) & APBH_CH_CMD_SEMAPHORE_MASK)
3048#define APBH_CH_CMD_WAIT4ENDCMD_MASK (0x80U)
3049#define APBH_CH_CMD_WAIT4ENDCMD_SHIFT (7U)
3050#define APBH_CH_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH_CMD_WAIT4ENDCMD_MASK)
3051#define APBH_CH_CMD_HALTONTERMINATE_MASK (0x100U)
3052#define APBH_CH_CMD_HALTONTERMINATE_SHIFT (8U)
3053#define APBH_CH_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH_CMD_HALTONTERMINATE_MASK)
3054#define APBH_CH_CMD_CMDWORDS_MASK (0xF000U)
3055#define APBH_CH_CMD_CMDWORDS_SHIFT (12U)
3056#define APBH_CH_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CMDWORDS_SHIFT)) & APBH_CH_CMD_CMDWORDS_MASK)
3057#define APBH_CH_CMD_XFER_COUNT_MASK (0xFFFF0000U)
3058#define APBH_CH_CMD_XFER_COUNT_SHIFT (16U)
3059#define APBH_CH_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_XFER_COUNT_SHIFT)) & APBH_CH_CMD_XFER_COUNT_MASK)
3060/*! @} */
3061
3062/* The count of APBH_CH_CMD */
3063#define APBH_CH_CMD_COUNT (16U)
3064
3065/*! @name CH_BAR - APBH DMA Channel n Buffer Address Register */
3066/*! @{ */
3067#define APBH_CH_BAR_ADDRESS_MASK (0xFFFFFFFFU)
3068#define APBH_CH_BAR_ADDRESS_SHIFT (0U)
3069#define APBH_CH_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_BAR_ADDRESS_SHIFT)) & APBH_CH_BAR_ADDRESS_MASK)
3070/*! @} */
3071
3072/* The count of APBH_CH_BAR */
3073#define APBH_CH_BAR_COUNT (16U)
3074
3075/*! @name CH_SEMA - APBH DMA Channel n Semaphore Register */
3076/*! @{ */
3077#define APBH_CH_SEMA_INCREMENT_SEMA_MASK (0xFFU)
3078#define APBH_CH_SEMA_INCREMENT_SEMA_SHIFT (0U)
3079#define APBH_CH_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH_SEMA_INCREMENT_SEMA_MASK)
3080#define APBH_CH_SEMA_PHORE_MASK (0xFF0000U)
3081#define APBH_CH_SEMA_PHORE_SHIFT (16U)
3082#define APBH_CH_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_PHORE_SHIFT)) & APBH_CH_SEMA_PHORE_MASK)
3083/*! @} */
3084
3085/* The count of APBH_CH_SEMA */
3086#define APBH_CH_SEMA_COUNT (16U)
3087
3088/*! @name CH_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
3089/*! @{ */
3090#define APBH_CH_DEBUG1_STATEMACHINE_MASK (0x1FU)
3091#define APBH_CH_DEBUG1_STATEMACHINE_SHIFT (0U)
3092/*! STATEMACHINE
3093 * 0b00000..This is the idle state of the DMA state machine.
3094 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
3095 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
3096 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
3097 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
3098 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
3099 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the
3100 * PIO words when PIO count is greater than 1.
3101 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
3102 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
3103 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
3104 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3105 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3106 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
3107 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
3108 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
3109 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
3110 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
3111 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and
3112 * effectively halts. A channel reset is required to exit this state
3113 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
3114 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device
3115 * indicates that the external device is ready.
3116 */
3117#define APBH_CH_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH_DEBUG1_STATEMACHINE_MASK)
3118#define APBH_CH_DEBUG1_RSVD1_MASK (0xFFFE0U)
3119#define APBH_CH_DEBUG1_RSVD1_SHIFT (5U)
3120#define APBH_CH_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RSVD1_SHIFT)) & APBH_CH_DEBUG1_RSVD1_MASK)
3121#define APBH_CH_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
3122#define APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
3123#define APBH_CH_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_FULL_MASK)
3124#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
3125#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
3126#define APBH_CH_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK)
3127#define APBH_CH_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
3128#define APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
3129#define APBH_CH_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_FULL_MASK)
3130#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
3131#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
3132#define APBH_CH_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK)
3133#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
3134#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
3135#define APBH_CH_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK)
3136#define APBH_CH_DEBUG1_LOCK_MASK (0x2000000U)
3137#define APBH_CH_DEBUG1_LOCK_SHIFT (25U)
3138#define APBH_CH_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_LOCK_SHIFT)) & APBH_CH_DEBUG1_LOCK_MASK)
3139#define APBH_CH_DEBUG1_READY_MASK (0x4000000U)
3140#define APBH_CH_DEBUG1_READY_SHIFT (26U)
3141#define APBH_CH_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_READY_SHIFT)) & APBH_CH_DEBUG1_READY_MASK)
3142#define APBH_CH_DEBUG1_SENSE_MASK (0x8000000U)
3143#define APBH_CH_DEBUG1_SENSE_SHIFT (27U)
3144#define APBH_CH_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_SENSE_SHIFT)) & APBH_CH_DEBUG1_SENSE_MASK)
3145#define APBH_CH_DEBUG1_END_MASK (0x10000000U)
3146#define APBH_CH_DEBUG1_END_SHIFT (28U)
3147#define APBH_CH_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_END_SHIFT)) & APBH_CH_DEBUG1_END_MASK)
3148#define APBH_CH_DEBUG1_KICK_MASK (0x20000000U)
3149#define APBH_CH_DEBUG1_KICK_SHIFT (29U)
3150#define APBH_CH_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_KICK_SHIFT)) & APBH_CH_DEBUG1_KICK_MASK)
3151#define APBH_CH_DEBUG1_BURST_MASK (0x40000000U)
3152#define APBH_CH_DEBUG1_BURST_SHIFT (30U)
3153#define APBH_CH_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_BURST_SHIFT)) & APBH_CH_DEBUG1_BURST_MASK)
3154#define APBH_CH_DEBUG1_REQ_MASK (0x80000000U)
3155#define APBH_CH_DEBUG1_REQ_SHIFT (31U)
3156#define APBH_CH_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_REQ_SHIFT)) & APBH_CH_DEBUG1_REQ_MASK)
3157/*! @} */
3158
3159/* The count of APBH_CH_DEBUG1 */
3160#define APBH_CH_DEBUG1_COUNT (16U)
3161
3162/*! @name CH_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
3163/*! @{ */
3164#define APBH_CH_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
3165#define APBH_CH_DEBUG2_AHB_BYTES_SHIFT (0U)
3166#define APBH_CH_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH_DEBUG2_AHB_BYTES_MASK)
3167#define APBH_CH_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
3168#define APBH_CH_DEBUG2_APB_BYTES_SHIFT (16U)
3169#define APBH_CH_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH_DEBUG2_APB_BYTES_MASK)
3170/*! @} */
3171
3172/* The count of APBH_CH_DEBUG2 */
3173#define APBH_CH_DEBUG2_COUNT (16U)
3174
3175/*! @name VERSION - APBH Bridge Version Register */
3176/*! @{ */
3177#define APBH_VERSION_STEP_MASK (0xFFFFU)
3178#define APBH_VERSION_STEP_SHIFT (0U)
3179#define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK)
3180#define APBH_VERSION_MINOR_MASK (0xFF0000U)
3181#define APBH_VERSION_MINOR_SHIFT (16U)
3182#define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK)
3183#define APBH_VERSION_MAJOR_MASK (0xFF000000U)
3184#define APBH_VERSION_MAJOR_SHIFT (24U)
3185#define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK)
3186/*! @} */
3187
3188
3189/*!
3190 * @}
3191 */ /* end of group APBH_Register_Masks */
3192
3193
3194/* APBH - Peripheral instance base addresses */
3195/** Peripheral APBH base address */
3196#define APBH_BASE (0x33000000u)
3197/** Peripheral APBH base pointer */
3198#define APBH ((APBH_Type *)APBH_BASE)
3199/** Array initializer of APBH peripheral base addresses */
3200#define APBH_BASE_ADDRS { APBH_BASE }
3201/** Array initializer of APBH peripheral base pointers */
3202#define APBH_BASE_PTRS { APBH }
3203/** Interrupt vectors for the APBH peripheral type */
3204#define APBH_IRQS { APBHDMA_IRQn }
3205
3206/*!
3207 * @}
3208 */ /* end of group APBH_Peripheral_Access_Layer */
3209
3210
3211/* ----------------------------------------------------------------------------
3212 -- BCH Peripheral Access Layer
3213 ---------------------------------------------------------------------------- */
3214
3215/*!
3216 * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer
3217 * @{
3218 */
3219
3220/** BCH - Register Layout Typedef */
3221typedef struct {
3222 __IO uint32_t CTRL; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */
3223 __IO uint32_t CTRL_SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */
3224 __IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */
3225 __IO uint32_t CTRL_TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */
3226 __I uint32_t STATUS0; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */
3227 uint8_t RESERVED_0[12];
3228 __IO uint32_t MODE; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */
3229 uint8_t RESERVED_1[12];
3230 __IO uint32_t ENCODEPTR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */
3231 uint8_t RESERVED_2[12];
3232 __IO uint32_t DATAPTR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */
3233 uint8_t RESERVED_3[12];
3234 __IO uint32_t METAPTR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */
3235 uint8_t RESERVED_4[28];
3236 __IO uint32_t LAYOUTSELECT; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */
3237 uint8_t RESERVED_5[12];
3238 __IO uint32_t FLASH0LAYOUT0; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */
3239 uint8_t RESERVED_6[12];
3240 __IO uint32_t FLASH0LAYOUT1; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */
3241 uint8_t RESERVED_7[12];
3242 __IO uint32_t FLASH1LAYOUT0; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */
3243 uint8_t RESERVED_8[12];
3244 __IO uint32_t FLASH1LAYOUT1; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */
3245 uint8_t RESERVED_9[12];
3246 __IO uint32_t FLASH2LAYOUT0; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */
3247 uint8_t RESERVED_10[12];
3248 __IO uint32_t FLASH2LAYOUT1; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */
3249 uint8_t RESERVED_11[12];
3250 __IO uint32_t FLASH3LAYOUT0; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */
3251 uint8_t RESERVED_12[12];
3252 __IO uint32_t FLASH3LAYOUT1; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */
3253 uint8_t RESERVED_13[12];
3254 __IO uint32_t DEBUG0; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */
3255 __IO uint32_t DEBUG0_SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */
3256 __IO uint32_t DEBUG0_CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */
3257 __IO uint32_t DEBUG0_TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */
3258 __I uint32_t DBGKESREAD; /**< KES Debug Read Register, offset: 0x110 */
3259 uint8_t RESERVED_14[12];
3260 __I uint32_t DBGCSFEREAD; /**< Chien Search Debug Read Register, offset: 0x120 */
3261 uint8_t RESERVED_15[12];
3262 __I uint32_t DBGSYNDGENREAD; /**< Syndrome Generator Debug Read Register, offset: 0x130 */
3263 uint8_t RESERVED_16[12];
3264 __I uint32_t DBGAHBMREAD; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */
3265 uint8_t RESERVED_17[12];
3266 __I uint32_t BLOCKNAME; /**< Block Name Register, offset: 0x150 */
3267 uint8_t RESERVED_18[12];
3268 __I uint32_t VERSION; /**< BCH Version Register, offset: 0x160 */
3269 uint8_t RESERVED_19[12];
3270 __IO uint32_t DEBUG1; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */
3271} BCH_Type;
3272
3273/* ----------------------------------------------------------------------------
3274 -- BCH Register Masks
3275 ---------------------------------------------------------------------------- */
3276
3277/*!
3278 * @addtogroup BCH_Register_Masks BCH Register Masks
3279 * @{
3280 */
3281
3282/*! @name CTRL - Hardware BCH ECC Accelerator Control Register */
3283/*! @{ */
3284#define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U)
3285#define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U)
3286#define BCH_CTRL_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK)
3287#define BCH_CTRL_RSVD0_MASK (0x2U)
3288#define BCH_CTRL_RSVD0_SHIFT (1U)
3289#define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK)
3290#define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U)
3291#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U)
3292#define BCH_CTRL_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK)
3293#define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U)
3294#define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U)
3295#define BCH_CTRL_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK)
3296#define BCH_CTRL_RSVD1_MASK (0xF0U)
3297#define BCH_CTRL_RSVD1_SHIFT (4U)
3298#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK)
3299#define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U)
3300#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U)
3301#define BCH_CTRL_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK)
3302#define BCH_CTRL_RSVD2_MASK (0x200U)
3303#define BCH_CTRL_RSVD2_SHIFT (9U)
3304#define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK)
3305#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U)
3306#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U)
3307#define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK)
3308#define BCH_CTRL_RSVD3_MASK (0xF800U)
3309#define BCH_CTRL_RSVD3_SHIFT (11U)
3310#define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK)
3311#define BCH_CTRL_M2M_ENABLE_MASK (0x10000U)
3312#define BCH_CTRL_M2M_ENABLE_SHIFT (16U)
3313#define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK)
3314#define BCH_CTRL_M2M_ENCODE_MASK (0x20000U)
3315#define BCH_CTRL_M2M_ENCODE_SHIFT (17U)
3316#define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK)
3317#define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U)
3318#define BCH_CTRL_M2M_LAYOUT_SHIFT (18U)
3319#define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK)
3320#define BCH_CTRL_RSVD4_MASK (0x300000U)
3321#define BCH_CTRL_RSVD4_SHIFT (20U)
3322#define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK)
3323#define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U)
3324#define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U)
3325#define BCH_CTRL_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK)
3326#define BCH_CTRL_RSVD5_MASK (0x3F800000U)
3327#define BCH_CTRL_RSVD5_SHIFT (23U)
3328#define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK)
3329#define BCH_CTRL_CLKGATE_MASK (0x40000000U)
3330#define BCH_CTRL_CLKGATE_SHIFT (30U)
3331/*! CLKGATE
3332 * 0b0..Allow BCH to operate normally.
3333 * 0b1..Do not clock BCH gates in order to minimize power consumption.
3334 */
3335#define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK)
3336#define BCH_CTRL_SFTRST_MASK (0x80000000U)
3337#define BCH_CTRL_SFTRST_SHIFT (31U)
3338/*! SFTRST
3339 * 0b0..Allow BCH to operate normally.
3340 * 0b1..Hold BCH in reset.
3341 */
3342#define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK)
3343/*! @} */
3344
3345/*! @name CTRL_SET - Hardware BCH ECC Accelerator Control Register */
3346/*! @{ */
3347#define BCH_CTRL_SET_COMPLETE_IRQ_MASK (0x1U)
3348#define BCH_CTRL_SET_COMPLETE_IRQ_SHIFT (0U)
3349#define BCH_CTRL_SET_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_MASK)
3350#define BCH_CTRL_SET_RSVD0_MASK (0x2U)
3351#define BCH_CTRL_SET_RSVD0_SHIFT (1U)
3352#define BCH_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD0_SHIFT)) & BCH_CTRL_SET_RSVD0_MASK)
3353#define BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK (0x4U)
3354#define BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT (2U)
3355#define BCH_CTRL_SET_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK)
3356#define BCH_CTRL_SET_BM_ERROR_IRQ_MASK (0x8U)
3357#define BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT (3U)
3358#define BCH_CTRL_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_SET_BM_ERROR_IRQ_MASK)
3359#define BCH_CTRL_SET_RSVD1_MASK (0xF0U)
3360#define BCH_CTRL_SET_RSVD1_SHIFT (4U)
3361#define BCH_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD1_SHIFT)) & BCH_CTRL_SET_RSVD1_MASK)
3362#define BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK (0x100U)
3363#define BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT (8U)
3364#define BCH_CTRL_SET_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK)
3365#define BCH_CTRL_SET_RSVD2_MASK (0x200U)
3366#define BCH_CTRL_SET_RSVD2_SHIFT (9U)
3367#define BCH_CTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD2_SHIFT)) & BCH_CTRL_SET_RSVD2_MASK)
3368#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK (0x400U)
3369#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT (10U)
3370#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK)
3371#define BCH_CTRL_SET_RSVD3_MASK (0xF800U)
3372#define BCH_CTRL_SET_RSVD3_SHIFT (11U)
3373#define BCH_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD3_SHIFT)) & BCH_CTRL_SET_RSVD3_MASK)
3374#define BCH_CTRL_SET_M2M_ENABLE_MASK (0x10000U)
3375#define BCH_CTRL_SET_M2M_ENABLE_SHIFT (16U)
3376#define BCH_CTRL_SET_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENABLE_SHIFT)) & BCH_CTRL_SET_M2M_ENABLE_MASK)
3377#define BCH_CTRL_SET_M2M_ENCODE_MASK (0x20000U)
3378#define BCH_CTRL_SET_M2M_ENCODE_SHIFT (17U)
3379#define BCH_CTRL_SET_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENCODE_SHIFT)) & BCH_CTRL_SET_M2M_ENCODE_MASK)
3380#define BCH_CTRL_SET_M2M_LAYOUT_MASK (0xC0000U)
3381#define BCH_CTRL_SET_M2M_LAYOUT_SHIFT (18U)
3382#define BCH_CTRL_SET_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_LAYOUT_SHIFT)) & BCH_CTRL_SET_M2M_LAYOUT_MASK)
3383#define BCH_CTRL_SET_RSVD4_MASK (0x300000U)
3384#define BCH_CTRL_SET_RSVD4_SHIFT (20U)
3385#define BCH_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD4_SHIFT)) & BCH_CTRL_SET_RSVD4_MASK)
3386#define BCH_CTRL_SET_DEBUGSYNDROME_MASK (0x400000U)
3387#define BCH_CTRL_SET_DEBUGSYNDROME_SHIFT (22U)
3388#define BCH_CTRL_SET_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_SET_DEBUGSYNDROME_MASK)
3389#define BCH_CTRL_SET_RSVD5_MASK (0x3F800000U)
3390#define BCH_CTRL_SET_RSVD5_SHIFT (23U)
3391#define BCH_CTRL_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD5_SHIFT)) & BCH_CTRL_SET_RSVD5_MASK)
3392#define BCH_CTRL_SET_CLKGATE_MASK (0x40000000U)
3393#define BCH_CTRL_SET_CLKGATE_SHIFT (30U)
3394/*! CLKGATE
3395 * 0b0..Allow BCH to operate normally.
3396 * 0b1..Do not clock BCH gates in order to minimize power consumption.
3397 */
3398#define BCH_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_CLKGATE_SHIFT)) & BCH_CTRL_SET_CLKGATE_MASK)
3399#define BCH_CTRL_SET_SFTRST_MASK (0x80000000U)
3400#define BCH_CTRL_SET_SFTRST_SHIFT (31U)
3401/*! SFTRST
3402 * 0b0..Allow BCH to operate normally.
3403 * 0b1..Hold BCH in reset.
3404 */
3405#define BCH_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_SFTRST_SHIFT)) & BCH_CTRL_SET_SFTRST_MASK)
3406/*! @} */
3407
3408/*! @name CTRL_CLR - Hardware BCH ECC Accelerator Control Register */
3409/*! @{ */
3410#define BCH_CTRL_CLR_COMPLETE_IRQ_MASK (0x1U)
3411#define BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT (0U)
3412#define BCH_CTRL_CLR_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_MASK)
3413#define BCH_CTRL_CLR_RSVD0_MASK (0x2U)
3414#define BCH_CTRL_CLR_RSVD0_SHIFT (1U)
3415#define BCH_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD0_SHIFT)) & BCH_CTRL_CLR_RSVD0_MASK)
3416#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK (0x4U)
3417#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT (2U)
3418#define BCH_CTRL_CLR_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK)
3419#define BCH_CTRL_CLR_BM_ERROR_IRQ_MASK (0x8U)
3420#define BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT (3U)
3421#define BCH_CTRL_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_CLR_BM_ERROR_IRQ_MASK)
3422#define BCH_CTRL_CLR_RSVD1_MASK (0xF0U)
3423#define BCH_CTRL_CLR_RSVD1_SHIFT (4U)
3424#define BCH_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD1_SHIFT)) & BCH_CTRL_CLR_RSVD1_MASK)
3425#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK (0x100U)
3426#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT (8U)
3427#define BCH_CTRL_CLR_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK)
3428#define BCH_CTRL_CLR_RSVD2_MASK (0x200U)
3429#define BCH_CTRL_CLR_RSVD2_SHIFT (9U)
3430#define BCH_CTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD2_SHIFT)) & BCH_CTRL_CLR_RSVD2_MASK)
3431#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK (0x400U)
3432#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT (10U)
3433#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK)
3434#define BCH_CTRL_CLR_RSVD3_MASK (0xF800U)
3435#define BCH_CTRL_CLR_RSVD3_SHIFT (11U)
3436#define BCH_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD3_SHIFT)) & BCH_CTRL_CLR_RSVD3_MASK)
3437#define BCH_CTRL_CLR_M2M_ENABLE_MASK (0x10000U)
3438#define BCH_CTRL_CLR_M2M_ENABLE_SHIFT (16U)
3439#define BCH_CTRL_CLR_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENABLE_SHIFT)) & BCH_CTRL_CLR_M2M_ENABLE_MASK)
3440#define BCH_CTRL_CLR_M2M_ENCODE_MASK (0x20000U)
3441#define BCH_CTRL_CLR_M2M_ENCODE_SHIFT (17U)
3442#define BCH_CTRL_CLR_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENCODE_SHIFT)) & BCH_CTRL_CLR_M2M_ENCODE_MASK)
3443#define BCH_CTRL_CLR_M2M_LAYOUT_MASK (0xC0000U)
3444#define BCH_CTRL_CLR_M2M_LAYOUT_SHIFT (18U)
3445#define BCH_CTRL_CLR_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_LAYOUT_SHIFT)) & BCH_CTRL_CLR_M2M_LAYOUT_MASK)
3446#define BCH_CTRL_CLR_RSVD4_MASK (0x300000U)
3447#define BCH_CTRL_CLR_RSVD4_SHIFT (20U)
3448#define BCH_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD4_SHIFT)) & BCH_CTRL_CLR_RSVD4_MASK)
3449#define BCH_CTRL_CLR_DEBUGSYNDROME_MASK (0x400000U)
3450#define BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT (22U)
3451#define BCH_CTRL_CLR_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_CLR_DEBUGSYNDROME_MASK)
3452#define BCH_CTRL_CLR_RSVD5_MASK (0x3F800000U)
3453#define BCH_CTRL_CLR_RSVD5_SHIFT (23U)
3454#define BCH_CTRL_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD5_SHIFT)) & BCH_CTRL_CLR_RSVD5_MASK)
3455#define BCH_CTRL_CLR_CLKGATE_MASK (0x40000000U)
3456#define BCH_CTRL_CLR_CLKGATE_SHIFT (30U)
3457/*! CLKGATE
3458 * 0b0..Allow BCH to operate normally.
3459 * 0b1..Do not clock BCH gates in order to minimize power consumption.
3460 */
3461#define BCH_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_CLKGATE_SHIFT)) & BCH_CTRL_CLR_CLKGATE_MASK)
3462#define BCH_CTRL_CLR_SFTRST_MASK (0x80000000U)
3463#define BCH_CTRL_CLR_SFTRST_SHIFT (31U)
3464/*! SFTRST
3465 * 0b0..Allow BCH to operate normally.
3466 * 0b1..Hold BCH in reset.
3467 */
3468#define BCH_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_SFTRST_SHIFT)) & BCH_CTRL_CLR_SFTRST_MASK)
3469/*! @} */
3470
3471/*! @name CTRL_TOG - Hardware BCH ECC Accelerator Control Register */
3472/*! @{ */
3473#define BCH_CTRL_TOG_COMPLETE_IRQ_MASK (0x1U)
3474#define BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT (0U)
3475#define BCH_CTRL_TOG_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_MASK)
3476#define BCH_CTRL_TOG_RSVD0_MASK (0x2U)
3477#define BCH_CTRL_TOG_RSVD0_SHIFT (1U)
3478#define BCH_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD0_SHIFT)) & BCH_CTRL_TOG_RSVD0_MASK)
3479#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK (0x4U)
3480#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT (2U)
3481#define BCH_CTRL_TOG_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK)
3482#define BCH_CTRL_TOG_BM_ERROR_IRQ_MASK (0x8U)
3483#define BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT (3U)
3484#define BCH_CTRL_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_TOG_BM_ERROR_IRQ_MASK)
3485#define BCH_CTRL_TOG_RSVD1_MASK (0xF0U)
3486#define BCH_CTRL_TOG_RSVD1_SHIFT (4U)
3487#define BCH_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD1_SHIFT)) & BCH_CTRL_TOG_RSVD1_MASK)
3488#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK (0x100U)
3489#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT (8U)
3490#define BCH_CTRL_TOG_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK)
3491#define BCH_CTRL_TOG_RSVD2_MASK (0x200U)
3492#define BCH_CTRL_TOG_RSVD2_SHIFT (9U)
3493#define BCH_CTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD2_SHIFT)) & BCH_CTRL_TOG_RSVD2_MASK)
3494#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK (0x400U)
3495#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT (10U)
3496#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK)
3497#define BCH_CTRL_TOG_RSVD3_MASK (0xF800U)
3498#define BCH_CTRL_TOG_RSVD3_SHIFT (11U)
3499#define BCH_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD3_SHIFT)) & BCH_CTRL_TOG_RSVD3_MASK)
3500#define BCH_CTRL_TOG_M2M_ENABLE_MASK (0x10000U)
3501#define BCH_CTRL_TOG_M2M_ENABLE_SHIFT (16U)
3502#define BCH_CTRL_TOG_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENABLE_SHIFT)) & BCH_CTRL_TOG_M2M_ENABLE_MASK)
3503#define BCH_CTRL_TOG_M2M_ENCODE_MASK (0x20000U)
3504#define BCH_CTRL_TOG_M2M_ENCODE_SHIFT (17U)
3505#define BCH_CTRL_TOG_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENCODE_SHIFT)) & BCH_CTRL_TOG_M2M_ENCODE_MASK)
3506#define BCH_CTRL_TOG_M2M_LAYOUT_MASK (0xC0000U)
3507#define BCH_CTRL_TOG_M2M_LAYOUT_SHIFT (18U)
3508#define BCH_CTRL_TOG_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_LAYOUT_SHIFT)) & BCH_CTRL_TOG_M2M_LAYOUT_MASK)
3509#define BCH_CTRL_TOG_RSVD4_MASK (0x300000U)
3510#define BCH_CTRL_TOG_RSVD4_SHIFT (20U)
3511#define BCH_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD4_SHIFT)) & BCH_CTRL_TOG_RSVD4_MASK)
3512#define BCH_CTRL_TOG_DEBUGSYNDROME_MASK (0x400000U)
3513#define BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT (22U)
3514#define BCH_CTRL_TOG_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_TOG_DEBUGSYNDROME_MASK)
3515#define BCH_CTRL_TOG_RSVD5_MASK (0x3F800000U)
3516#define BCH_CTRL_TOG_RSVD5_SHIFT (23U)
3517#define BCH_CTRL_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD5_SHIFT)) & BCH_CTRL_TOG_RSVD5_MASK)
3518#define BCH_CTRL_TOG_CLKGATE_MASK (0x40000000U)
3519#define BCH_CTRL_TOG_CLKGATE_SHIFT (30U)
3520/*! CLKGATE
3521 * 0b0..Allow BCH to operate normally.
3522 * 0b1..Do not clock BCH gates in order to minimize power consumption.
3523 */
3524#define BCH_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_CLKGATE_SHIFT)) & BCH_CTRL_TOG_CLKGATE_MASK)
3525#define BCH_CTRL_TOG_SFTRST_MASK (0x80000000U)
3526#define BCH_CTRL_TOG_SFTRST_SHIFT (31U)
3527/*! SFTRST
3528 * 0b0..Allow BCH to operate normally.
3529 * 0b1..Hold BCH in reset.
3530 */
3531#define BCH_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_SFTRST_SHIFT)) & BCH_CTRL_TOG_SFTRST_MASK)
3532/*! @} */
3533
3534/*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */
3535/*! @{ */
3536#define BCH_STATUS0_RSVD0_MASK (0x3U)
3537#define BCH_STATUS0_RSVD0_SHIFT (0U)
3538#define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK)
3539#define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U)
3540#define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U)
3541#define BCH_STATUS0_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK)
3542#define BCH_STATUS0_CORRECTED_MASK (0x8U)
3543#define BCH_STATUS0_CORRECTED_SHIFT (3U)
3544#define BCH_STATUS0_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK)
3545#define BCH_STATUS0_ALLONES_MASK (0x10U)
3546#define BCH_STATUS0_ALLONES_SHIFT (4U)
3547#define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK)
3548#define BCH_STATUS0_RSVD1_MASK (0xE0U)
3549#define BCH_STATUS0_RSVD1_SHIFT (5U)
3550#define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK)
3551#define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U)
3552#define BCH_STATUS0_STATUS_BLK0_SHIFT (8U)
3553/*! STATUS_BLK0
3554 * 0b00000000..No errors found on block.
3555 * 0b00000001..One error found on block.
3556 * 0b00000010..One errors found on block.
3557 * 0b00000011..One errors found on block.
3558 * 0b00000100..One errors found on block.
3559 * 0b11111110..Block exhibited uncorrectable errors.
3560 * 0b11111111..Page is erased.
3561 */
3562#define BCH_STATUS0_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK)
3563#define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U)
3564#define BCH_STATUS0_COMPLETED_CE_SHIFT (16U)
3565#define BCH_STATUS0_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK)
3566#define BCH_STATUS0_HANDLE_MASK (0xFFF00000U)
3567#define BCH_STATUS0_HANDLE_SHIFT (20U)
3568#define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK)
3569/*! @} */
3570
3571/*! @name MODE - Hardware ECC Accelerator Mode Register */
3572/*! @{ */
3573#define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU)
3574#define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U)
3575#define BCH_MODE_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK)
3576#define BCH_MODE_RSVD_MASK (0xFFFFFF00U)
3577#define BCH_MODE_RSVD_SHIFT (8U)
3578#define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK)
3579/*! @} */
3580
3581/*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */
3582/*! @{ */
3583#define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU)
3584#define BCH_ENCODEPTR_ADDR_SHIFT (0U)
3585#define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK)
3586/*! @} */
3587
3588/*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */
3589/*! @{ */
3590#define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU)
3591#define BCH_DATAPTR_ADDR_SHIFT (0U)
3592#define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK)
3593/*! @} */
3594
3595/*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */
3596/*! @{ */
3597#define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU)
3598#define BCH_METAPTR_ADDR_SHIFT (0U)
3599#define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK)
3600/*! @} */
3601
3602/*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */
3603/*! @{ */
3604#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U)
3605#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U)
3606#define BCH_LAYOUTSELECT_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK)
3607#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU)
3608#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U)
3609#define BCH_LAYOUTSELECT_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK)
3610#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U)
3611#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U)
3612#define BCH_LAYOUTSELECT_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK)
3613#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U)
3614#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U)
3615#define BCH_LAYOUTSELECT_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK)
3616#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U)
3617#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U)
3618#define BCH_LAYOUTSELECT_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK)
3619#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U)
3620#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U)
3621#define BCH_LAYOUTSELECT_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK)
3622#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U)
3623#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U)
3624#define BCH_LAYOUTSELECT_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK)
3625#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U)
3626#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U)
3627#define BCH_LAYOUTSELECT_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK)
3628#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U)
3629#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U)
3630#define BCH_LAYOUTSELECT_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK)
3631#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U)
3632#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U)
3633#define BCH_LAYOUTSELECT_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK)
3634#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U)
3635#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U)
3636#define BCH_LAYOUTSELECT_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK)
3637#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U)
3638#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U)
3639#define BCH_LAYOUTSELECT_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK)
3640#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U)
3641#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U)
3642#define BCH_LAYOUTSELECT_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK)
3643#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U)
3644#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U)
3645#define BCH_LAYOUTSELECT_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK)
3646#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U)
3647#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U)
3648#define BCH_LAYOUTSELECT_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK)
3649#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U)
3650#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U)
3651#define BCH_LAYOUTSELECT_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK)
3652/*! @} */
3653
3654/*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */
3655/*! @{ */
3656#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
3657#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U)
3658#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK)
3659#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
3660#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
3661#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK)
3662#define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF800U)
3663#define BCH_FLASH0LAYOUT0_ECC0_SHIFT (11U)
3664/*! ECC0
3665 * 0b00000..No ECC to be performed
3666 * 0b00001..ECC 2 to be performed
3667 * 0b00010..ECC 4 to be performed
3668 * 0b11110..ECC 60 to be performed
3669 * 0b11111..ECC 62 to be performed
3670 */
3671#define BCH_FLASH0LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK)
3672#define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U)
3673#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U)
3674#define BCH_FLASH0LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK)
3675#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U)
3676#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U)
3677#define BCH_FLASH0LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK)
3678/*! @} */
3679
3680/*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */
3681/*! @{ */
3682#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
3683#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U)
3684#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK)
3685#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
3686#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
3687#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK)
3688#define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF800U)
3689#define BCH_FLASH0LAYOUT1_ECCN_SHIFT (11U)
3690/*! ECCN
3691 * 0b00000..No ECC to be performed
3692 * 0b00001..ECC 2 to be performed
3693 * 0b00010..ECC 4 to be performed
3694 * 0b11110..ECC 60 to be performed
3695 * 0b11111..ECC 62 to be performed
3696 */
3697#define BCH_FLASH0LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK)
3698#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
3699#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U)
3700#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK)
3701/*! @} */
3702
3703/*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */
3704/*! @{ */
3705#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
3706#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U)
3707#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK)
3708#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
3709#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
3710#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK)
3711#define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF800U)
3712#define BCH_FLASH1LAYOUT0_ECC0_SHIFT (11U)
3713/*! ECC0
3714 * 0b00000..No ECC to be performed
3715 * 0b00001..ECC 2 to be performed
3716 * 0b00010..ECC 4 to be performed
3717 * 0b11110..ECC 60 to be performed
3718 * 0b11111..ECC 62 to be performed
3719 */
3720#define BCH_FLASH1LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK)
3721#define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U)
3722#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U)
3723#define BCH_FLASH1LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK)
3724#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U)
3725#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U)
3726#define BCH_FLASH1LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK)
3727/*! @} */
3728
3729/*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */
3730/*! @{ */
3731#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
3732#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U)
3733#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK)
3734#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
3735#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
3736#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK)
3737#define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF800U)
3738#define BCH_FLASH1LAYOUT1_ECCN_SHIFT (11U)
3739/*! ECCN
3740 * 0b00000..No ECC to be performed
3741 * 0b00001..ECC 2 to be performed
3742 * 0b00010..ECC 4 to be performed
3743 * 0b11110..ECC 60 to be performed
3744 * 0b11111..ECC 62 to be performed
3745 */
3746#define BCH_FLASH1LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK)
3747#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
3748#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U)
3749#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK)
3750/*! @} */
3751
3752/*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */
3753/*! @{ */
3754#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
3755#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U)
3756#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK)
3757#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
3758#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
3759#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK)
3760#define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF800U)
3761#define BCH_FLASH2LAYOUT0_ECC0_SHIFT (11U)
3762/*! ECC0
3763 * 0b00000..No ECC to be performed
3764 * 0b00001..ECC 2 to be performed
3765 * 0b00010..ECC 4 to be performed
3766 * 0b11110..ECC 60 to be performed
3767 * 0b11111..ECC 62 to be performed
3768 */
3769#define BCH_FLASH2LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK)
3770#define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U)
3771#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U)
3772#define BCH_FLASH2LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK)
3773#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U)
3774#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U)
3775#define BCH_FLASH2LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK)
3776/*! @} */
3777
3778/*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */
3779/*! @{ */
3780#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
3781#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U)
3782#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK)
3783#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
3784#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
3785#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK)
3786#define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF800U)
3787#define BCH_FLASH2LAYOUT1_ECCN_SHIFT (11U)
3788/*! ECCN
3789 * 0b00000..No ECC to be performed
3790 * 0b00001..ECC 2 to be performed
3791 * 0b00010..ECC 4 to be performed
3792 * 0b11110..ECC 60 to be performed
3793 * 0b11111..ECC 62 to be performed
3794 */
3795#define BCH_FLASH2LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK)
3796#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
3797#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U)
3798#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK)
3799/*! @} */
3800
3801/*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */
3802/*! @{ */
3803#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
3804#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U)
3805#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK)
3806#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
3807#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
3808#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK)
3809#define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF800U)
3810#define BCH_FLASH3LAYOUT0_ECC0_SHIFT (11U)
3811/*! ECC0
3812 * 0b00000..No ECC to be performed
3813 * 0b00001..ECC 2 to be performed
3814 * 0b00010..ECC 4 to be performed
3815 * 0b11110..ECC 60 to be performed
3816 * 0b11111..ECC 62 to be performed
3817 */
3818#define BCH_FLASH3LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK)
3819#define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U)
3820#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U)
3821#define BCH_FLASH3LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK)
3822#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U)
3823#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U)
3824#define BCH_FLASH3LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK)
3825/*! @} */
3826
3827/*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */
3828/*! @{ */
3829#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
3830#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U)
3831#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK)
3832#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
3833#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
3834#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK)
3835#define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF800U)
3836#define BCH_FLASH3LAYOUT1_ECCN_SHIFT (11U)
3837/*! ECCN
3838 * 0b00000..No ECC to be performed
3839 * 0b00001..ECC 2 to be performed
3840 * 0b00010..ECC 4 to be performed
3841 * 0b11110..ECC 60 to be performed
3842 * 0b11111..ECC 62 to be performed
3843 */
3844#define BCH_FLASH3LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK)
3845#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
3846#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U)
3847#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK)
3848/*! @} */
3849
3850/*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */
3851/*! @{ */
3852#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU)
3853#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U)
3854#define BCH_DEBUG0_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK)
3855#define BCH_DEBUG0_RSVD0_MASK (0xC0U)
3856#define BCH_DEBUG0_RSVD0_SHIFT (6U)
3857#define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK)
3858#define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK (0x100U)
3859#define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT (8U)
3860/*! BM_KES_TEST_BYPASS
3861 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
3862 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
3863 */
3864#define BCH_DEBUG0_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK)
3865#define BCH_DEBUG0_KES_DEBUG_STALL_MASK (0x200U)
3866#define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT (9U)
3867/*! KES_DEBUG_STALL
3868 * 0b0..KES FSM proceeds to next block supplied by bus master.
3869 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
3870 */
3871#define BCH_DEBUG0_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK)
3872#define BCH_DEBUG0_KES_DEBUG_STEP_MASK (0x400U)
3873#define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT (10U)
3874#define BCH_DEBUG0_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK)
3875#define BCH_DEBUG0_KES_STANDALONE_MASK (0x800U)
3876#define BCH_DEBUG0_KES_STANDALONE_SHIFT (11U)
3877/*! KES_STANDALONE
3878 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
3879 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
3880 */
3881#define BCH_DEBUG0_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK)
3882#define BCH_DEBUG0_KES_DEBUG_KICK_MASK (0x1000U)
3883#define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT (12U)
3884#define BCH_DEBUG0_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK)
3885#define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK (0x2000U)
3886#define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT (13U)
3887/*! KES_DEBUG_MODE4K
3888 * 0b1..Mode is set for 4K NAND pages.
3889 * 0b1..Mode is set for 2K NAND pages.
3890 */
3891#define BCH_DEBUG0_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK)
3892#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
3893#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
3894/*! KES_DEBUG_PAYLOAD_FLAG
3895 * 0b1..Payload is set for 512 bytes data block.
3896 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
3897 */
3898#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK)
3899#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
3900#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
3901#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK)
3902#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
3903#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
3904/*! KES_DEBUG_SYNDROME_SYMBOL
3905 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
3906 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
3907 */
3908#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK)
3909#define BCH_DEBUG0_RSVD1_MASK (0xFE000000U)
3910#define BCH_DEBUG0_RSVD1_SHIFT (25U)
3911#define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK)
3912/*! @} */
3913
3914/*! @name DEBUG0_SET - Hardware BCH ECC Debug Register0 */
3915/*! @{ */
3916#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK (0x3FU)
3917#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT (0U)
3918#define BCH_DEBUG0_SET_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK)
3919#define BCH_DEBUG0_SET_RSVD0_MASK (0xC0U)
3920#define BCH_DEBUG0_SET_RSVD0_SHIFT (6U)
3921#define BCH_DEBUG0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD0_SHIFT)) & BCH_DEBUG0_SET_RSVD0_MASK)
3922#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK (0x100U)
3923#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT (8U)
3924/*! BM_KES_TEST_BYPASS
3925 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
3926 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
3927 */
3928#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK)
3929#define BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK (0x200U)
3930#define BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT (9U)
3931/*! KES_DEBUG_STALL
3932 * 0b0..KES FSM proceeds to next block supplied by bus master.
3933 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
3934 */
3935#define BCH_DEBUG0_SET_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK)
3936#define BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK (0x400U)
3937#define BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT (10U)
3938#define BCH_DEBUG0_SET_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK)
3939#define BCH_DEBUG0_SET_KES_STANDALONE_MASK (0x800U)
3940#define BCH_DEBUG0_SET_KES_STANDALONE_SHIFT (11U)
3941/*! KES_STANDALONE
3942 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
3943 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
3944 */
3945#define BCH_DEBUG0_SET_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_SET_KES_STANDALONE_MASK)
3946#define BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK (0x1000U)
3947#define BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT (12U)
3948#define BCH_DEBUG0_SET_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK)
3949#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK (0x2000U)
3950#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT (13U)
3951/*! KES_DEBUG_MODE4K
3952 * 0b1..Mode is set for 4K NAND pages.
3953 * 0b1..Mode is set for 2K NAND pages.
3954 */
3955#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK)
3956#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
3957#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
3958/*! KES_DEBUG_PAYLOAD_FLAG
3959 * 0b1..Payload is set for 512 bytes data block.
3960 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
3961 */
3962#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK)
3963#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
3964#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
3965#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK)
3966#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
3967#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
3968/*! KES_DEBUG_SYNDROME_SYMBOL
3969 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
3970 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
3971 */
3972#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK)
3973#define BCH_DEBUG0_SET_RSVD1_MASK (0xFE000000U)
3974#define BCH_DEBUG0_SET_RSVD1_SHIFT (25U)
3975#define BCH_DEBUG0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD1_SHIFT)) & BCH_DEBUG0_SET_RSVD1_MASK)
3976/*! @} */
3977
3978/*! @name DEBUG0_CLR - Hardware BCH ECC Debug Register0 */
3979/*! @{ */
3980#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK (0x3FU)
3981#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT (0U)
3982#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK)
3983#define BCH_DEBUG0_CLR_RSVD0_MASK (0xC0U)
3984#define BCH_DEBUG0_CLR_RSVD0_SHIFT (6U)
3985#define BCH_DEBUG0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD0_SHIFT)) & BCH_DEBUG0_CLR_RSVD0_MASK)
3986#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK (0x100U)
3987#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT (8U)
3988/*! BM_KES_TEST_BYPASS
3989 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
3990 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
3991 */
3992#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK)
3993#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK (0x200U)
3994#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT (9U)
3995/*! KES_DEBUG_STALL
3996 * 0b0..KES FSM proceeds to next block supplied by bus master.
3997 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
3998 */
3999#define BCH_DEBUG0_CLR_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK)
4000#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK (0x400U)
4001#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT (10U)
4002#define BCH_DEBUG0_CLR_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK)
4003#define BCH_DEBUG0_CLR_KES_STANDALONE_MASK (0x800U)
4004#define BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT (11U)
4005/*! KES_STANDALONE
4006 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
4007 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
4008 */
4009#define BCH_DEBUG0_CLR_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_CLR_KES_STANDALONE_MASK)
4010#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK (0x1000U)
4011#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT (12U)
4012#define BCH_DEBUG0_CLR_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK)
4013#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK (0x2000U)
4014#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT (13U)
4015/*! KES_DEBUG_MODE4K
4016 * 0b1..Mode is set for 4K NAND pages.
4017 * 0b1..Mode is set for 2K NAND pages.
4018 */
4019#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK)
4020#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
4021#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
4022/*! KES_DEBUG_PAYLOAD_FLAG
4023 * 0b1..Payload is set for 512 bytes data block.
4024 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
4025 */
4026#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK)
4027#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
4028#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
4029#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK)
4030#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
4031#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
4032/*! KES_DEBUG_SYNDROME_SYMBOL
4033 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
4034 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
4035 */
4036#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK)
4037#define BCH_DEBUG0_CLR_RSVD1_MASK (0xFE000000U)
4038#define BCH_DEBUG0_CLR_RSVD1_SHIFT (25U)
4039#define BCH_DEBUG0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD1_SHIFT)) & BCH_DEBUG0_CLR_RSVD1_MASK)
4040/*! @} */
4041
4042/*! @name DEBUG0_TOG - Hardware BCH ECC Debug Register0 */
4043/*! @{ */
4044#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK (0x3FU)
4045#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT (0U)
4046#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK)
4047#define BCH_DEBUG0_TOG_RSVD0_MASK (0xC0U)
4048#define BCH_DEBUG0_TOG_RSVD0_SHIFT (6U)
4049#define BCH_DEBUG0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD0_SHIFT)) & BCH_DEBUG0_TOG_RSVD0_MASK)
4050#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK (0x100U)
4051#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT (8U)
4052/*! BM_KES_TEST_BYPASS
4053 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
4054 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
4055 */
4056#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK)
4057#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK (0x200U)
4058#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT (9U)
4059/*! KES_DEBUG_STALL
4060 * 0b0..KES FSM proceeds to next block supplied by bus master.
4061 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
4062 */
4063#define BCH_DEBUG0_TOG_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK)
4064#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK (0x400U)
4065#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT (10U)
4066#define BCH_DEBUG0_TOG_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK)
4067#define BCH_DEBUG0_TOG_KES_STANDALONE_MASK (0x800U)
4068#define BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT (11U)
4069/*! KES_STANDALONE
4070 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
4071 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
4072 */
4073#define BCH_DEBUG0_TOG_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_TOG_KES_STANDALONE_MASK)
4074#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK (0x1000U)
4075#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT (12U)
4076#define BCH_DEBUG0_TOG_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK)
4077#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK (0x2000U)
4078#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT (13U)
4079/*! KES_DEBUG_MODE4K
4080 * 0b1..Mode is set for 4K NAND pages.
4081 * 0b1..Mode is set for 2K NAND pages.
4082 */
4083#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK)
4084#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
4085#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
4086/*! KES_DEBUG_PAYLOAD_FLAG
4087 * 0b1..Payload is set for 512 bytes data block.
4088 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
4089 */
4090#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK)
4091#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
4092#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
4093#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK)
4094#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
4095#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
4096/*! KES_DEBUG_SYNDROME_SYMBOL
4097 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
4098 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
4099 */
4100#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK)
4101#define BCH_DEBUG0_TOG_RSVD1_MASK (0xFE000000U)
4102#define BCH_DEBUG0_TOG_RSVD1_SHIFT (25U)
4103#define BCH_DEBUG0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD1_SHIFT)) & BCH_DEBUG0_TOG_RSVD1_MASK)
4104/*! @} */
4105
4106/*! @name DBGKESREAD - KES Debug Read Register */
4107/*! @{ */
4108#define BCH_DBGKESREAD_VALUES_MASK (0xFFFFFFFFU)
4109#define BCH_DBGKESREAD_VALUES_SHIFT (0U)
4110#define BCH_DBGKESREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK)
4111/*! @} */
4112
4113/*! @name DBGCSFEREAD - Chien Search Debug Read Register */
4114/*! @{ */
4115#define BCH_DBGCSFEREAD_VALUES_MASK (0xFFFFFFFFU)
4116#define BCH_DBGCSFEREAD_VALUES_SHIFT (0U)
4117#define BCH_DBGCSFEREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK)
4118/*! @} */
4119
4120/*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */
4121/*! @{ */
4122#define BCH_DBGSYNDGENREAD_VALUES_MASK (0xFFFFFFFFU)
4123#define BCH_DBGSYNDGENREAD_VALUES_SHIFT (0U)
4124#define BCH_DBGSYNDGENREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK)
4125/*! @} */
4126
4127/*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */
4128/*! @{ */
4129#define BCH_DBGAHBMREAD_VALUES_MASK (0xFFFFFFFFU)
4130#define BCH_DBGAHBMREAD_VALUES_SHIFT (0U)
4131#define BCH_DBGAHBMREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK)
4132/*! @} */
4133
4134/*! @name BLOCKNAME - Block Name Register */
4135/*! @{ */
4136#define BCH_BLOCKNAME_NAME_MASK (0xFFFFFFFFU)
4137#define BCH_BLOCKNAME_NAME_SHIFT (0U)
4138#define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK)
4139/*! @} */
4140
4141/*! @name VERSION - BCH Version Register */
4142/*! @{ */
4143#define BCH_VERSION_STEP_MASK (0xFFFFU)
4144#define BCH_VERSION_STEP_SHIFT (0U)
4145#define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK)
4146#define BCH_VERSION_MINOR_MASK (0xFF0000U)
4147#define BCH_VERSION_MINOR_SHIFT (16U)
4148#define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK)
4149#define BCH_VERSION_MAJOR_MASK (0xFF000000U)
4150#define BCH_VERSION_MAJOR_SHIFT (24U)
4151#define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK)
4152/*! @} */
4153
4154/*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */
4155/*! @{ */
4156#define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK (0x1FFU)
4157#define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT (0U)
4158#define BCH_DEBUG1_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK)
4159#define BCH_DEBUG1_RSVD_MASK (0x7FFFFE00U)
4160#define BCH_DEBUG1_RSVD_SHIFT (9U)
4161#define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK)
4162#define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK (0x80000000U)
4163#define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT (31U)
4164/*! DEBUG1_PREERASECHK
4165 * 0b0..Turn off pre-erase check
4166 * 0b1..Turn on pre-erase check
4167 */
4168#define BCH_DEBUG1_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK)
4169/*! @} */
4170
4171
4172/*!
4173 * @}
4174 */ /* end of group BCH_Register_Masks */
4175
4176
4177/* BCH - Peripheral instance base addresses */
4178/** Peripheral BCH base address */
4179#define BCH_BASE (0x33004000u)
4180/** Peripheral BCH base pointer */
4181#define BCH ((BCH_Type *)BCH_BASE)
4182/** Array initializer of BCH peripheral base addresses */
4183#define BCH_BASE_ADDRS { BCH_BASE }
4184/** Array initializer of BCH peripheral base pointers */
4185#define BCH_BASE_PTRS { BCH }
4186/** Interrupt vectors for the BCH peripheral type */
4187#define BCH_IRQS { BCH_IRQn }
4188
4189/*!
4190 * @}
4191 */ /* end of group BCH_Peripheral_Access_Layer */
4192
4193
4194/* ----------------------------------------------------------------------------
4195 -- CCM Peripheral Access Layer
4196 ---------------------------------------------------------------------------- */
4197
4198/*!
4199 * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
4200 * @{
4201 */
4202
4203/** CCM - Register Layout Typedef */
4204typedef struct {
4205 __IO uint32_t GPR0; /**< General Purpose Register, offset: 0x0 */
4206 __IO uint32_t GPR0_SET; /**< General Purpose Register, offset: 0x4 */
4207 __IO uint32_t GPR0_CLR; /**< General Purpose Register, offset: 0x8 */
4208 __IO uint32_t GPR0_TOG; /**< General Purpose Register, offset: 0xC */
4209 uint8_t RESERVED_0[2032];
4210 struct { /* offset: 0x800, array step: 0x10 */
4211 __IO uint32_t PLL_CTRL; /**< CCM PLL Control Register, array offset: 0x800, array step: 0x10 */
4212 __IO uint32_t PLL_CTRL_SET; /**< CCM PLL Control Register, array offset: 0x804, array step: 0x10 */
4213 __IO uint32_t PLL_CTRL_CLR; /**< CCM PLL Control Register, array offset: 0x808, array step: 0x10 */
4214 __IO uint32_t PLL_CTRL_TOG; /**< CCM PLL Control Register, array offset: 0x80C, array step: 0x10 */
4215 } PLL_CTRL[39];
4216 uint8_t RESERVED_1[13712];
4217 struct { /* offset: 0x4000, array step: 0x10 */
4218 __IO uint32_t CCGR; /**< CCM Clock Gating Register, array offset: 0x4000, array step: 0x10 */
4219 __IO uint32_t CCGR_SET; /**< CCM Clock Gating Register, array offset: 0x4004, array step: 0x10 */
4220 __IO uint32_t CCGR_CLR; /**< CCM Clock Gating Register, array offset: 0x4008, array step: 0x10 */
4221 __IO uint32_t CCGR_TOG; /**< CCM Clock Gating Register, array offset: 0x400C, array step: 0x10 */
4222 } CCGR[191];
4223 uint8_t RESERVED_2[13328];
4224 struct { /* offset: 0x8000, array step: 0x80 */
4225 __IO uint32_t TARGET_ROOT; /**< Target Register, array offset: 0x8000, array step: 0x80 */
4226 __IO uint32_t TARGET_ROOT_SET; /**< Target Register, array offset: 0x8004, array step: 0x80 */
4227 __IO uint32_t TARGET_ROOT_CLR; /**< Target Register, array offset: 0x8008, array step: 0x80 */
4228 __IO uint32_t TARGET_ROOT_TOG; /**< Target Register, array offset: 0x800C, array step: 0x80 */
4229 __IO uint32_t MISC; /**< Miscellaneous Register, array offset: 0x8010, array step: 0x80 */
4230 __IO uint32_t MISC_ROOT_SET; /**< Miscellaneous Register, array offset: 0x8014, array step: 0x80 */
4231 __IO uint32_t MISC_ROOT_CLR; /**< Miscellaneous Register, array offset: 0x8018, array step: 0x80 */
4232 __IO uint32_t MISC_ROOT_TOG; /**< Miscellaneous Register, array offset: 0x801C, array step: 0x80 */
4233 __IO uint32_t POST; /**< Post Divider Register, array offset: 0x8020, array step: 0x80 */
4234 __IO uint32_t POST_ROOT_SET; /**< Post Divider Register, array offset: 0x8024, array step: 0x80 */
4235 __IO uint32_t POST_ROOT_CLR; /**< Post Divider Register, array offset: 0x8028, array step: 0x80 */
4236 __IO uint32_t POST_ROOT_TOG; /**< Post Divider Register, array offset: 0x802C, array step: 0x80 */
4237 __IO uint32_t PRE; /**< Pre Divider Register, array offset: 0x8030, array step: 0x80 */
4238 __IO uint32_t PRE_ROOT_SET; /**< Pre Divider Register, array offset: 0x8034, array step: 0x80 */
4239 __IO uint32_t PRE_ROOT_CLR; /**< Pre Divider Register, array offset: 0x8038, array step: 0x80 */
4240 __IO uint32_t PRE_ROOT_TOG; /**< Pre Divider Register, array offset: 0x803C, array step: 0x80 */
4241 uint8_t RESERVED_0[48];
4242 __IO uint32_t ACCESS_CTRL; /**< Access Control Register, array offset: 0x8070, array step: 0x80 */
4243 __IO uint32_t ACCESS_CTRL_ROOT_SET; /**< Access Control Register, array offset: 0x8074, array step: 0x80 */
4244 __IO uint32_t ACCESS_CTRL_ROOT_CLR; /**< Access Control Register, array offset: 0x8078, array step: 0x80 */
4245 __IO uint32_t ACCESS_CTRL_ROOT_TOG; /**< Access Control Register, array offset: 0x807C, array step: 0x80 */
4246 } ROOT[142];
4247} CCM_Type;
4248
4249/* ----------------------------------------------------------------------------
4250 -- CCM Register Masks
4251 ---------------------------------------------------------------------------- */
4252
4253/*!
4254 * @addtogroup CCM_Register_Masks CCM Register Masks
4255 * @{
4256 */
4257
4258/*! @name GPR0 - General Purpose Register */
4259/*! @{ */
4260#define CCM_GPR0_GP0_MASK (0xFFFFFFFFU)
4261#define CCM_GPR0_GP0_SHIFT (0U)
4262#define CCM_GPR0_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_GP0_SHIFT)) & CCM_GPR0_GP0_MASK)
4263/*! @} */
4264
4265/*! @name GPR0_SET - General Purpose Register */
4266/*! @{ */
4267#define CCM_GPR0_SET_GP0_MASK (0xFFFFFFFFU)
4268#define CCM_GPR0_SET_GP0_SHIFT (0U)
4269#define CCM_GPR0_SET_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_SET_GP0_SHIFT)) & CCM_GPR0_SET_GP0_MASK)
4270/*! @} */
4271
4272/*! @name GPR0_CLR - General Purpose Register */
4273/*! @{ */
4274#define CCM_GPR0_CLR_GP0_MASK (0xFFFFFFFFU)
4275#define CCM_GPR0_CLR_GP0_SHIFT (0U)
4276#define CCM_GPR0_CLR_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_CLR_GP0_SHIFT)) & CCM_GPR0_CLR_GP0_MASK)
4277/*! @} */
4278
4279/*! @name GPR0_TOG - General Purpose Register */
4280/*! @{ */
4281#define CCM_GPR0_TOG_GP0_MASK (0xFFFFFFFFU)
4282#define CCM_GPR0_TOG_GP0_SHIFT (0U)
4283#define CCM_GPR0_TOG_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_TOG_GP0_SHIFT)) & CCM_GPR0_TOG_GP0_MASK)
4284/*! @} */
4285
4286/*! @name PLL_CTRL - CCM PLL Control Register */
4287/*! @{ */
4288#define CCM_PLL_CTRL_SETTING0_MASK (0x3U)
4289#define CCM_PLL_CTRL_SETTING0_SHIFT (0U)
4290/*! SETTING0
4291 * 0b00..Domain clocks not needed
4292 * 0b01..Domain clocks needed when in RUN
4293 * 0b10..Domain clocks needed when in RUN and WAIT
4294 * 0b11..Domain clocks needed all the time
4295 */
4296#define CCM_PLL_CTRL_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING0_SHIFT)) & CCM_PLL_CTRL_SETTING0_MASK)
4297#define CCM_PLL_CTRL_SETTING1_MASK (0x30U)
4298#define CCM_PLL_CTRL_SETTING1_SHIFT (4U)
4299/*! SETTING1
4300 * 0b00..Domain clocks not needed
4301 * 0b01..Domain clocks needed when in RUN
4302 * 0b10..Domain clocks needed when in RUN and WAIT
4303 * 0b11..Domain clocks needed all the time
4304 */
4305#define CCM_PLL_CTRL_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING1_SHIFT)) & CCM_PLL_CTRL_SETTING1_MASK)
4306#define CCM_PLL_CTRL_SETTING2_MASK (0x300U)
4307#define CCM_PLL_CTRL_SETTING2_SHIFT (8U)
4308/*! SETTING2
4309 * 0b00..Domain clocks not needed
4310 * 0b01..Domain clocks needed when in RUN
4311 * 0b10..Domain clocks needed when in RUN and WAIT
4312 * 0b11..Domain clocks needed all the time
4313 */
4314#define CCM_PLL_CTRL_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING2_SHIFT)) & CCM_PLL_CTRL_SETTING2_MASK)
4315#define CCM_PLL_CTRL_SETTING3_MASK (0x3000U)
4316#define CCM_PLL_CTRL_SETTING3_SHIFT (12U)
4317/*! SETTING3
4318 * 0b00..Domain clocks not needed
4319 * 0b01..Domain clocks needed when in RUN
4320 * 0b10..Domain clocks needed when in RUN and WAIT
4321 * 0b11..Domain clocks needed all the time
4322 */
4323#define CCM_PLL_CTRL_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING3_SHIFT)) & CCM_PLL_CTRL_SETTING3_MASK)
4324/*! @} */
4325
4326/* The count of CCM_PLL_CTRL */
4327#define CCM_PLL_CTRL_COUNT (39U)
4328
4329/*! @name PLL_CTRL_SET - CCM PLL Control Register */
4330/*! @{ */
4331#define CCM_PLL_CTRL_SET_SETTING0_MASK (0x3U)
4332#define CCM_PLL_CTRL_SET_SETTING0_SHIFT (0U)
4333/*! SETTING0
4334 * 0b00..Domain clocks not needed
4335 * 0b01..Domain clocks needed when in RUN
4336 * 0b10..Domain clocks needed when in RUN and WAIT
4337 * 0b11..Domain clocks needed all the time
4338 */
4339#define CCM_PLL_CTRL_SET_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING0_SHIFT)) & CCM_PLL_CTRL_SET_SETTING0_MASK)
4340#define CCM_PLL_CTRL_SET_SETTING1_MASK (0x30U)
4341#define CCM_PLL_CTRL_SET_SETTING1_SHIFT (4U)
4342/*! SETTING1
4343 * 0b00..Domain clocks not needed
4344 * 0b01..Domain clocks needed when in RUN
4345 * 0b10..Domain clocks needed when in RUN and WAIT
4346 * 0b11..Domain clocks needed all the time
4347 */
4348#define CCM_PLL_CTRL_SET_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING1_SHIFT)) & CCM_PLL_CTRL_SET_SETTING1_MASK)
4349#define CCM_PLL_CTRL_SET_SETTING2_MASK (0x300U)
4350#define CCM_PLL_CTRL_SET_SETTING2_SHIFT (8U)
4351/*! SETTING2
4352 * 0b00..Domain clocks not needed
4353 * 0b01..Domain clocks needed when in RUN
4354 * 0b10..Domain clocks needed when in RUN and WAIT
4355 * 0b11..Domain clocks needed all the time
4356 */
4357#define CCM_PLL_CTRL_SET_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING2_SHIFT)) & CCM_PLL_CTRL_SET_SETTING2_MASK)
4358#define CCM_PLL_CTRL_SET_SETTING3_MASK (0x3000U)
4359#define CCM_PLL_CTRL_SET_SETTING3_SHIFT (12U)
4360/*! SETTING3
4361 * 0b00..Domain clocks not needed
4362 * 0b01..Domain clocks needed when in RUN
4363 * 0b10..Domain clocks needed when in RUN and WAIT
4364 * 0b11..Domain clocks needed all the time
4365 */
4366#define CCM_PLL_CTRL_SET_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING3_SHIFT)) & CCM_PLL_CTRL_SET_SETTING3_MASK)
4367/*! @} */
4368
4369/* The count of CCM_PLL_CTRL_SET */
4370#define CCM_PLL_CTRL_SET_COUNT (39U)
4371
4372/*! @name PLL_CTRL_CLR - CCM PLL Control Register */
4373/*! @{ */
4374#define CCM_PLL_CTRL_CLR_SETTING0_MASK (0x3U)
4375#define CCM_PLL_CTRL_CLR_SETTING0_SHIFT (0U)
4376/*! SETTING0
4377 * 0b00..Domain clocks not needed
4378 * 0b01..Domain clocks needed when in RUN
4379 * 0b10..Domain clocks needed when in RUN and WAIT
4380 * 0b11..Domain clocks needed all the time
4381 */
4382#define CCM_PLL_CTRL_CLR_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING0_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING0_MASK)
4383#define CCM_PLL_CTRL_CLR_SETTING1_MASK (0x30U)
4384#define CCM_PLL_CTRL_CLR_SETTING1_SHIFT (4U)
4385/*! SETTING1
4386 * 0b00..Domain clocks not needed
4387 * 0b01..Domain clocks needed when in RUN
4388 * 0b10..Domain clocks needed when in RUN and WAIT
4389 * 0b11..Domain clocks needed all the time
4390 */
4391#define CCM_PLL_CTRL_CLR_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING1_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING1_MASK)
4392#define CCM_PLL_CTRL_CLR_SETTING2_MASK (0x300U)
4393#define CCM_PLL_CTRL_CLR_SETTING2_SHIFT (8U)
4394/*! SETTING2
4395 * 0b00..Domain clocks not needed
4396 * 0b01..Domain clocks needed when in RUN
4397 * 0b10..Domain clocks needed when in RUN and WAIT
4398 * 0b11..Domain clocks needed all the time
4399 */
4400#define CCM_PLL_CTRL_CLR_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING2_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING2_MASK)
4401#define CCM_PLL_CTRL_CLR_SETTING3_MASK (0x3000U)
4402#define CCM_PLL_CTRL_CLR_SETTING3_SHIFT (12U)
4403/*! SETTING3
4404 * 0b00..Domain clocks not needed
4405 * 0b01..Domain clocks needed when in RUN
4406 * 0b10..Domain clocks needed when in RUN and WAIT
4407 * 0b11..Domain clocks needed all the time
4408 */
4409#define CCM_PLL_CTRL_CLR_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING3_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING3_MASK)
4410/*! @} */
4411
4412/* The count of CCM_PLL_CTRL_CLR */
4413#define CCM_PLL_CTRL_CLR_COUNT (39U)
4414
4415/*! @name PLL_CTRL_TOG - CCM PLL Control Register */
4416/*! @{ */
4417#define CCM_PLL_CTRL_TOG_SETTING0_MASK (0x3U)
4418#define CCM_PLL_CTRL_TOG_SETTING0_SHIFT (0U)
4419/*! SETTING0
4420 * 0b00..Domain clocks not needed
4421 * 0b01..Domain clocks needed when in RUN
4422 * 0b10..Domain clocks needed when in RUN and WAIT
4423 * 0b11..Domain clocks needed all the time
4424 */
4425#define CCM_PLL_CTRL_TOG_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING0_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING0_MASK)
4426#define CCM_PLL_CTRL_TOG_SETTING1_MASK (0x30U)
4427#define CCM_PLL_CTRL_TOG_SETTING1_SHIFT (4U)
4428/*! SETTING1
4429 * 0b00..Domain clocks not needed
4430 * 0b01..Domain clocks needed when in RUN
4431 * 0b10..Domain clocks needed when in RUN and WAIT
4432 * 0b11..Domain clocks needed all the time
4433 */
4434#define CCM_PLL_CTRL_TOG_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING1_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING1_MASK)
4435#define CCM_PLL_CTRL_TOG_SETTING2_MASK (0x300U)
4436#define CCM_PLL_CTRL_TOG_SETTING2_SHIFT (8U)
4437/*! SETTING2
4438 * 0b00..Domain clocks not needed
4439 * 0b01..Domain clocks needed when in RUN
4440 * 0b10..Domain clocks needed when in RUN and WAIT
4441 * 0b11..Domain clocks needed all the time
4442 */
4443#define CCM_PLL_CTRL_TOG_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING2_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING2_MASK)
4444#define CCM_PLL_CTRL_TOG_SETTING3_MASK (0x3000U)
4445#define CCM_PLL_CTRL_TOG_SETTING3_SHIFT (12U)
4446/*! SETTING3
4447 * 0b00..Domain clocks not needed
4448 * 0b01..Domain clocks needed when in RUN
4449 * 0b10..Domain clocks needed when in RUN and WAIT
4450 * 0b11..Domain clocks needed all the time
4451 */
4452#define CCM_PLL_CTRL_TOG_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING3_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING3_MASK)
4453/*! @} */
4454
4455/* The count of CCM_PLL_CTRL_TOG */
4456#define CCM_PLL_CTRL_TOG_COUNT (39U)
4457
4458/*! @name CCGR - CCM Clock Gating Register */
4459/*! @{ */
4460#define CCM_CCGR_SETTING0_MASK (0x3U)
4461#define CCM_CCGR_SETTING0_SHIFT (0U)
4462/*! SETTING0
4463 * 0b00..Domain clocks not needed
4464 * 0b01..Domain clocks needed when in RUN
4465 * 0b10..Domain clocks needed when in RUN and WAIT
4466 * 0b11..Domain clocks needed all the time
4467 */
4468#define CCM_CCGR_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING0_SHIFT)) & CCM_CCGR_SETTING0_MASK)
4469#define CCM_CCGR_SETTING1_MASK (0x30U)
4470#define CCM_CCGR_SETTING1_SHIFT (4U)
4471/*! SETTING1
4472 * 0b00..Domain clocks not needed
4473 * 0b01..Domain clocks needed when in RUN
4474 * 0b10..Domain clocks needed when in RUN and WAIT
4475 * 0b11..Domain clocks needed all the time
4476 */
4477#define CCM_CCGR_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING1_SHIFT)) & CCM_CCGR_SETTING1_MASK)
4478#define CCM_CCGR_SETTING2_MASK (0x300U)
4479#define CCM_CCGR_SETTING2_SHIFT (8U)
4480/*! SETTING2
4481 * 0b00..Domain clocks not needed
4482 * 0b01..Domain clocks needed when in RUN
4483 * 0b10..Domain clocks needed when in RUN and WAIT
4484 * 0b11..Domain clocks needed all the time
4485 */
4486#define CCM_CCGR_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING2_SHIFT)) & CCM_CCGR_SETTING2_MASK)
4487#define CCM_CCGR_SETTING3_MASK (0x3000U)
4488#define CCM_CCGR_SETTING3_SHIFT (12U)
4489/*! SETTING3
4490 * 0b00..Domain clocks not needed
4491 * 0b01..Domain clocks needed when in RUN
4492 * 0b10..Domain clocks needed when in RUN and WAIT
4493 * 0b11..Domain clocks needed all the time
4494 */
4495#define CCM_CCGR_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING3_SHIFT)) & CCM_CCGR_SETTING3_MASK)
4496/*! @} */
4497
4498/* The count of CCM_CCGR */
4499#define CCM_CCGR_COUNT (191U)
4500
4501/*! @name CCGR_SET - CCM Clock Gating Register */
4502/*! @{ */
4503#define CCM_CCGR_SET_SETTING0_MASK (0x3U)
4504#define CCM_CCGR_SET_SETTING0_SHIFT (0U)
4505/*! SETTING0
4506 * 0b00..Domain clocks not needed
4507 * 0b01..Domain clocks needed when in RUN
4508 * 0b10..Domain clocks needed when in RUN and WAIT
4509 * 0b11..Domain clocks needed all the time
4510 */
4511#define CCM_CCGR_SET_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING0_SHIFT)) & CCM_CCGR_SET_SETTING0_MASK)
4512#define CCM_CCGR_SET_SETTING1_MASK (0x30U)
4513#define CCM_CCGR_SET_SETTING1_SHIFT (4U)
4514/*! SETTING1
4515 * 0b00..Domain clocks not needed
4516 * 0b01..Domain clocks needed when in RUN
4517 * 0b10..Domain clocks needed when in RUN and WAIT
4518 * 0b11..Domain clocks needed all the time
4519 */
4520#define CCM_CCGR_SET_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING1_SHIFT)) & CCM_CCGR_SET_SETTING1_MASK)
4521#define CCM_CCGR_SET_SETTING2_MASK (0x300U)
4522#define CCM_CCGR_SET_SETTING2_SHIFT (8U)
4523/*! SETTING2
4524 * 0b00..Domain clocks not needed
4525 * 0b01..Domain clocks needed when in RUN
4526 * 0b10..Domain clocks needed when in RUN and WAIT
4527 * 0b11..Domain clocks needed all the time
4528 */
4529#define CCM_CCGR_SET_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING2_SHIFT)) & CCM_CCGR_SET_SETTING2_MASK)
4530#define CCM_CCGR_SET_SETTING3_MASK (0x3000U)
4531#define CCM_CCGR_SET_SETTING3_SHIFT (12U)
4532/*! SETTING3
4533 * 0b00..Domain clocks not needed
4534 * 0b01..Domain clocks needed when in RUN
4535 * 0b10..Domain clocks needed when in RUN and WAIT
4536 * 0b11..Domain clocks needed all the time
4537 */
4538#define CCM_CCGR_SET_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING3_SHIFT)) & CCM_CCGR_SET_SETTING3_MASK)
4539/*! @} */
4540
4541/* The count of CCM_CCGR_SET */
4542#define CCM_CCGR_SET_COUNT (191U)
4543
4544/*! @name CCGR_CLR - CCM Clock Gating Register */
4545/*! @{ */
4546#define CCM_CCGR_CLR_SETTING0_MASK (0x3U)
4547#define CCM_CCGR_CLR_SETTING0_SHIFT (0U)
4548/*! SETTING0
4549 * 0b00..Domain clocks not needed
4550 * 0b01..Domain clocks needed when in RUN
4551 * 0b10..Domain clocks needed when in RUN and WAIT
4552 * 0b11..Domain clocks needed all the time
4553 */
4554#define CCM_CCGR_CLR_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING0_SHIFT)) & CCM_CCGR_CLR_SETTING0_MASK)
4555#define CCM_CCGR_CLR_SETTING1_MASK (0x30U)
4556#define CCM_CCGR_CLR_SETTING1_SHIFT (4U)
4557/*! SETTING1
4558 * 0b00..Domain clocks not needed
4559 * 0b01..Domain clocks needed when in RUN
4560 * 0b10..Domain clocks needed when in RUN and WAIT
4561 * 0b11..Domain clocks needed all the time
4562 */
4563#define CCM_CCGR_CLR_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING1_SHIFT)) & CCM_CCGR_CLR_SETTING1_MASK)
4564#define CCM_CCGR_CLR_SETTING2_MASK (0x300U)
4565#define CCM_CCGR_CLR_SETTING2_SHIFT (8U)
4566/*! SETTING2
4567 * 0b00..Domain clocks not needed
4568 * 0b01..Domain clocks needed when in RUN
4569 * 0b10..Domain clocks needed when in RUN and WAIT
4570 * 0b11..Domain clocks needed all the time
4571 */
4572#define CCM_CCGR_CLR_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING2_SHIFT)) & CCM_CCGR_CLR_SETTING2_MASK)
4573#define CCM_CCGR_CLR_SETTING3_MASK (0x3000U)
4574#define CCM_CCGR_CLR_SETTING3_SHIFT (12U)
4575/*! SETTING3
4576 * 0b00..Domain clocks not needed
4577 * 0b01..Domain clocks needed when in RUN
4578 * 0b10..Domain clocks needed when in RUN and WAIT
4579 * 0b11..Domain clocks needed all the time
4580 */
4581#define CCM_CCGR_CLR_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING3_SHIFT)) & CCM_CCGR_CLR_SETTING3_MASK)
4582/*! @} */
4583
4584/* The count of CCM_CCGR_CLR */
4585#define CCM_CCGR_CLR_COUNT (191U)
4586
4587/*! @name CCGR_TOG - CCM Clock Gating Register */
4588/*! @{ */
4589#define CCM_CCGR_TOG_SETTING0_MASK (0x3U)
4590#define CCM_CCGR_TOG_SETTING0_SHIFT (0U)
4591/*! SETTING0
4592 * 0b00..Domain clocks not needed
4593 * 0b01..Domain clocks needed when in RUN
4594 * 0b10..Domain clocks needed when in RUN and WAIT
4595 * 0b11..Domain clocks needed all the time
4596 */
4597#define CCM_CCGR_TOG_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING0_SHIFT)) & CCM_CCGR_TOG_SETTING0_MASK)
4598#define CCM_CCGR_TOG_SETTING1_MASK (0x30U)
4599#define CCM_CCGR_TOG_SETTING1_SHIFT (4U)
4600/*! SETTING1
4601 * 0b00..Domain clocks not needed
4602 * 0b01..Domain clocks needed when in RUN
4603 * 0b10..Domain clocks needed when in RUN and WAIT
4604 * 0b11..Domain clocks needed all the time
4605 */
4606#define CCM_CCGR_TOG_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING1_SHIFT)) & CCM_CCGR_TOG_SETTING1_MASK)
4607#define CCM_CCGR_TOG_SETTING2_MASK (0x300U)
4608#define CCM_CCGR_TOG_SETTING2_SHIFT (8U)
4609/*! SETTING2
4610 * 0b00..Domain clocks not needed
4611 * 0b01..Domain clocks needed when in RUN
4612 * 0b10..Domain clocks needed when in RUN and WAIT
4613 * 0b11..Domain clocks needed all the time
4614 */
4615#define CCM_CCGR_TOG_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING2_SHIFT)) & CCM_CCGR_TOG_SETTING2_MASK)
4616#define CCM_CCGR_TOG_SETTING3_MASK (0x3000U)
4617#define CCM_CCGR_TOG_SETTING3_SHIFT (12U)
4618/*! SETTING3
4619 * 0b00..Domain clocks not needed
4620 * 0b01..Domain clocks needed when in RUN
4621 * 0b10..Domain clocks needed when in RUN and WAIT
4622 * 0b11..Domain clocks needed all the time
4623 */
4624#define CCM_CCGR_TOG_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING3_SHIFT)) & CCM_CCGR_TOG_SETTING3_MASK)
4625/*! @} */
4626
4627/* The count of CCM_CCGR_TOG */
4628#define CCM_CCGR_TOG_COUNT (191U)
4629
4630/*! @name TARGET_ROOT - Target Register */
4631/*! @{ */
4632#define CCM_TARGET_ROOT_POST_PODF_MASK (0x3FU)
4633#define CCM_TARGET_ROOT_POST_PODF_SHIFT (0U)
4634/*! POST_PODF
4635 * 0b000000..Divide by 1
4636 * 0b000001..Divide by 2
4637 * 0b000010..Divide by 3
4638 * 0b000011..Divide by 4
4639 * 0b000100..Divide by 5
4640 * 0b000101..Divide by 6
4641 * 0b111111..Divide by 64
4642 */
4643#define CCM_TARGET_ROOT_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_POST_PODF_MASK)
4644#define CCM_TARGET_ROOT_PRE_PODF_MASK (0x70000U)
4645#define CCM_TARGET_ROOT_PRE_PODF_SHIFT (16U)
4646/*! PRE_PODF
4647 * 0b000..Divide by 1
4648 * 0b001..Divide by 2
4649 * 0b010..Divide by 3
4650 * 0b011..Divide by 4
4651 * 0b100..Divide by 5
4652 * 0b101..Divide by 6
4653 * 0b110..Divide by 7
4654 * 0b111..Divide by 8
4655 */
4656#define CCM_TARGET_ROOT_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_PRE_PODF_MASK)
4657#define CCM_TARGET_ROOT_MUX_MASK (0x7000000U)
4658#define CCM_TARGET_ROOT_MUX_SHIFT (24U)
4659#define CCM_TARGET_ROOT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_MUX_SHIFT)) & CCM_TARGET_ROOT_MUX_MASK)
4660#define CCM_TARGET_ROOT_ENABLE_MASK (0x10000000U)
4661#define CCM_TARGET_ROOT_ENABLE_SHIFT (28U)
4662/*! ENABLE
4663 * 0b0..clock root is OFF
4664 * 0b1..clock root is ON
4665 */
4666#define CCM_TARGET_ROOT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_ENABLE_SHIFT)) & CCM_TARGET_ROOT_ENABLE_MASK)
4667/*! @} */
4668
4669/* The count of CCM_TARGET_ROOT */
4670#define CCM_TARGET_ROOT_COUNT (142U)
4671
4672/*! @name TARGET_ROOT_SET - Target Register */
4673/*! @{ */
4674#define CCM_TARGET_ROOT_SET_POST_PODF_MASK (0x3FU)
4675#define CCM_TARGET_ROOT_SET_POST_PODF_SHIFT (0U)
4676/*! POST_PODF
4677 * 0b000000..Divide by 1
4678 * 0b000001..Divide by 2
4679 * 0b000010..Divide by 3
4680 * 0b000011..Divide by 4
4681 * 0b000100..Divide by 5
4682 * 0b000101..Divide by 6
4683 * 0b111111..Divide by 64
4684 */
4685#define CCM_TARGET_ROOT_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_POST_PODF_MASK)
4686#define CCM_TARGET_ROOT_SET_PRE_PODF_MASK (0x70000U)
4687#define CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT (16U)
4688/*! PRE_PODF
4689 * 0b000..Divide by 1
4690 * 0b001..Divide by 2
4691 * 0b010..Divide by 3
4692 * 0b011..Divide by 4
4693 * 0b100..Divide by 5
4694 * 0b101..Divide by 6
4695 * 0b110..Divide by 7
4696 * 0b111..Divide by 8
4697 */
4698#define CCM_TARGET_ROOT_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_PRE_PODF_MASK)
4699#define CCM_TARGET_ROOT_SET_MUX_MASK (0x7000000U)
4700#define CCM_TARGET_ROOT_SET_MUX_SHIFT (24U)
4701#define CCM_TARGET_ROOT_SET_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_MUX_SHIFT)) & CCM_TARGET_ROOT_SET_MUX_MASK)
4702#define CCM_TARGET_ROOT_SET_ENABLE_MASK (0x10000000U)
4703#define CCM_TARGET_ROOT_SET_ENABLE_SHIFT (28U)
4704/*! ENABLE
4705 * 0b0..clock root is OFF
4706 * 0b1..clock root is ON
4707 */
4708#define CCM_TARGET_ROOT_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_ENABLE_SHIFT)) & CCM_TARGET_ROOT_SET_ENABLE_MASK)
4709/*! @} */
4710
4711/* The count of CCM_TARGET_ROOT_SET */
4712#define CCM_TARGET_ROOT_SET_COUNT (142U)
4713
4714/*! @name TARGET_ROOT_CLR - Target Register */
4715/*! @{ */
4716#define CCM_TARGET_ROOT_CLR_POST_PODF_MASK (0x3FU)
4717#define CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT (0U)
4718/*! POST_PODF
4719 * 0b000000..Divide by 1
4720 * 0b000001..Divide by 2
4721 * 0b000010..Divide by 3
4722 * 0b000011..Divide by 4
4723 * 0b000100..Divide by 5
4724 * 0b000101..Divide by 6
4725 * 0b111111..Divide by 64
4726 */
4727#define CCM_TARGET_ROOT_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_POST_PODF_MASK)
4728#define CCM_TARGET_ROOT_CLR_PRE_PODF_MASK (0x70000U)
4729#define CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT (16U)
4730/*! PRE_PODF
4731 * 0b000..Divide by 1
4732 * 0b001..Divide by 2
4733 * 0b010..Divide by 3
4734 * 0b011..Divide by 4
4735 * 0b100..Divide by 5
4736 * 0b101..Divide by 6
4737 * 0b110..Divide by 7
4738 * 0b111..Divide by 8
4739 */
4740#define CCM_TARGET_ROOT_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_PRE_PODF_MASK)
4741#define CCM_TARGET_ROOT_CLR_MUX_MASK (0x7000000U)
4742#define CCM_TARGET_ROOT_CLR_MUX_SHIFT (24U)
4743#define CCM_TARGET_ROOT_CLR_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_MUX_SHIFT)) & CCM_TARGET_ROOT_CLR_MUX_MASK)
4744#define CCM_TARGET_ROOT_CLR_ENABLE_MASK (0x10000000U)
4745#define CCM_TARGET_ROOT_CLR_ENABLE_SHIFT (28U)
4746/*! ENABLE
4747 * 0b0..clock root is OFF
4748 * 0b1..clock root is ON
4749 */
4750#define CCM_TARGET_ROOT_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_ENABLE_SHIFT)) & CCM_TARGET_ROOT_CLR_ENABLE_MASK)
4751/*! @} */
4752
4753/* The count of CCM_TARGET_ROOT_CLR */
4754#define CCM_TARGET_ROOT_CLR_COUNT (142U)
4755
4756/*! @name TARGET_ROOT_TOG - Target Register */
4757/*! @{ */
4758#define CCM_TARGET_ROOT_TOG_POST_PODF_MASK (0x3FU)
4759#define CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT (0U)
4760/*! POST_PODF
4761 * 0b000000..Divide by 1
4762 * 0b000001..Divide by 2
4763 * 0b000010..Divide by 3
4764 * 0b000011..Divide by 4
4765 * 0b000100..Divide by 5
4766 * 0b000101..Divide by 6
4767 * 0b111111..Divide by 64
4768 */
4769#define CCM_TARGET_ROOT_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_POST_PODF_MASK)
4770#define CCM_TARGET_ROOT_TOG_PRE_PODF_MASK (0x70000U)
4771#define CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT (16U)
4772/*! PRE_PODF
4773 * 0b000..Divide by 1
4774 * 0b001..Divide by 2
4775 * 0b010..Divide by 3
4776 * 0b011..Divide by 4
4777 * 0b100..Divide by 5
4778 * 0b101..Divide by 6
4779 * 0b110..Divide by 7
4780 * 0b111..Divide by 8
4781 */
4782#define CCM_TARGET_ROOT_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_PRE_PODF_MASK)
4783#define CCM_TARGET_ROOT_TOG_MUX_MASK (0x7000000U)
4784#define CCM_TARGET_ROOT_TOG_MUX_SHIFT (24U)
4785#define CCM_TARGET_ROOT_TOG_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_MUX_SHIFT)) & CCM_TARGET_ROOT_TOG_MUX_MASK)
4786#define CCM_TARGET_ROOT_TOG_ENABLE_MASK (0x10000000U)
4787#define CCM_TARGET_ROOT_TOG_ENABLE_SHIFT (28U)
4788/*! ENABLE
4789 * 0b0..clock root is OFF
4790 * 0b1..clock root is ON
4791 */
4792#define CCM_TARGET_ROOT_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_ENABLE_SHIFT)) & CCM_TARGET_ROOT_TOG_ENABLE_MASK)
4793/*! @} */
4794
4795/* The count of CCM_TARGET_ROOT_TOG */
4796#define CCM_TARGET_ROOT_TOG_COUNT (142U)
4797
4798/*! @name MISC - Miscellaneous Register */
4799/*! @{ */
4800#define CCM_MISC_AUTHEN_FAIL_MASK (0x1U)
4801#define CCM_MISC_AUTHEN_FAIL_SHIFT (0U)
4802#define CCM_MISC_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_AUTHEN_FAIL_SHIFT)) & CCM_MISC_AUTHEN_FAIL_MASK)
4803#define CCM_MISC_TIMEOUT_MASK (0x10U)
4804#define CCM_MISC_TIMEOUT_SHIFT (4U)
4805#define CCM_MISC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_TIMEOUT_SHIFT)) & CCM_MISC_TIMEOUT_MASK)
4806#define CCM_MISC_VIOLATE_MASK (0x100U)
4807#define CCM_MISC_VIOLATE_SHIFT (8U)
4808#define CCM_MISC_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_VIOLATE_SHIFT)) & CCM_MISC_VIOLATE_MASK)
4809/*! @} */
4810
4811/* The count of CCM_MISC */
4812#define CCM_MISC_COUNT (142U)
4813
4814/*! @name MISC_ROOT_SET - Miscellaneous Register */
4815/*! @{ */
4816#define CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK (0x1U)
4817#define CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT (0U)
4818#define CCM_MISC_ROOT_SET_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK)
4819#define CCM_MISC_ROOT_SET_TIMEOUT_MASK (0x10U)
4820#define CCM_MISC_ROOT_SET_TIMEOUT_SHIFT (4U)
4821#define CCM_MISC_ROOT_SET_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_SET_TIMEOUT_MASK)
4822#define CCM_MISC_ROOT_SET_VIOLATE_MASK (0x100U)
4823#define CCM_MISC_ROOT_SET_VIOLATE_SHIFT (8U)
4824#define CCM_MISC_ROOT_SET_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_VIOLATE_SHIFT)) & CCM_MISC_ROOT_SET_VIOLATE_MASK)
4825/*! @} */
4826
4827/* The count of CCM_MISC_ROOT_SET */
4828#define CCM_MISC_ROOT_SET_COUNT (142U)
4829
4830/*! @name MISC_ROOT_CLR - Miscellaneous Register */
4831/*! @{ */
4832#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK (0x1U)
4833#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT (0U)
4834#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK)
4835#define CCM_MISC_ROOT_CLR_TIMEOUT_MASK (0x10U)
4836#define CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT (4U)
4837#define CCM_MISC_ROOT_CLR_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_CLR_TIMEOUT_MASK)
4838#define CCM_MISC_ROOT_CLR_VIOLATE_MASK (0x100U)
4839#define CCM_MISC_ROOT_CLR_VIOLATE_SHIFT (8U)
4840#define CCM_MISC_ROOT_CLR_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_VIOLATE_SHIFT)) & CCM_MISC_ROOT_CLR_VIOLATE_MASK)
4841/*! @} */
4842
4843/* The count of CCM_MISC_ROOT_CLR */
4844#define CCM_MISC_ROOT_CLR_COUNT (142U)
4845
4846/*! @name MISC_ROOT_TOG - Miscellaneous Register */
4847/*! @{ */
4848#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK (0x1U)
4849#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT (0U)
4850#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK)
4851#define CCM_MISC_ROOT_TOG_TIMEOUT_MASK (0x10U)
4852#define CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT (4U)
4853#define CCM_MISC_ROOT_TOG_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_TOG_TIMEOUT_MASK)
4854#define CCM_MISC_ROOT_TOG_VIOLATE_MASK (0x100U)
4855#define CCM_MISC_ROOT_TOG_VIOLATE_SHIFT (8U)
4856#define CCM_MISC_ROOT_TOG_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_VIOLATE_SHIFT)) & CCM_MISC_ROOT_TOG_VIOLATE_MASK)
4857/*! @} */
4858
4859/* The count of CCM_MISC_ROOT_TOG */
4860#define CCM_MISC_ROOT_TOG_COUNT (142U)
4861
4862/*! @name POST - Post Divider Register */
4863/*! @{ */
4864#define CCM_POST_POST_PODF_MASK (0x3FU)
4865#define CCM_POST_POST_PODF_SHIFT (0U)
4866/*! POST_PODF
4867 * 0b000000..Divide by 1
4868 * 0b000001..Divide by 2
4869 * 0b000010..Divide by 3
4870 * 0b000011..Divide by 4
4871 * 0b000100..Divide by 5
4872 * 0b000101..Divide by 6
4873 * 0b111111..Divide by 64
4874 */
4875#define CCM_POST_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_POST_PODF_SHIFT)) & CCM_POST_POST_PODF_MASK)
4876#define CCM_POST_BUSY1_MASK (0x80U)
4877#define CCM_POST_BUSY1_SHIFT (7U)
4878#define CCM_POST_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY1_SHIFT)) & CCM_POST_BUSY1_MASK)
4879#define CCM_POST_SELECT_MASK (0x10000000U)
4880#define CCM_POST_SELECT_SHIFT (28U)
4881/*! SELECT
4882 * 0b0..select branch A
4883 * 0b1..select branch B
4884 */
4885#define CCM_POST_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_SELECT_SHIFT)) & CCM_POST_SELECT_MASK)
4886#define CCM_POST_BUSY2_MASK (0x80000000U)
4887#define CCM_POST_BUSY2_SHIFT (31U)
4888#define CCM_POST_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY2_SHIFT)) & CCM_POST_BUSY2_MASK)
4889/*! @} */
4890
4891/* The count of CCM_POST */
4892#define CCM_POST_COUNT (142U)
4893
4894/*! @name POST_ROOT_SET - Post Divider Register */
4895/*! @{ */
4896#define CCM_POST_ROOT_SET_POST_PODF_MASK (0x3FU)
4897#define CCM_POST_ROOT_SET_POST_PODF_SHIFT (0U)
4898/*! POST_PODF
4899 * 0b000000..Divide by 1
4900 * 0b000001..Divide by 2
4901 * 0b000010..Divide by 3
4902 * 0b000011..Divide by 4
4903 * 0b000100..Divide by 5
4904 * 0b000101..Divide by 6
4905 * 0b111111..Divide by 64
4906 */
4907#define CCM_POST_ROOT_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_POST_PODF_SHIFT)) & CCM_POST_ROOT_SET_POST_PODF_MASK)
4908#define CCM_POST_ROOT_SET_BUSY1_MASK (0x80U)
4909#define CCM_POST_ROOT_SET_BUSY1_SHIFT (7U)
4910#define CCM_POST_ROOT_SET_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY1_SHIFT)) & CCM_POST_ROOT_SET_BUSY1_MASK)
4911#define CCM_POST_ROOT_SET_SELECT_MASK (0x10000000U)
4912#define CCM_POST_ROOT_SET_SELECT_SHIFT (28U)
4913/*! SELECT
4914 * 0b0..select branch A
4915 * 0b1..select branch B
4916 */
4917#define CCM_POST_ROOT_SET_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_SELECT_SHIFT)) & CCM_POST_ROOT_SET_SELECT_MASK)
4918#define CCM_POST_ROOT_SET_BUSY2_MASK (0x80000000U)
4919#define CCM_POST_ROOT_SET_BUSY2_SHIFT (31U)
4920#define CCM_POST_ROOT_SET_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY2_SHIFT)) & CCM_POST_ROOT_SET_BUSY2_MASK)
4921/*! @} */
4922
4923/* The count of CCM_POST_ROOT_SET */
4924#define CCM_POST_ROOT_SET_COUNT (142U)
4925
4926/*! @name POST_ROOT_CLR - Post Divider Register */
4927/*! @{ */
4928#define CCM_POST_ROOT_CLR_POST_PODF_MASK (0x3FU)
4929#define CCM_POST_ROOT_CLR_POST_PODF_SHIFT (0U)
4930/*! POST_PODF
4931 * 0b000000..Divide by 1
4932 * 0b000001..Divide by 2
4933 * 0b000010..Divide by 3
4934 * 0b000011..Divide by 4
4935 * 0b000100..Divide by 5
4936 * 0b000101..Divide by 6
4937 * 0b111111..Divide by 64
4938 */
4939#define CCM_POST_ROOT_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_POST_PODF_SHIFT)) & CCM_POST_ROOT_CLR_POST_PODF_MASK)
4940#define CCM_POST_ROOT_CLR_BUSY1_MASK (0x80U)
4941#define CCM_POST_ROOT_CLR_BUSY1_SHIFT (7U)
4942#define CCM_POST_ROOT_CLR_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY1_SHIFT)) & CCM_POST_ROOT_CLR_BUSY1_MASK)
4943#define CCM_POST_ROOT_CLR_SELECT_MASK (0x10000000U)
4944#define CCM_POST_ROOT_CLR_SELECT_SHIFT (28U)
4945/*! SELECT
4946 * 0b0..select branch A
4947 * 0b1..select branch B
4948 */
4949#define CCM_POST_ROOT_CLR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_SELECT_SHIFT)) & CCM_POST_ROOT_CLR_SELECT_MASK)
4950#define CCM_POST_ROOT_CLR_BUSY2_MASK (0x80000000U)
4951#define CCM_POST_ROOT_CLR_BUSY2_SHIFT (31U)
4952#define CCM_POST_ROOT_CLR_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY2_SHIFT)) & CCM_POST_ROOT_CLR_BUSY2_MASK)
4953/*! @} */
4954
4955/* The count of CCM_POST_ROOT_CLR */
4956#define CCM_POST_ROOT_CLR_COUNT (142U)
4957
4958/*! @name POST_ROOT_TOG - Post Divider Register */
4959/*! @{ */
4960#define CCM_POST_ROOT_TOG_POST_PODF_MASK (0x3FU)
4961#define CCM_POST_ROOT_TOG_POST_PODF_SHIFT (0U)
4962/*! POST_PODF
4963 * 0b000000..Divide by 1
4964 * 0b000001..Divide by 2
4965 * 0b000010..Divide by 3
4966 * 0b000011..Divide by 4
4967 * 0b000100..Divide by 5
4968 * 0b000101..Divide by 6
4969 * 0b111111..Divide by 64
4970 */
4971#define CCM_POST_ROOT_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_POST_PODF_SHIFT)) & CCM_POST_ROOT_TOG_POST_PODF_MASK)
4972#define CCM_POST_ROOT_TOG_BUSY1_MASK (0x80U)
4973#define CCM_POST_ROOT_TOG_BUSY1_SHIFT (7U)
4974#define CCM_POST_ROOT_TOG_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY1_SHIFT)) & CCM_POST_ROOT_TOG_BUSY1_MASK)
4975#define CCM_POST_ROOT_TOG_SELECT_MASK (0x10000000U)
4976#define CCM_POST_ROOT_TOG_SELECT_SHIFT (28U)
4977/*! SELECT
4978 * 0b0..select branch A
4979 * 0b1..select branch B
4980 */
4981#define CCM_POST_ROOT_TOG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_SELECT_SHIFT)) & CCM_POST_ROOT_TOG_SELECT_MASK)
4982#define CCM_POST_ROOT_TOG_BUSY2_MASK (0x80000000U)
4983#define CCM_POST_ROOT_TOG_BUSY2_SHIFT (31U)
4984#define CCM_POST_ROOT_TOG_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY2_SHIFT)) & CCM_POST_ROOT_TOG_BUSY2_MASK)
4985/*! @} */
4986
4987/* The count of CCM_POST_ROOT_TOG */
4988#define CCM_POST_ROOT_TOG_COUNT (142U)
4989
4990/*! @name PRE - Pre Divider Register */
4991/*! @{ */
4992#define CCM_PRE_PRE_PODF_B_MASK (0x7U)
4993#define CCM_PRE_PRE_PODF_B_SHIFT (0U)
4994/*! PRE_PODF_B
4995 * 0b000..Divide by 1
4996 * 0b001..Divide by 2
4997 * 0b010..Divide by 3
4998 * 0b011..Divide by 4
4999 * 0b100..Divide by 5
5000 * 0b101..Divide by 6
5001 * 0b110..Divide by 7
5002 * 0b111..Divide by 8
5003 */
5004#define CCM_PRE_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_B_SHIFT)) & CCM_PRE_PRE_PODF_B_MASK)
5005#define CCM_PRE_BUSY0_MASK (0x8U)
5006#define CCM_PRE_BUSY0_SHIFT (3U)
5007#define CCM_PRE_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY0_SHIFT)) & CCM_PRE_BUSY0_MASK)
5008#define CCM_PRE_MUX_B_MASK (0x700U)
5009#define CCM_PRE_MUX_B_SHIFT (8U)
5010#define CCM_PRE_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_B_SHIFT)) & CCM_PRE_MUX_B_MASK)
5011#define CCM_PRE_EN_B_MASK (0x1000U)
5012#define CCM_PRE_EN_B_SHIFT (12U)
5013/*! EN_B
5014 * 0b0..Clock shutdown
5015 * 0b1..Clock ON
5016 */
5017#define CCM_PRE_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_B_SHIFT)) & CCM_PRE_EN_B_MASK)
5018#define CCM_PRE_BUSY1_MASK (0x8000U)
5019#define CCM_PRE_BUSY1_SHIFT (15U)
5020#define CCM_PRE_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY1_SHIFT)) & CCM_PRE_BUSY1_MASK)
5021#define CCM_PRE_PRE_PODF_A_MASK (0x70000U)
5022#define CCM_PRE_PRE_PODF_A_SHIFT (16U)
5023/*! PRE_PODF_A
5024 * 0b000..Divide by 1
5025 * 0b001..Divide by 2
5026 * 0b010..Divide by 3
5027 * 0b011..Divide by 4
5028 * 0b100..Divide by 5
5029 * 0b101..Divide by 6
5030 * 0b110..Divide by 7
5031 * 0b111..Divide by 8
5032 */
5033#define CCM_PRE_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_A_SHIFT)) & CCM_PRE_PRE_PODF_A_MASK)
5034#define CCM_PRE_BUSY3_MASK (0x80000U)
5035#define CCM_PRE_BUSY3_SHIFT (19U)
5036#define CCM_PRE_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY3_SHIFT)) & CCM_PRE_BUSY3_MASK)
5037#define CCM_PRE_MUX_A_MASK (0x7000000U)
5038#define CCM_PRE_MUX_A_SHIFT (24U)
5039#define CCM_PRE_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_A_SHIFT)) & CCM_PRE_MUX_A_MASK)
5040#define CCM_PRE_EN_A_MASK (0x10000000U)
5041#define CCM_PRE_EN_A_SHIFT (28U)
5042/*! EN_A
5043 * 0b0..Clock shutdown
5044 * 0b1..clock ON
5045 */
5046#define CCM_PRE_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_A_SHIFT)) & CCM_PRE_EN_A_MASK)
5047#define CCM_PRE_BUSY4_MASK (0x80000000U)
5048#define CCM_PRE_BUSY4_SHIFT (31U)
5049#define CCM_PRE_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY4_SHIFT)) & CCM_PRE_BUSY4_MASK)
5050/*! @} */
5051
5052/* The count of CCM_PRE */
5053#define CCM_PRE_COUNT (142U)
5054
5055/*! @name PRE_ROOT_SET - Pre Divider Register */
5056/*! @{ */
5057#define CCM_PRE_ROOT_SET_PRE_PODF_B_MASK (0x7U)
5058#define CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT (0U)
5059/*! PRE_PODF_B
5060 * 0b000..Divide by 1
5061 * 0b001..Divide by 2
5062 * 0b010..Divide by 3
5063 * 0b011..Divide by 4
5064 * 0b100..Divide by 5
5065 * 0b101..Divide by 6
5066 * 0b110..Divide by 7
5067 * 0b111..Divide by 8
5068 */
5069#define CCM_PRE_ROOT_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_B_MASK)
5070#define CCM_PRE_ROOT_SET_BUSY0_MASK (0x8U)
5071#define CCM_PRE_ROOT_SET_BUSY0_SHIFT (3U)
5072#define CCM_PRE_ROOT_SET_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY0_SHIFT)) & CCM_PRE_ROOT_SET_BUSY0_MASK)
5073#define CCM_PRE_ROOT_SET_MUX_B_MASK (0x700U)
5074#define CCM_PRE_ROOT_SET_MUX_B_SHIFT (8U)
5075#define CCM_PRE_ROOT_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_B_SHIFT)) & CCM_PRE_ROOT_SET_MUX_B_MASK)
5076#define CCM_PRE_ROOT_SET_EN_B_MASK (0x1000U)
5077#define CCM_PRE_ROOT_SET_EN_B_SHIFT (12U)
5078/*! EN_B
5079 * 0b0..Clock shutdown
5080 * 0b1..Clock ON
5081 */
5082#define CCM_PRE_ROOT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_B_SHIFT)) & CCM_PRE_ROOT_SET_EN_B_MASK)
5083#define CCM_PRE_ROOT_SET_BUSY1_MASK (0x8000U)
5084#define CCM_PRE_ROOT_SET_BUSY1_SHIFT (15U)
5085#define CCM_PRE_ROOT_SET_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY1_SHIFT)) & CCM_PRE_ROOT_SET_BUSY1_MASK)
5086#define CCM_PRE_ROOT_SET_PRE_PODF_A_MASK (0x70000U)
5087#define CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT (16U)
5088/*! PRE_PODF_A
5089 * 0b000..Divide by 1
5090 * 0b001..Divide by 2
5091 * 0b010..Divide by 3
5092 * 0b011..Divide by 4
5093 * 0b100..Divide by 5
5094 * 0b101..Divide by 6
5095 * 0b110..Divide by 7
5096 * 0b111..Divide by 8
5097 */
5098#define CCM_PRE_ROOT_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_A_MASK)
5099#define CCM_PRE_ROOT_SET_BUSY3_MASK (0x80000U)
5100#define CCM_PRE_ROOT_SET_BUSY3_SHIFT (19U)
5101#define CCM_PRE_ROOT_SET_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY3_SHIFT)) & CCM_PRE_ROOT_SET_BUSY3_MASK)
5102#define CCM_PRE_ROOT_SET_MUX_A_MASK (0x7000000U)
5103#define CCM_PRE_ROOT_SET_MUX_A_SHIFT (24U)
5104#define CCM_PRE_ROOT_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_A_SHIFT)) & CCM_PRE_ROOT_SET_MUX_A_MASK)
5105#define CCM_PRE_ROOT_SET_EN_A_MASK (0x10000000U)
5106#define CCM_PRE_ROOT_SET_EN_A_SHIFT (28U)
5107/*! EN_A
5108 * 0b0..Clock shutdown
5109 * 0b1..clock ON
5110 */
5111#define CCM_PRE_ROOT_SET_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_A_SHIFT)) & CCM_PRE_ROOT_SET_EN_A_MASK)
5112#define CCM_PRE_ROOT_SET_BUSY4_MASK (0x80000000U)
5113#define CCM_PRE_ROOT_SET_BUSY4_SHIFT (31U)
5114#define CCM_PRE_ROOT_SET_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY4_SHIFT)) & CCM_PRE_ROOT_SET_BUSY4_MASK)
5115/*! @} */
5116
5117/* The count of CCM_PRE_ROOT_SET */
5118#define CCM_PRE_ROOT_SET_COUNT (142U)
5119
5120/*! @name PRE_ROOT_CLR - Pre Divider Register */
5121/*! @{ */
5122#define CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK (0x7U)
5123#define CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT (0U)
5124/*! PRE_PODF_B
5125 * 0b000..Divide by 1
5126 * 0b001..Divide by 2
5127 * 0b010..Divide by 3
5128 * 0b011..Divide by 4
5129 * 0b100..Divide by 5
5130 * 0b101..Divide by 6
5131 * 0b110..Divide by 7
5132 * 0b111..Divide by 8
5133 */
5134#define CCM_PRE_ROOT_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK)
5135#define CCM_PRE_ROOT_CLR_BUSY0_MASK (0x8U)
5136#define CCM_PRE_ROOT_CLR_BUSY0_SHIFT (3U)
5137#define CCM_PRE_ROOT_CLR_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY0_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY0_MASK)
5138#define CCM_PRE_ROOT_CLR_MUX_B_MASK (0x700U)
5139#define CCM_PRE_ROOT_CLR_MUX_B_SHIFT (8U)
5140#define CCM_PRE_ROOT_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_B_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_B_MASK)
5141#define CCM_PRE_ROOT_CLR_EN_B_MASK (0x1000U)
5142#define CCM_PRE_ROOT_CLR_EN_B_SHIFT (12U)
5143/*! EN_B
5144 * 0b0..Clock shutdown
5145 * 0b1..Clock ON
5146 */
5147#define CCM_PRE_ROOT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_B_SHIFT)) & CCM_PRE_ROOT_CLR_EN_B_MASK)
5148#define CCM_PRE_ROOT_CLR_BUSY1_MASK (0x8000U)
5149#define CCM_PRE_ROOT_CLR_BUSY1_SHIFT (15U)
5150#define CCM_PRE_ROOT_CLR_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY1_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY1_MASK)
5151#define CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK (0x70000U)
5152#define CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT (16U)
5153/*! PRE_PODF_A
5154 * 0b000..Divide by 1
5155 * 0b001..Divide by 2
5156 * 0b010..Divide by 3
5157 * 0b011..Divide by 4
5158 * 0b100..Divide by 5
5159 * 0b101..Divide by 6
5160 * 0b110..Divide by 7
5161 * 0b111..Divide by 8
5162 */
5163#define CCM_PRE_ROOT_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK)
5164#define CCM_PRE_ROOT_CLR_BUSY3_MASK (0x80000U)
5165#define CCM_PRE_ROOT_CLR_BUSY3_SHIFT (19U)
5166#define CCM_PRE_ROOT_CLR_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY3_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY3_MASK)
5167#define CCM_PRE_ROOT_CLR_MUX_A_MASK (0x7000000U)
5168#define CCM_PRE_ROOT_CLR_MUX_A_SHIFT (24U)
5169#define CCM_PRE_ROOT_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_A_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_A_MASK)
5170#define CCM_PRE_ROOT_CLR_EN_A_MASK (0x10000000U)
5171#define CCM_PRE_ROOT_CLR_EN_A_SHIFT (28U)
5172/*! EN_A
5173 * 0b0..Clock shutdown
5174 * 0b1..clock ON
5175 */
5176#define CCM_PRE_ROOT_CLR_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_A_SHIFT)) & CCM_PRE_ROOT_CLR_EN_A_MASK)
5177#define CCM_PRE_ROOT_CLR_BUSY4_MASK (0x80000000U)
5178#define CCM_PRE_ROOT_CLR_BUSY4_SHIFT (31U)
5179#define CCM_PRE_ROOT_CLR_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY4_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY4_MASK)
5180/*! @} */
5181
5182/* The count of CCM_PRE_ROOT_CLR */
5183#define CCM_PRE_ROOT_CLR_COUNT (142U)
5184
5185/*! @name PRE_ROOT_TOG - Pre Divider Register */
5186/*! @{ */
5187#define CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK (0x7U)
5188#define CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT (0U)
5189/*! PRE_PODF_B
5190 * 0b000..Divide by 1
5191 * 0b001..Divide by 2
5192 * 0b010..Divide by 3
5193 * 0b011..Divide by 4
5194 * 0b100..Divide by 5
5195 * 0b101..Divide by 6
5196 * 0b110..Divide by 7
5197 * 0b111..Divide by 8
5198 */
5199#define CCM_PRE_ROOT_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK)
5200#define CCM_PRE_ROOT_TOG_BUSY0_MASK (0x8U)
5201#define CCM_PRE_ROOT_TOG_BUSY0_SHIFT (3U)
5202#define CCM_PRE_ROOT_TOG_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY0_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY0_MASK)
5203#define CCM_PRE_ROOT_TOG_MUX_B_MASK (0x700U)
5204#define CCM_PRE_ROOT_TOG_MUX_B_SHIFT (8U)
5205#define CCM_PRE_ROOT_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_B_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_B_MASK)
5206#define CCM_PRE_ROOT_TOG_EN_B_MASK (0x1000U)
5207#define CCM_PRE_ROOT_TOG_EN_B_SHIFT (12U)
5208/*! EN_B
5209 * 0b0..Clock shutdown
5210 * 0b1..Clock ON
5211 */
5212#define CCM_PRE_ROOT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_B_SHIFT)) & CCM_PRE_ROOT_TOG_EN_B_MASK)
5213#define CCM_PRE_ROOT_TOG_BUSY1_MASK (0x8000U)
5214#define CCM_PRE_ROOT_TOG_BUSY1_SHIFT (15U)
5215#define CCM_PRE_ROOT_TOG_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY1_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY1_MASK)
5216#define CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK (0x70000U)
5217#define CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT (16U)
5218/*! PRE_PODF_A
5219 * 0b000..Divide by 1
5220 * 0b001..Divide by 2
5221 * 0b010..Divide by 3
5222 * 0b011..Divide by 4
5223 * 0b100..Divide by 5
5224 * 0b101..Divide by 6
5225 * 0b110..Divide by 7
5226 * 0b111..Divide by 8
5227 */
5228#define CCM_PRE_ROOT_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK)
5229#define CCM_PRE_ROOT_TOG_BUSY3_MASK (0x80000U)
5230#define CCM_PRE_ROOT_TOG_BUSY3_SHIFT (19U)
5231#define CCM_PRE_ROOT_TOG_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY3_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY3_MASK)
5232#define CCM_PRE_ROOT_TOG_MUX_A_MASK (0x7000000U)
5233#define CCM_PRE_ROOT_TOG_MUX_A_SHIFT (24U)
5234#define CCM_PRE_ROOT_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_A_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_A_MASK)
5235#define CCM_PRE_ROOT_TOG_EN_A_MASK (0x10000000U)
5236#define CCM_PRE_ROOT_TOG_EN_A_SHIFT (28U)
5237/*! EN_A
5238 * 0b0..Clock shutdown
5239 * 0b1..clock ON
5240 */
5241#define CCM_PRE_ROOT_TOG_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_A_SHIFT)) & CCM_PRE_ROOT_TOG_EN_A_MASK)
5242#define CCM_PRE_ROOT_TOG_BUSY4_MASK (0x80000000U)
5243#define CCM_PRE_ROOT_TOG_BUSY4_SHIFT (31U)
5244#define CCM_PRE_ROOT_TOG_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY4_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY4_MASK)
5245/*! @} */
5246
5247/* The count of CCM_PRE_ROOT_TOG */
5248#define CCM_PRE_ROOT_TOG_COUNT (142U)
5249
5250/*! @name ACCESS_CTRL - Access Control Register */
5251/*! @{ */
5252#define CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK (0xFU)
5253#define CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT (0U)
5254#define CCM_ACCESS_CTRL_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK)
5255#define CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK (0xF0U)
5256#define CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT (4U)
5257#define CCM_ACCESS_CTRL_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK)
5258#define CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK (0xF00U)
5259#define CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT (8U)
5260#define CCM_ACCESS_CTRL_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK)
5261#define CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK (0xF000U)
5262#define CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT (12U)
5263#define CCM_ACCESS_CTRL_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK)
5264#define CCM_ACCESS_CTRL_OWNER_ID_MASK (0x30000U)
5265#define CCM_ACCESS_CTRL_OWNER_ID_SHIFT (16U)
5266/*! OWNER_ID
5267 * 0b00..domaino
5268 * 0b01..domain1
5269 * 0b10..domain2
5270 * 0b11..domain3
5271 */
5272#define CCM_ACCESS_CTRL_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_OWNER_ID_MASK)
5273#define CCM_ACCESS_CTRL_MUTEX_MASK (0x100000U)
5274#define CCM_ACCESS_CTRL_MUTEX_SHIFT (20U)
5275/*! MUTEX
5276 * 0b0..Semaphore is free to take
5277 * 0b1..Semaphore is taken
5278 */
5279#define CCM_ACCESS_CTRL_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_MUTEX_MASK)
5280#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK (0x1000000U)
5281#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT (24U)
5282/*! DOMAIN0_WHITELIST
5283 * 0b0..Domain cannot change the setting
5284 * 0b1..Domain can change the setting
5285 */
5286#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK)
5287#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK (0x2000000U)
5288#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT (25U)
5289/*! DOMAIN1_WHITELIST
5290 * 0b0..Domain cannot change the setting
5291 * 0b1..Domain can change the setting
5292 */
5293#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK)
5294#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK (0x4000000U)
5295#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT (26U)
5296/*! DOMAIN2_WHITELIST
5297 * 0b0..Domain cannot change the setting
5298 * 0b1..Domain can change the setting
5299 */
5300#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK)
5301#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK (0x8000000U)
5302#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT (27U)
5303/*! DOMAIN3_WHITELIST
5304 * 0b0..Domain cannot change the setting
5305 * 0b1..Domain can change the setting
5306 */
5307#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK)
5308#define CCM_ACCESS_CTRL_SEMA_EN_MASK (0x10000000U)
5309#define CCM_ACCESS_CTRL_SEMA_EN_SHIFT (28U)
5310/*! SEMA_EN
5311 * 0b0..Disable
5312 * 0b1..Enable
5313 */
5314#define CCM_ACCESS_CTRL_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_SEMA_EN_MASK)
5315#define CCM_ACCESS_CTRL_LOCK_MASK (0x80000000U)
5316#define CCM_ACCESS_CTRL_LOCK_SHIFT (31U)
5317/*! LOCK
5318 * 0b0..Access control inactive
5319 * 0b1..Access control active
5320 */
5321#define CCM_ACCESS_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_LOCK_SHIFT)) & CCM_ACCESS_CTRL_LOCK_MASK)
5322/*! @} */
5323
5324/* The count of CCM_ACCESS_CTRL */
5325#define CCM_ACCESS_CTRL_COUNT (142U)
5326
5327/*! @name ACCESS_CTRL_ROOT_SET - Access Control Register */
5328/*! @{ */
5329#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK (0xFU)
5330#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT (0U)
5331#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK)
5332#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK (0xF0U)
5333#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT (4U)
5334#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK)
5335#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK (0xF00U)
5336#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT (8U)
5337#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK)
5338#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK (0xF000U)
5339#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT (12U)
5340#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK)
5341#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK (0x30000U)
5342#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT (16U)
5343/*! OWNER_ID
5344 * 0b00..domaino
5345 * 0b01..domain1
5346 * 0b10..domain2
5347 * 0b11..domain3
5348 */
5349#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK)
5350#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK (0x100000U)
5351#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT (20U)
5352/*! MUTEX
5353 * 0b0..Semaphore is free to take
5354 * 0b1..Semaphore is taken
5355 */
5356#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK)
5357#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK (0x1000000U)
5358#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT (24U)
5359/*! DOMAIN0_WHITELIST
5360 * 0b0..Domain cannot change the setting
5361 * 0b1..Domain can change the setting
5362 */
5363#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK)
5364#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK (0x2000000U)
5365#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT (25U)
5366/*! DOMAIN1_WHITELIST
5367 * 0b0..Domain cannot change the setting
5368 * 0b1..Domain can change the setting
5369 */
5370#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK)
5371#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK (0x4000000U)
5372#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT (26U)
5373/*! DOMAIN2_WHITELIST
5374 * 0b0..Domain cannot change the setting
5375 * 0b1..Domain can change the setting
5376 */
5377#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK)
5378#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK (0x8000000U)
5379#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT (27U)
5380/*! DOMAIN3_WHITELIST
5381 * 0b0..Domain cannot change the setting
5382 * 0b1..Domain can change the setting
5383 */
5384#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK)
5385#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK (0x10000000U)
5386#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT (28U)
5387/*! SEMA_EN
5388 * 0b0..Disable
5389 * 0b1..Enable
5390 */
5391#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK)
5392#define CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK (0x80000000U)
5393#define CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT (31U)
5394/*! LOCK
5395 * 0b0..Access control inactive
5396 * 0b1..Access control active
5397 */
5398#define CCM_ACCESS_CTRL_ROOT_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK)
5399/*! @} */
5400
5401/* The count of CCM_ACCESS_CTRL_ROOT_SET */
5402#define CCM_ACCESS_CTRL_ROOT_SET_COUNT (142U)
5403
5404/*! @name ACCESS_CTRL_ROOT_CLR - Access Control Register */
5405/*! @{ */
5406#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK (0xFU)
5407#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT (0U)
5408#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK)
5409#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK (0xF0U)
5410#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT (4U)
5411#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK)
5412#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK (0xF00U)
5413#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT (8U)
5414#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK)
5415#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK (0xF000U)
5416#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT (12U)
5417#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK)
5418#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK (0x30000U)
5419#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT (16U)
5420/*! OWNER_ID
5421 * 0b00..domaino
5422 * 0b01..domain1
5423 * 0b10..domain2
5424 * 0b11..domain3
5425 */
5426#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK)
5427#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK (0x100000U)
5428#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT (20U)
5429/*! MUTEX
5430 * 0b0..Semaphore is free to take
5431 * 0b1..Semaphore is taken
5432 */
5433#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK)
5434#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK (0x1000000U)
5435#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT (24U)
5436/*! DOMAIN0_WHITELIST
5437 * 0b0..Domain cannot change the setting
5438 * 0b1..Domain can change the setting
5439 */
5440#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK)
5441#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK (0x2000000U)
5442#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT (25U)
5443/*! DOMAIN1_WHITELIST
5444 * 0b0..Domain cannot change the setting
5445 * 0b1..Domain can change the setting
5446 */
5447#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK)
5448#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK (0x4000000U)
5449#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT (26U)
5450/*! DOMAIN2_WHITELIST
5451 * 0b0..Domain cannot change the setting
5452 * 0b1..Domain can change the setting
5453 */
5454#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK)
5455#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK (0x8000000U)
5456#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT (27U)
5457/*! DOMAIN3_WHITELIST
5458 * 0b0..Domain cannot change the setting
5459 * 0b1..Domain can change the setting
5460 */
5461#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK)
5462#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK (0x10000000U)
5463#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT (28U)
5464/*! SEMA_EN
5465 * 0b0..Disable
5466 * 0b1..Enable
5467 */
5468#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK)
5469#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK (0x80000000U)
5470#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT (31U)
5471/*! LOCK
5472 * 0b0..Access control inactive
5473 * 0b1..Access control active
5474 */
5475#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK)
5476/*! @} */
5477
5478/* The count of CCM_ACCESS_CTRL_ROOT_CLR */
5479#define CCM_ACCESS_CTRL_ROOT_CLR_COUNT (142U)
5480
5481/*! @name ACCESS_CTRL_ROOT_TOG - Access Control Register */
5482/*! @{ */
5483#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK (0xFU)
5484#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT (0U)
5485#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK)
5486#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK (0xF0U)
5487#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT (4U)
5488#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK)
5489#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK (0xF00U)
5490#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT (8U)
5491#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK)
5492#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK (0xF000U)
5493#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT (12U)
5494#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK)
5495#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK (0x30000U)
5496#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT (16U)
5497/*! OWNER_ID
5498 * 0b00..domaino
5499 * 0b01..domain1
5500 * 0b10..domain2
5501 * 0b11..domain3
5502 */
5503#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK)
5504#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK (0x100000U)
5505#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT (20U)
5506/*! MUTEX
5507 * 0b0..Semaphore is free to take
5508 * 0b1..Semaphore is taken
5509 */
5510#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK)
5511#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK (0x1000000U)
5512#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT (24U)
5513/*! DOMAIN0_WHITELIST
5514 * 0b0..Domain cannot change the setting
5515 * 0b1..Domain can change the setting
5516 */
5517#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK)
5518#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK (0x2000000U)
5519#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT (25U)
5520/*! DOMAIN1_WHITELIST
5521 * 0b0..Domain cannot change the setting
5522 * 0b1..Domain can change the setting
5523 */
5524#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK)
5525#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK (0x4000000U)
5526#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT (26U)
5527/*! DOMAIN2_WHITELIST
5528 * 0b0..Domain cannot change the setting
5529 * 0b1..Domain can change the setting
5530 */
5531#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK)
5532#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK (0x8000000U)
5533#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT (27U)
5534/*! DOMAIN3_WHITELIST
5535 * 0b0..Domain cannot change the setting
5536 * 0b1..Domain can change the setting
5537 */
5538#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK)
5539#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK (0x10000000U)
5540#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT (28U)
5541/*! SEMA_EN
5542 * 0b0..Disable
5543 * 0b1..Enable
5544 */
5545#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK)
5546#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK (0x80000000U)
5547#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT (31U)
5548/*! LOCK
5549 * 0b0..Access control inactive
5550 * 0b1..Access control active
5551 */
5552#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK)
5553/*! @} */
5554
5555/* The count of CCM_ACCESS_CTRL_ROOT_TOG */
5556#define CCM_ACCESS_CTRL_ROOT_TOG_COUNT (142U)
5557
5558
5559/*!
5560 * @}
5561 */ /* end of group CCM_Register_Masks */
5562
5563
5564/* CCM - Peripheral instance base addresses */
5565/** Peripheral CCM base address */
5566#define CCM_BASE (0x30380000u)
5567/** Peripheral CCM base pointer */
5568#define CCM ((CCM_Type *)CCM_BASE)
5569/** Array initializer of CCM peripheral base addresses */
5570#define CCM_BASE_ADDRS { CCM_BASE }
5571/** Array initializer of CCM peripheral base pointers */
5572#define CCM_BASE_PTRS { CCM }
5573/** Interrupt vectors for the CCM peripheral type */
5574#define CCM_IRQS { CCM_IRQ1_IRQn, CCM_IRQ2_IRQn }
5575
5576/*!
5577 * @}
5578 */ /* end of group CCM_Peripheral_Access_Layer */
5579
5580
5581/* ----------------------------------------------------------------------------
5582 -- CCM_ANALOG Peripheral Access Layer
5583 ---------------------------------------------------------------------------- */
5584
5585/*!
5586 * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer
5587 * @{
5588 */
5589
5590/** CCM_ANALOG - Register Layout Typedef */
5591typedef struct {
5592 __IO uint32_t AUDIO_PLL1_GEN_CTRL; /**< AUDIO PLL1 General Function Control Register, offset: 0x0 */
5593 __IO uint32_t AUDIO_PLL1_FDIV_CTL0; /**< AUDIO PLL1 Divide and Fraction Data Control 0 Register, offset: 0x4 */
5594 __IO uint32_t AUDIO_PLL1_FDIV_CTL1; /**< AUDIO PLL1 Divide and Fraction Data Control 1 Register, offset: 0x8 */
5595 __IO uint32_t AUDIO_PLL1_SSCG_CTRL; /**< AUDIO PLL1 PLL SSCG Control Register, offset: 0xC */
5596 __IO uint32_t AUDIO_PLL1_MNIT_CTRL; /**< AUDIO PLL1 PLL Monitoring Control Register, offset: 0x10 */
5597 __IO uint32_t AUDIO_PLL2_GEN_CTRL; /**< AUDIO PLL2 General Function Control Register, offset: 0x14 */
5598 __IO uint32_t AUDIO_PLL2_FDIV_CTL0; /**< AUDIO PLL2 Divide and Fraction Data Control 0 Register, offset: 0x18 */
5599 __IO uint32_t AUDIO_PLL2_FDIV_CTL1; /**< AUDIO PLL2 Divide and Fraction Data Control 1 Register, offset: 0x1C */
5600 __IO uint32_t AUDIO_PLL2_SSCG_CTRL; /**< AUDIO PLL2 PLL SSCG Control Register, offset: 0x20 */
5601 __IO uint32_t AUDIO_PLL2_MNIT_CTRL; /**< AUDIO PLL2 PLL Monitoring Control Register, offset: 0x24 */
5602 __IO uint32_t VIDEO_PLL1_GEN_CTRL; /**< VIDEO PLL1 General Function Control Register, offset: 0x28 */
5603 __IO uint32_t VIDEO_PLL1_FDIV_CTL0; /**< VIDEO PLL1 Divide and Fraction Data Control 0 Register, offset: 0x2C */
5604 __IO uint32_t VIDEO_PLL1_FDIV_CTL1; /**< VIDEO PLL1 Divide and Fraction Data Control 1 Register, offset: 0x30 */
5605 __IO uint32_t VIDEO_PLL1_SSCG_CTRL; /**< VIDEO PLL1 PLL SSCG Control Register, offset: 0x34 */
5606 __IO uint32_t VIDEO_PLL1_MNIT_CTRL; /**< VIDEO PLL1 PLL Monitoring Control Register, offset: 0x38 */
5607 uint8_t RESERVED_0[20];
5608 __IO uint32_t DRAM_PLL_GEN_CTRL; /**< DRAM PLL General Function Control Register, offset: 0x50 */
5609 __IO uint32_t DRAM_PLL_FDIV_CTL0; /**< DRAM PLL Divide and Fraction Data Control 0 Register, offset: 0x54 */
5610 __IO uint32_t DRAM_PLL_FDIV_CTL1; /**< DRAM PLL Divide and Fraction Data Control 1 Register, offset: 0x58 */
5611 __IO uint32_t DRAM_PLL_SSCG_CTRL; /**< DRAM PLL PLL SSCG Control Register, offset: 0x5C */
5612 __IO uint32_t DRAM_PLL_MNIT_CTRL; /**< DRAM PLL PLL Monitoring Control Register, offset: 0x60 */
5613 __IO uint32_t GPU_PLL_GEN_CTRL; /**< GPU PLL General Function Control Register, offset: 0x64 */
5614 __IO uint32_t GPU_PLL_FDIV_CTL0; /**< GPU PLL Divide and Fraction Data Control 0 Register, offset: 0x68 */
5615 __IO uint32_t GPU_PLL_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x6C */
5616 __IO uint32_t GPU_PLL_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x70 */
5617 __IO uint32_t VPU_PLL_GEN_CTRL; /**< VPU PLL General Function Control Register, offset: 0x74 */
5618 __IO uint32_t VPU_PLL_FDIV_CTL0; /**< VPU PLL Divide and Fraction Data Control 0 Register, offset: 0x78 */
5619 __IO uint32_t VPU_PLL_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x7C */
5620 __IO uint32_t VPU_PLL_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x80 */
5621 __IO uint32_t ARM_PLL_GEN_CTRL; /**< ARM PLL General Function Control Register, offset: 0x84 */
5622 __IO uint32_t ARM_PLL_FDIV_CTL0; /**< ARM PLL Divide and Fraction Data Control 0 Register, offset: 0x88 */
5623 __IO uint32_t ARM_PLL_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x8C */
5624 __IO uint32_t ARM_PLL_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x90 */
5625 __IO uint32_t SYS_PLL1_GEN_CTRL; /**< SYS PLL1 General Function Control Register, offset: 0x94 */
5626 __IO uint32_t SYS_PLL1_FDIV_CTL0; /**< SYS PLL1 Divide and Fraction Data Control 0 Register, offset: 0x98 */
5627 __IO uint32_t SYS_PLL1_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x9C */
5628 uint8_t RESERVED_1[96];
5629 __IO uint32_t SYS_PLL1_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x100 */
5630 __IO uint32_t SYS_PLL2_GEN_CTRL; /**< SYS PLL2 General Function Control Register, offset: 0x104 */
5631 __IO uint32_t SYS_PLL2_FDIV_CTL0; /**< SYS PLL2 Divide and Fraction Data Control 0 Register, offset: 0x108 */
5632 __IO uint32_t SYS_PLL2_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x10C */
5633 __IO uint32_t SYS_PLL2_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x110 */
5634 __IO uint32_t SYS_PLL3_GEN_CTRL; /**< SYS PLL3 General Function Control Register, offset: 0x114 */
5635 __IO uint32_t SYS_PLL3_FDIV_CTL0; /**< SYS PLL3 Divide and Fraction Data Control 0 Register, offset: 0x118 */
5636 __IO uint32_t SYS_PLL3_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x11C */
5637 __IO uint32_t SYS_PLL3_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x120 */
5638 __IO uint32_t OSC_MISC_CFG; /**< Osc Misc Configuration Register, offset: 0x124 */
5639 __IO uint32_t ANAMIX_PLL_MNIT_CTL; /**< PLL Clock Output for Test Enable and Select Register, offset: 0x128 */
5640 uint8_t RESERVED_2[1748];
5641 __I uint32_t DIGPROG; /**< DIGPROG Register, offset: 0x800 */
5642} CCM_ANALOG_Type;
5643
5644/* ----------------------------------------------------------------------------
5645 -- CCM_ANALOG Register Masks
5646 ---------------------------------------------------------------------------- */
5647
5648/*!
5649 * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks
5650 * @{
5651 */
5652
5653/*! @name AUDIO_PLL1_GEN_CTRL - AUDIO PLL1 General Function Control Register */
5654/*! @{ */
5655#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
5656#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
5657/*! PLL_REF_CLK_SEL
5658 * 0b00..SYS_XTAL
5659 * 0b01..PAD_CLK
5660 * 0b10..Reserved
5661 * 0b11..Reserved
5662 */
5663#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
5664#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
5665#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
5666/*! PAD_CLK_SEL
5667 * 0b00..CLKIN1 XOR CLKIN2
5668 * 0b01..CLKIN2
5669 * 0b10..CLKIN1
5670 * 0b11..Reserved
5671 */
5672#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK)
5673#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
5674#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
5675#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_MASK)
5676#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
5677#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
5678#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
5679#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U)
5680#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U)
5681#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_MASK)
5682#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
5683#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
5684#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
5685#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
5686#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (13U)
5687#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_MASK)
5688#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
5689#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
5690#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK)
5691#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
5692#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U)
5693#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_MASK)
5694/*! @} */
5695
5696/*! @name AUDIO_PLL1_FDIV_CTL0 - AUDIO PLL1 Divide and Fraction Data Control 0 Register */
5697/*! @{ */
5698#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
5699#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
5700#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK)
5701#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
5702#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
5703#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK)
5704#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
5705#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
5706#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK)
5707/*! @} */
5708
5709/*! @name AUDIO_PLL1_FDIV_CTL1 - AUDIO PLL1 Divide and Fraction Data Control 1 Register */
5710/*! @{ */
5711#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
5712#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT (0U)
5713#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_MASK)
5714/*! @} */
5715
5716/*! @name AUDIO_PLL1_SSCG_CTRL - AUDIO PLL1 PLL SSCG Control Register */
5717/*! @{ */
5718#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_MASK (0x3U)
5719#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_SHIFT (0U)
5720/*! SEL_PF
5721 * 0b00..Down spread
5722 * 0b01..Up spread
5723 * 0b1x..Center spread
5724 */
5725#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_MASK)
5726#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
5727#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
5728#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK)
5729#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
5730#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
5731#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
5732#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
5733#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT (31U)
5734#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_MASK)
5735/*! @} */
5736
5737/*! @name AUDIO_PLL1_MNIT_CTRL - AUDIO PLL1 PLL Monitoring Control Register */
5738/*! @{ */
5739#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_MASK (0x7U)
5740#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_SHIFT (0U)
5741#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_MASK)
5742#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_MASK (0x8U)
5743#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_SHIFT (3U)
5744#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_MASK)
5745#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
5746#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_SHIFT (4U)
5747#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_MASK)
5748#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_MASK (0x4000U)
5749#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_SHIFT (14U)
5750#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_MASK)
5751#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_MASK (0x8000U)
5752#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_SHIFT (15U)
5753/*! FSEL
5754 * 0b0..FEED_OUT = FREF
5755 * 0b1..FEED_OUT = FEED
5756 */
5757#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_MASK)
5758#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
5759#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
5760/*! AFCINIT_SEL
5761 * 0b0..nominal delay
5762 * 0b1..nominal delay * 2
5763 */
5764#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK)
5765#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
5766#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
5767#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
5768#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
5769#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
5770/*! PBIAS_CTRL
5771 * 0b0..0.50*VDD
5772 * 0b1..0.67*VDD
5773 */
5774#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK)
5775#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
5776#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (20U)
5777#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_MASK)
5778/*! @} */
5779
5780/*! @name AUDIO_PLL2_GEN_CTRL - AUDIO PLL2 General Function Control Register */
5781/*! @{ */
5782#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
5783#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
5784/*! PLL_REF_CLK_SEL
5785 * 0b00..SYS_XTAL
5786 * 0b01..PAD_CLK
5787 * 0b10..Reserved
5788 * 0b11..Reserved
5789 */
5790#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
5791#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
5792#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
5793/*! PAD_CLK_SEL
5794 * 0b00..CLKIN1 XOR CLKIN2
5795 * 0b01..CLKIN2
5796 * 0b10..CLKIN1
5797 * 0b11..Reserved
5798 */
5799#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK)
5800#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
5801#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
5802#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_MASK)
5803#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
5804#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
5805#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
5806#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_MASK (0x200U)
5807#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT (9U)
5808#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_MASK)
5809#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
5810#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
5811#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
5812#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
5813#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT (13U)
5814#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_MASK)
5815#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
5816#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
5817#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK)
5818#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
5819#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_SHIFT (31U)
5820#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_MASK)
5821/*! @} */
5822
5823/*! @name AUDIO_PLL2_FDIV_CTL0 - AUDIO PLL2 Divide and Fraction Data Control 0 Register */
5824/*! @{ */
5825#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
5826#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
5827#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK)
5828#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
5829#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
5830#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK)
5831#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
5832#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
5833#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK)
5834/*! @} */
5835
5836/*! @name AUDIO_PLL2_FDIV_CTL1 - AUDIO PLL2 Divide and Fraction Data Control 1 Register */
5837/*! @{ */
5838#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
5839#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_SHIFT (0U)
5840#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_MASK)
5841/*! @} */
5842
5843/*! @name AUDIO_PLL2_SSCG_CTRL - AUDIO PLL2 PLL SSCG Control Register */
5844/*! @{ */
5845#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_MASK (0x3U)
5846#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_SHIFT (0U)
5847/*! SEL_PF
5848 * 0b00..Down spread
5849 * 0b01..Up spread
5850 * 0b1x..Center spread
5851 */
5852#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_MASK)
5853#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
5854#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
5855#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_MASK)
5856#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
5857#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
5858#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
5859#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
5860#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_SHIFT (31U)
5861#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_MASK)
5862/*! @} */
5863
5864/*! @name AUDIO_PLL2_MNIT_CTRL - AUDIO PLL2 PLL Monitoring Control Register */
5865/*! @{ */
5866#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_MASK (0x7U)
5867#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_SHIFT (0U)
5868#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_MASK)
5869#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_MASK (0x8U)
5870#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_SHIFT (3U)
5871#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_MASK)
5872#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
5873#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_SHIFT (4U)
5874#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_MASK)
5875#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_MASK (0x4000U)
5876#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_SHIFT (14U)
5877#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_MASK)
5878#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_MASK (0x8000U)
5879#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_SHIFT (15U)
5880/*! FSEL
5881 * 0b0..FEED_OUT = FREF
5882 * 0b1..FEED_OUT = FEED
5883 */
5884#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_MASK)
5885#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
5886#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
5887/*! AFCINIT_SEL
5888 * 0b0..nominal delay
5889 * 0b1..nominal delay * 2
5890 */
5891#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK)
5892#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
5893#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
5894#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
5895#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
5896#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
5897/*! PBIAS_CTRL
5898 * 0b0..0.50*VDD
5899 * 0b1..0.67*VDD
5900 */
5901#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK)
5902#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
5903#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_SHIFT (20U)
5904#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_MASK)
5905/*! @} */
5906
5907/*! @name VIDEO_PLL1_GEN_CTRL - VIDEO PLL1 General Function Control Register */
5908/*! @{ */
5909#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
5910#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
5911/*! PLL_REF_CLK_SEL
5912 * 0b00..SYS_XTAL
5913 * 0b01..PAD_CLK
5914 * 0b10..Reserved
5915 * 0b11..Reserved
5916 */
5917#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
5918#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
5919#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
5920/*! PAD_CLK_SEL
5921 * 0b00..CLKIN1 XOR CLKIN2
5922 * 0b01..CLKIN2
5923 * 0b10..CLKIN1
5924 * 0b11..Reserved
5925 */
5926#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK)
5927#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
5928#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
5929#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_MASK)
5930#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
5931#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
5932#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
5933#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U)
5934#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U)
5935#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_MASK)
5936#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
5937#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
5938#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
5939#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
5940#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (13U)
5941#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_MASK)
5942#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
5943#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
5944#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK)
5945#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
5946#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U)
5947#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_MASK)
5948/*! @} */
5949
5950/*! @name VIDEO_PLL1_FDIV_CTL0 - VIDEO PLL1 Divide and Fraction Data Control 0 Register */
5951/*! @{ */
5952#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
5953#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
5954#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK)
5955#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
5956#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
5957#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK)
5958#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
5959#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
5960#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK)
5961/*! @} */
5962
5963/*! @name VIDEO_PLL1_FDIV_CTL1 - VIDEO PLL1 Divide and Fraction Data Control 1 Register */
5964/*! @{ */
5965#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
5966#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT (0U)
5967#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_MASK)
5968/*! @} */
5969
5970/*! @name VIDEO_PLL1_SSCG_CTRL - VIDEO PLL1 PLL SSCG Control Register */
5971/*! @{ */
5972#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_MASK (0x3U)
5973#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_SHIFT (0U)
5974/*! SEL_PF
5975 * 0b00..Down spread
5976 * 0b01..Up spread
5977 * 0b1x..Center spread
5978 */
5979#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_MASK)
5980#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
5981#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
5982#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK)
5983#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
5984#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
5985#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
5986#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
5987#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT (31U)
5988#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_MASK)
5989/*! @} */
5990
5991/*! @name VIDEO_PLL1_MNIT_CTRL - VIDEO PLL1 PLL Monitoring Control Register */
5992/*! @{ */
5993#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_MASK (0x7U)
5994#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_SHIFT (0U)
5995#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_MASK)
5996#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_MASK (0x8U)
5997#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_SHIFT (3U)
5998#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_MASK)
5999#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
6000#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_SHIFT (4U)
6001#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_MASK)
6002#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_MASK (0x4000U)
6003#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_SHIFT (14U)
6004#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_MASK)
6005#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_MASK (0x8000U)
6006#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_SHIFT (15U)
6007/*! FSEL
6008 * 0b0..FEED_OUT = FREF
6009 * 0b1..FEED_OUT = FEED
6010 */
6011#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_MASK)
6012#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
6013#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
6014/*! AFCINIT_SEL
6015 * 0b0..nominal delay
6016 * 0b1..nominal delay * 2
6017 */
6018#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK)
6019#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
6020#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
6021#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
6022#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
6023#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
6024/*! PBIAS_CTRL
6025 * 0b0..0.50*VDD
6026 * 0b1..0.67*VDD
6027 */
6028#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK)
6029#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
6030#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (20U)
6031#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_MASK)
6032/*! @} */
6033
6034/*! @name DRAM_PLL_GEN_CTRL - DRAM PLL General Function Control Register */
6035/*! @{ */
6036#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
6037#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
6038/*! PLL_REF_CLK_SEL
6039 * 0b00..SYS_XTAL
6040 * 0b01..PAD_CLK
6041 * 0b10..Reserved
6042 * 0b11..Reserved
6043 */
6044#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
6045#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
6046#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
6047/*! PAD_CLK_SEL
6048 * 0b00..CLKIN1 XOR CLKIN2
6049 * 0b01..CLKIN2
6050 * 0b10..CLKIN1
6051 * 0b11..Reserved
6052 */
6053#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
6054#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
6055#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
6056#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_MASK)
6057#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
6058#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
6059#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
6060#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
6061#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
6062#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_MASK)
6063#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
6064#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
6065#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
6066#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
6067#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT (13U)
6068#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_MASK)
6069#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
6070#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
6071#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
6072#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
6073#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
6074#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_MASK)
6075/*! @} */
6076
6077/*! @name DRAM_PLL_FDIV_CTL0 - DRAM PLL Divide and Fraction Data Control 0 Register */
6078/*! @{ */
6079#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
6080#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
6081#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
6082#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
6083#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
6084#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
6085#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
6086#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
6087#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
6088/*! @} */
6089
6090/*! @name DRAM_PLL_FDIV_CTL1 - DRAM PLL Divide and Fraction Data Control 1 Register */
6091/*! @{ */
6092#define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
6093#define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_SHIFT (0U)
6094#define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_SHIFT)) & CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_MASK)
6095/*! @} */
6096
6097/*! @name DRAM_PLL_SSCG_CTRL - DRAM PLL PLL SSCG Control Register */
6098/*! @{ */
6099#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_MASK (0x3U)
6100#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_SHIFT (0U)
6101/*! SEL_PF
6102 * 0b00..Down spread
6103 * 0b01..Up spread
6104 * 0b1x..Center spread
6105 */
6106#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_SHIFT)) & CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_MASK)
6107#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
6108#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
6109#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_MASK)
6110#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
6111#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
6112#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
6113#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
6114#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_SHIFT (31U)
6115#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_SHIFT)) & CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_MASK)
6116/*! @} */
6117
6118/*! @name DRAM_PLL_MNIT_CTRL - DRAM PLL PLL Monitoring Control Register */
6119/*! @{ */
6120#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_MASK (0x7U)
6121#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_SHIFT (0U)
6122#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_MASK)
6123#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_MASK (0x8U)
6124#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_SHIFT (3U)
6125#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_MASK)
6126#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
6127#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_SHIFT (4U)
6128#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_MASK)
6129#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_MASK (0x4000U)
6130#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_SHIFT (14U)
6131#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_MASK)
6132#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_MASK (0x8000U)
6133#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_SHIFT (15U)
6134/*! FSEL
6135 * 0b0..FEED_OUT = FREF
6136 * 0b1..FEED_OUT = FEED
6137 */
6138#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_MASK)
6139#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
6140#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
6141/*! AFCINIT_SEL
6142 * 0b0..nominal delay
6143 * 0b1..nominal delay * 2
6144 */
6145#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
6146#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
6147#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
6148#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
6149#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
6150#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
6151/*! PBIAS_CTRL
6152 * 0b0..0.50*VDD
6153 * 0b1..0.67*VDD
6154 */
6155#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
6156#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
6157#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_SHIFT (20U)
6158#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_MASK)
6159/*! @} */
6160
6161/*! @name GPU_PLL_GEN_CTRL - GPU PLL General Function Control Register */
6162/*! @{ */
6163#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
6164#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
6165/*! PLL_REF_CLK_SEL
6166 * 0b00..SYS_XTAL
6167 * 0b01..PAD_CLK
6168 * 0b10..Reserved
6169 * 0b11..Reserved
6170 */
6171#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
6172#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
6173#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
6174/*! PAD_CLK_SEL
6175 * 0b00..CLKIN1 XOR CLKIN2
6176 * 0b01..CLKIN2
6177 * 0b10..CLKIN1
6178 * 0b11..Reserved
6179 */
6180#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
6181#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
6182#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
6183#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_MASK)
6184#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
6185#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
6186#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
6187#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
6188#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
6189#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_MASK)
6190#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
6191#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
6192#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
6193#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U)
6194#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U)
6195#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_MASK)
6196#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
6197#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
6198#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
6199#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
6200#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
6201/*! PLL_LOCK_SEL
6202 * 0b0..Using PLL maximum lock time
6203 * 0b1..Using PLL output lock
6204 */
6205#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK)
6206#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
6207#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
6208#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_MASK)
6209/*! @} */
6210
6211/*! @name GPU_PLL_FDIV_CTL0 - GPU PLL Divide and Fraction Data Control 0 Register */
6212/*! @{ */
6213#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
6214#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
6215#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
6216#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
6217#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
6218#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
6219#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
6220#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
6221#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
6222/*! @} */
6223
6224/*! @name GPU_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
6225/*! @{ */
6226#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
6227#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
6228#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK)
6229#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
6230#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
6231#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK)
6232#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
6233#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
6234#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK)
6235/*! @} */
6236
6237/*! @name GPU_PLL_MNIT_CTRL - PLL Monitoring Control Register */
6238/*! @{ */
6239#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_MASK (0x3U)
6240#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_SHIFT (0U)
6241#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_MASK)
6242#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U)
6243#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U)
6244#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_MASK)
6245#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U)
6246#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U)
6247#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_MASK)
6248#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U)
6249#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U)
6250#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_MASK)
6251#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_MASK (0x4000U)
6252#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_SHIFT (14U)
6253/*! FSEL
6254 * 0b0..FEED_OUT = FREF
6255 * 0b1..FEED_OUT = FEED
6256 */
6257#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_MASK)
6258#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
6259#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
6260/*! AFCINIT_SEL
6261 * 0b0..nominal delay
6262 * 0b1..nominal delay * 2
6263 */
6264#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
6265#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
6266#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
6267#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
6268#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
6269#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
6270/*! PBIAS_CTRL
6271 * 0b0..0.50*VDD
6272 * 0b1..0.67*VDD
6273 */
6274#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
6275#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
6276#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U)
6277#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_MASK)
6278#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
6279#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
6280#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_MASK)
6281#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U)
6282#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U)
6283#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_MASK)
6284/*! @} */
6285
6286/*! @name VPU_PLL_GEN_CTRL - VPU PLL General Function Control Register */
6287/*! @{ */
6288#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
6289#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
6290/*! PLL_REF_CLK_SEL
6291 * 0b00..SYS_XTAL
6292 * 0b01..PAD_CLK
6293 * 0b10..Reserved
6294 * 0b11..Reserved
6295 */
6296#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
6297#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
6298#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
6299/*! PAD_CLK_SEL
6300 * 0b00..CLKIN1 XOR CLKIN2
6301 * 0b01..CLKIN2
6302 * 0b10..CLKIN1
6303 * 0b11..Reserved
6304 */
6305#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
6306#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
6307#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
6308#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_MASK)
6309#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
6310#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
6311#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
6312#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
6313#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
6314#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_MASK)
6315#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
6316#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
6317#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
6318#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U)
6319#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U)
6320#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_MASK)
6321#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
6322#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
6323#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
6324#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
6325#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
6326/*! PLL_LOCK_SEL
6327 * 0b0..Using PLL maximum lock time
6328 * 0b1..Using PLL output lock
6329 */
6330#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK)
6331#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
6332#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
6333#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_MASK)
6334/*! @} */
6335
6336/*! @name VPU_PLL_FDIV_CTL0 - VPU PLL Divide and Fraction Data Control 0 Register */
6337/*! @{ */
6338#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
6339#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
6340#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
6341#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
6342#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
6343#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
6344#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
6345#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
6346#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
6347/*! @} */
6348
6349/*! @name VPU_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
6350/*! @{ */
6351#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
6352#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
6353#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK)
6354#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
6355#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
6356#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK)
6357#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
6358#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
6359#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK)
6360/*! @} */
6361
6362/*! @name VPU_PLL_MNIT_CTRL - PLL Monitoring Control Register */
6363/*! @{ */
6364#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP_MASK (0x3U)
6365#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP_SHIFT (0U)
6366#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP_MASK)
6367#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U)
6368#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U)
6369#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN_MASK)
6370#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U)
6371#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U)
6372#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC_MASK)
6373#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U)
6374#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U)
6375#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN_MASK)
6376#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL_MASK (0x4000U)
6377#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL_SHIFT (14U)
6378/*! FSEL
6379 * 0b0..FEED_OUT = FREF
6380 * 0b1..FEED_OUT = FEED
6381 */
6382#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL_MASK)
6383#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
6384#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
6385/*! AFCINIT_SEL
6386 * 0b0..nominal delay
6387 * 0b1..nominal delay * 2
6388 */
6389#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
6390#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
6391#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
6392#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
6393#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
6394#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
6395/*! PBIAS_CTRL
6396 * 0b0..0.50*VDD
6397 * 0b1..0.67*VDD
6398 */
6399#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
6400#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
6401#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U)
6402#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL_MASK)
6403#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
6404#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
6405#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK_MASK)
6406#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U)
6407#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U)
6408#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN_MASK)
6409/*! @} */
6410
6411/*! @name ARM_PLL_GEN_CTRL - ARM PLL General Function Control Register */
6412/*! @{ */
6413#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
6414#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
6415/*! PLL_REF_CLK_SEL
6416 * 0b00..SYS_XTAL
6417 * 0b01..PAD_CLK
6418 * 0b10..Reserved
6419 * 0b11..Reserved
6420 */
6421#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
6422#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
6423#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
6424/*! PAD_CLK_SEL
6425 * 0b00..CLKIN1 XOR CLKIN2
6426 * 0b01..CLKIN2
6427 * 0b10..CLKIN1
6428 * 0b11..Reserved
6429 */
6430#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
6431#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
6432#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
6433#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_MASK)
6434#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
6435#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
6436#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
6437#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
6438#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
6439#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_MASK)
6440#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
6441#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
6442#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
6443#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U)
6444#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U)
6445#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_MASK)
6446#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
6447#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
6448#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
6449#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
6450#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
6451/*! PLL_LOCK_SEL
6452 * 0b0..Using PLL maximum lock time
6453 * 0b1..Using PLL output lock
6454 */
6455#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK)
6456#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
6457#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
6458#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_MASK)
6459/*! @} */
6460
6461/*! @name ARM_PLL_FDIV_CTL0 - ARM PLL Divide and Fraction Data Control 0 Register */
6462/*! @{ */
6463#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
6464#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
6465#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
6466#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
6467#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
6468#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
6469#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
6470#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
6471#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
6472/*! @} */
6473
6474/*! @name ARM_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
6475/*! @{ */
6476#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
6477#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
6478#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK)
6479#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
6480#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
6481#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK)
6482#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
6483#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
6484#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK)
6485/*! @} */
6486
6487/*! @name ARM_PLL_MNIT_CTRL - PLL Monitoring Control Register */
6488/*! @{ */
6489#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_MASK (0x3U)
6490#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_SHIFT (0U)
6491#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_MASK)
6492#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U)
6493#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U)
6494#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_MASK)
6495#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U)
6496#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U)
6497#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_MASK)
6498#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U)
6499#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U)
6500#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_MASK)
6501#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_MASK (0x4000U)
6502#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_SHIFT (14U)
6503/*! FSEL
6504 * 0b0..FEED_OUT = FREF
6505 * 0b1..FEED_OUT = FEED
6506 */
6507#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_MASK)
6508#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
6509#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
6510/*! AFCINIT_SEL
6511 * 0b0..nominal delay
6512 * 0b1..nominal delay * 2
6513 */
6514#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
6515#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
6516#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
6517#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
6518#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
6519#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
6520/*! PBIAS_CTRL
6521 * 0b0..0.50*VDD
6522 * 0b1..0.67*VDD
6523 */
6524#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
6525#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
6526#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U)
6527#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_MASK)
6528#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
6529#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
6530#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_MASK)
6531#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U)
6532#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U)
6533#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_MASK)
6534/*! @} */
6535
6536/*! @name SYS_PLL1_GEN_CTRL - SYS PLL1 General Function Control Register */
6537/*! @{ */
6538#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
6539#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
6540/*! PLL_REF_CLK_SEL
6541 * 0b00..SYS_XTAL
6542 * 0b01..PAD_CLK
6543 * 0b10..Reserved
6544 * 0b11..Reserved
6545 */
6546#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
6547#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
6548#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
6549/*! PAD_CLK_SEL
6550 * 0b00..CLKIN1 XOR CLKIN2
6551 * 0b01..CLKIN2
6552 * 0b10..CLKIN1
6553 * 0b11..Reserved
6554 */
6555#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK)
6556#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
6557#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
6558#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_MASK)
6559#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
6560#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
6561#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
6562#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U)
6563#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U)
6564#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_MASK)
6565#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
6566#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
6567#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
6568#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x800U)
6569#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (11U)
6570#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_MASK)
6571#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK (0x1000U)
6572#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT (12U)
6573#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK)
6574#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_MASK (0x2000U)
6575#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT (13U)
6576#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_MASK)
6577#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK (0x4000U)
6578#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT (14U)
6579#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK)
6580#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_MASK (0x8000U)
6581#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT (15U)
6582#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_MASK)
6583#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK (0x10000U)
6584#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT (16U)
6585#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK)
6586#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_MASK (0x20000U)
6587#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT (17U)
6588#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_MASK)
6589#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK (0x40000U)
6590#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT (18U)
6591#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK)
6592#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_MASK (0x80000U)
6593#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT (19U)
6594#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_MASK)
6595#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK (0x100000U)
6596#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT (20U)
6597#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK)
6598#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_MASK (0x200000U)
6599#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT (21U)
6600#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_MASK)
6601#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK (0x400000U)
6602#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT (22U)
6603#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK)
6604#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_MASK (0x800000U)
6605#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT (23U)
6606#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_MASK)
6607#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK (0x1000000U)
6608#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT (24U)
6609#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK)
6610#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_MASK (0x2000000U)
6611#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT (25U)
6612#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_MASK)
6613#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK (0x4000000U)
6614#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT (26U)
6615#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK)
6616#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_MASK (0x8000000U)
6617#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT (27U)
6618#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_MASK)
6619#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
6620#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
6621#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK)
6622#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
6623#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
6624/*! PLL_LOCK_SEL
6625 * 0b0..Using PLL maximum lock time
6626 * 0b1..Using PLL output lock
6627 */
6628#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_MASK)
6629#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
6630#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U)
6631#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK)
6632/*! @} */
6633
6634/*! @name SYS_PLL1_FDIV_CTL0 - SYS PLL1 Divide and Fraction Data Control 0 Register */
6635/*! @{ */
6636#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
6637#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
6638#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK)
6639#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
6640#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
6641#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK)
6642#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
6643#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
6644#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK)
6645/*! @} */
6646
6647/*! @name SYS_PLL1_LOCKD_CTRL - PLL Lock Detector Control Register */
6648/*! @{ */
6649#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
6650#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
6651#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_MASK)
6652#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
6653#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
6654#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_MASK)
6655#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
6656#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
6657#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_MASK)
6658/*! @} */
6659
6660/*! @name SYS_PLL1_MNIT_CTRL - PLL Monitoring Control Register */
6661/*! @{ */
6662#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_MASK (0x3U)
6663#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_SHIFT (0U)
6664#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_MASK)
6665#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_MASK (0x4U)
6666#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_SHIFT (2U)
6667#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_MASK)
6668#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_MASK (0xF8U)
6669#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_SHIFT (3U)
6670#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_MASK)
6671#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_MASK (0x2000U)
6672#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_SHIFT (13U)
6673#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_MASK)
6674#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_MASK (0x4000U)
6675#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_SHIFT (14U)
6676/*! FSEL
6677 * 0b0..FEED_OUT = FREF
6678 * 0b1..FEED_OUT = FEED
6679 */
6680#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_MASK)
6681#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
6682#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
6683/*! AFCINIT_SEL
6684 * 0b0..nominal delay
6685 * 0b1..nominal delay * 2
6686 */
6687#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK)
6688#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
6689#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
6690#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
6691#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
6692#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
6693/*! PBIAS_CTRL
6694 * 0b0..0.50*VDD
6695 * 0b1..0.67*VDD
6696 */
6697#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK)
6698#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
6699#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (19U)
6700#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_MASK)
6701#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
6702#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
6703#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_MASK)
6704#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_MASK (0x200000U)
6705#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_SHIFT (21U)
6706#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_MASK)
6707/*! @} */
6708
6709/*! @name SYS_PLL2_GEN_CTRL - SYS PLL2 General Function Control Register */
6710/*! @{ */
6711#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
6712#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
6713/*! PLL_REF_CLK_SEL
6714 * 0b00..SYS_XTAL
6715 * 0b01..PAD_CLK
6716 * 0b10..Reserved
6717 * 0b11..Reserved
6718 */
6719#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
6720#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
6721#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
6722/*! PAD_CLK_SEL
6723 * 0b00..CLKIN1 XOR CLKIN2
6724 * 0b01..CLKIN2
6725 * 0b10..CLKIN1
6726 * 0b11..Reserved
6727 */
6728#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK)
6729#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
6730#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
6731#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_MASK)
6732#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
6733#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
6734#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
6735#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_MASK (0x200U)
6736#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT (9U)
6737#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_MASK)
6738#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
6739#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
6740#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
6741#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_MASK (0x800U)
6742#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT (11U)
6743#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_MASK)
6744#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK (0x1000U)
6745#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT (12U)
6746#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK)
6747#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_MASK (0x2000U)
6748#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT (13U)
6749#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_MASK)
6750#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK (0x4000U)
6751#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT (14U)
6752#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK)
6753#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_MASK (0x8000U)
6754#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT (15U)
6755#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_MASK)
6756#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK (0x10000U)
6757#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT (16U)
6758#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK)
6759#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_MASK (0x20000U)
6760#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT (17U)
6761#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_MASK)
6762#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK (0x40000U)
6763#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT (18U)
6764#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK)
6765#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_MASK (0x80000U)
6766#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT (19U)
6767#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_MASK)
6768#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK (0x100000U)
6769#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT (20U)
6770#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK)
6771#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_MASK (0x200000U)
6772#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT (21U)
6773#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_MASK)
6774#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK (0x400000U)
6775#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT (22U)
6776#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK)
6777#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_MASK (0x800000U)
6778#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT (23U)
6779#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_MASK)
6780#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK (0x1000000U)
6781#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT (24U)
6782#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK)
6783#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_MASK (0x2000000U)
6784#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT (25U)
6785#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_MASK)
6786#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK (0x4000000U)
6787#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT (26U)
6788#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK)
6789#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_MASK (0x8000000U)
6790#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT (27U)
6791#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_MASK)
6792#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
6793#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
6794#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK)
6795#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
6796#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
6797/*! PLL_LOCK_SEL
6798 * 0b0..Using PLL maximum lock time
6799 * 0b1..Using PLL output lock
6800 */
6801#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_MASK)
6802#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
6803#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SHIFT (31U)
6804#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_MASK)
6805/*! @} */
6806
6807/*! @name SYS_PLL2_FDIV_CTL0 - SYS PLL2 Divide and Fraction Data Control 0 Register */
6808/*! @{ */
6809#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
6810#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
6811#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK)
6812#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
6813#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
6814#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK)
6815#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
6816#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
6817#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK)
6818/*! @} */
6819
6820/*! @name SYS_PLL2_LOCKD_CTRL - PLL Lock Detector Control Register */
6821/*! @{ */
6822#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
6823#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
6824#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_MASK)
6825#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
6826#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
6827#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_MASK)
6828#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
6829#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
6830#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_MASK)
6831/*! @} */
6832
6833/*! @name SYS_PLL2_MNIT_CTRL - PLL Monitoring Control Register */
6834/*! @{ */
6835#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_MASK (0x3U)
6836#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_SHIFT (0U)
6837#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_MASK)
6838#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_MASK (0x4U)
6839#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_SHIFT (2U)
6840#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_MASK)
6841#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_MASK (0xF8U)
6842#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_SHIFT (3U)
6843#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_MASK)
6844#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_MASK (0x2000U)
6845#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_SHIFT (13U)
6846#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_MASK)
6847#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_MASK (0x4000U)
6848#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_SHIFT (14U)
6849/*! FSEL
6850 * 0b0..FEED_OUT = FREF
6851 * 0b1..FEED_OUT = FEED
6852 */
6853#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_MASK)
6854#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
6855#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
6856/*! AFCINIT_SEL
6857 * 0b0..nominal delay
6858 * 0b1..nominal delay * 2
6859 */
6860#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK)
6861#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
6862#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
6863#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
6864#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
6865#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
6866/*! PBIAS_CTRL
6867 * 0b0..0.50*VDD
6868 * 0b1..0.67*VDD
6869 */
6870#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK)
6871#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
6872#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_SHIFT (19U)
6873#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_MASK)
6874#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
6875#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
6876#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_MASK)
6877#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_MASK (0x200000U)
6878#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_SHIFT (21U)
6879#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_MASK)
6880/*! @} */
6881
6882/*! @name SYS_PLL3_GEN_CTRL - SYS PLL3 General Function Control Register */
6883/*! @{ */
6884#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
6885#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
6886/*! PLL_REF_CLK_SEL
6887 * 0b00..SYS_XTAL
6888 * 0b01..PAD_CLK
6889 * 0b10..Reserved
6890 * 0b11..Reserved
6891 */
6892#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
6893#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
6894#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
6895/*! PAD_CLK_SEL
6896 * 0b00..CLKIN1 XOR CLKIN2
6897 * 0b01..CLKIN2
6898 * 0b10..CLKIN1
6899 * 0b11..Reserved
6900 */
6901#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_MASK)
6902#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
6903#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
6904#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_MASK)
6905#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
6906#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
6907#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
6908#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_MASK (0x200U)
6909#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT (9U)
6910#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_MASK)
6911#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
6912#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
6913#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
6914#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_MASK (0x800U)
6915#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT (11U)
6916#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_MASK)
6917#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
6918#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
6919#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_MASK)
6920#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
6921#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
6922/*! PLL_LOCK_SEL
6923 * 0b0..Using PLL maximum lock time
6924 * 0b1..Using PLL output lock
6925 */
6926#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_MASK)
6927#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
6928#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SHIFT (31U)
6929#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_MASK)
6930/*! @} */
6931
6932/*! @name SYS_PLL3_FDIV_CTL0 - SYS PLL3 Divide and Fraction Data Control 0 Register */
6933/*! @{ */
6934#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
6935#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
6936#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_MASK)
6937#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
6938#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
6939#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_MASK)
6940#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
6941#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
6942#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_MASK)
6943/*! @} */
6944
6945/*! @name SYS_PLL3_LOCKD_CTRL - PLL Lock Detector Control Register */
6946/*! @{ */
6947#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
6948#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
6949#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_MASK)
6950#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
6951#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
6952#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_MASK)
6953#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
6954#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
6955#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_MASK)
6956/*! @} */
6957
6958/*! @name SYS_PLL3_MNIT_CTRL - PLL Monitoring Control Register */
6959/*! @{ */
6960#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_MASK (0x3U)
6961#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_SHIFT (0U)
6962#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_MASK)
6963#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_MASK (0x4U)
6964#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_SHIFT (2U)
6965#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_MASK)
6966#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_MASK (0xF8U)
6967#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_SHIFT (3U)
6968#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_MASK)
6969#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_MASK (0x2000U)
6970#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_SHIFT (13U)
6971#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_MASK)
6972#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_MASK (0x4000U)
6973#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_SHIFT (14U)
6974/*! FSEL
6975 * 0b0..FEED_OUT = FREF
6976 * 0b1..FEED_OUT = FEED
6977 */
6978#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_MASK)
6979#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
6980#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
6981/*! AFCINIT_SEL
6982 * 0b0..nominal delay
6983 * 0b1..nominal delay * 2
6984 */
6985#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_MASK)
6986#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
6987#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
6988#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
6989#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
6990#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
6991/*! PBIAS_CTRL
6992 * 0b0..0.50*VDD
6993 * 0b1..0.67*VDD
6994 */
6995#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_MASK)
6996#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
6997#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_SHIFT (19U)
6998#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_MASK)
6999#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
7000#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
7001#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_MASK)
7002#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_MASK (0x200000U)
7003#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_SHIFT (21U)
7004#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_MASK)
7005/*! @} */
7006
7007/*! @name OSC_MISC_CFG - Osc Misc Configuration Register */
7008/*! @{ */
7009#define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK (0x1U)
7010#define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT (0U)
7011/*! OSC_32K_SEL
7012 * 0b0..Divided by 24M clock
7013 * 0b1..32K Oscillator
7014 */
7015#define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK)
7016/*! @} */
7017
7018/*! @name ANAMIX_PLL_MNIT_CTL - PLL Clock Output for Test Enable and Select Register */
7019/*! @{ */
7020#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_MASK (0xFU)
7021#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_SHIFT (0U)
7022#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_MASK)
7023#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_MASK (0xF0U)
7024#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_SHIFT (4U)
7025#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_MASK)
7026#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_MASK (0x100U)
7027#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_SHIFT (8U)
7028#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_MASK)
7029#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_MASK (0xF0000U)
7030#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_SHIFT (16U)
7031#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_MASK)
7032#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_MASK (0xF00000U)
7033#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_SHIFT (20U)
7034#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_MASK)
7035#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_MASK (0x1000000U)
7036#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_SHIFT (24U)
7037#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_MASK)
7038/*! @} */
7039
7040/*! @name DIGPROG - DIGPROG Register */
7041/*! @{ */
7042#define CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK (0xFFU)
7043#define CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT (0U)
7044#define CCM_ANALOG_DIGPROG_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK)
7045#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK (0xFF00U)
7046#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT (8U)
7047#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK)
7048#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U)
7049#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT (16U)
7050#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK)
7051/*! @} */
7052
7053
7054/*!
7055 * @}
7056 */ /* end of group CCM_ANALOG_Register_Masks */
7057
7058
7059/* CCM_ANALOG - Peripheral instance base addresses */
7060/** Peripheral CCM_ANALOG base address */
7061#define CCM_ANALOG_BASE (0x30360000u)
7062/** Peripheral CCM_ANALOG base pointer */
7063#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
7064/** Array initializer of CCM_ANALOG peripheral base addresses */
7065#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }
7066/** Array initializer of CCM_ANALOG peripheral base pointers */
7067#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG }
7068
7069/*!
7070 * @}
7071 */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */
7072
7073
7074/* ----------------------------------------------------------------------------
7075 -- CSI Peripheral Access Layer
7076 ---------------------------------------------------------------------------- */
7077
7078/*!
7079 * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer
7080 * @{
7081 */
7082
7083/** CSI - Register Layout Typedef */
7084typedef struct {
7085 __IO uint32_t CSICR1; /**< CSI Control Register 1, offset: 0x0 */
7086 __IO uint32_t CSICR2; /**< CSI Control Register 2, offset: 0x4 */
7087 __IO uint32_t CSICR3; /**< CSI Control Register 3, offset: 0x8 */
7088 __I uint32_t CSISTATFIFO; /**< CSI Statistic FIFO Register, offset: 0xC */
7089 __I uint32_t CSIRFIFO; /**< CSI RX FIFO Register, offset: 0x10 */
7090 __IO uint32_t CSIRXCNT; /**< CSI RX Count Register, offset: 0x14 */
7091 __IO uint32_t CSISR; /**< CSI Status Register, offset: 0x18 */
7092 uint8_t RESERVED_0[4];
7093 __IO uint32_t CSIDMASA_STATFIFO; /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */
7094 __IO uint32_t CSIDMATS_STATFIFO; /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */
7095 __IO uint32_t CSIDMASA_FB1; /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */
7096 __IO uint32_t CSIDMASA_FB2; /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */
7097 __IO uint32_t CSIFBUF_PARA; /**< CSI Frame Buffer Parameter Register, offset: 0x30 */
7098 __IO uint32_t CSIIMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */
7099 uint8_t RESERVED_1[16];
7100 __IO uint32_t CSICR18; /**< CSI Control Register 18, offset: 0x48 */
7101} CSI_Type;
7102
7103/* ----------------------------------------------------------------------------
7104 -- CSI Register Masks
7105 ---------------------------------------------------------------------------- */
7106
7107/*!
7108 * @addtogroup CSI_Register_Masks CSI Register Masks
7109 * @{
7110 */
7111
7112/*! @name CSICR1 - CSI Control Register 1 */
7113/*! @{ */
7114#define CSI_CSICR1_PIXEL_BIT_MASK (0x1U)
7115#define CSI_CSICR1_PIXEL_BIT_SHIFT (0U)
7116/*! PIXEL_BIT
7117 * 0b0..8-bit data for each pixel
7118 * 0b1..10-bit data for each pixel
7119 */
7120#define CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK)
7121#define CSI_CSICR1_REDGE_MASK (0x2U)
7122#define CSI_CSICR1_REDGE_SHIFT (1U)
7123/*! REDGE
7124 * 0b0..Pixel data is latched at the falling edge of CSI_PIXCLK
7125 * 0b1..Pixel data is latched at the rising edge of CSI_PIXCLK
7126 */
7127#define CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK)
7128#define CSI_CSICR1_INV_PCLK_MASK (0x4U)
7129#define CSI_CSICR1_INV_PCLK_SHIFT (2U)
7130/*! INV_PCLK
7131 * 0b0..CSI_PIXCLK is directly applied to internal circuitry
7132 * 0b1..CSI_PIXCLK is inverted before applied to internal circuitry
7133 */
7134#define CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK)
7135#define CSI_CSICR1_INV_DATA_MASK (0x8U)
7136#define CSI_CSICR1_INV_DATA_SHIFT (3U)
7137/*! INV_DATA
7138 * 0b0..CSI_D[7:0] data lines are directly applied to internal circuitry
7139 * 0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry
7140 */
7141#define CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK)
7142#define CSI_CSICR1_GCLK_MODE_MASK (0x10U)
7143#define CSI_CSICR1_GCLK_MODE_SHIFT (4U)
7144/*! GCLK_MODE
7145 * 0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored.
7146 * 0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active.
7147 */
7148#define CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK)
7149#define CSI_CSICR1_CLR_RXFIFO_MASK (0x20U)
7150#define CSI_CSICR1_CLR_RXFIFO_SHIFT (5U)
7151#define CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK)
7152#define CSI_CSICR1_CLR_STATFIFO_MASK (0x40U)
7153#define CSI_CSICR1_CLR_STATFIFO_SHIFT (6U)
7154#define CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK)
7155#define CSI_CSICR1_PACK_DIR_MASK (0x80U)
7156#define CSI_CSICR1_PACK_DIR_SHIFT (7U)
7157/*! PACK_DIR
7158 * 0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For
7159 * stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO.
7160 * 0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For
7161 * stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO.
7162 */
7163#define CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK)
7164#define CSI_CSICR1_FCC_MASK (0x100U)
7165#define CSI_CSICR1_FCC_SHIFT (8U)
7166/*! FCC
7167 * 0b0..Asynchronous FIFO clear is selected.
7168 * 0b1..Synchronous FIFO clear is selected.
7169 */
7170#define CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK)
7171#define CSI_CSICR1_CCIR_EN_MASK (0x400U)
7172#define CSI_CSICR1_CCIR_EN_SHIFT (10U)
7173/*! CCIR_EN
7174 * 0b0..Traditional interface is selected. Timing interface logic is used to latch data.
7175 * 0b1..CCIR656 interface is selected.
7176 */
7177#define CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK)
7178#define CSI_CSICR1_HSYNC_POL_MASK (0x800U)
7179#define CSI_CSICR1_HSYNC_POL_SHIFT (11U)
7180/*! HSYNC_POL
7181 * 0b0..HSYNC is active low
7182 * 0b1..HSYNC is active high
7183 */
7184#define CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK)
7185#define CSI_CSICR1_SOF_INTEN_MASK (0x10000U)
7186#define CSI_CSICR1_SOF_INTEN_SHIFT (16U)
7187/*! SOF_INTEN
7188 * 0b0..SOF interrupt disable
7189 * 0b1..SOF interrupt enable
7190 */
7191#define CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK)
7192#define CSI_CSICR1_SOF_POL_MASK (0x20000U)
7193#define CSI_CSICR1_SOF_POL_SHIFT (17U)
7194/*! SOF_POL
7195 * 0b0..SOF interrupt is generated on SOF falling edge
7196 * 0b1..SOF interrupt is generated on SOF rising edge
7197 */
7198#define CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK)
7199#define CSI_CSICR1_RXFF_INTEN_MASK (0x40000U)
7200#define CSI_CSICR1_RXFF_INTEN_SHIFT (18U)
7201/*! RXFF_INTEN
7202 * 0b0..RxFIFO full interrupt disable
7203 * 0b1..RxFIFO full interrupt enable
7204 */
7205#define CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK)
7206#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U)
7207#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U)
7208/*! FB1_DMA_DONE_INTEN
7209 * 0b0..Frame Buffer1 DMA Transfer Done interrupt disable
7210 * 0b1..Frame Buffer1 DMA Transfer Done interrupt enable
7211 */
7212#define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK)
7213#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U)
7214#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U)
7215/*! FB2_DMA_DONE_INTEN
7216 * 0b0..Frame Buffer2 DMA Transfer Done interrupt disable
7217 * 0b1..Frame Buffer2 DMA Transfer Done interrupt enable
7218 */
7219#define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK)
7220#define CSI_CSICR1_STATFF_INTEN_MASK (0x200000U)
7221#define CSI_CSICR1_STATFF_INTEN_SHIFT (21U)
7222/*! STATFF_INTEN
7223 * 0b0..STATFIFO full interrupt disable
7224 * 0b1..STATFIFO full interrupt enable
7225 */
7226#define CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK)
7227#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U)
7228#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U)
7229/*! SFF_DMA_DONE_INTEN
7230 * 0b0..STATFIFO DMA Transfer Done interrupt disable
7231 * 0b1..STATFIFO DMA Transfer Done interrupt enable
7232 */
7233#define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK)
7234#define CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U)
7235#define CSI_CSICR1_RF_OR_INTEN_SHIFT (24U)
7236/*! RF_OR_INTEN
7237 * 0b0..RxFIFO overrun interrupt is disabled
7238 * 0b1..RxFIFO overrun interrupt is enabled
7239 */
7240#define CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK)
7241#define CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U)
7242#define CSI_CSICR1_SF_OR_INTEN_SHIFT (25U)
7243/*! SF_OR_INTEN
7244 * 0b0..STATFIFO overrun interrupt is disabled
7245 * 0b1..STATFIFO overrun interrupt is enabled
7246 */
7247#define CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK)
7248#define CSI_CSICR1_COF_INT_EN_MASK (0x4000000U)
7249#define CSI_CSICR1_COF_INT_EN_SHIFT (26U)
7250/*! COF_INT_EN
7251 * 0b0..COF interrupt is disabled
7252 * 0b1..COF interrupt is enabled
7253 */
7254#define CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK)
7255#define CSI_CSICR1_VIDEO_MODE_MASK (0x8000000U)
7256#define CSI_CSICR1_VIDEO_MODE_SHIFT (27U)
7257/*! VIDEO_MODE
7258 * 0b0..Progressive mode is selected
7259 * 0b1..Interlace mode is selected
7260 */
7261#define CSI_CSICR1_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_VIDEO_MODE_SHIFT)) & CSI_CSICR1_VIDEO_MODE_MASK)
7262#define CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U)
7263#define CSI_CSICR1_PrP_IF_EN_SHIFT (28U)
7264/*! PrP_IF_EN
7265 * 0b0..CSI to PrP bus is disabled
7266 * 0b1..CSI to PrP bus is enabled
7267 */
7268#define CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK)
7269#define CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U)
7270#define CSI_CSICR1_EOF_INT_EN_SHIFT (29U)
7271/*! EOF_INT_EN
7272 * 0b0..EOF interrupt is disabled.
7273 * 0b1..EOF interrupt is generated when RX count value is reached.
7274 */
7275#define CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK)
7276#define CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U)
7277#define CSI_CSICR1_EXT_VSYNC_SHIFT (30U)
7278/*! EXT_VSYNC
7279 * 0b0..Internal VSYNC mode
7280 * 0b1..External VSYNC mode
7281 */
7282#define CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK)
7283#define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U)
7284#define CSI_CSICR1_SWAP16_EN_SHIFT (31U)
7285/*! SWAP16_EN
7286 * 0b0..Disable swapping
7287 * 0b1..Enable swapping
7288 */
7289#define CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK)
7290/*! @} */
7291
7292/*! @name CSICR2 - CSI Control Register 2 */
7293/*! @{ */
7294#define CSI_CSICR2_HSC_MASK (0xFFU)
7295#define CSI_CSICR2_HSC_SHIFT (0U)
7296#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK)
7297#define CSI_CSICR2_VSC_MASK (0xFF00U)
7298#define CSI_CSICR2_VSC_SHIFT (8U)
7299#define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK)
7300#define CSI_CSICR2_LVRM_MASK (0x70000U)
7301#define CSI_CSICR2_LVRM_SHIFT (16U)
7302/*! LVRM
7303 * 0b000..512 x 384
7304 * 0b001..448 x 336
7305 * 0b010..384 x 288
7306 * 0b011..384 x 256
7307 * 0b100..320 x 240
7308 * 0b101..288 x 216
7309 * 0b110..400 x 300
7310 */
7311#define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK)
7312#define CSI_CSICR2_BTS_MASK (0x180000U)
7313#define CSI_CSICR2_BTS_SHIFT (19U)
7314/*! BTS
7315 * 0b00..GR
7316 * 0b01..RG
7317 * 0b10..BG
7318 * 0b11..GB
7319 */
7320#define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK)
7321#define CSI_CSICR2_SCE_MASK (0x800000U)
7322#define CSI_CSICR2_SCE_SHIFT (23U)
7323/*! SCE
7324 * 0b0..Skip count disable
7325 * 0b1..Skip count enable
7326 */
7327#define CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK)
7328#define CSI_CSICR2_AFS_MASK (0x3000000U)
7329#define CSI_CSICR2_AFS_SHIFT (24U)
7330/*! AFS
7331 * 0b00..Abs Diff on consecutive green pixels
7332 * 0b01..Abs Diff on every third green pixels
7333 * 0b1x..Abs Diff on every four green pixels
7334 */
7335#define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK)
7336#define CSI_CSICR2_DRM_MASK (0x4000000U)
7337#define CSI_CSICR2_DRM_SHIFT (26U)
7338/*! DRM
7339 * 0b0..Stats grid of 8 x 6
7340 * 0b1..Stats grid of 8 x 12
7341 */
7342#define CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK)
7343#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U)
7344#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U)
7345/*! DMA_BURST_TYPE_SFF
7346 * 0bx0..INCR8
7347 * 0b01..INCR4
7348 * 0b11..INCR16
7349 */
7350#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK)
7351#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U)
7352#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U)
7353/*! DMA_BURST_TYPE_RFF
7354 * 0bx0..INCR8
7355 * 0b01..INCR4
7356 * 0b11..INCR16
7357 */
7358#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK)
7359/*! @} */
7360
7361/*! @name CSICR3 - CSI Control Register 3 */
7362/*! @{ */
7363#define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U)
7364#define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U)
7365/*! ECC_AUTO_EN
7366 * 0b0..Auto Error correction is disabled.
7367 * 0b1..Auto Error correction is enabled.
7368 */
7369#define CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK)
7370#define CSI_CSICR3_ECC_INT_EN_MASK (0x2U)
7371#define CSI_CSICR3_ECC_INT_EN_SHIFT (1U)
7372/*! ECC_INT_EN
7373 * 0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set.
7374 * 0b1..Interrupt is generated when error is detected.
7375 */
7376#define CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK)
7377#define CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U)
7378#define CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U)
7379/*! ZERO_PACK_EN
7380 * 0b0..Zero packing disabled
7381 * 0b1..Zero packing enabled
7382 */
7383#define CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK)
7384#define CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U)
7385#define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U)
7386/*! TWO_8BIT_SENSOR
7387 * 0b0..Only one 8-bit sensor is connected.
7388 * 0b1..One 16-bit sensor is connected.
7389 */
7390#define CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK)
7391#define CSI_CSICR3_RxFF_LEVEL_MASK (0x70U)
7392#define CSI_CSICR3_RxFF_LEVEL_SHIFT (4U)
7393/*! RxFF_LEVEL
7394 * 0b000..4 Double words
7395 * 0b001..8 Double words
7396 * 0b010..16 Double words
7397 * 0b011..24 Double words
7398 * 0b100..32 Double words
7399 * 0b101..48 Double words
7400 * 0b110..64 Double words
7401 * 0b111..96 Double words
7402 */
7403#define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK)
7404#define CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U)
7405#define CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U)
7406/*! HRESP_ERR_EN
7407 * 0b0..Disable hresponse error interrupt
7408 * 0b1..Enable hresponse error interrupt
7409 */
7410#define CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK)
7411#define CSI_CSICR3_STATFF_LEVEL_MASK (0x700U)
7412#define CSI_CSICR3_STATFF_LEVEL_SHIFT (8U)
7413/*! STATFF_LEVEL
7414 * 0b000..4 Double words
7415 * 0b001..8 Double words
7416 * 0b010..12 Double words
7417 * 0b011..16 Double words
7418 * 0b100..24 Double words
7419 * 0b101..32 Double words
7420 * 0b110..48 Double words
7421 * 0b111..64 Double words
7422 */
7423#define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK)
7424#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U)
7425#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U)
7426/*! DMA_REQ_EN_SFF
7427 * 0b0..Disable the dma request
7428 * 0b1..Enable the dma request
7429 */
7430#define CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK)
7431#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U)
7432#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U)
7433/*! DMA_REQ_EN_RFF
7434 * 0b0..Disable the dma request
7435 * 0b1..Enable the dma request
7436 */
7437#define CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK)
7438#define CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U)
7439#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U)
7440/*! DMA_REFLASH_SFF
7441 * 0b0..No reflashing
7442 * 0b1..Reflash the embedded DMA controller
7443 */
7444#define CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK)
7445#define CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U)
7446#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U)
7447/*! DMA_REFLASH_RFF
7448 * 0b0..No reflashing
7449 * 0b1..Reflash the embedded DMA controller
7450 */
7451#define CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK)
7452#define CSI_CSICR3_FRMCNT_RST_MASK (0x8000U)
7453#define CSI_CSICR3_FRMCNT_RST_SHIFT (15U)
7454/*! FRMCNT_RST
7455 * 0b0..Do not reset
7456 * 0b1..Reset frame counter immediately
7457 */
7458#define CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK)
7459#define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U)
7460#define CSI_CSICR3_FRMCNT_SHIFT (16U)
7461#define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK)
7462/*! @} */
7463
7464/*! @name CSISTATFIFO - CSI Statistic FIFO Register */
7465/*! @{ */
7466#define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU)
7467#define CSI_CSISTATFIFO_STAT_SHIFT (0U)
7468#define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK)
7469/*! @} */
7470
7471/*! @name CSIRFIFO - CSI RX FIFO Register */
7472/*! @{ */
7473#define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU)
7474#define CSI_CSIRFIFO_IMAGE_SHIFT (0U)
7475#define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK)
7476/*! @} */
7477
7478/*! @name CSIRXCNT - CSI RX Count Register */
7479/*! @{ */
7480#define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU)
7481#define CSI_CSIRXCNT_RXCNT_SHIFT (0U)
7482#define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK)
7483/*! @} */
7484
7485/*! @name CSISR - CSI Status Register */
7486/*! @{ */
7487#define CSI_CSISR_DRDY_MASK (0x1U)
7488#define CSI_CSISR_DRDY_SHIFT (0U)
7489/*! DRDY
7490 * 0b0..No data (word) is ready
7491 * 0b1..At least 1 datum (word) is ready in RXFIFO.
7492 */
7493#define CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK)
7494#define CSI_CSISR_ECC_INT_MASK (0x2U)
7495#define CSI_CSISR_ECC_INT_SHIFT (1U)
7496/*! ECC_INT
7497 * 0b0..No error detected
7498 * 0b1..Error is detected in CCIR coding
7499 */
7500#define CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK)
7501#define CSI_CSISR_HRESP_ERR_INT_MASK (0x80U)
7502#define CSI_CSISR_HRESP_ERR_INT_SHIFT (7U)
7503/*! HRESP_ERR_INT
7504 * 0b0..No hresponse error.
7505 * 0b1..Hresponse error is detected.
7506 */
7507#define CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK)
7508#define CSI_CSISR_COF_INT_MASK (0x2000U)
7509#define CSI_CSISR_COF_INT_SHIFT (13U)
7510/*! COF_INT
7511 * 0b0..Video field has no change.
7512 * 0b1..Change of video field is detected.
7513 */
7514#define CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK)
7515#define CSI_CSISR_F1_INT_MASK (0x4000U)
7516#define CSI_CSISR_F1_INT_SHIFT (14U)
7517/*! F1_INT
7518 * 0b0..Field 1 of video is not detected.
7519 * 0b1..Field 1 of video is about to start.
7520 */
7521#define CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK)
7522#define CSI_CSISR_F2_INT_MASK (0x8000U)
7523#define CSI_CSISR_F2_INT_SHIFT (15U)
7524/*! F2_INT
7525 * 0b0..Field 2 of video is not detected
7526 * 0b1..Field 2 of video is about to start
7527 */
7528#define CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK)
7529#define CSI_CSISR_SOF_INT_MASK (0x10000U)
7530#define CSI_CSISR_SOF_INT_SHIFT (16U)
7531/*! SOF_INT
7532 * 0b0..SOF is not detected.
7533 * 0b1..SOF is detected.
7534 */
7535#define CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK)
7536#define CSI_CSISR_EOF_INT_MASK (0x20000U)
7537#define CSI_CSISR_EOF_INT_SHIFT (17U)
7538/*! EOF_INT
7539 * 0b0..EOF is not detected.
7540 * 0b1..EOF is detected.
7541 */
7542#define CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK)
7543#define CSI_CSISR_RxFF_INT_MASK (0x40000U)
7544#define CSI_CSISR_RxFF_INT_SHIFT (18U)
7545/*! RxFF_INT
7546 * 0b0..RxFIFO is not full.
7547 * 0b1..RxFIFO is full.
7548 */
7549#define CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK)
7550#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U)
7551#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U)
7552/*! DMA_TSF_DONE_FB1
7553 * 0b0..DMA transfer is not completed.
7554 * 0b1..DMA transfer is completed.
7555 */
7556#define CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK)
7557#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U)
7558#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U)
7559/*! DMA_TSF_DONE_FB2
7560 * 0b0..DMA transfer is not completed.
7561 * 0b1..DMA transfer is completed.
7562 */
7563#define CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK)
7564#define CSI_CSISR_STATFF_INT_MASK (0x200000U)
7565#define CSI_CSISR_STATFF_INT_SHIFT (21U)
7566/*! STATFF_INT
7567 * 0b0..STATFIFO is not full.
7568 * 0b1..STATFIFO is full.
7569 */
7570#define CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK)
7571#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U)
7572#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U)
7573/*! DMA_TSF_DONE_SFF
7574 * 0b0..DMA transfer is not completed.
7575 * 0b1..DMA transfer is completed.
7576 */
7577#define CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK)
7578#define CSI_CSISR_RF_OR_INT_MASK (0x1000000U)
7579#define CSI_CSISR_RF_OR_INT_SHIFT (24U)
7580/*! RF_OR_INT
7581 * 0b0..RXFIFO has not overflowed.
7582 * 0b1..RXFIFO has overflowed.
7583 */
7584#define CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK)
7585#define CSI_CSISR_SF_OR_INT_MASK (0x2000000U)
7586#define CSI_CSISR_SF_OR_INT_SHIFT (25U)
7587/*! SF_OR_INT
7588 * 0b0..STATFIFO has not overflowed.
7589 * 0b1..STATFIFO has overflowed.
7590 */
7591#define CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK)
7592#define CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U)
7593#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U)
7594#define CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK)
7595#define CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U)
7596#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U)
7597#define CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK)
7598#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U)
7599#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U)
7600#define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK)
7601/*! @} */
7602
7603/*! @name CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */
7604/*! @{ */
7605#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)
7606#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)
7607#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)
7608/*! @} */
7609
7610/*! @name CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */
7611/*! @{ */
7612#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)
7613#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)
7614#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)
7615/*! @} */
7616
7617/*! @name CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */
7618/*! @{ */
7619#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU)
7620#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U)
7621#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK)
7622/*! @} */
7623
7624/*! @name CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */
7625/*! @{ */
7626#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU)
7627#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U)
7628#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK)
7629/*! @} */
7630
7631/*! @name CSIFBUF_PARA - CSI Frame Buffer Parameter Register */
7632/*! @{ */
7633#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU)
7634#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U)
7635#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK)
7636#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U)
7637#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U)
7638#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK)
7639/*! @} */
7640
7641/*! @name CSIIMAG_PARA - CSI Image Parameter Register */
7642/*! @{ */
7643#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU)
7644#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U)
7645#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK)
7646#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U)
7647#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U)
7648#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK)
7649/*! @} */
7650
7651/*! @name CSICR18 - CSI Control Register 18 */
7652/*! @{ */
7653#define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U)
7654#define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U)
7655/*! DEINTERLACE_EN
7656 * 0b0..Deinterlace disabled
7657 * 0b1..Deinterlace enabled
7658 */
7659#define CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK)
7660#define CSI_CSICR18_PARALLEL24_EN_MASK (0x8U)
7661#define CSI_CSICR18_PARALLEL24_EN_SHIFT (3U)
7662#define CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK)
7663#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U)
7664#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U)
7665#define CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK)
7666#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U)
7667#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U)
7668/*! BASEADDR_SWITCH_SEL
7669 * 0b0..Switching base address at the edge of the vsync
7670 * 0b1..Switching base address at the edge of the first data of each frame
7671 */
7672#define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK)
7673#define CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U)
7674#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U)
7675/*! FIELD0_DONE_IE
7676 * 0b0..Interrupt disabled
7677 * 0b1..Interrupt enabled
7678 */
7679#define CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK)
7680#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U)
7681#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U)
7682/*! DMA_FIELD1_DONE_IE
7683 * 0b0..Interrupt disabled
7684 * 0b1..Interrupt enabled
7685 */
7686#define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK)
7687#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U)
7688#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U)
7689/*! LAST_DMA_REQ_SEL
7690 * 0b0..fifo_full_level
7691 * 0b1..hburst_length
7692 */
7693#define CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK)
7694#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U)
7695#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U)
7696#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK)
7697#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U)
7698#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U)
7699/*! RGB888A_FORMAT_SEL
7700 * 0b0..{8'h0, data[23:0]}
7701 * 0b1..{data[23:0], 8'h0}
7702 */
7703#define CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK)
7704#define CSI_CSICR18_AHB_HPROT_MASK (0xF000U)
7705#define CSI_CSICR18_AHB_HPROT_SHIFT (12U)
7706#define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK)
7707#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK (0x30000U)
7708#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT (16U)
7709/*! CSI_LCDIF_BUFFER_LINES
7710 * 0b00..4 lines
7711 * 0b01..8 lines
7712 * 0b10..16 lines
7713 * 0b11..16 lines
7714 */
7715#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT)) & CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK)
7716#define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U)
7717#define CSI_CSICR18_MASK_OPTION_SHIFT (18U)
7718/*! MASK_OPTION
7719 * 0b00..Writing to memory from first completely frame, when using this option, the CSI_ENABLE should be 1.
7720 * 0b01..Writing to memory when CSI_ENABLE is 1.
7721 * 0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1.
7722 * 0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0.
7723 */
7724#define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK)
7725#define CSI_CSICR18_MIPI_DOUBLE_CMPNT_MASK (0x100000U)
7726#define CSI_CSICR18_MIPI_DOUBLE_CMPNT_SHIFT (20U)
7727/*! MIPI_DOUBLE_CMPNT
7728 * 0b0..Single component per clock cycle (half pixel per clock cycle)
7729 * 0b1..Double component per clock cycle (a pixel per clock cycle)
7730 */
7731#define CSI_CSICR18_MIPI_DOUBLE_CMPNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MIPI_DOUBLE_CMPNT_SHIFT)) & CSI_CSICR18_MIPI_DOUBLE_CMPNT_MASK)
7732#define CSI_CSICR18_MIPI_YU_SWAP_MASK (0x200000U)
7733#define CSI_CSICR18_MIPI_YU_SWAP_SHIFT (21U)
7734#define CSI_CSICR18_MIPI_YU_SWAP(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MIPI_YU_SWAP_SHIFT)) & CSI_CSICR18_MIPI_YU_SWAP_MASK)
7735#define CSI_CSICR18_DATA_FROM_MIPI_MASK (0x400000U)
7736#define CSI_CSICR18_DATA_FROM_MIPI_SHIFT (22U)
7737/*! DATA_FROM_MIPI
7738 * 0b0..Data from parallel sensor
7739 * 0b1..Data from MIPI
7740 */
7741#define CSI_CSICR18_DATA_FROM_MIPI(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DATA_FROM_MIPI_SHIFT)) & CSI_CSICR18_DATA_FROM_MIPI_MASK)
7742#define CSI_CSICR18_LINE_STRIDE_EN_MASK (0x1000000U)
7743#define CSI_CSICR18_LINE_STRIDE_EN_SHIFT (24U)
7744#define CSI_CSICR18_LINE_STRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LINE_STRIDE_EN_SHIFT)) & CSI_CSICR18_LINE_STRIDE_EN_MASK)
7745#define CSI_CSICR18_MIPI_DATA_FORMAT_MASK (0x7E000000U)
7746#define CSI_CSICR18_MIPI_DATA_FORMAT_SHIFT (25U)
7747#define CSI_CSICR18_MIPI_DATA_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MIPI_DATA_FORMAT_SHIFT)) & CSI_CSICR18_MIPI_DATA_FORMAT_MASK)
7748#define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U)
7749#define CSI_CSICR18_CSI_ENABLE_SHIFT (31U)
7750#define CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK)
7751/*! @} */
7752
7753
7754/*!
7755 * @}
7756 */ /* end of group CSI_Register_Masks */
7757
7758
7759/* CSI - Peripheral instance base addresses */
7760/** Peripheral CSI base address */
7761#define CSI_BASE (0x32E20000u)
7762/** Peripheral CSI base pointer */
7763#define CSI ((CSI_Type *)CSI_BASE)
7764/** Array initializer of CSI peripheral base addresses */
7765#define CSI_BASE_ADDRS { CSI_BASE }
7766/** Array initializer of CSI peripheral base pointers */
7767#define CSI_BASE_PTRS { CSI }
7768
7769/*!
7770 * @}
7771 */ /* end of group CSI_Peripheral_Access_Layer */
7772
7773
7774/* ----------------------------------------------------------------------------
7775 -- DDRC Peripheral Access Layer
7776 ---------------------------------------------------------------------------- */
7777
7778/*!
7779 * @addtogroup DDRC_Peripheral_Access_Layer DDRC Peripheral Access Layer
7780 * @{
7781 */
7782
7783/** DDRC - Register Layout Typedef */
7784typedef struct {
7785 __IO uint32_t MSTR; /**< Master Register0, offset: 0x0 */
7786 __I uint32_t STAT; /**< Operating Mode Status Register, offset: 0x4 */
7787 __IO uint32_t MSTR1; /**< Operating Mode Status Register, offset: 0x8 */
7788 __IO uint32_t MRCTRL3; /**< Operating Mode Status Register, offset: 0xC */
7789 __IO uint32_t MRCTRL0; /**< Mode Register Read/Write Control Register 0., offset: 0x10 */
7790 __IO uint32_t MRCTRL1; /**< Mode Register Read/Write Control Register 1, offset: 0x14 */
7791 __I uint32_t MRSTAT; /**< Mode Register Read/Write Status Register, offset: 0x18 */
7792 __IO uint32_t MRCTRL2; /**< Mode Register Read/Write Control Register 2, offset: 0x1C */
7793 __IO uint32_t DERATEEN; /**< Temperature Derate Enable Register, offset: 0x20 */
7794 __IO uint32_t DERATEINT; /**< Temperature Derate Interval Register, offset: 0x24 */
7795 uint8_t RESERVED_0[8];
7796 __IO uint32_t PWRCTL; /**< Low Power Control Register, offset: 0x30 */
7797 __IO uint32_t PWRTMG; /**< Low Power Timing Register, offset: 0x34 */
7798 __IO uint32_t HWLPCTL; /**< Hardware Low Power Control Register, offset: 0x38 */
7799 uint8_t RESERVED_1[20];
7800 __IO uint32_t RFSHCTL0; /**< Refresh Control Register 0, offset: 0x50 */
7801 __IO uint32_t RFSHCTL1; /**< Refresh Control Register 1, offset: 0x54 */
7802 uint8_t RESERVED_2[8];
7803 __IO uint32_t RFSHCTL3; /**< Refresh Control Register 3, offset: 0x60 */
7804 __IO uint32_t RFSHTMG; /**< Refresh Timing Register, offset: 0x64 */
7805 uint8_t RESERVED_3[104];
7806 __IO uint32_t INIT0; /**< SDRAM Initialization Register 0, offset: 0xD0 */
7807 __IO uint32_t INIT1; /**< SDRAM Initialization Register 1, offset: 0xD4 */
7808 __IO uint32_t INIT2; /**< SDRAM Initialization Register 2, offset: 0xD8 */
7809 __IO uint32_t INIT3; /**< SDRAM Initialization Register 3, offset: 0xDC */
7810 __IO uint32_t INIT4; /**< SDRAM Initialization Register 4, offset: 0xE0 */
7811 __IO uint32_t INIT5; /**< SDRAM Initialization Register 5, offset: 0xE4 */
7812 __IO uint32_t INIT6; /**< SDRAM Initialization Register 6, offset: 0xE8 */
7813 __IO uint32_t INIT7; /**< SDRAM Initialization Register 7, offset: 0xEC */
7814 __IO uint32_t DIMMCTL; /**< DIMM Control Register, offset: 0xF0 */
7815 __IO uint32_t RANKCTL; /**< Rank Control Register, offset: 0xF4 */
7816 uint8_t RESERVED_4[8];
7817 __IO uint32_t DRAMTMG0; /**< SDRAM Timing Register 0, offset: 0x100 */
7818 __IO uint32_t DRAMTMG1; /**< SDRAM Timing Register 1, offset: 0x104 */
7819 __IO uint32_t DRAMTMG2; /**< SDRAM Timing Register 2, offset: 0x108 */
7820 __IO uint32_t DRAMTMG3; /**< SDRAM Timing Register 3, offset: 0x10C */
7821 __IO uint32_t DRAMTMG4; /**< SDRAM Timing Register 4, offset: 0x110 */
7822 __IO uint32_t DRAMTMG5; /**< SDRAM Timing Register 5, offset: 0x114 */
7823 __IO uint32_t DRAMTMG6; /**< SDRAM Timing Register 6, offset: 0x118 */
7824 __IO uint32_t DRAMTMG7; /**< SDRAM Timing Register 7, offset: 0x11C */
7825 __IO uint32_t DRAMTMG8; /**< SDRAM Timing Register 8, offset: 0x120 */
7826 __IO uint32_t DRAMTMG9; /**< SDRAM Timing Register 9, offset: 0x124 */
7827 __IO uint32_t DRAMTMG10; /**< SDRAM Timing Register 10, offset: 0x128 */
7828 __IO uint32_t DRAMTMG11; /**< SDRAM Timing Register 11, offset: 0x12C */
7829 __IO uint32_t DRAMTMG12; /**< SDRAM Timing Register 12, offset: 0x130 */
7830 __IO uint32_t DRAMTMG13; /**< SDRAM Timing Register 13, offset: 0x134 */
7831 __IO uint32_t DRAMTMG14; /**< SDRAM Timing Register 14, offset: 0x138 */
7832 __IO uint32_t DRAMTMG15; /**< SDRAM Timing Register 15, offset: 0x13C */
7833 uint8_t RESERVED_5[64];
7834 __IO uint32_t ZQCTL0; /**< ZQ Control Register 0, offset: 0x180 */
7835 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */
7836 __IO uint32_t ZQCTL2; /**< ZQ Control Register 2, offset: 0x188 */
7837 __I uint32_t ZQSTAT; /**< ZQ Status Register, offset: 0x18C */
7838 __IO uint32_t DFITMG0; /**< DFI Timing Register 0, offset: 0x190 */
7839 __IO uint32_t DFITMG1; /**< DFI Timing Register 1, offset: 0x194 */
7840 __IO uint32_t DFILPCFG0; /**< DFI Low Power Configuration Register 0, offset: 0x198 */
7841 __IO uint32_t DFILPCFG1; /**< DFI Low Power Configuration Register 1, offset: 0x19C */
7842 __IO uint32_t DFIUPD0; /**< DFI Update Register 0, offset: 0x1A0 */
7843 __IO uint32_t DFIUPD1; /**< DFI Update Register 1, offset: 0x1A4 */
7844 __IO uint32_t DFIUPD2; /**< DFI Update Register 2, offset: 0x1A8 */
7845 uint8_t RESERVED_6[4];
7846 __IO uint32_t DFIMISC; /**< DFI Miscellaneous Control Register, offset: 0x1B0 */
7847 __IO uint32_t DFITMG2; /**< DFI Timing Register 2, offset: 0x1B4 */
7848 __IO uint32_t DFITMG3; /**< DFI Timing Register 3, offset: 0x1B8 */
7849 __I uint32_t DFISTAT; /**< DFI Status Register, offset: 0x1BC */
7850 __IO uint32_t DBICTL; /**< DM/DBI Control Register, offset: 0x1C0 */
7851 uint8_t RESERVED_7[60];
7852 __IO uint32_t ADDRMAP0; /**< Address Map Register 0, offset: 0x200 */
7853 __IO uint32_t ADDRMAP1; /**< Address Map Register 1, offset: 0x204 */
7854 __IO uint32_t ADDRMAP2; /**< Address Map Register 2, offset: 0x208 */
7855 __IO uint32_t ADDRMAP3; /**< Address Map Register 3, offset: 0x20C */
7856 __IO uint32_t ADDRMAP4; /**< Address Map Register 4, offset: 0x210 */
7857 __IO uint32_t ADDRMAP5; /**< Address Map Register 5, offset: 0x214 */
7858 __IO uint32_t ADDRMAP6; /**< Address Map Register 6, offset: 0x218 */
7859 __IO uint32_t ADDRMAP7; /**< Address Map Register 7, offset: 0x21C */
7860 __IO uint32_t ADDRMAP8; /**< Address Map Register 8, offset: 0x220 */
7861 __IO uint32_t ADDRMAP9; /**< Address Map Register 9, offset: 0x224 */
7862 __IO uint32_t ADDRMAP10; /**< Address Map Register 10, offset: 0x228 */
7863 __IO uint32_t ADDRMAP11; /**< Address Map Register 11, offset: 0x22C */
7864 uint8_t RESERVED_8[16];
7865 __IO uint32_t ODTCFG; /**< ODT Configuration Register, offset: 0x240 */
7866 __IO uint32_t ODTMAP; /**< ODT/Rank Map Register, offset: 0x244 */
7867 uint8_t RESERVED_9[8];
7868 __IO uint32_t SCHED; /**< Scheduler Control Register, offset: 0x250 */
7869 __IO uint32_t SCHED1; /**< Scheduler Control Register 1, offset: 0x254 */
7870 uint8_t RESERVED_10[4];
7871 __IO uint32_t PERFHPR1; /**< High Priority Read CAM Register 1, offset: 0x25C */
7872 uint8_t RESERVED_11[4];
7873 __IO uint32_t PERFLPR1; /**< Low Priority Read CAM Register 1, offset: 0x264 */
7874 uint8_t RESERVED_12[4];
7875 __IO uint32_t PERFWR1; /**< Write CAM Register 1, offset: 0x26C */
7876 uint8_t RESERVED_13[144];
7877 __IO uint32_t DBG0; /**< Debug Register 0, offset: 0x300 */
7878 __IO uint32_t DBG1; /**< Debug Register 1, offset: 0x304 */
7879 __I uint32_t DBGCAM; /**< CAM Debug Register, offset: 0x308 */
7880 __IO uint32_t DBGCMD; /**< Command Debug Register, offset: 0x30C */
7881 __I uint32_t DBGSTAT; /**< Status Debug Register, offset: 0x310 */
7882 uint8_t RESERVED_14[12];
7883 __IO uint32_t SWCTL; /**< Software Register Programming Control Enable, offset: 0x320 */
7884 __I uint32_t SWSTAT; /**< Software Register Programming Control Status, offset: 0x324 */
7885 uint8_t RESERVED_15[68];
7886 __IO uint32_t POISONCFG; /**< AXI Poison Configuration Register., offset: 0x36C */
7887 __I uint32_t POISONSTAT; /**< AXI Poison Status Register, offset: 0x370 */
7888 uint8_t RESERVED_16[136];
7889 __I uint32_t PSTAT; /**< Port Status Register, offset: 0x3FC */
7890 __IO uint32_t PCCFG; /**< Port Common Configuration Register, offset: 0x400 */
7891 __IO uint32_t PCFGR_0; /**< Port n Configuration Read Register, offset: 0x404 */
7892 __IO uint32_t PCFGW_0; /**< Port n Configuration Write Register, offset: 0x408 */
7893 uint8_t RESERVED_17[132];
7894 __IO uint32_t PCTRL_0; /**< Port n Control Register, offset: 0x490 */
7895 __IO uint32_t PCFGQOS0_0; /**< Port n Read QoS Configuration Register 0, offset: 0x494 */
7896 __IO uint32_t PCFGQOS1_0; /**< Port n Read QoS Configuration Register 1, offset: 0x498 */
7897 __IO uint32_t PCFGWQOS0_0; /**< Port n Write QoS Configuration Register 0, offset: 0x49C */
7898 __IO uint32_t PCFGWQOS1_0; /**< Port n Write QoS Configuration Register 1, offset: 0x4A0 */
7899 uint8_t RESERVED_18[7036];
7900 __IO uint32_t DERATEEN_SHADOW; /**< [SHADOW] Temperature Derate Enable Register, offset: 0x2020 */
7901 __IO uint32_t DERATEINT_SHADOW; /**< [SHADOW] Temperature Derate Interval Register, offset: 0x2024 */
7902 uint8_t RESERVED_19[40];
7903 __IO uint32_t RFSHCTL0_SHADOW; /**< [SHADOW] Refresh Control Register 0, offset: 0x2050 */
7904 uint8_t RESERVED_20[16];
7905 __IO uint32_t RFSHTMG_SHADOW; /**< [SHADOW] Refresh Timing Register, offset: 0x2064 */
7906 uint8_t RESERVED_21[116];
7907 __IO uint32_t INIT3_SHADOW; /**< [SHADOW] SDRAM Initialization Register 3, offset: 0x20DC */
7908 __IO uint32_t INIT4_SHADOW; /**< [SHADOW] SDRAM Initialization Register 4, offset: 0x20E0 */
7909 uint8_t RESERVED_22[4];
7910 __IO uint32_t INIT6_SHADOW; /**< [SHADOW] SDRAM Initialization Register 6, offset: 0x20E8 */
7911 __IO uint32_t INIT7_SHADOW; /**< [SHADOW] SDRAM Initialization Register 7, offset: 0x20EC */
7912 uint8_t RESERVED_23[16];
7913 __IO uint32_t DRAMTMG0_SHADOW; /**< [SHADOW] SDRAM Timing Register 0, offset: 0x2100 */
7914 __IO uint32_t DRAMTMG1_SHADOW; /**< [SHADOW] SDRAM Timing Register 1, offset: 0x2104 */
7915 __IO uint32_t DRAMTMG2_SHADOW; /**< [SHADOW] SDRAM Timing Register 2, offset: 0x2108 */
7916 __IO uint32_t DRAMTMG3_SHADOW; /**< [SHADOW] SDRAM Timing Register 3, offset: 0x210C */
7917 __IO uint32_t DRAMTMG4_SHADOW; /**< [SHADOW] SDRAM Timing Register 4, offset: 0x2110 */
7918 __IO uint32_t DRAMTMG5_SHADOW; /**< [SHADOW] SDRAM Timing Register 5, offset: 0x2114 */
7919 __IO uint32_t DRAMTMG6_SHADOW; /**< [SHADOW] SDRAM Timing Register 6, offset: 0x2118 */
7920 __IO uint32_t DRAMTMG7_SHADOW; /**< [SHADOW] SDRAM Timing Register 7, offset: 0x211C */
7921 __IO uint32_t DRAMTMG8_SHADOW; /**< [SHADOW] SDRAM Timing Register 8, offset: 0x2120 */
7922 __IO uint32_t DRAMTMG9_SHADOW; /**< [SHADOW] SDRAM Timing Register 9, offset: 0x2124 */
7923 __IO uint32_t DRAMTMG10_SHADOW; /**< [SHADOW] SDRAM Timing Register 10, offset: 0x2128 */
7924 __IO uint32_t DRAMTMG11_SHADOW; /**< [SHADOW] SDRAM Timing Register 11, offset: 0x212C */
7925 __IO uint32_t DRAMTMG12_SHADOW; /**< [SHADOW] SDRAM Timing Register 12, offset: 0x2130 */
7926 __IO uint32_t DRAMTMG13_SHADOW; /**< [SHADOW] SDRAM Timing Register 13, offset: 0x2134 */
7927 __IO uint32_t DRAMTMG14_SHADOW; /**< [SHADOW] SDRAM Timing Register 14, offset: 0x2138 */
7928 __IO uint32_t DRAMTMG15_SHADOW; /**< [SHADOW] SDRAM Timing Register 15, offset: 0x213C */
7929 uint8_t RESERVED_24[64];
7930 __IO uint32_t ZQCTL0_SHADOW; /**< [SHADOW] ZQ Control Register 0, offset: 0x2180 */
7931 uint8_t RESERVED_25[12];
7932 __IO uint32_t DFITMG0_SHADOW; /**< [SHADOW] DFI Timing Register 0, offset: 0x2190 */
7933 __IO uint32_t DFITMG1_SHADOW; /**< [SHADOW] DFI Timing Register 1, offset: 0x2194 */
7934 uint8_t RESERVED_26[28];
7935 __IO uint32_t DFITMG2_SHADOW; /**< [SHADOW] DFI Timing Register 2, offset: 0x21B4 */
7936 __IO uint32_t DFITMG3_SHADOW; /**< [SHADOW] DFI Timing Register 3, offset: 0x21B8 */
7937 uint8_t RESERVED_27[132];
7938 __IO uint32_t ODTCFG_SHADOW; /**< [SHADOW] ODT Configuration Register, offset: 0x2240 */
7939} DDRC_Type;
7940
7941/* ----------------------------------------------------------------------------
7942 -- DDRC Register Masks
7943 ---------------------------------------------------------------------------- */
7944
7945/*!
7946 * @addtogroup DDRC_Register_Masks DDRC Register Masks
7947 * @{
7948 */
7949
7950/*! @name MSTR - Master Register0 */
7951/*! @{ */
7952#define DDRC_MSTR_ddr3_MASK (0x1U)
7953#define DDRC_MSTR_ddr3_SHIFT (0U)
7954#define DDRC_MSTR_ddr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ddr3_SHIFT)) & DDRC_MSTR_ddr3_MASK)
7955#define DDRC_MSTR_lpddr2_MASK (0x4U)
7956#define DDRC_MSTR_lpddr2_SHIFT (2U)
7957#define DDRC_MSTR_lpddr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr2_SHIFT)) & DDRC_MSTR_lpddr2_MASK)
7958#define DDRC_MSTR_lpddr3_MASK (0x8U)
7959#define DDRC_MSTR_lpddr3_SHIFT (3U)
7960#define DDRC_MSTR_lpddr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr3_SHIFT)) & DDRC_MSTR_lpddr3_MASK)
7961#define DDRC_MSTR_ddr4_MASK (0x10U)
7962#define DDRC_MSTR_ddr4_SHIFT (4U)
7963#define DDRC_MSTR_ddr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ddr4_SHIFT)) & DDRC_MSTR_ddr4_MASK)
7964#define DDRC_MSTR_lpddr4_MASK (0x20U)
7965#define DDRC_MSTR_lpddr4_SHIFT (5U)
7966#define DDRC_MSTR_lpddr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr4_SHIFT)) & DDRC_MSTR_lpddr4_MASK)
7967#define DDRC_MSTR_burstchop_MASK (0x200U)
7968#define DDRC_MSTR_burstchop_SHIFT (9U)
7969#define DDRC_MSTR_burstchop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_burstchop_SHIFT)) & DDRC_MSTR_burstchop_MASK)
7970#define DDRC_MSTR_en_2t_timing_mode_MASK (0x400U)
7971#define DDRC_MSTR_en_2t_timing_mode_SHIFT (10U)
7972#define DDRC_MSTR_en_2t_timing_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_en_2t_timing_mode_SHIFT)) & DDRC_MSTR_en_2t_timing_mode_MASK)
7973#define DDRC_MSTR_geardown_mode_MASK (0x800U)
7974#define DDRC_MSTR_geardown_mode_SHIFT (11U)
7975#define DDRC_MSTR_geardown_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_geardown_mode_SHIFT)) & DDRC_MSTR_geardown_mode_MASK)
7976#define DDRC_MSTR_data_bus_width_MASK (0x3000U)
7977#define DDRC_MSTR_data_bus_width_SHIFT (12U)
7978#define DDRC_MSTR_data_bus_width(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_data_bus_width_SHIFT)) & DDRC_MSTR_data_bus_width_MASK)
7979#define DDRC_MSTR_dll_off_mode_MASK (0x8000U)
7980#define DDRC_MSTR_dll_off_mode_SHIFT (15U)
7981#define DDRC_MSTR_dll_off_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_dll_off_mode_SHIFT)) & DDRC_MSTR_dll_off_mode_MASK)
7982#define DDRC_MSTR_burst_rdwr_MASK (0xF0000U)
7983#define DDRC_MSTR_burst_rdwr_SHIFT (16U)
7984/*! burst_rdwr - SDRAM burst length used
7985 * 0b0001..Burst length of 2 (only supported for mDDR)
7986 * 0b0010..Burst length of 4
7987 * 0b0100..Burst length of 8
7988 * 0b1000..Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4)
7989 */
7990#define DDRC_MSTR_burst_rdwr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_burst_rdwr_SHIFT)) & DDRC_MSTR_burst_rdwr_MASK)
7991#define DDRC_MSTR_frequency_ratio_MASK (0x400000U)
7992#define DDRC_MSTR_frequency_ratio_SHIFT (22U)
7993/*! frequency_ratio - Selects the Frequency Ratio
7994 * 0b0..1:2 Mode
7995 * 0b1..1:1 Mode
7996 */
7997#define DDRC_MSTR_frequency_ratio(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_frequency_ratio_SHIFT)) & DDRC_MSTR_frequency_ratio_MASK)
7998#define DDRC_MSTR_active_ranks_MASK (0x3000000U)
7999#define DDRC_MSTR_active_ranks_SHIFT (24U)
8000#define DDRC_MSTR_active_ranks(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_active_ranks_SHIFT)) & DDRC_MSTR_active_ranks_MASK)
8001#define DDRC_MSTR_frequency_mode_MASK (0x20000000U)
8002#define DDRC_MSTR_frequency_mode_SHIFT (29U)
8003/*! frequency_mode - Choose which registers are used.
8004 * 0b0..Original Registers
8005 * 0b1..Shadow Registers
8006 */
8007#define DDRC_MSTR_frequency_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_frequency_mode_SHIFT)) & DDRC_MSTR_frequency_mode_MASK)
8008#define DDRC_MSTR_device_config_MASK (0xC0000000U)
8009#define DDRC_MSTR_device_config_SHIFT (30U)
8010/*! device_config - Indicates the configuration of the device used in the system.
8011 * 0b00..x4 device
8012 * 0b01..x8 device
8013 * 0b10..x16 device
8014 * 0b11..x32 device
8015 */
8016#define DDRC_MSTR_device_config(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_device_config_SHIFT)) & DDRC_MSTR_device_config_MASK)
8017/*! @} */
8018
8019/*! @name STAT - Operating Mode Status Register */
8020/*! @{ */
8021#define DDRC_STAT_operating_mode_MASK (0x7U)
8022#define DDRC_STAT_operating_mode_SHIFT (0U)
8023#define DDRC_STAT_operating_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_operating_mode_SHIFT)) & DDRC_STAT_operating_mode_MASK)
8024#define DDRC_STAT_selfref_type_MASK (0x30U)
8025#define DDRC_STAT_selfref_type_SHIFT (4U)
8026/*! selfref_type - Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if
8027 * it was under Automatic Self Refresh control only or not.
8028 * 0b00..SDRAM is not in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by
8029 * CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still in parity error window or retry is
8030 * in-progress.
8031 * 0b11..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was caused by Automatic Self
8032 * Refresh only. If retry is enabled, this guarantees SRE command is executed correctly without parity error.
8033 * 0b10..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was not caused solely under
8034 * Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software
8035 * (reg_ddrc_selfref_sw). If retry is enabled, this guarantees SRE command is executed correctly without parity
8036 */
8037#define DDRC_STAT_selfref_type(x) (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_selfref_type_SHIFT)) & DDRC_STAT_selfref_type_MASK)
8038#define DDRC_STAT_selfref_state_MASK (0x300U)
8039#define DDRC_STAT_selfref_state_SHIFT (8U)
8040/*! selfref_state - Self refresh state. This indicates self refresh or self refresh power down state
8041 * for LPDDR4. This register is used for frequency change and MRR/MRW access during self refresh.
8042 * 0b00..SDRAM is not in Self Refresh.
8043 * 0b01..Self refresh 1
8044 * 0b10..Self refresh power down
8045 * 0b11..Self refresh
8046 */
8047#define DDRC_STAT_selfref_state(x) (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_selfref_state_SHIFT)) & DDRC_STAT_selfref_state_MASK)
8048/*! @} */
8049
8050/*! @name MSTR1 - Operating Mode Status Register */
8051/*! @{ */
8052#define DDRC_MSTR1_rank_tmgreg_sel_MASK (0x3U)
8053#define DDRC_MSTR1_rank_tmgreg_sel_SHIFT (0U)
8054/*! rank_tmgreg_sel - rank_tmgreg_sel
8055 * 0b00..USE DRAMTMGx registers for the rank
8056 * 0b01..USE MRAMTMGx registers for the rank
8057 */
8058#define DDRC_MSTR1_rank_tmgreg_sel(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_rank_tmgreg_sel_SHIFT)) & DDRC_MSTR1_rank_tmgreg_sel_MASK)
8059#define DDRC_MSTR1_alt_addrmap_en_MASK (0x10000U)
8060#define DDRC_MSTR1_alt_addrmap_en_SHIFT (16U)
8061/*! alt_addrmap_en - Enable Alternative Address Map
8062 * 0b0..Disable Alternative Address Map
8063 * 0b1..Enable Alternative Address Map
8064 */
8065#define DDRC_MSTR1_alt_addrmap_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_alt_addrmap_en_SHIFT)) & DDRC_MSTR1_alt_addrmap_en_MASK)
8066/*! @} */
8067
8068/*! @name MRCTRL3 - Operating Mode Status Register */
8069/*! @{ */
8070#define DDRC_MRCTRL3_mr_rank_sel_MASK (0x3U)
8071#define DDRC_MRCTRL3_mr_rank_sel_SHIFT (0U)
8072#define DDRC_MRCTRL3_mr_rank_sel(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL3_mr_rank_sel_SHIFT)) & DDRC_MRCTRL3_mr_rank_sel_MASK)
8073/*! @} */
8074
8075/*! @name MRCTRL0 - Mode Register Read/Write Control Register 0. */
8076/*! @{ */
8077#define DDRC_MRCTRL0_mr_type_MASK (0x1U)
8078#define DDRC_MRCTRL0_mr_type_SHIFT (0U)
8079/*! mr_type - Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4.
8080 * 0b0..Write
8081 * 0b1..Read
8082 */
8083#define DDRC_MRCTRL0_mr_type(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_type_SHIFT)) & DDRC_MRCTRL0_mr_type_MASK)
8084#define DDRC_MRCTRL0_mpr_en_MASK (0x2U)
8085#define DDRC_MRCTRL0_mpr_en_SHIFT (1U)
8086/*! mpr_en - Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4).
8087 * 0b0..MRS
8088 * 0b1..WR/RD for MPR
8089 */
8090#define DDRC_MRCTRL0_mpr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mpr_en_SHIFT)) & DDRC_MRCTRL0_mpr_en_MASK)
8091#define DDRC_MRCTRL0_pda_en_MASK (0x4U)
8092#define DDRC_MRCTRL0_pda_en_SHIFT (2U)
8093/*! pda_en - Indicates whether the mode register operation is MRS in PDA mode or not. Note that when
8094 * pba_mode=1, PBA access is initiated instead of PDA access.
8095 * 0b0..MRS
8096 * 0b1..MRS in Per DRAM Addressability
8097 */
8098#define DDRC_MRCTRL0_pda_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_pda_en_SHIFT)) & DDRC_MRCTRL0_pda_en_MASK)
8099#define DDRC_MRCTRL0_sw_init_int_MASK (0x8U)
8100#define DDRC_MRCTRL0_sw_init_int_SHIFT (3U)
8101/*! sw_init_int - Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before
8102 * automatic SDRAM initialization routine or not. For DDR4, this bit can be used to initialize the
8103 * DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit can be used to
8104 * program additional mode registers before automatic SDRAM initialization if necessary. In LPDDR4
8105 * independent channel mode, note that this must be programmed to both channels beforehand. Note that
8106 * this must be cleared to 0 after completing Software operation. Otherwise, SDRAM
8107 * initialization routine will not re-start.
8108 * 0b0..Software intervention is not allowed
8109 * 0b1..Software intervention is allowed
8110 */
8111#define DDRC_MRCTRL0_sw_init_int(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_sw_init_int_SHIFT)) & DDRC_MRCTRL0_sw_init_int_MASK)
8112#define DDRC_MRCTRL0_mr_rank_MASK (0x30U)
8113#define DDRC_MRCTRL0_mr_rank_SHIFT (4U)
8114#define DDRC_MRCTRL0_mr_rank(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_rank_SHIFT)) & DDRC_MRCTRL0_mr_rank_MASK)
8115#define DDRC_MRCTRL0_mr_addr_MASK (0xF000U)
8116#define DDRC_MRCTRL0_mr_addr_SHIFT (12U)
8117/*! mr_addr - Address of the mode register that is to be written to.
8118 * 0b0000..MR0
8119 * 0b0001..MR1
8120 * 0b0010..MR2
8121 * 0b0011..MR3
8122 * 0b0100..MR4
8123 * 0b0101..MR5
8124 * 0b0110..MR6
8125 * 0b0111..MR7
8126 */
8127#define DDRC_MRCTRL0_mr_addr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_addr_SHIFT)) & DDRC_MRCTRL0_mr_addr_MASK)
8128#define DDRC_MRCTRL0_pba_mode_MASK (0x40000000U)
8129#define DDRC_MRCTRL0_pba_mode_SHIFT (30U)
8130#define DDRC_MRCTRL0_pba_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_pba_mode_SHIFT)) & DDRC_MRCTRL0_pba_mode_MASK)
8131#define DDRC_MRCTRL0_mr_wr_MASK (0x80000000U)
8132#define DDRC_MRCTRL0_mr_wr_SHIFT (31U)
8133#define DDRC_MRCTRL0_mr_wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_wr_SHIFT)) & DDRC_MRCTRL0_mr_wr_MASK)
8134/*! @} */
8135
8136/*! @name MRCTRL1 - Mode Register Read/Write Control Register 1 */
8137/*! @{ */
8138#define DDRC_MRCTRL1_mr_data_MASK (0x3FFFFU)
8139#define DDRC_MRCTRL1_mr_data_SHIFT (0U)
8140#define DDRC_MRCTRL1_mr_data(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL1_mr_data_SHIFT)) & DDRC_MRCTRL1_mr_data_MASK)
8141/*! @} */
8142
8143/*! @name MRSTAT - Mode Register Read/Write Status Register */
8144/*! @{ */
8145#define DDRC_MRSTAT_mr_wr_busy_MASK (0x1U)
8146#define DDRC_MRSTAT_mr_wr_busy_SHIFT (0U)
8147/*! mr_wr_busy - The SoC core may initiate a MR write operation only if this signal is low. This
8148 * signal goes high in the clock after the DDRC accepts the MRW/MRR request. It goes low when the
8149 * MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when
8150 * 'MRSTAT.mr_wr_busy' is high.
8151 * 0b0..Indicates that the SoC core can initiate a mode register write operation
8152 * 0b1..Indicates that mode register write operation is in progress
8153 */
8154#define DDRC_MRSTAT_mr_wr_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_mr_wr_busy_SHIFT)) & DDRC_MRSTAT_mr_wr_busy_MASK)
8155#define DDRC_MRSTAT_pda_done_MASK (0x100U)
8156#define DDRC_MRSTAT_pda_done_SHIFT (8U)
8157/*! pda_done - The SoC core may initiate a MR write operation in PDA/PBA mode only if this signal is
8158 * low. This signal goes high when three consecutive MRS commands related to the PDA/PBA mode
8159 * are issued to the SDRAM. This signal goes low when MRCTRL0.pda_en becomes 0. Therefore, it is
8160 * recommended to write MRCTRL0.pda_en to 0 after this signal goes high in order to prepare to
8161 * perform PDA operation next time
8162 * 0b0..Indicates that mode register write operation related to PDA/PBA is in progress or has not started yet.
8163 * 0b1..Indicates that mode register write operation related to PDA/PBA has competed.
8164 */
8165#define DDRC_MRSTAT_pda_done(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_pda_done_SHIFT)) & DDRC_MRSTAT_pda_done_MASK)
8166/*! @} */
8167
8168/*! @name MRCTRL2 - Mode Register Read/Write Control Register 2 */
8169/*! @{ */
8170#define DDRC_MRCTRL2_mr_device_sel_MASK (0xFFFFFFFFU)
8171#define DDRC_MRCTRL2_mr_device_sel_SHIFT (0U)
8172#define DDRC_MRCTRL2_mr_device_sel(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL2_mr_device_sel_SHIFT)) & DDRC_MRCTRL2_mr_device_sel_MASK)
8173/*! @} */
8174
8175/*! @name DERATEEN - Temperature Derate Enable Register */
8176/*! @{ */
8177#define DDRC_DERATEEN_derate_enable_MASK (0x1U)
8178#define DDRC_DERATEEN_derate_enable_SHIFT (0U)
8179/*! derate_enable - Enables derating. Present only in designs configured to support
8180 * LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
8181 * 0b0..Timing parameter derating is disabled
8182 * 0b1..Timing parameter derating is enabled using MR4 read value.
8183 */
8184#define DDRC_DERATEEN_derate_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_enable_SHIFT)) & DDRC_DERATEEN_derate_enable_MASK)
8185#define DDRC_DERATEEN_derate_value_MASK (0x2U)
8186#define DDRC_DERATEEN_derate_value_SHIFT (1U)
8187/*! derate_value - Derate value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
8188 * Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a
8189 * core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this
8190 * register field should be set to 1; otherwise it should be set to 0.
8191 * 0b0..Derating uses +1
8192 * 0b1..Derating uses +2
8193 */
8194#define DDRC_DERATEEN_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_value_SHIFT)) & DDRC_DERATEEN_derate_value_MASK)
8195#define DDRC_DERATEEN_derate_byte_MASK (0xF0U)
8196#define DDRC_DERATEEN_derate_byte_SHIFT (4U)
8197#define DDRC_DERATEEN_derate_byte(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_byte_SHIFT)) & DDRC_DERATEEN_derate_byte_MASK)
8198#define DDRC_DERATEEN_rc_derate_value_MASK (0x300U)
8199#define DDRC_DERATEEN_rc_derate_value_SHIFT (8U)
8200/*! rc_derate_value - Derate value of tRC for LPDDR4. Present only in designs configured to support
8201 * LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the
8202 * core_ddrc_core_clk period, and rounding up the next integer.
8203 * 0b00..Derating uses +1
8204 * 0b01..Derating uses +2
8205 * 0b10..Derating uses +3
8206 * 0b11..Derating uses +4
8207 */
8208#define DDRC_DERATEEN_rc_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_rc_derate_value_SHIFT)) & DDRC_DERATEEN_rc_derate_value_MASK)
8209/*! @} */
8210
8211/*! @name DERATEINT - Temperature Derate Interval Register */
8212/*! @{ */
8213#define DDRC_DERATEINT_mr4_read_interval_MASK (0xFFFFFFFFU)
8214#define DDRC_DERATEINT_mr4_read_interval_SHIFT (0U)
8215#define DDRC_DERATEINT_mr4_read_interval(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_mr4_read_interval_SHIFT)) & DDRC_DERATEINT_mr4_read_interval_MASK)
8216/*! @} */
8217
8218/*! @name PWRCTL - Low Power Control Register */
8219/*! @{ */
8220#define DDRC_PWRCTL_selfref_en_MASK (0x1U)
8221#define DDRC_PWRCTL_selfref_en_SHIFT (0U)
8222#define DDRC_PWRCTL_selfref_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_selfref_en_SHIFT)) & DDRC_PWRCTL_selfref_en_MASK)
8223#define DDRC_PWRCTL_powerdown_en_MASK (0x2U)
8224#define DDRC_PWRCTL_powerdown_en_SHIFT (1U)
8225#define DDRC_PWRCTL_powerdown_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_powerdown_en_SHIFT)) & DDRC_PWRCTL_powerdown_en_MASK)
8226#define DDRC_PWRCTL_deeppowerdown_en_MASK (0x4U)
8227#define DDRC_PWRCTL_deeppowerdown_en_SHIFT (2U)
8228#define DDRC_PWRCTL_deeppowerdown_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_deeppowerdown_en_SHIFT)) & DDRC_PWRCTL_deeppowerdown_en_MASK)
8229#define DDRC_PWRCTL_en_dfi_dram_clk_disable_MASK (0x8U)
8230#define DDRC_PWRCTL_en_dfi_dram_clk_disable_SHIFT (3U)
8231#define DDRC_PWRCTL_en_dfi_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_en_dfi_dram_clk_disable_SHIFT)) & DDRC_PWRCTL_en_dfi_dram_clk_disable_MASK)
8232#define DDRC_PWRCTL_mpsm_en_MASK (0x10U)
8233#define DDRC_PWRCTL_mpsm_en_SHIFT (4U)
8234#define DDRC_PWRCTL_mpsm_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_mpsm_en_SHIFT)) & DDRC_PWRCTL_mpsm_en_MASK)
8235#define DDRC_PWRCTL_selfref_sw_MASK (0x20U)
8236#define DDRC_PWRCTL_selfref_sw_SHIFT (5U)
8237/*! selfref_sw - A value of 1 to this register causes system to move to Self Refresh state
8238 * immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software
8239 * Entry/Exit to Self Refresh.
8240 * 0b0..Software Exit from Self Refresh
8241 * 0b1..Software Entry to Self Refresh
8242 */
8243#define DDRC_PWRCTL_selfref_sw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_selfref_sw_SHIFT)) & DDRC_PWRCTL_selfref_sw_MASK)
8244#define DDRC_PWRCTL_stay_in_selfref_MASK (0x40U)
8245#define DDRC_PWRCTL_stay_in_selfref_SHIFT (6U)
8246/*! stay_in_selfref - Self refresh state is an intermediate state to enter to Self refresh power
8247 * down state or exit Self refresh power down state for LPDDR4. This register controls transition
8248 * from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 0 - Allow
8249 * transition from Self refresh state
8250 * 0b0..
8251 * 0b1..
8252 */
8253#define DDRC_PWRCTL_stay_in_selfref(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_stay_in_selfref_SHIFT)) & DDRC_PWRCTL_stay_in_selfref_MASK)
8254/*! @} */
8255
8256/*! @name PWRTMG - Low Power Timing Register */
8257/*! @{ */
8258#define DDRC_PWRTMG_powerdown_to_x32_MASK (0x1FU)
8259#define DDRC_PWRTMG_powerdown_to_x32_SHIFT (0U)
8260#define DDRC_PWRTMG_powerdown_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_powerdown_to_x32_SHIFT)) & DDRC_PWRTMG_powerdown_to_x32_MASK)
8261#define DDRC_PWRTMG_t_dpd_x4096_MASK (0xFF00U)
8262#define DDRC_PWRTMG_t_dpd_x4096_SHIFT (8U)
8263#define DDRC_PWRTMG_t_dpd_x4096(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_t_dpd_x4096_SHIFT)) & DDRC_PWRTMG_t_dpd_x4096_MASK)
8264#define DDRC_PWRTMG_selfref_to_x32_MASK (0xFF0000U)
8265#define DDRC_PWRTMG_selfref_to_x32_SHIFT (16U)
8266#define DDRC_PWRTMG_selfref_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_selfref_to_x32_SHIFT)) & DDRC_PWRTMG_selfref_to_x32_MASK)
8267/*! @} */
8268
8269/*! @name HWLPCTL - Hardware Low Power Control Register */
8270/*! @{ */
8271#define DDRC_HWLPCTL_hw_lp_en_MASK (0x1U)
8272#define DDRC_HWLPCTL_hw_lp_en_SHIFT (0U)
8273#define DDRC_HWLPCTL_hw_lp_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_en_SHIFT)) & DDRC_HWLPCTL_hw_lp_en_MASK)
8274#define DDRC_HWLPCTL_hw_lp_exit_idle_en_MASK (0x2U)
8275#define DDRC_HWLPCTL_hw_lp_exit_idle_en_SHIFT (1U)
8276#define DDRC_HWLPCTL_hw_lp_exit_idle_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_exit_idle_en_SHIFT)) & DDRC_HWLPCTL_hw_lp_exit_idle_en_MASK)
8277#define DDRC_HWLPCTL_hw_lp_idle_x32_MASK (0xFFF0000U)
8278#define DDRC_HWLPCTL_hw_lp_idle_x32_SHIFT (16U)
8279#define DDRC_HWLPCTL_hw_lp_idle_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_idle_x32_SHIFT)) & DDRC_HWLPCTL_hw_lp_idle_x32_MASK)
8280/*! @} */
8281
8282/*! @name RFSHCTL0 - Refresh Control Register 0 */
8283/*! @{ */
8284#define DDRC_RFSHCTL0_per_bank_refresh_MASK (0x4U)
8285#define DDRC_RFSHCTL0_per_bank_refresh_SHIFT (2U)
8286/*! per_bank_refresh - Per bank refresh allows traffic to flow to other banks. Per bank refresh is
8287 * not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices.
8288 * Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
8289 * 0b1..Per bank refresh
8290 * 0b0..All bank refresh
8291 */
8292#define DDRC_RFSHCTL0_per_bank_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_per_bank_refresh_SHIFT)) & DDRC_RFSHCTL0_per_bank_refresh_MASK)
8293#define DDRC_RFSHCTL0_refresh_burst_MASK (0x1F0U)
8294#define DDRC_RFSHCTL0_refresh_burst_SHIFT (4U)
8295#define DDRC_RFSHCTL0_refresh_burst(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_burst_SHIFT)) & DDRC_RFSHCTL0_refresh_burst_MASK)
8296#define DDRC_RFSHCTL0_refresh_to_x32_MASK (0x1F000U)
8297#define DDRC_RFSHCTL0_refresh_to_x32_SHIFT (12U)
8298#define DDRC_RFSHCTL0_refresh_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_to_x32_SHIFT)) & DDRC_RFSHCTL0_refresh_to_x32_MASK)
8299#define DDRC_RFSHCTL0_refresh_margin_MASK (0xF00000U)
8300#define DDRC_RFSHCTL0_refresh_margin_SHIFT (20U)
8301#define DDRC_RFSHCTL0_refresh_margin(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_margin_SHIFT)) & DDRC_RFSHCTL0_refresh_margin_MASK)
8302/*! @} */
8303
8304/*! @name RFSHCTL1 - Refresh Control Register 1 */
8305/*! @{ */
8306#define DDRC_RFSHCTL1_refresh_timer0_start_value_x32_MASK (0xFFFU)
8307#define DDRC_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT (0U)
8308#define DDRC_RFSHCTL1_refresh_timer0_start_value_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT)) & DDRC_RFSHCTL1_refresh_timer0_start_value_x32_MASK)
8309#define DDRC_RFSHCTL1_refresh_timer1_start_value_x32_MASK (0xFFF0000U)
8310#define DDRC_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT (16U)
8311#define DDRC_RFSHCTL1_refresh_timer1_start_value_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT)) & DDRC_RFSHCTL1_refresh_timer1_start_value_x32_MASK)
8312/*! @} */
8313
8314/*! @name RFSHCTL3 - Refresh Control Register 3 */
8315/*! @{ */
8316#define DDRC_RFSHCTL3_dis_auto_refresh_MASK (0x1U)
8317#define DDRC_RFSHCTL3_dis_auto_refresh_SHIFT (0U)
8318#define DDRC_RFSHCTL3_dis_auto_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_dis_auto_refresh_SHIFT)) & DDRC_RFSHCTL3_dis_auto_refresh_MASK)
8319#define DDRC_RFSHCTL3_refresh_update_level_MASK (0x2U)
8320#define DDRC_RFSHCTL3_refresh_update_level_SHIFT (1U)
8321#define DDRC_RFSHCTL3_refresh_update_level(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_refresh_update_level_SHIFT)) & DDRC_RFSHCTL3_refresh_update_level_MASK)
8322#define DDRC_RFSHCTL3_refresh_mode_MASK (0x70U)
8323#define DDRC_RFSHCTL3_refresh_mode_SHIFT (4U)
8324#define DDRC_RFSHCTL3_refresh_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_refresh_mode_SHIFT)) & DDRC_RFSHCTL3_refresh_mode_MASK)
8325/*! @} */
8326
8327/*! @name RFSHTMG - Refresh Timing Register */
8328/*! @{ */
8329#define DDRC_RFSHTMG_t_rfc_min_MASK (0x3FFU)
8330#define DDRC_RFSHTMG_t_rfc_min_SHIFT (0U)
8331#define DDRC_RFSHTMG_t_rfc_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_t_rfc_min_SHIFT)) & DDRC_RFSHTMG_t_rfc_min_MASK)
8332#define DDRC_RFSHTMG_lpddr3_trefbw_en_MASK (0x8000U)
8333#define DDRC_RFSHTMG_lpddr3_trefbw_en_SHIFT (15U)
8334#define DDRC_RFSHTMG_lpddr3_trefbw_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_lpddr3_trefbw_en_SHIFT)) & DDRC_RFSHTMG_lpddr3_trefbw_en_MASK)
8335#define DDRC_RFSHTMG_t_rfc_nom_x32_MASK (0xFFF0000U)
8336#define DDRC_RFSHTMG_t_rfc_nom_x32_SHIFT (16U)
8337#define DDRC_RFSHTMG_t_rfc_nom_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_t_rfc_nom_x32_SHIFT)) & DDRC_RFSHTMG_t_rfc_nom_x32_MASK)
8338/*! @} */
8339
8340/*! @name INIT0 - SDRAM Initialization Register 0 */
8341/*! @{ */
8342#define DDRC_INIT0_pre_cke_x1024_MASK (0xFFFU)
8343#define DDRC_INIT0_pre_cke_x1024_SHIFT (0U)
8344#define DDRC_INIT0_pre_cke_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_pre_cke_x1024_SHIFT)) & DDRC_INIT0_pre_cke_x1024_MASK)
8345#define DDRC_INIT0_post_cke_x1024_MASK (0x3FF0000U)
8346#define DDRC_INIT0_post_cke_x1024_SHIFT (16U)
8347#define DDRC_INIT0_post_cke_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_post_cke_x1024_SHIFT)) & DDRC_INIT0_post_cke_x1024_MASK)
8348#define DDRC_INIT0_skip_dram_init_MASK (0xC0000000U)
8349#define DDRC_INIT0_skip_dram_init_SHIFT (30U)
8350/*! skip_dram_init - If lower bit is enabled the SDRAM initialization routine is skipped. The upper
8351 * bit decides what state the controller starts up in when reset is removed - 00 - SDRAM
8352 * Intialization routine is run after power-up - 01 - SDRAM Initialization routine is skipped after
8353 * power-up. Controller starts up in Normal Mode - 11 - SDRAM Initialization routine is skipped after
8354 * power-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Initialization routine is run
8355 * after power-up.
8356 * 0b00..SDRAM Initialization routine is run after power-up
8357 * 0b01..SDRAM Initialization routine is skipped after power-up
8358 * 0b10..SDRAM Initialization routine is run after power-up
8359 * 0b11..SDRAM Initialization routine is skipped after power-up
8360 */
8361#define DDRC_INIT0_skip_dram_init(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_skip_dram_init_SHIFT)) & DDRC_INIT0_skip_dram_init_MASK)
8362/*! @} */
8363
8364/*! @name INIT1 - SDRAM Initialization Register 1 */
8365/*! @{ */
8366#define DDRC_INIT1_pre_ocd_x32_MASK (0xFU)
8367#define DDRC_INIT1_pre_ocd_x32_SHIFT (0U)
8368#define DDRC_INIT1_pre_ocd_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_pre_ocd_x32_SHIFT)) & DDRC_INIT1_pre_ocd_x32_MASK)
8369#define DDRC_INIT1_dram_rstn_x1024_MASK (0x1FF0000U)
8370#define DDRC_INIT1_dram_rstn_x1024_SHIFT (16U)
8371#define DDRC_INIT1_dram_rstn_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_dram_rstn_x1024_SHIFT)) & DDRC_INIT1_dram_rstn_x1024_MASK)
8372/*! @} */
8373
8374/*! @name INIT2 - SDRAM Initialization Register 2 */
8375/*! @{ */
8376#define DDRC_INIT2_min_stable_clock_x1_MASK (0xFU)
8377#define DDRC_INIT2_min_stable_clock_x1_SHIFT (0U)
8378#define DDRC_INIT2_min_stable_clock_x1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_min_stable_clock_x1_SHIFT)) & DDRC_INIT2_min_stable_clock_x1_MASK)
8379#define DDRC_INIT2_idle_after_reset_x32_MASK (0xFF00U)
8380#define DDRC_INIT2_idle_after_reset_x32_SHIFT (8U)
8381#define DDRC_INIT2_idle_after_reset_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_idle_after_reset_x32_SHIFT)) & DDRC_INIT2_idle_after_reset_x32_MASK)
8382/*! @} */
8383
8384/*! @name INIT3 - SDRAM Initialization Register 3 */
8385/*! @{ */
8386#define DDRC_INIT3_emr_MASK (0xFFFFU)
8387#define DDRC_INIT3_emr_SHIFT (0U)
8388#define DDRC_INIT3_emr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_emr_SHIFT)) & DDRC_INIT3_emr_MASK)
8389#define DDRC_INIT3_mr_MASK (0xFFFF0000U)
8390#define DDRC_INIT3_mr_SHIFT (16U)
8391#define DDRC_INIT3_mr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_mr_SHIFT)) & DDRC_INIT3_mr_MASK)
8392/*! @} */
8393
8394/*! @name INIT4 - SDRAM Initialization Register 4 */
8395/*! @{ */
8396#define DDRC_INIT4_emr3_MASK (0xFFFFU)
8397#define DDRC_INIT4_emr3_SHIFT (0U)
8398#define DDRC_INIT4_emr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_emr3_SHIFT)) & DDRC_INIT4_emr3_MASK)
8399#define DDRC_INIT4_emr2_MASK (0xFFFF0000U)
8400#define DDRC_INIT4_emr2_SHIFT (16U)
8401#define DDRC_INIT4_emr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_emr2_SHIFT)) & DDRC_INIT4_emr2_MASK)
8402/*! @} */
8403
8404/*! @name INIT5 - SDRAM Initialization Register 5 */
8405/*! @{ */
8406#define DDRC_INIT5_max_auto_init_x1024_MASK (0x3FFU)
8407#define DDRC_INIT5_max_auto_init_x1024_SHIFT (0U)
8408#define DDRC_INIT5_max_auto_init_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_max_auto_init_x1024_SHIFT)) & DDRC_INIT5_max_auto_init_x1024_MASK)
8409#define DDRC_INIT5_dev_zqinit_x32_MASK (0xFF0000U)
8410#define DDRC_INIT5_dev_zqinit_x32_SHIFT (16U)
8411#define DDRC_INIT5_dev_zqinit_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_dev_zqinit_x32_SHIFT)) & DDRC_INIT5_dev_zqinit_x32_MASK)
8412/*! @} */
8413
8414/*! @name INIT6 - SDRAM Initialization Register 6 */
8415/*! @{ */
8416#define DDRC_INIT6_mr5_MASK (0xFFFFU)
8417#define DDRC_INIT6_mr5_SHIFT (0U)
8418#define DDRC_INIT6_mr5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_mr5_SHIFT)) & DDRC_INIT6_mr5_MASK)
8419#define DDRC_INIT6_mr4_MASK (0xFFFF0000U)
8420#define DDRC_INIT6_mr4_SHIFT (16U)
8421#define DDRC_INIT6_mr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_mr4_SHIFT)) & DDRC_INIT6_mr4_MASK)
8422/*! @} */
8423
8424/*! @name INIT7 - SDRAM Initialization Register 7 */
8425/*! @{ */
8426#define DDRC_INIT7_mr6_MASK (0xFFFF0000U)
8427#define DDRC_INIT7_mr6_SHIFT (16U)
8428#define DDRC_INIT7_mr6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_mr6_SHIFT)) & DDRC_INIT7_mr6_MASK)
8429/*! @} */
8430
8431/*! @name DIMMCTL - DIMM Control Register */
8432/*! @{ */
8433#define DDRC_DIMMCTL_dimm_stagger_cs_en_MASK (0x1U)
8434#define DDRC_DIMMCTL_dimm_stagger_cs_en_SHIFT (0U)
8435/*! dimm_stagger_cs_en - Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and
8436 * LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs.
8437 * Even if this bit is set it does not take care of software driven MR commands (via
8438 * MRCTRL0/MRCTRL1), where software is responsible to send them to separate ranks as appropriate.
8439 * 0b0..Do not stagger accesses
8440 * 0b1..For(non-DDR4) Send all commands to even and odd ranks separately; For(DDR4) Send MRS commands to each ranks separately
8441 */
8442#define DDRC_DIMMCTL_dimm_stagger_cs_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_stagger_cs_en_SHIFT)) & DDRC_DIMMCTL_dimm_stagger_cs_en_MASK)
8443#define DDRC_DIMMCTL_dimm_addr_mirr_en_MASK (0x2U)
8444#define DDRC_DIMMCTL_dimm_addr_mirr_en_SHIFT (1U)
8445/*! dimm_addr_mirr_en - Address Mirroring Enable (for multi-rank UDIMM implementations and
8446 * multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address
8447 * mirroring for odd ranks, which means that the following address, bank address and bank group
8448 * bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for
8449 * the DDR4. Setting this bit ensures that, for mode register accesses during the automatic
8450 * initialization routine, these bits are swapped within the DDRC to compensate for this
8451 * UDIMM/RDIMM/LRDIMM swapping. In addition to the automatic initialization routine, in case of DDR4
8452 * UDIMM/RDIMM/LRDIMM, they are swapped during the automatic MRS access to enable/disable of a particular
8453 * DDR4 feature. Note: This has no effect on the address of any other memory accesses, or of
8454 * software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4
8455 * SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0
8456 * because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1.
8457 * 0b0..Do not implement address mirroring
8458 * 0b1..For odd ranks, implement address mirroring for MRS commands to during initialization and for any
8459 * automatic DDR4 MRS commands (to be used if UDIMM/RDIMM/LRDIMM implements address mirroring)
8460 */
8461#define DDRC_DIMMCTL_dimm_addr_mirr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_addr_mirr_en_SHIFT)) & DDRC_DIMMCTL_dimm_addr_mirr_en_MASK)
8462#define DDRC_DIMMCTL_dimm_output_inv_en_MASK (0x4U)
8463#define DDRC_DIMMCTL_dimm_output_inv_en_SHIFT (2U)
8464/*! dimm_output_inv_en - Output Inversion Enable (for DDR4 RDIMM/LRDIMM implementations only). DDR4
8465 * RDIMM/LRDIMM implements the Output Inversion feature by default, which means that the
8466 * following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13,
8467 * A17, BA0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the
8468 * DDRC during the automatic initialization routine and enabling of a particular DDR4 feature,
8469 * separate A-side and B-side mode register accesses are generated. For B-side mode register
8470 * accesses, these bits are inverted within the DDRC to compensate for this RDIMM/LRDIMM inversion. It
8471 * is recommended to set this bit always, if using DDR4 RDIMMs/LRDIMMs. Note: This has no effect
8472 * on the address of any other memory accesses, or of software-driven mode register accesses.
8473 * 0b0..Do not implement output inversion for B-side DRAMs.
8474 * 0b1..Implement output inversion for B-side DRAMs.
8475 */
8476#define DDRC_DIMMCTL_dimm_output_inv_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_output_inv_en_SHIFT)) & DDRC_DIMMCTL_dimm_output_inv_en_MASK)
8477#define DDRC_DIMMCTL_mrs_a17_en_MASK (0x8U)
8478#define DDRC_DIMMCTL_mrs_a17_en_SHIFT (3U)
8479/*! mrs_a17_en - Enable for A17 bit of MRS command. A17 bit of the mode register address is
8480 * specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs
8481 * which do not have A17 are attached and the Output Inversion are enabled, this must be set to
8482 * 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on
8483 * the address of any other memory accesses, or of software-driven mode register accesses.
8484 * 0b0..Disabled
8485 * 0b1..Enabled
8486 */
8487#define DDRC_DIMMCTL_mrs_a17_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_mrs_a17_en_SHIFT)) & DDRC_DIMMCTL_mrs_a17_en_MASK)
8488#define DDRC_DIMMCTL_mrs_bg1_en_MASK (0x10U)
8489#define DDRC_DIMMCTL_mrs_bg1_en_SHIFT (4U)
8490/*! mrs_bg1_en - Enable for BG1 bit of MRS command. BG1 bit of the mode register address is
8491 * specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs
8492 * which do not have BG1 are attached and both the CA parity and the Output Inversion are
8493 * enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note:
8494 * This has no effect on the address of any other memory accesses, or of software-driven mode
8495 * register accesses. If address mirroring is enabled, this is applied to BG1 of even ranks and BG0
8496 * of odd ranks.
8497 * 0b0..Disabled
8498 * 0b1..Enabled
8499 */
8500#define DDRC_DIMMCTL_mrs_bg1_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_mrs_bg1_en_SHIFT)) & DDRC_DIMMCTL_mrs_bg1_en_MASK)
8501#define DDRC_DIMMCTL_dimm_dis_bg_mirroring_MASK (0x20U)
8502#define DDRC_DIMMCTL_dimm_dis_bg_mirroring_SHIFT (5U)
8503/*! dimm_dis_bg_mirroring - Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and
8504 * BG1 are NOT swapped even if Address Mirroring is enabled. This will be required for DDR4 DIMMs
8505 * with x16 devices.
8506 * 0b0..BG0 and BG1 are swapped if address mirroring is enabled.
8507 * 0b1..BG0 and BG1 are NOT swapped.
8508 */
8509#define DDRC_DIMMCTL_dimm_dis_bg_mirroring(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_dis_bg_mirroring_SHIFT)) & DDRC_DIMMCTL_dimm_dis_bg_mirroring_MASK)
8510#define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_MASK (0x40U)
8511#define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT (6U)
8512#define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT)) & DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_MASK)
8513/*! @} */
8514
8515/*! @name RANKCTL - Rank Control Register */
8516/*! @{ */
8517#define DDRC_RANKCTL_max_rank_rd_MASK (0xFU)
8518#define DDRC_RANKCTL_max_rank_rd_SHIFT (0U)
8519#define DDRC_RANKCTL_max_rank_rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_max_rank_rd_SHIFT)) & DDRC_RANKCTL_max_rank_rd_MASK)
8520#define DDRC_RANKCTL_diff_rank_rd_gap_MASK (0xF0U)
8521#define DDRC_RANKCTL_diff_rank_rd_gap_SHIFT (4U)
8522#define DDRC_RANKCTL_diff_rank_rd_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_diff_rank_rd_gap_SHIFT)) & DDRC_RANKCTL_diff_rank_rd_gap_MASK)
8523#define DDRC_RANKCTL_diff_rank_wr_gap_MASK (0xF00U)
8524#define DDRC_RANKCTL_diff_rank_wr_gap_SHIFT (8U)
8525#define DDRC_RANKCTL_diff_rank_wr_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_diff_rank_wr_gap_SHIFT)) & DDRC_RANKCTL_diff_rank_wr_gap_MASK)
8526/*! @} */
8527
8528/*! @name DRAMTMG0 - SDRAM Timing Register 0 */
8529/*! @{ */
8530#define DDRC_DRAMTMG0_t_ras_min_MASK (0x3FU)
8531#define DDRC_DRAMTMG0_t_ras_min_SHIFT (0U)
8532#define DDRC_DRAMTMG0_t_ras_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_ras_min_SHIFT)) & DDRC_DRAMTMG0_t_ras_min_MASK)
8533#define DDRC_DRAMTMG0_t_ras_max_MASK (0x7F00U)
8534#define DDRC_DRAMTMG0_t_ras_max_SHIFT (8U)
8535#define DDRC_DRAMTMG0_t_ras_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_ras_max_SHIFT)) & DDRC_DRAMTMG0_t_ras_max_MASK)
8536#define DDRC_DRAMTMG0_t_faw_MASK (0x3F0000U)
8537#define DDRC_DRAMTMG0_t_faw_SHIFT (16U)
8538#define DDRC_DRAMTMG0_t_faw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_faw_SHIFT)) & DDRC_DRAMTMG0_t_faw_MASK)
8539#define DDRC_DRAMTMG0_wr2pre_MASK (0x7F000000U)
8540#define DDRC_DRAMTMG0_wr2pre_SHIFT (24U)
8541#define DDRC_DRAMTMG0_wr2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_wr2pre_SHIFT)) & DDRC_DRAMTMG0_wr2pre_MASK)
8542/*! @} */
8543
8544/*! @name DRAMTMG1 - SDRAM Timing Register 1 */
8545/*! @{ */
8546#define DDRC_DRAMTMG1_t_rc_MASK (0x7FU)
8547#define DDRC_DRAMTMG1_t_rc_SHIFT (0U)
8548#define DDRC_DRAMTMG1_t_rc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_t_rc_SHIFT)) & DDRC_DRAMTMG1_t_rc_MASK)
8549#define DDRC_DRAMTMG1_rd2pre_MASK (0x3F00U)
8550#define DDRC_DRAMTMG1_rd2pre_SHIFT (8U)
8551#define DDRC_DRAMTMG1_rd2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_rd2pre_SHIFT)) & DDRC_DRAMTMG1_rd2pre_MASK)
8552#define DDRC_DRAMTMG1_t_xp_MASK (0x1F0000U)
8553#define DDRC_DRAMTMG1_t_xp_SHIFT (16U)
8554#define DDRC_DRAMTMG1_t_xp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_t_xp_SHIFT)) & DDRC_DRAMTMG1_t_xp_MASK)
8555/*! @} */
8556
8557/*! @name DRAMTMG2 - SDRAM Timing Register 2 */
8558/*! @{ */
8559#define DDRC_DRAMTMG2_wr2rd_MASK (0x3FU)
8560#define DDRC_DRAMTMG2_wr2rd_SHIFT (0U)
8561#define DDRC_DRAMTMG2_wr2rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_wr2rd_SHIFT)) & DDRC_DRAMTMG2_wr2rd_MASK)
8562#define DDRC_DRAMTMG2_rd2wr_MASK (0x3F00U)
8563#define DDRC_DRAMTMG2_rd2wr_SHIFT (8U)
8564#define DDRC_DRAMTMG2_rd2wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_rd2wr_SHIFT)) & DDRC_DRAMTMG2_rd2wr_MASK)
8565#define DDRC_DRAMTMG2_read_latency_MASK (0x3F0000U)
8566#define DDRC_DRAMTMG2_read_latency_SHIFT (16U)
8567#define DDRC_DRAMTMG2_read_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_read_latency_SHIFT)) & DDRC_DRAMTMG2_read_latency_MASK)
8568#define DDRC_DRAMTMG2_write_latency_MASK (0x3F000000U)
8569#define DDRC_DRAMTMG2_write_latency_SHIFT (24U)
8570#define DDRC_DRAMTMG2_write_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_write_latency_SHIFT)) & DDRC_DRAMTMG2_write_latency_MASK)
8571/*! @} */
8572
8573/*! @name DRAMTMG3 - SDRAM Timing Register 3 */
8574/*! @{ */
8575#define DDRC_DRAMTMG3_t_mod_MASK (0x3FFU)
8576#define DDRC_DRAMTMG3_t_mod_SHIFT (0U)
8577#define DDRC_DRAMTMG3_t_mod(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mod_SHIFT)) & DDRC_DRAMTMG3_t_mod_MASK)
8578#define DDRC_DRAMTMG3_t_mrd_MASK (0x3F000U)
8579#define DDRC_DRAMTMG3_t_mrd_SHIFT (12U)
8580#define DDRC_DRAMTMG3_t_mrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mrd_SHIFT)) & DDRC_DRAMTMG3_t_mrd_MASK)
8581#define DDRC_DRAMTMG3_t_mrw_MASK (0x3FF00000U)
8582#define DDRC_DRAMTMG3_t_mrw_SHIFT (20U)
8583#define DDRC_DRAMTMG3_t_mrw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mrw_SHIFT)) & DDRC_DRAMTMG3_t_mrw_MASK)
8584/*! @} */
8585
8586/*! @name DRAMTMG4 - SDRAM Timing Register 4 */
8587/*! @{ */
8588#define DDRC_DRAMTMG4_t_rp_MASK (0x1FU)
8589#define DDRC_DRAMTMG4_t_rp_SHIFT (0U)
8590#define DDRC_DRAMTMG4_t_rp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rp_SHIFT)) & DDRC_DRAMTMG4_t_rp_MASK)
8591#define DDRC_DRAMTMG4_t_rrd_MASK (0xF00U)
8592#define DDRC_DRAMTMG4_t_rrd_SHIFT (8U)
8593#define DDRC_DRAMTMG4_t_rrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rrd_SHIFT)) & DDRC_DRAMTMG4_t_rrd_MASK)
8594#define DDRC_DRAMTMG4_t_ccd_MASK (0xF0000U)
8595#define DDRC_DRAMTMG4_t_ccd_SHIFT (16U)
8596#define DDRC_DRAMTMG4_t_ccd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_ccd_SHIFT)) & DDRC_DRAMTMG4_t_ccd_MASK)
8597#define DDRC_DRAMTMG4_t_rcd_MASK (0x1F000000U)
8598#define DDRC_DRAMTMG4_t_rcd_SHIFT (24U)
8599#define DDRC_DRAMTMG4_t_rcd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rcd_SHIFT)) & DDRC_DRAMTMG4_t_rcd_MASK)
8600/*! @} */
8601
8602/*! @name DRAMTMG5 - SDRAM Timing Register 5 */
8603/*! @{ */
8604#define DDRC_DRAMTMG5_t_cke_MASK (0x1FU)
8605#define DDRC_DRAMTMG5_t_cke_SHIFT (0U)
8606#define DDRC_DRAMTMG5_t_cke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cke_SHIFT)) & DDRC_DRAMTMG5_t_cke_MASK)
8607#define DDRC_DRAMTMG5_t_ckesr_MASK (0x3F00U)
8608#define DDRC_DRAMTMG5_t_ckesr_SHIFT (8U)
8609#define DDRC_DRAMTMG5_t_ckesr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_ckesr_SHIFT)) & DDRC_DRAMTMG5_t_ckesr_MASK)
8610#define DDRC_DRAMTMG5_t_cksre_MASK (0xF0000U)
8611#define DDRC_DRAMTMG5_t_cksre_SHIFT (16U)
8612#define DDRC_DRAMTMG5_t_cksre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cksre_SHIFT)) & DDRC_DRAMTMG5_t_cksre_MASK)
8613#define DDRC_DRAMTMG5_t_cksrx_MASK (0xF000000U)
8614#define DDRC_DRAMTMG5_t_cksrx_SHIFT (24U)
8615#define DDRC_DRAMTMG5_t_cksrx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cksrx_SHIFT)) & DDRC_DRAMTMG5_t_cksrx_MASK)
8616/*! @} */
8617
8618/*! @name DRAMTMG6 - SDRAM Timing Register 6 */
8619/*! @{ */
8620#define DDRC_DRAMTMG6_t_ckcsx_MASK (0xFU)
8621#define DDRC_DRAMTMG6_t_ckcsx_SHIFT (0U)
8622#define DDRC_DRAMTMG6_t_ckcsx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckcsx_SHIFT)) & DDRC_DRAMTMG6_t_ckcsx_MASK)
8623#define DDRC_DRAMTMG6_t_ckdpdx_MASK (0xF0000U)
8624#define DDRC_DRAMTMG6_t_ckdpdx_SHIFT (16U)
8625#define DDRC_DRAMTMG6_t_ckdpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckdpdx_SHIFT)) & DDRC_DRAMTMG6_t_ckdpdx_MASK)
8626#define DDRC_DRAMTMG6_t_ckdpde_MASK (0xF000000U)
8627#define DDRC_DRAMTMG6_t_ckdpde_SHIFT (24U)
8628#define DDRC_DRAMTMG6_t_ckdpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckdpde_SHIFT)) & DDRC_DRAMTMG6_t_ckdpde_MASK)
8629/*! @} */
8630
8631/*! @name DRAMTMG7 - SDRAM Timing Register 7 */
8632/*! @{ */
8633#define DDRC_DRAMTMG7_t_ckpdx_MASK (0xFU)
8634#define DDRC_DRAMTMG7_t_ckpdx_SHIFT (0U)
8635#define DDRC_DRAMTMG7_t_ckpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_t_ckpdx_SHIFT)) & DDRC_DRAMTMG7_t_ckpdx_MASK)
8636#define DDRC_DRAMTMG7_t_ckpde_MASK (0xF00U)
8637#define DDRC_DRAMTMG7_t_ckpde_SHIFT (8U)
8638#define DDRC_DRAMTMG7_t_ckpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_t_ckpde_SHIFT)) & DDRC_DRAMTMG7_t_ckpde_MASK)
8639/*! @} */
8640
8641/*! @name DRAMTMG8 - SDRAM Timing Register 8 */
8642/*! @{ */
8643#define DDRC_DRAMTMG8_t_xs_x32_MASK (0x7FU)
8644#define DDRC_DRAMTMG8_t_xs_x32_SHIFT (0U)
8645#define DDRC_DRAMTMG8_t_xs_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_x32_MASK)
8646#define DDRC_DRAMTMG8_t_xs_dll_x32_MASK (0x7F00U)
8647#define DDRC_DRAMTMG8_t_xs_dll_x32_SHIFT (8U)
8648#define DDRC_DRAMTMG8_t_xs_dll_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_dll_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_dll_x32_MASK)
8649#define DDRC_DRAMTMG8_t_xs_abort_x32_MASK (0x7F0000U)
8650#define DDRC_DRAMTMG8_t_xs_abort_x32_SHIFT (16U)
8651#define DDRC_DRAMTMG8_t_xs_abort_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_abort_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_abort_x32_MASK)
8652#define DDRC_DRAMTMG8_t_xs_fast_x32_MASK (0x7F000000U)
8653#define DDRC_DRAMTMG8_t_xs_fast_x32_SHIFT (24U)
8654#define DDRC_DRAMTMG8_t_xs_fast_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_fast_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_fast_x32_MASK)
8655/*! @} */
8656
8657/*! @name DRAMTMG9 - SDRAM Timing Register 9 */
8658/*! @{ */
8659#define DDRC_DRAMTMG9_wr2rd_s_MASK (0x3FU)
8660#define DDRC_DRAMTMG9_wr2rd_s_SHIFT (0U)
8661#define DDRC_DRAMTMG9_wr2rd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_wr2rd_s_SHIFT)) & DDRC_DRAMTMG9_wr2rd_s_MASK)
8662#define DDRC_DRAMTMG9_t_rrd_s_MASK (0xF00U)
8663#define DDRC_DRAMTMG9_t_rrd_s_SHIFT (8U)
8664#define DDRC_DRAMTMG9_t_rrd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_t_rrd_s_SHIFT)) & DDRC_DRAMTMG9_t_rrd_s_MASK)
8665#define DDRC_DRAMTMG9_t_ccd_s_MASK (0x70000U)
8666#define DDRC_DRAMTMG9_t_ccd_s_SHIFT (16U)
8667#define DDRC_DRAMTMG9_t_ccd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_t_ccd_s_SHIFT)) & DDRC_DRAMTMG9_t_ccd_s_MASK)
8668#define DDRC_DRAMTMG9_ddr4_wr_preamble_MASK (0x40000000U)
8669#define DDRC_DRAMTMG9_ddr4_wr_preamble_SHIFT (30U)
8670#define DDRC_DRAMTMG9_ddr4_wr_preamble(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_ddr4_wr_preamble_SHIFT)) & DDRC_DRAMTMG9_ddr4_wr_preamble_MASK)
8671/*! @} */
8672
8673/*! @name DRAMTMG10 - SDRAM Timing Register 10 */
8674/*! @{ */
8675#define DDRC_DRAMTMG10_t_gear_hold_MASK (0x3U)
8676#define DDRC_DRAMTMG10_t_gear_hold_SHIFT (0U)
8677#define DDRC_DRAMTMG10_t_gear_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_gear_hold_SHIFT)) & DDRC_DRAMTMG10_t_gear_hold_MASK)
8678#define DDRC_DRAMTMG10_t_gear_setup_MASK (0xCU)
8679#define DDRC_DRAMTMG10_t_gear_setup_SHIFT (2U)
8680#define DDRC_DRAMTMG10_t_gear_setup(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_gear_setup_SHIFT)) & DDRC_DRAMTMG10_t_gear_setup_MASK)
8681#define DDRC_DRAMTMG10_t_cmd_gear_MASK (0x1F00U)
8682#define DDRC_DRAMTMG10_t_cmd_gear_SHIFT (8U)
8683#define DDRC_DRAMTMG10_t_cmd_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_cmd_gear_SHIFT)) & DDRC_DRAMTMG10_t_cmd_gear_MASK)
8684#define DDRC_DRAMTMG10_t_sync_gear_MASK (0x1F0000U)
8685#define DDRC_DRAMTMG10_t_sync_gear_SHIFT (16U)
8686#define DDRC_DRAMTMG10_t_sync_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_sync_gear_SHIFT)) & DDRC_DRAMTMG10_t_sync_gear_MASK)
8687/*! @} */
8688
8689/*! @name DRAMTMG11 - SDRAM Timing Register 11 */
8690/*! @{ */
8691#define DDRC_DRAMTMG11_t_ckmpe_MASK (0x1FU)
8692#define DDRC_DRAMTMG11_t_ckmpe_SHIFT (0U)
8693#define DDRC_DRAMTMG11_t_ckmpe(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_ckmpe_SHIFT)) & DDRC_DRAMTMG11_t_ckmpe_MASK)
8694#define DDRC_DRAMTMG11_t_mpx_s_MASK (0x300U)
8695#define DDRC_DRAMTMG11_t_mpx_s_SHIFT (8U)
8696#define DDRC_DRAMTMG11_t_mpx_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_mpx_s_SHIFT)) & DDRC_DRAMTMG11_t_mpx_s_MASK)
8697#define DDRC_DRAMTMG11_t_mpx_lh_MASK (0x1F0000U)
8698#define DDRC_DRAMTMG11_t_mpx_lh_SHIFT (16U)
8699#define DDRC_DRAMTMG11_t_mpx_lh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_mpx_lh_SHIFT)) & DDRC_DRAMTMG11_t_mpx_lh_MASK)
8700#define DDRC_DRAMTMG11_post_mpsm_gap_x32_MASK (0x7F000000U)
8701#define DDRC_DRAMTMG11_post_mpsm_gap_x32_SHIFT (24U)
8702#define DDRC_DRAMTMG11_post_mpsm_gap_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_post_mpsm_gap_x32_SHIFT)) & DDRC_DRAMTMG11_post_mpsm_gap_x32_MASK)
8703/*! @} */
8704
8705/*! @name DRAMTMG12 - SDRAM Timing Register 12 */
8706/*! @{ */
8707#define DDRC_DRAMTMG12_t_mrd_pda_MASK (0x1FU)
8708#define DDRC_DRAMTMG12_t_mrd_pda_SHIFT (0U)
8709#define DDRC_DRAMTMG12_t_mrd_pda(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_mrd_pda_SHIFT)) & DDRC_DRAMTMG12_t_mrd_pda_MASK)
8710#define DDRC_DRAMTMG12_t_ckehcmd_MASK (0xF00U)
8711#define DDRC_DRAMTMG12_t_ckehcmd_SHIFT (8U)
8712#define DDRC_DRAMTMG12_t_ckehcmd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_ckehcmd_SHIFT)) & DDRC_DRAMTMG12_t_ckehcmd_MASK)
8713#define DDRC_DRAMTMG12_t_cmdcke_MASK (0x30000U)
8714#define DDRC_DRAMTMG12_t_cmdcke_SHIFT (16U)
8715#define DDRC_DRAMTMG12_t_cmdcke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_cmdcke_SHIFT)) & DDRC_DRAMTMG12_t_cmdcke_MASK)
8716/*! @} */
8717
8718/*! @name DRAMTMG13 - SDRAM Timing Register 13 */
8719/*! @{ */
8720#define DDRC_DRAMTMG13_t_ppd_MASK (0x7U)
8721#define DDRC_DRAMTMG13_t_ppd_SHIFT (0U)
8722#define DDRC_DRAMTMG13_t_ppd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_t_ppd_SHIFT)) & DDRC_DRAMTMG13_t_ppd_MASK)
8723#define DDRC_DRAMTMG13_t_ccd_mw_MASK (0x3F0000U)
8724#define DDRC_DRAMTMG13_t_ccd_mw_SHIFT (16U)
8725#define DDRC_DRAMTMG13_t_ccd_mw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_t_ccd_mw_SHIFT)) & DDRC_DRAMTMG13_t_ccd_mw_MASK)
8726#define DDRC_DRAMTMG13_odtloff_MASK (0x7F000000U)
8727#define DDRC_DRAMTMG13_odtloff_SHIFT (24U)
8728#define DDRC_DRAMTMG13_odtloff(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_odtloff_SHIFT)) & DDRC_DRAMTMG13_odtloff_MASK)
8729/*! @} */
8730
8731/*! @name DRAMTMG14 - SDRAM Timing Register 14 */
8732/*! @{ */
8733#define DDRC_DRAMTMG14_t_xsr_MASK (0xFFFU)
8734#define DDRC_DRAMTMG14_t_xsr_SHIFT (0U)
8735#define DDRC_DRAMTMG14_t_xsr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_t_xsr_SHIFT)) & DDRC_DRAMTMG14_t_xsr_MASK)
8736/*! @} */
8737
8738/*! @name DRAMTMG15 - SDRAM Timing Register 15 */
8739/*! @{ */
8740#define DDRC_DRAMTMG15_t_stab_x32_MASK (0xFFU)
8741#define DDRC_DRAMTMG15_t_stab_x32_SHIFT (0U)
8742#define DDRC_DRAMTMG15_t_stab_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_t_stab_x32_SHIFT)) & DDRC_DRAMTMG15_t_stab_x32_MASK)
8743#define DDRC_DRAMTMG15_en_dfi_lp_t_stab_MASK (0x80000000U)
8744#define DDRC_DRAMTMG15_en_dfi_lp_t_stab_SHIFT (31U)
8745/*! en_dfi_lp_t_stab - Enable DFI tSTAB
8746 * 0b0..Disable using tSTAB when exiting DFI LP
8747 * 0b1..Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power.
8748 */
8749#define DDRC_DRAMTMG15_en_dfi_lp_t_stab(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_en_dfi_lp_t_stab_SHIFT)) & DDRC_DRAMTMG15_en_dfi_lp_t_stab_MASK)
8750/*! @} */
8751
8752/*! @name ZQCTL0 - ZQ Control Register 0 */
8753/*! @{ */
8754#define DDRC_ZQCTL0_t_zq_short_nop_MASK (0x3FFU)
8755#define DDRC_ZQCTL0_t_zq_short_nop_SHIFT (0U)
8756#define DDRC_ZQCTL0_t_zq_short_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_t_zq_short_nop_SHIFT)) & DDRC_ZQCTL0_t_zq_short_nop_MASK)
8757#define DDRC_ZQCTL0_t_zq_long_nop_MASK (0x7FF0000U)
8758#define DDRC_ZQCTL0_t_zq_long_nop_SHIFT (16U)
8759#define DDRC_ZQCTL0_t_zq_long_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_t_zq_long_nop_SHIFT)) & DDRC_ZQCTL0_t_zq_long_nop_MASK)
8760#define DDRC_ZQCTL0_dis_mpsmx_zqcl_MASK (0x10000000U)
8761#define DDRC_ZQCTL0_dis_mpsmx_zqcl_SHIFT (28U)
8762/*! dis_mpsmx_zqcl - Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC
8763 * configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting
8764 * MPSM mode.
8765 * 0b0..Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode.
8766 * This is only present for designs supporting DDR4 devices.
8767 * 0b1..Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode.
8768 */
8769#define DDRC_ZQCTL0_dis_mpsmx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_mpsmx_zqcl_SHIFT)) & DDRC_ZQCTL0_dis_mpsmx_zqcl_MASK)
8770#define DDRC_ZQCTL0_zq_resistor_shared_MASK (0x20000000U)
8771#define DDRC_ZQCTL0_zq_resistor_shared_SHIFT (29U)
8772/*! zq_resistor_shared - ZQ resistor sharing
8773 * 0b0..ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
8774 * 0b1..Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are
8775 * sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that
8776 * commands to different ranks do not overlap.
8777 */
8778#define DDRC_ZQCTL0_zq_resistor_shared(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_zq_resistor_shared_SHIFT)) & DDRC_ZQCTL0_zq_resistor_shared_MASK)
8779#define DDRC_ZQCTL0_dis_srx_zqcl_MASK (0x40000000U)
8780#define DDRC_ZQCTL0_dis_srx_zqcl_SHIFT (30U)
8781/*! dis_srx_zqcl - Disable ZQCL/MPC
8782 * 0b0..Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable
8783 * when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting
8784 * DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
8785 * 0b1..Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable
8786 * when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode.
8787 */
8788#define DDRC_ZQCTL0_dis_srx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_srx_zqcl_SHIFT)) & DDRC_ZQCTL0_dis_srx_zqcl_MASK)
8789#define DDRC_ZQCTL0_dis_auto_zq_MASK (0x80000000U)
8790#define DDRC_ZQCTL0_dis_auto_zq_SHIFT (31U)
8791/*! dis_auto_zq - Disable Auto ZQCS/MPC
8792 * 0b0..Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024.
8793 * 0b1..Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used
8794 * instead to issue ZQ calibration request from APB module.
8795 */
8796#define DDRC_ZQCTL0_dis_auto_zq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_auto_zq_SHIFT)) & DDRC_ZQCTL0_dis_auto_zq_MASK)
8797/*! @} */
8798
8799/*! @name ZQCTL1 - ZQ Control Register 1 */
8800/*! @{ */
8801#define DDRC_ZQCTL1_t_zq_short_interval_x1024_MASK (0xFFFFFU)
8802#define DDRC_ZQCTL1_t_zq_short_interval_x1024_SHIFT (0U)
8803#define DDRC_ZQCTL1_t_zq_short_interval_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_t_zq_short_interval_x1024_SHIFT)) & DDRC_ZQCTL1_t_zq_short_interval_x1024_MASK)
8804#define DDRC_ZQCTL1_t_zq_reset_nop_MASK (0x3FF00000U)
8805#define DDRC_ZQCTL1_t_zq_reset_nop_SHIFT (20U)
8806#define DDRC_ZQCTL1_t_zq_reset_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_t_zq_reset_nop_SHIFT)) & DDRC_ZQCTL1_t_zq_reset_nop_MASK)
8807/*! @} */
8808
8809/*! @name ZQCTL2 - ZQ Control Register 2 */
8810/*! @{ */
8811#define DDRC_ZQCTL2_zq_reset_MASK (0x1U)
8812#define DDRC_ZQCTL2_zq_reset_SHIFT (0U)
8813#define DDRC_ZQCTL2_zq_reset(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL2_zq_reset_SHIFT)) & DDRC_ZQCTL2_zq_reset_MASK)
8814/*! @} */
8815
8816/*! @name ZQSTAT - ZQ Status Register */
8817/*! @{ */
8818#define DDRC_ZQSTAT_zq_reset_busy_MASK (0x1U)
8819#define DDRC_ZQSTAT_zq_reset_busy_SHIFT (0U)
8820/*! zq_reset_busy - SoC core may initiate a ZQ Reset operation only if this signal is low. This
8821 * signal goes high in the clock after the DDRC accepts the ZQ Reset request. It goes low when the ZQ
8822 * Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended
8823 * not to perform ZQ Reset commands when this signal is high.
8824 * 0b0..Indicates that the SoC core can initiate a ZQ Reset operation
8825 * 0b1..Indicates that ZQ Reset operation is in progress
8826 */
8827#define DDRC_ZQSTAT_zq_reset_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQSTAT_zq_reset_busy_SHIFT)) & DDRC_ZQSTAT_zq_reset_busy_MASK)
8828/*! @} */
8829
8830/*! @name DFITMG0 - DFI Timing Register 0 */
8831/*! @{ */
8832#define DDRC_DFITMG0_dfi_tphy_wrlat_MASK (0x3FU)
8833#define DDRC_DFITMG0_dfi_tphy_wrlat_SHIFT (0U)
8834#define DDRC_DFITMG0_dfi_tphy_wrlat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_tphy_wrlat_SHIFT)) & DDRC_DFITMG0_dfi_tphy_wrlat_MASK)
8835#define DDRC_DFITMG0_dfi_tphy_wrdata_MASK (0x3F00U)
8836#define DDRC_DFITMG0_dfi_tphy_wrdata_SHIFT (8U)
8837#define DDRC_DFITMG0_dfi_tphy_wrdata(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_tphy_wrdata_SHIFT)) & DDRC_DFITMG0_dfi_tphy_wrdata_MASK)
8838#define DDRC_DFITMG0_dfi_wrdata_use_sdr_MASK (0x8000U)
8839#define DDRC_DFITMG0_dfi_wrdata_use_sdr_SHIFT (15U)
8840#define DDRC_DFITMG0_dfi_wrdata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_wrdata_use_sdr_SHIFT)) & DDRC_DFITMG0_dfi_wrdata_use_sdr_MASK)
8841#define DDRC_DFITMG0_dfi_t_rddata_en_MASK (0x7F0000U)
8842#define DDRC_DFITMG0_dfi_t_rddata_en_SHIFT (16U)
8843#define DDRC_DFITMG0_dfi_t_rddata_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_t_rddata_en_SHIFT)) & DDRC_DFITMG0_dfi_t_rddata_en_MASK)
8844#define DDRC_DFITMG0_dfi_rddata_use_sdr_MASK (0x800000U)
8845#define DDRC_DFITMG0_dfi_rddata_use_sdr_SHIFT (23U)
8846#define DDRC_DFITMG0_dfi_rddata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_rddata_use_sdr_SHIFT)) & DDRC_DFITMG0_dfi_rddata_use_sdr_MASK)
8847#define DDRC_DFITMG0_dfi_t_ctrl_delay_MASK (0x1F000000U)
8848#define DDRC_DFITMG0_dfi_t_ctrl_delay_SHIFT (24U)
8849#define DDRC_DFITMG0_dfi_t_ctrl_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_t_ctrl_delay_SHIFT)) & DDRC_DFITMG0_dfi_t_ctrl_delay_MASK)
8850/*! @} */
8851
8852/*! @name DFITMG1 - DFI Timing Register 1 */
8853/*! @{ */
8854#define DDRC_DFITMG1_dfi_t_dram_clk_enable_MASK (0x1FU)
8855#define DDRC_DFITMG1_dfi_t_dram_clk_enable_SHIFT (0U)
8856#define DDRC_DFITMG1_dfi_t_dram_clk_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_dram_clk_enable_SHIFT)) & DDRC_DFITMG1_dfi_t_dram_clk_enable_MASK)
8857#define DDRC_DFITMG1_dfi_t_dram_clk_disable_MASK (0x1F00U)
8858#define DDRC_DFITMG1_dfi_t_dram_clk_disable_SHIFT (8U)
8859#define DDRC_DFITMG1_dfi_t_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_dram_clk_disable_SHIFT)) & DDRC_DFITMG1_dfi_t_dram_clk_disable_MASK)
8860#define DDRC_DFITMG1_dfi_t_wrdata_delay_MASK (0x1F0000U)
8861#define DDRC_DFITMG1_dfi_t_wrdata_delay_SHIFT (16U)
8862#define DDRC_DFITMG1_dfi_t_wrdata_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_wrdata_delay_SHIFT)) & DDRC_DFITMG1_dfi_t_wrdata_delay_MASK)
8863#define DDRC_DFITMG1_dfi_t_parin_lat_MASK (0x3000000U)
8864#define DDRC_DFITMG1_dfi_t_parin_lat_SHIFT (24U)
8865#define DDRC_DFITMG1_dfi_t_parin_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_parin_lat_SHIFT)) & DDRC_DFITMG1_dfi_t_parin_lat_MASK)
8866#define DDRC_DFITMG1_dfi_t_cmd_lat_MASK (0xF0000000U)
8867#define DDRC_DFITMG1_dfi_t_cmd_lat_SHIFT (28U)
8868#define DDRC_DFITMG1_dfi_t_cmd_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_cmd_lat_SHIFT)) & DDRC_DFITMG1_dfi_t_cmd_lat_MASK)
8869/*! @} */
8870
8871/*! @name DFILPCFG0 - DFI Low Power Configuration Register 0 */
8872/*! @{ */
8873#define DDRC_DFILPCFG0_dfi_lp_en_pd_MASK (0x1U)
8874#define DDRC_DFILPCFG0_dfi_lp_en_pd_SHIFT (0U)
8875#define DDRC_DFILPCFG0_dfi_lp_en_pd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_pd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_pd_MASK)
8876#define DDRC_DFILPCFG0_dfi_lp_wakeup_pd_MASK (0xF0U)
8877#define DDRC_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT (4U)
8878/*! dfi_lp_wakeup_pd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down
8879 * mode is entered. Determines the DFI's tlp_wakeup time:
8880 * 0b0000..16 cycles
8881 * 0b0001..32 cycles
8882 * 0b0010..64 cycles
8883 * 0b0011..128 cycles
8884 * 0b0100..256 cycles
8885 * 0b0101..512 cycles
8886 * 0b0110..1024 cycles
8887 * 0b0111..2048 cycles
8888 * 0b1000..4096 cycles
8889 * 0b1001..8192 cycles
8890 * 0b1010..16384 cycles
8891 * 0b1011..32768 cycles
8892 * 0b1100..65536 cycles
8893 * 0b1101..131072 cycles
8894 * 0b1110..262144 cycles
8895 * 0b1111..Unlimited cycles
8896 */
8897#define DDRC_DFILPCFG0_dfi_lp_wakeup_pd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_pd_MASK)
8898#define DDRC_DFILPCFG0_dfi_lp_en_sr_MASK (0x100U)
8899#define DDRC_DFILPCFG0_dfi_lp_en_sr_SHIFT (8U)
8900/*! dfi_lp_en_sr - Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled
8901 * 0b0..Disabled
8902 * 0b1..Enabled
8903 */
8904#define DDRC_DFILPCFG0_dfi_lp_en_sr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_sr_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_sr_MASK)
8905#define DDRC_DFILPCFG0_dfi_lp_wakeup_sr_MASK (0xF000U)
8906#define DDRC_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT (12U)
8907/*! dfi_lp_wakeup_sr - Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh
8908 * mode is entered. Determines the DFI's tlp_wakeup time:
8909 * 0b0000..16 cycles
8910 * 0b0001..32 cycles
8911 * 0b0010..64 cycles
8912 * 0b0011..128 cycles
8913 * 0b0100..256 cycles
8914 * 0b0101..512 cycles
8915 * 0b0110..1024 cycles
8916 * 0b0111..2048 cycles
8917 * 0b1000..4096 cycles
8918 * 0b1001..8192 cycles
8919 * 0b1010..16384 cycles
8920 * 0b1011..32768 cycles
8921 * 0b1100..65536 cycles
8922 * 0b1101..131072 cycles
8923 * 0b1110..262144 cycles
8924 * 0b1111..Unlimited cycles
8925 */
8926#define DDRC_DFILPCFG0_dfi_lp_wakeup_sr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_sr_MASK)
8927#define DDRC_DFILPCFG0_dfi_lp_en_dpd_MASK (0x10000U)
8928#define DDRC_DFILPCFG0_dfi_lp_en_dpd_SHIFT (16U)
8929#define DDRC_DFILPCFG0_dfi_lp_en_dpd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_dpd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_dpd_MASK)
8930#define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_MASK (0xF00000U)
8931#define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT (20U)
8932/*! dfi_lp_wakeup_dpd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power
8933 * Down mode is entered. Determines the DFI's tlp_wakeup time: This is only present for designs
8934 * supporting mDDR or LPDDR2/LPDDR3 devices.
8935 * 0b0000..16 cycles
8936 * 0b0001..32 cycles
8937 * 0b0010..64 cycles
8938 * 0b0011..128 cycles
8939 * 0b0100..256 cycles
8940 * 0b0101..512 cycles
8941 * 0b0110..1024 cycles
8942 * 0b0111..2048 cycles
8943 * 0b1000..4096 cycles
8944 * 0b1001..8192 cycles
8945 * 0b1010..16384 cycles
8946 * 0b1011..32768 cycles
8947 * 0b1100..65536 cycles
8948 * 0b1101..131072 cycles
8949 * 0b1110..262144 cycles
8950 * 0b1111..Unlimited cycles
8951 */
8952#define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_MASK)
8953#define DDRC_DFILPCFG0_dfi_tlp_resp_MASK (0x1F000000U)
8954#define DDRC_DFILPCFG0_dfi_tlp_resp_SHIFT (24U)
8955#define DDRC_DFILPCFG0_dfi_tlp_resp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_tlp_resp_SHIFT)) & DDRC_DFILPCFG0_dfi_tlp_resp_MASK)
8956/*! @} */
8957
8958/*! @name DFILPCFG1 - DFI Low Power Configuration Register 1 */
8959/*! @{ */
8960#define DDRC_DFILPCFG1_dfi_lp_en_mpsm_MASK (0x1U)
8961#define DDRC_DFILPCFG1_dfi_lp_en_mpsm_SHIFT (0U)
8962#define DDRC_DFILPCFG1_dfi_lp_en_mpsm(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_dfi_lp_en_mpsm_SHIFT)) & DDRC_DFILPCFG1_dfi_lp_en_mpsm_MASK)
8963#define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK (0xF0U)
8964#define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT (4U)
8965/*! dfi_lp_wakeup_mpsm - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum
8966 * Power Saving Mode is entered. Determines the DFI's tlp_wakeup time:
8967 * 0b0000..16 cycles
8968 * 0b0001..32 cycles
8969 * 0b0010..64 cycles
8970 * 0b0011..128 cycles
8971 * 0b0100..256 cycles
8972 * 0b0101..512 cycles
8973 * 0b0110..1024 cycles
8974 * 0b0111..2048 cycles
8975 * 0b1000..4096 cycles
8976 * 0b1001..8192 cycles
8977 * 0b1010..16384 cycles
8978 * 0b1011..32768 cycles
8979 * 0b1100..65536 cycles
8980 * 0b1101..131072 cycles
8981 * 0b1110..262144 cycles
8982 * 0b1111..Unlimited cycles
8983 */
8984#define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT)) & DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK)
8985/*! @} */
8986
8987/*! @name DFIUPD0 - DFI Update Register 0 */
8988/*! @{ */
8989#define DDRC_DFIUPD0_dfi_t_ctrlup_min_MASK (0x3FFU)
8990#define DDRC_DFIUPD0_dfi_t_ctrlup_min_SHIFT (0U)
8991#define DDRC_DFIUPD0_dfi_t_ctrlup_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dfi_t_ctrlup_min_SHIFT)) & DDRC_DFIUPD0_dfi_t_ctrlup_min_MASK)
8992#define DDRC_DFIUPD0_dfi_t_ctrlup_max_MASK (0x3FF0000U)
8993#define DDRC_DFIUPD0_dfi_t_ctrlup_max_SHIFT (16U)
8994#define DDRC_DFIUPD0_dfi_t_ctrlup_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dfi_t_ctrlup_max_SHIFT)) & DDRC_DFIUPD0_dfi_t_ctrlup_max_MASK)
8995#define DDRC_DFIUPD0_ctrlupd_pre_srx_MASK (0x20000000U)
8996#define DDRC_DFIUPD0_ctrlupd_pre_srx_SHIFT (29U)
8997/*! ctrlupd_pre_srx - Selects dfi_ctrlupd_req requirements at SRX: - 0 : send ctrlupd after SRX - 1
8998 * : send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact,
8999 * because no dfi_ctrlupd_req will be issued when SRX.
9000 * 0b0..send ctrlupd after SRX
9001 * 0b1..send ctrlupd before SRX
9002 */
9003#define DDRC_DFIUPD0_ctrlupd_pre_srx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_ctrlupd_pre_srx_SHIFT)) & DDRC_DFIUPD0_ctrlupd_pre_srx_MASK)
9004#define DDRC_DFIUPD0_dis_auto_ctrlupd_srx_MASK (0x40000000U)
9005#define DDRC_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT (30U)
9006/*! dis_auto_ctrlupd_srx - Auto ctrlupd request generation
9007 * 0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC at self-refresh exit.
9008 * 0b0..DDRC issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on DFIUPD0.ctrlupd_pre_srx.
9009 */
9010#define DDRC_DFIUPD0_dis_auto_ctrlupd_srx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT)) & DDRC_DFIUPD0_dis_auto_ctrlupd_srx_MASK)
9011#define DDRC_DFIUPD0_dis_auto_ctrlupd_MASK (0x80000000U)
9012#define DDRC_DFIUPD0_dis_auto_ctrlupd_SHIFT (31U)
9013/*! dis_auto_ctrlupd - automatic dfi_ctrlupd_req generation by the DDRC
9014 * 0b0..DDRC issues dfi_ctrlupd_req periodically.
9015 * 0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC. The core must issue the dfi_ctrlupd_req
9016 * signal using register reg_ddrc_ctrlupd.
9017 */
9018#define DDRC_DFIUPD0_dis_auto_ctrlupd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dis_auto_ctrlupd_SHIFT)) & DDRC_DFIUPD0_dis_auto_ctrlupd_MASK)
9019/*! @} */
9020
9021/*! @name DFIUPD1 - DFI Update Register 1 */
9022/*! @{ */
9023#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK (0xFFU)
9024#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT (0U)
9025#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT)) & DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK)
9026#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK (0xFF0000U)
9027#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT (16U)
9028#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT)) & DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK)
9029/*! @} */
9030
9031/*! @name DFIUPD2 - DFI Update Register 2 */
9032/*! @{ */
9033#define DDRC_DFIUPD2_dfi_phyupd_en_MASK (0x80000000U)
9034#define DDRC_DFIUPD2_dfi_phyupd_en_SHIFT (31U)
9035/*! dfi_phyupd_en - Enables the support for acknowledging PHY-initiated updates:
9036 * 0b0..Disabled
9037 * 0b1..Enabled
9038 */
9039#define DDRC_DFIUPD2_dfi_phyupd_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD2_dfi_phyupd_en_SHIFT)) & DDRC_DFIUPD2_dfi_phyupd_en_MASK)
9040/*! @} */
9041
9042/*! @name DFIMISC - DFI Miscellaneous Control Register */
9043/*! @{ */
9044#define DDRC_DFIMISC_dfi_init_complete_en_MASK (0x1U)
9045#define DDRC_DFIMISC_dfi_init_complete_en_SHIFT (0U)
9046#define DDRC_DFIMISC_dfi_init_complete_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_init_complete_en_SHIFT)) & DDRC_DFIMISC_dfi_init_complete_en_MASK)
9047#define DDRC_DFIMISC_phy_dbi_mode_MASK (0x2U)
9048#define DDRC_DFIMISC_phy_dbi_mode_SHIFT (1U)
9049/*! phy_dbi_mode - DBI implemented in DDRC or PHY. Present only in designs configured to support DDR4 and LPDDR4.
9050 * 0b0..DDRC implements DBI functionality.
9051 * 0b1..PHY implements DBI functionality.
9052 */
9053#define DDRC_DFIMISC_phy_dbi_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_phy_dbi_mode_SHIFT)) & DDRC_DFIMISC_phy_dbi_mode_MASK)
9054#define DDRC_DFIMISC_dfi_data_cs_polarity_MASK (0x4U)
9055#define DDRC_DFIMISC_dfi_data_cs_polarity_SHIFT (2U)
9056/*! dfi_data_cs_polarity - Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals.
9057 * 0b0..Signals are active low
9058 * 0b1..Signals are active high
9059 */
9060#define DDRC_DFIMISC_dfi_data_cs_polarity(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_data_cs_polarity_SHIFT)) & DDRC_DFIMISC_dfi_data_cs_polarity_MASK)
9061#define DDRC_DFIMISC_ctl_idle_en_MASK (0x10U)
9062#define DDRC_DFIMISC_ctl_idle_en_SHIFT (4U)
9063#define DDRC_DFIMISC_ctl_idle_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_ctl_idle_en_SHIFT)) & DDRC_DFIMISC_ctl_idle_en_MASK)
9064#define DDRC_DFIMISC_dfi_init_start_MASK (0x20U)
9065#define DDRC_DFIMISC_dfi_init_start_SHIFT (5U)
9066#define DDRC_DFIMISC_dfi_init_start(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_init_start_SHIFT)) & DDRC_DFIMISC_dfi_init_start_MASK)
9067#define DDRC_DFIMISC_dfi_frequency_MASK (0x1F00U)
9068#define DDRC_DFIMISC_dfi_frequency_SHIFT (8U)
9069#define DDRC_DFIMISC_dfi_frequency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_frequency_SHIFT)) & DDRC_DFIMISC_dfi_frequency_MASK)
9070/*! @} */
9071
9072/*! @name DFITMG2 - DFI Timing Register 2 */
9073/*! @{ */
9074#define DDRC_DFITMG2_dfi_tphy_wrcslat_MASK (0x3FU)
9075#define DDRC_DFITMG2_dfi_tphy_wrcslat_SHIFT (0U)
9076#define DDRC_DFITMG2_dfi_tphy_wrcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_dfi_tphy_wrcslat_SHIFT)) & DDRC_DFITMG2_dfi_tphy_wrcslat_MASK)
9077#define DDRC_DFITMG2_dfi_tphy_rdcslat_MASK (0x7F00U)
9078#define DDRC_DFITMG2_dfi_tphy_rdcslat_SHIFT (8U)
9079#define DDRC_DFITMG2_dfi_tphy_rdcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_dfi_tphy_rdcslat_SHIFT)) & DDRC_DFITMG2_dfi_tphy_rdcslat_MASK)
9080/*! @} */
9081
9082/*! @name DFITMG3 - DFI Timing Register 3 */
9083/*! @{ */
9084#define DDRC_DFITMG3_dfi_t_geardown_delay_MASK (0x1FU)
9085#define DDRC_DFITMG3_dfi_t_geardown_delay_SHIFT (0U)
9086#define DDRC_DFITMG3_dfi_t_geardown_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_dfi_t_geardown_delay_SHIFT)) & DDRC_DFITMG3_dfi_t_geardown_delay_MASK)
9087/*! @} */
9088
9089/*! @name DFISTAT - DFI Status Register */
9090/*! @{ */
9091#define DDRC_DFISTAT_dfi_init_complete_MASK (0x1U)
9092#define DDRC_DFISTAT_dfi_init_complete_SHIFT (0U)
9093#define DDRC_DFISTAT_dfi_init_complete(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_dfi_init_complete_SHIFT)) & DDRC_DFISTAT_dfi_init_complete_MASK)
9094#define DDRC_DFISTAT_dfi_lp_ack_MASK (0x2U)
9095#define DDRC_DFISTAT_dfi_lp_ack_SHIFT (1U)
9096#define DDRC_DFISTAT_dfi_lp_ack(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_dfi_lp_ack_SHIFT)) & DDRC_DFISTAT_dfi_lp_ack_MASK)
9097/*! @} */
9098
9099/*! @name DBICTL - DM/DBI Control Register */
9100/*! @{ */
9101#define DDRC_DBICTL_dm_en_MASK (0x1U)
9102#define DDRC_DBICTL_dm_en_SHIFT (0U)
9103/*! dm_en - DM enable signal in DDRC. This signal must be set the same logical value as DRAM's mode
9104 * register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal
9105 * must be set to 0. - LPDDR4: Set this to inverted value of MR13[5] which is opposite polarity
9106 * from this signal
9107 * 0b0..DM is disabled
9108 * 0b1..DM is enabled
9109 */
9110#define DDRC_DBICTL_dm_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_dm_en_SHIFT)) & DDRC_DBICTL_dm_en_MASK)
9111#define DDRC_DBICTL_wr_dbi_en_MASK (0x2U)
9112#define DDRC_DBICTL_wr_dbi_en_SHIFT (1U)
9113/*! wr_dbi_en - This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A11.
9114 * When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]
9115 * 0b0..Write DBI is disabled
9116 * 0b1..Write DBI is enabled.
9117 */
9118#define DDRC_DBICTL_wr_dbi_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_wr_dbi_en_SHIFT)) & DDRC_DBICTL_wr_dbi_en_MASK)
9119#define DDRC_DBICTL_rd_dbi_en_MASK (0x4U)
9120#define DDRC_DBICTL_rd_dbi_en_SHIFT (2U)
9121#define DDRC_DBICTL_rd_dbi_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_rd_dbi_en_SHIFT)) & DDRC_DBICTL_rd_dbi_en_MASK)
9122/*! @} */
9123
9124/*! @name ADDRMAP0 - Address Map Register 0 */
9125/*! @{ */
9126#define DDRC_ADDRMAP0_addrmap_cs_bit0_MASK (0x1FU)
9127#define DDRC_ADDRMAP0_addrmap_cs_bit0_SHIFT (0U)
9128#define DDRC_ADDRMAP0_addrmap_cs_bit0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP0_addrmap_cs_bit0_SHIFT)) & DDRC_ADDRMAP0_addrmap_cs_bit0_MASK)
9129/*! @} */
9130
9131/*! @name ADDRMAP1 - Address Map Register 1 */
9132/*! @{ */
9133#define DDRC_ADDRMAP1_addrmap_bank_b0_MASK (0x1FU)
9134#define DDRC_ADDRMAP1_addrmap_bank_b0_SHIFT (0U)
9135#define DDRC_ADDRMAP1_addrmap_bank_b0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b0_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b0_MASK)
9136#define DDRC_ADDRMAP1_addrmap_bank_b1_MASK (0x1F00U)
9137#define DDRC_ADDRMAP1_addrmap_bank_b1_SHIFT (8U)
9138#define DDRC_ADDRMAP1_addrmap_bank_b1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b1_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b1_MASK)
9139#define DDRC_ADDRMAP1_addrmap_bank_b2_MASK (0x1F0000U)
9140#define DDRC_ADDRMAP1_addrmap_bank_b2_SHIFT (16U)
9141#define DDRC_ADDRMAP1_addrmap_bank_b2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b2_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b2_MASK)
9142/*! @} */
9143
9144/*! @name ADDRMAP2 - Address Map Register 2 */
9145/*! @{ */
9146#define DDRC_ADDRMAP2_addrmap_col_b2_MASK (0xFU)
9147#define DDRC_ADDRMAP2_addrmap_col_b2_SHIFT (0U)
9148#define DDRC_ADDRMAP2_addrmap_col_b2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b2_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b2_MASK)
9149#define DDRC_ADDRMAP2_addrmap_col_b3_MASK (0xF00U)
9150#define DDRC_ADDRMAP2_addrmap_col_b3_SHIFT (8U)
9151#define DDRC_ADDRMAP2_addrmap_col_b3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b3_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b3_MASK)
9152#define DDRC_ADDRMAP2_addrmap_col_b4_MASK (0xF0000U)
9153#define DDRC_ADDRMAP2_addrmap_col_b4_SHIFT (16U)
9154#define DDRC_ADDRMAP2_addrmap_col_b4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b4_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b4_MASK)
9155#define DDRC_ADDRMAP2_addrmap_col_b5_MASK (0xF000000U)
9156#define DDRC_ADDRMAP2_addrmap_col_b5_SHIFT (24U)
9157#define DDRC_ADDRMAP2_addrmap_col_b5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b5_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b5_MASK)
9158/*! @} */
9159
9160/*! @name ADDRMAP3 - Address Map Register 3 */
9161/*! @{ */
9162#define DDRC_ADDRMAP3_addrmap_col_b6_MASK (0xFU)
9163#define DDRC_ADDRMAP3_addrmap_col_b6_SHIFT (0U)
9164#define DDRC_ADDRMAP3_addrmap_col_b6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b6_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b6_MASK)
9165#define DDRC_ADDRMAP3_addrmap_col_b7_MASK (0xF00U)
9166#define DDRC_ADDRMAP3_addrmap_col_b7_SHIFT (8U)
9167#define DDRC_ADDRMAP3_addrmap_col_b7(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b7_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b7_MASK)
9168#define DDRC_ADDRMAP3_addrmap_col_b8_MASK (0xF0000U)
9169#define DDRC_ADDRMAP3_addrmap_col_b8_SHIFT (16U)
9170#define DDRC_ADDRMAP3_addrmap_col_b8(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b8_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b8_MASK)
9171#define DDRC_ADDRMAP3_addrmap_col_b9_MASK (0xF000000U)
9172#define DDRC_ADDRMAP3_addrmap_col_b9_SHIFT (24U)
9173#define DDRC_ADDRMAP3_addrmap_col_b9(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b9_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b9_MASK)
9174/*! @} */
9175
9176/*! @name ADDRMAP4 - Address Map Register 4 */
9177/*! @{ */
9178#define DDRC_ADDRMAP4_addrmap_col_b10_MASK (0xFU)
9179#define DDRC_ADDRMAP4_addrmap_col_b10_SHIFT (0U)
9180#define DDRC_ADDRMAP4_addrmap_col_b10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_addrmap_col_b10_SHIFT)) & DDRC_ADDRMAP4_addrmap_col_b10_MASK)
9181#define DDRC_ADDRMAP4_addrmap_col_b11_MASK (0xF00U)
9182#define DDRC_ADDRMAP4_addrmap_col_b11_SHIFT (8U)
9183#define DDRC_ADDRMAP4_addrmap_col_b11(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_addrmap_col_b11_SHIFT)) & DDRC_ADDRMAP4_addrmap_col_b11_MASK)
9184/*! @} */
9185
9186/*! @name ADDRMAP5 - Address Map Register 5 */
9187/*! @{ */
9188#define DDRC_ADDRMAP5_addrmap_row_b0_MASK (0xFU)
9189#define DDRC_ADDRMAP5_addrmap_row_b0_SHIFT (0U)
9190#define DDRC_ADDRMAP5_addrmap_row_b0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b0_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b0_MASK)
9191#define DDRC_ADDRMAP5_addrmap_row_b1_MASK (0xF00U)
9192#define DDRC_ADDRMAP5_addrmap_row_b1_SHIFT (8U)
9193#define DDRC_ADDRMAP5_addrmap_row_b1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b1_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b1_MASK)
9194#define DDRC_ADDRMAP5_addrmap_row_b2_10_MASK (0xF0000U)
9195#define DDRC_ADDRMAP5_addrmap_row_b2_10_SHIFT (16U)
9196#define DDRC_ADDRMAP5_addrmap_row_b2_10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b2_10_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b2_10_MASK)
9197#define DDRC_ADDRMAP5_addrmap_row_b11_MASK (0xF000000U)
9198#define DDRC_ADDRMAP5_addrmap_row_b11_SHIFT (24U)
9199#define DDRC_ADDRMAP5_addrmap_row_b11(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b11_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b11_MASK)
9200/*! @} */
9201
9202/*! @name ADDRMAP6 - Address Map Register 6 */
9203/*! @{ */
9204#define DDRC_ADDRMAP6_addrmap_row_b12_MASK (0xFU)
9205#define DDRC_ADDRMAP6_addrmap_row_b12_SHIFT (0U)
9206#define DDRC_ADDRMAP6_addrmap_row_b12(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b12_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b12_MASK)
9207#define DDRC_ADDRMAP6_addrmap_row_b13_MASK (0xF00U)
9208#define DDRC_ADDRMAP6_addrmap_row_b13_SHIFT (8U)
9209#define DDRC_ADDRMAP6_addrmap_row_b13(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b13_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b13_MASK)
9210#define DDRC_ADDRMAP6_addrmap_row_b14_MASK (0xF0000U)
9211#define DDRC_ADDRMAP6_addrmap_row_b14_SHIFT (16U)
9212#define DDRC_ADDRMAP6_addrmap_row_b14(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b14_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b14_MASK)
9213#define DDRC_ADDRMAP6_addrmap_row_b15_MASK (0xF000000U)
9214#define DDRC_ADDRMAP6_addrmap_row_b15_SHIFT (24U)
9215#define DDRC_ADDRMAP6_addrmap_row_b15(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b15_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b15_MASK)
9216#define DDRC_ADDRMAP6_lpddr3_6gb_12gb_MASK (0x80000000U)
9217#define DDRC_ADDRMAP6_lpddr3_6gb_12gb_SHIFT (31U)
9218#define DDRC_ADDRMAP6_lpddr3_6gb_12gb(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_lpddr3_6gb_12gb_SHIFT)) & DDRC_ADDRMAP6_lpddr3_6gb_12gb_MASK)
9219/*! @} */
9220
9221/*! @name ADDRMAP7 - Address Map Register 7 */
9222/*! @{ */
9223#define DDRC_ADDRMAP7_addrmap_row_b16_MASK (0xFU)
9224#define DDRC_ADDRMAP7_addrmap_row_b16_SHIFT (0U)
9225#define DDRC_ADDRMAP7_addrmap_row_b16(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_addrmap_row_b16_SHIFT)) & DDRC_ADDRMAP7_addrmap_row_b16_MASK)
9226#define DDRC_ADDRMAP7_addrmap_row_b17_MASK (0xF00U)
9227#define DDRC_ADDRMAP7_addrmap_row_b17_SHIFT (8U)
9228#define DDRC_ADDRMAP7_addrmap_row_b17(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_addrmap_row_b17_SHIFT)) & DDRC_ADDRMAP7_addrmap_row_b17_MASK)
9229/*! @} */
9230
9231/*! @name ADDRMAP8 - Address Map Register 8 */
9232/*! @{ */
9233#define DDRC_ADDRMAP8_addrmap_bg_b0_MASK (0x1FU)
9234#define DDRC_ADDRMAP8_addrmap_bg_b0_SHIFT (0U)
9235#define DDRC_ADDRMAP8_addrmap_bg_b0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_addrmap_bg_b0_SHIFT)) & DDRC_ADDRMAP8_addrmap_bg_b0_MASK)
9236#define DDRC_ADDRMAP8_addrmap_bg_b1_MASK (0x3F00U)
9237#define DDRC_ADDRMAP8_addrmap_bg_b1_SHIFT (8U)
9238#define DDRC_ADDRMAP8_addrmap_bg_b1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_addrmap_bg_b1_SHIFT)) & DDRC_ADDRMAP8_addrmap_bg_b1_MASK)
9239/*! @} */
9240
9241/*! @name ADDRMAP9 - Address Map Register 9 */
9242/*! @{ */
9243#define DDRC_ADDRMAP9_addrmap_row_b2_MASK (0xFU)
9244#define DDRC_ADDRMAP9_addrmap_row_b2_SHIFT (0U)
9245#define DDRC_ADDRMAP9_addrmap_row_b2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b2_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b2_MASK)
9246#define DDRC_ADDRMAP9_addrmap_row_b3_MASK (0xF00U)
9247#define DDRC_ADDRMAP9_addrmap_row_b3_SHIFT (8U)
9248#define DDRC_ADDRMAP9_addrmap_row_b3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b3_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b3_MASK)
9249#define DDRC_ADDRMAP9_addrmap_row_b4_MASK (0xF0000U)
9250#define DDRC_ADDRMAP9_addrmap_row_b4_SHIFT (16U)
9251#define DDRC_ADDRMAP9_addrmap_row_b4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b4_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b4_MASK)
9252#define DDRC_ADDRMAP9_addrmap_row_b5_MASK (0xF000000U)
9253#define DDRC_ADDRMAP9_addrmap_row_b5_SHIFT (24U)
9254#define DDRC_ADDRMAP9_addrmap_row_b5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b5_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b5_MASK)
9255/*! @} */
9256
9257/*! @name ADDRMAP10 - Address Map Register 10 */
9258/*! @{ */
9259#define DDRC_ADDRMAP10_addrmap_row_b6_MASK (0xFU)
9260#define DDRC_ADDRMAP10_addrmap_row_b6_SHIFT (0U)
9261#define DDRC_ADDRMAP10_addrmap_row_b6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b6_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b6_MASK)
9262#define DDRC_ADDRMAP10_addrmap_row_b7_MASK (0xF00U)
9263#define DDRC_ADDRMAP10_addrmap_row_b7_SHIFT (8U)
9264#define DDRC_ADDRMAP10_addrmap_row_b7(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b7_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b7_MASK)
9265#define DDRC_ADDRMAP10_addrmap_row_b8_MASK (0xF0000U)
9266#define DDRC_ADDRMAP10_addrmap_row_b8_SHIFT (16U)
9267#define DDRC_ADDRMAP10_addrmap_row_b8(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b8_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b8_MASK)
9268#define DDRC_ADDRMAP10_addrmap_row_b9_MASK (0xF000000U)
9269#define DDRC_ADDRMAP10_addrmap_row_b9_SHIFT (24U)
9270#define DDRC_ADDRMAP10_addrmap_row_b9(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b9_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b9_MASK)
9271/*! @} */
9272
9273/*! @name ADDRMAP11 - Address Map Register 11 */
9274/*! @{ */
9275#define DDRC_ADDRMAP11_addrmap_row_b10_MASK (0xFU)
9276#define DDRC_ADDRMAP11_addrmap_row_b10_SHIFT (0U)
9277#define DDRC_ADDRMAP11_addrmap_row_b10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP11_addrmap_row_b10_SHIFT)) & DDRC_ADDRMAP11_addrmap_row_b10_MASK)
9278/*! @} */
9279
9280/*! @name ODTCFG - ODT Configuration Register */
9281/*! @{ */
9282#define DDRC_ODTCFG_rd_odt_delay_MASK (0x7CU)
9283#define DDRC_ODTCFG_rd_odt_delay_SHIFT (2U)
9284#define DDRC_ODTCFG_rd_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_rd_odt_delay_SHIFT)) & DDRC_ODTCFG_rd_odt_delay_MASK)
9285#define DDRC_ODTCFG_rd_odt_hold_MASK (0xF00U)
9286#define DDRC_ODTCFG_rd_odt_hold_SHIFT (8U)
9287#define DDRC_ODTCFG_rd_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_rd_odt_hold_SHIFT)) & DDRC_ODTCFG_rd_odt_hold_MASK)
9288#define DDRC_ODTCFG_wr_odt_delay_MASK (0x1F0000U)
9289#define DDRC_ODTCFG_wr_odt_delay_SHIFT (16U)
9290#define DDRC_ODTCFG_wr_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_wr_odt_delay_SHIFT)) & DDRC_ODTCFG_wr_odt_delay_MASK)
9291#define DDRC_ODTCFG_wr_odt_hold_MASK (0xF000000U)
9292#define DDRC_ODTCFG_wr_odt_hold_SHIFT (24U)
9293#define DDRC_ODTCFG_wr_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_wr_odt_hold_SHIFT)) & DDRC_ODTCFG_wr_odt_hold_MASK)
9294/*! @} */
9295
9296/*! @name ODTMAP - ODT/Rank Map Register */
9297/*! @{ */
9298#define DDRC_ODTMAP_rank0_wr_odt_MASK (0x3U)
9299#define DDRC_ODTMAP_rank0_wr_odt_SHIFT (0U)
9300#define DDRC_ODTMAP_rank0_wr_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank0_wr_odt_SHIFT)) & DDRC_ODTMAP_rank0_wr_odt_MASK)
9301#define DDRC_ODTMAP_rank0_rd_odt_MASK (0x30U)
9302#define DDRC_ODTMAP_rank0_rd_odt_SHIFT (4U)
9303#define DDRC_ODTMAP_rank0_rd_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank0_rd_odt_SHIFT)) & DDRC_ODTMAP_rank0_rd_odt_MASK)
9304#define DDRC_ODTMAP_rank1_wr_odt_MASK (0x300U)
9305#define DDRC_ODTMAP_rank1_wr_odt_SHIFT (8U)
9306#define DDRC_ODTMAP_rank1_wr_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank1_wr_odt_SHIFT)) & DDRC_ODTMAP_rank1_wr_odt_MASK)
9307#define DDRC_ODTMAP_rank1_rd_odt_MASK (0x3000U)
9308#define DDRC_ODTMAP_rank1_rd_odt_SHIFT (12U)
9309#define DDRC_ODTMAP_rank1_rd_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank1_rd_odt_SHIFT)) & DDRC_ODTMAP_rank1_rd_odt_MASK)
9310/*! @} */
9311
9312/*! @name SCHED - Scheduler Control Register */
9313/*! @{ */
9314#define DDRC_SCHED_force_low_pri_n_MASK (0x1U)
9315#define DDRC_SCHED_force_low_pri_n_SHIFT (0U)
9316#define DDRC_SCHED_force_low_pri_n(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_force_low_pri_n_SHIFT)) & DDRC_SCHED_force_low_pri_n_MASK)
9317#define DDRC_SCHED_prefer_write_MASK (0x2U)
9318#define DDRC_SCHED_prefer_write_SHIFT (1U)
9319#define DDRC_SCHED_prefer_write(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_prefer_write_SHIFT)) & DDRC_SCHED_prefer_write_MASK)
9320#define DDRC_SCHED_pageclose_MASK (0x4U)
9321#define DDRC_SCHED_pageclose_SHIFT (2U)
9322#define DDRC_SCHED_pageclose(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_pageclose_SHIFT)) & DDRC_SCHED_pageclose_MASK)
9323#define DDRC_SCHED_lpr_num_entries_MASK (0x1F00U)
9324#define DDRC_SCHED_lpr_num_entries_SHIFT (8U)
9325#define DDRC_SCHED_lpr_num_entries(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_lpr_num_entries_SHIFT)) & DDRC_SCHED_lpr_num_entries_MASK)
9326#define DDRC_SCHED_go2critical_hysteresis_MASK (0xFF0000U)
9327#define DDRC_SCHED_go2critical_hysteresis_SHIFT (16U)
9328#define DDRC_SCHED_go2critical_hysteresis(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_go2critical_hysteresis_SHIFT)) & DDRC_SCHED_go2critical_hysteresis_MASK)
9329#define DDRC_SCHED_rdwr_idle_gap_MASK (0x7F000000U)
9330#define DDRC_SCHED_rdwr_idle_gap_SHIFT (24U)
9331#define DDRC_SCHED_rdwr_idle_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_rdwr_idle_gap_SHIFT)) & DDRC_SCHED_rdwr_idle_gap_MASK)
9332/*! @} */
9333
9334/*! @name SCHED1 - Scheduler Control Register 1 */
9335/*! @{ */
9336#define DDRC_SCHED1_pageclose_timer_MASK (0xFFU)
9337#define DDRC_SCHED1_pageclose_timer_SHIFT (0U)
9338#define DDRC_SCHED1_pageclose_timer(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED1_pageclose_timer_SHIFT)) & DDRC_SCHED1_pageclose_timer_MASK)
9339/*! @} */
9340
9341/*! @name PERFHPR1 - High Priority Read CAM Register 1 */
9342/*! @{ */
9343#define DDRC_PERFHPR1_hpr_max_starve_MASK (0xFFFFU)
9344#define DDRC_PERFHPR1_hpr_max_starve_SHIFT (0U)
9345#define DDRC_PERFHPR1_hpr_max_starve(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_hpr_max_starve_SHIFT)) & DDRC_PERFHPR1_hpr_max_starve_MASK)
9346#define DDRC_PERFHPR1_hpr_xact_run_length_MASK (0xFF000000U)
9347#define DDRC_PERFHPR1_hpr_xact_run_length_SHIFT (24U)
9348#define DDRC_PERFHPR1_hpr_xact_run_length(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_hpr_xact_run_length_SHIFT)) & DDRC_PERFHPR1_hpr_xact_run_length_MASK)
9349/*! @} */
9350
9351/*! @name PERFLPR1 - Low Priority Read CAM Register 1 */
9352/*! @{ */
9353#define DDRC_PERFLPR1_lpr_max_starve_MASK (0xFFFFU)
9354#define DDRC_PERFLPR1_lpr_max_starve_SHIFT (0U)
9355#define DDRC_PERFLPR1_lpr_max_starve(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_lpr_max_starve_SHIFT)) & DDRC_PERFLPR1_lpr_max_starve_MASK)
9356#define DDRC_PERFLPR1_lpr_xact_run_length_MASK (0xFF000000U)
9357#define DDRC_PERFLPR1_lpr_xact_run_length_SHIFT (24U)
9358#define DDRC_PERFLPR1_lpr_xact_run_length(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_lpr_xact_run_length_SHIFT)) & DDRC_PERFLPR1_lpr_xact_run_length_MASK)
9359/*! @} */
9360
9361/*! @name PERFWR1 - Write CAM Register 1 */
9362/*! @{ */
9363#define DDRC_PERFWR1_w_max_starve_MASK (0xFFFFU)
9364#define DDRC_PERFWR1_w_max_starve_SHIFT (0U)
9365#define DDRC_PERFWR1_w_max_starve(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_w_max_starve_SHIFT)) & DDRC_PERFWR1_w_max_starve_MASK)
9366#define DDRC_PERFWR1_w_xact_run_length_MASK (0xFF000000U)
9367#define DDRC_PERFWR1_w_xact_run_length_SHIFT (24U)
9368#define DDRC_PERFWR1_w_xact_run_length(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_w_xact_run_length_SHIFT)) & DDRC_PERFWR1_w_xact_run_length_MASK)
9369/*! @} */
9370
9371/*! @name DBG0 - Debug Register 0 */
9372/*! @{ */
9373#define DDRC_DBG0_dis_wc_MASK (0x1U)
9374#define DDRC_DBG0_dis_wc_SHIFT (0U)
9375#define DDRC_DBG0_dis_wc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_wc_SHIFT)) & DDRC_DBG0_dis_wc_MASK)
9376#define DDRC_DBG0_dis_rd_bypass_MASK (0x2U)
9377#define DDRC_DBG0_dis_rd_bypass_SHIFT (1U)
9378#define DDRC_DBG0_dis_rd_bypass(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_rd_bypass_SHIFT)) & DDRC_DBG0_dis_rd_bypass_MASK)
9379#define DDRC_DBG0_dis_act_bypass_MASK (0x4U)
9380#define DDRC_DBG0_dis_act_bypass_SHIFT (2U)
9381#define DDRC_DBG0_dis_act_bypass(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_act_bypass_SHIFT)) & DDRC_DBG0_dis_act_bypass_MASK)
9382#define DDRC_DBG0_dis_collision_page_opt_MASK (0x10U)
9383#define DDRC_DBG0_dis_collision_page_opt_SHIFT (4U)
9384#define DDRC_DBG0_dis_collision_page_opt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_collision_page_opt_SHIFT)) & DDRC_DBG0_dis_collision_page_opt_MASK)
9385/*! @} */
9386
9387/*! @name DBG1 - Debug Register 1 */
9388/*! @{ */
9389#define DDRC_DBG1_dis_dq_MASK (0x1U)
9390#define DDRC_DBG1_dis_dq_SHIFT (0U)
9391#define DDRC_DBG1_dis_dq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG1_dis_dq_SHIFT)) & DDRC_DBG1_dis_dq_MASK)
9392#define DDRC_DBG1_dis_hif_MASK (0x2U)
9393#define DDRC_DBG1_dis_hif_SHIFT (1U)
9394#define DDRC_DBG1_dis_hif(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG1_dis_hif_SHIFT)) & DDRC_DBG1_dis_hif_MASK)
9395/*! @} */
9396
9397/*! @name DBGCAM - CAM Debug Register */
9398/*! @{ */
9399#define DDRC_DBGCAM_dbg_hpr_q_depth_MASK (0x3FU)
9400#define DDRC_DBGCAM_dbg_hpr_q_depth_SHIFT (0U)
9401#define DDRC_DBGCAM_dbg_hpr_q_depth(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_hpr_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_hpr_q_depth_MASK)
9402#define DDRC_DBGCAM_dbg_lpr_q_depth_MASK (0x3F00U)
9403#define DDRC_DBGCAM_dbg_lpr_q_depth_SHIFT (8U)
9404#define DDRC_DBGCAM_dbg_lpr_q_depth(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_lpr_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_lpr_q_depth_MASK)
9405#define DDRC_DBGCAM_dbg_w_q_depth_MASK (0x3F0000U)
9406#define DDRC_DBGCAM_dbg_w_q_depth_SHIFT (16U)
9407#define DDRC_DBGCAM_dbg_w_q_depth(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_w_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_w_q_depth_MASK)
9408#define DDRC_DBGCAM_dbg_stall_MASK (0x1000000U)
9409#define DDRC_DBGCAM_dbg_stall_SHIFT (24U)
9410#define DDRC_DBGCAM_dbg_stall(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_SHIFT)) & DDRC_DBGCAM_dbg_stall_MASK)
9411#define DDRC_DBGCAM_dbg_rd_q_empty_MASK (0x2000000U)
9412#define DDRC_DBGCAM_dbg_rd_q_empty_SHIFT (25U)
9413#define DDRC_DBGCAM_dbg_rd_q_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_rd_q_empty_SHIFT)) & DDRC_DBGCAM_dbg_rd_q_empty_MASK)
9414#define DDRC_DBGCAM_dbg_wr_q_empty_MASK (0x4000000U)
9415#define DDRC_DBGCAM_dbg_wr_q_empty_SHIFT (26U)
9416#define DDRC_DBGCAM_dbg_wr_q_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_wr_q_empty_SHIFT)) & DDRC_DBGCAM_dbg_wr_q_empty_MASK)
9417#define DDRC_DBGCAM_rd_data_pipeline_empty_MASK (0x10000000U)
9418#define DDRC_DBGCAM_rd_data_pipeline_empty_SHIFT (28U)
9419#define DDRC_DBGCAM_rd_data_pipeline_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_rd_data_pipeline_empty_SHIFT)) & DDRC_DBGCAM_rd_data_pipeline_empty_MASK)
9420#define DDRC_DBGCAM_wr_data_pipeline_empty_MASK (0x20000000U)
9421#define DDRC_DBGCAM_wr_data_pipeline_empty_SHIFT (29U)
9422#define DDRC_DBGCAM_wr_data_pipeline_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_wr_data_pipeline_empty_SHIFT)) & DDRC_DBGCAM_wr_data_pipeline_empty_MASK)
9423#define DDRC_DBGCAM_dbg_stall_wr_MASK (0x40000000U)
9424#define DDRC_DBGCAM_dbg_stall_wr_SHIFT (30U)
9425#define DDRC_DBGCAM_dbg_stall_wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_wr_SHIFT)) & DDRC_DBGCAM_dbg_stall_wr_MASK)
9426#define DDRC_DBGCAM_dbg_stall_rd_MASK (0x80000000U)
9427#define DDRC_DBGCAM_dbg_stall_rd_SHIFT (31U)
9428#define DDRC_DBGCAM_dbg_stall_rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_rd_SHIFT)) & DDRC_DBGCAM_dbg_stall_rd_MASK)
9429/*! @} */
9430
9431/*! @name DBGCMD - Command Debug Register */
9432/*! @{ */
9433#define DDRC_DBGCMD_rank0_refresh_MASK (0x1U)
9434#define DDRC_DBGCMD_rank0_refresh_SHIFT (0U)
9435#define DDRC_DBGCMD_rank0_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_rank0_refresh_SHIFT)) & DDRC_DBGCMD_rank0_refresh_MASK)
9436#define DDRC_DBGCMD_rank1_refresh_MASK (0x2U)
9437#define DDRC_DBGCMD_rank1_refresh_SHIFT (1U)
9438#define DDRC_DBGCMD_rank1_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_rank1_refresh_SHIFT)) & DDRC_DBGCMD_rank1_refresh_MASK)
9439#define DDRC_DBGCMD_zq_calib_short_MASK (0x10U)
9440#define DDRC_DBGCMD_zq_calib_short_SHIFT (4U)
9441#define DDRC_DBGCMD_zq_calib_short(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_zq_calib_short_SHIFT)) & DDRC_DBGCMD_zq_calib_short_MASK)
9442#define DDRC_DBGCMD_ctrlupd_MASK (0x20U)
9443#define DDRC_DBGCMD_ctrlupd_SHIFT (5U)
9444#define DDRC_DBGCMD_ctrlupd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_ctrlupd_SHIFT)) & DDRC_DBGCMD_ctrlupd_MASK)
9445/*! @} */
9446
9447/*! @name DBGSTAT - Status Debug Register */
9448/*! @{ */
9449#define DDRC_DBGSTAT_rank0_refresh_busy_MASK (0x1U)
9450#define DDRC_DBGSTAT_rank0_refresh_busy_SHIFT (0U)
9451#define DDRC_DBGSTAT_rank0_refresh_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_rank0_refresh_busy_SHIFT)) & DDRC_DBGSTAT_rank0_refresh_busy_MASK)
9452#define DDRC_DBGSTAT_rank1_refresh_busy_MASK (0x2U)
9453#define DDRC_DBGSTAT_rank1_refresh_busy_SHIFT (1U)
9454#define DDRC_DBGSTAT_rank1_refresh_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_rank1_refresh_busy_SHIFT)) & DDRC_DBGSTAT_rank1_refresh_busy_MASK)
9455#define DDRC_DBGSTAT_zq_calib_short_busy_MASK (0x10U)
9456#define DDRC_DBGSTAT_zq_calib_short_busy_SHIFT (4U)
9457#define DDRC_DBGSTAT_zq_calib_short_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_zq_calib_short_busy_SHIFT)) & DDRC_DBGSTAT_zq_calib_short_busy_MASK)
9458#define DDRC_DBGSTAT_ctrlupd_busy_MASK (0x20U)
9459#define DDRC_DBGSTAT_ctrlupd_busy_SHIFT (5U)
9460#define DDRC_DBGSTAT_ctrlupd_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_ctrlupd_busy_SHIFT)) & DDRC_DBGSTAT_ctrlupd_busy_MASK)
9461/*! @} */
9462
9463/*! @name SWCTL - Software Register Programming Control Enable */
9464/*! @{ */
9465#define DDRC_SWCTL_sw_done_MASK (0x1U)
9466#define DDRC_SWCTL_sw_done_SHIFT (0U)
9467#define DDRC_SWCTL_sw_done(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SWCTL_sw_done_SHIFT)) & DDRC_SWCTL_sw_done_MASK)
9468/*! @} */
9469
9470/*! @name SWSTAT - Software Register Programming Control Status */
9471/*! @{ */
9472#define DDRC_SWSTAT_sw_done_ack_MASK (0x1U)
9473#define DDRC_SWSTAT_sw_done_ack_SHIFT (0U)
9474#define DDRC_SWSTAT_sw_done_ack(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SWSTAT_sw_done_ack_SHIFT)) & DDRC_SWSTAT_sw_done_ack_MASK)
9475/*! @} */
9476
9477/*! @name POISONCFG - AXI Poison Configuration Register. */
9478/*! @{ */
9479#define DDRC_POISONCFG_wr_poison_slverr_en_MASK (0x1U)
9480#define DDRC_POISONCFG_wr_poison_slverr_en_SHIFT (0U)
9481#define DDRC_POISONCFG_wr_poison_slverr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_slverr_en_SHIFT)) & DDRC_POISONCFG_wr_poison_slverr_en_MASK)
9482#define DDRC_POISONCFG_wr_poison_intr_en_MASK (0x10U)
9483#define DDRC_POISONCFG_wr_poison_intr_en_SHIFT (4U)
9484#define DDRC_POISONCFG_wr_poison_intr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_intr_en_SHIFT)) & DDRC_POISONCFG_wr_poison_intr_en_MASK)
9485#define DDRC_POISONCFG_wr_poison_intr_clr_MASK (0x100U)
9486#define DDRC_POISONCFG_wr_poison_intr_clr_SHIFT (8U)
9487#define DDRC_POISONCFG_wr_poison_intr_clr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_intr_clr_SHIFT)) & DDRC_POISONCFG_wr_poison_intr_clr_MASK)
9488#define DDRC_POISONCFG_rd_poison_slverr_en_MASK (0x10000U)
9489#define DDRC_POISONCFG_rd_poison_slverr_en_SHIFT (16U)
9490#define DDRC_POISONCFG_rd_poison_slverr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_slverr_en_SHIFT)) & DDRC_POISONCFG_rd_poison_slverr_en_MASK)
9491#define DDRC_POISONCFG_rd_poison_intr_en_MASK (0x100000U)
9492#define DDRC_POISONCFG_rd_poison_intr_en_SHIFT (20U)
9493#define DDRC_POISONCFG_rd_poison_intr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_intr_en_SHIFT)) & DDRC_POISONCFG_rd_poison_intr_en_MASK)
9494#define DDRC_POISONCFG_rd_poison_intr_clr_MASK (0x1000000U)
9495#define DDRC_POISONCFG_rd_poison_intr_clr_SHIFT (24U)
9496#define DDRC_POISONCFG_rd_poison_intr_clr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_intr_clr_SHIFT)) & DDRC_POISONCFG_rd_poison_intr_clr_MASK)
9497/*! @} */
9498
9499/*! @name POISONSTAT - AXI Poison Status Register */
9500/*! @{ */
9501#define DDRC_POISONSTAT_wr_poison_intr_0_MASK (0x1U)
9502#define DDRC_POISONSTAT_wr_poison_intr_0_SHIFT (0U)
9503#define DDRC_POISONSTAT_wr_poison_intr_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONSTAT_wr_poison_intr_0_SHIFT)) & DDRC_POISONSTAT_wr_poison_intr_0_MASK)
9504#define DDRC_POISONSTAT_rd_poison_intr_0_MASK (0x10000U)
9505#define DDRC_POISONSTAT_rd_poison_intr_0_SHIFT (16U)
9506#define DDRC_POISONSTAT_rd_poison_intr_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONSTAT_rd_poison_intr_0_SHIFT)) & DDRC_POISONSTAT_rd_poison_intr_0_MASK)
9507/*! @} */
9508
9509/*! @name PSTAT - Port Status Register */
9510/*! @{ */
9511#define DDRC_PSTAT_rd_port_busy_0_MASK (0x1U)
9512#define DDRC_PSTAT_rd_port_busy_0_SHIFT (0U)
9513#define DDRC_PSTAT_rd_port_busy_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PSTAT_rd_port_busy_0_SHIFT)) & DDRC_PSTAT_rd_port_busy_0_MASK)
9514#define DDRC_PSTAT_wr_port_busy_0_MASK (0x10000U)
9515#define DDRC_PSTAT_wr_port_busy_0_SHIFT (16U)
9516#define DDRC_PSTAT_wr_port_busy_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PSTAT_wr_port_busy_0_SHIFT)) & DDRC_PSTAT_wr_port_busy_0_MASK)
9517/*! @} */
9518
9519/*! @name PCCFG - Port Common Configuration Register */
9520/*! @{ */
9521#define DDRC_PCCFG_go2critical_en_MASK (0x1U)
9522#define DDRC_PCCFG_go2critical_en_SHIFT (0U)
9523#define DDRC_PCCFG_go2critical_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_go2critical_en_SHIFT)) & DDRC_PCCFG_go2critical_en_MASK)
9524#define DDRC_PCCFG_pagematch_limit_MASK (0x10U)
9525#define DDRC_PCCFG_pagematch_limit_SHIFT (4U)
9526#define DDRC_PCCFG_pagematch_limit(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_pagematch_limit_SHIFT)) & DDRC_PCCFG_pagematch_limit_MASK)
9527#define DDRC_PCCFG_bl_exp_mode_MASK (0x100U)
9528#define DDRC_PCCFG_bl_exp_mode_SHIFT (8U)
9529#define DDRC_PCCFG_bl_exp_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_bl_exp_mode_SHIFT)) & DDRC_PCCFG_bl_exp_mode_MASK)
9530/*! @} */
9531
9532/*! @name PCFGR_0 - Port n Configuration Read Register */
9533/*! @{ */
9534#define DDRC_PCFGR_0_rd_port_priority_MASK (0x3FFU)
9535#define DDRC_PCFGR_0_rd_port_priority_SHIFT (0U)
9536#define DDRC_PCFGR_0_rd_port_priority(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_priority_SHIFT)) & DDRC_PCFGR_0_rd_port_priority_MASK)
9537#define DDRC_PCFGR_0_rd_port_aging_en_MASK (0x1000U)
9538#define DDRC_PCFGR_0_rd_port_aging_en_SHIFT (12U)
9539#define DDRC_PCFGR_0_rd_port_aging_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_aging_en_SHIFT)) & DDRC_PCFGR_0_rd_port_aging_en_MASK)
9540#define DDRC_PCFGR_0_rd_port_urgent_en_MASK (0x2000U)
9541#define DDRC_PCFGR_0_rd_port_urgent_en_SHIFT (13U)
9542#define DDRC_PCFGR_0_rd_port_urgent_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_urgent_en_SHIFT)) & DDRC_PCFGR_0_rd_port_urgent_en_MASK)
9543#define DDRC_PCFGR_0_rd_port_pagematch_en_MASK (0x4000U)
9544#define DDRC_PCFGR_0_rd_port_pagematch_en_SHIFT (14U)
9545#define DDRC_PCFGR_0_rd_port_pagematch_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_pagematch_en_SHIFT)) & DDRC_PCFGR_0_rd_port_pagematch_en_MASK)
9546#define DDRC_PCFGR_0_rdwr_ordered_en_MASK (0x10000U)
9547#define DDRC_PCFGR_0_rdwr_ordered_en_SHIFT (16U)
9548#define DDRC_PCFGR_0_rdwr_ordered_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rdwr_ordered_en_SHIFT)) & DDRC_PCFGR_0_rdwr_ordered_en_MASK)
9549/*! @} */
9550
9551/*! @name PCFGW_0 - Port n Configuration Write Register */
9552/*! @{ */
9553#define DDRC_PCFGW_0_wr_port_priority_MASK (0x3FFU)
9554#define DDRC_PCFGW_0_wr_port_priority_SHIFT (0U)
9555#define DDRC_PCFGW_0_wr_port_priority(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_priority_SHIFT)) & DDRC_PCFGW_0_wr_port_priority_MASK)
9556#define DDRC_PCFGW_0_wr_port_aging_en_MASK (0x1000U)
9557#define DDRC_PCFGW_0_wr_port_aging_en_SHIFT (12U)
9558#define DDRC_PCFGW_0_wr_port_aging_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_aging_en_SHIFT)) & DDRC_PCFGW_0_wr_port_aging_en_MASK)
9559#define DDRC_PCFGW_0_wr_port_urgent_en_MASK (0x2000U)
9560#define DDRC_PCFGW_0_wr_port_urgent_en_SHIFT (13U)
9561#define DDRC_PCFGW_0_wr_port_urgent_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_urgent_en_SHIFT)) & DDRC_PCFGW_0_wr_port_urgent_en_MASK)
9562#define DDRC_PCFGW_0_wr_port_pagematch_en_MASK (0x4000U)
9563#define DDRC_PCFGW_0_wr_port_pagematch_en_SHIFT (14U)
9564#define DDRC_PCFGW_0_wr_port_pagematch_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_pagematch_en_SHIFT)) & DDRC_PCFGW_0_wr_port_pagematch_en_MASK)
9565/*! @} */
9566
9567/*! @name PCTRL_0 - Port n Control Register */
9568/*! @{ */
9569#define DDRC_PCTRL_0_port_en_MASK (0x1U)
9570#define DDRC_PCTRL_0_port_en_SHIFT (0U)
9571#define DDRC_PCTRL_0_port_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCTRL_0_port_en_SHIFT)) & DDRC_PCTRL_0_port_en_MASK)
9572/*! @} */
9573
9574/*! @name PCFGQOS0_0 - Port n Read QoS Configuration Register 0 */
9575/*! @{ */
9576#define DDRC_PCFGQOS0_0_rqos_map_level1_MASK (0xFU)
9577#define DDRC_PCFGQOS0_0_rqos_map_level1_SHIFT (0U)
9578#define DDRC_PCFGQOS0_0_rqos_map_level1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_level1_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_level1_MASK)
9579#define DDRC_PCFGQOS0_0_rqos_map_region0_MASK (0x30000U)
9580#define DDRC_PCFGQOS0_0_rqos_map_region0_SHIFT (16U)
9581#define DDRC_PCFGQOS0_0_rqos_map_region0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_region0_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_region0_MASK)
9582#define DDRC_PCFGQOS0_0_rqos_map_region1_MASK (0x300000U)
9583#define DDRC_PCFGQOS0_0_rqos_map_region1_SHIFT (20U)
9584#define DDRC_PCFGQOS0_0_rqos_map_region1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_region1_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_region1_MASK)
9585/*! @} */
9586
9587/*! @name PCFGQOS1_0 - Port n Read QoS Configuration Register 1 */
9588/*! @{ */
9589#define DDRC_PCFGQOS1_0_rqos_map_timeoutb_MASK (0x7FFU)
9590#define DDRC_PCFGQOS1_0_rqos_map_timeoutb_SHIFT (0U)
9591#define DDRC_PCFGQOS1_0_rqos_map_timeoutb(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS1_0_rqos_map_timeoutb_SHIFT)) & DDRC_PCFGQOS1_0_rqos_map_timeoutb_MASK)
9592#define DDRC_PCFGQOS1_0_rqos_map_timeoutr_MASK (0x7FF0000U)
9593#define DDRC_PCFGQOS1_0_rqos_map_timeoutr_SHIFT (16U)
9594#define DDRC_PCFGQOS1_0_rqos_map_timeoutr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS1_0_rqos_map_timeoutr_SHIFT)) & DDRC_PCFGQOS1_0_rqos_map_timeoutr_MASK)
9595/*! @} */
9596
9597/*! @name PCFGWQOS0_0 - Port n Write QoS Configuration Register 0 */
9598/*! @{ */
9599#define DDRC_PCFGWQOS0_0_wqos_map_level_MASK (0xFU)
9600#define DDRC_PCFGWQOS0_0_wqos_map_level_SHIFT (0U)
9601#define DDRC_PCFGWQOS0_0_wqos_map_level(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_level_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_level_MASK)
9602#define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U)
9603#define DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT (16U)
9604#define DDRC_PCFGWQOS0_0_wqos_map_region0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
9605#define DDRC_PCFGWQOS0_0_wqos_map_region1_MASK (0x300000U)
9606#define DDRC_PCFGWQOS0_0_wqos_map_region1_SHIFT (20U)
9607#define DDRC_PCFGWQOS0_0_wqos_map_region1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region1_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region1_MASK)
9608/*! @} */
9609
9610/*! @name PCFGWQOS1_0 - Port n Write QoS Configuration Register 1 */
9611/*! @{ */
9612#define DDRC_PCFGWQOS1_0_wqos_map_timeout_MASK (0x7FFU)
9613#define DDRC_PCFGWQOS1_0_wqos_map_timeout_SHIFT (0U)
9614#define DDRC_PCFGWQOS1_0_wqos_map_timeout(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS1_0_wqos_map_timeout_SHIFT)) & DDRC_PCFGWQOS1_0_wqos_map_timeout_MASK)
9615/*! @} */
9616
9617/*! @name DERATEEN_SHADOW - [SHADOW] Temperature Derate Enable Register */
9618/*! @{ */
9619#define DDRC_DERATEEN_SHADOW_derate_enable_MASK (0x1U)
9620#define DDRC_DERATEEN_SHADOW_derate_enable_SHIFT (0U)
9621#define DDRC_DERATEEN_SHADOW_derate_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_enable_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_enable_MASK)
9622#define DDRC_DERATEEN_SHADOW_derate_value_MASK (0x2U)
9623#define DDRC_DERATEEN_SHADOW_derate_value_SHIFT (1U)
9624#define DDRC_DERATEEN_SHADOW_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_value_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_value_MASK)
9625#define DDRC_DERATEEN_SHADOW_derate_byte_MASK (0xF0U)
9626#define DDRC_DERATEEN_SHADOW_derate_byte_SHIFT (4U)
9627#define DDRC_DERATEEN_SHADOW_derate_byte(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_byte_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_byte_MASK)
9628#define DDRC_DERATEEN_SHADOW_rc_derate_value_MASK (0x300U)
9629#define DDRC_DERATEEN_SHADOW_rc_derate_value_SHIFT (8U)
9630#define DDRC_DERATEEN_SHADOW_rc_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_rc_derate_value_SHIFT)) & DDRC_DERATEEN_SHADOW_rc_derate_value_MASK)
9631/*! @} */
9632
9633/*! @name DERATEINT_SHADOW - [SHADOW] Temperature Derate Interval Register */
9634/*! @{ */
9635#define DDRC_DERATEINT_SHADOW_mr4_read_interval_MASK (0xFFFFFFFFU)
9636#define DDRC_DERATEINT_SHADOW_mr4_read_interval_SHIFT (0U)
9637#define DDRC_DERATEINT_SHADOW_mr4_read_interval(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_SHADOW_mr4_read_interval_SHIFT)) & DDRC_DERATEINT_SHADOW_mr4_read_interval_MASK)
9638/*! @} */
9639
9640/*! @name RFSHCTL0_SHADOW - [SHADOW] Refresh Control Register 0 */
9641/*! @{ */
9642#define DDRC_RFSHCTL0_SHADOW_per_bank_refresh_MASK (0x4U)
9643#define DDRC_RFSHCTL0_SHADOW_per_bank_refresh_SHIFT (2U)
9644#define DDRC_RFSHCTL0_SHADOW_per_bank_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_per_bank_refresh_SHIFT)) & DDRC_RFSHCTL0_SHADOW_per_bank_refresh_MASK)
9645#define DDRC_RFSHCTL0_SHADOW_refresh_burst_MASK (0x1F0U)
9646#define DDRC_RFSHCTL0_SHADOW_refresh_burst_SHIFT (4U)
9647#define DDRC_RFSHCTL0_SHADOW_refresh_burst(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_burst_SHIFT)) & DDRC_RFSHCTL0_SHADOW_refresh_burst_MASK)
9648#define DDRC_RFSHCTL0_SHADOW_refresh_to_x32_MASK (0x1F000U)
9649#define DDRC_RFSHCTL0_SHADOW_refresh_to_x32_SHIFT (12U)
9650#define DDRC_RFSHCTL0_SHADOW_refresh_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_to_x32_SHIFT)) & DDRC_RFSHCTL0_SHADOW_refresh_to_x32_MASK)
9651#define DDRC_RFSHCTL0_SHADOW_refresh_margin_MASK (0xF00000U)
9652#define DDRC_RFSHCTL0_SHADOW_refresh_margin_SHIFT (20U)
9653#define DDRC_RFSHCTL0_SHADOW_refresh_margin(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_margin_SHIFT)) & DDRC_RFSHCTL0_SHADOW_refresh_margin_MASK)
9654/*! @} */
9655
9656/*! @name RFSHTMG_SHADOW - [SHADOW] Refresh Timing Register */
9657/*! @{ */
9658#define DDRC_RFSHTMG_SHADOW_t_rfc_min_MASK (0x3FFU)
9659#define DDRC_RFSHTMG_SHADOW_t_rfc_min_SHIFT (0U)
9660#define DDRC_RFSHTMG_SHADOW_t_rfc_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_t_rfc_min_SHIFT)) & DDRC_RFSHTMG_SHADOW_t_rfc_min_MASK)
9661#define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_MASK (0x8000U)
9662#define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_SHIFT (15U)
9663#define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_SHIFT)) & DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_MASK)
9664#define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_MASK (0xFFF0000U)
9665#define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_SHIFT (16U)
9666#define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_SHIFT)) & DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_MASK)
9667/*! @} */
9668
9669/*! @name INIT3_SHADOW - [SHADOW] SDRAM Initialization Register 3 */
9670/*! @{ */
9671#define DDRC_INIT3_SHADOW_emr_MASK (0xFFFFU)
9672#define DDRC_INIT3_SHADOW_emr_SHIFT (0U)
9673#define DDRC_INIT3_SHADOW_emr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_SHADOW_emr_SHIFT)) & DDRC_INIT3_SHADOW_emr_MASK)
9674#define DDRC_INIT3_SHADOW_mr_MASK (0xFFFF0000U)
9675#define DDRC_INIT3_SHADOW_mr_SHIFT (16U)
9676#define DDRC_INIT3_SHADOW_mr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_SHADOW_mr_SHIFT)) & DDRC_INIT3_SHADOW_mr_MASK)
9677/*! @} */
9678
9679/*! @name INIT4_SHADOW - [SHADOW] SDRAM Initialization Register 4 */
9680/*! @{ */
9681#define DDRC_INIT4_SHADOW_emr3_MASK (0xFFFFU)
9682#define DDRC_INIT4_SHADOW_emr3_SHIFT (0U)
9683#define DDRC_INIT4_SHADOW_emr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_SHADOW_emr3_SHIFT)) & DDRC_INIT4_SHADOW_emr3_MASK)
9684#define DDRC_INIT4_SHADOW_emr2_MASK (0xFFFF0000U)
9685#define DDRC_INIT4_SHADOW_emr2_SHIFT (16U)
9686#define DDRC_INIT4_SHADOW_emr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_SHADOW_emr2_SHIFT)) & DDRC_INIT4_SHADOW_emr2_MASK)
9687/*! @} */
9688
9689/*! @name INIT6_SHADOW - [SHADOW] SDRAM Initialization Register 6 */
9690/*! @{ */
9691#define DDRC_INIT6_SHADOW_mr5_MASK (0xFFFFU)
9692#define DDRC_INIT6_SHADOW_mr5_SHIFT (0U)
9693#define DDRC_INIT6_SHADOW_mr5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_SHADOW_mr5_SHIFT)) & DDRC_INIT6_SHADOW_mr5_MASK)
9694#define DDRC_INIT6_SHADOW_mr4_MASK (0xFFFF0000U)
9695#define DDRC_INIT6_SHADOW_mr4_SHIFT (16U)
9696#define DDRC_INIT6_SHADOW_mr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_SHADOW_mr4_SHIFT)) & DDRC_INIT6_SHADOW_mr4_MASK)
9697/*! @} */
9698
9699/*! @name INIT7_SHADOW - [SHADOW] SDRAM Initialization Register 7 */
9700/*! @{ */
9701#define DDRC_INIT7_SHADOW_mr6_MASK (0xFFFF0000U)
9702#define DDRC_INIT7_SHADOW_mr6_SHIFT (16U)
9703#define DDRC_INIT7_SHADOW_mr6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_SHADOW_mr6_SHIFT)) & DDRC_INIT7_SHADOW_mr6_MASK)
9704/*! @} */
9705
9706/*! @name DRAMTMG0_SHADOW - [SHADOW] SDRAM Timing Register 0 */
9707/*! @{ */
9708#define DDRC_DRAMTMG0_SHADOW_t_ras_min_MASK (0x3FU)
9709#define DDRC_DRAMTMG0_SHADOW_t_ras_min_SHIFT (0U)
9710#define DDRC_DRAMTMG0_SHADOW_t_ras_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_ras_min_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_ras_min_MASK)
9711#define DDRC_DRAMTMG0_SHADOW_t_ras_max_MASK (0x7F00U)
9712#define DDRC_DRAMTMG0_SHADOW_t_ras_max_SHIFT (8U)
9713#define DDRC_DRAMTMG0_SHADOW_t_ras_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_ras_max_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_ras_max_MASK)
9714#define DDRC_DRAMTMG0_SHADOW_t_faw_MASK (0x3F0000U)
9715#define DDRC_DRAMTMG0_SHADOW_t_faw_SHIFT (16U)
9716#define DDRC_DRAMTMG0_SHADOW_t_faw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_faw_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_faw_MASK)
9717#define DDRC_DRAMTMG0_SHADOW_wr2pre_MASK (0x7F000000U)
9718#define DDRC_DRAMTMG0_SHADOW_wr2pre_SHIFT (24U)
9719#define DDRC_DRAMTMG0_SHADOW_wr2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_wr2pre_SHIFT)) & DDRC_DRAMTMG0_SHADOW_wr2pre_MASK)
9720/*! @} */
9721
9722/*! @name DRAMTMG1_SHADOW - [SHADOW] SDRAM Timing Register 1 */
9723/*! @{ */
9724#define DDRC_DRAMTMG1_SHADOW_t_rc_MASK (0x7FU)
9725#define DDRC_DRAMTMG1_SHADOW_t_rc_SHIFT (0U)
9726#define DDRC_DRAMTMG1_SHADOW_t_rc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_t_rc_SHIFT)) & DDRC_DRAMTMG1_SHADOW_t_rc_MASK)
9727#define DDRC_DRAMTMG1_SHADOW_rd2pre_MASK (0x3F00U)
9728#define DDRC_DRAMTMG1_SHADOW_rd2pre_SHIFT (8U)
9729#define DDRC_DRAMTMG1_SHADOW_rd2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_rd2pre_SHIFT)) & DDRC_DRAMTMG1_SHADOW_rd2pre_MASK)
9730#define DDRC_DRAMTMG1_SHADOW_t_xp_MASK (0x1F0000U)
9731#define DDRC_DRAMTMG1_SHADOW_t_xp_SHIFT (16U)
9732#define DDRC_DRAMTMG1_SHADOW_t_xp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_t_xp_SHIFT)) & DDRC_DRAMTMG1_SHADOW_t_xp_MASK)
9733/*! @} */
9734
9735/*! @name DRAMTMG2_SHADOW - [SHADOW] SDRAM Timing Register 2 */
9736/*! @{ */
9737#define DDRC_DRAMTMG2_SHADOW_wr2rd_MASK (0x3FU)
9738#define DDRC_DRAMTMG2_SHADOW_wr2rd_SHIFT (0U)
9739#define DDRC_DRAMTMG2_SHADOW_wr2rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_wr2rd_SHIFT)) & DDRC_DRAMTMG2_SHADOW_wr2rd_MASK)
9740#define DDRC_DRAMTMG2_SHADOW_rd2wr_MASK (0x3F00U)
9741#define DDRC_DRAMTMG2_SHADOW_rd2wr_SHIFT (8U)
9742#define DDRC_DRAMTMG2_SHADOW_rd2wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_rd2wr_SHIFT)) & DDRC_DRAMTMG2_SHADOW_rd2wr_MASK)
9743#define DDRC_DRAMTMG2_SHADOW_read_latency_MASK (0x3F0000U)
9744#define DDRC_DRAMTMG2_SHADOW_read_latency_SHIFT (16U)
9745#define DDRC_DRAMTMG2_SHADOW_read_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_read_latency_SHIFT)) & DDRC_DRAMTMG2_SHADOW_read_latency_MASK)
9746#define DDRC_DRAMTMG2_SHADOW_write_latency_MASK (0x3F000000U)
9747#define DDRC_DRAMTMG2_SHADOW_write_latency_SHIFT (24U)
9748#define DDRC_DRAMTMG2_SHADOW_write_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_write_latency_SHIFT)) & DDRC_DRAMTMG2_SHADOW_write_latency_MASK)
9749/*! @} */
9750
9751/*! @name DRAMTMG3_SHADOW - [SHADOW] SDRAM Timing Register 3 */
9752/*! @{ */
9753#define DDRC_DRAMTMG3_SHADOW_t_mod_MASK (0x3FFU)
9754#define DDRC_DRAMTMG3_SHADOW_t_mod_SHIFT (0U)
9755#define DDRC_DRAMTMG3_SHADOW_t_mod(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mod_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mod_MASK)
9756#define DDRC_DRAMTMG3_SHADOW_t_mrd_MASK (0x3F000U)
9757#define DDRC_DRAMTMG3_SHADOW_t_mrd_SHIFT (12U)
9758#define DDRC_DRAMTMG3_SHADOW_t_mrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mrd_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mrd_MASK)
9759#define DDRC_DRAMTMG3_SHADOW_t_mrw_MASK (0x3FF00000U)
9760#define DDRC_DRAMTMG3_SHADOW_t_mrw_SHIFT (20U)
9761#define DDRC_DRAMTMG3_SHADOW_t_mrw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mrw_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mrw_MASK)
9762/*! @} */
9763
9764/*! @name DRAMTMG4_SHADOW - [SHADOW] SDRAM Timing Register 4 */
9765/*! @{ */
9766#define DDRC_DRAMTMG4_SHADOW_t_rp_MASK (0x1FU)
9767#define DDRC_DRAMTMG4_SHADOW_t_rp_SHIFT (0U)
9768#define DDRC_DRAMTMG4_SHADOW_t_rp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rp_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rp_MASK)
9769#define DDRC_DRAMTMG4_SHADOW_t_rrd_MASK (0xF00U)
9770#define DDRC_DRAMTMG4_SHADOW_t_rrd_SHIFT (8U)
9771#define DDRC_DRAMTMG4_SHADOW_t_rrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rrd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rrd_MASK)
9772#define DDRC_DRAMTMG4_SHADOW_t_ccd_MASK (0xF0000U)
9773#define DDRC_DRAMTMG4_SHADOW_t_ccd_SHIFT (16U)
9774#define DDRC_DRAMTMG4_SHADOW_t_ccd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_ccd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_ccd_MASK)
9775#define DDRC_DRAMTMG4_SHADOW_t_rcd_MASK (0x1F000000U)
9776#define DDRC_DRAMTMG4_SHADOW_t_rcd_SHIFT (24U)
9777#define DDRC_DRAMTMG4_SHADOW_t_rcd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rcd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rcd_MASK)
9778/*! @} */
9779
9780/*! @name DRAMTMG5_SHADOW - [SHADOW] SDRAM Timing Register 5 */
9781/*! @{ */
9782#define DDRC_DRAMTMG5_SHADOW_t_cke_MASK (0x1FU)
9783#define DDRC_DRAMTMG5_SHADOW_t_cke_SHIFT (0U)
9784#define DDRC_DRAMTMG5_SHADOW_t_cke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cke_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cke_MASK)
9785#define DDRC_DRAMTMG5_SHADOW_t_ckesr_MASK (0x3F00U)
9786#define DDRC_DRAMTMG5_SHADOW_t_ckesr_SHIFT (8U)
9787#define DDRC_DRAMTMG5_SHADOW_t_ckesr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_ckesr_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_ckesr_MASK)
9788#define DDRC_DRAMTMG5_SHADOW_t_cksre_MASK (0xF0000U)
9789#define DDRC_DRAMTMG5_SHADOW_t_cksre_SHIFT (16U)
9790#define DDRC_DRAMTMG5_SHADOW_t_cksre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cksre_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cksre_MASK)
9791#define DDRC_DRAMTMG5_SHADOW_t_cksrx_MASK (0xF000000U)
9792#define DDRC_DRAMTMG5_SHADOW_t_cksrx_SHIFT (24U)
9793#define DDRC_DRAMTMG5_SHADOW_t_cksrx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cksrx_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cksrx_MASK)
9794/*! @} */
9795
9796/*! @name DRAMTMG6_SHADOW - [SHADOW] SDRAM Timing Register 6 */
9797/*! @{ */
9798#define DDRC_DRAMTMG6_SHADOW_t_ckcsx_MASK (0xFU)
9799#define DDRC_DRAMTMG6_SHADOW_t_ckcsx_SHIFT (0U)
9800#define DDRC_DRAMTMG6_SHADOW_t_ckcsx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckcsx_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckcsx_MASK)
9801#define DDRC_DRAMTMG6_SHADOW_t_ckdpdx_MASK (0xF0000U)
9802#define DDRC_DRAMTMG6_SHADOW_t_ckdpdx_SHIFT (16U)
9803#define DDRC_DRAMTMG6_SHADOW_t_ckdpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckdpdx_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckdpdx_MASK)
9804#define DDRC_DRAMTMG6_SHADOW_t_ckdpde_MASK (0xF000000U)
9805#define DDRC_DRAMTMG6_SHADOW_t_ckdpde_SHIFT (24U)
9806#define DDRC_DRAMTMG6_SHADOW_t_ckdpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckdpde_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckdpde_MASK)
9807/*! @} */
9808
9809/*! @name DRAMTMG7_SHADOW - [SHADOW] SDRAM Timing Register 7 */
9810/*! @{ */
9811#define DDRC_DRAMTMG7_SHADOW_t_ckpdx_MASK (0xFU)
9812#define DDRC_DRAMTMG7_SHADOW_t_ckpdx_SHIFT (0U)
9813#define DDRC_DRAMTMG7_SHADOW_t_ckpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_SHADOW_t_ckpdx_SHIFT)) & DDRC_DRAMTMG7_SHADOW_t_ckpdx_MASK)
9814#define DDRC_DRAMTMG7_SHADOW_t_ckpde_MASK (0xF00U)
9815#define DDRC_DRAMTMG7_SHADOW_t_ckpde_SHIFT (8U)
9816#define DDRC_DRAMTMG7_SHADOW_t_ckpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_SHADOW_t_ckpde_SHIFT)) & DDRC_DRAMTMG7_SHADOW_t_ckpde_MASK)
9817/*! @} */
9818
9819/*! @name DRAMTMG8_SHADOW - [SHADOW] SDRAM Timing Register 8 */
9820/*! @{ */
9821#define DDRC_DRAMTMG8_SHADOW_t_xs_x32_MASK (0x7FU)
9822#define DDRC_DRAMTMG8_SHADOW_t_xs_x32_SHIFT (0U)
9823#define DDRC_DRAMTMG8_SHADOW_t_xs_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_x32_MASK)
9824#define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_MASK (0x7F00U)
9825#define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_SHIFT (8U)
9826#define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_MASK)
9827#define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_MASK (0x7F0000U)
9828#define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_SHIFT (16U)
9829#define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_MASK)
9830#define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_MASK (0x7F000000U)
9831#define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_SHIFT (24U)
9832#define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_MASK)
9833/*! @} */
9834
9835/*! @name DRAMTMG9_SHADOW - [SHADOW] SDRAM Timing Register 9 */
9836/*! @{ */
9837#define DDRC_DRAMTMG9_SHADOW_wr2rd_s_MASK (0x3FU)
9838#define DDRC_DRAMTMG9_SHADOW_wr2rd_s_SHIFT (0U)
9839#define DDRC_DRAMTMG9_SHADOW_wr2rd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_wr2rd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_wr2rd_s_MASK)
9840#define DDRC_DRAMTMG9_SHADOW_t_rrd_s_MASK (0xF00U)
9841#define DDRC_DRAMTMG9_SHADOW_t_rrd_s_SHIFT (8U)
9842#define DDRC_DRAMTMG9_SHADOW_t_rrd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_t_rrd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_t_rrd_s_MASK)
9843#define DDRC_DRAMTMG9_SHADOW_t_ccd_s_MASK (0x70000U)
9844#define DDRC_DRAMTMG9_SHADOW_t_ccd_s_SHIFT (16U)
9845#define DDRC_DRAMTMG9_SHADOW_t_ccd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_t_ccd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_t_ccd_s_MASK)
9846#define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_MASK (0x40000000U)
9847#define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_SHIFT (30U)
9848#define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_SHIFT)) & DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_MASK)
9849/*! @} */
9850
9851/*! @name DRAMTMG10_SHADOW - [SHADOW] SDRAM Timing Register 10 */
9852/*! @{ */
9853#define DDRC_DRAMTMG10_SHADOW_t_gear_hold_MASK (0x3U)
9854#define DDRC_DRAMTMG10_SHADOW_t_gear_hold_SHIFT (0U)
9855#define DDRC_DRAMTMG10_SHADOW_t_gear_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_gear_hold_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_gear_hold_MASK)
9856#define DDRC_DRAMTMG10_SHADOW_t_gear_setup_MASK (0xCU)
9857#define DDRC_DRAMTMG10_SHADOW_t_gear_setup_SHIFT (2U)
9858#define DDRC_DRAMTMG10_SHADOW_t_gear_setup(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_gear_setup_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_gear_setup_MASK)
9859#define DDRC_DRAMTMG10_SHADOW_t_cmd_gear_MASK (0x1F00U)
9860#define DDRC_DRAMTMG10_SHADOW_t_cmd_gear_SHIFT (8U)
9861#define DDRC_DRAMTMG10_SHADOW_t_cmd_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_cmd_gear_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_cmd_gear_MASK)
9862#define DDRC_DRAMTMG10_SHADOW_t_sync_gear_MASK (0x1F0000U)
9863#define DDRC_DRAMTMG10_SHADOW_t_sync_gear_SHIFT (16U)
9864#define DDRC_DRAMTMG10_SHADOW_t_sync_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_sync_gear_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_sync_gear_MASK)
9865/*! @} */
9866
9867/*! @name DRAMTMG11_SHADOW - [SHADOW] SDRAM Timing Register 11 */
9868/*! @{ */
9869#define DDRC_DRAMTMG11_SHADOW_t_ckmpe_MASK (0x1FU)
9870#define DDRC_DRAMTMG11_SHADOW_t_ckmpe_SHIFT (0U)
9871#define DDRC_DRAMTMG11_SHADOW_t_ckmpe(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_ckmpe_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_ckmpe_MASK)
9872#define DDRC_DRAMTMG11_SHADOW_t_mpx_s_MASK (0x300U)
9873#define DDRC_DRAMTMG11_SHADOW_t_mpx_s_SHIFT (8U)
9874#define DDRC_DRAMTMG11_SHADOW_t_mpx_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_mpx_s_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_mpx_s_MASK)
9875#define DDRC_DRAMTMG11_SHADOW_t_mpx_lh_MASK (0x1F0000U)
9876#define DDRC_DRAMTMG11_SHADOW_t_mpx_lh_SHIFT (16U)
9877#define DDRC_DRAMTMG11_SHADOW_t_mpx_lh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_mpx_lh_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_mpx_lh_MASK)
9878#define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_MASK (0x7F000000U)
9879#define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_SHIFT (24U)
9880#define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_SHIFT)) & DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_MASK)
9881/*! @} */
9882
9883/*! @name DRAMTMG12_SHADOW - [SHADOW] SDRAM Timing Register 12 */
9884/*! @{ */
9885#define DDRC_DRAMTMG12_SHADOW_t_mrd_pda_MASK (0x1FU)
9886#define DDRC_DRAMTMG12_SHADOW_t_mrd_pda_SHIFT (0U)
9887#define DDRC_DRAMTMG12_SHADOW_t_mrd_pda(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_mrd_pda_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_mrd_pda_MASK)
9888#define DDRC_DRAMTMG12_SHADOW_t_ckehcmd_MASK (0xF00U)
9889#define DDRC_DRAMTMG12_SHADOW_t_ckehcmd_SHIFT (8U)
9890#define DDRC_DRAMTMG12_SHADOW_t_ckehcmd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_ckehcmd_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_ckehcmd_MASK)
9891#define DDRC_DRAMTMG12_SHADOW_t_cmdcke_MASK (0x30000U)
9892#define DDRC_DRAMTMG12_SHADOW_t_cmdcke_SHIFT (16U)
9893#define DDRC_DRAMTMG12_SHADOW_t_cmdcke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_cmdcke_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_cmdcke_MASK)
9894/*! @} */
9895
9896/*! @name DRAMTMG13_SHADOW - [SHADOW] SDRAM Timing Register 13 */
9897/*! @{ */
9898#define DDRC_DRAMTMG13_SHADOW_t_ppd_MASK (0x7U)
9899#define DDRC_DRAMTMG13_SHADOW_t_ppd_SHIFT (0U)
9900#define DDRC_DRAMTMG13_SHADOW_t_ppd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_t_ppd_SHIFT)) & DDRC_DRAMTMG13_SHADOW_t_ppd_MASK)
9901#define DDRC_DRAMTMG13_SHADOW_t_ccd_mw_MASK (0x3F0000U)
9902#define DDRC_DRAMTMG13_SHADOW_t_ccd_mw_SHIFT (16U)
9903#define DDRC_DRAMTMG13_SHADOW_t_ccd_mw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_t_ccd_mw_SHIFT)) & DDRC_DRAMTMG13_SHADOW_t_ccd_mw_MASK)
9904#define DDRC_DRAMTMG13_SHADOW_odtloff_MASK (0x7F000000U)
9905#define DDRC_DRAMTMG13_SHADOW_odtloff_SHIFT (24U)
9906#define DDRC_DRAMTMG13_SHADOW_odtloff(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_odtloff_SHIFT)) & DDRC_DRAMTMG13_SHADOW_odtloff_MASK)
9907/*! @} */
9908
9909/*! @name DRAMTMG14_SHADOW - [SHADOW] SDRAM Timing Register 14 */
9910/*! @{ */
9911#define DDRC_DRAMTMG14_SHADOW_t_xsr_MASK (0xFFFU)
9912#define DDRC_DRAMTMG14_SHADOW_t_xsr_SHIFT (0U)
9913#define DDRC_DRAMTMG14_SHADOW_t_xsr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_SHADOW_t_xsr_SHIFT)) & DDRC_DRAMTMG14_SHADOW_t_xsr_MASK)
9914/*! @} */
9915
9916/*! @name DRAMTMG15_SHADOW - [SHADOW] SDRAM Timing Register 15 */
9917/*! @{ */
9918#define DDRC_DRAMTMG15_SHADOW_t_stab_x32_MASK (0xFFU)
9919#define DDRC_DRAMTMG15_SHADOW_t_stab_x32_SHIFT (0U)
9920#define DDRC_DRAMTMG15_SHADOW_t_stab_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_SHADOW_t_stab_x32_SHIFT)) & DDRC_DRAMTMG15_SHADOW_t_stab_x32_MASK)
9921#define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_MASK (0x80000000U)
9922#define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_SHIFT (31U)
9923#define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_SHIFT)) & DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_MASK)
9924/*! @} */
9925
9926/*! @name ZQCTL0_SHADOW - [SHADOW] ZQ Control Register 0 */
9927/*! @{ */
9928#define DDRC_ZQCTL0_SHADOW_t_zq_short_nop_MASK (0x3FFU)
9929#define DDRC_ZQCTL0_SHADOW_t_zq_short_nop_SHIFT (0U)
9930#define DDRC_ZQCTL0_SHADOW_t_zq_short_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_t_zq_short_nop_SHIFT)) & DDRC_ZQCTL0_SHADOW_t_zq_short_nop_MASK)
9931#define DDRC_ZQCTL0_SHADOW_t_zq_long_nop_MASK (0x7FF0000U)
9932#define DDRC_ZQCTL0_SHADOW_t_zq_long_nop_SHIFT (16U)
9933#define DDRC_ZQCTL0_SHADOW_t_zq_long_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_t_zq_long_nop_SHIFT)) & DDRC_ZQCTL0_SHADOW_t_zq_long_nop_MASK)
9934#define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_MASK (0x10000000U)
9935#define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_SHIFT (28U)
9936#define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_MASK)
9937#define DDRC_ZQCTL0_SHADOW_zq_resistor_shared_MASK (0x20000000U)
9938#define DDRC_ZQCTL0_SHADOW_zq_resistor_shared_SHIFT (29U)
9939#define DDRC_ZQCTL0_SHADOW_zq_resistor_shared(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_zq_resistor_shared_SHIFT)) & DDRC_ZQCTL0_SHADOW_zq_resistor_shared_MASK)
9940#define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_MASK (0x40000000U)
9941#define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_SHIFT (30U)
9942#define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_MASK)
9943#define DDRC_ZQCTL0_SHADOW_dis_auto_zq_MASK (0x80000000U)
9944#define DDRC_ZQCTL0_SHADOW_dis_auto_zq_SHIFT (31U)
9945#define DDRC_ZQCTL0_SHADOW_dis_auto_zq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_auto_zq_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_auto_zq_MASK)
9946/*! @} */
9947
9948/*! @name DFITMG0_SHADOW - [SHADOW] DFI Timing Register 0 */
9949/*! @{ */
9950#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_MASK (0x3FU)
9951#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_SHIFT (0U)
9952#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_MASK)
9953#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_MASK (0x3F00U)
9954#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_SHIFT (8U)
9955#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_MASK)
9956#define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_MASK (0x8000U)
9957#define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_SHIFT (15U)
9958#define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_MASK)
9959#define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_MASK (0x7F0000U)
9960#define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_SHIFT (16U)
9961#define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_MASK)
9962#define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_MASK (0x800000U)
9963#define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_SHIFT (23U)
9964#define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_MASK)
9965#define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_MASK (0x1F000000U)
9966#define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_SHIFT (24U)
9967#define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_MASK)
9968/*! @} */
9969
9970/*! @name DFITMG1_SHADOW - [SHADOW] DFI Timing Register 1 */
9971/*! @{ */
9972#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_MASK (0x1FU)
9973#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_SHIFT (0U)
9974#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_MASK)
9975#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_MASK (0x1F00U)
9976#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_SHIFT (8U)
9977#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_MASK)
9978#define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_MASK (0x1F0000U)
9979#define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_SHIFT (16U)
9980#define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_MASK)
9981#define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_MASK (0x3000000U)
9982#define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_SHIFT (24U)
9983#define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_MASK)
9984#define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_MASK (0xF0000000U)
9985#define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_SHIFT (28U)
9986#define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_MASK)
9987/*! @} */
9988
9989/*! @name DFITMG2_SHADOW - [SHADOW] DFI Timing Register 2 */
9990/*! @{ */
9991#define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_MASK (0x3FU)
9992#define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_SHIFT (0U)
9993#define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_SHIFT)) & DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_MASK)
9994#define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_MASK (0x7F00U)
9995#define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_SHIFT (8U)
9996#define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_SHIFT)) & DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_MASK)
9997/*! @} */
9998
9999/*! @name DFITMG3_SHADOW - [SHADOW] DFI Timing Register 3 */
10000/*! @{ */
10001#define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_MASK (0x1FU)
10002#define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_SHIFT (0U)
10003#define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_SHIFT)) & DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_MASK)
10004/*! @} */
10005
10006/*! @name ODTCFG_SHADOW - [SHADOW] ODT Configuration Register */
10007/*! @{ */
10008#define DDRC_ODTCFG_SHADOW_rd_odt_delay_MASK (0x7CU)
10009#define DDRC_ODTCFG_SHADOW_rd_odt_delay_SHIFT (2U)
10010#define DDRC_ODTCFG_SHADOW_rd_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_rd_odt_delay_SHIFT)) & DDRC_ODTCFG_SHADOW_rd_odt_delay_MASK)
10011#define DDRC_ODTCFG_SHADOW_rd_odt_hold_MASK (0xF00U)
10012#define DDRC_ODTCFG_SHADOW_rd_odt_hold_SHIFT (8U)
10013#define DDRC_ODTCFG_SHADOW_rd_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_rd_odt_hold_SHIFT)) & DDRC_ODTCFG_SHADOW_rd_odt_hold_MASK)
10014#define DDRC_ODTCFG_SHADOW_wr_odt_delay_MASK (0x1F0000U)
10015#define DDRC_ODTCFG_SHADOW_wr_odt_delay_SHIFT (16U)
10016#define DDRC_ODTCFG_SHADOW_wr_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_wr_odt_delay_SHIFT)) & DDRC_ODTCFG_SHADOW_wr_odt_delay_MASK)
10017#define DDRC_ODTCFG_SHADOW_wr_odt_hold_MASK (0xF000000U)
10018#define DDRC_ODTCFG_SHADOW_wr_odt_hold_SHIFT (24U)
10019#define DDRC_ODTCFG_SHADOW_wr_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_wr_odt_hold_SHIFT)) & DDRC_ODTCFG_SHADOW_wr_odt_hold_MASK)
10020/*! @} */
10021
10022
10023/*!
10024 * @}
10025 */ /* end of group DDRC_Register_Masks */
10026
10027
10028/* DDRC - Peripheral instance base addresses */
10029/** Peripheral DDRC base address */
10030#define DDRC_BASE (0x3D400000u)
10031/** Peripheral DDRC base pointer */
10032#define DDRC ((DDRC_Type *)DDRC_BASE)
10033/** Array initializer of DDRC peripheral base addresses */
10034#define DDRC_BASE_ADDRS { DDRC_BASE }
10035/** Array initializer of DDRC peripheral base pointers */
10036#define DDRC_BASE_PTRS { DDRC }
10037
10038/*!
10039 * @}
10040 */ /* end of group DDRC_Peripheral_Access_Layer */
10041
10042
10043/* ----------------------------------------------------------------------------
10044 -- DWC_DDRPHYA_ANIB Peripheral Access Layer
10045 ---------------------------------------------------------------------------- */
10046
10047/*!
10048 * @addtogroup DWC_DDRPHYA_ANIB_Peripheral_Access_Layer DWC_DDRPHYA_ANIB Peripheral Access Layer
10049 * @{
10050 */
10051
10052/** DWC_DDRPHYA_ANIB - Register Layout Typedef */
10053typedef struct {
10054 uint8_t RESERVED_0[52];
10055 __IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x34 */
10056 uint8_t RESERVED_1[24];
10057 __IO uint16_t AFORCEDRVCONT; /**< Force Address/Command Driven (Lanes A3-A0), offset: 0x4E */
10058 __IO uint16_t AFORCETRICONT; /**< Force Address/Command Tristate (Lanes A3-A0), offset: 0x50 */
10059 uint8_t RESERVED_2[52];
10060 __IO uint16_t ATXIMPEDANCE; /**< Address TX impedance controls, offset: 0x86 */
10061 uint8_t RESERVED_3[30];
10062 __I uint16_t ATESTPRBSERR; /**< Address Loopback PRBS Error status for an entire ACX4 block, offset: 0xA6 */
10063 uint8_t RESERVED_4[2];
10064 __IO uint16_t ATXSLEWRATE; /**< Address TX slew rate and predriver controls, offset: 0xAA */
10065 __I uint16_t ATESTPRBSERRCNT; /**< Address Loopback Test Result register, offset: 0xAC */
10066 uint8_t RESERVED_5[82];
10067 __IO uint16_t ATXDLY_P0; /**< Address/Command Delay, per pstate., offset: 0x100 */
10068 uint8_t RESERVED_6[2097150];
10069 __IO uint16_t ATXDLY_P1; /**< Address/Command Delay, per pstate., offset: 0x200100 */
10070 uint8_t RESERVED_7[2097150];
10071 __IO uint16_t ATXDLY_P2; /**< Address/Command Delay, per pstate., offset: 0x400100 */
10072 uint8_t RESERVED_8[2097150];
10073 __IO uint16_t ATXDLY_P3; /**< Address/Command Delay, per pstate., offset: 0x600100 */
10074} DWC_DDRPHYA_ANIB_Type;
10075
10076/* ----------------------------------------------------------------------------
10077 -- DWC_DDRPHYA_ANIB Register Masks
10078 ---------------------------------------------------------------------------- */
10079
10080/*!
10081 * @addtogroup DWC_DDRPHYA_ANIB_Register_Masks DWC_DDRPHYA_ANIB Register Masks
10082 * @{
10083 */
10084
10085/*! @name MTESTMUXSEL - Digital Observation Pin control */
10086/*! @{ */
10087#define DWC_DDRPHYA_ANIB_MTESTMUXSEL_MtestMuxSel_MASK (0x3FU)
10088#define DWC_DDRPHYA_ANIB_MTESTMUXSEL_MtestMuxSel_SHIFT (0U)
10089#define DWC_DDRPHYA_ANIB_MTESTMUXSEL_MtestMuxSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_MTESTMUXSEL_MtestMuxSel_SHIFT)) & DWC_DDRPHYA_ANIB_MTESTMUXSEL_MtestMuxSel_MASK)
10090/*! @} */
10091
10092/*! @name AFORCEDRVCONT - Force Address/Command Driven (Lanes A3-A0) */
10093/*! @{ */
10094#define DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AForceDrvCont_MASK (0xFU)
10095#define DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AForceDrvCont_SHIFT (0U)
10096#define DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AForceDrvCont(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AForceDrvCont_SHIFT)) & DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AForceDrvCont_MASK)
10097/*! @} */
10098
10099/*! @name AFORCETRICONT - Force Address/Command Tristate (Lanes A3-A0) */
10100/*! @{ */
10101#define DWC_DDRPHYA_ANIB_AFORCETRICONT_AForceTriCont_MASK (0xFU)
10102#define DWC_DDRPHYA_ANIB_AFORCETRICONT_AForceTriCont_SHIFT (0U)
10103#define DWC_DDRPHYA_ANIB_AFORCETRICONT_AForceTriCont(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_AFORCETRICONT_AForceTriCont_SHIFT)) & DWC_DDRPHYA_ANIB_AFORCETRICONT_AForceTriCont_MASK)
10104/*! @} */
10105
10106/*! @name ATXIMPEDANCE - Address TX impedance controls */
10107/*! @{ */
10108#define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenP_MASK (0x1FU)
10109#define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenP_SHIFT (0U)
10110#define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenP_SHIFT)) & DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenP_MASK)
10111#define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenN_MASK (0x3E0U)
10112#define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenN_SHIFT (5U)
10113#define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenN_SHIFT)) & DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenN_MASK)
10114/*! @} */
10115
10116/*! @name ATESTPRBSERR - Address Loopback PRBS Error status for an entire ACX4 block */
10117/*! @{ */
10118#define DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATestPrbsErr_MASK (0xFU)
10119#define DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATestPrbsErr_SHIFT (0U)
10120#define DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATestPrbsErr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATestPrbsErr_SHIFT)) & DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATestPrbsErr_MASK)
10121/*! @} */
10122
10123/*! @name ATXSLEWRATE - Address TX slew rate and predriver controls */
10124/*! @{ */
10125#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreP_MASK (0xFU)
10126#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreP_SHIFT (0U)
10127#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreP_SHIFT)) & DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreP_MASK)
10128#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreN_MASK (0xF0U)
10129#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreN_SHIFT (4U)
10130#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreN_SHIFT)) & DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreN_MASK)
10131#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreDrvMode_MASK (0x700U)
10132#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreDrvMode_SHIFT (8U)
10133#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreDrvMode_SHIFT)) & DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreDrvMode_MASK)
10134/*! @} */
10135
10136/*! @name ATESTPRBSERRCNT - Address Loopback Test Result register */
10137/*! @{ */
10138#define DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATestPrbsErrCnt_MASK (0xFFFFU)
10139#define DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATestPrbsErrCnt_SHIFT (0U)
10140#define DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATestPrbsErrCnt(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATestPrbsErrCnt_SHIFT)) & DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATestPrbsErrCnt_MASK)
10141/*! @} */
10142
10143/*! @name ATXDLY_P0 - Address/Command Delay, per pstate. */
10144/*! @{ */
10145#define DWC_DDRPHYA_ANIB_ATXDLY_P0_ATxDly_p0_MASK (0x7FU)
10146#define DWC_DDRPHYA_ANIB_ATXDLY_P0_ATxDly_p0_SHIFT (0U)
10147#define DWC_DDRPHYA_ANIB_ATXDLY_P0_ATxDly_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P0_ATxDly_p0_SHIFT)) & DWC_DDRPHYA_ANIB_ATXDLY_P0_ATxDly_p0_MASK)
10148/*! @} */
10149
10150/*! @name ATXDLY_P1 - Address/Command Delay, per pstate. */
10151/*! @{ */
10152#define DWC_DDRPHYA_ANIB_ATXDLY_P1_ATxDly_p1_MASK (0x7FU)
10153#define DWC_DDRPHYA_ANIB_ATXDLY_P1_ATxDly_p1_SHIFT (0U)
10154#define DWC_DDRPHYA_ANIB_ATXDLY_P1_ATxDly_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P1_ATxDly_p1_SHIFT)) & DWC_DDRPHYA_ANIB_ATXDLY_P1_ATxDly_p1_MASK)
10155/*! @} */
10156
10157/*! @name ATXDLY_P2 - Address/Command Delay, per pstate. */
10158/*! @{ */
10159#define DWC_DDRPHYA_ANIB_ATXDLY_P2_ATxDly_p2_MASK (0x7FU)
10160#define DWC_DDRPHYA_ANIB_ATXDLY_P2_ATxDly_p2_SHIFT (0U)
10161#define DWC_DDRPHYA_ANIB_ATXDLY_P2_ATxDly_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P2_ATxDly_p2_SHIFT)) & DWC_DDRPHYA_ANIB_ATXDLY_P2_ATxDly_p2_MASK)
10162/*! @} */
10163
10164/*! @name ATXDLY_P3 - Address/Command Delay, per pstate. */
10165/*! @{ */
10166#define DWC_DDRPHYA_ANIB_ATXDLY_P3_ATxDly_p3_MASK (0x7FU)
10167#define DWC_DDRPHYA_ANIB_ATXDLY_P3_ATxDly_p3_SHIFT (0U)
10168#define DWC_DDRPHYA_ANIB_ATXDLY_P3_ATxDly_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P3_ATxDly_p3_SHIFT)) & DWC_DDRPHYA_ANIB_ATXDLY_P3_ATxDly_p3_MASK)
10169/*! @} */
10170
10171
10172/*!
10173 * @}
10174 */ /* end of group DWC_DDRPHYA_ANIB_Register_Masks */
10175
10176
10177/* DWC_DDRPHYA_ANIB - Peripheral instance base addresses */
10178/** Peripheral DWC_DDRPHYA_ANIB0 base address */
10179#define DWC_DDRPHYA_ANIB0_BASE (0x3C000000u)
10180/** Peripheral DWC_DDRPHYA_ANIB0 base pointer */
10181#define DWC_DDRPHYA_ANIB0 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB0_BASE)
10182/** Peripheral DWC_DDRPHYA_ANIB1 base address */
10183#define DWC_DDRPHYA_ANIB1_BASE (0x3C001000u)
10184/** Peripheral DWC_DDRPHYA_ANIB1 base pointer */
10185#define DWC_DDRPHYA_ANIB1 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB1_BASE)
10186/** Peripheral DWC_DDRPHYA_ANIB2 base address */
10187#define DWC_DDRPHYA_ANIB2_BASE (0x3C002000u)
10188/** Peripheral DWC_DDRPHYA_ANIB2 base pointer */
10189#define DWC_DDRPHYA_ANIB2 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB2_BASE)
10190/** Peripheral DWC_DDRPHYA_ANIB3 base address */
10191#define DWC_DDRPHYA_ANIB3_BASE (0x3C003000u)
10192/** Peripheral DWC_DDRPHYA_ANIB3 base pointer */
10193#define DWC_DDRPHYA_ANIB3 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB3_BASE)
10194/** Peripheral DWC_DDRPHYA_ANIB4 base address */
10195#define DWC_DDRPHYA_ANIB4_BASE (0x3C004000u)
10196/** Peripheral DWC_DDRPHYA_ANIB4 base pointer */
10197#define DWC_DDRPHYA_ANIB4 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB4_BASE)
10198/** Peripheral DWC_DDRPHYA_ANIB5 base address */
10199#define DWC_DDRPHYA_ANIB5_BASE (0x3C005000u)
10200/** Peripheral DWC_DDRPHYA_ANIB5 base pointer */
10201#define DWC_DDRPHYA_ANIB5 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB5_BASE)
10202/** Peripheral DWC_DDRPHYA_ANIB6 base address */
10203#define DWC_DDRPHYA_ANIB6_BASE (0x3C006000u)
10204/** Peripheral DWC_DDRPHYA_ANIB6 base pointer */
10205#define DWC_DDRPHYA_ANIB6 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB6_BASE)
10206/** Peripheral DWC_DDRPHYA_ANIB7 base address */
10207#define DWC_DDRPHYA_ANIB7_BASE (0x3C007000u)
10208/** Peripheral DWC_DDRPHYA_ANIB7 base pointer */
10209#define DWC_DDRPHYA_ANIB7 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB7_BASE)
10210/** Peripheral DWC_DDRPHYA_ANIB8 base address */
10211#define DWC_DDRPHYA_ANIB8_BASE (0x3C008000u)
10212/** Peripheral DWC_DDRPHYA_ANIB8 base pointer */
10213#define DWC_DDRPHYA_ANIB8 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB8_BASE)
10214/** Peripheral DWC_DDRPHYA_ANIB9 base address */
10215#define DWC_DDRPHYA_ANIB9_BASE (0x3C009000u)
10216/** Peripheral DWC_DDRPHYA_ANIB9 base pointer */
10217#define DWC_DDRPHYA_ANIB9 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB9_BASE)
10218/** Array initializer of DWC_DDRPHYA_ANIB peripheral base addresses */
10219#define DWC_DDRPHYA_ANIB_BASE_ADDRS { DWC_DDRPHYA_ANIB0_BASE, DWC_DDRPHYA_ANIB1_BASE, DWC_DDRPHYA_ANIB2_BASE, DWC_DDRPHYA_ANIB3_BASE, DWC_DDRPHYA_ANIB4_BASE, DWC_DDRPHYA_ANIB5_BASE, DWC_DDRPHYA_ANIB6_BASE, DWC_DDRPHYA_ANIB7_BASE, DWC_DDRPHYA_ANIB8_BASE, DWC_DDRPHYA_ANIB9_BASE }
10220/** Array initializer of DWC_DDRPHYA_ANIB peripheral base pointers */
10221#define DWC_DDRPHYA_ANIB_BASE_PTRS { DWC_DDRPHYA_ANIB0, DWC_DDRPHYA_ANIB1, DWC_DDRPHYA_ANIB2, DWC_DDRPHYA_ANIB3, DWC_DDRPHYA_ANIB4, DWC_DDRPHYA_ANIB5, DWC_DDRPHYA_ANIB6, DWC_DDRPHYA_ANIB7, DWC_DDRPHYA_ANIB8, DWC_DDRPHYA_ANIB9 }
10222
10223/*!
10224 * @}
10225 */ /* end of group DWC_DDRPHYA_ANIB_Peripheral_Access_Layer */
10226
10227
10228/* ----------------------------------------------------------------------------
10229 -- DWC_DDRPHYA_APBONLY Peripheral Access Layer
10230 ---------------------------------------------------------------------------- */
10231
10232/*!
10233 * @addtogroup DWC_DDRPHYA_APBONLY_Peripheral_Access_Layer DWC_DDRPHYA_APBONLY Peripheral Access Layer
10234 * @{
10235 */
10236
10237/** DWC_DDRPHYA_APBONLY - Register Layout Typedef */
10238typedef struct {
10239 __IO uint16_t MICROCONTMUXSEL; /**< PMU Config Mux Select, offset: 0x0 */
10240 uint8_t RESERVED_0[6];
10241 __I uint16_t UCTSHADOWREGS; /**< PMU/Controller Protocol - Controller Read-only Shadow, offset: 0x8 */
10242 uint8_t RESERVED_1[86];
10243 __IO uint16_t DCTWRITEONLY; /**< Reserved for future use., offset: 0x60 */
10244 __IO uint16_t DCTWRITEPROT; /**< DCT downstream mailbox protocol CSR., offset: 0x62 */
10245 __I uint16_t UCTWRITEONLYSHADOW; /**< Read-only view of the csr UctDatWriteOnly, offset: 0x64 */
10246 uint8_t RESERVED_2[2];
10247 __I uint16_t UCTDATWRITEONLYSHADOW; /**< Read-only view of the csr UctDatWriteOnly, offset: 0x68 */
10248 uint8_t RESERVED_3[4];
10249 __IO uint16_t DFICFGRDDATAVALIDTICKS; /**< Number of DfiClk ticks required for valid csr Rd Data., offset: 0x6E */
10250 uint8_t RESERVED_4[194];
10251 __IO uint16_t MICRORESET; /**< Controls reset and clock shutdown on the local microcontroller, offset: 0x132 */
10252 uint8_t RESERVED_5[192];
10253 __I uint16_t DFIINITCOMPLETESHADOW; /**< dfi_init_complete - Controller Read-only Shadow, offset: 0x1F4 */
10254} DWC_DDRPHYA_APBONLY_Type;
10255
10256/* ----------------------------------------------------------------------------
10257 -- DWC_DDRPHYA_APBONLY Register Masks
10258 ---------------------------------------------------------------------------- */
10259
10260/*!
10261 * @addtogroup DWC_DDRPHYA_APBONLY_Register_Masks DWC_DDRPHYA_APBONLY Register Masks
10262 * @{
10263 */
10264
10265/*! @name MICROCONTMUXSEL - PMU Config Mux Select */
10266/*! @{ */
10267#define DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MicroContMuxSel_MASK (0x1U)
10268#define DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MicroContMuxSel_SHIFT (0U)
10269#define DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MicroContMuxSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MicroContMuxSel_SHIFT)) & DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MicroContMuxSel_MASK)
10270/*! @} */
10271
10272/*! @name UCTSHADOWREGS - PMU/Controller Protocol - Controller Read-only Shadow */
10273/*! @{ */
10274#define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctWriteProtShadow_MASK (0x1U)
10275#define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctWriteProtShadow_SHIFT (0U)
10276#define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctWriteProtShadow(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctWriteProtShadow_SHIFT)) & DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctWriteProtShadow_MASK)
10277#define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctDatWriteProtShadow_MASK (0x2U)
10278#define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctDatWriteProtShadow_SHIFT (1U)
10279#define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctDatWriteProtShadow(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctDatWriteProtShadow_SHIFT)) & DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctDatWriteProtShadow_MASK)
10280/*! @} */
10281
10282/*! @name DCTWRITEONLY - Reserved for future use. */
10283/*! @{ */
10284#define DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DctWriteOnly_MASK (0xFFFFU)
10285#define DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DctWriteOnly_SHIFT (0U)
10286#define DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DctWriteOnly(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DctWriteOnly_SHIFT)) & DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DctWriteOnly_MASK)
10287/*! @} */
10288
10289/*! @name DCTWRITEPROT - DCT downstream mailbox protocol CSR. */
10290/*! @{ */
10291#define DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DctWriteProt_MASK (0x1U)
10292#define DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DctWriteProt_SHIFT (0U)
10293#define DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DctWriteProt(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DctWriteProt_SHIFT)) & DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DctWriteProt_MASK)
10294/*! @} */
10295
10296/*! @name UCTWRITEONLYSHADOW - Read-only view of the csr UctDatWriteOnly */
10297/*! @{ */
10298#define DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UctWriteOnlyShadow_MASK (0xFFFFU)
10299#define DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UctWriteOnlyShadow_SHIFT (0U)
10300#define DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UctWriteOnlyShadow(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UctWriteOnlyShadow_SHIFT)) & DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UctWriteOnlyShadow_MASK)
10301/*! @} */
10302
10303/*! @name UCTDATWRITEONLYSHADOW - Read-only view of the csr UctDatWriteOnly */
10304/*! @{ */
10305#define DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UctDatWriteOnlyShadow_MASK (0xFFFFU)
10306#define DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UctDatWriteOnlyShadow_SHIFT (0U)
10307#define DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UctDatWriteOnlyShadow(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UctDatWriteOnlyShadow_SHIFT)) & DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UctDatWriteOnlyShadow_MASK)
10308/*! @} */
10309
10310/*! @name DFICFGRDDATAVALIDTICKS - Number of DfiClk ticks required for valid csr Rd Data. */
10311/*! @{ */
10312#define DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DfiCfgRdDataValidTicks_MASK (0x3FU)
10313#define DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DfiCfgRdDataValidTicks_SHIFT (0U)
10314#define DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DfiCfgRdDataValidTicks(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DfiCfgRdDataValidTicks_SHIFT)) & DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DfiCfgRdDataValidTicks_MASK)
10315/*! @} */
10316
10317/*! @name MICRORESET - Controls reset and clock shutdown on the local microcontroller */
10318/*! @{ */
10319#define DWC_DDRPHYA_APBONLY_MICRORESET_StallToMicro_MASK (0x1U)
10320#define DWC_DDRPHYA_APBONLY_MICRORESET_StallToMicro_SHIFT (0U)
10321#define DWC_DDRPHYA_APBONLY_MICRORESET_StallToMicro(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_StallToMicro_SHIFT)) & DWC_DDRPHYA_APBONLY_MICRORESET_StallToMicro_MASK)
10322#define DWC_DDRPHYA_APBONLY_MICRORESET_TestWakeup_MASK (0x2U)
10323#define DWC_DDRPHYA_APBONLY_MICRORESET_TestWakeup_SHIFT (1U)
10324#define DWC_DDRPHYA_APBONLY_MICRORESET_TestWakeup(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_TestWakeup_SHIFT)) & DWC_DDRPHYA_APBONLY_MICRORESET_TestWakeup_MASK)
10325#define DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMicro_MASK (0x4U)
10326#define DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMicro_SHIFT (2U)
10327#define DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMicro(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMicro_SHIFT)) & DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMicro_MASK)
10328#define DWC_DDRPHYA_APBONLY_MICRORESET_ResetToMicro_MASK (0x8U)
10329#define DWC_DDRPHYA_APBONLY_MICRORESET_ResetToMicro_SHIFT (3U)
10330#define DWC_DDRPHYA_APBONLY_MICRORESET_ResetToMicro(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_ResetToMicro_SHIFT)) & DWC_DDRPHYA_APBONLY_MICRORESET_ResetToMicro_MASK)
10331/*! @} */
10332
10333/*! @name DFIINITCOMPLETESHADOW - dfi_init_complete - Controller Read-only Shadow */
10334/*! @{ */
10335#define DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DfiInitCompleteShadow_MASK (0x1U)
10336#define DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DfiInitCompleteShadow_SHIFT (0U)
10337#define DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DfiInitCompleteShadow(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DfiInitCompleteShadow_SHIFT)) & DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DfiInitCompleteShadow_MASK)
10338/*! @} */
10339
10340
10341/*!
10342 * @}
10343 */ /* end of group DWC_DDRPHYA_APBONLY_Register_Masks */
10344
10345
10346/* DWC_DDRPHYA_APBONLY - Peripheral instance base addresses */
10347/** Peripheral DWC_DDRPHYA_APBONLY0 base address */
10348#define DWC_DDRPHYA_APBONLY0_BASE (0x3C0D0000u)
10349/** Peripheral DWC_DDRPHYA_APBONLY0 base pointer */
10350#define DWC_DDRPHYA_APBONLY0 ((DWC_DDRPHYA_APBONLY_Type *)DWC_DDRPHYA_APBONLY0_BASE)
10351/** Array initializer of DWC_DDRPHYA_APBONLY peripheral base addresses */
10352#define DWC_DDRPHYA_APBONLY_BASE_ADDRS { DWC_DDRPHYA_APBONLY0_BASE }
10353/** Array initializer of DWC_DDRPHYA_APBONLY peripheral base pointers */
10354#define DWC_DDRPHYA_APBONLY_BASE_PTRS { DWC_DDRPHYA_APBONLY0 }
10355
10356/*!
10357 * @}
10358 */ /* end of group DWC_DDRPHYA_APBONLY_Peripheral_Access_Layer */
10359
10360
10361/* ----------------------------------------------------------------------------
10362 -- DWC_DDRPHYA_DBYTE Peripheral Access Layer
10363 ---------------------------------------------------------------------------- */
10364
10365/*!
10366 * @addtogroup DWC_DDRPHYA_DBYTE_Peripheral_Access_Layer DWC_DDRPHYA_DBYTE Peripheral Access Layer
10367 * @{
10368 */
10369
10370/** DWC_DDRPHYA_DBYTE - Register Layout Typedef */
10371typedef struct {
10372 __IO uint16_t DBYTEMISCMODE; /**< DBYTE Module Disable, offset: 0x0 */
10373 uint8_t RESERVED_0[50];
10374 __IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x34 */
10375 uint8_t RESERVED_1[10];
10376 __IO uint16_t DFIMRL_P0; /**< DFI MaxReadLatency, offset: 0x40 */
10377 uint8_t RESERVED_2[30];
10378 __IO uint16_t VREFDAC1_R0; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x60 */
10379 uint8_t RESERVED_3[30];
10380 __IO uint16_t VREFDAC0_R0; /**< VrefDAC0 control for DQ Receiver, offset: 0x80 */
10381 __IO uint16_t TXIMPEDANCECTRL0_B0_P0; /**< Data TX impedance controls, offset: 0x82 */
10382 uint8_t RESERVED_4[2];
10383 __IO uint16_t DQDQSRCVCNTRL_B0_P0; /**< Dq/Dqs receiver control, offset: 0x86 */
10384 uint8_t RESERVED_5[8];
10385 __IO uint16_t TXEQUALIZATIONMODE_P0; /**< Tx dq driver equalization mode controls., offset: 0x90 */
10386 __IO uint16_t TXIMPEDANCECTRL1_B0_P0; /**< TX impedance controls, offset: 0x92 */
10387 __IO uint16_t DQDQSRCVCNTRL1; /**< Dq/Dqs receiver control, offset: 0x94 */
10388 __IO uint16_t TXIMPEDANCECTRL2_B0_P0; /**< TX equalization impedance controls, offset: 0x96 */
10389 __IO uint16_t DQDQSRCVCNTRL2_P0; /**< Dq/Dqs receiver control, offset: 0x98 */
10390 __IO uint16_t TXODTDRVSTREN_B0_P0; /**< TX ODT driver strength control, offset: 0x9A */
10391 uint8_t RESERVED_6[16];
10392 __I uint16_t RXFIFOCHECKSTATUS; /**< Status of RX FIFO Consistency Checks, offset: 0xAC */
10393 __I uint16_t RXFIFOCHECKERRVALUES; /**< Contains the captured values associated with an RxFifo consistency error, offset: 0xAE */
10394 __I uint16_t RXFIFOINFO; /**< Data Receive FIFO Pointer Values, offset: 0xB0 */
10395 __IO uint16_t RXFIFOVISIBILITY; /**< RX FIFO visibility, offset: 0xB2 */
10396 __I uint16_t RXFIFOCONTENTSDQ3210; /**< RX FIFO contents, lane[3:0], offset: 0xB4 */
10397 __I uint16_t RXFIFOCONTENTSDQ7654; /**< RX FIFO contents, lane[7:4], offset: 0xB6 */
10398 __I uint16_t RXFIFOCONTENTSDBI; /**< RX FIFO contents, dbi, offset: 0xB8 */
10399 uint8_t RESERVED_7[4];
10400 __IO uint16_t TXSLEWRATE_B0_P0; /**< TX slew rate controls, offset: 0xBE */
10401 uint8_t RESERVED_8[16];
10402 __IO uint16_t RXPBDLYTG0_R0; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xD0 */
10403 __IO uint16_t RXPBDLYTG1_R0; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xD2 */
10404 __IO uint16_t RXPBDLYTG2_R0; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xD4 */
10405 __IO uint16_t RXPBDLYTG3_R0; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xD6 */
10406 uint8_t RESERVED_9[40];
10407 __IO uint16_t RXENDLYTG0_U0_P0; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x100 */
10408 __IO uint16_t RXENDLYTG1_U0_P0; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x102 */
10409 __IO uint16_t RXENDLYTG2_U0_P0; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x104 */
10410 __IO uint16_t RXENDLYTG3_U0_P0; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x106 */
10411 uint8_t RESERVED_10[16];
10412 __IO uint16_t RXCLKDLYTG0_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x118 */
10413 __IO uint16_t RXCLKDLYTG1_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x11A */
10414 __IO uint16_t RXCLKDLYTG2_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x11C */
10415 __IO uint16_t RXCLKDLYTG3_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x11E */
10416 __IO uint16_t RXCLKCDLYTG0_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x120 */
10417 __IO uint16_t RXCLKCDLYTG1_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x122 */
10418 __IO uint16_t RXCLKCDLYTG2_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x124 */
10419 uint8_t RESERVED_11[2];
10420 __IO uint16_t RXCLKCDLYTG3_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x128 */
10421 uint8_t RESERVED_12[22];
10422 __IO uint16_t DQLNSEL[8]; /**< Maps Phy DQ lane to memory DQ0, array offset: 0x140, array step: 0x2 */
10423 uint8_t RESERVED_13[48];
10424 __IO uint16_t TXDQDLYTG0_R0_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x180 */
10425 __IO uint16_t TXDQDLYTG1_R0_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x182 */
10426 __IO uint16_t TXDQDLYTG2_R0_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x184 */
10427 __IO uint16_t TXDQDLYTG3_R0_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x186 */
10428 uint8_t RESERVED_14[24];
10429 __IO uint16_t TXDQSDLYTG0_U0_P0; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x1A0 */
10430 __IO uint16_t TXDQSDLYTG1_U0_P0; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x1A2 */
10431 __IO uint16_t TXDQSDLYTG2_U0_P0; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x1A4 */
10432 __IO uint16_t TXDQSDLYTG3_U0_P0; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x1A6 */
10433 uint8_t RESERVED_15[32];
10434 __I uint16_t DXLCDLSTATUS; /**< Debug status of the DBYTE LCDL, offset: 0x1C8 */
10435 uint8_t RESERVED_16[150];
10436 __IO uint16_t VREFDAC1_R1; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x260 */
10437 uint8_t RESERVED_17[30];
10438 __IO uint16_t VREFDAC0_R1; /**< VrefDAC0 control for DQ Receiver, offset: 0x280 */
10439 __IO uint16_t TXIMPEDANCECTRL0_B1_P0; /**< Data TX impedance controls, offset: 0x282 */
10440 uint8_t RESERVED_18[2];
10441 __IO uint16_t DQDQSRCVCNTRL_B1_P0; /**< Dq/Dqs receiver control, offset: 0x286 */
10442 uint8_t RESERVED_19[10];
10443 __IO uint16_t TXIMPEDANCECTRL1_B1_P0; /**< TX impedance controls, offset: 0x292 */
10444 uint8_t RESERVED_20[2];
10445 __IO uint16_t TXIMPEDANCECTRL2_B1_P0; /**< TX equalization impedance controls, offset: 0x296 */
10446 uint8_t RESERVED_21[2];
10447 __IO uint16_t TXODTDRVSTREN_B1_P0; /**< TX ODT driver strength control, offset: 0x29A */
10448 uint8_t RESERVED_22[34];
10449 __IO uint16_t TXSLEWRATE_B1_P0; /**< TX slew rate controls, offset: 0x2BE */
10450 uint8_t RESERVED_23[16];
10451 __IO uint16_t RXPBDLYTG0_R1; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x2D0 */
10452 __IO uint16_t RXPBDLYTG1_R1; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x2D2 */
10453 __IO uint16_t RXPBDLYTG2_R1; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x2D4 */
10454 __IO uint16_t RXPBDLYTG3_R1; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x2D6 */
10455 uint8_t RESERVED_24[40];
10456 __IO uint16_t RXENDLYTG0_U1_P0; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x300 */
10457 __IO uint16_t RXENDLYTG1_U1_P0; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x302 */
10458 __IO uint16_t RXENDLYTG2_U1_P0; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x304 */
10459 __IO uint16_t RXENDLYTG3_U1_P0; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x306 */
10460 uint8_t RESERVED_25[16];
10461 __IO uint16_t RXCLKDLYTG0_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x318 */
10462 __IO uint16_t RXCLKDLYTG1_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x31A */
10463 __IO uint16_t RXCLKDLYTG2_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x31C */
10464 __IO uint16_t RXCLKDLYTG3_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x31E */
10465 __IO uint16_t RXCLKCDLYTG0_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x320 */
10466 __IO uint16_t RXCLKCDLYTG1_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x322 */
10467 __IO uint16_t RXCLKCDLYTG2_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x324 */
10468 uint8_t RESERVED_26[2];
10469 __IO uint16_t RXCLKCDLYTG3_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x328 */
10470 uint8_t RESERVED_27[86];
10471 __IO uint16_t TXDQDLYTG0_R1_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x380 */
10472 __IO uint16_t TXDQDLYTG1_R1_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x382 */
10473 __IO uint16_t TXDQDLYTG2_R1_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x384 */
10474 __IO uint16_t TXDQDLYTG3_R1_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x386 */
10475 uint8_t RESERVED_28[24];
10476 __IO uint16_t TXDQSDLYTG0_U1_P0; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x3A0 */
10477 __IO uint16_t TXDQSDLYTG1_U1_P0; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x3A2 */
10478 __IO uint16_t TXDQSDLYTG2_U1_P0; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x3A4 */
10479 __IO uint16_t TXDQSDLYTG3_U1_P0; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x3A6 */
10480 uint8_t RESERVED_29[184];
10481 __IO uint16_t VREFDAC1_R2; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x460 */
10482 uint8_t RESERVED_30[30];
10483 __IO uint16_t VREFDAC0_R2; /**< VrefDAC0 control for DQ Receiver, offset: 0x480 */
10484 uint8_t RESERVED_31[78];
10485 __IO uint16_t RXPBDLYTG0_R2; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x4D0 */
10486 __IO uint16_t RXPBDLYTG1_R2; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x4D2 */
10487 __IO uint16_t RXPBDLYTG2_R2; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x4D4 */
10488 __IO uint16_t RXPBDLYTG3_R2; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x4D6 */
10489 uint8_t RESERVED_32[168];
10490 __IO uint16_t TXDQDLYTG0_R2_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x580 */
10491 __IO uint16_t TXDQDLYTG1_R2_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x582 */
10492 __IO uint16_t TXDQDLYTG2_R2_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x584 */
10493 __IO uint16_t TXDQDLYTG3_R2_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x586 */
10494 uint8_t RESERVED_33[216];
10495 __IO uint16_t VREFDAC1_R3; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x660 */
10496 uint8_t RESERVED_34[30];
10497 __IO uint16_t VREFDAC0_R3; /**< VrefDAC0 control for DQ Receiver, offset: 0x680 */
10498 uint8_t RESERVED_35[78];
10499 __IO uint16_t RXPBDLYTG0_R3; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x6D0 */
10500 __IO uint16_t RXPBDLYTG1_R3; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x6D2 */
10501 __IO uint16_t RXPBDLYTG2_R3; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x6D4 */
10502 __IO uint16_t RXPBDLYTG3_R3; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x6D6 */
10503 uint8_t RESERVED_36[168];
10504 __IO uint16_t TXDQDLYTG0_R3_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x780 */
10505 __IO uint16_t TXDQDLYTG1_R3_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x782 */
10506 __IO uint16_t TXDQDLYTG2_R3_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x784 */
10507 __IO uint16_t TXDQDLYTG3_R3_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x786 */
10508 uint8_t RESERVED_37[216];
10509 __IO uint16_t VREFDAC1_R4; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x860 */
10510 uint8_t RESERVED_38[30];
10511 __IO uint16_t VREFDAC0_R4; /**< VrefDAC0 control for DQ Receiver, offset: 0x880 */
10512 uint8_t RESERVED_39[78];
10513 __IO uint16_t RXPBDLYTG0_R4; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x8D0 */
10514 __IO uint16_t RXPBDLYTG1_R4; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x8D2 */
10515 __IO uint16_t RXPBDLYTG2_R4; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x8D4 */
10516 __IO uint16_t RXPBDLYTG3_R4; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x8D6 */
10517 uint8_t RESERVED_40[168];
10518 __IO uint16_t TXDQDLYTG0_R4_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x980 */
10519 __IO uint16_t TXDQDLYTG1_R4_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x982 */
10520 __IO uint16_t TXDQDLYTG2_R4_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x984 */
10521 __IO uint16_t TXDQDLYTG3_R4_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x986 */
10522 uint8_t RESERVED_41[216];
10523 __IO uint16_t VREFDAC1_R5; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0xA60 */
10524 uint8_t RESERVED_42[30];
10525 __IO uint16_t VREFDAC0_R5; /**< VrefDAC0 control for DQ Receiver, offset: 0xA80 */
10526 uint8_t RESERVED_43[78];
10527 __IO uint16_t RXPBDLYTG0_R5; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xAD0 */
10528 __IO uint16_t RXPBDLYTG1_R5; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xAD2 */
10529 __IO uint16_t RXPBDLYTG2_R5; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xAD4 */
10530 __IO uint16_t RXPBDLYTG3_R5; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xAD6 */
10531 uint8_t RESERVED_44[168];
10532 __IO uint16_t TXDQDLYTG0_R5_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0xB80 */
10533 __IO uint16_t TXDQDLYTG1_R5_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0xB82 */
10534 __IO uint16_t TXDQDLYTG2_R5_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0xB84 */
10535 __IO uint16_t TXDQDLYTG3_R5_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0xB86 */
10536 uint8_t RESERVED_45[216];
10537 __IO uint16_t VREFDAC1_R6; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0xC60 */
10538 uint8_t RESERVED_46[30];
10539 __IO uint16_t VREFDAC0_R6; /**< VrefDAC0 control for DQ Receiver, offset: 0xC80 */
10540 uint8_t RESERVED_47[78];
10541 __IO uint16_t RXPBDLYTG0_R6; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xCD0 */
10542 __IO uint16_t RXPBDLYTG1_R6; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xCD2 */
10543 __IO uint16_t RXPBDLYTG2_R6; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xCD4 */
10544 __IO uint16_t RXPBDLYTG3_R6; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xCD6 */
10545 uint8_t RESERVED_48[168];
10546 __IO uint16_t TXDQDLYTG0_R6_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0xD80 */
10547 __IO uint16_t TXDQDLYTG1_R6_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0xD82 */
10548 __IO uint16_t TXDQDLYTG2_R6_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0xD84 */
10549 __IO uint16_t TXDQDLYTG3_R6_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0xD86 */
10550 uint8_t RESERVED_49[216];
10551 __IO uint16_t VREFDAC1_R7; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0xE60 */
10552 uint8_t RESERVED_50[30];
10553 __IO uint16_t VREFDAC0_R7; /**< VrefDAC0 control for DQ Receiver, offset: 0xE80 */
10554 uint8_t RESERVED_51[78];
10555 __IO uint16_t RXPBDLYTG0_R7; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xED0 */
10556 __IO uint16_t RXPBDLYTG1_R7; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xED2 */
10557 __IO uint16_t RXPBDLYTG2_R7; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xED4 */
10558 __IO uint16_t RXPBDLYTG3_R7; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xED6 */
10559 uint8_t RESERVED_52[168];
10560 __IO uint16_t TXDQDLYTG0_R7_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0xF80 */
10561 __IO uint16_t TXDQDLYTG1_R7_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0xF82 */
10562 __IO uint16_t TXDQDLYTG2_R7_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0xF84 */
10563 __IO uint16_t TXDQDLYTG3_R7_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0xF86 */
10564 uint8_t RESERVED_53[216];
10565 __IO uint16_t VREFDAC1_R8; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x1060 */
10566 uint8_t RESERVED_54[30];
10567 __IO uint16_t VREFDAC0_R8; /**< VrefDAC0 control for DQ Receiver, offset: 0x1080 */
10568 uint8_t RESERVED_55[78];
10569 __IO uint16_t RXPBDLYTG0_R8; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x10D0 */
10570 __IO uint16_t RXPBDLYTG1_R8; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x10D2 */
10571 __IO uint16_t RXPBDLYTG2_R8; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x10D4 */
10572 __IO uint16_t RXPBDLYTG3_R8; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x10D6 */
10573 uint8_t RESERVED_56[168];
10574 __IO uint16_t TXDQDLYTG0_R8_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x1180 */
10575 __IO uint16_t TXDQDLYTG1_R8_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x1182 */
10576 __IO uint16_t TXDQDLYTG2_R8_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x1184 */
10577 __IO uint16_t TXDQDLYTG3_R8_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x1186 */
10578 uint8_t RESERVED_57[2092728];
10579 __IO uint16_t DFIMRL_P1; /**< DFI MaxReadLatency, offset: 0x200040 */
10580 uint8_t RESERVED_58[64];
10581 __IO uint16_t TXIMPEDANCECTRL0_B0_P1; /**< Data TX impedance controls, offset: 0x200082 */
10582 uint8_t RESERVED_59[2];
10583 __IO uint16_t DQDQSRCVCNTRL_B0_P1; /**< Dq/Dqs receiver control, offset: 0x200086 */
10584 uint8_t RESERVED_60[8];
10585 __IO uint16_t TXEQUALIZATIONMODE_P1; /**< Tx dq driver equalization mode controls., offset: 0x200090 */
10586 __IO uint16_t TXIMPEDANCECTRL1_B0_P1; /**< TX impedance controls, offset: 0x200092 */
10587 uint8_t RESERVED_61[2];
10588 __IO uint16_t TXIMPEDANCECTRL2_B0_P1; /**< TX equalization impedance controls, offset: 0x200096 */
10589 __IO uint16_t DQDQSRCVCNTRL2_P1; /**< Dq/Dqs receiver control, offset: 0x200098 */
10590 __IO uint16_t TXODTDRVSTREN_B0_P1; /**< TX ODT driver strength control, offset: 0x20009A */
10591 uint8_t RESERVED_62[34];
10592 __IO uint16_t TXSLEWRATE_B0_P1; /**< TX slew rate controls, offset: 0x2000BE */
10593 uint8_t RESERVED_63[64];
10594 __IO uint16_t RXENDLYTG0_U0_P1; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x200100 */
10595 __IO uint16_t RXENDLYTG1_U0_P1; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x200102 */
10596 __IO uint16_t RXENDLYTG2_U0_P1; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x200104 */
10597 __IO uint16_t RXENDLYTG3_U0_P1; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x200106 */
10598 uint8_t RESERVED_64[16];
10599 __IO uint16_t RXCLKDLYTG0_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x200118 */
10600 __IO uint16_t RXCLKDLYTG1_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x20011A */
10601 __IO uint16_t RXCLKDLYTG2_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x20011C */
10602 __IO uint16_t RXCLKDLYTG3_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x20011E */
10603 __IO uint16_t RXCLKCDLYTG0_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200120 */
10604 __IO uint16_t RXCLKCDLYTG1_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200122 */
10605 __IO uint16_t RXCLKCDLYTG2_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x200124 */
10606 uint8_t RESERVED_65[2];
10607 __IO uint16_t RXCLKCDLYTG3_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x200128 */
10608 uint8_t RESERVED_66[86];
10609 __IO uint16_t TXDQDLYTG0_R0_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200180 */
10610 __IO uint16_t TXDQDLYTG1_R0_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200182 */
10611 __IO uint16_t TXDQDLYTG2_R0_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200184 */
10612 __IO uint16_t TXDQDLYTG3_R0_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200186 */
10613 uint8_t RESERVED_67[24];
10614 __IO uint16_t TXDQSDLYTG0_U0_P1; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x2001A0 */
10615 __IO uint16_t TXDQSDLYTG1_U0_P1; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x2001A2 */
10616 __IO uint16_t TXDQSDLYTG2_U0_P1; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x2001A4 */
10617 __IO uint16_t TXDQSDLYTG3_U0_P1; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x2001A6 */
10618 uint8_t RESERVED_68[218];
10619 __IO uint16_t TXIMPEDANCECTRL0_B1_P1; /**< Data TX impedance controls, offset: 0x200282 */
10620 uint8_t RESERVED_69[2];
10621 __IO uint16_t DQDQSRCVCNTRL_B1_P1; /**< Dq/Dqs receiver control, offset: 0x200286 */
10622 uint8_t RESERVED_70[10];
10623 __IO uint16_t TXIMPEDANCECTRL1_B1_P1; /**< TX impedance controls, offset: 0x200292 */
10624 uint8_t RESERVED_71[2];
10625 __IO uint16_t TXIMPEDANCECTRL2_B1_P1; /**< TX equalization impedance controls, offset: 0x200296 */
10626 uint8_t RESERVED_72[2];
10627 __IO uint16_t TXODTDRVSTREN_B1_P1; /**< TX ODT driver strength control, offset: 0x20029A */
10628 uint8_t RESERVED_73[34];
10629 __IO uint16_t TXSLEWRATE_B1_P1; /**< TX slew rate controls, offset: 0x2002BE */
10630 uint8_t RESERVED_74[64];
10631 __IO uint16_t RXENDLYTG0_U1_P1; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x200300 */
10632 __IO uint16_t RXENDLYTG1_U1_P1; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x200302 */
10633 __IO uint16_t RXENDLYTG2_U1_P1; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x200304 */
10634 __IO uint16_t RXENDLYTG3_U1_P1; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x200306 */
10635 uint8_t RESERVED_75[16];
10636 __IO uint16_t RXCLKDLYTG0_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x200318 */
10637 __IO uint16_t RXCLKDLYTG1_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x20031A */
10638 __IO uint16_t RXCLKDLYTG2_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x20031C */
10639 __IO uint16_t RXCLKDLYTG3_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x20031E */
10640 __IO uint16_t RXCLKCDLYTG0_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200320 */
10641 __IO uint16_t RXCLKCDLYTG1_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200322 */
10642 __IO uint16_t RXCLKCDLYTG2_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x200324 */
10643 uint8_t RESERVED_76[2];
10644 __IO uint16_t RXCLKCDLYTG3_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x200328 */
10645 uint8_t RESERVED_77[86];
10646 __IO uint16_t TXDQDLYTG0_R1_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200380 */
10647 __IO uint16_t TXDQDLYTG1_R1_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200382 */
10648 __IO uint16_t TXDQDLYTG2_R1_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200384 */
10649 __IO uint16_t TXDQDLYTG3_R1_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200386 */
10650 uint8_t RESERVED_78[24];
10651 __IO uint16_t TXDQSDLYTG0_U1_P1; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x2003A0 */
10652 __IO uint16_t TXDQSDLYTG1_U1_P1; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x2003A2 */
10653 __IO uint16_t TXDQSDLYTG2_U1_P1; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x2003A4 */
10654 __IO uint16_t TXDQSDLYTG3_U1_P1; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x2003A6 */
10655 uint8_t RESERVED_79[472];
10656 __IO uint16_t TXDQDLYTG0_R2_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200580 */
10657 __IO uint16_t TXDQDLYTG1_R2_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200582 */
10658 __IO uint16_t TXDQDLYTG2_R2_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200584 */
10659 __IO uint16_t TXDQDLYTG3_R2_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200586 */
10660 uint8_t RESERVED_80[504];
10661 __IO uint16_t TXDQDLYTG0_R3_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200780 */
10662 __IO uint16_t TXDQDLYTG1_R3_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200782 */
10663 __IO uint16_t TXDQDLYTG2_R3_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200784 */
10664 __IO uint16_t TXDQDLYTG3_R3_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200786 */
10665 uint8_t RESERVED_81[504];
10666 __IO uint16_t TXDQDLYTG0_R4_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200980 */
10667 __IO uint16_t TXDQDLYTG1_R4_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200982 */
10668 __IO uint16_t TXDQDLYTG2_R4_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200984 */
10669 __IO uint16_t TXDQDLYTG3_R4_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200986 */
10670 uint8_t RESERVED_82[504];
10671 __IO uint16_t TXDQDLYTG0_R5_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200B80 */
10672 __IO uint16_t TXDQDLYTG1_R5_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200B82 */
10673 __IO uint16_t TXDQDLYTG2_R5_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200B84 */
10674 __IO uint16_t TXDQDLYTG3_R5_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200B86 */
10675 uint8_t RESERVED_83[504];
10676 __IO uint16_t TXDQDLYTG0_R6_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200D80 */
10677 __IO uint16_t TXDQDLYTG1_R6_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200D82 */
10678 __IO uint16_t TXDQDLYTG2_R6_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200D84 */
10679 __IO uint16_t TXDQDLYTG3_R6_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200D86 */
10680 uint8_t RESERVED_84[504];
10681 __IO uint16_t TXDQDLYTG0_R7_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200F80 */
10682 __IO uint16_t TXDQDLYTG1_R7_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200F82 */
10683 __IO uint16_t TXDQDLYTG2_R7_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200F84 */
10684 __IO uint16_t TXDQDLYTG3_R7_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200F86 */
10685 uint8_t RESERVED_85[504];
10686 __IO uint16_t TXDQDLYTG0_R8_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x201180 */
10687 __IO uint16_t TXDQDLYTG1_R8_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x201182 */
10688 __IO uint16_t TXDQDLYTG2_R8_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x201184 */
10689 __IO uint16_t TXDQDLYTG3_R8_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x201186 */
10690 uint8_t RESERVED_86[2092728];
10691 __IO uint16_t DFIMRL_P2; /**< DFI MaxReadLatency, offset: 0x400040 */
10692 uint8_t RESERVED_87[64];
10693 __IO uint16_t TXIMPEDANCECTRL0_B0_P2; /**< Data TX impedance controls, offset: 0x400082 */
10694 uint8_t RESERVED_88[2];
10695 __IO uint16_t DQDQSRCVCNTRL_B0_P2; /**< Dq/Dqs receiver control, offset: 0x400086 */
10696 uint8_t RESERVED_89[8];
10697 __IO uint16_t TXEQUALIZATIONMODE_P2; /**< Tx dq driver equalization mode controls., offset: 0x400090 */
10698 __IO uint16_t TXIMPEDANCECTRL1_B0_P2; /**< TX impedance controls, offset: 0x400092 */
10699 uint8_t RESERVED_90[2];
10700 __IO uint16_t TXIMPEDANCECTRL2_B0_P2; /**< TX equalization impedance controls, offset: 0x400096 */
10701 __IO uint16_t DQDQSRCVCNTRL2_P2; /**< Dq/Dqs receiver control, offset: 0x400098 */
10702 __IO uint16_t TXODTDRVSTREN_B0_P2; /**< TX ODT driver strength control, offset: 0x40009A */
10703 uint8_t RESERVED_91[34];
10704 __IO uint16_t TXSLEWRATE_B0_P2; /**< TX slew rate controls, offset: 0x4000BE */
10705 uint8_t RESERVED_92[64];
10706 __IO uint16_t RXENDLYTG0_U0_P2; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x400100 */
10707 __IO uint16_t RXENDLYTG1_U0_P2; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x400102 */
10708 __IO uint16_t RXENDLYTG2_U0_P2; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x400104 */
10709 __IO uint16_t RXENDLYTG3_U0_P2; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x400106 */
10710 uint8_t RESERVED_93[16];
10711 __IO uint16_t RXCLKDLYTG0_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x400118 */
10712 __IO uint16_t RXCLKDLYTG1_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x40011A */
10713 __IO uint16_t RXCLKDLYTG2_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x40011C */
10714 __IO uint16_t RXCLKDLYTG3_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x40011E */
10715 __IO uint16_t RXCLKCDLYTG0_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400120 */
10716 __IO uint16_t RXCLKCDLYTG1_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400122 */
10717 __IO uint16_t RXCLKCDLYTG2_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x400124 */
10718 uint8_t RESERVED_94[2];
10719 __IO uint16_t RXCLKCDLYTG3_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x400128 */
10720 uint8_t RESERVED_95[50];
10721 __IO uint16_t PPTDQSCNTINVTRNTG0_P2; /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation, offset: 0x40015C */
10722 __IO uint16_t PPTDQSCNTINVTRNTG1_P2; /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation, offset: 0x40015E */
10723 uint8_t RESERVED_96[32];
10724 __IO uint16_t TXDQDLYTG0_R0_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400180 */
10725 __IO uint16_t TXDQDLYTG1_R0_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400182 */
10726 __IO uint16_t TXDQDLYTG2_R0_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400184 */
10727 __IO uint16_t TXDQDLYTG3_R0_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400186 */
10728 uint8_t RESERVED_97[24];
10729 __IO uint16_t TXDQSDLYTG0_U0_P2; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x4001A0 */
10730 __IO uint16_t TXDQSDLYTG1_U0_P2; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x4001A2 */
10731 __IO uint16_t TXDQSDLYTG2_U0_P2; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x4001A4 */
10732 __IO uint16_t TXDQSDLYTG3_U0_P2; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x4001A6 */
10733 uint8_t RESERVED_98[218];
10734 __IO uint16_t TXIMPEDANCECTRL0_B1_P2; /**< Data TX impedance controls, offset: 0x400282 */
10735 uint8_t RESERVED_99[2];
10736 __IO uint16_t DQDQSRCVCNTRL_B1_P2; /**< Dq/Dqs receiver control, offset: 0x400286 */
10737 uint8_t RESERVED_100[10];
10738 __IO uint16_t TXIMPEDANCECTRL1_B1_P2; /**< TX impedance controls, offset: 0x400292 */
10739 uint8_t RESERVED_101[2];
10740 __IO uint16_t TXIMPEDANCECTRL2_B1_P2; /**< TX equalization impedance controls, offset: 0x400296 */
10741 uint8_t RESERVED_102[2];
10742 __IO uint16_t TXODTDRVSTREN_B1_P2; /**< TX ODT driver strength control, offset: 0x40029A */
10743 uint8_t RESERVED_103[34];
10744 __IO uint16_t TXSLEWRATE_B1_P2; /**< TX slew rate controls, offset: 0x4002BE */
10745 uint8_t RESERVED_104[64];
10746 __IO uint16_t RXENDLYTG0_U1_P2; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x400300 */
10747 __IO uint16_t RXENDLYTG1_U1_P2; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x400302 */
10748 __IO uint16_t RXENDLYTG2_U1_P2; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x400304 */
10749 __IO uint16_t RXENDLYTG3_U1_P2; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x400306 */
10750 uint8_t RESERVED_105[16];
10751 __IO uint16_t RXCLKDLYTG0_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x400318 */
10752 __IO uint16_t RXCLKDLYTG1_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x40031A */
10753 __IO uint16_t RXCLKDLYTG2_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x40031C */
10754 __IO uint16_t RXCLKDLYTG3_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x40031E */
10755 __IO uint16_t RXCLKCDLYTG0_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400320 */
10756 __IO uint16_t RXCLKCDLYTG1_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400322 */
10757 __IO uint16_t RXCLKCDLYTG2_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x400324 */
10758 uint8_t RESERVED_106[2];
10759 __IO uint16_t RXCLKCDLYTG3_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x400328 */
10760 uint8_t RESERVED_107[86];
10761 __IO uint16_t TXDQDLYTG0_R1_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400380 */
10762 __IO uint16_t TXDQDLYTG1_R1_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400382 */
10763 __IO uint16_t TXDQDLYTG2_R1_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400384 */
10764 __IO uint16_t TXDQDLYTG3_R1_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400386 */
10765 uint8_t RESERVED_108[24];
10766 __IO uint16_t TXDQSDLYTG0_U1_P2; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x4003A0 */
10767 __IO uint16_t TXDQSDLYTG1_U1_P2; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x4003A2 */
10768 __IO uint16_t TXDQSDLYTG2_U1_P2; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x4003A4 */
10769 __IO uint16_t TXDQSDLYTG3_U1_P2; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x4003A6 */
10770 uint8_t RESERVED_109[472];
10771 __IO uint16_t TXDQDLYTG0_R2_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400580 */
10772 __IO uint16_t TXDQDLYTG1_R2_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400582 */
10773 __IO uint16_t TXDQDLYTG2_R2_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400584 */
10774 __IO uint16_t TXDQDLYTG3_R2_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400586 */
10775 uint8_t RESERVED_110[504];
10776 __IO uint16_t TXDQDLYTG0_R3_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400780 */
10777 __IO uint16_t TXDQDLYTG1_R3_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400782 */
10778 __IO uint16_t TXDQDLYTG2_R3_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400784 */
10779 __IO uint16_t TXDQDLYTG3_R3_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400786 */
10780 uint8_t RESERVED_111[504];
10781 __IO uint16_t TXDQDLYTG0_R4_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400980 */
10782 __IO uint16_t TXDQDLYTG1_R4_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400982 */
10783 __IO uint16_t TXDQDLYTG2_R4_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400984 */
10784 __IO uint16_t TXDQDLYTG3_R4_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400986 */
10785 uint8_t RESERVED_112[504];
10786 __IO uint16_t TXDQDLYTG0_R5_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400B80 */
10787 __IO uint16_t TXDQDLYTG1_R5_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400B82 */
10788 __IO uint16_t TXDQDLYTG2_R5_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400B84 */
10789 __IO uint16_t TXDQDLYTG3_R5_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400B86 */
10790 uint8_t RESERVED_113[504];
10791 __IO uint16_t TXDQDLYTG0_R6_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400D80 */
10792 __IO uint16_t TXDQDLYTG1_R6_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400D82 */
10793 __IO uint16_t TXDQDLYTG2_R6_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400D84 */
10794 __IO uint16_t TXDQDLYTG3_R6_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400D86 */
10795 uint8_t RESERVED_114[504];
10796 __IO uint16_t TXDQDLYTG0_R7_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400F80 */
10797 __IO uint16_t TXDQDLYTG1_R7_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400F82 */
10798 __IO uint16_t TXDQDLYTG2_R7_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400F84 */
10799 __IO uint16_t TXDQDLYTG3_R7_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400F86 */
10800 uint8_t RESERVED_115[504];
10801 __IO uint16_t TXDQDLYTG0_R8_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x401180 */
10802 __IO uint16_t TXDQDLYTG1_R8_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x401182 */
10803 __IO uint16_t TXDQDLYTG2_R8_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x401184 */
10804 __IO uint16_t TXDQDLYTG3_R8_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x401186 */
10805 uint8_t RESERVED_116[2092728];
10806 __IO uint16_t DFIMRL_P3; /**< DFI MaxReadLatency, offset: 0x600040 */
10807 uint8_t RESERVED_117[64];
10808 __IO uint16_t TXIMPEDANCECTRL0_B0_P3; /**< Data TX impedance controls, offset: 0x600082 */
10809 uint8_t RESERVED_118[2];
10810 __IO uint16_t DQDQSRCVCNTRL_B0_P3; /**< Dq/Dqs receiver control, offset: 0x600086 */
10811 uint8_t RESERVED_119[8];
10812 __IO uint16_t TXEQUALIZATIONMODE_P3; /**< Tx dq driver equalization mode controls., offset: 0x600090 */
10813 __IO uint16_t TXIMPEDANCECTRL1_B0_P3; /**< TX impedance controls, offset: 0x600092 */
10814 uint8_t RESERVED_120[2];
10815 __IO uint16_t TXIMPEDANCECTRL2_B0_P3; /**< TX equalization impedance controls, offset: 0x600096 */
10816 __IO uint16_t DQDQSRCVCNTRL2_P3; /**< Dq/Dqs receiver control, offset: 0x600098 */
10817 __IO uint16_t TXODTDRVSTREN_B0_P3; /**< TX ODT driver strength control, offset: 0x60009A */
10818 uint8_t RESERVED_121[34];
10819 __IO uint16_t TXSLEWRATE_B0_P3; /**< TX slew rate controls, offset: 0x6000BE */
10820 uint8_t RESERVED_122[64];
10821 __IO uint16_t RXENDLYTG0_U0_P3; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x600100 */
10822 __IO uint16_t RXENDLYTG1_U0_P3; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x600102 */
10823 __IO uint16_t RXENDLYTG2_U0_P3; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x600104 */
10824 __IO uint16_t RXENDLYTG3_U0_P3; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x600106 */
10825 uint8_t RESERVED_123[16];
10826 __IO uint16_t RXCLKDLYTG0_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x600118 */
10827 __IO uint16_t RXCLKDLYTG1_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x60011A */
10828 __IO uint16_t RXCLKDLYTG2_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x60011C */
10829 __IO uint16_t RXCLKDLYTG3_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x60011E */
10830 __IO uint16_t RXCLKCDLYTG0_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600120 */
10831 __IO uint16_t RXCLKCDLYTG1_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600122 */
10832 __IO uint16_t RXCLKCDLYTG2_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x600124 */
10833 uint8_t RESERVED_124[2];
10834 __IO uint16_t RXCLKCDLYTG3_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x600128 */
10835 uint8_t RESERVED_125[50];
10836 __IO uint16_t PPTDQSCNTINVTRNTG0_P3; /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation, offset: 0x60015C */
10837 __IO uint16_t PPTDQSCNTINVTRNTG1_P3; /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation, offset: 0x60015E */
10838 uint8_t RESERVED_126[32];
10839 __IO uint16_t TXDQDLYTG0_R0_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600180 */
10840 __IO uint16_t TXDQDLYTG1_R0_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600182 */
10841 __IO uint16_t TXDQDLYTG2_R0_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600184 */
10842 __IO uint16_t TXDQDLYTG3_R0_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600186 */
10843 uint8_t RESERVED_127[24];
10844 __IO uint16_t TXDQSDLYTG0_U0_P3; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x6001A0 */
10845 __IO uint16_t TXDQSDLYTG1_U0_P3; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x6001A2 */
10846 __IO uint16_t TXDQSDLYTG2_U0_P3; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x6001A4 */
10847 __IO uint16_t TXDQSDLYTG3_U0_P3; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x6001A6 */
10848 uint8_t RESERVED_128[218];
10849 __IO uint16_t TXIMPEDANCECTRL0_B1_P3; /**< Data TX impedance controls, offset: 0x600282 */
10850 uint8_t RESERVED_129[2];
10851 __IO uint16_t DQDQSRCVCNTRL_B1_P3; /**< Dq/Dqs receiver control, offset: 0x600286 */
10852 uint8_t RESERVED_130[10];
10853 __IO uint16_t TXIMPEDANCECTRL1_B1_P3; /**< TX impedance controls, offset: 0x600292 */
10854 uint8_t RESERVED_131[2];
10855 __IO uint16_t TXIMPEDANCECTRL2_B1_P3; /**< TX equalization impedance controls, offset: 0x600296 */
10856 uint8_t RESERVED_132[2];
10857 __IO uint16_t TXODTDRVSTREN_B1_P3; /**< TX ODT driver strength control, offset: 0x60029A */
10858 uint8_t RESERVED_133[34];
10859 __IO uint16_t TXSLEWRATE_B1_P3; /**< TX slew rate controls, offset: 0x6002BE */
10860 uint8_t RESERVED_134[64];
10861 __IO uint16_t RXENDLYTG0_U1_P3; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x600300 */
10862 __IO uint16_t RXENDLYTG1_U1_P3; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x600302 */
10863 __IO uint16_t RXENDLYTG2_U1_P3; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x600304 */
10864 __IO uint16_t RXENDLYTG3_U1_P3; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x600306 */
10865 uint8_t RESERVED_135[16];
10866 __IO uint16_t RXCLKDLYTG0_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x600318 */
10867 __IO uint16_t RXCLKDLYTG1_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x60031A */
10868 __IO uint16_t RXCLKDLYTG2_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x60031C */
10869 __IO uint16_t RXCLKDLYTG3_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x60031E */
10870 __IO uint16_t RXCLKCDLYTG0_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600320 */
10871 __IO uint16_t RXCLKCDLYTG1_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600322 */
10872 __IO uint16_t RXCLKCDLYTG2_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x600324 */
10873 uint8_t RESERVED_136[2];
10874 __IO uint16_t RXCLKCDLYTG3_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x600328 */
10875 uint8_t RESERVED_137[86];
10876 __IO uint16_t TXDQDLYTG0_R1_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600380 */
10877 __IO uint16_t TXDQDLYTG1_R1_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600382 */
10878 __IO uint16_t TXDQDLYTG2_R1_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600384 */
10879 __IO uint16_t TXDQDLYTG3_R1_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600386 */
10880 uint8_t RESERVED_138[24];
10881 __IO uint16_t TXDQSDLYTG0_U1_P3; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x6003A0 */
10882 __IO uint16_t TXDQSDLYTG1_U1_P3; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x6003A2 */
10883 __IO uint16_t TXDQSDLYTG2_U1_P3; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x6003A4 */
10884 __IO uint16_t TXDQSDLYTG3_U1_P3; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x6003A6 */
10885 uint8_t RESERVED_139[472];
10886 __IO uint16_t TXDQDLYTG0_R2_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600580 */
10887 __IO uint16_t TXDQDLYTG1_R2_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600582 */
10888 __IO uint16_t TXDQDLYTG2_R2_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600584 */
10889 __IO uint16_t TXDQDLYTG3_R2_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600586 */
10890 uint8_t RESERVED_140[504];
10891 __IO uint16_t TXDQDLYTG0_R3_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600780 */
10892 __IO uint16_t TXDQDLYTG1_R3_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600782 */
10893 __IO uint16_t TXDQDLYTG2_R3_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600784 */
10894 __IO uint16_t TXDQDLYTG3_R3_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600786 */
10895 uint8_t RESERVED_141[504];
10896 __IO uint16_t TXDQDLYTG0_R4_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600980 */
10897 __IO uint16_t TXDQDLYTG1_R4_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600982 */
10898 __IO uint16_t TXDQDLYTG2_R4_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600984 */
10899 __IO uint16_t TXDQDLYTG3_R4_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600986 */
10900 uint8_t RESERVED_142[504];
10901 __IO uint16_t TXDQDLYTG0_R5_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600B80 */
10902 __IO uint16_t TXDQDLYTG1_R5_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600B82 */
10903 __IO uint16_t TXDQDLYTG2_R5_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600B84 */
10904 __IO uint16_t TXDQDLYTG3_R5_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600B86 */
10905 uint8_t RESERVED_143[504];
10906 __IO uint16_t TXDQDLYTG0_R6_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600D80 */
10907 __IO uint16_t TXDQDLYTG1_R6_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600D82 */
10908 __IO uint16_t TXDQDLYTG2_R6_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600D84 */
10909 __IO uint16_t TXDQDLYTG3_R6_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600D86 */
10910 uint8_t RESERVED_144[504];
10911 __IO uint16_t TXDQDLYTG0_R7_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600F80 */
10912 __IO uint16_t TXDQDLYTG1_R7_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600F82 */
10913 __IO uint16_t TXDQDLYTG2_R7_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600F84 */
10914 __IO uint16_t TXDQDLYTG3_R7_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600F86 */
10915 uint8_t RESERVED_145[504];
10916 __IO uint16_t TXDQDLYTG0_R8_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x601180 */
10917 __IO uint16_t TXDQDLYTG1_R8_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x601182 */
10918 __IO uint16_t TXDQDLYTG2_R8_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x601184 */
10919 __IO uint16_t TXDQDLYTG3_R8_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x601186 */
10920} DWC_DDRPHYA_DBYTE_Type;
10921
10922/* ----------------------------------------------------------------------------
10923 -- DWC_DDRPHYA_DBYTE Register Masks
10924 ---------------------------------------------------------------------------- */
10925
10926/*!
10927 * @addtogroup DWC_DDRPHYA_DBYTE_Register_Masks DWC_DDRPHYA_DBYTE Register Masks
10928 * @{
10929 */
10930
10931/*! @name DBYTEMISCMODE - DBYTE Module Disable */
10932/*! @{ */
10933#define DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DByteDisable_MASK (0x4U)
10934#define DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DByteDisable_SHIFT (2U)
10935#define DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DByteDisable(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DByteDisable_SHIFT)) & DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DByteDisable_MASK)
10936/*! @} */
10937
10938/*! @name MTESTMUXSEL - Digital Observation Pin control */
10939/*! @{ */
10940#define DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MtestMuxSel_MASK (0x3FU)
10941#define DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MtestMuxSel_SHIFT (0U)
10942#define DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MtestMuxSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MtestMuxSel_SHIFT)) & DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MtestMuxSel_MASK)
10943/*! @} */
10944
10945/*! @name DFIMRL_P0 - DFI MaxReadLatency */
10946/*! @{ */
10947#define DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_p0_MASK (0x1FU)
10948#define DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_p0_SHIFT (0U)
10949#define DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_p0_SHIFT)) & DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_p0_MASK)
10950/*! @} */
10951
10952/*! @name VREFDAC1_R0 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
10953/*! @{ */
10954#define DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VrefDAC1_rx_MASK (0x7FU)
10955#define DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VrefDAC1_rx_SHIFT (0U)
10956#define DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VrefDAC1_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VrefDAC1_rx_MASK)
10957/*! @} */
10958
10959/*! @name VREFDAC0_R0 - VrefDAC0 control for DQ Receiver */
10960/*! @{ */
10961#define DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VrefDAC0_rx_MASK (0x7FU)
10962#define DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VrefDAC0_rx_SHIFT (0U)
10963#define DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VrefDAC0_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VrefDAC0_rx_MASK)
10964/*! @} */
10965
10966/*! @name TXIMPEDANCECTRL0_B0_P0 - Data TX impedance controls */
10967/*! @{ */
10968#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqP_MASK (0x3FU)
10969#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqP_SHIFT (0U)
10970#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqP_MASK)
10971#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqN_MASK (0xFC0U)
10972#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqN_SHIFT (6U)
10973#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqN_MASK)
10974/*! @} */
10975
10976/*! @name DQDQSRCVCNTRL_B0_P0 - Dq/Dqs receiver control */
10977/*! @{ */
10978#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SelAnalogVref_MASK (0x1U)
10979#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SelAnalogVref_SHIFT (0U)
10980#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SelAnalogVref_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SelAnalogVref_MASK)
10981#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_ExtVrefRange_MASK (0x2U)
10982#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_ExtVrefRange_SHIFT (1U)
10983#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_ExtVrefRange_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_ExtVrefRange_MASK)
10984#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DfeCtrl_MASK (0xCU)
10985#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DfeCtrl_SHIFT (2U)
10986#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DfeCtrl_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DfeCtrl_MASK)
10987#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MajorModeDbyte_MASK (0x70U)
10988#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MajorModeDbyte_SHIFT (4U)
10989#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MajorModeDbyte_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MajorModeDbyte_MASK)
10990#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GainCurrAdj_MASK (0xF80U)
10991#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GainCurrAdj_SHIFT (7U)
10992#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GainCurrAdj_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GainCurrAdj_MASK)
10993/*! @} */
10994
10995/*! @name TXEQUALIZATIONMODE_P0 - Tx dq driver equalization mode controls. */
10996/*! @{ */
10997#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TxEqMode_MASK (0x3U)
10998#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TxEqMode_SHIFT (0U)
10999#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TxEqMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TxEqMode_SHIFT)) & DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TxEqMode_MASK)
11000/*! @} */
11001
11002/*! @name TXIMPEDANCECTRL1_B0_P0 - TX impedance controls */
11003/*! @{ */
11004#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqP_MASK (0x3FU)
11005#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqP_SHIFT (0U)
11006#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqP_MASK)
11007#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqN_MASK (0xFC0U)
11008#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqN_SHIFT (6U)
11009#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqN_MASK)
11010/*! @} */
11011
11012/*! @name DQDQSRCVCNTRL1 - Dq/Dqs receiver control */
11013/*! @{ */
11014#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvr_MASK (0x1FFU)
11015#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvr_SHIFT (0U)
11016#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvr_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvr_MASK)
11017#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvrDqs_MASK (0x200U)
11018#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvrDqs_SHIFT (9U)
11019#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvrDqs(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvrDqs_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvrDqs_MASK)
11020#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RxPadStandbyEn_MASK (0x400U)
11021#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RxPadStandbyEn_SHIFT (10U)
11022#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RxPadStandbyEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RxPadStandbyEn_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RxPadStandbyEn_MASK)
11023#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_EnLPReqPDR_MASK (0x800U)
11024#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_EnLPReqPDR_SHIFT (11U)
11025#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_EnLPReqPDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_EnLPReqPDR_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_EnLPReqPDR_MASK)
11026/*! @} */
11027
11028/*! @name TXIMPEDANCECTRL2_B0_P0 - TX equalization impedance controls */
11029/*! @{ */
11030#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQHiDqP_MASK (0x3FU)
11031#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQHiDqP_SHIFT (0U)
11032#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQHiDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQHiDqP_MASK)
11033#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQLoDqN_MASK (0xFC0U)
11034#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQLoDqN_SHIFT (6U)
11035#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQLoDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQLoDqN_MASK)
11036/*! @} */
11037
11038/*! @name DQDQSRCVCNTRL2_P0 - Dq/Dqs receiver control */
11039/*! @{ */
11040#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_EnRxAgressivePDR_MASK (0x1U)
11041#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_EnRxAgressivePDR_SHIFT (0U)
11042#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_EnRxAgressivePDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_EnRxAgressivePDR_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_EnRxAgressivePDR_MASK)
11043/*! @} */
11044
11045/*! @name TXODTDRVSTREN_B0_P0 - TX ODT driver strength control */
11046/*! @{ */
11047#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenP_MASK (0x3FU)
11048#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenP_SHIFT (0U)
11049#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenP_MASK)
11050#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenN_MASK (0xFC0U)
11051#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenN_SHIFT (6U)
11052#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenN_MASK)
11053/*! @} */
11054
11055/*! @name RXFIFOCHECKSTATUS - Status of RX FIFO Consistency Checks */
11056/*! @{ */
11057#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocErr_MASK (0x1U)
11058#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocErr_SHIFT (0U)
11059#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocErr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocErr_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocErr_MASK)
11060#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocErr_MASK (0x2U)
11061#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocErr_SHIFT (1U)
11062#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocErr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocErr_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocErr_MASK)
11063#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocUErr_MASK (0x4U)
11064#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocUErr_SHIFT (2U)
11065#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocUErr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocUErr_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocUErr_MASK)
11066#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocUErr_MASK (0x8U)
11067#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocUErr_SHIFT (3U)
11068#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocUErr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocUErr_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocUErr_MASK)
11069/*! @} */
11070
11071/*! @name RXFIFOCHECKERRVALUES - Contains the captured values associated with an RxFifo consistency error */
11072/*! @{ */
11073#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocErrValue_MASK (0xFU)
11074#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocErrValue_SHIFT (0U)
11075#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocErrValue(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocErrValue_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocErrValue_MASK)
11076#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocErrValue_MASK (0xF0U)
11077#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocErrValue_SHIFT (4U)
11078#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocErrValue(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocErrValue_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocErrValue_MASK)
11079#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocUErrValue_MASK (0xF00U)
11080#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocUErrValue_SHIFT (8U)
11081#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocUErrValue(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocUErrValue_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocUErrValue_MASK)
11082#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocUErrValue_MASK (0xF000U)
11083#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocUErrValue_SHIFT (12U)
11084#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocUErrValue(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocUErrValue_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocUErrValue_MASK)
11085/*! @} */
11086
11087/*! @name RXFIFOINFO - Data Receive FIFO Pointer Values */
11088/*! @{ */
11089#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLoc_MASK (0xFU)
11090#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLoc_SHIFT (0U)
11091#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLoc(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLoc_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLoc_MASK)
11092#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLoc_MASK (0xF0U)
11093#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLoc_SHIFT (4U)
11094#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLoc(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLoc_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLoc_MASK)
11095#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLocU_MASK (0xF00U)
11096#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLocU_SHIFT (8U)
11097#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLocU(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLocU_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLocU_MASK)
11098#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLocU_MASK (0xF000U)
11099#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLocU_SHIFT (12U)
11100#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLocU(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLocU_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLocU_MASK)
11101/*! @} */
11102
11103/*! @name RXFIFOVISIBILITY - RX FIFO visibility */
11104/*! @{ */
11105#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtr_MASK (0x7U)
11106#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtr_SHIFT (0U)
11107#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtr_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtr_MASK)
11108#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtrOvr_MASK (0x8U)
11109#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtrOvr_SHIFT (3U)
11110#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtrOvr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtrOvr_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtrOvr_MASK)
11111#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdEn_MASK (0x10U)
11112#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdEn_SHIFT (4U)
11113#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdEn_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdEn_MASK)
11114/*! @} */
11115
11116/*! @name RXFIFOCONTENTSDQ3210 - RX FIFO contents, lane[3:0] */
11117/*! @{ */
11118#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RxFifoContentsDQ3210_MASK (0xFFFFU)
11119#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RxFifoContentsDQ3210_SHIFT (0U)
11120#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RxFifoContentsDQ3210(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RxFifoContentsDQ3210_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RxFifoContentsDQ3210_MASK)
11121/*! @} */
11122
11123/*! @name RXFIFOCONTENTSDQ7654 - RX FIFO contents, lane[7:4] */
11124/*! @{ */
11125#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RxFifoContentsDQ7654_MASK (0xFFFFU)
11126#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RxFifoContentsDQ7654_SHIFT (0U)
11127#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RxFifoContentsDQ7654(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RxFifoContentsDQ7654_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RxFifoContentsDQ7654_MASK)
11128/*! @} */
11129
11130/*! @name RXFIFOCONTENTSDBI - RX FIFO contents, dbi */
11131/*! @{ */
11132#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RxFifoContentsDBI_MASK (0xFU)
11133#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RxFifoContentsDBI_SHIFT (0U)
11134#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RxFifoContentsDBI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RxFifoContentsDBI_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RxFifoContentsDBI_MASK)
11135/*! @} */
11136
11137/*! @name TXSLEWRATE_B0_P0 - TX slew rate controls */
11138/*! @{ */
11139#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreP_MASK (0xFU)
11140#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreP_SHIFT (0U)
11141#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreP_MASK)
11142#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreN_MASK (0xF0U)
11143#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreN_SHIFT (4U)
11144#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreN_MASK)
11145#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreDrvMode_MASK (0x700U)
11146#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreDrvMode_SHIFT (8U)
11147#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreDrvMode_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreDrvMode_MASK)
11148/*! @} */
11149
11150/*! @name RXPBDLYTG0_R0 - Read DQ per-bit BDL delay (Timing Group 0). */
11151/*! @{ */
11152#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RxPBDlyTg0_rx_MASK (0x7FU)
11153#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RxPBDlyTg0_rx_SHIFT (0U)
11154#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RxPBDlyTg0_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RxPBDlyTg0_rx_MASK)
11155/*! @} */
11156
11157/*! @name RXPBDLYTG1_R0 - Read DQ per-bit BDL delay (Timing Group 1). */
11158/*! @{ */
11159#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RxPBDlyTg1_rx_MASK (0x7FU)
11160#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RxPBDlyTg1_rx_SHIFT (0U)
11161#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RxPBDlyTg1_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RxPBDlyTg1_rx_MASK)
11162/*! @} */
11163
11164/*! @name RXPBDLYTG2_R0 - Read DQ per-bit BDL delay (Timing Group 2). */
11165/*! @{ */
11166#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RxPBDlyTg2_rx_MASK (0x7FU)
11167#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RxPBDlyTg2_rx_SHIFT (0U)
11168#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RxPBDlyTg2_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RxPBDlyTg2_rx_MASK)
11169/*! @} */
11170
11171/*! @name RXPBDLYTG3_R0 - Read DQ per-bit BDL delay (Timing Group 3). */
11172/*! @{ */
11173#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RxPBDlyTg3_rx_MASK (0x7FU)
11174#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RxPBDlyTg3_rx_SHIFT (0U)
11175#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RxPBDlyTg3_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RxPBDlyTg3_rx_MASK)
11176/*! @} */
11177
11178/*! @name RXENDLYTG0_U0_P0 - Trained Receive Enable Delay (For Timing Group 0) */
11179/*! @{ */
11180#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RxEnDlyTg0_un_px_MASK (0x7FFU)
11181#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RxEnDlyTg0_un_px_SHIFT (0U)
11182#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RxEnDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RxEnDlyTg0_un_px_MASK)
11183/*! @} */
11184
11185/*! @name RXENDLYTG1_U0_P0 - Trained Receive Enable Delay (For Timing Group 1) */
11186/*! @{ */
11187#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RxEnDlyTg1_un_px_MASK (0x7FFU)
11188#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RxEnDlyTg1_un_px_SHIFT (0U)
11189#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RxEnDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RxEnDlyTg1_un_px_MASK)
11190/*! @} */
11191
11192/*! @name RXENDLYTG2_U0_P0 - Trained Receive Enable Delay (For Timing Group 2) */
11193/*! @{ */
11194#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RxEnDlyTg2_un_px_MASK (0x7FFU)
11195#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RxEnDlyTg2_un_px_SHIFT (0U)
11196#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RxEnDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RxEnDlyTg2_un_px_MASK)
11197/*! @} */
11198
11199/*! @name RXENDLYTG3_U0_P0 - Trained Receive Enable Delay (For Timing Group 3) */
11200/*! @{ */
11201#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RxEnDlyTg3_un_px_MASK (0x7FFU)
11202#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RxEnDlyTg3_un_px_SHIFT (0U)
11203#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RxEnDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RxEnDlyTg3_un_px_MASK)
11204/*! @} */
11205
11206/*! @name RXCLKDLYTG0_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
11207/*! @{ */
11208#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RxClkDlyTg0_un_px_MASK (0x3FU)
11209#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RxClkDlyTg0_un_px_SHIFT (0U)
11210#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RxClkDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RxClkDlyTg0_un_px_MASK)
11211/*! @} */
11212
11213/*! @name RXCLKDLYTG1_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
11214/*! @{ */
11215#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RxClkDlyTg1_un_px_MASK (0x3FU)
11216#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RxClkDlyTg1_un_px_SHIFT (0U)
11217#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RxClkDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RxClkDlyTg1_un_px_MASK)
11218/*! @} */
11219
11220/*! @name RXCLKDLYTG2_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
11221/*! @{ */
11222#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RxClkDlyTg2_un_px_MASK (0x3FU)
11223#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RxClkDlyTg2_un_px_SHIFT (0U)
11224#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RxClkDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RxClkDlyTg2_un_px_MASK)
11225/*! @} */
11226
11227/*! @name RXCLKDLYTG3_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
11228/*! @{ */
11229#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RxClkDlyTg3_un_px_MASK (0x3FU)
11230#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RxClkDlyTg3_un_px_SHIFT (0U)
11231#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RxClkDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RxClkDlyTg3_un_px_MASK)
11232/*! @} */
11233
11234/*! @name RXCLKCDLYTG0_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
11235/*! @{ */
11236#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RxClkcDlyTg0_un_px_MASK (0x3FU)
11237#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RxClkcDlyTg0_un_px_SHIFT (0U)
11238#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RxClkcDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RxClkcDlyTg0_un_px_MASK)
11239/*! @} */
11240
11241/*! @name RXCLKCDLYTG1_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
11242/*! @{ */
11243#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RxClkcDlyTg1_un_px_MASK (0x3FU)
11244#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RxClkcDlyTg1_un_px_SHIFT (0U)
11245#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RxClkcDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RxClkcDlyTg1_un_px_MASK)
11246/*! @} */
11247
11248/*! @name RXCLKCDLYTG2_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
11249/*! @{ */
11250#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RxClkcDlyTg2_un_px_MASK (0x3FU)
11251#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RxClkcDlyTg2_un_px_SHIFT (0U)
11252#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RxClkcDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RxClkcDlyTg2_un_px_MASK)
11253/*! @} */
11254
11255/*! @name RXCLKCDLYTG3_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
11256/*! @{ */
11257#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RxClkcDlyTg3_un_px_MASK (0x3FU)
11258#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RxClkcDlyTg3_un_px_SHIFT (0U)
11259#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RxClkcDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RxClkcDlyTg3_un_px_MASK)
11260/*! @} */
11261
11262/*! @name DQLNSEL - Maps Phy DQ lane to memory DQ0 */
11263/*! @{ */
11264#define DWC_DDRPHYA_DBYTE_DQLNSEL_DqLnSel_MASK (0x7U)
11265#define DWC_DDRPHYA_DBYTE_DQLNSEL_DqLnSel_SHIFT (0U)
11266#define DWC_DDRPHYA_DBYTE_DQLNSEL_DqLnSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQLNSEL_DqLnSel_SHIFT)) & DWC_DDRPHYA_DBYTE_DQLNSEL_DqLnSel_MASK)
11267/*! @} */
11268
11269/* The count of DWC_DDRPHYA_DBYTE_DQLNSEL */
11270#define DWC_DDRPHYA_DBYTE_DQLNSEL_COUNT (8U)
11271
11272/*! @name TXDQDLYTG0_R0_P0 - Write DQ Delay (Timing Group 0). */
11273/*! @{ */
11274#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU)
11275#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TxDqDlyTg0_rn_px_SHIFT (0U)
11276#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TxDqDlyTg0_rn_px_MASK)
11277/*! @} */
11278
11279/*! @name TXDQDLYTG1_R0_P0 - Write DQ Delay (Timing Group 1). */
11280/*! @{ */
11281#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU)
11282#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TxDqDlyTg1_rn_px_SHIFT (0U)
11283#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TxDqDlyTg1_rn_px_MASK)
11284/*! @} */
11285
11286/*! @name TXDQDLYTG2_R0_P0 - Write DQ Delay (Timing Group 2). */
11287/*! @{ */
11288#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU)
11289#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TxDqDlyTg2_rn_px_SHIFT (0U)
11290#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TxDqDlyTg2_rn_px_MASK)
11291/*! @} */
11292
11293/*! @name TXDQDLYTG3_R0_P0 - Write DQ Delay (Timing Group 3). */
11294/*! @{ */
11295#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU)
11296#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TxDqDlyTg3_rn_px_SHIFT (0U)
11297#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TxDqDlyTg3_rn_px_MASK)
11298/*! @} */
11299
11300/*! @name TXDQSDLYTG0_U0_P0 - Write DQS Delay (Timing Group DEST=0). */
11301/*! @{ */
11302#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TxDqsDlyTg0_un_px_MASK (0x3FFU)
11303#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TxDqsDlyTg0_un_px_SHIFT (0U)
11304#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TxDqsDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TxDqsDlyTg0_un_px_MASK)
11305/*! @} */
11306
11307/*! @name TXDQSDLYTG1_U0_P0 - Write DQS Delay (Timing Group DEST=1). */
11308/*! @{ */
11309#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TxDqsDlyTg1_un_px_MASK (0x3FFU)
11310#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TxDqsDlyTg1_un_px_SHIFT (0U)
11311#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TxDqsDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TxDqsDlyTg1_un_px_MASK)
11312/*! @} */
11313
11314/*! @name TXDQSDLYTG2_U0_P0 - Write DQS Delay (Timing Group DEST=2). */
11315/*! @{ */
11316#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TxDqsDlyTg2_un_px_MASK (0x3FFU)
11317#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TxDqsDlyTg2_un_px_SHIFT (0U)
11318#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TxDqsDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TxDqsDlyTg2_un_px_MASK)
11319/*! @} */
11320
11321/*! @name TXDQSDLYTG3_U0_P0 - Write DQS Delay (Timing Group DEST=3). */
11322/*! @{ */
11323#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TxDqsDlyTg3_un_px_MASK (0x3FFU)
11324#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TxDqsDlyTg3_un_px_SHIFT (0U)
11325#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TxDqsDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TxDqsDlyTg3_un_px_MASK)
11326/*! @} */
11327
11328/*! @name DXLCDLSTATUS - Debug status of the DBYTE LCDL */
11329/*! @{ */
11330#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlFineSnapVal_MASK (0x3FFU)
11331#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlFineSnapVal_SHIFT (0U)
11332#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlFineSnapVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlFineSnapVal_SHIFT)) & DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlFineSnapVal_MASK)
11333#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlPhdSnapVal_MASK (0x400U)
11334#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlPhdSnapVal_SHIFT (10U)
11335#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlPhdSnapVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlPhdSnapVal_SHIFT)) & DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlPhdSnapVal_MASK)
11336#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyLock_MASK (0x800U)
11337#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyLock_SHIFT (11U)
11338#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyLock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyLock_SHIFT)) & DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyLock_MASK)
11339#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyUnlock_MASK (0x1000U)
11340#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyUnlock_SHIFT (12U)
11341#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyUnlock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyUnlock_SHIFT)) & DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyUnlock_MASK)
11342#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlLiveLock_MASK (0x2000U)
11343#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlLiveLock_SHIFT (13U)
11344#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlLiveLock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlLiveLock_SHIFT)) & DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlLiveLock_MASK)
11345/*! @} */
11346
11347/*! @name VREFDAC1_R1 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
11348/*! @{ */
11349#define DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VrefDAC1_rx_MASK (0x7FU)
11350#define DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VrefDAC1_rx_SHIFT (0U)
11351#define DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VrefDAC1_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VrefDAC1_rx_MASK)
11352/*! @} */
11353
11354/*! @name VREFDAC0_R1 - VrefDAC0 control for DQ Receiver */
11355/*! @{ */
11356#define DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VrefDAC0_rx_MASK (0x7FU)
11357#define DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VrefDAC0_rx_SHIFT (0U)
11358#define DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VrefDAC0_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VrefDAC0_rx_MASK)
11359/*! @} */
11360
11361/*! @name TXIMPEDANCECTRL0_B1_P0 - Data TX impedance controls */
11362/*! @{ */
11363#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqP_MASK (0x3FU)
11364#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqP_SHIFT (0U)
11365#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqP_MASK)
11366#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqN_MASK (0xFC0U)
11367#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqN_SHIFT (6U)
11368#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqN_MASK)
11369/*! @} */
11370
11371/*! @name DQDQSRCVCNTRL_B1_P0 - Dq/Dqs receiver control */
11372/*! @{ */
11373#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SelAnalogVref_MASK (0x1U)
11374#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SelAnalogVref_SHIFT (0U)
11375#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SelAnalogVref_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SelAnalogVref_MASK)
11376#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_ExtVrefRange_MASK (0x2U)
11377#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_ExtVrefRange_SHIFT (1U)
11378#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_ExtVrefRange_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_ExtVrefRange_MASK)
11379#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DfeCtrl_MASK (0xCU)
11380#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DfeCtrl_SHIFT (2U)
11381#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DfeCtrl_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DfeCtrl_MASK)
11382#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MajorModeDbyte_MASK (0x70U)
11383#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MajorModeDbyte_SHIFT (4U)
11384#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MajorModeDbyte_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MajorModeDbyte_MASK)
11385#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GainCurrAdj_MASK (0xF80U)
11386#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GainCurrAdj_SHIFT (7U)
11387#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GainCurrAdj_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GainCurrAdj_MASK)
11388/*! @} */
11389
11390/*! @name TXIMPEDANCECTRL1_B1_P0 - TX impedance controls */
11391/*! @{ */
11392#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqP_MASK (0x3FU)
11393#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqP_SHIFT (0U)
11394#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqP_MASK)
11395#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqN_MASK (0xFC0U)
11396#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqN_SHIFT (6U)
11397#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqN_MASK)
11398/*! @} */
11399
11400/*! @name TXIMPEDANCECTRL2_B1_P0 - TX equalization impedance controls */
11401/*! @{ */
11402#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQHiDqP_MASK (0x3FU)
11403#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQHiDqP_SHIFT (0U)
11404#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQHiDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQHiDqP_MASK)
11405#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQLoDqN_MASK (0xFC0U)
11406#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQLoDqN_SHIFT (6U)
11407#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQLoDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQLoDqN_MASK)
11408/*! @} */
11409
11410/*! @name TXODTDRVSTREN_B1_P0 - TX ODT driver strength control */
11411/*! @{ */
11412#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenP_MASK (0x3FU)
11413#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenP_SHIFT (0U)
11414#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenP_MASK)
11415#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenN_MASK (0xFC0U)
11416#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenN_SHIFT (6U)
11417#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenN_MASK)
11418/*! @} */
11419
11420/*! @name TXSLEWRATE_B1_P0 - TX slew rate controls */
11421/*! @{ */
11422#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreP_MASK (0xFU)
11423#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreP_SHIFT (0U)
11424#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreP_MASK)
11425#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreN_MASK (0xF0U)
11426#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreN_SHIFT (4U)
11427#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreN_MASK)
11428#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreDrvMode_MASK (0x700U)
11429#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreDrvMode_SHIFT (8U)
11430#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreDrvMode_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreDrvMode_MASK)
11431/*! @} */
11432
11433/*! @name RXPBDLYTG0_R1 - Read DQ per-bit BDL delay (Timing Group 0). */
11434/*! @{ */
11435#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RxPBDlyTg0_rx_MASK (0x7FU)
11436#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RxPBDlyTg0_rx_SHIFT (0U)
11437#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RxPBDlyTg0_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RxPBDlyTg0_rx_MASK)
11438/*! @} */
11439
11440/*! @name RXPBDLYTG1_R1 - Read DQ per-bit BDL delay (Timing Group 1). */
11441/*! @{ */
11442#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RxPBDlyTg1_rx_MASK (0x7FU)
11443#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RxPBDlyTg1_rx_SHIFT (0U)
11444#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RxPBDlyTg1_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RxPBDlyTg1_rx_MASK)
11445/*! @} */
11446
11447/*! @name RXPBDLYTG2_R1 - Read DQ per-bit BDL delay (Timing Group 2). */
11448/*! @{ */
11449#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RxPBDlyTg2_rx_MASK (0x7FU)
11450#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RxPBDlyTg2_rx_SHIFT (0U)
11451#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RxPBDlyTg2_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RxPBDlyTg2_rx_MASK)
11452/*! @} */
11453
11454/*! @name RXPBDLYTG3_R1 - Read DQ per-bit BDL delay (Timing Group 3). */
11455/*! @{ */
11456#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RxPBDlyTg3_rx_MASK (0x7FU)
11457#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RxPBDlyTg3_rx_SHIFT (0U)
11458#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RxPBDlyTg3_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RxPBDlyTg3_rx_MASK)
11459/*! @} */
11460
11461/*! @name RXENDLYTG0_U1_P0 - Trained Receive Enable Delay (For Timing Group 0) */
11462/*! @{ */
11463#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RxEnDlyTg0_un_px_MASK (0x7FFU)
11464#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RxEnDlyTg0_un_px_SHIFT (0U)
11465#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RxEnDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RxEnDlyTg0_un_px_MASK)
11466/*! @} */
11467
11468/*! @name RXENDLYTG1_U1_P0 - Trained Receive Enable Delay (For Timing Group 1) */
11469/*! @{ */
11470#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RxEnDlyTg1_un_px_MASK (0x7FFU)
11471#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RxEnDlyTg1_un_px_SHIFT (0U)
11472#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RxEnDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RxEnDlyTg1_un_px_MASK)
11473/*! @} */
11474
11475/*! @name RXENDLYTG2_U1_P0 - Trained Receive Enable Delay (For Timing Group 2) */
11476/*! @{ */
11477#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RxEnDlyTg2_un_px_MASK (0x7FFU)
11478#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RxEnDlyTg2_un_px_SHIFT (0U)
11479#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RxEnDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RxEnDlyTg2_un_px_MASK)
11480/*! @} */
11481
11482/*! @name RXENDLYTG3_U1_P0 - Trained Receive Enable Delay (For Timing Group 3) */
11483/*! @{ */
11484#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RxEnDlyTg3_un_px_MASK (0x7FFU)
11485#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RxEnDlyTg3_un_px_SHIFT (0U)
11486#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RxEnDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RxEnDlyTg3_un_px_MASK)
11487/*! @} */
11488
11489/*! @name RXCLKDLYTG0_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
11490/*! @{ */
11491#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RxClkDlyTg0_un_px_MASK (0x3FU)
11492#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RxClkDlyTg0_un_px_SHIFT (0U)
11493#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RxClkDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RxClkDlyTg0_un_px_MASK)
11494/*! @} */
11495
11496/*! @name RXCLKDLYTG1_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
11497/*! @{ */
11498#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RxClkDlyTg1_un_px_MASK (0x3FU)
11499#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RxClkDlyTg1_un_px_SHIFT (0U)
11500#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RxClkDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RxClkDlyTg1_un_px_MASK)
11501/*! @} */
11502
11503/*! @name RXCLKDLYTG2_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
11504/*! @{ */
11505#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RxClkDlyTg2_un_px_MASK (0x3FU)
11506#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RxClkDlyTg2_un_px_SHIFT (0U)
11507#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RxClkDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RxClkDlyTg2_un_px_MASK)
11508/*! @} */
11509
11510/*! @name RXCLKDLYTG3_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
11511/*! @{ */
11512#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RxClkDlyTg3_un_px_MASK (0x3FU)
11513#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RxClkDlyTg3_un_px_SHIFT (0U)
11514#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RxClkDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RxClkDlyTg3_un_px_MASK)
11515/*! @} */
11516
11517/*! @name RXCLKCDLYTG0_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
11518/*! @{ */
11519#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RxClkcDlyTg0_un_px_MASK (0x3FU)
11520#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RxClkcDlyTg0_un_px_SHIFT (0U)
11521#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RxClkcDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RxClkcDlyTg0_un_px_MASK)
11522/*! @} */
11523
11524/*! @name RXCLKCDLYTG1_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
11525/*! @{ */
11526#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RxClkcDlyTg1_un_px_MASK (0x3FU)
11527#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RxClkcDlyTg1_un_px_SHIFT (0U)
11528#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RxClkcDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RxClkcDlyTg1_un_px_MASK)
11529/*! @} */
11530
11531/*! @name RXCLKCDLYTG2_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
11532/*! @{ */
11533#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RxClkcDlyTg2_un_px_MASK (0x3FU)
11534#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RxClkcDlyTg2_un_px_SHIFT (0U)
11535#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RxClkcDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RxClkcDlyTg2_un_px_MASK)
11536/*! @} */
11537
11538/*! @name RXCLKCDLYTG3_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
11539/*! @{ */
11540#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RxClkcDlyTg3_un_px_MASK (0x3FU)
11541#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RxClkcDlyTg3_un_px_SHIFT (0U)
11542#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RxClkcDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RxClkcDlyTg3_un_px_MASK)
11543/*! @} */
11544
11545/*! @name TXDQDLYTG0_R1_P0 - Write DQ Delay (Timing Group 0). */
11546/*! @{ */
11547#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU)
11548#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TxDqDlyTg0_rn_px_SHIFT (0U)
11549#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TxDqDlyTg0_rn_px_MASK)
11550/*! @} */
11551
11552/*! @name TXDQDLYTG1_R1_P0 - Write DQ Delay (Timing Group 1). */
11553/*! @{ */
11554#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU)
11555#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TxDqDlyTg1_rn_px_SHIFT (0U)
11556#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TxDqDlyTg1_rn_px_MASK)
11557/*! @} */
11558
11559/*! @name TXDQDLYTG2_R1_P0 - Write DQ Delay (Timing Group 2). */
11560/*! @{ */
11561#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU)
11562#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TxDqDlyTg2_rn_px_SHIFT (0U)
11563#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TxDqDlyTg2_rn_px_MASK)
11564/*! @} */
11565
11566/*! @name TXDQDLYTG3_R1_P0 - Write DQ Delay (Timing Group 3). */
11567/*! @{ */
11568#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU)
11569#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TxDqDlyTg3_rn_px_SHIFT (0U)
11570#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TxDqDlyTg3_rn_px_MASK)
11571/*! @} */
11572
11573/*! @name TXDQSDLYTG0_U1_P0 - Write DQS Delay (Timing Group DEST=0). */
11574/*! @{ */
11575#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TxDqsDlyTg0_un_px_MASK (0x3FFU)
11576#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TxDqsDlyTg0_un_px_SHIFT (0U)
11577#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TxDqsDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TxDqsDlyTg0_un_px_MASK)
11578/*! @} */
11579
11580/*! @name TXDQSDLYTG1_U1_P0 - Write DQS Delay (Timing Group DEST=1). */
11581/*! @{ */
11582#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TxDqsDlyTg1_un_px_MASK (0x3FFU)
11583#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TxDqsDlyTg1_un_px_SHIFT (0U)
11584#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TxDqsDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TxDqsDlyTg1_un_px_MASK)
11585/*! @} */
11586
11587/*! @name TXDQSDLYTG2_U1_P0 - Write DQS Delay (Timing Group DEST=2). */
11588/*! @{ */
11589#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TxDqsDlyTg2_un_px_MASK (0x3FFU)
11590#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TxDqsDlyTg2_un_px_SHIFT (0U)
11591#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TxDqsDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TxDqsDlyTg2_un_px_MASK)
11592/*! @} */
11593
11594/*! @name TXDQSDLYTG3_U1_P0 - Write DQS Delay (Timing Group DEST=3). */
11595/*! @{ */
11596#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TxDqsDlyTg3_un_px_MASK (0x3FFU)
11597#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TxDqsDlyTg3_un_px_SHIFT (0U)
11598#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TxDqsDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TxDqsDlyTg3_un_px_MASK)
11599/*! @} */
11600
11601/*! @name VREFDAC1_R2 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
11602/*! @{ */
11603#define DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VrefDAC1_rx_MASK (0x7FU)
11604#define DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VrefDAC1_rx_SHIFT (0U)
11605#define DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VrefDAC1_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VrefDAC1_rx_MASK)
11606/*! @} */
11607
11608/*! @name VREFDAC0_R2 - VrefDAC0 control for DQ Receiver */
11609/*! @{ */
11610#define DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VrefDAC0_rx_MASK (0x7FU)
11611#define DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VrefDAC0_rx_SHIFT (0U)
11612#define DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VrefDAC0_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VrefDAC0_rx_MASK)
11613/*! @} */
11614
11615/*! @name RXPBDLYTG0_R2 - Read DQ per-bit BDL delay (Timing Group 0). */
11616/*! @{ */
11617#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RxPBDlyTg0_rx_MASK (0x7FU)
11618#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RxPBDlyTg0_rx_SHIFT (0U)
11619#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RxPBDlyTg0_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RxPBDlyTg0_rx_MASK)
11620/*! @} */
11621
11622/*! @name RXPBDLYTG1_R2 - Read DQ per-bit BDL delay (Timing Group 1). */
11623/*! @{ */
11624#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RxPBDlyTg1_rx_MASK (0x7FU)
11625#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RxPBDlyTg1_rx_SHIFT (0U)
11626#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RxPBDlyTg1_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RxPBDlyTg1_rx_MASK)
11627/*! @} */
11628
11629/*! @name RXPBDLYTG2_R2 - Read DQ per-bit BDL delay (Timing Group 2). */
11630/*! @{ */
11631#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RxPBDlyTg2_rx_MASK (0x7FU)
11632#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RxPBDlyTg2_rx_SHIFT (0U)
11633#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RxPBDlyTg2_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RxPBDlyTg2_rx_MASK)
11634/*! @} */
11635
11636/*! @name RXPBDLYTG3_R2 - Read DQ per-bit BDL delay (Timing Group 3). */
11637/*! @{ */
11638#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RxPBDlyTg3_rx_MASK (0x7FU)
11639#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RxPBDlyTg3_rx_SHIFT (0U)
11640#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RxPBDlyTg3_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RxPBDlyTg3_rx_MASK)
11641/*! @} */
11642
11643/*! @name TXDQDLYTG0_R2_P0 - Write DQ Delay (Timing Group 0). */
11644/*! @{ */
11645#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU)
11646#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TxDqDlyTg0_rn_px_SHIFT (0U)
11647#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TxDqDlyTg0_rn_px_MASK)
11648/*! @} */
11649
11650/*! @name TXDQDLYTG1_R2_P0 - Write DQ Delay (Timing Group 1). */
11651/*! @{ */
11652#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU)
11653#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TxDqDlyTg1_rn_px_SHIFT (0U)
11654#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TxDqDlyTg1_rn_px_MASK)
11655/*! @} */
11656
11657/*! @name TXDQDLYTG2_R2_P0 - Write DQ Delay (Timing Group 2). */
11658/*! @{ */
11659#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU)
11660#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TxDqDlyTg2_rn_px_SHIFT (0U)
11661#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TxDqDlyTg2_rn_px_MASK)
11662/*! @} */
11663
11664/*! @name TXDQDLYTG3_R2_P0 - Write DQ Delay (Timing Group 3). */
11665/*! @{ */
11666#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU)
11667#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TxDqDlyTg3_rn_px_SHIFT (0U)
11668#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TxDqDlyTg3_rn_px_MASK)
11669/*! @} */
11670
11671/*! @name VREFDAC1_R3 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
11672/*! @{ */
11673#define DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VrefDAC1_rx_MASK (0x7FU)
11674#define DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VrefDAC1_rx_SHIFT (0U)
11675#define DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VrefDAC1_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VrefDAC1_rx_MASK)
11676/*! @} */
11677
11678/*! @name VREFDAC0_R3 - VrefDAC0 control for DQ Receiver */
11679/*! @{ */
11680#define DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VrefDAC0_rx_MASK (0x7FU)
11681#define DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VrefDAC0_rx_SHIFT (0U)
11682#define DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VrefDAC0_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VrefDAC0_rx_MASK)
11683/*! @} */
11684
11685/*! @name RXPBDLYTG0_R3 - Read DQ per-bit BDL delay (Timing Group 0). */
11686/*! @{ */
11687#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RxPBDlyTg0_rx_MASK (0x7FU)
11688#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RxPBDlyTg0_rx_SHIFT (0U)
11689#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RxPBDlyTg0_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RxPBDlyTg0_rx_MASK)
11690/*! @} */
11691
11692/*! @name RXPBDLYTG1_R3 - Read DQ per-bit BDL delay (Timing Group 1). */
11693/*! @{ */
11694#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RxPBDlyTg1_rx_MASK (0x7FU)
11695#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RxPBDlyTg1_rx_SHIFT (0U)
11696#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RxPBDlyTg1_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RxPBDlyTg1_rx_MASK)
11697/*! @} */
11698
11699/*! @name RXPBDLYTG2_R3 - Read DQ per-bit BDL delay (Timing Group 2). */
11700/*! @{ */
11701#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RxPBDlyTg2_rx_MASK (0x7FU)
11702#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RxPBDlyTg2_rx_SHIFT (0U)
11703#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RxPBDlyTg2_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RxPBDlyTg2_rx_MASK)
11704/*! @} */
11705
11706/*! @name RXPBDLYTG3_R3 - Read DQ per-bit BDL delay (Timing Group 3). */
11707/*! @{ */
11708#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RxPBDlyTg3_rx_MASK (0x7FU)
11709#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RxPBDlyTg3_rx_SHIFT (0U)
11710#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RxPBDlyTg3_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RxPBDlyTg3_rx_MASK)
11711/*! @} */
11712
11713/*! @name TXDQDLYTG0_R3_P0 - Write DQ Delay (Timing Group 0). */
11714/*! @{ */
11715#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU)
11716#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TxDqDlyTg0_rn_px_SHIFT (0U)
11717#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TxDqDlyTg0_rn_px_MASK)
11718/*! @} */
11719
11720/*! @name TXDQDLYTG1_R3_P0 - Write DQ Delay (Timing Group 1). */
11721/*! @{ */
11722#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU)
11723#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TxDqDlyTg1_rn_px_SHIFT (0U)
11724#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TxDqDlyTg1_rn_px_MASK)
11725/*! @} */
11726
11727/*! @name TXDQDLYTG2_R3_P0 - Write DQ Delay (Timing Group 2). */
11728/*! @{ */
11729#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU)
11730#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TxDqDlyTg2_rn_px_SHIFT (0U)
11731#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TxDqDlyTg2_rn_px_MASK)
11732/*! @} */
11733
11734/*! @name TXDQDLYTG3_R3_P0 - Write DQ Delay (Timing Group 3). */
11735/*! @{ */
11736#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU)
11737#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TxDqDlyTg3_rn_px_SHIFT (0U)
11738#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TxDqDlyTg3_rn_px_MASK)
11739/*! @} */
11740
11741/*! @name VREFDAC1_R4 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
11742/*! @{ */
11743#define DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VrefDAC1_rx_MASK (0x7FU)
11744#define DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VrefDAC1_rx_SHIFT (0U)
11745#define DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VrefDAC1_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VrefDAC1_rx_MASK)
11746/*! @} */
11747
11748/*! @name VREFDAC0_R4 - VrefDAC0 control for DQ Receiver */
11749/*! @{ */
11750#define DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VrefDAC0_rx_MASK (0x7FU)
11751#define DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VrefDAC0_rx_SHIFT (0U)
11752#define DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VrefDAC0_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VrefDAC0_rx_MASK)
11753/*! @} */
11754
11755/*! @name RXPBDLYTG0_R4 - Read DQ per-bit BDL delay (Timing Group 0). */
11756/*! @{ */
11757#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RxPBDlyTg0_rx_MASK (0x7FU)
11758#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RxPBDlyTg0_rx_SHIFT (0U)
11759#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RxPBDlyTg0_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RxPBDlyTg0_rx_MASK)
11760/*! @} */
11761
11762/*! @name RXPBDLYTG1_R4 - Read DQ per-bit BDL delay (Timing Group 1). */
11763/*! @{ */
11764#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RxPBDlyTg1_rx_MASK (0x7FU)
11765#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RxPBDlyTg1_rx_SHIFT (0U)
11766#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RxPBDlyTg1_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RxPBDlyTg1_rx_MASK)
11767/*! @} */
11768
11769/*! @name RXPBDLYTG2_R4 - Read DQ per-bit BDL delay (Timing Group 2). */
11770/*! @{ */
11771#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RxPBDlyTg2_rx_MASK (0x7FU)
11772#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RxPBDlyTg2_rx_SHIFT (0U)
11773#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RxPBDlyTg2_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RxPBDlyTg2_rx_MASK)
11774/*! @} */
11775
11776/*! @name RXPBDLYTG3_R4 - Read DQ per-bit BDL delay (Timing Group 3). */
11777/*! @{ */
11778#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RxPBDlyTg3_rx_MASK (0x7FU)
11779#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RxPBDlyTg3_rx_SHIFT (0U)
11780#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RxPBDlyTg3_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RxPBDlyTg3_rx_MASK)
11781/*! @} */
11782
11783/*! @name TXDQDLYTG0_R4_P0 - Write DQ Delay (Timing Group 0). */
11784/*! @{ */
11785#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU)
11786#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TxDqDlyTg0_rn_px_SHIFT (0U)
11787#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TxDqDlyTg0_rn_px_MASK)
11788/*! @} */
11789
11790/*! @name TXDQDLYTG1_R4_P0 - Write DQ Delay (Timing Group 1). */
11791/*! @{ */
11792#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU)
11793#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TxDqDlyTg1_rn_px_SHIFT (0U)
11794#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TxDqDlyTg1_rn_px_MASK)
11795/*! @} */
11796
11797/*! @name TXDQDLYTG2_R4_P0 - Write DQ Delay (Timing Group 2). */
11798/*! @{ */
11799#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU)
11800#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TxDqDlyTg2_rn_px_SHIFT (0U)
11801#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TxDqDlyTg2_rn_px_MASK)
11802/*! @} */
11803
11804/*! @name TXDQDLYTG3_R4_P0 - Write DQ Delay (Timing Group 3). */
11805/*! @{ */
11806#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU)
11807#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TxDqDlyTg3_rn_px_SHIFT (0U)
11808#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TxDqDlyTg3_rn_px_MASK)
11809/*! @} */
11810
11811/*! @name VREFDAC1_R5 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
11812/*! @{ */
11813#define DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VrefDAC1_rx_MASK (0x7FU)
11814#define DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VrefDAC1_rx_SHIFT (0U)
11815#define DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VrefDAC1_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VrefDAC1_rx_MASK)
11816/*! @} */
11817
11818/*! @name VREFDAC0_R5 - VrefDAC0 control for DQ Receiver */
11819/*! @{ */
11820#define DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VrefDAC0_rx_MASK (0x7FU)
11821#define DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VrefDAC0_rx_SHIFT (0U)
11822#define DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VrefDAC0_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VrefDAC0_rx_MASK)
11823/*! @} */
11824
11825/*! @name RXPBDLYTG0_R5 - Read DQ per-bit BDL delay (Timing Group 0). */
11826/*! @{ */
11827#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RxPBDlyTg0_rx_MASK (0x7FU)
11828#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RxPBDlyTg0_rx_SHIFT (0U)
11829#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RxPBDlyTg0_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RxPBDlyTg0_rx_MASK)
11830/*! @} */
11831
11832/*! @name RXPBDLYTG1_R5 - Read DQ per-bit BDL delay (Timing Group 1). */
11833/*! @{ */
11834#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RxPBDlyTg1_rx_MASK (0x7FU)
11835#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RxPBDlyTg1_rx_SHIFT (0U)
11836#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RxPBDlyTg1_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RxPBDlyTg1_rx_MASK)
11837/*! @} */
11838
11839/*! @name RXPBDLYTG2_R5 - Read DQ per-bit BDL delay (Timing Group 2). */
11840/*! @{ */
11841#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RxPBDlyTg2_rx_MASK (0x7FU)
11842#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RxPBDlyTg2_rx_SHIFT (0U)
11843#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RxPBDlyTg2_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RxPBDlyTg2_rx_MASK)
11844/*! @} */
11845
11846/*! @name RXPBDLYTG3_R5 - Read DQ per-bit BDL delay (Timing Group 3). */
11847/*! @{ */
11848#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RxPBDlyTg3_rx_MASK (0x7FU)
11849#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RxPBDlyTg3_rx_SHIFT (0U)
11850#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RxPBDlyTg3_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RxPBDlyTg3_rx_MASK)
11851/*! @} */
11852
11853/*! @name TXDQDLYTG0_R5_P0 - Write DQ Delay (Timing Group 0). */
11854/*! @{ */
11855#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU)
11856#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TxDqDlyTg0_rn_px_SHIFT (0U)
11857#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TxDqDlyTg0_rn_px_MASK)
11858/*! @} */
11859
11860/*! @name TXDQDLYTG1_R5_P0 - Write DQ Delay (Timing Group 1). */
11861/*! @{ */
11862#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU)
11863#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TxDqDlyTg1_rn_px_SHIFT (0U)
11864#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TxDqDlyTg1_rn_px_MASK)
11865/*! @} */
11866
11867/*! @name TXDQDLYTG2_R5_P0 - Write DQ Delay (Timing Group 2). */
11868/*! @{ */
11869#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU)
11870#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TxDqDlyTg2_rn_px_SHIFT (0U)
11871#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TxDqDlyTg2_rn_px_MASK)
11872/*! @} */
11873
11874/*! @name TXDQDLYTG3_R5_P0 - Write DQ Delay (Timing Group 3). */
11875/*! @{ */
11876#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU)
11877#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TxDqDlyTg3_rn_px_SHIFT (0U)
11878#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TxDqDlyTg3_rn_px_MASK)
11879/*! @} */
11880
11881/*! @name VREFDAC1_R6 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
11882/*! @{ */
11883#define DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VrefDAC1_rx_MASK (0x7FU)
11884#define DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VrefDAC1_rx_SHIFT (0U)
11885#define DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VrefDAC1_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VrefDAC1_rx_MASK)
11886/*! @} */
11887
11888/*! @name VREFDAC0_R6 - VrefDAC0 control for DQ Receiver */
11889/*! @{ */
11890#define DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VrefDAC0_rx_MASK (0x7FU)
11891#define DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VrefDAC0_rx_SHIFT (0U)
11892#define DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VrefDAC0_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VrefDAC0_rx_MASK)
11893/*! @} */
11894
11895/*! @name RXPBDLYTG0_R6 - Read DQ per-bit BDL delay (Timing Group 0). */
11896/*! @{ */
11897#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RxPBDlyTg0_rx_MASK (0x7FU)
11898#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RxPBDlyTg0_rx_SHIFT (0U)
11899#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RxPBDlyTg0_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RxPBDlyTg0_rx_MASK)
11900/*! @} */
11901
11902/*! @name RXPBDLYTG1_R6 - Read DQ per-bit BDL delay (Timing Group 1). */
11903/*! @{ */
11904#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RxPBDlyTg1_rx_MASK (0x7FU)
11905#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RxPBDlyTg1_rx_SHIFT (0U)
11906#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RxPBDlyTg1_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RxPBDlyTg1_rx_MASK)
11907/*! @} */
11908
11909/*! @name RXPBDLYTG2_R6 - Read DQ per-bit BDL delay (Timing Group 2). */
11910/*! @{ */
11911#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RxPBDlyTg2_rx_MASK (0x7FU)
11912#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RxPBDlyTg2_rx_SHIFT (0U)
11913#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RxPBDlyTg2_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RxPBDlyTg2_rx_MASK)
11914/*! @} */
11915
11916/*! @name RXPBDLYTG3_R6 - Read DQ per-bit BDL delay (Timing Group 3). */
11917/*! @{ */
11918#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RxPBDlyTg3_rx_MASK (0x7FU)
11919#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RxPBDlyTg3_rx_SHIFT (0U)
11920#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RxPBDlyTg3_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RxPBDlyTg3_rx_MASK)
11921/*! @} */
11922
11923/*! @name TXDQDLYTG0_R6_P0 - Write DQ Delay (Timing Group 0). */
11924/*! @{ */
11925#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU)
11926#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TxDqDlyTg0_rn_px_SHIFT (0U)
11927#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TxDqDlyTg0_rn_px_MASK)
11928/*! @} */
11929
11930/*! @name TXDQDLYTG1_R6_P0 - Write DQ Delay (Timing Group 1). */
11931/*! @{ */
11932#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU)
11933#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TxDqDlyTg1_rn_px_SHIFT (0U)
11934#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TxDqDlyTg1_rn_px_MASK)
11935/*! @} */
11936
11937/*! @name TXDQDLYTG2_R6_P0 - Write DQ Delay (Timing Group 2). */
11938/*! @{ */
11939#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU)
11940#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TxDqDlyTg2_rn_px_SHIFT (0U)
11941#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TxDqDlyTg2_rn_px_MASK)
11942/*! @} */
11943
11944/*! @name TXDQDLYTG3_R6_P0 - Write DQ Delay (Timing Group 3). */
11945/*! @{ */
11946#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU)
11947#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TxDqDlyTg3_rn_px_SHIFT (0U)
11948#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TxDqDlyTg3_rn_px_MASK)
11949/*! @} */
11950
11951/*! @name VREFDAC1_R7 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
11952/*! @{ */
11953#define DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VrefDAC1_rx_MASK (0x7FU)
11954#define DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VrefDAC1_rx_SHIFT (0U)
11955#define DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VrefDAC1_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VrefDAC1_rx_MASK)
11956/*! @} */
11957
11958/*! @name VREFDAC0_R7 - VrefDAC0 control for DQ Receiver */
11959/*! @{ */
11960#define DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VrefDAC0_rx_MASK (0x7FU)
11961#define DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VrefDAC0_rx_SHIFT (0U)
11962#define DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VrefDAC0_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VrefDAC0_rx_MASK)
11963/*! @} */
11964
11965/*! @name RXPBDLYTG0_R7 - Read DQ per-bit BDL delay (Timing Group 0). */
11966/*! @{ */
11967#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RxPBDlyTg0_rx_MASK (0x7FU)
11968#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RxPBDlyTg0_rx_SHIFT (0U)
11969#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RxPBDlyTg0_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RxPBDlyTg0_rx_MASK)
11970/*! @} */
11971
11972/*! @name RXPBDLYTG1_R7 - Read DQ per-bit BDL delay (Timing Group 1). */
11973/*! @{ */
11974#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RxPBDlyTg1_rx_MASK (0x7FU)
11975#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RxPBDlyTg1_rx_SHIFT (0U)
11976#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RxPBDlyTg1_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RxPBDlyTg1_rx_MASK)
11977/*! @} */
11978
11979/*! @name RXPBDLYTG2_R7 - Read DQ per-bit BDL delay (Timing Group 2). */
11980/*! @{ */
11981#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RxPBDlyTg2_rx_MASK (0x7FU)
11982#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RxPBDlyTg2_rx_SHIFT (0U)
11983#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RxPBDlyTg2_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RxPBDlyTg2_rx_MASK)
11984/*! @} */
11985
11986/*! @name RXPBDLYTG3_R7 - Read DQ per-bit BDL delay (Timing Group 3). */
11987/*! @{ */
11988#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RxPBDlyTg3_rx_MASK (0x7FU)
11989#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RxPBDlyTg3_rx_SHIFT (0U)
11990#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RxPBDlyTg3_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RxPBDlyTg3_rx_MASK)
11991/*! @} */
11992
11993/*! @name TXDQDLYTG0_R7_P0 - Write DQ Delay (Timing Group 0). */
11994/*! @{ */
11995#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU)
11996#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TxDqDlyTg0_rn_px_SHIFT (0U)
11997#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TxDqDlyTg0_rn_px_MASK)
11998/*! @} */
11999
12000/*! @name TXDQDLYTG1_R7_P0 - Write DQ Delay (Timing Group 1). */
12001/*! @{ */
12002#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU)
12003#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TxDqDlyTg1_rn_px_SHIFT (0U)
12004#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TxDqDlyTg1_rn_px_MASK)
12005/*! @} */
12006
12007/*! @name TXDQDLYTG2_R7_P0 - Write DQ Delay (Timing Group 2). */
12008/*! @{ */
12009#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU)
12010#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TxDqDlyTg2_rn_px_SHIFT (0U)
12011#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TxDqDlyTg2_rn_px_MASK)
12012/*! @} */
12013
12014/*! @name TXDQDLYTG3_R7_P0 - Write DQ Delay (Timing Group 3). */
12015/*! @{ */
12016#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU)
12017#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TxDqDlyTg3_rn_px_SHIFT (0U)
12018#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TxDqDlyTg3_rn_px_MASK)
12019/*! @} */
12020
12021/*! @name VREFDAC1_R8 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
12022/*! @{ */
12023#define DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VrefDAC1_rx_MASK (0x7FU)
12024#define DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VrefDAC1_rx_SHIFT (0U)
12025#define DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VrefDAC1_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VrefDAC1_rx_MASK)
12026/*! @} */
12027
12028/*! @name VREFDAC0_R8 - VrefDAC0 control for DQ Receiver */
12029/*! @{ */
12030#define DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VrefDAC0_rx_MASK (0x7FU)
12031#define DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VrefDAC0_rx_SHIFT (0U)
12032#define DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VrefDAC0_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VrefDAC0_rx_MASK)
12033/*! @} */
12034
12035/*! @name RXPBDLYTG0_R8 - Read DQ per-bit BDL delay (Timing Group 0). */
12036/*! @{ */
12037#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RxPBDlyTg0_rx_MASK (0x7FU)
12038#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RxPBDlyTg0_rx_SHIFT (0U)
12039#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RxPBDlyTg0_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RxPBDlyTg0_rx_MASK)
12040/*! @} */
12041
12042/*! @name RXPBDLYTG1_R8 - Read DQ per-bit BDL delay (Timing Group 1). */
12043/*! @{ */
12044#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RxPBDlyTg1_rx_MASK (0x7FU)
12045#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RxPBDlyTg1_rx_SHIFT (0U)
12046#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RxPBDlyTg1_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RxPBDlyTg1_rx_MASK)
12047/*! @} */
12048
12049/*! @name RXPBDLYTG2_R8 - Read DQ per-bit BDL delay (Timing Group 2). */
12050/*! @{ */
12051#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RxPBDlyTg2_rx_MASK (0x7FU)
12052#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RxPBDlyTg2_rx_SHIFT (0U)
12053#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RxPBDlyTg2_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RxPBDlyTg2_rx_MASK)
12054/*! @} */
12055
12056/*! @name RXPBDLYTG3_R8 - Read DQ per-bit BDL delay (Timing Group 3). */
12057/*! @{ */
12058#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RxPBDlyTg3_rx_MASK (0x7FU)
12059#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RxPBDlyTg3_rx_SHIFT (0U)
12060#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RxPBDlyTg3_rx_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RxPBDlyTg3_rx_MASK)
12061/*! @} */
12062
12063/*! @name TXDQDLYTG0_R8_P0 - Write DQ Delay (Timing Group 0). */
12064/*! @{ */
12065#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU)
12066#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TxDqDlyTg0_rn_px_SHIFT (0U)
12067#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TxDqDlyTg0_rn_px_MASK)
12068/*! @} */
12069
12070/*! @name TXDQDLYTG1_R8_P0 - Write DQ Delay (Timing Group 1). */
12071/*! @{ */
12072#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU)
12073#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TxDqDlyTg1_rn_px_SHIFT (0U)
12074#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TxDqDlyTg1_rn_px_MASK)
12075/*! @} */
12076
12077/*! @name TXDQDLYTG2_R8_P0 - Write DQ Delay (Timing Group 2). */
12078/*! @{ */
12079#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU)
12080#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TxDqDlyTg2_rn_px_SHIFT (0U)
12081#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TxDqDlyTg2_rn_px_MASK)
12082/*! @} */
12083
12084/*! @name TXDQDLYTG3_R8_P0 - Write DQ Delay (Timing Group 3). */
12085/*! @{ */
12086#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU)
12087#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TxDqDlyTg3_rn_px_SHIFT (0U)
12088#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TxDqDlyTg3_rn_px_MASK)
12089/*! @} */
12090
12091/*! @name DFIMRL_P1 - DFI MaxReadLatency */
12092/*! @{ */
12093#define DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_p1_MASK (0x1FU)
12094#define DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_p1_SHIFT (0U)
12095#define DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_p1_SHIFT)) & DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_p1_MASK)
12096/*! @} */
12097
12098/*! @name TXIMPEDANCECTRL0_B0_P1 - Data TX impedance controls */
12099/*! @{ */
12100#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqP_MASK (0x3FU)
12101#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqP_SHIFT (0U)
12102#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqP_MASK)
12103#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqN_MASK (0xFC0U)
12104#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqN_SHIFT (6U)
12105#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqN_MASK)
12106/*! @} */
12107
12108/*! @name DQDQSRCVCNTRL_B0_P1 - Dq/Dqs receiver control */
12109/*! @{ */
12110#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SelAnalogVref_MASK (0x1U)
12111#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SelAnalogVref_SHIFT (0U)
12112#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SelAnalogVref_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SelAnalogVref_MASK)
12113#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_ExtVrefRange_MASK (0x2U)
12114#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_ExtVrefRange_SHIFT (1U)
12115#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_ExtVrefRange_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_ExtVrefRange_MASK)
12116#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DfeCtrl_MASK (0xCU)
12117#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DfeCtrl_SHIFT (2U)
12118#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DfeCtrl_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DfeCtrl_MASK)
12119#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MajorModeDbyte_MASK (0x70U)
12120#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MajorModeDbyte_SHIFT (4U)
12121#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MajorModeDbyte_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MajorModeDbyte_MASK)
12122#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GainCurrAdj_MASK (0xF80U)
12123#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GainCurrAdj_SHIFT (7U)
12124#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GainCurrAdj_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GainCurrAdj_MASK)
12125/*! @} */
12126
12127/*! @name TXEQUALIZATIONMODE_P1 - Tx dq driver equalization mode controls. */
12128/*! @{ */
12129#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TxEqMode_MASK (0x3U)
12130#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TxEqMode_SHIFT (0U)
12131#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TxEqMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TxEqMode_SHIFT)) & DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TxEqMode_MASK)
12132/*! @} */
12133
12134/*! @name TXIMPEDANCECTRL1_B0_P1 - TX impedance controls */
12135/*! @{ */
12136#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqP_MASK (0x3FU)
12137#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqP_SHIFT (0U)
12138#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqP_MASK)
12139#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqN_MASK (0xFC0U)
12140#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqN_SHIFT (6U)
12141#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqN_MASK)
12142/*! @} */
12143
12144/*! @name TXIMPEDANCECTRL2_B0_P1 - TX equalization impedance controls */
12145/*! @{ */
12146#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQHiDqP_MASK (0x3FU)
12147#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQHiDqP_SHIFT (0U)
12148#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQHiDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQHiDqP_MASK)
12149#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQLoDqN_MASK (0xFC0U)
12150#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQLoDqN_SHIFT (6U)
12151#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQLoDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQLoDqN_MASK)
12152/*! @} */
12153
12154/*! @name DQDQSRCVCNTRL2_P1 - Dq/Dqs receiver control */
12155/*! @{ */
12156#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_EnRxAgressivePDR_MASK (0x1U)
12157#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_EnRxAgressivePDR_SHIFT (0U)
12158#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_EnRxAgressivePDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_EnRxAgressivePDR_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_EnRxAgressivePDR_MASK)
12159/*! @} */
12160
12161/*! @name TXODTDRVSTREN_B0_P1 - TX ODT driver strength control */
12162/*! @{ */
12163#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenP_MASK (0x3FU)
12164#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenP_SHIFT (0U)
12165#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenP_MASK)
12166#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenN_MASK (0xFC0U)
12167#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenN_SHIFT (6U)
12168#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenN_MASK)
12169/*! @} */
12170
12171/*! @name TXSLEWRATE_B0_P1 - TX slew rate controls */
12172/*! @{ */
12173#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreP_MASK (0xFU)
12174#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreP_SHIFT (0U)
12175#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreP_MASK)
12176#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreN_MASK (0xF0U)
12177#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreN_SHIFT (4U)
12178#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreN_MASK)
12179#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreDrvMode_MASK (0x700U)
12180#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreDrvMode_SHIFT (8U)
12181#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreDrvMode_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreDrvMode_MASK)
12182/*! @} */
12183
12184/*! @name RXENDLYTG0_U0_P1 - Trained Receive Enable Delay (For Timing Group 0) */
12185/*! @{ */
12186#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RxEnDlyTg0_un_px_MASK (0x7FFU)
12187#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RxEnDlyTg0_un_px_SHIFT (0U)
12188#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RxEnDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RxEnDlyTg0_un_px_MASK)
12189/*! @} */
12190
12191/*! @name RXENDLYTG1_U0_P1 - Trained Receive Enable Delay (For Timing Group 1) */
12192/*! @{ */
12193#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RxEnDlyTg1_un_px_MASK (0x7FFU)
12194#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RxEnDlyTg1_un_px_SHIFT (0U)
12195#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RxEnDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RxEnDlyTg1_un_px_MASK)
12196/*! @} */
12197
12198/*! @name RXENDLYTG2_U0_P1 - Trained Receive Enable Delay (For Timing Group 2) */
12199/*! @{ */
12200#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RxEnDlyTg2_un_px_MASK (0x7FFU)
12201#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RxEnDlyTg2_un_px_SHIFT (0U)
12202#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RxEnDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RxEnDlyTg2_un_px_MASK)
12203/*! @} */
12204
12205/*! @name RXENDLYTG3_U0_P1 - Trained Receive Enable Delay (For Timing Group 3) */
12206/*! @{ */
12207#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RxEnDlyTg3_un_px_MASK (0x7FFU)
12208#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RxEnDlyTg3_un_px_SHIFT (0U)
12209#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RxEnDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RxEnDlyTg3_un_px_MASK)
12210/*! @} */
12211
12212/*! @name RXCLKDLYTG0_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
12213/*! @{ */
12214#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RxClkDlyTg0_un_px_MASK (0x3FU)
12215#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RxClkDlyTg0_un_px_SHIFT (0U)
12216#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RxClkDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RxClkDlyTg0_un_px_MASK)
12217/*! @} */
12218
12219/*! @name RXCLKDLYTG1_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
12220/*! @{ */
12221#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RxClkDlyTg1_un_px_MASK (0x3FU)
12222#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RxClkDlyTg1_un_px_SHIFT (0U)
12223#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RxClkDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RxClkDlyTg1_un_px_MASK)
12224/*! @} */
12225
12226/*! @name RXCLKDLYTG2_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
12227/*! @{ */
12228#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RxClkDlyTg2_un_px_MASK (0x3FU)
12229#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RxClkDlyTg2_un_px_SHIFT (0U)
12230#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RxClkDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RxClkDlyTg2_un_px_MASK)
12231/*! @} */
12232
12233/*! @name RXCLKDLYTG3_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
12234/*! @{ */
12235#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RxClkDlyTg3_un_px_MASK (0x3FU)
12236#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RxClkDlyTg3_un_px_SHIFT (0U)
12237#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RxClkDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RxClkDlyTg3_un_px_MASK)
12238/*! @} */
12239
12240/*! @name RXCLKCDLYTG0_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
12241/*! @{ */
12242#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RxClkcDlyTg0_un_px_MASK (0x3FU)
12243#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RxClkcDlyTg0_un_px_SHIFT (0U)
12244#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RxClkcDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RxClkcDlyTg0_un_px_MASK)
12245/*! @} */
12246
12247/*! @name RXCLKCDLYTG1_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
12248/*! @{ */
12249#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RxClkcDlyTg1_un_px_MASK (0x3FU)
12250#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RxClkcDlyTg1_un_px_SHIFT (0U)
12251#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RxClkcDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RxClkcDlyTg1_un_px_MASK)
12252/*! @} */
12253
12254/*! @name RXCLKCDLYTG2_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
12255/*! @{ */
12256#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RxClkcDlyTg2_un_px_MASK (0x3FU)
12257#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RxClkcDlyTg2_un_px_SHIFT (0U)
12258#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RxClkcDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RxClkcDlyTg2_un_px_MASK)
12259/*! @} */
12260
12261/*! @name RXCLKCDLYTG3_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
12262/*! @{ */
12263#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RxClkcDlyTg3_un_px_MASK (0x3FU)
12264#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RxClkcDlyTg3_un_px_SHIFT (0U)
12265#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RxClkcDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RxClkcDlyTg3_un_px_MASK)
12266/*! @} */
12267
12268/*! @name TXDQDLYTG0_R0_P1 - Write DQ Delay (Timing Group 0). */
12269/*! @{ */
12270#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU)
12271#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TxDqDlyTg0_rn_px_SHIFT (0U)
12272#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TxDqDlyTg0_rn_px_MASK)
12273/*! @} */
12274
12275/*! @name TXDQDLYTG1_R0_P1 - Write DQ Delay (Timing Group 1). */
12276/*! @{ */
12277#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU)
12278#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TxDqDlyTg1_rn_px_SHIFT (0U)
12279#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TxDqDlyTg1_rn_px_MASK)
12280/*! @} */
12281
12282/*! @name TXDQDLYTG2_R0_P1 - Write DQ Delay (Timing Group 2). */
12283/*! @{ */
12284#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU)
12285#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TxDqDlyTg2_rn_px_SHIFT (0U)
12286#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TxDqDlyTg2_rn_px_MASK)
12287/*! @} */
12288
12289/*! @name TXDQDLYTG3_R0_P1 - Write DQ Delay (Timing Group 3). */
12290/*! @{ */
12291#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU)
12292#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TxDqDlyTg3_rn_px_SHIFT (0U)
12293#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TxDqDlyTg3_rn_px_MASK)
12294/*! @} */
12295
12296/*! @name TXDQSDLYTG0_U0_P1 - Write DQS Delay (Timing Group DEST=0). */
12297/*! @{ */
12298#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TxDqsDlyTg0_un_px_MASK (0x3FFU)
12299#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TxDqsDlyTg0_un_px_SHIFT (0U)
12300#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TxDqsDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TxDqsDlyTg0_un_px_MASK)
12301/*! @} */
12302
12303/*! @name TXDQSDLYTG1_U0_P1 - Write DQS Delay (Timing Group DEST=1). */
12304/*! @{ */
12305#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TxDqsDlyTg1_un_px_MASK (0x3FFU)
12306#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TxDqsDlyTg1_un_px_SHIFT (0U)
12307#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TxDqsDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TxDqsDlyTg1_un_px_MASK)
12308/*! @} */
12309
12310/*! @name TXDQSDLYTG2_U0_P1 - Write DQS Delay (Timing Group DEST=2). */
12311/*! @{ */
12312#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TxDqsDlyTg2_un_px_MASK (0x3FFU)
12313#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TxDqsDlyTg2_un_px_SHIFT (0U)
12314#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TxDqsDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TxDqsDlyTg2_un_px_MASK)
12315/*! @} */
12316
12317/*! @name TXDQSDLYTG3_U0_P1 - Write DQS Delay (Timing Group DEST=3). */
12318/*! @{ */
12319#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TxDqsDlyTg3_un_px_MASK (0x3FFU)
12320#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TxDqsDlyTg3_un_px_SHIFT (0U)
12321#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TxDqsDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TxDqsDlyTg3_un_px_MASK)
12322/*! @} */
12323
12324/*! @name TXIMPEDANCECTRL0_B1_P1 - Data TX impedance controls */
12325/*! @{ */
12326#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqP_MASK (0x3FU)
12327#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqP_SHIFT (0U)
12328#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqP_MASK)
12329#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqN_MASK (0xFC0U)
12330#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqN_SHIFT (6U)
12331#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqN_MASK)
12332/*! @} */
12333
12334/*! @name DQDQSRCVCNTRL_B1_P1 - Dq/Dqs receiver control */
12335/*! @{ */
12336#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SelAnalogVref_MASK (0x1U)
12337#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SelAnalogVref_SHIFT (0U)
12338#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SelAnalogVref_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SelAnalogVref_MASK)
12339#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_ExtVrefRange_MASK (0x2U)
12340#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_ExtVrefRange_SHIFT (1U)
12341#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_ExtVrefRange_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_ExtVrefRange_MASK)
12342#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DfeCtrl_MASK (0xCU)
12343#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DfeCtrl_SHIFT (2U)
12344#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DfeCtrl_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DfeCtrl_MASK)
12345#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MajorModeDbyte_MASK (0x70U)
12346#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MajorModeDbyte_SHIFT (4U)
12347#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MajorModeDbyte_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MajorModeDbyte_MASK)
12348#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GainCurrAdj_MASK (0xF80U)
12349#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GainCurrAdj_SHIFT (7U)
12350#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GainCurrAdj_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GainCurrAdj_MASK)
12351/*! @} */
12352
12353/*! @name TXIMPEDANCECTRL1_B1_P1 - TX impedance controls */
12354/*! @{ */
12355#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqP_MASK (0x3FU)
12356#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqP_SHIFT (0U)
12357#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqP_MASK)
12358#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqN_MASK (0xFC0U)
12359#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqN_SHIFT (6U)
12360#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqN_MASK)
12361/*! @} */
12362
12363/*! @name TXIMPEDANCECTRL2_B1_P1 - TX equalization impedance controls */
12364/*! @{ */
12365#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQHiDqP_MASK (0x3FU)
12366#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQHiDqP_SHIFT (0U)
12367#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQHiDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQHiDqP_MASK)
12368#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQLoDqN_MASK (0xFC0U)
12369#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQLoDqN_SHIFT (6U)
12370#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQLoDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQLoDqN_MASK)
12371/*! @} */
12372
12373/*! @name TXODTDRVSTREN_B1_P1 - TX ODT driver strength control */
12374/*! @{ */
12375#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenP_MASK (0x3FU)
12376#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenP_SHIFT (0U)
12377#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenP_MASK)
12378#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenN_MASK (0xFC0U)
12379#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenN_SHIFT (6U)
12380#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenN_MASK)
12381/*! @} */
12382
12383/*! @name TXSLEWRATE_B1_P1 - TX slew rate controls */
12384/*! @{ */
12385#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreP_MASK (0xFU)
12386#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreP_SHIFT (0U)
12387#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreP_MASK)
12388#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreN_MASK (0xF0U)
12389#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreN_SHIFT (4U)
12390#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreN_MASK)
12391#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreDrvMode_MASK (0x700U)
12392#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreDrvMode_SHIFT (8U)
12393#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreDrvMode_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreDrvMode_MASK)
12394/*! @} */
12395
12396/*! @name RXENDLYTG0_U1_P1 - Trained Receive Enable Delay (For Timing Group 0) */
12397/*! @{ */
12398#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RxEnDlyTg0_un_px_MASK (0x7FFU)
12399#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RxEnDlyTg0_un_px_SHIFT (0U)
12400#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RxEnDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RxEnDlyTg0_un_px_MASK)
12401/*! @} */
12402
12403/*! @name RXENDLYTG1_U1_P1 - Trained Receive Enable Delay (For Timing Group 1) */
12404/*! @{ */
12405#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RxEnDlyTg1_un_px_MASK (0x7FFU)
12406#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RxEnDlyTg1_un_px_SHIFT (0U)
12407#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RxEnDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RxEnDlyTg1_un_px_MASK)
12408/*! @} */
12409
12410/*! @name RXENDLYTG2_U1_P1 - Trained Receive Enable Delay (For Timing Group 2) */
12411/*! @{ */
12412#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RxEnDlyTg2_un_px_MASK (0x7FFU)
12413#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RxEnDlyTg2_un_px_SHIFT (0U)
12414#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RxEnDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RxEnDlyTg2_un_px_MASK)
12415/*! @} */
12416
12417/*! @name RXENDLYTG3_U1_P1 - Trained Receive Enable Delay (For Timing Group 3) */
12418/*! @{ */
12419#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RxEnDlyTg3_un_px_MASK (0x7FFU)
12420#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RxEnDlyTg3_un_px_SHIFT (0U)
12421#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RxEnDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RxEnDlyTg3_un_px_MASK)
12422/*! @} */
12423
12424/*! @name RXCLKDLYTG0_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
12425/*! @{ */
12426#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RxClkDlyTg0_un_px_MASK (0x3FU)
12427#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RxClkDlyTg0_un_px_SHIFT (0U)
12428#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RxClkDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RxClkDlyTg0_un_px_MASK)
12429/*! @} */
12430
12431/*! @name RXCLKDLYTG1_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
12432/*! @{ */
12433#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RxClkDlyTg1_un_px_MASK (0x3FU)
12434#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RxClkDlyTg1_un_px_SHIFT (0U)
12435#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RxClkDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RxClkDlyTg1_un_px_MASK)
12436/*! @} */
12437
12438/*! @name RXCLKDLYTG2_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
12439/*! @{ */
12440#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RxClkDlyTg2_un_px_MASK (0x3FU)
12441#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RxClkDlyTg2_un_px_SHIFT (0U)
12442#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RxClkDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RxClkDlyTg2_un_px_MASK)
12443/*! @} */
12444
12445/*! @name RXCLKDLYTG3_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
12446/*! @{ */
12447#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RxClkDlyTg3_un_px_MASK (0x3FU)
12448#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RxClkDlyTg3_un_px_SHIFT (0U)
12449#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RxClkDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RxClkDlyTg3_un_px_MASK)
12450/*! @} */
12451
12452/*! @name RXCLKCDLYTG0_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
12453/*! @{ */
12454#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RxClkcDlyTg0_un_px_MASK (0x3FU)
12455#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RxClkcDlyTg0_un_px_SHIFT (0U)
12456#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RxClkcDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RxClkcDlyTg0_un_px_MASK)
12457/*! @} */
12458
12459/*! @name RXCLKCDLYTG1_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
12460/*! @{ */
12461#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RxClkcDlyTg1_un_px_MASK (0x3FU)
12462#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RxClkcDlyTg1_un_px_SHIFT (0U)
12463#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RxClkcDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RxClkcDlyTg1_un_px_MASK)
12464/*! @} */
12465
12466/*! @name RXCLKCDLYTG2_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
12467/*! @{ */
12468#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RxClkcDlyTg2_un_px_MASK (0x3FU)
12469#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RxClkcDlyTg2_un_px_SHIFT (0U)
12470#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RxClkcDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RxClkcDlyTg2_un_px_MASK)
12471/*! @} */
12472
12473/*! @name RXCLKCDLYTG3_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
12474/*! @{ */
12475#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RxClkcDlyTg3_un_px_MASK (0x3FU)
12476#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RxClkcDlyTg3_un_px_SHIFT (0U)
12477#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RxClkcDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RxClkcDlyTg3_un_px_MASK)
12478/*! @} */
12479
12480/*! @name TXDQDLYTG0_R1_P1 - Write DQ Delay (Timing Group 0). */
12481/*! @{ */
12482#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU)
12483#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TxDqDlyTg0_rn_px_SHIFT (0U)
12484#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TxDqDlyTg0_rn_px_MASK)
12485/*! @} */
12486
12487/*! @name TXDQDLYTG1_R1_P1 - Write DQ Delay (Timing Group 1). */
12488/*! @{ */
12489#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU)
12490#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TxDqDlyTg1_rn_px_SHIFT (0U)
12491#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TxDqDlyTg1_rn_px_MASK)
12492/*! @} */
12493
12494/*! @name TXDQDLYTG2_R1_P1 - Write DQ Delay (Timing Group 2). */
12495/*! @{ */
12496#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU)
12497#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TxDqDlyTg2_rn_px_SHIFT (0U)
12498#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TxDqDlyTg2_rn_px_MASK)
12499/*! @} */
12500
12501/*! @name TXDQDLYTG3_R1_P1 - Write DQ Delay (Timing Group 3). */
12502/*! @{ */
12503#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU)
12504#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TxDqDlyTg3_rn_px_SHIFT (0U)
12505#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TxDqDlyTg3_rn_px_MASK)
12506/*! @} */
12507
12508/*! @name TXDQSDLYTG0_U1_P1 - Write DQS Delay (Timing Group DEST=0). */
12509/*! @{ */
12510#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TxDqsDlyTg0_un_px_MASK (0x3FFU)
12511#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TxDqsDlyTg0_un_px_SHIFT (0U)
12512#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TxDqsDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TxDqsDlyTg0_un_px_MASK)
12513/*! @} */
12514
12515/*! @name TXDQSDLYTG1_U1_P1 - Write DQS Delay (Timing Group DEST=1). */
12516/*! @{ */
12517#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TxDqsDlyTg1_un_px_MASK (0x3FFU)
12518#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TxDqsDlyTg1_un_px_SHIFT (0U)
12519#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TxDqsDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TxDqsDlyTg1_un_px_MASK)
12520/*! @} */
12521
12522/*! @name TXDQSDLYTG2_U1_P1 - Write DQS Delay (Timing Group DEST=2). */
12523/*! @{ */
12524#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TxDqsDlyTg2_un_px_MASK (0x3FFU)
12525#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TxDqsDlyTg2_un_px_SHIFT (0U)
12526#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TxDqsDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TxDqsDlyTg2_un_px_MASK)
12527/*! @} */
12528
12529/*! @name TXDQSDLYTG3_U1_P1 - Write DQS Delay (Timing Group DEST=3). */
12530/*! @{ */
12531#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TxDqsDlyTg3_un_px_MASK (0x3FFU)
12532#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TxDqsDlyTg3_un_px_SHIFT (0U)
12533#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TxDqsDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TxDqsDlyTg3_un_px_MASK)
12534/*! @} */
12535
12536/*! @name TXDQDLYTG0_R2_P1 - Write DQ Delay (Timing Group 0). */
12537/*! @{ */
12538#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU)
12539#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TxDqDlyTg0_rn_px_SHIFT (0U)
12540#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TxDqDlyTg0_rn_px_MASK)
12541/*! @} */
12542
12543/*! @name TXDQDLYTG1_R2_P1 - Write DQ Delay (Timing Group 1). */
12544/*! @{ */
12545#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU)
12546#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TxDqDlyTg1_rn_px_SHIFT (0U)
12547#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TxDqDlyTg1_rn_px_MASK)
12548/*! @} */
12549
12550/*! @name TXDQDLYTG2_R2_P1 - Write DQ Delay (Timing Group 2). */
12551/*! @{ */
12552#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU)
12553#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TxDqDlyTg2_rn_px_SHIFT (0U)
12554#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TxDqDlyTg2_rn_px_MASK)
12555/*! @} */
12556
12557/*! @name TXDQDLYTG3_R2_P1 - Write DQ Delay (Timing Group 3). */
12558/*! @{ */
12559#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU)
12560#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TxDqDlyTg3_rn_px_SHIFT (0U)
12561#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TxDqDlyTg3_rn_px_MASK)
12562/*! @} */
12563
12564/*! @name TXDQDLYTG0_R3_P1 - Write DQ Delay (Timing Group 0). */
12565/*! @{ */
12566#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU)
12567#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TxDqDlyTg0_rn_px_SHIFT (0U)
12568#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TxDqDlyTg0_rn_px_MASK)
12569/*! @} */
12570
12571/*! @name TXDQDLYTG1_R3_P1 - Write DQ Delay (Timing Group 1). */
12572/*! @{ */
12573#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU)
12574#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TxDqDlyTg1_rn_px_SHIFT (0U)
12575#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TxDqDlyTg1_rn_px_MASK)
12576/*! @} */
12577
12578/*! @name TXDQDLYTG2_R3_P1 - Write DQ Delay (Timing Group 2). */
12579/*! @{ */
12580#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU)
12581#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TxDqDlyTg2_rn_px_SHIFT (0U)
12582#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TxDqDlyTg2_rn_px_MASK)
12583/*! @} */
12584
12585/*! @name TXDQDLYTG3_R3_P1 - Write DQ Delay (Timing Group 3). */
12586/*! @{ */
12587#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU)
12588#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TxDqDlyTg3_rn_px_SHIFT (0U)
12589#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TxDqDlyTg3_rn_px_MASK)
12590/*! @} */
12591
12592/*! @name TXDQDLYTG0_R4_P1 - Write DQ Delay (Timing Group 0). */
12593/*! @{ */
12594#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU)
12595#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TxDqDlyTg0_rn_px_SHIFT (0U)
12596#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TxDqDlyTg0_rn_px_MASK)
12597/*! @} */
12598
12599/*! @name TXDQDLYTG1_R4_P1 - Write DQ Delay (Timing Group 1). */
12600/*! @{ */
12601#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU)
12602#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TxDqDlyTg1_rn_px_SHIFT (0U)
12603#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TxDqDlyTg1_rn_px_MASK)
12604/*! @} */
12605
12606/*! @name TXDQDLYTG2_R4_P1 - Write DQ Delay (Timing Group 2). */
12607/*! @{ */
12608#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU)
12609#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TxDqDlyTg2_rn_px_SHIFT (0U)
12610#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TxDqDlyTg2_rn_px_MASK)
12611/*! @} */
12612
12613/*! @name TXDQDLYTG3_R4_P1 - Write DQ Delay (Timing Group 3). */
12614/*! @{ */
12615#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU)
12616#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TxDqDlyTg3_rn_px_SHIFT (0U)
12617#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TxDqDlyTg3_rn_px_MASK)
12618/*! @} */
12619
12620/*! @name TXDQDLYTG0_R5_P1 - Write DQ Delay (Timing Group 0). */
12621/*! @{ */
12622#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU)
12623#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TxDqDlyTg0_rn_px_SHIFT (0U)
12624#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TxDqDlyTg0_rn_px_MASK)
12625/*! @} */
12626
12627/*! @name TXDQDLYTG1_R5_P1 - Write DQ Delay (Timing Group 1). */
12628/*! @{ */
12629#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU)
12630#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TxDqDlyTg1_rn_px_SHIFT (0U)
12631#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TxDqDlyTg1_rn_px_MASK)
12632/*! @} */
12633
12634/*! @name TXDQDLYTG2_R5_P1 - Write DQ Delay (Timing Group 2). */
12635/*! @{ */
12636#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU)
12637#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TxDqDlyTg2_rn_px_SHIFT (0U)
12638#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TxDqDlyTg2_rn_px_MASK)
12639/*! @} */
12640
12641/*! @name TXDQDLYTG3_R5_P1 - Write DQ Delay (Timing Group 3). */
12642/*! @{ */
12643#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU)
12644#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TxDqDlyTg3_rn_px_SHIFT (0U)
12645#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TxDqDlyTg3_rn_px_MASK)
12646/*! @} */
12647
12648/*! @name TXDQDLYTG0_R6_P1 - Write DQ Delay (Timing Group 0). */
12649/*! @{ */
12650#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU)
12651#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TxDqDlyTg0_rn_px_SHIFT (0U)
12652#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TxDqDlyTg0_rn_px_MASK)
12653/*! @} */
12654
12655/*! @name TXDQDLYTG1_R6_P1 - Write DQ Delay (Timing Group 1). */
12656/*! @{ */
12657#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU)
12658#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TxDqDlyTg1_rn_px_SHIFT (0U)
12659#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TxDqDlyTg1_rn_px_MASK)
12660/*! @} */
12661
12662/*! @name TXDQDLYTG2_R6_P1 - Write DQ Delay (Timing Group 2). */
12663/*! @{ */
12664#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU)
12665#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TxDqDlyTg2_rn_px_SHIFT (0U)
12666#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TxDqDlyTg2_rn_px_MASK)
12667/*! @} */
12668
12669/*! @name TXDQDLYTG3_R6_P1 - Write DQ Delay (Timing Group 3). */
12670/*! @{ */
12671#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU)
12672#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TxDqDlyTg3_rn_px_SHIFT (0U)
12673#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TxDqDlyTg3_rn_px_MASK)
12674/*! @} */
12675
12676/*! @name TXDQDLYTG0_R7_P1 - Write DQ Delay (Timing Group 0). */
12677/*! @{ */
12678#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU)
12679#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TxDqDlyTg0_rn_px_SHIFT (0U)
12680#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TxDqDlyTg0_rn_px_MASK)
12681/*! @} */
12682
12683/*! @name TXDQDLYTG1_R7_P1 - Write DQ Delay (Timing Group 1). */
12684/*! @{ */
12685#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU)
12686#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TxDqDlyTg1_rn_px_SHIFT (0U)
12687#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TxDqDlyTg1_rn_px_MASK)
12688/*! @} */
12689
12690/*! @name TXDQDLYTG2_R7_P1 - Write DQ Delay (Timing Group 2). */
12691/*! @{ */
12692#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU)
12693#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TxDqDlyTg2_rn_px_SHIFT (0U)
12694#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TxDqDlyTg2_rn_px_MASK)
12695/*! @} */
12696
12697/*! @name TXDQDLYTG3_R7_P1 - Write DQ Delay (Timing Group 3). */
12698/*! @{ */
12699#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU)
12700#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TxDqDlyTg3_rn_px_SHIFT (0U)
12701#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TxDqDlyTg3_rn_px_MASK)
12702/*! @} */
12703
12704/*! @name TXDQDLYTG0_R8_P1 - Write DQ Delay (Timing Group 0). */
12705/*! @{ */
12706#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU)
12707#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TxDqDlyTg0_rn_px_SHIFT (0U)
12708#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TxDqDlyTg0_rn_px_MASK)
12709/*! @} */
12710
12711/*! @name TXDQDLYTG1_R8_P1 - Write DQ Delay (Timing Group 1). */
12712/*! @{ */
12713#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU)
12714#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TxDqDlyTg1_rn_px_SHIFT (0U)
12715#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TxDqDlyTg1_rn_px_MASK)
12716/*! @} */
12717
12718/*! @name TXDQDLYTG2_R8_P1 - Write DQ Delay (Timing Group 2). */
12719/*! @{ */
12720#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU)
12721#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TxDqDlyTg2_rn_px_SHIFT (0U)
12722#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TxDqDlyTg2_rn_px_MASK)
12723/*! @} */
12724
12725/*! @name TXDQDLYTG3_R8_P1 - Write DQ Delay (Timing Group 3). */
12726/*! @{ */
12727#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU)
12728#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TxDqDlyTg3_rn_px_SHIFT (0U)
12729#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TxDqDlyTg3_rn_px_MASK)
12730/*! @} */
12731
12732/*! @name DFIMRL_P2 - DFI MaxReadLatency */
12733/*! @{ */
12734#define DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_p2_MASK (0x1FU)
12735#define DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_p2_SHIFT (0U)
12736#define DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_p2_SHIFT)) & DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_p2_MASK)
12737/*! @} */
12738
12739/*! @name TXIMPEDANCECTRL0_B0_P2 - Data TX impedance controls */
12740/*! @{ */
12741#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqP_MASK (0x3FU)
12742#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqP_SHIFT (0U)
12743#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqP_MASK)
12744#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqN_MASK (0xFC0U)
12745#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqN_SHIFT (6U)
12746#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqN_MASK)
12747/*! @} */
12748
12749/*! @name DQDQSRCVCNTRL_B0_P2 - Dq/Dqs receiver control */
12750/*! @{ */
12751#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SelAnalogVref_MASK (0x1U)
12752#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SelAnalogVref_SHIFT (0U)
12753#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SelAnalogVref_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SelAnalogVref_MASK)
12754#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_ExtVrefRange_MASK (0x2U)
12755#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_ExtVrefRange_SHIFT (1U)
12756#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_ExtVrefRange_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_ExtVrefRange_MASK)
12757#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DfeCtrl_MASK (0xCU)
12758#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DfeCtrl_SHIFT (2U)
12759#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DfeCtrl_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DfeCtrl_MASK)
12760#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MajorModeDbyte_MASK (0x70U)
12761#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MajorModeDbyte_SHIFT (4U)
12762#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MajorModeDbyte_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MajorModeDbyte_MASK)
12763#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GainCurrAdj_MASK (0xF80U)
12764#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GainCurrAdj_SHIFT (7U)
12765#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GainCurrAdj_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GainCurrAdj_MASK)
12766/*! @} */
12767
12768/*! @name TXEQUALIZATIONMODE_P2 - Tx dq driver equalization mode controls. */
12769/*! @{ */
12770#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TxEqMode_MASK (0x3U)
12771#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TxEqMode_SHIFT (0U)
12772#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TxEqMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TxEqMode_SHIFT)) & DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TxEqMode_MASK)
12773/*! @} */
12774
12775/*! @name TXIMPEDANCECTRL1_B0_P2 - TX impedance controls */
12776/*! @{ */
12777#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqP_MASK (0x3FU)
12778#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqP_SHIFT (0U)
12779#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqP_MASK)
12780#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqN_MASK (0xFC0U)
12781#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqN_SHIFT (6U)
12782#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqN_MASK)
12783/*! @} */
12784
12785/*! @name TXIMPEDANCECTRL2_B0_P2 - TX equalization impedance controls */
12786/*! @{ */
12787#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQHiDqP_MASK (0x3FU)
12788#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQHiDqP_SHIFT (0U)
12789#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQHiDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQHiDqP_MASK)
12790#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQLoDqN_MASK (0xFC0U)
12791#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQLoDqN_SHIFT (6U)
12792#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQLoDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQLoDqN_MASK)
12793/*! @} */
12794
12795/*! @name DQDQSRCVCNTRL2_P2 - Dq/Dqs receiver control */
12796/*! @{ */
12797#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_EnRxAgressivePDR_MASK (0x1U)
12798#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_EnRxAgressivePDR_SHIFT (0U)
12799#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_EnRxAgressivePDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_EnRxAgressivePDR_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_EnRxAgressivePDR_MASK)
12800/*! @} */
12801
12802/*! @name TXODTDRVSTREN_B0_P2 - TX ODT driver strength control */
12803/*! @{ */
12804#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenP_MASK (0x3FU)
12805#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenP_SHIFT (0U)
12806#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenP_MASK)
12807#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenN_MASK (0xFC0U)
12808#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenN_SHIFT (6U)
12809#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenN_MASK)
12810/*! @} */
12811
12812/*! @name TXSLEWRATE_B0_P2 - TX slew rate controls */
12813/*! @{ */
12814#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreP_MASK (0xFU)
12815#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreP_SHIFT (0U)
12816#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreP_MASK)
12817#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreN_MASK (0xF0U)
12818#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreN_SHIFT (4U)
12819#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreN_MASK)
12820#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreDrvMode_MASK (0x700U)
12821#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreDrvMode_SHIFT (8U)
12822#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreDrvMode_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreDrvMode_MASK)
12823/*! @} */
12824
12825/*! @name RXENDLYTG0_U0_P2 - Trained Receive Enable Delay (For Timing Group 0) */
12826/*! @{ */
12827#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RxEnDlyTg0_un_px_MASK (0x7FFU)
12828#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RxEnDlyTg0_un_px_SHIFT (0U)
12829#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RxEnDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RxEnDlyTg0_un_px_MASK)
12830/*! @} */
12831
12832/*! @name RXENDLYTG1_U0_P2 - Trained Receive Enable Delay (For Timing Group 1) */
12833/*! @{ */
12834#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RxEnDlyTg1_un_px_MASK (0x7FFU)
12835#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RxEnDlyTg1_un_px_SHIFT (0U)
12836#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RxEnDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RxEnDlyTg1_un_px_MASK)
12837/*! @} */
12838
12839/*! @name RXENDLYTG2_U0_P2 - Trained Receive Enable Delay (For Timing Group 2) */
12840/*! @{ */
12841#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RxEnDlyTg2_un_px_MASK (0x7FFU)
12842#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RxEnDlyTg2_un_px_SHIFT (0U)
12843#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RxEnDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RxEnDlyTg2_un_px_MASK)
12844/*! @} */
12845
12846/*! @name RXENDLYTG3_U0_P2 - Trained Receive Enable Delay (For Timing Group 3) */
12847/*! @{ */
12848#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RxEnDlyTg3_un_px_MASK (0x7FFU)
12849#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RxEnDlyTg3_un_px_SHIFT (0U)
12850#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RxEnDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RxEnDlyTg3_un_px_MASK)
12851/*! @} */
12852
12853/*! @name RXCLKDLYTG0_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
12854/*! @{ */
12855#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RxClkDlyTg0_un_px_MASK (0x3FU)
12856#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RxClkDlyTg0_un_px_SHIFT (0U)
12857#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RxClkDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RxClkDlyTg0_un_px_MASK)
12858/*! @} */
12859
12860/*! @name RXCLKDLYTG1_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
12861/*! @{ */
12862#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RxClkDlyTg1_un_px_MASK (0x3FU)
12863#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RxClkDlyTg1_un_px_SHIFT (0U)
12864#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RxClkDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RxClkDlyTg1_un_px_MASK)
12865/*! @} */
12866
12867/*! @name RXCLKDLYTG2_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
12868/*! @{ */
12869#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RxClkDlyTg2_un_px_MASK (0x3FU)
12870#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RxClkDlyTg2_un_px_SHIFT (0U)
12871#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RxClkDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RxClkDlyTg2_un_px_MASK)
12872/*! @} */
12873
12874/*! @name RXCLKDLYTG3_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
12875/*! @{ */
12876#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RxClkDlyTg3_un_px_MASK (0x3FU)
12877#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RxClkDlyTg3_un_px_SHIFT (0U)
12878#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RxClkDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RxClkDlyTg3_un_px_MASK)
12879/*! @} */
12880
12881/*! @name RXCLKCDLYTG0_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
12882/*! @{ */
12883#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RxClkcDlyTg0_un_px_MASK (0x3FU)
12884#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RxClkcDlyTg0_un_px_SHIFT (0U)
12885#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RxClkcDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RxClkcDlyTg0_un_px_MASK)
12886/*! @} */
12887
12888/*! @name RXCLKCDLYTG1_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
12889/*! @{ */
12890#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RxClkcDlyTg1_un_px_MASK (0x3FU)
12891#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RxClkcDlyTg1_un_px_SHIFT (0U)
12892#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RxClkcDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RxClkcDlyTg1_un_px_MASK)
12893/*! @} */
12894
12895/*! @name RXCLKCDLYTG2_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
12896/*! @{ */
12897#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RxClkcDlyTg2_un_px_MASK (0x3FU)
12898#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RxClkcDlyTg2_un_px_SHIFT (0U)
12899#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RxClkcDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RxClkcDlyTg2_un_px_MASK)
12900/*! @} */
12901
12902/*! @name RXCLKCDLYTG3_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
12903/*! @{ */
12904#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RxClkcDlyTg3_un_px_MASK (0x3FU)
12905#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RxClkcDlyTg3_un_px_SHIFT (0U)
12906#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RxClkcDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RxClkcDlyTg3_un_px_MASK)
12907/*! @} */
12908
12909/*! @name PPTDQSCNTINVTRNTG0_P2 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */
12910/*! @{ */
12911#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PptDqsCntInvTrnTg0_p2_MASK (0xFFFFU)
12912#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PptDqsCntInvTrnTg0_p2_SHIFT (0U)
12913#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PptDqsCntInvTrnTg0_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PptDqsCntInvTrnTg0_p2_SHIFT)) & DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PptDqsCntInvTrnTg0_p2_MASK)
12914/*! @} */
12915
12916/*! @name PPTDQSCNTINVTRNTG1_P2 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */
12917/*! @{ */
12918#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PptDqsCntInvTrnTg1_p2_MASK (0xFFFFU)
12919#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PptDqsCntInvTrnTg1_p2_SHIFT (0U)
12920#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PptDqsCntInvTrnTg1_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PptDqsCntInvTrnTg1_p2_SHIFT)) & DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PptDqsCntInvTrnTg1_p2_MASK)
12921/*! @} */
12922
12923/*! @name TXDQDLYTG0_R0_P2 - Write DQ Delay (Timing Group 0). */
12924/*! @{ */
12925#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU)
12926#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TxDqDlyTg0_rn_px_SHIFT (0U)
12927#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TxDqDlyTg0_rn_px_MASK)
12928/*! @} */
12929
12930/*! @name TXDQDLYTG1_R0_P2 - Write DQ Delay (Timing Group 1). */
12931/*! @{ */
12932#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU)
12933#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TxDqDlyTg1_rn_px_SHIFT (0U)
12934#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TxDqDlyTg1_rn_px_MASK)
12935/*! @} */
12936
12937/*! @name TXDQDLYTG2_R0_P2 - Write DQ Delay (Timing Group 2). */
12938/*! @{ */
12939#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU)
12940#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TxDqDlyTg2_rn_px_SHIFT (0U)
12941#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TxDqDlyTg2_rn_px_MASK)
12942/*! @} */
12943
12944/*! @name TXDQDLYTG3_R0_P2 - Write DQ Delay (Timing Group 3). */
12945/*! @{ */
12946#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU)
12947#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TxDqDlyTg3_rn_px_SHIFT (0U)
12948#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TxDqDlyTg3_rn_px_MASK)
12949/*! @} */
12950
12951/*! @name TXDQSDLYTG0_U0_P2 - Write DQS Delay (Timing Group DEST=0). */
12952/*! @{ */
12953#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TxDqsDlyTg0_un_px_MASK (0x3FFU)
12954#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TxDqsDlyTg0_un_px_SHIFT (0U)
12955#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TxDqsDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TxDqsDlyTg0_un_px_MASK)
12956/*! @} */
12957
12958/*! @name TXDQSDLYTG1_U0_P2 - Write DQS Delay (Timing Group DEST=1). */
12959/*! @{ */
12960#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TxDqsDlyTg1_un_px_MASK (0x3FFU)
12961#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TxDqsDlyTg1_un_px_SHIFT (0U)
12962#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TxDqsDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TxDqsDlyTg1_un_px_MASK)
12963/*! @} */
12964
12965/*! @name TXDQSDLYTG2_U0_P2 - Write DQS Delay (Timing Group DEST=2). */
12966/*! @{ */
12967#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TxDqsDlyTg2_un_px_MASK (0x3FFU)
12968#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TxDqsDlyTg2_un_px_SHIFT (0U)
12969#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TxDqsDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TxDqsDlyTg2_un_px_MASK)
12970/*! @} */
12971
12972/*! @name TXDQSDLYTG3_U0_P2 - Write DQS Delay (Timing Group DEST=3). */
12973/*! @{ */
12974#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TxDqsDlyTg3_un_px_MASK (0x3FFU)
12975#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TxDqsDlyTg3_un_px_SHIFT (0U)
12976#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TxDqsDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TxDqsDlyTg3_un_px_MASK)
12977/*! @} */
12978
12979/*! @name TXIMPEDANCECTRL0_B1_P2 - Data TX impedance controls */
12980/*! @{ */
12981#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqP_MASK (0x3FU)
12982#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqP_SHIFT (0U)
12983#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqP_MASK)
12984#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqN_MASK (0xFC0U)
12985#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqN_SHIFT (6U)
12986#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqN_MASK)
12987/*! @} */
12988
12989/*! @name DQDQSRCVCNTRL_B1_P2 - Dq/Dqs receiver control */
12990/*! @{ */
12991#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SelAnalogVref_MASK (0x1U)
12992#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SelAnalogVref_SHIFT (0U)
12993#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SelAnalogVref_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SelAnalogVref_MASK)
12994#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_ExtVrefRange_MASK (0x2U)
12995#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_ExtVrefRange_SHIFT (1U)
12996#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_ExtVrefRange_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_ExtVrefRange_MASK)
12997#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DfeCtrl_MASK (0xCU)
12998#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DfeCtrl_SHIFT (2U)
12999#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DfeCtrl_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DfeCtrl_MASK)
13000#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MajorModeDbyte_MASK (0x70U)
13001#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MajorModeDbyte_SHIFT (4U)
13002#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MajorModeDbyte_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MajorModeDbyte_MASK)
13003#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GainCurrAdj_MASK (0xF80U)
13004#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GainCurrAdj_SHIFT (7U)
13005#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GainCurrAdj_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GainCurrAdj_MASK)
13006/*! @} */
13007
13008/*! @name TXIMPEDANCECTRL1_B1_P2 - TX impedance controls */
13009/*! @{ */
13010#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqP_MASK (0x3FU)
13011#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqP_SHIFT (0U)
13012#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqP_MASK)
13013#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqN_MASK (0xFC0U)
13014#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqN_SHIFT (6U)
13015#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqN_MASK)
13016/*! @} */
13017
13018/*! @name TXIMPEDANCECTRL2_B1_P2 - TX equalization impedance controls */
13019/*! @{ */
13020#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQHiDqP_MASK (0x3FU)
13021#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQHiDqP_SHIFT (0U)
13022#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQHiDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQHiDqP_MASK)
13023#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQLoDqN_MASK (0xFC0U)
13024#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQLoDqN_SHIFT (6U)
13025#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQLoDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQLoDqN_MASK)
13026/*! @} */
13027
13028/*! @name TXODTDRVSTREN_B1_P2 - TX ODT driver strength control */
13029/*! @{ */
13030#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenP_MASK (0x3FU)
13031#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenP_SHIFT (0U)
13032#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenP_MASK)
13033#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenN_MASK (0xFC0U)
13034#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenN_SHIFT (6U)
13035#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenN_MASK)
13036/*! @} */
13037
13038/*! @name TXSLEWRATE_B1_P2 - TX slew rate controls */
13039/*! @{ */
13040#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreP_MASK (0xFU)
13041#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreP_SHIFT (0U)
13042#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreP_MASK)
13043#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreN_MASK (0xF0U)
13044#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreN_SHIFT (4U)
13045#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreN_MASK)
13046#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreDrvMode_MASK (0x700U)
13047#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreDrvMode_SHIFT (8U)
13048#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreDrvMode_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreDrvMode_MASK)
13049/*! @} */
13050
13051/*! @name RXENDLYTG0_U1_P2 - Trained Receive Enable Delay (For Timing Group 0) */
13052/*! @{ */
13053#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RxEnDlyTg0_un_px_MASK (0x7FFU)
13054#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RxEnDlyTg0_un_px_SHIFT (0U)
13055#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RxEnDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RxEnDlyTg0_un_px_MASK)
13056/*! @} */
13057
13058/*! @name RXENDLYTG1_U1_P2 - Trained Receive Enable Delay (For Timing Group 1) */
13059/*! @{ */
13060#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RxEnDlyTg1_un_px_MASK (0x7FFU)
13061#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RxEnDlyTg1_un_px_SHIFT (0U)
13062#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RxEnDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RxEnDlyTg1_un_px_MASK)
13063/*! @} */
13064
13065/*! @name RXENDLYTG2_U1_P2 - Trained Receive Enable Delay (For Timing Group 2) */
13066/*! @{ */
13067#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RxEnDlyTg2_un_px_MASK (0x7FFU)
13068#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RxEnDlyTg2_un_px_SHIFT (0U)
13069#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RxEnDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RxEnDlyTg2_un_px_MASK)
13070/*! @} */
13071
13072/*! @name RXENDLYTG3_U1_P2 - Trained Receive Enable Delay (For Timing Group 3) */
13073/*! @{ */
13074#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RxEnDlyTg3_un_px_MASK (0x7FFU)
13075#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RxEnDlyTg3_un_px_SHIFT (0U)
13076#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RxEnDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RxEnDlyTg3_un_px_MASK)
13077/*! @} */
13078
13079/*! @name RXCLKDLYTG0_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
13080/*! @{ */
13081#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RxClkDlyTg0_un_px_MASK (0x3FU)
13082#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RxClkDlyTg0_un_px_SHIFT (0U)
13083#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RxClkDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RxClkDlyTg0_un_px_MASK)
13084/*! @} */
13085
13086/*! @name RXCLKDLYTG1_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
13087/*! @{ */
13088#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RxClkDlyTg1_un_px_MASK (0x3FU)
13089#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RxClkDlyTg1_un_px_SHIFT (0U)
13090#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RxClkDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RxClkDlyTg1_un_px_MASK)
13091/*! @} */
13092
13093/*! @name RXCLKDLYTG2_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
13094/*! @{ */
13095#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RxClkDlyTg2_un_px_MASK (0x3FU)
13096#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RxClkDlyTg2_un_px_SHIFT (0U)
13097#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RxClkDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RxClkDlyTg2_un_px_MASK)
13098/*! @} */
13099
13100/*! @name RXCLKDLYTG3_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
13101/*! @{ */
13102#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RxClkDlyTg3_un_px_MASK (0x3FU)
13103#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RxClkDlyTg3_un_px_SHIFT (0U)
13104#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RxClkDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RxClkDlyTg3_un_px_MASK)
13105/*! @} */
13106
13107/*! @name RXCLKCDLYTG0_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
13108/*! @{ */
13109#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RxClkcDlyTg0_un_px_MASK (0x3FU)
13110#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RxClkcDlyTg0_un_px_SHIFT (0U)
13111#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RxClkcDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RxClkcDlyTg0_un_px_MASK)
13112/*! @} */
13113
13114/*! @name RXCLKCDLYTG1_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
13115/*! @{ */
13116#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RxClkcDlyTg1_un_px_MASK (0x3FU)
13117#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RxClkcDlyTg1_un_px_SHIFT (0U)
13118#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RxClkcDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RxClkcDlyTg1_un_px_MASK)
13119/*! @} */
13120
13121/*! @name RXCLKCDLYTG2_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
13122/*! @{ */
13123#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RxClkcDlyTg2_un_px_MASK (0x3FU)
13124#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RxClkcDlyTg2_un_px_SHIFT (0U)
13125#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RxClkcDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RxClkcDlyTg2_un_px_MASK)
13126/*! @} */
13127
13128/*! @name RXCLKCDLYTG3_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
13129/*! @{ */
13130#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RxClkcDlyTg3_un_px_MASK (0x3FU)
13131#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RxClkcDlyTg3_un_px_SHIFT (0U)
13132#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RxClkcDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RxClkcDlyTg3_un_px_MASK)
13133/*! @} */
13134
13135/*! @name TXDQDLYTG0_R1_P2 - Write DQ Delay (Timing Group 0). */
13136/*! @{ */
13137#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13138#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TxDqDlyTg0_rn_px_SHIFT (0U)
13139#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TxDqDlyTg0_rn_px_MASK)
13140/*! @} */
13141
13142/*! @name TXDQDLYTG1_R1_P2 - Write DQ Delay (Timing Group 1). */
13143/*! @{ */
13144#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13145#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TxDqDlyTg1_rn_px_SHIFT (0U)
13146#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TxDqDlyTg1_rn_px_MASK)
13147/*! @} */
13148
13149/*! @name TXDQDLYTG2_R1_P2 - Write DQ Delay (Timing Group 2). */
13150/*! @{ */
13151#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU)
13152#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TxDqDlyTg2_rn_px_SHIFT (0U)
13153#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TxDqDlyTg2_rn_px_MASK)
13154/*! @} */
13155
13156/*! @name TXDQDLYTG3_R1_P2 - Write DQ Delay (Timing Group 3). */
13157/*! @{ */
13158#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU)
13159#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TxDqDlyTg3_rn_px_SHIFT (0U)
13160#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TxDqDlyTg3_rn_px_MASK)
13161/*! @} */
13162
13163/*! @name TXDQSDLYTG0_U1_P2 - Write DQS Delay (Timing Group DEST=0). */
13164/*! @{ */
13165#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TxDqsDlyTg0_un_px_MASK (0x3FFU)
13166#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TxDqsDlyTg0_un_px_SHIFT (0U)
13167#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TxDqsDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TxDqsDlyTg0_un_px_MASK)
13168/*! @} */
13169
13170/*! @name TXDQSDLYTG1_U1_P2 - Write DQS Delay (Timing Group DEST=1). */
13171/*! @{ */
13172#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TxDqsDlyTg1_un_px_MASK (0x3FFU)
13173#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TxDqsDlyTg1_un_px_SHIFT (0U)
13174#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TxDqsDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TxDqsDlyTg1_un_px_MASK)
13175/*! @} */
13176
13177/*! @name TXDQSDLYTG2_U1_P2 - Write DQS Delay (Timing Group DEST=2). */
13178/*! @{ */
13179#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TxDqsDlyTg2_un_px_MASK (0x3FFU)
13180#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TxDqsDlyTg2_un_px_SHIFT (0U)
13181#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TxDqsDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TxDqsDlyTg2_un_px_MASK)
13182/*! @} */
13183
13184/*! @name TXDQSDLYTG3_U1_P2 - Write DQS Delay (Timing Group DEST=3). */
13185/*! @{ */
13186#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TxDqsDlyTg3_un_px_MASK (0x3FFU)
13187#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TxDqsDlyTg3_un_px_SHIFT (0U)
13188#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TxDqsDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TxDqsDlyTg3_un_px_MASK)
13189/*! @} */
13190
13191/*! @name TXDQDLYTG0_R2_P2 - Write DQ Delay (Timing Group 0). */
13192/*! @{ */
13193#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13194#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TxDqDlyTg0_rn_px_SHIFT (0U)
13195#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TxDqDlyTg0_rn_px_MASK)
13196/*! @} */
13197
13198/*! @name TXDQDLYTG1_R2_P2 - Write DQ Delay (Timing Group 1). */
13199/*! @{ */
13200#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13201#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TxDqDlyTg1_rn_px_SHIFT (0U)
13202#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TxDqDlyTg1_rn_px_MASK)
13203/*! @} */
13204
13205/*! @name TXDQDLYTG2_R2_P2 - Write DQ Delay (Timing Group 2). */
13206/*! @{ */
13207#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU)
13208#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TxDqDlyTg2_rn_px_SHIFT (0U)
13209#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TxDqDlyTg2_rn_px_MASK)
13210/*! @} */
13211
13212/*! @name TXDQDLYTG3_R2_P2 - Write DQ Delay (Timing Group 3). */
13213/*! @{ */
13214#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU)
13215#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TxDqDlyTg3_rn_px_SHIFT (0U)
13216#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TxDqDlyTg3_rn_px_MASK)
13217/*! @} */
13218
13219/*! @name TXDQDLYTG0_R3_P2 - Write DQ Delay (Timing Group 0). */
13220/*! @{ */
13221#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13222#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TxDqDlyTg0_rn_px_SHIFT (0U)
13223#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TxDqDlyTg0_rn_px_MASK)
13224/*! @} */
13225
13226/*! @name TXDQDLYTG1_R3_P2 - Write DQ Delay (Timing Group 1). */
13227/*! @{ */
13228#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13229#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TxDqDlyTg1_rn_px_SHIFT (0U)
13230#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TxDqDlyTg1_rn_px_MASK)
13231/*! @} */
13232
13233/*! @name TXDQDLYTG2_R3_P2 - Write DQ Delay (Timing Group 2). */
13234/*! @{ */
13235#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU)
13236#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TxDqDlyTg2_rn_px_SHIFT (0U)
13237#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TxDqDlyTg2_rn_px_MASK)
13238/*! @} */
13239
13240/*! @name TXDQDLYTG3_R3_P2 - Write DQ Delay (Timing Group 3). */
13241/*! @{ */
13242#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU)
13243#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TxDqDlyTg3_rn_px_SHIFT (0U)
13244#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TxDqDlyTg3_rn_px_MASK)
13245/*! @} */
13246
13247/*! @name TXDQDLYTG0_R4_P2 - Write DQ Delay (Timing Group 0). */
13248/*! @{ */
13249#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13250#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TxDqDlyTg0_rn_px_SHIFT (0U)
13251#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TxDqDlyTg0_rn_px_MASK)
13252/*! @} */
13253
13254/*! @name TXDQDLYTG1_R4_P2 - Write DQ Delay (Timing Group 1). */
13255/*! @{ */
13256#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13257#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TxDqDlyTg1_rn_px_SHIFT (0U)
13258#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TxDqDlyTg1_rn_px_MASK)
13259/*! @} */
13260
13261/*! @name TXDQDLYTG2_R4_P2 - Write DQ Delay (Timing Group 2). */
13262/*! @{ */
13263#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU)
13264#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TxDqDlyTg2_rn_px_SHIFT (0U)
13265#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TxDqDlyTg2_rn_px_MASK)
13266/*! @} */
13267
13268/*! @name TXDQDLYTG3_R4_P2 - Write DQ Delay (Timing Group 3). */
13269/*! @{ */
13270#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU)
13271#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TxDqDlyTg3_rn_px_SHIFT (0U)
13272#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TxDqDlyTg3_rn_px_MASK)
13273/*! @} */
13274
13275/*! @name TXDQDLYTG0_R5_P2 - Write DQ Delay (Timing Group 0). */
13276/*! @{ */
13277#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13278#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TxDqDlyTg0_rn_px_SHIFT (0U)
13279#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TxDqDlyTg0_rn_px_MASK)
13280/*! @} */
13281
13282/*! @name TXDQDLYTG1_R5_P2 - Write DQ Delay (Timing Group 1). */
13283/*! @{ */
13284#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13285#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TxDqDlyTg1_rn_px_SHIFT (0U)
13286#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TxDqDlyTg1_rn_px_MASK)
13287/*! @} */
13288
13289/*! @name TXDQDLYTG2_R5_P2 - Write DQ Delay (Timing Group 2). */
13290/*! @{ */
13291#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU)
13292#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TxDqDlyTg2_rn_px_SHIFT (0U)
13293#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TxDqDlyTg2_rn_px_MASK)
13294/*! @} */
13295
13296/*! @name TXDQDLYTG3_R5_P2 - Write DQ Delay (Timing Group 3). */
13297/*! @{ */
13298#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU)
13299#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TxDqDlyTg3_rn_px_SHIFT (0U)
13300#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TxDqDlyTg3_rn_px_MASK)
13301/*! @} */
13302
13303/*! @name TXDQDLYTG0_R6_P2 - Write DQ Delay (Timing Group 0). */
13304/*! @{ */
13305#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13306#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TxDqDlyTg0_rn_px_SHIFT (0U)
13307#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TxDqDlyTg0_rn_px_MASK)
13308/*! @} */
13309
13310/*! @name TXDQDLYTG1_R6_P2 - Write DQ Delay (Timing Group 1). */
13311/*! @{ */
13312#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13313#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TxDqDlyTg1_rn_px_SHIFT (0U)
13314#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TxDqDlyTg1_rn_px_MASK)
13315/*! @} */
13316
13317/*! @name TXDQDLYTG2_R6_P2 - Write DQ Delay (Timing Group 2). */
13318/*! @{ */
13319#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU)
13320#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TxDqDlyTg2_rn_px_SHIFT (0U)
13321#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TxDqDlyTg2_rn_px_MASK)
13322/*! @} */
13323
13324/*! @name TXDQDLYTG3_R6_P2 - Write DQ Delay (Timing Group 3). */
13325/*! @{ */
13326#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU)
13327#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TxDqDlyTg3_rn_px_SHIFT (0U)
13328#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TxDqDlyTg3_rn_px_MASK)
13329/*! @} */
13330
13331/*! @name TXDQDLYTG0_R7_P2 - Write DQ Delay (Timing Group 0). */
13332/*! @{ */
13333#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13334#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TxDqDlyTg0_rn_px_SHIFT (0U)
13335#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TxDqDlyTg0_rn_px_MASK)
13336/*! @} */
13337
13338/*! @name TXDQDLYTG1_R7_P2 - Write DQ Delay (Timing Group 1). */
13339/*! @{ */
13340#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13341#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TxDqDlyTg1_rn_px_SHIFT (0U)
13342#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TxDqDlyTg1_rn_px_MASK)
13343/*! @} */
13344
13345/*! @name TXDQDLYTG2_R7_P2 - Write DQ Delay (Timing Group 2). */
13346/*! @{ */
13347#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU)
13348#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TxDqDlyTg2_rn_px_SHIFT (0U)
13349#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TxDqDlyTg2_rn_px_MASK)
13350/*! @} */
13351
13352/*! @name TXDQDLYTG3_R7_P2 - Write DQ Delay (Timing Group 3). */
13353/*! @{ */
13354#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU)
13355#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TxDqDlyTg3_rn_px_SHIFT (0U)
13356#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TxDqDlyTg3_rn_px_MASK)
13357/*! @} */
13358
13359/*! @name TXDQDLYTG0_R8_P2 - Write DQ Delay (Timing Group 0). */
13360/*! @{ */
13361#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13362#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TxDqDlyTg0_rn_px_SHIFT (0U)
13363#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TxDqDlyTg0_rn_px_MASK)
13364/*! @} */
13365
13366/*! @name TXDQDLYTG1_R8_P2 - Write DQ Delay (Timing Group 1). */
13367/*! @{ */
13368#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13369#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TxDqDlyTg1_rn_px_SHIFT (0U)
13370#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TxDqDlyTg1_rn_px_MASK)
13371/*! @} */
13372
13373/*! @name TXDQDLYTG2_R8_P2 - Write DQ Delay (Timing Group 2). */
13374/*! @{ */
13375#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU)
13376#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TxDqDlyTg2_rn_px_SHIFT (0U)
13377#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TxDqDlyTg2_rn_px_MASK)
13378/*! @} */
13379
13380/*! @name TXDQDLYTG3_R8_P2 - Write DQ Delay (Timing Group 3). */
13381/*! @{ */
13382#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU)
13383#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TxDqDlyTg3_rn_px_SHIFT (0U)
13384#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TxDqDlyTg3_rn_px_MASK)
13385/*! @} */
13386
13387/*! @name DFIMRL_P3 - DFI MaxReadLatency */
13388/*! @{ */
13389#define DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_p3_MASK (0x1FU)
13390#define DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_p3_SHIFT (0U)
13391#define DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_p3_SHIFT)) & DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_p3_MASK)
13392/*! @} */
13393
13394/*! @name TXIMPEDANCECTRL0_B0_P3 - Data TX impedance controls */
13395/*! @{ */
13396#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqP_MASK (0x3FU)
13397#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqP_SHIFT (0U)
13398#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqP_MASK)
13399#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqN_MASK (0xFC0U)
13400#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqN_SHIFT (6U)
13401#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqN_MASK)
13402/*! @} */
13403
13404/*! @name DQDQSRCVCNTRL_B0_P3 - Dq/Dqs receiver control */
13405/*! @{ */
13406#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SelAnalogVref_MASK (0x1U)
13407#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SelAnalogVref_SHIFT (0U)
13408#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SelAnalogVref_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SelAnalogVref_MASK)
13409#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_ExtVrefRange_MASK (0x2U)
13410#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_ExtVrefRange_SHIFT (1U)
13411#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_ExtVrefRange_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_ExtVrefRange_MASK)
13412#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DfeCtrl_MASK (0xCU)
13413#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DfeCtrl_SHIFT (2U)
13414#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DfeCtrl_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DfeCtrl_MASK)
13415#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MajorModeDbyte_MASK (0x70U)
13416#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MajorModeDbyte_SHIFT (4U)
13417#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MajorModeDbyte_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MajorModeDbyte_MASK)
13418#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GainCurrAdj_MASK (0xF80U)
13419#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GainCurrAdj_SHIFT (7U)
13420#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GainCurrAdj_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GainCurrAdj_MASK)
13421/*! @} */
13422
13423/*! @name TXEQUALIZATIONMODE_P3 - Tx dq driver equalization mode controls. */
13424/*! @{ */
13425#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TxEqMode_MASK (0x3U)
13426#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TxEqMode_SHIFT (0U)
13427#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TxEqMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TxEqMode_SHIFT)) & DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TxEqMode_MASK)
13428/*! @} */
13429
13430/*! @name TXIMPEDANCECTRL1_B0_P3 - TX impedance controls */
13431/*! @{ */
13432#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqP_MASK (0x3FU)
13433#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqP_SHIFT (0U)
13434#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqP_MASK)
13435#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqN_MASK (0xFC0U)
13436#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqN_SHIFT (6U)
13437#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqN_MASK)
13438/*! @} */
13439
13440/*! @name TXIMPEDANCECTRL2_B0_P3 - TX equalization impedance controls */
13441/*! @{ */
13442#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQHiDqP_MASK (0x3FU)
13443#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQHiDqP_SHIFT (0U)
13444#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQHiDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQHiDqP_MASK)
13445#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQLoDqN_MASK (0xFC0U)
13446#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQLoDqN_SHIFT (6U)
13447#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQLoDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQLoDqN_MASK)
13448/*! @} */
13449
13450/*! @name DQDQSRCVCNTRL2_P3 - Dq/Dqs receiver control */
13451/*! @{ */
13452#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_EnRxAgressivePDR_MASK (0x1U)
13453#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_EnRxAgressivePDR_SHIFT (0U)
13454#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_EnRxAgressivePDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_EnRxAgressivePDR_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_EnRxAgressivePDR_MASK)
13455/*! @} */
13456
13457/*! @name TXODTDRVSTREN_B0_P3 - TX ODT driver strength control */
13458/*! @{ */
13459#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenP_MASK (0x3FU)
13460#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenP_SHIFT (0U)
13461#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenP_MASK)
13462#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenN_MASK (0xFC0U)
13463#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenN_SHIFT (6U)
13464#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenN_MASK)
13465/*! @} */
13466
13467/*! @name TXSLEWRATE_B0_P3 - TX slew rate controls */
13468/*! @{ */
13469#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreP_MASK (0xFU)
13470#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreP_SHIFT (0U)
13471#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreP_MASK)
13472#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreN_MASK (0xF0U)
13473#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreN_SHIFT (4U)
13474#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreN_MASK)
13475#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreDrvMode_MASK (0x700U)
13476#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreDrvMode_SHIFT (8U)
13477#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreDrvMode_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreDrvMode_MASK)
13478/*! @} */
13479
13480/*! @name RXENDLYTG0_U0_P3 - Trained Receive Enable Delay (For Timing Group 0) */
13481/*! @{ */
13482#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RxEnDlyTg0_un_px_MASK (0x7FFU)
13483#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RxEnDlyTg0_un_px_SHIFT (0U)
13484#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RxEnDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RxEnDlyTg0_un_px_MASK)
13485/*! @} */
13486
13487/*! @name RXENDLYTG1_U0_P3 - Trained Receive Enable Delay (For Timing Group 1) */
13488/*! @{ */
13489#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RxEnDlyTg1_un_px_MASK (0x7FFU)
13490#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RxEnDlyTg1_un_px_SHIFT (0U)
13491#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RxEnDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RxEnDlyTg1_un_px_MASK)
13492/*! @} */
13493
13494/*! @name RXENDLYTG2_U0_P3 - Trained Receive Enable Delay (For Timing Group 2) */
13495/*! @{ */
13496#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RxEnDlyTg2_un_px_MASK (0x7FFU)
13497#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RxEnDlyTg2_un_px_SHIFT (0U)
13498#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RxEnDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RxEnDlyTg2_un_px_MASK)
13499/*! @} */
13500
13501/*! @name RXENDLYTG3_U0_P3 - Trained Receive Enable Delay (For Timing Group 3) */
13502/*! @{ */
13503#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RxEnDlyTg3_un_px_MASK (0x7FFU)
13504#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RxEnDlyTg3_un_px_SHIFT (0U)
13505#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RxEnDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RxEnDlyTg3_un_px_MASK)
13506/*! @} */
13507
13508/*! @name RXCLKDLYTG0_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
13509/*! @{ */
13510#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RxClkDlyTg0_un_px_MASK (0x3FU)
13511#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RxClkDlyTg0_un_px_SHIFT (0U)
13512#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RxClkDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RxClkDlyTg0_un_px_MASK)
13513/*! @} */
13514
13515/*! @name RXCLKDLYTG1_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
13516/*! @{ */
13517#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RxClkDlyTg1_un_px_MASK (0x3FU)
13518#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RxClkDlyTg1_un_px_SHIFT (0U)
13519#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RxClkDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RxClkDlyTg1_un_px_MASK)
13520/*! @} */
13521
13522/*! @name RXCLKDLYTG2_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
13523/*! @{ */
13524#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RxClkDlyTg2_un_px_MASK (0x3FU)
13525#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RxClkDlyTg2_un_px_SHIFT (0U)
13526#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RxClkDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RxClkDlyTg2_un_px_MASK)
13527/*! @} */
13528
13529/*! @name RXCLKDLYTG3_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
13530/*! @{ */
13531#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RxClkDlyTg3_un_px_MASK (0x3FU)
13532#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RxClkDlyTg3_un_px_SHIFT (0U)
13533#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RxClkDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RxClkDlyTg3_un_px_MASK)
13534/*! @} */
13535
13536/*! @name RXCLKCDLYTG0_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
13537/*! @{ */
13538#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RxClkcDlyTg0_un_px_MASK (0x3FU)
13539#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RxClkcDlyTg0_un_px_SHIFT (0U)
13540#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RxClkcDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RxClkcDlyTg0_un_px_MASK)
13541/*! @} */
13542
13543/*! @name RXCLKCDLYTG1_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
13544/*! @{ */
13545#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RxClkcDlyTg1_un_px_MASK (0x3FU)
13546#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RxClkcDlyTg1_un_px_SHIFT (0U)
13547#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RxClkcDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RxClkcDlyTg1_un_px_MASK)
13548/*! @} */
13549
13550/*! @name RXCLKCDLYTG2_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
13551/*! @{ */
13552#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RxClkcDlyTg2_un_px_MASK (0x3FU)
13553#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RxClkcDlyTg2_un_px_SHIFT (0U)
13554#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RxClkcDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RxClkcDlyTg2_un_px_MASK)
13555/*! @} */
13556
13557/*! @name RXCLKCDLYTG3_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
13558/*! @{ */
13559#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RxClkcDlyTg3_un_px_MASK (0x3FU)
13560#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RxClkcDlyTg3_un_px_SHIFT (0U)
13561#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RxClkcDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RxClkcDlyTg3_un_px_MASK)
13562/*! @} */
13563
13564/*! @name PPTDQSCNTINVTRNTG0_P3 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */
13565/*! @{ */
13566#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PptDqsCntInvTrnTg0_p3_MASK (0xFFFFU)
13567#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PptDqsCntInvTrnTg0_p3_SHIFT (0U)
13568#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PptDqsCntInvTrnTg0_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PptDqsCntInvTrnTg0_p3_SHIFT)) & DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PptDqsCntInvTrnTg0_p3_MASK)
13569/*! @} */
13570
13571/*! @name PPTDQSCNTINVTRNTG1_P3 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */
13572/*! @{ */
13573#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PptDqsCntInvTrnTg1_p3_MASK (0xFFFFU)
13574#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PptDqsCntInvTrnTg1_p3_SHIFT (0U)
13575#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PptDqsCntInvTrnTg1_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PptDqsCntInvTrnTg1_p3_SHIFT)) & DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PptDqsCntInvTrnTg1_p3_MASK)
13576/*! @} */
13577
13578/*! @name TXDQDLYTG0_R0_P3 - Write DQ Delay (Timing Group 0). */
13579/*! @{ */
13580#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13581#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TxDqDlyTg0_rn_px_SHIFT (0U)
13582#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TxDqDlyTg0_rn_px_MASK)
13583/*! @} */
13584
13585/*! @name TXDQDLYTG1_R0_P3 - Write DQ Delay (Timing Group 1). */
13586/*! @{ */
13587#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13588#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TxDqDlyTg1_rn_px_SHIFT (0U)
13589#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TxDqDlyTg1_rn_px_MASK)
13590/*! @} */
13591
13592/*! @name TXDQDLYTG2_R0_P3 - Write DQ Delay (Timing Group 2). */
13593/*! @{ */
13594#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU)
13595#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TxDqDlyTg2_rn_px_SHIFT (0U)
13596#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TxDqDlyTg2_rn_px_MASK)
13597/*! @} */
13598
13599/*! @name TXDQDLYTG3_R0_P3 - Write DQ Delay (Timing Group 3). */
13600/*! @{ */
13601#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU)
13602#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TxDqDlyTg3_rn_px_SHIFT (0U)
13603#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TxDqDlyTg3_rn_px_MASK)
13604/*! @} */
13605
13606/*! @name TXDQSDLYTG0_U0_P3 - Write DQS Delay (Timing Group DEST=0). */
13607/*! @{ */
13608#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TxDqsDlyTg0_un_px_MASK (0x3FFU)
13609#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TxDqsDlyTg0_un_px_SHIFT (0U)
13610#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TxDqsDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TxDqsDlyTg0_un_px_MASK)
13611/*! @} */
13612
13613/*! @name TXDQSDLYTG1_U0_P3 - Write DQS Delay (Timing Group DEST=1). */
13614/*! @{ */
13615#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TxDqsDlyTg1_un_px_MASK (0x3FFU)
13616#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TxDqsDlyTg1_un_px_SHIFT (0U)
13617#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TxDqsDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TxDqsDlyTg1_un_px_MASK)
13618/*! @} */
13619
13620/*! @name TXDQSDLYTG2_U0_P3 - Write DQS Delay (Timing Group DEST=2). */
13621/*! @{ */
13622#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TxDqsDlyTg2_un_px_MASK (0x3FFU)
13623#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TxDqsDlyTg2_un_px_SHIFT (0U)
13624#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TxDqsDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TxDqsDlyTg2_un_px_MASK)
13625/*! @} */
13626
13627/*! @name TXDQSDLYTG3_U0_P3 - Write DQS Delay (Timing Group DEST=3). */
13628/*! @{ */
13629#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TxDqsDlyTg3_un_px_MASK (0x3FFU)
13630#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TxDqsDlyTg3_un_px_SHIFT (0U)
13631#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TxDqsDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TxDqsDlyTg3_un_px_MASK)
13632/*! @} */
13633
13634/*! @name TXIMPEDANCECTRL0_B1_P3 - Data TX impedance controls */
13635/*! @{ */
13636#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqP_MASK (0x3FU)
13637#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqP_SHIFT (0U)
13638#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqP_MASK)
13639#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqN_MASK (0xFC0U)
13640#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqN_SHIFT (6U)
13641#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqN_MASK)
13642/*! @} */
13643
13644/*! @name DQDQSRCVCNTRL_B1_P3 - Dq/Dqs receiver control */
13645/*! @{ */
13646#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SelAnalogVref_MASK (0x1U)
13647#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SelAnalogVref_SHIFT (0U)
13648#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SelAnalogVref_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SelAnalogVref_MASK)
13649#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_ExtVrefRange_MASK (0x2U)
13650#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_ExtVrefRange_SHIFT (1U)
13651#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_ExtVrefRange_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_ExtVrefRange_MASK)
13652#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DfeCtrl_MASK (0xCU)
13653#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DfeCtrl_SHIFT (2U)
13654#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DfeCtrl_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DfeCtrl_MASK)
13655#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MajorModeDbyte_MASK (0x70U)
13656#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MajorModeDbyte_SHIFT (4U)
13657#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MajorModeDbyte_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MajorModeDbyte_MASK)
13658#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GainCurrAdj_MASK (0xF80U)
13659#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GainCurrAdj_SHIFT (7U)
13660#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GainCurrAdj_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GainCurrAdj_MASK)
13661/*! @} */
13662
13663/*! @name TXIMPEDANCECTRL1_B1_P3 - TX impedance controls */
13664/*! @{ */
13665#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqP_MASK (0x3FU)
13666#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqP_SHIFT (0U)
13667#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqP_MASK)
13668#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqN_MASK (0xFC0U)
13669#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqN_SHIFT (6U)
13670#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqN_MASK)
13671/*! @} */
13672
13673/*! @name TXIMPEDANCECTRL2_B1_P3 - TX equalization impedance controls */
13674/*! @{ */
13675#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQHiDqP_MASK (0x3FU)
13676#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQHiDqP_SHIFT (0U)
13677#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQHiDqP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQHiDqP_MASK)
13678#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQLoDqN_MASK (0xFC0U)
13679#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQLoDqN_SHIFT (6U)
13680#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQLoDqN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQLoDqN_MASK)
13681/*! @} */
13682
13683/*! @name TXODTDRVSTREN_B1_P3 - TX ODT driver strength control */
13684/*! @{ */
13685#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenP_MASK (0x3FU)
13686#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenP_SHIFT (0U)
13687#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenP_MASK)
13688#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenN_MASK (0xFC0U)
13689#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenN_SHIFT (6U)
13690#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenN_MASK)
13691/*! @} */
13692
13693/*! @name TXSLEWRATE_B1_P3 - TX slew rate controls */
13694/*! @{ */
13695#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreP_MASK (0xFU)
13696#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreP_SHIFT (0U)
13697#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreP_MASK)
13698#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreN_MASK (0xF0U)
13699#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreN_SHIFT (4U)
13700#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreN_MASK)
13701#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreDrvMode_MASK (0x700U)
13702#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreDrvMode_SHIFT (8U)
13703#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreDrvMode_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreDrvMode_MASK)
13704/*! @} */
13705
13706/*! @name RXENDLYTG0_U1_P3 - Trained Receive Enable Delay (For Timing Group 0) */
13707/*! @{ */
13708#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RxEnDlyTg0_un_px_MASK (0x7FFU)
13709#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RxEnDlyTg0_un_px_SHIFT (0U)
13710#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RxEnDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RxEnDlyTg0_un_px_MASK)
13711/*! @} */
13712
13713/*! @name RXENDLYTG1_U1_P3 - Trained Receive Enable Delay (For Timing Group 1) */
13714/*! @{ */
13715#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RxEnDlyTg1_un_px_MASK (0x7FFU)
13716#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RxEnDlyTg1_un_px_SHIFT (0U)
13717#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RxEnDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RxEnDlyTg1_un_px_MASK)
13718/*! @} */
13719
13720/*! @name RXENDLYTG2_U1_P3 - Trained Receive Enable Delay (For Timing Group 2) */
13721/*! @{ */
13722#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RxEnDlyTg2_un_px_MASK (0x7FFU)
13723#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RxEnDlyTg2_un_px_SHIFT (0U)
13724#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RxEnDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RxEnDlyTg2_un_px_MASK)
13725/*! @} */
13726
13727/*! @name RXENDLYTG3_U1_P3 - Trained Receive Enable Delay (For Timing Group 3) */
13728/*! @{ */
13729#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RxEnDlyTg3_un_px_MASK (0x7FFU)
13730#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RxEnDlyTg3_un_px_SHIFT (0U)
13731#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RxEnDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RxEnDlyTg3_un_px_MASK)
13732/*! @} */
13733
13734/*! @name RXCLKDLYTG0_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
13735/*! @{ */
13736#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RxClkDlyTg0_un_px_MASK (0x3FU)
13737#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RxClkDlyTg0_un_px_SHIFT (0U)
13738#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RxClkDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RxClkDlyTg0_un_px_MASK)
13739/*! @} */
13740
13741/*! @name RXCLKDLYTG1_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
13742/*! @{ */
13743#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RxClkDlyTg1_un_px_MASK (0x3FU)
13744#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RxClkDlyTg1_un_px_SHIFT (0U)
13745#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RxClkDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RxClkDlyTg1_un_px_MASK)
13746/*! @} */
13747
13748/*! @name RXCLKDLYTG2_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
13749/*! @{ */
13750#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RxClkDlyTg2_un_px_MASK (0x3FU)
13751#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RxClkDlyTg2_un_px_SHIFT (0U)
13752#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RxClkDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RxClkDlyTg2_un_px_MASK)
13753/*! @} */
13754
13755/*! @name RXCLKDLYTG3_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
13756/*! @{ */
13757#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RxClkDlyTg3_un_px_MASK (0x3FU)
13758#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RxClkDlyTg3_un_px_SHIFT (0U)
13759#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RxClkDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RxClkDlyTg3_un_px_MASK)
13760/*! @} */
13761
13762/*! @name RXCLKCDLYTG0_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
13763/*! @{ */
13764#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RxClkcDlyTg0_un_px_MASK (0x3FU)
13765#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RxClkcDlyTg0_un_px_SHIFT (0U)
13766#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RxClkcDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RxClkcDlyTg0_un_px_MASK)
13767/*! @} */
13768
13769/*! @name RXCLKCDLYTG1_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
13770/*! @{ */
13771#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RxClkcDlyTg1_un_px_MASK (0x3FU)
13772#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RxClkcDlyTg1_un_px_SHIFT (0U)
13773#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RxClkcDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RxClkcDlyTg1_un_px_MASK)
13774/*! @} */
13775
13776/*! @name RXCLKCDLYTG2_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
13777/*! @{ */
13778#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RxClkcDlyTg2_un_px_MASK (0x3FU)
13779#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RxClkcDlyTg2_un_px_SHIFT (0U)
13780#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RxClkcDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RxClkcDlyTg2_un_px_MASK)
13781/*! @} */
13782
13783/*! @name RXCLKCDLYTG3_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
13784/*! @{ */
13785#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RxClkcDlyTg3_un_px_MASK (0x3FU)
13786#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RxClkcDlyTg3_un_px_SHIFT (0U)
13787#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RxClkcDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RxClkcDlyTg3_un_px_MASK)
13788/*! @} */
13789
13790/*! @name TXDQDLYTG0_R1_P3 - Write DQ Delay (Timing Group 0). */
13791/*! @{ */
13792#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13793#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TxDqDlyTg0_rn_px_SHIFT (0U)
13794#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TxDqDlyTg0_rn_px_MASK)
13795/*! @} */
13796
13797/*! @name TXDQDLYTG1_R1_P3 - Write DQ Delay (Timing Group 1). */
13798/*! @{ */
13799#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13800#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TxDqDlyTg1_rn_px_SHIFT (0U)
13801#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TxDqDlyTg1_rn_px_MASK)
13802/*! @} */
13803
13804/*! @name TXDQDLYTG2_R1_P3 - Write DQ Delay (Timing Group 2). */
13805/*! @{ */
13806#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU)
13807#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TxDqDlyTg2_rn_px_SHIFT (0U)
13808#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TxDqDlyTg2_rn_px_MASK)
13809/*! @} */
13810
13811/*! @name TXDQDLYTG3_R1_P3 - Write DQ Delay (Timing Group 3). */
13812/*! @{ */
13813#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU)
13814#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TxDqDlyTg3_rn_px_SHIFT (0U)
13815#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TxDqDlyTg3_rn_px_MASK)
13816/*! @} */
13817
13818/*! @name TXDQSDLYTG0_U1_P3 - Write DQS Delay (Timing Group DEST=0). */
13819/*! @{ */
13820#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TxDqsDlyTg0_un_px_MASK (0x3FFU)
13821#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TxDqsDlyTg0_un_px_SHIFT (0U)
13822#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TxDqsDlyTg0_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TxDqsDlyTg0_un_px_MASK)
13823/*! @} */
13824
13825/*! @name TXDQSDLYTG1_U1_P3 - Write DQS Delay (Timing Group DEST=1). */
13826/*! @{ */
13827#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TxDqsDlyTg1_un_px_MASK (0x3FFU)
13828#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TxDqsDlyTg1_un_px_SHIFT (0U)
13829#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TxDqsDlyTg1_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TxDqsDlyTg1_un_px_MASK)
13830/*! @} */
13831
13832/*! @name TXDQSDLYTG2_U1_P3 - Write DQS Delay (Timing Group DEST=2). */
13833/*! @{ */
13834#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TxDqsDlyTg2_un_px_MASK (0x3FFU)
13835#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TxDqsDlyTg2_un_px_SHIFT (0U)
13836#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TxDqsDlyTg2_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TxDqsDlyTg2_un_px_MASK)
13837/*! @} */
13838
13839/*! @name TXDQSDLYTG3_U1_P3 - Write DQS Delay (Timing Group DEST=3). */
13840/*! @{ */
13841#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TxDqsDlyTg3_un_px_MASK (0x3FFU)
13842#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TxDqsDlyTg3_un_px_SHIFT (0U)
13843#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TxDqsDlyTg3_un_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TxDqsDlyTg3_un_px_MASK)
13844/*! @} */
13845
13846/*! @name TXDQDLYTG0_R2_P3 - Write DQ Delay (Timing Group 0). */
13847/*! @{ */
13848#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13849#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TxDqDlyTg0_rn_px_SHIFT (0U)
13850#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TxDqDlyTg0_rn_px_MASK)
13851/*! @} */
13852
13853/*! @name TXDQDLYTG1_R2_P3 - Write DQ Delay (Timing Group 1). */
13854/*! @{ */
13855#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13856#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TxDqDlyTg1_rn_px_SHIFT (0U)
13857#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TxDqDlyTg1_rn_px_MASK)
13858/*! @} */
13859
13860/*! @name TXDQDLYTG2_R2_P3 - Write DQ Delay (Timing Group 2). */
13861/*! @{ */
13862#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU)
13863#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TxDqDlyTg2_rn_px_SHIFT (0U)
13864#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TxDqDlyTg2_rn_px_MASK)
13865/*! @} */
13866
13867/*! @name TXDQDLYTG3_R2_P3 - Write DQ Delay (Timing Group 3). */
13868/*! @{ */
13869#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU)
13870#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TxDqDlyTg3_rn_px_SHIFT (0U)
13871#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TxDqDlyTg3_rn_px_MASK)
13872/*! @} */
13873
13874/*! @name TXDQDLYTG0_R3_P3 - Write DQ Delay (Timing Group 0). */
13875/*! @{ */
13876#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13877#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TxDqDlyTg0_rn_px_SHIFT (0U)
13878#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TxDqDlyTg0_rn_px_MASK)
13879/*! @} */
13880
13881/*! @name TXDQDLYTG1_R3_P3 - Write DQ Delay (Timing Group 1). */
13882/*! @{ */
13883#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13884#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TxDqDlyTg1_rn_px_SHIFT (0U)
13885#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TxDqDlyTg1_rn_px_MASK)
13886/*! @} */
13887
13888/*! @name TXDQDLYTG2_R3_P3 - Write DQ Delay (Timing Group 2). */
13889/*! @{ */
13890#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU)
13891#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TxDqDlyTg2_rn_px_SHIFT (0U)
13892#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TxDqDlyTg2_rn_px_MASK)
13893/*! @} */
13894
13895/*! @name TXDQDLYTG3_R3_P3 - Write DQ Delay (Timing Group 3). */
13896/*! @{ */
13897#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU)
13898#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TxDqDlyTg3_rn_px_SHIFT (0U)
13899#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TxDqDlyTg3_rn_px_MASK)
13900/*! @} */
13901
13902/*! @name TXDQDLYTG0_R4_P3 - Write DQ Delay (Timing Group 0). */
13903/*! @{ */
13904#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13905#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TxDqDlyTg0_rn_px_SHIFT (0U)
13906#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TxDqDlyTg0_rn_px_MASK)
13907/*! @} */
13908
13909/*! @name TXDQDLYTG1_R4_P3 - Write DQ Delay (Timing Group 1). */
13910/*! @{ */
13911#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13912#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TxDqDlyTg1_rn_px_SHIFT (0U)
13913#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TxDqDlyTg1_rn_px_MASK)
13914/*! @} */
13915
13916/*! @name TXDQDLYTG2_R4_P3 - Write DQ Delay (Timing Group 2). */
13917/*! @{ */
13918#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU)
13919#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TxDqDlyTg2_rn_px_SHIFT (0U)
13920#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TxDqDlyTg2_rn_px_MASK)
13921/*! @} */
13922
13923/*! @name TXDQDLYTG3_R4_P3 - Write DQ Delay (Timing Group 3). */
13924/*! @{ */
13925#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU)
13926#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TxDqDlyTg3_rn_px_SHIFT (0U)
13927#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TxDqDlyTg3_rn_px_MASK)
13928/*! @} */
13929
13930/*! @name TXDQDLYTG0_R5_P3 - Write DQ Delay (Timing Group 0). */
13931/*! @{ */
13932#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13933#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TxDqDlyTg0_rn_px_SHIFT (0U)
13934#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TxDqDlyTg0_rn_px_MASK)
13935/*! @} */
13936
13937/*! @name TXDQDLYTG1_R5_P3 - Write DQ Delay (Timing Group 1). */
13938/*! @{ */
13939#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13940#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TxDqDlyTg1_rn_px_SHIFT (0U)
13941#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TxDqDlyTg1_rn_px_MASK)
13942/*! @} */
13943
13944/*! @name TXDQDLYTG2_R5_P3 - Write DQ Delay (Timing Group 2). */
13945/*! @{ */
13946#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU)
13947#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TxDqDlyTg2_rn_px_SHIFT (0U)
13948#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TxDqDlyTg2_rn_px_MASK)
13949/*! @} */
13950
13951/*! @name TXDQDLYTG3_R5_P3 - Write DQ Delay (Timing Group 3). */
13952/*! @{ */
13953#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU)
13954#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TxDqDlyTg3_rn_px_SHIFT (0U)
13955#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TxDqDlyTg3_rn_px_MASK)
13956/*! @} */
13957
13958/*! @name TXDQDLYTG0_R6_P3 - Write DQ Delay (Timing Group 0). */
13959/*! @{ */
13960#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13961#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TxDqDlyTg0_rn_px_SHIFT (0U)
13962#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TxDqDlyTg0_rn_px_MASK)
13963/*! @} */
13964
13965/*! @name TXDQDLYTG1_R6_P3 - Write DQ Delay (Timing Group 1). */
13966/*! @{ */
13967#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13968#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TxDqDlyTg1_rn_px_SHIFT (0U)
13969#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TxDqDlyTg1_rn_px_MASK)
13970/*! @} */
13971
13972/*! @name TXDQDLYTG2_R6_P3 - Write DQ Delay (Timing Group 2). */
13973/*! @{ */
13974#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU)
13975#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TxDqDlyTg2_rn_px_SHIFT (0U)
13976#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TxDqDlyTg2_rn_px_MASK)
13977/*! @} */
13978
13979/*! @name TXDQDLYTG3_R6_P3 - Write DQ Delay (Timing Group 3). */
13980/*! @{ */
13981#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU)
13982#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TxDqDlyTg3_rn_px_SHIFT (0U)
13983#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TxDqDlyTg3_rn_px_MASK)
13984/*! @} */
13985
13986/*! @name TXDQDLYTG0_R7_P3 - Write DQ Delay (Timing Group 0). */
13987/*! @{ */
13988#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13989#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TxDqDlyTg0_rn_px_SHIFT (0U)
13990#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TxDqDlyTg0_rn_px_MASK)
13991/*! @} */
13992
13993/*! @name TXDQDLYTG1_R7_P3 - Write DQ Delay (Timing Group 1). */
13994/*! @{ */
13995#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13996#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TxDqDlyTg1_rn_px_SHIFT (0U)
13997#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TxDqDlyTg1_rn_px_MASK)
13998/*! @} */
13999
14000/*! @name TXDQDLYTG2_R7_P3 - Write DQ Delay (Timing Group 2). */
14001/*! @{ */
14002#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU)
14003#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TxDqDlyTg2_rn_px_SHIFT (0U)
14004#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TxDqDlyTg2_rn_px_MASK)
14005/*! @} */
14006
14007/*! @name TXDQDLYTG3_R7_P3 - Write DQ Delay (Timing Group 3). */
14008/*! @{ */
14009#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU)
14010#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TxDqDlyTg3_rn_px_SHIFT (0U)
14011#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TxDqDlyTg3_rn_px_MASK)
14012/*! @} */
14013
14014/*! @name TXDQDLYTG0_R8_P3 - Write DQ Delay (Timing Group 0). */
14015/*! @{ */
14016#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU)
14017#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TxDqDlyTg0_rn_px_SHIFT (0U)
14018#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TxDqDlyTg0_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TxDqDlyTg0_rn_px_MASK)
14019/*! @} */
14020
14021/*! @name TXDQDLYTG1_R8_P3 - Write DQ Delay (Timing Group 1). */
14022/*! @{ */
14023#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU)
14024#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TxDqDlyTg1_rn_px_SHIFT (0U)
14025#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TxDqDlyTg1_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TxDqDlyTg1_rn_px_MASK)
14026/*! @} */
14027
14028/*! @name TXDQDLYTG2_R8_P3 - Write DQ Delay (Timing Group 2). */
14029/*! @{ */
14030#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU)
14031#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TxDqDlyTg2_rn_px_SHIFT (0U)
14032#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TxDqDlyTg2_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TxDqDlyTg2_rn_px_MASK)
14033/*! @} */
14034
14035/*! @name TXDQDLYTG3_R8_P3 - Write DQ Delay (Timing Group 3). */
14036/*! @{ */
14037#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU)
14038#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TxDqDlyTg3_rn_px_SHIFT (0U)
14039#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TxDqDlyTg3_rn_px_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TxDqDlyTg3_rn_px_MASK)
14040/*! @} */
14041
14042
14043/*!
14044 * @}
14045 */ /* end of group DWC_DDRPHYA_DBYTE_Register_Masks */
14046
14047
14048/* DWC_DDRPHYA_DBYTE - Peripheral instance base addresses */
14049/** Peripheral DWC_DDRPHYA_DBYTE0 base address */
14050#define DWC_DDRPHYA_DBYTE0_BASE (0x3C010000u)
14051/** Peripheral DWC_DDRPHYA_DBYTE0 base pointer */
14052#define DWC_DDRPHYA_DBYTE0 ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE0_BASE)
14053/** Peripheral DWC_DDRPHYA_DBYTE1 base address */
14054#define DWC_DDRPHYA_DBYTE1_BASE (0x3C011000u)
14055/** Peripheral DWC_DDRPHYA_DBYTE1 base pointer */
14056#define DWC_DDRPHYA_DBYTE1 ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE1_BASE)
14057/** Peripheral DWC_DDRPHYA_DBYTE2 base address */
14058#define DWC_DDRPHYA_DBYTE2_BASE (0x3C012000u)
14059/** Peripheral DWC_DDRPHYA_DBYTE2 base pointer */
14060#define DWC_DDRPHYA_DBYTE2 ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE2_BASE)
14061/** Peripheral DWC_DDRPHYA_DBYTE3 base address */
14062#define DWC_DDRPHYA_DBYTE3_BASE (0x3C013000u)
14063/** Peripheral DWC_DDRPHYA_DBYTE3 base pointer */
14064#define DWC_DDRPHYA_DBYTE3 ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE3_BASE)
14065/** Array initializer of DWC_DDRPHYA_DBYTE peripheral base addresses */
14066#define DWC_DDRPHYA_DBYTE_BASE_ADDRS { DWC_DDRPHYA_DBYTE0_BASE, DWC_DDRPHYA_DBYTE1_BASE, DWC_DDRPHYA_DBYTE2_BASE, DWC_DDRPHYA_DBYTE3_BASE }
14067/** Array initializer of DWC_DDRPHYA_DBYTE peripheral base pointers */
14068#define DWC_DDRPHYA_DBYTE_BASE_PTRS { DWC_DDRPHYA_DBYTE0, DWC_DDRPHYA_DBYTE1, DWC_DDRPHYA_DBYTE2, DWC_DDRPHYA_DBYTE3 }
14069
14070/*!
14071 * @}
14072 */ /* end of group DWC_DDRPHYA_DBYTE_Peripheral_Access_Layer */
14073
14074
14075/* ----------------------------------------------------------------------------
14076 -- DWC_DDRPHYA_DRTUB Peripheral Access Layer
14077 ---------------------------------------------------------------------------- */
14078
14079/*!
14080 * @addtogroup DWC_DDRPHYA_DRTUB_Peripheral_Access_Layer DWC_DDRPHYA_DRTUB Peripheral Access Layer
14081 * @{
14082 */
14083
14084/** DWC_DDRPHYA_DRTUB - Register Layout Typedef */
14085typedef struct {
14086 uint8_t RESERVED_0[256];
14087 __IO uint16_t UCCLKHCLKENABLES; /**< Ucclk and Hclk enables, offset: 0x100 */
14088 __IO uint16_t CURPSTATE0B; /**< PIE current Pstate value, offset: 0x102 */
14089 uint8_t RESERVED_1[214];
14090 __I uint16_t CUSTPUBREV; /**< Customer settable by the customer, offset: 0x1DA */
14091 __I uint16_t PUBREV; /**< The hardware version of this PUB, excluding the PHY, offset: 0x1DC */
14092} DWC_DDRPHYA_DRTUB_Type;
14093
14094/* ----------------------------------------------------------------------------
14095 -- DWC_DDRPHYA_DRTUB Register Masks
14096 ---------------------------------------------------------------------------- */
14097
14098/*!
14099 * @addtogroup DWC_DDRPHYA_DRTUB_Register_Masks DWC_DDRPHYA_DRTUB Register Masks
14100 * @{
14101 */
14102
14103/*! @name UCCLKHCLKENABLES - Ucclk and Hclk enables */
14104/*! @{ */
14105#define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UcclkEn_MASK (0x1U)
14106#define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UcclkEn_SHIFT (0U)
14107#define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UcclkEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UcclkEn_SHIFT)) & DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UcclkEn_MASK)
14108#define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HclkEn_MASK (0x2U)
14109#define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HclkEn_SHIFT (1U)
14110#define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HclkEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HclkEn_SHIFT)) & DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HclkEn_MASK)
14111/*! @} */
14112
14113/*! @name CURPSTATE0B - PIE current Pstate value */
14114/*! @{ */
14115#define DWC_DDRPHYA_DRTUB_CURPSTATE0B_CurPstate0b_MASK (0xFU)
14116#define DWC_DDRPHYA_DRTUB_CURPSTATE0B_CurPstate0b_SHIFT (0U)
14117#define DWC_DDRPHYA_DRTUB_CURPSTATE0B_CurPstate0b(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_CURPSTATE0B_CurPstate0b_SHIFT)) & DWC_DDRPHYA_DRTUB_CURPSTATE0B_CurPstate0b_MASK)
14118/*! @} */
14119
14120/*! @name CUSTPUBREV - Customer settable by the customer */
14121/*! @{ */
14122#define DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_MASK (0x3FU)
14123#define DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_SHIFT (0U)
14124#define DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_SHIFT)) & DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_MASK)
14125/*! @} */
14126
14127/*! @name PUBREV - The hardware version of this PUB, excluding the PHY */
14128/*! @{ */
14129#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_MASK (0xFU)
14130#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_SHIFT (0U)
14131#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_SHIFT)) & DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_MASK)
14132#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_MASK (0xF0U)
14133#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_SHIFT (4U)
14134#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_SHIFT)) & DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_MASK)
14135#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_MASK (0xFF00U)
14136#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_SHIFT (8U)
14137#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_SHIFT)) & DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_MASK)
14138/*! @} */
14139
14140
14141/*!
14142 * @}
14143 */ /* end of group DWC_DDRPHYA_DRTUB_Register_Masks */
14144
14145
14146/* DWC_DDRPHYA_DRTUB - Peripheral instance base addresses */
14147/** Peripheral DWC_DDRPHYA_DRTUB0 base address */
14148#define DWC_DDRPHYA_DRTUB0_BASE (0x3C0C0000u)
14149/** Peripheral DWC_DDRPHYA_DRTUB0 base pointer */
14150#define DWC_DDRPHYA_DRTUB0 ((DWC_DDRPHYA_DRTUB_Type *)DWC_DDRPHYA_DRTUB0_BASE)
14151/** Array initializer of DWC_DDRPHYA_DRTUB peripheral base addresses */
14152#define DWC_DDRPHYA_DRTUB_BASE_ADDRS { DWC_DDRPHYA_DRTUB0_BASE }
14153/** Array initializer of DWC_DDRPHYA_DRTUB peripheral base pointers */
14154#define DWC_DDRPHYA_DRTUB_BASE_PTRS { DWC_DDRPHYA_DRTUB0 }
14155
14156/*!
14157 * @}
14158 */ /* end of group DWC_DDRPHYA_DRTUB_Peripheral_Access_Layer */
14159
14160
14161/* ----------------------------------------------------------------------------
14162 -- DWC_DDRPHYA_INITENG Peripheral Access Layer
14163 ---------------------------------------------------------------------------- */
14164
14165/*!
14166 * @addtogroup DWC_DDRPHYA_INITENG_Peripheral_Access_Layer DWC_DDRPHYA_INITENG Peripheral Access Layer
14167 * @{
14168 */
14169
14170/** DWC_DDRPHYA_INITENG - Register Layout Typedef */
14171typedef struct {
14172 uint8_t RESERVED_0[80];
14173 __IO uint16_t PHYINLP3; /**< Indicator for PIE Lower Power 3 (LP3) Status, offset: 0x50 */
14174} DWC_DDRPHYA_INITENG_Type;
14175
14176/* ----------------------------------------------------------------------------
14177 -- DWC_DDRPHYA_INITENG Register Masks
14178 ---------------------------------------------------------------------------- */
14179
14180/*!
14181 * @addtogroup DWC_DDRPHYA_INITENG_Register_Masks DWC_DDRPHYA_INITENG Register Masks
14182 * @{
14183 */
14184
14185/*! @name PHYINLP3 - Indicator for PIE Lower Power 3 (LP3) Status */
14186/*! @{ */
14187#define DWC_DDRPHYA_INITENG_PHYINLP3_PhyInLP3_MASK (0x1U)
14188#define DWC_DDRPHYA_INITENG_PHYINLP3_PhyInLP3_SHIFT (0U)
14189#define DWC_DDRPHYA_INITENG_PHYINLP3_PhyInLP3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_INITENG_PHYINLP3_PhyInLP3_SHIFT)) & DWC_DDRPHYA_INITENG_PHYINLP3_PhyInLP3_MASK)
14190/*! @} */
14191
14192
14193/*!
14194 * @}
14195 */ /* end of group DWC_DDRPHYA_INITENG_Register_Masks */
14196
14197
14198/* DWC_DDRPHYA_INITENG - Peripheral instance base addresses */
14199/** Peripheral DWC_DDRPHYA_INITENG0 base address */
14200#define DWC_DDRPHYA_INITENG0_BASE (0x3C090000u)
14201/** Peripheral DWC_DDRPHYA_INITENG0 base pointer */
14202#define DWC_DDRPHYA_INITENG0 ((DWC_DDRPHYA_INITENG_Type *)DWC_DDRPHYA_INITENG0_BASE)
14203/** Array initializer of DWC_DDRPHYA_INITENG peripheral base addresses */
14204#define DWC_DDRPHYA_INITENG_BASE_ADDRS { DWC_DDRPHYA_INITENG0_BASE }
14205/** Array initializer of DWC_DDRPHYA_INITENG peripheral base pointers */
14206#define DWC_DDRPHYA_INITENG_BASE_PTRS { DWC_DDRPHYA_INITENG0 }
14207
14208/*!
14209 * @}
14210 */ /* end of group DWC_DDRPHYA_INITENG_Peripheral_Access_Layer */
14211
14212
14213/* ----------------------------------------------------------------------------
14214 -- DWC_DDRPHYA_MASTER Peripheral Access Layer
14215 ---------------------------------------------------------------------------- */
14216
14217/*!
14218 * @addtogroup DWC_DDRPHYA_MASTER_Peripheral_Access_Layer DWC_DDRPHYA_MASTER Peripheral Access Layer
14219 * @{
14220 */
14221
14222/** DWC_DDRPHYA_MASTER - Register Layout Typedef */
14223typedef struct {
14224 __IO uint16_t RXFIFOINIT; /**< Rx FIFO pointer initialization control, offset: 0x0 */
14225 __IO uint16_t FORCECLKDISABLE; /**< Clock gating control, offset: 0x2 */
14226 uint8_t RESERVED_0[2];
14227 __IO uint16_t FORCEINTERNALUPDATE; /**< This Register used by Training Firmware to force an internal PHY Update Event., offset: 0x6 */
14228 __I uint16_t PHYCONFIG; /**< Read Only displays PHY Configuration., offset: 0x8 */
14229 __IO uint16_t PGCR; /**< PHY General Configuration Register(PGCR)., offset: 0xA */
14230 uint8_t RESERVED_1[2];
14231 __IO uint16_t TESTBUMPCNTRL1; /**< Test Bump Control1, offset: 0xE */
14232 __IO uint16_t CALUCLKINFO_P0; /**< Impedance Calibration Clock Ratio, offset: 0x10 */
14233 uint8_t RESERVED_2[2];
14234 __IO uint16_t TESTBUMPCNTRL; /**< Test Bump Control, offset: 0x14 */
14235 __IO uint16_t SEQ0BDLY0_P0; /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x16 */
14236 __IO uint16_t SEQ0BDLY1_P0; /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x18 */
14237 __IO uint16_t SEQ0BDLY2_P0; /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x1A */
14238 __IO uint16_t SEQ0BDLY3_P0; /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x1C */
14239 __I uint16_t PHYALERTSTATUS; /**< PHY Alert status bit, offset: 0x1E */
14240 __IO uint16_t PPTTRAINSETUP_P0; /**< Setup Intervals for DFI PHY Master operations, offset: 0x20 */
14241 uint8_t RESERVED_3[2];
14242 __IO uint16_t ATESTMODE; /**< ATestMode control, offset: 0x24 */
14243 uint8_t RESERVED_4[2];
14244 __I uint16_t TXCALBINP; /**< TX P Impedance Calibration observation, offset: 0x28 */
14245 __I uint16_t TXCALBINN; /**< TX N Impedance Calibration observation, offset: 0x2A */
14246 __IO uint16_t TXCALPOVR; /**< TX P Impedance Calibration override, offset: 0x2C */
14247 __IO uint16_t TXCALNOVR; /**< TX N Impedance Calibration override, offset: 0x2E */
14248 __IO uint16_t DFIMODE; /**< Enables for update and low-power interfaces for DFI0 and DFI1, offset: 0x30 */
14249 __IO uint16_t TRISTATEMODECA_P0; /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x32 */
14250 __IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x34 */
14251 __IO uint16_t MTESTPGMINFO; /**< Digital Observation Pin program info for debug, offset: 0x36 */
14252 __IO uint16_t DYNPWRDNUP; /**< Dynaimc Power Up/Down control, offset: 0x38 */
14253 uint8_t RESERVED_5[2];
14254 __IO uint16_t PHYTID; /**< PHY Technology ID Register, offset: 0x3C */
14255 uint8_t RESERVED_6[2];
14256 __IO uint16_t HWTMRL_P0; /**< HWT MaxReadLatency., offset: 0x40 */
14257 __IO uint16_t DFIPHYUPD; /**< DFI PhyUpdate Request time counter (in MEMCLKs), offset: 0x42 */
14258 __IO uint16_t PDAMRSWRITEMODE; /**< Controls the write DQ generation for Per-Dram-Addressing of MRS, offset: 0x44 */
14259 __IO uint16_t DFIGEARDOWNCTL; /**< Controls whether dfi_geardown_en will cause CS and CKE timing to change., offset: 0x46 */
14260 __IO uint16_t DQSPREAMBLECONTROL_P0; /**< Control the PHY logic related to the read and write DQS preamble, offset: 0x48 */
14261 __IO uint16_t MASTERX4CONFIG; /**< DBYTE module controls to select X4 Dram device mode, offset: 0x4A */
14262 __IO uint16_t WRLEVBITS; /**< Write level feedback DQ observability select., offset: 0x4C */
14263 __IO uint16_t ENABLECSMULTICAST; /**< In DDR4 Mode , this controls whether CS_N[3:2] should be multicast on CID[1:0], offset: 0x4E */
14264 __IO uint16_t HWTLPCSMULTICAST; /**< Drives cs_n[0] onto cs_n[1] during training, offset: 0x50 */
14265 uint8_t RESERVED_7[6];
14266 __IO uint16_t ACX4ANIBDIS; /**< Disable for unused ACX Nibbles, offset: 0x58 */
14267 __IO uint16_t DMIPINPRESENT_P0; /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x5A */
14268 __IO uint16_t ARDPTRINITVAL_P0; /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x5C */
14269 uint8_t RESERVED_8[22];
14270 __IO uint16_t DBYTEDLLMODECNTRL; /**< DLL Mode control CSR for DBYTEs, offset: 0x74 */
14271 uint8_t RESERVED_9[20];
14272 __IO uint16_t CALOFFSETS; /**< Impedance Calibration offsets control, offset: 0x8A */
14273 uint8_t RESERVED_10[2];
14274 __IO uint16_t SARINITVALS; /**< Sar Init Vals, offset: 0x8E */
14275 uint8_t RESERVED_11[2];
14276 __IO uint16_t CALPEXTOVR; /**< Impedance Calibration PExt Override control, offset: 0x92 */
14277 __IO uint16_t CALCMPR5OVR; /**< Impedance Calibration Cmpr 50 control, offset: 0x94 */
14278 __IO uint16_t CALNINTOVR; /**< Impedance Calibration NInt Override control, offset: 0x96 */
14279 uint8_t RESERVED_12[8];
14280 __IO uint16_t CALDRVSTR0; /**< Impedance Calibration driver strength control, offset: 0xA0 */
14281 uint8_t RESERVED_13[10];
14282 __IO uint16_t PROCODTTIMECTL_P0; /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0xAC */
14283 uint8_t RESERVED_14[8];
14284 __IO uint16_t MEMALERTCONTROL; /**< This Register is used to configure the MemAlert Receiver, offset: 0xB6 */
14285 __IO uint16_t MEMALERTCONTROL2; /**< This Register is used to configure the MemAlert Receiver, offset: 0xB8 */
14286 uint8_t RESERVED_15[6];
14287 __IO uint16_t MEMRESETL; /**< Protection and control of BP_MemReset_L, offset: 0xC0 */
14288 uint8_t RESERVED_16[24];
14289 __IO uint16_t DRIVECSLOWONTOHIGH; /**< Drive CS_N 3:0 onto CS_N 7:4, offset: 0xDA */
14290 __IO uint16_t PUBMODE; /**< PUBMODE - HWT Mux Select, offset: 0xDC */
14291 __I uint16_t MISCPHYSTATUS; /**< Misc PHY status bits, offset: 0xDE */
14292 __IO uint16_t CORELOOPBACKSEL; /**< Controls whether the loopback path bypasses the final PAD node., offset: 0xE0 */
14293 __IO uint16_t DLLTRAINPARAM; /**< DLL Various Training Parameters, offset: 0xE2 */
14294 uint8_t RESERVED_17[4];
14295 __IO uint16_t HWTLPCSENBYPASS; /**< CSn Disable Bypass for LPDDR3/4, offset: 0xE8 */
14296 __IO uint16_t DFICAMODE; /**< Dfi Command/Address Mode, offset: 0xEA */
14297 uint8_t RESERVED_18[4];
14298 __IO uint16_t DLLCONTROL; /**< DLL Lock State machine control register, offset: 0xF0 */
14299 __IO uint16_t PULSEDLLUPDATEPHASE; /**< DLL update phase control, offset: 0xF2 */
14300 uint8_t RESERVED_19[4];
14301 __IO uint16_t DLLGAINCTL_P0; /**< DLL gain control, offset: 0xF8 */
14302 uint8_t RESERVED_20[22];
14303 __IO uint16_t CALRATE; /**< Impedance Calibration Control, offset: 0x110 */
14304 __IO uint16_t CALZAP; /**< Impedance Calibration Zap/Reset, offset: 0x112 */
14305 uint8_t RESERVED_21[2];
14306 __IO uint16_t PSTATE; /**< PSTATE Selection, offset: 0x116 */
14307 uint8_t RESERVED_22[2];
14308 __IO uint16_t PLLOUTGATECONTROL; /**< PLL Output Control, offset: 0x11A */
14309 uint8_t RESERVED_23[4];
14310 __IO uint16_t PORCONTROL; /**< PMU Power-on Reset Control (PLL/DLL Lock Done), offset: 0x120 */
14311 uint8_t RESERVED_24[12];
14312 __I uint16_t CALBUSY; /**< Impedance Calibration Busy Status, offset: 0x12E */
14313 __IO uint16_t CALMISC2; /**< Miscellaneous impedance calibration controls., offset: 0x130 */
14314 uint8_t RESERVED_25[2];
14315 __IO uint16_t CALMISC; /**< Controls for disabling the impedance calibration of certain targets., offset: 0x134 */
14316 __I uint16_t CALVREFS; /**< , offset: 0x136 */
14317 __I uint16_t CALCMPR5; /**< Impedance Calibration Cmpr control, offset: 0x138 */
14318 __I uint16_t CALNINT; /**< Impedance Calibration NInt control, offset: 0x13A */
14319 __I uint16_t CALPEXT; /**< Impedance Calibration PExt control, offset: 0x13C */
14320 uint8_t RESERVED_26[18];
14321 __IO uint16_t CALCMPINVERT; /**< Impedance Calibration Cmp Invert control, offset: 0x150 */
14322 uint8_t RESERVED_27[10];
14323 __IO uint16_t CALCMPANACNTRL; /**< Impedance Calibration Cmpana control, offset: 0x15C */
14324 uint8_t RESERVED_28[2];
14325 __IO uint16_t DFIRDDATACSDESTMAP_P0; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x160 */
14326 uint8_t RESERVED_29[2];
14327 __IO uint16_t VREFINGLOBAL_P0; /**< PHY Global Vref Controls, offset: 0x164 */
14328 uint8_t RESERVED_30[2];
14329 __IO uint16_t DFIWRDATACSDESTMAP_P0; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x168 */
14330 __I uint16_t MASUPDGOODCTR; /**< Counts successful PHY Master Interface Updates (PPTs), offset: 0x16A */
14331 __I uint16_t PHYUPD0GOODCTR; /**< Counts successful PHY-initiated DFI0 Interface Updates, offset: 0x16C */
14332 __I uint16_t PHYUPD1GOODCTR; /**< Counts successful PHY-initiated DFI1 Interface Updates, offset: 0x16E */
14333 __I uint16_t CTLUPD0GOODCTR; /**< Counts successful Memory Controller DFI0 Interface Updates, offset: 0x170 */
14334 __I uint16_t CTLUPD1GOODCTR; /**< Counts successful Memory Controller DFI1 Interface Updates, offset: 0x172 */
14335 __I uint16_t MASUPDFAILCTR; /**< Counts unsuccessful PHY Master Interface Updates, offset: 0x174 */
14336 __I uint16_t PHYUPD0FAILCTR; /**< Counts unsuccessful PHY-initiated DFI0 Interface Updates, offset: 0x176 */
14337 __I uint16_t PHYUPD1FAILCTR; /**< Counts unsuccessful PHY-initiated DFI1 Interface Updates, offset: 0x178 */
14338 __IO uint16_t PHYPERFCTRENABLE; /**< Enables for Performance Counters, offset: 0x17A */
14339 uint8_t RESERVED_31[10];
14340 __IO uint16_t PLLPWRDN; /**< PLL Power Down, offset: 0x186 */
14341 __IO uint16_t PLLRESET; /**< PLL Reset, offset: 0x188 */
14342 __IO uint16_t PLLCTRL2_P0; /**< PState dependent PLL Control Register 2, offset: 0x18A */
14343 __IO uint16_t PLLCTRL0; /**< PLL Control Register 0, offset: 0x18C */
14344 __IO uint16_t PLLCTRL1_P0; /**< PState dependent PLL Control Register 1, offset: 0x18E */
14345 __IO uint16_t PLLTST; /**< PLL Testing Control Register, offset: 0x190 */
14346 __I uint16_t PLLLOCKSTATUS; /**< PLL's pll_lock pin output, offset: 0x192 */
14347 __IO uint16_t PLLTESTMODE_P0; /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x194 */
14348 __IO uint16_t PLLCTRL3; /**< PLL Control Register 3, offset: 0x196 */
14349 __IO uint16_t PLLCTRL4_P0; /**< PState dependent PLL Control Register 4, offset: 0x198 */
14350 __I uint16_t PLLENDOFCAL; /**< PLL's eoc (end of calibration) output, offset: 0x19A */
14351 __I uint16_t PLLSTANDBYEFF; /**< PLL's standby_eff (effective standby) output, offset: 0x19C */
14352 __I uint16_t PLLDACVALOUT; /**< PLL's Dacval_out output, offset: 0x19E */
14353 uint8_t RESERVED_32[38];
14354 __IO uint16_t LCDLDBGCNTL; /**< Controls for use in observing and testing the LCDLs., offset: 0x1C6 */
14355 __I uint16_t ACLCDLSTATUS; /**< Debug status of the DBYTE LCDL, offset: 0x1C8 */
14356 uint8_t RESERVED_33[16];
14357 __I uint16_t CUSTPHYREV; /**< Customer settable by the customer, offset: 0x1DA */
14358 __I uint16_t PHYREV; /**< The hardware version of this PHY, excluding the PUB, offset: 0x1DC */
14359 __IO uint16_t LP3EXITSEQ0BSTARTVECTOR; /**< Start vector value to be used for LP3-exit or Init PIE Sequence, offset: 0x1DE */
14360 __IO uint16_t DFIFREQXLAT0; /**< DFI Frequency Translation Register 0, offset: 0x1E0 */
14361 __IO uint16_t DFIFREQXLAT1; /**< DFI Frequency Translation Register 1, offset: 0x1E2 */
14362 __IO uint16_t DFIFREQXLAT2; /**< DFI Frequency Translation Register 2, offset: 0x1E4 */
14363 __IO uint16_t DFIFREQXLAT3; /**< DFI Frequency Translation Register 3, offset: 0x1E6 */
14364 __IO uint16_t DFIFREQXLAT4; /**< DFI Frequency Translation Register 4, offset: 0x1E8 */
14365 __IO uint16_t DFIFREQXLAT5; /**< DFI Frequency Translation Register 5, offset: 0x1EA */
14366 __IO uint16_t DFIFREQXLAT6; /**< DFI Frequency Translation Register 6, offset: 0x1EC */
14367 __IO uint16_t DFIFREQXLAT7; /**< DFI Frequency Translation Register 7, offset: 0x1EE */
14368 __IO uint16_t TXRDPTRINIT; /**< TxRdPtrInit control register, offset: 0x1F0 */
14369 __IO uint16_t DFIINITCOMPLETE; /**< DFI Init Complete control, offset: 0x1F2 */
14370 __IO uint16_t DFIFREQRATIO_P0; /**< DFI Frequency Ratio, offset: 0x1F4 */
14371 __IO uint16_t RXFIFOCHECKS; /**< Enable more frequent consistency checks of the RX FIFOs, offset: 0x1F6 */
14372 uint8_t RESERVED_34[6];
14373 __IO uint16_t MTESTDTOCTRL; /**< , offset: 0x1FE */
14374 __IO uint16_t MAPCAA0TODFI; /**< Maps PHY CAA lane 0 from dfi0_address of the index of the register contents, offset: 0x200 */
14375 __IO uint16_t MAPCAA1TODFI; /**< Maps PHY CAA lane 1 from dfi0_address of the index of the register contents, offset: 0x202 */
14376 __IO uint16_t MAPCAA2TODFI; /**< Maps PHY CAA lane 2 from dfi0_address of the index of the register contents, offset: 0x204 */
14377 __IO uint16_t MAPCAA3TODFI; /**< Maps PHY CAA lane 3 from dfi0_address of the index of the register contents, offset: 0x206 */
14378 __IO uint16_t MAPCAA4TODFI; /**< Maps PHY CAA lane 4 from dfi0_address of the index of the register contents, offset: 0x208 */
14379 __IO uint16_t MAPCAA5TODFI; /**< Maps PHY CAA lane 5 from dfi0_address of the index of the register contents, offset: 0x20A */
14380 __IO uint16_t MAPCAA6TODFI; /**< Maps PHY CAA lane 6 from dfi0_address of the index of the register contents, offset: 0x20C */
14381 __IO uint16_t MAPCAA7TODFI; /**< Maps PHY CAA lane 7 from dfi0_address of the index of the register contents, offset: 0x20E */
14382 __IO uint16_t MAPCAA8TODFI; /**< Maps PHY CAA lane 8 from dfi0_address of the index of the register contents, offset: 0x210 */
14383 __IO uint16_t MAPCAA9TODFI; /**< Maps PHY CAA lane 9 from dfi0_address of the index of the register contents, offset: 0x212 */
14384 uint8_t RESERVED_35[12];
14385 __IO uint16_t MAPCAB0TODFI; /**< Maps PHY CAB lane 0 from dfi1_address of the index of the register contents, offset: 0x220 */
14386 __IO uint16_t MAPCAB1TODFI; /**< Maps PHY CAB lane 1 from dfi1_address of the index of the register contents, offset: 0x222 */
14387 __IO uint16_t MAPCAB2TODFI; /**< Maps PHY CAB lane 2 from dfi1_address of the index of the register contents, offset: 0x224 */
14388 __IO uint16_t MAPCAB3TODFI; /**< Maps PHY CAB lane 3 from dfi1_address of the index of the register contents, offset: 0x226 */
14389 __IO uint16_t MAPCAB4TODFI; /**< Maps PHY CAB lane 4 from dfi1_address of the index of the register contents, offset: 0x228 */
14390 __IO uint16_t MAPCAB5TODFI; /**< Maps PHY CAB lane 5 from dfi1_address of the index of the register contents, offset: 0x22A */
14391 __IO uint16_t MAPCAB6TODFI; /**< Maps PHY CAB lane 6 from dfi1_address of the index of the register contents, offset: 0x22C */
14392 __IO uint16_t MAPCAB7TODFI; /**< Maps PHY CAB lane 7 from dfi1_address of the index of the register contents, offset: 0x22E */
14393 __IO uint16_t MAPCAB8TODFI; /**< Maps PHY CAB lane 8 from dfi1_address of the index of the register contents, offset: 0x230 */
14394 __IO uint16_t MAPCAB9TODFI; /**< Maps PHY CAB lane 9 from dfi1_address of the index of the register contents, offset: 0x232 */
14395 uint8_t RESERVED_36[2];
14396 __IO uint16_t PHYINTERRUPTENABLE; /**< Interrupt Enable Bits, offset: 0x236 */
14397 __IO uint16_t PHYINTERRUPTFWCONTROL; /**< Interrupt Firmware Control Bits, offset: 0x238 */
14398 __IO uint16_t PHYINTERRUPTMASK; /**< Interrupt Mask Bits, offset: 0x23A */
14399 __IO uint16_t PHYINTERRUPTCLEAR; /**< Interrupt Clear Bits, offset: 0x23C */
14400 __I uint16_t PHYINTERRUPTSTATUS; /**< Interrupt Status Bits, offset: 0x23E */
14401 __IO uint16_t HWTSWIZZLEHWTADDRESS0; /**< Signal swizzle selection for HWT swizzle, offset: 0x240 */
14402 __IO uint16_t HWTSWIZZLEHWTADDRESS1; /**< Signal swizzle selection for HWT swizzle, offset: 0x242 */
14403 __IO uint16_t HWTSWIZZLEHWTADDRESS2; /**< Signal swizzle selection for HWT swizzle, offset: 0x244 */
14404 __IO uint16_t HWTSWIZZLEHWTADDRESS3; /**< Signal swizzle selection for HWT swizzle, offset: 0x246 */
14405 __IO uint16_t HWTSWIZZLEHWTADDRESS4; /**< Signal swizzle selection for HWT swizzle, offset: 0x248 */
14406 __IO uint16_t HWTSWIZZLEHWTADDRESS5; /**< Signal swizzle selection for HWT swizzle, offset: 0x24A */
14407 __IO uint16_t HWTSWIZZLEHWTADDRESS6; /**< Signal swizzle selection for HWT swizzle, offset: 0x24C */
14408 __IO uint16_t HWTSWIZZLEHWTADDRESS7; /**< Signal swizzle selection for HWT swizzle, offset: 0x24E */
14409 __IO uint16_t HWTSWIZZLEHWTADDRESS8; /**< Signal swizzle selection for HWT swizzle, offset: 0x250 */
14410 __IO uint16_t HWTSWIZZLEHWTADDRESS9; /**< Signal swizzle selection for HWT swizzle, offset: 0x252 */
14411 __IO uint16_t HWTSWIZZLEHWTADDRESS10; /**< Signal swizzle selection for HWT swizzle, offset: 0x254 */
14412 __IO uint16_t HWTSWIZZLEHWTADDRESS11; /**< Signal swizzle selection for HWT swizzle, offset: 0x256 */
14413 __IO uint16_t HWTSWIZZLEHWTADDRESS12; /**< Signal swizzle selection for HWT swizzle, offset: 0x258 */
14414 __IO uint16_t HWTSWIZZLEHWTADDRESS13; /**< Signal swizzle selection for HWT swizzle, offset: 0x25A */
14415 __IO uint16_t HWTSWIZZLEHWTADDRESS14; /**< Signal swizzle selection for HWT swizzle, offset: 0x25C */
14416 __IO uint16_t HWTSWIZZLEHWTADDRESS15; /**< Signal swizzle selection for HWT swizzle, offset: 0x25E */
14417 __IO uint16_t HWTSWIZZLEHWTADDRESS17; /**< Signal swizzle selection for HWT swizzle, offset: 0x260 */
14418 __IO uint16_t HWTSWIZZLEHWTACTN; /**< Signal swizzle selection for HWT swizzle, offset: 0x262 */
14419 __IO uint16_t HWTSWIZZLEHWTBANK0; /**< Signal swizzle selection for HWT swizzle, offset: 0x264 */
14420 __IO uint16_t HWTSWIZZLEHWTBANK1; /**< Signal swizzle selection for HWT swizzle, offset: 0x266 */
14421 __IO uint16_t HWTSWIZZLEHWTBANK2; /**< Signal swizzle selection for HWT swizzle, offset: 0x268 */
14422 __IO uint16_t HWTSWIZZLEHWTBG0; /**< Signal swizzle selection for HWT swizzle, offset: 0x26A */
14423 __IO uint16_t HWTSWIZZLEHWTBG1; /**< Signal swizzle selection for HWT swizzle, offset: 0x26C */
14424 __IO uint16_t HWTSWIZZLEHWTCASN; /**< Signal swizzle selection for HWT swizzle, offset: 0x26E */
14425 __IO uint16_t HWTSWIZZLEHWTRASN; /**< Signal swizzle selection for HWT swizzle, offset: 0x270 */
14426 __IO uint16_t HWTSWIZZLEHWTWEN; /**< Signal swizzle selection for HWT swizzle, offset: 0x272 */
14427 __IO uint16_t HWTSWIZZLEHWTPARITYIN; /**< Signal swizzle selection for HWT swizzle, offset: 0x274 */
14428 uint8_t RESERVED_37[2];
14429 __IO uint16_t DFIHANDSHAKEDELAYS0; /**< Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal assertions exceed the programmed delays, offset: 0x278 */
14430 __IO uint16_t DFIHANDSHAKEDELAYS1; /**< Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal assertions exceed the programmed delays, offset: 0x27A */
14431 uint8_t RESERVED_38[2096532];
14432 __IO uint16_t CALUCLKINFO_P1; /**< Impedance Calibration Clock Ratio, offset: 0x200010 */
14433 uint8_t RESERVED_39[4];
14434 __IO uint16_t SEQ0BDLY0_P1; /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x200016 */
14435 __IO uint16_t SEQ0BDLY1_P1; /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x200018 */
14436 __IO uint16_t SEQ0BDLY2_P1; /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x20001A */
14437 __IO uint16_t SEQ0BDLY3_P1; /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x20001C */
14438 uint8_t RESERVED_40[2];
14439 __IO uint16_t PPTTRAINSETUP_P1; /**< Setup Intervals for DFI PHY Master operations, offset: 0x200020 */
14440 uint8_t RESERVED_41[16];
14441 __IO uint16_t TRISTATEMODECA_P1; /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x200032 */
14442 uint8_t RESERVED_42[12];
14443 __IO uint16_t HWTMRL_P1; /**< HWT MaxReadLatency., offset: 0x200040 */
14444 uint8_t RESERVED_43[6];
14445 __IO uint16_t DQSPREAMBLECONTROL_P1; /**< Control the PHY logic related to the read and write DQS preamble, offset: 0x200048 */
14446 uint8_t RESERVED_44[16];
14447 __IO uint16_t DMIPINPRESENT_P1; /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x20005A */
14448 __IO uint16_t ARDPTRINITVAL_P1; /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x20005C */
14449 uint8_t RESERVED_45[78];
14450 __IO uint16_t PROCODTTIMECTL_P1; /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0x2000AC */
14451 uint8_t RESERVED_46[74];
14452 __IO uint16_t DLLGAINCTL_P1; /**< DLL gain control, offset: 0x2000F8 */
14453 uint8_t RESERVED_47[102];
14454 __IO uint16_t DFIRDDATACSDESTMAP_P1; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x200160 */
14455 uint8_t RESERVED_48[2];
14456 __IO uint16_t VREFINGLOBAL_P1; /**< PHY Global Vref Controls, offset: 0x200164 */
14457 uint8_t RESERVED_49[2];
14458 __IO uint16_t DFIWRDATACSDESTMAP_P1; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x200168 */
14459 uint8_t RESERVED_50[32];
14460 __IO uint16_t PLLCTRL2_P1; /**< PState dependent PLL Control Register 2, offset: 0x20018A */
14461 uint8_t RESERVED_51[2];
14462 __IO uint16_t PLLCTRL1_P1; /**< PState dependent PLL Control Register 1, offset: 0x20018E */
14463 uint8_t RESERVED_52[4];
14464 __IO uint16_t PLLTESTMODE_P1; /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x200194 */
14465 uint8_t RESERVED_53[2];
14466 __IO uint16_t PLLCTRL4_P1; /**< PState dependent PLL Control Register 4, offset: 0x200198 */
14467 uint8_t RESERVED_54[90];
14468 __IO uint16_t DFIFREQRATIO_P1; /**< DFI Frequency Ratio, offset: 0x2001F4 */
14469 uint8_t RESERVED_55[2096666];
14470 __IO uint16_t CALUCLKINFO_P2; /**< Impedance Calibration Clock Ratio, offset: 0x400010 */
14471 uint8_t RESERVED_56[4];
14472 __IO uint16_t SEQ0BDLY0_P2; /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x400016 */
14473 __IO uint16_t SEQ0BDLY1_P2; /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x400018 */
14474 __IO uint16_t SEQ0BDLY2_P2; /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x40001A */
14475 __IO uint16_t SEQ0BDLY3_P2; /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x40001C */
14476 uint8_t RESERVED_57[2];
14477 __IO uint16_t PPTTRAINSETUP_P2; /**< Setup Intervals for DFI PHY Master operations, offset: 0x400020 */
14478 uint8_t RESERVED_58[16];
14479 __IO uint16_t TRISTATEMODECA_P2; /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x400032 */
14480 uint8_t RESERVED_59[12];
14481 __IO uint16_t HWTMRL_P2; /**< HWT MaxReadLatency., offset: 0x400040 */
14482 uint8_t RESERVED_60[6];
14483 __IO uint16_t DQSPREAMBLECONTROL_P2; /**< Control the PHY logic related to the read and write DQS preamble, offset: 0x400048 */
14484 uint8_t RESERVED_61[16];
14485 __IO uint16_t DMIPINPRESENT_P2; /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x40005A */
14486 __IO uint16_t ARDPTRINITVAL_P2; /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x40005C */
14487 uint8_t RESERVED_62[78];
14488 __IO uint16_t PROCODTTIMECTL_P2; /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0x4000AC */
14489 uint8_t RESERVED_63[74];
14490 __IO uint16_t DLLGAINCTL_P2; /**< DLL gain control, offset: 0x4000F8 */
14491 uint8_t RESERVED_64[102];
14492 __IO uint16_t DFIRDDATACSDESTMAP_P2; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x400160 */
14493 uint8_t RESERVED_65[2];
14494 __IO uint16_t VREFINGLOBAL_P2; /**< PHY Global Vref Controls, offset: 0x400164 */
14495 uint8_t RESERVED_66[2];
14496 __IO uint16_t DFIWRDATACSDESTMAP_P2; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x400168 */
14497 uint8_t RESERVED_67[32];
14498 __IO uint16_t PLLCTRL2_P2; /**< PState dependent PLL Control Register 2, offset: 0x40018A */
14499 uint8_t RESERVED_68[2];
14500 __IO uint16_t PLLCTRL1_P2; /**< PState dependent PLL Control Register 1, offset: 0x40018E */
14501 uint8_t RESERVED_69[4];
14502 __IO uint16_t PLLTESTMODE_P2; /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x400194 */
14503 uint8_t RESERVED_70[2];
14504 __IO uint16_t PLLCTRL4_P2; /**< PState dependent PLL Control Register 4, offset: 0x400198 */
14505 uint8_t RESERVED_71[90];
14506 __IO uint16_t DFIFREQRATIO_P2; /**< DFI Frequency Ratio, offset: 0x4001F4 */
14507 uint8_t RESERVED_72[2096666];
14508 __IO uint16_t CALUCLKINFO_P3; /**< Impedance Calibration Clock Ratio, offset: 0x600010 */
14509 uint8_t RESERVED_73[4];
14510 __IO uint16_t SEQ0BDLY0_P3; /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x600016 */
14511 __IO uint16_t SEQ0BDLY1_P3; /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x600018 */
14512 __IO uint16_t SEQ0BDLY2_P3; /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x60001A */
14513 __IO uint16_t SEQ0BDLY3_P3; /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x60001C */
14514 uint8_t RESERVED_74[2];
14515 __IO uint16_t PPTTRAINSETUP_P3; /**< Setup Intervals for DFI PHY Master operations, offset: 0x600020 */
14516 uint8_t RESERVED_75[16];
14517 __IO uint16_t TRISTATEMODECA_P3; /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x600032 */
14518 uint8_t RESERVED_76[12];
14519 __IO uint16_t HWTMRL_P3; /**< HWT MaxReadLatency., offset: 0x600040 */
14520 uint8_t RESERVED_77[6];
14521 __IO uint16_t DQSPREAMBLECONTROL_P3; /**< Control the PHY logic related to the read and write DQS preamble, offset: 0x600048 */
14522 uint8_t RESERVED_78[16];
14523 __IO uint16_t DMIPINPRESENT_P3; /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x60005A */
14524 __IO uint16_t ARDPTRINITVAL_P3; /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x60005C */
14525 uint8_t RESERVED_79[78];
14526 __IO uint16_t PROCODTTIMECTL_P3; /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0x6000AC */
14527 uint8_t RESERVED_80[74];
14528 __IO uint16_t DLLGAINCTL_P3; /**< DLL gain control, offset: 0x6000F8 */
14529 uint8_t RESERVED_81[102];
14530 __IO uint16_t DFIRDDATACSDESTMAP_P3; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x600160 */
14531 uint8_t RESERVED_82[2];
14532 __IO uint16_t VREFINGLOBAL_P3; /**< PHY Global Vref Controls, offset: 0x600164 */
14533 uint8_t RESERVED_83[2];
14534 __IO uint16_t DFIWRDATACSDESTMAP_P3; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x600168 */
14535 uint8_t RESERVED_84[32];
14536 __IO uint16_t PLLCTRL2_P3; /**< PState dependent PLL Control Register 2, offset: 0x60018A */
14537 uint8_t RESERVED_85[2];
14538 __IO uint16_t PLLCTRL1_P3; /**< PState dependent PLL Control Register 1, offset: 0x60018E */
14539 uint8_t RESERVED_86[4];
14540 __IO uint16_t PLLTESTMODE_P3; /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x600194 */
14541 uint8_t RESERVED_87[2];
14542 __IO uint16_t PLLCTRL4_P3; /**< PState dependent PLL Control Register 4, offset: 0x600198 */
14543 uint8_t RESERVED_88[90];
14544 __IO uint16_t DFIFREQRATIO_P3; /**< DFI Frequency Ratio, offset: 0x6001F4 */
14545} DWC_DDRPHYA_MASTER_Type;
14546
14547/* ----------------------------------------------------------------------------
14548 -- DWC_DDRPHYA_MASTER Register Masks
14549 ---------------------------------------------------------------------------- */
14550
14551/*!
14552 * @addtogroup DWC_DDRPHYA_MASTER_Register_Masks DWC_DDRPHYA_MASTER Register Masks
14553 * @{
14554 */
14555
14556/*! @name RXFIFOINIT - Rx FIFO pointer initialization control */
14557/*! @{ */
14558#define DWC_DDRPHYA_MASTER_RXFIFOINIT_RxFifoInitPtr_MASK (0x1U)
14559#define DWC_DDRPHYA_MASTER_RXFIFOINIT_RxFifoInitPtr_SHIFT (0U)
14560#define DWC_DDRPHYA_MASTER_RXFIFOINIT_RxFifoInitPtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_RXFIFOINIT_RxFifoInitPtr_SHIFT)) & DWC_DDRPHYA_MASTER_RXFIFOINIT_RxFifoInitPtr_MASK)
14561#define DWC_DDRPHYA_MASTER_RXFIFOINIT_InhibitRxFifoRd_MASK (0x2U)
14562#define DWC_DDRPHYA_MASTER_RXFIFOINIT_InhibitRxFifoRd_SHIFT (1U)
14563#define DWC_DDRPHYA_MASTER_RXFIFOINIT_InhibitRxFifoRd(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_RXFIFOINIT_InhibitRxFifoRd_SHIFT)) & DWC_DDRPHYA_MASTER_RXFIFOINIT_InhibitRxFifoRd_MASK)
14564/*! @} */
14565
14566/*! @name FORCECLKDISABLE - Clock gating control */
14567/*! @{ */
14568#define DWC_DDRPHYA_MASTER_FORCECLKDISABLE_ForceClkDisable_MASK (0xFU)
14569#define DWC_DDRPHYA_MASTER_FORCECLKDISABLE_ForceClkDisable_SHIFT (0U)
14570#define DWC_DDRPHYA_MASTER_FORCECLKDISABLE_ForceClkDisable(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_FORCECLKDISABLE_ForceClkDisable_SHIFT)) & DWC_DDRPHYA_MASTER_FORCECLKDISABLE_ForceClkDisable_MASK)
14571/*! @} */
14572
14573/*! @name FORCEINTERNALUPDATE - This Register used by Training Firmware to force an internal PHY Update Event. */
14574/*! @{ */
14575#define DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_ForceInternalUpdate_MASK (0x1U)
14576#define DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_ForceInternalUpdate_SHIFT (0U)
14577#define DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_ForceInternalUpdate(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_ForceInternalUpdate_SHIFT)) & DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_ForceInternalUpdate_MASK)
14578/*! @} */
14579
14580/*! @name PHYCONFIG - Read Only displays PHY Configuration. */
14581/*! @{ */
14582#define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigAnibs_MASK (0xFU)
14583#define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigAnibs_SHIFT (0U)
14584#define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigAnibs(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigAnibs_SHIFT)) & DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigAnibs_MASK)
14585#define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDbytes_MASK (0xF0U)
14586#define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDbytes_SHIFT (4U)
14587#define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDbytes(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDbytes_SHIFT)) & DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDbytes_MASK)
14588#define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDfi_MASK (0x300U)
14589#define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDfi_SHIFT (8U)
14590#define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDfi_SHIFT)) & DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDfi_MASK)
14591/*! @} */
14592
14593/*! @name PGCR - PHY General Configuration Register(PGCR). */
14594/*! @{ */
14595#define DWC_DDRPHYA_MASTER_PGCR_RxClkRiseFallMode_MASK (0x1U)
14596#define DWC_DDRPHYA_MASTER_PGCR_RxClkRiseFallMode_SHIFT (0U)
14597#define DWC_DDRPHYA_MASTER_PGCR_RxClkRiseFallMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PGCR_RxClkRiseFallMode_SHIFT)) & DWC_DDRPHYA_MASTER_PGCR_RxClkRiseFallMode_MASK)
14598/*! @} */
14599
14600/*! @name TESTBUMPCNTRL1 - Test Bump Control1 */
14601/*! @{ */
14602#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestMajorMode_MASK (0x7U)
14603#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestMajorMode_SHIFT (0U)
14604#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestMajorMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestMajorMode_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestMajorMode_MASK)
14605#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestBiasBypassEn_MASK (0x8U)
14606#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestBiasBypassEn_SHIFT (3U)
14607#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestBiasBypassEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestBiasBypassEn_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestBiasBypassEn_MASK)
14608#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestAnalogOutCtrl_MASK (0xF0U)
14609#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestAnalogOutCtrl_SHIFT (4U)
14610#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestAnalogOutCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestAnalogOutCtrl_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestAnalogOutCtrl_MASK)
14611#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestGainCurrAdj_MASK (0x1F00U)
14612#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestGainCurrAdj_SHIFT (8U)
14613#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestGainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestGainCurrAdj_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestGainCurrAdj_MASK)
14614#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestSelExternalVref_MASK (0x2000U)
14615#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestSelExternalVref_SHIFT (13U)
14616#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestSelExternalVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestSelExternalVref_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestSelExternalVref_MASK)
14617#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestExtVrefRange_MASK (0x4000U)
14618#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestExtVrefRange_SHIFT (14U)
14619#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestExtVrefRange_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestExtVrefRange_MASK)
14620#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestPowerGateEn_MASK (0x8000U)
14621#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestPowerGateEn_SHIFT (15U)
14622#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestPowerGateEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestPowerGateEn_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestPowerGateEn_MASK)
14623/*! @} */
14624
14625/*! @name CALUCLKINFO_P0 - Impedance Calibration Clock Ratio */
14626/*! @{ */
14627#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CalUClkTicksPer1uS_MASK (0x3FFU)
14628#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CalUClkTicksPer1uS_SHIFT (0U)
14629#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CalUClkTicksPer1uS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CalUClkTicksPer1uS_SHIFT)) & DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CalUClkTicksPer1uS_MASK)
14630/*! @} */
14631
14632/*! @name TESTBUMPCNTRL - Test Bump Control */
14633/*! @{ */
14634#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpEn_MASK (0x3U)
14635#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpEn_SHIFT (0U)
14636#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpEn_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpEn_MASK)
14637#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpToggle_MASK (0x4U)
14638#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpToggle_SHIFT (2U)
14639#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpToggle(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpToggle_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpToggle_MASK)
14640#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpDataSel_MASK (0x1F8U)
14641#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpDataSel_SHIFT (3U)
14642#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpDataSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpDataSel_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpDataSel_MASK)
14643#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_ForceMtestOnAlert_MASK (0x200U)
14644#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_ForceMtestOnAlert_SHIFT (9U)
14645#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_ForceMtestOnAlert(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_ForceMtestOnAlert_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_ForceMtestOnAlert_MASK)
14646/*! @} */
14647
14648/*! @name SEQ0BDLY0_P0 - PHY Initialization Engine (PIE) Delay Register 0 */
14649/*! @{ */
14650#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_Seq0BDLY0_p0_MASK (0xFFFFU)
14651#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_Seq0BDLY0_p0_SHIFT (0U)
14652#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_Seq0BDLY0_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_Seq0BDLY0_p0_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_Seq0BDLY0_p0_MASK)
14653/*! @} */
14654
14655/*! @name SEQ0BDLY1_P0 - PHY Initialization Engine (PIE) Delay Register 1 */
14656/*! @{ */
14657#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_Seq0BDLY1_p0_MASK (0xFFFFU)
14658#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_Seq0BDLY1_p0_SHIFT (0U)
14659#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_Seq0BDLY1_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_Seq0BDLY1_p0_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_Seq0BDLY1_p0_MASK)
14660/*! @} */
14661
14662/*! @name SEQ0BDLY2_P0 - PHY Initialization Engine (PIE) Delay Register 2 */
14663/*! @{ */
14664#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_Seq0BDLY2_p0_MASK (0xFFFFU)
14665#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_Seq0BDLY2_p0_SHIFT (0U)
14666#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_Seq0BDLY2_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_Seq0BDLY2_p0_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_Seq0BDLY2_p0_MASK)
14667/*! @} */
14668
14669/*! @name SEQ0BDLY3_P0 - PHY Initialization Engine (PIE) Delay Register 3 */
14670/*! @{ */
14671#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_Seq0BDLY3_p0_MASK (0xFFFFU)
14672#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_Seq0BDLY3_p0_SHIFT (0U)
14673#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_Seq0BDLY3_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_Seq0BDLY3_p0_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_Seq0BDLY3_p0_MASK)
14674/*! @} */
14675
14676/*! @name PHYALERTSTATUS - PHY Alert status bit */
14677/*! @{ */
14678#define DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PhyAlert_MASK (0x1U)
14679#define DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PhyAlert_SHIFT (0U)
14680#define DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PhyAlert(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PhyAlert_SHIFT)) & DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PhyAlert_MASK)
14681/*! @} */
14682
14683/*! @name PPTTRAINSETUP_P0 - Setup Intervals for DFI PHY Master operations */
14684/*! @{ */
14685#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrTrainInterval_MASK (0xFU)
14686#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrTrainInterval_SHIFT (0U)
14687#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrTrainInterval(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrTrainInterval_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrTrainInterval_MASK)
14688#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrMaxReqToAck_MASK (0x70U)
14689#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrMaxReqToAck_SHIFT (4U)
14690#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrMaxReqToAck(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrMaxReqToAck_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrMaxReqToAck_MASK)
14691/*! @} */
14692
14693/*! @name ATESTMODE - ATestMode control */
14694/*! @{ */
14695#define DWC_DDRPHYA_MASTER_ATESTMODE_ATestPrbsEn_MASK (0x1U)
14696#define DWC_DDRPHYA_MASTER_ATESTMODE_ATestPrbsEn_SHIFT (0U)
14697#define DWC_DDRPHYA_MASTER_ATESTMODE_ATestPrbsEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ATESTMODE_ATestPrbsEn_SHIFT)) & DWC_DDRPHYA_MASTER_ATESTMODE_ATestPrbsEn_MASK)
14698#define DWC_DDRPHYA_MASTER_ATESTMODE_ATestClkEn_MASK (0x2U)
14699#define DWC_DDRPHYA_MASTER_ATESTMODE_ATestClkEn_SHIFT (1U)
14700#define DWC_DDRPHYA_MASTER_ATESTMODE_ATestClkEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ATESTMODE_ATestClkEn_SHIFT)) & DWC_DDRPHYA_MASTER_ATESTMODE_ATestClkEn_MASK)
14701#define DWC_DDRPHYA_MASTER_ATESTMODE_ATestModeSel_MASK (0x1CU)
14702#define DWC_DDRPHYA_MASTER_ATESTMODE_ATestModeSel_SHIFT (2U)
14703#define DWC_DDRPHYA_MASTER_ATESTMODE_ATestModeSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ATESTMODE_ATestModeSel_SHIFT)) & DWC_DDRPHYA_MASTER_ATESTMODE_ATestModeSel_MASK)
14704/*! @} */
14705
14706/*! @name TXCALBINP - TX P Impedance Calibration observation */
14707/*! @{ */
14708#define DWC_DDRPHYA_MASTER_TXCALBINP_TxCalBinP_MASK (0x1FU)
14709#define DWC_DDRPHYA_MASTER_TXCALBINP_TxCalBinP_SHIFT (0U)
14710#define DWC_DDRPHYA_MASTER_TXCALBINP_TxCalBinP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALBINP_TxCalBinP_SHIFT)) & DWC_DDRPHYA_MASTER_TXCALBINP_TxCalBinP_MASK)
14711/*! @} */
14712
14713/*! @name TXCALBINN - TX N Impedance Calibration observation */
14714/*! @{ */
14715#define DWC_DDRPHYA_MASTER_TXCALBINN_TxCalBinN_MASK (0x1FU)
14716#define DWC_DDRPHYA_MASTER_TXCALBINN_TxCalBinN_SHIFT (0U)
14717#define DWC_DDRPHYA_MASTER_TXCALBINN_TxCalBinN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALBINN_TxCalBinN_SHIFT)) & DWC_DDRPHYA_MASTER_TXCALBINN_TxCalBinN_MASK)
14718/*! @} */
14719
14720/*! @name TXCALPOVR - TX P Impedance Calibration override */
14721/*! @{ */
14722#define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrVal_MASK (0x1FU)
14723#define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrVal_SHIFT (0U)
14724#define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrVal_SHIFT)) & DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrVal_MASK)
14725#define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrEn_MASK (0x20U)
14726#define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrEn_SHIFT (5U)
14727#define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrEn_SHIFT)) & DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrEn_MASK)
14728/*! @} */
14729
14730/*! @name TXCALNOVR - TX N Impedance Calibration override */
14731/*! @{ */
14732#define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrVal_MASK (0x1FU)
14733#define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrVal_SHIFT (0U)
14734#define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrVal_SHIFT)) & DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrVal_MASK)
14735#define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrEn_MASK (0x20U)
14736#define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrEn_SHIFT (5U)
14737#define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrEn_SHIFT)) & DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrEn_MASK)
14738/*! @} */
14739
14740/*! @name DFIMODE - Enables for update and low-power interfaces for DFI0 and DFI1 */
14741/*! @{ */
14742#define DWC_DDRPHYA_MASTER_DFIMODE_Dfi0Enable_MASK (0x1U)
14743#define DWC_DDRPHYA_MASTER_DFIMODE_Dfi0Enable_SHIFT (0U)
14744#define DWC_DDRPHYA_MASTER_DFIMODE_Dfi0Enable(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIMODE_Dfi0Enable_SHIFT)) & DWC_DDRPHYA_MASTER_DFIMODE_Dfi0Enable_MASK)
14745#define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Enable_MASK (0x2U)
14746#define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Enable_SHIFT (1U)
14747#define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Enable(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Enable_SHIFT)) & DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Enable_MASK)
14748#define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Override_MASK (0x4U)
14749#define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Override_SHIFT (2U)
14750#define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Override(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Override_SHIFT)) & DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Override_MASK)
14751/*! @} */
14752
14753/*! @name TRISTATEMODECA_P0 - Mode select register for MEMCLK/Address/Command Tristates */
14754/*! @{ */
14755#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DisDynAdrTri_MASK (0x1U)
14756#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DisDynAdrTri_SHIFT (0U)
14757#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DisDynAdrTri(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DisDynAdrTri_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DisDynAdrTri_MASK)
14758#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMode_MASK (0x2U)
14759#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMode_SHIFT (1U)
14760#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMode_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMode_MASK)
14761#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CkDisVal_MASK (0xCU)
14762#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CkDisVal_SHIFT (2U)
14763#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CkDisVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CkDisVal_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CkDisVal_MASK)
14764/*! @} */
14765
14766/*! @name MTESTMUXSEL - Digital Observation Pin control */
14767/*! @{ */
14768#define DWC_DDRPHYA_MASTER_MTESTMUXSEL_MtestMuxSel_MASK (0x3FU)
14769#define DWC_DDRPHYA_MASTER_MTESTMUXSEL_MtestMuxSel_SHIFT (0U)
14770#define DWC_DDRPHYA_MASTER_MTESTMUXSEL_MtestMuxSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MTESTMUXSEL_MtestMuxSel_SHIFT)) & DWC_DDRPHYA_MASTER_MTESTMUXSEL_MtestMuxSel_MASK)
14771/*! @} */
14772
14773/*! @name MTESTPGMINFO - Digital Observation Pin program info for debug */
14774/*! @{ */
14775#define DWC_DDRPHYA_MASTER_MTESTPGMINFO_MtestPgmInfo_MASK (0x1U)
14776#define DWC_DDRPHYA_MASTER_MTESTPGMINFO_MtestPgmInfo_SHIFT (0U)
14777#define DWC_DDRPHYA_MASTER_MTESTPGMINFO_MtestPgmInfo(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MTESTPGMINFO_MtestPgmInfo_SHIFT)) & DWC_DDRPHYA_MASTER_MTESTPGMINFO_MtestPgmInfo_MASK)
14778/*! @} */
14779
14780/*! @name DYNPWRDNUP - Dynaimc Power Up/Down control */
14781/*! @{ */
14782#define DWC_DDRPHYA_MASTER_DYNPWRDNUP_DynPowerDown_MASK (0x1U)
14783#define DWC_DDRPHYA_MASTER_DYNPWRDNUP_DynPowerDown_SHIFT (0U)
14784#define DWC_DDRPHYA_MASTER_DYNPWRDNUP_DynPowerDown(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DYNPWRDNUP_DynPowerDown_SHIFT)) & DWC_DDRPHYA_MASTER_DYNPWRDNUP_DynPowerDown_MASK)
14785/*! @} */
14786
14787/*! @name PHYTID - PHY Technology ID Register */
14788/*! @{ */
14789#define DWC_DDRPHYA_MASTER_PHYTID_PhyTID_MASK (0xFFFFU)
14790#define DWC_DDRPHYA_MASTER_PHYTID_PhyTID_SHIFT (0U)
14791#define DWC_DDRPHYA_MASTER_PHYTID_PhyTID(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYTID_PhyTID_SHIFT)) & DWC_DDRPHYA_MASTER_PHYTID_PhyTID_MASK)
14792/*! @} */
14793
14794/*! @name HWTMRL_P0 - HWT MaxReadLatency. */
14795/*! @{ */
14796#define DWC_DDRPHYA_MASTER_HWTMRL_P0_HwtMRL_p0_MASK (0x1FU)
14797#define DWC_DDRPHYA_MASTER_HWTMRL_P0_HwtMRL_p0_SHIFT (0U)
14798#define DWC_DDRPHYA_MASTER_HWTMRL_P0_HwtMRL_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P0_HwtMRL_p0_SHIFT)) & DWC_DDRPHYA_MASTER_HWTMRL_P0_HwtMRL_p0_MASK)
14799/*! @} */
14800
14801/*! @name DFIPHYUPD - DFI PhyUpdate Request time counter (in MEMCLKs) */
14802/*! @{ */
14803#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_MASK (0xFU)
14804#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_SHIFT (0U)
14805#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_SHIFT)) & DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_MASK)
14806#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_MASK (0x70U)
14807#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_SHIFT (4U)
14808#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_SHIFT)) & DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_MASK)
14809#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_MASK (0x80U)
14810#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_SHIFT (7U)
14811#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_SHIFT)) & DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_MASK)
14812#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_MASK (0xF00U)
14813#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_SHIFT (8U)
14814#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_SHIFT)) & DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_MASK)
14815#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_MASK (0xF000U)
14816#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_SHIFT (12U)
14817#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_SHIFT)) & DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_MASK)
14818/*! @} */
14819
14820/*! @name PDAMRSWRITEMODE - Controls the write DQ generation for Per-Dram-Addressing of MRS */
14821/*! @{ */
14822#define DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PdaMrsWriteMode_MASK (0x1U)
14823#define DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PdaMrsWriteMode_SHIFT (0U)
14824#define DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PdaMrsWriteMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PdaMrsWriteMode_SHIFT)) & DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PdaMrsWriteMode_MASK)
14825/*! @} */
14826
14827/*! @name DFIGEARDOWNCTL - Controls whether dfi_geardown_en will cause CS and CKE timing to change. */
14828/*! @{ */
14829#define DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_MASK (0x3U)
14830#define DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_SHIFT (0U)
14831#define DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_SHIFT)) & DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_MASK)
14832/*! @} */
14833
14834/*! @name DQSPREAMBLECONTROL_P0 - Control the PHY logic related to the read and write DQS preamble */
14835/*! @{ */
14836#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckRxDqsPre_MASK (0x1U)
14837#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckRxDqsPre_SHIFT (0U)
14838#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckRxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckRxDqsPre_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckRxDqsPre_MASK)
14839#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckTxDqsPre_MASK (0x2U)
14840#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckTxDqsPre_SHIFT (1U)
14841#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckTxDqsPre_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckTxDqsPre_MASK)
14842#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_PositionDfeInit_MASK (0x1CU)
14843#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_PositionDfeInit_SHIFT (2U)
14844#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_PositionDfeInit(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_PositionDfeInit_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_PositionDfeInit_MASK)
14845#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TglTwoTckTxDqsPre_MASK (0x20U)
14846#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TglTwoTckTxDqsPre_SHIFT (5U)
14847#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TglTwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TglTwoTckTxDqsPre_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TglTwoTckTxDqsPre_MASK)
14848#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4PostambleExt_MASK (0x40U)
14849#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4PostambleExt_SHIFT (6U)
14850#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4PostambleExt(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4PostambleExt_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4PostambleExt_MASK)
14851#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4SttcPreBridgeRxEn_MASK (0x80U)
14852#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4SttcPreBridgeRxEn_SHIFT (7U)
14853#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4SttcPreBridgeRxEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4SttcPreBridgeRxEn_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4SttcPreBridgeRxEn_MASK)
14854#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_MASK (0x100U)
14855#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_SHIFT (8U)
14856#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_MASK)
14857/*! @} */
14858
14859/*! @name MASTERX4CONFIG - DBYTE module controls to select X4 Dram device mode */
14860/*! @{ */
14861#define DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_MASK (0xFU)
14862#define DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_SHIFT (0U)
14863#define DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_SHIFT)) & DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_MASK)
14864/*! @} */
14865
14866/*! @name WRLEVBITS - Write level feedback DQ observability select. */
14867/*! @{ */
14868#define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSL_MASK (0xFU)
14869#define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSL_SHIFT (0U)
14870#define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSL_SHIFT)) & DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSL_MASK)
14871#define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSU_MASK (0xF0U)
14872#define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSU_SHIFT (4U)
14873#define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSU(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSU_SHIFT)) & DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSU_MASK)
14874/*! @} */
14875
14876/*! @name ENABLECSMULTICAST - In DDR4 Mode , this controls whether CS_N[3:2] should be multicast on CID[1:0] */
14877/*! @{ */
14878#define DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_EnableCsMulticast_MASK (0x1U)
14879#define DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_EnableCsMulticast_SHIFT (0U)
14880#define DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_EnableCsMulticast(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_EnableCsMulticast_SHIFT)) & DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_EnableCsMulticast_MASK)
14881/*! @} */
14882
14883/*! @name HWTLPCSMULTICAST - Drives cs_n[0] onto cs_n[1] during training */
14884/*! @{ */
14885#define DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HwtLpCsMultiCast_MASK (0x1U)
14886#define DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HwtLpCsMultiCast_SHIFT (0U)
14887#define DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HwtLpCsMultiCast(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HwtLpCsMultiCast_SHIFT)) & DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HwtLpCsMultiCast_MASK)
14888/*! @} */
14889
14890/*! @name ACX4ANIBDIS - Disable for unused ACX Nibbles */
14891/*! @{ */
14892#define DWC_DDRPHYA_MASTER_ACX4ANIBDIS_Acx4AnibDis_MASK (0xFFFU)
14893#define DWC_DDRPHYA_MASTER_ACX4ANIBDIS_Acx4AnibDis_SHIFT (0U)
14894#define DWC_DDRPHYA_MASTER_ACX4ANIBDIS_Acx4AnibDis(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACX4ANIBDIS_Acx4AnibDis_SHIFT)) & DWC_DDRPHYA_MASTER_ACX4ANIBDIS_Acx4AnibDis_MASK)
14895/*! @} */
14896
14897/*! @name DMIPINPRESENT_P0 - This Register is used to enable the Read-DBI function in each DBYTE */
14898/*! @{ */
14899#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RdDbiEnabled_MASK (0x1U)
14900#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RdDbiEnabled_SHIFT (0U)
14901#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RdDbiEnabled(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RdDbiEnabled_SHIFT)) & DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RdDbiEnabled_MASK)
14902/*! @} */
14903
14904/*! @name ARDPTRINITVAL_P0 - Address/Command FIFO ReadPointer Initial Value */
14905/*! @{ */
14906#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARdPtrInitVal_p0_MASK (0xFU)
14907#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARdPtrInitVal_p0_SHIFT (0U)
14908#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARdPtrInitVal_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARdPtrInitVal_p0_SHIFT)) & DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARdPtrInitVal_p0_MASK)
14909/*! @} */
14910
14911/*! @name DBYTEDLLMODECNTRL - DLL Mode control CSR for DBYTEs */
14912/*! @{ */
14913#define DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DllRxPreambleMode_MASK (0x2U)
14914#define DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DllRxPreambleMode_SHIFT (1U)
14915#define DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DllRxPreambleMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DllRxPreambleMode_SHIFT)) & DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DllRxPreambleMode_MASK)
14916/*! @} */
14917
14918/*! @name CALOFFSETS - Impedance Calibration offsets control */
14919/*! @{ */
14920#define DWC_DDRPHYA_MASTER_CALOFFSETS_CalCmpr5Offset_MASK (0x3FU)
14921#define DWC_DDRPHYA_MASTER_CALOFFSETS_CalCmpr5Offset_SHIFT (0U)
14922#define DWC_DDRPHYA_MASTER_CALOFFSETS_CalCmpr5Offset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALOFFSETS_CalCmpr5Offset_SHIFT)) & DWC_DDRPHYA_MASTER_CALOFFSETS_CalCmpr5Offset_MASK)
14923#define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPdThOffset_MASK (0x3C0U)
14924#define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPdThOffset_SHIFT (6U)
14925#define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPdThOffset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPdThOffset_SHIFT)) & DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPdThOffset_MASK)
14926#define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPuThOffset_MASK (0x3C00U)
14927#define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPuThOffset_SHIFT (10U)
14928#define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPuThOffset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPuThOffset_SHIFT)) & DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPuThOffset_MASK)
14929/*! @} */
14930
14931/*! @name SARINITVALS - Sar Init Vals */
14932/*! @{ */
14933#define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitOFFSET05_MASK (0x7U)
14934#define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitOFFSET05_SHIFT (0U)
14935#define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitOFFSET05(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SARINITVALS_SarInitOFFSET05_SHIFT)) & DWC_DDRPHYA_MASTER_SARINITVALS_SarInitOFFSET05_MASK)
14936#define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitNINT_MASK (0x38U)
14937#define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitNINT_SHIFT (3U)
14938#define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitNINT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SARINITVALS_SarInitNINT_SHIFT)) & DWC_DDRPHYA_MASTER_SARINITVALS_SarInitNINT_MASK)
14939#define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitPEXT_MASK (0x1C0U)
14940#define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitPEXT_SHIFT (6U)
14941#define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitPEXT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SARINITVALS_SarInitPEXT_SHIFT)) & DWC_DDRPHYA_MASTER_SARINITVALS_SarInitPEXT_MASK)
14942/*! @} */
14943
14944/*! @name CALPEXTOVR - Impedance Calibration PExt Override control */
14945/*! @{ */
14946#define DWC_DDRPHYA_MASTER_CALPEXTOVR_CalPExtOvr_MASK (0x1FU)
14947#define DWC_DDRPHYA_MASTER_CALPEXTOVR_CalPExtOvr_SHIFT (0U)
14948#define DWC_DDRPHYA_MASTER_CALPEXTOVR_CalPExtOvr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALPEXTOVR_CalPExtOvr_SHIFT)) & DWC_DDRPHYA_MASTER_CALPEXTOVR_CalPExtOvr_MASK)
14949/*! @} */
14950
14951/*! @name CALCMPR5OVR - Impedance Calibration Cmpr 50 control */
14952/*! @{ */
14953#define DWC_DDRPHYA_MASTER_CALCMPR5OVR_CalCmpr5Ovr_MASK (0xFFU)
14954#define DWC_DDRPHYA_MASTER_CALCMPR5OVR_CalCmpr5Ovr_SHIFT (0U)
14955#define DWC_DDRPHYA_MASTER_CALCMPR5OVR_CalCmpr5Ovr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPR5OVR_CalCmpr5Ovr_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPR5OVR_CalCmpr5Ovr_MASK)
14956/*! @} */
14957
14958/*! @name CALNINTOVR - Impedance Calibration NInt Override control */
14959/*! @{ */
14960#define DWC_DDRPHYA_MASTER_CALNINTOVR_CalNIntOvr_MASK (0x1FU)
14961#define DWC_DDRPHYA_MASTER_CALNINTOVR_CalNIntOvr_SHIFT (0U)
14962#define DWC_DDRPHYA_MASTER_CALNINTOVR_CalNIntOvr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALNINTOVR_CalNIntOvr_SHIFT)) & DWC_DDRPHYA_MASTER_CALNINTOVR_CalNIntOvr_MASK)
14963/*! @} */
14964
14965/*! @name CALDRVSTR0 - Impedance Calibration driver strength control */
14966/*! @{ */
14967#define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPd50_MASK (0xFU)
14968#define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPd50_SHIFT (0U)
14969#define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPd50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPd50_SHIFT)) & DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPd50_MASK)
14970#define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPu50_MASK (0xF0U)
14971#define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPu50_SHIFT (4U)
14972#define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPu50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPu50_SHIFT)) & DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPu50_MASK)
14973/*! @} */
14974
14975/*! @name PROCODTTIMECTL_P0 - READ DATA On-Die Termination Timing Control (by PHY) */
14976/*! @{ */
14977#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtTailWidth_MASK (0x3U)
14978#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtTailWidth_SHIFT (0U)
14979#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtTailWidth(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtTailWidth_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtTailWidth_MASK)
14980#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtStartDelay_MASK (0xCU)
14981#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtStartDelay_SHIFT (2U)
14982#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtStartDelay(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtStartDelay_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtStartDelay_MASK)
14983/*! @} */
14984
14985/*! @name MEMALERTCONTROL - This Register is used to configure the MemAlert Receiver */
14986/*! @{ */
14987#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefLevel_MASK (0x7FU)
14988#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefLevel_SHIFT (0U)
14989#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefLevel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefLevel_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefLevel_MASK)
14990#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefExtEn_MASK (0x80U)
14991#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefExtEn_SHIFT (7U)
14992#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefExtEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefExtEn_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefExtEn_MASK)
14993#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuStren_MASK (0xF00U)
14994#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuStren_SHIFT (8U)
14995#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuStren(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuStren_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuStren_MASK)
14996#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuEn_MASK (0x1000U)
14997#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuEn_SHIFT (12U)
14998#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuEn_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuEn_MASK)
14999#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRxEn_MASK (0x2000U)
15000#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRxEn_SHIFT (13U)
15001#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRxEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRxEn_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRxEn_MASK)
15002#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDisableVal_MASK (0x4000U)
15003#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDisableVal_SHIFT (14U)
15004#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDisableVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDisableVal_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDisableVal_MASK)
15005#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTForceError_MASK (0x8000U)
15006#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTForceError_SHIFT (15U)
15007#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTForceError(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTForceError_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTForceError_MASK)
15008/*! @} */
15009
15010/*! @name MEMALERTCONTROL2 - This Register is used to configure the MemAlert Receiver */
15011/*! @{ */
15012#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSyncBypass_MASK (0x1U)
15013#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSyncBypass_SHIFT (0U)
15014#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSyncBypass(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSyncBypass_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSyncBypass_MASK)
15015/*! @} */
15016
15017/*! @name MEMRESETL - Protection and control of BP_MemReset_L */
15018/*! @{ */
15019#define DWC_DDRPHYA_MASTER_MEMRESETL_MemResetLValue_MASK (0x1U)
15020#define DWC_DDRPHYA_MASTER_MEMRESETL_MemResetLValue_SHIFT (0U)
15021#define DWC_DDRPHYA_MASTER_MEMRESETL_MemResetLValue(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMRESETL_MemResetLValue_SHIFT)) & DWC_DDRPHYA_MASTER_MEMRESETL_MemResetLValue_MASK)
15022#define DWC_DDRPHYA_MASTER_MEMRESETL_ProtectMemReset_MASK (0x2U)
15023#define DWC_DDRPHYA_MASTER_MEMRESETL_ProtectMemReset_SHIFT (1U)
15024#define DWC_DDRPHYA_MASTER_MEMRESETL_ProtectMemReset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMRESETL_ProtectMemReset_SHIFT)) & DWC_DDRPHYA_MASTER_MEMRESETL_ProtectMemReset_MASK)
15025/*! @} */
15026
15027/*! @name DRIVECSLOWONTOHIGH - Drive CS_N 3:0 onto CS_N 7:4 */
15028/*! @{ */
15029#define DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CsLowOntoHigh_MASK (0x1U)
15030#define DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CsLowOntoHigh_SHIFT (0U)
15031#define DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CsLowOntoHigh(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CsLowOntoHigh_SHIFT)) & DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CsLowOntoHigh_MASK)
15032/*! @} */
15033
15034/*! @name PUBMODE - PUBMODE - HWT Mux Select */
15035/*! @{ */
15036#define DWC_DDRPHYA_MASTER_PUBMODE_HwtMemSrc_MASK (0x1U)
15037#define DWC_DDRPHYA_MASTER_PUBMODE_HwtMemSrc_SHIFT (0U)
15038#define DWC_DDRPHYA_MASTER_PUBMODE_HwtMemSrc(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PUBMODE_HwtMemSrc_SHIFT)) & DWC_DDRPHYA_MASTER_PUBMODE_HwtMemSrc_MASK)
15039/*! @} */
15040
15041/*! @name MISCPHYSTATUS - Misc PHY status bits */
15042/*! @{ */
15043#define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DctSane_MASK (0x1U)
15044#define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DctSane_SHIFT (0U)
15045#define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DctSane(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DctSane_SHIFT)) & DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DctSane_MASK)
15046#define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMemReset_MASK (0x2U)
15047#define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMemReset_SHIFT (1U)
15048#define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMemReset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMemReset_SHIFT)) & DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMemReset_MASK)
15049/*! @} */
15050
15051/*! @name CORELOOPBACKSEL - Controls whether the loopback path bypasses the final PAD node. */
15052/*! @{ */
15053#define DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CoreLoopbackSel_MASK (0x1U)
15054#define DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CoreLoopbackSel_SHIFT (0U)
15055#define DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CoreLoopbackSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CoreLoopbackSel_SHIFT)) & DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CoreLoopbackSel_MASK)
15056/*! @} */
15057
15058/*! @name DLLTRAINPARAM - DLL Various Training Parameters */
15059/*! @{ */
15060#define DWC_DDRPHYA_MASTER_DLLTRAINPARAM_ExtendPhdTime_MASK (0x3U)
15061#define DWC_DDRPHYA_MASTER_DLLTRAINPARAM_ExtendPhdTime_SHIFT (0U)
15062#define DWC_DDRPHYA_MASTER_DLLTRAINPARAM_ExtendPhdTime(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLTRAINPARAM_ExtendPhdTime_SHIFT)) & DWC_DDRPHYA_MASTER_DLLTRAINPARAM_ExtendPhdTime_MASK)
15063/*! @} */
15064
15065/*! @name HWTLPCSENBYPASS - CSn Disable Bypass for LPDDR3/4 */
15066/*! @{ */
15067#define DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HwtLpCsEnBypass_MASK (0x1U)
15068#define DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HwtLpCsEnBypass_SHIFT (0U)
15069#define DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HwtLpCsEnBypass(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HwtLpCsEnBypass_SHIFT)) & DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HwtLpCsEnBypass_MASK)
15070/*! @} */
15071
15072/*! @name DFICAMODE - Dfi Command/Address Mode */
15073/*! @{ */
15074#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp3CAMode_MASK (0x1U)
15075#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp3CAMode_SHIFT (0U)
15076#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp3CAMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp3CAMode_SHIFT)) & DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp3CAMode_MASK)
15077#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4CAMode_MASK (0x2U)
15078#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4CAMode_SHIFT (1U)
15079#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4CAMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4CAMode_SHIFT)) & DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4CAMode_MASK)
15080#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp4CAMode_MASK (0x4U)
15081#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp4CAMode_SHIFT (2U)
15082#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp4CAMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp4CAMode_SHIFT)) & DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp4CAMode_MASK)
15083#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4AltCAMode_MASK (0x8U)
15084#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4AltCAMode_SHIFT (3U)
15085#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4AltCAMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4AltCAMode_SHIFT)) & DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4AltCAMode_MASK)
15086/*! @} */
15087
15088/*! @name DLLCONTROL - DLL Lock State machine control register */
15089/*! @{ */
15090#define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRelock_MASK (0x1U)
15091#define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRelock_SHIFT (0U)
15092#define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRelock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRelock_SHIFT)) & DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRelock_MASK)
15093#define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetSlave_MASK (0x2U)
15094#define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetSlave_SHIFT (1U)
15095#define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetSlave(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetSlave_SHIFT)) & DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetSlave_MASK)
15096#define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRSVD_MASK (0x4U)
15097#define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRSVD_SHIFT (2U)
15098#define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRSVD(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRSVD_SHIFT)) & DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRSVD_MASK)
15099/*! @} */
15100
15101/*! @name PULSEDLLUPDATEPHASE - DLL update phase control */
15102/*! @{ */
15103#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseDbyteDllUpdatePhase_MASK (0x1U)
15104#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseDbyteDllUpdatePhase_SHIFT (0U)
15105#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseDbyteDllUpdatePhase(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseDbyteDllUpdatePhase_SHIFT)) & DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseDbyteDllUpdatePhase_MASK)
15106#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACkDllUpdatePhase_MASK (0x2U)
15107#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACkDllUpdatePhase_SHIFT (1U)
15108#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACkDllUpdatePhase(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACkDllUpdatePhase_SHIFT)) & DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACkDllUpdatePhase_MASK)
15109#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACaDllUpdatePhase_MASK (0x4U)
15110#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACaDllUpdatePhase_SHIFT (2U)
15111#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACaDllUpdatePhase(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACaDllUpdatePhase_SHIFT)) & DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACaDllUpdatePhase_MASK)
15112#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UpdatePhaseDestReserved_MASK (0x38U)
15113#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UpdatePhaseDestReserved_SHIFT (3U)
15114#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UpdatePhaseDestReserved(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UpdatePhaseDestReserved_SHIFT)) & DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UpdatePhaseDestReserved_MASK)
15115#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TrainUpdatePhaseOnLongBubble_MASK (0x40U)
15116#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TrainUpdatePhaseOnLongBubble_SHIFT (6U)
15117#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TrainUpdatePhaseOnLongBubble(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TrainUpdatePhaseOnLongBubble_SHIFT)) & DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TrainUpdatePhaseOnLongBubble_MASK)
15118#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_AlwaysUpdateLcdlPhase_MASK (0x80U)
15119#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_AlwaysUpdateLcdlPhase_SHIFT (7U)
15120#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_AlwaysUpdateLcdlPhase(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_AlwaysUpdateLcdlPhase_SHIFT)) & DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_AlwaysUpdateLcdlPhase_MASK)
15121/*! @} */
15122
15123/*! @name DLLGAINCTL_P0 - DLL gain control */
15124/*! @{ */
15125#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainIV_MASK (0xFU)
15126#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainIV_SHIFT (0U)
15127#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainIV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainIV_MASK)
15128#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainTV_MASK (0xF0U)
15129#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainTV_SHIFT (4U)
15130#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainTV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainTV_MASK)
15131#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllSeedSel_MASK (0xF00U)
15132#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllSeedSel_SHIFT (8U)
15133#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllSeedSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllSeedSel_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllSeedSel_MASK)
15134/*! @} */
15135
15136/*! @name CALRATE - Impedance Calibration Control */
15137/*! @{ */
15138#define DWC_DDRPHYA_MASTER_CALRATE_CalInterval_MASK (0xFU)
15139#define DWC_DDRPHYA_MASTER_CALRATE_CalInterval_SHIFT (0U)
15140#define DWC_DDRPHYA_MASTER_CALRATE_CalInterval(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_CalInterval_SHIFT)) & DWC_DDRPHYA_MASTER_CALRATE_CalInterval_MASK)
15141#define DWC_DDRPHYA_MASTER_CALRATE_CalRun_MASK (0x10U)
15142#define DWC_DDRPHYA_MASTER_CALRATE_CalRun_SHIFT (4U)
15143#define DWC_DDRPHYA_MASTER_CALRATE_CalRun(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_CalRun_SHIFT)) & DWC_DDRPHYA_MASTER_CALRATE_CalRun_MASK)
15144#define DWC_DDRPHYA_MASTER_CALRATE_CalOnce_MASK (0x20U)
15145#define DWC_DDRPHYA_MASTER_CALRATE_CalOnce_SHIFT (5U)
15146#define DWC_DDRPHYA_MASTER_CALRATE_CalOnce(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_CalOnce_SHIFT)) & DWC_DDRPHYA_MASTER_CALRATE_CalOnce_MASK)
15147#define DWC_DDRPHYA_MASTER_CALRATE_DisableBackgroundZQUpdates_MASK (0x40U)
15148#define DWC_DDRPHYA_MASTER_CALRATE_DisableBackgroundZQUpdates_SHIFT (6U)
15149#define DWC_DDRPHYA_MASTER_CALRATE_DisableBackgroundZQUpdates(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_DisableBackgroundZQUpdates_SHIFT)) & DWC_DDRPHYA_MASTER_CALRATE_DisableBackgroundZQUpdates_MASK)
15150/*! @} */
15151
15152/*! @name CALZAP - Impedance Calibration Zap/Reset */
15153/*! @{ */
15154#define DWC_DDRPHYA_MASTER_CALZAP_CalZap_MASK (0x1U)
15155#define DWC_DDRPHYA_MASTER_CALZAP_CalZap_SHIFT (0U)
15156#define DWC_DDRPHYA_MASTER_CALZAP_CalZap(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALZAP_CalZap_SHIFT)) & DWC_DDRPHYA_MASTER_CALZAP_CalZap_MASK)
15157/*! @} */
15158
15159/*! @name PSTATE - PSTATE Selection */
15160/*! @{ */
15161#define DWC_DDRPHYA_MASTER_PSTATE_PState_MASK (0xFU)
15162#define DWC_DDRPHYA_MASTER_PSTATE_PState_SHIFT (0U)
15163#define DWC_DDRPHYA_MASTER_PSTATE_PState(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PSTATE_PState_SHIFT)) & DWC_DDRPHYA_MASTER_PSTATE_PState_MASK)
15164/*! @} */
15165
15166/*! @name PLLOUTGATECONTROL - PLL Output Control */
15167/*! @{ */
15168#define DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PclkGateEn_MASK (0x1U)
15169#define DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PclkGateEn_SHIFT (0U)
15170#define DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PclkGateEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PclkGateEn_SHIFT)) & DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PclkGateEn_MASK)
15171/*! @} */
15172
15173/*! @name PORCONTROL - PMU Power-on Reset Control (PLL/DLL Lock Done) */
15174/*! @{ */
15175#define DWC_DDRPHYA_MASTER_PORCONTROL_PllDllLockDone_MASK (0x1U)
15176#define DWC_DDRPHYA_MASTER_PORCONTROL_PllDllLockDone_SHIFT (0U)
15177#define DWC_DDRPHYA_MASTER_PORCONTROL_PllDllLockDone(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PORCONTROL_PllDllLockDone_SHIFT)) & DWC_DDRPHYA_MASTER_PORCONTROL_PllDllLockDone_MASK)
15178/*! @} */
15179
15180/*! @name CALBUSY - Impedance Calibration Busy Status */
15181/*! @{ */
15182#define DWC_DDRPHYA_MASTER_CALBUSY_CalBusy_MASK (0x1U)
15183#define DWC_DDRPHYA_MASTER_CALBUSY_CalBusy_SHIFT (0U)
15184#define DWC_DDRPHYA_MASTER_CALBUSY_CalBusy(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALBUSY_CalBusy_SHIFT)) & DWC_DDRPHYA_MASTER_CALBUSY_CalBusy_MASK)
15185/*! @} */
15186
15187/*! @name CALMISC2 - Miscellaneous impedance calibration controls. */
15188/*! @{ */
15189#define DWC_DDRPHYA_MASTER_CALMISC2_CalNumVotes_MASK (0x7U)
15190#define DWC_DDRPHYA_MASTER_CALMISC2_CalNumVotes_SHIFT (0U)
15191#define DWC_DDRPHYA_MASTER_CALMISC2_CalNumVotes(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CalNumVotes_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC2_CalNumVotes_MASK)
15192#define DWC_DDRPHYA_MASTER_CALMISC2_CalCmptrResTrim_MASK (0x1000U)
15193#define DWC_DDRPHYA_MASTER_CALMISC2_CalCmptrResTrim_SHIFT (12U)
15194#define DWC_DDRPHYA_MASTER_CALMISC2_CalCmptrResTrim(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CalCmptrResTrim_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC2_CalCmptrResTrim_MASK)
15195#define DWC_DDRPHYA_MASTER_CALMISC2_CalCancelRoundErrDis_MASK (0x2000U)
15196#define DWC_DDRPHYA_MASTER_CALMISC2_CalCancelRoundErrDis_SHIFT (13U)
15197#define DWC_DDRPHYA_MASTER_CALMISC2_CalCancelRoundErrDis(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CalCancelRoundErrDis_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC2_CalCancelRoundErrDis_MASK)
15198#define DWC_DDRPHYA_MASTER_CALMISC2_CalSlowCmpana_MASK (0x4000U)
15199#define DWC_DDRPHYA_MASTER_CALMISC2_CalSlowCmpana_SHIFT (14U)
15200#define DWC_DDRPHYA_MASTER_CALMISC2_CalSlowCmpana(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CalSlowCmpana_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC2_CalSlowCmpana_MASK)
15201/*! @} */
15202
15203/*! @name CALMISC - Controls for disabling the impedance calibration of certain targets. */
15204/*! @{ */
15205#define DWC_DDRPHYA_MASTER_CALMISC_CalCmpr5Dis_MASK (0x1U)
15206#define DWC_DDRPHYA_MASTER_CALMISC_CalCmpr5Dis_SHIFT (0U)
15207#define DWC_DDRPHYA_MASTER_CALMISC_CalCmpr5Dis(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC_CalCmpr5Dis_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC_CalCmpr5Dis_MASK)
15208#define DWC_DDRPHYA_MASTER_CALMISC_CalNIntDis_MASK (0x2U)
15209#define DWC_DDRPHYA_MASTER_CALMISC_CalNIntDis_SHIFT (1U)
15210#define DWC_DDRPHYA_MASTER_CALMISC_CalNIntDis(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC_CalNIntDis_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC_CalNIntDis_MASK)
15211#define DWC_DDRPHYA_MASTER_CALMISC_CalPExtDis_MASK (0x4U)
15212#define DWC_DDRPHYA_MASTER_CALMISC_CalPExtDis_SHIFT (2U)
15213#define DWC_DDRPHYA_MASTER_CALMISC_CalPExtDis(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC_CalPExtDis_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC_CalPExtDis_MASK)
15214/*! @} */
15215
15216/*! @name CALVREFS - */
15217/*! @{ */
15218#define DWC_DDRPHYA_MASTER_CALVREFS_CalVRefs_MASK (0x3U)
15219#define DWC_DDRPHYA_MASTER_CALVREFS_CalVRefs_SHIFT (0U)
15220#define DWC_DDRPHYA_MASTER_CALVREFS_CalVRefs(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALVREFS_CalVRefs_SHIFT)) & DWC_DDRPHYA_MASTER_CALVREFS_CalVRefs_MASK)
15221/*! @} */
15222
15223/*! @name CALCMPR5 - Impedance Calibration Cmpr control */
15224/*! @{ */
15225#define DWC_DDRPHYA_MASTER_CALCMPR5_CalCmpr5_MASK (0xFFU)
15226#define DWC_DDRPHYA_MASTER_CALCMPR5_CalCmpr5_SHIFT (0U)
15227#define DWC_DDRPHYA_MASTER_CALCMPR5_CalCmpr5(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPR5_CalCmpr5_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPR5_CalCmpr5_MASK)
15228/*! @} */
15229
15230/*! @name CALNINT - Impedance Calibration NInt control */
15231/*! @{ */
15232#define DWC_DDRPHYA_MASTER_CALNINT_CalNIntThB_MASK (0x1FU)
15233#define DWC_DDRPHYA_MASTER_CALNINT_CalNIntThB_SHIFT (0U)
15234#define DWC_DDRPHYA_MASTER_CALNINT_CalNIntThB(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALNINT_CalNIntThB_SHIFT)) & DWC_DDRPHYA_MASTER_CALNINT_CalNIntThB_MASK)
15235/*! @} */
15236
15237/*! @name CALPEXT - Impedance Calibration PExt control */
15238/*! @{ */
15239#define DWC_DDRPHYA_MASTER_CALPEXT_CalPExtThB_MASK (0x1FU)
15240#define DWC_DDRPHYA_MASTER_CALPEXT_CalPExtThB_SHIFT (0U)
15241#define DWC_DDRPHYA_MASTER_CALPEXT_CalPExtThB(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALPEXT_CalPExtThB_SHIFT)) & DWC_DDRPHYA_MASTER_CALPEXT_CalPExtThB_MASK)
15242/*! @} */
15243
15244/*! @name CALCMPINVERT - Impedance Calibration Cmp Invert control */
15245/*! @{ */
15246#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDac50_MASK (0x1U)
15247#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDac50_SHIFT (0U)
15248#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDac50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDac50_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDac50_MASK)
15249#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPd50_MASK (0x2U)
15250#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPd50_SHIFT (1U)
15251#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPd50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPd50_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPd50_MASK)
15252#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPu50_MASK (0x4U)
15253#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPu50_SHIFT (2U)
15254#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPu50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPu50_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPu50_MASK)
15255#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPd_MASK (0x8U)
15256#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPd_SHIFT (3U)
15257#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPd(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPd_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPd_MASK)
15258#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPu_MASK (0x10U)
15259#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPu_SHIFT (4U)
15260#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPu(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPu_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPu_MASK)
15261/*! @} */
15262
15263/*! @name CALCMPANACNTRL - Impedance Calibration Cmpana control */
15264/*! @{ */
15265#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainCurrAdj_MASK (0xFFU)
15266#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainCurrAdj_SHIFT (0U)
15267#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainCurrAdj_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainCurrAdj_MASK)
15268#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainResAdj_MASK (0x100U)
15269#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainResAdj_SHIFT (8U)
15270#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainResAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainResAdj_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainResAdj_MASK)
15271#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprBiasBypassEn_MASK (0x200U)
15272#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprBiasBypassEn_SHIFT (9U)
15273#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprBiasBypassEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprBiasBypassEn_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprBiasBypassEn_MASK)
15274/*! @} */
15275
15276/*! @name DFIRDDATACSDESTMAP_P0 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
15277/*! @{ */
15278#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm0_MASK (0x3U)
15279#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm0_SHIFT (0U)
15280#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm0_MASK)
15281#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm1_MASK (0xCU)
15282#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm1_SHIFT (2U)
15283#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm1_MASK)
15284#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm2_MASK (0x30U)
15285#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm2_SHIFT (4U)
15286#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm2_MASK)
15287#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm3_MASK (0xC0U)
15288#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm3_SHIFT (6U)
15289#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm3_MASK)
15290/*! @} */
15291
15292/*! @name VREFINGLOBAL_P0 - PHY Global Vref Controls */
15293/*! @{ */
15294#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInSel_MASK (0x7U)
15295#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInSel_SHIFT (0U)
15296#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInSel_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInSel_MASK)
15297#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInDAC_MASK (0x3F8U)
15298#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInDAC_SHIFT (3U)
15299#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInDAC_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInDAC_MASK)
15300#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInTrim_MASK (0x3C00U)
15301#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInTrim_SHIFT (10U)
15302#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInTrim(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInTrim_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInTrim_MASK)
15303#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInMode_MASK (0x4000U)
15304#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInMode_SHIFT (14U)
15305#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInMode_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInMode_MASK)
15306/*! @} */
15307
15308/*! @name DFIWRDATACSDESTMAP_P0 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
15309/*! @{ */
15310#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm0_MASK (0x3U)
15311#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm0_SHIFT (0U)
15312#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm0_MASK)
15313#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm1_MASK (0xCU)
15314#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm1_SHIFT (2U)
15315#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm1_MASK)
15316#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm2_MASK (0x30U)
15317#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm2_SHIFT (4U)
15318#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm2_MASK)
15319#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm3_MASK (0xC0U)
15320#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm3_SHIFT (6U)
15321#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm3_MASK)
15322/*! @} */
15323
15324/*! @name MASUPDGOODCTR - Counts successful PHY Master Interface Updates (PPTs) */
15325/*! @{ */
15326#define DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MasUpdGoodCtr_MASK (0xFFFFU)
15327#define DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MasUpdGoodCtr_SHIFT (0U)
15328#define DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MasUpdGoodCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MasUpdGoodCtr_SHIFT)) & DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MasUpdGoodCtr_MASK)
15329/*! @} */
15330
15331/*! @name PHYUPD0GOODCTR - Counts successful PHY-initiated DFI0 Interface Updates */
15332/*! @{ */
15333#define DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PhyUpd0GoodCtr_MASK (0xFFFFU)
15334#define DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PhyUpd0GoodCtr_SHIFT (0U)
15335#define DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PhyUpd0GoodCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PhyUpd0GoodCtr_SHIFT)) & DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PhyUpd0GoodCtr_MASK)
15336/*! @} */
15337
15338/*! @name PHYUPD1GOODCTR - Counts successful PHY-initiated DFI1 Interface Updates */
15339/*! @{ */
15340#define DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PhyUpd1GoodCtr_MASK (0xFFFFU)
15341#define DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PhyUpd1GoodCtr_SHIFT (0U)
15342#define DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PhyUpd1GoodCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PhyUpd1GoodCtr_SHIFT)) & DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PhyUpd1GoodCtr_MASK)
15343/*! @} */
15344
15345/*! @name CTLUPD0GOODCTR - Counts successful Memory Controller DFI0 Interface Updates */
15346/*! @{ */
15347#define DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CtlUpd0GoodCtr_MASK (0xFFFFU)
15348#define DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CtlUpd0GoodCtr_SHIFT (0U)
15349#define DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CtlUpd0GoodCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CtlUpd0GoodCtr_SHIFT)) & DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CtlUpd0GoodCtr_MASK)
15350/*! @} */
15351
15352/*! @name CTLUPD1GOODCTR - Counts successful Memory Controller DFI1 Interface Updates */
15353/*! @{ */
15354#define DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CtlUpd1GoodCtr_MASK (0xFFFFU)
15355#define DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CtlUpd1GoodCtr_SHIFT (0U)
15356#define DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CtlUpd1GoodCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CtlUpd1GoodCtr_SHIFT)) & DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CtlUpd1GoodCtr_MASK)
15357/*! @} */
15358
15359/*! @name MASUPDFAILCTR - Counts unsuccessful PHY Master Interface Updates */
15360/*! @{ */
15361#define DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MasUpdFailCtr_MASK (0xFFFFU)
15362#define DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MasUpdFailCtr_SHIFT (0U)
15363#define DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MasUpdFailCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MasUpdFailCtr_SHIFT)) & DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MasUpdFailCtr_MASK)
15364/*! @} */
15365
15366/*! @name PHYUPD0FAILCTR - Counts unsuccessful PHY-initiated DFI0 Interface Updates */
15367/*! @{ */
15368#define DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PhyUpd0FailCtr_MASK (0xFFFFU)
15369#define DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PhyUpd0FailCtr_SHIFT (0U)
15370#define DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PhyUpd0FailCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PhyUpd0FailCtr_SHIFT)) & DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PhyUpd0FailCtr_MASK)
15371/*! @} */
15372
15373/*! @name PHYUPD1FAILCTR - Counts unsuccessful PHY-initiated DFI1 Interface Updates */
15374/*! @{ */
15375#define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PhyUpd1FailCtr_MASK (0xFFFFU)
15376#define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PhyUpd1FailCtr_SHIFT (0U)
15377#define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PhyUpd1FailCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PhyUpd1FailCtr_SHIFT)) & DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PhyUpd1FailCtr_MASK)
15378/*! @} */
15379
15380/*! @name PHYPERFCTRENABLE - Enables for Performance Counters */
15381/*! @{ */
15382#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdGoodCtl_MASK (0x1U)
15383#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdGoodCtl_SHIFT (0U)
15384#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdGoodCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdGoodCtl_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdGoodCtl_MASK)
15385#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0GoodCtl_MASK (0x2U)
15386#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0GoodCtl_SHIFT (1U)
15387#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0GoodCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0GoodCtl_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0GoodCtl_MASK)
15388#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1GoodCtl_MASK (0x4U)
15389#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1GoodCtl_SHIFT (2U)
15390#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1GoodCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1GoodCtl_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1GoodCtl_MASK)
15391#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd0GoodCtl_MASK (0x8U)
15392#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd0GoodCtl_SHIFT (3U)
15393#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd0GoodCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd0GoodCtl_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd0GoodCtl_MASK)
15394#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd1GoodCtl_MASK (0x10U)
15395#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd1GoodCtl_SHIFT (4U)
15396#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd1GoodCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd1GoodCtl_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd1GoodCtl_MASK)
15397#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdFailCtl_MASK (0x20U)
15398#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdFailCtl_SHIFT (5U)
15399#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdFailCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdFailCtl_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdFailCtl_MASK)
15400#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0FailCtl_MASK (0x40U)
15401#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0FailCtl_SHIFT (6U)
15402#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0FailCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0FailCtl_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0FailCtl_MASK)
15403#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1FailCtl_MASK (0x80U)
15404#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1FailCtl_SHIFT (7U)
15405#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1FailCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1FailCtl_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1FailCtl_MASK)
15406/*! @} */
15407
15408/*! @name PLLPWRDN - PLL Power Down */
15409/*! @{ */
15410#define DWC_DDRPHYA_MASTER_PLLPWRDN_PllPwrDn_MASK (0x1U)
15411#define DWC_DDRPHYA_MASTER_PLLPWRDN_PllPwrDn_SHIFT (0U)
15412#define DWC_DDRPHYA_MASTER_PLLPWRDN_PllPwrDn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLPWRDN_PllPwrDn_SHIFT)) & DWC_DDRPHYA_MASTER_PLLPWRDN_PllPwrDn_MASK)
15413/*! @} */
15414
15415/*! @name PLLRESET - PLL Reset */
15416/*! @{ */
15417#define DWC_DDRPHYA_MASTER_PLLRESET_PllReset_MASK (0x1U)
15418#define DWC_DDRPHYA_MASTER_PLLRESET_PllReset_SHIFT (0U)
15419#define DWC_DDRPHYA_MASTER_PLLRESET_PllReset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLRESET_PllReset_SHIFT)) & DWC_DDRPHYA_MASTER_PLLRESET_PllReset_MASK)
15420/*! @} */
15421
15422/*! @name PLLCTRL2_P0 - PState dependent PLL Control Register 2 */
15423/*! @{ */
15424#define DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PllFreqSel_MASK (0x1FU)
15425#define DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PllFreqSel_SHIFT (0U)
15426#define DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PllFreqSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PllFreqSel_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PllFreqSel_MASK)
15427/*! @} */
15428
15429/*! @name PLLCTRL0 - PLL Control Register 0 */
15430/*! @{ */
15431#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllStandby_MASK (0x1U)
15432#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllStandby_SHIFT (0U)
15433#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllStandby(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllStandby_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PllStandby_MASK)
15434#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypSel_MASK (0x2U)
15435#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypSel_SHIFT (1U)
15436#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypSel_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypSel_MASK)
15437#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllX2Mode_MASK (0x4U)
15438#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllX2Mode_SHIFT (2U)
15439#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllX2Mode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllX2Mode_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PllX2Mode_MASK)
15440#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllOutBypEn_MASK (0x8U)
15441#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllOutBypEn_SHIFT (3U)
15442#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllOutBypEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllOutBypEn_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PllOutBypEn_MASK)
15443#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllPreset_MASK (0x10U)
15444#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllPreset_SHIFT (4U)
15445#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllPreset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllPreset_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PllPreset_MASK)
15446#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypassMode_MASK (0x20U)
15447#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypassMode_SHIFT (5U)
15448#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypassMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypassMode_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypassMode_MASK)
15449#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSelDfiFreqRatio_MASK (0x40U)
15450#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSelDfiFreqRatio_SHIFT (6U)
15451#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSelDfiFreqRatio(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllSelDfiFreqRatio_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PllSelDfiFreqRatio_MASK)
15452#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusFlush_MASK (0x80U)
15453#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusFlush_SHIFT (7U)
15454#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusFlush(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusFlush_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusFlush_MASK)
15455#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusByp_MASK (0x100U)
15456#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusByp_SHIFT (8U)
15457#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusByp(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusByp_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusByp_MASK)
15458#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllReserved10x9_MASK (0x600U)
15459#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllReserved10x9_SHIFT (9U)
15460#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllReserved10x9(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllReserved10x9_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PllReserved10x9_MASK)
15461#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllGearShift_MASK (0x800U)
15462#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllGearShift_SHIFT (11U)
15463#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllGearShift(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllGearShift_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PllGearShift_MASK)
15464#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockCntSel_MASK (0x1000U)
15465#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockCntSel_SHIFT (12U)
15466#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockCntSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockCntSel_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockCntSel_MASK)
15467#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockPhSel_MASK (0x6000U)
15468#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockPhSel_SHIFT (13U)
15469#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockPhSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockPhSel_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockPhSel_MASK)
15470#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSpareCtrl0_MASK (0x8000U)
15471#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSpareCtrl0_SHIFT (15U)
15472#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSpareCtrl0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllSpareCtrl0_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PllSpareCtrl0_MASK)
15473/*! @} */
15474
15475/*! @name PLLCTRL1_P0 - PState dependent PLL Control Register 1 */
15476/*! @{ */
15477#define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpIntCtrl_MASK (0x1FU)
15478#define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpIntCtrl_SHIFT (0U)
15479#define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpIntCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpIntCtrl_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpIntCtrl_MASK)
15480#define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpPropCtrl_MASK (0x1E0U)
15481#define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpPropCtrl_SHIFT (5U)
15482#define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpPropCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpPropCtrl_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpPropCtrl_MASK)
15483/*! @} */
15484
15485/*! @name PLLTST - PLL Testing Control Register */
15486/*! @{ */
15487#define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstEn_MASK (0x1U)
15488#define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstEn_SHIFT (0U)
15489#define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstEn_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstEn_MASK)
15490#define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstSel_MASK (0x1EU)
15491#define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstSel_SHIFT (1U)
15492#define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstSel_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstSel_MASK)
15493#define DWC_DDRPHYA_MASTER_PLLTST_PllDigTstSel_MASK (0x1E0U)
15494#define DWC_DDRPHYA_MASTER_PLLTST_PllDigTstSel_SHIFT (5U)
15495#define DWC_DDRPHYA_MASTER_PLLTST_PllDigTstSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTST_PllDigTstSel_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTST_PllDigTstSel_MASK)
15496/*! @} */
15497
15498/*! @name PLLLOCKSTATUS - PLL's pll_lock pin output */
15499/*! @{ */
15500#define DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PllLockStatus_MASK (0x1U)
15501#define DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PllLockStatus_SHIFT (0U)
15502#define DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PllLockStatus(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PllLockStatus_SHIFT)) & DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PllLockStatus_MASK)
15503/*! @} */
15504
15505/*! @name PLLTESTMODE_P0 - Additional controls for PLL CP/VCO modes of operation */
15506/*! @{ */
15507#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PllTestMode_p0_MASK (0xFFFFU)
15508#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PllTestMode_p0_SHIFT (0U)
15509#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PllTestMode_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PllTestMode_p0_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PllTestMode_p0_MASK)
15510/*! @} */
15511
15512/*! @name PLLCTRL3 - PLL Control Register 3 */
15513/*! @{ */
15514#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllSpare_MASK (0xFU)
15515#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllSpare_SHIFT (0U)
15516#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllSpare(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PllSpare_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL3_PllSpare_MASK)
15517#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllMaxRange_MASK (0x1F0U)
15518#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllMaxRange_SHIFT (4U)
15519#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllMaxRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PllMaxRange_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL3_PllMaxRange_MASK)
15520#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllDacValIn_MASK (0x3E00U)
15521#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllDacValIn_SHIFT (9U)
15522#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllDacValIn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PllDacValIn_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL3_PllDacValIn_MASK)
15523#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllForceCal_MASK (0x4000U)
15524#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllForceCal_SHIFT (14U)
15525#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllForceCal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PllForceCal_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL3_PllForceCal_MASK)
15526#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllEnCal_MASK (0x8000U)
15527#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllEnCal_SHIFT (15U)
15528#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllEnCal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PllEnCal_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL3_PllEnCal_MASK)
15529/*! @} */
15530
15531/*! @name PLLCTRL4_P0 - PState dependent PLL Control Register 4 */
15532/*! @{ */
15533#define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpIntGsCtrl_MASK (0x1FU)
15534#define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpIntGsCtrl_SHIFT (0U)
15535#define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpIntGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpIntGsCtrl_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpIntGsCtrl_MASK)
15536#define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpPropGsCtrl_MASK (0x1E0U)
15537#define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpPropGsCtrl_SHIFT (5U)
15538#define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpPropGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpPropGsCtrl_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpPropGsCtrl_MASK)
15539/*! @} */
15540
15541/*! @name PLLENDOFCAL - PLL's eoc (end of calibration) output */
15542/*! @{ */
15543#define DWC_DDRPHYA_MASTER_PLLENDOFCAL_PllEndofCal_MASK (0x1U)
15544#define DWC_DDRPHYA_MASTER_PLLENDOFCAL_PllEndofCal_SHIFT (0U)
15545#define DWC_DDRPHYA_MASTER_PLLENDOFCAL_PllEndofCal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLENDOFCAL_PllEndofCal_SHIFT)) & DWC_DDRPHYA_MASTER_PLLENDOFCAL_PllEndofCal_MASK)
15546/*! @} */
15547
15548/*! @name PLLSTANDBYEFF - PLL's standby_eff (effective standby) output */
15549/*! @{ */
15550#define DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PllStandbyEff_MASK (0x1U)
15551#define DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PllStandbyEff_SHIFT (0U)
15552#define DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PllStandbyEff(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PllStandbyEff_SHIFT)) & DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PllStandbyEff_MASK)
15553/*! @} */
15554
15555/*! @name PLLDACVALOUT - PLL's Dacval_out output */
15556/*! @{ */
15557#define DWC_DDRPHYA_MASTER_PLLDACVALOUT_PllDacValOut_MASK (0x1FU)
15558#define DWC_DDRPHYA_MASTER_PLLDACVALOUT_PllDacValOut_SHIFT (0U)
15559#define DWC_DDRPHYA_MASTER_PLLDACVALOUT_PllDacValOut(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLDACVALOUT_PllDacValOut_SHIFT)) & DWC_DDRPHYA_MASTER_PLLDACVALOUT_PllDacValOut_MASK)
15560/*! @} */
15561
15562/*! @name LCDLDBGCNTL - Controls for use in observing and testing the LCDLs. */
15563/*! @{ */
15564#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvrVal_MASK (0x1FFU)
15565#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvrVal_SHIFT (0U)
15566#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvrVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvrVal_SHIFT)) & DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvrVal_MASK)
15567#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvr_MASK (0x200U)
15568#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvr_SHIFT (9U)
15569#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvr_SHIFT)) & DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvr_MASK)
15570#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineSnap_MASK (0x400U)
15571#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineSnap_SHIFT (10U)
15572#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineSnap(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineSnap_SHIFT)) & DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineSnap_MASK)
15573#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlTstEnable_MASK (0x800U)
15574#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlTstEnable_SHIFT (11U)
15575#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlTstEnable(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlTstEnable_SHIFT)) & DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlTstEnable_MASK)
15576#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlStatusSel_MASK (0xF000U)
15577#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlStatusSel_SHIFT (12U)
15578#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlStatusSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlStatusSel_SHIFT)) & DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlStatusSel_MASK)
15579/*! @} */
15580
15581/*! @name ACLCDLSTATUS - Debug status of the DBYTE LCDL */
15582/*! @{ */
15583#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlFineSnapVal_MASK (0x3FFU)
15584#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlFineSnapVal_SHIFT (0U)
15585#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlFineSnapVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlFineSnapVal_SHIFT)) & DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlFineSnapVal_MASK)
15586#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlPhdSnapVal_MASK (0x400U)
15587#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlPhdSnapVal_SHIFT (10U)
15588#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlPhdSnapVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlPhdSnapVal_SHIFT)) & DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlPhdSnapVal_MASK)
15589#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyLock_MASK (0x800U)
15590#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyLock_SHIFT (11U)
15591#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyLock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyLock_SHIFT)) & DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyLock_MASK)
15592#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyUnlock_MASK (0x1000U)
15593#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyUnlock_SHIFT (12U)
15594#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyUnlock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyUnlock_SHIFT)) & DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyUnlock_MASK)
15595#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlLiveLock_MASK (0x2000U)
15596#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlLiveLock_SHIFT (13U)
15597#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlLiveLock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlLiveLock_SHIFT)) & DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlLiveLock_MASK)
15598/*! @} */
15599
15600/*! @name CUSTPHYREV - Customer settable by the customer */
15601/*! @{ */
15602#define DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_MASK (0x3FU)
15603#define DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_SHIFT (0U)
15604#define DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_SHIFT)) & DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_MASK)
15605/*! @} */
15606
15607/*! @name PHYREV - The hardware version of this PHY, excluding the PUB */
15608/*! @{ */
15609#define DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_MASK (0xFU)
15610#define DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_SHIFT (0U)
15611#define DWC_DDRPHYA_MASTER_PHYREV_PHYMNR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_MASK)
15612#define DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_MASK (0xF0U)
15613#define DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_SHIFT (4U)
15614#define DWC_DDRPHYA_MASTER_PHYREV_PHYMDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_MASK)
15615#define DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_MASK (0xFF00U)
15616#define DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_SHIFT (8U)
15617#define DWC_DDRPHYA_MASTER_PHYREV_PHYMJR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_MASK)
15618/*! @} */
15619
15620/*! @name LP3EXITSEQ0BSTARTVECTOR - Start vector value to be used for LP3-exit or Init PIE Sequence */
15621/*! @{ */
15622#define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllEnabled_MASK (0xFU)
15623#define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllEnabled_SHIFT (0U)
15624#define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllEnabled(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllEnabled_SHIFT)) & DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllEnabled_MASK)
15625#define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllBypassed_MASK (0xF0U)
15626#define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllBypassed_SHIFT (4U)
15627#define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllBypassed(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllBypassed_SHIFT)) & DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllBypassed_MASK)
15628/*! @} */
15629
15630/*! @name DFIFREQXLAT0 - DFI Frequency Translation Register 0 */
15631/*! @{ */
15632#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal0_MASK (0xFU)
15633#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal0_SHIFT (0U)
15634#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal0_MASK)
15635#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal1_MASK (0xF0U)
15636#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal1_SHIFT (4U)
15637#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal1_MASK)
15638#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal2_MASK (0xF00U)
15639#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal2_SHIFT (8U)
15640#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal2_MASK)
15641#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal3_MASK (0xF000U)
15642#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal3_SHIFT (12U)
15643#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal3_MASK)
15644/*! @} */
15645
15646/*! @name DFIFREQXLAT1 - DFI Frequency Translation Register 1 */
15647/*! @{ */
15648#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal4_MASK (0xFU)
15649#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal4_SHIFT (0U)
15650#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal4(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal4_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal4_MASK)
15651#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal5_MASK (0xF0U)
15652#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal5_SHIFT (4U)
15653#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal5(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal5_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal5_MASK)
15654#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal6_MASK (0xF00U)
15655#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal6_SHIFT (8U)
15656#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal6(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal6_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal6_MASK)
15657#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal7_MASK (0xF000U)
15658#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal7_SHIFT (12U)
15659#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal7(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal7_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal7_MASK)
15660/*! @} */
15661
15662/*! @name DFIFREQXLAT2 - DFI Frequency Translation Register 2 */
15663/*! @{ */
15664#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal8_MASK (0xFU)
15665#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal8_SHIFT (0U)
15666#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal8(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal8_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal8_MASK)
15667#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal9_MASK (0xF0U)
15668#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal9_SHIFT (4U)
15669#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal9(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal9_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal9_MASK)
15670#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal10_MASK (0xF00U)
15671#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal10_SHIFT (8U)
15672#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal10(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal10_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal10_MASK)
15673#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal11_MASK (0xF000U)
15674#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal11_SHIFT (12U)
15675#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal11(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal11_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal11_MASK)
15676/*! @} */
15677
15678/*! @name DFIFREQXLAT3 - DFI Frequency Translation Register 3 */
15679/*! @{ */
15680#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal12_MASK (0xFU)
15681#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal12_SHIFT (0U)
15682#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal12(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal12_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal12_MASK)
15683#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal13_MASK (0xF0U)
15684#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal13_SHIFT (4U)
15685#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal13(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal13_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal13_MASK)
15686#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal14_MASK (0xF00U)
15687#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal14_SHIFT (8U)
15688#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal14(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal14_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal14_MASK)
15689#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal15_MASK (0xF000U)
15690#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal15_SHIFT (12U)
15691#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal15(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal15_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal15_MASK)
15692/*! @} */
15693
15694/*! @name DFIFREQXLAT4 - DFI Frequency Translation Register 4 */
15695/*! @{ */
15696#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal16_MASK (0xFU)
15697#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal16_SHIFT (0U)
15698#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal16(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal16_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal16_MASK)
15699#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal17_MASK (0xF0U)
15700#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal17_SHIFT (4U)
15701#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal17(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal17_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal17_MASK)
15702#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal18_MASK (0xF00U)
15703#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal18_SHIFT (8U)
15704#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal18(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal18_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal18_MASK)
15705#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal19_MASK (0xF000U)
15706#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal19_SHIFT (12U)
15707#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal19(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal19_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal19_MASK)
15708/*! @} */
15709
15710/*! @name DFIFREQXLAT5 - DFI Frequency Translation Register 5 */
15711/*! @{ */
15712#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal20_MASK (0xFU)
15713#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal20_SHIFT (0U)
15714#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal20(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal20_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal20_MASK)
15715#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal21_MASK (0xF0U)
15716#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal21_SHIFT (4U)
15717#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal21(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal21_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal21_MASK)
15718#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal22_MASK (0xF00U)
15719#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal22_SHIFT (8U)
15720#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal22(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal22_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal22_MASK)
15721#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal23_MASK (0xF000U)
15722#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal23_SHIFT (12U)
15723#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal23(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal23_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal23_MASK)
15724/*! @} */
15725
15726/*! @name DFIFREQXLAT6 - DFI Frequency Translation Register 6 */
15727/*! @{ */
15728#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal24_MASK (0xFU)
15729#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal24_SHIFT (0U)
15730#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal24(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal24_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal24_MASK)
15731#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal25_MASK (0xF0U)
15732#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal25_SHIFT (4U)
15733#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal25(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal25_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal25_MASK)
15734#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal26_MASK (0xF00U)
15735#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal26_SHIFT (8U)
15736#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal26(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal26_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal26_MASK)
15737#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal27_MASK (0xF000U)
15738#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal27_SHIFT (12U)
15739#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal27(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal27_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal27_MASK)
15740/*! @} */
15741
15742/*! @name DFIFREQXLAT7 - DFI Frequency Translation Register 7 */
15743/*! @{ */
15744#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal28_MASK (0xFU)
15745#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal28_SHIFT (0U)
15746#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal28(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal28_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal28_MASK)
15747#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal29_MASK (0xF0U)
15748#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal29_SHIFT (4U)
15749#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal29(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal29_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal29_MASK)
15750#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal30_MASK (0xF00U)
15751#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal30_SHIFT (8U)
15752#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal30(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal30_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal30_MASK)
15753#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal31_MASK (0xF000U)
15754#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal31_SHIFT (12U)
15755#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal31(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal31_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal31_MASK)
15756/*! @} */
15757
15758/*! @name TXRDPTRINIT - TxRdPtrInit control register */
15759/*! @{ */
15760#define DWC_DDRPHYA_MASTER_TXRDPTRINIT_TxRdPtrInit_MASK (0x1U)
15761#define DWC_DDRPHYA_MASTER_TXRDPTRINIT_TxRdPtrInit_SHIFT (0U)
15762#define DWC_DDRPHYA_MASTER_TXRDPTRINIT_TxRdPtrInit(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXRDPTRINIT_TxRdPtrInit_SHIFT)) & DWC_DDRPHYA_MASTER_TXRDPTRINIT_TxRdPtrInit_MASK)
15763/*! @} */
15764
15765/*! @name DFIINITCOMPLETE - DFI Init Complete control */
15766/*! @{ */
15767#define DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DfiInitComplete_MASK (0x1U)
15768#define DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DfiInitComplete_SHIFT (0U)
15769#define DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DfiInitComplete(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DfiInitComplete_SHIFT)) & DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DfiInitComplete_MASK)
15770/*! @} */
15771
15772/*! @name DFIFREQRATIO_P0 - DFI Frequency Ratio */
15773/*! @{ */
15774#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DfiFreqRatio_p0_MASK (0x3U)
15775#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DfiFreqRatio_p0_SHIFT (0U)
15776#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DfiFreqRatio_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DfiFreqRatio_p0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DfiFreqRatio_p0_MASK)
15777/*! @} */
15778
15779/*! @name RXFIFOCHECKS - Enable more frequent consistency checks of the RX FIFOs */
15780/*! @{ */
15781#define DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DoFrequentRxFifoChecks_MASK (0x1U)
15782#define DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DoFrequentRxFifoChecks_SHIFT (0U)
15783#define DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DoFrequentRxFifoChecks(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DoFrequentRxFifoChecks_SHIFT)) & DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DoFrequentRxFifoChecks_MASK)
15784/*! @} */
15785
15786/*! @name MTESTDTOCTRL - */
15787/*! @{ */
15788#define DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTestDtoCtrl_MASK (0x1U)
15789#define DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTestDtoCtrl_SHIFT (0U)
15790#define DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTestDtoCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTestDtoCtrl_SHIFT)) & DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTestDtoCtrl_MASK)
15791/*! @} */
15792
15793/*! @name MAPCAA0TODFI - Maps PHY CAA lane 0 from dfi0_address of the index of the register contents */
15794/*! @{ */
15795#define DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MapCAA0toDfi_MASK (0xFU)
15796#define DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MapCAA0toDfi_SHIFT (0U)
15797#define DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MapCAA0toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MapCAA0toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MapCAA0toDfi_MASK)
15798/*! @} */
15799
15800/*! @name MAPCAA1TODFI - Maps PHY CAA lane 1 from dfi0_address of the index of the register contents */
15801/*! @{ */
15802#define DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MapCAA1toDfi_MASK (0xFU)
15803#define DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MapCAA1toDfi_SHIFT (0U)
15804#define DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MapCAA1toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MapCAA1toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MapCAA1toDfi_MASK)
15805/*! @} */
15806
15807/*! @name MAPCAA2TODFI - Maps PHY CAA lane 2 from dfi0_address of the index of the register contents */
15808/*! @{ */
15809#define DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MapCAA2toDfi_MASK (0xFU)
15810#define DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MapCAA2toDfi_SHIFT (0U)
15811#define DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MapCAA2toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MapCAA2toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MapCAA2toDfi_MASK)
15812/*! @} */
15813
15814/*! @name MAPCAA3TODFI - Maps PHY CAA lane 3 from dfi0_address of the index of the register contents */
15815/*! @{ */
15816#define DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MapCAA3toDfi_MASK (0xFU)
15817#define DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MapCAA3toDfi_SHIFT (0U)
15818#define DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MapCAA3toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MapCAA3toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MapCAA3toDfi_MASK)
15819/*! @} */
15820
15821/*! @name MAPCAA4TODFI - Maps PHY CAA lane 4 from dfi0_address of the index of the register contents */
15822/*! @{ */
15823#define DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MapCAA4toDfi_MASK (0xFU)
15824#define DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MapCAA4toDfi_SHIFT (0U)
15825#define DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MapCAA4toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MapCAA4toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MapCAA4toDfi_MASK)
15826/*! @} */
15827
15828/*! @name MAPCAA5TODFI - Maps PHY CAA lane 5 from dfi0_address of the index of the register contents */
15829/*! @{ */
15830#define DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MapCAA5toDfi_MASK (0xFU)
15831#define DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MapCAA5toDfi_SHIFT (0U)
15832#define DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MapCAA5toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MapCAA5toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MapCAA5toDfi_MASK)
15833/*! @} */
15834
15835/*! @name MAPCAA6TODFI - Maps PHY CAA lane 6 from dfi0_address of the index of the register contents */
15836/*! @{ */
15837#define DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MapCAA6toDfi_MASK (0xFU)
15838#define DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MapCAA6toDfi_SHIFT (0U)
15839#define DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MapCAA6toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MapCAA6toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MapCAA6toDfi_MASK)
15840/*! @} */
15841
15842/*! @name MAPCAA7TODFI - Maps PHY CAA lane 7 from dfi0_address of the index of the register contents */
15843/*! @{ */
15844#define DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MapCAA7toDfi_MASK (0xFU)
15845#define DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MapCAA7toDfi_SHIFT (0U)
15846#define DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MapCAA7toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MapCAA7toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MapCAA7toDfi_MASK)
15847/*! @} */
15848
15849/*! @name MAPCAA8TODFI - Maps PHY CAA lane 8 from dfi0_address of the index of the register contents */
15850/*! @{ */
15851#define DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MapCAA8toDfi_MASK (0xFU)
15852#define DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MapCAA8toDfi_SHIFT (0U)
15853#define DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MapCAA8toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MapCAA8toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MapCAA8toDfi_MASK)
15854/*! @} */
15855
15856/*! @name MAPCAA9TODFI - Maps PHY CAA lane 9 from dfi0_address of the index of the register contents */
15857/*! @{ */
15858#define DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MapCAA9toDfi_MASK (0xFU)
15859#define DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MapCAA9toDfi_SHIFT (0U)
15860#define DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MapCAA9toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MapCAA9toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MapCAA9toDfi_MASK)
15861/*! @} */
15862
15863/*! @name MAPCAB0TODFI - Maps PHY CAB lane 0 from dfi1_address of the index of the register contents */
15864/*! @{ */
15865#define DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MapCAB0toDfi_MASK (0xFU)
15866#define DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MapCAB0toDfi_SHIFT (0U)
15867#define DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MapCAB0toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MapCAB0toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MapCAB0toDfi_MASK)
15868/*! @} */
15869
15870/*! @name MAPCAB1TODFI - Maps PHY CAB lane 1 from dfi1_address of the index of the register contents */
15871/*! @{ */
15872#define DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MapCAB1toDfi_MASK (0xFU)
15873#define DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MapCAB1toDfi_SHIFT (0U)
15874#define DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MapCAB1toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MapCAB1toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MapCAB1toDfi_MASK)
15875/*! @} */
15876
15877/*! @name MAPCAB2TODFI - Maps PHY CAB lane 2 from dfi1_address of the index of the register contents */
15878/*! @{ */
15879#define DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MapCAB2toDfi_MASK (0xFU)
15880#define DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MapCAB2toDfi_SHIFT (0U)
15881#define DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MapCAB2toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MapCAB2toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MapCAB2toDfi_MASK)
15882/*! @} */
15883
15884/*! @name MAPCAB3TODFI - Maps PHY CAB lane 3 from dfi1_address of the index of the register contents */
15885/*! @{ */
15886#define DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MapCAB3toDfi_MASK (0xFU)
15887#define DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MapCAB3toDfi_SHIFT (0U)
15888#define DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MapCAB3toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MapCAB3toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MapCAB3toDfi_MASK)
15889/*! @} */
15890
15891/*! @name MAPCAB4TODFI - Maps PHY CAB lane 4 from dfi1_address of the index of the register contents */
15892/*! @{ */
15893#define DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MapCAB4toDfi_MASK (0xFU)
15894#define DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MapCAB4toDfi_SHIFT (0U)
15895#define DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MapCAB4toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MapCAB4toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MapCAB4toDfi_MASK)
15896/*! @} */
15897
15898/*! @name MAPCAB5TODFI - Maps PHY CAB lane 5 from dfi1_address of the index of the register contents */
15899/*! @{ */
15900#define DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MapCAB5toDfi_MASK (0xFU)
15901#define DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MapCAB5toDfi_SHIFT (0U)
15902#define DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MapCAB5toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MapCAB5toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MapCAB5toDfi_MASK)
15903/*! @} */
15904
15905/*! @name MAPCAB6TODFI - Maps PHY CAB lane 6 from dfi1_address of the index of the register contents */
15906/*! @{ */
15907#define DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MapCAB6toDfi_MASK (0xFU)
15908#define DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MapCAB6toDfi_SHIFT (0U)
15909#define DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MapCAB6toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MapCAB6toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MapCAB6toDfi_MASK)
15910/*! @} */
15911
15912/*! @name MAPCAB7TODFI - Maps PHY CAB lane 7 from dfi1_address of the index of the register contents */
15913/*! @{ */
15914#define DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MapCAB7toDfi_MASK (0xFU)
15915#define DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MapCAB7toDfi_SHIFT (0U)
15916#define DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MapCAB7toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MapCAB7toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MapCAB7toDfi_MASK)
15917/*! @} */
15918
15919/*! @name MAPCAB8TODFI - Maps PHY CAB lane 8 from dfi1_address of the index of the register contents */
15920/*! @{ */
15921#define DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MapCAB8toDfi_MASK (0xFU)
15922#define DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MapCAB8toDfi_SHIFT (0U)
15923#define DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MapCAB8toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MapCAB8toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MapCAB8toDfi_MASK)
15924/*! @} */
15925
15926/*! @name MAPCAB9TODFI - Maps PHY CAB lane 9 from dfi1_address of the index of the register contents */
15927/*! @{ */
15928#define DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MapCAB9toDfi_MASK (0xFU)
15929#define DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MapCAB9toDfi_SHIFT (0U)
15930#define DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MapCAB9toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MapCAB9toDfi_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MapCAB9toDfi_MASK)
15931/*! @} */
15932
15933/*! @name PHYINTERRUPTENABLE - Interrupt Enable Bits */
15934/*! @{ */
15935#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngCmpltEn_MASK (0x1U)
15936#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngCmpltEn_SHIFT (0U)
15937#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngCmpltEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngCmpltEn_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngCmpltEn_MASK)
15938#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyInitCmpltEn_MASK (0x2U)
15939#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyInitCmpltEn_SHIFT (1U)
15940#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyInitCmpltEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyInitCmpltEn_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyInitCmpltEn_MASK)
15941#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngFailEn_MASK (0x4U)
15942#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngFailEn_SHIFT (2U)
15943#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngFailEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngFailEn_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngFailEn_MASK)
15944#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyFWReservedEn_MASK (0xF8U)
15945#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyFWReservedEn_SHIFT (3U)
15946#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyFWReservedEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyFWReservedEn_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyFWReservedEn_MASK)
15947#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyVTDriftAlarmEn_MASK (0x300U)
15948#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyVTDriftAlarmEn_SHIFT (8U)
15949#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyVTDriftAlarmEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyVTDriftAlarmEn_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyVTDriftAlarmEn_MASK)
15950#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyRxFifoCheckEn_MASK (0x400U)
15951#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyRxFifoCheckEn_SHIFT (10U)
15952#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyRxFifoCheckEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyRxFifoCheckEn_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyRxFifoCheckEn_MASK)
15953#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyHWReservedEn_MASK (0xF800U)
15954#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyHWReservedEn_SHIFT (11U)
15955#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyHWReservedEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyHWReservedEn_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyHWReservedEn_MASK)
15956/*! @} */
15957
15958/*! @name PHYINTERRUPTFWCONTROL - Interrupt Firmware Control Bits */
15959/*! @{ */
15960#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngCmpltFW_MASK (0x1U)
15961#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngCmpltFW_SHIFT (0U)
15962#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngCmpltFW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngCmpltFW_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngCmpltFW_MASK)
15963#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyInitCmpltFW_MASK (0x2U)
15964#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyInitCmpltFW_SHIFT (1U)
15965#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyInitCmpltFW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyInitCmpltFW_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyInitCmpltFW_MASK)
15966#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngFailFW_MASK (0x4U)
15967#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngFailFW_SHIFT (2U)
15968#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngFailFW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngFailFW_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngFailFW_MASK)
15969#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyFWReservedFW_MASK (0xF8U)
15970#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyFWReservedFW_SHIFT (3U)
15971#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyFWReservedFW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyFWReservedFW_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyFWReservedFW_MASK)
15972/*! @} */
15973
15974/*! @name PHYINTERRUPTMASK - Interrupt Mask Bits */
15975/*! @{ */
15976#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngCmpltMsk_MASK (0x1U)
15977#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngCmpltMsk_SHIFT (0U)
15978#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngCmpltMsk(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngCmpltMsk_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngCmpltMsk_MASK)
15979#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyInitCmpltMsk_MASK (0x2U)
15980#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyInitCmpltMsk_SHIFT (1U)
15981#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyInitCmpltMsk(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyInitCmpltMsk_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyInitCmpltMsk_MASK)
15982#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngFailMsk_MASK (0x4U)
15983#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngFailMsk_SHIFT (2U)
15984#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngFailMsk(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngFailMsk_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngFailMsk_MASK)
15985#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyFWReservedMsk_MASK (0xF8U)
15986#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyFWReservedMsk_SHIFT (3U)
15987#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyFWReservedMsk(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyFWReservedMsk_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyFWReservedMsk_MASK)
15988#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyVTDriftAlarmMsk_MASK (0x300U)
15989#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyVTDriftAlarmMsk_SHIFT (8U)
15990#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyVTDriftAlarmMsk(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyVTDriftAlarmMsk_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyVTDriftAlarmMsk_MASK)
15991#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyRxFifoCheckMsk_MASK (0x400U)
15992#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyRxFifoCheckMsk_SHIFT (10U)
15993#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyRxFifoCheckMsk(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyRxFifoCheckMsk_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyRxFifoCheckMsk_MASK)
15994#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyHWReservedMsk_MASK (0xF800U)
15995#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyHWReservedMsk_SHIFT (11U)
15996#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyHWReservedMsk(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyHWReservedMsk_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyHWReservedMsk_MASK)
15997/*! @} */
15998
15999/*! @name PHYINTERRUPTCLEAR - Interrupt Clear Bits */
16000/*! @{ */
16001#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngCmpltClr_MASK (0x1U)
16002#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngCmpltClr_SHIFT (0U)
16003#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngCmpltClr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngCmpltClr_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngCmpltClr_MASK)
16004#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyInitCmpltClr_MASK (0x2U)
16005#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyInitCmpltClr_SHIFT (1U)
16006#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyInitCmpltClr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyInitCmpltClr_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyInitCmpltClr_MASK)
16007#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngFailClr_MASK (0x4U)
16008#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngFailClr_SHIFT (2U)
16009#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngFailClr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngFailClr_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngFailClr_MASK)
16010#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyFWReservedClr_MASK (0xF8U)
16011#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyFWReservedClr_SHIFT (3U)
16012#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyFWReservedClr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyFWReservedClr_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyFWReservedClr_MASK)
16013#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyVTDriftAlarmClr_MASK (0x300U)
16014#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyVTDriftAlarmClr_SHIFT (8U)
16015#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyVTDriftAlarmClr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyVTDriftAlarmClr_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyVTDriftAlarmClr_MASK)
16016#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyRxFifoCheckClr_MASK (0x400U)
16017#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyRxFifoCheckClr_SHIFT (10U)
16018#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyRxFifoCheckClr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyRxFifoCheckClr_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyRxFifoCheckClr_MASK)
16019#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyHWReservedClr_MASK (0xF800U)
16020#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyHWReservedClr_SHIFT (11U)
16021#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyHWReservedClr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyHWReservedClr_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyHWReservedClr_MASK)
16022/*! @} */
16023
16024/*! @name PHYINTERRUPTSTATUS - Interrupt Status Bits */
16025/*! @{ */
16026#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngCmplt_MASK (0x1U)
16027#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngCmplt_SHIFT (0U)
16028#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngCmplt(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngCmplt_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngCmplt_MASK)
16029#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyInitCmplt_MASK (0x2U)
16030#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyInitCmplt_SHIFT (1U)
16031#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyInitCmplt(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyInitCmplt_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyInitCmplt_MASK)
16032#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngFail_MASK (0x4U)
16033#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngFail_SHIFT (2U)
16034#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngFail(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngFail_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngFail_MASK)
16035#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyFWReserved_MASK (0xF8U)
16036#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyFWReserved_SHIFT (3U)
16037#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyFWReserved(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyFWReserved_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyFWReserved_MASK)
16038#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDriftAlarm_MASK (0x300U)
16039#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDriftAlarm_SHIFT (8U)
16040#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDriftAlarm(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDriftAlarm_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDriftAlarm_MASK)
16041#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyRxFifoCheck_MASK (0x400U)
16042#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyRxFifoCheck_SHIFT (10U)
16043#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyRxFifoCheck(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyRxFifoCheck_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyRxFifoCheck_MASK)
16044#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyHWReserved_MASK (0xF800U)
16045#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyHWReserved_SHIFT (11U)
16046#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyHWReserved(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyHWReserved_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyHWReserved_MASK)
16047/*! @} */
16048
16049/*! @name HWTSWIZZLEHWTADDRESS0 - Signal swizzle selection for HWT swizzle */
16050/*! @{ */
16051#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HwtSwizzleHwtAddress0_MASK (0x1FU)
16052#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HwtSwizzleHwtAddress0_SHIFT (0U)
16053#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HwtSwizzleHwtAddress0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HwtSwizzleHwtAddress0_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HwtSwizzleHwtAddress0_MASK)
16054/*! @} */
16055
16056/*! @name HWTSWIZZLEHWTADDRESS1 - Signal swizzle selection for HWT swizzle */
16057/*! @{ */
16058#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HwtSwizzleHwtAddress1_MASK (0x1FU)
16059#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HwtSwizzleHwtAddress1_SHIFT (0U)
16060#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HwtSwizzleHwtAddress1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HwtSwizzleHwtAddress1_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HwtSwizzleHwtAddress1_MASK)
16061/*! @} */
16062
16063/*! @name HWTSWIZZLEHWTADDRESS2 - Signal swizzle selection for HWT swizzle */
16064/*! @{ */
16065#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HwtSwizzleHwtAddress2_MASK (0x1FU)
16066#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HwtSwizzleHwtAddress2_SHIFT (0U)
16067#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HwtSwizzleHwtAddress2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HwtSwizzleHwtAddress2_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HwtSwizzleHwtAddress2_MASK)
16068/*! @} */
16069
16070/*! @name HWTSWIZZLEHWTADDRESS3 - Signal swizzle selection for HWT swizzle */
16071/*! @{ */
16072#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HwtSwizzleHwtAddress3_MASK (0x1FU)
16073#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HwtSwizzleHwtAddress3_SHIFT (0U)
16074#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HwtSwizzleHwtAddress3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HwtSwizzleHwtAddress3_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HwtSwizzleHwtAddress3_MASK)
16075/*! @} */
16076
16077/*! @name HWTSWIZZLEHWTADDRESS4 - Signal swizzle selection for HWT swizzle */
16078/*! @{ */
16079#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HwtSwizzleHwtAddress4_MASK (0x1FU)
16080#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HwtSwizzleHwtAddress4_SHIFT (0U)
16081#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HwtSwizzleHwtAddress4(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HwtSwizzleHwtAddress4_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HwtSwizzleHwtAddress4_MASK)
16082/*! @} */
16083
16084/*! @name HWTSWIZZLEHWTADDRESS5 - Signal swizzle selection for HWT swizzle */
16085/*! @{ */
16086#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HwtSwizzleHwtAddress5_MASK (0x1FU)
16087#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HwtSwizzleHwtAddress5_SHIFT (0U)
16088#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HwtSwizzleHwtAddress5(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HwtSwizzleHwtAddress5_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HwtSwizzleHwtAddress5_MASK)
16089/*! @} */
16090
16091/*! @name HWTSWIZZLEHWTADDRESS6 - Signal swizzle selection for HWT swizzle */
16092/*! @{ */
16093#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HwtSwizzleHwtAddress6_MASK (0x1FU)
16094#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HwtSwizzleHwtAddress6_SHIFT (0U)
16095#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HwtSwizzleHwtAddress6(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HwtSwizzleHwtAddress6_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HwtSwizzleHwtAddress6_MASK)
16096/*! @} */
16097
16098/*! @name HWTSWIZZLEHWTADDRESS7 - Signal swizzle selection for HWT swizzle */
16099/*! @{ */
16100#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HwtSwizzleHwtAddress7_MASK (0x1FU)
16101#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HwtSwizzleHwtAddress7_SHIFT (0U)
16102#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HwtSwizzleHwtAddress7(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HwtSwizzleHwtAddress7_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HwtSwizzleHwtAddress7_MASK)
16103/*! @} */
16104
16105/*! @name HWTSWIZZLEHWTADDRESS8 - Signal swizzle selection for HWT swizzle */
16106/*! @{ */
16107#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HwtSwizzleHwtAddress8_MASK (0x1FU)
16108#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HwtSwizzleHwtAddress8_SHIFT (0U)
16109#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HwtSwizzleHwtAddress8(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HwtSwizzleHwtAddress8_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HwtSwizzleHwtAddress8_MASK)
16110/*! @} */
16111
16112/*! @name HWTSWIZZLEHWTADDRESS9 - Signal swizzle selection for HWT swizzle */
16113/*! @{ */
16114#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HwtSwizzleHwtAddress9_MASK (0x1FU)
16115#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HwtSwizzleHwtAddress9_SHIFT (0U)
16116#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HwtSwizzleHwtAddress9(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HwtSwizzleHwtAddress9_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HwtSwizzleHwtAddress9_MASK)
16117/*! @} */
16118
16119/*! @name HWTSWIZZLEHWTADDRESS10 - Signal swizzle selection for HWT swizzle */
16120/*! @{ */
16121#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HwtSwizzleHwtAddress10_MASK (0x1FU)
16122#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HwtSwizzleHwtAddress10_SHIFT (0U)
16123#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HwtSwizzleHwtAddress10(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HwtSwizzleHwtAddress10_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HwtSwizzleHwtAddress10_MASK)
16124/*! @} */
16125
16126/*! @name HWTSWIZZLEHWTADDRESS11 - Signal swizzle selection for HWT swizzle */
16127/*! @{ */
16128#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HwtSwizzleHwtAddress11_MASK (0x1FU)
16129#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HwtSwizzleHwtAddress11_SHIFT (0U)
16130#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HwtSwizzleHwtAddress11(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HwtSwizzleHwtAddress11_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HwtSwizzleHwtAddress11_MASK)
16131/*! @} */
16132
16133/*! @name HWTSWIZZLEHWTADDRESS12 - Signal swizzle selection for HWT swizzle */
16134/*! @{ */
16135#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HwtSwizzleHwtAddress12_MASK (0x1FU)
16136#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HwtSwizzleHwtAddress12_SHIFT (0U)
16137#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HwtSwizzleHwtAddress12(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HwtSwizzleHwtAddress12_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HwtSwizzleHwtAddress12_MASK)
16138/*! @} */
16139
16140/*! @name HWTSWIZZLEHWTADDRESS13 - Signal swizzle selection for HWT swizzle */
16141/*! @{ */
16142#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HwtSwizzleHwtAddress13_MASK (0x1FU)
16143#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HwtSwizzleHwtAddress13_SHIFT (0U)
16144#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HwtSwizzleHwtAddress13(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HwtSwizzleHwtAddress13_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HwtSwizzleHwtAddress13_MASK)
16145/*! @} */
16146
16147/*! @name HWTSWIZZLEHWTADDRESS14 - Signal swizzle selection for HWT swizzle */
16148/*! @{ */
16149#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HwtSwizzleHwtAddress14_MASK (0x1FU)
16150#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HwtSwizzleHwtAddress14_SHIFT (0U)
16151#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HwtSwizzleHwtAddress14(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HwtSwizzleHwtAddress14_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HwtSwizzleHwtAddress14_MASK)
16152/*! @} */
16153
16154/*! @name HWTSWIZZLEHWTADDRESS15 - Signal swizzle selection for HWT swizzle */
16155/*! @{ */
16156#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HwtSwizzleHwtAddress15_MASK (0x1FU)
16157#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HwtSwizzleHwtAddress15_SHIFT (0U)
16158#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HwtSwizzleHwtAddress15(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HwtSwizzleHwtAddress15_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HwtSwizzleHwtAddress15_MASK)
16159/*! @} */
16160
16161/*! @name HWTSWIZZLEHWTADDRESS17 - Signal swizzle selection for HWT swizzle */
16162/*! @{ */
16163#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HwtSwizzleHwtAddress17_MASK (0x1FU)
16164#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HwtSwizzleHwtAddress17_SHIFT (0U)
16165#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HwtSwizzleHwtAddress17(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HwtSwizzleHwtAddress17_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HwtSwizzleHwtAddress17_MASK)
16166/*! @} */
16167
16168/*! @name HWTSWIZZLEHWTACTN - Signal swizzle selection for HWT swizzle */
16169/*! @{ */
16170#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HwtSwizzleHwtActN_MASK (0x1FU)
16171#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HwtSwizzleHwtActN_SHIFT (0U)
16172#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HwtSwizzleHwtActN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HwtSwizzleHwtActN_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HwtSwizzleHwtActN_MASK)
16173/*! @} */
16174
16175/*! @name HWTSWIZZLEHWTBANK0 - Signal swizzle selection for HWT swizzle */
16176/*! @{ */
16177#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HwtSwizzleHwtBank0_MASK (0x1FU)
16178#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HwtSwizzleHwtBank0_SHIFT (0U)
16179#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HwtSwizzleHwtBank0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HwtSwizzleHwtBank0_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HwtSwizzleHwtBank0_MASK)
16180/*! @} */
16181
16182/*! @name HWTSWIZZLEHWTBANK1 - Signal swizzle selection for HWT swizzle */
16183/*! @{ */
16184#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HwtSwizzleHwtBank1_MASK (0x1FU)
16185#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HwtSwizzleHwtBank1_SHIFT (0U)
16186#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HwtSwizzleHwtBank1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HwtSwizzleHwtBank1_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HwtSwizzleHwtBank1_MASK)
16187/*! @} */
16188
16189/*! @name HWTSWIZZLEHWTBANK2 - Signal swizzle selection for HWT swizzle */
16190/*! @{ */
16191#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HwtSwizzleHwtBank2_MASK (0x1FU)
16192#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HwtSwizzleHwtBank2_SHIFT (0U)
16193#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HwtSwizzleHwtBank2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HwtSwizzleHwtBank2_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HwtSwizzleHwtBank2_MASK)
16194/*! @} */
16195
16196/*! @name HWTSWIZZLEHWTBG0 - Signal swizzle selection for HWT swizzle */
16197/*! @{ */
16198#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HwtSwizzleHwtBg0_MASK (0x1FU)
16199#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HwtSwizzleHwtBg0_SHIFT (0U)
16200#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HwtSwizzleHwtBg0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HwtSwizzleHwtBg0_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HwtSwizzleHwtBg0_MASK)
16201/*! @} */
16202
16203/*! @name HWTSWIZZLEHWTBG1 - Signal swizzle selection for HWT swizzle */
16204/*! @{ */
16205#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HwtSwizzleHwtBg1_MASK (0x1FU)
16206#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HwtSwizzleHwtBg1_SHIFT (0U)
16207#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HwtSwizzleHwtBg1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HwtSwizzleHwtBg1_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HwtSwizzleHwtBg1_MASK)
16208/*! @} */
16209
16210/*! @name HWTSWIZZLEHWTCASN - Signal swizzle selection for HWT swizzle */
16211/*! @{ */
16212#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HwtSwizzleHwtCasN_MASK (0x1FU)
16213#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HwtSwizzleHwtCasN_SHIFT (0U)
16214#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HwtSwizzleHwtCasN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HwtSwizzleHwtCasN_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HwtSwizzleHwtCasN_MASK)
16215/*! @} */
16216
16217/*! @name HWTSWIZZLEHWTRASN - Signal swizzle selection for HWT swizzle */
16218/*! @{ */
16219#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HwtSwizzleHwtRasN_MASK (0x1FU)
16220#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HwtSwizzleHwtRasN_SHIFT (0U)
16221#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HwtSwizzleHwtRasN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HwtSwizzleHwtRasN_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HwtSwizzleHwtRasN_MASK)
16222/*! @} */
16223
16224/*! @name HWTSWIZZLEHWTWEN - Signal swizzle selection for HWT swizzle */
16225/*! @{ */
16226#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HwtSwizzleHwtWeN_MASK (0x1FU)
16227#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HwtSwizzleHwtWeN_SHIFT (0U)
16228#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HwtSwizzleHwtWeN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HwtSwizzleHwtWeN_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HwtSwizzleHwtWeN_MASK)
16229/*! @} */
16230
16231/*! @name HWTSWIZZLEHWTPARITYIN - Signal swizzle selection for HWT swizzle */
16232/*! @{ */
16233#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HwtSwizzleHwtParityIn_MASK (0x1FU)
16234#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HwtSwizzleHwtParityIn_SHIFT (0U)
16235#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HwtSwizzleHwtParityIn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HwtSwizzleHwtParityIn_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HwtSwizzleHwtParityIn_MASK)
16236/*! @} */
16237
16238/*! @name DFIHANDSHAKEDELAYS0 - Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal assertions exceed the programmed delays */
16239/*! @{ */
16240#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdAckDelay0_MASK (0xFU)
16241#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdAckDelay0_SHIFT (0U)
16242#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdAckDelay0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdAckDelay0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdAckDelay0_MASK)
16243#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdReqDelay0_MASK (0xF0U)
16244#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdReqDelay0_SHIFT (4U)
16245#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdReqDelay0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdReqDelay0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdReqDelay0_MASK)
16246#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdAckDelay0_MASK (0xF00U)
16247#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdAckDelay0_SHIFT (8U)
16248#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdAckDelay0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdAckDelay0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdAckDelay0_MASK)
16249#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdReqDelay0_MASK (0xF000U)
16250#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdReqDelay0_SHIFT (12U)
16251#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdReqDelay0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdReqDelay0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdReqDelay0_MASK)
16252/*! @} */
16253
16254/*! @name DFIHANDSHAKEDELAYS1 - Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal assertions exceed the programmed delays */
16255/*! @{ */
16256#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdAckDelay1_MASK (0xFU)
16257#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdAckDelay1_SHIFT (0U)
16258#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdAckDelay1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdAckDelay1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdAckDelay1_MASK)
16259#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdReqDelay1_MASK (0xF0U)
16260#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdReqDelay1_SHIFT (4U)
16261#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdReqDelay1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdReqDelay1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdReqDelay1_MASK)
16262#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdAckDelay1_MASK (0xF00U)
16263#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdAckDelay1_SHIFT (8U)
16264#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdAckDelay1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdAckDelay1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdAckDelay1_MASK)
16265#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdReqDelay1_MASK (0xF000U)
16266#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdReqDelay1_SHIFT (12U)
16267#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdReqDelay1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdReqDelay1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdReqDelay1_MASK)
16268/*! @} */
16269
16270/*! @name CALUCLKINFO_P1 - Impedance Calibration Clock Ratio */
16271/*! @{ */
16272#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CalUClkTicksPer1uS_MASK (0x3FFU)
16273#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CalUClkTicksPer1uS_SHIFT (0U)
16274#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CalUClkTicksPer1uS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CalUClkTicksPer1uS_SHIFT)) & DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CalUClkTicksPer1uS_MASK)
16275/*! @} */
16276
16277/*! @name SEQ0BDLY0_P1 - PHY Initialization Engine (PIE) Delay Register 0 */
16278/*! @{ */
16279#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_Seq0BDLY0_p1_MASK (0xFFFFU)
16280#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_Seq0BDLY0_p1_SHIFT (0U)
16281#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_Seq0BDLY0_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_Seq0BDLY0_p1_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_Seq0BDLY0_p1_MASK)
16282/*! @} */
16283
16284/*! @name SEQ0BDLY1_P1 - PHY Initialization Engine (PIE) Delay Register 1 */
16285/*! @{ */
16286#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_Seq0BDLY1_p1_MASK (0xFFFFU)
16287#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_Seq0BDLY1_p1_SHIFT (0U)
16288#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_Seq0BDLY1_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_Seq0BDLY1_p1_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_Seq0BDLY1_p1_MASK)
16289/*! @} */
16290
16291/*! @name SEQ0BDLY2_P1 - PHY Initialization Engine (PIE) Delay Register 2 */
16292/*! @{ */
16293#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_Seq0BDLY2_p1_MASK (0xFFFFU)
16294#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_Seq0BDLY2_p1_SHIFT (0U)
16295#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_Seq0BDLY2_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_Seq0BDLY2_p1_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_Seq0BDLY2_p1_MASK)
16296/*! @} */
16297
16298/*! @name SEQ0BDLY3_P1 - PHY Initialization Engine (PIE) Delay Register 3 */
16299/*! @{ */
16300#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_Seq0BDLY3_p1_MASK (0xFFFFU)
16301#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_Seq0BDLY3_p1_SHIFT (0U)
16302#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_Seq0BDLY3_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_Seq0BDLY3_p1_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_Seq0BDLY3_p1_MASK)
16303/*! @} */
16304
16305/*! @name PPTTRAINSETUP_P1 - Setup Intervals for DFI PHY Master operations */
16306/*! @{ */
16307#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrTrainInterval_MASK (0xFU)
16308#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrTrainInterval_SHIFT (0U)
16309#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrTrainInterval(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrTrainInterval_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrTrainInterval_MASK)
16310#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrMaxReqToAck_MASK (0x70U)
16311#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrMaxReqToAck_SHIFT (4U)
16312#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrMaxReqToAck(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrMaxReqToAck_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrMaxReqToAck_MASK)
16313/*! @} */
16314
16315/*! @name TRISTATEMODECA_P1 - Mode select register for MEMCLK/Address/Command Tristates */
16316/*! @{ */
16317#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DisDynAdrTri_MASK (0x1U)
16318#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DisDynAdrTri_SHIFT (0U)
16319#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DisDynAdrTri(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DisDynAdrTri_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DisDynAdrTri_MASK)
16320#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMode_MASK (0x2U)
16321#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMode_SHIFT (1U)
16322#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMode_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMode_MASK)
16323#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CkDisVal_MASK (0xCU)
16324#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CkDisVal_SHIFT (2U)
16325#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CkDisVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CkDisVal_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CkDisVal_MASK)
16326/*! @} */
16327
16328/*! @name HWTMRL_P1 - HWT MaxReadLatency. */
16329/*! @{ */
16330#define DWC_DDRPHYA_MASTER_HWTMRL_P1_HwtMRL_p1_MASK (0x1FU)
16331#define DWC_DDRPHYA_MASTER_HWTMRL_P1_HwtMRL_p1_SHIFT (0U)
16332#define DWC_DDRPHYA_MASTER_HWTMRL_P1_HwtMRL_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P1_HwtMRL_p1_SHIFT)) & DWC_DDRPHYA_MASTER_HWTMRL_P1_HwtMRL_p1_MASK)
16333/*! @} */
16334
16335/*! @name DQSPREAMBLECONTROL_P1 - Control the PHY logic related to the read and write DQS preamble */
16336/*! @{ */
16337#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckRxDqsPre_MASK (0x1U)
16338#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckRxDqsPre_SHIFT (0U)
16339#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckRxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckRxDqsPre_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckRxDqsPre_MASK)
16340#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckTxDqsPre_MASK (0x2U)
16341#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckTxDqsPre_SHIFT (1U)
16342#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckTxDqsPre_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckTxDqsPre_MASK)
16343#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_PositionDfeInit_MASK (0x1CU)
16344#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_PositionDfeInit_SHIFT (2U)
16345#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_PositionDfeInit(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_PositionDfeInit_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_PositionDfeInit_MASK)
16346#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TglTwoTckTxDqsPre_MASK (0x20U)
16347#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TglTwoTckTxDqsPre_SHIFT (5U)
16348#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TglTwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TglTwoTckTxDqsPre_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TglTwoTckTxDqsPre_MASK)
16349#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4PostambleExt_MASK (0x40U)
16350#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4PostambleExt_SHIFT (6U)
16351#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4PostambleExt(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4PostambleExt_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4PostambleExt_MASK)
16352#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4SttcPreBridgeRxEn_MASK (0x80U)
16353#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4SttcPreBridgeRxEn_SHIFT (7U)
16354#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4SttcPreBridgeRxEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4SttcPreBridgeRxEn_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4SttcPreBridgeRxEn_MASK)
16355#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_MASK (0x100U)
16356#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_SHIFT (8U)
16357#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_MASK)
16358/*! @} */
16359
16360/*! @name DMIPINPRESENT_P1 - This Register is used to enable the Read-DBI function in each DBYTE */
16361/*! @{ */
16362#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RdDbiEnabled_MASK (0x1U)
16363#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RdDbiEnabled_SHIFT (0U)
16364#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RdDbiEnabled(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RdDbiEnabled_SHIFT)) & DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RdDbiEnabled_MASK)
16365/*! @} */
16366
16367/*! @name ARDPTRINITVAL_P1 - Address/Command FIFO ReadPointer Initial Value */
16368/*! @{ */
16369#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARdPtrInitVal_p1_MASK (0xFU)
16370#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARdPtrInitVal_p1_SHIFT (0U)
16371#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARdPtrInitVal_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARdPtrInitVal_p1_SHIFT)) & DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARdPtrInitVal_p1_MASK)
16372/*! @} */
16373
16374/*! @name PROCODTTIMECTL_P1 - READ DATA On-Die Termination Timing Control (by PHY) */
16375/*! @{ */
16376#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtTailWidth_MASK (0x3U)
16377#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtTailWidth_SHIFT (0U)
16378#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtTailWidth(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtTailWidth_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtTailWidth_MASK)
16379#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtStartDelay_MASK (0xCU)
16380#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtStartDelay_SHIFT (2U)
16381#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtStartDelay(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtStartDelay_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtStartDelay_MASK)
16382/*! @} */
16383
16384/*! @name DLLGAINCTL_P1 - DLL gain control */
16385/*! @{ */
16386#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainIV_MASK (0xFU)
16387#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainIV_SHIFT (0U)
16388#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainIV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainIV_MASK)
16389#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainTV_MASK (0xF0U)
16390#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainTV_SHIFT (4U)
16391#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainTV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainTV_MASK)
16392#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllSeedSel_MASK (0xF00U)
16393#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllSeedSel_SHIFT (8U)
16394#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllSeedSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllSeedSel_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllSeedSel_MASK)
16395/*! @} */
16396
16397/*! @name DFIRDDATACSDESTMAP_P1 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
16398/*! @{ */
16399#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm0_MASK (0x3U)
16400#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm0_SHIFT (0U)
16401#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm0_MASK)
16402#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm1_MASK (0xCU)
16403#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm1_SHIFT (2U)
16404#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm1_MASK)
16405#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm2_MASK (0x30U)
16406#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm2_SHIFT (4U)
16407#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm2_MASK)
16408#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm3_MASK (0xC0U)
16409#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm3_SHIFT (6U)
16410#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm3_MASK)
16411/*! @} */
16412
16413/*! @name VREFINGLOBAL_P1 - PHY Global Vref Controls */
16414/*! @{ */
16415#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInSel_MASK (0x7U)
16416#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInSel_SHIFT (0U)
16417#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInSel_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInSel_MASK)
16418#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInDAC_MASK (0x3F8U)
16419#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInDAC_SHIFT (3U)
16420#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInDAC_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInDAC_MASK)
16421#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInTrim_MASK (0x3C00U)
16422#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInTrim_SHIFT (10U)
16423#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInTrim(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInTrim_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInTrim_MASK)
16424#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInMode_MASK (0x4000U)
16425#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInMode_SHIFT (14U)
16426#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInMode_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInMode_MASK)
16427/*! @} */
16428
16429/*! @name DFIWRDATACSDESTMAP_P1 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
16430/*! @{ */
16431#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm0_MASK (0x3U)
16432#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm0_SHIFT (0U)
16433#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm0_MASK)
16434#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm1_MASK (0xCU)
16435#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm1_SHIFT (2U)
16436#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm1_MASK)
16437#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm2_MASK (0x30U)
16438#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm2_SHIFT (4U)
16439#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm2_MASK)
16440#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm3_MASK (0xC0U)
16441#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm3_SHIFT (6U)
16442#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm3_MASK)
16443/*! @} */
16444
16445/*! @name PLLCTRL2_P1 - PState dependent PLL Control Register 2 */
16446/*! @{ */
16447#define DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PllFreqSel_MASK (0x1FU)
16448#define DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PllFreqSel_SHIFT (0U)
16449#define DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PllFreqSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PllFreqSel_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PllFreqSel_MASK)
16450/*! @} */
16451
16452/*! @name PLLCTRL1_P1 - PState dependent PLL Control Register 1 */
16453/*! @{ */
16454#define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpIntCtrl_MASK (0x1FU)
16455#define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpIntCtrl_SHIFT (0U)
16456#define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpIntCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpIntCtrl_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpIntCtrl_MASK)
16457#define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpPropCtrl_MASK (0x1E0U)
16458#define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpPropCtrl_SHIFT (5U)
16459#define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpPropCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpPropCtrl_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpPropCtrl_MASK)
16460/*! @} */
16461
16462/*! @name PLLTESTMODE_P1 - Additional controls for PLL CP/VCO modes of operation */
16463/*! @{ */
16464#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PllTestMode_p1_MASK (0xFFFFU)
16465#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PllTestMode_p1_SHIFT (0U)
16466#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PllTestMode_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PllTestMode_p1_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PllTestMode_p1_MASK)
16467/*! @} */
16468
16469/*! @name PLLCTRL4_P1 - PState dependent PLL Control Register 4 */
16470/*! @{ */
16471#define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpIntGsCtrl_MASK (0x1FU)
16472#define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpIntGsCtrl_SHIFT (0U)
16473#define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpIntGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpIntGsCtrl_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpIntGsCtrl_MASK)
16474#define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpPropGsCtrl_MASK (0x1E0U)
16475#define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpPropGsCtrl_SHIFT (5U)
16476#define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpPropGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpPropGsCtrl_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpPropGsCtrl_MASK)
16477/*! @} */
16478
16479/*! @name DFIFREQRATIO_P1 - DFI Frequency Ratio */
16480/*! @{ */
16481#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DfiFreqRatio_p1_MASK (0x3U)
16482#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DfiFreqRatio_p1_SHIFT (0U)
16483#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DfiFreqRatio_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DfiFreqRatio_p1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DfiFreqRatio_p1_MASK)
16484/*! @} */
16485
16486/*! @name CALUCLKINFO_P2 - Impedance Calibration Clock Ratio */
16487/*! @{ */
16488#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CalUClkTicksPer1uS_MASK (0x3FFU)
16489#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CalUClkTicksPer1uS_SHIFT (0U)
16490#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CalUClkTicksPer1uS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CalUClkTicksPer1uS_SHIFT)) & DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CalUClkTicksPer1uS_MASK)
16491/*! @} */
16492
16493/*! @name SEQ0BDLY0_P2 - PHY Initialization Engine (PIE) Delay Register 0 */
16494/*! @{ */
16495#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_Seq0BDLY0_p2_MASK (0xFFFFU)
16496#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_Seq0BDLY0_p2_SHIFT (0U)
16497#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_Seq0BDLY0_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_Seq0BDLY0_p2_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_Seq0BDLY0_p2_MASK)
16498/*! @} */
16499
16500/*! @name SEQ0BDLY1_P2 - PHY Initialization Engine (PIE) Delay Register 1 */
16501/*! @{ */
16502#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_Seq0BDLY1_p2_MASK (0xFFFFU)
16503#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_Seq0BDLY1_p2_SHIFT (0U)
16504#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_Seq0BDLY1_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_Seq0BDLY1_p2_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_Seq0BDLY1_p2_MASK)
16505/*! @} */
16506
16507/*! @name SEQ0BDLY2_P2 - PHY Initialization Engine (PIE) Delay Register 2 */
16508/*! @{ */
16509#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_Seq0BDLY2_p2_MASK (0xFFFFU)
16510#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_Seq0BDLY2_p2_SHIFT (0U)
16511#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_Seq0BDLY2_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_Seq0BDLY2_p2_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_Seq0BDLY2_p2_MASK)
16512/*! @} */
16513
16514/*! @name SEQ0BDLY3_P2 - PHY Initialization Engine (PIE) Delay Register 3 */
16515/*! @{ */
16516#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_Seq0BDLY3_p2_MASK (0xFFFFU)
16517#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_Seq0BDLY3_p2_SHIFT (0U)
16518#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_Seq0BDLY3_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_Seq0BDLY3_p2_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_Seq0BDLY3_p2_MASK)
16519/*! @} */
16520
16521/*! @name PPTTRAINSETUP_P2 - Setup Intervals for DFI PHY Master operations */
16522/*! @{ */
16523#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrTrainInterval_MASK (0xFU)
16524#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrTrainInterval_SHIFT (0U)
16525#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrTrainInterval(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrTrainInterval_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrTrainInterval_MASK)
16526#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrMaxReqToAck_MASK (0x70U)
16527#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrMaxReqToAck_SHIFT (4U)
16528#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrMaxReqToAck(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrMaxReqToAck_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrMaxReqToAck_MASK)
16529/*! @} */
16530
16531/*! @name TRISTATEMODECA_P2 - Mode select register for MEMCLK/Address/Command Tristates */
16532/*! @{ */
16533#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DisDynAdrTri_MASK (0x1U)
16534#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DisDynAdrTri_SHIFT (0U)
16535#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DisDynAdrTri(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DisDynAdrTri_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DisDynAdrTri_MASK)
16536#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMode_MASK (0x2U)
16537#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMode_SHIFT (1U)
16538#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMode_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMode_MASK)
16539#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CkDisVal_MASK (0xCU)
16540#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CkDisVal_SHIFT (2U)
16541#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CkDisVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CkDisVal_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CkDisVal_MASK)
16542/*! @} */
16543
16544/*! @name HWTMRL_P2 - HWT MaxReadLatency. */
16545/*! @{ */
16546#define DWC_DDRPHYA_MASTER_HWTMRL_P2_HwtMRL_p2_MASK (0x1FU)
16547#define DWC_DDRPHYA_MASTER_HWTMRL_P2_HwtMRL_p2_SHIFT (0U)
16548#define DWC_DDRPHYA_MASTER_HWTMRL_P2_HwtMRL_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P2_HwtMRL_p2_SHIFT)) & DWC_DDRPHYA_MASTER_HWTMRL_P2_HwtMRL_p2_MASK)
16549/*! @} */
16550
16551/*! @name DQSPREAMBLECONTROL_P2 - Control the PHY logic related to the read and write DQS preamble */
16552/*! @{ */
16553#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckRxDqsPre_MASK (0x1U)
16554#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckRxDqsPre_SHIFT (0U)
16555#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckRxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckRxDqsPre_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckRxDqsPre_MASK)
16556#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckTxDqsPre_MASK (0x2U)
16557#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckTxDqsPre_SHIFT (1U)
16558#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckTxDqsPre_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckTxDqsPre_MASK)
16559#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_PositionDfeInit_MASK (0x1CU)
16560#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_PositionDfeInit_SHIFT (2U)
16561#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_PositionDfeInit(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_PositionDfeInit_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_PositionDfeInit_MASK)
16562#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TglTwoTckTxDqsPre_MASK (0x20U)
16563#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TglTwoTckTxDqsPre_SHIFT (5U)
16564#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TglTwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TglTwoTckTxDqsPre_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TglTwoTckTxDqsPre_MASK)
16565#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4PostambleExt_MASK (0x40U)
16566#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4PostambleExt_SHIFT (6U)
16567#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4PostambleExt(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4PostambleExt_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4PostambleExt_MASK)
16568#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4SttcPreBridgeRxEn_MASK (0x80U)
16569#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4SttcPreBridgeRxEn_SHIFT (7U)
16570#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4SttcPreBridgeRxEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4SttcPreBridgeRxEn_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4SttcPreBridgeRxEn_MASK)
16571#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_MASK (0x100U)
16572#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_SHIFT (8U)
16573#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_MASK)
16574/*! @} */
16575
16576/*! @name DMIPINPRESENT_P2 - This Register is used to enable the Read-DBI function in each DBYTE */
16577/*! @{ */
16578#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RdDbiEnabled_MASK (0x1U)
16579#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RdDbiEnabled_SHIFT (0U)
16580#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RdDbiEnabled(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RdDbiEnabled_SHIFT)) & DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RdDbiEnabled_MASK)
16581/*! @} */
16582
16583/*! @name ARDPTRINITVAL_P2 - Address/Command FIFO ReadPointer Initial Value */
16584/*! @{ */
16585#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARdPtrInitVal_p2_MASK (0xFU)
16586#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARdPtrInitVal_p2_SHIFT (0U)
16587#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARdPtrInitVal_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARdPtrInitVal_p2_SHIFT)) & DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARdPtrInitVal_p2_MASK)
16588/*! @} */
16589
16590/*! @name PROCODTTIMECTL_P2 - READ DATA On-Die Termination Timing Control (by PHY) */
16591/*! @{ */
16592#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtTailWidth_MASK (0x3U)
16593#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtTailWidth_SHIFT (0U)
16594#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtTailWidth(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtTailWidth_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtTailWidth_MASK)
16595#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtStartDelay_MASK (0xCU)
16596#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtStartDelay_SHIFT (2U)
16597#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtStartDelay(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtStartDelay_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtStartDelay_MASK)
16598/*! @} */
16599
16600/*! @name DLLGAINCTL_P2 - DLL gain control */
16601/*! @{ */
16602#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainIV_MASK (0xFU)
16603#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainIV_SHIFT (0U)
16604#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainIV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainIV_MASK)
16605#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainTV_MASK (0xF0U)
16606#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainTV_SHIFT (4U)
16607#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainTV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainTV_MASK)
16608#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllSeedSel_MASK (0xF00U)
16609#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllSeedSel_SHIFT (8U)
16610#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllSeedSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllSeedSel_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllSeedSel_MASK)
16611/*! @} */
16612
16613/*! @name DFIRDDATACSDESTMAP_P2 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
16614/*! @{ */
16615#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm0_MASK (0x3U)
16616#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm0_SHIFT (0U)
16617#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm0_MASK)
16618#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm1_MASK (0xCU)
16619#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm1_SHIFT (2U)
16620#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm1_MASK)
16621#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm2_MASK (0x30U)
16622#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm2_SHIFT (4U)
16623#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm2_MASK)
16624#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm3_MASK (0xC0U)
16625#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm3_SHIFT (6U)
16626#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm3_MASK)
16627/*! @} */
16628
16629/*! @name VREFINGLOBAL_P2 - PHY Global Vref Controls */
16630/*! @{ */
16631#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInSel_MASK (0x7U)
16632#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInSel_SHIFT (0U)
16633#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInSel_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInSel_MASK)
16634#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInDAC_MASK (0x3F8U)
16635#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInDAC_SHIFT (3U)
16636#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInDAC_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInDAC_MASK)
16637#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInTrim_MASK (0x3C00U)
16638#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInTrim_SHIFT (10U)
16639#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInTrim(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInTrim_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInTrim_MASK)
16640#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInMode_MASK (0x4000U)
16641#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInMode_SHIFT (14U)
16642#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInMode_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInMode_MASK)
16643/*! @} */
16644
16645/*! @name DFIWRDATACSDESTMAP_P2 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
16646/*! @{ */
16647#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm0_MASK (0x3U)
16648#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm0_SHIFT (0U)
16649#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm0_MASK)
16650#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm1_MASK (0xCU)
16651#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm1_SHIFT (2U)
16652#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm1_MASK)
16653#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm2_MASK (0x30U)
16654#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm2_SHIFT (4U)
16655#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm2_MASK)
16656#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm3_MASK (0xC0U)
16657#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm3_SHIFT (6U)
16658#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm3_MASK)
16659/*! @} */
16660
16661/*! @name PLLCTRL2_P2 - PState dependent PLL Control Register 2 */
16662/*! @{ */
16663#define DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PllFreqSel_MASK (0x1FU)
16664#define DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PllFreqSel_SHIFT (0U)
16665#define DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PllFreqSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PllFreqSel_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PllFreqSel_MASK)
16666/*! @} */
16667
16668/*! @name PLLCTRL1_P2 - PState dependent PLL Control Register 1 */
16669/*! @{ */
16670#define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpIntCtrl_MASK (0x1FU)
16671#define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpIntCtrl_SHIFT (0U)
16672#define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpIntCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpIntCtrl_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpIntCtrl_MASK)
16673#define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpPropCtrl_MASK (0x1E0U)
16674#define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpPropCtrl_SHIFT (5U)
16675#define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpPropCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpPropCtrl_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpPropCtrl_MASK)
16676/*! @} */
16677
16678/*! @name PLLTESTMODE_P2 - Additional controls for PLL CP/VCO modes of operation */
16679/*! @{ */
16680#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PllTestMode_p2_MASK (0xFFFFU)
16681#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PllTestMode_p2_SHIFT (0U)
16682#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PllTestMode_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PllTestMode_p2_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PllTestMode_p2_MASK)
16683/*! @} */
16684
16685/*! @name PLLCTRL4_P2 - PState dependent PLL Control Register 4 */
16686/*! @{ */
16687#define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpIntGsCtrl_MASK (0x1FU)
16688#define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpIntGsCtrl_SHIFT (0U)
16689#define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpIntGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpIntGsCtrl_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpIntGsCtrl_MASK)
16690#define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpPropGsCtrl_MASK (0x1E0U)
16691#define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpPropGsCtrl_SHIFT (5U)
16692#define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpPropGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpPropGsCtrl_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpPropGsCtrl_MASK)
16693/*! @} */
16694
16695/*! @name DFIFREQRATIO_P2 - DFI Frequency Ratio */
16696/*! @{ */
16697#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DfiFreqRatio_p2_MASK (0x3U)
16698#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DfiFreqRatio_p2_SHIFT (0U)
16699#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DfiFreqRatio_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DfiFreqRatio_p2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DfiFreqRatio_p2_MASK)
16700/*! @} */
16701
16702/*! @name CALUCLKINFO_P3 - Impedance Calibration Clock Ratio */
16703/*! @{ */
16704#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CalUClkTicksPer1uS_MASK (0x3FFU)
16705#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CalUClkTicksPer1uS_SHIFT (0U)
16706#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CalUClkTicksPer1uS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CalUClkTicksPer1uS_SHIFT)) & DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CalUClkTicksPer1uS_MASK)
16707/*! @} */
16708
16709/*! @name SEQ0BDLY0_P3 - PHY Initialization Engine (PIE) Delay Register 0 */
16710/*! @{ */
16711#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_Seq0BDLY0_p3_MASK (0xFFFFU)
16712#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_Seq0BDLY0_p3_SHIFT (0U)
16713#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_Seq0BDLY0_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_Seq0BDLY0_p3_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_Seq0BDLY0_p3_MASK)
16714/*! @} */
16715
16716/*! @name SEQ0BDLY1_P3 - PHY Initialization Engine (PIE) Delay Register 1 */
16717/*! @{ */
16718#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_Seq0BDLY1_p3_MASK (0xFFFFU)
16719#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_Seq0BDLY1_p3_SHIFT (0U)
16720#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_Seq0BDLY1_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_Seq0BDLY1_p3_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_Seq0BDLY1_p3_MASK)
16721/*! @} */
16722
16723/*! @name SEQ0BDLY2_P3 - PHY Initialization Engine (PIE) Delay Register 2 */
16724/*! @{ */
16725#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_Seq0BDLY2_p3_MASK (0xFFFFU)
16726#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_Seq0BDLY2_p3_SHIFT (0U)
16727#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_Seq0BDLY2_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_Seq0BDLY2_p3_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_Seq0BDLY2_p3_MASK)
16728/*! @} */
16729
16730/*! @name SEQ0BDLY3_P3 - PHY Initialization Engine (PIE) Delay Register 3 */
16731/*! @{ */
16732#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_Seq0BDLY3_p3_MASK (0xFFFFU)
16733#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_Seq0BDLY3_p3_SHIFT (0U)
16734#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_Seq0BDLY3_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_Seq0BDLY3_p3_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_Seq0BDLY3_p3_MASK)
16735/*! @} */
16736
16737/*! @name PPTTRAINSETUP_P3 - Setup Intervals for DFI PHY Master operations */
16738/*! @{ */
16739#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrTrainInterval_MASK (0xFU)
16740#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrTrainInterval_SHIFT (0U)
16741#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrTrainInterval(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrTrainInterval_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrTrainInterval_MASK)
16742#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrMaxReqToAck_MASK (0x70U)
16743#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrMaxReqToAck_SHIFT (4U)
16744#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrMaxReqToAck(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrMaxReqToAck_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrMaxReqToAck_MASK)
16745/*! @} */
16746
16747/*! @name TRISTATEMODECA_P3 - Mode select register for MEMCLK/Address/Command Tristates */
16748/*! @{ */
16749#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DisDynAdrTri_MASK (0x1U)
16750#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DisDynAdrTri_SHIFT (0U)
16751#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DisDynAdrTri(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DisDynAdrTri_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DisDynAdrTri_MASK)
16752#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMode_MASK (0x2U)
16753#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMode_SHIFT (1U)
16754#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMode_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMode_MASK)
16755#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CkDisVal_MASK (0xCU)
16756#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CkDisVal_SHIFT (2U)
16757#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CkDisVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CkDisVal_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CkDisVal_MASK)
16758/*! @} */
16759
16760/*! @name HWTMRL_P3 - HWT MaxReadLatency. */
16761/*! @{ */
16762#define DWC_DDRPHYA_MASTER_HWTMRL_P3_HwtMRL_p3_MASK (0x1FU)
16763#define DWC_DDRPHYA_MASTER_HWTMRL_P3_HwtMRL_p3_SHIFT (0U)
16764#define DWC_DDRPHYA_MASTER_HWTMRL_P3_HwtMRL_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P3_HwtMRL_p3_SHIFT)) & DWC_DDRPHYA_MASTER_HWTMRL_P3_HwtMRL_p3_MASK)
16765/*! @} */
16766
16767/*! @name DQSPREAMBLECONTROL_P3 - Control the PHY logic related to the read and write DQS preamble */
16768/*! @{ */
16769#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckRxDqsPre_MASK (0x1U)
16770#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckRxDqsPre_SHIFT (0U)
16771#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckRxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckRxDqsPre_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckRxDqsPre_MASK)
16772#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckTxDqsPre_MASK (0x2U)
16773#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckTxDqsPre_SHIFT (1U)
16774#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckTxDqsPre_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckTxDqsPre_MASK)
16775#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_PositionDfeInit_MASK (0x1CU)
16776#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_PositionDfeInit_SHIFT (2U)
16777#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_PositionDfeInit(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_PositionDfeInit_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_PositionDfeInit_MASK)
16778#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TglTwoTckTxDqsPre_MASK (0x20U)
16779#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TglTwoTckTxDqsPre_SHIFT (5U)
16780#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TglTwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TglTwoTckTxDqsPre_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TglTwoTckTxDqsPre_MASK)
16781#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4PostambleExt_MASK (0x40U)
16782#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4PostambleExt_SHIFT (6U)
16783#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4PostambleExt(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4PostambleExt_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4PostambleExt_MASK)
16784#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4SttcPreBridgeRxEn_MASK (0x80U)
16785#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4SttcPreBridgeRxEn_SHIFT (7U)
16786#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4SttcPreBridgeRxEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4SttcPreBridgeRxEn_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4SttcPreBridgeRxEn_MASK)
16787#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_MASK (0x100U)
16788#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_SHIFT (8U)
16789#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_MASK)
16790/*! @} */
16791
16792/*! @name DMIPINPRESENT_P3 - This Register is used to enable the Read-DBI function in each DBYTE */
16793/*! @{ */
16794#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RdDbiEnabled_MASK (0x1U)
16795#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RdDbiEnabled_SHIFT (0U)
16796#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RdDbiEnabled(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RdDbiEnabled_SHIFT)) & DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RdDbiEnabled_MASK)
16797/*! @} */
16798
16799/*! @name ARDPTRINITVAL_P3 - Address/Command FIFO ReadPointer Initial Value */
16800/*! @{ */
16801#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARdPtrInitVal_p3_MASK (0xFU)
16802#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARdPtrInitVal_p3_SHIFT (0U)
16803#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARdPtrInitVal_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARdPtrInitVal_p3_SHIFT)) & DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARdPtrInitVal_p3_MASK)
16804/*! @} */
16805
16806/*! @name PROCODTTIMECTL_P3 - READ DATA On-Die Termination Timing Control (by PHY) */
16807/*! @{ */
16808#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtTailWidth_MASK (0x3U)
16809#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtTailWidth_SHIFT (0U)
16810#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtTailWidth(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtTailWidth_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtTailWidth_MASK)
16811#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtStartDelay_MASK (0xCU)
16812#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtStartDelay_SHIFT (2U)
16813#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtStartDelay(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtStartDelay_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtStartDelay_MASK)
16814/*! @} */
16815
16816/*! @name DLLGAINCTL_P3 - DLL gain control */
16817/*! @{ */
16818#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainIV_MASK (0xFU)
16819#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainIV_SHIFT (0U)
16820#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainIV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainIV_MASK)
16821#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainTV_MASK (0xF0U)
16822#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainTV_SHIFT (4U)
16823#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainTV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainTV_MASK)
16824#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllSeedSel_MASK (0xF00U)
16825#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllSeedSel_SHIFT (8U)
16826#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllSeedSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllSeedSel_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllSeedSel_MASK)
16827/*! @} */
16828
16829/*! @name DFIRDDATACSDESTMAP_P3 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
16830/*! @{ */
16831#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm0_MASK (0x3U)
16832#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm0_SHIFT (0U)
16833#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm0_MASK)
16834#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm1_MASK (0xCU)
16835#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm1_SHIFT (2U)
16836#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm1_MASK)
16837#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm2_MASK (0x30U)
16838#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm2_SHIFT (4U)
16839#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm2_MASK)
16840#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm3_MASK (0xC0U)
16841#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm3_SHIFT (6U)
16842#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm3_MASK)
16843/*! @} */
16844
16845/*! @name VREFINGLOBAL_P3 - PHY Global Vref Controls */
16846/*! @{ */
16847#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInSel_MASK (0x7U)
16848#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInSel_SHIFT (0U)
16849#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInSel_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInSel_MASK)
16850#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInDAC_MASK (0x3F8U)
16851#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInDAC_SHIFT (3U)
16852#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInDAC_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInDAC_MASK)
16853#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInTrim_MASK (0x3C00U)
16854#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInTrim_SHIFT (10U)
16855#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInTrim(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInTrim_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInTrim_MASK)
16856#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInMode_MASK (0x4000U)
16857#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInMode_SHIFT (14U)
16858#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInMode_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInMode_MASK)
16859/*! @} */
16860
16861/*! @name DFIWRDATACSDESTMAP_P3 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
16862/*! @{ */
16863#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm0_MASK (0x3U)
16864#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm0_SHIFT (0U)
16865#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm0_MASK)
16866#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm1_MASK (0xCU)
16867#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm1_SHIFT (2U)
16868#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm1_MASK)
16869#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm2_MASK (0x30U)
16870#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm2_SHIFT (4U)
16871#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm2_MASK)
16872#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm3_MASK (0xC0U)
16873#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm3_SHIFT (6U)
16874#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm3_MASK)
16875/*! @} */
16876
16877/*! @name PLLCTRL2_P3 - PState dependent PLL Control Register 2 */
16878/*! @{ */
16879#define DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PllFreqSel_MASK (0x1FU)
16880#define DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PllFreqSel_SHIFT (0U)
16881#define DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PllFreqSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PllFreqSel_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PllFreqSel_MASK)
16882/*! @} */
16883
16884/*! @name PLLCTRL1_P3 - PState dependent PLL Control Register 1 */
16885/*! @{ */
16886#define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpIntCtrl_MASK (0x1FU)
16887#define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpIntCtrl_SHIFT (0U)
16888#define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpIntCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpIntCtrl_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpIntCtrl_MASK)
16889#define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpPropCtrl_MASK (0x1E0U)
16890#define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpPropCtrl_SHIFT (5U)
16891#define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpPropCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpPropCtrl_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpPropCtrl_MASK)
16892/*! @} */
16893
16894/*! @name PLLTESTMODE_P3 - Additional controls for PLL CP/VCO modes of operation */
16895/*! @{ */
16896#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PllTestMode_p3_MASK (0xFFFFU)
16897#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PllTestMode_p3_SHIFT (0U)
16898#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PllTestMode_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PllTestMode_p3_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PllTestMode_p3_MASK)
16899/*! @} */
16900
16901/*! @name PLLCTRL4_P3 - PState dependent PLL Control Register 4 */
16902/*! @{ */
16903#define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpIntGsCtrl_MASK (0x1FU)
16904#define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpIntGsCtrl_SHIFT (0U)
16905#define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpIntGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpIntGsCtrl_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpIntGsCtrl_MASK)
16906#define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpPropGsCtrl_MASK (0x1E0U)
16907#define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpPropGsCtrl_SHIFT (5U)
16908#define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpPropGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpPropGsCtrl_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpPropGsCtrl_MASK)
16909/*! @} */
16910
16911/*! @name DFIFREQRATIO_P3 - DFI Frequency Ratio */
16912/*! @{ */
16913#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DfiFreqRatio_p3_MASK (0x3U)
16914#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DfiFreqRatio_p3_SHIFT (0U)
16915#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DfiFreqRatio_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DfiFreqRatio_p3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DfiFreqRatio_p3_MASK)
16916/*! @} */
16917
16918
16919/*!
16920 * @}
16921 */ /* end of group DWC_DDRPHYA_MASTER_Register_Masks */
16922
16923
16924/* DWC_DDRPHYA_MASTER - Peripheral instance base addresses */
16925/** Peripheral DWC_DDRPHYA_MASTER0 base address */
16926#define DWC_DDRPHYA_MASTER0_BASE (0x3C020000u)
16927/** Peripheral DWC_DDRPHYA_MASTER0 base pointer */
16928#define DWC_DDRPHYA_MASTER0 ((DWC_DDRPHYA_MASTER_Type *)DWC_DDRPHYA_MASTER0_BASE)
16929/** Array initializer of DWC_DDRPHYA_MASTER peripheral base addresses */
16930#define DWC_DDRPHYA_MASTER_BASE_ADDRS { DWC_DDRPHYA_MASTER0_BASE }
16931/** Array initializer of DWC_DDRPHYA_MASTER peripheral base pointers */
16932#define DWC_DDRPHYA_MASTER_BASE_PTRS { DWC_DDRPHYA_MASTER0 }
16933
16934/*!
16935 * @}
16936 */ /* end of group DWC_DDRPHYA_MASTER_Peripheral_Access_Layer */
16937
16938
16939/* ----------------------------------------------------------------------------
16940 -- ECSPI Peripheral Access Layer
16941 ---------------------------------------------------------------------------- */
16942
16943/*!
16944 * @addtogroup ECSPI_Peripheral_Access_Layer ECSPI Peripheral Access Layer
16945 * @{
16946 */
16947
16948/** ECSPI - Register Layout Typedef */
16949typedef struct {
16950 __I uint32_t RXDATA; /**< Receive Data Register, offset: 0x0 */
16951 __O uint32_t TXDATA; /**< Transmit Data Register, offset: 0x4 */
16952 __IO uint32_t CONREG; /**< Control Register, offset: 0x8 */
16953 __IO uint32_t CONFIGREG; /**< Config Register, offset: 0xC */
16954 __IO uint32_t INTREG; /**< Interrupt Control Register, offset: 0x10 */
16955 __IO uint32_t DMAREG; /**< DMA Control Register, offset: 0x14 */
16956 __IO uint32_t STATREG; /**< Status Register, offset: 0x18 */
16957 __IO uint32_t PERIODREG; /**< Sample Period Control Register, offset: 0x1C */
16958 __IO uint32_t TESTREG; /**< Test Control Register, offset: 0x20 */
16959 uint8_t RESERVED_0[28];
16960 __O uint32_t MSGDATA; /**< Message Data Register, offset: 0x40 */
16961} ECSPI_Type;
16962
16963/* ----------------------------------------------------------------------------
16964 -- ECSPI Register Masks
16965 ---------------------------------------------------------------------------- */
16966
16967/*!
16968 * @addtogroup ECSPI_Register_Masks ECSPI Register Masks
16969 * @{
16970 */
16971
16972/*! @name RXDATA - Receive Data Register */
16973/*! @{ */
16974#define ECSPI_RXDATA_ECSPI_RXDATA_MASK (0xFFFFFFFFU)
16975#define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT (0U)
16976#define ECSPI_RXDATA_ECSPI_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_RXDATA_ECSPI_RXDATA_SHIFT)) & ECSPI_RXDATA_ECSPI_RXDATA_MASK)
16977/*! @} */
16978
16979/*! @name TXDATA - Transmit Data Register */
16980/*! @{ */
16981#define ECSPI_TXDATA_ECSPI_TXDATA_MASK (0xFFFFFFFFU)
16982#define ECSPI_TXDATA_ECSPI_TXDATA_SHIFT (0U)
16983#define ECSPI_TXDATA_ECSPI_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TXDATA_ECSPI_TXDATA_SHIFT)) & ECSPI_TXDATA_ECSPI_TXDATA_MASK)
16984/*! @} */
16985
16986/*! @name CONREG - Control Register */
16987/*! @{ */
16988#define ECSPI_CONREG_EN_MASK (0x1U)
16989#define ECSPI_CONREG_EN_SHIFT (0U)
16990/*! EN
16991 * 0b0..Disable the block.
16992 * 0b1..Enable the block.
16993 */
16994#define ECSPI_CONREG_EN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_EN_SHIFT)) & ECSPI_CONREG_EN_MASK)
16995#define ECSPI_CONREG_HT_MASK (0x2U)
16996#define ECSPI_CONREG_HT_SHIFT (1U)
16997/*! HT
16998 * 0b0..Disable HT mode.
16999 * 0b1..Enable HT mode.
17000 */
17001#define ECSPI_CONREG_HT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_HT_SHIFT)) & ECSPI_CONREG_HT_MASK)
17002#define ECSPI_CONREG_XCH_MASK (0x4U)
17003#define ECSPI_CONREG_XCH_SHIFT (2U)
17004/*! XCH
17005 * 0b0..Idle.
17006 * 0b1..Initiates exchange (write) or busy (read).
17007 */
17008#define ECSPI_CONREG_XCH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_XCH_SHIFT)) & ECSPI_CONREG_XCH_MASK)
17009#define ECSPI_CONREG_SMC_MASK (0x8U)
17010#define ECSPI_CONREG_SMC_SHIFT (3U)
17011/*! SMC
17012 * 0b0..SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst or
17013 * multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer to XCH and SS_CTL
17014 * descriptions.
17015 * 0b1..Immediately starts a SPI burst when data is written in TXFIFO.
17016 */
17017#define ECSPI_CONREG_SMC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_SMC_SHIFT)) & ECSPI_CONREG_SMC_MASK)
17018#define ECSPI_CONREG_CHANNEL_MODE_MASK (0xF0U)
17019#define ECSPI_CONREG_CHANNEL_MODE_SHIFT (4U)
17020/*! CHANNEL_MODE
17021 * 0b0000..Slave mode.
17022 * 0b0001..Master mode.
17023 */
17024#define ECSPI_CONREG_CHANNEL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_MODE_SHIFT)) & ECSPI_CONREG_CHANNEL_MODE_MASK)
17025#define ECSPI_CONREG_POST_DIVIDER_MASK (0xF00U)
17026#define ECSPI_CONREG_POST_DIVIDER_SHIFT (8U)
17027/*! POST_DIVIDER
17028 * 0b0000..Divide by 1.
17029 * 0b0001..Divide by 2.
17030 * 0b0010..Divide by 4.
17031 * 0b1110..Divide by 2 14 .
17032 * 0b1111..Divide by 2 15 .
17033 */
17034#define ECSPI_CONREG_POST_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_POST_DIVIDER_SHIFT)) & ECSPI_CONREG_POST_DIVIDER_MASK)
17035#define ECSPI_CONREG_PRE_DIVIDER_MASK (0xF000U)
17036#define ECSPI_CONREG_PRE_DIVIDER_SHIFT (12U)
17037/*! PRE_DIVIDER
17038 * 0b0000..Divide by 1.
17039 * 0b0001..Divide by 2.
17040 * 0b0010..Divide by 3.
17041 * 0b1101..Divide by 14.
17042 * 0b1110..Divide by 15.
17043 * 0b1111..Divide by 16.
17044 */
17045#define ECSPI_CONREG_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_PRE_DIVIDER_SHIFT)) & ECSPI_CONREG_PRE_DIVIDER_MASK)
17046#define ECSPI_CONREG_DRCTL_MASK (0x30000U)
17047#define ECSPI_CONREG_DRCTL_SHIFT (16U)
17048/*! DRCTL
17049 * 0b00..The SPI_RDY signal is a don't care.
17050 * 0b01..Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered).
17051 * 0b10..Burst will be triggered by a low level of the SPI_RDY signal (level-triggered).
17052 * 0b11..Reserved.
17053 */
17054#define ECSPI_CONREG_DRCTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_DRCTL_SHIFT)) & ECSPI_CONREG_DRCTL_MASK)
17055#define ECSPI_CONREG_CHANNEL_SELECT_MASK (0xC0000U)
17056#define ECSPI_CONREG_CHANNEL_SELECT_SHIFT (18U)
17057/*! CHANNEL_SELECT
17058 * 0b00..Channel 0 is selected. Chip Select 0 (SS0) will be asserted.
17059 * 0b01..Channel 1 is selected. Chip Select 1 (SS1) will be asserted.
17060 * 0b10..Channel 2 is selected. Chip Select 2 (SS2) will be asserted.
17061 * 0b11..Channel 3 is selected. Chip Select 3 (SS3) will be asserted.
17062 */
17063#define ECSPI_CONREG_CHANNEL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_SELECT_SHIFT)) & ECSPI_CONREG_CHANNEL_SELECT_MASK)
17064#define ECSPI_CONREG_BURST_LENGTH_MASK (0xFFF00000U)
17065#define ECSPI_CONREG_BURST_LENGTH_SHIFT (20U)
17066/*! BURST_LENGTH
17067 * 0b000000000000..A SPI burst contains the 1 LSB in a word.
17068 * 0b000000000001..A SPI burst contains the 2 LSB in a word.
17069 * 0b000000000010..A SPI burst contains the 3 LSB in a word.
17070 * 0b000000011111..A SPI burst contains all 32 bits in a word.
17071 * 0b000000100000..A SPI burst contains the 1 LSB in first word and all 32 bits in second word.
17072 * 0b000000100001..A SPI burst contains the 2 LSB in first word and all 32 bits in second word.
17073 * 0b111111111110..A SPI burst contains the 31 LSB in first word and 2^7 -1 words.
17074 * 0b111111111111..A SPI burst contains 2^7 words.
17075 */
17076#define ECSPI_CONREG_BURST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_BURST_LENGTH_SHIFT)) & ECSPI_CONREG_BURST_LENGTH_MASK)
17077/*! @} */
17078
17079/*! @name CONFIGREG - Config Register */
17080/*! @{ */
17081#define ECSPI_CONFIGREG_SCLK_PHA_MASK (0xFU)
17082#define ECSPI_CONFIGREG_SCLK_PHA_SHIFT (0U)
17083/*! SCLK_PHA
17084 * 0b0000..Phase 0 operation.
17085 * 0b0001..Phase 1 operation.
17086 */
17087#define ECSPI_CONFIGREG_SCLK_PHA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_PHA_SHIFT)) & ECSPI_CONFIGREG_SCLK_PHA_MASK)
17088#define ECSPI_CONFIGREG_SCLK_POL_MASK (0xF0U)
17089#define ECSPI_CONFIGREG_SCLK_POL_SHIFT (4U)
17090/*! SCLK_POL
17091 * 0b0000..Active high polarity (0 = Idle).
17092 * 0b0001..Active low polarity (1 = Idle).
17093 */
17094#define ECSPI_CONFIGREG_SCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_POL_SHIFT)) & ECSPI_CONFIGREG_SCLK_POL_MASK)
17095#define ECSPI_CONFIGREG_SS_CTL_MASK (0xF00U)
17096#define ECSPI_CONFIGREG_SS_CTL_SHIFT (8U)
17097/*! SS_CTL
17098 * 0b0000..In master mode - only one SPI burst will be transmitted.
17099 * 0b0001..In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be
17100 * transmitted. The SPI transfer will automatically stop when the TXFIFO is empty.
17101 * 0b0000..In slave mode - an SPI burst is completed when the number of bits received in the shift register is
17102 * equal to (BURST LENGTH + 1). Only the n least-significant bits (n = BURST LENGTH[4:0] + 1) of the first
17103 * received word are valid. All bits subsequent to the first received word in RXFIFO are valid.
17104 * 0b0001..Reserved
17105 */
17106#define ECSPI_CONFIGREG_SS_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_CTL_SHIFT)) & ECSPI_CONFIGREG_SS_CTL_MASK)
17107#define ECSPI_CONFIGREG_SS_POL_MASK (0xF000U)
17108#define ECSPI_CONFIGREG_SS_POL_SHIFT (12U)
17109/*! SS_POL
17110 * 0b0000..Active low.
17111 * 0b0001..Active high.
17112 */
17113#define ECSPI_CONFIGREG_SS_POL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_POL_SHIFT)) & ECSPI_CONFIGREG_SS_POL_MASK)
17114#define ECSPI_CONFIGREG_DATA_CTL_MASK (0xF0000U)
17115#define ECSPI_CONFIGREG_DATA_CTL_SHIFT (16U)
17116/*! DATA_CTL
17117 * 0b0000..Stay high.
17118 * 0b0001..Stay low.
17119 */
17120#define ECSPI_CONFIGREG_DATA_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_DATA_CTL_SHIFT)) & ECSPI_CONFIGREG_DATA_CTL_MASK)
17121#define ECSPI_CONFIGREG_SCLK_CTL_MASK (0xF00000U)
17122#define ECSPI_CONFIGREG_SCLK_CTL_SHIFT (20U)
17123/*! SCLK_CTL
17124 * 0b0000..Stay low.
17125 * 0b0001..Stay high.
17126 */
17127#define ECSPI_CONFIGREG_SCLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_CTL_SHIFT)) & ECSPI_CONFIGREG_SCLK_CTL_MASK)
17128#define ECSPI_CONFIGREG_HT_LENGTH_MASK (0x1F000000U)
17129#define ECSPI_CONFIGREG_HT_LENGTH_SHIFT (24U)
17130#define ECSPI_CONFIGREG_HT_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_HT_LENGTH_SHIFT)) & ECSPI_CONFIGREG_HT_LENGTH_MASK)
17131/*! @} */
17132
17133/*! @name INTREG - Interrupt Control Register */
17134/*! @{ */
17135#define ECSPI_INTREG_TEEN_MASK (0x1U)
17136#define ECSPI_INTREG_TEEN_SHIFT (0U)
17137/*! TEEN
17138 * 0b0..Disable
17139 * 0b1..Enable
17140 */
17141#define ECSPI_INTREG_TEEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TEEN_SHIFT)) & ECSPI_INTREG_TEEN_MASK)
17142#define ECSPI_INTREG_TDREN_MASK (0x2U)
17143#define ECSPI_INTREG_TDREN_SHIFT (1U)
17144/*! TDREN
17145 * 0b0..Disable
17146 * 0b1..Enable
17147 */
17148#define ECSPI_INTREG_TDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TDREN_SHIFT)) & ECSPI_INTREG_TDREN_MASK)
17149#define ECSPI_INTREG_TFEN_MASK (0x4U)
17150#define ECSPI_INTREG_TFEN_SHIFT (2U)
17151/*! TFEN
17152 * 0b0..Disable
17153 * 0b1..Enable
17154 */
17155#define ECSPI_INTREG_TFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TFEN_SHIFT)) & ECSPI_INTREG_TFEN_MASK)
17156#define ECSPI_INTREG_RREN_MASK (0x8U)
17157#define ECSPI_INTREG_RREN_SHIFT (3U)
17158/*! RREN
17159 * 0b0..Disable
17160 * 0b1..Enable
17161 */
17162#define ECSPI_INTREG_RREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RREN_SHIFT)) & ECSPI_INTREG_RREN_MASK)
17163#define ECSPI_INTREG_RDREN_MASK (0x10U)
17164#define ECSPI_INTREG_RDREN_SHIFT (4U)
17165/*! RDREN
17166 * 0b0..Disable
17167 * 0b1..Enable
17168 */
17169#define ECSPI_INTREG_RDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RDREN_SHIFT)) & ECSPI_INTREG_RDREN_MASK)
17170#define ECSPI_INTREG_RFEN_MASK (0x20U)
17171#define ECSPI_INTREG_RFEN_SHIFT (5U)
17172/*! RFEN
17173 * 0b0..Disable
17174 * 0b1..Enable
17175 */
17176#define ECSPI_INTREG_RFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RFEN_SHIFT)) & ECSPI_INTREG_RFEN_MASK)
17177#define ECSPI_INTREG_ROEN_MASK (0x40U)
17178#define ECSPI_INTREG_ROEN_SHIFT (6U)
17179/*! ROEN
17180 * 0b0..Disable
17181 * 0b1..Enable
17182 */
17183#define ECSPI_INTREG_ROEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_ROEN_SHIFT)) & ECSPI_INTREG_ROEN_MASK)
17184#define ECSPI_INTREG_TCEN_MASK (0x80U)
17185#define ECSPI_INTREG_TCEN_SHIFT (7U)
17186/*! TCEN
17187 * 0b0..Disable
17188 * 0b1..Enable
17189 */
17190#define ECSPI_INTREG_TCEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TCEN_SHIFT)) & ECSPI_INTREG_TCEN_MASK)
17191/*! @} */
17192
17193/*! @name DMAREG - DMA Control Register */
17194/*! @{ */
17195#define ECSPI_DMAREG_TX_THRESHOLD_MASK (0x3FU)
17196#define ECSPI_DMAREG_TX_THRESHOLD_SHIFT (0U)
17197#define ECSPI_DMAREG_TX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_TX_THRESHOLD_MASK)
17198#define ECSPI_DMAREG_TEDEN_MASK (0x80U)
17199#define ECSPI_DMAREG_TEDEN_SHIFT (7U)
17200/*! TEDEN
17201 * 0b0..Disable
17202 * 0b1..Enable
17203 */
17204#define ECSPI_DMAREG_TEDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TEDEN_SHIFT)) & ECSPI_DMAREG_TEDEN_MASK)
17205#define ECSPI_DMAREG_RX_THRESHOLD_MASK (0x3F0000U)
17206#define ECSPI_DMAREG_RX_THRESHOLD_SHIFT (16U)
17207#define ECSPI_DMAREG_RX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_RX_THRESHOLD_MASK)
17208#define ECSPI_DMAREG_RXDEN_MASK (0x800000U)
17209#define ECSPI_DMAREG_RXDEN_SHIFT (23U)
17210/*! RXDEN
17211 * 0b0..Disable
17212 * 0b1..Enable
17213 */
17214#define ECSPI_DMAREG_RXDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXDEN_SHIFT)) & ECSPI_DMAREG_RXDEN_MASK)
17215#define ECSPI_DMAREG_RX_DMA_LENGTH_MASK (0x3F000000U)
17216#define ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT (24U)
17217#define ECSPI_DMAREG_RX_DMA_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT)) & ECSPI_DMAREG_RX_DMA_LENGTH_MASK)
17218#define ECSPI_DMAREG_RXTDEN_MASK (0x80000000U)
17219#define ECSPI_DMAREG_RXTDEN_SHIFT (31U)
17220/*! RXTDEN
17221 * 0b0..Disable
17222 * 0b1..Enable
17223 */
17224#define ECSPI_DMAREG_RXTDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXTDEN_SHIFT)) & ECSPI_DMAREG_RXTDEN_MASK)
17225/*! @} */
17226
17227/*! @name STATREG - Status Register */
17228/*! @{ */
17229#define ECSPI_STATREG_TE_MASK (0x1U)
17230#define ECSPI_STATREG_TE_SHIFT (0U)
17231/*! TE
17232 * 0b0..TXFIFO contains one or more words.
17233 * 0b1..TXFIFO is empty.
17234 */
17235#define ECSPI_STATREG_TE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TE_SHIFT)) & ECSPI_STATREG_TE_MASK)
17236#define ECSPI_STATREG_TDR_MASK (0x2U)
17237#define ECSPI_STATREG_TDR_SHIFT (1U)
17238/*! TDR
17239 * 0b0..Number of valid data slots in TXFIFO is greater than TX_THRESHOLD.
17240 * 0b1..Number of valid data slots in TXFIFO is not greater than TX_THRESHOLD.
17241 */
17242#define ECSPI_STATREG_TDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TDR_SHIFT)) & ECSPI_STATREG_TDR_MASK)
17243#define ECSPI_STATREG_TF_MASK (0x4U)
17244#define ECSPI_STATREG_TF_SHIFT (2U)
17245/*! TF
17246 * 0b0..TXFIFO is not Full.
17247 * 0b1..TXFIFO is Full.
17248 */
17249#define ECSPI_STATREG_TF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TF_SHIFT)) & ECSPI_STATREG_TF_MASK)
17250#define ECSPI_STATREG_RR_MASK (0x8U)
17251#define ECSPI_STATREG_RR_SHIFT (3U)
17252/*! RR
17253 * 0b0..No valid data in RXFIFO.
17254 * 0b1..More than 1 word in RXFIFO.
17255 */
17256#define ECSPI_STATREG_RR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RR_SHIFT)) & ECSPI_STATREG_RR_MASK)
17257#define ECSPI_STATREG_RDR_MASK (0x10U)
17258#define ECSPI_STATREG_RDR_SHIFT (4U)
17259/*! RDR
17260 * 0b0..When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD.
17261 * 0b1..When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a DMA TAIL DMA condition exists.
17262 * 0b0..When RXTDE is clear - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD.
17263 * 0b1..When RXTDE is clear - Number of data entries in the RXFIFO is greater than RX_THRESHOLD.
17264 */
17265#define ECSPI_STATREG_RDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RDR_SHIFT)) & ECSPI_STATREG_RDR_MASK)
17266#define ECSPI_STATREG_RF_MASK (0x20U)
17267#define ECSPI_STATREG_RF_SHIFT (5U)
17268/*! RF
17269 * 0b0..Not Full.
17270 * 0b1..Full.
17271 */
17272#define ECSPI_STATREG_RF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RF_SHIFT)) & ECSPI_STATREG_RF_MASK)
17273#define ECSPI_STATREG_RO_MASK (0x40U)
17274#define ECSPI_STATREG_RO_SHIFT (6U)
17275/*! RO
17276 * 0b0..RXFIFO has no overflow.
17277 * 0b1..RXFIFO has overflowed.
17278 */
17279#define ECSPI_STATREG_RO(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RO_SHIFT)) & ECSPI_STATREG_RO_MASK)
17280#define ECSPI_STATREG_TC_MASK (0x80U)
17281#define ECSPI_STATREG_TC_SHIFT (7U)
17282/*! TC
17283 * 0b0..Transfer in progress.
17284 * 0b1..Transfer completed.
17285 */
17286#define ECSPI_STATREG_TC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TC_SHIFT)) & ECSPI_STATREG_TC_MASK)
17287/*! @} */
17288
17289/*! @name PERIODREG - Sample Period Control Register */
17290/*! @{ */
17291#define ECSPI_PERIODREG_SAMPLE_PERIOD_MASK (0x7FFFU)
17292#define ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT (0U)
17293/*! SAMPLE_PERIOD
17294 * 0b000000000000000..0 wait states inserted
17295 * 0b000000000000001..1 wait state inserted
17296 * 0b111111111111110..32766 wait states inserted
17297 * 0b111111111111111..32767 wait states inserted
17298 */
17299#define ECSPI_PERIODREG_SAMPLE_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT)) & ECSPI_PERIODREG_SAMPLE_PERIOD_MASK)
17300#define ECSPI_PERIODREG_CSRC_MASK (0x8000U)
17301#define ECSPI_PERIODREG_CSRC_SHIFT (15U)
17302/*! CSRC
17303 * 0b0..SPI Clock (SCLK)
17304 * 0b1..Low-Frequency Reference Clock (32.768 KHz)
17305 */
17306#define ECSPI_PERIODREG_CSRC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSRC_SHIFT)) & ECSPI_PERIODREG_CSRC_MASK)
17307#define ECSPI_PERIODREG_CSD_CTL_MASK (0x3F0000U)
17308#define ECSPI_PERIODREG_CSD_CTL_SHIFT (16U)
17309#define ECSPI_PERIODREG_CSD_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSD_CTL_SHIFT)) & ECSPI_PERIODREG_CSD_CTL_MASK)
17310/*! @} */
17311
17312/*! @name TESTREG - Test Control Register */
17313/*! @{ */
17314#define ECSPI_TESTREG_TXCNT_MASK (0x7FU)
17315#define ECSPI_TESTREG_TXCNT_SHIFT (0U)
17316#define ECSPI_TESTREG_TXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_TXCNT_SHIFT)) & ECSPI_TESTREG_TXCNT_MASK)
17317#define ECSPI_TESTREG_RXCNT_MASK (0x7F00U)
17318#define ECSPI_TESTREG_RXCNT_SHIFT (8U)
17319#define ECSPI_TESTREG_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_RXCNT_SHIFT)) & ECSPI_TESTREG_RXCNT_MASK)
17320#define ECSPI_TESTREG_LBC_MASK (0x80000000U)
17321#define ECSPI_TESTREG_LBC_SHIFT (31U)
17322/*! LBC
17323 * 0b0..Not connected.
17324 * 0b1..Transmitter and receiver sections internally connected for Loopback.
17325 */
17326#define ECSPI_TESTREG_LBC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_LBC_SHIFT)) & ECSPI_TESTREG_LBC_MASK)
17327/*! @} */
17328
17329/*! @name MSGDATA - Message Data Register */
17330/*! @{ */
17331#define ECSPI_MSGDATA_ECSPI_MSGDATA_MASK (0xFFFFFFFFU)
17332#define ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT (0U)
17333#define ECSPI_MSGDATA_ECSPI_MSGDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT)) & ECSPI_MSGDATA_ECSPI_MSGDATA_MASK)
17334/*! @} */
17335
17336
17337/*!
17338 * @}
17339 */ /* end of group ECSPI_Register_Masks */
17340
17341
17342/* ECSPI - Peripheral instance base addresses */
17343/** Peripheral ECSPI1 base address */
17344#define ECSPI1_BASE (0x30820000u)
17345/** Peripheral ECSPI1 base pointer */
17346#define ECSPI1 ((ECSPI_Type *)ECSPI1_BASE)
17347/** Peripheral ECSPI2 base address */
17348#define ECSPI2_BASE (0x30830000u)
17349/** Peripheral ECSPI2 base pointer */
17350#define ECSPI2 ((ECSPI_Type *)ECSPI2_BASE)
17351/** Peripheral ECSPI3 base address */
17352#define ECSPI3_BASE (0x30840000u)
17353/** Peripheral ECSPI3 base pointer */
17354#define ECSPI3 ((ECSPI_Type *)ECSPI3_BASE)
17355/** Array initializer of ECSPI peripheral base addresses */
17356#define ECSPI_BASE_ADDRS { 0u, ECSPI1_BASE, ECSPI2_BASE, ECSPI3_BASE }
17357/** Array initializer of ECSPI peripheral base pointers */
17358#define ECSPI_BASE_PTRS { (ECSPI_Type *)0u, ECSPI1, ECSPI2, ECSPI3 }
17359/** Interrupt vectors for the ECSPI peripheral type */
17360#define ECSPI_IRQS { NotAvail_IRQn, ECSPI1_IRQn, ECSPI2_IRQn, ECSPI3_IRQn }
17361
17362/*!
17363 * @}
17364 */ /* end of group ECSPI_Peripheral_Access_Layer */
17365
17366
17367/* ----------------------------------------------------------------------------
17368 -- ENET Peripheral Access Layer
17369 ---------------------------------------------------------------------------- */
17370
17371/*!
17372 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
17373 * @{
17374 */
17375
17376/** ENET - Register Layout Typedef */
17377typedef struct {
17378 uint8_t RESERVED_0[4];
17379 __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
17380 __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
17381 uint8_t RESERVED_1[4];
17382 __IO uint32_t RDAR; /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */
17383 __IO uint32_t TDAR; /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */
17384 uint8_t RESERVED_2[12];
17385 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
17386 uint8_t RESERVED_3[24];
17387 __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
17388 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
17389 uint8_t RESERVED_4[28];
17390 __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
17391 uint8_t RESERVED_5[28];
17392 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
17393 uint8_t RESERVED_6[60];
17394 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
17395 uint8_t RESERVED_7[28];
17396 __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
17397 __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
17398 __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
17399 __IO uint32_t TXIC[3]; /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */
17400 uint8_t RESERVED_8[4];
17401 __IO uint32_t RXIC[3]; /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */
17402 uint8_t RESERVED_9[12];
17403 __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
17404 __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
17405 __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
17406 __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
17407 uint8_t RESERVED_10[28];
17408 __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
17409 uint8_t RESERVED_11[24];
17410 __IO uint32_t RDSR1; /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */
17411 __IO uint32_t TDSR1; /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */
17412 __IO uint32_t MRBR1; /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */
17413 __IO uint32_t RDSR2; /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */
17414 __IO uint32_t TDSR2; /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */
17415 __IO uint32_t MRBR2; /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */
17416 uint8_t RESERVED_12[8];
17417 __IO uint32_t RDSR; /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */
17418 __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */
17419 __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */
17420 uint8_t RESERVED_13[4];
17421 __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
17422 __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
17423 __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
17424 __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
17425 __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
17426 __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
17427 __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
17428 __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
17429 __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
17430 uint8_t RESERVED_14[12];
17431 __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
17432 __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
17433 __IO uint32_t RCMR[2]; /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */
17434 uint8_t RESERVED_15[8];
17435 __IO uint32_t DMACFG[2]; /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */
17436 __IO uint32_t RDAR1; /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */
17437 __IO uint32_t TDAR1; /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */
17438 __IO uint32_t RDAR2; /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */
17439 __IO uint32_t TDAR2; /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */
17440 __IO uint32_t QOS; /**< QOS Scheme, offset: 0x1F0 */
17441 uint8_t RESERVED_16[12];
17442 uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */
17443 __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
17444 __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
17445 __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
17446 __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
17447 __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
17448 __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
17449 __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
17450 __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
17451 __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
17452 __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
17453 __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
17454 __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
17455 __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
17456 __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
17457 __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
17458 __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
17459 __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
17460 uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */
17461 __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
17462 __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
17463 __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
17464 __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
17465 __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
17466 __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
17467 __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
17468 __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
17469 __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */
17470 __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
17471 __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
17472 uint8_t RESERVED_17[12];
17473 __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
17474 __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
17475 __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
17476 __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
17477 __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
17478 __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
17479 __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
17480 __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
17481 uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */
17482 __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
17483 __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
17484 __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
17485 __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
17486 __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
17487 __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
17488 __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
17489 __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
17490 __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
17491 __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
17492 __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
17493 __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
17494 __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
17495 __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
17496 __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
17497 uint8_t RESERVED_18[284];
17498 __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
17499 __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
17500 __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
17501 __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
17502 __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
17503 __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
17504 __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
17505 uint8_t RESERVED_19[488];
17506 __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
17507 struct { /* offset: 0x608, array step: 0x8 */
17508 __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
17509 __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
17510 } CHANNEL[4];
17511} ENET_Type;
17512
17513/* ----------------------------------------------------------------------------
17514 -- ENET Register Masks
17515 ---------------------------------------------------------------------------- */
17516
17517/*!
17518 * @addtogroup ENET_Register_Masks ENET Register Masks
17519 * @{
17520 */
17521
17522/*! @name EIR - Interrupt Event Register */
17523/*! @{ */
17524#define ENET_EIR_RXB1_MASK (0x1U)
17525#define ENET_EIR_RXB1_SHIFT (0U)
17526#define ENET_EIR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK)
17527#define ENET_EIR_RXF1_MASK (0x2U)
17528#define ENET_EIR_RXF1_SHIFT (1U)
17529#define ENET_EIR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK)
17530#define ENET_EIR_TXB1_MASK (0x4U)
17531#define ENET_EIR_TXB1_SHIFT (2U)
17532#define ENET_EIR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK)
17533#define ENET_EIR_TXF1_MASK (0x8U)
17534#define ENET_EIR_TXF1_SHIFT (3U)
17535#define ENET_EIR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK)
17536#define ENET_EIR_RXB2_MASK (0x10U)
17537#define ENET_EIR_RXB2_SHIFT (4U)
17538#define ENET_EIR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK)
17539#define ENET_EIR_RXF2_MASK (0x20U)
17540#define ENET_EIR_RXF2_SHIFT (5U)
17541#define ENET_EIR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK)
17542#define ENET_EIR_TXB2_MASK (0x40U)
17543#define ENET_EIR_TXB2_SHIFT (6U)
17544#define ENET_EIR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK)
17545#define ENET_EIR_TXF2_MASK (0x80U)
17546#define ENET_EIR_TXF2_SHIFT (7U)
17547#define ENET_EIR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK)
17548#define ENET_EIR_RXFLUSH_0_MASK (0x1000U)
17549#define ENET_EIR_RXFLUSH_0_SHIFT (12U)
17550#define ENET_EIR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK)
17551#define ENET_EIR_RXFLUSH_1_MASK (0x2000U)
17552#define ENET_EIR_RXFLUSH_1_SHIFT (13U)
17553#define ENET_EIR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK)
17554#define ENET_EIR_RXFLUSH_2_MASK (0x4000U)
17555#define ENET_EIR_RXFLUSH_2_SHIFT (14U)
17556#define ENET_EIR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK)
17557#define ENET_EIR_TS_TIMER_MASK (0x8000U)
17558#define ENET_EIR_TS_TIMER_SHIFT (15U)
17559#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
17560#define ENET_EIR_TS_AVAIL_MASK (0x10000U)
17561#define ENET_EIR_TS_AVAIL_SHIFT (16U)
17562#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
17563#define ENET_EIR_WAKEUP_MASK (0x20000U)
17564#define ENET_EIR_WAKEUP_SHIFT (17U)
17565#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
17566#define ENET_EIR_PLR_MASK (0x40000U)
17567#define ENET_EIR_PLR_SHIFT (18U)
17568#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
17569#define ENET_EIR_UN_MASK (0x80000U)
17570#define ENET_EIR_UN_SHIFT (19U)
17571#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
17572#define ENET_EIR_RL_MASK (0x100000U)
17573#define ENET_EIR_RL_SHIFT (20U)
17574#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
17575#define ENET_EIR_LC_MASK (0x200000U)
17576#define ENET_EIR_LC_SHIFT (21U)
17577#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
17578#define ENET_EIR_EBERR_MASK (0x400000U)
17579#define ENET_EIR_EBERR_SHIFT (22U)
17580#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
17581#define ENET_EIR_MII_MASK (0x800000U)
17582#define ENET_EIR_MII_SHIFT (23U)
17583#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
17584#define ENET_EIR_RXB_MASK (0x1000000U)
17585#define ENET_EIR_RXB_SHIFT (24U)
17586#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
17587#define ENET_EIR_RXF_MASK (0x2000000U)
17588#define ENET_EIR_RXF_SHIFT (25U)
17589#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
17590#define ENET_EIR_TXB_MASK (0x4000000U)
17591#define ENET_EIR_TXB_SHIFT (26U)
17592#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
17593#define ENET_EIR_TXF_MASK (0x8000000U)
17594#define ENET_EIR_TXF_SHIFT (27U)
17595#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
17596#define ENET_EIR_GRA_MASK (0x10000000U)
17597#define ENET_EIR_GRA_SHIFT (28U)
17598#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
17599#define ENET_EIR_BABT_MASK (0x20000000U)
17600#define ENET_EIR_BABT_SHIFT (29U)
17601#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
17602#define ENET_EIR_BABR_MASK (0x40000000U)
17603#define ENET_EIR_BABR_SHIFT (30U)
17604#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
17605/*! @} */
17606
17607/*! @name EIMR - Interrupt Mask Register */
17608/*! @{ */
17609#define ENET_EIMR_RXB1_MASK (0x1U)
17610#define ENET_EIMR_RXB1_SHIFT (0U)
17611#define ENET_EIMR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK)
17612#define ENET_EIMR_RXF1_MASK (0x2U)
17613#define ENET_EIMR_RXF1_SHIFT (1U)
17614#define ENET_EIMR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK)
17615#define ENET_EIMR_TXB1_MASK (0x4U)
17616#define ENET_EIMR_TXB1_SHIFT (2U)
17617#define ENET_EIMR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK)
17618#define ENET_EIMR_TXF1_MASK (0x8U)
17619#define ENET_EIMR_TXF1_SHIFT (3U)
17620#define ENET_EIMR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK)
17621#define ENET_EIMR_RXB2_MASK (0x10U)
17622#define ENET_EIMR_RXB2_SHIFT (4U)
17623#define ENET_EIMR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK)
17624#define ENET_EIMR_RXF2_MASK (0x20U)
17625#define ENET_EIMR_RXF2_SHIFT (5U)
17626#define ENET_EIMR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK)
17627#define ENET_EIMR_TXB2_MASK (0x40U)
17628#define ENET_EIMR_TXB2_SHIFT (6U)
17629#define ENET_EIMR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK)
17630#define ENET_EIMR_TXF2_MASK (0x80U)
17631#define ENET_EIMR_TXF2_SHIFT (7U)
17632#define ENET_EIMR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK)
17633#define ENET_EIMR_RXFLUSH_0_MASK (0x1000U)
17634#define ENET_EIMR_RXFLUSH_0_SHIFT (12U)
17635#define ENET_EIMR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK)
17636#define ENET_EIMR_RXFLUSH_1_MASK (0x2000U)
17637#define ENET_EIMR_RXFLUSH_1_SHIFT (13U)
17638#define ENET_EIMR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK)
17639#define ENET_EIMR_RXFLUSH_2_MASK (0x4000U)
17640#define ENET_EIMR_RXFLUSH_2_SHIFT (14U)
17641#define ENET_EIMR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK)
17642#define ENET_EIMR_TS_TIMER_MASK (0x8000U)
17643#define ENET_EIMR_TS_TIMER_SHIFT (15U)
17644#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
17645#define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
17646#define ENET_EIMR_TS_AVAIL_SHIFT (16U)
17647#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
17648#define ENET_EIMR_WAKEUP_MASK (0x20000U)
17649#define ENET_EIMR_WAKEUP_SHIFT (17U)
17650#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
17651#define ENET_EIMR_PLR_MASK (0x40000U)
17652#define ENET_EIMR_PLR_SHIFT (18U)
17653#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
17654#define ENET_EIMR_UN_MASK (0x80000U)
17655#define ENET_EIMR_UN_SHIFT (19U)
17656#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
17657#define ENET_EIMR_RL_MASK (0x100000U)
17658#define ENET_EIMR_RL_SHIFT (20U)
17659#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
17660#define ENET_EIMR_LC_MASK (0x200000U)
17661#define ENET_EIMR_LC_SHIFT (21U)
17662#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
17663#define ENET_EIMR_EBERR_MASK (0x400000U)
17664#define ENET_EIMR_EBERR_SHIFT (22U)
17665#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
17666#define ENET_EIMR_MII_MASK (0x800000U)
17667#define ENET_EIMR_MII_SHIFT (23U)
17668#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
17669#define ENET_EIMR_RXB_MASK (0x1000000U)
17670#define ENET_EIMR_RXB_SHIFT (24U)
17671#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
17672#define ENET_EIMR_RXF_MASK (0x2000000U)
17673#define ENET_EIMR_RXF_SHIFT (25U)
17674#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
17675#define ENET_EIMR_TXB_MASK (0x4000000U)
17676#define ENET_EIMR_TXB_SHIFT (26U)
17677/*! TXB - TXB Interrupt Mask
17678 * 0b0..The corresponding interrupt source is masked.
17679 * 0b1..The corresponding interrupt source is not masked.
17680 */
17681#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
17682#define ENET_EIMR_TXF_MASK (0x8000000U)
17683#define ENET_EIMR_TXF_SHIFT (27U)
17684/*! TXF - TXF Interrupt Mask
17685 * 0b0..The corresponding interrupt source is masked.
17686 * 0b1..The corresponding interrupt source is not masked.
17687 */
17688#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
17689#define ENET_EIMR_GRA_MASK (0x10000000U)
17690#define ENET_EIMR_GRA_SHIFT (28U)
17691/*! GRA - GRA Interrupt Mask
17692 * 0b0..The corresponding interrupt source is masked.
17693 * 0b1..The corresponding interrupt source is not masked.
17694 */
17695#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
17696#define ENET_EIMR_BABT_MASK (0x20000000U)
17697#define ENET_EIMR_BABT_SHIFT (29U)
17698/*! BABT - BABT Interrupt Mask
17699 * 0b0..The corresponding interrupt source is masked.
17700 * 0b1..The corresponding interrupt source is not masked.
17701 */
17702#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
17703#define ENET_EIMR_BABR_MASK (0x40000000U)
17704#define ENET_EIMR_BABR_SHIFT (30U)
17705/*! BABR - BABR Interrupt Mask
17706 * 0b0..The corresponding interrupt source is masked.
17707 * 0b1..The corresponding interrupt source is not masked.
17708 */
17709#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
17710/*! @} */
17711
17712/*! @name RDAR - Receive Descriptor Active Register - Ring 0 */
17713/*! @{ */
17714#define ENET_RDAR_RDAR_MASK (0x1000000U)
17715#define ENET_RDAR_RDAR_SHIFT (24U)
17716#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
17717/*! @} */
17718
17719/*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */
17720/*! @{ */
17721#define ENET_TDAR_TDAR_MASK (0x1000000U)
17722#define ENET_TDAR_TDAR_SHIFT (24U)
17723#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
17724/*! @} */
17725
17726/*! @name ECR - Ethernet Control Register */
17727/*! @{ */
17728#define ENET_ECR_RESET_MASK (0x1U)
17729#define ENET_ECR_RESET_SHIFT (0U)
17730#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
17731#define ENET_ECR_ETHEREN_MASK (0x2U)
17732#define ENET_ECR_ETHEREN_SHIFT (1U)
17733/*! ETHEREN - Ethernet Enable
17734 * 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.
17735 * 0b1..MAC is enabled, and reception and transmission are possible.
17736 */
17737#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
17738#define ENET_ECR_MAGICEN_MASK (0x4U)
17739#define ENET_ECR_MAGICEN_SHIFT (2U)
17740/*! MAGICEN - Magic Packet Detection Enable
17741 * 0b0..Magic detection logic disabled.
17742 * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
17743 */
17744#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
17745#define ENET_ECR_SLEEP_MASK (0x8U)
17746#define ENET_ECR_SLEEP_SHIFT (3U)
17747/*! SLEEP - Sleep Mode Enable
17748 * 0b0..Normal operating mode.
17749 * 0b1..Sleep mode.
17750 */
17751#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
17752#define ENET_ECR_EN1588_MASK (0x10U)
17753#define ENET_ECR_EN1588_SHIFT (4U)
17754/*! EN1588 - EN1588 Enable
17755 * 0b0..Legacy FEC buffer descriptors and functions enabled.
17756 * 0b1..Enhanced frame time-stamping functions enabled.
17757 */
17758#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
17759#define ENET_ECR_SPEED_MASK (0x20U)
17760#define ENET_ECR_SPEED_SHIFT (5U)
17761/*! SPEED
17762 * 0b0..10/100-Mbit/s mode
17763 * 0b1..1000-Mbit/s mode
17764 */
17765#define ENET_ECR_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK)
17766#define ENET_ECR_DBGEN_MASK (0x40U)
17767#define ENET_ECR_DBGEN_SHIFT (6U)
17768/*! DBGEN - Debug Enable
17769 * 0b0..MAC continues operation in debug mode.
17770 * 0b1..MAC enters hardware freeze mode when the processor is in debug mode.
17771 */
17772#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
17773#define ENET_ECR_DBSWP_MASK (0x100U)
17774#define ENET_ECR_DBSWP_SHIFT (8U)
17775/*! DBSWP - Descriptor Byte Swapping Enable
17776 * 0b0..The buffer descriptor bytes are not swapped to support big-endian devices.
17777 * 0b1..The buffer descriptor bytes are swapped to support little-endian devices.
17778 */
17779#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
17780#define ENET_ECR_SVLANEN_MASK (0x200U)
17781#define ENET_ECR_SVLANEN_SHIFT (9U)
17782/*! SVLANEN - S-VLAN enable
17783 * 0b0..Only the EtherType 0x8100 will be considered for VLAN detection.
17784 * 0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in
17785 * receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the
17786 * classification match comparators, RCMRn.
17787 */
17788#define ENET_ECR_SVLANEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK)
17789#define ENET_ECR_VLANUSE2ND_MASK (0x400U)
17790#define ENET_ECR_VLANUSE2ND_SHIFT (10U)
17791/*! VLANUSE2ND - VLAN use second tag
17792 * 0b0..Always extract data from the first VLAN tag if it exists.
17793 * 0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A
17794 * double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The
17795 * second tag must be a C-VLAN
17796 */
17797#define ENET_ECR_VLANUSE2ND(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK)
17798#define ENET_ECR_SVLANDBL_MASK (0x800U)
17799#define ENET_ECR_SVLANDBL_SHIFT (11U)
17800#define ENET_ECR_SVLANDBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK)
17801/*! @} */
17802
17803/*! @name MMFR - MII Management Frame Register */
17804/*! @{ */
17805#define ENET_MMFR_DATA_MASK (0xFFFFU)
17806#define ENET_MMFR_DATA_SHIFT (0U)
17807#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
17808#define ENET_MMFR_TA_MASK (0x30000U)
17809#define ENET_MMFR_TA_SHIFT (16U)
17810#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
17811#define ENET_MMFR_RA_MASK (0x7C0000U)
17812#define ENET_MMFR_RA_SHIFT (18U)
17813#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
17814#define ENET_MMFR_PA_MASK (0xF800000U)
17815#define ENET_MMFR_PA_SHIFT (23U)
17816#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
17817#define ENET_MMFR_OP_MASK (0x30000000U)
17818#define ENET_MMFR_OP_SHIFT (28U)
17819#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
17820#define ENET_MMFR_ST_MASK (0xC0000000U)
17821#define ENET_MMFR_ST_SHIFT (30U)
17822#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
17823/*! @} */
17824
17825/*! @name MSCR - MII Speed Control Register */
17826/*! @{ */
17827#define ENET_MSCR_MII_SPEED_MASK (0x7EU)
17828#define ENET_MSCR_MII_SPEED_SHIFT (1U)
17829#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
17830#define ENET_MSCR_DIS_PRE_MASK (0x80U)
17831#define ENET_MSCR_DIS_PRE_SHIFT (7U)
17832/*! DIS_PRE - Disable Preamble
17833 * 0b0..Preamble enabled.
17834 * 0b1..Preamble (32 ones) is not prepended to the MII management frame.
17835 */
17836#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
17837#define ENET_MSCR_HOLDTIME_MASK (0x700U)
17838#define ENET_MSCR_HOLDTIME_SHIFT (8U)
17839/*! HOLDTIME - Hold time On MDIO Output
17840 * 0b000..1 internal module clock cycle
17841 * 0b001..2 internal module clock cycles
17842 * 0b010..3 internal module clock cycles
17843 * 0b111..8 internal module clock cycles
17844 */
17845#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
17846/*! @} */
17847
17848/*! @name MIBC - MIB Control Register */
17849/*! @{ */
17850#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
17851#define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
17852/*! MIB_CLEAR - MIB Clear
17853 * 0b0..See note above.
17854 * 0b1..All statistics counters are reset to 0.
17855 */
17856#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
17857#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
17858#define ENET_MIBC_MIB_IDLE_SHIFT (30U)
17859/*! MIB_IDLE - MIB Idle
17860 * 0b0..The MIB block is updating MIB counters.
17861 * 0b1..The MIB block is not currently updating any MIB counters.
17862 */
17863#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
17864#define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
17865#define ENET_MIBC_MIB_DIS_SHIFT (31U)
17866/*! MIB_DIS - Disable MIB Logic
17867 * 0b0..MIB logic is enabled.
17868 * 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
17869 */
17870#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
17871/*! @} */
17872
17873/*! @name RCR - Receive Control Register */
17874/*! @{ */
17875#define ENET_RCR_LOOP_MASK (0x1U)
17876#define ENET_RCR_LOOP_SHIFT (0U)
17877/*! LOOP - Internal Loopback
17878 * 0b0..Loopback disabled.
17879 * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
17880 */
17881#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
17882#define ENET_RCR_DRT_MASK (0x2U)
17883#define ENET_RCR_DRT_SHIFT (1U)
17884/*! DRT - Disable Receive On Transmit
17885 * 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode.
17886 * 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
17887 */
17888#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
17889#define ENET_RCR_MII_MODE_MASK (0x4U)
17890#define ENET_RCR_MII_MODE_SHIFT (2U)
17891/*! MII_MODE - Media Independent Interface Mode
17892 * 0b0..Reserved.
17893 * 0b1..MII or RMII mode, as indicated by the RMII_MODE field.
17894 */
17895#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
17896#define ENET_RCR_PROM_MASK (0x8U)
17897#define ENET_RCR_PROM_SHIFT (3U)
17898/*! PROM - Promiscuous Mode
17899 * 0b0..Disabled.
17900 * 0b1..Enabled.
17901 */
17902#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
17903#define ENET_RCR_BC_REJ_MASK (0x10U)
17904#define ENET_RCR_BC_REJ_SHIFT (4U)
17905#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
17906#define ENET_RCR_FCE_MASK (0x20U)
17907#define ENET_RCR_FCE_SHIFT (5U)
17908#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
17909#define ENET_RCR_RGMII_EN_MASK (0x40U)
17910#define ENET_RCR_RGMII_EN_SHIFT (6U)
17911/*! RGMII_EN - RGMII Mode Enable
17912 * 0b0..MAC configured for non-RGMII operation
17913 * 0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If
17914 * ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode.
17915 */
17916#define ENET_RCR_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK)
17917#define ENET_RCR_RMII_MODE_MASK (0x100U)
17918#define ENET_RCR_RMII_MODE_SHIFT (8U)
17919/*! RMII_MODE - RMII Mode Enable
17920 * 0b0..MAC configured for MII mode.
17921 * 0b1..MAC configured for RMII operation.
17922 */
17923#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
17924#define ENET_RCR_RMII_10T_MASK (0x200U)
17925#define ENET_RCR_RMII_10T_SHIFT (9U)
17926/*! RMII_10T
17927 * 0b0..100-Mbit/s operation.
17928 * 0b1..10-Mbit/s operation.
17929 */
17930#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
17931#define ENET_RCR_PADEN_MASK (0x1000U)
17932#define ENET_RCR_PADEN_SHIFT (12U)
17933/*! PADEN - Enable Frame Padding Remove On Receive
17934 * 0b0..No padding is removed on receive by the MAC.
17935 * 0b1..Padding is removed from received frames.
17936 */
17937#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
17938#define ENET_RCR_PAUFWD_MASK (0x2000U)
17939#define ENET_RCR_PAUFWD_SHIFT (13U)
17940/*! PAUFWD - Terminate/Forward Pause Frames
17941 * 0b0..Pause frames are terminated and discarded in the MAC.
17942 * 0b1..Pause frames are forwarded to the user application.
17943 */
17944#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
17945#define ENET_RCR_CRCFWD_MASK (0x4000U)
17946#define ENET_RCR_CRCFWD_SHIFT (14U)
17947/*! CRCFWD - Terminate/Forward Received CRC
17948 * 0b0..The CRC field of received frames is transmitted to the user application.
17949 * 0b1..The CRC field is stripped from the frame.
17950 */
17951#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
17952#define ENET_RCR_CFEN_MASK (0x8000U)
17953#define ENET_RCR_CFEN_SHIFT (15U)
17954/*! CFEN - MAC Control Frame Enable
17955 * 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface.
17956 * 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
17957 */
17958#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
17959#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
17960#define ENET_RCR_MAX_FL_SHIFT (16U)
17961#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
17962#define ENET_RCR_NLC_MASK (0x40000000U)
17963#define ENET_RCR_NLC_SHIFT (30U)
17964/*! NLC - Payload Length Check Disable
17965 * 0b0..The payload length check is disabled.
17966 * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.
17967 */
17968#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
17969#define ENET_RCR_GRS_MASK (0x80000000U)
17970#define ENET_RCR_GRS_SHIFT (31U)
17971#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
17972/*! @} */
17973
17974/*! @name TCR - Transmit Control Register */
17975/*! @{ */
17976#define ENET_TCR_GTS_MASK (0x1U)
17977#define ENET_TCR_GTS_SHIFT (0U)
17978#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
17979#define ENET_TCR_FDEN_MASK (0x4U)
17980#define ENET_TCR_FDEN_SHIFT (2U)
17981#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
17982#define ENET_TCR_TFC_PAUSE_MASK (0x8U)
17983#define ENET_TCR_TFC_PAUSE_SHIFT (3U)
17984/*! TFC_PAUSE - Transmit Frame Control Pause
17985 * 0b0..No PAUSE frame transmitted.
17986 * 0b1..The MAC stops transmission of data frames after the current transmission is complete.
17987 */
17988#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
17989#define ENET_TCR_RFC_PAUSE_MASK (0x10U)
17990#define ENET_TCR_RFC_PAUSE_SHIFT (4U)
17991#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
17992#define ENET_TCR_ADDSEL_MASK (0xE0U)
17993#define ENET_TCR_ADDSEL_SHIFT (5U)
17994/*! ADDSEL - Source MAC Address Select On Transmit
17995 * 0b000..Node MAC address programmed on PADDR1/2 registers.
17996 * 0b100..Reserved.
17997 * 0b101..Reserved.
17998 * 0b110..Reserved.
17999 */
18000#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
18001#define ENET_TCR_ADDINS_MASK (0x100U)
18002#define ENET_TCR_ADDINS_SHIFT (8U)
18003/*! ADDINS - Set MAC Address On Transmit
18004 * 0b0..The source MAC address is not modified by the MAC.
18005 * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
18006 */
18007#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
18008#define ENET_TCR_CRCFWD_MASK (0x200U)
18009#define ENET_TCR_CRCFWD_SHIFT (9U)
18010/*! CRCFWD - Forward Frame From Application With CRC
18011 * 0b0..TxBD[TC] controls whether the frame has a CRC from the application.
18012 * 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
18013 */
18014#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
18015/*! @} */
18016
18017/*! @name PALR - Physical Address Lower Register */
18018/*! @{ */
18019#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
18020#define ENET_PALR_PADDR1_SHIFT (0U)
18021#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
18022/*! @} */
18023
18024/*! @name PAUR - Physical Address Upper Register */
18025/*! @{ */
18026#define ENET_PAUR_TYPE_MASK (0xFFFFU)
18027#define ENET_PAUR_TYPE_SHIFT (0U)
18028#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
18029#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
18030#define ENET_PAUR_PADDR2_SHIFT (16U)
18031#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
18032/*! @} */
18033
18034/*! @name OPD - Opcode/Pause Duration Register */
18035/*! @{ */
18036#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
18037#define ENET_OPD_PAUSE_DUR_SHIFT (0U)
18038#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
18039#define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
18040#define ENET_OPD_OPCODE_SHIFT (16U)
18041#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
18042/*! @} */
18043
18044/*! @name TXIC - Transmit Interrupt Coalescing Register */
18045/*! @{ */
18046#define ENET_TXIC_ICTT_MASK (0xFFFFU)
18047#define ENET_TXIC_ICTT_SHIFT (0U)
18048#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
18049#define ENET_TXIC_ICFT_MASK (0xFF00000U)
18050#define ENET_TXIC_ICFT_SHIFT (20U)
18051#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
18052#define ENET_TXIC_ICCS_MASK (0x40000000U)
18053#define ENET_TXIC_ICCS_SHIFT (30U)
18054/*! ICCS - Interrupt Coalescing Timer Clock Source Select
18055 * 0b0..Use MII/GMII TX clocks.
18056 * 0b1..Use ENET system clock.
18057 */
18058#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
18059#define ENET_TXIC_ICEN_MASK (0x80000000U)
18060#define ENET_TXIC_ICEN_SHIFT (31U)
18061/*! ICEN - Interrupt Coalescing Enable
18062 * 0b0..Disable Interrupt coalescing.
18063 * 0b1..Enable Interrupt coalescing.
18064 */
18065#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
18066/*! @} */
18067
18068/* The count of ENET_TXIC */
18069#define ENET_TXIC_COUNT (3U)
18070
18071/*! @name RXIC - Receive Interrupt Coalescing Register */
18072/*! @{ */
18073#define ENET_RXIC_ICTT_MASK (0xFFFFU)
18074#define ENET_RXIC_ICTT_SHIFT (0U)
18075#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
18076#define ENET_RXIC_ICFT_MASK (0xFF00000U)
18077#define ENET_RXIC_ICFT_SHIFT (20U)
18078#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
18079#define ENET_RXIC_ICCS_MASK (0x40000000U)
18080#define ENET_RXIC_ICCS_SHIFT (30U)
18081/*! ICCS - Interrupt Coalescing Timer Clock Source Select
18082 * 0b0..Use MII/GMII TX clocks.
18083 * 0b1..Use ENET system clock.
18084 */
18085#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
18086#define ENET_RXIC_ICEN_MASK (0x80000000U)
18087#define ENET_RXIC_ICEN_SHIFT (31U)
18088/*! ICEN - Interrupt Coalescing Enable
18089 * 0b0..Disable Interrupt coalescing.
18090 * 0b1..Enable Interrupt coalescing.
18091 */
18092#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
18093/*! @} */
18094
18095/* The count of ENET_RXIC */
18096#define ENET_RXIC_COUNT (3U)
18097
18098/*! @name IAUR - Descriptor Individual Upper Address Register */
18099/*! @{ */
18100#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
18101#define ENET_IAUR_IADDR1_SHIFT (0U)
18102#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
18103/*! @} */
18104
18105/*! @name IALR - Descriptor Individual Lower Address Register */
18106/*! @{ */
18107#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
18108#define ENET_IALR_IADDR2_SHIFT (0U)
18109#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
18110/*! @} */
18111
18112/*! @name GAUR - Descriptor Group Upper Address Register */
18113/*! @{ */
18114#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
18115#define ENET_GAUR_GADDR1_SHIFT (0U)
18116#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
18117/*! @} */
18118
18119/*! @name GALR - Descriptor Group Lower Address Register */
18120/*! @{ */
18121#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
18122#define ENET_GALR_GADDR2_SHIFT (0U)
18123#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
18124/*! @} */
18125
18126/*! @name TFWR - Transmit FIFO Watermark Register */
18127/*! @{ */
18128#define ENET_TFWR_TFWR_MASK (0x3FU)
18129#define ENET_TFWR_TFWR_SHIFT (0U)
18130/*! TFWR - Transmit FIFO Write
18131 * 0b000000..64 bytes written.
18132 * 0b000001..64 bytes written.
18133 * 0b000010..128 bytes written.
18134 * 0b000011..192 bytes written.
18135 * 0b111111..4032 bytes written.
18136 */
18137#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
18138#define ENET_TFWR_STRFWD_MASK (0x100U)
18139#define ENET_TFWR_STRFWD_SHIFT (8U)
18140/*! STRFWD - Store And Forward Enable
18141 * 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR].
18142 * 0b1..Enabled.
18143 */
18144#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
18145/*! @} */
18146
18147/*! @name RDSR1 - Receive Descriptor Ring 1 Start Register */
18148/*! @{ */
18149#define ENET_RDSR1_R_DES_START_MASK (0xFFFFFFF8U)
18150#define ENET_RDSR1_R_DES_START_SHIFT (3U)
18151#define ENET_RDSR1_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK)
18152/*! @} */
18153
18154/*! @name TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register */
18155/*! @{ */
18156#define ENET_TDSR1_X_DES_START_MASK (0xFFFFFFF8U)
18157#define ENET_TDSR1_X_DES_START_SHIFT (3U)
18158#define ENET_TDSR1_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK)
18159/*! @} */
18160
18161/*! @name MRBR1 - Maximum Receive Buffer Size Register - Ring 1 */
18162/*! @{ */
18163#define ENET_MRBR1_R_BUF_SIZE_MASK (0x7F0U)
18164#define ENET_MRBR1_R_BUF_SIZE_SHIFT (4U)
18165#define ENET_MRBR1_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK)
18166/*! @} */
18167
18168/*! @name RDSR2 - Receive Descriptor Ring 2 Start Register */
18169/*! @{ */
18170#define ENET_RDSR2_R_DES_START_MASK (0xFFFFFFF8U)
18171#define ENET_RDSR2_R_DES_START_SHIFT (3U)
18172#define ENET_RDSR2_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK)
18173/*! @} */
18174
18175/*! @name TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register */
18176/*! @{ */
18177#define ENET_TDSR2_X_DES_START_MASK (0xFFFFFFF8U)
18178#define ENET_TDSR2_X_DES_START_SHIFT (3U)
18179#define ENET_TDSR2_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK)
18180/*! @} */
18181
18182/*! @name MRBR2 - Maximum Receive Buffer Size Register - Ring 2 */
18183/*! @{ */
18184#define ENET_MRBR2_R_BUF_SIZE_MASK (0x7F0U)
18185#define ENET_MRBR2_R_BUF_SIZE_SHIFT (4U)
18186#define ENET_MRBR2_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK)
18187/*! @} */
18188
18189/*! @name RDSR - Receive Descriptor Ring 0 Start Register */
18190/*! @{ */
18191#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
18192#define ENET_RDSR_R_DES_START_SHIFT (3U)
18193#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
18194/*! @} */
18195
18196/*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */
18197/*! @{ */
18198#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
18199#define ENET_TDSR_X_DES_START_SHIFT (3U)
18200#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
18201/*! @} */
18202
18203/*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */
18204/*! @{ */
18205#define ENET_MRBR_R_BUF_SIZE_MASK (0x7F0U)
18206#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
18207#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
18208/*! @} */
18209
18210/*! @name RSFL - Receive FIFO Section Full Threshold */
18211/*! @{ */
18212#define ENET_RSFL_RX_SECTION_FULL_MASK (0x3FFU)
18213#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
18214#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
18215/*! @} */
18216
18217/*! @name RSEM - Receive FIFO Section Empty Threshold */
18218/*! @{ */
18219#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0x3FFU)
18220#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
18221#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
18222#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
18223#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
18224#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
18225/*! @} */
18226
18227/*! @name RAEM - Receive FIFO Almost Empty Threshold */
18228/*! @{ */
18229#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0x3FFU)
18230#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
18231#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
18232/*! @} */
18233
18234/*! @name RAFL - Receive FIFO Almost Full Threshold */
18235/*! @{ */
18236#define ENET_RAFL_RX_ALMOST_FULL_MASK (0x3FFU)
18237#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
18238#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
18239/*! @} */
18240
18241/*! @name TSEM - Transmit FIFO Section Empty Threshold */
18242/*! @{ */
18243#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0x3FFU)
18244#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
18245#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
18246/*! @} */
18247
18248/*! @name TAEM - Transmit FIFO Almost Empty Threshold */
18249/*! @{ */
18250#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0x3FFU)
18251#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
18252#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
18253/*! @} */
18254
18255/*! @name TAFL - Transmit FIFO Almost Full Threshold */
18256/*! @{ */
18257#define ENET_TAFL_TX_ALMOST_FULL_MASK (0x3FFU)
18258#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
18259#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
18260/*! @} */
18261
18262/*! @name TIPG - Transmit Inter-Packet Gap */
18263/*! @{ */
18264#define ENET_TIPG_IPG_MASK (0x1FU)
18265#define ENET_TIPG_IPG_SHIFT (0U)
18266#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
18267/*! @} */
18268
18269/*! @name FTRL - Frame Truncation Length */
18270/*! @{ */
18271#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
18272#define ENET_FTRL_TRUNC_FL_SHIFT (0U)
18273#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
18274/*! @} */
18275
18276/*! @name TACC - Transmit Accelerator Function Configuration */
18277/*! @{ */
18278#define ENET_TACC_SHIFT16_MASK (0x1U)
18279#define ENET_TACC_SHIFT16_SHIFT (0U)
18280/*! SHIFT16 - TX FIFO Shift-16
18281 * 0b0..Disabled.
18282 * 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the
18283 * frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This
18284 * function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is
18285 * extended to a 16-byte header.
18286 */
18287#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
18288#define ENET_TACC_IPCHK_MASK (0x8U)
18289#define ENET_TACC_IPCHK_SHIFT (3U)
18290/*! IPCHK
18291 * 0b0..Checksum is not inserted.
18292 * 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must
18293 * be cleared. If a non-IP frame is transmitted the frame is not modified.
18294 */
18295#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
18296#define ENET_TACC_PROCHK_MASK (0x10U)
18297#define ENET_TACC_PROCHK_SHIFT (4U)
18298/*! PROCHK
18299 * 0b0..Checksum not inserted.
18300 * 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the
18301 * frame. The checksum field must be cleared. The other frames are not modified.
18302 */
18303#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
18304/*! @} */
18305
18306/*! @name RACC - Receive Accelerator Function Configuration */
18307/*! @{ */
18308#define ENET_RACC_PADREM_MASK (0x1U)
18309#define ENET_RACC_PADREM_SHIFT (0U)
18310/*! PADREM - Enable Padding Removal For Short IP Frames
18311 * 0b0..Padding not removed.
18312 * 0b1..Any bytes following the IP payload section of the frame are removed from the frame.
18313 */
18314#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
18315#define ENET_RACC_IPDIS_MASK (0x2U)
18316#define ENET_RACC_IPDIS_SHIFT (1U)
18317/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum
18318 * 0b0..Frames with wrong IPv4 header checksum are not discarded.
18319 * 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no
18320 * header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in
18321 * store and forward mode (RSFL cleared).
18322 */
18323#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
18324#define ENET_RACC_PRODIS_MASK (0x4U)
18325#define ENET_RACC_PRODIS_SHIFT (2U)
18326/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum
18327 * 0b0..Frames with wrong checksum are not discarded.
18328 * 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame
18329 * is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL
18330 * cleared).
18331 */
18332#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
18333#define ENET_RACC_LINEDIS_MASK (0x40U)
18334#define ENET_RACC_LINEDIS_SHIFT (6U)
18335/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors
18336 * 0b0..Frames with errors are not discarded.
18337 * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
18338 */
18339#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
18340#define ENET_RACC_SHIFT16_MASK (0x80U)
18341#define ENET_RACC_SHIFT16_SHIFT (7U)
18342/*! SHIFT16 - RX FIFO Shift-16
18343 * 0b0..Disabled.
18344 * 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
18345 */
18346#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
18347/*! @} */
18348
18349/*! @name RCMR - Receive Classification Match Register for Class n */
18350/*! @{ */
18351#define ENET_RCMR_CMP0_MASK (0x7U)
18352#define ENET_RCMR_CMP0_SHIFT (0U)
18353#define ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK)
18354#define ENET_RCMR_CMP1_MASK (0x70U)
18355#define ENET_RCMR_CMP1_SHIFT (4U)
18356#define ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK)
18357#define ENET_RCMR_CMP2_MASK (0x700U)
18358#define ENET_RCMR_CMP2_SHIFT (8U)
18359#define ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK)
18360#define ENET_RCMR_CMP3_MASK (0x7000U)
18361#define ENET_RCMR_CMP3_SHIFT (12U)
18362#define ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK)
18363#define ENET_RCMR_MATCHEN_MASK (0x10000U)
18364#define ENET_RCMR_MATCHEN_SHIFT (16U)
18365/*! MATCHEN - Match Enable
18366 * 0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert.
18367 * 0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received.
18368 */
18369#define ENET_RCMR_MATCHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK)
18370/*! @} */
18371
18372/* The count of ENET_RCMR */
18373#define ENET_RCMR_COUNT (2U)
18374
18375/*! @name DMACFG - DMA Class Based Configuration */
18376/*! @{ */
18377#define ENET_DMACFG_IDLE_SLOPE_MASK (0xFFFFU)
18378#define ENET_DMACFG_IDLE_SLOPE_SHIFT (0U)
18379#define ENET_DMACFG_IDLE_SLOPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK)
18380#define ENET_DMACFG_DMA_CLASS_EN_MASK (0x10000U)
18381#define ENET_DMACFG_DMA_CLASS_EN_SHIFT (16U)
18382/*! DMA_CLASS_EN - DMA class enable
18383 * 0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also
18384 * requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2
18385 * queues are disabled then their frames will be placed in queue 0.
18386 * 0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic.
18387 */
18388#define ENET_DMACFG_DMA_CLASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK)
18389#define ENET_DMACFG_CALC_NOIPG_MASK (0x20000U)
18390#define ENET_DMACFG_CALC_NOIPG_SHIFT (17U)
18391/*! CALC_NOIPG - Calculate no IPG
18392 * 0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred
18393 * for a frame when doing bandwidth calculations. This is the default.
18394 * 0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping,
18395 * when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every
18396 * frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames
18397 * will become more bandwidth than large frames due to the relation of data to IPG overhead).
18398 */
18399#define ENET_DMACFG_CALC_NOIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK)
18400/*! @} */
18401
18402/* The count of ENET_DMACFG */
18403#define ENET_DMACFG_COUNT (2U)
18404
18405/*! @name RDAR1 - Receive Descriptor Active Register - Ring 1 */
18406/*! @{ */
18407#define ENET_RDAR1_RDAR_MASK (0x1000000U)
18408#define ENET_RDAR1_RDAR_SHIFT (24U)
18409#define ENET_RDAR1_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK)
18410/*! @} */
18411
18412/*! @name TDAR1 - Transmit Descriptor Active Register - Ring 1 */
18413/*! @{ */
18414#define ENET_TDAR1_TDAR_MASK (0x1000000U)
18415#define ENET_TDAR1_TDAR_SHIFT (24U)
18416#define ENET_TDAR1_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK)
18417/*! @} */
18418
18419/*! @name RDAR2 - Receive Descriptor Active Register - Ring 2 */
18420/*! @{ */
18421#define ENET_RDAR2_RDAR_MASK (0x1000000U)
18422#define ENET_RDAR2_RDAR_SHIFT (24U)
18423#define ENET_RDAR2_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK)
18424/*! @} */
18425
18426/*! @name TDAR2 - Transmit Descriptor Active Register - Ring 2 */
18427/*! @{ */
18428#define ENET_TDAR2_TDAR_MASK (0x1000000U)
18429#define ENET_TDAR2_TDAR_SHIFT (24U)
18430#define ENET_TDAR2_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK)
18431/*! @} */
18432
18433/*! @name QOS - QOS Scheme */
18434/*! @{ */
18435#define ENET_QOS_TX_SCHEME_MASK (0x7U)
18436#define ENET_QOS_TX_SCHEME_SHIFT (0U)
18437/*! TX_SCHEME - TX scheme configuration
18438 * 0b000..Credit-based scheme
18439 * 0b001..Round-robin scheme
18440 */
18441#define ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK)
18442#define ENET_QOS_RX_FLUSH0_MASK (0x8U)
18443#define ENET_QOS_RX_FLUSH0_SHIFT (3U)
18444/*! RX_FLUSH0 - RX Flush Ring 0
18445 * 0b0..Disable
18446 * 0b1..Enable
18447 */
18448#define ENET_QOS_RX_FLUSH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK)
18449#define ENET_QOS_RX_FLUSH1_MASK (0x10U)
18450#define ENET_QOS_RX_FLUSH1_SHIFT (4U)
18451/*! RX_FLUSH1 - RX Flush Ring 1
18452 * 0b0..Disable
18453 * 0b1..Enable
18454 */
18455#define ENET_QOS_RX_FLUSH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK)
18456#define ENET_QOS_RX_FLUSH2_MASK (0x20U)
18457#define ENET_QOS_RX_FLUSH2_SHIFT (5U)
18458/*! RX_FLUSH2 - RX Flush Ring 2
18459 * 0b0..Disable
18460 * 0b1..Enable
18461 */
18462#define ENET_QOS_RX_FLUSH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK)
18463/*! @} */
18464
18465/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
18466/*! @{ */
18467#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
18468#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
18469#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
18470/*! @} */
18471
18472/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
18473/*! @{ */
18474#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
18475#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
18476#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
18477/*! @} */
18478
18479/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
18480/*! @{ */
18481#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
18482#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
18483#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
18484/*! @} */
18485
18486/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
18487/*! @{ */
18488#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
18489#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
18490#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
18491/*! @} */
18492
18493/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
18494/*! @{ */
18495#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
18496#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
18497#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
18498/*! @} */
18499
18500/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
18501/*! @{ */
18502#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
18503#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
18504#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
18505/*! @} */
18506
18507/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
18508/*! @{ */
18509#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
18510#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
18511#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
18512/*! @} */
18513
18514/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
18515/*! @{ */
18516#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
18517#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
18518#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
18519/*! @} */
18520
18521/*! @name RMON_T_COL - Tx Collision Count Statistic Register */
18522/*! @{ */
18523#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
18524#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
18525#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
18526/*! @} */
18527
18528/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
18529/*! @{ */
18530#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
18531#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
18532#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
18533/*! @} */
18534
18535/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
18536/*! @{ */
18537#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
18538#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
18539#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
18540/*! @} */
18541
18542/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
18543/*! @{ */
18544#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
18545#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
18546#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
18547/*! @} */
18548
18549/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
18550/*! @{ */
18551#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
18552#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
18553#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
18554/*! @} */
18555
18556/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
18557/*! @{ */
18558#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
18559#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
18560#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
18561/*! @} */
18562
18563/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
18564/*! @{ */
18565#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
18566#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
18567#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
18568/*! @} */
18569
18570/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
18571/*! @{ */
18572#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
18573#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
18574#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
18575/*! @} */
18576
18577/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
18578/*! @{ */
18579#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
18580#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
18581#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
18582/*! @} */
18583
18584/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
18585/*! @{ */
18586#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
18587#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
18588#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
18589/*! @} */
18590
18591/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
18592/*! @{ */
18593#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
18594#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
18595#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
18596/*! @} */
18597
18598/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
18599/*! @{ */
18600#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
18601#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
18602#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
18603/*! @} */
18604
18605/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
18606/*! @{ */
18607#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
18608#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
18609#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
18610/*! @} */
18611
18612/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
18613/*! @{ */
18614#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
18615#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
18616#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
18617/*! @} */
18618
18619/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
18620/*! @{ */
18621#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
18622#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
18623#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
18624/*! @} */
18625
18626/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
18627/*! @{ */
18628#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
18629#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
18630#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
18631/*! @} */
18632
18633/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
18634/*! @{ */
18635#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
18636#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
18637#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
18638/*! @} */
18639
18640/*! @name IEEE_T_SQE - Reserved Statistic Register */
18641/*! @{ */
18642#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
18643#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
18644#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
18645/*! @} */
18646
18647/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
18648/*! @{ */
18649#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
18650#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
18651#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
18652/*! @} */
18653
18654/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
18655/*! @{ */
18656#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
18657#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
18658#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
18659/*! @} */
18660
18661/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
18662/*! @{ */
18663#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
18664#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
18665#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
18666/*! @} */
18667
18668/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
18669/*! @{ */
18670#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
18671#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
18672#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
18673/*! @} */
18674
18675/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
18676/*! @{ */
18677#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
18678#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
18679#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
18680/*! @} */
18681
18682/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
18683/*! @{ */
18684#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
18685#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
18686#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
18687/*! @} */
18688
18689/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
18690/*! @{ */
18691#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
18692#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
18693#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
18694/*! @} */
18695
18696/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
18697/*! @{ */
18698#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
18699#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
18700#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
18701/*! @} */
18702
18703/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
18704/*! @{ */
18705#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
18706#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
18707#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
18708/*! @} */
18709
18710/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
18711/*! @{ */
18712#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
18713#define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
18714#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
18715/*! @} */
18716
18717/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
18718/*! @{ */
18719#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
18720#define ENET_RMON_R_P64_COUNT_SHIFT (0U)
18721#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
18722/*! @} */
18723
18724/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
18725/*! @{ */
18726#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
18727#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
18728#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
18729/*! @} */
18730
18731/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
18732/*! @{ */
18733#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
18734#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
18735#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
18736/*! @} */
18737
18738/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
18739/*! @{ */
18740#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
18741#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
18742#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
18743/*! @} */
18744
18745/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
18746/*! @{ */
18747#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
18748#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
18749#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
18750/*! @} */
18751
18752/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
18753/*! @{ */
18754#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
18755#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
18756#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
18757/*! @} */
18758
18759/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
18760/*! @{ */
18761#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
18762#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
18763#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
18764/*! @} */
18765
18766/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
18767/*! @{ */
18768#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
18769#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
18770#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
18771/*! @} */
18772
18773/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
18774/*! @{ */
18775#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
18776#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
18777#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
18778/*! @} */
18779
18780/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
18781/*! @{ */
18782#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
18783#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
18784#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
18785/*! @} */
18786
18787/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
18788/*! @{ */
18789#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
18790#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
18791#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
18792/*! @} */
18793
18794/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
18795/*! @{ */
18796#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
18797#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
18798#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
18799/*! @} */
18800
18801/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
18802/*! @{ */
18803#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
18804#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
18805#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
18806/*! @} */
18807
18808/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
18809/*! @{ */
18810#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
18811#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
18812#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
18813/*! @} */
18814
18815/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
18816/*! @{ */
18817#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
18818#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
18819#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
18820/*! @} */
18821
18822/*! @name ATCR - Adjustable Timer Control Register */
18823/*! @{ */
18824#define ENET_ATCR_EN_MASK (0x1U)
18825#define ENET_ATCR_EN_SHIFT (0U)
18826/*! EN - Enable Timer
18827 * 0b0..The timer stops at the current value.
18828 * 0b1..The timer starts incrementing.
18829 */
18830#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
18831#define ENET_ATCR_OFFEN_MASK (0x4U)
18832#define ENET_ATCR_OFFEN_SHIFT (2U)
18833/*! OFFEN - Enable One-Shot Offset Event
18834 * 0b0..Disable.
18835 * 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared
18836 * when the offset event is reached, so no further event occurs until the field is set again. The timer
18837 * offset value must be set before setting this field.
18838 */
18839#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
18840#define ENET_ATCR_OFFRST_MASK (0x8U)
18841#define ENET_ATCR_OFFRST_SHIFT (3U)
18842/*! OFFRST - Reset Timer On Offset Event
18843 * 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
18844 * 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
18845 */
18846#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
18847#define ENET_ATCR_PEREN_MASK (0x10U)
18848#define ENET_ATCR_PEREN_SHIFT (4U)
18849/*! PEREN - Enable Periodical Event
18850 * 0b0..Disable.
18851 * 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when
18852 * the timer wraps around according to the periodic setting ATPER. The timer period value must be set before
18853 * setting this bit. Not all devices contain the event signal output. See the chip configuration details.
18854 */
18855#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
18856#define ENET_ATCR_PINPER_MASK (0x80U)
18857#define ENET_ATCR_PINPER_SHIFT (7U)
18858/*! PINPER
18859 * 0b0..Disable.
18860 * 0b1..Enable.
18861 */
18862#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
18863#define ENET_ATCR_RESTART_MASK (0x200U)
18864#define ENET_ATCR_RESTART_SHIFT (9U)
18865#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
18866#define ENET_ATCR_CAPTURE_MASK (0x800U)
18867#define ENET_ATCR_CAPTURE_SHIFT (11U)
18868/*! CAPTURE - Capture Timer Value
18869 * 0b0..No effect.
18870 * 0b1..The current time is captured and can be read from the ATVR register.
18871 */
18872#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
18873#define ENET_ATCR_SLAVE_MASK (0x2000U)
18874#define ENET_ATCR_SLAVE_SHIFT (13U)
18875/*! SLAVE - Enable Timer Slave Mode
18876 * 0b0..The timer is active and all configuration fields in this register are relevant.
18877 * 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except
18878 * CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
18879 */
18880#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
18881/*! @} */
18882
18883/*! @name ATVR - Timer Value Register */
18884/*! @{ */
18885#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
18886#define ENET_ATVR_ATIME_SHIFT (0U)
18887#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
18888/*! @} */
18889
18890/*! @name ATOFF - Timer Offset Register */
18891/*! @{ */
18892#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
18893#define ENET_ATOFF_OFFSET_SHIFT (0U)
18894#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
18895/*! @} */
18896
18897/*! @name ATPER - Timer Period Register */
18898/*! @{ */
18899#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
18900#define ENET_ATPER_PERIOD_SHIFT (0U)
18901#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
18902/*! @} */
18903
18904/*! @name ATCOR - Timer Correction Register */
18905/*! @{ */
18906#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
18907#define ENET_ATCOR_COR_SHIFT (0U)
18908#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
18909/*! @} */
18910
18911/*! @name ATINC - Time-Stamping Clock Period Register */
18912/*! @{ */
18913#define ENET_ATINC_INC_MASK (0x7FU)
18914#define ENET_ATINC_INC_SHIFT (0U)
18915#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
18916#define ENET_ATINC_INC_CORR_MASK (0x7F00U)
18917#define ENET_ATINC_INC_CORR_SHIFT (8U)
18918#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
18919/*! @} */
18920
18921/*! @name ATSTMP - Timestamp of Last Transmitted Frame */
18922/*! @{ */
18923#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
18924#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
18925#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
18926/*! @} */
18927
18928/*! @name TGSR - Timer Global Status Register */
18929/*! @{ */
18930#define ENET_TGSR_TF0_MASK (0x1U)
18931#define ENET_TGSR_TF0_SHIFT (0U)
18932/*! TF0 - Copy Of Timer Flag For Channel 0
18933 * 0b0..Timer Flag for Channel 0 is clear
18934 * 0b1..Timer Flag for Channel 0 is set
18935 */
18936#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
18937#define ENET_TGSR_TF1_MASK (0x2U)
18938#define ENET_TGSR_TF1_SHIFT (1U)
18939/*! TF1 - Copy Of Timer Flag For Channel 1
18940 * 0b0..Timer Flag for Channel 1 is clear
18941 * 0b1..Timer Flag for Channel 1 is set
18942 */
18943#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
18944#define ENET_TGSR_TF2_MASK (0x4U)
18945#define ENET_TGSR_TF2_SHIFT (2U)
18946/*! TF2 - Copy Of Timer Flag For Channel 2
18947 * 0b0..Timer Flag for Channel 2 is clear
18948 * 0b1..Timer Flag for Channel 2 is set
18949 */
18950#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
18951#define ENET_TGSR_TF3_MASK (0x8U)
18952#define ENET_TGSR_TF3_SHIFT (3U)
18953/*! TF3 - Copy Of Timer Flag For Channel 3
18954 * 0b0..Timer Flag for Channel 3 is clear
18955 * 0b1..Timer Flag for Channel 3 is set
18956 */
18957#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
18958/*! @} */
18959
18960/*! @name TCSR - Timer Control Status Register */
18961/*! @{ */
18962#define ENET_TCSR_TDRE_MASK (0x1U)
18963#define ENET_TCSR_TDRE_SHIFT (0U)
18964/*! TDRE - Timer DMA Request Enable
18965 * 0b0..DMA request is disabled
18966 * 0b1..DMA request is enabled
18967 */
18968#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
18969#define ENET_TCSR_TMODE_MASK (0x3CU)
18970#define ENET_TCSR_TMODE_SHIFT (2U)
18971/*! TMODE - Timer Mode
18972 * 0b0000..Timer Channel is disabled.
18973 * 0b0001..Timer Channel is configured for Input Capture on rising edge.
18974 * 0b0010..Timer Channel is configured for Input Capture on falling edge.
18975 * 0b0011..Timer Channel is configured for Input Capture on both edges.
18976 * 0b0100..Timer Channel is configured for Output Compare - software only.
18977 * 0b0101..Timer Channel is configured for Output Compare - toggle output on compare.
18978 * 0b0110..Timer Channel is configured for Output Compare - clear output on compare.
18979 * 0b0111..Timer Channel is configured for Output Compare - set output on compare.
18980 * 0b1000..Reserved
18981 * 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
18982 * 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
18983 * 0b110x..Reserved
18984 * 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle.
18985 * 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle.
18986 */
18987#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
18988#define ENET_TCSR_TIE_MASK (0x40U)
18989#define ENET_TCSR_TIE_SHIFT (6U)
18990/*! TIE - Timer Interrupt Enable
18991 * 0b0..Interrupt is disabled
18992 * 0b1..Interrupt is enabled
18993 */
18994#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
18995#define ENET_TCSR_TF_MASK (0x80U)
18996#define ENET_TCSR_TF_SHIFT (7U)
18997/*! TF - Timer Flag
18998 * 0b0..Input Capture or Output Compare has not occurred.
18999 * 0b1..Input Capture or Output Compare has occurred.
19000 */
19001#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
19002/*! @} */
19003
19004/* The count of ENET_TCSR */
19005#define ENET_TCSR_COUNT (4U)
19006
19007/*! @name TCCR - Timer Compare Capture Register */
19008/*! @{ */
19009#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
19010#define ENET_TCCR_TCC_SHIFT (0U)
19011#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
19012/*! @} */
19013
19014/* The count of ENET_TCCR */
19015#define ENET_TCCR_COUNT (4U)
19016
19017
19018/*!
19019 * @}
19020 */ /* end of group ENET_Register_Masks */
19021
19022
19023/* ENET - Peripheral instance base addresses */
19024/** Peripheral ENET base address */
19025#define ENET_BASE (0x30BE0000u)
19026/** Peripheral ENET base pointer */
19027#define ENET ((ENET_Type *)ENET_BASE)
19028/** Array initializer of ENET peripheral base addresses */
19029#define ENET_BASE_ADDRS { ENET_BASE }
19030/** Array initializer of ENET peripheral base pointers */
19031#define ENET_BASE_PTRS { ENET }
19032/** Interrupt vectors for the ENET peripheral type */
19033#define ENET_Transmit_IRQS { ENET_IRQn }
19034#define ENET_Receive_IRQS { ENET_IRQn }
19035#define ENET_Error_IRQS { ENET_IRQn }
19036#define ENET_1588_Timer_IRQS { ENET_IRQn }
19037/* ENET Buffer Descriptor and Buffer Address Alignment. */
19038#define ENET_BUFF_ALIGNMENT (64U)
19039
19040
19041/*!
19042 * @}
19043 */ /* end of group ENET_Peripheral_Access_Layer */
19044
19045
19046/* ----------------------------------------------------------------------------
19047 -- FlexSPI Peripheral Access Layer
19048 ---------------------------------------------------------------------------- */
19049
19050/*!
19051 * @addtogroup FlexSPI_Peripheral_Access_Layer FlexSPI Peripheral Access Layer
19052 * @{
19053 */
19054
19055/** FlexSPI - Register Layout Typedef */
19056typedef struct {
19057 __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */
19058 __IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */
19059 __IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */
19060 __IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */
19061 __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */
19062 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */
19063 __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */
19064 __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */
19065 __IO uint32_t AHBRXBUFCR0[8]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */
19066 uint8_t RESERVED_0[32];
19067 __IO uint32_t FLSHCR0[4]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */
19068 __IO uint32_t FLSHCR1[4]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */
19069 __IO uint32_t FLSHCR2[4]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */
19070 uint8_t RESERVED_1[4];
19071 __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */
19072 uint8_t RESERVED_2[8];
19073 __IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */
19074 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */
19075 uint8_t RESERVED_3[8];
19076 __IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */
19077 __IO uint32_t DLPR; /**< Data Learn Pattern Register, offset: 0xB4 */
19078 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */
19079 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */
19080 __IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */
19081 uint8_t RESERVED_4[24];
19082 __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */
19083 __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */
19084 __I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */
19085 __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */
19086 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */
19087 __I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */
19088 uint8_t RESERVED_5[8];
19089 __I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */
19090 __O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */
19091 __IO uint32_t LUT[128]; /**< LUT 0..LUT 127, array offset: 0x200, array step: 0x4 */
19092} FlexSPI_Type;
19093
19094/* ----------------------------------------------------------------------------
19095 -- FlexSPI Register Masks
19096 ---------------------------------------------------------------------------- */
19097
19098/*!
19099 * @addtogroup FlexSPI_Register_Masks FlexSPI Register Masks
19100 * @{
19101 */
19102
19103/*! @name MCR0 - Module Control Register 0 */
19104/*! @{ */
19105#define FlexSPI_MCR0_SWRESET_MASK (0x1U)
19106#define FlexSPI_MCR0_SWRESET_SHIFT (0U)
19107#define FlexSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_SWRESET_SHIFT)) & FlexSPI_MCR0_SWRESET_MASK)
19108#define FlexSPI_MCR0_MDIS_MASK (0x2U)
19109#define FlexSPI_MCR0_MDIS_SHIFT (1U)
19110#define FlexSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_MDIS_SHIFT)) & FlexSPI_MCR0_MDIS_MASK)
19111#define FlexSPI_MCR0_RXCLKSRC_MASK (0x30U)
19112#define FlexSPI_MCR0_RXCLKSRC_SHIFT (4U)
19113/*! RXCLKSRC - Sample Clock source selection for Flash Reading
19114 * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
19115 * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
19116 * 0b10..Reserved
19117 * 0b11..Flash provided Read strobe and input from DQS pad
19118 */
19119#define FlexSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_RXCLKSRC_SHIFT)) & FlexSPI_MCR0_RXCLKSRC_MASK)
19120#define FlexSPI_MCR0_ARDFEN_MASK (0x40U)
19121#define FlexSPI_MCR0_ARDFEN_SHIFT (6U)
19122/*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO.
19123 * 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response.
19124 * 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
19125 */
19126#define FlexSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_ARDFEN_SHIFT)) & FlexSPI_MCR0_ARDFEN_MASK)
19127#define FlexSPI_MCR0_ATDFEN_MASK (0x80U)
19128#define FlexSPI_MCR0_ATDFEN_SHIFT (7U)
19129/*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO.
19130 * 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response.
19131 * 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
19132 */
19133#define FlexSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_ATDFEN_SHIFT)) & FlexSPI_MCR0_ATDFEN_MASK)
19134#define FlexSPI_MCR0_SERCLKDIV_MASK (0x700U)
19135#define FlexSPI_MCR0_SERCLKDIV_SHIFT (8U)
19136/*! SERCLKDIV - The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking.
19137 * 0b000..Divided by 1
19138 * 0b001..Divided by 2
19139 * 0b010..Divided by 3
19140 * 0b011..Divided by 4
19141 * 0b100..Divided by 5
19142 * 0b101..Divided by 6
19143 * 0b110..Divided by 7
19144 * 0b111..Divided by 8
19145 */
19146#define FlexSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_SERCLKDIV_SHIFT)) & FlexSPI_MCR0_SERCLKDIV_MASK)
19147#define FlexSPI_MCR0_HSEN_MASK (0x800U)
19148#define FlexSPI_MCR0_HSEN_SHIFT (11U)
19149/*! HSEN - Half Speed Serial Flash access Enable.
19150 * 0b0..Disable divide by 2 of serial flash clock for half speed commands.
19151 * 0b1..Enable divide by 2 of serial flash clock for half speed commands.
19152 */
19153#define FlexSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_HSEN_SHIFT)) & FlexSPI_MCR0_HSEN_MASK)
19154#define FlexSPI_MCR0_DOZEEN_MASK (0x1000U)
19155#define FlexSPI_MCR0_DOZEEN_SHIFT (12U)
19156/*! DOZEEN - Doze mode enable bit
19157 * 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
19158 * 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
19159 */
19160#define FlexSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_DOZEEN_SHIFT)) & FlexSPI_MCR0_DOZEEN_MASK)
19161#define FlexSPI_MCR0_COMBINATIONEN_MASK (0x2000U)
19162#define FlexSPI_MCR0_COMBINATIONEN_SHIFT (13U)
19163/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]).
19164 * 0b0..Disable.
19165 * 0b1..Enable.
19166 */
19167#define FlexSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_COMBINATIONEN_SHIFT)) & FlexSPI_MCR0_COMBINATIONEN_MASK)
19168#define FlexSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)
19169#define FlexSPI_MCR0_SCKFREERUNEN_SHIFT (14U)
19170/*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications,
19171 * external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is
19172 * enabled, data sampling with loopback