1 files changed, 65947 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/MIMX8MM2_cm4.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/MIMX8MM2_cm4.h
new file mode 100644
index 000000000..8127cbdd8
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MM2/MIMX8MM2_cm4.h
@@ -0,0 +1,65947 @@
+/*
+** ###################################################################
+**     Processors:          MIMX8MM2CVTKZ
+**                          MIMX8MM2DVTLZ
+**
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**
+**     Reference manual:    MX8MMRM, Rev. 0, 02/2019
+**     Version:             rev. 4.0, 2019-02-18
+**     Build:               b190228
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MIMX8MM2_cm4
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2019 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2018-03-26)
+**         Initial version.
+**     - rev. 2.0 (2018-07-20)
+**         Rev.A Header EAR
+**     - rev. 3.0 (2018-10-24)
+**         Rev.B Header PRC
+**     - rev. 4.0 (2019-02-18)
+**         Rev.0 Header RFP
+**
+** ###################################################################
+*/
+/*!
+ * @file MIMX8MM2_cm4.h
+ * @version 4.0
+ * @date 2019-02-18
+ * @brief CMSIS Peripheral Access Layer for MIMX8MM2_cm4
+ *
+ * CMSIS Peripheral Access Layer for MIMX8MM2_cm4
+ */
+#ifndef _MIMX8MM2_CM4_H_
+#define _MIMX8MM2_CM4_H_                         /**< Symbol preventing repeated inclusion */
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0400U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 144                /**< Number of interrupts in the Vector table */
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+  /* Device specific interrupts */
+  GPR_IRQ_IRQn                 = 0,                /**< GPR Interrupt. Used to notify cores on exception condition while boot. */
+  DAP_IRQn                     = 1,                /**< DAP Interrupt */
+  SDMA1_IRQn                   = 2,                /**< AND of all 48 SDMA1 interrupts (events) from all the channels */
+  GPU3D_IRQn                   = 3,                /**< GPU3D Interrupt */
+  SNVS_IRQn                    = 4,                /**< ON-OFF button press shorter than 5 seconds (pulse event) */
+  LCDIF_IRQn                   = 5,                /**< LCDIF Interrupt */
+  SPDIF1_IRQn                  = 6,                /**< SPDIF1 RZX/TX Interrupt */
+  VPU_G1_IRQn                  = 7,                /**< VPU G1 Decoder Interrupt */
+  VPU_G2_IRQn                  = 8,                /**< VPU G2 Decoder Interrupt */
+  QOS_IRQn                     = 9,                /**< QOS interrupt */
+  WDOG3_IRQn                   = 10,               /**< Watchdog Timer reset */
+  HS_CP1_IRQn                  = 11,               /**< HS Interrupt Request */
+  APBHDMA_IRQn                 = 12,               /**< GPMI operation channel 0-3 description complete interrupt */
+  Reserved29_IRQn              = 13,               /**< Reserved */
+  BCH_IRQn                     = 14,               /**< BCH operation complete interrupt */
+  GPMI_IRQn                    = 15,               /**< GPMI operation TIMEOUT ERROR interrupt */
+  CSI1_IRQn                    = 16,               /**< CSI Interrupt */
+  MIPI_CSI1_IRQn               = 17,               /**< MIPI CSI Interrupt */
+  MIPI_DSI_IRQn                = 18,               /**< MIPI DSI Interrupt */
+  SNVS_Consolidated_IRQn       = 19,               /**< SRTC Consolidated Interrupt. Non TZ. */
+  SNVS_Security_IRQn           = 20,               /**< SRTC Security Interrupt. TZ. */
+  CSU_IRQn                     = 21,               /**< CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted. */
+  USDHC1_IRQn                  = 22,               /**< uSDHC1 Enhanced SDHC Interrupt Request */
+  USDHC2_IRQn                  = 23,               /**< uSDHC2 Enhanced SDHC Interrupt Request */
+  USDHC3_IRQn                  = 24,               /**< uSDHC3 Enhanced SDHC Interrupt Request */
+  GPU2D_IRQn                   = 25,               /**< GPU2D Interrupt */
+  UART1_IRQn                   = 26,               /**< UART-1 ORed interrupt */
+  UART2_IRQn                   = 27,               /**< UART-2 ORed interrupt */
+  UART3_IRQn                   = 28,               /**< UART-3 ORed interrupt */
+  UART4_IRQn                   = 29,               /**< UART-4 ORed interrupt */
+  VPU_H1_IRQn                  = 30,               /**< VPU H1 Encoder Interrupt */
+  ECSPI1_IRQn                  = 31,               /**< ECSPI1 interrupt request line to the core. */
+  ECSPI2_IRQn                  = 32,               /**< ECSPI2 interrupt request line to the core. */
+  ECSPI3_IRQn                  = 33,               /**< ECSPI3 interrupt request line to the core. */
+  SDMA3_IRQn                   = 34,               /**< AND of all 48 SDMA3 interrupts (events) from all the channels */
+  I2C1_IRQn                    = 35,               /**< I2C-1 Interrupt */
+  I2C2_IRQn                    = 36,               /**< I2C-2 Interrupt */
+  I2C3_IRQn                    = 37,               /**< I2C-3 Interrupt */
+  I2C4_IRQn                    = 38,               /**< I2C-4 Interrupt */
+  RDC_IRQn                     = 39,               /**< RDC interrupt */
+  USB1_IRQn                    = 40,               /**< USB1 Interrupt */
+  USB2_IRQn                    = 41,               /**< USB1 Interrupt */
+  Reserved58_IRQn              = 42,               /**< Reserved interrupt */
+  Reserved59_IRQn              = 43,               /**< Reserved interrupt */
+  PDM_HWVAD_EVENT_IRQn         = 44,               /**< Digital Microphone interface voice activity detector event interrupt */
+  PDM_HWVAD_ERROR_IRQn         = 45,               /**< Digital Microphone interface voice activity detector error interrupt */
+  GPT6_IRQn                    = 46,               /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
+  SCTR_IRQ0_IRQn               = 47,               /**< System Counter Interrupt 0 */
+  SCTR_IRQ1_IRQn               = 48,               /**< System Counter Interrupt 1 */
+  TEMPMON_LOW_IRQn             = 49,               /**< TempSensor (Temperature low alarm). */
+  I2S3_IRQn                    = 50,               /**< SAI3 Receive / Transmit Interrupt */
+  GPT5_IRQn                    = 51,               /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
+  GPT4_IRQn                    = 52,               /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
+  GPT3_IRQn                    = 53,               /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
+  GPT2_IRQn                    = 54,               /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
+  GPT1_IRQn                    = 55,               /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
+  GPIO1_INT7_IRQn              = 56,               /**< Active HIGH Interrupt from INT7 from GPIO */
+  GPIO1_INT6_IRQn              = 57,               /**< Active HIGH Interrupt from INT6 from GPIO */
+  GPIO1_INT5_IRQn              = 58,               /**< Active HIGH Interrupt from INT5 from GPIO */
+  GPIO1_INT4_IRQn              = 59,               /**< Active HIGH Interrupt from INT4 from GPIO */
+  GPIO1_INT3_IRQn              = 60,               /**< Active HIGH Interrupt from INT3 from GPIO */
+  GPIO1_INT2_IRQn              = 61,               /**< Active HIGH Interrupt from INT2 from GPIO */
+  GPIO1_INT1_IRQn              = 62,               /**< Active HIGH Interrupt from INT1 from GPIO */
+  GPIO1_INT0_IRQn              = 63,               /**< Active HIGH Interrupt from INT0 from GPIO */
+  GPIO1_Combined_0_15_IRQn     = 64,               /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
+  GPIO1_Combined_16_31_IRQn    = 65,               /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
+  GPIO2_Combined_0_15_IRQn     = 66,               /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
+  GPIO2_Combined_16_31_IRQn    = 67,               /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
+  GPIO3_Combined_0_15_IRQn     = 68,               /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
+  GPIO3_Combined_16_31_IRQn    = 69,               /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
+  GPIO4_Combined_0_15_IRQn     = 70,               /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */
+  GPIO4_Combined_16_31_IRQn    = 71,               /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */
+  GPIO5_Combined_0_15_IRQn     = 72,               /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
+  GPIO5_Combined_16_31_IRQn    = 73,               /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
+  Reserved90_IRQn              = 74,               /**< Reserved interrupt */
+  Reserved91_IRQn              = 75,               /**< Reserved interrupt */
+  Reserved92_IRQn              = 76,               /**< Reserved interrupt */
+  Reserved93_IRQn              = 77,               /**< Reserved interrupt */
+  WDOG1_IRQn                   = 78,               /**< Watchdog Timer reset */
+  WDOG2_IRQn                   = 79,               /**< Watchdog Timer reset */
+  Reserved96_IRQn              = 80,               /**< Reserved interrupt */
+  PWM1_IRQn                    = 81,               /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
+  PWM2_IRQn                    = 82,               /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
+  PWM3_IRQn                    = 83,               /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
+  PWM4_IRQn                    = 84,               /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
+  CCM_IRQ1_IRQn                = 85,               /**< CCM Interrupt Request 1 */
+  CCM_IRQ2_IRQn                = 86,               /**< CCM Interrupt Request 2 */
+  GPC_IRQn                     = 87,               /**< GPC Interrupt Request 1 */
+  MU_A53_IRQn                  = 88,               /**< Interrupt to A53 */
+  SRC_IRQn                     = 89,               /**< SRC interrupt request */
+  I2S56_IRQn                   = 90,               /**< SAI5/6 Receive / Transmit Interrupt */
+  RTIC_IRQn                    = 91,               /**< RTIC Interrupt */
+  CPU_PerformanceUnit_IRQn     = 92,               /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n] */
+  CPU_CTI_Trigger_IRQn         = 93,               /**< CTI trigger outputs (internal: nCTIIRQ[n] */
+  SRC_Combined_IRQn            = 94,               /**< Combined CPU wdog interrupts (4x) out of SRC. */
+  I2S1_IRQn                    = 95,               /**< SAI1 Receive / Transmit Interrupt */
+  I2S2_IRQn                    = 96,               /**< SAI2 Receive / Transmit Interrupt */
+  MU_M4_IRQn                   = 97,               /**< Interrupt to M4 */
+  DDR_PerformanceMonitor_IRQn  = 98,               /**< ddr Interrupt for performance monitor */
+  DDR_IRQn                     = 99,               /**< ddr Interrupt */
+  Reserved116_IRQn             = 100,              /**< Reserved interrupt */
+  CPU_Error_AXI_IRQn           = 101,              /**< CPU Error indicator for AXI transaction with a write response error condition */
+  CPU_Error_L2RAM_IRQn         = 102,              /**< CPU Error indicator for L2 RAM double-bit ECC error */
+  SDMA2_IRQn                   = 103,              /**< AND of all 48 SDMA2 interrupts (events) from all the channels */
+  SJC_IRQn                     = 104,              /**< Interrupt triggered by SJC register */
+  CAAM_IRQ0_IRQn               = 105,              /**< CAAM interrupt queue for JQ */
+  CAAM_IRQ1_IRQn               = 106,              /**< CAAM interrupt queue for JQ */
+  QSPI_IRQn                    = 107,              /**< QSPI Interrupt */
+  TZASC_IRQn                   = 108,              /**< TZASC (PL380) interrupt */
+  PDM_EVENT_IRQn               = 109,              /**< Digital Microphone interface interrupt */
+  PDM_ERROR_IRQn               = 110,              /**< Digital Microphone interface error interrupt */
+  Reserved127_IRQn             = 111,              /**< Reserved interrupt */
+  PERFMON1_IRQn                = 112,              /**< General Interrupt */
+  PERFMON2_IRQn                = 113,              /**< General Interrupt */
+  CAAM_IRQ2_IRQn               = 114,              /**< CAAM interrupt queue for JQ */
+  CAAM_ERROR_IRQn              = 115,              /**< Recoverable error interrupt */
+  HS_CP0_IRQn                  = 116,              /**< HS Interrupt Request */
+  Reserved133_IRQn             = 117,              /**< Reserved interrupt */
+  ENET_MAC0_Rx_Tx_Done1_IRQn   = 118,              /**< MAC 0 Receive / Trasmit Frame / Buffer Done */
+  ENET_MAC0_Rx_Tx_Done2_IRQn   = 119,              /**< MAC 0 Receive / Trasmit Frame / Buffer Done */
+  ENET_IRQn                    = 120,              /**< MAC 0 IRQ */
+  ENET_1588_IRQn               = 121,              /**< MAC 0 1588 Timer Interrupt - synchronous */
+  PCIE_CTRL1_IRQ0_IRQn         = 122,              /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
+  PCIE_CTRL1_IRQ1_IRQn         = 123,              /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
+  PCIE_CTRL1_IRQ2_IRQn         = 124,              /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
+  PCIE_CTRL1_IRQ3_IRQn         = 125,              /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
+  Reserved142_IRQn             = 126,              /**< Reserved */
+  PCIE_CTRL1_IRQn              = 127               /**< Channels [63:32] interrupts requests */
+} IRQn_Type;
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_MIMX8MM2_cm4.h"       /* Device specific configuration file */
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+/** Mapping Information */
+/*!
+ * @addtogroup iomuxc_pads
+ * @{ */
+/*******************************************************************************
+ * Definitions
+*******************************************************************************/
+/*!
+ * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
+ *
+ * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
+ */
+typedef enum _iomuxc_sw_mux_ctl_pad
+{
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 = 0U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 = 1U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 = 2U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 = 3U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 = 4U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 = 5U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 = 6U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 = 7U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 = 8U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 = 9U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 = 10U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 = 11U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 = 12U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13 = 13U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 = 14U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 = 15U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_MDC = 16U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_MDIO = 17U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_TD3 = 18U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_TD2 = 19U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_TD1 = 20U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_TD0 = 21U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL = 22U,      /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_TXC = 23U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL = 24U,      /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_RXC = 25U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_RD0 = 26U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_RD1 = 27U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_RD2 = 28U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_RD3 = 29U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_CLK  = 30U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_CMD  = 31U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 = 32U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 = 33U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 = 34U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 = 35U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA4 = 36U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA5 = 37U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA6 = 38U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA7 = 39U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B = 40U,      /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_STROBE = 41U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD2_CD_B = 42U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD2_CLK  = 43U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD2_CMD  = 44U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 = 45U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 = 46U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 = 47U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 = 48U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B = 49U,      /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD2_WP   = 50U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_ALE = 51U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B = 52U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B = 53U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B = 54U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B = 55U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_CLE = 56U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 = 57U,      /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 = 58U,      /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 = 59U,      /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 = 60U,      /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 = 61U,      /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 = 62U,      /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 = 63U,      /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 = 64U,      /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_DQS = 65U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_RE_B = 66U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_READY_B = 67U,     /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_WE_B = 68U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_WP_B = 69U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS = 70U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXC = 71U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0 = 72U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1 = 73U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2 = 74U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3 = 75U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK = 76U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXFS = 77U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXC = 78U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD0 = 79U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD1 = 80U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD2 = 81U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD3 = 82U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD4 = 83U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD5 = 84U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD6 = 85U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD7 = 86U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXFS = 87U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXC = 88U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD0 = 89U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD1 = 90U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD2 = 91U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD3 = 92U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD4 = 93U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD5 = 94U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD6 = 95U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD7 = 96U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK = 97U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS = 98U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXC = 99U,         /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0 = 100U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS = 101U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXC = 102U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0 = 103U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI2_MCLK = 104U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS = 105U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXC = 106U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXD = 107U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS = 108U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXC = 109U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXD = 110U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK = 111U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SPDIF_TX = 112U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SPDIF_RX = 113U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK = 114U,   /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK = 115U,     /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI = 116U,     /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO = 117U,     /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 = 118U,      /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK = 119U,     /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI = 120U,     /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO = 121U,     /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 = 122U,      /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_I2C1_SCL = 123U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_I2C1_SDA = 124U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_I2C2_SCL = 125U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_I2C2_SDA = 126U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_I2C3_SCL = 127U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_I2C3_SDA = 128U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_I2C4_SCL = 129U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_I2C4_SDA = 130U,        /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_UART1_RXD = 131U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_UART1_TXD = 132U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_UART2_RXD = 133U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_UART2_TXD = 134U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_UART3_RXD = 135U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_UART3_TXD = 136U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_UART4_RXD = 137U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_UART4_TXD = 138U,       /**< IOMUXC SW_MUX_CTL_PAD index */
+} iomuxc_sw_mux_ctl_pad_t;
+/*!
+ * @addtogroup iomuxc_pads
+ * @{ */
+/*******************************************************************************
+ * Definitions
+*******************************************************************************/
+/*!
+ * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
+ *
+ * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
+ */
+typedef enum _iomuxc_sw_pad_ctl_pad
+{
+    kIOMUXC_SW_PAD_CTL_PAD_TEST_MODE = 0U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 = 1U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 = 2U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_JTAG_MOD = 3U,          /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B = 4U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDI = 5U,          /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_JTAG_TMS = 6U,          /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_JTAG_TCK = 7U,          /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDO = 8U,          /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_RTC      = 9U,          /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ = 10U,    /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ = 11U,      /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ONOFF    = 12U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_POR_B    = 13U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_RTC_RESET_B = 14U,      /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 = 15U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 = 16U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 = 17U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 = 18U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 = 19U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 = 20U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 = 21U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 = 22U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 = 23U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 = 24U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10 = 25U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11 = 26U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 = 27U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13 = 28U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14 = 29U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15 = 30U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_MDC = 31U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_MDIO = 32U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_TD3 = 33U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_TD2 = 34U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_TD1 = 35U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_TD0 = 36U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_TX_CTL = 37U,      /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_TXC = 38U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_RX_CTL = 39U,      /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_RXC = 40U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_RD0 = 41U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_RD1 = 42U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_RD2 = 43U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_RD3 = 44U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_CLK  = 45U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_CMD  = 46U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 = 47U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 = 48U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 = 49U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 = 50U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA4 = 51U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA5 = 52U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA6 = 53U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA7 = 54U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B = 55U,      /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_STROBE = 56U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD2_CD_B = 57U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD2_CLK  = 58U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD2_CMD  = 59U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 = 60U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 = 61U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 = 62U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 = 63U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B = 64U,      /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD2_WP   = 65U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_ALE = 66U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B = 67U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B = 68U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_CE2_B = 69U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_CE3_B = 70U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_CLE = 71U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 = 72U,      /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 = 73U,      /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 = 74U,      /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 = 75U,      /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 = 76U,      /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 = 77U,      /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 = 78U,      /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 = 79U,      /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_DQS = 80U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_RE_B = 81U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_READY_B = 82U,     /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_WE_B = 83U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_WP_B = 84U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXFS = 85U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXC = 86U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD0 = 87U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD1 = 88U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD2 = 89U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD3 = 90U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI5_MCLK = 91U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXFS = 92U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXC = 93U,         /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD0 = 94U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD1 = 95U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD2 = 96U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD3 = 97U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD4 = 98U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD5 = 99U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD6 = 100U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD7 = 101U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXFS = 102U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXC = 103U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD0 = 104U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD1 = 105U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD2 = 106U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD3 = 107U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD4 = 108U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD5 = 109U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD6 = 110U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD7 = 111U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK = 112U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXFS = 113U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXC = 114U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXD0 = 115U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXFS = 116U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXC = 117U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXD0 = 118U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI2_MCLK = 119U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXFS = 120U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXC = 121U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXD = 122U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXFS = 123U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXC = 124U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXD = 125U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI3_MCLK = 126U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SPDIF_TX = 127U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SPDIF_RX = 128U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SPDIF_EXT_CLK = 129U,   /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK = 130U,     /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI = 131U,     /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO = 132U,     /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0 = 133U,      /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK = 134U,     /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI = 135U,     /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO = 136U,     /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0 = 137U,      /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_I2C1_SCL = 138U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_I2C1_SDA = 139U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_I2C2_SCL = 140U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_I2C2_SDA = 141U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_I2C3_SCL = 142U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_I2C3_SDA = 143U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_I2C4_SCL = 144U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_I2C4_SDA = 145U,        /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_UART1_RXD = 146U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_UART1_TXD = 147U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_UART2_RXD = 148U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_UART2_TXD = 149U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_UART3_RXD = 150U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_UART3_TXD = 151U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_UART4_RXD = 152U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_UART4_TXD = 153U,       /**< IOMUXC SW_PAD_CTL_PAD index */
+} iomuxc_sw_pad_ctl_pad_t;
+/* @} */
+/*!
+ * @brief Enumeration for the IOMUXC select input
+ *
+ * Defines the enumeration for the IOMUXC select input collections.
+ */
+typedef enum _iomuxc_select_input
+{
+    kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 0U,      /**< IOMUXC select input index */
+    kIOMUXC_ENET1_MDIO_SELECT_INPUT = 1U,          /**< IOMUXC select input index */
+    kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 2U,        /**< IOMUXC select input index */
+    kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 3U,        /**< IOMUXC select input index */
+    kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 4U,        /**< IOMUXC select input index */
+    kIOMUXC_SAI5_RX_BCLK_SELECT_INPUT = 5U,        /**< IOMUXC select input index */
+    kIOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 = 6U,      /**< IOMUXC select input index */
+    kIOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 = 7U,      /**< IOMUXC select input index */
+    kIOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 = 8U,      /**< IOMUXC select input index */
+    kIOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 = 9U,      /**< IOMUXC select input index */
+    kIOMUXC_SAI5_RX_SYNC_SELECT_INPUT = 10U,       /**< IOMUXC select input index */
+    kIOMUXC_SAI5_TX_BCLK_SELECT_INPUT = 11U,       /**< IOMUXC select input index */
+    kIOMUXC_SAI5_TX_SYNC_SELECT_INPUT = 12U,       /**< IOMUXC select input index */
+    kIOMUXC_UART1_RTS_B_SELECT_INPUT = 13U,        /**< IOMUXC select input index */
+    kIOMUXC_UART1_RXD_SELECT_INPUT  = 14U,         /**< IOMUXC select input index */
+    kIOMUXC_UART2_RTS_B_SELECT_INPUT = 15U,        /**< IOMUXC select input index */
+    kIOMUXC_UART2_RXD_SELECT_INPUT  = 16U,         /**< IOMUXC select input index */
+    kIOMUXC_UART3_RTS_B_SELECT_INPUT = 17U,        /**< IOMUXC select input index */
+    kIOMUXC_UART3_RXD_SELECT_INPUT  = 18U,         /**< IOMUXC select input index */
+    kIOMUXC_UART4_RTS_B_SELECT_INPUT = 19U,        /**< IOMUXC select input index */
+    kIOMUXC_UART4_RXD_SELECT_INPUT  = 20U,         /**< IOMUXC select input index */
+    kIOMUXC_SAI6_RX_BCLK_SELECT_INPUT = 21U,       /**< IOMUXC select input index */
+    kIOMUXC_SAI6_RX_DATA_SELECT_INPUT_0 = 22U,     /**< IOMUXC select input index */
+    kIOMUXC_SAI6_RX_SYNC_SELECT_INPUT = 23U,       /**< IOMUXC select input index */
+    kIOMUXC_SAI6_TX_BCLK_SELECT_INPUT = 24U,       /**< IOMUXC select input index */
+    kIOMUXC_SAI6_TX_SYNC_SELECT_INPUT = 25U,       /**< IOMUXC select input index */
+    kIOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT = 26U,     /**< IOMUXC select input index */
+    kIOMUXC_SAI5_MCLK_SELECT_INPUT  = 28U,         /**< IOMUXC select input index */
+    kIOMUXC_SAI6_MCLK_SELECT_INPUT  = 29U,         /**< IOMUXC select input index */
+    kIOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 = 30U,   /**< IOMUXC select input index */
+    kIOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 = 31U,   /**< IOMUXC select input index */
+    kIOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 = 32U,   /**< IOMUXC select input index */
+    kIOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 = 33U,   /**< IOMUXC select input index */
+    kIOMUXC_USDHC3_CD_B_SELECT_INPUT = 34U,        /**< IOMUXC select input index */
+    kIOMUXC_USDHC3_WP_SELECT_INPUT  = 35U,         /**< IOMUXC select input index */
+} iomuxc_select_input_t;
+/*!
+ * @addtogroup rdc_mapping
+ * @{
+ */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!
+ * @brief Structure for the RDC mapping
+ *
+ * Defines the structure for the RDC resource collections.
+ */
+typedef enum _rdc_master
+{
+    kRDC_Master_A53                 = 0U,          /**< ARM Cortex-A53 RDC Master */
+    kRDC_Master_M4                  = 1U,          /**< ARM Cortex-M4 RDC Master */
+    kRDC_Master_PCIE_CTRL1          = 2U,          /**< PCIE CTRL1 RDC Master */
+    kRDC_Master_SDMA3_PERIPH        = 3U,          /**< SDMA3 PERIPHERAL RDC Master */
+    kRDC_Master_VPU                 = 4U,          /**< VPU RDC Master */
+    kRDC_Master_LCDIF               = 5U,          /**< LCDIF RDC Master */
+    kRDC_Master_CSI                 = 6U,          /**< CSI PORT RDC Master */
+    kRDC_Master_SDMA3_BURST         = 7U,          /**< SDMA3 BURST RDC Master */
+    kRDC_Master_Coresight           = 8U,          /**< CORESIGHT RDC Master */
+    kRDC_Master_DAP                 = 9U,          /**< DAP RDC Master */
+    kRDC_Master_CAAM                = 10U,         /**< CAAM RDC Master */
+    kRDC_Master_SDMA1_PERIPH        = 11U,         /**< SDMA1 PERIPHERAL RDC Master */
+    kRDC_Master_SDMA1_BURST         = 12U,         /**< SDMA1 BURST RDC Master */
+    kRDC_Master_APBHDMA             = 13U,         /**< APBH DMA RDC Master */
+    kRDC_Master_RAWNAND             = 14U,         /**< RAW NAND RDC Master */
+    kRDC_Master_USDHC1              = 15U,         /**< USDHC1 RDC Master */
+    kRDC_Master_USDHC2              = 16U,         /**< USDHC2 RDC Master */
+    kRDC_Master_USDHC3              = 17U,         /**< USDHC3 RDC Master */
+    kRDC_Master_GPU                 = 18U,         /**< GPU RDC Master */
+    kRDC_Master_USB1                = 19U,         /**< USB1 RDC Master */
+    kRDC_Master_USB2                = 20U,         /**< USB2 RDC Master */
+    kRDC_Master_TESTPORT            = 21U,         /**< TESTPORT RDC Master */
+    kRDC_Master_ENET1TX             = 22U,         /**< ENET1 TX RDC Master */
+    kRDC_Master_ENET1RX             = 23U,         /**< ENET1 RX RDC Master */
+    kRDC_Master_SDMA2_PERIPH        = 24U,         /**< SDMA2 PERIPH RDC Master */
+    kRDC_Master_SDMA2_BURST         = 24U,         /**< SDMA2 BURST RDC Master */
+    kRDC_Master_SDMA2_SPBA2         = 24U,         /**< SDMA2 to SPBA2 RDC Master */
+    kRDC_Master_SDMA3_SPBA2         = 25U,         /**< SDMA3 to SPBA2 RDC Master */
+    kRDC_Master_SDMA1_SPBA1         = 26U,         /**< SDMA1 to SPBA1 RDC Master */
+} rdc_master_t;
+typedef enum _rdc_mem
+{
+    kRDC_Mem_MRC0_0                 = 0U,          /**< MMDC/DRAM. Region resolution 4KB. */
+    kRDC_Mem_MRC0_1                 = 1U,
+    kRDC_Mem_MRC0_2                 = 2U,
+    kRDC_Mem_MRC0_3                 = 3U,
+    kRDC_Mem_MRC0_4                 = 4U,
+    kRDC_Mem_MRC0_5                 = 5U,
+    kRDC_Mem_MRC0_6                 = 6U,
+    kRDC_Mem_MRC0_7                 = 7U,
+    kRDC_Mem_MRC1_0                 = 8U,          /**< QSPI. Region resolution 4KB. */
+    kRDC_Mem_MRC1_1                 = 9U,
+    kRDC_Mem_MRC1_2                 = 10U,
+    kRDC_Mem_MRC1_3                 = 11U,
+    kRDC_Mem_MRC1_4                 = 12U,
+    kRDC_Mem_MRC1_5                 = 13U,
+    kRDC_Mem_MRC1_6                 = 14U,
+    kRDC_Mem_MRC1_7                 = 15U,
+    kRDC_Mem_MRC2_0                 = 16U,         /**< PCIE1. Region resolution 4KB. */
+    kRDC_Mem_MRC2_1                 = 17U,
+    kRDC_Mem_MRC2_2                 = 18U,
+    kRDC_Mem_MRC2_3                 = 19U,
+    kRDC_Mem_MRC2_4                 = 20U,
+    kRDC_Mem_MRC2_5                 = 21U,
+    kRDC_Mem_MRC2_6                 = 22U,
+    kRDC_Mem_MRC2_7                 = 23U,
+    kRDC_Mem_MRC3_0                 = 24U,         /**< OCRAM. Region resolution 128B. */
+    kRDC_Mem_MRC3_1                 = 25U,
+    kRDC_Mem_MRC3_2                 = 26U,
+    kRDC_Mem_MRC3_3                 = 27U,
+    kRDC_Mem_MRC3_4                 = 28U,
+    kRDC_Mem_MRC4_0                 = 29U,         /**< OCRAM_S. Region resolution 128B. */
+    kRDC_Mem_MRC4_1                 = 30U,
+    kRDC_Mem_MRC4_2                 = 31U,
+    kRDC_Mem_MRC4_3                 = 32U,
+    kRDC_Mem_MRC4_4                 = 33U,
+    kRDC_Mem_MRC5_0                 = 34U,         /**< TCM. Region resolution 128B. */
+    kRDC_Mem_MRC5_1                 = 35U,
+    kRDC_Mem_MRC5_2                 = 36U,
+    kRDC_Mem_MRC5_3                 = 37U,
+    kRDC_Mem_MRC5_4                 = 38U,
+    kRDC_Mem_MRC6_0                 = 39U,         /**< GIC. Region resolution 4KB. */
+    kRDC_Mem_MRC6_1                 = 40U,
+    kRDC_Mem_MRC6_2                 = 41U,
+    kRDC_Mem_MRC6_3                 = 42U,
+    kRDC_Mem_MRC7_0                 = 43U,         /**< GPU. Region resolution 4KB. */
+    kRDC_Mem_MRC7_1                 = 44U,
+    kRDC_Mem_MRC7_2                 = 45U,
+    kRDC_Mem_MRC7_3                 = 46U,
+    kRDC_Mem_MRC8_4                 = 47U,
+    kRDC_Mem_MRC8_5                 = 48U,
+    kRDC_Mem_MRC8_6                 = 49U,
+    kRDC_Mem_MRC8_7                 = 50U,
+    kRDC_Mem_MRC9_0                 = 51U,         /**< VPU(Decoder). Region resolution 4KB. */
+    kRDC_Mem_MRC9_1                 = 52U,
+    kRDC_Mem_MRC9_2                 = 53U,
+    kRDC_Mem_MRC9_3                 = 54U,
+    kRDC_Mem_MRC10_0                = 55U,         /**< DEBUG(DAP). Region resolution 4KB. */
+    kRDC_Mem_MRC10_1                = 56U,
+    kRDC_Mem_MRC10_2                = 57U,
+    kRDC_Mem_MRC10_3                = 58U,
+    kRDC_Mem_MRC11_0                = 59U,         /**< DDRC(REG). Region resolution 4KB. */
+    kRDC_Mem_MRC11_1                = 60U,
+    kRDC_Mem_MRC11_2                = 61U,
+    kRDC_Mem_MRC11_3                = 62U,
+    kRDC_Mem_MRC11_4                = 63U,
+} rdc_mem_t;
+typedef enum _rdc_periph
+{
+    kRDC_Periph_GPIO1               = 0U,          /**< GPIO1 RDC Peripheral */
+    kRDC_Periph_GPIO2               = 1U,          /**< GPIO2 RDC Peripheral */
+    kRDC_Periph_GPIO3               = 2U,          /**< GPIO3 RDC Peripheral */
+    kRDC_Periph_GPIO4               = 3U,          /**< GPIO4 RDC Peripheral */
+    kRDC_Periph_GPIO5               = 4U,          /**< GPIO5 RDC Peripheral */
+    kRDC_Periph_ANA_TSENSOR         = 6U,          /**< ANA_TSENSOR RDC Peripheral */
+    kRDC_Periph_ANA_OSC             = 7U,          /**< ANA_OSC RDC Peripheral */
+    kRDC_Periph_WDOG1               = 8U,          /**< WDOG1 RDC Peripheral */
+    kRDC_Periph_WDOG2               = 9U,          /**< WDOG2 RDC Peripheral */
+    kRDC_Periph_WDOG3               = 10U,         /**< WDOG3 RDC Peripheral */
+    kRDC_Periph_SDMA3               = 11U,         /**< SDMA3 RDC Peripheral */
+    kRDC_Periph_SDMA2               = 12U,         /**< SDMA2 RDC Peripheral */
+    kRDC_Periph_GPT1                = 13U,         /**< GPT1 RDC Peripheral */
+    kRDC_Periph_GPT2                = 14U,         /**< GPT2 RDC Peripheral */
+    kRDC_Periph_GPT3                = 15U,         /**< GPT3 RDC Peripheral */
+    kRDC_Periph_ROMCP               = 17U,         /**< ROMCP RDC Peripheral */
+    kRDC_Periph_IOMUXC              = 19U,         /**< IOMUXC RDC Peripheral */
+    kRDC_Periph_IOMUXC_GPR          = 20U,         /**< IOMUXC_GPR RDC Peripheral */
+    kRDC_Periph_OCOTP_CTRL          = 21U,         /**< OCOTP_CTRL RDC Peripheral */
+    kRDC_Periph_ANA_PLL             = 22U,         /**< ANA_PLL RDC Peripheral */
+    kRDC_Periph_SNVS_HP             = 23U,         /**< SNVS_HP GPR RDC Peripheral */
+    kRDC_Periph_CCM                 = 24U,         /**< CCM RDC Peripheral */
+    kRDC_Periph_SRC                 = 25U,         /**< SRC RDC Peripheral */
+    kRDC_Periph_GPC                 = 26U,         /**< GPC RDC Peripheral */
+    kRDC_Periph_SEMAPHORE1          = 27U,         /**< SEMAPHORE1 RDC Peripheral */
+    kRDC_Periph_SEMAPHORE2          = 28U,         /**< SEMAPHORE2 RDC Peripheral */
+    kRDC_Periph_RDC                 = 29U,         /**< RDC RDC Peripheral */
+    kRDC_Periph_CSU                 = 30U,         /**< CSU RDC Peripheral */
+    kRDC_Periph_LCDIF               = 32U,         /**< LCDIF RDC Peripheral */
+    kRDC_Periph_MIPI_DSI            = 33U,         /**< MIPI_DSI RDC Peripheral */
+    kRDC_Periph_CSI                 = 34U,         /**< CSI RDC Peripheral */
+    kRDC_Periph_MIPI_CSI            = 35U,         /**< MIPI_CSI RDC Peripheral */
+    kRDC_Periph_USB1                = 36U,         /**< USB1 RDC Peripheral */
+    kRDC_Periph_PWM1                = 38U,         /**< PWM1 RDC Peripheral */
+    kRDC_Periph_PWM2                = 39U,         /**< PWM2 RDC Peripheral */
+    kRDC_Periph_PWM3                = 40U,         /**< PWM3 RDC Peripheral */
+    kRDC_Periph_PWM4                = 41U,         /**< PWM4 RDC Peripheral */
+    kRDC_Periph_SYS_COUNTER_RD      = 42U,         /**< System counter read RDC Peripheral */
+    kRDC_Periph_SYS_COUNTER_CMP     = 43U,         /**< System counter compare RDC Peripheral */
+    kRDC_Periph_SYS_COUNTER_CTRL    = 44U,         /**< System counter control RDC Peripheral */
+    kRDC_Periph_GPT6                = 46U,         /**< GPT6 RDC Peripheral */
+    kRDC_Periph_GPT5                = 47U,         /**< GPT5 RDC Peripheral */
+    kRDC_Periph_GPT4                = 48U,         /**< GPT4 RDC Peripheral */
+    kRDC_Periph_TZASC               = 56U,         /**< TZASC RDC Peripheral */
+    kRDC_Periph_USB2                = 59U,         /**< USB2 RDC Peripheral */
+    kRDC_Periph_PERFMON1            = 60U,         /**< PERFMON1 RDC Peripheral */
+    kRDC_Periph_PERFMON2            = 61U,         /**< PERFMON2 RDC Peripheral */
+    kRDC_Periph_PLATFORM_CTRL       = 62U,         /**< PLATFORM_CTRL RDC Peripheral */
+    kRDC_Periph_QOSC                = 63U,         /**< QOSC RDC Peripheral */
+    kRDC_Periph_I2C1                = 66U,         /**< I2C1 RDC Peripheral */
+    kRDC_Periph_I2C2                = 67U,         /**< I2C2 RDC Peripheral */
+    kRDC_Periph_I2C3                = 68U,         /**< I2C3 RDC Peripheral */
+    kRDC_Periph_I2C4                = 69U,         /**< I2C4 RDC Peripheral */
+    kRDC_Periph_UART4               = 70U,         /**< UART4 RDC Peripheral */
+    kRDC_Periph_MU_A                = 74U,         /**< MU_A RDC Peripheral */
+    kRDC_Periph_MU_B                = 75U,         /**< MU_B RDC Peripheral */
+    kRDC_Periph_SEMAPHORE_HS        = 76U,         /**< SEMAPHORE_HS RDC Peripheral */
+    kRDC_Periph_SAI1                = 78U,         /**< SAI1 RDC Peripheral */
+    kRDC_Periph_SAI2_ACCESS         = 79U,         /**< SAI2 RDC Peripheral Access Control */
+    kRDC_Periph_SAI3_ACCESS         = 80U,         /**< SAI3 RDC Peripheral Access Control */
+    kRDC_Periph_SAI6_LPM            = 80U,         /**< SAI6 RDC Low Power Mode Control */
+    kRDC_Periph_SAI5_LPM            = 81U,         /**< SAI5 RDC Low Power Mode Control */
+    kRDC_Periph_SAI5_ACCESS         = 82U,         /**< SAI5 RDC Peripheral Access Control */
+    kRDC_Periph_SAI6_ACCESS         = 83U,         /**< SAI6 RDC Peripheral Access Control */
+    kRDC_Periph_USDHC1              = 84U,         /**< USDHC1 RDC Peripheral */
+    kRDC_Periph_USDHC2              = 85U,         /**< USDHC2 RDC Peripheral */
+    kRDC_Periph_USDHC3              = 86U,         /**< USDHC3 RDC Peripheral */
+    kRDC_Periph_PCIE_PHY1           = 88U,         /**< PCIE_PHY1 RDC Peripheral */
+    kRDC_Periph_SPBA2               = 90U,         /**< SPBA2 RDC Peripheral */
+    kRDC_Periph_QSPI                = 91U,         /**< QSPI RDC Peripheral */
+    kRDC_Periph_SDMA1               = 93U,         /**< SDMA1 RDC Peripheral */
+    kRDC_Periph_ENET1               = 94U,         /**< ENET1 RDC Peripheral */
+    kRDC_Periph_SPDIF1              = 97U,         /**< SPDIF1 RDC Peripheral */
+    kRDC_Periph_ECSPI1              = 98U,         /**< ECSPI1 RDC Peripheral */
+    kRDC_Periph_ECSPI2              = 99U,         /**< ECSPI2 RDC Peripheral */
+    kRDC_Periph_ECSPI3              = 100U,        /**< ECSPI3 RDC Peripheral */
+    kRDC_Periph_MICFIL              = 101U,        /**< MICFIL RDC Peripheral */
+    kRDC_Periph_UART1               = 102U,        /**< UART1 RDC Peripheral */
+    kRDC_Periph_UART3               = 104U,        /**< UART3 RDC Peripheral */
+    kRDC_Periph_UART2               = 105U,        /**< UART2 RDC Peripheral */
+    kRDC_Periph_SPDIF2              = 106U,        /**< SPDIF2 RDC Peripheral */
+    kRDC_Periph_SAI2_LPM            = 107U,        /**< SAI2 RDC Low Power Mode Control */
+    kRDC_Periph_SAI3_LPM            = 108U,        /**< SAI3 RDC Low Power Mode Control */
+    kRDC_Periph_SPBA1               = 111U,        /**< SPBA1 RDC Peripheral */
+    kRDC_Periph_CAAM                = 114U,        /**< CAAM RDC Peripheral */
+} rdc_periph_t;
+/* @} */
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+/*
+** Start of section using anonymous unions
+*/
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+/* ----------------------------------------------------------------------------
+   -- AIPSTZ Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
+ * @{
+ */
+/** AIPSTZ - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MPR;                               /**< Master Priviledge Registers, offset: 0x0 */
+       uint8_t RESERVED_0[60];
+  __IO uint32_t OPACR;                             /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */
+  __IO uint32_t OPACR1;                            /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */
+  __IO uint32_t OPACR2;                            /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */
+  __IO uint32_t OPACR3;                            /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */
+  __IO uint32_t OPACR4;                            /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */
+} AIPSTZ_Type;
+/* ----------------------------------------------------------------------------
+   -- AIPSTZ Register Masks
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
+ * @{
+ */
+/*! @name MPR - Master Priviledge Registers */
+/*! @{ */
+#define AIPSTZ_MPR_MPROT5_MASK                   (0xF00U)
+#define AIPSTZ_MPR_MPROT5_SHIFT                  (8U)
+/*! MPROT5
+ *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
+ *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
+ *  0bxx0x..This master is not trusted for write accesses.
+ *  0bxx1x..This master is trusted for write accesses.
+ *  0bx0xx..This master is not trusted for read accesses.
+ *  0bx1xx..This master is trusted for read accesses.
+ *  0b1xxx..Write accesses from this master are allowed to be buffered
+ */
+#define AIPSTZ_MPR_MPROT5(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
+#define AIPSTZ_MPR_MPROT3_MASK                   (0xF0000U)
+#define AIPSTZ_MPR_MPROT3_SHIFT                  (16U)
+/*! MPROT3
+ *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
+ *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
+ *  0bxx0x..This master is not trusted for write accesses.
+ *  0bxx1x..This master is trusted for write accesses.
+ *  0bx0xx..This master is not trusted for read accesses.
+ *  0bx1xx..This master is trusted for read accesses.
+ *  0b1xxx..Write accesses from this master are allowed to be buffered
+ */
+#define AIPSTZ_MPR_MPROT3(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
+#define AIPSTZ_MPR_MPROT2_MASK                   (0xF00000U)
+#define AIPSTZ_MPR_MPROT2_SHIFT                  (20U)
+/*! MPROT2
+ *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
+ *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
+ *  0bxx0x..This master is not trusted for write accesses.
+ *  0bxx1x..This master is trusted for write accesses.
+ *  0bx0xx..This master is not trusted for read accesses.
+ *  0bx1xx..This master is trusted for read accesses.
+ *  0b1xxx..Write accesses from this master are allowed to be buffered
+ */
+#define AIPSTZ_MPR_MPROT2(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
+#define AIPSTZ_MPR_MPROT1_MASK                   (0xF000000U)
+#define AIPSTZ_MPR_MPROT1_SHIFT                  (24U)
+/*! MPROT1
+ *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
+ *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
+ *  0bxx0x..This master is not trusted for write accesses.
+ *  0bxx1x..This master is trusted for write accesses.
+ *  0bx0xx..This master is not trusted for read accesses.
+ *  0bx1xx..This master is trusted for read accesses.
+ *  0b1xxx..Write accesses from this master are allowed to be buffered
+ */
+#define AIPSTZ_MPR_MPROT1(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
+#define AIPSTZ_MPR_MPROT0_MASK                   (0xF0000000U)
+#define AIPSTZ_MPR_MPROT0_SHIFT                  (28U)
+/*! MPROT0
+ *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
+ *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
+ *  0bxx0x..This master is not trusted for write accesses.
+ *  0bxx1x..This master is trusted for write accesses.
+ *  0bx0xx..This master is not trusted for read accesses.
+ *  0bx1xx..This master is trusted for read accesses.
+ *  0b1xxx..Write accesses from this master are allowed to be buffered
+ */
+#define AIPSTZ_MPR_MPROT0(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
+/*! @} */
+/*! @name OPACR - Off-Platform Peripheral Access Control Registers */
+/*! @{ */
+#define AIPSTZ_OPACR_OPAC7_MASK                  (0xFU)
+#define AIPSTZ_OPACR_OPAC7_SHIFT                 (0U)
+/*! OPAC7
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC7(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
+#define AIPSTZ_OPACR_OPAC6_MASK                  (0xF0U)
+#define AIPSTZ_OPACR_OPAC6_SHIFT                 (4U)
+/*! OPAC6
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC6(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
+#define AIPSTZ_OPACR_OPAC5_MASK                  (0xF00U)
+#define AIPSTZ_OPACR_OPAC5_SHIFT                 (8U)
+/*! OPAC5
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC5(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
+#define AIPSTZ_OPACR_OPAC4_MASK                  (0xF000U)
+#define AIPSTZ_OPACR_OPAC4_SHIFT                 (12U)
+/*! OPAC4
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC4(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
+#define AIPSTZ_OPACR_OPAC3_MASK                  (0xF0000U)
+#define AIPSTZ_OPACR_OPAC3_SHIFT                 (16U)
+/*! OPAC3
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC3(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
+#define AIPSTZ_OPACR_OPAC2_MASK                  (0xF00000U)
+#define AIPSTZ_OPACR_OPAC2_SHIFT                 (20U)
+/*! OPAC2
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC2(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
+#define AIPSTZ_OPACR_OPAC1_MASK                  (0xF000000U)
+#define AIPSTZ_OPACR_OPAC1_SHIFT                 (24U)
+/*! OPAC1
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC1(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
+#define AIPSTZ_OPACR_OPAC0_MASK                  (0xF0000000U)
+#define AIPSTZ_OPACR_OPAC0_SHIFT                 (28U)
+/*! OPAC0
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC0(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
+/*! @} */
+/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */
+/*! @{ */
+#define AIPSTZ_OPACR1_OPAC15_MASK                (0xFU)
+#define AIPSTZ_OPACR1_OPAC15_SHIFT               (0U)
+/*! OPAC15
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC15(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
+#define AIPSTZ_OPACR1_OPAC14_MASK                (0xF0U)
+#define AIPSTZ_OPACR1_OPAC14_SHIFT               (4U)
+/*! OPAC14
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC14(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
+#define AIPSTZ_OPACR1_OPAC13_MASK                (0xF00U)
+#define AIPSTZ_OPACR1_OPAC13_SHIFT               (8U)
+/*! OPAC13
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC13(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
+#define AIPSTZ_OPACR1_OPAC12_MASK                (0xF000U)
+#define AIPSTZ_OPACR1_OPAC12_SHIFT               (12U)
+/*! OPAC12
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC12(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
+#define AIPSTZ_OPACR1_OPAC11_MASK                (0xF0000U)
+#define AIPSTZ_OPACR1_OPAC11_SHIFT               (16U)
+/*! OPAC11
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC11(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
+#define AIPSTZ_OPACR1_OPAC10_MASK                (0xF00000U)
+#define AIPSTZ_OPACR1_OPAC10_SHIFT               (20U)
+/*! OPAC10
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC10(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
+#define AIPSTZ_OPACR1_OPAC9_MASK                 (0xF000000U)
+#define AIPSTZ_OPACR1_OPAC9_SHIFT                (24U)
+/*! OPAC9
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC9(x)                   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
+#define AIPSTZ_OPACR1_OPAC8_MASK                 (0xF0000000U)
+#define AIPSTZ_OPACR1_OPAC8_SHIFT                (28U)
+/*! OPAC8
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC8(x)                   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
+/*! @} */
+/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */
+/*! @{ */
+#define AIPSTZ_OPACR2_OPAC23_MASK                (0xFU)
+#define AIPSTZ_OPACR2_OPAC23_SHIFT               (0U)
+/*! OPAC23
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC23(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
+#define AIPSTZ_OPACR2_OPAC22_MASK                (0xF0U)
+#define AIPSTZ_OPACR2_OPAC22_SHIFT               (4U)
+/*! OPAC22
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC22(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
+#define AIPSTZ_OPACR2_OPAC21_MASK                (0xF00U)
+#define AIPSTZ_OPACR2_OPAC21_SHIFT               (8U)
+/*! OPAC21
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC21(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
+#define AIPSTZ_OPACR2_OPAC20_MASK                (0xF000U)
+#define AIPSTZ_OPACR2_OPAC20_SHIFT               (12U)
+/*! OPAC20
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC20(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
+#define AIPSTZ_OPACR2_OPAC19_MASK                (0xF0000U)
+#define AIPSTZ_OPACR2_OPAC19_SHIFT               (16U)
+/*! OPAC19
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC19(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
+#define AIPSTZ_OPACR2_OPAC18_MASK                (0xF00000U)
+#define AIPSTZ_OPACR2_OPAC18_SHIFT               (20U)
+/*! OPAC18
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC18(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
+#define AIPSTZ_OPACR2_OPAC17_MASK                (0xF000000U)
+#define AIPSTZ_OPACR2_OPAC17_SHIFT               (24U)
+/*! OPAC17
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC17(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
+#define AIPSTZ_OPACR2_OPAC16_MASK                (0xF0000000U)
+#define AIPSTZ_OPACR2_OPAC16_SHIFT               (28U)
+/*! OPAC16
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC16(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
+/*! @} */
+/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */
+/*! @{ */
+#define AIPSTZ_OPACR3_OPAC31_MASK                (0xFU)
+#define AIPSTZ_OPACR3_OPAC31_SHIFT               (0U)
+/*! OPAC31
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC31(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
+#define AIPSTZ_OPACR3_OPAC30_MASK                (0xF0U)
+#define AIPSTZ_OPACR3_OPAC30_SHIFT               (4U)
+/*! OPAC30
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC30(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
+#define AIPSTZ_OPACR3_OPAC29_MASK                (0xF00U)
+#define AIPSTZ_OPACR3_OPAC29_SHIFT               (8U)
+/*! OPAC29
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC29(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
+#define AIPSTZ_OPACR3_OPAC28_MASK                (0xF000U)
+#define AIPSTZ_OPACR3_OPAC28_SHIFT               (12U)
+/*! OPAC28
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC28(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
+#define AIPSTZ_OPACR3_OPAC27_MASK                (0xF0000U)
+#define AIPSTZ_OPACR3_OPAC27_SHIFT               (16U)
+/*! OPAC27
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC27(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
+#define AIPSTZ_OPACR3_OPAC26_MASK                (0xF00000U)
+#define AIPSTZ_OPACR3_OPAC26_SHIFT               (20U)
+/*! OPAC26
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC26(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
+#define AIPSTZ_OPACR3_OPAC25_MASK                (0xF000000U)
+#define AIPSTZ_OPACR3_OPAC25_SHIFT               (24U)
+/*! OPAC25
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC25(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
+#define AIPSTZ_OPACR3_OPAC24_MASK                (0xF0000000U)
+#define AIPSTZ_OPACR3_OPAC24_SHIFT               (28U)
+/*! OPAC24
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC24(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
+/*! @} */
+/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */
+/*! @{ */
+#define AIPSTZ_OPACR4_OPAC33_MASK                (0xF000000U)
+#define AIPSTZ_OPACR4_OPAC33_SHIFT               (24U)
+/*! OPAC33
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR4_OPAC33(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
+#define AIPSTZ_OPACR4_OPAC32_MASK                (0xF0000000U)
+#define AIPSTZ_OPACR4_OPAC32_SHIFT               (28U)
+/*! OPAC32
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR4_OPAC32(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
+/*! @} */
+/*!
+ * @}
+ */ /* end of group AIPSTZ_Register_Masks */
+/* AIPSTZ - Peripheral instance base addresses */
+/** Peripheral AIPSTZ base address */
+#define AIPSTZ_BASE                              (0x30000000u)
+/** Peripheral AIPSTZ base pointer */
+#define AIPSTZ                                   ((AIPSTZ_Type *)AIPSTZ_BASE)
+/** Array initializer of AIPSTZ peripheral base addresses */
+#define AIPSTZ_BASE_ADDRS                        { AIPSTZ_BASE }
+/** Array initializer of AIPSTZ peripheral base pointers */
+#define AIPSTZ_BASE_PTRS                         { AIPSTZ }
+/*!
+ * @}
+ */ /* end of group AIPSTZ_Peripheral_Access_Layer */
+/* ----------------------------------------------------------------------------
+   -- APBH Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer
+ * @{
+ */
+/** APBH - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL0;                             /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */
+  __IO uint32_t CTRL0_SET;                         /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */
+  __IO uint32_t CTRL0_CLR;                         /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */
+  __IO uint32_t CTRL0_TOG;                         /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */
+  __IO uint32_t CTRL1;                             /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */
+  __IO uint32_t CTRL1_SET;                         /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */
+  __IO uint32_t CTRL1_CLR;                         /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */
+  __IO uint32_t CTRL1_TOG;                         /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */
+  __IO uint32_t CTRL2;                             /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */
+  __IO uint32_t CTRL2_SET;                         /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */
+  __IO uint32_t CTRL2_CLR;                         /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */
+  __IO uint32_t CTRL2_TOG;                         /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */
+  __IO uint32_t CHANNEL_CTRL;                      /**< AHB to APBH Bridge Channel Register, offset: 0x30 */
+  __IO uint32_t CHANNEL_CTRL_SET;                  /**< AHB to APBH Bridge Channel Register, offset: 0x34 */
+  __IO uint32_t CHANNEL_CTRL_CLR;                  /**< AHB to APBH Bridge Channel Register, offset: 0x38 */
+  __IO uint32_t CHANNEL_CTRL_TOG;                  /**< AHB to APBH Bridge Channel Register, offset: 0x3C */
+       uint32_t DEVSEL;                            /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t DMA_BURST_SIZE;                    /**< AHB to APBH DMA burst size, offset: 0x50 */
+       uint8_t RESERVED_1[12];
+  __IO uint32_t DEBUGr;                            /**< AHB to APBH DMA Debug Register, offset: 0x60 */
+       uint8_t RESERVED_2[156];
+  struct {                                         /* offset: 0x100, array step: 0x70 */
+    __I  uint32_t CH_CURCMDAR;                       /**< APBH DMA Channel n Current Command Address Register, array offset: 0x100, array step: 0x70 */
+         uint8_t RESERVED_0[12];
+    __IO uint32_t CH_NXTCMDAR;                       /**< APBH DMA Channel n Next Command Address Register, array offset: 0x110, array step: 0x70 */
+         uint8_t RESERVED_1[12];
+    __I  uint32_t CH_CMD;                            /**< APBH DMA Channel n Command Register, array offset: 0x120, array step: 0x70 */
+         uint8_t RESERVED_2[12];
+    __I  uint32_t CH_BAR;                            /**< APBH DMA Channel n Buffer Address Register, array offset: 0x130, array step: 0x70 */
+         uint8_t RESERVED_3[12];
+    __IO uint32_t CH_SEMA;                           /**< APBH DMA Channel n Semaphore Register, array offset: 0x140, array step: 0x70 */
+         uint8_t RESERVED_4[12];
+    __I  uint32_t CH_DEBUG1;                         /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x150, array step: 0x70 */
+         uint8_t RESERVED_5[12];
+    __I  uint32_t CH_DEBUG2;                         /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */
+         uint8_t RESERVED_6[12];
+  } CH_CFGn[16];
+  __I  uint32_t VERSION;                           /**< APBH Bridge Version Register, offset: 0x800 */
+} APBH_Type;
+/* ----------------------------------------------------------------------------
+   -- APBH Register Masks
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup APBH_Register_Masks APBH Register Masks
+ * @{
+ */
+/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */
+/*! @{ */
+#define APBH_CTRL0_CLKGATE_CHANNEL_MASK          (0xFFFFU)
+#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT         (0U)
+/*! CLKGATE_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CTRL0_CLKGATE_CHANNEL(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK)
+#define APBH_CTRL0_RSVD0_MASK                    (0xFFF0000U)
+#define APBH_CTRL0_RSVD0_SHIFT                   (16U)
+#define APBH_CTRL0_RSVD0(x)                      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_RSVD0_SHIFT)) & APBH_CTRL0_RSVD0_MASK)
+#define APBH_CTRL0_APB_BURST_EN_MASK             (0x10000000U)
+#define APBH_CTRL0_APB_BURST_EN_SHIFT            (28U)
+#define APBH_CTRL0_APB_BURST_EN(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK)
+#define APBH_CTRL0_AHB_BURST8_EN_MASK            (0x20000000U)
+#define APBH_CTRL0_AHB_BURST8_EN_SHIFT           (29U)
+#define APBH_CTRL0_AHB_BURST8_EN(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK)
+#define APBH_CTRL0_CLKGATE_MASK                  (0x40000000U)
+#define APBH_CTRL0_CLKGATE_SHIFT                 (30U)
+#define APBH_CTRL0_CLKGATE(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK)
+#define APBH_CTRL0_SFTRST_MASK                   (0x80000000U)
+#define APBH_CTRL0_SFTRST_SHIFT                  (31U)
+#define APBH_CTRL0_SFTRST(x)                     (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK)
+/*! @} */
+/*! @name CTRL0_SET - AHB to APBH Bridge Control and Status Register 0 */
+/*! @{ */
+#define APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK      (0xFFFFU)
+#define APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT     (0U)
+/*! CLKGATE_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CTRL0_SET_CLKGATE_CHANNEL(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK)
+#define APBH_CTRL0_SET_RSVD0_MASK                (0xFFF0000U)
+#define APBH_CTRL0_SET_RSVD0_SHIFT               (16U)
+#define APBH_CTRL0_SET_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_RSVD0_SHIFT)) & APBH_CTRL0_SET_RSVD0_MASK)
+#define APBH_CTRL0_SET_APB_BURST_EN_MASK         (0x10000000U)
+#define APBH_CTRL0_SET_APB_BURST_EN_SHIFT        (28U)
+#define APBH_CTRL0_SET_APB_BURST_EN(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_APB_BURST_EN_SHIFT)) & APBH_CTRL0_SET_APB_BURST_EN_MASK)
+#define APBH_CTRL0_SET_AHB_BURST8_EN_MASK        (0x20000000U)
+#define APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT       (29U)
+#define APBH_CTRL0_SET_AHB_BURST8_EN(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_SET_AHB_BURST8_EN_MASK)
+#define APBH_CTRL0_SET_CLKGATE_MASK              (0x40000000U)
+#define APBH_CTRL0_SET_CLKGATE_SHIFT             (30U)
+#define APBH_CTRL0_SET_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_SHIFT)) & APBH_CTRL0_SET_CLKGATE_MASK)
+#define APBH_CTRL0_SET_SFTRST_MASK               (0x80000000U)
+#define APBH_CTRL0_SET_SFTRST_SHIFT              (31U)
+#define APBH_CTRL0_SET_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_SFTRST_SHIFT)) & APBH_CTRL0_SET_SFTRST_MASK)
+/*! @} */
+/*! @name CTRL0_CLR - AHB to APBH Bridge Control and Status Register 0 */
+/*! @{ */
+#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK      (0xFFFFU)
+#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT     (0U)
+/*! CLKGATE_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CTRL0_CLR_CLKGATE_CHANNEL(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK)
+#define APBH_CTRL0_CLR_RSVD0_MASK                (0xFFF0000U)
+#define APBH_CTRL0_CLR_RSVD0_SHIFT               (16U)
+#define APBH_CTRL0_CLR_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_RSVD0_SHIFT)) & APBH_CTRL0_CLR_RSVD0_MASK)
+#define APBH_CTRL0_CLR_APB_BURST_EN_MASK         (0x10000000U)
+#define APBH_CTRL0_CLR_APB_BURST_EN_SHIFT        (28U)
+#define APBH_CTRL0_CLR_APB_BURST_EN(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_APB_BURST_EN_SHIFT)) & APBH_CTRL0_CLR_APB_BURST_EN_MASK)
+#define APBH_CTRL0_CLR_AHB_BURST8_EN_MASK        (0x20000000U)
+#define APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT       (29U)
+#define APBH_CTRL0_CLR_AHB_BURST8_EN(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_CLR_AHB_BURST8_EN_MASK)
+#define APBH_CTRL0_CLR_CLKGATE_MASK              (0x40000000U)
+#define APBH_CTRL0_CLR_CLKGATE_SHIFT             (30U)
+#define APBH_CTRL0_CLR_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_MASK)
+#define APBH_CTRL0_CLR_SFTRST_MASK               (0x80000000U)
+#define APBH_CTRL0_CLR_SFTRST_SHIFT              (31U)
+#define APBH_CTRL0_CLR_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_SFTRST_SHIFT)) & APBH_CTRL0_CLR_SFTRST_MASK)
+/*! @} */
+/*! @name CTRL0_TOG - AHB to APBH Bridge Control and Status Register 0 */
+/*! @{ */
+#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK      (0xFFFFU)
+#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT     (0U)
+/*! CLKGATE_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CTRL0_TOG_CLKGATE_CHANNEL(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK)
+#define APBH_CTRL0_TOG_RSVD0_MASK                (0xFFF0000U)
+#define APBH_CTRL0_TOG_RSVD0_SHIFT               (16U)
+#define APBH_CTRL0_TOG_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_RSVD0_SHIFT)) & APBH_CTRL0_TOG_RSVD0_MASK)
+#define APBH_CTRL0_TOG_APB_BURST_EN_MASK         (0x10000000U)
+#define APBH_CTRL0_TOG_APB_BURST_EN_SHIFT        (28U)
+#define APBH_CTRL0_TOG_APB_BURST_EN(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_APB_BURST_EN_SHIFT)) & APBH_CTRL0_TOG_APB_BURST_EN_MASK)
+#define APBH_CTRL0_TOG_AHB_BURST8_EN_MASK        (0x20000000U)
+#define APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT       (29U)
+#define APBH_CTRL0_TOG_AHB_BURST8_EN(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_TOG_AHB_BURST8_EN_MASK)
+#define APBH_CTRL0_TOG_CLKGATE_MASK              (0x40000000U)
+#define APBH_CTRL0_TOG_CLKGATE_SHIFT             (30U)
+#define APBH_CTRL0_TOG_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_MASK)
+#define APBH_CTRL0_TOG_SFTRST_MASK               (0x80000000U)
+#define APBH_CTRL0_TOG_SFTRST_SHIFT              (31U)
+#define APBH_CTRL0_TOG_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_SFTRST_SHIFT)) & APBH_CTRL0_TOG_SFTRST_MASK)
+/*! @} */
+/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */
+/*! @{ */
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK         (0x1U)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT        (0U)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK         (0x2U)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT        (1U)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK         (0x4U)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT        (2U)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK         (0x8U)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT        (3U)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK         (0x10U)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT        (4U)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK         (0x20U)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT        (5U)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK         (0x40U)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT        (6U)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK         (0x80U)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT        (7U)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK         (0x100U)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT        (8U)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK         (0x200U)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT        (9U)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK        (0x400U)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT       (10U)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK        (0x800U)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT       (11U)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK        (0x1000U)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT       (12U)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK        (0x2000U)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT       (13U)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK        (0x4000U)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT       (14U)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK        (0x8000U)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT       (15U)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK      (0x10000U)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT     (16U)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK      (0x20000U)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT     (17U)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK      (0x40000U)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT     (18U)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK      (0x80000U)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT     (19U)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK      (0x100000U)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT     (20U)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK      (0x200000U)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT     (21U)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK      (0x400000U)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT     (22U)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK      (0x800000U)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT     (23U)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK      (0x1000000U)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT     (24U)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK      (0x2000000U)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT     (25U)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK     (0x4000000U)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT    (26U)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK     (0x8000000U)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT    (27U)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK     (0x10000000U)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT    (28U)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK     (0x20000000U)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT    (29U)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK     (0x40000000U)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT    (30U)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK     (0x80000000U)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT    (31U)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK)
+/*! @} */
+/*! @name CTRL1_SET - AHB to APBH Bridge Control and Status Register 1 */
+/*! @{ */
+#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK     (0x1U)
+#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT    (0U)
+#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK     (0x2U)
+#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT    (1U)
+#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK     (0x4U)
+#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT    (2U)
+#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK     (0x8U)
+#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT    (3U)
+#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK     (0x10U)
+#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT    (4U)
+#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK     (0x20U)
+#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT    (5U)
+#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK     (0x40U)
+#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT    (6U)
+#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK     (0x80U)
+#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT    (7U)
+#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK     (0x100U)
+#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT    (8U)
+#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK     (0x200U)
+#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT    (9U)
+#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK    (0x400U)
+#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT   (10U)
+#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK    (0x800U)
+#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT   (11U)
+#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK    (0x1000U)
+#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT   (12U)
+#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK    (0x2000U)
+#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT   (13U)
+#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK    (0x4000U)
+#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT   (14U)
+#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK    (0x8000U)
+#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT   (15U)
+#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK  (0x10000U)
+#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
+#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK  (0x20000U)
+#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
+#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK  (0x40000U)
+#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
+#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK  (0x80000U)
+#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
+#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK  (0x100000U)
+#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
+#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK  (0x200000U)
+#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
+#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK  (0x400000U)
+#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
+#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK  (0x800000U)
+#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
+#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK  (0x1000000U)
+#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
+#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK  (0x2000000U)
+#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
+#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
+#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
+#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
+#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
+#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
+#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
+#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
+#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
+#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
+#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
+#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
+#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
+#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK)
+/*! @} */
+/*! @name CTRL1_CLR - AHB to APBH Bridge Control and Status Register 1 */
+/*! @{ */
+#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK     (0x1U)
+#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT    (0U)
+#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK     (0x2U)
+#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT    (1U)
+#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK     (0x4U)
+#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT    (2U)
+#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK     (0x8U)
+#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT    (3U)
+#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK     (0x10U)
+#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT    (4U)
+#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK     (0x20U)
+#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT    (5U)
+#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK     (0x40U)
+#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT    (6U)
+#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK     (0x80U)
+#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT    (7U)
+#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK     (0x100U)
+#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT    (8U)
+#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK     (0x200U)
+#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT    (9U)
+#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK    (0x400U)
+#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT   (10U)
+#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK    (0x800U)
+#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT   (11U)
+#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK    (0x1000U)
+#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT   (12U)
+#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK    (0x2000U)
+#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT   (13U)
+#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK    (0x4000U)
+#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT   (14U)
+#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK    (0x8000U)
+#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT   (15U)
+#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK  (0x10000U)
+#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
+#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK  (0x20000U)
+#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
+#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK  (0x40000U)
+#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
+#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK  (0x80000U)
+#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
+#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK  (0x100000U)
+#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
+#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK  (0x200000U)
+#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
+#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK  (0x400000U)
+#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
+#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK  (0x800000U)
+#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
+#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK  (0x1000000U)
+#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
+#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK  (0x2000000U)
+#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
+#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
+#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
+#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
+#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
+#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
+#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
+#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
+#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
+#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
+#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
+#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
+#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
+#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK)
+/*! @} */
+/*! @name CTRL1_TOG - AHB to APBH Bridge Control and Status Register 1 */
+/*! @{ */
+#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK     (0x1U)
+#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT    (0U)
+#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK     (0x2U)
+#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT    (1U)
+#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK     (0x4U)
+#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT    (2U)
+#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK     (0x8U)
+#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT    (3U)
+#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK     (0x10U)
+#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT    (4U)
+#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK     (0x20U)
+#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT    (5U)
+#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK     (0x40U)
+#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT    (6U)
+#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK     (0x80U)
+#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT    (7U)
+#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK     (0x100U)
+#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT    (8U)
+#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK     (0x200U)
+#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT    (9U)
+#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK    (0x400U)
+#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT   (10U)
+#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK    (0x800U)
+#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT   (11U)
+#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK    (0x1000U)
+#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT   (12U)
+#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK    (0x2000U)
+#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT   (13U)
+#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK    (0x4000U)
+#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT   (14U)
+#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK    (0x8000U)
+#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT   (15U)
+#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK  (0x10000U)
+#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
+#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK  (0x20000U)
+#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
+#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK  (0x40000U)
+#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
+#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK  (0x80000U)
+#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
+#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK  (0x100000U)
+#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
+#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK  (0x200000U)
+#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
+#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK  (0x400000U)
+#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
+#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK  (0x800000U)
+#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
+#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK  (0x1000000U)
+#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
+#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK  (0x2000000U)
+#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
+#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
+#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
+#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
+#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
+#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
+#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
+#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
+#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
+#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
+#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
+#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
+#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
+#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK)
+/*! @} */
+/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */
+/*! @{ */
+#define APBH_CTRL2_CH0_ERROR_IRQ_MASK            (0x1U)
+#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT           (0U)
+#define APBH_CTRL2_CH0_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH1_ERROR_IRQ_MASK            (0x2U)
+#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT           (1U)
+#define APBH_CTRL2_CH1_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH2_ERROR_IRQ_MASK            (0x4U)
+#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT           (2U)
+#define APBH_CTRL2_CH2_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH3_ERROR_IRQ_MASK            (0x8U)
+#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT           (3U)
+#define APBH_CTRL2_CH3_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH4_ERROR_IRQ_MASK            (0x10U)
+#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT           (4U)
+#define APBH_CTRL2_CH4_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH5_ERROR_IRQ_MASK            (0x20U)
+#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT           (5U)
+#define APBH_CTRL2_CH5_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH6_ERROR_IRQ_MASK            (0x40U)
+#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT           (6U)
+#define APBH_CTRL2_CH6_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH7_ERROR_IRQ_MASK            (0x80U)
+#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT           (7U)
+#define APBH_CTRL2_CH7_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH8_ERROR_IRQ_MASK            (0x100U)
+#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT           (8U)
+#define APBH_CTRL2_CH8_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH9_ERROR_IRQ_MASK            (0x200U)
+#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT           (9U)
+#define APBH_CTRL2_CH9_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH10_ERROR_IRQ_MASK           (0x400U)
+#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT          (10U)
+#define APBH_CTRL2_CH10_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH11_ERROR_IRQ_MASK           (0x800U)
+#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT          (11U)
+#define APBH_CTRL2_CH11_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH12_ERROR_IRQ_MASK           (0x1000U)
+#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT          (12U)
+#define APBH_CTRL2_CH12_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH13_ERROR_IRQ_MASK           (0x2000U)
+#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT          (13U)
+#define APBH_CTRL2_CH13_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH14_ERROR_IRQ_MASK           (0x4000U)
+#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT          (14U)
+#define APBH_CTRL2_CH14_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH15_ERROR_IRQ_MASK           (0x8000U)
+#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT          (15U)
+#define APBH_CTRL2_CH15_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH0_ERROR_STATUS_MASK         (0x10000U)
+#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT        (16U)
+/*! CH0_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH0_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH1_ERROR_STATUS_MASK         (0x20000U)
+#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT        (17U)
+/*! CH1_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH1_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH2_ERROR_STATUS_MASK         (0x40000U)
+#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT        (18U)
+/*! CH2_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH2_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH3_ERROR_STATUS_MASK         (0x80000U)
+#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT        (19U)
+/*! CH3_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH3_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH4_ERROR_STATUS_MASK         (0x100000U)
+#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT        (20U)
+/*! CH4_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH4_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH5_ERROR_STATUS_MASK         (0x200000U)
+#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT        (21U)
+/*! CH5_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH5_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH6_ERROR_STATUS_MASK         (0x400000U)
+#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT        (22U)
+/*! CH6_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH6_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH7_ERROR_STATUS_MASK         (0x800000U)
+#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT        (23U)
+/*! CH7_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH7_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH8_ERROR_STATUS_MASK         (0x1000000U)
+#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT        (24U)
+/*! CH8_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH8_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH9_ERROR_STATUS_MASK         (0x2000000U)
+#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT        (25U)
+/*! CH9_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH9_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH10_ERROR_STATUS_MASK        (0x4000000U)
+#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT       (26U)
+/*! CH10_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH10_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH11_ERROR_STATUS_MASK        (0x8000000U)
+#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT       (27U)
+/*! CH11_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH11_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH12_ERROR_STATUS_MASK        (0x10000000U)
+#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT       (28U)
+/*! CH12_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH12_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH13_ERROR_STATUS_MASK        (0x20000000U)
+#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT       (29U)
+/*! CH13_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH13_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH14_ERROR_STATUS_MASK        (0x40000000U)
+#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT       (30U)
+/*! CH14_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH14_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH15_ERROR_STATUS_MASK        (0x80000000U)
+#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT       (31U)
+/*! CH15_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH15_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK)
+/*! @} */
+/*! @name CTRL2_SET - AHB to APBH Bridge Control and Status Register 2 */
+/*! @{ */
+#define APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK        (0x1U)
+#define APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT       (0U)
+#define APBH_CTRL2_SET_CH0_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK        (0x2U)
+#define APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT       (1U)
+#define APBH_CTRL2_SET_CH1_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK        (0x4U)
+#define APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT       (2U)
+#define APBH_CTRL2_SET_CH2_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK        (0x8U)
+#define APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT       (3U)
+#define APBH_CTRL2_SET_CH3_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK        (0x10U)
+#define APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT       (4U)
+#define APBH_CTRL2_SET_CH4_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK        (0x20U)
+#define APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT       (5U)
+#define APBH_CTRL2_SET_CH5_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK        (0x40U)
+#define APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT       (6U)
+#define APBH_CTRL2_SET_CH6_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK        (0x80U)
+#define APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT       (7U)
+#define APBH_CTRL2_SET_CH7_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK        (0x100U)
+#define APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT       (8U)
+#define APBH_CTRL2_SET_CH8_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK        (0x200U)
+#define APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT       (9U)
+#define APBH_CTRL2_SET_CH9_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK       (0x400U)
+#define APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT      (10U)
+#define APBH_CTRL2_SET_CH10_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK       (0x800U)
+#define APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT      (11U)
+#define APBH_CTRL2_SET_CH11_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK       (0x1000U)
+#define APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT      (12U)
+#define APBH_CTRL2_SET_CH12_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK       (0x2000U)
+#define APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT      (13U)
+#define APBH_CTRL2_SET_CH13_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK       (0x4000U)
+#define APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT      (14U)
+#define APBH_CTRL2_SET_CH14_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK       (0x8000U)
+#define APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT      (15U)
+#define APBH_CTRL2_SET_CH15_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK     (0x10000U)
+#define APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT    (16U)
+/*! CH0_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH0_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK     (0x20000U)
+#define APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT    (17U)
+/*! CH1_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH1_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK     (0x40000U)
+#define APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT    (18U)
+/*! CH2_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH2_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK     (0x80000U)
+#define APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT    (19U)
+/*! CH3_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH3_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK     (0x100000U)
+#define APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT    (20U)
+/*! CH4_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH4_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK     (0x200000U)
+#define APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT    (21U)
+/*! CH5_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH5_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK     (0x400000U)
+#define APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT    (22U)
+/*! CH6_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH6_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK     (0x800000U)
+#define APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT    (23U)
+/*! CH7_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH7_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK     (0x1000000U)
+#define APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT    (24U)
+/*! CH8_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH8_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK     (0x2000000U)
+#define APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT    (25U)
+/*! CH9_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH9_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK    (0x4000000U)
+#define APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT   (26U)
+/*! CH10_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH10_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK    (0x8000000U)
+#define APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT   (27U)
+/*! CH11_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH11_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK    (0x10000000U)
+#define APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT   (28U)
+/*! CH12_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH12_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK    (0x20000000U)
+#define APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT   (29U)
+/*! CH13_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH13_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK    (0x40000000U)
+#define APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT   (30U)
+/*! CH14_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH14_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK    (0x80000000U)
+#define APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT   (31U)
+/*! CH15_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH15_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK)
+/*! @} */
+/*! @name CTRL2_CLR - AHB to APBH Bridge Control and Status Register 2 */
+/*! @{ */
+#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK        (0x1U)
+#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT       (0U)
+#define APBH_CTRL2_CLR_CH0_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK        (0x2U)
+#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT       (1U)
+#define APBH_CTRL2_CLR_CH1_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK        (0x4U)
+#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT       (2U)
+#define APBH_CTRL2_CLR_CH2_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK        (0x8U)
+#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT       (3U)
+#define APBH_CTRL2_CLR_CH3_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK        (0x10U)
+#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT       (4U)
+#define APBH_CTRL2_CLR_CH4_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK        (0x20U)
+#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT       (5U)
+#define APBH_CTRL2_CLR_CH5_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK        (0x40U)
+#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT       (6U)
+#define APBH_CTRL2_CLR_CH6_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK        (0x80U)
+#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT       (7U)
+#define APBH_CTRL2_CLR_CH7_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK        (0x100U)
+#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT       (8U)
+#define APBH_CTRL2_CLR_CH8_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK        (0x200U)
+#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT       (9U)
+#define APBH_CTRL2_CLR_CH9_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK       (0x400U)
+#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT      (10U)
+#define APBH_CTRL2_CLR_CH10_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK       (0x800U)
+#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT      (11U)
+#define APBH_CTRL2_CLR_CH11_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK       (0x1000U)
+#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT      (12U)
+#define APBH_CTRL2_CLR_CH12_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK       (0x2000U)
+#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT      (13U)
+#define APBH_CTRL2_CLR_CH13_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK       (0x4000U)
+#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT      (14U)
+#define APBH_CTRL2_CLR_CH14_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK       (0x8000U)
+#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT      (15U)
+#define APBH_CTRL2_CLR_CH15_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK     (0x10000U)
+#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT    (16U)
+/*! CH0_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH0_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK     (0x20000U)
+#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT    (17U)
+/*! CH1_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH1_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK     (0x40000U)
+#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT    (18U)
+/*! CH2_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH2_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK     (0x80000U)
+#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT    (19U)
+/*! CH3_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH3_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK     (0x100000U)
+#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT    (20U)
+/*! CH4_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH4_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK     (0x200000U)
+#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT    (21U)
+/*! CH5_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH5_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK     (0x400000U)
+#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT    (22U)
+/*! CH6_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH6_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK     (0x800000U)
+#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT    (23U)
+/*! CH7_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH7_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK     (0x1000000U)
+#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT    (24U)
+/*! CH8_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH8_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK     (0x2000000U)
+#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT    (25U)
+/*! CH9_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH9_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK    (0x4000000U)
+#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT   (26U)
+/*! CH10_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH10_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK    (0x8000000U)
+#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT   (27U)
+/*! CH11_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH11_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK    (0x10000000U)
+#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT   (28U)
+/*! CH12_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH12_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK    (0x20000000U)
+#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT   (29U)
+/*! CH13_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH13_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK    (0x40000000U)
+#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT   (30U)
+/*! CH14_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH14_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK    (0x80000000U)
+#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT   (31U)
+/*! CH15_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH15_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK)
+/*! @} */
+/*! @name CTRL2_TOG - AHB to APBH Bridge Control and Status Register 2 */
+/*! @{ */
+#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK        (0x1U)
+#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT       (0U)
+#define APBH_CTRL2_TOG_CH0_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK        (0x2U)
+#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT       (1U)
+#define APBH_CTRL2_TOG_CH1_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK        (0x4U)
+#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT       (2U)
+#define APBH_CTRL2_TOG_CH2_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK        (0x8U)
+#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT       (3U)
+#define APBH_CTRL2_TOG_CH3_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK        (0x10U)
+#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT       (4U)
+#define APBH_CTRL2_TOG_CH4_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK        (0x20U)
+#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT       (5U)
+#define APBH_CTRL2_TOG_CH5_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK        (0x40U)
+#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT       (6U)
+#define APBH_CTRL2_TOG_CH6_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK        (0x80U)
+#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT       (7U)
+#define APBH_CTRL2_TOG_CH7_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK        (0x100U)
+#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT       (8U)
+#define APBH_CTRL2_TOG_CH8_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK        (0x200U)
+#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT       (9U)
+#define APBH_CTRL2_TOG_CH9_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK       (0x400U)
+#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT      (10U)
+#define APBH_CTRL2_TOG_CH10_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK       (0x800U)
+#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT      (11U)
+#define APBH_CTRL2_TOG_CH11_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK       (0x1000U)
+#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT      (12U)
+#define APBH_CTRL2_TOG_CH12_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK       (0x2000U)
+#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT      (13U)
+#define APBH_CTRL2_TOG_CH13_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK       (0x4000U)
+#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT      (14U)
+#define APBH_CTRL2_TOG_CH14_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK       (0x8000U)
+#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT      (15U)
+#define APBH_CTRL2_TOG_CH15_ERROR_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK     (0x10000U)
+#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT    (16U)
+/*! CH0_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH0_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK     (0x20000U)
+#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT    (17U)
+/*! CH1_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH1_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK     (0x40000U)
+#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT    (18U)
+/*! CH2_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH2_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK     (0x80000U)
+#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT    (19U)
+/*! CH3_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH3_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK     (0x100000U)
+#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT    (20U)
+/*! CH4_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH4_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK     (0x200000U)
+#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT    (21U)
+/*! CH5_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH5_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK     (0x400000U)
+#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT    (22U)
+/*! CH6_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH6_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK     (0x800000U)
+#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT    (23U)
+/*! CH7_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH7_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK     (0x1000000U)
+#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT    (24U)
+/*! CH8_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH8_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK     (0x2000000U)
+#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT    (25U)
+/*! CH9_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH9_ERROR_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK    (0x4000000U)
+#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT   (26U)
+/*! CH10_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH10_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK    (0x8000000U)
+#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT   (27U)
+/*! CH11_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH11_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK    (0x10000000U)
+#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT   (28U)
+/*! CH12_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH12_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK    (0x20000000U)
+#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT   (29U)
+/*! CH13_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH13_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK    (0x40000000U)
+#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT   (30U)
+/*! CH14_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH14_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK    (0x80000000U)
+#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT   (31U)
+/*! CH15_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH15_ERROR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK)
+/*! @} */
+/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */
+/*! @{ */
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK    (0xFFFFU)
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT   (0U)
+/*! FREEZE_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK     (0xFFFF0000U)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT    (16U)
+/*! RESET_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK)
+/*! @} */
+/*! @name CHANNEL_CTRL_SET - AHB to APBH Bridge Channel Register */
+/*! @{ */
+#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK (0xFFFFU)
+#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT (0U)
+/*! FREEZE_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL(x)  (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK)
+#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK (0xFFFF0000U)
+#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT (16U)
+/*! RESET_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK)
+/*! @} */
+/*! @name CHANNEL_CTRL_CLR - AHB to APBH Bridge Channel Register */
+/*! @{ */
+#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK (0xFFFFU)
+#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT (0U)
+/*! FREEZE_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL(x)  (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK)
+#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK (0xFFFF0000U)
+#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT (16U)
+/*! RESET_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK)
+/*! @} */
+/*! @name CHANNEL_CTRL_TOG - AHB to APBH Bridge Channel Register */
+/*! @{ */
+#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK (0xFFFFU)
+#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT (0U)
+/*! FREEZE_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL(x)  (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK)
+#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK (0xFFFF0000U)
+#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT (16U)
+/*! RESET_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL(x)   (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK)
+/*! @} */
+/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */
+/*! @{ */
+#define APBH_DMA_BURST_SIZE_CH0_MASK             (0x3U)
+#define APBH_DMA_BURST_SIZE_CH0_SHIFT            (0U)
+#define APBH_DMA_BURST_SIZE_CH0(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK)
+#define APBH_DMA_BURST_SIZE_CH1_MASK             (0xCU)
+#define APBH_DMA_BURST_SIZE_CH1_SHIFT            (2U)
+#define APBH_DMA_BURST_SIZE_CH1(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK)
+#define APBH_DMA_BURST_SIZE_CH2_MASK             (0x30U)
+#define APBH_DMA_BURST_SIZE_CH2_SHIFT            (4U)
+#define APBH_DMA_BURST_SIZE_CH2(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK)
+#define APBH_DMA_BURST_SIZE_CH3_MASK             (0xC0U)
+#define APBH_DMA_BURST_SIZE_CH3_SHIFT            (6U)
+#define APBH_DMA_BURST_SIZE_CH3(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK)
+#define APBH_DMA_BURST_SIZE_CH4_MASK             (0x300U)
+#define APBH_DMA_BURST_SIZE_CH4_SHIFT            (8U)
+#define APBH_DMA_BURST_SIZE_CH4(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK)
+#define APBH_DMA_BURST_SIZE_CH5_MASK             (0xC00U)
+#define APBH_DMA_BURST_SIZE_CH5_SHIFT            (10U)
+#define APBH_DMA_BURST_SIZE_CH5(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK)
+#define APBH_DMA_BURST_SIZE_CH6_MASK             (0x3000U)
+#define APBH_DMA_BURST_SIZE_CH6_SHIFT            (12U)
+#define APBH_DMA_BURST_SIZE_CH6(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK)
+#define APBH_DMA_BURST_SIZE_CH7_MASK             (0xC000U)
+#define APBH_DMA_BURST_SIZE_CH7_SHIFT            (14U)
+#define APBH_DMA_BURST_SIZE_CH7(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK)
+#define APBH_DMA_BURST_SIZE_CH8_MASK             (0x30000U)
+#define APBH_DMA_BURST_SIZE_CH8_SHIFT            (16U)
+/*! CH8
+ *  0b00..BURST0
+ *  0b01..BURST4
+ *  0b10..BURST8
+ */
+#define APBH_DMA_BURST_SIZE_CH8(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK)
+/*! @} */
+/*! @name DEBUG - AHB to APBH DMA Debug Register */
+/*! @{ */
+#define APBH_DEBUG_GPMI_ONE_FIFO_MASK            (0x1U)
+#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT           (0U)
+#define APBH_DEBUG_GPMI_ONE_FIFO(x)              (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK)
+/*! @} */
+/*! @name CH_CURCMDAR - APBH DMA Channel n Current Command Address Register */
+/*! @{ */
+#define APBH_CH_CURCMDAR_CMD_ADDR_MASK           (0xFFFFFFFFU)
+#define APBH_CH_CURCMDAR_CMD_ADDR_SHIFT          (0U)
+#define APBH_CH_CURCMDAR_CMD_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_CURCMDAR_CMD_ADDR_MASK)
+/*! @} */
+/* The count of APBH_CH_CURCMDAR */
+#define APBH_CH_CURCMDAR_COUNT                   (16U)
+/*! @name CH_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
+/*! @{ */
+#define APBH_CH_NXTCMDAR_CMD_ADDR_MASK           (0xFFFFFFFFU)
+#define APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT          (0U)
+#define APBH_CH_NXTCMDAR_CMD_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_NXTCMDAR_CMD_ADDR_MASK)
+/*! @} */
+/* The count of APBH_CH_NXTCMDAR */
+#define APBH_CH_NXTCMDAR_COUNT                   (16U)
+/*! @name CH_CMD - APBH DMA Channel n Command Register */
+/*! @{ */
+#define APBH_CH_CMD_COMMAND_MASK                 (0x3U)
+#define APBH_CH_CMD_COMMAND_SHIFT                (0U)
+/*! COMMAND
+ *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
+ *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
+ *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
+ *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained
+ *        device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain
+ *        pointer if the peripheral sense line is false.
+ */
+#define APBH_CH_CMD_COMMAND(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_COMMAND_SHIFT)) & APBH_CH_CMD_COMMAND_MASK)
+#define APBH_CH_CMD_CHAIN_MASK                   (0x4U)
+#define APBH_CH_CMD_CHAIN_SHIFT                  (2U)
+#define APBH_CH_CMD_CHAIN(x)                     (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CHAIN_SHIFT)) & APBH_CH_CMD_CHAIN_MASK)
+#define APBH_CH_CMD_IRQONCMPLT_MASK              (0x8U)
+#define APBH_CH_CMD_IRQONCMPLT_SHIFT             (3U)
+#define APBH_CH_CMD_IRQONCMPLT(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_IRQONCMPLT_SHIFT)) & APBH_CH_CMD_IRQONCMPLT_MASK)
+#define APBH_CH_CMD_NANDLOCK_MASK                (0x10U)
+#define APBH_CH_CMD_NANDLOCK_SHIFT               (4U)
+#define APBH_CH_CMD_NANDLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDLOCK_SHIFT)) & APBH_CH_CMD_NANDLOCK_MASK)
+#define APBH_CH_CMD_NANDWAIT4READY_MASK          (0x20U)
+#define APBH_CH_CMD_NANDWAIT4READY_SHIFT         (5U)
+#define APBH_CH_CMD_NANDWAIT4READY(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH_CMD_NANDWAIT4READY_MASK)
+#define APBH_CH_CMD_SEMAPHORE_MASK               (0x40U)
+#define APBH_CH_CMD_SEMAPHORE_SHIFT              (6U)
+#define APBH_CH_CMD_SEMAPHORE(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_SEMAPHORE_SHIFT)) & APBH_CH_CMD_SEMAPHORE_MASK)
+#define APBH_CH_CMD_WAIT4ENDCMD_MASK             (0x80U)
+#define APBH_CH_CMD_WAIT4ENDCMD_SHIFT            (7U)
+#define APBH_CH_CMD_WAIT4ENDCMD(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH_CMD_WAIT4ENDCMD_MASK)
+#define APBH_CH_CMD_HALTONTERMINATE_MASK         (0x100U)
+#define APBH_CH_CMD_HALTONTERMINATE_SHIFT        (8U)
+#define APBH_CH_CMD_HALTONTERMINATE(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH_CMD_HALTONTERMINATE_MASK)
+#define APBH_CH_CMD_CMDWORDS_MASK                (0xF000U)
+#define APBH_CH_CMD_CMDWORDS_SHIFT               (12U)
+#define APBH_CH_CMD_CMDWORDS(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CMDWORDS_SHIFT)) & APBH_CH_CMD_CMDWORDS_MASK)
+#define APBH_CH_CMD_XFER_COUNT_MASK              (0xFFFF0000U)
+#define APBH_CH_CMD_XFER_COUNT_SHIFT             (16U)
+#define APBH_CH_CMD_XFER_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_XFER_COUNT_SHIFT)) & APBH_CH_CMD_XFER_COUNT_MASK)
+/*! @} */
+/* The count of APBH_CH_CMD */
+#define APBH_CH_CMD_COUNT                        (16U)
+/*! @name CH_BAR - APBH DMA Channel n Buffer Address Register */
+/*! @{ */
+#define APBH_CH_BAR_ADDRESS_MASK                 (0xFFFFFFFFU)
+#define APBH_CH_BAR_ADDRESS_SHIFT                (0U)
+#define APBH_CH_BAR_ADDRESS(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH_BAR_ADDRESS_SHIFT)) & APBH_CH_BAR_ADDRESS_MASK)
+/*! @} */
+/* The count of APBH_CH_BAR */
+#define APBH_CH_BAR_COUNT                        (16U)
+/*! @name CH_SEMA - APBH DMA Channel n Semaphore Register */
+/*! @{ */
+#define APBH_CH_SEMA_INCREMENT_SEMA_MASK         (0xFFU)
+#define APBH_CH_SEMA_INCREMENT_SEMA_SHIFT        (0U)
+#define APBH_CH_SEMA_INCREMENT_SEMA(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH_SEMA_INCREMENT_SEMA_MASK)
+#define APBH_CH_SEMA_PHORE_MASK                  (0xFF0000U)
+#define APBH_CH_SEMA_PHORE_SHIFT                 (16U)
+#define APBH_CH_SEMA_PHORE(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_PHORE_SHIFT)) & APBH_CH_SEMA_PHORE_MASK)
+/*! @} */
+/* The count of APBH_CH_SEMA */
+#define APBH_CH_SEMA_COUNT                       (16U)
+/*! @name CH_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
+/*! @{ */
+#define APBH_CH_DEBUG1_STATEMACHINE_MASK         (0x1FU)
+#define APBH_CH_DEBUG1_STATEMACHINE_SHIFT        (0U)
+/*! STATEMACHINE
+ *  0b00000..This is the idle state of the DMA state machine.
+ *  0b00001..State in which the DMA is waiting to receive the first word of a command.
+ *  0b00010..State in which the DMA is waiting to receive the third word of a command.
+ *  0b00011..State in which the DMA is waiting to receive the second word of a command.
+ *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
+ *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
+ *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the
+ *           PIO words when PIO count is greater than 1.
+ *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
+ *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
+ *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
+ *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
+ *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
+ *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
+ *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
+ *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
+ *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
+ *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
+ *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and
+ *           effectively halts. A channel reset is required to exit this state
+ *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
+ *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device
+ *           indicates that the external device is ready.
+ */
+#define APBH_CH_DEBUG1_STATEMACHINE(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH_DEBUG1_STATEMACHINE_MASK)
+#define APBH_CH_DEBUG1_RSVD1_MASK                (0xFFFE0U)
+#define APBH_CH_DEBUG1_RSVD1_SHIFT               (5U)
+#define APBH_CH_DEBUG1_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RSVD1_SHIFT)) & APBH_CH_DEBUG1_RSVD1_MASK)
+#define APBH_CH_DEBUG1_WR_FIFO_FULL_MASK         (0x100000U)
+#define APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT        (20U)
+#define APBH_CH_DEBUG1_WR_FIFO_FULL(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_FULL_MASK)
+#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK        (0x200000U)
+#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT       (21U)
+#define APBH_CH_DEBUG1_WR_FIFO_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK)
+#define APBH_CH_DEBUG1_RD_FIFO_FULL_MASK         (0x400000U)
+#define APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT        (22U)
+#define APBH_CH_DEBUG1_RD_FIFO_FULL(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_FULL_MASK)
+#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK        (0x800000U)
+#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT       (23U)
+#define APBH_CH_DEBUG1_RD_FIFO_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK)
+#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK     (0x1000000U)
+#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT    (24U)
+#define APBH_CH_DEBUG1_NEXTCMDADDRVALID(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK)
+#define APBH_CH_DEBUG1_LOCK_MASK                 (0x2000000U)
+#define APBH_CH_DEBUG1_LOCK_SHIFT                (25U)
+#define APBH_CH_DEBUG1_LOCK(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_LOCK_SHIFT)) & APBH_CH_DEBUG1_LOCK_MASK)
+#define APBH_CH_DEBUG1_READY_MASK                (0x4000000U)
+#define APBH_CH_DEBUG1_READY_SHIFT               (26U)
+#define APBH_CH_DEBUG1_READY(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_READY_SHIFT)) & APBH_CH_DEBUG1_READY_MASK)
+#define APBH_CH_DEBUG1_SENSE_MASK                (0x8000000U)
+#define APBH_CH_DEBUG1_SENSE_SHIFT               (27U)
+#define APBH_CH_DEBUG1_SENSE(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_SENSE_SHIFT)) & APBH_CH_DEBUG1_SENSE_MASK)
+#define APBH_CH_DEBUG1_END_MASK                  (0x10000000U)
+#define APBH_CH_DEBUG1_END_SHIFT                 (28U)
+#define APBH_CH_DEBUG1_END(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_END_SHIFT)) & APBH_CH_DEBUG1_END_MASK)
+#define APBH_CH_DEBUG1_KICK_MASK                 (0x20000000U)
+#define APBH_CH_DEBUG1_KICK_SHIFT                (29U)
+#define APBH_CH_DEBUG1_KICK(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_KICK_SHIFT)) & APBH_CH_DEBUG1_KICK_MASK)
+#define APBH_CH_DEBUG1_BURST_MASK                (0x40000000U)
+#define APBH_CH_DEBUG1_BURST_SHIFT               (30U)
+#define APBH_CH_DEBUG1_BURST(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_BURST_SHIFT)) & APBH_CH_DEBUG1_BURST_MASK)
+#define APBH_CH_DEBUG1_REQ_MASK                  (0x80000000U)
+#define APBH_CH_DEBUG1_REQ_SHIFT                 (31U)
+#define APBH_CH_DEBUG1_REQ(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_REQ_SHIFT)) & APBH_CH_DEBUG1_REQ_MASK)
+/*! @} */
+/* The count of APBH_CH_DEBUG1 */
+#define APBH_CH_DEBUG1_COUNT                     (16U)
+/*! @name CH_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
+/*! @{ */
+#define APBH_CH_DEBUG2_AHB_BYTES_MASK            (0xFFFFU)
+#define APBH_CH_DEBUG2_AHB_BYTES_SHIFT           (0U)
+#define APBH_CH_DEBUG2_AHB_BYTES(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH_DEBUG2_AHB_BYTES_MASK)
+#define APBH_CH_DEBUG2_APB_BYTES_MASK            (0xFFFF0000U)
+#define APBH_CH_DEBUG2_APB_BYTES_SHIFT           (16U)
+#define APBH_CH_DEBUG2_APB_BYTES(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH_DEBUG2_APB_BYTES_MASK)
+/*! @} */
+/* The count of APBH_CH_DEBUG2 */
+#define APBH_CH_DEBUG2_COUNT                     (16U)
+/*! @name VERSION - APBH Bridge Version Register */
+/*! @{ */
+#define APBH_VERSION_STEP_MASK                   (0xFFFFU)
+#define APBH_VERSION_STEP_SHIFT                  (0U)
+#define APBH_VERSION_STEP(x)                     (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK)
+#define APBH_VERSION_MINOR_MASK                  (0xFF0000U)
+#define APBH_VERSION_MINOR_SHIFT                 (16U)
+#define APBH_VERSION_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK)
+#define APBH_VERSION_MAJOR_MASK                  (0xFF000000U)
+#define APBH_VERSION_MAJOR_SHIFT                 (24U)
+#define APBH_VERSION_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK)
+/*! @} */
+/*!
+ * @}
+ */ /* end of group APBH_Register_Masks */
+/* APBH - Peripheral instance base addresses */
+/** Peripheral APBH base address */
+#define APBH_BASE                                (0x33000000u)
+/** Peripheral APBH base pointer */
+#define APBH                                     ((APBH_Type *)APBH_BASE)
+/** Array initializer of APBH peripheral base addresses */
+#define APBH_BASE_ADDRS                          { APBH_BASE }
+/** Array initializer of APBH peripheral base pointers */
+#define APBH_BASE_PTRS                           { APBH }
+/** Interrupt vectors for the APBH peripheral type */
+#define APBH_IRQS                                { APBHDMA_IRQn }
+/*!
+ * @}
+ */ /* end of group APBH_Peripheral_Access_Layer */
+/* ----------------------------------------------------------------------------
+   -- BCH Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer
+ * @{
+ */
+/** BCH - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */
+  __IO uint32_t CTRL_SET;                          /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */
+  __IO uint32_t CTRL_CLR;                          /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */
+  __IO uint32_t CTRL_TOG;                          /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */
+  __I  uint32_t STATUS0;                           /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t MODE;                              /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */
+       uint8_t RESERVED_1[12];
+  __IO uint32_t ENCODEPTR;                         /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t DATAPTR;                           /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */
+       uint8_t RESERVED_3[12];
+  __IO uint32_t METAPTR;                           /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */
+       uint8_t RESERVED_4[28];
+  __IO uint32_t LAYOUTSELECT;                      /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */
+       uint8_t RESERVED_5[12];
+  __IO uint32_t FLASH0LAYOUT0;                     /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */
+       uint8_t RESERVED_6[12];
+  __IO uint32_t FLASH0LAYOUT1;                     /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */
+       uint8_t RESERVED_7[12];
+  __IO uint32_t FLASH1LAYOUT0;                     /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */
+       uint8_t RESERVED_8[12];
+  __IO uint32_t FLASH1LAYOUT1;                     /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */
+       uint8_t RESERVED_9[12];
+  __IO uint32_t FLASH2LAYOUT0;                     /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */
+       uint8_t RESERVED_10[12];
+  __IO uint32_t FLASH2LAYOUT1;                     /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */
+       uint8_t RESERVED_11[12];
+  __IO uint32_t FLASH3LAYOUT0;                     /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */
+       uint8_t RESERVED_12[12];
+  __IO uint32_t FLASH3LAYOUT1;                     /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */
+       uint8_t RESERVED_13[12];
+  __IO uint32_t DEBUG0;                            /**< Hardware BCH ECC Debug Register0, offset: 0x100 */
+  __IO uint32_t DEBUG0_SET;                        /**< Hardware BCH ECC Debug Register0, offset: 0x104 */
+  __IO uint32_t DEBUG0_CLR;                        /**< Hardware BCH ECC Debug Register0, offset: 0x108 */
+  __IO uint32_t DEBUG0_TOG;                        /**< Hardware BCH ECC Debug Register0, offset: 0x10C */
+  __I  uint32_t DBGKESREAD;                        /**< KES Debug Read Register, offset: 0x110 */
+       uint8_t RESERVED_14[12];
+  __I  uint32_t DBGCSFEREAD;                       /**< Chien Search Debug Read Register, offset: 0x120 */
+       uint8_t RESERVED_15[12];
+  __I  uint32_t DBGSYNDGENREAD;                    /**< Syndrome Generator Debug Read Register, offset: 0x130 */
+       uint8_t RESERVED_16[12];
+  __I  uint32_t DBGAHBMREAD;                       /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */
+       uint8_t RESERVED_17[12];
+  __I  uint32_t BLOCKNAME;                         /**< Block Name Register, offset: 0x150 */
+       uint8_t RESERVED_18[12];
+  __I  uint32_t VERSION;                           /**< BCH Version Register, offset: 0x160 */
+       uint8_t RESERVED_19[12];
+  __IO uint32_t DEBUG1;                            /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */
+} BCH_Type;
+/* ----------------------------------------------------------------------------
+   -- BCH Register Masks
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup BCH_Register_Masks BCH Register Masks
+ * @{
+ */
+/*! @name CTRL - Hardware BCH ECC Accelerator Control Register */
+/*! @{ */
+#define BCH_CTRL_COMPLETE_IRQ_MASK               (0x1U)
+#define BCH_CTRL_COMPLETE_IRQ_SHIFT              (0U)
+#define BCH_CTRL_COMPLETE_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK)
+#define BCH_CTRL_RSVD0_MASK                      (0x2U)
+#define BCH_CTRL_RSVD0_SHIFT                     (1U)
+#define BCH_CTRL_RSVD0(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK)
+#define BCH_CTRL_DEBUG_STALL_IRQ_MASK            (0x4U)
+#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT           (2U)
+#define BCH_CTRL_DEBUG_STALL_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK)
+#define BCH_CTRL_BM_ERROR_IRQ_MASK               (0x8U)
+#define BCH_CTRL_BM_ERROR_IRQ_SHIFT              (3U)
+#define BCH_CTRL_BM_ERROR_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK)
+#define BCH_CTRL_RSVD1_MASK                      (0xF0U)
+#define BCH_CTRL_RSVD1_SHIFT                     (4U)
+#define BCH_CTRL_RSVD1(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK)
+#define BCH_CTRL_COMPLETE_IRQ_EN_MASK            (0x100U)
+#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT           (8U)
+#define BCH_CTRL_COMPLETE_IRQ_EN(x)              (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK)
+#define BCH_CTRL_RSVD2_MASK                      (0x200U)
+#define BCH_CTRL_RSVD2_SHIFT                     (9U)
+#define BCH_CTRL_RSVD2(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK)
+#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK         (0x400U)
+#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT        (10U)
+#define BCH_CTRL_DEBUG_STALL_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK)
+#define BCH_CTRL_RSVD3_MASK                      (0xF800U)
+#define BCH_CTRL_RSVD3_SHIFT                     (11U)
+#define BCH_CTRL_RSVD3(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK)
+#define BCH_CTRL_M2M_ENABLE_MASK                 (0x10000U)
+#define BCH_CTRL_M2M_ENABLE_SHIFT                (16U)
+#define BCH_CTRL_M2M_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK)
+#define BCH_CTRL_M2M_ENCODE_MASK                 (0x20000U)
+#define BCH_CTRL_M2M_ENCODE_SHIFT                (17U)
+#define BCH_CTRL_M2M_ENCODE(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK)
+#define BCH_CTRL_M2M_LAYOUT_MASK                 (0xC0000U)
+#define BCH_CTRL_M2M_LAYOUT_SHIFT                (18U)
+#define BCH_CTRL_M2M_LAYOUT(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK)
+#define BCH_CTRL_RSVD4_MASK                      (0x300000U)
+#define BCH_CTRL_RSVD4_SHIFT                     (20U)
+#define BCH_CTRL_RSVD4(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK)
+#define BCH_CTRL_DEBUGSYNDROME_MASK              (0x400000U)
+#define BCH_CTRL_DEBUGSYNDROME_SHIFT             (22U)
+#define BCH_CTRL_DEBUGSYNDROME(x)                (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK)
+#define BCH_CTRL_RSVD5_MASK                      (0x3F800000U)
+#define BCH_CTRL_RSVD5_SHIFT                     (23U)
+#define BCH_CTRL_RSVD5(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK)
+#define BCH_CTRL_CLKGATE_MASK                    (0x40000000U)
+#define BCH_CTRL_CLKGATE_SHIFT                   (30U)
+/*! CLKGATE
+ *  0b0..Allow BCH to operate normally.
+ *  0b1..Do not clock BCH gates in order to minimize power consumption.
+ */
+#define BCH_CTRL_CLKGATE(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK)
+#define BCH_CTRL_SFTRST_MASK                     (0x80000000U)
+#define BCH_CTRL_SFTRST_SHIFT                    (31U)
+/*! SFTRST
+ *  0b0..Allow BCH to operate normally.
+ *  0b1..Hold BCH in reset.
+ */
+#define BCH_CTRL_SFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK)
+/*! @} */
+/*! @name CTRL_SET - Hardware BCH ECC Accelerator Control Register */
+/*! @{ */
+#define BCH_CTRL_SET_COMPLETE_IRQ_MASK           (0x1U)
+#define BCH_CTRL_SET_COMPLETE_IRQ_SHIFT          (0U)
+#define BCH_CTRL_SET_COMPLETE_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_MASK)
+#define BCH_CTRL_SET_RSVD0_MASK                  (0x2U)
+#define BCH_CTRL_SET_RSVD0_SHIFT                 (1U)
+#define BCH_CTRL_SET_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD0_SHIFT)) & BCH_CTRL_SET_RSVD0_MASK)
+#define BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK        (0x4U)
+#define BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT       (2U)
+#define BCH_CTRL_SET_DEBUG_STALL_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK)
+#define BCH_CTRL_SET_BM_ERROR_IRQ_MASK           (0x8U)
+#define BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT          (3U)
+#define BCH_CTRL_SET_BM_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_SET_BM_ERROR_IRQ_MASK)
+#define BCH_CTRL_SET_RSVD1_MASK                  (0xF0U)
+#define BCH_CTRL_SET_RSVD1_SHIFT                 (4U)
+#define BCH_CTRL_SET_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD1_SHIFT)) & BCH_CTRL_SET_RSVD1_MASK)
+#define BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK        (0x100U)
+#define BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT       (8U)
+#define BCH_CTRL_SET_COMPLETE_IRQ_EN(x)          (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK)
+#define BCH_CTRL_SET_RSVD2_MASK                  (0x200U)
+#define BCH_CTRL_SET_RSVD2_SHIFT                 (9U)
+#define BCH_CTRL_SET_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD2_SHIFT)) & BCH_CTRL_SET_RSVD2_MASK)
+#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK     (0x400U)
+#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT    (10U)
+#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK)
+#define BCH_CTRL_SET_RSVD3_MASK                  (0xF800U)
+#define BCH_CTRL_SET_RSVD3_SHIFT                 (11U)
+#define BCH_CTRL_SET_RSVD3(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD3_SHIFT)) & BCH_CTRL_SET_RSVD3_MASK)
+#define BCH_CTRL_SET_M2M_ENABLE_MASK             (0x10000U)
+#define BCH_CTRL_SET_M2M_ENABLE_SHIFT            (16U)
+#define BCH_CTRL_SET_M2M_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENABLE_SHIFT)) & BCH_CTRL_SET_M2M_ENABLE_MASK)
+#define BCH_CTRL_SET_M2M_ENCODE_MASK             (0x20000U)
+#define BCH_CTRL_SET_M2M_ENCODE_SHIFT            (17U)
+#define BCH_CTRL_SET_M2M_ENCODE(x)               (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENCODE_SHIFT)) & BCH_CTRL_SET_M2M_ENCODE_MASK)
+#define BCH_CTRL_SET_M2M_LAYOUT_MASK             (0xC0000U)
+#define BCH_CTRL_SET_M2M_LAYOUT_SHIFT            (18U)
+#define BCH_CTRL_SET_M2M_LAYOUT(x)               (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_LAYOUT_SHIFT)) & BCH_CTRL_SET_M2M_LAYOUT_MASK)
+#define BCH_CTRL_SET_RSVD4_MASK                  (0x300000U)
+#define BCH_CTRL_SET_RSVD4_SHIFT                 (20U)
+#define BCH_CTRL_SET_RSVD4(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD4_SHIFT)) & BCH_CTRL_SET_RSVD4_MASK)
+#define BCH_CTRL_SET_DEBUGSYNDROME_MASK          (0x400000U)
+#define BCH_CTRL_SET_DEBUGSYNDROME_SHIFT         (22U)
+#define BCH_CTRL_SET_DEBUGSYNDROME(x)            (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_SET_DEBUGSYNDROME_MASK)
+#define BCH_CTRL_SET_RSVD5_MASK                  (0x3F800000U)
+#define BCH_CTRL_SET_RSVD5_SHIFT                 (23U)
+#define BCH_CTRL_SET_RSVD5(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD5_SHIFT)) & BCH_CTRL_SET_RSVD5_MASK)
+#define BCH_CTRL_SET_CLKGATE_MASK                (0x40000000U)
+#define BCH_CTRL_SET_CLKGATE_SHIFT               (30U)
+/*! CLKGATE
+ *  0b0..Allow BCH to operate normally.
+ *  0b1..Do not clock BCH gates in order to minimize power consumption.
+ */
+#define BCH_CTRL_SET_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_CLKGATE_SHIFT)) & BCH_CTRL_SET_CLKGATE_MASK)
+#define BCH_CTRL_SET_SFTRST_MASK                 (0x80000000U)
+#define BCH_CTRL_SET_SFTRST_SHIFT                (31U)
+/*! SFTRST
+ *  0b0..Allow BCH to operate normally.
+ *  0b1..Hold BCH in reset.
+ */
+#define BCH_CTRL_SET_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_SFTRST_SHIFT)) & BCH_CTRL_SET_SFTRST_MASK)
+/*! @} */
+/*! @name CTRL_CLR - Hardware BCH ECC Accelerator Control Register */
+/*! @{ */
+#define BCH_CTRL_CLR_COMPLETE_IRQ_MASK           (0x1U)
+#define BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT          (0U)
+#define BCH_CTRL_CLR_COMPLETE_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_MASK)
+#define BCH_CTRL_CLR_RSVD0_MASK                  (0x2U)
+#define BCH_CTRL_CLR_RSVD0_SHIFT                 (1U)
+#define BCH_CTRL_CLR_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD0_SHIFT)) & BCH_CTRL_CLR_RSVD0_MASK)
+#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK        (0x4U)
+#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT       (2U)
+#define BCH_CTRL_CLR_DEBUG_STALL_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK)
+#define BCH_CTRL_CLR_BM_ERROR_IRQ_MASK           (0x8U)
+#define BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT          (3U)
+#define BCH_CTRL_CLR_BM_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_CLR_BM_ERROR_IRQ_MASK)
+#define BCH_CTRL_CLR_RSVD1_MASK                  (0xF0U)
+#define BCH_CTRL_CLR_RSVD1_SHIFT                 (4U)
+#define BCH_CTRL_CLR_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD1_SHIFT)) & BCH_CTRL_CLR_RSVD1_MASK)
+#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK        (0x100U)
+#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT       (8U)
+#define BCH_CTRL_CLR_COMPLETE_IRQ_EN(x)          (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK)
+#define BCH_CTRL_CLR_RSVD2_MASK                  (0x200U)
+#define BCH_CTRL_CLR_RSVD2_SHIFT                 (9U)
+#define BCH_CTRL_CLR_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD2_SHIFT)) & BCH_CTRL_CLR_RSVD2_MASK)
+#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK     (0x400U)
+#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT    (10U)
+#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK)
+#define BCH_CTRL_CLR_RSVD3_MASK                  (0xF800U)
+#define BCH_CTRL_CLR_RSVD3_SHIFT                 (11U)
+#define BCH_CTRL_CLR_RSVD3(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD3_SHIFT)) & BCH_CTRL_CLR_RSVD3_MASK)
+#define BCH_CTRL_CLR_M2M_ENABLE_MASK             (0x10000U)
+#define BCH_CTRL_CLR_M2M_ENABLE_SHIFT            (16U)
+#define BCH_CTRL_CLR_M2M_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENABLE_SHIFT)) & BCH_CTRL_CLR_M2M_ENABLE_MASK)
+#define BCH_CTRL_CLR_M2M_ENCODE_MASK             (0x20000U)
+#define BCH_CTRL_CLR_M2M_ENCODE_SHIFT            (17U)
+#define BCH_CTRL_CLR_M2M_ENCODE(x)               (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENCODE_SHIFT)) & BCH_CTRL_CLR_M2M_ENCODE_MASK)
+#define BCH_CTRL_CLR_M2M_LAYOUT_MASK             (0xC0000U)
+#define BCH_CTRL_CLR_M2M_LAYOUT_SHIFT            (18U)
+#define BCH_CTRL_CLR_M2M_LAYOUT(x)               (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_LAYOUT_SHIFT)) & BCH_CTRL_CLR_M2M_LAYOUT_MASK)
+#define BCH_CTRL_CLR_RSVD4_MASK                  (0x300000U)
+#define BCH_CTRL_CLR_RSVD4_SHIFT                 (20U)
+#define BCH_CTRL_CLR_RSVD4(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD4_SHIFT)) & BCH_CTRL_CLR_RSVD4_MASK)
+#define BCH_CTRL_CLR_DEBUGSYNDROME_MASK          (0x400000U)
+#define BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT         (22U)
+#define BCH_CTRL_CLR_DEBUGSYNDROME(x)            (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_CLR_DEBUGSYNDROME_MASK)
+#define BCH_CTRL_CLR_RSVD5_MASK                  (0x3F800000U)
+#define BCH_CTRL_CLR_RSVD5_SHIFT                 (23U)
+#define BCH_CTRL_CLR_RSVD5(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD5_SHIFT)) & BCH_CTRL_CLR_RSVD5_MASK)
+#define BCH_CTRL_CLR_CLKGATE_MASK                (0x40000000U)
+#define BCH_CTRL_CLR_CLKGATE_SHIFT               (30U)
+/*! CLKGATE
+ *  0b0..Allow BCH to operate normally.
+ *  0b1..Do not clock BCH gates in order to minimize power consumption.
+ */
+#define BCH_CTRL_CLR_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_CLKGATE_SHIFT)) & BCH_CTRL_CLR_CLKGATE_MASK)
+#define BCH_CTRL_CLR_SFTRST_MASK                 (0x80000000U)
+#define BCH_CTRL_CLR_SFTRST_SHIFT                (31U)
+/*! SFTRST
+ *  0b0..Allow BCH to operate normally.
+ *  0b1..Hold BCH in reset.
+ */
+#define BCH_CTRL_CLR_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_SFTRST_SHIFT)) & BCH_CTRL_CLR_SFTRST_MASK)
+/*! @} */
+/*! @name CTRL_TOG - Hardware BCH ECC Accelerator Control Register */
+/*! @{ */
+#define BCH_CTRL_TOG_COMPLETE_IRQ_MASK           (0x1U)
+#define BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT          (0U)
+#define BCH_CTRL_TOG_COMPLETE_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_MASK)
+#define BCH_CTRL_TOG_RSVD0_MASK                  (0x2U)
+#define BCH_CTRL_TOG_RSVD0_SHIFT                 (1U)
+#define BCH_CTRL_TOG_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD0_SHIFT)) & BCH_CTRL_TOG_RSVD0_MASK)
+#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK        (0x4U)
+#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT       (2U)
+#define BCH_CTRL_TOG_DEBUG_STALL_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK)
+#define BCH_CTRL_TOG_BM_ERROR_IRQ_MASK           (0x8U)
+#define BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT          (3U)
+#define BCH_CTRL_TOG_BM_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_TOG_BM_ERROR_IRQ_MASK)
+#define BCH_CTRL_TOG_RSVD1_MASK                  (0xF0U)
+#define BCH_CTRL_TOG_RSVD1_SHIFT                 (4U)
+#define BCH_CTRL_TOG_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD1_SHIFT)) & BCH_CTRL_TOG_RSVD1_MASK)
+#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK        (0x100U)
+#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT       (8U)
+#define BCH_CTRL_TOG_COMPLETE_IRQ_EN(x)          (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK)
+#define BCH_CTRL_TOG_RSVD2_MASK                  (0x200U)
+#define BCH_CTRL_TOG_RSVD2_SHIFT                 (9U)
+#define BCH_CTRL_TOG_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD2_SHIFT)) & BCH_CTRL_TOG_RSVD2_MASK)
+#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK     (0x400U)
+#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT    (10U)
+#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK)
+#define BCH_CTRL_TOG_RSVD3_MASK                  (0xF800U)
+#define BCH_CTRL_TOG_RSVD3_SHIFT                 (11U)
+#define BCH_CTRL_TOG_RSVD3(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD3_SHIFT)) & BCH_CTRL_TOG_RSVD3_MASK)
+#define BCH_CTRL_TOG_M2M_ENABLE_MASK             (0x10000U)
+#define BCH_CTRL_TOG_M2M_ENABLE_SHIFT            (16U)
+#define BCH_CTRL_TOG_M2M_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENABLE_SHIFT)) & BCH_CTRL_TOG_M2M_ENABLE_MASK)
+#define BCH_CTRL_TOG_M2M_ENCODE_MASK             (0x20000U)
+#define BCH_CTRL_TOG_M2M_ENCODE_SHIFT            (17U)
+#define BCH_CTRL_TOG_M2M_ENCODE(x)               (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENCODE_SHIFT)) & BCH_CTRL_TOG_M2M_ENCODE_MASK)
+#define BCH_CTRL_TOG_M2M_LAYOUT_MASK             (0xC0000U)
+#define BCH_CTRL_TOG_M2M_LAYOUT_SHIFT            (18U)
+#define BCH_CTRL_TOG_M2M_LAYOUT(x)               (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_LAYOUT_SHIFT)) & BCH_CTRL_TOG_M2M_LAYOUT_MASK)
+#define BCH_CTRL_TOG_RSVD4_MASK                  (0x300000U)
+#define BCH_CTRL_TOG_RSVD4_SHIFT                 (20U)
+#define BCH_CTRL_TOG_RSVD4(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD4_SHIFT)) & BCH_CTRL_TOG_RSVD4_MASK)
+#define BCH_CTRL_TOG_DEBUGSYNDROME_MASK          (0x400000U)
+#define BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT         (22U)
+#define BCH_CTRL_TOG_DEBUGSYNDROME(x)            (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_TOG_DEBUGSYNDROME_MASK)
+#define BCH_CTRL_TOG_RSVD5_MASK                  (0x3F800000U)
+#define BCH_CTRL_TOG_RSVD5_SHIFT                 (23U)
+#define BCH_CTRL_TOG_RSVD5(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD5_SHIFT)) & BCH_CTRL_TOG_RSVD5_MASK)
+#define BCH_CTRL_TOG_CLKGATE_MASK                (0x40000000U)
+#define BCH_CTRL_TOG_CLKGATE_SHIFT               (30U)
+/*! CLKGATE
+ *  0b0..Allow BCH to operate normally.
+ *  0b1..Do not clock BCH gates in order to minimize power consumption.
+ */
+#define BCH_CTRL_TOG_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_CLKGATE_SHIFT)) & BCH_CTRL_TOG_CLKGATE_MASK)
+#define BCH_CTRL_TOG_SFTRST_MASK                 (0x80000000U)
+#define BCH_CTRL_TOG_SFTRST_SHIFT                (31U)
+/*! SFTRST
+ *  0b0..Allow BCH to operate normally.
+ *  0b1..Hold BCH in reset.
+ */
+#define BCH_CTRL_TOG_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_SFTRST_SHIFT)) & BCH_CTRL_TOG_SFTRST_MASK)
+/*! @} */
+/*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */
+/*! @{ */
+#define BCH_STATUS0_RSVD0_MASK                   (0x3U)
+#define BCH_STATUS0_RSVD0_SHIFT                  (0U)
+#define BCH_STATUS0_RSVD0(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK)
+#define BCH_STATUS0_UNCORRECTABLE_MASK           (0x4U)
+#define BCH_STATUS0_UNCORRECTABLE_SHIFT          (2U)
+#define BCH_STATUS0_UNCORRECTABLE(x)             (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK)
+#define BCH_STATUS0_CORRECTED_MASK               (0x8U)
+#define BCH_STATUS0_CORRECTED_SHIFT              (3U)
+#define BCH_STATUS0_CORRECTED(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK)
+#define BCH_STATUS0_ALLONES_MASK                 (0x10U)
+#define BCH_STATUS0_ALLONES_SHIFT                (4U)
+#define BCH_STATUS0_ALLONES(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK)
+#define BCH_STATUS0_RSVD1_MASK                   (0xE0U)
+#define BCH_STATUS0_RSVD1_SHIFT                  (5U)
+#define BCH_STATUS0_RSVD1(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK)
+#define BCH_STATUS0_STATUS_BLK0_MASK             (0xFF00U)
+#define BCH_STATUS0_STATUS_BLK0_SHIFT            (8U)
+/*! STATUS_BLK0
+ *  0b00000000..No errors found on block.
+ *  0b00000001..One error found on block.
+ *  0b00000010..One errors found on block.
+ *  0b00000011..One errors found on block.
+ *  0b00000100..One errors found on block.
+ *  0b11111110..Block exhibited uncorrectable errors.
+ *  0b11111111..Page is erased.
+ */
+#define BCH_STATUS0_STATUS_BLK0(x)               (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK)
+#define BCH_STATUS0_COMPLETED_CE_MASK            (0xF0000U)
+#define BCH_STATUS0_COMPLETED_CE_SHIFT           (16U)
+#define BCH_STATUS0_COMPLETED_CE(x)              (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK)
+#define BCH_STATUS0_HANDLE_MASK                  (0xFFF00000U)
+#define BCH_STATUS0_HANDLE_SHIFT                 (20U)
+#define BCH_STATUS0_HANDLE(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK)
+/*! @} */
+/*! @name MODE - Hardware ECC Accelerator Mode Register */
+/*! @{ */
+#define BCH_MODE_ERASE_THRESHOLD_MASK            (0xFFU)
+#define BCH_MODE_ERASE_THRESHOLD_SHIFT           (0U)
+#define BCH_MODE_ERASE_THRESHOLD(x)              (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK)
+#define BCH_MODE_RSVD_MASK                       (0xFFFFFF00U)
+#define BCH_MODE_RSVD_SHIFT                      (8U)
+#define BCH_MODE_RSVD(x)                         (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK)
+/*! @} */
+/*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */
+/*! @{ */
+#define BCH_ENCODEPTR_ADDR_MASK                  (0xFFFFFFFFU)
+#define BCH_ENCODEPTR_ADDR_SHIFT                 (0U)
+#define BCH_ENCODEPTR_ADDR(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK)
+/*! @} */
+/*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */
+/*! @{ */
+#define BCH_DATAPTR_ADDR_MASK                    (0xFFFFFFFFU)
+#define BCH_DATAPTR_ADDR_SHIFT                   (0U)
+#define BCH_DATAPTR_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK)
+/*! @} */
+/*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */
+/*! @{ */
+#define BCH_METAPTR_ADDR_MASK                    (0xFFFFFFFFU)
+#define BCH_METAPTR_ADDR_SHIFT                   (0U)
+#define BCH_METAPTR_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK)
+/*! @} */
+/*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */
+/*! @{ */
+#define BCH_LAYOUTSELECT_CS0_SELECT_MASK         (0x3U)
+#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT        (0U)
+#define BCH_LAYOUTSELECT_CS0_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS1_SELECT_MASK         (0xCU)
+#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT        (2U)
+#define BCH_LAYOUTSELECT_CS1_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS2_SELECT_MASK         (0x30U)
+#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT        (4U)
+#define BCH_LAYOUTSELECT_CS2_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS3_SELECT_MASK         (0xC0U)
+#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT        (6U)
+#define BCH_LAYOUTSELECT_CS3_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS4_SELECT_MASK         (0x300U)
+#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT        (8U)
+#define BCH_LAYOUTSELECT_CS4_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS5_SELECT_MASK         (0xC00U)
+#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT        (10U)
+#define BCH_LAYOUTSELECT_CS5_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS6_SELECT_MASK         (0x3000U)
+#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT        (12U)
+#define BCH_LAYOUTSELECT_CS6_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS7_SELECT_MASK         (0xC000U)
+#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT        (14U)
+#define BCH_LAYOUTSELECT_CS7_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS8_SELECT_MASK         (0x30000U)
+#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT        (16U)
+#define BCH_LAYOUTSELECT_CS8_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS9_SELECT_MASK         (0xC0000U)
+#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT        (18U)
+#define BCH_LAYOUTSELECT_CS9_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS10_SELECT_MASK        (0x300000U)
+#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT       (20U)
+#define BCH_LAYOUTSELECT_CS10_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS11_SELECT_MASK        (0xC00000U)
+#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT       (22U)
+#define BCH_LAYOUTSELECT_CS11_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS12_SELECT_MASK        (0x3000000U)
+#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT       (24U)
+#define BCH_LAYOUTSELECT_CS12_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS13_SELECT_MASK        (0xC000000U)
+#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT       (26U)
+#define BCH_LAYOUTSELECT_CS13_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS14_SELECT_MASK        (0x30000000U)
+#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT       (28U)
+#define BCH_LAYOUTSELECT_CS14_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS15_SELECT_MASK        (0xC0000000U)
+#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT       (30U)
+#define BCH_LAYOUTSELECT_CS15_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK)
+/*! @} */
+/*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */
+/*! @{ */
+#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK        (0x3FFU)
+#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT       (0U)
+#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK)
+#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK     (0x400U)
+#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT    (10U)
+#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK)
+#define BCH_FLASH0LAYOUT0_ECC0_MASK              (0xF800U)
+#define BCH_FLASH0LAYOUT0_ECC0_SHIFT             (11U)
+/*! ECC0
+ *  0b00000..No ECC to be performed
+ *  0b00001..ECC 2 to be performed
+ *  0b00010..ECC 4 to be performed
+ *  0b11110..ECC 60 to be performed
+ *  0b11111..ECC 62 to be performed
+ */
+#define BCH_FLASH0LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK)
+#define BCH_FLASH0LAYOUT0_META_SIZE_MASK         (0xFF0000U)
+#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT        (16U)
+#define BCH_FLASH0LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK)
+#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
+#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT          (24U)
+#define BCH_FLASH0LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK)
+/*! @} */
+/*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */
+/*! @{ */
+#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK        (0x3FFU)
+#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT       (0U)
+#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK)
+#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK     (0x400U)
+#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT    (10U)
+#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK)
+#define BCH_FLASH0LAYOUT1_ECCN_MASK              (0xF800U)
+#define BCH_FLASH0LAYOUT1_ECCN_SHIFT             (11U)
+/*! ECCN
+ *  0b00000..No ECC to be performed
+ *  0b00001..ECC 2 to be performed
+ *  0b00010..ECC 4 to be performed
+ *  0b11110..ECC 60 to be performed
+ *  0b11111..ECC 62 to be performed
+ */
+#define BCH_FLASH0LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK)
+#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
+#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT        (16U)
+#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK)
+/*! @} */
+/*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */
+/*! @{ */
+#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK        (0x3FFU)
+#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT       (0U)
+#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK)
+#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK     (0x400U)
+#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT    (10U)
+#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK)
+#define BCH_FLASH1LAYOUT0_ECC0_MASK              (0xF800U)
+#define BCH_FLASH1LAYOUT0_ECC0_SHIFT             (11U)
+/*! ECC0
+ *  0b00000..No ECC to be performed
+ *  0b00001..ECC 2 to be performed
+ *  0b00010..ECC 4 to be performed
+ *  0b11110..ECC 60 to be performed
+ *  0b11111..ECC 62 to be performed
+ */
+#define BCH_FLASH1LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK)
+#define BCH_FLASH1LAYOUT0_META_SIZE_MASK         (0xFF0000U)
+#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT        (16U)
+#define BCH_FLASH1LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK)
+#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
+#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT          (24U)
+#define BCH_FLASH1LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK)
+/*! @} */
+/*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */
+/*! @{ */
+#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK        (0x3FFU)
+#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT       (0U)
+#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK)
+#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK     (0x400U)
+#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT    (10U)
+#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK)
+#define BCH_FLASH1LAYOUT1_ECCN_MASK              (0xF800U)
+#define BCH_FLASH1LAYOUT1_ECCN_SHIFT             (11U)
+/*! ECCN
+ *  0b00000..No ECC to be performed
+ *  0b00001..ECC 2 to be performed
+ *  0b00010..ECC 4 to be performed
+ *  0b11110..ECC 60 to be performed
+ *  0b11111..ECC 62 to be performed
+ */
+#define BCH_FLASH1LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK)
+#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
+#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT        (16U)
+#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK)
+/*! @} */
+/*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */
+/*! @{ */
+#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK        (0x3FFU)
+#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT       (0U)
+#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK)
+#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK     (0x400U)
+#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT    (10U)
+#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK)
+#define BCH_FLASH2LAYOUT0_ECC0_MASK              (0xF800U)
+#define BCH_FLASH2LAYOUT0_ECC0_SHIFT             (11U)
+/*! ECC0
+ *  0b00000..No ECC to be performed
+ *  0b00001..ECC 2 to be performed
+ *  0b00010..ECC 4 to be performed
+ *  0b11110..ECC 60 to be performed
+ *  0b11111..ECC 62 to be performed
+ */
+#define BCH_FLASH2LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK)
+#define BCH_FLASH2LAYOUT0_META_SIZE_MASK         (0xFF0000U)
+#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT        (16U)
+#define BCH_FLASH2LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK)
+#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
+#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT          (24U)
+#define BCH_FLASH2LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK)
+/*! @} */
+/*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */
+/*! @{ */
+#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK        (0x3FFU)
+#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT       (0U)
+#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK)
+#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK     (0x400U)
+#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT    (10U)
+#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK)
+#define BCH_FLASH2LAYOUT1_ECCN_MASK              (0xF800U)
+#define BCH_FLASH2LAYOUT1_ECCN_SHIFT             (11U)
+/*! ECCN
+ *  0b00000..No ECC to be performed
+ *  0b00001..ECC 2 to be performed
+ *  0b00010..ECC 4 to be performed
+ *  0b11110..ECC 60 to be performed
+ *  0b11111..ECC 62 to be performed
+ */
+#define BCH_FLASH2LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK)
+#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
+#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT        (16U)
+#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK)
+/*! @} */
+/*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */
+/*! @{ */
+#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK        (0x3FFU)
+#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT       (0U)
+#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK)
+#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK     (0x400U)
+#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT    (10U)
+#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK)
+#define BCH_FLASH3LAYOUT0_ECC0_MASK              (0xF800U)
+#define BCH_FLASH3LAYOUT0_ECC0_SHIFT             (11U)
+/*! ECC0
+ *  0b00000..No ECC to be performed
+ *  0b00001..ECC 2 to be performed
+ *  0b00010..ECC 4 to be performed
+ *  0b11110..ECC 60 to be performed
+ *  0b11111..ECC 62 to be performed
+ */
+#define BCH_FLASH3LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK)
+#define BCH_FLASH3LAYOUT0_META_SIZE_MASK         (0xFF0000U)
+#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT        (16U)
+#define BCH_FLASH3LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK)
+#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
+#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT          (24U)
+#define BCH_FLASH3LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK)
+/*! @} */
+/*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */
+/*! @{ */
+#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK        (0x3FFU)
+#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT       (0U)
+#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK)
+#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK     (0x400U)
+#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT    (10U)
+#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK)
+#define BCH_FLASH3LAYOUT1_ECCN_MASK              (0xF800U)
+#define BCH_FLASH3LAYOUT1_ECCN_SHIFT             (11U)
+/*! ECCN
+ *  0b00000..No ECC to be performed
+ *  0b00001..ECC 2 to be performed
+ *  0b00010..ECC 4 to be performed
+ *  0b11110..ECC 60 to be performed
+ *  0b11111..ECC 62 to be performed
+ */
+#define BCH_FLASH3LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK)
+#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
+#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT        (16U)
+#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK)
+/*! @} */
+/*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */
+/*! @{ */
+#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK         (0x3FU)
+#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT        (0U)
+#define BCH_DEBUG0_DEBUG_REG_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK)
+#define BCH_DEBUG0_RSVD0_MASK                    (0xC0U)
+#define BCH_DEBUG0_RSVD0_SHIFT                   (6U)
+#define BCH_DEBUG0_RSVD0(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK)
+#define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK       (0x100U)
+#define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT      (8U)
+/*! BM_KES_TEST_BYPASS
+ *  0b0..Bus master address generator for SYND_GEN writes operates normally.
+ *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
+ */
+#define BCH_DEBUG0_BM_KES_TEST_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK)
+#define BCH_DEBUG0_KES_DEBUG_STALL_MASK          (0x200U)
+#define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT         (9U)
+/*! KES_DEBUG_STALL
+ *  0b0..KES FSM proceeds to next block supplied by bus master.
+ *  0b1..KES FSM waits after current equations are solved and the search engine is started.
+ */
+#define BCH_DEBUG0_KES_DEBUG_STALL(x)            (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK)
+#define BCH_DEBUG0_KES_DEBUG_STEP_MASK           (0x400U)
+#define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT          (10U)
+#define BCH_DEBUG0_KES_DEBUG_STEP(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK)
+#define BCH_DEBUG0_KES_STANDALONE_MASK           (0x800U)
+#define BCH_DEBUG0_KES_STANDALONE_SHIFT          (11U)
+/*! KES_STANDALONE
+ *  0b0..Bus master address generator for SYND_GEN writes operates normally.
+ *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
+ */
+#define BCH_DEBUG0_KES_STANDALONE(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK)
+#define BCH_DEBUG0_KES_DEBUG_KICK_MASK           (0x1000U)
+#define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT          (12U)
+#define BCH_DEBUG0_KES_DEBUG_KICK(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK)
+#define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK         (0x2000U)
+#define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT        (13U)
+/*! KES_DEBUG_MODE4K
+ *  0b1..Mode is set for 4K NAND pages.
+ *  0b1..Mode is set for 2K NAND pages.
+ */
+#define BCH_DEBUG0_KES_DEBUG_MODE4K(x)           (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK)
+#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK   (0x4000U)
+#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT  (14U)
+/*! KES_DEBUG_PAYLOAD_FLAG
+ *  0b1..Payload is set for 512 bytes data block.
+ *  0b1..Payload is set for 65 or 19 bytes auxiliary block.
+ */
+#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x)     (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK)
+#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK     (0x8000U)
+#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT    (15U)
+#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x)       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK)
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
+/*! KES_DEBUG_SYNDROME_SYMBOL
+ *  0b000000000..Bus master address generator for SYND_GEN writes operates normally.
+ *  0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
+ */
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x)  (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK)
+#define BCH_DEBUG0_RSVD1_MASK                    (0xFE000000U)
+#define BCH_DEBUG0_RSVD1_SHIFT                   (25U)
+#define BCH_DEBUG0_RSVD1(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK)
+/*! @} */
+/*! @name DEBUG0_SET - Hardware BCH ECC Debug Register0 */
+/*! @{ */
+#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK     (0x3FU)
+#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT    (0U)
+#define BCH_DEBUG0_SET_DEBUG_REG_SELECT(x)       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK)
+#define BCH_DEBUG0_SET_RSVD0_MASK                (0xC0U)
+#define BCH_DEBUG0_SET_RSVD0_SHIFT               (6U)
+#define BCH_DEBUG0_SET_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD0_SHIFT)) & BCH_DEBUG0_SET_RSVD0_MASK)
+#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK   (0x100U)
+#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT  (8U)
+/*! BM_KES_TEST_BYPASS
+ *  0b0..Bus master address generator for SYND_GEN writes operates normally.
+ *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
+ */
+#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS(x)     (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK)
+#define BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK      (0x200U)
+#define BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT     (9U)
+/*! KES_DEBUG_STALL
+ *  0b0..KES FSM proceeds to next block supplied by bus master.
+ *  0b1..KES FSM waits after current equations are solved and the search engine is started.
+ */
+#define BCH_DEBUG0_SET_KES_DEBUG_STALL(x)        (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK)
+#define BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK       (0x400U)
+#define BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT      (10U)
+#define BCH_DEBUG0_SET_KES_DEBUG_STEP(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK)
+#define BCH_DEBUG0_SET_KES_STANDALONE_MASK       (0x800U)
+#define BCH_DEBUG0_SET_KES_STANDALONE_SHIFT      (11U)
+/*! KES_STANDALONE
+ *  0b0..Bus master address generator for SYND_GEN writes operates normally.
+ *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
+ */
+#define BCH_DEBUG0_SET_KES_STANDALONE(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_SET_KES_STANDALONE_MASK)
+#define BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK       (0x1000U)
+#define BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT      (12U)
+#define BCH_DEBUG0_SET_KES_DEBUG_KICK(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK)
+#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK     (0x2000U)
+#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT    (13U)
+/*! KES_DEBUG_MODE4K
+ *  0b1..Mode is set for 4K NAND pages.
+ *  0b1..Mode is set for 2K NAND pages.
+ */
+#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K(x)       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK)
+#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
+#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
+/*! KES_DEBUG_PAYLOAD_FLAG
+ *  0b1..Payload is set for 512 bytes data block.
+ *  0b1..Payload is set for 65 or 19 bytes auxiliary block.
+ */
+#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK)
+#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
+#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
+#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND(x)   (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK)
+#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
+#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
+/*! KES_DEBUG_SYNDROME_SYMBOL
+ *  0b000000000..Bus master address generator for SYND_GEN writes operates normally.
+ *  0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
+ */
+#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK)
+#define BCH_DEBUG0_SET_RSVD1_MASK                (0xFE000000U)
+#define BCH_DEBUG0_SET_RSVD1_SHIFT               (25U)
+#define BCH_DEBUG0_SET_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD1_SHIFT)) & BCH_DEBUG0_SET_RSVD1_MASK)
+/*! @} */
+/*! @name DEBUG0_CLR - Hardware BCH ECC Debug Register0 */
+/*! @{ */
+#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK     (0x3FU)
+#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT    (0U)
+#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT(x)       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK)
+#define BCH_DEBUG0_CLR_RSVD0_MASK                (0xC0U)
+#define BCH_DEBUG0_CLR_RSVD0_SHIFT               (6U)
+#define BCH_DEBUG0_CLR_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD0_SHIFT)) & BCH_DEBUG0_CLR_RSVD0_MASK)
+#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK   (0x100U)
+#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT  (8U)
+/*! BM_KES_TEST_BYPASS
+ *  0b0..Bus master address generator for SYND_GEN writes operates normally.
+ *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
+ */
+#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS(x)     (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK)
+#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK      (0x200U)
+#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT     (9U)
+/*! KES_DEBUG_STALL
+ *  0b0..KES FSM proceeds to next block supplied by bus master.
+ *  0b1..KES FSM waits after current equations are solved and the search engine is started.
+ */
+#define BCH_DEBUG0_CLR_KES_DEBUG_STALL(x)        (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK)
+#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK       (0x400U)
+#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT      (10U)
+#define BCH_DEBUG0_CLR_KES_DEBUG_STEP(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK)
+#define BCH_DEBUG0_CLR_KES_STANDALONE_MASK       (0x800U)
+#define BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT      (11U)
+/*! KES_STANDALONE
+ *  0b0..Bus master address generator for SYND_GEN writes operates normally.
+ *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
+ */
+#define BCH_DEBUG0_CLR_KES_STANDALONE(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_CLR_KES_STANDALONE_MASK)
+#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK       (0x1000U)
+#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT      (12U)
+#define BCH_DEBUG0_CLR_KES_DEBUG_KICK(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK)
+#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK     (0x2000U)
+#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT    (13U)
+/*! KES_DEBUG_MODE4K
+ *  0b1..Mode is set for 4K NAND pages.
+ *  0b1..Mode is set for 2K NAND pages.
+ */
+#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K(x)       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK)
+#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
+#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
+/*! KES_DEBUG_PAYLOAD_FLAG
+ *  0b1..Payload is set for 512 bytes data block.
+ *  0b1..Payload is set for 65 or 19 bytes auxiliary block.
+ */
+#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK)
+#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
+#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
+#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND(x)   (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK)
+#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
+#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
+/*! KES_DEBUG_SYNDROME_SYMBOL
+ *  0b000000000..Bus master address generator for SYND_GEN writes operates normally.
+ *  0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
+ */
+#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK)
+#define BCH_DEBUG0_CLR_RSVD1_MASK                (0xFE000000U)
+#define BCH_DEBUG0_CLR_RSVD1_SHIFT               (25U)
+#define BCH_DEBUG0_CLR_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD1_SHIFT)) & BCH_DEBUG0_CLR_RSVD1_MASK)
+/*! @} */
+/*! @name DEBUG0_TOG - Hardware BCH ECC Debug Register0 */
+/*! @{ */
+#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK     (0x3FU)
+#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT    (0U)
+#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT(x)       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK)
+#define BCH_DEBUG0_TOG_RSVD0_MASK                (0xC0U)
+#define BCH_DEBUG0_TOG_RSVD0_SHIFT               (6U)
+#define BCH_DEBUG0_TOG_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD0_SHIFT)) & BCH_DEBUG0_TOG_RSVD0_MASK)
+#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK   (0x100U)
+#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT  (8U)
+/*! BM_KES_TEST_BYPASS
+ *  0b0..Bus master address generator for SYND_GEN writes operates normally.
+ *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
+ */
+#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS(x)     (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK)
+#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK      (0x200U)
+#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT     (9U)
+/*! KES_DEBUG_STALL
+ *  0b0..KES FSM proceeds to next block supplied by bus master.
+ *  0b1..KES FSM waits after current equations are solved and the search engine is started.
+ */
+#define BCH_DEBUG0_TOG_KES_DEBUG_STALL(x)        (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK)
+#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK       (0x400U)
+#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT      (10U)
+#define BCH_DEBUG0_TOG_KES_DEBUG_STEP(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK)
+#define BCH_DEBUG0_TOG_KES_STANDALONE_MASK       (0x800U)
+#define BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT      (11U)
+/*! KES_STANDALONE
+ *  0b0..Bus master address generator for SYND_GEN writes operates normally.
+ *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
+ */
+#define BCH_DEBUG0_TOG_KES_STANDALONE(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_TOG_KES_STANDALONE_MASK)
+#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK       (0x1000U)
+#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT      (12U)
+#define BCH_DEBUG0_TOG_KES_DEBUG_KICK(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK)
+#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK     (0x2000U)
+#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT    (13U)
+/*! KES_DEBUG_MODE4K
+ *  0b1..Mode is set for 4K NAND pages.
+ *  0b1..Mode is set for 2K NAND pages.
+ */
+#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K(x)       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK)
+#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
+#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
+/*! KES_DEBUG_PAYLOAD_FLAG
+ *  0b1..Payload is set for 512 bytes data block.
+ *  0b1..Payload is set for 65 or 19 bytes auxiliary block.
+ */
+#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK)
+#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
+#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
+#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND(x)   (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK)
+#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
+#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
+/*! KES_DEBUG_SYNDROME_SYMBOL
+ *  0b000000000..Bus master address generator for SYND_GEN writes operates normally.
+ *  0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
+ */
+#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK)
+#define BCH_DEBUG0_TOG_RSVD1_MASK                (0xFE000000U)
+#define BCH_DEBUG0_TOG_RSVD1_SHIFT               (25U)
+#define BCH_DEBUG0_TOG_RSVD1(x)                  (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD1_SHIFT)) & BCH_DEBUG0_TOG_RSVD1_MASK)
+/*! @} */
+/*! @name DBGKESREAD - KES Debug Read Register */
+/*! @{ */
+#define BCH_DBGKESREAD_VALUES_MASK               (0xFFFFFFFFU)
+#define BCH_DBGKESREAD_VALUES_SHIFT              (0U)
+#define BCH_DBGKESREAD_VALUES(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK)
+/*! @} */
+/*! @name DBGCSFEREAD - Chien Search Debug Read Register */
+/*! @{ */
+#define BCH_DBGCSFEREAD_VALUES_MASK              (0xFFFFFFFFU)
+#define BCH_DBGCSFEREAD_VALUES_SHIFT             (0U)
+#define BCH_DBGCSFEREAD_VALUES(x)                (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK)
+/*! @} */
+/*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */
+/*! @{ */
+#define BCH_DBGSYNDGENREAD_VALUES_MASK           (0xFFFFFFFFU)
+#define BCH_DBGSYNDGENREAD_VALUES_SHIFT          (0U)
+#define BCH_DBGSYNDGENREAD_VALUES(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK)
+/*! @} */
+/*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */
+/*! @{ */
+#define BCH_DBGAHBMREAD_VALUES_MASK              (0xFFFFFFFFU)
+#define BCH_DBGAHBMREAD_VALUES_SHIFT             (0U)
+#define BCH_DBGAHBMREAD_VALUES(x)                (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK)
+/*! @} */
+/*! @name BLOCKNAME - Block Name Register */
+/*! @{ */
+#define BCH_BLOCKNAME_NAME_MASK                  (0xFFFFFFFFU)
+#define BCH_BLOCKNAME_NAME_SHIFT                 (0U)
+#define BCH_BLOCKNAME_NAME(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK)
+/*! @} */
+/*! @name VERSION - BCH Version Register */
+/*! @{ */
+#define BCH_VERSION_STEP_MASK                    (0xFFFFU)
+#define BCH_VERSION_STEP_SHIFT                   (0U)
+#define BCH_VERSION_STEP(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK)
+#define BCH_VERSION_MINOR_MASK                   (0xFF0000U)
+#define BCH_VERSION_MINOR_SHIFT                  (16U)
+#define BCH_VERSION_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK)
+#define BCH_VERSION_MAJOR_MASK                   (0xFF000000U)
+#define BCH_VERSION_MAJOR_SHIFT                  (24U)
+#define BCH_VERSION_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK)
+/*! @} */
+/*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */
+/*! @{ */
+#define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK        (0x1FFU)
+#define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT       (0U)
+#define BCH_DEBUG1_ERASED_ZERO_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK)
+#define BCH_DEBUG1_RSVD_MASK                     (0x7FFFFE00U)
+#define BCH_DEBUG1_RSVD_SHIFT                    (9U)
+#define BCH_DEBUG1_RSVD(x)                       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK)
+#define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK       (0x80000000U)
+#define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT      (31U)
+/*! DEBUG1_PREERASECHK
+ *  0b0..Turn off pre-erase check
+ *  0b1..Turn on pre-erase check
+ */
+#define BCH_DEBUG1_DEBUG1_PREERASECHK(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK)
+/*! @} */
+/*!
+ * @}
+ */ /* end of group BCH_Register_Masks */
+/* BCH - Peripheral instance base addresses */
+/** Peripheral BCH base address */
+#define BCH_BASE                                 (0x33004000u)
+/** Peripheral BCH base pointer */
+#define BCH                                      ((BCH_Type *)BCH_BASE)
+/** Array initializer of BCH peripheral base addresses */
+#define BCH_BASE_ADDRS                           { BCH_BASE }
+/** Array initializer of BCH peripheral base pointers */
+#define BCH_BASE_PTRS                            { BCH }
+/** Interrupt vectors for the BCH peripheral type */
+#define BCH_IRQS                                 { BCH_IRQn }
+/*!
+ * @}
+ */ /* end of group BCH_Peripheral_Access_Layer */
+/* ----------------------------------------------------------------------------
+   -- CCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
+ * @{
+ */
+/** CCM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t GPR0;                              /**< General Purpose Register, offset: 0x0 */
+  __IO uint32_t GPR0_SET;                          /**< General Purpose Register, offset: 0x4 */
+  __IO uint32_t GPR0_CLR;                          /**< General Purpose Register, offset: 0x8 */
+  __IO uint32_t GPR0_TOG;                          /**< General Purpose Register, offset: 0xC */
+       uint8_t RESERVED_0[2032];
+  struct {                                         /* offset: 0x800, array step: 0x10 */
+    __IO uint32_t PLL_CTRL;                          /**< CCM PLL Control Register, array offset: 0x800, array step: 0x10 */
+    __IO uint32_t PLL_CTRL_SET;                      /**< CCM PLL Control Register, array offset: 0x804, array step: 0x10 */
+    __IO uint32_t PLL_CTRL_CLR;                      /**< CCM PLL Control Register, array offset: 0x808, array step: 0x10 */
+    __IO uint32_t PLL_CTRL_TOG;                      /**< CCM PLL Control Register, array offset: 0x80C, array step: 0x10 */
+  } PLL_CTRL[39];
+       uint8_t RESERVED_1[13712];
+  struct {                                         /* offset: 0x4000, array step: 0x10 */
+    __IO uint32_t CCGR;                              /**< CCM Clock Gating Register, array offset: 0x4000, array step: 0x10 */
+    __IO uint32_t CCGR_SET;                          /**< CCM Clock Gating Register, array offset: 0x4004, array step: 0x10 */
+    __IO uint32_t CCGR_CLR;                          /**< CCM Clock Gating Register, array offset: 0x4008, array step: 0x10 */
+    __IO uint32_t CCGR_TOG;                          /**< CCM Clock Gating Register, array offset: 0x400C, array step: 0x10 */
+  } CCGR[191];
+       uint8_t RESERVED_2[13328];
+  struct {                                         /* offset: 0x8000, array step: 0x80 */
+    __IO uint32_t TARGET_ROOT;                       /**< Target Register, array offset: 0x8000, array step: 0x80 */
+    __IO uint32_t TARGET_ROOT_SET;                   /**< Target Register, array offset: 0x8004, array step: 0x80 */
+    __IO uint32_t TARGET_ROOT_CLR;                   /**< Target Register, array offset: 0x8008, array step: 0x80 */
+    __IO uint32_t TARGET_ROOT_TOG;                   /**< Target Register, array offset: 0x800C, array step: 0x80 */
+    __IO uint32_t MISC;                              /**< Miscellaneous Register, array offset: 0x8010, array step: 0x80 */
+    __IO uint32_t MISC_ROOT_SET;                     /**< Miscellaneous Register, array offset: 0x8014, array step: 0x80 */
+    __IO uint32_t MISC_ROOT_CLR;                     /**< Miscellaneous Register, array offset: 0x8018, array step: 0x80 */
+    __IO uint32_t MISC_ROOT_TOG;                     /**< Miscellaneous Register, array offset: 0x801C, array step: 0x80 */
+    __IO uint32_t POST;                              /**< Post Divider Register, array offset: 0x8020, array step: 0x80 */
+    __IO uint32_t POST_ROOT_SET;                     /**< Post Divider Register, array offset: 0x8024, array step: 0x80 */
+    __IO uint32_t POST_ROOT_CLR;                     /**< Post Divider Register, array offset: 0x8028, array step: 0x80 */
+    __IO uint32_t POST_ROOT_TOG;                     /**< Post Divider Register, array offset: 0x802C, array step: 0x80 */
+    __IO uint32_t PRE;                               /**< Pre Divider Register, array offset: 0x8030, array step: 0x80 */
+    __IO uint32_t PRE_ROOT_SET;                      /**< Pre Divider Register, array offset: 0x8034, array step: 0x80 */
+    __IO uint32_t PRE_ROOT_CLR;                      /**< Pre Divider Register, array offset: 0x8038, array step: 0x80 */
+    __IO uint32_t PRE_ROOT_TOG;                      /**< Pre Divider Register, array offset: 0x803C, array step: 0x80 */
+         uint8_t RESERVED_0[48];
+    __IO uint32_t ACCESS_CTRL;                       /**< Access Control Register, array offset: 0x8070, array step: 0x80 */
+    __IO uint32_t ACCESS_CTRL_ROOT_SET;              /**< Access Control Register, array offset: 0x8074, array step: 0x80 */
+    __IO uint32_t ACCESS_CTRL_ROOT_CLR;              /**< Access Control Register, array offset: 0x8078, array step: 0x80 */
+    __IO uint32_t ACCESS_CTRL_ROOT_TOG;              /**< Access Control Register, array offset: 0x807C, array step: 0x80 */
+  } ROOT[142];
+} CCM_Type;
+/* ----------------------------------------------------------------------------
+   -- CCM Register Masks
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup CCM_Register_Masks CCM Register Masks
+ * @{
+ */
+/*! @name GPR0 - General Purpose Register */
+/*! @{ */
+#define CCM_GPR0_GP0_MASK                        (0xFFFFFFFFU)
+#define CCM_GPR0_GP0_SHIFT                       (0U)
+#define CCM_GPR0_GP0(x)                          (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_GP0_SHIFT)) & CCM_GPR0_GP0_MASK)
+/*! @} */
+/*! @name GPR0_SET - General Purpose Register */
+/*! @{ */
+#define CCM_GPR0_SET_GP0_MASK                    (0xFFFFFFFFU)
+#define CCM_GPR0_SET_GP0_SHIFT                   (0U)
+#define CCM_GPR0_SET_GP0(x)                      (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_SET_GP0_SHIFT)) & CCM_GPR0_SET_GP0_MASK)
+/*! @} */
+/*! @name GPR0_CLR - General Purpose Register */
+/*! @{ */
+#define CCM_GPR0_CLR_GP0_MASK                    (0xFFFFFFFFU)
+#define CCM_GPR0_CLR_GP0_SHIFT                   (0U)
+#define CCM_GPR0_CLR_GP0(x)                      (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_CLR_GP0_SHIFT)) & CCM_GPR0_CLR_GP0_MASK)
+/*! @} */
+/*! @name GPR0_TOG - General Purpose Register */
+/*! @{ */
+#define CCM_GPR0_TOG_GP0_MASK                    (0xFFFFFFFFU)
+#define CCM_GPR0_TOG_GP0_SHIFT                   (0U)
+#define CCM_GPR0_TOG_GP0(x)                      (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_TOG_GP0_SHIFT)) & CCM_GPR0_TOG_GP0_MASK)
+/*! @} */
+/*! @name PLL_CTRL - CCM PLL Control Register */
+/*! @{ */
+#define CCM_PLL_CTRL_SETTING0_MASK               (0x3U)
+#define CCM_PLL_CTRL_SETTING0_SHIFT              (0U)
+/*! SETTING0
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_PLL_CTRL_SETTING0(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING0_SHIFT)) & CCM_PLL_CTRL_SETTING0_MASK)
+#define CCM_PLL_CTRL_SETTING1_MASK               (0x30U)
+#define CCM_PLL_CTRL_SETTING1_SHIFT              (4U)
+/*! SETTING1
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_PLL_CTRL_SETTING1(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING1_SHIFT)) & CCM_PLL_CTRL_SETTING1_MASK)
+#define CCM_PLL_CTRL_SETTING2_MASK               (0x300U)
+#define CCM_PLL_CTRL_SETTING2_SHIFT              (8U)
+/*! SETTING2
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_PLL_CTRL_SETTING2(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING2_SHIFT)) & CCM_PLL_CTRL_SETTING2_MASK)
+#define CCM_PLL_CTRL_SETTING3_MASK               (0x3000U)
+#define CCM_PLL_CTRL_SETTING3_SHIFT              (12U)
+/*! SETTING3
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_PLL_CTRL_SETTING3(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING3_SHIFT)) & CCM_PLL_CTRL_SETTING3_MASK)
+/*! @} */
+/* The count of CCM_PLL_CTRL */
+#define CCM_PLL_CTRL_COUNT                       (39U)
+/*! @name PLL_CTRL_SET - CCM PLL Control Register */
+/*! @{ */
+#define CCM_PLL_CTRL_SET_SETTING0_MASK           (0x3U)
+#define CCM_PLL_CTRL_SET_SETTING0_SHIFT          (0U)
+/*! SETTING0
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_PLL_CTRL_SET_SETTING0(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING0_SHIFT)) & CCM_PLL_CTRL_SET_SETTING0_MASK)
+#define CCM_PLL_CTRL_SET_SETTING1_MASK           (0x30U)
+#define CCM_PLL_CTRL_SET_SETTING1_SHIFT          (4U)
+/*! SETTING1
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_PLL_CTRL_SET_SETTING1(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING1_SHIFT)) & CCM_PLL_CTRL_SET_SETTING1_MASK)
+#define CCM_PLL_CTRL_SET_SETTING2_MASK           (0x300U)
+#define CCM_PLL_CTRL_SET_SETTING2_SHIFT          (8U)
+/*! SETTING2
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_PLL_CTRL_SET_SETTING2(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING2_SHIFT)) & CCM_PLL_CTRL_SET_SETTING2_MASK)
+#define CCM_PLL_CTRL_SET_SETTING3_MASK           (0x3000U)
+#define CCM_PLL_CTRL_SET_SETTING3_SHIFT          (12U)
+/*! SETTING3
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_PLL_CTRL_SET_SETTING3(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING3_SHIFT)) & CCM_PLL_CTRL_SET_SETTING3_MASK)
+/*! @} */
+/* The count of CCM_PLL_CTRL_SET */
+#define CCM_PLL_CTRL_SET_COUNT                   (39U)
+/*! @name PLL_CTRL_CLR - CCM PLL Control Register */
+/*! @{ */
+#define CCM_PLL_CTRL_CLR_SETTING0_MASK           (0x3U)
+#define CCM_PLL_CTRL_CLR_SETTING0_SHIFT          (0U)
+/*! SETTING0
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_PLL_CTRL_CLR_SETTING0(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING0_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING0_MASK)
+#define CCM_PLL_CTRL_CLR_SETTING1_MASK           (0x30U)
+#define CCM_PLL_CTRL_CLR_SETTING1_SHIFT          (4U)
+/*! SETTING1
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_PLL_CTRL_CLR_SETTING1(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING1_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING1_MASK)
+#define CCM_PLL_CTRL_CLR_SETTING2_MASK           (0x300U)
+#define CCM_PLL_CTRL_CLR_SETTING2_SHIFT          (8U)
+/*! SETTING2
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_PLL_CTRL_CLR_SETTING2(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING2_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING2_MASK)
+#define CCM_PLL_CTRL_CLR_SETTING3_MASK           (0x3000U)
+#define CCM_PLL_CTRL_CLR_SETTING3_SHIFT          (12U)
+/*! SETTING3
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_PLL_CTRL_CLR_SETTING3(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING3_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING3_MASK)
+/*! @} */
+/* The count of CCM_PLL_CTRL_CLR */
+#define CCM_PLL_CTRL_CLR_COUNT                   (39U)
+/*! @name PLL_CTRL_TOG - CCM PLL Control Register */
+/*! @{ */
+#define CCM_PLL_CTRL_TOG_SETTING0_MASK           (0x3U)
+#define CCM_PLL_CTRL_TOG_SETTING0_SHIFT          (0U)
+/*! SETTING0
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_PLL_CTRL_TOG_SETTING0(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING0_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING0_MASK)
+#define CCM_PLL_CTRL_TOG_SETTING1_MASK           (0x30U)
+#define CCM_PLL_CTRL_TOG_SETTING1_SHIFT          (4U)
+/*! SETTING1
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_PLL_CTRL_TOG_SETTING1(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING1_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING1_MASK)
+#define CCM_PLL_CTRL_TOG_SETTING2_MASK           (0x300U)
+#define CCM_PLL_CTRL_TOG_SETTING2_SHIFT          (8U)
+/*! SETTING2
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_PLL_CTRL_TOG_SETTING2(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING2_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING2_MASK)
+#define CCM_PLL_CTRL_TOG_SETTING3_MASK           (0x3000U)
+#define CCM_PLL_CTRL_TOG_SETTING3_SHIFT          (12U)
+/*! SETTING3
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_PLL_CTRL_TOG_SETTING3(x)             (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING3_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING3_MASK)
+/*! @} */
+/* The count of CCM_PLL_CTRL_TOG */
+#define CCM_PLL_CTRL_TOG_COUNT                   (39U)
+/*! @name CCGR - CCM Clock Gating Register */
+/*! @{ */
+#define CCM_CCGR_SETTING0_MASK                   (0x3U)
+#define CCM_CCGR_SETTING0_SHIFT                  (0U)
+/*! SETTING0
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_CCGR_SETTING0(x)                     (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING0_SHIFT)) & CCM_CCGR_SETTING0_MASK)
+#define CCM_CCGR_SETTING1_MASK                   (0x30U)
+#define CCM_CCGR_SETTING1_SHIFT                  (4U)
+/*! SETTING1
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_CCGR_SETTING1(x)                     (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING1_SHIFT)) & CCM_CCGR_SETTING1_MASK)
+#define CCM_CCGR_SETTING2_MASK                   (0x300U)
+#define CCM_CCGR_SETTING2_SHIFT                  (8U)
+/*! SETTING2
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_CCGR_SETTING2(x)                     (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING2_SHIFT)) & CCM_CCGR_SETTING2_MASK)
+#define CCM_CCGR_SETTING3_MASK                   (0x3000U)
+#define CCM_CCGR_SETTING3_SHIFT                  (12U)
+/*! SETTING3
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_CCGR_SETTING3(x)                     (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING3_SHIFT)) & CCM_CCGR_SETTING3_MASK)
+/*! @} */
+/* The count of CCM_CCGR */
+#define CCM_CCGR_COUNT                           (191U)
+/*! @name CCGR_SET - CCM Clock Gating Register */
+/*! @{ */
+#define CCM_CCGR_SET_SETTING0_MASK               (0x3U)
+#define CCM_CCGR_SET_SETTING0_SHIFT              (0U)
+/*! SETTING0
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_CCGR_SET_SETTING0(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING0_SHIFT)) & CCM_CCGR_SET_SETTING0_MASK)
+#define CCM_CCGR_SET_SETTING1_MASK               (0x30U)
+#define CCM_CCGR_SET_SETTING1_SHIFT              (4U)
+/*! SETTING1
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_CCGR_SET_SETTING1(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING1_SHIFT)) & CCM_CCGR_SET_SETTING1_MASK)
+#define CCM_CCGR_SET_SETTING2_MASK               (0x300U)
+#define CCM_CCGR_SET_SETTING2_SHIFT              (8U)
+/*! SETTING2
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_CCGR_SET_SETTING2(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING2_SHIFT)) & CCM_CCGR_SET_SETTING2_MASK)
+#define CCM_CCGR_SET_SETTING3_MASK               (0x3000U)
+#define CCM_CCGR_SET_SETTING3_SHIFT              (12U)
+/*! SETTING3
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_CCGR_SET_SETTING3(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING3_SHIFT)) & CCM_CCGR_SET_SETTING3_MASK)
+/*! @} */
+/* The count of CCM_CCGR_SET */
+#define CCM_CCGR_SET_COUNT                       (191U)
+/*! @name CCGR_CLR - CCM Clock Gating Register */
+/*! @{ */
+#define CCM_CCGR_CLR_SETTING0_MASK               (0x3U)
+#define CCM_CCGR_CLR_SETTING0_SHIFT              (0U)
+/*! SETTING0
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_CCGR_CLR_SETTING0(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING0_SHIFT)) & CCM_CCGR_CLR_SETTING0_MASK)
+#define CCM_CCGR_CLR_SETTING1_MASK               (0x30U)
+#define CCM_CCGR_CLR_SETTING1_SHIFT              (4U)
+/*! SETTING1
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_CCGR_CLR_SETTING1(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING1_SHIFT)) & CCM_CCGR_CLR_SETTING1_MASK)
+#define CCM_CCGR_CLR_SETTING2_MASK               (0x300U)
+#define CCM_CCGR_CLR_SETTING2_SHIFT              (8U)
+/*! SETTING2
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_CCGR_CLR_SETTING2(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING2_SHIFT)) & CCM_CCGR_CLR_SETTING2_MASK)
+#define CCM_CCGR_CLR_SETTING3_MASK               (0x3000U)
+#define CCM_CCGR_CLR_SETTING3_SHIFT              (12U)
+/*! SETTING3
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_CCGR_CLR_SETTING3(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING3_SHIFT)) & CCM_CCGR_CLR_SETTING3_MASK)
+/*! @} */
+/* The count of CCM_CCGR_CLR */
+#define CCM_CCGR_CLR_COUNT                       (191U)
+/*! @name CCGR_TOG - CCM Clock Gating Register */
+/*! @{ */
+#define CCM_CCGR_TOG_SETTING0_MASK               (0x3U)
+#define CCM_CCGR_TOG_SETTING0_SHIFT              (0U)
+/*! SETTING0
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_CCGR_TOG_SETTING0(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING0_SHIFT)) & CCM_CCGR_TOG_SETTING0_MASK)
+#define CCM_CCGR_TOG_SETTING1_MASK               (0x30U)
+#define CCM_CCGR_TOG_SETTING1_SHIFT              (4U)
+/*! SETTING1
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_CCGR_TOG_SETTING1(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING1_SHIFT)) & CCM_CCGR_TOG_SETTING1_MASK)
+#define CCM_CCGR_TOG_SETTING2_MASK               (0x300U)
+#define CCM_CCGR_TOG_SETTING2_SHIFT              (8U)
+/*! SETTING2
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_CCGR_TOG_SETTING2(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING2_SHIFT)) & CCM_CCGR_TOG_SETTING2_MASK)
+#define CCM_CCGR_TOG_SETTING3_MASK               (0x3000U)
+#define CCM_CCGR_TOG_SETTING3_SHIFT              (12U)
+/*! SETTING3
+ *  0b00..Domain clocks not needed
+ *  0b01..Domain clocks needed when in RUN
+ *  0b10..Domain clocks needed when in RUN and WAIT
+ *  0b11..Domain clocks needed all the time
+ */
+#define CCM_CCGR_TOG_SETTING3(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING3_SHIFT)) & CCM_CCGR_TOG_SETTING3_MASK)
+/*! @} */
+/* The count of CCM_CCGR_TOG */
+#define CCM_CCGR_TOG_COUNT                       (191U)
+/*! @name TARGET_ROOT - Target Register */
+/*! @{ */
+#define CCM_TARGET_ROOT_POST_PODF_MASK           (0x3FU)
+#define CCM_TARGET_ROOT_POST_PODF_SHIFT          (0U)
+/*! POST_PODF
+ *  0b000000..Divide by 1
+ *  0b000001..Divide by 2
+ *  0b000010..Divide by 3
+ *  0b000011..Divide by 4
+ *  0b000100..Divide by 5
+ *  0b000101..Divide by 6
+ *  0b111111..Divide by 64
+ */
+#define CCM_TARGET_ROOT_POST_PODF(x)             (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_POST_PODF_MASK)
+#define CCM_TARGET_ROOT_PRE_PODF_MASK            (0x70000U)
+#define CCM_TARGET_ROOT_PRE_PODF_SHIFT           (16U)
+/*! PRE_PODF
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 3
+ *  0b011..Divide by 4
+ *  0b100..Divide by 5
+ *  0b101..Divide by 6
+ *  0b110..Divide by 7
+ *  0b111..Divide by 8
+ */
+#define CCM_TARGET_ROOT_PRE_PODF(x)              (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_PRE_PODF_MASK)
+#define CCM_TARGET_ROOT_MUX_MASK                 (0x7000000U)
+#define CCM_TARGET_ROOT_MUX_SHIFT                (24U)
+#define CCM_TARGET_ROOT_MUX(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_MUX_SHIFT)) & CCM_TARGET_ROOT_MUX_MASK)
+#define CCM_TARGET_ROOT_ENABLE_MASK              (0x10000000U)
+#define CCM_TARGET_ROOT_ENABLE_SHIFT             (28U)
+/*! ENABLE
+ *  0b0..clock root is OFF
+ *  0b1..clock root is ON
+ */
+#define CCM_TARGET_ROOT_ENABLE(x)                (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_ENABLE_SHIFT)) & CCM_TARGET_ROOT_ENABLE_MASK)
+/*! @} */
+/* The count of CCM_TARGET_ROOT */
+#define CCM_TARGET_ROOT_COUNT                    (142U)
+/*! @name TARGET_ROOT_SET - Target Register */
+/*! @{ */
+#define CCM_TARGET_ROOT_SET_POST_PODF_MASK       (0x3FU)
+#define CCM_TARGET_ROOT_SET_POST_PODF_SHIFT      (0U)
+/*! POST_PODF
+ *  0b000000..Divide by 1
+ *  0b000001..Divide by 2
+ *  0b000010..Divide by 3
+ *  0b000011..Divide by 4
+ *  0b000100..Divide by 5
+ *  0b000101..Divide by 6
+ *  0b111111..Divide by 64
+ */
+#define CCM_TARGET_ROOT_SET_POST_PODF(x)         (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_POST_PODF_MASK)
+#define CCM_TARGET_ROOT_SET_PRE_PODF_MASK        (0x70000U)
+#define CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT       (16U)
+/*! PRE_PODF
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 3
+ *  0b011..Divide by 4
+ *  0b100..Divide by 5
+ *  0b101..Divide by 6
+ *  0b110..Divide by 7
+ *  0b111..Divide by 8
+ */
+#define CCM_TARGET_ROOT_SET_PRE_PODF(x)          (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_PRE_PODF_MASK)
+#define CCM_TARGET_ROOT_SET_MUX_MASK             (0x7000000U)
+#define CCM_TARGET_ROOT_SET_MUX_SHIFT            (24U)
+#define CCM_TARGET_ROOT_SET_MUX(x)               (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_MUX_SHIFT)) & CCM_TARGET_ROOT_SET_MUX_MASK)
+#define CCM_TARGET_ROOT_SET_ENABLE_MASK          (0x10000000U)
+#define CCM_TARGET_ROOT_SET_ENABLE_SHIFT         (28U)
+/*! ENABLE
+ *  0b0..clock root is OFF
+ *  0b1..clock root is ON
+ */
+#define CCM_TARGET_ROOT_SET_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_ENABLE_SHIFT)) & CCM_TARGET_ROOT_SET_ENABLE_MASK)
+/*! @} */
+/* The count of CCM_TARGET_ROOT_SET */
+#define CCM_TARGET_ROOT_SET_COUNT                (142U)
+/*! @name TARGET_ROOT_CLR - Target Register */
+/*! @{ */
+#define CCM_TARGET_ROOT_CLR_POST_PODF_MASK       (0x3FU)
+#define CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT      (0U)
+/*! POST_PODF
+ *  0b000000..Divide by 1
+ *  0b000001..Divide by 2
+ *  0b000010..Divide by 3
+ *  0b000011..Divide by 4
+ *  0b000100..Divide by 5
+ *  0b000101..Divide by 6
+ *  0b111111..Divide by 64
+ */
+#define CCM_TARGET_ROOT_CLR_POST_PODF(x)         (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_POST_PODF_MASK)
+#define CCM_TARGET_ROOT_CLR_PRE_PODF_MASK        (0x70000U)
+#define CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT       (16U)
+/*! PRE_PODF
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 3
+ *  0b011..Divide by 4
+ *  0b100..Divide by 5
+ *  0b101..Divide by 6
+ *  0b110..Divide by 7
+ *  0b111..Divide by 8
+ */
+#define CCM_TARGET_ROOT_CLR_PRE_PODF(x)          (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_PRE_PODF_MASK)
+#define CCM_TARGET_ROOT_CLR_MUX_MASK             (0x7000000U)
+#define CCM_TARGET_ROOT_CLR_MUX_SHIFT            (24U)
+#define CCM_TARGET_ROOT_CLR_MUX(x)               (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_MUX_SHIFT)) & CCM_TARGET_ROOT_CLR_MUX_MASK)
+#define CCM_TARGET_ROOT_CLR_ENABLE_MASK          (0x10000000U)
+#define CCM_TARGET_ROOT_CLR_ENABLE_SHIFT         (28U)
+/*! ENABLE
+ *  0b0..clock root is OFF
+ *  0b1..clock root is ON
+ */
+#define CCM_TARGET_ROOT_CLR_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_ENABLE_SHIFT)) & CCM_TARGET_ROOT_CLR_ENABLE_MASK)
+/*! @} */
+/* The count of CCM_TARGET_ROOT_CLR */
+#define CCM_TARGET_ROOT_CLR_COUNT                (142U)
+/*! @name TARGET_ROOT_TOG - Target Register */
+/*! @{ */
+#define CCM_TARGET_ROOT_TOG_POST_PODF_MASK       (0x3FU)
+#define CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT      (0U)
+/*! POST_PODF
+ *  0b000000..Divide by 1
+ *  0b000001..Divide by 2
+ *  0b000010..Divide by 3
+ *  0b000011..Divide by 4
+ *  0b000100..Divide by 5
+ *  0b000101..Divide by 6
+ *  0b111111..Divide by 64
+ */
+#define CCM_TARGET_ROOT_TOG_POST_PODF(x)         (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_POST_PODF_MASK)
+#define CCM_TARGET_ROOT_TOG_PRE_PODF_MASK        (0x70000U)
+#define CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT       (16U)
+/*! PRE_PODF
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 3
+ *  0b011..Divide by 4
+ *  0b100..Divide by 5
+ *  0b101..Divide by 6
+ *  0b110..Divide by 7
+ *  0b111..Divide by 8
+ */
+#define CCM_TARGET_ROOT_TOG_PRE_PODF(x)          (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_PRE_PODF_MASK)
+#define CCM_TARGET_ROOT_TOG_MUX_MASK             (0x7000000U)
+#define CCM_TARGET_ROOT_TOG_MUX_SHIFT            (24U)
+#define CCM_TARGET_ROOT_TOG_MUX(x)               (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_MUX_SHIFT)) & CCM_TARGET_ROOT_TOG_MUX_MASK)
+#define CCM_TARGET_ROOT_TOG_ENABLE_MASK          (0x10000000U)
+#define CCM_TARGET_ROOT_TOG_ENABLE_SHIFT         (28U)
+/*! ENABLE
+ *  0b0..clock root is OFF
+ *  0b1..clock root is ON
+ */
+#define CCM_TARGET_ROOT_TOG_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_ENABLE_SHIFT)) & CCM_TARGET_ROOT_TOG_ENABLE_MASK)
+/*! @} */
+/* The count of CCM_TARGET_ROOT_TOG */
+#define CCM_TARGET_ROOT_TOG_COUNT                (142U)
+/*! @name MISC - Miscellaneous Register */
+/*! @{ */
+#define CCM_MISC_AUTHEN_FAIL_MASK                (0x1U)
+#define CCM_MISC_AUTHEN_FAIL_SHIFT               (0U)
+#define CCM_MISC_AUTHEN_FAIL(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_MISC_AUTHEN_FAIL_SHIFT)) & CCM_MISC_AUTHEN_FAIL_MASK)
+#define CCM_MISC_TIMEOUT_MASK                    (0x10U)
+#define CCM_MISC_TIMEOUT_SHIFT                   (4U)
+#define CCM_MISC_TIMEOUT(x)                      (((uint32_t)(((uint32_t)(x)) << CCM_MISC_TIMEOUT_SHIFT)) & CCM_MISC_TIMEOUT_MASK)
+#define CCM_MISC_VIOLATE_MASK                    (0x100U)
+#define CCM_MISC_VIOLATE_SHIFT                   (8U)
+#define CCM_MISC_VIOLATE(x)                      (((uint32_t)(((uint32_t)(x)) << CCM_MISC_VIOLATE_SHIFT)) & CCM_MISC_VIOLATE_MASK)
+/*! @} */
+/* The count of CCM_MISC */
+#define CCM_MISC_COUNT                           (142U)
+/*! @name MISC_ROOT_SET - Miscellaneous Register */
+/*! @{ */
+#define CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK       (0x1U)
+#define CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT      (0U)
+#define CCM_MISC_ROOT_SET_AUTHEN_FAIL(x)         (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK)
+#define CCM_MISC_ROOT_SET_TIMEOUT_MASK           (0x10U)
+#define CCM_MISC_ROOT_SET_TIMEOUT_SHIFT          (4U)
+#define CCM_MISC_ROOT_SET_TIMEOUT(x)             (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_SET_TIMEOUT_MASK)
+#define CCM_MISC_ROOT_SET_VIOLATE_MASK           (0x100U)
+#define CCM_MISC_ROOT_SET_VIOLATE_SHIFT          (8U)
+#define CCM_MISC_ROOT_SET_VIOLATE(x)             (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_VIOLATE_SHIFT)) & CCM_MISC_ROOT_SET_VIOLATE_MASK)
+/*! @} */
+/* The count of CCM_MISC_ROOT_SET */
+#define CCM_MISC_ROOT_SET_COUNT                  (142U)
+/*! @name MISC_ROOT_CLR - Miscellaneous Register */
+/*! @{ */
+#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK       (0x1U)
+#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT      (0U)
+#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL(x)         (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK)
+#define CCM_MISC_ROOT_CLR_TIMEOUT_MASK           (0x10U)
+#define CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT          (4U)
+#define CCM_MISC_ROOT_CLR_TIMEOUT(x)             (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_CLR_TIMEOUT_MASK)
+#define CCM_MISC_ROOT_CLR_VIOLATE_MASK           (0x100U)
+#define CCM_MISC_ROOT_CLR_VIOLATE_SHIFT          (8U)
+#define CCM_MISC_ROOT_CLR_VIOLATE(x)             (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_VIOLATE_SHIFT)) & CCM_MISC_ROOT_CLR_VIOLATE_MASK)
+/*! @} */
+/* The count of CCM_MISC_ROOT_CLR */
+#define CCM_MISC_ROOT_CLR_COUNT                  (142U)
+/*! @name MISC_ROOT_TOG - Miscellaneous Register */
+/*! @{ */
+#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK       (0x1U)
+#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT      (0U)
+#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL(x)         (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK)
+#define CCM_MISC_ROOT_TOG_TIMEOUT_MASK           (0x10U)
+#define CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT          (4U)
+#define CCM_MISC_ROOT_TOG_TIMEOUT(x)             (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_TOG_TIMEOUT_MASK)
+#define CCM_MISC_ROOT_TOG_VIOLATE_MASK           (0x100U)
+#define CCM_MISC_ROOT_TOG_VIOLATE_SHIFT          (8U)
+#define CCM_MISC_ROOT_TOG_VIOLATE(x)             (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_VIOLATE_SHIFT)) & CCM_MISC_ROOT_TOG_VIOLATE_MASK)
+/*! @} */
+/* The count of CCM_MISC_ROOT_TOG */
+#define CCM_MISC_ROOT_TOG_COUNT                  (142U)
+/*! @name POST - Post Divider Register */
+/*! @{ */
+#define CCM_POST_POST_PODF_MASK                  (0x3FU)
+#define CCM_POST_POST_PODF_SHIFT                 (0U)
+/*! POST_PODF
+ *  0b000000..Divide by 1
+ *  0b000001..Divide by 2
+ *  0b000010..Divide by 3
+ *  0b000011..Divide by 4
+ *  0b000100..Divide by 5
+ *  0b000101..Divide by 6
+ *  0b111111..Divide by 64
+ */
+#define CCM_POST_POST_PODF(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_POST_POST_PODF_SHIFT)) & CCM_POST_POST_PODF_MASK)
+#define CCM_POST_BUSY1_MASK                      (0x80U)
+#define CCM_POST_BUSY1_SHIFT                     (7U)
+#define CCM_POST_BUSY1(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY1_SHIFT)) & CCM_POST_BUSY1_MASK)
+#define CCM_POST_SELECT_MASK                     (0x10000000U)
+#define CCM_POST_SELECT_SHIFT                    (28U)
+/*! SELECT
+ *  0b0..select branch A
+ *  0b1..select branch B
+ */
+#define CCM_POST_SELECT(x)                       (((uint32_t)(((uint32_t)(x)) << CCM_POST_SELECT_SHIFT)) & CCM_POST_SELECT_MASK)
+#define CCM_POST_BUSY2_MASK                      (0x80000000U)
+#define CCM_POST_BUSY2_SHIFT                     (31U)
+#define CCM_POST_BUSY2(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY2_SHIFT)) & CCM_POST_BUSY2_MASK)
+/*! @} */
+/* The count of CCM_POST */
+#define CCM_POST_COUNT                           (142U)
+/*! @name POST_ROOT_SET - Post Divider Register */
+/*! @{ */
+#define CCM_POST_ROOT_SET_POST_PODF_MASK         (0x3FU)
+#define CCM_POST_ROOT_SET_POST_PODF_SHIFT        (0U)
+/*! POST_PODF
+ *  0b000000..Divide by 1
+ *  0b000001..Divide by 2
+ *  0b000010..Divide by 3
+ *  0b000011..Divide by 4
+ *  0b000100..Divide by 5
+ *  0b000101..Divide by 6
+ *  0b111111..Divide by 64
+ */
+#define CCM_POST_ROOT_SET_POST_PODF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_POST_PODF_SHIFT)) & CCM_POST_ROOT_SET_POST_PODF_MASK)
+#define CCM_POST_ROOT_SET_BUSY1_MASK             (0x80U)
+#define CCM_POST_ROOT_SET_BUSY1_SHIFT            (7U)
+#define CCM_POST_ROOT_SET_BUSY1(x)               (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY1_SHIFT)) & CCM_POST_ROOT_SET_BUSY1_MASK)
+#define CCM_POST_ROOT_SET_SELECT_MASK            (0x10000000U)
+#define CCM_POST_ROOT_SET_SELECT_SHIFT           (28U)
+/*! SELECT
+ *  0b0..select branch A
+ *  0b1..select branch B
+ */
+#define CCM_POST_ROOT_SET_SELECT(x)              (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_SELECT_SHIFT)) & CCM_POST_ROOT_SET_SELECT_MASK)
+#define CCM_POST_ROOT_SET_BUSY2_MASK             (0x80000000U)
+#define CCM_POST_ROOT_SET_BUSY2_SHIFT            (31U)
+#define CCM_POST_ROOT_SET_BUSY2(x)               (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY2_SHIFT)) & CCM_POST_ROOT_SET_BUSY2_MASK)
+/*! @} */
+/* The count of CCM_POST_ROOT_SET */
+#define CCM_POST_ROOT_SET_COUNT                  (142U)
+/*! @name POST_ROOT_CLR - Post Divider Register */
+/*! @{ */
+#define CCM_POST_ROOT_CLR_POST_PODF_MASK         (0x3FU)
+#define CCM_POST_ROOT_CLR_POST_PODF_SHIFT        (0U)
+/*! POST_PODF
+ *  0b000000..Divide by 1
+ *  0b000001..Divide by 2
+ *  0b000010..Divide by 3
+ *  0b000011..Divide by 4
+ *  0b000100..Divide by 5
+ *  0b000101..Divide by 6
+ *  0b111111..Divide by 64
+ */
+#define CCM_POST_ROOT_CLR_POST_PODF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_POST_PODF_SHIFT)) & CCM_POST_ROOT_CLR_POST_PODF_MASK)
+#define CCM_POST_ROOT_CLR_BUSY1_MASK             (0x80U)
+#define CCM_POST_ROOT_CLR_BUSY1_SHIFT            (7U)
+#define CCM_POST_ROOT_CLR_BUSY1(x)               (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY1_SHIFT)) & CCM_POST_ROOT_CLR_BUSY1_MASK)
+#define CCM_POST_ROOT_CLR_SELECT_MASK            (0x10000000U)
+#define CCM_POST_ROOT_CLR_SELECT_SHIFT           (28U)
+/*! SELECT
+ *  0b0..select branch A
+ *  0b1..select branch B
+ */
+#define CCM_POST_ROOT_CLR_SELECT(x)              (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_SELECT_SHIFT)) & CCM_POST_ROOT_CLR_SELECT_MASK)
+#define CCM_POST_ROOT_CLR_BUSY2_MASK             (0x80000000U)
+#define CCM_POST_ROOT_CLR_BUSY2_SHIFT            (31U)
+#define CCM_POST_ROOT_CLR_BUSY2(x)               (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY2_SHIFT)) & CCM_POST_ROOT_CLR_BUSY2_MASK)
+/*! @} */
+/* The count of CCM_POST_ROOT_CLR */
+#define CCM_POST_ROOT_CLR_COUNT                  (142U)
+/*! @name POST_ROOT_TOG - Post Divider Register */
+/*! @{ */
+#define CCM_POST_ROOT_TOG_POST_PODF_MASK         (0x3FU)
+#define CCM_POST_ROOT_TOG_POST_PODF_SHIFT        (0U)
+/*! POST_PODF
+ *  0b000000..Divide by 1
+ *  0b000001..Divide by 2
+ *  0b000010..Divide by 3
+ *  0b000011..Divide by 4
+ *  0b000100..Divide by 5
+ *  0b000101..Divide by 6
+ *  0b111111..Divide by 64
+ */
+#define CCM_POST_ROOT_TOG_POST_PODF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_POST_PODF_SHIFT)) & CCM_POST_ROOT_TOG_POST_PODF_MASK)
+#define CCM_POST_ROOT_TOG_BUSY1_MASK             (0x80U)
+#define CCM_POST_ROOT_TOG_BUSY1_SHIFT            (7U)
+#define CCM_POST_ROOT_TOG_BUSY1(x)               (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY1_SHIFT)) & CCM_POST_ROOT_TOG_BUSY1_MASK)
+#define CCM_POST_ROOT_TOG_SELECT_MASK            (0x10000000U)
+#define CCM_POST_ROOT_TOG_SELECT_SHIFT           (28U)
+/*! SELECT
+ *  0b0..select branch A
+ *  0b1..select branch B
+ */
+#define CCM_POST_ROOT_TOG_SELECT(x)              (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_SELECT_SHIFT)) & CCM_POST_ROOT_TOG_SELECT_MASK)
+#define CCM_POST_ROOT_TOG_BUSY2_MASK             (0x80000000U)
+#define CCM_POST_ROOT_TOG_BUSY2_SHIFT            (31U)
+#define CCM_POST_ROOT_TOG_BUSY2(x)               (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY2_SHIFT)) & CCM_POST_ROOT_TOG_BUSY2_MASK)
+/*! @} */
+/* The count of CCM_POST_ROOT_TOG */
+#define CCM_POST_ROOT_TOG_COUNT                  (142U)
+/*! @name PRE - Pre Divider Register */
+/*! @{ */
+#define CCM_PRE_PRE_PODF_B_MASK                  (0x7U)
+#define CCM_PRE_PRE_PODF_B_SHIFT                 (0U)
+/*! PRE_PODF_B
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 3
+ *  0b011..Divide by 4
+ *  0b100..Divide by 5
+ *  0b101..Divide by 6
+ *  0b110..Divide by 7
+ *  0b111..Divide by 8
+ */
+#define CCM_PRE_PRE_PODF_B(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_B_SHIFT)) & CCM_PRE_PRE_PODF_B_MASK)
+#define CCM_PRE_BUSY0_MASK                       (0x8U)
+#define CCM_PRE_BUSY0_SHIFT                      (3U)
+#define CCM_PRE_BUSY0(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY0_SHIFT)) & CCM_PRE_BUSY0_MASK)
+#define CCM_PRE_MUX_B_MASK                       (0x700U)
+#define CCM_PRE_MUX_B_SHIFT                      (8U)
+#define CCM_PRE_MUX_B(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_B_SHIFT)) & CCM_PRE_MUX_B_MASK)
+#define CCM_PRE_EN_B_MASK                        (0x1000U)
+#define CCM_PRE_EN_B_SHIFT                       (12U)
+/*! EN_B
+ *  0b0..Clock shutdown
+ *  0b1..Clock ON
+ */
+#define CCM_PRE_EN_B(x)                          (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_B_SHIFT)) & CCM_PRE_EN_B_MASK)
+#define CCM_PRE_BUSY1_MASK                       (0x8000U)
+#define CCM_PRE_BUSY1_SHIFT                      (15U)
+#define CCM_PRE_BUSY1(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY1_SHIFT)) & CCM_PRE_BUSY1_MASK)
+#define CCM_PRE_PRE_PODF_A_MASK                  (0x70000U)
+#define CCM_PRE_PRE_PODF_A_SHIFT                 (16U)
+/*! PRE_PODF_A
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 3
+ *  0b011..Divide by 4
+ *  0b100..Divide by 5
+ *  0b101..Divide by 6
+ *  0b110..Divide by 7
+ *  0b111..Divide by 8
+ */
+#define CCM_PRE_PRE_PODF_A(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_A_SHIFT)) & CCM_PRE_PRE_PODF_A_MASK)
+#define CCM_PRE_BUSY3_MASK                       (0x80000U)
+#define CCM_PRE_BUSY3_SHIFT                      (19U)
+#define CCM_PRE_BUSY3(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY3_SHIFT)) & CCM_PRE_BUSY3_MASK)
+#define CCM_PRE_MUX_A_MASK                       (0x7000000U)
+#define CCM_PRE_MUX_A_SHIFT                      (24U)
+#define CCM_PRE_MUX_A(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_A_SHIFT)) & CCM_PRE_MUX_A_MASK)
+#define CCM_PRE_EN_A_MASK                        (0x10000000U)
+#define CCM_PRE_EN_A_SHIFT                       (28U)
+/*! EN_A
+ *  0b0..Clock shutdown
+ *  0b1..clock ON
+ */
+#define CCM_PRE_EN_A(x)                          (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_A_SHIFT)) & CCM_PRE_EN_A_MASK)
+#define CCM_PRE_BUSY4_MASK                       (0x80000000U)
+#define CCM_PRE_BUSY4_SHIFT                      (31U)
+#define CCM_PRE_BUSY4(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY4_SHIFT)) & CCM_PRE_BUSY4_MASK)
+/*! @} */
+/* The count of CCM_PRE */
+#define CCM_PRE_COUNT                            (142U)
+/*! @name PRE_ROOT_SET - Pre Divider Register */
+/*! @{ */
+#define CCM_PRE_ROOT_SET_PRE_PODF_B_MASK         (0x7U)
+#define CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT        (0U)
+/*! PRE_PODF_B
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 3
+ *  0b011..Divide by 4
+ *  0b100..Divide by 5
+ *  0b101..Divide by 6
+ *  0b110..Divide by 7
+ *  0b111..Divide by 8
+ */
+#define CCM_PRE_ROOT_SET_PRE_PODF_B(x)           (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_B_MASK)
+#define CCM_PRE_ROOT_SET_BUSY0_MASK              (0x8U)
+#define CCM_PRE_ROOT_SET_BUSY0_SHIFT             (3U)
+#define CCM_PRE_ROOT_SET_BUSY0(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY0_SHIFT)) & CCM_PRE_ROOT_SET_BUSY0_MASK)
+#define CCM_PRE_ROOT_SET_MUX_B_MASK              (0x700U)
+#define CCM_PRE_ROOT_SET_MUX_B_SHIFT             (8U)
+#define CCM_PRE_ROOT_SET_MUX_B(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_B_SHIFT)) & CCM_PRE_ROOT_SET_MUX_B_MASK)
+#define CCM_PRE_ROOT_SET_EN_B_MASK               (0x1000U)
+#define CCM_PRE_ROOT_SET_EN_B_SHIFT              (12U)
+/*! EN_B
+ *  0b0..Clock shutdown
+ *  0b1..Clock ON
+ */
+#define CCM_PRE_ROOT_SET_EN_B(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_B_SHIFT)) & CCM_PRE_ROOT_SET_EN_B_MASK)
+#define CCM_PRE_ROOT_SET_BUSY1_MASK              (0x8000U)
+#define CCM_PRE_ROOT_SET_BUSY1_SHIFT             (15U)
+#define CCM_PRE_ROOT_SET_BUSY1(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY1_SHIFT)) & CCM_PRE_ROOT_SET_BUSY1_MASK)
+#define CCM_PRE_ROOT_SET_PRE_PODF_A_MASK         (0x70000U)
+#define CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT        (16U)
+/*! PRE_PODF_A
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 3
+ *  0b011..Divide by 4
+ *  0b100..Divide by 5
+ *  0b101..Divide by 6
+ *  0b110..Divide by 7
+ *  0b111..Divide by 8
+ */
+#define CCM_PRE_ROOT_SET_PRE_PODF_A(x)           (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_A_MASK)
+#define CCM_PRE_ROOT_SET_BUSY3_MASK              (0x80000U)
+#define CCM_PRE_ROOT_SET_BUSY3_SHIFT             (19U)
+#define CCM_PRE_ROOT_SET_BUSY3(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY3_SHIFT)) & CCM_PRE_ROOT_SET_BUSY3_MASK)
+#define CCM_PRE_ROOT_SET_MUX_A_MASK              (0x7000000U)
+#define CCM_PRE_ROOT_SET_MUX_A_SHIFT             (24U)
+#define CCM_PRE_ROOT_SET_MUX_A(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_A_SHIFT)) & CCM_PRE_ROOT_SET_MUX_A_MASK)
+#define CCM_PRE_ROOT_SET_EN_A_MASK               (0x10000000U)
+#define CCM_PRE_ROOT_SET_EN_A_SHIFT              (28U)
+/*! EN_A
+ *  0b0..Clock shutdown
+ *  0b1..clock ON
+ */
+#define CCM_PRE_ROOT_SET_EN_A(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_A_SHIFT)) & CCM_PRE_ROOT_SET_EN_A_MASK)
+#define CCM_PRE_ROOT_SET_BUSY4_MASK              (0x80000000U)
+#define CCM_PRE_ROOT_SET_BUSY4_SHIFT             (31U)
+#define CCM_PRE_ROOT_SET_BUSY4(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY4_SHIFT)) & CCM_PRE_ROOT_SET_BUSY4_MASK)
+/*! @} */
+/* The count of CCM_PRE_ROOT_SET */
+#define CCM_PRE_ROOT_SET_COUNT                   (142U)
+/*! @name PRE_ROOT_CLR - Pre Divider Register */
+/*! @{ */
+#define CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK         (0x7U)
+#define CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT        (0U)
+/*! PRE_PODF_B
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 3
+ *  0b011..Divide by 4
+ *  0b100..Divide by 5
+ *  0b101..Divide by 6
+ *  0b110..Divide by 7
+ *  0b111..Divide by 8
+ */
+#define CCM_PRE_ROOT_CLR_PRE_PODF_B(x)           (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK)
+#define CCM_PRE_ROOT_CLR_BUSY0_MASK              (0x8U)
+#define CCM_PRE_ROOT_CLR_BUSY0_SHIFT             (3U)
+#define CCM_PRE_ROOT_CLR_BUSY0(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY0_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY0_MASK)
+#define CCM_PRE_ROOT_CLR_MUX_B_MASK              (0x700U)
+#define CCM_PRE_ROOT_CLR_MUX_B_SHIFT             (8U)
+#define CCM_PRE_ROOT_CLR_MUX_B(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_B_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_B_MASK)
+#define CCM_PRE_ROOT_CLR_EN_B_MASK               (0x1000U)
+#define CCM_PRE_ROOT_CLR_EN_B_SHIFT              (12U)
+/*! EN_B
+ *  0b0..Clock shutdown
+ *  0b1..Clock ON
+ */
+#define CCM_PRE_ROOT_CLR_EN_B(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_B_SHIFT)) & CCM_PRE_ROOT_CLR_EN_B_MASK)
+#define CCM_PRE_ROOT_CLR_BUSY1_MASK              (0x8000U)
+#define CCM_PRE_ROOT_CLR_BUSY1_SHIFT             (15U)
+#define CCM_PRE_ROOT_CLR_BUSY1(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY1_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY1_MASK)
+#define CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK         (0x70000U)
+#define CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT        (16U)
+/*! PRE_PODF_A
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 3
+ *  0b011..Divide by 4
+ *  0b100..Divide by 5
+ *  0b101..Divide by 6
+ *  0b110..Divide by 7
+ *  0b111..Divide by 8
+ */
+#define CCM_PRE_ROOT_CLR_PRE_PODF_A(x)           (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK)
+#define CCM_PRE_ROOT_CLR_BUSY3_MASK              (0x80000U)
+#define CCM_PRE_ROOT_CLR_BUSY3_SHIFT             (19U)
+#define CCM_PRE_ROOT_CLR_BUSY3(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY3_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY3_MASK)
+#define CCM_PRE_ROOT_CLR_MUX_A_MASK              (0x7000000U)
+#define CCM_PRE_ROOT_CLR_MUX_A_SHIFT             (24U)
+#define CCM_PRE_ROOT_CLR_MUX_A(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_A_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_A_MASK)
+#define CCM_PRE_ROOT_CLR_EN_A_MASK               (0x10000000U)
+#define CCM_PRE_ROOT_CLR_EN_A_SHIFT              (28U)
+/*! EN_A
+ *  0b0..Clock shutdown
+ *  0b1..clock ON
+ */
+#define CCM_PRE_ROOT_CLR_EN_A(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_A_SHIFT)) & CCM_PRE_ROOT_CLR_EN_A_MASK)
+#define CCM_PRE_ROOT_CLR_BUSY4_MASK              (0x80000000U)
+#define CCM_PRE_ROOT_CLR_BUSY4_SHIFT             (31U)
+#define CCM_PRE_ROOT_CLR_BUSY4(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY4_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY4_MASK)
+/*! @} */
+/* The count of CCM_PRE_ROOT_CLR */
+#define CCM_PRE_ROOT_CLR_COUNT                   (142U)
+/*! @name PRE_ROOT_TOG - Pre Divider Register */
+/*! @{ */
+#define CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK         (0x7U)
+#define CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT        (0U)
+/*! PRE_PODF_B
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 3
+ *  0b011..Divide by 4
+ *  0b100..Divide by 5
+ *  0b101..Divide by 6
+ *  0b110..Divide by 7
+ *  0b111..Divide by 8
+ */
+#define CCM_PRE_ROOT_TOG_PRE_PODF_B(x)           (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK)
+#define CCM_PRE_ROOT_TOG_BUSY0_MASK              (0x8U)
+#define CCM_PRE_ROOT_TOG_BUSY0_SHIFT             (3U)
+#define CCM_PRE_ROOT_TOG_BUSY0(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY0_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY0_MASK)
+#define CCM_PRE_ROOT_TOG_MUX_B_MASK              (0x700U)
+#define CCM_PRE_ROOT_TOG_MUX_B_SHIFT             (8U)
+#define CCM_PRE_ROOT_TOG_MUX_B(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_B_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_B_MASK)
+#define CCM_PRE_ROOT_TOG_EN_B_MASK               (0x1000U)
+#define CCM_PRE_ROOT_TOG_EN_B_SHIFT              (12U)
+/*! EN_B
+ *  0b0..Clock shutdown
+ *  0b1..Clock ON
+ */
+#define CCM_PRE_ROOT_TOG_EN_B(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_B_SHIFT)) & CCM_PRE_ROOT_TOG_EN_B_MASK)
+#define CCM_PRE_ROOT_TOG_BUSY1_MASK              (0x8000U)
+#define CCM_PRE_ROOT_TOG_BUSY1_SHIFT             (15U)
+#define CCM_PRE_ROOT_TOG_BUSY1(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY1_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY1_MASK)
+#define CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK         (0x70000U)
+#define CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT        (16U)
+/*! PRE_PODF_A
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 3
+ *  0b011..Divide by 4
+ *  0b100..Divide by 5
+ *  0b101..Divide by 6
+ *  0b110..Divide by 7
+ *  0b111..Divide by 8
+ */
+#define CCM_PRE_ROOT_TOG_PRE_PODF_A(x)           (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK)
+#define CCM_PRE_ROOT_TOG_BUSY3_MASK              (0x80000U)
+#define CCM_PRE_ROOT_TOG_BUSY3_SHIFT             (19U)
+#define CCM_PRE_ROOT_TOG_BUSY3(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY3_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY3_MASK)
+#define CCM_PRE_ROOT_TOG_MUX_A_MASK              (0x7000000U)
+#define CCM_PRE_ROOT_TOG_MUX_A_SHIFT             (24U)
+#define CCM_PRE_ROOT_TOG_MUX_A(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_A_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_A_MASK)
+#define CCM_PRE_ROOT_TOG_EN_A_MASK               (0x10000000U)
+#define CCM_PRE_ROOT_TOG_EN_A_SHIFT              (28U)
+/*! EN_A
+ *  0b0..Clock shutdown
+ *  0b1..clock ON
+ */
+#define CCM_PRE_ROOT_TOG_EN_A(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_A_SHIFT)) & CCM_PRE_ROOT_TOG_EN_A_MASK)
+#define CCM_PRE_ROOT_TOG_BUSY4_MASK              (0x80000000U)
+#define CCM_PRE_ROOT_TOG_BUSY4_SHIFT             (31U)
+#define CCM_PRE_ROOT_TOG_BUSY4(x)                (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY4_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY4_MASK)
+/*! @} */
+/* The count of CCM_PRE_ROOT_TOG */
+#define CCM_PRE_ROOT_TOG_COUNT                   (142U)
+/*! @name ACCESS_CTRL - Access Control Register */
+/*! @{ */
+#define CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK        (0xFU)
+#define CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT       (0U)
+#define CCM_ACCESS_CTRL_DOMAIN0_INFO(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK)
+#define CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK        (0xF0U)
+#define CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT       (4U)
+#define CCM_ACCESS_CTRL_DOMAIN1_INFO(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK)
+#define CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK        (0xF00U)
+#define CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT       (8U)
+#define CCM_ACCESS_CTRL_DOMAIN2_INFO(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK)
+#define CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK        (0xF000U)
+#define CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT       (12U)
+#define CCM_ACCESS_CTRL_DOMAIN3_INFO(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK)
+#define CCM_ACCESS_CTRL_OWNER_ID_MASK            (0x30000U)
+#define CCM_ACCESS_CTRL_OWNER_ID_SHIFT           (16U)
+/*! OWNER_ID
+ *  0b00..domaino
+ *  0b01..domain1
+ *  0b10..domain2
+ *  0b11..domain3
+ */
+#define CCM_ACCESS_CTRL_OWNER_ID(x)              (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_OWNER_ID_MASK)
+#define CCM_ACCESS_CTRL_MUTEX_MASK               (0x100000U)
+#define CCM_ACCESS_CTRL_MUTEX_SHIFT              (20U)
+/*! MUTEX
+ *  0b0..Semaphore is free to take
+ *  0b1..Semaphore is taken
+ */
+#define CCM_ACCESS_CTRL_MUTEX(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_MUTEX_MASK)
+#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK   (0x1000000U)
+#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT  (24U)
+/*! DOMAIN0_WHITELIST
+ *  0b0..Domain cannot change the setting
+ *  0b1..Domain can change the setting
+ */
+#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK)
+#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK   (0x2000000U)
+#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT  (25U)
+/*! DOMAIN1_WHITELIST
+ *  0b0..Domain cannot change the setting
+ *  0b1..Domain can change the setting
+ */
+#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK)
+#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK   (0x4000000U)
+#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT  (26U)
+/*! DOMAIN2_WHITELIST
+ *  0b0..Domain cannot change the setting
+ *  0b1..Domain can change the setting
+ */
+#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK)
+#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK   (0x8000000U)
+#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT  (27U)
+/*! DOMAIN3_WHITELIST
+ *  0b0..Domain cannot change the setting
+ *  0b1..Domain can change the setting
+ */
+#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK)
+#define CCM_ACCESS_CTRL_SEMA_EN_MASK             (0x10000000U)
+#define CCM_ACCESS_CTRL_SEMA_EN_SHIFT            (28U)
+/*! SEMA_EN
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CCM_ACCESS_CTRL_SEMA_EN(x)               (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_SEMA_EN_MASK)
+#define CCM_ACCESS_CTRL_LOCK_MASK                (0x80000000U)
+#define CCM_ACCESS_CTRL_LOCK_SHIFT               (31U)
+/*! LOCK
+ *  0b0..Access control inactive
+ *  0b1..Access control active
+ */
+#define CCM_ACCESS_CTRL_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_LOCK_SHIFT)) & CCM_ACCESS_CTRL_LOCK_MASK)
+/*! @} */
+/* The count of CCM_ACCESS_CTRL */
+#define CCM_ACCESS_CTRL_COUNT                    (142U)
+/*! @name ACCESS_CTRL_ROOT_SET - Access Control Register */
+/*! @{ */
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK (0xFU)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT (0U)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK (0xF0U)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT (4U)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK (0xF00U)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT (8U)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK (0xF000U)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT (12U)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK)
+#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK   (0x30000U)
+#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT  (16U)
+/*! OWNER_ID
+ *  0b00..domaino
+ *  0b01..domain1
+ *  0b10..domain2
+ *  0b11..domain3
+ */
+#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK)
+#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK      (0x100000U)
+#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT     (20U)
+/*! MUTEX
+ *  0b0..Semaphore is free to take
+ *  0b1..Semaphore is taken
+ */
+#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK (0x1000000U)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT (24U)
+/*! DOMAIN0_WHITELIST
+ *  0b0..Domain cannot change the setting
+ *  0b1..Domain can change the setting
+ */
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK (0x2000000U)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT (25U)
+/*! DOMAIN1_WHITELIST
+ *  0b0..Domain cannot change the setting
+ *  0b1..Domain can change the setting
+ */
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK (0x4000000U)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT (26U)
+/*! DOMAIN2_WHITELIST
+ *  0b0..Domain cannot change the setting
+ *  0b1..Domain can change the setting
+ */
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK (0x8000000U)
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT (27U)
+/*! DOMAIN3_WHITELIST
+ *  0b0..Domain cannot change the setting
+ *  0b1..Domain can change the setting
+ */
+#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK)
+#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK    (0x10000000U)
+#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT   (28U)
+/*! SEMA_EN
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK)
+#define CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK       (0x80000000U)
+#define CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT      (31U)
+/*! LOCK
+ *  0b0..Access control inactive
+ *  0b1..Access control active
+ */
+#define CCM_ACCESS_CTRL_ROOT_SET_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK)
+/*! @} */
+/* The count of CCM_ACCESS_CTRL_ROOT_SET */
+#define CCM_ACCESS_CTRL_ROOT_SET_COUNT           (142U)
+/*! @name ACCESS_CTRL_ROOT_CLR - Access Control Register */
+/*! @{ */
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK (0xFU)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT (0U)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK (0xF0U)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT (4U)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK (0xF00U)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT (8U)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK (0xF000U)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT (12U)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK)
+#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK   (0x30000U)
+#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT  (16U)
+/*! OWNER_ID
+ *  0b00..domaino
+ *  0b01..domain1
+ *  0b10..domain2
+ *  0b11..domain3
+ */
+#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK)
+#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK      (0x100000U)
+#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT     (20U)
+/*! MUTEX
+ *  0b0..Semaphore is free to take
+ *  0b1..Semaphore is taken
+ */
+#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK (0x1000000U)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT (24U)
+/*! DOMAIN0_WHITELIST
+ *  0b0..Domain cannot change the setting
+ *  0b1..Domain can change the setting
+ */
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK (0x2000000U)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT (25U)
+/*! DOMAIN1_WHITELIST
+ *  0b0..Domain cannot change the setting
+ *  0b1..Domain can change the setting
+ */
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK (0x4000000U)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT (26U)
+/*! DOMAIN2_WHITELIST
+ *  0b0..Domain cannot change the setting
+ *  0b1..Domain can change the setting
+ */
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK (0x8000000U)
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT (27U)
+/*! DOMAIN3_WHITELIST
+ *  0b0..Domain cannot change the setting
+ *  0b1..Domain can change the setting
+ */
+#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK)
+#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK    (0x10000000U)
+#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT   (28U)
+/*! SEMA_EN
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK)
+#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK       (0x80000000U)
+#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT      (31U)
+/*! LOCK
+ *  0b0..Access control inactive
+ *  0b1..Access control active
+ */
+#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK)
+/*! @} */
+/* The count of CCM_ACCESS_CTRL_ROOT_CLR */
+#define CCM_ACCESS_CTRL_ROOT_CLR_COUNT           (142U)
+/*! @name ACCESS_CTRL_ROOT_TOG - Access Control Register */
+/*! @{ */
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK (0xFU)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT (0U)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK (0xF0U)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT (4U)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK (0xF00U)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT (8U)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK (0xF000U)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT (12U)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK)
+#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK   (0x30000U)
+#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT  (16U)
+/*! OWNER_ID
+ *  0b00..domaino
+ *  0b01..domain1
+ *  0b10..domain2
+ *  0b11..domain3
+ */
+#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK)
+#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK      (0x100000U)
+#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT     (20U)
+/*! MUTEX
+ *  0b0..Semaphore is free to take
+ *  0b1..Semaphore is taken
+ */
+#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK (0x1000000U)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT (24U)
+/*! DOMAIN0_WHITELIST
+ *  0b0..Domain cannot change the setting
+ *  0b1..Domain can change the setting
+ */
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK (0x2000000U)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT (25U)
+/*! DOMAIN1_WHITELIST
+ *  0b0..Domain cannot change the setting
+ *  0b1..Domain can change the setting
+ */
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK (0x4000000U)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT (26U)
+/*! DOMAIN2_WHITELIST
+ *  0b0..Domain cannot change the setting
+ *  0b1..Domain can change the setting
+ */
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK (0x8000000U)
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT (27U)
+/*! DOMAIN3_WHITELIST
+ *  0b0..Domain cannot change the setting
+ *  0b1..Domain can change the setting
+ */
+#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK)
+#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK    (0x10000000U)
+#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT   (28U)
+/*! SEMA_EN
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK)
+#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK       (0x80000000U)
+#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT      (31U)
+/*! LOCK
+ *  0b0..Access control inactive
+ *  0b1..Access control active
+ */
+#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK)
+/*! @} */
+/* The count of CCM_ACCESS_CTRL_ROOT_TOG */
+#define CCM_ACCESS_CTRL_ROOT_TOG_COUNT           (142U)
+/*!
+ * @}
+ */ /* end of group CCM_Register_Masks */
+/* CCM - Peripheral instance base addresses */
+/** Peripheral CCM base address */
+#define CCM_BASE                                 (0x30380000u)
+/** Peripheral CCM base pointer */
+#define CCM                                      ((CCM_Type *)CCM_BASE)
+/** Array initializer of CCM peripheral base addresses */
+#define CCM_BASE_ADDRS                           { CCM_BASE }
+/** Array initializer of CCM peripheral base pointers */
+#define CCM_BASE_PTRS                            { CCM }
+/** Interrupt vectors for the CCM peripheral type */
+#define CCM_IRQS                                 { CCM_IRQ1_IRQn, CCM_IRQ2_IRQn }
+/*!
+ * @}
+ */ /* end of group CCM_Peripheral_Access_Layer */
+/* ----------------------------------------------------------------------------
+   -- CCM_ANALOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer
+ * @{
+ */
+/** CCM_ANALOG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t AUDIO_PLL1_GEN_CTRL;               /**< AUDIO PLL1 General Function Control Register, offset: 0x0 */
+  __IO uint32_t AUDIO_PLL1_FDIV_CTL0;              /**< AUDIO PLL1 Divide and Fraction Data Control 0 Register, offset: 0x4 */
+  __IO uint32_t AUDIO_PLL1_FDIV_CTL1;              /**< AUDIO PLL1 Divide and Fraction Data Control 1 Register, offset: 0x8 */
+  __IO uint32_t AUDIO_PLL1_SSCG_CTRL;              /**< AUDIO PLL1 PLL SSCG Control Register, offset: 0xC */
+  __IO uint32_t AUDIO_PLL1_MNIT_CTRL;              /**< AUDIO PLL1 PLL Monitoring Control Register, offset: 0x10 */
+  __IO uint32_t AUDIO_PLL2_GEN_CTRL;               /**< AUDIO PLL2 General Function Control Register, offset: 0x14 */
+  __IO uint32_t AUDIO_PLL2_FDIV_CTL0;              /**< AUDIO PLL2 Divide and Fraction Data Control 0 Register, offset: 0x18 */
+  __IO uint32_t AUDIO_PLL2_FDIV_CTL1;              /**< AUDIO PLL2 Divide and Fraction Data Control 1 Register, offset: 0x1C */
+  __IO uint32_t AUDIO_PLL2_SSCG_CTRL;              /**< AUDIO PLL2 PLL SSCG Control Register, offset: 0x20 */
+  __IO uint32_t AUDIO_PLL2_MNIT_CTRL;              /**< AUDIO PLL2 PLL Monitoring Control Register, offset: 0x24 */
+  __IO uint32_t VIDEO_PLL1_GEN_CTRL;               /**< VIDEO PLL1 General Function Control Register, offset: 0x28 */
+  __IO uint32_t VIDEO_PLL1_FDIV_CTL0;              /**< VIDEO PLL1 Divide and Fraction Data Control 0 Register, offset: 0x2C */
+  __IO uint32_t VIDEO_PLL1_FDIV_CTL1;              /**< VIDEO PLL1 Divide and Fraction Data Control 1 Register, offset: 0x30 */
+  __IO uint32_t VIDEO_PLL1_SSCG_CTRL;              /**< VIDEO PLL1 PLL SSCG Control Register, offset: 0x34 */
+  __IO uint32_t VIDEO_PLL1_MNIT_CTRL;              /**< VIDEO PLL1 PLL Monitoring Control Register, offset: 0x38 */
+       uint8_t RESERVED_0[20];
+  __IO uint32_t DRAM_PLL_GEN_CTRL;                 /**< DRAM PLL General Function Control Register, offset: 0x50 */
+  __IO uint32_t DRAM_PLL_FDIV_CTL0;                /**< DRAM PLL Divide and Fraction Data Control 0 Register, offset: 0x54 */
+  __IO uint32_t DRAM_PLL_FDIV_CTL1;                /**< DRAM PLL Divide and Fraction Data Control 1 Register, offset: 0x58 */
+  __IO uint32_t DRAM_PLL_SSCG_CTRL;                /**< DRAM PLL PLL SSCG Control Register, offset: 0x5C */
+  __IO uint32_t DRAM_PLL_MNIT_CTRL;                /**< DRAM PLL PLL Monitoring Control Register, offset: 0x60 */
+  __IO uint32_t GPU_PLL_GEN_CTRL;                  /**< GPU PLL General Function Control Register, offset: 0x64 */
+  __IO uint32_t GPU_PLL_FDIV_CTL0;                 /**< GPU PLL Divide and Fraction Data Control 0 Register, offset: 0x68 */
+  __IO uint32_t GPU_PLL_LOCKD_CTRL;                /**< PLL Lock Detector Control Register, offset: 0x6C */
+  __IO uint32_t GPU_PLL_MNIT_CTRL;                 /**< PLL Monitoring Control Register, offset: 0x70 */
+  __IO uint32_t VPU_PLL_GEN_CTRL;                  /**< VPU PLL General Function Control Register, offset: 0x74 */
+  __IO uint32_t VPU_PLL_FDIV_CTL0;                 /**< VPU PLL Divide and Fraction Data Control 0 Register, offset: 0x78 */
+  __IO uint32_t VPU_PLL_LOCKD_CTRL;                /**< PLL Lock Detector Control Register, offset: 0x7C */
+  __IO uint32_t VPU_PLL_MNIT_CTRL;                 /**< PLL Monitoring Control Register, offset: 0x80 */
+  __IO uint32_t ARM_PLL_GEN_CTRL;                  /**< ARM PLL General Function Control Register, offset: 0x84 */
+  __IO uint32_t ARM_PLL_FDIV_CTL0;                 /**< ARM PLL Divide and Fraction Data Control 0 Register, offset: 0x88 */
+  __IO uint32_t ARM_PLL_LOCKD_CTRL;                /**< PLL Lock Detector Control Register, offset: 0x8C */
+  __IO uint32_t ARM_PLL_MNIT_CTRL;                 /**< PLL Monitoring Control Register, offset: 0x90 */
+  __IO uint32_t SYS_PLL1_GEN_CTRL;                 /**< SYS PLL1 General Function Control Register, offset: 0x94 */
+  __IO uint32_t SYS_PLL1_FDIV_CTL0;                /**< SYS PLL1 Divide and Fraction Data Control 0 Register, offset: 0x98 */
+  __IO uint32_t SYS_PLL1_LOCKD_CTRL;               /**< PLL Lock Detector Control Register, offset: 0x9C */
+       uint8_t RESERVED_1[96];
+  __IO uint32_t SYS_PLL1_MNIT_CTRL;                /**< PLL Monitoring Control Register, offset: 0x100 */
+  __IO uint32_t SYS_PLL2_GEN_CTRL;                 /**< SYS PLL2 General Function Control Register, offset: 0x104 */
+  __IO uint32_t SYS_PLL2_FDIV_CTL0;                /**< SYS PLL2 Divide and Fraction Data Control 0 Register, offset: 0x108 */
+  __IO uint32_t SYS_PLL2_LOCKD_CTRL;               /**< PLL Lock Detector Control Register, offset: 0x10C */
+  __IO uint32_t SYS_PLL2_MNIT_CTRL;                /**< PLL Monitoring Control Register, offset: 0x110 */
+  __IO uint32_t SYS_PLL3_GEN_CTRL;                 /**< SYS PLL3 General Function Control Register, offset: 0x114 */
+  __IO uint32_t SYS_PLL3_FDIV_CTL0;                /**< SYS PLL3 Divide and Fraction Data Control 0 Register, offset: 0x118 */
+  __IO uint32_t SYS_PLL3_LOCKD_CTRL;               /**< PLL Lock Detector Control Register, offset: 0x11C */
+  __IO uint32_t SYS_PLL3_MNIT_CTRL;                /**< PLL Monitoring Control Register, offset: 0x120 */
+  __IO uint32_t OSC_MISC_CFG;                      /**< Osc Misc Configuration Register, offset: 0x124 */
+  __IO uint32_t ANAMIX_PLL_MNIT_CTL;               /**< PLL Clock Output for Test Enable and Select Register, offset: 0x128 */
+       uint8_t RESERVED_2[1748];
+  __I  uint32_t DIGPROG;                           /**< DIGPROG Register, offset: 0x800 */
+} CCM_ANALOG_Type;
+/* ----------------------------------------------------------------------------
+   -- CCM_ANALOG Register Masks
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks
+ * @{
+ */
+/*! @name AUDIO_PLL1_GEN_CTRL - AUDIO PLL1 General Function Control Register */
+/*! @{ */
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
+/*! PLL_REF_CLK_SEL
+ *  0b00..SYS_XTAL
+ *  0b01..PAD_CLK
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
+/*! PAD_CLK_SEL
+ *  0b00..CLKIN1 XOR CLKIN2
+ *  0b01..CLKIN2
+ *  0b10..CLKIN1
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (13U)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U)
+#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_MASK)
+/*! @} */
+/*! @name AUDIO_PLL1_FDIV_CTL0 - AUDIO PLL1 Divide and Fraction Data Control 0 Register */
+/*! @{ */
+#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
+#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
+#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
+#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
+#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
+#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
+#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK)
+/*! @} */
+/*! @name AUDIO_PLL1_FDIV_CTL1 - AUDIO PLL1 Divide and Fraction Data Control 1 Register */
+/*! @{ */
+#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
+#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT (0U)
+#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_MASK)
+/*! @} */
+/*! @name AUDIO_PLL1_SSCG_CTRL - AUDIO PLL1 PLL SSCG Control Register */
+/*! @{ */
+#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_MASK (0x3U)
+#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_SHIFT (0U)
+/*! SEL_PF
+ *  0b00..Down spread
+ *  0b01..Up spread
+ *  0b1x..Center spread
+ */
+#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
+#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
+#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
+#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
+#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
+#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT (31U)
+#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_MASK)
+/*! @} */
+/*! @name AUDIO_PLL1_MNIT_CTRL - AUDIO PLL1 PLL Monitoring Control Register */
+/*! @{ */
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_MASK (0x7U)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_SHIFT (0U)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_MASK (0x8U)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_SHIFT (3U)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_SHIFT (4U)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_MASK (0x4000U)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_SHIFT (14U)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_MASK (0x8000U)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_SHIFT (15U)
+/*! FSEL
+ *  0b0..FEED_OUT = FREF
+ *  0b1..FEED_OUT = FEED
+ */
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
+/*! AFCINIT_SEL
+ *  0b0..nominal delay
+ *  0b1..nominal delay * 2
+ */
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
+/*! PBIAS_CTRL
+ *  0b0..0.50*VDD
+ *  0b1..0.67*VDD
+ */
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (20U)
+#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_MASK)
+/*! @} */
+/*! @name AUDIO_PLL2_GEN_CTRL - AUDIO PLL2 General Function Control Register */
+/*! @{ */
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
+/*! PLL_REF_CLK_SEL
+ *  0b00..SYS_XTAL
+ *  0b01..PAD_CLK
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
+/*! PAD_CLK_SEL
+ *  0b00..CLKIN1 XOR CLKIN2
+ *  0b01..CLKIN2
+ *  0b10..CLKIN1
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_MASK (0x200U)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT (9U)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT (13U)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_SHIFT (31U)
+#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_MASK)
+/*! @} */
+/*! @name AUDIO_PLL2_FDIV_CTL0 - AUDIO PLL2 Divide and Fraction Data Control 0 Register */
+/*! @{ */
+#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
+#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
+#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
+#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
+#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
+#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
+#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK)
+/*! @} */
+/*! @name AUDIO_PLL2_FDIV_CTL1 - AUDIO PLL2 Divide and Fraction Data Control 1 Register */
+/*! @{ */
+#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
+#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_SHIFT (0U)
+#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_MASK)
+/*! @} */
+/*! @name AUDIO_PLL2_SSCG_CTRL - AUDIO PLL2 PLL SSCG Control Register */
+/*! @{ */
+#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_MASK (0x3U)
+#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_SHIFT (0U)
+/*! SEL_PF
+ *  0b00..Down spread
+ *  0b01..Up spread
+ *  0b1x..Center spread
+ */
+#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
+#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
+#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
+#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
+#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
+#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_SHIFT (31U)
+#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_MASK)
+/*! @} */
+/*! @name AUDIO_PLL2_MNIT_CTRL - AUDIO PLL2 PLL Monitoring Control Register */
+/*! @{ */
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_MASK (0x7U)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_SHIFT (0U)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_MASK (0x8U)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_SHIFT (3U)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_SHIFT (4U)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_MASK (0x4000U)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_SHIFT (14U)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_MASK (0x8000U)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_SHIFT (15U)
+/*! FSEL
+ *  0b0..FEED_OUT = FREF
+ *  0b1..FEED_OUT = FEED
+ */
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
+/*! AFCINIT_SEL
+ *  0b0..nominal delay
+ *  0b1..nominal delay * 2
+ */
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
+/*! PBIAS_CTRL
+ *  0b0..0.50*VDD
+ *  0b1..0.67*VDD
+ */
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_SHIFT (20U)
+#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_MASK)
+/*! @} */
+/*! @name VIDEO_PLL1_GEN_CTRL - VIDEO PLL1 General Function Control Register */
+/*! @{ */
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
+/*! PLL_REF_CLK_SEL
+ *  0b00..SYS_XTAL
+ *  0b01..PAD_CLK
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
+/*! PAD_CLK_SEL
+ *  0b00..CLKIN1 XOR CLKIN2
+ *  0b01..CLKIN2
+ *  0b10..CLKIN1
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (13U)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U)
+#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_MASK)
+/*! @} */
+/*! @name VIDEO_PLL1_FDIV_CTL0 - VIDEO PLL1 Divide and Fraction Data Control 0 Register */
+/*! @{ */
+#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
+#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
+#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
+#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
+#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
+#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
+#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK)
+/*! @} */
+/*! @name VIDEO_PLL1_FDIV_CTL1 - VIDEO PLL1 Divide and Fraction Data Control 1 Register */
+/*! @{ */
+#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
+#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT (0U)
+#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_MASK)
+/*! @} */
+/*! @name VIDEO_PLL1_SSCG_CTRL - VIDEO PLL1 PLL SSCG Control Register */
+/*! @{ */
+#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_MASK (0x3U)
+#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_SHIFT (0U)
+/*! SEL_PF
+ *  0b00..Down spread
+ *  0b01..Up spread
+ *  0b1x..Center spread
+ */
+#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
+#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
+#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
+#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
+#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
+#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT (31U)
+#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_MASK)
+/*! @} */
+/*! @name VIDEO_PLL1_MNIT_CTRL - VIDEO PLL1 PLL Monitoring Control Register */
+/*! @{ */
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_MASK (0x7U)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_SHIFT (0U)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_MASK (0x8U)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_SHIFT (3U)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_SHIFT (4U)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_MASK (0x4000U)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_SHIFT (14U)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_MASK (0x8000U)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_SHIFT (15U)
+/*! FSEL
+ *  0b0..FEED_OUT = FREF
+ *  0b1..FEED_OUT = FEED
+ */
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
+/*! AFCINIT_SEL
+ *  0b0..nominal delay
+ *  0b1..nominal delay * 2
+ */
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
+/*! PBIAS_CTRL
+ *  0b0..0.50*VDD
+ *  0b1..0.67*VDD
+ */
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (20U)
+#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_MASK)
+/*! @} */
+/*! @name DRAM_PLL_GEN_CTRL - DRAM PLL General Function Control Register */
+/*! @{ */
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
+/*! PLL_REF_CLK_SEL
+ *  0b00..SYS_XTAL
+ *  0b01..PAD_CLK
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
+/*! PAD_CLK_SEL
+ *  0b00..CLKIN1 XOR CLKIN2
+ *  0b01..CLKIN2
+ *  0b10..CLKIN1
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_MASK)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_MASK)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT (13U)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_MASK)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
+#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_MASK)
+/*! @} */
+/*! @name DRAM_PLL_FDIV_CTL0 - DRAM PLL Divide and Fraction Data Control 0 Register */
+/*! @{ */
+#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
+#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
+#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
+#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
+#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
+#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
+#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
+#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
+#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
+/*! @} */
+/*! @name DRAM_PLL_FDIV_CTL1 - DRAM PLL Divide and Fraction Data Control 1 Register */
+/*! @{ */
+#define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
+#define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_SHIFT (0U)
+#define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_SHIFT)) & CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_MASK)
+/*! @} */
+/*! @name DRAM_PLL_SSCG_CTRL - DRAM PLL PLL SSCG Control Register */
+/*! @{ */
+#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_MASK (0x3U)
+#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_SHIFT (0U)
+/*! SEL_PF
+ *  0b00..Down spread
+ *  0b01..Up spread
+ *  0b1x..Center spread
+ */
+#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_SHIFT)) & CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_MASK)
+#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
+#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
+#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_MASK)
+#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
+#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
+#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
+#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
+#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_SHIFT (31U)
+#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_SHIFT)) & CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_MASK)
+/*! @} */
+/*! @name DRAM_PLL_MNIT_CTRL - DRAM PLL PLL Monitoring Control Register */
+/*! @{ */
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_MASK   (0x7U)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_SHIFT  (0U)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_MASK)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_MASK (0x8U)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_SHIFT (3U)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_MASK)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_SHIFT (4U)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_MASK)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_MASK (0x4000U)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_SHIFT (14U)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_MASK)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_MASK  (0x8000U)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_SHIFT (15U)
+/*! FSEL
+ *  0b0..FEED_OUT = FREF
+ *  0b1..FEED_OUT = FEED
+ */
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_MASK)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
+/*! AFCINIT_SEL
+ *  0b0..nominal delay
+ *  0b1..nominal delay * 2
+ */
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
+/*! PBIAS_CTRL
+ *  0b0..0.50*VDD
+ *  0b1..0.67*VDD
+ */
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_SHIFT (20U)
+#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_MASK)
+/*! @} */
+/*! @name GPU_PLL_GEN_CTRL - GPU PLL General Function Control Register */
+/*! @{ */
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
+/*! PLL_REF_CLK_SEL
+ *  0b00..SYS_XTAL
+ *  0b01..PAD_CLK
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
+/*! PAD_CLK_SEL
+ *  0b00..CLKIN1 XOR CLKIN2
+ *  0b01..CLKIN2
+ *  0b10..CLKIN1
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_MASK)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_MASK)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_MASK)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
+/*! PLL_LOCK_SEL
+ *  0b0..Using PLL maximum lock time
+ *  0b1..Using PLL output lock
+ */
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
+#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_MASK)
+/*! @} */
+/*! @name GPU_PLL_FDIV_CTL0 - GPU PLL Divide and Fraction Data Control 0 Register */
+/*! @{ */
+#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
+#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
+#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
+#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
+#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
+#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
+#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
+#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
+#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
+/*! @} */
+/*! @name GPU_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
+/*! @{ */
+#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
+#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
+#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK)
+#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
+#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
+#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK)
+#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
+#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
+#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK)
+/*! @} */
+/*! @name GPU_PLL_MNIT_CTRL - PLL Monitoring Control Register */
+/*! @{ */
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_MASK    (0x3U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_SHIFT   (0U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_MASK)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_MASK)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_MASK)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_MASK)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_MASK   (0x4000U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_SHIFT  (14U)
+/*! FSEL
+ *  0b0..FEED_OUT = FREF
+ *  0b1..FEED_OUT = FEED
+ */
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_MASK)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
+/*! AFCINIT_SEL
+ *  0b0..nominal delay
+ *  0b1..nominal delay * 2
+ */
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
+/*! PBIAS_CTRL
+ *  0b0..0.50*VDD
+ *  0b1..0.67*VDD
+ */
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_MASK)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_MASK)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U)
+#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_MASK)
+/*! @} */
+/*! @name VPU_PLL_GEN_CTRL - VPU PLL General Function Control Register */
+/*! @{ */
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
+/*! PLL_REF_CLK_SEL
+ *  0b00..SYS_XTAL
+ *  0b01..PAD_CLK
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
+/*! PAD_CLK_SEL
+ *  0b00..CLKIN1 XOR CLKIN2
+ *  0b01..CLKIN2
+ *  0b10..CLKIN1
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_MASK)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_MASK)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_MASK)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
+/*! PLL_LOCK_SEL
+ *  0b0..Using PLL maximum lock time
+ *  0b1..Using PLL output lock
+ */
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
+#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_MASK)
+/*! @} */
+/*! @name VPU_PLL_FDIV_CTL0 - VPU PLL Divide and Fraction Data Control 0 Register */
+/*! @{ */
+#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
+#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
+#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
+#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
+#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
+#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
+#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
+#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
+#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
+/*! @} */
+/*! @name VPU_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
+/*! @{ */
+#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
+#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
+#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK)
+#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
+#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
+#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK)
+#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
+#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
+#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK)
+/*! @} */
+/*! @name VPU_PLL_MNIT_CTRL - PLL Monitoring Control Register */
+/*! @{ */
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP_MASK    (0x3U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP_SHIFT   (0U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP_MASK)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN_MASK)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC_MASK)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN_MASK)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL_MASK   (0x4000U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL_SHIFT  (14U)
+/*! FSEL
+ *  0b0..FEED_OUT = FREF
+ *  0b1..FEED_OUT = FEED
+ */
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL_MASK)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
+/*! AFCINIT_SEL
+ *  0b0..nominal delay
+ *  0b1..nominal delay * 2
+ */
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
+/*! PBIAS_CTRL
+ *  0b0..0.50*VDD
+ *  0b1..0.67*VDD
+ */
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL_MASK)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK_MASK)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U)
+#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN_MASK)
+/*! @} */
+/*! @name ARM_PLL_GEN_CTRL - ARM PLL General Function Control Register */
+/*! @{ */
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
+/*! PLL_REF_CLK_SEL
+ *  0b00..SYS_XTAL
+ *  0b01..PAD_CLK
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
+/*! PAD_CLK_SEL
+ *  0b00..CLKIN1 XOR CLKIN2
+ *  0b01..CLKIN2
+ *  0b10..CLKIN1
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_MASK)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_MASK)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_MASK)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
+/*! PLL_LOCK_SEL
+ *  0b0..Using PLL maximum lock time
+ *  0b1..Using PLL output lock
+ */
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
+#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_MASK)
+/*! @} */
+/*! @name ARM_PLL_FDIV_CTL0 - ARM PLL Divide and Fraction Data Control 0 Register */
+/*! @{ */
+#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
+#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
+#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
+#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
+#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
+#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
+#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
+#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
+#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
+/*! @} */
+/*! @name ARM_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
+/*! @{ */
+#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
+#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
+#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK)
+#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
+#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
+#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK)
+#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
+#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
+#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK)
+/*! @} */
+/*! @name ARM_PLL_MNIT_CTRL - PLL Monitoring Control Register */
+/*! @{ */
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_MASK    (0x3U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_SHIFT   (0U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_MASK)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_MASK)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_MASK)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_MASK)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_MASK   (0x4000U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_SHIFT  (14U)
+/*! FSEL
+ *  0b0..FEED_OUT = FREF
+ *  0b1..FEED_OUT = FEED
+ */
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_MASK)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
+/*! AFCINIT_SEL
+ *  0b0..nominal delay
+ *  0b1..nominal delay * 2
+ */
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
+/*! PBIAS_CTRL
+ *  0b0..0.50*VDD
+ *  0b1..0.67*VDD
+ */
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_MASK)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_MASK)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U)
+#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_MASK)
+/*! @} */
+/*! @name SYS_PLL1_GEN_CTRL - SYS PLL1 General Function Control Register */
+/*! @{ */
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
+/*! PLL_REF_CLK_SEL
+ *  0b00..SYS_XTAL
+ *  0b01..PAD_CLK
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
+/*! PAD_CLK_SEL
+ *  0b00..CLKIN1 XOR CLKIN2
+ *  0b01..CLKIN2
+ *  0b10..CLKIN1
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x800U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (11U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK (0x1000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT (12U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_MASK (0x2000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT (13U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK (0x4000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT (14U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_MASK (0x8000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT (15U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK (0x10000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT (16U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_MASK (0x20000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT (17U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK (0x40000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT (18U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_MASK (0x80000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT (19U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK (0x100000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT (20U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_MASK (0x200000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT (21U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK (0x400000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT (22U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_MASK (0x800000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT (23U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK (0x1000000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT (24U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_MASK (0x2000000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT (25U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK (0x4000000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT (26U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_MASK (0x8000000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT (27U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
+/*! PLL_LOCK_SEL
+ *  0b0..Using PLL maximum lock time
+ *  0b1..Using PLL output lock
+ */
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_MASK)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U)
+#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK)
+/*! @} */
+/*! @name SYS_PLL1_FDIV_CTL0 - SYS PLL1 Divide and Fraction Data Control 0 Register */
+/*! @{ */
+#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
+#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
+#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK)
+#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
+#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
+#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK)
+#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
+#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
+#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK)
+/*! @} */
+/*! @name SYS_PLL1_LOCKD_CTRL - PLL Lock Detector Control Register */
+/*! @{ */
+#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
+#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
+#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_MASK)
+#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
+#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
+#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_MASK)
+#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
+#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
+#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_MASK)
+/*! @} */
+/*! @name SYS_PLL1_MNIT_CTRL - PLL Monitoring Control Register */
+/*! @{ */
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_MASK   (0x3U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_SHIFT  (0U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_MASK)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_MASK (0x4U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_SHIFT (2U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_MASK)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_MASK (0xF8U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_SHIFT (3U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_MASK)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_MASK (0x2000U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_SHIFT (13U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_MASK)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_MASK  (0x4000U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_SHIFT (14U)
+/*! FSEL
+ *  0b0..FEED_OUT = FREF
+ *  0b1..FEED_OUT = FEED
+ */
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_MASK)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
+/*! AFCINIT_SEL
+ *  0b0..nominal delay
+ *  0b1..nominal delay * 2
+ */
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
+/*! PBIAS_CTRL
+ *  0b0..0.50*VDD
+ *  0b1..0.67*VDD
+ */
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (19U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_MASK)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_MASK)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_MASK (0x200000U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_SHIFT (21U)
+#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_MASK)
+/*! @} */
+/*! @name SYS_PLL2_GEN_CTRL - SYS PLL2 General Function Control Register */
+/*! @{ */
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
+/*! PLL_REF_CLK_SEL
+ *  0b00..SYS_XTAL
+ *  0b01..PAD_CLK
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
+/*! PAD_CLK_SEL
+ *  0b00..CLKIN1 XOR CLKIN2
+ *  0b01..CLKIN2
+ *  0b10..CLKIN1
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_MASK (0x200U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT (9U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_MASK (0x800U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT (11U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK (0x1000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT (12U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_MASK (0x2000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT (13U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK (0x4000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT (14U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_MASK (0x8000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT (15U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK (0x10000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT (16U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_MASK (0x20000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT (17U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK (0x40000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT (18U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_MASK (0x80000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT (19U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK (0x100000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT (20U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_MASK (0x200000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT (21U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK (0x400000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT (22U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_MASK (0x800000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT (23U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK (0x1000000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT (24U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_MASK (0x2000000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT (25U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK (0x4000000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT (26U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_MASK (0x8000000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT (27U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
+/*! PLL_LOCK_SEL
+ *  0b0..Using PLL maximum lock time
+ *  0b1..Using PLL output lock
+ */
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_MASK)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SHIFT (31U)
+#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_MASK)
+/*! @} */
+/*! @name SYS_PLL2_FDIV_CTL0 - SYS PLL2 Divide and Fraction Data Control 0 Register */
+/*! @{ */
+#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
+#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
+#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK)
+#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
+#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
+#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK)
+#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
+#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
+#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK)
+/*! @} */
+/*! @name SYS_PLL2_LOCKD_CTRL - PLL Lock Detector Control Register */
+/*! @{ */
+#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
+#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
+#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_MASK)
+#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
+#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
+#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_MASK)
+#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
+#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
+#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_MASK)
+/*! @} */
+/*! @name SYS_PLL2_MNIT_CTRL - PLL Monitoring Control Register */
+/*! @{ */
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_MASK   (0x3U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_SHIFT  (0U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_MASK)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_MASK (0x4U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_SHIFT (2U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_MASK)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_MASK (0xF8U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_SHIFT (3U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_MASK)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_MASK (0x2000U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_SHIFT (13U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_MASK)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_MASK  (0x4000U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_SHIFT (14U)
+/*! FSEL
+ *  0b0..FEED_OUT = FREF
+ *  0b1..FEED_OUT = FEED
+ */
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_MASK)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
+/*! AFCINIT_SEL
+ *  0b0..nominal delay
+ *  0b1..nominal delay * 2
+ */
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
+/*! PBIAS_CTRL
+ *  0b0..0.50*VDD
+ *  0b1..0.67*VDD
+ */
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_SHIFT (19U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_MASK)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_MASK)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_MASK (0x200000U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_SHIFT (21U)
+#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_MASK)
+/*! @} */
+/*! @name SYS_PLL3_GEN_CTRL - SYS PLL3 General Function Control Register */
+/*! @{ */
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
+/*! PLL_REF_CLK_SEL
+ *  0b00..SYS_XTAL
+ *  0b01..PAD_CLK
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
+/*! PAD_CLK_SEL
+ *  0b00..CLKIN1 XOR CLKIN2
+ *  0b01..CLKIN2
+ *  0b10..CLKIN1
+ *  0b11..Reserved
+ */
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_MASK)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_MASK)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_MASK (0x200U)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT (9U)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_MASK)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_MASK (0x800U)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT (11U)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_MASK)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_MASK)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
+/*! PLL_LOCK_SEL
+ *  0b0..Using PLL maximum lock time
+ *  0b1..Using PLL output lock
+ */
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_MASK)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SHIFT (31U)
+#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_MASK)
+/*! @} */
+/*! @name SYS_PLL3_FDIV_CTL0 - SYS PLL3 Divide and Fraction Data Control 0 Register */
+/*! @{ */
+#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
+#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
+#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_MASK)
+#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
+#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
+#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_MASK)
+#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
+#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
+#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_MASK)
+/*! @} */
+/*! @name SYS_PLL3_LOCKD_CTRL - PLL Lock Detector Control Register */
+/*! @{ */
+#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
+#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
+#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_MASK)
+#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
+#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
+#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_MASK)
+#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
+#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
+#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_MASK)
+/*! @} */
+/*! @name SYS_PLL3_MNIT_CTRL - PLL Monitoring Control Register */
+/*! @{ */
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_MASK   (0x3U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_SHIFT  (0U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_MASK)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_MASK (0x4U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_SHIFT (2U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_MASK)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_MASK (0xF8U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_SHIFT (3U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_MASK)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_MASK (0x2000U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_SHIFT (13U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_MASK)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_MASK  (0x4000U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_SHIFT (14U)
+/*! FSEL
+ *  0b0..FEED_OUT = FREF
+ *  0b1..FEED_OUT = FEED
+ */
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_MASK)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
+/*! AFCINIT_SEL
+ *  0b0..nominal delay
+ *  0b1..nominal delay * 2
+ */
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_MASK)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
+/*! PBIAS_CTRL
+ *  0b0..0.50*VDD
+ *  0b1..0.67*VDD
+ */
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_MASK)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_SHIFT (19U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_MASK)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_MASK)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_MASK (0x200000U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_SHIFT (21U)
+#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_MASK)
+/*! @} */
+/*! @name OSC_MISC_CFG - Osc Misc Configuration Register */
+/*! @{ */
+#define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK (0x1U)
+#define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT (0U)
+/*! OSC_32K_SEL
+ *  0b0..Divided by 24M clock
+ *  0b1..32K Oscillator
+ */
+#define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK)
+/*! @} */
+/*! @name ANAMIX_PLL_MNIT_CTL - PLL Clock Output for Test Enable and Select Register */
+/*! @{ */
+#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_MASK (0xFU)
+#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_SHIFT (0U)
+#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_MASK)
+#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_MASK (0xF0U)
+#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_SHIFT (4U)
+#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_MASK)
+#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_MASK (0x100U)
+#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_SHIFT (8U)
+#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_MASK)
+#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_MASK (0xF0000U)
+#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_SHIFT (16U)
+#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_MASK)
+#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_MASK (0xF00000U)
+#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_SHIFT (20U)
+#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_MASK)
+#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_MASK (0x1000000U)
+#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_SHIFT (24U)
+#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_MASK)
+/*! @} */
+/*! @name DIGPROG - DIGPROG Register */
+/*! @{ */
+#define CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK    (0xFFU)
+#define CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT   (0U)
+#define CCM_ANALOG_DIGPROG_DIGPROG_MINOR(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK)
+#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK (0xFF00U)
+#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT (8U)
+#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK)
+#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U)
+#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT (16U)
+#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK)
+/*! @} */
+/*!
+ * @}
+ */ /* end of group CCM_ANALOG_Register_Masks */
+/* CCM_ANALOG - Peripheral instance base addresses */
+/** Peripheral CCM_ANALOG base address */
+#define CCM_ANALOG_BASE                          (0x30360000u)
+/** Peripheral CCM_ANALOG base pointer */
+#define CCM_ANALOG                               ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
+/** Array initializer of CCM_ANALOG peripheral base addresses */
+#define CCM_ANALOG_BASE_ADDRS                    { CCM_ANALOG_BASE }
+/** Array initializer of CCM_ANALOG peripheral base pointers */
+#define CCM_ANALOG_BASE_PTRS                     { CCM_ANALOG }
+/*!
+ * @}
+ */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */
+/* ----------------------------------------------------------------------------
+   -- CSI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer
+ * @{
+ */
+/** CSI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSICR1;                            /**< CSI Control Register 1, offset: 0x0 */
+  __IO uint32_t CSICR2;                            /**< CSI Control Register 2, offset: 0x4 */
+  __IO uint32_t CSICR3;                            /**< CSI Control Register 3, offset: 0x8 */
+  __I  uint32_t CSISTATFIFO;                       /**< CSI Statistic FIFO Register, offset: 0xC */
+  __I  uint32_t CSIRFIFO;                          /**< CSI RX FIFO Register, offset: 0x10 */
+  __IO uint32_t CSIRXCNT;                          /**< CSI RX Count Register, offset: 0x14 */
+  __IO uint32_t CSISR;                             /**< CSI Status Register, offset: 0x18 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CSIDMASA_STATFIFO;                 /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */
+  __IO uint32_t CSIDMATS_STATFIFO;                 /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */
+  __IO uint32_t CSIDMASA_FB1;                      /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */
+  __IO uint32_t CSIDMASA_FB2;                      /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */
+  __IO uint32_t CSIFBUF_PARA;                      /**< CSI Frame Buffer Parameter Register, offset: 0x30 */
+  __IO uint32_t CSIIMAG_PARA;                      /**< CSI Image Parameter Register, offset: 0x34 */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t CSICR18;                           /**< CSI Control Register 18, offset: 0x48 */
+} CSI_Type;
+/* ----------------------------------------------------------------------------
+   -- CSI Register Masks
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup CSI_Register_Masks CSI Register Masks
+ * @{
+ */
+/*! @name CSICR1 - CSI Control Register 1 */
+/*! @{ */
+#define CSI_CSICR1_PIXEL_BIT_MASK                (0x1U)
+#define CSI_CSICR1_PIXEL_BIT_SHIFT               (0U)
+/*! PIXEL_BIT
+ *  0b0..8-bit data for each pixel
+ *  0b1..10-bit data for each pixel
+ */
+#define CSI_CSICR1_PIXEL_BIT(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK)
+#define CSI_CSICR1_REDGE_MASK                    (0x2U)
+#define CSI_CSICR1_REDGE_SHIFT                   (1U)
+/*! REDGE
+ *  0b0..Pixel data is latched at the falling edge of CSI_PIXCLK
+ *  0b1..Pixel data is latched at the rising edge of CSI_PIXCLK
+ */
+#define CSI_CSICR1_REDGE(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK)
+#define CSI_CSICR1_INV_PCLK_MASK                 (0x4U)
+#define CSI_CSICR1_INV_PCLK_SHIFT                (2U)
+/*! INV_PCLK
+ *  0b0..CSI_PIXCLK is directly applied to internal circuitry
+ *  0b1..CSI_PIXCLK is inverted before applied to internal circuitry
+ */
+#define CSI_CSICR1_INV_PCLK(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK)
+#define CSI_CSICR1_INV_DATA_MASK                 (0x8U)
+#define CSI_CSICR1_INV_DATA_SHIFT                (3U)
+/*! INV_DATA
+ *  0b0..CSI_D[7:0] data lines are directly applied to internal circuitry
+ *  0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry
+ */
+#define CSI_CSICR1_INV_DATA(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK)
+#define CSI_CSICR1_GCLK_MODE_MASK                (0x10U)
+#define CSI_CSICR1_GCLK_MODE_SHIFT               (4U)
+/*! GCLK_MODE
+ *  0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored.
+ *  0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active.
+ */
+#define CSI_CSICR1_GCLK_MODE(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK)
+#define CSI_CSICR1_CLR_RXFIFO_MASK               (0x20U)
+#define CSI_CSICR1_CLR_RXFIFO_SHIFT              (5U)
+#define CSI_CSICR1_CLR_RXFIFO(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK)
+#define CSI_CSICR1_CLR_STATFIFO_MASK             (0x40U)
+#define CSI_CSICR1_CLR_STATFIFO_SHIFT            (6U)
+#define CSI_CSICR1_CLR_STATFIFO(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK)
+#define CSI_CSICR1_PACK_DIR_MASK                 (0x80U)
+#define CSI_CSICR1_PACK_DIR_SHIFT                (7U)
+/*! PACK_DIR
+ *  0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For
+ *       stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO.
+ *  0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For
+ *       stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO.
+ */
+#define CSI_CSICR1_PACK_DIR(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK)
+#define CSI_CSICR1_FCC_MASK                      (0x100U)
+#define CSI_CSICR1_FCC_SHIFT                     (8U)
+/*! FCC
+ *  0b0..Asynchronous FIFO clear is selected.
+ *  0b1..Synchronous FIFO clear is selected.
+ */
+#define CSI_CSICR1_FCC(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK)
+#define CSI_CSICR1_CCIR_EN_MASK                  (0x400U)
+#define CSI_CSICR1_CCIR_EN_SHIFT                 (10U)
+/*! CCIR_EN
+ *  0b0..Traditional interface is selected. Timing interface logic is used to latch data.
+ *  0b1..CCIR656 interface is selected.
+ */
+#define CSI_CSICR1_CCIR_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK)
+#define CSI_CSICR1_HSYNC_POL_MASK                (0x800U)
+#define CSI_CSICR1_HSYNC_POL_SHIFT               (11U)
+/*! HSYNC_POL
+ *  0b0..HSYNC is active low
+ *  0b1..HSYNC is active high
+ */
+#define CSI_CSICR1_HSYNC_POL(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK)
+#define CSI_CSICR1_SOF_INTEN_MASK                (0x10000U)
+#define CSI_CSICR1_SOF_INTEN_SHIFT               (16U)
+/*! SOF_INTEN
+ *  0b0..SOF interrupt disable
+ *  0b1..SOF interrupt enable
+ */
+#define CSI_CSICR1_SOF_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK)
+#define CSI_CSICR1_SOF_POL_MASK                  (0x20000U)
+#define CSI_CSICR1_SOF_POL_SHIFT                 (17U)
+/*! SOF_POL
+ *  0b0..SOF interrupt is generated on SOF falling edge
+ *  0b1..SOF interrupt is generated on SOF rising edge
+ */
+#define CSI_CSICR1_SOF_POL(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK)
+#define CSI_CSICR1_RXFF_INTEN_MASK               (0x40000U)
+#define CSI_CSICR1_RXFF_INTEN_SHIFT              (18U)
+/*! RXFF_INTEN
+ *  0b0..RxFIFO full interrupt disable
+ *  0b1..RxFIFO full interrupt enable
+ */
+#define CSI_CSICR1_RXFF_INTEN(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK)
+#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK       (0x80000U)
+#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT      (19U)
+/*! FB1_DMA_DONE_INTEN
+ *  0b0..Frame Buffer1 DMA Transfer Done interrupt disable
+ *  0b1..Frame Buffer1 DMA Transfer Done interrupt enable
+ */
+#define CSI_CSICR1_FB1_DMA_DONE_INTEN(x)         (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK)
+#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK       (0x100000U)
+#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT      (20U)
+/*! FB2_DMA_DONE_INTEN
+ *  0b0..Frame Buffer2 DMA Transfer Done interrupt disable
+ *  0b1..Frame Buffer2 DMA Transfer Done interrupt enable
+ */
+#define CSI_CSICR1_FB2_DMA_DONE_INTEN(x)         (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK)
+#define CSI_CSICR1_STATFF_INTEN_MASK             (0x200000U)
+#define CSI_CSICR1_STATFF_INTEN_SHIFT            (21U)
+/*! STATFF_INTEN
+ *  0b0..STATFIFO full interrupt disable
+ *  0b1..STATFIFO full interrupt enable
+ */
+#define CSI_CSICR1_STATFF_INTEN(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK)
+#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK       (0x400000U)
+#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT      (22U)
+/*! SFF_DMA_DONE_INTEN
+ *  0b0..STATFIFO DMA Transfer Done interrupt disable
+ *  0b1..STATFIFO DMA Transfer Done interrupt enable
+ */
+#define CSI_CSICR1_SFF_DMA_DONE_INTEN(x)         (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK)
+#define CSI_CSICR1_RF_OR_INTEN_MASK              (0x1000000U)
+#define CSI_CSICR1_RF_OR_INTEN_SHIFT             (24U)
+/*! RF_OR_INTEN
+ *  0b0..RxFIFO overrun interrupt is disabled
+ *  0b1..RxFIFO overrun interrupt is enabled
+ */
+#define CSI_CSICR1_RF_OR_INTEN(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK)
+#define CSI_CSICR1_SF_OR_INTEN_MASK              (0x2000000U)
+#define CSI_CSICR1_SF_OR_INTEN_SHIFT             (25U)
+/*! SF_OR_INTEN
+ *  0b0..STATFIFO overrun interrupt is disabled
+ *  0b1..STATFIFO overrun interrupt is enabled
+ */
+#define CSI_CSICR1_SF_OR_INTEN(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK)
+#define CSI_CSICR1_COF_INT_EN_MASK               (0x4000000U)
+#define CSI_CSICR1_COF_INT_EN_SHIFT              (26U)
+/*! COF_INT_EN
+ *  0b0..COF interrupt is disabled
+ *  0b1..COF interrupt is enabled
+ */
+#define CSI_CSICR1_COF_INT_EN(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK)
+#define CSI_CSICR1_VIDEO_MODE_MASK               (0x8000000U)
+#define CSI_CSICR1_VIDEO_MODE_SHIFT              (27U)
+/*! VIDEO_MODE
+ *  0b0..Progressive mode is selected
+ *  0b1..Interlace mode is selected
+ */
+#define CSI_CSICR1_VIDEO_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_VIDEO_MODE_SHIFT)) & CSI_CSICR1_VIDEO_MODE_MASK)
+#define CSI_CSICR1_PrP_IF_EN_MASK                (0x10000000U)
+#define CSI_CSICR1_PrP_IF_EN_SHIFT               (28U)
+/*! PrP_IF_EN
+ *  0b0..CSI to PrP bus is disabled
+ *  0b1..CSI to PrP bus is enabled
+ */
+#define CSI_CSICR1_PrP_IF_EN(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK)
+#define CSI_CSICR1_EOF_INT_EN_MASK               (0x20000000U)
+#define CSI_CSICR1_EOF_INT_EN_SHIFT              (29U)
+/*! EOF_INT_EN
+ *  0b0..EOF interrupt is disabled.
+ *  0b1..EOF interrupt is generated when RX count value is reached.
+ */
+#define CSI_CSICR1_EOF_INT_EN(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK)
+#define CSI_CSICR1_EXT_VSYNC_MASK                (0x40000000U)
+#define CSI_CSICR1_EXT_VSYNC_SHIFT               (30U)
+/*! EXT_VSYNC
+ *  0b0..Internal VSYNC mode
+ *  0b1..External VSYNC mode
+ */
+#define CSI_CSICR1_EXT_VSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK)
+#define CSI_CSICR1_SWAP16_EN_MASK                (0x80000000U)
+#define CSI_CSICR1_SWAP16_EN_SHIFT               (31U)
+/*! SWAP16_EN
+ *  0b0..Disable swapping
+ *  0b1..Enable swapping
+ */
+#define CSI_CSICR1_SWAP16_EN(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK)
+/*! @} */
+/*! @name CSICR2 - CSI Control Register 2 */
+/*! @{ */
+#define CSI_CSICR2_HSC_MASK                      (0xFFU)
+#define CSI_CSICR2_HSC_SHIFT                     (0U)
+#define CSI_CSICR2_HSC(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK)
+#define CSI_CSICR2_VSC_MASK                      (0xFF00U)
+#define CSI_CSICR2_VSC_SHIFT                     (8U)
+#define CSI_CSICR2_VSC(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK)
+#define CSI_CSICR2_LVRM_MASK                     (0x70000U)
+#define CSI_CSICR2_LVRM_SHIFT                    (16U)
+/*! LVRM
+ *  0b000..512 x 384
+ *  0b001..448 x 336
+ *  0b010..384 x 288
+ *  0b011..384 x 256
+ *  0b100..320 x 240
+ *  0b101..288 x 216
+ *  0b110..400 x 300
+ */
+#define CSI_CSICR2_LVRM(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK)
+#define CSI_CSICR2_BTS_MASK                      (0x180000U)
+#define CSI_CSICR2_BTS_SHIFT                     (19U)
+/*! BTS
+ *  0b00..GR
+ *  0b01..RG
+ *  0b10..BG
+ *  0b11..GB
+ */
+#define CSI_CSICR2_BTS(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK)
+#define CSI_CSICR2_SCE_MASK                      (0x800000U)
+#define CSI_CSICR2_SCE_SHIFT                     (23U)
+/*! SCE
+ *  0b0..Skip count disable
+ *  0b1..Skip count enable
+ */
+#define CSI_CSICR2_SCE(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK)
+#define CSI_CSICR2_AFS_MASK                      (0x3000000U)
+#define CSI_CSICR2_AFS_SHIFT                     (24U)
+/*! AFS
+ *  0b00..Abs Diff on consecutive green pixels
+ *  0b01..Abs Diff on every third green pixels
+ *  0b1x..Abs Diff on every four green pixels
+ */
+#define CSI_CSICR2_AFS(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK)
+#define CSI_CSICR2_DRM_MASK                      (0x4000000U)
+#define CSI_CSICR2_DRM_SHIFT                     (26U)
+/*! DRM
+ *  0b0..Stats grid of 8 x 6
+ *  0b1..Stats grid of 8 x 12
+ */
+#define CSI_CSICR2_DRM(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK)
+#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK       (0x30000000U)
+#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT      (28U)
+/*! DMA_BURST_TYPE_SFF
+ *  0bx0..INCR8
+ *  0b01..INCR4
+ *  0b11..INCR16
+ */
+#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x)         (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK)
+#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK       (0xC0000000U)
+#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT      (30U)
+/*! DMA_BURST_TYPE_RFF
+ *  0bx0..INCR8
+ *  0b01..INCR4
+ *  0b11..INCR16
+ */
+#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x)         (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK)
+/*! @} */
+/*! @name CSICR3 - CSI Control Register 3 */
+/*! @{ */
+#define CSI_CSICR3_ECC_AUTO_EN_MASK              (0x1U)
+#define CSI_CSICR3_ECC_AUTO_EN_SHIFT             (0U)
+/*! ECC_AUTO_EN
+ *  0b0..Auto Error correction is disabled.
+ *  0b1..Auto Error correction is enabled.
+ */
+#define CSI_CSICR3_ECC_AUTO_EN(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK)
+#define CSI_CSICR3_ECC_INT_EN_MASK               (0x2U)
+#define CSI_CSICR3_ECC_INT_EN_SHIFT              (1U)
+/*! ECC_INT_EN
+ *  0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set.
+ *  0b1..Interrupt is generated when error is detected.
+ */
+#define CSI_CSICR3_ECC_INT_EN(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK)
+#define CSI_CSICR3_ZERO_PACK_EN_MASK             (0x4U)
+#define CSI_CSICR3_ZERO_PACK_EN_SHIFT            (2U)
+/*! ZERO_PACK_EN
+ *  0b0..Zero packing disabled
+ *  0b1..Zero packing enabled
+ */
+#define CSI_CSICR3_ZERO_PACK_EN(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK)
+#define CSI_CSICR3_TWO_8BIT_SENSOR_MASK          (0x8U)
+#define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT         (3U)
+/*! TWO_8BIT_SENSOR
+ *  0b0..Only one 8-bit sensor is connected.
+ *  0b1..One 16-bit sensor is connected.
+ */
+#define CSI_CSICR3_TWO_8BIT_SENSOR(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK)
+#define CSI_CSICR3_RxFF_LEVEL_MASK               (0x70U)
+#define CSI_CSICR3_RxFF_LEVEL_SHIFT              (4U)
+/*! RxFF_LEVEL
+ *  0b000..4 Double words
+ *  0b001..8 Double words
+ *  0b010..16 Double words
+ *  0b011..24 Double words
+ *  0b100..32 Double words
+ *  0b101..48 Double words
+ *  0b110..64 Double words
+ *  0b111..96 Double words
+ */
+#define CSI_CSICR3_RxFF_LEVEL(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK)
+#define CSI_CSICR3_HRESP_ERR_EN_MASK             (0x80U)
+#define CSI_CSICR3_HRESP_ERR_EN_SHIFT            (7U)
+/*! HRESP_ERR_EN
+ *  0b0..Disable hresponse error interrupt
+ *  0b1..Enable hresponse error interrupt
+ */
+#define CSI_CSICR3_HRESP_ERR_EN(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK)
+#define CSI_CSICR3_STATFF_LEVEL_MASK             (0x700U)
+#define CSI_CSICR3_STATFF_LEVEL_SHIFT            (8U)
+/*! STATFF_LEVEL
+ *  0b000..4 Double words
+ *  0b001..8 Double words
+ *  0b010..12 Double words
+ *  0b011..16 Double words
+ *  0b100..24 Double words
+ *  0b101..32 Double words
+ *  0b110..48 Double words
+ *  0b111..64 Double words
+ */
+#define CSI_CSICR3_STATFF_LEVEL(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK)
+#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK           (0x800U)
+#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT          (11U)
+/*! DMA_REQ_EN_SFF
+ *  0b0..Disable the dma request
+ *  0b1..Enable the dma request
+ */
+#define CSI_CSICR3_DMA_REQ_EN_SFF(x)             (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK)
+#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK           (0x1000U)
+#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT          (12U)
+/*! DMA_REQ_EN_RFF
+ *  0b0..Disable the dma request
+ *  0b1..Enable the dma request
+ */
+#define CSI_CSICR3_DMA_REQ_EN_RFF(x)             (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK)
+#define CSI_CSICR3_DMA_REFLASH_SFF_MASK          (0x2000U)
+#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT         (13U)
+/*! DMA_REFLASH_SFF
+ *  0b0..No reflashing
+ *  0b1..Reflash the embedded DMA controller
+ */
+#define CSI_CSICR3_DMA_REFLASH_SFF(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK)
+#define CSI_CSICR3_DMA_REFLASH_RFF_MASK          (0x4000U)
+#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT         (14U)
+/*! DMA_REFLASH_RFF
+ *  0b0..No reflashing
+ *  0b1..Reflash the embedded DMA controller
+ */
+#define CSI_CSICR3_DMA_REFLASH_RFF(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK)
+#define CSI_CSICR3_FRMCNT_RST_MASK               (0x8000U)
+#define CSI_CSICR3_FRMCNT_RST_SHIFT              (15U)
+/*! FRMCNT_RST
+ *  0b0..Do not reset
+ *  0b1..Reset frame counter immediately
+ */
+#define CSI_CSICR3_FRMCNT_RST(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK)
+#define CSI_CSICR3_FRMCNT_MASK                   (0xFFFF0000U)
+#define CSI_CSICR3_FRMCNT_SHIFT                  (16U)
+#define CSI_CSICR3_FRMCNT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK)
+/*! @} */
+/*! @name CSISTATFIFO - CSI Statistic FIFO Register */
+/*! @{ */
+#define CSI_CSISTATFIFO_STAT_MASK                (0xFFFFFFFFU)
+#define CSI_CSISTATFIFO_STAT_SHIFT               (0U)
+#define CSI_CSISTATFIFO_STAT(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK)
+/*! @} */
+/*! @name CSIRFIFO - CSI RX FIFO Register */
+/*! @{ */
+#define CSI_CSIRFIFO_IMAGE_MASK                  (0xFFFFFFFFU)
+#define CSI_CSIRFIFO_IMAGE_SHIFT                 (0U)
+#define CSI_CSIRFIFO_IMAGE(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK)
+/*! @} */
+/*! @name CSIRXCNT - CSI RX Count Register */
+/*! @{ */
+#define CSI_CSIRXCNT_RXCNT_MASK                  (0x3FFFFFU)
+#define CSI_CSIRXCNT_RXCNT_SHIFT                 (0U)
+#define CSI_CSIRXCNT_RXCNT(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK)
+/*! @} */
+/*! @name CSISR - CSI Status Register */
+/*! @{ */
+#define CSI_CSISR_DRDY_MASK                      (0x1U)
+#define CSI_CSISR_DRDY_SHIFT                     (0U)
+/*! DRDY
+ *  0b0..No data (word) is ready
+ *  0b1..At least 1 datum (word) is ready in RXFIFO.
+ */
+#define CSI_CSISR_DRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK)
+#define CSI_CSISR_ECC_INT_MASK                   (0x2U)
+#define CSI_CSISR_ECC_INT_SHIFT                  (1U)
+/*! ECC_INT
+ *  0b0..No error detected
+ *  0b1..Error is detected in CCIR coding
+ */
+#define CSI_CSISR_ECC_INT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK)
+#define CSI_CSISR_HRESP_ERR_INT_MASK             (0x80U)
+#define CSI_CSISR_HRESP_ERR_INT_SHIFT            (7U)
+/*! HRESP_ERR_INT
+ *  0b0..No hresponse error.
+ *  0b1..Hresponse error is detected.
+ */
+#define CSI_CSISR_HRESP_ERR_INT(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK)
+#define CSI_CSISR_COF_INT_MASK                   (0x2000U)
+#define CSI_CSISR_COF_INT_SHIFT                  (13U)
+/*! COF_INT
+ *  0b0..Video field has no change.
+ *  0b1..Change of video field is detected.
+ */
+#define CSI_CSISR_COF_INT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK)
+#define CSI_CSISR_F1_INT_MASK                    (0x4000U)
+#define CSI_CSISR_F1_INT_SHIFT                   (14U)
+/*! F1_INT
+ *  0b0..Field 1 of video is not detected.
+ *  0b1..Field 1 of video is about to start.
+ */
+#define CSI_CSISR_F1_INT(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK)
+#define CSI_CSISR_F2_INT_MASK                    (0x8000U)
+#define CSI_CSISR_F2_INT_SHIFT                   (15U)
+/*! F2_INT
+ *  0b0..Field 2 of video is not detected
+ *  0b1..Field 2 of video is about to start
+ */
+#define CSI_CSISR_F2_INT(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK)
+#define CSI_CSISR_SOF_INT_MASK                   (0x10000U)
+#define CSI_CSISR_SOF_INT_SHIFT                  (16U)
+/*! SOF_INT
+ *  0b0..SOF is not detected.
+ *  0b1..SOF is detected.
+ */
+#define CSI_CSISR_SOF_INT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK)
+#define CSI_CSISR_EOF_INT_MASK                   (0x20000U)
+#define CSI_CSISR_EOF_INT_SHIFT                  (17U)
+/*! EOF_INT
+ *  0b0..EOF is not detected.
+ *  0b1..EOF is detected.
+ */
+#define CSI_CSISR_EOF_INT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK)
+#define CSI_CSISR_RxFF_INT_MASK                  (0x40000U)
+#define CSI_CSISR_RxFF_INT_SHIFT                 (18U)
+/*! RxFF_INT
+ *  0b0..RxFIFO is not full.
+ *  0b1..RxFIFO is full.
+ */
+#define CSI_CSISR_RxFF_INT(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK)
+#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK          (0x80000U)
+#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT         (19U)
+/*! DMA_TSF_DONE_FB1
+ *  0b0..DMA transfer is not completed.
+ *  0b1..DMA transfer is completed.
+ */
+#define CSI_CSISR_DMA_TSF_DONE_FB1(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK)
+#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK          (0x100000U)
+#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT         (20U)
+/*! DMA_TSF_DONE_FB2
+ *  0b0..DMA transfer is not completed.
+ *  0b1..DMA transfer is completed.
+ */
+#define CSI_CSISR_DMA_TSF_DONE_FB2(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK)
+#define CSI_CSISR_STATFF_INT_MASK                (0x200000U)
+#define CSI_CSISR_STATFF_INT_SHIFT               (21U)
+/*! STATFF_INT
+ *  0b0..STATFIFO is not full.
+ *  0b1..STATFIFO is full.
+ */
+#define CSI_CSISR_STATFF_INT(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK)
+#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK          (0x400000U)
+#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT         (22U)
+/*! DMA_TSF_DONE_SFF
+ *  0b0..DMA transfer is not completed.
+ *  0b1..DMA transfer is completed.
+ */
+#define CSI_CSISR_DMA_TSF_DONE_SFF(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK)
+#define CSI_CSISR_RF_OR_INT_MASK                 (0x1000000U)
+#define CSI_CSISR_RF_OR_INT_SHIFT                (24U)
+/*! RF_OR_INT
+ *  0b0..RXFIFO has not overflowed.
+ *  0b1..RXFIFO has overflowed.
+ */
+#define CSI_CSISR_RF_OR_INT(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK)
+#define CSI_CSISR_SF_OR_INT_MASK                 (0x2000000U)
+#define CSI_CSISR_SF_OR_INT_SHIFT                (25U)
+/*! SF_OR_INT
+ *  0b0..STATFIFO has not overflowed.
+ *  0b1..STATFIFO has overflowed.
+ */
+#define CSI_CSISR_SF_OR_INT(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK)
+#define CSI_CSISR_DMA_FIELD1_DONE_MASK           (0x4000000U)
+#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT          (26U)
+#define CSI_CSISR_DMA_FIELD1_DONE(x)             (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK)
+#define CSI_CSISR_DMA_FIELD0_DONE_MASK           (0x8000000U)
+#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT          (27U)
+#define CSI_CSISR_DMA_FIELD0_DONE(x)             (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK)
+#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK    (0x10000000U)
+#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT   (28U)
+#define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x)      (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK)
+/*! @} */
+/*! @name CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */
+/*! @{ */
+#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)
+#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)
+#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)
+/*! @} */
+/*! @name CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */
+/*! @{ */
+#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)
+#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)
+#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)
+/*! @} */
+/*! @name CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */
+/*! @{ */
+#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU)
+#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U)
+#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x)   (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK)
+/*! @} */
+/*! @name CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */
+/*! @{ */
+#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU)
+#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U)
+#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x)   (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK)
+/*! @} */
+/*! @name CSIFBUF_PARA - CSI Frame Buffer Parameter Register */
+/*! @{ */
+#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK        (0xFFFFU)
+#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT       (0U)
+#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x)          (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK)
+#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U)
+#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U)
+#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x)   (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK)
+/*! @} */
+/*! @name CSIIMAG_PARA - CSI Image Parameter Register */
+/*! @{ */
+#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK       (0xFFFFU)
+#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT      (0U)
+#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x)         (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK)
+#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK        (0xFFFF0000U)
+#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT       (16U)
+#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x)          (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK)
+/*! @} */
+/*! @name CSICR18 - CSI Control Register 18 */
+/*! @{ */
+#define CSI_CSICR18_DEINTERLACE_EN_MASK          (0x4U)
+#define CSI_CSICR18_DEINTERLACE_EN_SHIFT         (2U)
+/*! DEINTERLACE_EN
+ *  0b0..Deinterlace disabled
+ *  0b1..Deinterlace enabled
+ */
+#define CSI_CSICR18_DEINTERLACE_EN(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK)
+#define CSI_CSICR18_PARALLEL24_EN_MASK           (0x8U)
+#define CSI_CSICR18_PARALLEL24_EN_SHIFT          (3U)
+#define CSI_CSICR18_PARALLEL24_EN(x)             (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK)
+#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK      (0x10U)
+#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT     (4U)
+#define CSI_CSICR18_BASEADDR_SWITCH_EN(x)        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK)
+#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK     (0x20U)
+#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT    (5U)
+/*! BASEADDR_SWITCH_SEL
+ *  0b0..Switching base address at the edge of the vsync
+ *  0b1..Switching base address at the edge of the first data of each frame
+ */
+#define CSI_CSICR18_BASEADDR_SWITCH_SEL(x)       (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK)
+#define CSI_CSICR18_FIELD0_DONE_IE_MASK          (0x40U)
+#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT         (6U)
+/*! FIELD0_DONE_IE
+ *  0b0..Interrupt disabled
+ *  0b1..Interrupt enabled
+ */
+#define CSI_CSICR18_FIELD0_DONE_IE(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK)
+#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK      (0x80U)
+#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT     (7U)
+/*! DMA_FIELD1_DONE_IE
+ *  0b0..Interrupt disabled
+ *  0b1..Interrupt enabled
+ */
+#define CSI_CSICR18_DMA_FIELD1_DONE_IE(x)        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK)
+#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK        (0x100U)
+#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT       (8U)
+/*! LAST_DMA_REQ_SEL
+ *  0b0..fifo_full_level
+ *  0b1..hburst_length
+ */
+#define CSI_CSICR18_LAST_DMA_REQ_SEL(x)          (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK)
+#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U)
+#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U)
+#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x)  (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK)
+#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK      (0x400U)
+#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT     (10U)
+/*! RGB888A_FORMAT_SEL
+ *  0b0..{8'h0, data[23:0]}
+ *  0b1..{data[23:0], 8'h0}
+ */
+#define CSI_CSICR18_RGB888A_FORMAT_SEL(x)        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK)
+#define CSI_CSICR18_AHB_HPROT_MASK               (0xF000U)
+#define CSI_CSICR18_AHB_HPROT_SHIFT              (12U)
+#define CSI_CSICR18_AHB_HPROT(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK)
+#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK  (0x30000U)
+#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT (16U)
+/*! CSI_LCDIF_BUFFER_LINES
+ *  0b00..4 lines
+ *  0b01..8 lines
+ *  0b10..16 lines
+ *  0b11..16 lines
+ */
+#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES(x)    (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT)) & CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK)
+#define CSI_CSICR18_MASK_OPTION_MASK             (0xC0000U)
+#define CSI_CSICR18_MASK_OPTION_SHIFT            (18U)
+/*! MASK_OPTION
+ *  0b00..Writing to memory from first completely frame, when using this option, the CSI_ENABLE should be 1.
+ *  0b01..Writing to memory when CSI_ENABLE is 1.
+ *  0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1.
+ *  0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0.
+ */
+#define CSI_CSICR18_MASK_OPTION(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK)
+#define CSI_CSICR18_MIPI_DOUBLE_CMPNT_MASK       (0x100000U)
+#define CSI_CSICR18_MIPI_DOUBLE_CMPNT_SHIFT      (20U)
+/*! MIPI_DOUBLE_CMPNT
+ *  0b0..Single component per clock cycle (half pixel per clock cycle)
+ *  0b1..Double component per clock cycle (a pixel per clock cycle)
+ */
+#define CSI_CSICR18_MIPI_DOUBLE_CMPNT(x)         (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MIPI_DOUBLE_CMPNT_SHIFT)) & CSI_CSICR18_MIPI_DOUBLE_CMPNT_MASK)
+#define CSI_CSICR18_MIPI_YU_SWAP_MASK            (0x200000U)
+#define CSI_CSICR18_MIPI_YU_SWAP_SHIFT           (21U)
+#define CSI_CSICR18_MIPI_YU_SWAP(x)              (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MIPI_YU_SWAP_SHIFT)) & CSI_CSICR18_MIPI_YU_SWAP_MASK)
+#define CSI_CSICR18_DATA_FROM_MIPI_MASK          (0x400000U)
+#define CSI_CSICR18_DATA_FROM_MIPI_SHIFT         (22U)
+/*! DATA_FROM_MIPI
+ *  0b0..Data from parallel sensor
+ *  0b1..Data from MIPI
+ */
+#define CSI_CSICR18_DATA_FROM_MIPI(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DATA_FROM_MIPI_SHIFT)) & CSI_CSICR18_DATA_FROM_MIPI_MASK)
+#define CSI_CSICR18_LINE_STRIDE_EN_MASK          (0x1000000U)
+#define CSI_CSICR18_LINE_STRIDE_EN_SHIFT         (24U)
+#define CSI_CSICR18_LINE_STRIDE_EN(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LINE_STRIDE_EN_SHIFT)) & CSI_CSICR18_LINE_STRIDE_EN_MASK)
+#define CSI_CSICR18_MIPI_DATA_FORMAT_MASK        (0x7E000000U)
+#define CSI_CSICR18_MIPI_DATA_FORMAT_SHIFT       (25U)
+#define CSI_CSICR18_MIPI_DATA_FORMAT(x)          (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MIPI_DATA_FORMAT_SHIFT)) & CSI_CSICR18_MIPI_DATA_FORMAT_MASK)
+#define CSI_CSICR18_CSI_ENABLE_MASK              (0x80000000U)
+#define CSI_CSICR18_CSI_ENABLE_SHIFT             (31U)
+#define CSI_CSICR18_CSI_ENABLE(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK)
+/*! @} */
+/*!
+ * @}
+ */ /* end of group CSI_Register_Masks */
+/* CSI - Peripheral instance base addresses */
+/** Peripheral CSI base address */
+#define CSI_BASE                                 (0x32E20000u)
+/** Peripheral CSI base pointer */
+#define CSI                                      ((CSI_Type *)CSI_BASE)
+/** Array initializer of CSI peripheral base addresses */
+#define CSI_BASE_ADDRS                           { CSI_BASE }
+/** Array initializer of CSI peripheral base pointers */
+#define CSI_BASE_PTRS                            { CSI }
+/*!
+ * @}
+ */ /* end of group CSI_Peripheral_Access_Layer */
+/* ----------------------------------------------------------------------------
+   -- DDRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup DDRC_Peripheral_Access_Layer DDRC Peripheral Access Layer
+ * @{
+ */
+/** DDRC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MSTR;                              /**< Master Register0, offset: 0x0 */
+  __I  uint32_t STAT;                              /**< Operating Mode Status Register, offset: 0x4 */
+  __IO uint32_t MSTR1;                             /**< Operating Mode Status Register, offset: 0x8 */
+  __IO uint32_t MRCTRL3;                           /**< Operating Mode Status Register, offset: 0xC */
+  __IO uint32_t MRCTRL0;                           /**< Mode Register Read/Write Control Register 0., offset: 0x10 */
+  __IO uint32_t MRCTRL1;                           /**< Mode Register Read/Write Control Register 1, offset: 0x14 */
+  __I  uint32_t MRSTAT;                            /**< Mode Register Read/Write Status Register, offset: 0x18 */
+  __IO uint32_t MRCTRL2;                           /**< Mode Register Read/Write Control Register 2, offset: 0x1C */
+  __IO uint32_t DERATEEN;                          /**< Temperature Derate Enable Register, offset: 0x20 */
+  __IO uint32_t DERATEINT;                         /**< Temperature Derate Interval Register, offset: 0x24 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t PWRCTL;                            /**< Low Power Control Register, offset: 0x30 */
+  __IO uint32_t PWRTMG;                            /**< Low Power Timing Register, offset: 0x34 */
+  __IO uint32_t HWLPCTL;                           /**< Hardware Low Power Control Register, offset: 0x38 */
+       uint8_t RESERVED_1[20];
+  __IO uint32_t RFSHCTL0;                          /**< Refresh Control Register 0, offset: 0x50 */
+  __IO uint32_t RFSHCTL1;                          /**< Refresh Control Register 1, offset: 0x54 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t RFSHCTL3;                          /**< Refresh Control Register 3, offset: 0x60 */
+  __IO uint32_t RFSHTMG;                           /**< Refresh Timing Register, offset: 0x64 */
+       uint8_t RESERVED_3[104];
+  __IO uint32_t INIT0;                             /**< SDRAM Initialization Register 0, offset: 0xD0 */
+  __IO uint32_t INIT1;                             /**< SDRAM Initialization Register 1, offset: 0xD4 */
+  __IO uint32_t INIT2;                             /**< SDRAM Initialization Register 2, offset: 0xD8 */
+  __IO uint32_t INIT3;                             /**< SDRAM Initialization Register 3, offset: 0xDC */
+  __IO uint32_t INIT4;                             /**< SDRAM Initialization Register 4, offset: 0xE0 */
+  __IO uint32_t INIT5;                             /**< SDRAM Initialization Register 5, offset: 0xE4 */
+  __IO uint32_t INIT6;                             /**< SDRAM Initialization Register 6, offset: 0xE8 */
+  __IO uint32_t INIT7;                             /**< SDRAM Initialization Register 7, offset: 0xEC */
+  __IO uint32_t DIMMCTL;                           /**< DIMM Control Register, offset: 0xF0 */
+  __IO uint32_t RANKCTL;                           /**< Rank Control Register, offset: 0xF4 */
+       uint8_t RESERVED_4[8];
+  __IO uint32_t DRAMTMG0;                          /**< SDRAM Timing Register 0, offset: 0x100 */
+  __IO uint32_t DRAMTMG1;                          /**< SDRAM Timing Register 1, offset: 0x104 */
+  __IO uint32_t DRAMTMG2;                          /**< SDRAM Timing Register 2, offset: 0x108 */
+  __IO uint32_t DRAMTMG3;                          /**< SDRAM Timing Register 3, offset: 0x10C */
+  __IO uint32_t DRAMTMG4;                          /**< SDRAM Timing Register 4, offset: 0x110 */
+  __IO uint32_t DRAMTMG5;                          /**< SDRAM Timing Register 5, offset: 0x114 */
+  __IO uint32_t DRAMTMG6;                          /**< SDRAM Timing Register 6, offset: 0x118 */
+  __IO uint32_t DRAMTMG7;                          /**< SDRAM Timing Register 7, offset: 0x11C */
+  __IO uint32_t DRAMTMG8;                          /**< SDRAM Timing Register 8, offset: 0x120 */
+  __IO uint32_t DRAMTMG9;                          /**< SDRAM Timing Register 9, offset: 0x124 */
+  __IO uint32_t DRAMTMG10;                         /**< SDRAM Timing Register 10, offset: 0x128 */
+  __IO uint32_t DRAMTMG11;                         /**< SDRAM Timing Register 11, offset: 0x12C */
+  __IO uint32_t DRAMTMG12;                         /**< SDRAM Timing Register 12, offset: 0x130 */
+  __IO uint32_t DRAMTMG13;                         /**< SDRAM Timing Register 13, offset: 0x134 */
+  __IO uint32_t DRAMTMG14;                         /**< SDRAM Timing Register 14, offset: 0x138 */
+  __IO uint32_t DRAMTMG15;                         /**< SDRAM Timing Register 15, offset: 0x13C */
+       uint8_t RESERVED_5[64];
+  __IO uint32_t ZQCTL0;                            /**< ZQ Control Register 0, offset: 0x180 */
+  __IO uint32_t ZQCTL1;                            /**< ZQ Control Register 1, offset: 0x184 */
+  __IO uint32_t ZQCTL2;                            /**< ZQ Control Register 2, offset: 0x188 */
+  __I  uint32_t ZQSTAT;                            /**< ZQ Status Register, offset: 0x18C */
+  __IO uint32_t DFITMG0;                           /**< DFI Timing Register 0, offset: 0x190 */
+  __IO uint32_t DFITMG1;                           /**< DFI Timing Register 1, offset: 0x194 */
+  __IO uint32_t DFILPCFG0;                         /**< DFI Low Power Configuration Register 0, offset: 0x198 */
+  __IO uint32_t DFILPCFG1;                         /**< DFI Low Power Configuration Register 1, offset: 0x19C */
+  __IO uint32_t DFIUPD0;                           /**< DFI Update Register 0, offset: 0x1A0 */
+  __IO uint32_t DFIUPD1;                           /**< DFI Update Register 1, offset: 0x1A4 */
+  __IO uint32_t DFIUPD2;                           /**< DFI Update Register 2, offset: 0x1A8 */
+       uint8_t RESERVED_6[4];
+  __IO uint32_t DFIMISC;                           /**< DFI Miscellaneous Control Register, offset: 0x1B0 */
+  __IO uint32_t DFITMG2;                           /**< DFI Timing Register 2, offset: 0x1B4 */
+  __IO uint32_t DFITMG3;                           /**< DFI Timing Register 3, offset: 0x1B8 */
+  __I  uint32_t DFISTAT;                           /**< DFI Status Register, offset: 0x1BC */
+  __IO uint32_t DBICTL;                            /**< DM/DBI Control Register, offset: 0x1C0 */
+       uint8_t RESERVED_7[60];
+  __IO uint32_t ADDRMAP0;                          /**< Address Map Register 0, offset: 0x200 */
+  __IO uint32_t ADDRMAP1;                          /**< Address Map Register 1, offset: 0x204 */
+  __IO uint32_t ADDRMAP2;                          /**< Address Map Register 2, offset: 0x208 */
+  __IO uint32_t ADDRMAP3;                          /**< Address Map Register 3, offset: 0x20C */
+  __IO uint32_t ADDRMAP4;                          /**< Address Map Register 4, offset: 0x210 */
+  __IO uint32_t ADDRMAP5;                          /**< Address Map Register 5, offset: 0x214 */
+  __IO uint32_t ADDRMAP6;                          /**< Address Map Register 6, offset: 0x218 */
+  __IO uint32_t ADDRMAP7;                          /**< Address Map Register 7, offset: 0x21C */
+  __IO uint32_t ADDRMAP8;                          /**< Address Map Register 8, offset: 0x220 */
+  __IO uint32_t ADDRMAP9;                          /**< Address Map Register 9, offset: 0x224 */
+  __IO uint32_t ADDRMAP10;                         /**< Address Map Register 10, offset: 0x228 */
+  __IO uint32_t ADDRMAP11;                         /**< Address Map Register 11, offset: 0x22C */
+       uint8_t RESERVED_8[16];
+  __IO uint32_t ODTCFG;                            /**< ODT Configuration Register, offset: 0x240 */
+  __IO uint32_t ODTMAP;                            /**< ODT/Rank Map Register, offset: 0x244 */
+       uint8_t RESERVED_9[8];
+  __IO uint32_t SCHED;                             /**< Scheduler Control Register, offset: 0x250 */
+  __IO uint32_t SCHED1;                            /**< Scheduler Control Register 1, offset: 0x254 */
+       uint8_t RESERVED_10[4];
+  __IO uint32_t PERFHPR1;                          /**< High Priority Read CAM Register 1, offset: 0x25C */
+       uint8_t RESERVED_11[4];
+  __IO uint32_t PERFLPR1;                          /**< Low Priority Read CAM Register 1, offset: 0x264 */
+       uint8_t RESERVED_12[4];
+  __IO uint32_t PERFWR1;                           /**< Write CAM Register 1, offset: 0x26C */
+       uint8_t RESERVED_13[144];
+  __IO uint32_t DBG0;                              /**< Debug Register 0, offset: 0x300 */
+  __IO uint32_t DBG1;                              /**< Debug Register 1, offset: 0x304 */
+  __I  uint32_t DBGCAM;                            /**< CAM Debug Register, offset: 0x308 */
+  __IO uint32_t DBGCMD;                            /**< Command Debug Register, offset: 0x30C */
+  __I  uint32_t DBGSTAT;                           /**< Status Debug Register, offset: 0x310 */
+       uint8_t RESERVED_14[12];
+  __IO uint32_t SWCTL;                             /**< Software Register Programming Control Enable, offset: 0x320 */
+  __I  uint32_t SWSTAT;                            /**< Software Register Programming Control Status, offset: 0x324 */
+       uint8_t RESERVED_15[68];
+  __IO uint32_t POISONCFG;                         /**< AXI Poison Configuration Register., offset: 0x36C */
+  __I  uint32_t POISONSTAT;                        /**< AXI Poison Status Register, offset: 0x370 */
+       uint8_t RESERVED_16[136];
+  __I  uint32_t PSTAT;                             /**< Port Status Register, offset: 0x3FC */
+  __IO uint32_t PCCFG;                             /**< Port Common Configuration Register, offset: 0x400 */
+  __IO uint32_t PCFGR_0;                           /**< Port n Configuration Read Register, offset: 0x404 */
+  __IO uint32_t PCFGW_0;                           /**< Port n Configuration Write Register, offset: 0x408 */
+       uint8_t RESERVED_17[132];
+  __IO uint32_t PCTRL_0;                           /**< Port n Control Register, offset: 0x490 */
+  __IO uint32_t PCFGQOS0_0;                        /**< Port n Read QoS Configuration Register 0, offset: 0x494 */
+  __IO uint32_t PCFGQOS1_0;                        /**< Port n Read QoS Configuration Register 1, offset: 0x498 */
+  __IO uint32_t PCFGWQOS0_0;                       /**< Port n Write QoS Configuration Register 0, offset: 0x49C */
+  __IO uint32_t PCFGWQOS1_0;                       /**< Port n Write QoS Configuration Register 1, offset: 0x4A0 */
+       uint8_t RESERVED_18[7036];
+  __IO uint32_t DERATEEN_SHADOW;                   /**< [SHADOW] Temperature Derate Enable Register, offset: 0x2020 */
+  __IO uint32_t DERATEINT_SHADOW;                  /**< [SHADOW] Temperature Derate Interval Register, offset: 0x2024 */
+       uint8_t RESERVED_19[40];
+  __IO uint32_t RFSHCTL0_SHADOW;                   /**< [SHADOW] Refresh Control Register 0, offset: 0x2050 */
+       uint8_t RESERVED_20[16];
+  __IO uint32_t RFSHTMG_SHADOW;                    /**< [SHADOW] Refresh Timing Register, offset: 0x2064 */
+       uint8_t RESERVED_21[116];
+  __IO uint32_t INIT3_SHADOW;                      /**< [SHADOW] SDRAM Initialization Register 3, offset: 0x20DC */
+  __IO uint32_t INIT4_SHADOW;                      /**< [SHADOW] SDRAM Initialization Register 4, offset: 0x20E0 */
+       uint8_t RESERVED_22[4];
+  __IO uint32_t INIT6_SHADOW;                      /**< [SHADOW] SDRAM Initialization Register 6, offset: 0x20E8 */
+  __IO uint32_t INIT7_SHADOW;                      /**< [SHADOW] SDRAM Initialization Register 7, offset: 0x20EC */
+       uint8_t RESERVED_23[16];
+  __IO uint32_t DRAMTMG0_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 0, offset: 0x2100 */
+  __IO uint32_t DRAMTMG1_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 1, offset: 0x2104 */
+  __IO uint32_t DRAMTMG2_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 2, offset: 0x2108 */
+  __IO uint32_t DRAMTMG3_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 3, offset: 0x210C */
+  __IO uint32_t DRAMTMG4_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 4, offset: 0x2110 */
+  __IO uint32_t DRAMTMG5_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 5, offset: 0x2114 */
+  __IO uint32_t DRAMTMG6_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 6, offset: 0x2118 */
+  __IO uint32_t DRAMTMG7_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 7, offset: 0x211C */
+  __IO uint32_t DRAMTMG8_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 8, offset: 0x2120 */
+  __IO uint32_t DRAMTMG9_SHADOW;                   /**< [SHADOW] SDRAM Timing Register 9, offset: 0x2124 */
+  __IO uint32_t DRAMTMG10_SHADOW;                  /**< [SHADOW] SDRAM Timing Register 10, offset: 0x2128 */
+  __IO uint32_t DRAMTMG11_SHADOW;                  /**< [SHADOW] SDRAM Timing Register 11, offset: 0x212C */
+  __IO uint32_t DRAMTMG12_SHADOW;                  /**< [SHADOW] SDRAM Timing Register 12, offset: 0x2130 */
+  __IO uint32_t DRAMTMG13_SHADOW;                  /**< [SHADOW] SDRAM Timing Register 13, offset: 0x2134 */
+  __IO uint32_t DRAMTMG14_SHADOW;                  /**< [SHADOW] SDRAM Timing Register 14, offset: 0x2138 */
+  __IO uint32_t DRAMTMG15_SHADOW;                  /**< [SHADOW] SDRAM Timing Register 15, offset: 0x213C */
+       uint8_t RESERVED_24[64];
+  __IO uint32_t ZQCTL0_SHADOW;                     /**< [SHADOW] ZQ Control Register 0, offset: 0x2180 */
+       uint8_t RESERVED_25[12];
+  __IO uint32_t DFITMG0_SHADOW;                    /**< [SHADOW] DFI Timing Register 0, offset: 0x2190 */
+  __IO uint32_t DFITMG1_SHADOW;                    /**< [SHADOW] DFI Timing Register 1, offset: 0x2194 */
+       uint8_t RESERVED_26[28];
+  __IO uint32_t DFITMG2_SHADOW;                    /**< [SHADOW] DFI Timing Register 2, offset: 0x21B4 */
+  __IO uint32_t DFITMG3_SHADOW;                    /**< [SHADOW] DFI Timing Register 3, offset: 0x21B8 */
+       uint8_t RESERVED_27[132];
+  __IO uint32_t ODTCFG_SHADOW;                     /**< [SHADOW] ODT Configuration Register, offset: 0x2240 */
+} DDRC_Type;
+/* ----------------------------------------------------------------------------
+   -- DDRC Register Masks
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup DDRC_Register_Masks DDRC Register Masks
+ * @{
+ */
+/*! @name MSTR - Master Register0 */
+/*! @{ */
+#define DDRC_MSTR_ddr3_MASK                      (0x1U)
+#define DDRC_MSTR_ddr3_SHIFT                     (0U)
+#define DDRC_MSTR_ddr3(x)                        (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ddr3_SHIFT)) & DDRC_MSTR_ddr3_MASK)
+#define DDRC_MSTR_lpddr2_MASK                    (0x4U)
+#define DDRC_MSTR_lpddr2_SHIFT                   (2U)
+#define DDRC_MSTR_lpddr2(x)                      (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr2_SHIFT)) & DDRC_MSTR_lpddr2_MASK)
+#define DDRC_MSTR_lpddr3_MASK                    (0x8U)
+#define DDRC_MSTR_lpddr3_SHIFT                   (3U)
+#define DDRC_MSTR_lpddr3(x)                      (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr3_SHIFT)) & DDRC_MSTR_lpddr3_MASK)
+#define DDRC_MSTR_ddr4_MASK                      (0x10U)
+#define DDRC_MSTR_ddr4_SHIFT                     (4U)
+#define DDRC_MSTR_ddr4(x)                        (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ddr4_SHIFT)) & DDRC_MSTR_ddr4_MASK)
+#define DDRC_MSTR_lpddr4_MASK                    (0x20U)
+#define DDRC_MSTR_lpddr4_SHIFT                   (5U)
+#define DDRC_MSTR_lpddr4(x)                      (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr4_SHIFT)) & DDRC_MSTR_lpddr4_MASK)
+#define DDRC_MSTR_burstchop_MASK                 (0x200U)
+#define DDRC_MSTR_burstchop_SHIFT                (9U)
+#define DDRC_MSTR_burstchop(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_burstchop_SHIFT)) & DDRC_MSTR_burstchop_MASK)
+#define DDRC_MSTR_en_2t_timing_mode_MASK         (0x400U)
+#define DDRC_MSTR_en_2t_timing_mode_SHIFT        (10U)
+#define DDRC_MSTR_en_2t_timing_mode(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_en_2t_timing_mode_SHIFT)) & DDRC_MSTR_en_2t_timing_mode_MASK)
+#define DDRC_MSTR_geardown_mode_MASK             (0x800U)
+#define DDRC_MSTR_geardown_mode_SHIFT            (11U)
+#define DDRC_MSTR_geardown_mode(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_geardown_mode_SHIFT)) & DDRC_MSTR_geardown_mode_MASK)
+#define DDRC_MSTR_data_bus_width_MASK            (0x3000U)
+#define DDRC_MSTR_data_bus_width_SHIFT           (12U)
+#define DDRC_MSTR_data_bus_width(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_data_bus_width_SHIFT)) & DDRC_MSTR_data_bus_width_MASK)
+#define DDRC_MSTR_dll_off_mode_MASK              (0x8000U)
+#define DDRC_MSTR_dll_off_mode_SHIFT             (15U)
+#define DDRC_MSTR_dll_off_mode(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_dll_off_mode_SHIFT)) & DDRC_MSTR_dll_off_mode_MASK)
+#define DDRC_MSTR_burst_rdwr_MASK                (0xF0000U)
+#define DDRC_MSTR_burst_rdwr_SHIFT               (16U)
+/*! burst_rdwr - SDRAM burst length used
+ *  0b0001..Burst length of 2 (only supported for mDDR)
+ *  0b0010..Burst length of 4
+ *  0b0100..Burst length of 8
+ *  0b1000..Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4)
+ */
+#define DDRC_MSTR_burst_rdwr(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_burst_rdwr_SHIFT)) & DDRC_MSTR_burst_rdwr_MASK)
+#define DDRC_MSTR_frequency_ratio_MASK           (0x400000U)
+#define DDRC_MSTR_frequency_ratio_SHIFT          (22U)
+/*! frequency_ratio - Selects the Frequency Ratio
+ *  0b0..1:2 Mode
+ *  0b1..1:1 Mode
+ */
+#define DDRC_MSTR_frequency_ratio(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_frequency_ratio_SHIFT)) & DDRC_MSTR_frequency_ratio_MASK)
+#define DDRC_MSTR_active_ranks_MASK              (0x3000000U)
+#define DDRC_MSTR_active_ranks_SHIFT             (24U)
+#define DDRC_MSTR_active_ranks(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_active_ranks_SHIFT)) & DDRC_MSTR_active_ranks_MASK)
+#define DDRC_MSTR_frequency_mode_MASK            (0x20000000U)
+#define DDRC_MSTR_frequency_mode_SHIFT           (29U)
+/*! frequency_mode - Choose which registers are used.
+ *  0b0..Original Registers
+ *  0b1..Shadow Registers
+ */
+#define DDRC_MSTR_frequency_mode(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_frequency_mode_SHIFT)) & DDRC_MSTR_frequency_mode_MASK)
+#define DDRC_MSTR_device_config_MASK             (0xC0000000U)
+#define DDRC_MSTR_device_config_SHIFT            (30U)
+/*! device_config - Indicates the configuration of the device used in the system.
+ *  0b00..x4 device
+ *  0b01..x8 device
+ *  0b10..x16 device
+ *  0b11..x32 device
+ */
+#define DDRC_MSTR_device_config(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_device_config_SHIFT)) & DDRC_MSTR_device_config_MASK)
+/*! @} */
+/*! @name STAT - Operating Mode Status Register */
+/*! @{ */
+#define DDRC_STAT_operating_mode_MASK            (0x7U)
+#define DDRC_STAT_operating_mode_SHIFT           (0U)
+#define DDRC_STAT_operating_mode(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_operating_mode_SHIFT)) & DDRC_STAT_operating_mode_MASK)
+#define DDRC_STAT_selfref_type_MASK              (0x30U)
+#define DDRC_STAT_selfref_type_SHIFT             (4U)
+/*! selfref_type - Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if
+ *    it was under Automatic Self Refresh control only or not.
+ *  0b00..SDRAM is not in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by
+ *        CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still in parity error window or retry is
+ *        in-progress.
+ *  0b11..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was caused by Automatic Self
+ *        Refresh only. If retry is enabled, this guarantees SRE command is executed correctly without parity error.
+ *  0b10..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was not caused solely under
+ *        Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software
+ *        (reg_ddrc_selfref_sw). If retry is enabled, this guarantees SRE command is executed correctly without parity
+ */
+#define DDRC_STAT_selfref_type(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_selfref_type_SHIFT)) & DDRC_STAT_selfref_type_MASK)
+#define DDRC_STAT_selfref_state_MASK             (0x300U)
+#define DDRC_STAT_selfref_state_SHIFT            (8U)
+/*! selfref_state - Self refresh state. This indicates self refresh or self refresh power down state
+ *    for LPDDR4. This register is used for frequency change and MRR/MRW access during self refresh.
+ *  0b00..SDRAM is not in Self Refresh.
+ *  0b01..Self refresh 1
+ *  0b10..Self refresh power down
+ *  0b11..Self refresh
+ */
+#define DDRC_STAT_selfref_state(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_selfref_state_SHIFT)) & DDRC_STAT_selfref_state_MASK)
+/*! @} */
+/*! @name MSTR1 - Operating Mode Status Register */
+/*! @{ */
+#define DDRC_MSTR1_rank_tmgreg_sel_MASK          (0x3U)
+#define DDRC_MSTR1_rank_tmgreg_sel_SHIFT         (0U)
+/*! rank_tmgreg_sel - rank_tmgreg_sel
+ *  0b00..USE DRAMTMGx registers for the rank
+ *  0b01..USE MRAMTMGx registers for the rank
+ */
+#define DDRC_MSTR1_rank_tmgreg_sel(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_rank_tmgreg_sel_SHIFT)) & DDRC_MSTR1_rank_tmgreg_sel_MASK)
+#define DDRC_MSTR1_alt_addrmap_en_MASK           (0x10000U)
+#define DDRC_MSTR1_alt_addrmap_en_SHIFT          (16U)
+/*! alt_addrmap_en - Enable Alternative Address Map
+ *  0b0..Disable Alternative Address Map
+ *  0b1..Enable Alternative Address Map
+ */
+#define DDRC_MSTR1_alt_addrmap_en(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_alt_addrmap_en_SHIFT)) & DDRC_MSTR1_alt_addrmap_en_MASK)
+/*! @} */
+/*! @name MRCTRL3 - Operating Mode Status Register */
+/*! @{ */
+#define DDRC_MRCTRL3_mr_rank_sel_MASK            (0x3U)
+#define DDRC_MRCTRL3_mr_rank_sel_SHIFT           (0U)
+#define DDRC_MRCTRL3_mr_rank_sel(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL3_mr_rank_sel_SHIFT)) & DDRC_MRCTRL3_mr_rank_sel_MASK)
+/*! @} */
+/*! @name MRCTRL0 - Mode Register Read/Write Control Register 0. */
+/*! @{ */
+#define DDRC_MRCTRL0_mr_type_MASK                (0x1U)
+#define DDRC_MRCTRL0_mr_type_SHIFT               (0U)
+/*! mr_type - Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4.
+ *  0b0..Write
+ *  0b1..Read
+ */
+#define DDRC_MRCTRL0_mr_type(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_type_SHIFT)) & DDRC_MRCTRL0_mr_type_MASK)
+#define DDRC_MRCTRL0_mpr_en_MASK                 (0x2U)
+#define DDRC_MRCTRL0_mpr_en_SHIFT                (1U)
+/*! mpr_en - Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4).
+ *  0b0..MRS
+ *  0b1..WR/RD for MPR
+ */
+#define DDRC_MRCTRL0_mpr_en(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mpr_en_SHIFT)) & DDRC_MRCTRL0_mpr_en_MASK)
+#define DDRC_MRCTRL0_pda_en_MASK                 (0x4U)
+#define DDRC_MRCTRL0_pda_en_SHIFT                (2U)
+/*! pda_en - Indicates whether the mode register operation is MRS in PDA mode or not. Note that when
+ *    pba_mode=1, PBA access is initiated instead of PDA access.
+ *  0b0..MRS
+ *  0b1..MRS in Per DRAM Addressability
+ */
+#define DDRC_MRCTRL0_pda_en(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_pda_en_SHIFT)) & DDRC_MRCTRL0_pda_en_MASK)
+#define DDRC_MRCTRL0_sw_init_int_MASK            (0x8U)
+#define DDRC_MRCTRL0_sw_init_int_SHIFT           (3U)
+/*! sw_init_int - Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before
+ *    automatic SDRAM initialization routine or not. For DDR4, this bit can be used to initialize the
+ *    DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit can be used to
+ *    program additional mode registers before automatic SDRAM initialization if necessary. In LPDDR4
+ *    independent channel mode, note that this must be programmed to both channels beforehand. Note that
+ *    this must be cleared to 0 after completing Software operation. Otherwise, SDRAM
+ *    initialization routine will not re-start.
+ *  0b0..Software intervention is not allowed
+ *  0b1..Software intervention is allowed
+ */
+#define DDRC_MRCTRL0_sw_init_int(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_sw_init_int_SHIFT)) & DDRC_MRCTRL0_sw_init_int_MASK)
+#define DDRC_MRCTRL0_mr_rank_MASK                (0x30U)
+#define DDRC_MRCTRL0_mr_rank_SHIFT               (4U)
+#define DDRC_MRCTRL0_mr_rank(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_rank_SHIFT)) & DDRC_MRCTRL0_mr_rank_MASK)
+#define DDRC_MRCTRL0_mr_addr_MASK                (0xF000U)
+#define DDRC_MRCTRL0_mr_addr_SHIFT               (12U)
+/*! mr_addr - Address of the mode register that is to be written to.
+ *  0b0000..MR0
+ *  0b0001..MR1
+ *  0b0010..MR2
+ *  0b0011..MR3
+ *  0b0100..MR4
+ *  0b0101..MR5
+ *  0b0110..MR6
+ *  0b0111..MR7
+ */
+#define DDRC_MRCTRL0_mr_addr(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_addr_SHIFT)) & DDRC_MRCTRL0_mr_addr_MASK)
+#define DDRC_MRCTRL0_pba_mode_MASK               (0x40000000U)
+#define DDRC_MRCTRL0_pba_mode_SHIFT              (30U)
+#define DDRC_MRCTRL0_pba_mode(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_pba_mode_SHIFT)) & DDRC_MRCTRL0_pba_mode_MASK)
+#define DDRC_MRCTRL0_mr_wr_MASK                  (0x80000000U)
+#define DDRC_MRCTRL0_mr_wr_SHIFT                 (31U)
+#define DDRC_MRCTRL0_mr_wr(x)                    (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_wr_SHIFT)) & DDRC_MRCTRL0_mr_wr_MASK)
+/*! @} */
+/*! @name MRCTRL1 - Mode Register Read/Write Control Register 1 */
+/*! @{ */
+#define DDRC_MRCTRL1_mr_data_MASK                (0x3FFFFU)
+#define DDRC_MRCTRL1_mr_data_SHIFT               (0U)
+#define DDRC_MRCTRL1_mr_data(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL1_mr_data_SHIFT)) & DDRC_MRCTRL1_mr_data_MASK)
+/*! @} */
+/*! @name MRSTAT - Mode Register Read/Write Status Register */
+/*! @{ */
+#define DDRC_MRSTAT_mr_wr_busy_MASK              (0x1U)
+#define DDRC_MRSTAT_mr_wr_busy_SHIFT             (0U)
+/*! mr_wr_busy - The SoC core may initiate a MR write operation only if this signal is low. This
+ *    signal goes high in the clock after the DDRC accepts the MRW/MRR request. It goes low when the
+ *    MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when
+ *    'MRSTAT.mr_wr_busy' is high.
+ *  0b0..Indicates that the SoC core can initiate a mode register write operation
+ *  0b1..Indicates that mode register write operation is in progress
+ */
+#define DDRC_MRSTAT_mr_wr_busy(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_mr_wr_busy_SHIFT)) & DDRC_MRSTAT_mr_wr_busy_MASK)
+#define DDRC_MRSTAT_pda_done_MASK                (0x100U)
+#define DDRC_MRSTAT_pda_done_SHIFT               (8U)
+/*! pda_done - The SoC core may initiate a MR write operation in PDA/PBA mode only if this signal is
+ *    low. This signal goes high when three consecutive MRS commands related to the PDA/PBA mode
+ *    are issued to the SDRAM. This signal goes low when MRCTRL0.pda_en becomes 0. Therefore, it is
+ *    recommended to write MRCTRL0.pda_en to 0 after this signal goes high in order to prepare to
+ *    perform PDA operation next time
+ *  0b0..Indicates that mode register write operation related to PDA/PBA is in progress or has not started yet.
+ *  0b1..Indicates that mode register write operation related to PDA/PBA has competed.
+ */
+#define DDRC_MRSTAT_pda_done(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_pda_done_SHIFT)) & DDRC_MRSTAT_pda_done_MASK)
+/*! @} */
+/*! @name MRCTRL2 - Mode Register Read/Write Control Register 2 */
+/*! @{ */
+#define DDRC_MRCTRL2_mr_device_sel_MASK          (0xFFFFFFFFU)
+#define DDRC_MRCTRL2_mr_device_sel_SHIFT         (0U)
+#define DDRC_MRCTRL2_mr_device_sel(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL2_mr_device_sel_SHIFT)) & DDRC_MRCTRL2_mr_device_sel_MASK)
+/*! @} */
+/*! @name DERATEEN - Temperature Derate Enable Register */
+/*! @{ */
+#define DDRC_DERATEEN_derate_enable_MASK         (0x1U)
+#define DDRC_DERATEEN_derate_enable_SHIFT        (0U)
+/*! derate_enable - Enables derating. Present only in designs configured to support
+ *    LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
+ *  0b0..Timing parameter derating is disabled
+ *  0b1..Timing parameter derating is enabled using MR4 read value.
+ */
+#define DDRC_DERATEEN_derate_enable(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_enable_SHIFT)) & DDRC_DERATEEN_derate_enable_MASK)
+#define DDRC_DERATEEN_derate_value_MASK          (0x2U)
+#define DDRC_DERATEEN_derate_value_SHIFT         (1U)
+/*! derate_value - Derate value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
+ *    Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a
+ *    core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this
+ *    register field should be set to 1; otherwise it should be set to 0.
+ *  0b0..Derating uses +1
+ *  0b1..Derating uses +2
+ */
+#define DDRC_DERATEEN_derate_value(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_value_SHIFT)) & DDRC_DERATEEN_derate_value_MASK)
+#define DDRC_DERATEEN_derate_byte_MASK           (0xF0U)
+#define DDRC_DERATEEN_derate_byte_SHIFT          (4U)
+#define DDRC_DERATEEN_derate_byte(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_byte_SHIFT)) & DDRC_DERATEEN_derate_byte_MASK)
+#define DDRC_DERATEEN_rc_derate_value_MASK       (0x300U)
+#define DDRC_DERATEEN_rc_derate_value_SHIFT      (8U)
+/*! rc_derate_value - Derate value of tRC for LPDDR4. Present only in designs configured to support
+ *    LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the
+ *    core_ddrc_core_clk period, and rounding up the next integer.
+ *  0b00..Derating uses +1
+ *  0b01..Derating uses +2
+ *  0b10..Derating uses +3
+ *  0b11..Derating uses +4
+ */
+#define DDRC_DERATEEN_rc_derate_value(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_rc_derate_value_SHIFT)) & DDRC_DERATEEN_rc_derate_value_MASK)
+/*! @} */
+/*! @name DERATEINT - Temperature Derate Interval Register */
+/*! @{ */
+#define DDRC_DERATEINT_mr4_read_interval_MASK    (0xFFFFFFFFU)
+#define DDRC_DERATEINT_mr4_read_interval_SHIFT   (0U)
+#define DDRC_DERATEINT_mr4_read_interval(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_mr4_read_interval_SHIFT)) & DDRC_DERATEINT_mr4_read_interval_MASK)
+/*! @} */
+/*! @name PWRCTL - Low Power Control Register */
+/*! @{ */
+#define DDRC_PWRCTL_selfref_en_MASK              (0x1U)
+#define DDRC_PWRCTL_selfref_en_SHIFT             (0U)
+#define DDRC_PWRCTL_selfref_en(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_selfref_en_SHIFT)) & DDRC_PWRCTL_selfref_en_MASK)
+#define DDRC_PWRCTL_powerdown_en_MASK            (0x2U)
+#define DDRC_PWRCTL_powerdown_en_SHIFT           (1U)
+#define DDRC_PWRCTL_powerdown_en(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_powerdown_en_SHIFT)) & DDRC_PWRCTL_powerdown_en_MASK)
+#define DDRC_PWRCTL_deeppowerdown_en_MASK        (0x4U)
+#define DDRC_PWRCTL_deeppowerdown_en_SHIFT       (2U)
+#define DDRC_PWRCTL_deeppowerdown_en(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_deeppowerdown_en_SHIFT)) & DDRC_PWRCTL_deeppowerdown_en_MASK)
+#define DDRC_PWRCTL_en_dfi_dram_clk_disable_MASK (0x8U)
+#define DDRC_PWRCTL_en_dfi_dram_clk_disable_SHIFT (3U)
+#define DDRC_PWRCTL_en_dfi_dram_clk_disable(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_en_dfi_dram_clk_disable_SHIFT)) & DDRC_PWRCTL_en_dfi_dram_clk_disable_MASK)
+#define DDRC_PWRCTL_mpsm_en_MASK                 (0x10U)
+#define DDRC_PWRCTL_mpsm_en_SHIFT                (4U)
+#define DDRC_PWRCTL_mpsm_en(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_mpsm_en_SHIFT)) & DDRC_PWRCTL_mpsm_en_MASK)
+#define DDRC_PWRCTL_selfref_sw_MASK              (0x20U)
+#define DDRC_PWRCTL_selfref_sw_SHIFT             (5U)
+/*! selfref_sw - A value of 1 to this register causes system to move to Self Refresh state
+ *    immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software
+ *    Entry/Exit to Self Refresh.
+ *  0b0..Software Exit from Self Refresh
+ *  0b1..Software Entry to Self Refresh
+ */
+#define DDRC_PWRCTL_selfref_sw(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_selfref_sw_SHIFT)) & DDRC_PWRCTL_selfref_sw_MASK)
+#define DDRC_PWRCTL_stay_in_selfref_MASK         (0x40U)
+#define DDRC_PWRCTL_stay_in_selfref_SHIFT        (6U)
+/*! stay_in_selfref - Self refresh state is an intermediate state to enter to Self refresh power
+ *    down state or exit Self refresh power down state for LPDDR4. This register controls transition
+ *    from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 0 - Allow
+ *    transition from Self refresh state
+ *  0b0..
+ *  0b1..
+ */
+#define DDRC_PWRCTL_stay_in_selfref(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_stay_in_selfref_SHIFT)) & DDRC_PWRCTL_stay_in_selfref_MASK)
+/*! @} */
+/*! @name PWRTMG - Low Power Timing Register */
+/*! @{ */
+#define DDRC_PWRTMG_powerdown_to_x32_MASK        (0x1FU)
+#define DDRC_PWRTMG_powerdown_to_x32_SHIFT       (0U)
+#define DDRC_PWRTMG_powerdown_to_x32(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_powerdown_to_x32_SHIFT)) & DDRC_PWRTMG_powerdown_to_x32_MASK)
+#define DDRC_PWRTMG_t_dpd_x4096_MASK             (0xFF00U)
+#define DDRC_PWRTMG_t_dpd_x4096_SHIFT            (8U)
+#define DDRC_PWRTMG_t_dpd_x4096(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_t_dpd_x4096_SHIFT)) & DDRC_PWRTMG_t_dpd_x4096_MASK)
+#define DDRC_PWRTMG_selfref_to_x32_MASK          (0xFF0000U)
+#define DDRC_PWRTMG_selfref_to_x32_SHIFT         (16U)
+#define DDRC_PWRTMG_selfref_to_x32(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_selfref_to_x32_SHIFT)) & DDRC_PWRTMG_selfref_to_x32_MASK)
+/*! @} */
+/*! @name HWLPCTL - Hardware Low Power Control Register */
+/*! @{ */
+#define DDRC_HWLPCTL_hw_lp_en_MASK               (0x1U)
+#define DDRC_HWLPCTL_hw_lp_en_SHIFT              (0U)
+#define DDRC_HWLPCTL_hw_lp_en(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_en_SHIFT)) & DDRC_HWLPCTL_hw_lp_en_MASK)
+#define DDRC_HWLPCTL_hw_lp_exit_idle_en_MASK     (0x2U)
+#define DDRC_HWLPCTL_hw_lp_exit_idle_en_SHIFT    (1U)
+#define DDRC_HWLPCTL_hw_lp_exit_idle_en(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_exit_idle_en_SHIFT)) & DDRC_HWLPCTL_hw_lp_exit_idle_en_MASK)
+#define DDRC_HWLPCTL_hw_lp_idle_x32_MASK         (0xFFF0000U)
+#define DDRC_HWLPCTL_hw_lp_idle_x32_SHIFT        (16U)
+#define DDRC_HWLPCTL_hw_lp_idle_x32(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_idle_x32_SHIFT)) & DDRC_HWLPCTL_hw_lp_idle_x32_MASK)
+/*! @} */
+/*! @name RFSHCTL0 - Refresh Control Register 0 */
+/*! @{ */
+#define DDRC_RFSHCTL0_per_bank_refresh_MASK      (0x4U)
+#define DDRC_RFSHCTL0_per_bank_refresh_SHIFT     (2U)
+/*! per_bank_refresh - Per bank refresh allows traffic to flow to other banks. Per bank refresh is
+ *    not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices.
+ *    Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
+ *  0b1..Per bank refresh
+ *  0b0..All bank refresh
+ */
+#define DDRC_RFSHCTL0_per_bank_refresh(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_per_bank_refresh_SHIFT)) & DDRC_RFSHCTL0_per_bank_refresh_MASK)
+#define DDRC_RFSHCTL0_refresh_burst_MASK         (0x1F0U)
+#define DDRC_RFSHCTL0_refresh_burst_SHIFT        (4U)
+#define DDRC_RFSHCTL0_refresh_burst(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_burst_SHIFT)) & DDRC_RFSHCTL0_refresh_burst_MASK)
+#define DDRC_RFSHCTL0_refresh_to_x32_MASK        (0x1F000U)
+#define DDRC_RFSHCTL0_refresh_to_x32_SHIFT       (12U)
+#define DDRC_RFSHCTL0_refresh_to_x32(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_to_x32_SHIFT)) & DDRC_RFSHCTL0_refresh_to_x32_MASK)
+#define DDRC_RFSHCTL0_refresh_margin_MASK        (0xF00000U)
+#define DDRC_RFSHCTL0_refresh_margin_SHIFT       (20U)
+#define DDRC_RFSHCTL0_refresh_margin(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_margin_SHIFT)) & DDRC_RFSHCTL0_refresh_margin_MASK)
+/*! @} */
+/*! @name RFSHCTL1 - Refresh Control Register 1 */
+/*! @{ */
+#define DDRC_RFSHCTL1_refresh_timer0_start_value_x32_MASK (0xFFFU)
+#define DDRC_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT (0U)
+#define DDRC_RFSHCTL1_refresh_timer0_start_value_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT)) & DDRC_RFSHCTL1_refresh_timer0_start_value_x32_MASK)
+#define DDRC_RFSHCTL1_refresh_timer1_start_value_x32_MASK (0xFFF0000U)
+#define DDRC_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT (16U)
+#define DDRC_RFSHCTL1_refresh_timer1_start_value_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT)) & DDRC_RFSHCTL1_refresh_timer1_start_value_x32_MASK)
+/*! @} */
+/*! @name RFSHCTL3 - Refresh Control Register 3 */
+/*! @{ */
+#define DDRC_RFSHCTL3_dis_auto_refresh_MASK      (0x1U)
+#define DDRC_RFSHCTL3_dis_auto_refresh_SHIFT     (0U)
+#define DDRC_RFSHCTL3_dis_auto_refresh(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_dis_auto_refresh_SHIFT)) & DDRC_RFSHCTL3_dis_auto_refresh_MASK)
+#define DDRC_RFSHCTL3_refresh_update_level_MASK  (0x2U)
+#define DDRC_RFSHCTL3_refresh_update_level_SHIFT (1U)
+#define DDRC_RFSHCTL3_refresh_update_level(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_refresh_update_level_SHIFT)) & DDRC_RFSHCTL3_refresh_update_level_MASK)
+#define DDRC_RFSHCTL3_refresh_mode_MASK          (0x70U)
+#define DDRC_RFSHCTL3_refresh_mode_SHIFT         (4U)
+#define DDRC_RFSHCTL3_refresh_mode(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_refresh_mode_SHIFT)) & DDRC_RFSHCTL3_refresh_mode_MASK)
+/*! @} */
+/*! @name RFSHTMG - Refresh Timing Register */
+/*! @{ */
+#define DDRC_RFSHTMG_t_rfc_min_MASK              (0x3FFU)
+#define DDRC_RFSHTMG_t_rfc_min_SHIFT             (0U)
+#define DDRC_RFSHTMG_t_rfc_min(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_t_rfc_min_SHIFT)) & DDRC_RFSHTMG_t_rfc_min_MASK)
+#define DDRC_RFSHTMG_lpddr3_trefbw_en_MASK       (0x8000U)
+#define DDRC_RFSHTMG_lpddr3_trefbw_en_SHIFT      (15U)
+#define DDRC_RFSHTMG_lpddr3_trefbw_en(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_lpddr3_trefbw_en_SHIFT)) & DDRC_RFSHTMG_lpddr3_trefbw_en_MASK)
+#define DDRC_RFSHTMG_t_rfc_nom_x32_MASK          (0xFFF0000U)
+#define DDRC_RFSHTMG_t_rfc_nom_x32_SHIFT         (16U)
+#define DDRC_RFSHTMG_t_rfc_nom_x32(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_t_rfc_nom_x32_SHIFT)) & DDRC_RFSHTMG_t_rfc_nom_x32_MASK)
+/*! @} */
+/*! @name INIT0 - SDRAM Initialization Register 0 */
+/*! @{ */
+#define DDRC_INIT0_pre_cke_x1024_MASK            (0xFFFU)
+#define DDRC_INIT0_pre_cke_x1024_SHIFT           (0U)
+#define DDRC_INIT0_pre_cke_x1024(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_pre_cke_x1024_SHIFT)) & DDRC_INIT0_pre_cke_x1024_MASK)
+#define DDRC_INIT0_post_cke_x1024_MASK           (0x3FF0000U)
+#define DDRC_INIT0_post_cke_x1024_SHIFT          (16U)
+#define DDRC_INIT0_post_cke_x1024(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_post_cke_x1024_SHIFT)) & DDRC_INIT0_post_cke_x1024_MASK)
+#define DDRC_INIT0_skip_dram_init_MASK           (0xC0000000U)
+#define DDRC_INIT0_skip_dram_init_SHIFT          (30U)
+/*! skip_dram_init - If lower bit is enabled the SDRAM initialization routine is skipped. The upper
+ *    bit decides what state the controller starts up in when reset is removed - 00 - SDRAM
+ *    Intialization routine is run after power-up - 01 - SDRAM Initialization routine is skipped after
+ *    power-up. Controller starts up in Normal Mode - 11 - SDRAM Initialization routine is skipped after
+ *    power-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Initialization routine is run
+ *    after power-up.
+ *  0b00..SDRAM Initialization routine is run after power-up
+ *  0b01..SDRAM Initialization routine is skipped after power-up
+ *  0b10..SDRAM Initialization routine is run after power-up
+ *  0b11..SDRAM Initialization routine is skipped after power-up
+ */
+#define DDRC_INIT0_skip_dram_init(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_skip_dram_init_SHIFT)) & DDRC_INIT0_skip_dram_init_MASK)
+/*! @} */
+/*! @name INIT1 - SDRAM Initialization Register 1 */
+/*! @{ */
+#define DDRC_INIT1_pre_ocd_x32_MASK              (0xFU)
+#define DDRC_INIT1_pre_ocd_x32_SHIFT             (0U)
+#define DDRC_INIT1_pre_ocd_x32(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_pre_ocd_x32_SHIFT)) & DDRC_INIT1_pre_ocd_x32_MASK)
+#define DDRC_INIT1_dram_rstn_x1024_MASK          (0x1FF0000U)
+#define DDRC_INIT1_dram_rstn_x1024_SHIFT         (16U)
+#define DDRC_INIT1_dram_rstn_x1024(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_dram_rstn_x1024_SHIFT)) & DDRC_INIT1_dram_rstn_x1024_MASK)
+/*! @} */
+/*! @name INIT2 - SDRAM Initialization Register 2 */
+/*! @{ */
+#define DDRC_INIT2_min_stable_clock_x1_MASK      (0xFU)
+#define DDRC_INIT2_min_stable_clock_x1_SHIFT     (0U)
+#define DDRC_INIT2_min_stable_clock_x1(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_min_stable_clock_x1_SHIFT)) & DDRC_INIT2_min_stable_clock_x1_MASK)
+#define DDRC_INIT2_idle_after_reset_x32_MASK     (0xFF00U)
+#define DDRC_INIT2_idle_after_reset_x32_SHIFT    (8U)
+#define DDRC_INIT2_idle_after_reset_x32(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_idle_after_reset_x32_SHIFT)) & DDRC_INIT2_idle_after_reset_x32_MASK)
+/*! @} */
+/*! @name INIT3 - SDRAM Initialization Register 3 */
+/*! @{ */
+#define DDRC_INIT3_emr_MASK                      (0xFFFFU)
+#define DDRC_INIT3_emr_SHIFT                     (0U)
+#define DDRC_INIT3_emr(x)                        (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_emr_SHIFT)) & DDRC_INIT3_emr_MASK)
+#define DDRC_INIT3_mr_MASK                       (0xFFFF0000U)
+#define DDRC_INIT3_mr_SHIFT                      (16U)
+#define DDRC_INIT3_mr(x)                         (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_mr_SHIFT)) & DDRC_INIT3_mr_MASK)
+/*! @} */
+/*! @name INIT4 - SDRAM Initialization Register 4 */
+/*! @{ */
+#define DDRC_INIT4_emr3_MASK                     (0xFFFFU)
+#define DDRC_INIT4_emr3_SHIFT                    (0U)
+#define DDRC_INIT4_emr3(x)                       (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_emr3_SHIFT)) & DDRC_INIT4_emr3_MASK)
+#define DDRC_INIT4_emr2_MASK                     (0xFFFF0000U)
+#define DDRC_INIT4_emr2_SHIFT                    (16U)
+#define DDRC_INIT4_emr2(x)                       (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_emr2_SHIFT)) & DDRC_INIT4_emr2_MASK)
+/*! @} */
+/*! @name INIT5 - SDRAM Initialization Register 5 */
+/*! @{ */
+#define DDRC_INIT5_max_auto_init_x1024_MASK      (0x3FFU)
+#define DDRC_INIT5_max_auto_init_x1024_SHIFT     (0U)
+#define DDRC_INIT5_max_auto_init_x1024(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_max_auto_init_x1024_SHIFT)) & DDRC_INIT5_max_auto_init_x1024_MASK)
+#define DDRC_INIT5_dev_zqinit_x32_MASK           (0xFF0000U)
+#define DDRC_INIT5_dev_zqinit_x32_SHIFT          (16U)
+#define DDRC_INIT5_dev_zqinit_x32(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_dev_zqinit_x32_SHIFT)) & DDRC_INIT5_dev_zqinit_x32_MASK)
+/*! @} */
+/*! @name INIT6 - SDRAM Initialization Register 6 */
+/*! @{ */
+#define DDRC_INIT6_mr5_MASK                      (0xFFFFU)
+#define DDRC_INIT6_mr5_SHIFT                     (0U)
+#define DDRC_INIT6_mr5(x)                        (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_mr5_SHIFT)) & DDRC_INIT6_mr5_MASK)
+#define DDRC_INIT6_mr4_MASK                      (0xFFFF0000U)
+#define DDRC_INIT6_mr4_SHIFT                     (16U)
+#define DDRC_INIT6_mr4(x)                        (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_mr4_SHIFT)) & DDRC_INIT6_mr4_MASK)
+/*! @} */
+/*! @name INIT7 - SDRAM Initialization Register 7 */
+/*! @{ */
+#define DDRC_INIT7_mr6_MASK                      (0xFFFF0000U)
+#define DDRC_INIT7_mr6_SHIFT                     (16U)
+#define DDRC_INIT7_mr6(x)                        (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_mr6_SHIFT)) & DDRC_INIT7_mr6_MASK)
+/*! @} */
+/*! @name DIMMCTL - DIMM Control Register */
+/*! @{ */
+#define DDRC_DIMMCTL_dimm_stagger_cs_en_MASK     (0x1U)
+#define DDRC_DIMMCTL_dimm_stagger_cs_en_SHIFT    (0U)
+/*! dimm_stagger_cs_en - Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and
+ *    LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs.
+ *    Even if this bit is set it does not take care of software driven MR commands (via
+ *    MRCTRL0/MRCTRL1), where software is responsible to send them to separate ranks as appropriate.
+ *  0b0..Do not stagger accesses
+ *  0b1..For(non-DDR4) Send all commands to even and odd ranks separately; For(DDR4) Send MRS commands to each ranks separately
+ */
+#define DDRC_DIMMCTL_dimm_stagger_cs_en(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_stagger_cs_en_SHIFT)) & DDRC_DIMMCTL_dimm_stagger_cs_en_MASK)
+#define DDRC_DIMMCTL_dimm_addr_mirr_en_MASK      (0x2U)
+#define DDRC_DIMMCTL_dimm_addr_mirr_en_SHIFT     (1U)
+/*! dimm_addr_mirr_en - Address Mirroring Enable (for multi-rank UDIMM implementations and
+ *    multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address
+ *    mirroring for odd ranks, which means that the following address, bank address and bank group
+ *    bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for
+ *    the DDR4. Setting this bit ensures that, for mode register accesses during the automatic
+ *    initialization routine, these bits are swapped within the DDRC to compensate for this
+ *    UDIMM/RDIMM/LRDIMM swapping. In addition to the automatic initialization routine, in case of DDR4
+ *    UDIMM/RDIMM/LRDIMM, they are swapped during the automatic MRS access to enable/disable of a particular
+ *    DDR4 feature. Note: This has no effect on the address of any other memory accesses, or of
+ *    software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4
+ *    SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0
+ *    because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1.
+ *  0b0..Do not implement address mirroring
+ *  0b1..For odd ranks, implement address mirroring for MRS commands to during initialization and for any
+ *       automatic DDR4 MRS commands (to be used if UDIMM/RDIMM/LRDIMM implements address mirroring)
+ */
+#define DDRC_DIMMCTL_dimm_addr_mirr_en(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_addr_mirr_en_SHIFT)) & DDRC_DIMMCTL_dimm_addr_mirr_en_MASK)
+#define DDRC_DIMMCTL_dimm_output_inv_en_MASK     (0x4U)
+#define DDRC_DIMMCTL_dimm_output_inv_en_SHIFT    (2U)
+/*! dimm_output_inv_en - Output Inversion Enable (for DDR4 RDIMM/LRDIMM implementations only). DDR4
+ *    RDIMM/LRDIMM implements the Output Inversion feature by default, which means that the
+ *    following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13,
+ *    A17, BA0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the
+ *    DDRC during the automatic initialization routine and enabling of a particular DDR4 feature,
+ *    separate A-side and B-side mode register accesses are generated. For B-side mode register
+ *    accesses, these bits are inverted within the DDRC to compensate for this RDIMM/LRDIMM inversion. It
+ *    is recommended to set this bit always, if using DDR4 RDIMMs/LRDIMMs. Note: This has no effect
+ *    on the address of any other memory accesses, or of software-driven mode register accesses.
+ *  0b0..Do not implement output inversion for B-side DRAMs.
+ *  0b1..Implement output inversion for B-side DRAMs.
+ */
+#define DDRC_DIMMCTL_dimm_output_inv_en(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_output_inv_en_SHIFT)) & DDRC_DIMMCTL_dimm_output_inv_en_MASK)
+#define DDRC_DIMMCTL_mrs_a17_en_MASK             (0x8U)
+#define DDRC_DIMMCTL_mrs_a17_en_SHIFT            (3U)
+/*! mrs_a17_en - Enable for A17 bit of MRS command. A17 bit of the mode register address is
+ *    specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs
+ *    which do not have A17 are attached and the Output Inversion are enabled, this must be set to
+ *    0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on
+ *    the address of any other memory accesses, or of software-driven mode register accesses.
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define DDRC_DIMMCTL_mrs_a17_en(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_mrs_a17_en_SHIFT)) & DDRC_DIMMCTL_mrs_a17_en_MASK)
+#define DDRC_DIMMCTL_mrs_bg1_en_MASK             (0x10U)
+#define DDRC_DIMMCTL_mrs_bg1_en_SHIFT            (4U)
+/*! mrs_bg1_en - Enable for BG1 bit of MRS command. BG1 bit of the mode register address is
+ *    specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs
+ *    which do not have BG1 are attached and both the CA parity and the Output Inversion are
+ *    enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note:
+ *    This has no effect on the address of any other memory accesses, or of software-driven mode
+ *    register accesses. If address mirroring is enabled, this is applied to BG1 of even ranks and BG0
+ *    of odd ranks.
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define DDRC_DIMMCTL_mrs_bg1_en(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_mrs_bg1_en_SHIFT)) & DDRC_DIMMCTL_mrs_bg1_en_MASK)
+#define DDRC_DIMMCTL_dimm_dis_bg_mirroring_MASK  (0x20U)
+#define DDRC_DIMMCTL_dimm_dis_bg_mirroring_SHIFT (5U)
+/*! dimm_dis_bg_mirroring - Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and
+ *    BG1 are NOT swapped even if Address Mirroring is enabled. This will be required for DDR4 DIMMs
+ *    with x16 devices.
+ *  0b0..BG0 and BG1 are swapped if address mirroring is enabled.
+ *  0b1..BG0 and BG1 are NOT swapped.
+ */
+#define DDRC_DIMMCTL_dimm_dis_bg_mirroring(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_dis_bg_mirroring_SHIFT)) & DDRC_DIMMCTL_dimm_dis_bg_mirroring_MASK)
+#define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_MASK   (0x40U)
+#define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT  (6U)
+#define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT)) & DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_MASK)
+/*! @} */
+/*! @name RANKCTL - Rank Control Register */
+/*! @{ */
+#define DDRC_RANKCTL_max_rank_rd_MASK            (0xFU)
+#define DDRC_RANKCTL_max_rank_rd_SHIFT           (0U)
+#define DDRC_RANKCTL_max_rank_rd(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_max_rank_rd_SHIFT)) & DDRC_RANKCTL_max_rank_rd_MASK)
+#define DDRC_RANKCTL_diff_rank_rd_gap_MASK       (0xF0U)
+#define DDRC_RANKCTL_diff_rank_rd_gap_SHIFT      (4U)
+#define DDRC_RANKCTL_diff_rank_rd_gap(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_diff_rank_rd_gap_SHIFT)) & DDRC_RANKCTL_diff_rank_rd_gap_MASK)
+#define DDRC_RANKCTL_diff_rank_wr_gap_MASK       (0xF00U)
+#define DDRC_RANKCTL_diff_rank_wr_gap_SHIFT      (8U)
+#define DDRC_RANKCTL_diff_rank_wr_gap(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_diff_rank_wr_gap_SHIFT)) & DDRC_RANKCTL_diff_rank_wr_gap_MASK)
+/*! @} */
+/*! @name DRAMTMG0 - SDRAM Timing Register 0 */
+/*! @{ */
+#define DDRC_DRAMTMG0_t_ras_min_MASK             (0x3FU)
+#define DDRC_DRAMTMG0_t_ras_min_SHIFT            (0U)
+#define DDRC_DRAMTMG0_t_ras_min(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_ras_min_SHIFT)) & DDRC_DRAMTMG0_t_ras_min_MASK)
+#define DDRC_DRAMTMG0_t_ras_max_MASK             (0x7F00U)
+#define DDRC_DRAMTMG0_t_ras_max_SHIFT            (8U)
+#define DDRC_DRAMTMG0_t_ras_max(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_ras_max_SHIFT)) & DDRC_DRAMTMG0_t_ras_max_MASK)
+#define DDRC_DRAMTMG0_t_faw_MASK                 (0x3F0000U)
+#define DDRC_DRAMTMG0_t_faw_SHIFT                (16U)
+#define DDRC_DRAMTMG0_t_faw(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_faw_SHIFT)) & DDRC_DRAMTMG0_t_faw_MASK)
+#define DDRC_DRAMTMG0_wr2pre_MASK                (0x7F000000U)
+#define DDRC_DRAMTMG0_wr2pre_SHIFT               (24U)
+#define DDRC_DRAMTMG0_wr2pre(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_wr2pre_SHIFT)) & DDRC_DRAMTMG0_wr2pre_MASK)
+/*! @} */
+/*! @name DRAMTMG1 - SDRAM Timing Register 1 */
+/*! @{ */
+#define DDRC_DRAMTMG1_t_rc_MASK                  (0x7FU)
+#define DDRC_DRAMTMG1_t_rc_SHIFT                 (0U)
+#define DDRC_DRAMTMG1_t_rc(x)                    (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_t_rc_SHIFT)) & DDRC_DRAMTMG1_t_rc_MASK)
+#define DDRC_DRAMTMG1_rd2pre_MASK                (0x3F00U)
+#define DDRC_DRAMTMG1_rd2pre_SHIFT               (8U)
+#define DDRC_DRAMTMG1_rd2pre(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_rd2pre_SHIFT)) & DDRC_DRAMTMG1_rd2pre_MASK)
+#define DDRC_DRAMTMG1_t_xp_MASK                  (0x1F0000U)
+#define DDRC_DRAMTMG1_t_xp_SHIFT                 (16U)
+#define DDRC_DRAMTMG1_t_xp(x)                    (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_t_xp_SHIFT)) & DDRC_DRAMTMG1_t_xp_MASK)
+/*! @} */
+/*! @name DRAMTMG2 - SDRAM Timing Register 2 */
+/*! @{ */
+#define DDRC_DRAMTMG2_wr2rd_MASK                 (0x3FU)
+#define DDRC_DRAMTMG2_wr2rd_SHIFT                (0U)
+#define DDRC_DRAMTMG2_wr2rd(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_wr2rd_SHIFT)) & DDRC_DRAMTMG2_wr2rd_MASK)
+#define DDRC_DRAMTMG2_rd2wr_MASK                 (0x3F00U)
+#define DDRC_DRAMTMG2_rd2wr_SHIFT                (8U)
+#define DDRC_DRAMTMG2_rd2wr(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_rd2wr_SHIFT)) & DDRC_DRAMTMG2_rd2wr_MASK)
+#define DDRC_DRAMTMG2_read_latency_MASK          (0x3F0000U)
+#define DDRC_DRAMTMG2_read_latency_SHIFT         (16U)
+#define DDRC_DRAMTMG2_read_latency(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_read_latency_SHIFT)) & DDRC_DRAMTMG2_read_latency_MASK)
+#define DDRC_DRAMTMG2_write_latency_MASK         (0x3F000000U)
+#define DDRC_DRAMTMG2_write_latency_SHIFT        (24U)
+#define DDRC_DRAMTMG2_write_latency(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_write_latency_SHIFT)) & DDRC_DRAMTMG2_write_latency_MASK)
+/*! @} */
+/*! @name DRAMTMG3 - SDRAM Timing Register 3 */
+/*! @{ */
+#define DDRC_DRAMTMG3_t_mod_MASK                 (0x3FFU)
+#define DDRC_DRAMTMG3_t_mod_SHIFT                (0U)
+#define DDRC_DRAMTMG3_t_mod(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mod_SHIFT)) & DDRC_DRAMTMG3_t_mod_MASK)
+#define DDRC_DRAMTMG3_t_mrd_MASK                 (0x3F000U)
+#define DDRC_DRAMTMG3_t_mrd_SHIFT                (12U)
+#define DDRC_DRAMTMG3_t_mrd(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mrd_SHIFT)) & DDRC_DRAMTMG3_t_mrd_MASK)
+#define DDRC_DRAMTMG3_t_mrw_MASK                 (0x3FF00000U)
+#define DDRC_DRAMTMG3_t_mrw_SHIFT                (20U)
+#define DDRC_DRAMTMG3_t_mrw(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mrw_SHIFT)) & DDRC_DRAMTMG3_t_mrw_MASK)
+/*! @} */
+/*! @name DRAMTMG4 - SDRAM Timing Register 4 */
+/*! @{ */
+#define DDRC_DRAMTMG4_t_rp_MASK                  (0x1FU)
+#define DDRC_DRAMTMG4_t_rp_SHIFT                 (0U)
+#define DDRC_DRAMTMG4_t_rp(x)                    (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rp_SHIFT)) & DDRC_DRAMTMG4_t_rp_MASK)
+#define DDRC_DRAMTMG4_t_rrd_MASK                 (0xF00U)
+#define DDRC_DRAMTMG4_t_rrd_SHIFT                (8U)
+#define DDRC_DRAMTMG4_t_rrd(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rrd_SHIFT)) & DDRC_DRAMTMG4_t_rrd_MASK)
+#define DDRC_DRAMTMG4_t_ccd_MASK                 (0xF0000U)
+#define DDRC_DRAMTMG4_t_ccd_SHIFT                (16U)
+#define DDRC_DRAMTMG4_t_ccd(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_ccd_SHIFT)) & DDRC_DRAMTMG4_t_ccd_MASK)
+#define DDRC_DRAMTMG4_t_rcd_MASK                 (0x1F000000U)
+#define DDRC_DRAMTMG4_t_rcd_SHIFT                (24U)
+#define DDRC_DRAMTMG4_t_rcd(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rcd_SHIFT)) & DDRC_DRAMTMG4_t_rcd_MASK)
+/*! @} */
+/*! @name DRAMTMG5 - SDRAM Timing Register 5 */
+/*! @{ */
+#define DDRC_DRAMTMG5_t_cke_MASK                 (0x1FU)
+#define DDRC_DRAMTMG5_t_cke_SHIFT                (0U)
+#define DDRC_DRAMTMG5_t_cke(x)                   (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cke_SHIFT)) & DDRC_DRAMTMG5_t_cke_MASK)
+#define DDRC_DRAMTMG5_t_ckesr_MASK               (0x3F00U)
+#define DDRC_DRAMTMG5_t_ckesr_SHIFT              (8U)
+#define DDRC_DRAMTMG5_t_ckesr(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_ckesr_SHIFT)) & DDRC_DRAMTMG5_t_ckesr_MASK)
+#define DDRC_DRAMTMG5_t_cksre_MASK               (0xF0000U)
+#define DDRC_DRAMTMG5_t_cksre_SHIFT              (16U)
+#define DDRC_DRAMTMG5_t_cksre(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cksre_SHIFT)) & DDRC_DRAMTMG5_t_cksre_MASK)
+#define DDRC_DRAMTMG5_t_cksrx_MASK               (0xF000000U)
+#define DDRC_DRAMTMG5_t_cksrx_SHIFT              (24U)
+#define DDRC_DRAMTMG5_t_cksrx(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cksrx_SHIFT)) & DDRC_DRAMTMG5_t_cksrx_MASK)
+/*! @} */
+/*! @name DRAMTMG6 - SDRAM Timing Register 6 */
+/*! @{ */
+#define DDRC_DRAMTMG6_t_ckcsx_MASK               (0xFU)
+#define DDRC_DRAMTMG6_t_ckcsx_SHIFT              (0U)
+#define DDRC_DRAMTMG6_t_ckcsx(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckcsx_SHIFT)) & DDRC_DRAMTMG6_t_ckcsx_MASK)
+#define DDRC_DRAMTMG6_t_ckdpdx_MASK              (0xF0000U)
+#define DDRC_DRAMTMG6_t_ckdpdx_SHIFT             (16U)
+#define DDRC_DRAMTMG6_t_ckdpdx(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckdpdx_SHIFT)) & DDRC_DRAMTMG6_t_ckdpdx_MASK)
+#define DDRC_DRAMTMG6_t_ckdpde_MASK              (0xF000000U)
+#define DDRC_DRAMTMG6_t_ckdpde_SHIFT             (24U)
+#define DDRC_DRAMTMG6_t_ckdpde(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckdpde_SHIFT)) & DDRC_DRAMTMG6_t_ckdpde_MASK)
+/*! @} */
+/*! @name DRAMTMG7 - SDRAM Timing Register 7 */
+/*! @{ */
+#define DDRC_DRAMTMG7_t_ckpdx_MASK               (0xFU)
+#define DDRC_DRAMTMG7_t_ckpdx_SHIFT              (0U)
+#define DDRC_DRAMTMG7_t_ckpdx(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_t_ckpdx_SHIFT)) & DDRC_DRAMTMG7_t_ckpdx_MASK)
+#define DDRC_DRAMTMG7_t_ckpde_MASK               (0xF00U)
+#define DDRC_DRAMTMG7_t_ckpde_SHIFT              (8U)
+#define DDRC_DRAMTMG7_t_ckpde(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_t_ckpde_SHIFT)) & DDRC_DRAMTMG7_t_ckpde_MASK)
+/*! @} */
+/*! @name DRAMTMG8 - SDRAM Timing Register 8 */
+/*! @{ */
+#define DDRC_DRAMTMG8_t_xs_x32_MASK              (0x7FU)
+#define DDRC_DRAMTMG8_t_xs_x32_SHIFT             (0U)
+#define DDRC_DRAMTMG8_t_xs_x32(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_x32_MASK)
+#define DDRC_DRAMTMG8_t_xs_dll_x32_MASK          (0x7F00U)
+#define DDRC_DRAMTMG8_t_xs_dll_x32_SHIFT         (8U)
+#define DDRC_DRAMTMG8_t_xs_dll_x32(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_dll_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_dll_x32_MASK)
+#define DDRC_DRAMTMG8_t_xs_abort_x32_MASK        (0x7F0000U)
+#define DDRC_DRAMTMG8_t_xs_abort_x32_SHIFT       (16U)
+#define DDRC_DRAMTMG8_t_xs_abort_x32(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_abort_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_abort_x32_MASK)
+#define DDRC_DRAMTMG8_t_xs_fast_x32_MASK         (0x7F000000U)
+#define DDRC_DRAMTMG8_t_xs_fast_x32_SHIFT        (24U)
+#define DDRC_DRAMTMG8_t_xs_fast_x32(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_fast_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_fast_x32_MASK)
+/*! @} */
+/*! @name DRAMTMG9 - SDRAM Timing Register 9 */
+/*! @{ */
+#define DDRC_DRAMTMG9_wr2rd_s_MASK               (0x3FU)
+#define DDRC_DRAMTMG9_wr2rd_s_SHIFT              (0U)
+#define DDRC_DRAMTMG9_wr2rd_s(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_wr2rd_s_SHIFT)) & DDRC_DRAMTMG9_wr2rd_s_MASK)
+#define DDRC_DRAMTMG9_t_rrd_s_MASK               (0xF00U)
+#define DDRC_DRAMTMG9_t_rrd_s_SHIFT              (8U)
+#define DDRC_DRAMTMG9_t_rrd_s(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_t_rrd_s_SHIFT)) & DDRC_DRAMTMG9_t_rrd_s_MASK)
+#define DDRC_DRAMTMG9_t_ccd_s_MASK               (0x70000U)
+#define DDRC_DRAMTMG9_t_ccd_s_SHIFT              (16U)
+#define DDRC_DRAMTMG9_t_ccd_s(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_t_ccd_s_SHIFT)) & DDRC_DRAMTMG9_t_ccd_s_MASK)
+#define DDRC_DRAMTMG9_ddr4_wr_preamble_MASK      (0x40000000U)
+#define DDRC_DRAMTMG9_ddr4_wr_preamble_SHIFT     (30U)
+#define DDRC_DRAMTMG9_ddr4_wr_preamble(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_ddr4_wr_preamble_SHIFT)) & DDRC_DRAMTMG9_ddr4_wr_preamble_MASK)
+/*! @} */
+/*! @name DRAMTMG10 - SDRAM Timing Register 10 */
+/*! @{ */
+#define DDRC_DRAMTMG10_t_gear_hold_MASK          (0x3U)
+#define DDRC_DRAMTMG10_t_gear_hold_SHIFT         (0U)
+#define DDRC_DRAMTMG10_t_gear_hold(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_gear_hold_SHIFT)) & DDRC_DRAMTMG10_t_gear_hold_MASK)
+#define DDRC_DRAMTMG10_t_gear_setup_MASK         (0xCU)
+#define DDRC_DRAMTMG10_t_gear_setup_SHIFT        (2U)
+#define DDRC_DRAMTMG10_t_gear_setup(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_gear_setup_SHIFT)) & DDRC_DRAMTMG10_t_gear_setup_MASK)
+#define DDRC_DRAMTMG10_t_cmd_gear_MASK           (0x1F00U)
+#define DDRC_DRAMTMG10_t_cmd_gear_SHIFT          (8U)
+#define DDRC_DRAMTMG10_t_cmd_gear(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_cmd_gear_SHIFT)) & DDRC_DRAMTMG10_t_cmd_gear_MASK)
+#define DDRC_DRAMTMG10_t_sync_gear_MASK          (0x1F0000U)
+#define DDRC_DRAMTMG10_t_sync_gear_SHIFT         (16U)
+#define DDRC_DRAMTMG10_t_sync_gear(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_sync_gear_SHIFT)) & DDRC_DRAMTMG10_t_sync_gear_MASK)
+/*! @} */
+/*! @name DRAMTMG11 - SDRAM Timing Register 11 */
+/*! @{ */
+#define DDRC_DRAMTMG11_t_ckmpe_MASK              (0x1FU)
+#define DDRC_DRAMTMG11_t_ckmpe_SHIFT             (0U)
+#define DDRC_DRAMTMG11_t_ckmpe(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_ckmpe_SHIFT)) & DDRC_DRAMTMG11_t_ckmpe_MASK)
+#define DDRC_DRAMTMG11_t_mpx_s_MASK              (0x300U)
+#define DDRC_DRAMTMG11_t_mpx_s_SHIFT             (8U)
+#define DDRC_DRAMTMG11_t_mpx_s(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_mpx_s_SHIFT)) & DDRC_DRAMTMG11_t_mpx_s_MASK)
+#define DDRC_DRAMTMG11_t_mpx_lh_MASK             (0x1F0000U)
+#define DDRC_DRAMTMG11_t_mpx_lh_SHIFT            (16U)
+#define DDRC_DRAMTMG11_t_mpx_lh(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_mpx_lh_SHIFT)) & DDRC_DRAMTMG11_t_mpx_lh_MASK)
+#define DDRC_DRAMTMG11_post_mpsm_gap_x32_MASK    (0x7F000000U)
+#define DDRC_DRAMTMG11_post_mpsm_gap_x32_SHIFT   (24U)
+#define DDRC_DRAMTMG11_post_mpsm_gap_x32(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_post_mpsm_gap_x32_SHIFT)) & DDRC_DRAMTMG11_post_mpsm_gap_x32_MASK)
+/*! @} */
+/*! @name DRAMTMG12 - SDRAM Timing Register 12 */
+/*! @{ */
+#define DDRC_DRAMTMG12_t_mrd_pda_MASK            (0x1FU)
+#define DDRC_DRAMTMG12_t_mrd_pda_SHIFT           (0U)
+#define DDRC_DRAMTMG12_t_mrd_pda(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_mrd_pda_SHIFT)) & DDRC_DRAMTMG12_t_mrd_pda_MASK)
+#define DDRC_DRAMTMG12_t_ckehcmd_MASK            (0xF00U)
+#define DDRC_DRAMTMG12_t_ckehcmd_SHIFT           (8U)
+#define DDRC_DRAMTMG12_t_ckehcmd(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_ckehcmd_SHIFT)) & DDRC_DRAMTMG12_t_ckehcmd_MASK)
+#define DDRC_DRAMTMG12_t_cmdcke_MASK             (0x30000U)
+#define DDRC_DRAMTMG12_t_cmdcke_SHIFT            (16U)
+#define DDRC_DRAMTMG12_t_cmdcke(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_cmdcke_SHIFT)) & DDRC_DRAMTMG12_t_cmdcke_MASK)
+/*! @} */
+/*! @name DRAMTMG13 - SDRAM Timing Register 13 */
+/*! @{ */
+#define DDRC_DRAMTMG13_t_ppd_MASK                (0x7U)
+#define DDRC_DRAMTMG13_t_ppd_SHIFT               (0U)
+#define DDRC_DRAMTMG13_t_ppd(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_t_ppd_SHIFT)) & DDRC_DRAMTMG13_t_ppd_MASK)
+#define DDRC_DRAMTMG13_t_ccd_mw_MASK             (0x3F0000U)
+#define DDRC_DRAMTMG13_t_ccd_mw_SHIFT            (16U)
+#define DDRC_DRAMTMG13_t_ccd_mw(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_t_ccd_mw_SHIFT)) & DDRC_DRAMTMG13_t_ccd_mw_MASK)
+#define DDRC_DRAMTMG13_odtloff_MASK              (0x7F000000U)
+#define DDRC_DRAMTMG13_odtloff_SHIFT             (24U)
+#define DDRC_DRAMTMG13_odtloff(x)                (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_odtloff_SHIFT)) & DDRC_DRAMTMG13_odtloff_MASK)
+/*! @} */
+/*! @name DRAMTMG14 - SDRAM Timing Register 14 */
+/*! @{ */
+#define DDRC_DRAMTMG14_t_xsr_MASK                (0xFFFU)
+#define DDRC_DRAMTMG14_t_xsr_SHIFT               (0U)
+#define DDRC_DRAMTMG14_t_xsr(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_t_xsr_SHIFT)) & DDRC_DRAMTMG14_t_xsr_MASK)
+/*! @} */
+/*! @name DRAMTMG15 - SDRAM Timing Register 15 */
+/*! @{ */
+#define DDRC_DRAMTMG15_t_stab_x32_MASK           (0xFFU)
+#define DDRC_DRAMTMG15_t_stab_x32_SHIFT          (0U)
+#define DDRC_DRAMTMG15_t_stab_x32(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_t_stab_x32_SHIFT)) & DDRC_DRAMTMG15_t_stab_x32_MASK)
+#define DDRC_DRAMTMG15_en_dfi_lp_t_stab_MASK     (0x80000000U)
+#define DDRC_DRAMTMG15_en_dfi_lp_t_stab_SHIFT    (31U)
+/*! en_dfi_lp_t_stab - Enable DFI tSTAB
+ *  0b0..Disable using tSTAB when exiting DFI LP
+ *  0b1..Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power.
+ */
+#define DDRC_DRAMTMG15_en_dfi_lp_t_stab(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_en_dfi_lp_t_stab_SHIFT)) & DDRC_DRAMTMG15_en_dfi_lp_t_stab_MASK)
+/*! @} */
+/*! @name ZQCTL0 - ZQ Control Register 0 */
+/*! @{ */
+#define DDRC_ZQCTL0_t_zq_short_nop_MASK          (0x3FFU)
+#define DDRC_ZQCTL0_t_zq_short_nop_SHIFT         (0U)
+#define DDRC_ZQCTL0_t_zq_short_nop(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_t_zq_short_nop_SHIFT)) & DDRC_ZQCTL0_t_zq_short_nop_MASK)
+#define DDRC_ZQCTL0_t_zq_long_nop_MASK           (0x7FF0000U)
+#define DDRC_ZQCTL0_t_zq_long_nop_SHIFT          (16U)
+#define DDRC_ZQCTL0_t_zq_long_nop(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_t_zq_long_nop_SHIFT)) & DDRC_ZQCTL0_t_zq_long_nop_MASK)
+#define DDRC_ZQCTL0_dis_mpsmx_zqcl_MASK          (0x10000000U)
+#define DDRC_ZQCTL0_dis_mpsmx_zqcl_SHIFT         (28U)
+/*! dis_mpsmx_zqcl - Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC
+ *    configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting
+ *    MPSM mode.
+ *  0b0..Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode.
+ *       This is only present for designs supporting DDR4 devices.
+ *  0b1..Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode.
+ */
+#define DDRC_ZQCTL0_dis_mpsmx_zqcl(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_mpsmx_zqcl_SHIFT)) & DDRC_ZQCTL0_dis_mpsmx_zqcl_MASK)
+#define DDRC_ZQCTL0_zq_resistor_shared_MASK      (0x20000000U)
+#define DDRC_ZQCTL0_zq_resistor_shared_SHIFT     (29U)
+/*! zq_resistor_shared - ZQ resistor sharing
+ *  0b0..ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+ *  0b1..Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are
+ *       sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that
+ *       commands to different ranks do not overlap.
+ */
+#define DDRC_ZQCTL0_zq_resistor_shared(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_zq_resistor_shared_SHIFT)) & DDRC_ZQCTL0_zq_resistor_shared_MASK)
+#define DDRC_ZQCTL0_dis_srx_zqcl_MASK            (0x40000000U)
+#define DDRC_ZQCTL0_dis_srx_zqcl_SHIFT           (30U)
+/*! dis_srx_zqcl - Disable ZQCL/MPC
+ *  0b0..Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable
+ *       when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting
+ *       DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+ *  0b1..Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable
+ *       when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode.
+ */
+#define DDRC_ZQCTL0_dis_srx_zqcl(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_srx_zqcl_SHIFT)) & DDRC_ZQCTL0_dis_srx_zqcl_MASK)
+#define DDRC_ZQCTL0_dis_auto_zq_MASK             (0x80000000U)
+#define DDRC_ZQCTL0_dis_auto_zq_SHIFT            (31U)
+/*! dis_auto_zq - Disable Auto ZQCS/MPC
+ *  0b0..Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024.
+ *  0b1..Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used
+ *       instead to issue ZQ calibration request from APB module.
+ */
+#define DDRC_ZQCTL0_dis_auto_zq(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_auto_zq_SHIFT)) & DDRC_ZQCTL0_dis_auto_zq_MASK)
+/*! @} */
+/*! @name ZQCTL1 - ZQ Control Register 1 */
+/*! @{ */
+#define DDRC_ZQCTL1_t_zq_short_interval_x1024_MASK (0xFFFFFU)
+#define DDRC_ZQCTL1_t_zq_short_interval_x1024_SHIFT (0U)
+#define DDRC_ZQCTL1_t_zq_short_interval_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_t_zq_short_interval_x1024_SHIFT)) & DDRC_ZQCTL1_t_zq_short_interval_x1024_MASK)
+#define DDRC_ZQCTL1_t_zq_reset_nop_MASK          (0x3FF00000U)
+#define DDRC_ZQCTL1_t_zq_reset_nop_SHIFT         (20U)
+#define DDRC_ZQCTL1_t_zq_reset_nop(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_t_zq_reset_nop_SHIFT)) & DDRC_ZQCTL1_t_zq_reset_nop_MASK)
+/*! @} */
+/*! @name ZQCTL2 - ZQ Control Register 2 */
+/*! @{ */
+#define DDRC_ZQCTL2_zq_reset_MASK                (0x1U)
+#define DDRC_ZQCTL2_zq_reset_SHIFT               (0U)
+#define DDRC_ZQCTL2_zq_reset(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL2_zq_reset_SHIFT)) & DDRC_ZQCTL2_zq_reset_MASK)
+/*! @} */
+/*! @name ZQSTAT - ZQ Status Register */
+/*! @{ */
+#define DDRC_ZQSTAT_zq_reset_busy_MASK           (0x1U)
+#define DDRC_ZQSTAT_zq_reset_busy_SHIFT          (0U)
+/*! zq_reset_busy - SoC core may initiate a ZQ Reset operation only if this signal is low. This
+ *    signal goes high in the clock after the DDRC accepts the ZQ Reset request. It goes low when the ZQ
+ *    Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended
+ *    not to perform ZQ Reset commands when this signal is high.
+ *  0b0..Indicates that the SoC core can initiate a ZQ Reset operation
+ *  0b1..Indicates that ZQ Reset operation is in progress
+ */
+#define DDRC_ZQSTAT_zq_reset_busy(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_ZQSTAT_zq_reset_busy_SHIFT)) & DDRC_ZQSTAT_zq_reset_busy_MASK)
+/*! @} */
+/*! @name DFITMG0 - DFI Timing Register 0 */
+/*! @{ */
+#define DDRC_DFITMG0_dfi_tphy_wrlat_MASK         (0x3FU)
+#define DDRC_DFITMG0_dfi_tphy_wrlat_SHIFT        (0U)
+#define DDRC_DFITMG0_dfi_tphy_wrlat(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_tphy_wrlat_SHIFT)) & DDRC_DFITMG0_dfi_tphy_wrlat_MASK)
+#define DDRC_DFITMG0_dfi_tphy_wrdata_MASK        (0x3F00U)
+#define DDRC_DFITMG0_dfi_tphy_wrdata_SHIFT       (8U)
+#define DDRC_DFITMG0_dfi_tphy_wrdata(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_tphy_wrdata_SHIFT)) & DDRC_DFITMG0_dfi_tphy_wrdata_MASK)
+#define DDRC_DFITMG0_dfi_wrdata_use_sdr_MASK     (0x8000U)
+#define DDRC_DFITMG0_dfi_wrdata_use_sdr_SHIFT    (15U)
+#define DDRC_DFITMG0_dfi_wrdata_use_sdr(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_wrdata_use_sdr_SHIFT)) & DDRC_DFITMG0_dfi_wrdata_use_sdr_MASK)
+#define DDRC_DFITMG0_dfi_t_rddata_en_MASK        (0x7F0000U)
+#define DDRC_DFITMG0_dfi_t_rddata_en_SHIFT       (16U)
+#define DDRC_DFITMG0_dfi_t_rddata_en(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_t_rddata_en_SHIFT)) & DDRC_DFITMG0_dfi_t_rddata_en_MASK)
+#define DDRC_DFITMG0_dfi_rddata_use_sdr_MASK     (0x800000U)
+#define DDRC_DFITMG0_dfi_rddata_use_sdr_SHIFT    (23U)
+#define DDRC_DFITMG0_dfi_rddata_use_sdr(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_rddata_use_sdr_SHIFT)) & DDRC_DFITMG0_dfi_rddata_use_sdr_MASK)
+#define DDRC_DFITMG0_dfi_t_ctrl_delay_MASK       (0x1F000000U)
+#define DDRC_DFITMG0_dfi_t_ctrl_delay_SHIFT      (24U)
+#define DDRC_DFITMG0_dfi_t_ctrl_delay(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_t_ctrl_delay_SHIFT)) & DDRC_DFITMG0_dfi_t_ctrl_delay_MASK)
+/*! @} */
+/*! @name DFITMG1 - DFI Timing Register 1 */
+/*! @{ */
+#define DDRC_DFITMG1_dfi_t_dram_clk_enable_MASK  (0x1FU)
+#define DDRC_DFITMG1_dfi_t_dram_clk_enable_SHIFT (0U)
+#define DDRC_DFITMG1_dfi_t_dram_clk_enable(x)    (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_dram_clk_enable_SHIFT)) & DDRC_DFITMG1_dfi_t_dram_clk_enable_MASK)
+#define DDRC_DFITMG1_dfi_t_dram_clk_disable_MASK (0x1F00U)
+#define DDRC_DFITMG1_dfi_t_dram_clk_disable_SHIFT (8U)
+#define DDRC_DFITMG1_dfi_t_dram_clk_disable(x)   (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_dram_clk_disable_SHIFT)) & DDRC_DFITMG1_dfi_t_dram_clk_disable_MASK)
+#define DDRC_DFITMG1_dfi_t_wrdata_delay_MASK     (0x1F0000U)
+#define DDRC_DFITMG1_dfi_t_wrdata_delay_SHIFT    (16U)
+#define DDRC_DFITMG1_dfi_t_wrdata_delay(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_wrdata_delay_SHIFT)) & DDRC_DFITMG1_dfi_t_wrdata_delay_MASK)
+#define DDRC_DFITMG1_dfi_t_parin_lat_MASK        (0x3000000U)
+#define DDRC_DFITMG1_dfi_t_parin_lat_SHIFT       (24U)
+#define DDRC_DFITMG1_dfi_t_parin_lat(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_parin_lat_SHIFT)) & DDRC_DFITMG1_dfi_t_parin_lat_MASK)
+#define DDRC_DFITMG1_dfi_t_cmd_lat_MASK          (0xF0000000U)
+#define DDRC_DFITMG1_dfi_t_cmd_lat_SHIFT         (28U)
+#define DDRC_DFITMG1_dfi_t_cmd_lat(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_cmd_lat_SHIFT)) & DDRC_DFITMG1_dfi_t_cmd_lat_MASK)
+/*! @} */
+/*! @name DFILPCFG0 - DFI Low Power Configuration Register 0 */
+/*! @{ */
+#define DDRC_DFILPCFG0_dfi_lp_en_pd_MASK         (0x1U)
+#define DDRC_DFILPCFG0_dfi_lp_en_pd_SHIFT        (0U)
+#define DDRC_DFILPCFG0_dfi_lp_en_pd(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_pd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_pd_MASK)
+#define DDRC_DFILPCFG0_dfi_lp_wakeup_pd_MASK     (0xF0U)
+#define DDRC_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT    (4U)
+/*! dfi_lp_wakeup_pd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down
+ *    mode is entered. Determines the DFI's tlp_wakeup time:
+ *  0b0000..16 cycles
+ *  0b0001..32 cycles
+ *  0b0010..64 cycles
+ *  0b0011..128 cycles
+ *  0b0100..256 cycles
+ *  0b0101..512 cycles
+ *  0b0110..1024 cycles
+ *  0b0111..2048 cycles
+ *  0b1000..4096 cycles
+ *  0b1001..8192 cycles
+ *  0b1010..16384 cycles
+ *  0b1011..32768 cycles
+ *  0b1100..65536 cycles
+ *  0b1101..131072 cycles
+ *  0b1110..262144 cycles
+ *  0b1111..Unlimited cycles
+ */
+#define DDRC_DFILPCFG0_dfi_lp_wakeup_pd(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_pd_MASK)
+#define DDRC_DFILPCFG0_dfi_lp_en_sr_MASK         (0x100U)
+#define DDRC_DFILPCFG0_dfi_lp_en_sr_SHIFT        (8U)
+/*! dfi_lp_en_sr - Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define DDRC_DFILPCFG0_dfi_lp_en_sr(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_sr_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_sr_MASK)
+#define DDRC_DFILPCFG0_dfi_lp_wakeup_sr_MASK     (0xF000U)
+#define DDRC_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT    (12U)
+/*! dfi_lp_wakeup_sr - Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh
+ *    mode is entered. Determines the DFI's tlp_wakeup time:
+ *  0b0000..16 cycles
+ *  0b0001..32 cycles
+ *  0b0010..64 cycles
+ *  0b0011..128 cycles
+ *  0b0100..256 cycles
+ *  0b0101..512 cycles
+ *  0b0110..1024 cycles
+ *  0b0111..2048 cycles
+ *  0b1000..4096 cycles
+ *  0b1001..8192 cycles
+ *  0b1010..16384 cycles
+ *  0b1011..32768 cycles
+ *  0b1100..65536 cycles
+ *  0b1101..131072 cycles
+ *  0b1110..262144 cycles
+ *  0b1111..Unlimited cycles
+ */
+#define DDRC_DFILPCFG0_dfi_lp_wakeup_sr(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_sr_MASK)
+#define DDRC_DFILPCFG0_dfi_lp_en_dpd_MASK        (0x10000U)
+#define DDRC_DFILPCFG0_dfi_lp_en_dpd_SHIFT       (16U)
+#define DDRC_DFILPCFG0_dfi_lp_en_dpd(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_dpd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_dpd_MASK)
+#define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_MASK    (0xF00000U)
+#define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT   (20U)
+/*! dfi_lp_wakeup_dpd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power
+ *    Down mode is entered. Determines the DFI's tlp_wakeup time: This is only present for designs
+ *    supporting mDDR or LPDDR2/LPDDR3 devices.
+ *  0b0000..16 cycles
+ *  0b0001..32 cycles
+ *  0b0010..64 cycles
+ *  0b0011..128 cycles
+ *  0b0100..256 cycles
+ *  0b0101..512 cycles
+ *  0b0110..1024 cycles
+ *  0b0111..2048 cycles
+ *  0b1000..4096 cycles
+ *  0b1001..8192 cycles
+ *  0b1010..16384 cycles
+ *  0b1011..32768 cycles
+ *  0b1100..65536 cycles
+ *  0b1101..131072 cycles
+ *  0b1110..262144 cycles
+ *  0b1111..Unlimited cycles
+ */
+#define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd(x)      (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_MASK)
+#define DDRC_DFILPCFG0_dfi_tlp_resp_MASK         (0x1F000000U)
+#define DDRC_DFILPCFG0_dfi_tlp_resp_SHIFT        (24U)
+#define DDRC_DFILPCFG0_dfi_tlp_resp(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_tlp_resp_SHIFT)) & DDRC_DFILPCFG0_dfi_tlp_resp_MASK)
+/*! @} */
+/*! @name DFILPCFG1 - DFI Low Power Configuration Register 1 */
+/*! @{ */
+#define DDRC_DFILPCFG1_dfi_lp_en_mpsm_MASK       (0x1U)
+#define DDRC_DFILPCFG1_dfi_lp_en_mpsm_SHIFT      (0U)
+#define DDRC_DFILPCFG1_dfi_lp_en_mpsm(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_dfi_lp_en_mpsm_SHIFT)) & DDRC_DFILPCFG1_dfi_lp_en_mpsm_MASK)
+#define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK   (0xF0U)
+#define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT  (4U)
+/*! dfi_lp_wakeup_mpsm - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum
+ *    Power Saving Mode is entered. Determines the DFI's tlp_wakeup time:
+ *  0b0000..16 cycles
+ *  0b0001..32 cycles
+ *  0b0010..64 cycles
+ *  0b0011..128 cycles
+ *  0b0100..256 cycles
+ *  0b0101..512 cycles
+ *  0b0110..1024 cycles
+ *  0b0111..2048 cycles
+ *  0b1000..4096 cycles
+ *  0b1001..8192 cycles
+ *  0b1010..16384 cycles
+ *  0b1011..32768 cycles
+ *  0b1100..65536 cycles
+ *  0b1101..131072 cycles
+ *  0b1110..262144 cycles
+ *  0b1111..Unlimited cycles
+ */
+#define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT)) & DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK)
+/*! @} */
+/*! @name DFIUPD0 - DFI Update Register 0 */
+/*! @{ */
+#define DDRC_DFIUPD0_dfi_t_ctrlup_min_MASK       (0x3FFU)
+#define DDRC_DFIUPD0_dfi_t_ctrlup_min_SHIFT      (0U)
+#define DDRC_DFIUPD0_dfi_t_ctrlup_min(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dfi_t_ctrlup_min_SHIFT)) & DDRC_DFIUPD0_dfi_t_ctrlup_min_MASK)
+#define DDRC_DFIUPD0_dfi_t_ctrlup_max_MASK       (0x3FF0000U)
+#define DDRC_DFIUPD0_dfi_t_ctrlup_max_SHIFT      (16U)
+#define DDRC_DFIUPD0_dfi_t_ctrlup_max(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dfi_t_ctrlup_max_SHIFT)) & DDRC_DFIUPD0_dfi_t_ctrlup_max_MASK)
+#define DDRC_DFIUPD0_ctrlupd_pre_srx_MASK        (0x20000000U)
+#define DDRC_DFIUPD0_ctrlupd_pre_srx_SHIFT       (29U)
+/*! ctrlupd_pre_srx - Selects dfi_ctrlupd_req requirements at SRX: - 0 : send ctrlupd after SRX - 1
+ *    : send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact,
+ *    because no dfi_ctrlupd_req will be issued when SRX.
+ *  0b0..send ctrlupd after SRX
+ *  0b1..send ctrlupd before SRX
+ */
+#define DDRC_DFIUPD0_ctrlupd_pre_srx(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_ctrlupd_pre_srx_SHIFT)) & DDRC_DFIUPD0_ctrlupd_pre_srx_MASK)
+#define DDRC_DFIUPD0_dis_auto_ctrlupd_srx_MASK   (0x40000000U)
+#define DDRC_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT  (30U)
+/*! dis_auto_ctrlupd_srx - Auto ctrlupd request generation
+ *  0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC at self-refresh exit.
+ *  0b0..DDRC issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on DFIUPD0.ctrlupd_pre_srx.
+ */
+#define DDRC_DFIUPD0_dis_auto_ctrlupd_srx(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT)) & DDRC_DFIUPD0_dis_auto_ctrlupd_srx_MASK)
+#define DDRC_DFIUPD0_dis_auto_ctrlupd_MASK       (0x80000000U)
+#define DDRC_DFIUPD0_dis_auto_ctrlupd_SHIFT      (31U)
+/*! dis_auto_ctrlupd - automatic dfi_ctrlupd_req generation by the DDRC
+ *  0b0..DDRC issues dfi_ctrlupd_req periodically.
+ *  0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC. The core must issue the dfi_ctrlupd_req
+ *       signal using register reg_ddrc_ctrlupd.
+ */
+#define DDRC_DFIUPD0_dis_auto_ctrlupd(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dis_auto_ctrlupd_SHIFT)) & DDRC_DFIUPD0_dis_auto_ctrlupd_MASK)
+/*! @} */
+/*! @name DFIUPD1 - DFI Update Register 1 */
+/*! @{ */
+#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK (0xFFU)
+#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT (0U)
+#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT)) & DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK)
+#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK (0xFF0000U)
+#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT (16U)
+#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT)) & DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK)
+/*! @} */
+/*! @name DFIUPD2 - DFI Update Register 2 */
+/*! @{ */
+#define DDRC_DFIUPD2_dfi_phyupd_en_MASK          (0x80000000U)
+#define DDRC_DFIUPD2_dfi_phyupd_en_SHIFT         (31U)
+/*! dfi_phyupd_en - Enables the support for acknowledging PHY-initiated updates:
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define DDRC_DFIUPD2_dfi_phyupd_en(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD2_dfi_phyupd_en_SHIFT)) & DDRC_DFIUPD2_dfi_phyupd_en_MASK)
+/*! @} */
+/*! @name DFIMISC - DFI Miscellaneous Control Register */
+/*! @{ */
+#define DDRC_DFIMISC_dfi_init_complete_en_MASK   (0x1U)
+#define DDRC_DFIMISC_dfi_init_complete_en_SHIFT  (0U)
+#define DDRC_DFIMISC_dfi_init_complete_en(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_init_complete_en_SHIFT)) & DDRC_DFIMISC_dfi_init_complete_en_MASK)
+#define DDRC_DFIMISC_phy_dbi_mode_MASK           (0x2U)
+#define DDRC_DFIMISC_phy_dbi_mode_SHIFT          (1U)
+/*! phy_dbi_mode - DBI implemented in DDRC or PHY. Present only in designs configured to support DDR4 and LPDDR4.
+ *  0b0..DDRC implements DBI functionality.
+ *  0b1..PHY implements DBI functionality.
+ */
+#define DDRC_DFIMISC_phy_dbi_mode(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_phy_dbi_mode_SHIFT)) & DDRC_DFIMISC_phy_dbi_mode_MASK)
+#define DDRC_DFIMISC_dfi_data_cs_polarity_MASK   (0x4U)
+#define DDRC_DFIMISC_dfi_data_cs_polarity_SHIFT  (2U)
+/*! dfi_data_cs_polarity - Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals.
+ *  0b0..Signals are active low
+ *  0b1..Signals are active high
+ */
+#define DDRC_DFIMISC_dfi_data_cs_polarity(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_data_cs_polarity_SHIFT)) & DDRC_DFIMISC_dfi_data_cs_polarity_MASK)
+#define DDRC_DFIMISC_ctl_idle_en_MASK            (0x10U)
+#define DDRC_DFIMISC_ctl_idle_en_SHIFT           (4U)
+#define DDRC_DFIMISC_ctl_idle_en(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_ctl_idle_en_SHIFT)) & DDRC_DFIMISC_ctl_idle_en_MASK)
+#define DDRC_DFIMISC_dfi_init_start_MASK         (0x20U)
+#define DDRC_DFIMISC_dfi_init_start_SHIFT        (5U)
+#define DDRC_DFIMISC_dfi_init_start(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_init_start_SHIFT)) & DDRC_DFIMISC_dfi_init_start_MASK)
+#define DDRC_DFIMISC_dfi_frequency_MASK          (0x1F00U)
+#define DDRC_DFIMISC_dfi_frequency_SHIFT         (8U)
+#define DDRC_DFIMISC_dfi_frequency(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_frequency_SHIFT)) & DDRC_DFIMISC_dfi_frequency_MASK)
+/*! @} */
+/*! @name DFITMG2 - DFI Timing Register 2 */
+/*! @{ */
+#define DDRC_DFITMG2_dfi_tphy_wrcslat_MASK       (0x3FU)
+#define DDRC_DFITMG2_dfi_tphy_wrcslat_SHIFT      (0U)
+#define DDRC_DFITMG2_dfi_tphy_wrcslat(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_dfi_tphy_wrcslat_SHIFT)) & DDRC_DFITMG2_dfi_tphy_wrcslat_MASK)
+#define DDRC_DFITMG2_dfi_tphy_rdcslat_MASK       (0x7F00U)
+#define DDRC_DFITMG2_dfi_tphy_rdcslat_SHIFT      (8U)
+#define DDRC_DFITMG2_dfi_tphy_rdcslat(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_dfi_tphy_rdcslat_SHIFT)) & DDRC_DFITMG2_dfi_tphy_rdcslat_MASK)
+/*! @} */
+/*! @name DFITMG3 - DFI Timing Register 3 */
+/*! @{ */
+#define DDRC_DFITMG3_dfi_t_geardown_delay_MASK   (0x1FU)
+#define DDRC_DFITMG3_dfi_t_geardown_delay_SHIFT  (0U)
+#define DDRC_DFITMG3_dfi_t_geardown_delay(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_dfi_t_geardown_delay_SHIFT)) & DDRC_DFITMG3_dfi_t_geardown_delay_MASK)
+/*! @} */
+/*! @name DFISTAT - DFI Status Register */
+/*! @{ */
+#define DDRC_DFISTAT_dfi_init_complete_MASK      (0x1U)
+#define DDRC_DFISTAT_dfi_init_complete_SHIFT     (0U)
+#define DDRC_DFISTAT_dfi_init_complete(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_dfi_init_complete_SHIFT)) & DDRC_DFISTAT_dfi_init_complete_MASK)
+#define DDRC_DFISTAT_dfi_lp_ack_MASK             (0x2U)
+#define DDRC_DFISTAT_dfi_lp_ack_SHIFT            (1U)
+#define DDRC_DFISTAT_dfi_lp_ack(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_dfi_lp_ack_SHIFT)) & DDRC_DFISTAT_dfi_lp_ack_MASK)
+/*! @} */
+/*! @name DBICTL - DM/DBI Control Register */
+/*! @{ */
+#define DDRC_DBICTL_dm_en_MASK                   (0x1U)
+#define DDRC_DBICTL_dm_en_SHIFT                  (0U)
+/*! dm_en - DM enable signal in DDRC. This signal must be set the same logical value as DRAM's mode
+ *    register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal
+ *    must be set to 0. - LPDDR4: Set this to inverted value of MR13[5] which is opposite polarity
+ *    from this signal
+ *  0b0..DM is disabled
+ *  0b1..DM is enabled
+ */
+#define DDRC_DBICTL_dm_en(x)                     (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_dm_en_SHIFT)) & DDRC_DBICTL_dm_en_MASK)
+#define DDRC_DBICTL_wr_dbi_en_MASK               (0x2U)
+#define DDRC_DBICTL_wr_dbi_en_SHIFT              (1U)
+/*! wr_dbi_en - This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A11.
+ *    When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]
+ *  0b0..Write DBI is disabled
+ *  0b1..Write DBI is enabled.
+ */
+#define DDRC_DBICTL_wr_dbi_en(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_wr_dbi_en_SHIFT)) & DDRC_DBICTL_wr_dbi_en_MASK)
+#define DDRC_DBICTL_rd_dbi_en_MASK               (0x4U)
+#define DDRC_DBICTL_rd_dbi_en_SHIFT              (2U)
+#define DDRC_DBICTL_rd_dbi_en(x)                 (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_rd_dbi_en_SHIFT)) & DDRC_DBICTL_rd_dbi_en_MASK)
+/*! @} */
+/*! @name ADDRMAP0 - Address Map Register 0 */
+/*! @{ */
+#define DDRC_ADDRMAP0_addrmap_cs_bit0_MASK       (0x1FU)
+#define DDRC_ADDRMAP0_addrmap_cs_bit0_SHIFT      (0U)
+#define DDRC_ADDRMAP0_addrmap_cs_bit0(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP0_addrmap_cs_bit0_SHIFT)) & DDRC_ADDRMAP0_addrmap_cs_bit0_MASK)
+/*! @} */
+/*! @name ADDRMAP1 - Address Map Register 1 */
+/*! @{ */
+#define DDRC_ADDRMAP1_addrmap_bank_b0_MASK       (0x1FU)
+#define DDRC_ADDRMAP1_addrmap_bank_b0_SHIFT      (0U)
+#define DDRC_ADDRMAP1_addrmap_bank_b0(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b0_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b0_MASK)
+#define DDRC_ADDRMAP1_addrmap_bank_b1_MASK       (0x1F00U)
+#define DDRC_ADDRMAP1_addrmap_bank_b1_SHIFT      (8U)
+#define DDRC_ADDRMAP1_addrmap_bank_b1(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b1_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b1_MASK)
+#define DDRC_ADDRMAP1_addrmap_bank_b2_MASK       (0x1F0000U)
+#define DDRC_ADDRMAP1_addrmap_bank_b2_SHIFT      (16U)
+#define DDRC_ADDRMAP1_addrmap_bank_b2(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b2_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b2_MASK)
+/*! @} */
+/*! @name ADDRMAP2 - Address Map Register 2 */
+/*! @{ */
+#define DDRC_ADDRMAP2_addrmap_col_b2_MASK        (0xFU)
+#define DDRC_ADDRMAP2_addrmap_col_b2_SHIFT       (0U)
+#define DDRC_ADDRMAP2_addrmap_col_b2(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b2_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b2_MASK)
+#define DDRC_ADDRMAP2_addrmap_col_b3_MASK        (0xF00U)
+#define DDRC_ADDRMAP2_addrmap_col_b3_SHIFT       (8U)
+#define DDRC_ADDRMAP2_addrmap_col_b3(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b3_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b3_MASK)
+#define DDRC_ADDRMAP2_addrmap_col_b4_MASK        (0xF0000U)
+#define DDRC_ADDRMAP2_addrmap_col_b4_SHIFT       (16U)
+#define DDRC_ADDRMAP2_addrmap_col_b4(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b4_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b4_MASK)
+#define DDRC_ADDRMAP2_addrmap_col_b5_MASK        (0xF000000U)
+#define DDRC_ADDRMAP2_addrmap_col_b5_SHIFT       (24U)
+#define DDRC_ADDRMAP2_addrmap_col_b5(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b5_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b5_MASK)
+/*! @} */
+/*! @name ADDRMAP3 - Address Map Register 3 */
+/*! @{ */
+#define DDRC_ADDRMAP3_addrmap_col_b6_MASK        (0xFU)
+#define DDRC_ADDRMAP3_addrmap_col_b6_SHIFT       (0U)
+#define DDRC_ADDRMAP3_addrmap_col_b6(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b6_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b6_MASK)
+#define DDRC_ADDRMAP3_addrmap_col_b7_MASK        (0xF00U)
+#define DDRC_ADDRMAP3_addrmap_col_b7_SHIFT       (8U)
+#define DDRC_ADDRMAP3_addrmap_col_b7(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b7_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b7_MASK)
+#define DDRC_ADDRMAP3_addrmap_col_b8_MASK        (0xF0000U)
+#define DDRC_ADDRMAP3_addrmap_col_b8_SHIFT       (16U)
+#define DDRC_ADDRMAP3_addrmap_col_b8(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b8_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b8_MASK)
+#define DDRC_ADDRMAP3_addrmap_col_b9_MASK        (0xF000000U)
+#define DDRC_ADDRMAP3_addrmap_col_b9_SHIFT       (24U)
+#define DDRC_ADDRMAP3_addrmap_col_b9(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b9_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b9_MASK)
+/*! @} */
+/*! @name ADDRMAP4 - Address Map Register 4 */
+/*! @{ */
+#define DDRC_ADDRMAP4_addrmap_col_b10_MASK       (0xFU)
+#define DDRC_ADDRMAP4_addrmap_col_b10_SHIFT      (0U)
+#define DDRC_ADDRMAP4_addrmap_col_b10(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_addrmap_col_b10_SHIFT)) & DDRC_ADDRMAP4_addrmap_col_b10_MASK)
+#define DDRC_ADDRMAP4_addrmap_col_b11_MASK       (0xF00U)
+#define DDRC_ADDRMAP4_addrmap_col_b11_SHIFT      (8U)
+#define DDRC_ADDRMAP4_addrmap_col_b11(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_addrmap_col_b11_SHIFT)) & DDRC_ADDRMAP4_addrmap_col_b11_MASK)
+/*! @} */
+/*! @name ADDRMAP5 - Address Map Register 5 */
+/*! @{ */
+#define DDRC_ADDRMAP5_addrmap_row_b0_MASK        (0xFU)
+#define DDRC_ADDRMAP5_addrmap_row_b0_SHIFT       (0U)
+#define DDRC_ADDRMAP5_addrmap_row_b0(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b0_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b0_MASK)
+#define DDRC_ADDRMAP5_addrmap_row_b1_MASK        (0xF00U)
+#define DDRC_ADDRMAP5_addrmap_row_b1_SHIFT       (8U)
+#define DDRC_ADDRMAP5_addrmap_row_b1(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b1_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b1_MASK)
+#define DDRC_ADDRMAP5_addrmap_row_b2_10_MASK     (0xF0000U)
+#define DDRC_ADDRMAP5_addrmap_row_b2_10_SHIFT    (16U)
+#define DDRC_ADDRMAP5_addrmap_row_b2_10(x)       (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b2_10_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b2_10_MASK)
+#define DDRC_ADDRMAP5_addrmap_row_b11_MASK       (0xF000000U)
+#define DDRC_ADDRMAP5_addrmap_row_b11_SHIFT      (24U)
+#define DDRC_ADDRMAP5_addrmap_row_b11(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b11_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b11_MASK)
+/*! @} */
+/*! @name ADDRMAP6 - Address Map Register 6 */
+/*! @{ */
+#define DDRC_ADDRMAP6_addrmap_row_b12_MASK       (0xFU)
+#define DDRC_ADDRMAP6_addrmap_row_b12_SHIFT      (0U)
+#define DDRC_ADDRMAP6_addrmap_row_b12(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b12_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b12_MASK)
+#define DDRC_ADDRMAP6_addrmap_row_b13_MASK       (0xF00U)
+#define DDRC_ADDRMAP6_addrmap_row_b13_SHIFT      (8U)
+#define DDRC_ADDRMAP6_addrmap_row_b13(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b13_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b13_MASK)
+#define DDRC_ADDRMAP6_addrmap_row_b14_MASK       (0xF0000U)
+#define DDRC_ADDRMAP6_addrmap_row_b14_SHIFT      (16U)
+#define DDRC_ADDRMAP6_addrmap_row_b14(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b14_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b14_MASK)
+#define DDRC_ADDRMAP6_addrmap_row_b15_MASK       (0xF000000U)
+#define DDRC_ADDRMAP6_addrmap_row_b15_SHIFT      (24U)
+#define DDRC_ADDRMAP6_addrmap_row_b15(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b15_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b15_MASK)
+#define DDRC_ADDRMAP6_lpddr3_6gb_12gb_MASK       (0x80000000U)
+#define DDRC_ADDRMAP6_lpddr3_6gb_12gb_SHIFT      (31U)
+#define DDRC_ADDRMAP6_lpddr3_6gb_12gb(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_lpddr3_6gb_12gb_SHIFT)) & DDRC_ADDRMAP6_lpddr3_6gb_12gb_MASK)
+/*! @} */
+/*! @name ADDRMAP7 - Address Map Register 7 */
+/*! @{ */
+#define DDRC_ADDRMAP7_addrmap_row_b16_MASK       (0xFU)
+#define DDRC_ADDRMAP7_addrmap_row_b16_SHIFT      (0U)
+#define DDRC_ADDRMAP7_addrmap_row_b16(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_addrmap_row_b16_SHIFT)) & DDRC_ADDRMAP7_addrmap_row_b16_MASK)
+#define DDRC_ADDRMAP7_addrmap_row_b17_MASK       (0xF00U)
+#define DDRC_ADDRMAP7_addrmap_row_b17_SHIFT      (8U)
+#define DDRC_ADDRMAP7_addrmap_row_b17(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_addrmap_row_b17_SHIFT)) & DDRC_ADDRMAP7_addrmap_row_b17_MASK)
+/*! @} */
+/*! @name ADDRMAP8 - Address Map Register 8 */
+/*! @{ */
+#define DDRC_ADDRMAP8_addrmap_bg_b0_MASK         (0x1FU)
+#define DDRC_ADDRMAP8_addrmap_bg_b0_SHIFT        (0U)
+#define DDRC_ADDRMAP8_addrmap_bg_b0(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_addrmap_bg_b0_SHIFT)) & DDRC_ADDRMAP8_addrmap_bg_b0_MASK)
+#define DDRC_ADDRMAP8_addrmap_bg_b1_MASK         (0x3F00U)
+#define DDRC_ADDRMAP8_addrmap_bg_b1_SHIFT        (8U)
+#define DDRC_ADDRMAP8_addrmap_bg_b1(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_addrmap_bg_b1_SHIFT)) & DDRC_ADDRMAP8_addrmap_bg_b1_MASK)
+/*! @} */
+/*! @name ADDRMAP9 - Address Map Register 9 */
+/*! @{ */
+#define DDRC_ADDRMAP9_addrmap_row_b2_MASK        (0xFU)
+#define DDRC_ADDRMAP9_addrmap_row_b2_SHIFT       (0U)
+#define DDRC_ADDRMAP9_addrmap_row_b2(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b2_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b2_MASK)
+#define DDRC_ADDRMAP9_addrmap_row_b3_MASK        (0xF00U)
+#define DDRC_ADDRMAP9_addrmap_row_b3_SHIFT       (8U)
+#define DDRC_ADDRMAP9_addrmap_row_b3(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b3_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b3_MASK)
+#define DDRC_ADDRMAP9_addrmap_row_b4_MASK        (0xF0000U)
+#define DDRC_ADDRMAP9_addrmap_row_b4_SHIFT       (16U)
+#define DDRC_ADDRMAP9_addrmap_row_b4(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b4_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b4_MASK)
+#define DDRC_ADDRMAP9_addrmap_row_b5_MASK        (0xF000000U)
+#define DDRC_ADDRMAP9_addrmap_row_b5_SHIFT       (24U)
+#define DDRC_ADDRMAP9_addrmap_row_b5(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b5_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b5_MASK)
+/*! @} */
+/*! @name ADDRMAP10 - Address Map Register 10 */
+/*! @{ */
+#define DDRC_ADDRMAP10_addrmap_row_b6_MASK       (0xFU)
+#define DDRC_ADDRMAP10_addrmap_row_b6_SHIFT      (0U)
+#define DDRC_ADDRMAP10_addrmap_row_b6(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b6_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b6_MASK)
+#define DDRC_ADDRMAP10_addrmap_row_b7_MASK       (0xF00U)
+#define DDRC_ADDRMAP10_addrmap_row_b7_SHIFT      (8U)
+#define DDRC_ADDRMAP10_addrmap_row_b7(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b7_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b7_MASK)
+#define DDRC_ADDRMAP10_addrmap_row_b8_MASK       (0xF0000U)
+#define DDRC_ADDRMAP10_addrmap_row_b8_SHIFT      (16U)
+#define DDRC_ADDRMAP10_addrmap_row_b8(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b8_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b8_MASK)
+#define DDRC_ADDRMAP10_addrmap_row_b9_MASK       (0xF000000U)
+#define DDRC_ADDRMAP10_addrmap_row_b9_SHIFT      (24U)
+#define DDRC_ADDRMAP10_addrmap_row_b9(x)         (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b9_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b9_MASK)
+/*! @} */
+/*! @name ADDRMAP11 - Address Map Register 11 */
+/*! @{ */
+#define DDRC_ADDRMAP11_addrmap_row_b10_MASK      (0xFU)
+#define DDRC_ADDRMAP11_addrmap_row_b10_SHIFT     (0U)
+#define DDRC_ADDRMAP11_addrmap_row_b10(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP11_addrmap_row_b10_SHIFT)) & DDRC_ADDRMAP11_addrmap_row_b10_MASK)
+/*! @} */
+/*! @name ODTCFG - ODT Configuration Register */
+/*! @{ */
+#define DDRC_ODTCFG_rd_odt_delay_MASK            (0x7CU)
+#define DDRC_ODTCFG_rd_odt_delay_SHIFT           (2U)
+#define DDRC_ODTCFG_rd_odt_delay(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_rd_odt_delay_SHIFT)) & DDRC_ODTCFG_rd_odt_delay_MASK)
+#define DDRC_ODTCFG_rd_odt_hold_MASK             (0xF00U)
+#define DDRC_ODTCFG_rd_odt_hold_SHIFT            (8U)
+#define DDRC_ODTCFG_rd_odt_hold(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_rd_odt_hold_SHIFT)) & DDRC_ODTCFG_rd_odt_hold_MASK)
+#define DDRC_ODTCFG_wr_odt_delay_MASK            (0x1F0000U)
+#define DDRC_ODTCFG_wr_odt_delay_SHIFT           (16U)
+#define DDRC_ODTCFG_wr_odt_delay(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_wr_odt_delay_SHIFT)) & DDRC_ODTCFG_wr_odt_delay_MASK)
+#define DDRC_ODTCFG_wr_odt_hold_MASK             (0xF000000U)
+#define DDRC_ODTCFG_wr_odt_hold_SHIFT            (24U)
+#define DDRC_ODTCFG_wr_odt_hold(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_wr_odt_hold_SHIFT)) & DDRC_ODTCFG_wr_odt_hold_MASK)
+/*! @} */
+/*! @name ODTMAP - ODT/Rank Map Register */
+/*! @{ */
+#define DDRC_ODTMAP_rank0_wr_odt_MASK            (0x3U)
+#define DDRC_ODTMAP_rank0_wr_odt_SHIFT           (0U)
+#define DDRC_ODTMAP_rank0_wr_odt(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank0_wr_odt_SHIFT)) & DDRC_ODTMAP_rank0_wr_odt_MASK)
+#define DDRC_ODTMAP_rank0_rd_odt_MASK            (0x30U)
+#define DDRC_ODTMAP_rank0_rd_odt_SHIFT           (4U)
+#define DDRC_ODTMAP_rank0_rd_odt(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank0_rd_odt_SHIFT)) & DDRC_ODTMAP_rank0_rd_odt_MASK)
+#define DDRC_ODTMAP_rank1_wr_odt_MASK            (0x300U)
+#define DDRC_ODTMAP_rank1_wr_odt_SHIFT           (8U)
+#define DDRC_ODTMAP_rank1_wr_odt(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank1_wr_odt_SHIFT)) & DDRC_ODTMAP_rank1_wr_odt_MASK)
+#define DDRC_ODTMAP_rank1_rd_odt_MASK            (0x3000U)
+#define DDRC_ODTMAP_rank1_rd_odt_SHIFT           (12U)
+#define DDRC_ODTMAP_rank1_rd_odt(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank1_rd_odt_SHIFT)) & DDRC_ODTMAP_rank1_rd_odt_MASK)
+/*! @} */
+/*! @name SCHED - Scheduler Control Register */
+/*! @{ */
+#define DDRC_SCHED_force_low_pri_n_MASK          (0x1U)
+#define DDRC_SCHED_force_low_pri_n_SHIFT         (0U)
+#define DDRC_SCHED_force_low_pri_n(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_force_low_pri_n_SHIFT)) & DDRC_SCHED_force_low_pri_n_MASK)
+#define DDRC_SCHED_prefer_write_MASK             (0x2U)
+#define DDRC_SCHED_prefer_write_SHIFT            (1U)
+#define DDRC_SCHED_prefer_write(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_prefer_write_SHIFT)) & DDRC_SCHED_prefer_write_MASK)
+#define DDRC_SCHED_pageclose_MASK                (0x4U)
+#define DDRC_SCHED_pageclose_SHIFT               (2U)
+#define DDRC_SCHED_pageclose(x)                  (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_pageclose_SHIFT)) & DDRC_SCHED_pageclose_MASK)
+#define DDRC_SCHED_lpr_num_entries_MASK          (0x1F00U)
+#define DDRC_SCHED_lpr_num_entries_SHIFT         (8U)
+#define DDRC_SCHED_lpr_num_entries(x)            (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_lpr_num_entries_SHIFT)) & DDRC_SCHED_lpr_num_entries_MASK)
+#define DDRC_SCHED_go2critical_hysteresis_MASK   (0xFF0000U)
+#define DDRC_SCHED_go2critical_hysteresis_SHIFT  (16U)
+#define DDRC_SCHED_go2critical_hysteresis(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_go2critical_hysteresis_SHIFT)) & DDRC_SCHED_go2critical_hysteresis_MASK)
+#define DDRC_SCHED_rdwr_idle_gap_MASK            (0x7F000000U)
+#define DDRC_SCHED_rdwr_idle_gap_SHIFT           (24U)
+#define DDRC_SCHED_rdwr_idle_gap(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_rdwr_idle_gap_SHIFT)) & DDRC_SCHED_rdwr_idle_gap_MASK)
+/*! @} */
+/*! @name SCHED1 - Scheduler Control Register 1 */
+/*! @{ */
+#define DDRC_SCHED1_pageclose_timer_MASK         (0xFFU)
+#define DDRC_SCHED1_pageclose_timer_SHIFT        (0U)
+#define DDRC_SCHED1_pageclose_timer(x)           (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED1_pageclose_timer_SHIFT)) & DDRC_SCHED1_pageclose_timer_MASK)
+/*! @} */
+/*! @name PERFHPR1 - High Priority Read CAM Register 1 */
+/*! @{ */
+#define DDRC_PERFHPR1_hpr_max_starve_MASK        (0xFFFFU)
+#define DDRC_PERFHPR1_hpr_max_starve_SHIFT       (0U)
+#define DDRC_PERFHPR1_hpr_max_starve(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_hpr_max_starve_SHIFT)) & DDRC_PERFHPR1_hpr_max_starve_MASK)
+#define DDRC_PERFHPR1_hpr_xact_run_length_MASK   (0xFF000000U)
+#define DDRC_PERFHPR1_hpr_xact_run_length_SHIFT  (24U)
+#define DDRC_PERFHPR1_hpr_xact_run_length(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_hpr_xact_run_length_SHIFT)) & DDRC_PERFHPR1_hpr_xact_run_length_MASK)
+/*! @} */
+/*! @name PERFLPR1 - Low Priority Read CAM Register 1 */
+/*! @{ */
+#define DDRC_PERFLPR1_lpr_max_starve_MASK        (0xFFFFU)
+#define DDRC_PERFLPR1_lpr_max_starve_SHIFT       (0U)
+#define DDRC_PERFLPR1_lpr_max_starve(x)          (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_lpr_max_starve_SHIFT)) & DDRC_PERFLPR1_lpr_max_starve_MASK)
+#define DDRC_PERFLPR1_lpr_xact_run_length_MASK   (0xFF000000U)
+#define DDRC_PERFLPR1_lpr_xact_run_length_SHIFT  (24U)
+#define DDRC_PERFLPR1_lpr_xact_run_length(x)     (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_lpr_xact_run_length_SHIFT)) & DDRC_PERFLPR1_lpr_xact_run_length_MASK)
+/*! @} */
+/*! @name PERFWR1 - Write CAM Register 1 */
+/*! @{ */
+#define DDRC_PERFWR1_w_max_starve_MASK           (0xFFFFU)
+#define DDRC_PERFWR1_w_max_starve_SHIFT          (0U)
+#define DDRC_PERFWR1_w_max_starve(x)             (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_w_max_starve_SHIFT)) & DDRC_PERFWR1_w_max_starve_MASK)
+#define DDRC_PERFWR1_w_xact_run_length_MASK      (0xFF000000U)
+#define DDRC_PERFWR1_w_xact_run_length_SHIFT     (24U)
+#define DDRC_PERFWR1_w_xact_run_length(x)        (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_w_xact_run_length_SHIFT)) & DDRC_PERFWR1_w_xact_run_length_MASK)
+/*! @} */
+/*! @name DBG0 - Debug Register 0 */
+/*! @{ */
+#define DDRC_DBG0_dis_wc_MASK                    (0x1U)
+#define DDRC_DBG0_dis_wc_SHIFT                   (0U)
+#define DDRC_DBG0_dis_wc(x)                      (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_wc_SHIFT)) & DDRC_DBG0_dis_wc_MASK)
+#define DDRC_DBG0_dis_rd_bypass_MASK             (0x2U)
+#define DDRC_DBG0_dis_rd_bypass_SHIFT            (1U)
+#define DDRC_DBG0_dis_rd_bypass(x)               (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_rd_bypass_SHIFT)) & DDRC_DBG0_dis_rd_bypass_MASK)
+#define DDRC_DBG0_dis_act_bypass_MASK            (0x4U)
+#define DDRC_DBG0_dis_act_bypass_SHIFT           (2U)
+#define DDRC_DBG0_dis_act_bypass(x)              (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_act_bypass_SHIFT)) & DDRC_DBG0_dis_act_bypass_MASK)