31 files changed, 59429 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN6/MIMX8MN6_cm7.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN6/MIMX8MN6_cm7.h
new file mode 100644
index 000000000..a0069260b
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN6/MIMX8MN6_cm7.h
@@ -0,0 +1,51096 @@
+/*
+** ###################################################################
+**     Processors:          MIMX8MN6CVTIZ
+**                          MIMX8MN6DVTJZ
+**
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**
+**     Reference manual:    MX8MNRM, Rev.A, 04/2019
+**     Version:             rev. 2.0, 2019-09-23
+**     Build:               b190830
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MIMX8MN6_cm7
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2019 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2019-04-22)
+**         Initial version.
+**     - rev. 2.0 (2019-09-23)
+**         Rev.B Header RFP
+**
+** ###################################################################
+*/
+/*!
+ * @file MIMX8MN6_cm7.h
+ * @version 2.0
+ * @date 2019-09-23
+ * @brief CMSIS Peripheral Access Layer for MIMX8MN6_cm7
+ *
+ * CMSIS Peripheral Access Layer for MIMX8MN6_cm7
+ */
+#ifndef _MIMX8MN6_CM7_H_
+#define _MIMX8MN6_CM7_H_ /**< Symbol preventing repeated inclusion */
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 144 /**< Number of interrupts in the Vector table */
+typedef enum IRQn
+{
+    /* Auxiliary constants */
+    NotAvail_IRQn = -128, /**< Not available device specific interrupt */
+    /* Core interrupts */
+    NonMaskableInt_IRQn   = -14, /**< Non Maskable Interrupt */
+    HardFault_IRQn        = -13, /**< Cortex-M7 SV Hard Fault Interrupt */
+    MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */
+    BusFault_IRQn         = -11, /**< Cortex-M7 Bus Fault Interrupt */
+    UsageFault_IRQn       = -10, /**< Cortex-M7 Usage Fault Interrupt */
+    SVCall_IRQn           = -5,  /**< Cortex-M7 SV Call Interrupt */
+    DebugMonitor_IRQn     = -4,  /**< Cortex-M7 Debug Monitor Interrupt */
+    PendSV_IRQn           = -2,  /**< Cortex-M7 Pend SV Interrupt */
+    SysTick_IRQn          = -1,  /**< Cortex-M7 System Tick Interrupt */
+    /* Device specific interrupts */
+    GPR_IRQ_IRQn           = 0,  /**< GPR Interrupt. Used to notify cores on exception condition while boot. */
+    DAP_IRQn               = 1,  /**< DAP Interrupt */
+    SDMA1_IRQn             = 2,  /**< AND of all 48 SDMA1 interrupts (events) from all the channels */
+    GPU3D_IRQn             = 3,  /**< GPU3D Interrupt */
+    SNVS_IRQn              = 4,  /**< ON-OFF button press shorter than 5 seconds (pulse event) */
+    LCDIF_IRQn             = 5,  /**< LCDIF Interrupt */
+    SPDIF1_IRQn            = 6,  /**< SPDIF1 RZX/TX Interrupt */
+    Reserved23_IRQn        = 7,  /**< Reserved Interrupt */
+    Reserved24_IRQn        = 8,  /**< Reserved Interrupt */
+    QOS_IRQn               = 9,  /**< QOS interrupt */
+    WDOG3_IRQn             = 10, /**< Watchdog Timer reset */
+    HS_CP1_IRQn            = 11, /**< HS Interrupt Request */
+    APBHDMA_IRQn           = 12, /**< GPMI operation channel 0-3 description complete interrupt */
+    Reserved29_IRQn        = 13, /**< Reserved */
+    BCH_IRQn               = 14, /**< BCH operation complete interrupt */
+    GPMI_IRQn              = 15, /**< GPMI operation TIMEOUT ERROR interrupt */
+    ISI_CH0_IRQn           = 16, /**< ISI Camera Channel 0 Interrupt */
+    MIPI_CSI1_IRQn         = 17, /**< MIPI CSI Interrupt */
+    MIPI_DSI_IRQn          = 18, /**< MIPI DSI Interrupt */
+    SNVS_Consolidated_IRQn = 19, /**< SRTC Consolidated Interrupt. Non TZ. */
+    SNVS_Security_IRQn     = 20, /**< SRTC Security Interrupt. TZ. */
+    CSU_IRQn =
+        21, /**< CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted. */
+    USDHC1_IRQn          = 22, /**< uSDHC1 Enhanced SDHC Interrupt Request */
+    USDHC2_IRQn          = 23, /**< uSDHC2 Enhanced SDHC Interrupt Request */
+    USDHC3_IRQn          = 24, /**< uSDHC3 Enhanced SDHC Interrupt Request */
+    Reserved41_IRQn      = 25, /**< Reserved Interrupt */
+    UART1_IRQn           = 26, /**< UART-1 ORed interrupt */
+    UART2_IRQn           = 27, /**< UART-2 ORed interrupt */
+    UART3_IRQn           = 28, /**< UART-3 ORed interrupt */
+    UART4_IRQn           = 29, /**< UART-4 ORed interrupt */
+    Reserved46_IRQn      = 30, /**< Reserved Interrupt */
+    ECSPI1_IRQn          = 31, /**< ECSPI1 interrupt request line to the core. */
+    ECSPI2_IRQn          = 32, /**< ECSPI2 interrupt request line to the core. */
+    ECSPI3_IRQn          = 33, /**< ECSPI3 interrupt request line to the core. */
+    SDMA3_IRQn           = 34, /**< AND of all 48 SDMA3 interrupts (events) from all the channels */
+    I2C1_IRQn            = 35, /**< I2C-1 Interrupt */
+    I2C2_IRQn            = 36, /**< I2C-2 Interrupt */
+    I2C3_IRQn            = 37, /**< I2C-3 Interrupt */
+    I2C4_IRQn            = 38, /**< I2C-4 Interrupt */
+    RDC_IRQn             = 39, /**< RDC interrupt */
+    USB1_IRQn            = 40, /**< USB1 Interrupt */
+    Reserved57_IRQn      = 41, /**< Reserved Interrupt */
+    ISI_CH1_IRQn         = 42, /**< ISI Camera Channel 1 Interrupt */
+    ISI_CH2_IRQn         = 43, /**< ISI Camera Channel 2 Interrupt */
+    PDM_HWVAD_EVENT_IRQn = 44, /**< Digital Microphone interface voice activity detector event interrupt */
+    PDM_HWVAD_ERROR_IRQn = 45, /**< Digital Microphone interface voice activity detector error interrupt */
+    GPT6_IRQn = 46, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3
+                       Interrupt lines */
+    SCTR_IRQ0_IRQn   = 47, /**< System Counter Interrupt 0 */
+    SCTR_IRQ1_IRQn   = 48, /**< System Counter Interrupt 1 */
+    TEMPMON_LOW_IRQn = 49, /**< TempSensor (Temperature low alarm). */
+    I2S3_IRQn        = 50, /**< SAI3 Receive / Transmit Interrupt */
+    GPT5_IRQn = 51, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3
+                       Interrupt lines */
+    GPT4_IRQn = 52, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3
+                       Interrupt lines */
+    GPT3_IRQn = 53, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3
+                       Interrupt lines */
+    GPT2_IRQn = 54, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3
+                       Interrupt lines */
+    GPT1_IRQn = 55, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3
+                       Interrupt lines */
+    GPIO1_INT7_IRQn           = 56, /**< Active HIGH Interrupt from INT7 from GPIO */
+    GPIO1_INT6_IRQn           = 57, /**< Active HIGH Interrupt from INT6 from GPIO */
+    GPIO1_INT5_IRQn           = 58, /**< Active HIGH Interrupt from INT5 from GPIO */
+    GPIO1_INT4_IRQn           = 59, /**< Active HIGH Interrupt from INT4 from GPIO */
+    GPIO1_INT3_IRQn           = 60, /**< Active HIGH Interrupt from INT3 from GPIO */
+    GPIO1_INT2_IRQn           = 61, /**< Active HIGH Interrupt from INT2 from GPIO */
+    GPIO1_INT1_IRQn           = 62, /**< Active HIGH Interrupt from INT1 from GPIO */
+    GPIO1_INT0_IRQn           = 63, /**< Active HIGH Interrupt from INT0 from GPIO */
+    GPIO1_Combined_0_15_IRQn  = 64, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
+    GPIO1_Combined_16_31_IRQn = 65, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
+    GPIO2_Combined_0_15_IRQn  = 66, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
+    GPIO2_Combined_16_31_IRQn = 67, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
+    GPIO3_Combined_0_15_IRQn  = 68, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
+    GPIO3_Combined_16_31_IRQn = 69, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
+    GPIO4_Combined_0_15_IRQn  = 70, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */
+    GPIO4_Combined_16_31_IRQn = 71, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */
+    GPIO5_Combined_0_15_IRQn  = 72, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
+    GPIO5_Combined_16_31_IRQn = 73, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
+    Reserved90_IRQn           = 74, /**< Reserved interrupt */
+    Reserved91_IRQn           = 75, /**< Reserved interrupt */
+    Reserved92_IRQn           = 76, /**< Reserved interrupt */
+    Reserved93_IRQn           = 77, /**< Reserved interrupt */
+    WDOG1_IRQn                = 78, /**< Watchdog Timer reset */
+    WDOG2_IRQn                = 79, /**< Watchdog Timer reset */
+    Reserved96_IRQn           = 80, /**< Reserved interrupt */
+    PWM1_IRQn = 81, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO
+                       Waterlevel crossing interrupt line. */
+    PWM2_IRQn = 82, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO
+                       Waterlevel crossing interrupt line. */
+    PWM3_IRQn = 83, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO
+                       Waterlevel crossing interrupt line. */
+    PWM4_IRQn = 84, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO
+                       Waterlevel crossing interrupt line. */
+    CCM_IRQ1_IRQn               = 85,  /**< CCM Interrupt Request 1 */
+    CCM_IRQ2_IRQn               = 86,  /**< CCM Interrupt Request 2 */
+    GPC_IRQn                    = 87,  /**< GPC Interrupt Request 1 */
+    MU_A53_IRQn                 = 88,  /**< Interrupt to A53 */
+    SRC_IRQn                    = 89,  /**< SRC interrupt request */
+    I2S56_IRQn                  = 90,  /**< SAI5/6 Receive / Transmit Interrupt */
+    RTIC_IRQn                   = 91,  /**< RTIC Interrupt */
+    CPU_PerformanceUnit_IRQn    = 92,  /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n] */
+    CPU_CTI_Trigger_IRQn        = 93,  /**< CTI trigger outputs (internal: nCTIIRQ[n] */
+    SRC_Combined_IRQn           = 94,  /**< Combined CPU wdog interrupts (4x) out of SRC. */
+    Reserved111_IRQn            = 95,  /**< Reserved Interrupt */
+    I2S2_IRQn                   = 96,  /**< SAI2 Receive / Transmit Interrupt */
+    MU_M7_IRQn                  = 97,  /**< Interrupt to M7 */
+    DDR_PerformanceMonitor_IRQn = 98,  /**< ddr Interrupt for performance monitor */
+    DDR_IRQn                    = 99,  /**< ddr Interrupt */
+    Reserved116_IRQn            = 100, /**< Reserved interrupt */
+    CPU_Error_AXI_IRQn   = 101, /**< CPU Error indicator for AXI transaction with a write response error condition */
+    CPU_Error_L2RAM_IRQn = 102, /**< CPU Error indicator for L2 RAM double-bit ECC error */
+    SDMA2_IRQn           = 103, /**< AND of all 48 SDMA2 interrupts (events) from all the channels */
+    SJC_IRQn             = 104, /**< Interrupt triggered by SJC register */
+    CAAM_IRQ0_IRQn       = 105, /**< CAAM interrupt queue for JQ */
+    CAAM_IRQ1_IRQn       = 106, /**< CAAM interrupt queue for JQ */
+    QSPI_IRQn            = 107, /**< QSPI Interrupt */
+    TZASC_IRQn           = 108, /**< TZASC (PL380) interrupt */
+    PDM_EVENT_IRQn       = 109, /**< Digital Microphone interface interrupt */
+    PDM_ERROR_IRQn       = 110, /**< Digital Microphone interface error interrupt */
+    I2S7_IRQn            = 111, /**< SAI7 Receive / Transmit Interrupt */
+    PERFMON1_IRQn        = 112, /**< General Interrupt */
+    PERFMON2_IRQn        = 113, /**< General Interrupt */
+    CAAM_IRQ2_IRQn       = 114, /**< CAAM interrupt queue for JQ */
+    CAAM_ERROR_IRQn      = 115, /**< Recoverable error interrupt */
+    HS_CP0_IRQn          = 116, /**< HS Interrupt Request */
+    CM7_CTI_IRQn         = 117, /**< CTI trigger outputs from CM7 platform */
+    ENET_MAC0_Rx_Tx_Done1_IRQn = 118, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */
+    ENET_MAC0_Rx_Tx_Done2_IRQn = 119, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */
+    ENET_IRQn                  = 120, /**< MAC 0 IRQ */
+    ENET_1588_IRQn             = 121, /**< MAC 0 1588 Timer Interrupt - synchronous */
+    ASRC_IRQn                  = 122, /**< ASRC Interrupt */
+    Reserved139_IRQn           = 123, /**< Reserved Interrupt */
+    Reserved140_IRQn           = 124, /**< Reserved Interrupt */
+    Reserved141_IRQn           = 125, /**< Reserved Interrupt */
+    ISI_CH3_IRQn               = 126, /**< ISI Camera Channel 3 Interrupt */
+    Reserved143_IRQn           = 127  /**< Reserved Interrupt */
+} IRQn_Type;
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+/* ----------------------------------------------------------------------------
+   -- Cortex M7 Core Configuration
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration
+ * @{
+ */
+#define __MPU_PRESENT 1          /**< Defines if an MPU is present or not */
+#define __ICACHE_PRESENT 1       /**< Defines if an ICACHE is present or not */
+#define __DCACHE_PRESENT 1       /**< Defines if an DCACHE is present or not */
+#define __DTCM_PRESENT 1         /**< Defines if an DTCM is present or not */
+#define __NVIC_PRIO_BITS 4       /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT 1          /**< Defines if an FPU is present or not */
+#include "core_cm7.h"            /* Core Peripheral Access Layer */
+#include "system_MIMX8MN6_cm7.h" /* Device specific configuration file */
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+/** Mapping Information */
+/*!
+ * @addtogroup iomuxc_pads
+ * @{ */
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+/*!
+ * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
+ *
+ * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
+ */
+typedef enum _iomuxc_sw_mux_ctl_pad
+{
+    kIOMUXC_SW_MUX_CTL_PAD_BOOT_MODE2    = 0U,   /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_BOOT_MODE3    = 1U,   /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00    = 2U,   /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01    = 3U,   /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02    = 4U,   /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03    = 5U,   /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04    = 6U,   /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05    = 7U,   /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06    = 8U,   /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07    = 9U,   /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08    = 10U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09    = 11U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10    = 12U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11    = 13U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12    = 14U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13    = 15U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14    = 16U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15    = 17U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_MDC      = 18U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_MDIO     = 19U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_TD3      = 20U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_TD2      = 21U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_TD1      = 22U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_TD0      = 23U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL   = 24U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_TXC      = 25U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL   = 26U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_RXC      = 27U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_RD0      = 28U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_RD1      = 29U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_RD2      = 30U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ENET_RD3      = 31U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_CLK       = 32U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_CMD       = 33U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA0     = 34U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA1     = 35U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2     = 36U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA3     = 37U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA4     = 38U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA5     = 39U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA6     = 40U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA7     = 41U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B   = 42U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD1_STROBE    = 43U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD2_CD_B      = 44U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD2_CLK       = 45U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD2_CMD       = 46U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA0     = 47U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA1     = 48U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA2     = 49U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA3     = 50U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B   = 51U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SD2_WP        = 52U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_ALE      = 53U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B    = 54U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B    = 55U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B    = 56U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B    = 57U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_CLE      = 58U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA00   = 59U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA01   = 60U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA02   = 61U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA03   = 62U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA04   = 63U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA05   = 64U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA06   = 65U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA07   = 66U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_DQS      = 67U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_RE_B     = 68U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_READY_B  = 69U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_WE_B     = 70U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_NAND_WP_B     = 71U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS     = 72U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXC      = 73U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0     = 74U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1     = 75U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2     = 76U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3     = 77U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK     = 78U,  /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS     = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXC      = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0     = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS     = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXC      = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0     = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI2_MCLK     = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS     = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXC      = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXD      = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS     = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXC      = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXD      = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK     = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SPDIF_TX      = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SPDIF_RX      = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK   = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI   = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO   = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0    = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK   = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI   = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO   = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0    = 124U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_I2C1_SCL      = 125U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_I2C1_SDA      = 126U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_I2C2_SCL      = 127U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_I2C2_SDA      = 128U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_I2C3_SCL      = 129U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_I2C3_SDA      = 130U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_I2C4_SCL      = 131U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_I2C4_SDA      = 132U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_UART1_RXD     = 133U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_UART1_TXD     = 134U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_UART2_RXD     = 135U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_UART2_TXD     = 136U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_UART3_RXD     = 137U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_UART3_TXD     = 138U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_UART4_RXD     = 139U, /**< IOMUXC SW_MUX_CTL_PAD index */
+    kIOMUXC_SW_MUX_CTL_PAD_UART4_TXD     = 140U, /**< IOMUXC SW_MUX_CTL_PAD index */
+} iomuxc_sw_mux_ctl_pad_t;
+/*!
+ * @addtogroup iomuxc_pads
+ * @{ */
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+/*!
+ * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
+ *
+ * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
+ */
+typedef enum _iomuxc_sw_pad_ctl_pad
+{
+    kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0    = 0U,   /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1    = 1U,   /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE2    = 2U,   /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE3    = 3U,   /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_JTAG_MOD      = 4U,   /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDI      = 5U,   /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_JTAG_TMS      = 6U,   /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_JTAG_TCK      = 7U,   /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDO      = 8U,   /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ = 10U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ   = 11U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00    = 15U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01    = 16U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02    = 17U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03    = 18U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04    = 19U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05    = 20U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06    = 21U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07    = 22U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08    = 23U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09    = 24U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10    = 25U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11    = 26U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12    = 27U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13    = 28U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14    = 29U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15    = 30U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_MDC      = 31U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_MDIO     = 32U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_TD3      = 33U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_TD2      = 34U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_TD1      = 35U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_TD0      = 36U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_TX_CTL   = 37U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_TXC      = 38U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_RX_CTL   = 39U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_RXC      = 40U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_RD0      = 41U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_RD1      = 42U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_RD2      = 43U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ENET_RD3      = 44U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_CLK       = 45U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_CMD       = 46U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA0     = 47U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA1     = 48U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA2     = 49U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA3     = 50U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA4     = 51U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA5     = 52U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA6     = 53U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA7     = 54U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B   = 55U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD1_STROBE    = 56U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD2_CD_B      = 57U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD2_CLK       = 58U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD2_CMD       = 59U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA0     = 60U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA1     = 61U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA2     = 62U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA3     = 63U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B   = 64U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SD2_WP        = 65U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_ALE      = 66U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B    = 67U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B    = 68U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_CE2_B    = 69U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_CE3_B    = 70U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_CLE      = 71U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA00   = 72U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA01   = 73U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA02   = 74U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA03   = 75U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA04   = 76U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA05   = 77U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA06   = 78U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA07   = 79U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_DQS      = 80U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_RE_B     = 81U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_READY_B  = 82U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_WE_B     = 83U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_NAND_WP_B     = 84U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXFS     = 85U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXC      = 86U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD0     = 87U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD1     = 88U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD2     = 89U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD3     = 90U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI5_MCLK     = 91U,  /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXFS     = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXC      = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXD0     = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXFS     = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXC      = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXD0     = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI2_MCLK     = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXFS     = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXC      = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXD      = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXFS     = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXC      = 124U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXD      = 125U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SAI3_MCLK     = 126U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SPDIF_TX      = 127U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SPDIF_RX      = 128U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_SPDIF_EXT_CLK = 129U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK   = 130U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI   = 131U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO   = 132U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0    = 133U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK   = 134U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI   = 135U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO   = 136U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0    = 137U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_I2C1_SCL      = 138U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_I2C1_SDA      = 139U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_I2C2_SCL      = 140U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_I2C2_SDA      = 141U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_I2C3_SCL      = 142U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_I2C3_SDA      = 143U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_I2C4_SCL      = 144U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_I2C4_SDA      = 145U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_UART1_RXD     = 146U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_UART1_TXD     = 147U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_UART2_RXD     = 148U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_UART2_TXD     = 149U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_UART3_RXD     = 150U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_UART3_TXD     = 151U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_UART4_RXD     = 152U, /**< IOMUXC SW_PAD_CTL_PAD index */
+    kIOMUXC_SW_PAD_CTL_PAD_UART4_TXD     = 153U, /**< IOMUXC SW_PAD_CTL_PAD index */
+} iomuxc_sw_pad_ctl_pad_t;
+/* @} */
+/*!
+ * @brief Enumeration for the IOMUXC select input
+ *
+ * Defines the enumeration for the IOMUXC select input collections.
+ */
+typedef enum _iomuxc_select_input
+{
+    kIOMUXC_CCM_PMIC_READY_SELECT_INPUT     = 0U,  /**< IOMUXC select input index */
+    kIOMUXC_ENET1_MDIO_SELECT_INPUT         = 1U,  /**< IOMUXC select input index */
+    kIOMUXC_SAI5_RX_BCLK_SELECT_INPUT       = 5U,  /**< IOMUXC select input index */
+    kIOMUXC_SAI5_RX_DATA0_SELECT_INPUT      = 6U,  /**< IOMUXC select input index */
+    kIOMUXC_SAI5_RX_DATA1_SELECT_INPUT      = 7U,  /**< IOMUXC select input index */
+    kIOMUXC_SAI5_RX_DATA2_SELECT_INPUT      = 8U,  /**< IOMUXC select input index */
+    kIOMUXC_SAI5_RX_DATA3_SELECT_INPUT      = 9U,  /**< IOMUXC select input index */
+    kIOMUXC_SAI5_RX_SYNC_SELECT_INPUT       = 10U, /**< IOMUXC select input index */
+    kIOMUXC_SAI5_TX_BCLK_SELECT_INPUT       = 11U, /**< IOMUXC select input index */
+    kIOMUXC_SAI5_TX_SYNC_SELECT_INPUT       = 12U, /**< IOMUXC select input index */
+    kIOMUXC_UART1_RTS_B_SELECT_INPUT        = 13U, /**< IOMUXC select input index */
+    kIOMUXC_UART1_RX_SELECT_INPUT           = 14U, /**< IOMUXC select input index */
+    kIOMUXC_UART2_RTS_B_SELECT_INPUT        = 15U, /**< IOMUXC select input index */
+    kIOMUXC_UART2_RX_SELECT_INPUT           = 16U, /**< IOMUXC select input index */
+    kIOMUXC_UART3_RTS_B_SELECT_INPUT        = 17U, /**< IOMUXC select input index */
+    kIOMUXC_UART3_RX_SELECT_INPUT           = 18U, /**< IOMUXC select input index */
+    kIOMUXC_UART4_RTS_B_SELECT_INPUT        = 19U, /**< IOMUXC select input index */
+    kIOMUXC_UART4_RX_SELECT_INPUT           = 20U, /**< IOMUXC select input index */
+    kIOMUXC_PDM_BIT_STREAM0_SELECT_INPUT    = 30U, /**< IOMUXC select input index */
+    kIOMUXC_PDM_BIT_STREAM1_SELECT_INPUT    = 31U, /**< IOMUXC select input index */
+    kIOMUXC_PDM_BIT_STREAM2_SELECT_INPUT    = 32U, /**< IOMUXC select input index */
+    kIOMUXC_PDM_BIT_STREAM3_SELECT_INPUT    = 33U, /**< IOMUXC select input index */
+    kIOMUXC_USDHC3_DATA7_SELECT_INPUT       = 36U, /**< IOMUXC select input index */
+    kIOMUXC_USDHC3_DATA5_SELECT_INPUT       = 37U, /**< IOMUXC select input index */
+    kIOMUXC_ENET1_RGMII_RD1_SELECT_INPUT    = 38U, /**< IOMUXC select input index */
+    kIOMUXC_USDHC3_DATA4_SELECT_INPUT       = 39U, /**< IOMUXC select input index */
+    kIOMUXC_I2C1_SCL_SELECT_INPUT           = 40U, /**< IOMUXC select input index */
+    kIOMUXC_I2C2_SDA_SELECT_INPUT           = 41U, /**< IOMUXC select input index */
+    kIOMUXC_ECSPI1_SS0_SELECT_INPUT         = 42U, /**< IOMUXC select input index */
+    kIOMUXC_SPDIF1_EXT_CLK_SELECT_INPUT     = 43U, /**< IOMUXC select input index */
+    kIOMUXC_I2C1_SDA_SELECT_INPUT           = 44U, /**< IOMUXC select input index */
+    kIOMUXC_ECSPI2_SS0_SELECT_INPUT         = 45U, /**< IOMUXC select input index */
+    kIOMUXC_ENET1_RGMII_RX_CTL_SELECT_INPUT = 46U, /**< IOMUXC select input index */
+    kIOMUXC_ECSPI2_MISO_SELECT_INPUT        = 47U, /**< IOMUXC select input index */
+    kIOMUXC_ENET1_RGMII_RD0_SELECT_INPUT    = 48U, /**< IOMUXC select input index */
+    kIOMUXC_ECSPI2_SCLK_SELECT_INPUT        = 49U, /**< IOMUXC select input index */
+    kIOMUXC_USDHC3_DATA6_SELECT_INPUT       = 50U, /**< IOMUXC select input index */
+    kIOMUXC_I2C3_SCL_SELECT_INPUT           = 51U, /**< IOMUXC select input index */
+    kIOMUXC_I2C4_SDA_SELECT_INPUT           = 52U, /**< IOMUXC select input index */
+    kIOMUXC_ECSPI2_MOSI_SELECT_INPUT        = 53U, /**< IOMUXC select input index */
+    kIOMUXC_SAI5_MCLK_SELECT_INPUT          = 54U, /**< IOMUXC select input index */
+    kIOMUXC_USDHC3_CD_B_SELECT_INPUT        = 55U, /**< IOMUXC select input index */
+    kIOMUXC_USDHC3_STROBE_SELECT_INPUT      = 56U, /**< IOMUXC select input index */
+    kIOMUXC_USDHC3_CLK_SELECT_INPUT         = 57U, /**< IOMUXC select input index */
+    kIOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT = 58U, /**< IOMUXC select input index */
+    kIOMUXC_ECSPI1_MOSI_SELECT_INPUT        = 59U, /**< IOMUXC select input index */
+    kIOMUXC_SAI2_RX_DATA1_SELECT_INPUT      = 60U, /**< IOMUXC select input index */
+    kIOMUXC_USDHC3_DATA1_SELECT_INPUT       = 61U, /**< IOMUXC select input index */
+    kIOMUXC_USDHC3_DATA0_SELECT_INPUT       = 62U, /**< IOMUXC select input index */
+    kIOMUXC_USDHC3_WP_SELECT_INPUT          = 63U, /**< IOMUXC select input index */
+    kIOMUXC_I2C3_SDA_SELECT_INPUT           = 64U, /**< IOMUXC select input index */
+    kIOMUXC_SAI3_MCLK_SELECT_INPUT          = 65U, /**< IOMUXC select input index */
+    kIOMUXC_ECSPI1_MISO_SELECT_INPUT        = 66U, /**< IOMUXC select input index */
+    kIOMUXC_ENET1_RX_ER_SELECT_INPUT        = 67U, /**< IOMUXC select input index */
+    kIOMUXC_SPDIF1_IN_SELECT_INPUT          = 68U, /**< IOMUXC select input index */
+    kIOMUXC_I2C2_SCL_SELECT_INPUT           = 69U, /**< IOMUXC select input index */
+    kIOMUXC_I2C4_SCL_SELECT_INPUT           = 70U, /**< IOMUXC select input index */
+    kIOMUXC_ECSPI1_SCLK_SELECT_INPUT        = 71U, /**< IOMUXC select input index */
+    kIOMUXC_USDHC3_CMD_SELECT_INPUT         = 72U, /**< IOMUXC select input index */
+    kIOMUXC_USDHC3_DATA3_SELECT_INPUT       = 73U, /**< IOMUXC select input index */
+    kIOMUXC_USDHC3_DATA2_SELECT_INPUT       = 74U, /**< IOMUXC select input index */
+    kIOMUXC_GPT1_CLK_SELECT_INPUT           = 75U, /**< IOMUXC select input index */
+    kIOMUXC_GPT1_CAPTURE2_SELECT_INPUT      = 76U, /**< IOMUXC select input index */
+    kIOMUXC_GPT1_CAPTURE1_SELECT_INPUT      = 77U, /**< IOMUXC select input index */
+} iomuxc_select_input_t;
+/*!
+ * @addtogroup rdc_mapping
+ * @{
+ */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!
+ * @brief Structure for the RDC mapping
+ *
+ * Defines the structure for the RDC resource collections.
+ */
+typedef enum _rdc_master
+{
+    kRDC_Master_A53          = 0U,  /**< ARM Cortex-A53 RDC Master */
+    kRDC_Master_M7           = 1U,  /**< ARM Cortex-M7 RDC Master */
+    kRDC_Reserved0           = 2U,  /**< Reserved */
+    kRDC_Master_SDMA3_PERIPH = 3U,  /**< SDMA3 PERIPHERAL RDC Master */
+    kRDC_Reserved1           = 4U,  /**< Reserved */
+    kRDC_Master_LCDIF        = 5U,  /**< LCDIF RDC Master */
+    kRDC_Master_ISI          = 6U,  /**< ISI PORT RDC Master */
+    kRDC_Master_SDMA3_BURST  = 7U,  /**< SDMA3 BURST RDC Master */
+    kRDC_Master_Coresight    = 8U,  /**< CORESIGHT RDC Master */
+    kRDC_Master_DAP          = 9U,  /**< DAP RDC Master */
+    kRDC_Master_CAAM         = 10U, /**< CAAM RDC Master */
+    kRDC_Master_SDMA1_PERIPH = 11U, /**< SDMA1 PERIPHERAL RDC Master */
+    kRDC_Master_SDMA1_BURST  = 12U, /**< SDMA1 BURST RDC Master */
+    kRDC_Master_APBHDMA      = 13U, /**< APBH DMA RDC Master */
+    kRDC_Master_RAWNAND      = 14U, /**< RAW NAND RDC Master */
+    kRDC_Master_USDHC1       = 15U, /**< USDHC1 RDC Master */
+    kRDC_Master_USDHC2       = 16U, /**< USDHC2 RDC Master */
+    kRDC_Master_USDHC3       = 17U, /**< USDHC3 RDC Master */
+    kRDC_Master_GPU          = 18U, /**< GPU RDC Master */
+    kRDC_Master_USB1         = 19U, /**< USB1 RDC Master */
+    kRDC_Reserved2           = 20U, /**< Reserved */
+    kRDC_Master_TESTPORT     = 21U, /**< TESTPORT RDC Master */
+    kRDC_Master_ENET1TX      = 22U, /**< ENET1 TX RDC Master */
+    kRDC_Master_ENET1RX      = 23U, /**< ENET1 RX RDC Master */
+    kRDC_Master_SDMA2_PERIPH = 24U, /**< SDMA2 PERIPH RDC Master */
+    kRDC_Master_SDMA2_BURST  = 24U, /**< SDMA2 BURST RDC Master */
+    kRDC_Master_SDMA2_SPBA2  = 24U, /**< SDMA2 to SPBA2 RDC Master */
+    kRDC_Master_SDMA3_SPBA2  = 25U, /**< SDMA3 to SPBA2 RDC Master */
+    kRDC_Master_SDMA1_SPBA1  = 26U, /**< SDMA1 to SPBA1 RDC Master */
+} rdc_master_t;
+typedef enum _rdc_mem
+{
+    kRDC_Mem_MRC0_0 = 0U, /**< DRAM. Region resolution 4KB. */
+    kRDC_Mem_MRC0_1 = 1U,
+    kRDC_Mem_MRC0_2 = 2U,
+    kRDC_Mem_MRC0_3 = 3U,
+    kRDC_Mem_MRC0_4 = 4U,
+    kRDC_Mem_MRC0_5 = 5U,
+    kRDC_Mem_MRC0_6 = 6U,
+    kRDC_Mem_MRC0_7 = 7U,
+    kRDC_Mem_MRC1_0 = 8U, /**< QSPI. Region resolution 4KB. */
+    kRDC_Mem_MRC1_1 = 9U,
+    kRDC_Mem_MRC1_2 = 10U,
+    kRDC_Mem_MRC1_3 = 11U,
+    kRDC_Mem_MRC1_4 = 12U,
+    kRDC_Mem_MRC1_5 = 13U,
+    kRDC_Mem_MRC1_6 = 14U,
+    kRDC_Mem_MRC1_7 = 15U,
+    kRDC_Mem_MRC2_0 = 16U, /**< OCRAM. Region resolution 128B. */
+    kRDC_Mem_MRC2_1 = 17U,
+    kRDC_Mem_MRC2_2 = 18U,
+    kRDC_Mem_MRC2_3 = 19U,
+    kRDC_Mem_MRC2_4 = 20U,
+    kRDC_Mem_MRC3_0 = 21U, /**< OCRAM_S. Region resolution 128B. */
+    kRDC_Mem_MRC3_1 = 22U,
+    kRDC_Mem_MRC3_2 = 23U,
+    kRDC_Mem_MRC3_3 = 24U,
+    kRDC_Mem_MRC3_4 = 25U,
+    kRDC_Mem_MRC4_0 = 26U, /**< TCM. Region resolution 128B. */
+    kRDC_Mem_MRC4_1 = 27U,
+    kRDC_Mem_MRC4_2 = 28U,
+    kRDC_Mem_MRC4_3 = 29U,
+    kRDC_Mem_MRC4_4 = 30U,
+    kRDC_Mem_MRC5_0 = 31U, /**< GIC. Region resolution 4KB. */
+    kRDC_Mem_MRC5_1 = 32U,
+    kRDC_Mem_MRC5_2 = 33U,
+    kRDC_Mem_MRC5_3 = 34U,
+    kRDC_Mem_MRC6_0 = 35U, /**< GPU. Region resolution 4KB. */
+    kRDC_Mem_MRC6_1 = 36U,
+    kRDC_Mem_MRC6_2 = 37U,
+    kRDC_Mem_MRC6_3 = 38U,
+    kRDC_Mem_MRC6_4 = 39U,
+    kRDC_Mem_MRC6_5 = 40U,
+    kRDC_Mem_MRC6_6 = 41U,
+    kRDC_Mem_MRC6_7 = 42U,
+    kRDC_Mem_MRC7_0 = 43U, /**< DEBUG(DAP). Region resolution 4KB. */
+    kRDC_Mem_MRC7_1 = 44U,
+    kRDC_Mem_MRC7_2 = 45U,
+    kRDC_Mem_MRC7_3 = 46U,
+    kRDC_Mem_MRC8_0 = 47U, /**< DDRC(REG). Region resolution 4KB. */
+    kRDC_Mem_MRC8_1 = 48U,
+    kRDC_Mem_MRC8_2 = 49U,
+    kRDC_Mem_MRC8_3 = 50U,
+    kRDC_Mem_MRC8_4 = 51U,
+} rdc_mem_t;
+typedef enum _rdc_periph
+{
+    kRDC_Periph_GPIO1            = 0U,   /**< GPIO1 RDC Peripheral */
+    kRDC_Periph_GPIO2            = 1U,   /**< GPIO2 RDC Peripheral */
+    kRDC_Periph_GPIO3            = 2U,   /**< GPIO3 RDC Peripheral */
+    kRDC_Periph_GPIO4            = 3U,   /**< GPIO4 RDC Peripheral */
+    kRDC_Periph_GPIO5            = 4U,   /**< GPIO5 RDC Peripheral */
+    kRDC_Periph_ANA_TSENSOR      = 6U,   /**< ANA_TSENSOR RDC Peripheral */
+    kRDC_Periph_ANA_OSC          = 7U,   /**< ANA_OSC RDC Peripheral */
+    kRDC_Periph_WDOG1            = 8U,   /**< WDOG1 RDC Peripheral */
+    kRDC_Periph_WDOG2            = 9U,   /**< WDOG2 RDC Peripheral */
+    kRDC_Periph_WDOG3            = 10U,  /**< WDOG3 RDC Peripheral */
+    kRDC_Periph_SDMA3            = 11U,  /**< SDMA3 RDC Peripheral */
+    kRDC_Periph_SDMA2            = 12U,  /**< SDMA2 RDC Peripheral */
+    kRDC_Periph_GPT1             = 13U,  /**< GPT1 RDC Peripheral */
+    kRDC_Periph_GPT2             = 14U,  /**< GPT2 RDC Peripheral */
+    kRDC_Periph_GPT3             = 15U,  /**< GPT3 RDC Peripheral */
+    kRDC_Periph_ROMCP            = 17U,  /**< ROMCP RDC Peripheral */
+    kRDC_Periph_IOMUXC           = 19U,  /**< IOMUXC RDC Peripheral */
+    kRDC_Periph_IOMUXC_GPR       = 20U,  /**< IOMUXC_GPR RDC Peripheral */
+    kRDC_Periph_OCOTP_CTRL       = 21U,  /**< OCOTP_CTRL RDC Peripheral */
+    kRDC_Periph_ANA_PLL          = 22U,  /**< ANA_PLL RDC Peripheral */
+    kRDC_Periph_SNVS_HP          = 23U,  /**< SNVS_HP GPR RDC Peripheral */
+    kRDC_Periph_CCM              = 24U,  /**< CCM RDC Peripheral */
+    kRDC_Periph_SRC              = 25U,  /**< SRC RDC Peripheral */
+    kRDC_Periph_GPC              = 26U,  /**< GPC RDC Peripheral */
+    kRDC_Periph_SEMAPHORE1       = 27U,  /**< SEMAPHORE1 RDC Peripheral */
+    kRDC_Periph_SEMAPHORE2       = 28U,  /**< SEMAPHORE2 RDC Peripheral */
+    kRDC_Periph_RDC              = 29U,  /**< RDC RDC Peripheral */
+    kRDC_Periph_CSU              = 30U,  /**< CSU RDC Peripheral */
+    kRDC_Periph_LCDIF            = 32U,  /**< LCDIF RDC Peripheral */
+    kRDC_Periph_MIPI_DSI         = 33U,  /**< MIPI_DSI RDC Peripheral */
+    kRDC_Periph_ISI              = 34U,  /**< ISI RDC Peripheral */
+    kRDC_Periph_MIPI_CSI         = 35U,  /**< MIPI_CSI RDC Peripheral */
+    kRDC_Periph_USB1             = 36U,  /**< USB1 RDC Peripheral */
+    kRDC_Periph_PWM1             = 38U,  /**< PWM1 RDC Peripheral */
+    kRDC_Periph_PWM2             = 39U,  /**< PWM2 RDC Peripheral */
+    kRDC_Periph_PWM3             = 40U,  /**< PWM3 RDC Peripheral */
+    kRDC_Periph_PWM4             = 41U,  /**< PWM4 RDC Peripheral */
+    kRDC_Periph_SYS_COUNTER_RD   = 42U,  /**< System counter read RDC Peripheral */
+    kRDC_Periph_SYS_COUNTER_CMP  = 43U,  /**< System counter compare RDC Peripheral */
+    kRDC_Periph_SYS_COUNTER_CTRL = 44U,  /**< System counter control RDC Peripheral */
+    kRDC_Periph_GPT6             = 46U,  /**< GPT6 RDC Peripheral */
+    kRDC_Periph_GPT5             = 47U,  /**< GPT5 RDC Peripheral */
+    kRDC_Periph_GPT4             = 48U,  /**< GPT4 RDC Peripheral */
+    kRDC_Periph_TZASC            = 56U,  /**< TZASC RDC Peripheral */
+    kRDC_Periph_PERFMON1         = 60U,  /**< PERFMON1 RDC Peripheral */
+    kRDC_Periph_PERFMON2         = 61U,  /**< PERFMON2 RDC Peripheral */
+    kRDC_Periph_PLATFORM_CTRL    = 62U,  /**< PLATFORM_CTRL RDC Peripheral */
+    kRDC_Periph_QOSC             = 63U,  /**< QOSC RDC Peripheral */
+    kRDC_Periph_I2C1             = 66U,  /**< I2C1 RDC Peripheral */
+    kRDC_Periph_I2C2             = 67U,  /**< I2C2 RDC Peripheral */
+    kRDC_Periph_I2C3             = 68U,  /**< I2C3 RDC Peripheral */
+    kRDC_Periph_I2C4             = 69U,  /**< I2C4 RDC Peripheral */
+    kRDC_Periph_UART4            = 70U,  /**< UART4 RDC Peripheral */
+    kRDC_Periph_MU_A             = 74U,  /**< MU_A RDC Peripheral */
+    kRDC_Periph_MU_B             = 75U,  /**< MU_B RDC Peripheral */
+    kRDC_Periph_SEMAPHORE_HS     = 76U,  /**< SEMAPHORE_HS RDC Peripheral */
+    kRDC_Periph_SAI2             = 79U,  /**< SAI2 RDC Peripheral */
+    kRDC_Periph_SAI3             = 80U,  /**< SAI3 RDC Peripheral */
+    kRDC_Periph_SAI5             = 82U,  /**< SAI5 RDC Peripheral */
+    kRDC_Periph_SAI6             = 83U,  /**< SAI6 RDC Peripheral */
+    kRDC_Periph_USDHC1           = 84U,  /**< USDHC1 RDC Peripheral */
+    kRDC_Periph_USDHC2           = 85U,  /**< USDHC2 RDC Peripheral */
+    kRDC_Periph_USDHC3           = 86U,  /**< USDHC3 RDC Peripheral */
+    kRDC_Periph_SAI7             = 87U,  /**< SAI7 RDC Peripheral */
+    kRDC_Periph_SPBA2            = 90U,  /**< SPBA2 RDC Peripheral */
+    kRDC_Periph_QSPI             = 91U,  /**< QSPI RDC Peripheral */
+    kRDC_Periph_SDMA1            = 93U,  /**< SDMA1 RDC Peripheral */
+    kRDC_Periph_ENET1            = 94U,  /**< ENET1 RDC Peripheral */
+    kRDC_Periph_SPDIF1           = 97U,  /**< SPDIF1 RDC Peripheral */
+    kRDC_Periph_ECSPI1           = 98U,  /**< ECSPI1 RDC Peripheral */
+    kRDC_Periph_ECSPI2           = 99U,  /**< ECSPI2 RDC Peripheral */
+    kRDC_Periph_ECSPI3           = 100U, /**< ECSPI3 RDC Peripheral */
+    kRDC_Periph_MICFIL           = 101U, /**< MICFIL RDC Peripheral */
+    kRDC_Periph_UART1            = 102U, /**< UART1 RDC Peripheral */
+    kRDC_Periph_UART3            = 104U, /**< UART3 RDC Peripheral */
+    kRDC_Periph_UART2            = 105U, /**< UART2 RDC Peripheral */
+    kRDC_Periph_ASRC             = 107U, /**< ASRC RDC Peripheral */
+    kRDC_Periph_SPBA1            = 111U, /**< SPBA1 RDC Peripheral */
+    kRDC_Periph_CAAM             = 114U, /**< CAAM RDC Peripheral */
+} rdc_periph_t;
+/* @} */
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+/*
+** Start of section using anonymous unions
+*/
+#if defined(__ARMCC_VERSION)
+#if (__ARMCC_VERSION >= 6010050)
+#pragma clang diagnostic push
+#else
+#pragma push
+#pragma anon_unions
+#endif
+#elif defined(__GNUC__)
+/* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+#pragma language = extended
+#else
+#error Not supported compiler type
+#endif
+/* ----------------------------------------------------------------------------
+   -- AIPSTZ Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
+ * @{
+ */
+/** AIPSTZ - Register Layout Typedef */
+typedef struct
+{
+    __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */
+    uint8_t RESERVED_0[60];
+    __IO uint32_t OPACR;  /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */
+    __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */
+    __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */
+    __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */
+    __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */
+} AIPSTZ_Type;
+/* ----------------------------------------------------------------------------
+   -- AIPSTZ Register Masks
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
+ * @{
+ */
+/*! @name MPR - Master Priviledge Registers */
+/*! @{ */
+#define AIPSTZ_MPR_MPROT5_MASK (0xF00U)
+#define AIPSTZ_MPR_MPROT5_SHIFT (8U)
+/*! MPROT5
+ *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of
+ * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access
+ * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses.
+ *  0bxx1x..This master is trusted for write accesses.
+ *  0bx0xx..This master is not trusted for read accesses.
+ *  0bx1xx..This master is trusted for read accesses.
+ *  0b1xxx..Write accesses from this master are allowed to be buffered
+ */
+#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
+#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
+#define AIPSTZ_MPR_MPROT3_SHIFT (16U)
+/*! MPROT3
+ *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of
+ * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access
+ * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses.
+ *  0bxx1x..This master is trusted for write accesses.
+ *  0bx0xx..This master is not trusted for read accesses.
+ *  0bx1xx..This master is trusted for read accesses.
+ *  0b1xxx..Write accesses from this master are allowed to be buffered
+ */
+#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
+#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
+#define AIPSTZ_MPR_MPROT2_SHIFT (20U)
+/*! MPROT2
+ *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of
+ * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access
+ * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses.
+ *  0bxx1x..This master is trusted for write accesses.
+ *  0bx0xx..This master is not trusted for read accesses.
+ *  0bx1xx..This master is trusted for read accesses.
+ *  0b1xxx..Write accesses from this master are allowed to be buffered
+ */
+#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
+#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
+#define AIPSTZ_MPR_MPROT1_SHIFT (24U)
+/*! MPROT1
+ *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of
+ * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access
+ * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses.
+ *  0bxx1x..This master is trusted for write accesses.
+ *  0bx0xx..This master is not trusted for read accesses.
+ *  0bx1xx..This master is trusted for read accesses.
+ *  0b1xxx..Write accesses from this master are allowed to be buffered
+ */
+#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
+#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
+#define AIPSTZ_MPR_MPROT0_SHIFT (28U)
+/*! MPROT0
+ *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of
+ * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access
+ * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses.
+ *  0bxx1x..This master is trusted for write accesses.
+ *  0bx0xx..This master is not trusted for read accesses.
+ *  0bx1xx..This master is trusted for read accesses.
+ *  0b1xxx..Write accesses from this master are allowed to be buffered
+ */
+#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
+/*! @} */
+/*! @name OPACR - Off-Platform Peripheral Access Control Registers */
+/*! @{ */
+#define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
+#define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
+/*! OPAC7
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
+#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
+#define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
+/*! OPAC6
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
+#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
+#define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
+/*! OPAC5
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
+#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
+#define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
+/*! OPAC4
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
+#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
+#define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
+/*! OPAC3
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
+#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
+#define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
+/*! OPAC2
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
+#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
+#define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
+/*! OPAC1
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
+#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
+#define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
+/*! OPAC0
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
+/*! @} */
+/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */
+/*! @{ */
+#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
+#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
+/*! OPAC15
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC15(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
+#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
+#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
+/*! OPAC14
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC14(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
+#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
+#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
+/*! OPAC13
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC13(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
+#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
+#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
+/*! OPAC12
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC12(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
+#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
+#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
+/*! OPAC11
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC11(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
+#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
+#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
+/*! OPAC10
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC10(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
+#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
+#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
+/*! OPAC9
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
+#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
+#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
+/*! OPAC8
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
+/*! @} */
+/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */
+/*! @{ */
+#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
+#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
+/*! OPAC23
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC23(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
+#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
+#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
+/*! OPAC22
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC22(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
+#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
+#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
+/*! OPAC21
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC21(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
+#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
+#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
+/*! OPAC20
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC20(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
+#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
+#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
+/*! OPAC19
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC19(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
+#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
+#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
+/*! OPAC18
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC18(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
+#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
+#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
+/*! OPAC17
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC17(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
+#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
+#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
+/*! OPAC16
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC16(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
+/*! @} */
+/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */
+/*! @{ */
+#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
+#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
+/*! OPAC31
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC31(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
+#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
+#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
+/*! OPAC30
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC30(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
+#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
+#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
+/*! OPAC29
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC29(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
+#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
+#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
+/*! OPAC28
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC28(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
+#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
+#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
+/*! OPAC27
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC27(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
+#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
+#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
+/*! OPAC26
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC26(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
+#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
+#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
+/*! OPAC25
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC25(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
+#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
+#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
+/*! OPAC24
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC24(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
+/*! @} */
+/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */
+/*! @{ */
+#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
+#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
+/*! OPAC33
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR4_OPAC33(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
+#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
+#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
+/*! OPAC32
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR4_OPAC32(x) \
+    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
+/*! @} */
+/*!
+ * @}
+ */ /* end of group AIPSTZ_Register_Masks */
+/* AIPSTZ - Peripheral instance base addresses */
+/** Peripheral AIPSTZ base address */
+#define AIPSTZ_BASE (0x301F0000u)
+/** Peripheral AIPSTZ base pointer */
+#define AIPSTZ ((AIPSTZ_Type *)AIPSTZ_BASE)
+/** Array initializer of AIPSTZ peripheral base addresses */
+#define AIPSTZ_BASE_ADDRS \
+    {                     \
+        AIPSTZ_BASE       \
+    }
+/** Array initializer of AIPSTZ peripheral base pointers */
+#define AIPSTZ_BASE_PTRS \
+    {                    \
+        AIPSTZ           \
+    }
+/*!
+ * @}
+ */ /* end of group AIPSTZ_Peripheral_Access_Layer */
+/* ----------------------------------------------------------------------------
+   -- APBH Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer
+ * @{
+ */
+/** APBH - Register Layout Typedef */
+typedef struct
+{
+    __IO uint32_t CTRL0;            /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */
+    __IO uint32_t CTRL0_SET;        /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */
+    __IO uint32_t CTRL0_CLR;        /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */
+    __IO uint32_t CTRL0_TOG;        /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */
+    __IO uint32_t CTRL1;            /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */
+    __IO uint32_t CTRL1_SET;        /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */
+    __IO uint32_t CTRL1_CLR;        /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */
+    __IO uint32_t CTRL1_TOG;        /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */
+    __IO uint32_t CTRL2;            /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */
+    __IO uint32_t CTRL2_SET;        /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */
+    __IO uint32_t CTRL2_CLR;        /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */
+    __IO uint32_t CTRL2_TOG;        /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */
+    __IO uint32_t CHANNEL_CTRL;     /**< AHB to APBH Bridge Channel Register, offset: 0x30 */
+    __IO uint32_t CHANNEL_CTRL_SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */
+    __IO uint32_t CHANNEL_CTRL_CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */
+    __IO uint32_t CHANNEL_CTRL_TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */
+    __I uint32_t DEVSEL;            /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */
+    uint8_t RESERVED_0[12];
+    __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */
+    uint8_t RESERVED_1[12];
+    __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */
+    uint8_t RESERVED_2[156];
+    struct
+    {                             /* offset: 0x100, array step: 0x70 */
+        __I uint32_t CH_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, array offset: 0x100, array
+                                     step: 0x70 */
+        uint8_t RESERVED_0[12];
+        __IO uint32_t
+            CH_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, array offset: 0x110, array step: 0x70 */
+        uint8_t RESERVED_1[12];
+        __I uint32_t CH_CMD; /**< APBH DMA Channel n Command Register, array offset: 0x120, array step: 0x70 */
+        uint8_t RESERVED_2[12];
+        __I uint32_t CH_BAR; /**< APBH DMA Channel n Buffer Address Register, array offset: 0x130, array step: 0x70 */
+        uint8_t RESERVED_3[12];
+        __IO uint32_t CH_SEMA; /**< APBH DMA Channel n Semaphore Register, array offset: 0x140, array step: 0x70 */
+        uint8_t RESERVED_4[12];
+        __I uint32_t
+            CH_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x150, array step: 0x70 */
+        uint8_t RESERVED_5[12];
+        __I uint32_t
+            CH_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */
+        uint8_t RESERVED_6[12];
+    } CH_CFGn[16];
+    __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */
+} APBH_Type;
+/* ----------------------------------------------------------------------------
+   -- APBH Register Masks
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup APBH_Register_Masks APBH Register Masks
+ * @{
+ */
+/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */
+/*! @{ */
+#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU)
+#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U)
+/*! CLKGATE_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CTRL0_CLKGATE_CHANNEL(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK)
+#define APBH_CTRL0_RSVD0_MASK (0xFFF0000U)
+#define APBH_CTRL0_RSVD0_SHIFT (16U)
+#define APBH_CTRL0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_RSVD0_SHIFT)) & APBH_CTRL0_RSVD0_MASK)
+#define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U)
+#define APBH_CTRL0_APB_BURST_EN_SHIFT (28U)
+#define APBH_CTRL0_APB_BURST_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK)
+#define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U)
+#define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U)
+#define APBH_CTRL0_AHB_BURST8_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK)
+#define APBH_CTRL0_CLKGATE_MASK (0x40000000U)
+#define APBH_CTRL0_CLKGATE_SHIFT (30U)
+#define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK)
+#define APBH_CTRL0_SFTRST_MASK (0x80000000U)
+#define APBH_CTRL0_SFTRST_SHIFT (31U)
+#define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK)
+/*! @} */
+/*! @name CTRL0_SET - AHB to APBH Bridge Control and Status Register 0 */
+/*! @{ */
+#define APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK (0xFFFFU)
+#define APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT (0U)
+/*! CLKGATE_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CTRL0_SET_CLKGATE_CHANNEL(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK)
+#define APBH_CTRL0_SET_RSVD0_MASK (0xFFF0000U)
+#define APBH_CTRL0_SET_RSVD0_SHIFT (16U)
+#define APBH_CTRL0_SET_RSVD0(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_RSVD0_SHIFT)) & APBH_CTRL0_SET_RSVD0_MASK)
+#define APBH_CTRL0_SET_APB_BURST_EN_MASK (0x10000000U)
+#define APBH_CTRL0_SET_APB_BURST_EN_SHIFT (28U)
+#define APBH_CTRL0_SET_APB_BURST_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_APB_BURST_EN_SHIFT)) & APBH_CTRL0_SET_APB_BURST_EN_MASK)
+#define APBH_CTRL0_SET_AHB_BURST8_EN_MASK (0x20000000U)
+#define APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT (29U)
+#define APBH_CTRL0_SET_AHB_BURST8_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_SET_AHB_BURST8_EN_MASK)
+#define APBH_CTRL0_SET_CLKGATE_MASK (0x40000000U)
+#define APBH_CTRL0_SET_CLKGATE_SHIFT (30U)
+#define APBH_CTRL0_SET_CLKGATE(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_SHIFT)) & APBH_CTRL0_SET_CLKGATE_MASK)
+#define APBH_CTRL0_SET_SFTRST_MASK (0x80000000U)
+#define APBH_CTRL0_SET_SFTRST_SHIFT (31U)
+#define APBH_CTRL0_SET_SFTRST(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_SFTRST_SHIFT)) & APBH_CTRL0_SET_SFTRST_MASK)
+/*! @} */
+/*! @name CTRL0_CLR - AHB to APBH Bridge Control and Status Register 0 */
+/*! @{ */
+#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK (0xFFFFU)
+#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT (0U)
+/*! CLKGATE_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CTRL0_CLR_CLKGATE_CHANNEL(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK)
+#define APBH_CTRL0_CLR_RSVD0_MASK (0xFFF0000U)
+#define APBH_CTRL0_CLR_RSVD0_SHIFT (16U)
+#define APBH_CTRL0_CLR_RSVD0(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_RSVD0_SHIFT)) & APBH_CTRL0_CLR_RSVD0_MASK)
+#define APBH_CTRL0_CLR_APB_BURST_EN_MASK (0x10000000U)
+#define APBH_CTRL0_CLR_APB_BURST_EN_SHIFT (28U)
+#define APBH_CTRL0_CLR_APB_BURST_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_APB_BURST_EN_SHIFT)) & APBH_CTRL0_CLR_APB_BURST_EN_MASK)
+#define APBH_CTRL0_CLR_AHB_BURST8_EN_MASK (0x20000000U)
+#define APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT (29U)
+#define APBH_CTRL0_CLR_AHB_BURST8_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_CLR_AHB_BURST8_EN_MASK)
+#define APBH_CTRL0_CLR_CLKGATE_MASK (0x40000000U)
+#define APBH_CTRL0_CLR_CLKGATE_SHIFT (30U)
+#define APBH_CTRL0_CLR_CLKGATE(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_MASK)
+#define APBH_CTRL0_CLR_SFTRST_MASK (0x80000000U)
+#define APBH_CTRL0_CLR_SFTRST_SHIFT (31U)
+#define APBH_CTRL0_CLR_SFTRST(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_SFTRST_SHIFT)) & APBH_CTRL0_CLR_SFTRST_MASK)
+/*! @} */
+/*! @name CTRL0_TOG - AHB to APBH Bridge Control and Status Register 0 */
+/*! @{ */
+#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK (0xFFFFU)
+#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT (0U)
+/*! CLKGATE_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CTRL0_TOG_CLKGATE_CHANNEL(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK)
+#define APBH_CTRL0_TOG_RSVD0_MASK (0xFFF0000U)
+#define APBH_CTRL0_TOG_RSVD0_SHIFT (16U)
+#define APBH_CTRL0_TOG_RSVD0(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_RSVD0_SHIFT)) & APBH_CTRL0_TOG_RSVD0_MASK)
+#define APBH_CTRL0_TOG_APB_BURST_EN_MASK (0x10000000U)
+#define APBH_CTRL0_TOG_APB_BURST_EN_SHIFT (28U)
+#define APBH_CTRL0_TOG_APB_BURST_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_APB_BURST_EN_SHIFT)) & APBH_CTRL0_TOG_APB_BURST_EN_MASK)
+#define APBH_CTRL0_TOG_AHB_BURST8_EN_MASK (0x20000000U)
+#define APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT (29U)
+#define APBH_CTRL0_TOG_AHB_BURST8_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_TOG_AHB_BURST8_EN_MASK)
+#define APBH_CTRL0_TOG_CLKGATE_MASK (0x40000000U)
+#define APBH_CTRL0_TOG_CLKGATE_SHIFT (30U)
+#define APBH_CTRL0_TOG_CLKGATE(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_MASK)
+#define APBH_CTRL0_TOG_SFTRST_MASK (0x80000000U)
+#define APBH_CTRL0_TOG_SFTRST_SHIFT (31U)
+#define APBH_CTRL0_TOG_SFTRST(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_SFTRST_SHIFT)) & APBH_CTRL0_TOG_SFTRST_MASK)
+/*! @} */
+/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */
+/*! @{ */
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK)
+/*! @} */
+/*! @name CTRL1_SET - AHB to APBH Bridge Control and Status Register 1 */
+/*! @{ */
+#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK (0x1U)
+#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT (0U)
+#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK (0x2U)
+#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT (1U)
+#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK (0x4U)
+#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT (2U)
+#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK (0x8U)
+#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT (3U)
+#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK (0x10U)
+#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT (4U)
+#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK (0x20U)
+#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT (5U)
+#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK (0x40U)
+#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT (6U)
+#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK (0x80U)
+#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT (7U)
+#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK (0x100U)
+#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT (8U)
+#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK (0x200U)
+#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT (9U)
+#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK (0x400U)
+#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT (10U)
+#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK (0x800U)
+#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT (11U)
+#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
+#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT (12U)
+#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
+#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT (13U)
+#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
+#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT (14U)
+#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
+#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT (15U)
+#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
+#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
+#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
+#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
+#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
+#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
+#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
+#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
+#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
+#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
+#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
+#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
+#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
+#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
+#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
+#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
+#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
+#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
+#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
+#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
+#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
+#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
+#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
+#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
+#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
+#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
+#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
+#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
+#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
+#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
+#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
+#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
+#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK)
+/*! @} */
+/*! @name CTRL1_CLR - AHB to APBH Bridge Control and Status Register 1 */
+/*! @{ */
+#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK (0x1U)
+#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT (0U)
+#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK (0x2U)
+#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT (1U)
+#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK (0x4U)
+#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT (2U)
+#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK (0x8U)
+#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT (3U)
+#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK (0x10U)
+#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT (4U)
+#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK (0x20U)
+#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT (5U)
+#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK (0x40U)
+#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT (6U)
+#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK (0x80U)
+#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT (7U)
+#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK (0x100U)
+#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT (8U)
+#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK (0x200U)
+#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT (9U)
+#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK (0x400U)
+#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT (10U)
+#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK (0x800U)
+#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT (11U)
+#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
+#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT (12U)
+#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
+#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT (13U)
+#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
+#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT (14U)
+#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
+#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT (15U)
+#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
+#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
+#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
+#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
+#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
+#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
+#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
+#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
+#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
+#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
+#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
+#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
+#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
+#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
+#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
+#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
+#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
+#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
+#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
+#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
+#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
+#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
+#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
+#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
+#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
+#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
+#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
+#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
+#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
+#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
+#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
+#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
+#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK)
+/*! @} */
+/*! @name CTRL1_TOG - AHB to APBH Bridge Control and Status Register 1 */
+/*! @{ */
+#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK (0x1U)
+#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT (0U)
+#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK (0x2U)
+#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT (1U)
+#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK (0x4U)
+#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT (2U)
+#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK (0x8U)
+#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT (3U)
+#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK (0x10U)
+#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT (4U)
+#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK (0x20U)
+#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT (5U)
+#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK (0x40U)
+#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT (6U)
+#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK (0x80U)
+#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT (7U)
+#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK (0x100U)
+#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT (8U)
+#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK (0x200U)
+#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT (9U)
+#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK (0x400U)
+#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT (10U)
+#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK (0x800U)
+#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT (11U)
+#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
+#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT (12U)
+#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
+#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT (13U)
+#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
+#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT (14U)
+#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
+#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT (15U)
+#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
+#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
+#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
+#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
+#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
+#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
+#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
+#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
+#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
+#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
+#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
+#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
+#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
+#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
+#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
+#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
+#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
+#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
+#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
+#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
+#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
+#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
+#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
+#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
+#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
+#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
+#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
+#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
+#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
+#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
+#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
+#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
+#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & \
+     APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK)
+/*! @} */
+/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */
+/*! @{ */
+#define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U)
+#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U)
+#define APBH_CTRL2_CH0_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U)
+#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U)
+#define APBH_CTRL2_CH1_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U)
+#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U)
+#define APBH_CTRL2_CH2_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U)
+#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U)
+#define APBH_CTRL2_CH3_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U)
+#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U)
+#define APBH_CTRL2_CH4_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U)
+#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U)
+#define APBH_CTRL2_CH5_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U)
+#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U)
+#define APBH_CTRL2_CH6_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U)
+#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U)
+#define APBH_CTRL2_CH7_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U)
+#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U)
+#define APBH_CTRL2_CH8_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U)
+#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U)
+#define APBH_CTRL2_CH9_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U)
+#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U)
+#define APBH_CTRL2_CH10_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U)
+#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U)
+#define APBH_CTRL2_CH11_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U)
+#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U)
+#define APBH_CTRL2_CH12_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U)
+#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U)
+#define APBH_CTRL2_CH13_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U)
+#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U)
+#define APBH_CTRL2_CH14_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U)
+#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U)
+#define APBH_CTRL2_CH15_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U)
+#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U)
+/*! CH0_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH0_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U)
+#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U)
+/*! CH1_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH1_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U)
+#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U)
+/*! CH2_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH2_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U)
+#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U)
+/*! CH3_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH3_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U)
+#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U)
+/*! CH4_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH4_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U)
+#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U)
+/*! CH5_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH5_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U)
+#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U)
+/*! CH6_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH6_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U)
+#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U)
+/*! CH7_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH7_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U)
+#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U)
+/*! CH8_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH8_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U)
+#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U)
+/*! CH9_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH9_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U)
+#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U)
+/*! CH10_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH10_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U)
+#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U)
+/*! CH11_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH11_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U)
+#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U)
+/*! CH12_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH12_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U)
+#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U)
+/*! CH13_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH13_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U)
+#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U)
+/*! CH14_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH14_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U)
+#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U)
+/*! CH15_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH15_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK)
+/*! @} */
+/*! @name CTRL2_SET - AHB to APBH Bridge Control and Status Register 2 */
+/*! @{ */
+#define APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK (0x1U)
+#define APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT (0U)
+#define APBH_CTRL2_SET_CH0_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK (0x2U)
+#define APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT (1U)
+#define APBH_CTRL2_SET_CH1_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK (0x4U)
+#define APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT (2U)
+#define APBH_CTRL2_SET_CH2_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK (0x8U)
+#define APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT (3U)
+#define APBH_CTRL2_SET_CH3_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK (0x10U)
+#define APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT (4U)
+#define APBH_CTRL2_SET_CH4_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK (0x20U)
+#define APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT (5U)
+#define APBH_CTRL2_SET_CH5_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK (0x40U)
+#define APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT (6U)
+#define APBH_CTRL2_SET_CH6_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK (0x80U)
+#define APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT (7U)
+#define APBH_CTRL2_SET_CH7_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK (0x100U)
+#define APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT (8U)
+#define APBH_CTRL2_SET_CH8_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK (0x200U)
+#define APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT (9U)
+#define APBH_CTRL2_SET_CH9_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK (0x400U)
+#define APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT (10U)
+#define APBH_CTRL2_SET_CH10_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK (0x800U)
+#define APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT (11U)
+#define APBH_CTRL2_SET_CH11_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK (0x1000U)
+#define APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT (12U)
+#define APBH_CTRL2_SET_CH12_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK (0x2000U)
+#define APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT (13U)
+#define APBH_CTRL2_SET_CH13_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK (0x4000U)
+#define APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT (14U)
+#define APBH_CTRL2_SET_CH14_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK (0x8000U)
+#define APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT (15U)
+#define APBH_CTRL2_SET_CH15_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK)
+#define APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK (0x10000U)
+#define APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT (16U)
+/*! CH0_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH0_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK (0x20000U)
+#define APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT (17U)
+/*! CH1_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH1_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK (0x40000U)
+#define APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT (18U)
+/*! CH2_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH2_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK (0x80000U)
+#define APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT (19U)
+/*! CH3_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH3_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK (0x100000U)
+#define APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT (20U)
+/*! CH4_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH4_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK (0x200000U)
+#define APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT (21U)
+/*! CH5_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH5_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK (0x400000U)
+#define APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT (22U)
+/*! CH6_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH6_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK (0x800000U)
+#define APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT (23U)
+/*! CH7_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH7_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK (0x1000000U)
+#define APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT (24U)
+/*! CH8_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH8_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK (0x2000000U)
+#define APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT (25U)
+/*! CH9_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH9_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK (0x4000000U)
+#define APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT (26U)
+/*! CH10_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH10_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK (0x8000000U)
+#define APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT (27U)
+/*! CH11_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH11_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK (0x10000000U)
+#define APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT (28U)
+/*! CH12_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH12_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK (0x20000000U)
+#define APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT (29U)
+/*! CH13_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH13_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK (0x40000000U)
+#define APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT (30U)
+/*! CH14_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH14_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK)
+#define APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK (0x80000000U)
+#define APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT (31U)
+/*! CH15_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_SET_CH15_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK)
+/*! @} */
+/*! @name CTRL2_CLR - AHB to APBH Bridge Control and Status Register 2 */
+/*! @{ */
+#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK (0x1U)
+#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT (0U)
+#define APBH_CTRL2_CLR_CH0_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK (0x2U)
+#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT (1U)
+#define APBH_CTRL2_CLR_CH1_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK (0x4U)
+#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT (2U)
+#define APBH_CTRL2_CLR_CH2_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK (0x8U)
+#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT (3U)
+#define APBH_CTRL2_CLR_CH3_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK (0x10U)
+#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT (4U)
+#define APBH_CTRL2_CLR_CH4_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK (0x20U)
+#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT (5U)
+#define APBH_CTRL2_CLR_CH5_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK (0x40U)
+#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT (6U)
+#define APBH_CTRL2_CLR_CH6_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK (0x80U)
+#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT (7U)
+#define APBH_CTRL2_CLR_CH7_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK (0x100U)
+#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT (8U)
+#define APBH_CTRL2_CLR_CH8_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK (0x200U)
+#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT (9U)
+#define APBH_CTRL2_CLR_CH9_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK (0x400U)
+#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT (10U)
+#define APBH_CTRL2_CLR_CH10_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK (0x800U)
+#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT (11U)
+#define APBH_CTRL2_CLR_CH11_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK (0x1000U)
+#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT (12U)
+#define APBH_CTRL2_CLR_CH12_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK (0x2000U)
+#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT (13U)
+#define APBH_CTRL2_CLR_CH13_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK (0x4000U)
+#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT (14U)
+#define APBH_CTRL2_CLR_CH14_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK (0x8000U)
+#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT (15U)
+#define APBH_CTRL2_CLR_CH15_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK (0x10000U)
+#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT (16U)
+/*! CH0_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH0_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK (0x20000U)
+#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT (17U)
+/*! CH1_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH1_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK (0x40000U)
+#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT (18U)
+/*! CH2_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH2_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK (0x80000U)
+#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT (19U)
+/*! CH3_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH3_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK (0x100000U)
+#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT (20U)
+/*! CH4_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH4_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK (0x200000U)
+#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT (21U)
+/*! CH5_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH5_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK (0x400000U)
+#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT (22U)
+/*! CH6_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH6_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK (0x800000U)
+#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT (23U)
+/*! CH7_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH7_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK (0x1000000U)
+#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT (24U)
+/*! CH8_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH8_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK (0x2000000U)
+#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT (25U)
+/*! CH9_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH9_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK (0x4000000U)
+#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT (26U)
+/*! CH10_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH10_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK (0x8000000U)
+#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT (27U)
+/*! CH11_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH11_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK (0x10000000U)
+#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT (28U)
+/*! CH12_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH12_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK (0x20000000U)
+#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT (29U)
+/*! CH13_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH13_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK (0x40000000U)
+#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT (30U)
+/*! CH14_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH14_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK (0x80000000U)
+#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT (31U)
+/*! CH15_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CLR_CH15_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK)
+/*! @} */
+/*! @name CTRL2_TOG - AHB to APBH Bridge Control and Status Register 2 */
+/*! @{ */
+#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK (0x1U)
+#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT (0U)
+#define APBH_CTRL2_TOG_CH0_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK (0x2U)
+#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT (1U)
+#define APBH_CTRL2_TOG_CH1_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK (0x4U)
+#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT (2U)
+#define APBH_CTRL2_TOG_CH2_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK (0x8U)
+#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT (3U)
+#define APBH_CTRL2_TOG_CH3_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK (0x10U)
+#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT (4U)
+#define APBH_CTRL2_TOG_CH4_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK (0x20U)
+#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT (5U)
+#define APBH_CTRL2_TOG_CH5_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK (0x40U)
+#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT (6U)
+#define APBH_CTRL2_TOG_CH6_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK (0x80U)
+#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT (7U)
+#define APBH_CTRL2_TOG_CH7_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK (0x100U)
+#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT (8U)
+#define APBH_CTRL2_TOG_CH8_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK (0x200U)
+#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT (9U)
+#define APBH_CTRL2_TOG_CH9_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK (0x400U)
+#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT (10U)
+#define APBH_CTRL2_TOG_CH10_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK (0x800U)
+#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT (11U)
+#define APBH_CTRL2_TOG_CH11_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK (0x1000U)
+#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT (12U)
+#define APBH_CTRL2_TOG_CH12_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK (0x2000U)
+#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT (13U)
+#define APBH_CTRL2_TOG_CH13_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK (0x4000U)
+#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT (14U)
+#define APBH_CTRL2_TOG_CH14_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK (0x8000U)
+#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT (15U)
+#define APBH_CTRL2_TOG_CH15_ERROR_IRQ(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK)
+#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK (0x10000U)
+#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT (16U)
+/*! CH0_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH0_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK (0x20000U)
+#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT (17U)
+/*! CH1_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH1_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK (0x40000U)
+#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT (18U)
+/*! CH2_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH2_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK (0x80000U)
+#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT (19U)
+/*! CH3_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH3_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK (0x100000U)
+#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT (20U)
+/*! CH4_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH4_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK (0x200000U)
+#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT (21U)
+/*! CH5_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH5_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK (0x400000U)
+#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT (22U)
+/*! CH6_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH6_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK (0x800000U)
+#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT (23U)
+/*! CH7_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH7_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK (0x1000000U)
+#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT (24U)
+/*! CH8_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH8_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK (0x2000000U)
+#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT (25U)
+/*! CH9_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH9_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK (0x4000000U)
+#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT (26U)
+/*! CH10_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH10_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK (0x8000000U)
+#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT (27U)
+/*! CH11_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH11_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK (0x10000000U)
+#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT (28U)
+/*! CH12_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH12_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK (0x20000000U)
+#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT (29U)
+/*! CH13_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH13_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK (0x40000000U)
+#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT (30U)
+/*! CH14_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH14_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK)
+#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK (0x80000000U)
+#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT (31U)
+/*! CH15_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_TOG_CH15_ERROR_STATUS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK)
+/*! @} */
+/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */
+/*! @{ */
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU)
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U)
+/*! FREEZE_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U)
+/*! RESET_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK)
+/*! @} */
+/*! @name CHANNEL_CTRL_SET - AHB to APBH Bridge Channel Register */
+/*! @{ */
+#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK (0xFFFFU)
+#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT (0U)
+/*! FREEZE_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT)) & \
+     APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK)
+#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK (0xFFFF0000U)
+#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT (16U)
+/*! RESET_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT)) & \
+     APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK)
+/*! @} */
+/*! @name CHANNEL_CTRL_CLR - AHB to APBH Bridge Channel Register */
+/*! @{ */
+#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK (0xFFFFU)
+#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT (0U)
+/*! FREEZE_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT)) & \
+     APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK)
+#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK (0xFFFF0000U)
+#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT (16U)
+/*! RESET_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT)) & \
+     APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK)
+/*! @} */
+/*! @name CHANNEL_CTRL_TOG - AHB to APBH Bridge Channel Register */
+/*! @{ */
+#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK (0xFFFFU)
+#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT (0U)
+/*! FREEZE_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT)) & \
+     APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK)
+#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK (0xFFFF0000U)
+#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT (16U)
+/*! RESET_CHANNEL
+ *  0b0000000000000001..NAND0
+ *  0b0000000000000010..NAND1
+ *  0b0000000000000100..NAND2
+ *  0b0000000000001000..NAND3
+ *  0b0000000000010000..NAND4
+ *  0b0000000000100000..NAND5
+ *  0b0000000001000000..NAND6
+ *  0b0000000010000000..NAND7
+ *  0b0000000100000000..SSP
+ */
+#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT)) & \
+     APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK)
+/*! @} */
+/*! @name DEVSEL - AHB to APBH DMA Device Assignment Register */
+/*! @{ */
+#define APBH_DEVSEL_CH0_MASK (0x3U)
+#define APBH_DEVSEL_CH0_SHIFT (0U)
+#define APBH_DEVSEL_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH0_SHIFT)) & APBH_DEVSEL_CH0_MASK)
+#define APBH_DEVSEL_CH1_MASK (0xCU)
+#define APBH_DEVSEL_CH1_SHIFT (2U)
+#define APBH_DEVSEL_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH1_SHIFT)) & APBH_DEVSEL_CH1_MASK)
+#define APBH_DEVSEL_CH2_MASK (0x30U)
+#define APBH_DEVSEL_CH2_SHIFT (4U)
+#define APBH_DEVSEL_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH2_SHIFT)) & APBH_DEVSEL_CH2_MASK)
+#define APBH_DEVSEL_CH3_MASK (0xC0U)
+#define APBH_DEVSEL_CH3_SHIFT (6U)
+#define APBH_DEVSEL_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH3_SHIFT)) & APBH_DEVSEL_CH3_MASK)
+#define APBH_DEVSEL_CH4_MASK (0x300U)
+#define APBH_DEVSEL_CH4_SHIFT (8U)
+#define APBH_DEVSEL_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH4_SHIFT)) & APBH_DEVSEL_CH4_MASK)
+#define APBH_DEVSEL_CH5_MASK (0xC00U)
+#define APBH_DEVSEL_CH5_SHIFT (10U)
+#define APBH_DEVSEL_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH5_SHIFT)) & APBH_DEVSEL_CH5_MASK)
+#define APBH_DEVSEL_CH6_MASK (0x3000U)
+#define APBH_DEVSEL_CH6_SHIFT (12U)
+#define APBH_DEVSEL_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH6_SHIFT)) & APBH_DEVSEL_CH6_MASK)
+#define APBH_DEVSEL_CH7_MASK (0xC000U)
+#define APBH_DEVSEL_CH7_SHIFT (14U)
+#define APBH_DEVSEL_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH7_SHIFT)) & APBH_DEVSEL_CH7_MASK)
+#define APBH_DEVSEL_CH8_MASK (0x30000U)
+#define APBH_DEVSEL_CH8_SHIFT (16U)
+#define APBH_DEVSEL_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH8_SHIFT)) & APBH_DEVSEL_CH8_MASK)
+#define APBH_DEVSEL_CH9_MASK (0xC0000U)
+#define APBH_DEVSEL_CH9_SHIFT (18U)
+#define APBH_DEVSEL_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH9_SHIFT)) & APBH_DEVSEL_CH9_MASK)
+#define APBH_DEVSEL_CH10_MASK (0x300000U)
+#define APBH_DEVSEL_CH10_SHIFT (20U)
+#define APBH_DEVSEL_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH10_SHIFT)) & APBH_DEVSEL_CH10_MASK)
+#define APBH_DEVSEL_CH11_MASK (0xC00000U)
+#define APBH_DEVSEL_CH11_SHIFT (22U)
+#define APBH_DEVSEL_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH11_SHIFT)) & APBH_DEVSEL_CH11_MASK)
+#define APBH_DEVSEL_CH12_MASK (0x3000000U)
+#define APBH_DEVSEL_CH12_SHIFT (24U)
+#define APBH_DEVSEL_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH12_SHIFT)) & APBH_DEVSEL_CH12_MASK)
+#define APBH_DEVSEL_CH13_MASK (0xC000000U)
+#define APBH_DEVSEL_CH13_SHIFT (26U)
+#define APBH_DEVSEL_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH13_SHIFT)) & APBH_DEVSEL_CH13_MASK)
+#define APBH_DEVSEL_CH14_MASK (0x30000000U)
+#define APBH_DEVSEL_CH14_SHIFT (28U)
+#define APBH_DEVSEL_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH14_SHIFT)) & APBH_DEVSEL_CH14_MASK)
+#define APBH_DEVSEL_CH15_MASK (0xC0000000U)
+#define APBH_DEVSEL_CH15_SHIFT (30U)
+#define APBH_DEVSEL_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH15_SHIFT)) & APBH_DEVSEL_CH15_MASK)
+/*! @} */
+/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */
+/*! @{ */
+#define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U)
+#define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U)
+#define APBH_DMA_BURST_SIZE_CH0(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK)
+#define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU)
+#define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U)
+#define APBH_DMA_BURST_SIZE_CH1(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK)
+#define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U)
+#define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U)
+#define APBH_DMA_BURST_SIZE_CH2(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK)
+#define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U)
+#define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U)
+#define APBH_DMA_BURST_SIZE_CH3(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK)
+#define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U)
+#define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U)
+#define APBH_DMA_BURST_SIZE_CH4(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK)
+#define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U)
+#define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U)
+#define APBH_DMA_BURST_SIZE_CH5(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK)
+#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U)
+#define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U)
+#define APBH_DMA_BURST_SIZE_CH6(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK)
+#define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U)
+#define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U)
+#define APBH_DMA_BURST_SIZE_CH7(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK)
+#define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U)
+#define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U)
+/*! CH8
+ *  0b00..BURST0
+ *  0b01..BURST4
+ *  0b10..BURST8
+ */
+#define APBH_DMA_BURST_SIZE_CH8(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK)
+#define APBH_DMA_BURST_SIZE_CH9_MASK (0xC0000U)
+#define APBH_DMA_BURST_SIZE_CH9_SHIFT (18U)
+#define APBH_DMA_BURST_SIZE_CH9(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH9_SHIFT)) & APBH_DMA_BURST_SIZE_CH9_MASK)
+#define APBH_DMA_BURST_SIZE_CH10_MASK (0x300000U)
+#define APBH_DMA_BURST_SIZE_CH10_SHIFT (20U)
+#define APBH_DMA_BURST_SIZE_CH10(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH10_SHIFT)) & APBH_DMA_BURST_SIZE_CH10_MASK)
+#define APBH_DMA_BURST_SIZE_CH11_MASK (0xC00000U)
+#define APBH_DMA_BURST_SIZE_CH11_SHIFT (22U)
+#define APBH_DMA_BURST_SIZE_CH11(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH11_SHIFT)) & APBH_DMA_BURST_SIZE_CH11_MASK)
+#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3000000U)
+#define APBH_DMA_BURST_SIZE_CH12_SHIFT (24U)
+#define APBH_DMA_BURST_SIZE_CH12(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH12_SHIFT)) & APBH_DMA_BURST_SIZE_CH12_MASK)
+#define APBH_DMA_BURST_SIZE_CH13_MASK (0xC000000U)
+#define APBH_DMA_BURST_SIZE_CH13_SHIFT (26U)
+#define APBH_DMA_BURST_SIZE_CH13(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH13_SHIFT)) & APBH_DMA_BURST_SIZE_CH13_MASK)
+#define APBH_DMA_BURST_SIZE_CH14_MASK (0x30000000U)
+#define APBH_DMA_BURST_SIZE_CH14_SHIFT (28U)
+#define APBH_DMA_BURST_SIZE_CH14(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH14_SHIFT)) & APBH_DMA_BURST_SIZE_CH14_MASK)
+#define APBH_DMA_BURST_SIZE_CH15_MASK (0xC0000000U)
+#define APBH_DMA_BURST_SIZE_CH15_SHIFT (30U)
+#define APBH_DMA_BURST_SIZE_CH15(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH15_SHIFT)) & APBH_DMA_BURST_SIZE_CH15_MASK)
+/*! @} */
+/*! @name DEBUG - AHB to APBH DMA Debug Register */
+/*! @{ */
+#define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U)
+#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U)
+#define APBH_DEBUG_GPMI_ONE_FIFO(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK)
+/*! @} */
+/*! @name CH_CURCMDAR - APBH DMA Channel n Current Command Address Register */
+/*! @{ */
+#define APBH_CH_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
+#define APBH_CH_CURCMDAR_CMD_ADDR_SHIFT (0U)
+#define APBH_CH_CURCMDAR_CMD_ADDR(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_CURCMDAR_CMD_ADDR_MASK)
+/*! @} */
+/* The count of APBH_CH_CURCMDAR */
+#define APBH_CH_CURCMDAR_COUNT (16U)
+/*! @name CH_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
+/*! @{ */
+#define APBH_CH_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
+#define APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT (0U)
+#define APBH_CH_NXTCMDAR_CMD_ADDR(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_NXTCMDAR_CMD_ADDR_MASK)
+/*! @} */
+/* The count of APBH_CH_NXTCMDAR */
+#define APBH_CH_NXTCMDAR_COUNT (16U)
+/*! @name CH_CMD - APBH DMA Channel n Command Register */
+/*! @{ */
+#define APBH_CH_CMD_COMMAND_MASK (0x3U)
+#define APBH_CH_CMD_COMMAND_SHIFT (0U)
+/*! COMMAND
+ *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
+ *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified
+ * number of bytes. 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for
+ * the specified number of bytes. 0b11..Perform any requested PIO word transfers and then perform a conditional branch
+ * to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS
+ * as a chain pointer if the peripheral sense line is false.
+ */
+#define APBH_CH_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_COMMAND_SHIFT)) & APBH_CH_CMD_COMMAND_MASK)
+#define APBH_CH_CMD_CHAIN_MASK (0x4U)
+#define APBH_CH_CMD_CHAIN_SHIFT (2U)
+#define APBH_CH_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CHAIN_SHIFT)) & APBH_CH_CMD_CHAIN_MASK)
+#define APBH_CH_CMD_IRQONCMPLT_MASK (0x8U)
+#define APBH_CH_CMD_IRQONCMPLT_SHIFT (3U)
+#define APBH_CH_CMD_IRQONCMPLT(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_IRQONCMPLT_SHIFT)) & APBH_CH_CMD_IRQONCMPLT_MASK)
+#define APBH_CH_CMD_NANDLOCK_MASK (0x10U)
+#define APBH_CH_CMD_NANDLOCK_SHIFT (4U)
+#define APBH_CH_CMD_NANDLOCK(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDLOCK_SHIFT)) & APBH_CH_CMD_NANDLOCK_MASK)
+#define APBH_CH_CMD_NANDWAIT4READY_MASK (0x20U)
+#define APBH_CH_CMD_NANDWAIT4READY_SHIFT (5U)
+#define APBH_CH_CMD_NANDWAIT4READY(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH_CMD_NANDWAIT4READY_MASK)
+#define APBH_CH_CMD_SEMAPHORE_MASK (0x40U)
+#define APBH_CH_CMD_SEMAPHORE_SHIFT (6U)
+#define APBH_CH_CMD_SEMAPHORE(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_SEMAPHORE_SHIFT)) & APBH_CH_CMD_SEMAPHORE_MASK)
+#define APBH_CH_CMD_WAIT4ENDCMD_MASK (0x80U)
+#define APBH_CH_CMD_WAIT4ENDCMD_SHIFT (7U)
+#define APBH_CH_CMD_WAIT4ENDCMD(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH_CMD_WAIT4ENDCMD_MASK)
+#define APBH_CH_CMD_HALTONTERMINATE_MASK (0x100U)
+#define APBH_CH_CMD_HALTONTERMINATE_SHIFT (8U)
+#define APBH_CH_CMD_HALTONTERMINATE(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH_CMD_HALTONTERMINATE_MASK)
+#define APBH_CH_CMD_CMDWORDS_MASK (0xF000U)
+#define APBH_CH_CMD_CMDWORDS_SHIFT (12U)
+#define APBH_CH_CMD_CMDWORDS(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CMDWORDS_SHIFT)) & APBH_CH_CMD_CMDWORDS_MASK)
+#define APBH_CH_CMD_XFER_COUNT_MASK (0xFFFF0000U)
+#define APBH_CH_CMD_XFER_COUNT_SHIFT (16U)
+#define APBH_CH_CMD_XFER_COUNT(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_XFER_COUNT_SHIFT)) & APBH_CH_CMD_XFER_COUNT_MASK)
+/*! @} */
+/* The count of APBH_CH_CMD */
+#define APBH_CH_CMD_COUNT (16U)
+/*! @name CH_BAR - APBH DMA Channel n Buffer Address Register */
+/*! @{ */
+#define APBH_CH_BAR_ADDRESS_MASK (0xFFFFFFFFU)
+#define APBH_CH_BAR_ADDRESS_SHIFT (0U)
+#define APBH_CH_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_BAR_ADDRESS_SHIFT)) & APBH_CH_BAR_ADDRESS_MASK)
+/*! @} */
+/* The count of APBH_CH_BAR */
+#define APBH_CH_BAR_COUNT (16U)
+/*! @name CH_SEMA - APBH DMA Channel n Semaphore Register */
+/*! @{ */
+#define APBH_CH_SEMA_INCREMENT_SEMA_MASK (0xFFU)
+#define APBH_CH_SEMA_INCREMENT_SEMA_SHIFT (0U)
+#define APBH_CH_SEMA_INCREMENT_SEMA(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH_SEMA_INCREMENT_SEMA_MASK)
+#define APBH_CH_SEMA_PHORE_MASK (0xFF0000U)
+#define APBH_CH_SEMA_PHORE_SHIFT (16U)
+#define APBH_CH_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_PHORE_SHIFT)) & APBH_CH_SEMA_PHORE_MASK)
+/*! @} */
+/* The count of APBH_CH_SEMA */
+#define APBH_CH_SEMA_COUNT (16U)
+/*! @name CH_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
+/*! @{ */
+#define APBH_CH_DEBUG1_STATEMACHINE_MASK (0x1FU)
+#define APBH_CH_DEBUG1_STATEMACHINE_SHIFT (0U)
+/*! STATEMACHINE
+ *  0b00000..This is the idle state of the DMA state machine.
+ *  0b00001..State in which the DMA is waiting to receive the first word of a command.
+ *  0b00010..State in which the DMA is waiting to receive the third word of a command.
+ *  0b00011..State in which the DMA is waiting to receive the second word of a command.
+ *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
+ *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
+ *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the
+ *           PIO words when PIO count is greater than 1.
+ *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
+ *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on
+ * the APB. 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to
+ * complete. 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter
+ * accepts the request from this channel. 0b01101..During DMA Read transfers, the state machine waits in this state
+ * until the AHB master arbiter accepts the request from this channel. 0b01110..Upon completion of the DMA transfers,
+ * this state checks the value of the Chain bit and branches accordingly. 0b01111..The state machine goes to this state
+ * after the DMA transfers are complete, and determines what step to take next. 0b10100..When a terminate signal is set,
+ * the state machine enters this state until the current AHB transfer is completed. 0b10101..When the Wait for Command
+ * End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
+ *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write
+ * to the AHB memory space. 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters
+ * this state and effectively halts. A channel reset is required to exit this state 0b11110..If the Chain bit is a 0,
+ * the state machine enters this state and effectively halts. 0b11111..When the NAND Wait for Ready bit is set, the
+ * state machine enters this state until the GPMI device indicates that the external device is ready.
+ */
+#define APBH_CH_DEBUG1_STATEMACHINE(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH_DEBUG1_STATEMACHINE_MASK)
+#define APBH_CH_DEBUG1_RSVD1_MASK (0xFFFE0U)
+#define APBH_CH_DEBUG1_RSVD1_SHIFT (5U)
+#define APBH_CH_DEBUG1_RSVD1(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RSVD1_SHIFT)) & APBH_CH_DEBUG1_RSVD1_MASK)
+#define APBH_CH_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
+#define APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
+#define APBH_CH_DEBUG1_WR_FIFO_FULL(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_FULL_MASK)
+#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
+#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
+#define APBH_CH_DEBUG1_WR_FIFO_EMPTY(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK)
+#define APBH_CH_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
+#define APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
+#define APBH_CH_DEBUG1_RD_FIFO_FULL(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_FULL_MASK)
+#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
+#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
+#define APBH_CH_DEBUG1_RD_FIFO_EMPTY(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK)
+#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
+#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
+#define APBH_CH_DEBUG1_NEXTCMDADDRVALID(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK)
+#define APBH_CH_DEBUG1_LOCK_MASK (0x2000000U)
+#define APBH_CH_DEBUG1_LOCK_SHIFT (25U)
+#define APBH_CH_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_LOCK_SHIFT)) & APBH_CH_DEBUG1_LOCK_MASK)
+#define APBH_CH_DEBUG1_READY_MASK (0x4000000U)
+#define APBH_CH_DEBUG1_READY_SHIFT (26U)
+#define APBH_CH_DEBUG1_READY(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_READY_SHIFT)) & APBH_CH_DEBUG1_READY_MASK)
+#define APBH_CH_DEBUG1_SENSE_MASK (0x8000000U)
+#define APBH_CH_DEBUG1_SENSE_SHIFT (27U)
+#define APBH_CH_DEBUG1_SENSE(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_SENSE_SHIFT)) & APBH_CH_DEBUG1_SENSE_MASK)
+#define APBH_CH_DEBUG1_END_MASK (0x10000000U)
+#define APBH_CH_DEBUG1_END_SHIFT (28U)
+#define APBH_CH_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_END_SHIFT)) & APBH_CH_DEBUG1_END_MASK)
+#define APBH_CH_DEBUG1_KICK_MASK (0x20000000U)
+#define APBH_CH_DEBUG1_KICK_SHIFT (29U)
+#define APBH_CH_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_KICK_SHIFT)) & APBH_CH_DEBUG1_KICK_MASK)
+#define APBH_CH_DEBUG1_BURST_MASK (0x40000000U)
+#define APBH_CH_DEBUG1_BURST_SHIFT (30U)
+#define APBH_CH_DEBUG1_BURST(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_BURST_SHIFT)) & APBH_CH_DEBUG1_BURST_MASK)
+#define APBH_CH_DEBUG1_REQ_MASK (0x80000000U)
+#define APBH_CH_DEBUG1_REQ_SHIFT (31U)
+#define APBH_CH_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_REQ_SHIFT)) & APBH_CH_DEBUG1_REQ_MASK)
+/*! @} */
+/* The count of APBH_CH_DEBUG1 */
+#define APBH_CH_DEBUG1_COUNT (16U)
+/*! @name CH_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
+/*! @{ */
+#define APBH_CH_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
+#define APBH_CH_DEBUG2_AHB_BYTES_SHIFT (0U)
+#define APBH_CH_DEBUG2_AHB_BYTES(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH_DEBUG2_AHB_BYTES_MASK)
+#define APBH_CH_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
+#define APBH_CH_DEBUG2_APB_BYTES_SHIFT (16U)
+#define APBH_CH_DEBUG2_APB_BYTES(x) \
+    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH_DEBUG2_APB_BYTES_MASK)
+/*! @} */
+/* The count of APBH_CH_DEBUG2 */
+#define APBH_CH_DEBUG2_COUNT (16U)
+/*! @name VERSION - APBH Bridge Version Register */
+/*! @{ */
+#define APBH_VERSION_STEP_MASK (0xFFFFU)
+#define APBH_VERSION_STEP_SHIFT (0U)
+#define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK)
+#define APBH_VERSION_MINOR_MASK (0xFF0000U)
+#define APBH_VERSION_MINOR_SHIFT (16U)
+#define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK)
+#define APBH_VERSION_MAJOR_MASK (0xFF000000U)
+#define APBH_VERSION_MAJOR_SHIFT (24U)
+#define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK)
+/*! @} */
+/*!
+ * @}
+ */ /* end of group APBH_Register_Masks */
+/* APBH - Peripheral instance base addresses */
+/** Peripheral APBH base address */
+#define APBH_BASE (0x33000000u)
+/** Peripheral APBH base pointer */
+#define APBH ((APBH_Type *)APBH_BASE)
+/** Array initializer of APBH peripheral base addresses */
+#define APBH_BASE_ADDRS \
+    {                   \
+        APBH_BASE       \
+    }
+/** Array initializer of APBH peripheral base pointers */
+#define APBH_BASE_PTRS \
+    {                  \
+        APBH           \
+    }
+/** Interrupt vectors for the APBH peripheral type */
+#define APBH_IRQS    \
+    {                \
+        APBHDMA_IRQn \
+    }
+/*!
+ * @}
+ */ /* end of group APBH_Peripheral_Access_Layer */
+/* ----------------------------------------------------------------------------
+   -- ASRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
+ * @{
+ */
+/** ASRC - Register Layout Typedef */
+typedef struct
+{
+    __O uint32_t WRFIFO[4];              /**< ASRC Input Write FIFO, array offset: 0x0, array step: 0x4 */
+    __I uint32_t RDFIFO[4];              /**< ASRC Output Read FIFO, array offset: 0x10, array step: 0x4 */
+    __IO uint32_t CTX_CTRL[4];           /**< ASRC Context Control, array offset: 0x20, array step: 0x4 */
+    __IO uint32_t CTX_CTRL_EXT1[4];      /**< ASRC Context Control Extended 1, array offset: 0x30, array step: 0x4 */
+    __IO uint32_t CTX_CTRL_EXT2[4];      /**< ASRC Context Control Extended 2, array offset: 0x40, array step: 0x4 */
+    __IO uint32_t CTRL_IN_ACCESS[4];     /**< ASRC Control Input Access, array offset: 0x50, array step: 0x4 */
+    __IO uint32_t PROC_CTRL_SLOT0_R0[4]; /**< ASRC Datapath Processor Control Slot0 Register0, array offset: 0x60, array
+                                            step: 0x4 */
+    __IO uint32_t PROC_CTRL_SLOT0_R1[4]; /**< ASRC Datapath Processor Control Slot0 Register1, array offset: 0x70, array
+                                            step: 0x4 */
+    __IO uint32_t PROC_CTRL_SLOT0_R2[4]; /**< ASRC Datapath Processor Control Slot0 Register2, array offset: 0x80, array
+                                            step: 0x4 */
+    __IO uint32_t PROC_CTRL_SLOT0_R3[4]; /**< ASRC Datapath Processor Control Slot0 Register3, array offset: 0x90, array
+                                            step: 0x4 */
+    __IO uint32_t PROC_CTRL_SLOT1_R0[4]; /**< ASRC Datapath Processor Control Slot1 Register0, array offset: 0xA0, array
+                                            step: 0x4 */
+    __IO uint32_t PROC_CTRL_SLOT1_R1[4]; /**< ASRC Datapath Processor Control SLOT1 Register1, array offset: 0xB0, array
+                                            step: 0x4 */
+    __IO uint32_t PROC_CTRL_SLOT1_R2[4]; /**< ASRC Datapath Processor Control SLOT1 Register2, array offset: 0xC0, array
+                                            step: 0x4 */
+    __IO uint32_t PROC_CTRL_SLOT1_R3[4]; /**< ASRC Datapath Processor Control SLOT1 Register3, array offset: 0xD0, array
+                                            step: 0x4 */
+    __IO uint32_t CTX_OUT_CTRL[4];       /**< ASRC Context Output Control, array offset: 0xE0, array step: 0x4 */
+    __IO uint32_t CTRL_OUT_ACCESS[4];    /**< ASRC Control Output Access, array offset: 0xF0, array step: 0x4 */
+    __I uint32_t SAMPLE_FIFO_STATUS[4];  /**< ASRC Sample FIFO Status, array offset: 0x100, array step: 0x4 */
+    struct
+    {                                /* offset: 0x110, array step: 0x8 */
+        __IO uint32_t RS_RATIO_LOW;  /**< ASRC Resampling Ratio Low, array offset: 0x110, array step: 0x8 */
+        __IO uint32_t RS_RATIO_HIGH; /**< ASRC Resampling Ratio High, array offset: 0x114, array step: 0x8 */
+    } RS_RATIO_LOW[4];
+    __IO uint32_t RS_UPDATE_CTRL[4]; /**< ASRC Resampling Ratio Update Control, array offset: 0x130, array step: 0x4 */
+    __IO uint32_t RS_UPDATE_RATE[4]; /**< ASRC Resampling Ratio Update Rate, array offset: 0x140, array step: 0x4 */
+    __IO uint32_t RS_CT_LOW;         /**< ASRC Resampling Center Tap Coefficient Low, offset: 0x150 */
+    __IO uint32_t RS_CT_HIGH;        /**< ASRC Resampling Center Tap Coefficient High, offset: 0x154 */
+    uint8_t RESERVED_0[8];
+    __IO uint32_t PRE_COEFF_FIFO[4];   /**< ASRC Prefilter Coefficient FIFO, array offset: 0x160, array step: 0x4 */
+    __O uint32_t CTX_RS_COEFF_MEM;     /**< ASRC Context Resampling Coefficient Memory, offset: 0x170 */
+    __IO uint32_t CTX_RS_COEFF_CTRL;   /**< ASRC Context Resampling Coefficient Control, offset: 0x174 */
+    __IO uint32_t IRQ_CTRL;            /**< ASRC Interrupt Control, offset: 0x178 */
+    __IO uint32_t IRQ_FLAGS;           /**< ASRC Interrupt Status Flags, offset: 0x17C */
+    __IO uint32_t CHANNEL_STATUS_0[4]; /**< ASRC Channel Status 0, array offset: 0x180, array step: 0x4 */
+    __IO uint32_t CHANNEL_STATUS_1[4]; /**< ASRC Channel Status 1, array offset: 0x190, array step: 0x4 */
+    __IO uint32_t CHANNEL_STATUS_2[4]; /**< ASRC Channel Status 2, array offset: 0x1A0, array step: 0x4 */
+    __IO uint32_t CHANNEL_STATUS_3[4]; /**< ASRC Channel Status 3, array offset: 0x1B0, array step: 0x4 */
+    __IO uint32_t CHANNEL_STATUS_4[4]; /**< ASRC Channel Status 4, array offset: 0x1C0, array step: 0x4 */
+    __IO uint32_t CHANNEL_STATUS_5[4]; /**< ASRC Channel Status 5, array offset: 0x1D0, array step: 0x4 */
+} ASRC_Type;
+/* ----------------------------------------------------------------------------
+   -- ASRC Register Masks
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup ASRC_Register_Masks ASRC Register Masks
+ * @{
+ */
+/*! @name WRFIFO - ASRC Input Write FIFO */
+/*! @{ */
+#define ASRC_WRFIFO_CTX_WR_DATA_MASK (0xFFFFFFFFU)
+#define ASRC_WRFIFO_CTX_WR_DATA_SHIFT (0U)
+#define ASRC_WRFIFO_CTX_WR_DATA(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_WRFIFO_CTX_WR_DATA_SHIFT)) & ASRC_WRFIFO_CTX_WR_DATA_MASK)
+/*! @} */
+/* The count of ASRC_WRFIFO */
+#define ASRC_WRFIFO_COUNT (4U)
+/*! @name RDFIFO - ASRC Output Read FIFO */
+/*! @{ */
+#define ASRC_RDFIFO_CTX_RD_DATA_MASK (0xFFFFFFFFU)
+#define ASRC_RDFIFO_CTX_RD_DATA_SHIFT (0U)
+#define ASRC_RDFIFO_CTX_RD_DATA(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_RDFIFO_CTX_RD_DATA_SHIFT)) & ASRC_RDFIFO_CTX_RD_DATA_MASK)
+/*! @} */
+/* The count of ASRC_RDFIFO */
+#define ASRC_RDFIFO_COUNT (4U)
+/*! @name CTX_CTRL - ASRC Context Control */
+/*! @{ */
+#define ASRC_CTX_CTRL_NUM_CH_EN_MASK (0x1FU)
+#define ASRC_CTX_CTRL_NUM_CH_EN_SHIFT (0U)
+#define ASRC_CTX_CTRL_NUM_CH_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_NUM_CH_EN_SHIFT)) & ASRC_CTX_CTRL_NUM_CH_EN_MASK)
+#define ASRC_CTX_CTRL_SIGN_IN_MASK (0x40U)
+#define ASRC_CTX_CTRL_SIGN_IN_SHIFT (6U)
+/*! SIGN_IN - Input Data Sign
+ *  0b0..Signed Format
+ *  0b1..Unsigned Format
+ */
+#define ASRC_CTX_CTRL_SIGN_IN(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_SIGN_IN_SHIFT)) & ASRC_CTX_CTRL_SIGN_IN_MASK)
+#define ASRC_CTX_CTRL_FLOAT_FMT_MASK (0x80U)
+#define ASRC_CTX_CTRL_FLOAT_FMT_SHIFT (7U)
+/*! FLOAT_FMT - Context Input Floating Point Format
+ *  0b0..Integer Format
+ *  0b1..Single Precision Floating Point Format
+ */
+#define ASRC_CTX_CTRL_FLOAT_FMT(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_FLOAT_FMT_SHIFT)) & ASRC_CTX_CTRL_FLOAT_FMT_MASK)
+#define ASRC_CTX_CTRL_BITS_PER_SAMPLE_MASK (0x300U)
+#define ASRC_CTX_CTRL_BITS_PER_SAMPLE_SHIFT (8U)
+/*! BITS_PER_SAMPLE - Number of Bits Per Audio Sample
+ *  0b00..16-bits Per Sample
+ *  0b01..20-bits Per Sample
+ *  0b10..24-bits Per Sample
+ *  0b11..32-bits Per Sample
+ */
+#define ASRC_CTX_CTRL_BITS_PER_SAMPLE(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_BITS_PER_SAMPLE_SHIFT)) & ASRC_CTX_CTRL_BITS_PER_SAMPLE_MASK)
+#define ASRC_CTX_CTRL_BIT_REV_MASK (0x400U)
+#define ASRC_CTX_CTRL_BIT_REV_SHIFT (10U)
+/*! BIT_REV - Sample Bit Reversal
+ *  0b0..Keep Input Ordering
+ *  0b1..Reverse Bit Ordering
+ */
+#define ASRC_CTX_CTRL_BIT_REV(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_BIT_REV_SHIFT)) & ASRC_CTX_CTRL_BIT_REV_MASK)
+#define ASRC_CTX_CTRL_SAMPLE_POSITION_MASK (0xF800U)
+#define ASRC_CTX_CTRL_SAMPLE_POSITION_SHIFT (11U)
+#define ASRC_CTX_CTRL_SAMPLE_POSITION(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_SAMPLE_POSITION_SHIFT)) & ASRC_CTX_CTRL_SAMPLE_POSITION_MASK)
+#define ASRC_CTX_CTRL_FIFO_WTMK_MASK (0x7F0000U)
+#define ASRC_CTX_CTRL_FIFO_WTMK_SHIFT (16U)
+#define ASRC_CTX_CTRL_FIFO_WTMK(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_FIFO_WTMK_SHIFT)) & ASRC_CTX_CTRL_FIFO_WTMK_MASK)
+#define ASRC_CTX_CTRL_FWMDE_MASK (0x10000000U)
+#define ASRC_CTX_CTRL_FWMDE_SHIFT (28U)
+/*! FWMDE - FIFO Watermark DMA Enable
+ *  0b0..Input DMA Requests Not Enabled for This Context
+ *  0b1..Input DMA Requests Enabled for This Context
+ */
+#define ASRC_CTX_CTRL_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_FWMDE_SHIFT)) & ASRC_CTX_CTRL_FWMDE_MASK)
+#define ASRC_CTX_CTRL_RUN_STOP_MASK (0x20000000U)
+#define ASRC_CTX_CTRL_RUN_STOP_SHIFT (29U)
+#define ASRC_CTX_CTRL_RUN_STOP(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_RUN_STOP_SHIFT)) & ASRC_CTX_CTRL_RUN_STOP_MASK)
+#define ASRC_CTX_CTRL_RUN_EN_MASK (0x80000000U)
+#define ASRC_CTX_CTRL_RUN_EN_SHIFT (31U)
+#define ASRC_CTX_CTRL_RUN_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_RUN_EN_SHIFT)) & ASRC_CTX_CTRL_RUN_EN_MASK)
+/*! @} */
+/* The count of ASRC_CTX_CTRL */
+#define ASRC_CTX_CTRL_COUNT (4U)
+/*! @name CTX_CTRL_EXT1 - ASRC Context Control Extended 1 */
+/*! @{ */
+#define ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_MASK (0x3U)
+#define ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_SHIFT (0U)
+/*! PF_INIT_MODE - Prefilter Initialization Mode
+ *  0b00..Do not pre-fill any prefilter taps. The first sample written to the ASRC corresponds to the highest index
+ * prefilter filter tap. 0b01..Replicate the first sample to fill the right half of the prefilter. 0b10..Zero fill the
+ * right half of the prefilter. 0b11..N/A
+ */
+#define ASRC_CTX_CTRL_EXT1_PF_INIT_MODE(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_MASK)
+#define ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_MASK (0xCU)
+#define ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_SHIFT (2U)
+/*! RS_INIT_MODE - Resampler Initialization Mode
+ *  0b00..Do not pre-fill any resampler taps. The first sample output from the prefilter corresponds to the highest
+ * index resampling filter tap. 0b01..Replicate the first prefilter output sample to fill the right half of the
+ * resampler. 0b10..Fill the right half of the re-sampler with zeros. 0b11..N/A
+ */
+#define ASRC_CTX_CTRL_EXT1_RS_INIT_MODE(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_MASK)
+#define ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_MASK (0x10U)
+#define ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_SHIFT (4U)
+/*! PF_STOP_MODE - Pre-Filter Stop Mode
+ *  0b0..Replicate the last sample input to the ASRC_WRFIFO for the left-half of the pre-filter on RUN_STOP.
+ *  0b1..Zero-Fill the left-half of the pre-filter on RUN_STOP.
+ */
+#define ASRC_CTX_CTRL_EXT1_PF_STOP_MODE(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_MASK)
+#define ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_MASK (0x20U)
+#define ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_SHIFT (5U)
+/*! RS_STOP_MODE - Resampler Stop Mode
+ *  0b0..Replicate the final prefilter output for the left-half of the resampler on RUN_STOP.
+ *  0b1..Zero-Fill the left-half of the resampler on RUN_STOP.
+ */
+#define ASRC_CTX_CTRL_EXT1_RS_STOP_MODE(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_MASK)
+#define ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_MASK (0x40U)
+#define ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_SHIFT (6U)
+/*! PF_BYPASS_MODE - Prefilter Bypass Mode
+ *  0b0..Run the prefilter in normal operation.
+ *  0b1..Run the prefilter in bypass mode.
+ */
+#define ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_MASK)
+#define ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_MASK (0x80U)
+#define ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_SHIFT (7U)
+/*! RS_BYPASS_MODE - Resampler Bypass Mode
+ *  0b0..Run the resampler in normal operation.
+ *  0b1..Run the resampler in bypass mode.
+ */
+#define ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_MASK)
+#define ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_MASK (0x100U)
+#define ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_SHIFT (8U)
+/*! PF_TWO_STAGE_EN - Prefilter Two-Stage Enable
+ *  0b0..The pre-filter will run in single stage mode (ST1 only)
+ *  0b1..The pre-filter will run in two stage mode (ST1 and ST2)
+ */
+#define ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_SHIFT)) & \
+     ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_MASK)
+#define ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_MASK (0x200U)
+#define ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_SHIFT (9U)
+/*! PF_ST1_WB_FLOAT - Prefilter Stage1 Writeback Floating Point
+ *  0b0..The pre-filter stage1 results are stored in 32-bit integer format.
+ *  0b1..The pre-filter stage1 results are stored in 32-bit floating point format.
+ */
+#define ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_SHIFT)) & \
+     ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_MASK)
+#define ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_MASK (0xFF0000U)
+#define ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_SHIFT (16U)
+#define ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_SHIFT)) & \
+     ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_MASK)
+#define ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_MASK (0x1000000U)
+#define ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_SHIFT (24U)
+#define ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_SHIFT)) & \
+     ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_MASK)
+#define ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_MASK (0x2000000U)
+#define ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_SHIFT (25U)
+#define ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_SHIFT)) & \
+     ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_MASK)
+/*! @} */
+/* The count of ASRC_CTX_CTRL_EXT1 */
+#define ASRC_CTX_CTRL_EXT1_COUNT (4U)
+/*! @name CTX_CTRL_EXT2 - ASRC Context Control Extended 2 */
+/*! @{ */
+#define ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_MASK (0x1FFU)
+#define ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_SHIFT (0U)
+#define ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_SHIFT)) & ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_MASK)
+#define ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_MASK (0x1FF0000U)
+#define ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_SHIFT (16U)
+#define ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_SHIFT)) & ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_MASK)
+/*! @} */
+/* The count of ASRC_CTX_CTRL_EXT2 */
+#define ASRC_CTX_CTRL_EXT2_COUNT (4U)
+/*! @name CTRL_IN_ACCESS - ASRC Control Input Access */
+/*! @{ */
+#define ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_MASK (0x3FU)
+#define ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_SHIFT (0U)
+#define ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_SHIFT)) & ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_MASK)
+#define ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_MASK (0x3F00U)
+#define ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_SHIFT (8U)
+#define ASRC_CTRL_IN_ACCESS_GROUP_LENGTH(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_SHIFT)) & ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_MASK)
+#define ASRC_CTRL_IN_ACCESS_ITERATIONS_MASK (0x3F0000U)
+#define ASRC_CTRL_IN_ACCESS_ITERATIONS_SHIFT (16U)
+#define ASRC_CTRL_IN_ACCESS_ITERATIONS(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_IN_ACCESS_ITERATIONS_SHIFT)) & ASRC_CTRL_IN_ACCESS_ITERATIONS_MASK)
+/*! @} */
+/* The count of ASRC_CTRL_IN_ACCESS */
+#define ASRC_CTRL_IN_ACCESS_COUNT (4U)
+/*! @name PROC_CTRL_SLOT0_R0 - ASRC Datapath Processor Control Slot0 Register0 */
+/*! @{ */
+#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_MASK (0x1U)
+#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_SHIFT (0U)
+/*! SLOT0_EN - SLOT0 Enable
+ *  0b0..Context SLOT0 is disabled
+ *  0b1..Context SLOT0 is enabled
+ */
+#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_MASK)
+#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_MASK (0x6U)
+#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_SHIFT (1U)
+#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_SHIFT)) & \
+     ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_MASK)
+#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_MASK (0x1F00U)
+#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_SHIFT (8U)
+/*! SLOT0_NUM_CH - SLOT0 Number of Channels
+ *  0b00000..Context SLOT0 owns 1 of 8 channels
+ *  0b00001..Context SLOT0 owns 2 of 8 channels
+ *  0b00010..Context SLOT0 owns 3 of 8 channels
+ *  0b00011-0b00111..Context SLOT0 owns N of 8 channels
+ */
+#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_SHIFT)) & \
+     ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_MASK)
+#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_MASK (0x1F0000U)
+#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_SHIFT (16U)
+#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_SHIFT)) & \
+     ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_MASK)
+#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_MASK (0x1F000000U)
+#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_SHIFT (24U)
+#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_SHIFT)) & \
+     ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_MASK)
+/*! @} */
+/* The count of ASRC_PROC_CTRL_SLOT0_R0 */
+#define ASRC_PROC_CTRL_SLOT0_R0_COUNT (4U)
+/*! @name PROC_CTRL_SLOT0_R1 - ASRC Datapath Processor Control Slot0 Register1 */
+/*! @{ */
+#define ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_MASK (0x1FFFU)
+#define ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_SHIFT (0U)
+#define ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_SHIFT)) & \
+     ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_MASK)
+/*! @} */
+/* The count of ASRC_PROC_CTRL_SLOT0_R1 */
+#define ASRC_PROC_CTRL_SLOT0_R1_COUNT (4U)
+/*! @name PROC_CTRL_SLOT0_R2 - ASRC Datapath Processor Control Slot0 Register2 */
+/*! @{ */
+#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_MASK (0x1FFFU)
+#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_SHIFT (0U)
+#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_SHIFT)) & \
+     ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_MASK)
+#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_MASK (0x1FFF0000U)
+#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_SHIFT (16U)
+#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_SHIFT)) & \
+     ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_MASK)
+/*! @} */
+/* The count of ASRC_PROC_CTRL_SLOT0_R2 */
+#define ASRC_PROC_CTRL_SLOT0_R2_COUNT (4U)
+/*! @name PROC_CTRL_SLOT0_R3 - ASRC Datapath Processor Control Slot0 Register3 */
+/*! @{ */
+#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_MASK (0x1FFFU)
+#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_SHIFT (0U)
+#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_SHIFT)) & \
+     ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_MASK)
+#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_MASK (0x1FFF0000U)
+#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_SHIFT (16U)
+#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_SHIFT)) & \
+     ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_MASK)
+/*! @} */
+/* The count of ASRC_PROC_CTRL_SLOT0_R3 */
+#define ASRC_PROC_CTRL_SLOT0_R3_COUNT (4U)
+/*! @name PROC_CTRL_SLOT1_R0 - ASRC Datapath Processor Control Slot1 Register0 */
+/*! @{ */
+#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_MASK (0x1U)
+#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_SHIFT (0U)
+/*! SLOT1_EN - SLOT1 Enable
+ *  0b0..Context SLOT1 is disabled
+ *  0b1..Context SLOT1 is enabled
+ */
+#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_MASK)
+#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_MASK (0x6U)
+#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_SHIFT (1U)
+#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_SHIFT)) & \
+     ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_MASK)
+#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_MASK (0x1F00U)
+#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_SHIFT (8U)
+/*! SLOT1_NUM_CH - SLOT1 Number of Channels
+ *  0b00000..Context SLOT1 owns 1 of 8 channels
+ *  0b00001..Context SLOT1 owns 2 of 8 channels
+ *  0b00010..Context SLOT1 owns 3 of 8 channels
+ *  0b00011-0b00111..Context SLOT1 owns N of 8 channels
+ */
+#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_SHIFT)) & \
+     ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_MASK)
+#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_MASK (0x1F0000U)
+#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_SHIFT (16U)
+#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_SHIFT)) & \
+     ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_MASK)
+#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_MASK (0x1F000000U)
+#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_SHIFT (24U)
+#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_SHIFT)) & \
+     ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_MASK)
+/*! @} */
+/* The count of ASRC_PROC_CTRL_SLOT1_R0 */
+#define ASRC_PROC_CTRL_SLOT1_R0_COUNT (4U)
+/*! @name PROC_CTRL_SLOT1_R1 - ASRC Datapath Processor Control SLOT1 Register1 */
+/*! @{ */
+#define ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_MASK (0x1FFFU)
+#define ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_SHIFT (0U)
+#define ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_SHIFT)) & \
+     ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_MASK)
+/*! @} */
+/* The count of ASRC_PROC_CTRL_SLOT1_R1 */
+#define ASRC_PROC_CTRL_SLOT1_R1_COUNT (4U)
+/*! @name PROC_CTRL_SLOT1_R2 - ASRC Datapath Processor Control SLOT1 Register2 */
+/*! @{ */
+#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_MASK (0x1FFFU)
+#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_SHIFT (0U)
+#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_SHIFT)) & \
+     ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_MASK)
+#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_MASK (0x1FFF0000U)
+#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_SHIFT (16U)
+#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_SHIFT)) & \
+     ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_MASK)
+/*! @} */
+/* The count of ASRC_PROC_CTRL_SLOT1_R2 */
+#define ASRC_PROC_CTRL_SLOT1_R2_COUNT (4U)
+/*! @name PROC_CTRL_SLOT1_R3 - ASRC Datapath Processor Control SLOT1 Register3 */
+/*! @{ */
+#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_MASK (0x1FFFU)
+#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_SHIFT (0U)
+#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_SHIFT)) & \
+     ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_MASK)
+#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_MASK (0x1FFF0000U)
+#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_SHIFT (16U)
+#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_SHIFT)) & \
+     ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_MASK)
+/*! @} */
+/* The count of ASRC_PROC_CTRL_SLOT1_R3 */
+#define ASRC_PROC_CTRL_SLOT1_R3_COUNT (4U)
+/*! @name CTX_OUT_CTRL - ASRC Context Output Control */
+/*! @{ */
+#define ASRC_CTX_OUT_CTRL_DITHER_EN_MASK (0x1U)
+#define ASRC_CTX_OUT_CTRL_DITHER_EN_SHIFT (0U)
+#define ASRC_CTX_OUT_CTRL_DITHER_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_DITHER_EN_SHIFT)) & ASRC_CTX_OUT_CTRL_DITHER_EN_MASK)
+#define ASRC_CTX_OUT_CTRL_IEC_EN_MASK (0x2U)
+#define ASRC_CTX_OUT_CTRL_IEC_EN_SHIFT (1U)
+/*! IEC_EN - IEC60958 Bit-Field Insertion Enable
+ *  0b0..No Data Insertion Enabled.
+ *  0b1..IEC60958 Bit-Field Insertion Enabled.
+ */
+#define ASRC_CTX_OUT_CTRL_IEC_EN(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_IEC_EN_SHIFT)) & ASRC_CTX_OUT_CTRL_IEC_EN_MASK)
+#define ASRC_CTX_OUT_CTRL_IEC_V_DATA_MASK (0x4U)
+#define ASRC_CTX_OUT_CTRL_IEC_V_DATA_SHIFT (2U)
+#define ASRC_CTX_OUT_CTRL_IEC_V_DATA(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_IEC_V_DATA_SHIFT)) & ASRC_CTX_OUT_CTRL_IEC_V_DATA_MASK)
+#define ASRC_CTX_OUT_CTRL_SIGN_OUT_MASK (0x40U)
+#define ASRC_CTX_OUT_CTRL_SIGN_OUT_SHIFT (6U)
+/*! SIGN_OUT - Output Data Sign
+ *  0b0..Signed Format
+ *  0b1..Convert to Unsigned
+ */
+#define ASRC_CTX_OUT_CTRL_SIGN_OUT(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_SIGN_OUT_SHIFT)) & ASRC_CTX_OUT_CTRL_SIGN_OUT_MASK)
+#define ASRC_CTX_OUT_CTRL_FLOAT_FMT_MASK (0x80U)
+#define ASRC_CTX_OUT_CTRL_FLOAT_FMT_SHIFT (7U)
+/*! FLOAT_FMT - Context Output Floating Point Format
+ *  0b0..Integer Format
+ *  0b1..Single Precision Floating Point Format
+ */
+#define ASRC_CTX_OUT_CTRL_FLOAT_FMT(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_FLOAT_FMT_SHIFT)) & ASRC_CTX_OUT_CTRL_FLOAT_FMT_MASK)
+#define ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_MASK (0x300U)
+#define ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_SHIFT (8U)
+/*! BITS_PER_SAMPLE - Number of Bits Per Audio Sample
+ *  0b00..16-bits Per Sample
+ *  0b01..20-bits Per Sample
+ *  0b10..24-bits Per Sample
+ *  0b11..32-bits Per Sample
+ */
+#define ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_SHIFT)) & ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_MASK)
+#define ASRC_CTX_OUT_CTRL_BIT_REV_MASK (0x400U)
+#define ASRC_CTX_OUT_CTRL_BIT_REV_SHIFT (10U)
+/*! BIT_REV - Sample Bit-Reversal
+ *  0b0..No change.
+ *  0b1..Bit-reverse sample data.
+ */
+#define ASRC_CTX_OUT_CTRL_BIT_REV(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_BIT_REV_SHIFT)) & ASRC_CTX_OUT_CTRL_BIT_REV_MASK)
+#define ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_MASK (0xF800U)
+#define ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_SHIFT (11U)
+#define ASRC_CTX_OUT_CTRL_SAMPLE_POSITION(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_SHIFT)) & ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_MASK)
+#define ASRC_CTX_OUT_CTRL_FIFO_WTMK_MASK (0x7F0000U)
+#define ASRC_CTX_OUT_CTRL_FIFO_WTMK_SHIFT (16U)
+#define ASRC_CTX_OUT_CTRL_FIFO_WTMK(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_FIFO_WTMK_SHIFT)) & ASRC_CTX_OUT_CTRL_FIFO_WTMK_MASK)
+#define ASRC_CTX_OUT_CTRL_FWMDE_MASK (0x10000000U)
+#define ASRC_CTX_OUT_CTRL_FWMDE_SHIFT (28U)
+/*! FWMDE - Output FIFO Watermark DMA Enable
+ *  0b0..Output DMA Requests Not Enabled for This Context
+ *  0b1..Output DMA Requests Enabled for This Context
+ */
+#define ASRC_CTX_OUT_CTRL_FWMDE(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_FWMDE_SHIFT)) & ASRC_CTX_OUT_CTRL_FWMDE_MASK)
+/*! @} */
+/* The count of ASRC_CTX_OUT_CTRL */
+#define ASRC_CTX_OUT_CTRL_COUNT (4U)
+/*! @name CTRL_OUT_ACCESS - ASRC Control Output Access */
+/*! @{ */
+#define ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_MASK (0x3FU)
+#define ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_SHIFT (0U)
+#define ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_SHIFT)) & \
+     ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_MASK)
+#define ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_MASK (0x3F00U)
+#define ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_SHIFT (8U)
+#define ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_SHIFT)) & ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_MASK)
+#define ASRC_CTRL_OUT_ACCESS_ITERATIONS_MASK (0x3F0000U)
+#define ASRC_CTRL_OUT_ACCESS_ITERATIONS_SHIFT (16U)
+#define ASRC_CTRL_OUT_ACCESS_ITERATIONS(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_OUT_ACCESS_ITERATIONS_SHIFT)) & ASRC_CTRL_OUT_ACCESS_ITERATIONS_MASK)
+/*! @} */
+/* The count of ASRC_CTRL_OUT_ACCESS */
+#define ASRC_CTRL_OUT_ACCESS_COUNT (4U)
+/*! @name SAMPLE_FIFO_STATUS - ASRC Sample FIFO Status */
+/*! @{ */
+#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_MASK (0x7FU)
+#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_SHIFT (0U)
+#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_SHIFT)) & \
+     ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_MASK)
+#define ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_MASK (0x80U)
+#define ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_SHIFT (7U)
+#define ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_SHIFT)) & \
+     ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_MASK)
+#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_MASK (0x7F0000U)
+#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_SHIFT (16U)
+#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_SHIFT)) & \
+     ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_MASK)
+#define ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_MASK (0x800000U)
+#define ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_SHIFT (23U)
+#define ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_SHIFT)) & \
+     ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_MASK)
+/*! @} */
+/* The count of ASRC_SAMPLE_FIFO_STATUS */
+#define ASRC_SAMPLE_FIFO_STATUS_COUNT (4U)
+/*! @name RS_RATIO_LOW - ASRC Resampling Ratio Low */
+/*! @{ */
+#define ASRC_RS_RATIO_LOW_RS_RATIO_LOW_MASK (0xFFFFFFFFU)
+#define ASRC_RS_RATIO_LOW_RS_RATIO_LOW_SHIFT (0U)
+#define ASRC_RS_RATIO_LOW_RS_RATIO_LOW(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_RS_RATIO_LOW_RS_RATIO_LOW_SHIFT)) & ASRC_RS_RATIO_LOW_RS_RATIO_LOW_MASK)
+/*! @} */
+/* The count of ASRC_RS_RATIO_LOW */
+#define ASRC_RS_RATIO_LOW_COUNT (4U)
+/*! @name RS_RATIO_HIGH - ASRC Resampling Ratio High */
+/*! @{ */
+#define ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_MASK (0xFFFU)
+#define ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_SHIFT (0U)
+#define ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_SHIFT)) & ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_MASK)
+#define ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_MASK (0x80000000U)
+#define ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_SHIFT (31U)
+#define ASRC_RS_RATIO_HIGH_RS_RATIO_VLD(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_SHIFT)) & ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_MASK)
+/*! @} */
+/* The count of ASRC_RS_RATIO_HIGH */
+#define ASRC_RS_RATIO_HIGH_COUNT (4U)
+/*! @name RS_UPDATE_CTRL - ASRC Resampling Ratio Update Control */
+/*! @{ */
+#define ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_MASK (0xFFFFFFFFU)
+#define ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_SHIFT (0U)
+#define ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_SHIFT)) & ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_MASK)
+/*! @} */
+/* The count of ASRC_RS_UPDATE_CTRL */
+#define ASRC_RS_UPDATE_CTRL_COUNT (4U)
+/*! @name RS_UPDATE_RATE - ASRC Resampling Ratio Update Rate */
+/*! @{ */
+#define ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_MASK (0x7FFFFFFFU)
+#define ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_SHIFT (0U)
+#define ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_SHIFT)) & \
+     ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_MASK)
+/*! @} */
+/* The count of ASRC_RS_UPDATE_RATE */
+#define ASRC_RS_UPDATE_RATE_COUNT (4U)
+/*! @name RS_CT_LOW - ASRC Resampling Center Tap Coefficient Low */
+/*! @{ */
+#define ASRC_RS_CT_LOW_RS_CT_LOW_MASK (0xFFFFFFFFU)
+#define ASRC_RS_CT_LOW_RS_CT_LOW_SHIFT (0U)
+#define ASRC_RS_CT_LOW_RS_CT_LOW(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_RS_CT_LOW_RS_CT_LOW_SHIFT)) & ASRC_RS_CT_LOW_RS_CT_LOW_MASK)
+/*! @} */
+/*! @name RS_CT_HIGH - ASRC Resampling Center Tap Coefficient High */
+/*! @{ */
+#define ASRC_RS_CT_HIGH_RS_CT_HIGH_MASK (0xFFFFFFFFU)
+#define ASRC_RS_CT_HIGH_RS_CT_HIGH_SHIFT (0U)
+#define ASRC_RS_CT_HIGH_RS_CT_HIGH(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_RS_CT_HIGH_RS_CT_HIGH_SHIFT)) & ASRC_RS_CT_HIGH_RS_CT_HIGH_MASK)
+/*! @} */
+/*! @name PRE_COEFF_FIFO - ASRC Prefilter Coefficient FIFO */
+/*! @{ */
+#define ASRC_PRE_COEFF_FIFO_COEFF_DATA_MASK (0xFFFFFFFFU)
+#define ASRC_PRE_COEFF_FIFO_COEFF_DATA_SHIFT (0U)
+#define ASRC_PRE_COEFF_FIFO_COEFF_DATA(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_PRE_COEFF_FIFO_COEFF_DATA_SHIFT)) & ASRC_PRE_COEFF_FIFO_COEFF_DATA_MASK)
+/*! @} */
+/* The count of ASRC_PRE_COEFF_FIFO */
+#define ASRC_PRE_COEFF_FIFO_COUNT (4U)
+/*! @name CTX_RS_COEFF_MEM - ASRC Context Resampling Coefficient Memory */
+/*! @{ */
+#define ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_MASK (0xFFFFFFFFU)
+#define ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_SHIFT (0U)
+#define ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_SHIFT)) & \
+     ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_MASK)
+/*! @} */
+/*! @name CTX_RS_COEFF_CTRL - ASRC Context Resampling Coefficient Control */
+/*! @{ */
+#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_MASK (0x1U)
+#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_SHIFT (0U)
+#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_SHIFT)) & \
+     ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_MASK)
+#define ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_MASK (0x6U)
+#define ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_SHIFT (1U)
+/*! NUM_RES_TAPS - Number of Resampling Coefficient Taps
+ *  0b00..32-Tap Resampling Filter
+ *  0b01..64-Tap Resampling Filter
+ *  0b10..128-Tap Resampling Filter
+ *  0b11..N/A
+ */
+#define ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_SHIFT)) & \
+     ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_MASK)
+#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_MASK (0x7FF0000U)
+#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_SHIFT (16U)
+#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_SHIFT)) & \
+     ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_MASK)
+/*! @} */
+/*! @name IRQ_CTRL - ASRC Interrupt Control */
+/*! @{ */
+#define ASRC_IRQ_CTRL_INFIFO_OVF_MASK_MASK (0xFU)
+#define ASRC_IRQ_CTRL_INFIFO_OVF_MASK_SHIFT (0U)
+/*! INFIFO_OVF_MASK - ASRC Input FIFO Overflow Mask
+ *  0b0000..The INFIFO_OVF interrupt is enabled for Context 0 to 3.
+ *  0b0001..The INFIFO_OVF interrupt is disabled for Context 0 and enabled for Context 1 to 3.
+ *  0b0010..The INFIFO_OVF interrupt is disabled for Context 1 and enabled for Context 0, 2, and 3.
+ *  0b0011-0b1110..The INFIFO_OVF interrupt is enabled for any context with a 1'b0 bit field.
+ *  0b1111..The INFIFO_OVF interrupt is disabled for Context 0 to 3.
+ */
+#define ASRC_IRQ_CTRL_INFIFO_OVF_MASK(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_CTRL_INFIFO_OVF_MASK_SHIFT)) & ASRC_IRQ_CTRL_INFIFO_OVF_MASK_MASK)
+#define ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_MASK (0xF0U)
+#define ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_SHIFT (4U)
+/*! OUTFIFO_EMPTY_RD_MASK - ASRC Output FIFO Empty Read Mask
+ *  0b0000..The OUTFIFO_EMPTY_RD interrupt is enabled for Context 0 to 3.
+ *  0b0001..The OUTFIFO_EMPTY_RD interrupt is disabled for Context 0 and enabled for Context 1 to 3.
+ *  0b0010..The OUTFIFO_EMPTY_RD interrupt is disabled for Context 1 and enabled for Context 0, 2, and 3.
+ *  0b0011-0b1110..The OUTFIFO_EMPTY_RD interrupt is enabled for any context with a 1'b0 bit field.
+ *  0b1111..The OUTFIFO_EMPTY_RD interrupt is disabled for Context 0 to 3.
+ */
+#define ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK(x)                                    \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_SHIFT)) & \
+     ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_MASK)
+#define ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_MASK (0xF00U)
+#define ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_SHIFT (8U)
+/*! RUN_STOP_DONE_MASK - ASRC RUN STOP DONE MASK
+ *  0b0000..The RUN_STOP_DONE interrupt is enabled for Context 0 to 3.
+ *  0b0001..The RUN_STOP_DONE interrupt is disabled for Context 0 and enabled for Context 1 to 3.
+ *  0b0010..The RUN_STOP_DONE interrupt is disabled for Context 1 and enabled for Context 0, 2, and 3.
+ *  0b0011-0b1110..The RUN_STOP_DONE interrupt is enabled for any context with a 1'b0 bit field.
+ *  0b1111..The RUN_STOP_DONE interrupt is disabled for Context 0 to 3.
+ */
+#define ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK(x) \
+    (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_SHIFT)) & ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_MASK)
+/*! @} */
+/*! @name IRQ_FLAGS - ASRC Interrupt Status Flags */
+/*! @{ */
+#define ASRC_IRQ_FLAGS_INFIFO_OVF_MASK (0xFU)
+#define ASRC_IRQ_FLAGS_INFIFO_OVF_SHIFT (0U)
+/*! INFIFO_OVF - ASRC Input FIFO Overflow Flag
+ *  0b0000..No INFIFO_OVF errors have been recorded.
+ *  0b0001..The ASRC_WRFIFO0 has overflown.
+ *  0b0010..The ASRC_WRFIFO1 has overflown.
+ *  0b0011-0b1110..The ASRC_WRFIFOn has overflown. Where n = any bit position set to 0b1.