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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/driver_reset.cmake14
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/fsl_clock.c389
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/fsl_clock.h526
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/fsl_memory.h108
4 files changed, 1037 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/driver_reset.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/driver_reset.cmake
new file mode 100644
index 000000000..989530f6f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/driver_reset.cmake
@@ -0,0 +1,14 @@
1if(NOT DRIVER_RESET_INCLUDED)
2
3 set(DRIVER_RESET_INCLUDED true CACHE BOOL "driver_reset component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 )
7
8 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
9 ${CMAKE_CURRENT_LIST_DIR}/.
10 )
11
12
13
14endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/fsl_clock.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/fsl_clock.c
new file mode 100644
index 000000000..e04fc7548
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/fsl_clock.c
@@ -0,0 +1,389 @@
1/*
2 * Copyright 2017-2019 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include "fsl_clock.h"
8
9/*******************************************************************************
10 * Definitions
11 ******************************************************************************/
12/* Component ID definition, used by tools. */
13#ifndef FSL_COMPONENT_ID
14#define FSL_COMPONENT_ID "platform.drivers.clock"
15#endif
16/* LPCG register Bits Mask. LPCG register generally comes in four bit groups, a STOP, Reserved, [P|B]CG(SWEN), HWEN
17 * nibble. The HWEN bits are optional, but the allocations of the nibble always be on four bit boundaries. */
18#define LPCG_CLK_HWEN_MASK (0x11111111U)
19#define LPCG_CLK_SWEN_MASK (0x22222222U)
20#define LPCG_CLK_STOP_MASK (0x88888888U)
21
22/*******************************************************************************
23 * Variables
24 ******************************************************************************/
25static sc_ipc_t ipcHandle;
26
27/*******************************************************************************
28 * Prototypes
29 ******************************************************************************/
30
31/*******************************************************************************
32 * Code
33 ******************************************************************************/
34
35/*!
36 * brief Initialize Clock module.
37 *
38 * param ipc IPC handle for communication with SCU, see \ref sc_ipc_t.
39 */
40void CLOCK_Init(sc_ipc_t ipc)
41{
42 ipcHandle = ipc;
43}
44
45/*!
46 * brief Deinitialize Clock module.
47 */
48void CLOCK_Deinit(void)
49{
50}
51
52/*!
53 * brief Enable the clock for specific IP, with gate setting.
54 *
55 * param name Which clock to enable, see \ref clock_ip_name_t.
56 * param gate 0: clock always on, 1: HW auto clock gating.
57 * return true if success, false if failure.
58 */
59bool CLOCK_EnableClockExt(clock_ip_name_t name, uint32_t gate)
60{
61 sc_err_t err;
62
63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate);
64
65 /* Enable the Clock Gate control in LPCG */
66 CLOCK_ConfigLPCG(name, (bool)1U, (bool)gate);
67
68 if (err != SC_ERR_NONE)
69 {
70 return false;
71 }
72 else
73 {
74 return true;
75 }
76}
77
78/*!
79 * brief Disable the clock for specific IP.
80 *
81 * param name Which clock to disable, see \ref clock_ip_name_t.
82 * return true for success, false for failure.
83 */
84bool CLOCK_DisableClock(clock_ip_name_t name)
85{
86 sc_err_t err;
87
88 /* Disable the Clock Gate control in LPCG */
89 CLOCK_ConfigLPCG(name, (bool)0U, (bool)0U);
90
91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false);
92
93 if (err != SC_ERR_NONE)
94 {
95 return false;
96 }
97 else
98 {
99 return true;
100 }
101}
102
103/*!
104 * brief Set the clock frequency for specific IP module.
105 *
106 * This function sets the IP module clock frequency.
107 *
108 * param name Which peripheral to check, see \ref clock_ip_name_t.
109 * param freq Target clock frequency value in hertz.
110 * return the Real clock frequency value in hertz, or 0 if failed
111 */
112uint32_t CLOCK_SetIpFreq(clock_ip_name_t name, uint32_t freq)
113{
114 uint32_t target = freq;
115 sc_err_t err;
116
117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target);
118 if (err != SC_ERR_NONE)
119 {
120 return 0;
121 }
122 else
123 {
124 return target;
125 }
126}
127
128/*!
129 * brief Get the clock frequency for a specific IP module.
130 *
131 * This function gets the IP module clock frequency.
132 *
133 * param name Which peripheral to get, see \ref clock_ip_name_t.
134 * return Clock frequency value in hertz, or 0 if failed
135 */
136uint32_t CLOCK_GetIpFreq(clock_ip_name_t name)
137{
138 uint32_t freq;
139 sc_err_t err;
140
141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq);
142 if (err != SC_ERR_NONE)
143 {
144 return 0;
145 }
146 else
147 {
148 return freq;
149 }
150}
151
152/*!
153 * brief Get the core clock or system clock frequency.
154 *
155 * return Clock frequency in Hz.
156 */
157uint32_t CLOCK_GetCoreSysClkFreq(void)
158{
159 uint32_t freq;
160 sc_err_t err;
161
162 err = sc_pm_get_clock_rate(ipcHandle, SC_R_M4_0_PID0, SC_PM_CLK_PER, &freq);
163 if (err != SC_ERR_NONE)
164 {
165 freq = 0U;
166 }
167
168 return freq;
169}
170
171/*!
172 * brief Gets the clock frequency for a specific clock name.
173 *
174 * This function checks the current clock configurations and then calculates
175 * the clock frequency for a specific clock name defined in clock_name_t.
176 *
177 * param clockName Clock names defined in clock_name_t
178 * return Clock frequency value in hertz
179 */
180uint32_t CLOCK_GetFreq(clock_name_t name)
181{
182 uint32_t freq;
183
184 switch (name)
185 {
186 case kCLOCK_CONECTIVITY_AhbClk:
187 freq = 167000000U; /* The CONNECTIVITY SS AHB clock is fixed to 167MHZ */
188 break;
189 case kCLOCK_CoreSysClk:
190 freq = CLOCK_GetCoreSysClkFreq();
191 break;
192 default:
193 freq = 0U;
194 break;
195 }
196
197 return freq;
198}
199
200/*!
201 * brief Set LPCG gate for specific LPCG.
202 *
203 * param regBase LPCG register base address.
204 * param swGate Software clock gating. 0: clock is gated; 1: clock is enabled
205 * param hwGate Hardware auto gating. 0: disable the HW clock gate control; 1: HW clock gating is enabled
206 * param bitsMask The available bits in LPCG register. Each bit indicate the corresponding bit is available or not.
207 */
208void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask)
209{
210 if (regBase != NULL)
211 {
212 if (swGate)
213 {
214 *regBase |= bitsMask & LPCG_CLK_SWEN_MASK;
215 }
216 else
217 {
218 *regBase &= ~(bitsMask & LPCG_CLK_SWEN_MASK);
219 }
220
221 if (hwGate)
222 {
223 *regBase |= bitsMask & LPCG_CLK_HWEN_MASK;
224 }
225 else
226 {
227 *regBase &= ~(bitsMask & LPCG_CLK_HWEN_MASK);
228 }
229 }
230}
231
232/*!
233 * brief Config the LPCG cell for specific IP.
234 *
235 * param name Which clock to enable, see \ref clock_ip_name_t.
236 * param swGate Software clock gating. 0: clock is gated; 1: clock is enabled
237 * param hwGate Hardware auto gating. 0: disable the HW clock gate control; 1: HW clock gating is enabled
238 */
239void CLOCK_ConfigLPCG(clock_ip_name_t name, bool swGate, bool hwGate)
240{
241 volatile uint32_t *regBase;
242
243 regBase = LPCG_TUPLE_REG_BASE(name);
244
245 /* Return if LPCG Cell is not available. */
246 if (regBase == NULL)
247 {
248 return;
249 }
250
251 /* Config the LPCG. LPCG Cells have different configurations per each clock target. */
252 switch (name)
253 {
254 /* LPCG cell avalialbe bits field mask 0xBBAAAB, 0xBBAAAB (2 32-bits LPCG registers). */
255 case kCLOCK_CONNECTIVITY_Enet0:
256 case kCLOCK_CONNECTIVITY_Enet1:
257 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBBAAABU);
258 CLOCK_SetLpcgGate(regBase + 0x1U, swGate, hwGate, 0xAU);
259 break;
260
261 /* LPCG cell avalialbe bits field mask 0xBAB0AAB.*/
262 case kCLOCK_LSIO_Gpt0:
263 case kCLOCK_LSIO_Gpt1:
264 case kCLOCK_LSIO_Gpt2:
265 case kCLOCK_LSIO_Gpt3:
266 case kCLOCK_LSIO_Gpt4:
267 case kCLOCK_LSIO_Pwm0:
268 case kCLOCK_LSIO_Pwm1:
269 case kCLOCK_LSIO_Pwm2:
270 case kCLOCK_LSIO_Pwm3:
271 case kCLOCK_LSIO_Pwm4:
272 case kCLOCK_LSIO_Pwm5:
273 case kCLOCK_LSIO_Pwm6:
274 case kCLOCK_LSIO_Pwm7:
275 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBAB0AAB);
276 break;
277
278 /* LPCG cell avalialbe bits field mask 0xB0000.*/
279 case kCLOCK_HSIO_Gpio:
280 case kCLOCK_LSIO_Gpio0:
281 case kCLOCK_LSIO_Gpio1:
282 case kCLOCK_LSIO_Gpio2:
283 case kCLOCK_LSIO_Gpio3:
284 case kCLOCK_LSIO_Gpio4:
285 case kCLOCK_LSIO_Gpio5:
286 case kCLOCK_LSIO_Gpio6:
287 case kCLOCK_LSIO_Gpio7:
288 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xB0000U);
289 break;
290 /* LPCG cell avalialbe bits field mask 0xB000A. */
291 case kCLOCK_AUDIO_Gpt0:
292 case kCLOCK_AUDIO_Gpt1:
293 case kCLOCK_AUDIO_Gpt2:
294 case kCLOCK_AUDIO_Gpt3:
295 case kCLOCK_AUDIO_Gpt4:
296 case kCLOCK_AUDIO_Gpt5:
297 case kCLOCK_LSIO_Mu5A:
298 case kCLOCK_LSIO_Mu6A:
299 case kCLOCK_LSIO_Mu7A:
300 case kCLOCK_LSIO_Mu8A:
301 case kCLOCK_LSIO_Mu9A:
302 case kCLOCK_LSIO_Mu10A:
303 case kCLOCK_LSIO_Mu11A:
304 case kCLOCK_LSIO_Mu12A:
305 case kCLOCK_LSIO_Mu13A:
306 case kCLOCK_LSIO_Mu5B:
307 case kCLOCK_LSIO_Mu6B:
308 case kCLOCK_LSIO_Mu7B:
309 case kCLOCK_LSIO_Mu8B:
310 case kCLOCK_LSIO_Mu9B:
311 case kCLOCK_LSIO_Mu10B:
312 case kCLOCK_LSIO_Mu11B:
313 case kCLOCK_LSIO_Mu12B:
314 case kCLOCK_LSIO_Mu13B:
315 case kCLOCK_AUDIO_Sai0:
316 case kCLOCK_AUDIO_Sai1:
317 case kCLOCK_AUDIO_Sai2:
318 case kCLOCK_AUDIO_Sai3:
319 case kCLOCK_AUDIO_Sai4:
320 case kCLOCK_AUDIO_Sai5:
321 case kCLOCK_AUDIO_Esai0:
322 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xB000AU);
323 break;
324
325 /* LPCG cell avalialbe bits field mask 0xB000B. */
326 case kCLOCK_DMA_Lpspi0:
327 case kCLOCK_DMA_Lpspi1:
328 case kCLOCK_DMA_Lpspi2:
329 case kCLOCK_DMA_Lpspi3:
330 case kCLOCK_DMA_Lpuart0:
331 case kCLOCK_DMA_Lpuart1:
332 case kCLOCK_DMA_Lpuart2:
333 case kCLOCK_DMA_Lpuart3:
334 case kCLOCK_DMA_Lpi2c0:
335 case kCLOCK_DMA_Lpi2c1:
336 case kCLOCK_DMA_Lpi2c2:
337 case kCLOCK_DMA_Lpi2c3:
338 case kCLOCK_DMA_Ftm0:
339 case kCLOCK_DMA_Ftm1:
340 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xB000BU);
341 break;
342
343 /* LPCG cell avalialbe bits field mask 0xBB000B.*/
344 case kCLOCK_DMA_Can0:
345 case kCLOCK_DMA_Can1:
346 case kCLOCK_DMA_Can2:
347 case kCLOCK_M4_0_Tpm:
348 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBB000B);
349 break;
350
351 /* LPCG cell avalialbe bits field mask 0xAB000A.*/
352 case kCLOCK_CONNECTIVITY_Usdhc0:
353 case kCLOCK_CONNECTIVITY_Usdhc1:
354 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xAB000A);
355 break;
356
357 /* LPCG cell avalialbe bits field mask 0xBAA000A.*/
358 case kCLOCK_LSIO_Flexspi0:
359 case kCLOCK_LSIO_Flexspi1:
360 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBAA000A);
361 break;
362
363 /* LPCG cells avalialbe bits field mask 0xAA, 0xAB0000.*/
364 case kCLOCK_Dpu0:
365 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xAA);
366 CLOCK_SetLpcgGate(regBase + 0x5U, swGate, hwGate, 0xAB0000);
367 break;
368
369 /* LPCG cell avalialbe bits field mask 0xB000B.*/
370 case kCLOCK_DiMiPiDsiLvds0Lpi2c0:
371 case kCLOCK_DiMiPiDsiLvds1Lpi2c0:
372 CLOCK_SetLpcgGate(regBase + 0x4U, swGate, hwGate, 0xB000B);
373 break;
374
375 /* LPCG cell does not config due to LPCG back to back write protection. */
376 case kCLOCK_M4_0_Lpit:
377 case kCLOCK_M4_0_Lpuart:
378 case kCLOCK_M4_0_Lpi2c:
379 case kCLOCK_SCU_Lpit:
380 case kCLOCK_SCU_Lpuart:
381 case kCLOCK_SCU_Lpi2c:
382 break;
383
384 /* LPCG cell is not avaliable or is not supported by this function. */
385 default:
386 assert(false);
387 break;
388 }
389}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/fsl_clock.h
new file mode 100644
index 000000000..8634d8084
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/fsl_clock.h
@@ -0,0 +1,526 @@
1/*
2 * Copyright 2017-2019 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef _FSL_CLOCK_H_
8#define _FSL_CLOCK_H_
9
10#include "fsl_device_registers.h"
11#include <stdint.h>
12#include <stdbool.h>
13#include <assert.h>
14
15#include "svc/pm/pm_api.h"
16
17/*! @addtogroup clock */
18/*! @{ */
19
20/*! @file */
21
22/*******************************************************************************
23 * Definitions
24 ******************************************************************************/
25
26/*! @brief Configure whether driver controls clock
27 *
28 * When set to 0, peripheral drivers will enable clock in initialize function
29 * and disable clock in de-initialize function. When set to 1, peripheral
30 * driver will not control the clock, application could control the clock out of
31 * the driver.
32 *
33 * @note All drivers share this feature switcher. If it is set to 1, application
34 * should handle clock enable and disable for all drivers.
35 */
36#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
37#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
38#endif
39
40/*! @name Driver version */
41/*@{*/
42/*! @brief CLOCK driver version 2.3.1. */
43#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
44/*@}*/
45
46/* Definition for delay API in clock driver, users can redefine it to the real application. */
47#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
48#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (400000000UL)
49#endif
50
51/*! @brief Clock ip name array for MU. */
52#define MU_CLOCKS \
53 { \
54 kCLOCK_M4_0_Mu0A0, kCLOCK_M4_0_Mu0A1, kCLOCK_M4_0_Mu0A2, kCLOCK_M4_0_Mu0A3, kCLOCK_M4_0_Mu0B, \
55 kCLOCK_M4_0_Mu0B, kCLOCK_M4_0_Mu0B, kCLOCK_M4_0_Mu0B, kCLOCK_M4_0_Mu1A, kCLOCK_LSIO_Mu0A, \
56 kCLOCK_LSIO_Mu1A, kCLOCK_LSIO_Mu2A, kCLOCK_LSIO_Mu3A, kCLOCK_LSIO_Mu4A, kCLOCK_LSIO_Mu5A, \
57 kCLOCK_LSIO_Mu5B, kCLOCK_LSIO_Mu6A, kCLOCK_LSIO_Mu6B, kCLOCK_LSIO_Mu7A, kCLOCK_LSIO_Mu7B, \
58 kCLOCK_LSIO_Mu8A, kCLOCK_LSIO_Mu8B, kCLOCK_LSIO_Mu9A, kCLOCK_LSIO_Mu9B, kCLOCK_LSIO_Mu10A, \
59 kCLOCK_LSIO_Mu10B, kCLOCK_LSIO_Mu11A, kCLOCK_LSIO_Mu11B, kCLOCK_LSIO_Mu12A, kCLOCK_LSIO_Mu12B, \
60 kCLOCK_LSIO_Mu13A, kCLOCK_LSIO_Mu13B, kCLOCK_SCU_Mu0A0, kCLOCK_SCU_Mu0A1, kCLOCK_SCU_Mu0A2, \
61 kCLOCK_SCU_Mu0A3, kCLOCK_SCU_Mu0B, kCLOCK_SCU_Mu0B, kCLOCK_SCU_Mu0B, kCLOCK_SCU_Mu0B, kCLOCK_SCU_Mu1A, \
62 }
63
64/*! @brief Clock ip name array for GPIO. */
65#define GPIO_CLOCKS \
66 { \
67 kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_HSIO_Gpio, kCLOCK_LSIO_Gpio0, kCLOCK_LSIO_Gpio1, \
68 kCLOCK_LSIO_Gpio2, kCLOCK_LSIO_Gpio3, kCLOCK_LSIO_Gpio4, kCLOCK_LSIO_Gpio5, kCLOCK_LSIO_Gpio6, \
69 kCLOCK_LSIO_Gpio7, kCLOCK_IpInvalid, \
70 }
71
72/*! @brief Clock ip name array for FLEXSPI. */
73#define FLEXSPI_CLOCKS \
74 { \
75 kCLOCK_LSIO_Flexspi0, kCLOCK_LSIO_Flexspi1, \
76 }
77
78/*! @brief Clock ip name array for RGPIO. */
79#define RGPIO_CLOCKS \
80 { \
81 kCLOCK_M4_0_Rgpio, \
82 }
83
84/*! @brief Clock ip name array for FTM. */
85#define FTM_CLOCKS \
86 { \
87 kCLOCK_DMA_Ftm0, kCLOCK_DMA_Ftm1, \
88 }
89
90/*! @brief Clock ip name array for GPT. */
91#define GPT_CLOCKS \
92 { \
93 kCLOCK_AUDIO_Gpt0, kCLOCK_AUDIO_Gpt1, kCLOCK_AUDIO_Gpt2, kCLOCK_AUDIO_Gpt3, kCLOCK_AUDIO_Gpt4, \
94 kCLOCK_AUDIO_Gpt5, kCLOCK_LSIO_Gpt0, kCLOCK_LSIO_Gpt1, kCLOCK_LSIO_Gpt2, kCLOCK_LSIO_Gpt3, \
95 kCLOCK_LSIO_Gpt4, \
96 }
97/*! @brief Clock ip name array for FLEXCAN. */
98#define FLEXCAN_CLOCKS \
99 { \
100 kCLOCK_DMA_Can0, kCLOCK_DMA_Can0, kCLOCK_DMA_Can0, \
101 }
102
103/*! @brief Clock ip name array for LPUART. */
104#define LPUART_CLOCKS \
105 { \
106 kCLOCK_DMA_Lpuart0, kCLOCK_DMA_Lpuart1, kCLOCK_DMA_Lpuart2, kCLOCK_DMA_Lpuart3, kCLOCK_M4_0_Lpuart, \
107 kCLOCK_SCU_Lpuart, \
108 }
109
110/*! @brief Clock ip name array for LPADC. */
111#define LPADC_CLOCKS \
112 { \
113 kCLOCK_ADMA_Lpadc0, \
114 }
115
116/*! @brief Clock ip name array for INTMUX. */
117#define INTMUX_CLOCKS \
118 { \
119 kCLOCK_M4_0_Intmux, kCLOCK_SCU_Intmux, \
120 }
121
122/*! @brief Clock ip name array for SAI. */
123#define SAI_CLOCKS \
124 { \
125 kCLOCK_AUDIO_Sai0, kCLOCK_AUDIO_Sai1, kCLOCK_AUDIO_Sai2, kCLOCK_AUDIO_Sai3, kCLOCK_AUDIO_Sai4, \
126 kCLOCK_AUDIO_Sai5, \
127 }
128
129/*! @brief Clock ip name array for SAI. */
130#define SEMA42_CLOCKS \
131 { \
132 kCLOCK_M4_0_Sema42, kCLOCK_SCU_Sema42, \
133 }
134
135/*! @brief Clock ip name array for TPM. */
136#define TPM_CLOCKS \
137 { \
138 kCLOCK_M4_0_Tpm, kCLOCK_SCU_Tpm, \
139 }
140
141/*! @brief Clock ip name array for LPIT. */
142#define LPIT_CLOCKS \
143 { \
144 kCLOCK_M4_0_Lpit, kCLOCK_SCU_Lpit, \
145 }
146
147/*! @brief Clock ip name array for LPI2C. */
148#define LPI2C_CLOCKS \
149 { \
150 kCLOCK_DMA_Lpi2c0, kCLOCK_DMA_Lpi2c1, kCLOCK_DMA_Lpi2c2, kCLOCK_DMA_Lpi2c3, kCLOCK_CiPiLpi2c, \
151 kCLOCK_M4_0_Lpi2c, kCLOCK_DiMiPiDsiLvds0Lpi2c0, kCLOCK_DiMiPiDsiLvds0Lpi2c1, kCLOCK_DiMiPiDsiLvds1Lpi2c0, \
152 kCLOCK_DiMiPiDsiLvds1Lpi2c1, kCLOCK_MipiCsiLpi2c, kCLOCK_SCU_Lpi2c, \
153 }
154
155/*! @brief Clock ip name array for LPSPI. */
156#define LPSPI_CLOCKS \
157 { \
158 kCLOCK_DMA_Lpspi0, kCLOCK_DMA_Lpspi1, kCLOCK_DMA_Lpspi2, kCLOCK_DMA_Lpspi3, \
159 }
160
161/*! @brief Clock ip name array for IRQSTEER */
162#define IRQSTEER_CLOCKS \
163 { \
164 kCLOCK_M4_0_Irqsteer, \
165 }
166
167/*! @brief Clock ip name array for EDMA. */
168#define EDMA_CLOCKS \
169 { \
170 kCLOCK_DMA_Dma0, \
171 }
172
173/*! @brief Clock ip name array for LPIT. */
174#define ESAI_CLOCKS \
175 { \
176 kCLOCK_AUDIO_Esai0, kCLOCK_AUDIO_Esai1, \
177 }
178
179/*! @brief Clock ip name array for ISI. */
180#define ISI_CLOCKS \
181 { \
182 kCLOCK_IMAGING_Isi0, kCLOCK_IMAGING_Isi1, kCLOCK_IMAGING_Isi2, kCLOCK_IMAGING_Isi3, kCLOCK_IMAGING_Isi4, \
183 kCLOCK_IMAGING_Isi5, \
184 }
185
186/*! @brief Clock ip name array for MIPI CSI2 RX. */
187#define MIPI_CSI2RX_CLOCKS \
188 { \
189 kCLOCK_MipiCsi2Rx0, \
190 }
191
192/*! @brief Clock ip name array for MIPI DSI host. */
193#define MIPI_DSI_HOST_CLOCKS \
194 { \
195 kCLOCK_MipiDsiHost0, kCLOCK_MipiDsiHost1 \
196 }
197
198/*! @brief Clock ip name array for ENET. */
199#define ENET_CLOCKS \
200 { \
201 kCLOCK_CONNECTIVITY_Enet0, kCLOCK_CONNECTIVITY_Enet1 \
202 }
203
204/*! @brief Clock ip name array for DPU. */
205#define DPU_CLOCKS \
206 { \
207 kCLOCK_Dpu0, \
208 }
209
210/*! @brief Clock ip name array for CI_PI. */
211#define CI_PI_CLOCKS \
212 { \
213 kCLOCK_CiPi0, \
214 }
215
216/*! @brief Clock ip name array for CAAM. */
217#define CAAM_CLOCKS \
218 { \
219 kCLOCK_CAAM_JR1, kCLOCK_CAAM_JR2, kCLOCK_CAAM_JR3, \
220 }
221
222/*! @brief Clock ip name array for LVDS display bridge(LDB). */
223#define LDB_CLOCKS \
224 { \
225 kCLOCK_Ldb0, kCLOCK_Ldb1 \
226 }
227
228/*!
229 * @brief Clock source for peripherals that support various clock selections.
230 */
231typedef enum _clock_ip_src
232{
233 kCLOCK_IpSrcNone = 0U, /*!< Clock is off. */
234 kCLOCK_IpSrcDummy = 1U, /*!< Clock option 1. */
235} clock_ip_src_t;
236
237/*! @brief Clock name used to get clock frequency. */
238typedef enum _clock_name
239{
240 /* ----------------------------- System layer clock ---------------------- */
241 kCLOCK_CoreSysClk, /*!< Core/system clock for M4 */
242
243 /* --------------------------------- Other clock ------------------------- */
244 kCLOCK_CONECTIVITY_AhbClk, /*!< AHB clock in Connectivity subsystem */
245} clock_name_t;
246
247/*!
248 * @brief LPCG TUPLE macors to map corresponding ip clock name, SCFW API resource index and LPCG Register base address.
249 * The LPCG base should be 4KB aligned, if not it will be truncated.
250 */
251#define LPCG_TUPLE(rsrc, base) ((uint32_t)((((base) >> 12U) << 10U) | (rsrc)))
252/*! @brief Get the LPCG REG base address. */
253#define LPCG_TUPLE_REG_BASE(tuple) ((volatile uint32_t *)((((uint32_t)(tuple) >> 10U) & 0xFFFFFU) << 12U))
254/*! @brief Get the resource index. */
255#define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU))
256/*! @brief LPCG Cell not available. */
257#define NV (0U)
258
259/*!
260 * @brief Peripheral clock name difinition used for clock gate, clock source
261 * and clock divider setting. It is defined as the corresponding register address.
262 */
263typedef enum _clock_ip_name
264{
265 kCLOCK_M4_0_Irqsteer = LPCG_TUPLE(SC_R_IRQSTR_M4_0, NV),
266 kCLOCK_DMA_Lpspi0 = LPCG_TUPLE(SC_R_SPI_0, ADMA__LPCG_SPI0_IPG_CLK_BASE),
267 kCLOCK_DMA_Lpspi1 = LPCG_TUPLE(SC_R_SPI_1, ADMA__LPCG_SPI1_IPG_CLK_BASE),
268 kCLOCK_DMA_Lpspi2 = LPCG_TUPLE(SC_R_SPI_2, ADMA__LPCG_SPI2_IPG_CLK_BASE),
269 kCLOCK_DMA_Lpspi3 = LPCG_TUPLE(SC_R_SPI_3, ADMA__LPCG_SPI3_IPG_CLK_BASE),
270 kCLOCK_DMA_Lpuart0 = LPCG_TUPLE(SC_R_UART_0, ADMA__LPCG_UART0_IPG_CLK_BASE),
271 kCLOCK_DMA_Lpuart1 = LPCG_TUPLE(SC_R_UART_1, ADMA__LPCG_UART1_IPG_CLK_BASE),
272 kCLOCK_DMA_Lpuart2 = LPCG_TUPLE(SC_R_UART_2, ADMA__LPCG_UART2_IPG_CLK_BASE),
273 kCLOCK_DMA_Lpuart3 = LPCG_TUPLE(SC_R_UART_3, ADMA__LPCG_UART3_IPG_CLK_BASE),
274 kCLOCK_DMA_Dma0 = LPCG_TUPLE(SC_R_DMA_0_CH0, NV),
275 kCLOCK_DMA_Lpi2c0 = LPCG_TUPLE(SC_R_I2C_0, ADMA__LPCG_I2C0_IPG_CLK_BASE),
276 kCLOCK_DMA_Lpi2c1 = LPCG_TUPLE(SC_R_I2C_1, ADMA__LPCG_I2C1_IPG_CLK_BASE),
277 kCLOCK_DMA_Lpi2c2 = LPCG_TUPLE(SC_R_I2C_2, ADMA__LPCG_I2C2_IPG_CLK_BASE),
278 kCLOCK_DMA_Lpi2c3 = LPCG_TUPLE(SC_R_I2C_3, ADMA__LPCG_I2C3_IPG_CLK_BASE),
279 kCLOCK_DMA_Ftm0 = LPCG_TUPLE(SC_R_FTM_0, ADMA__LPCG_FTM0_IPG_CLK_BASE),
280 kCLOCK_DMA_Ftm1 = LPCG_TUPLE(SC_R_FTM_1, ADMA__LPCG_FTM1_IPG_CLK_BASE),
281 kCLOCK_DMA_Can0 = LPCG_TUPLE(SC_R_CAN_0, ADMA__LPCG_CAN0_IPG_CLK_BASE),
282 kCLOCK_DMA_Can1 = LPCG_TUPLE(SC_R_CAN_1, ADMA__LPCG_CAN1_IPG_CLK_BASE),
283 kCLOCK_DMA_Can2 = LPCG_TUPLE(SC_R_CAN_2, ADMA__LPCG_CAN2_IPG_CLK_BASE),
284 kCLOCK_HSIO_Gpio = LPCG_TUPLE(SC_R_HSIO_GPIO, HSIO__LPCG_GPIO_IPG_CLK_S_BASE),
285 kCLOCK_LVDS_0_Lpi2c0 = LPCG_TUPLE(SC_R_LVDS_0_I2C_0, NV),
286 kCLOCK_LVDS_0_Lpi2c1 = LPCG_TUPLE(SC_R_LVDS_0_I2C_1, NV),
287 kCLOCK_LVDS_1_Lpi2c0 = LPCG_TUPLE(SC_R_LVDS_1_I2C_0, NV),
288 kCLOCK_LVDS_1_Lpi2c1 = LPCG_TUPLE(SC_R_LVDS_1_I2C_1, NV),
289 kCLOCK_LSIO_Pwm0 = LPCG_TUPLE(SC_R_PWM_0, LSIO__LPCG_PWM0_BASE),
290 kCLOCK_LSIO_Pwm1 = LPCG_TUPLE(SC_R_PWM_1, LSIO__LPCG_PWM1_BASE),
291 kCLOCK_LSIO_Pwm2 = LPCG_TUPLE(SC_R_PWM_2, LSIO__LPCG_PWM2_BASE),
292 kCLOCK_LSIO_Pwm3 = LPCG_TUPLE(SC_R_PWM_3, LSIO__LPCG_PWM3_BASE),
293 kCLOCK_LSIO_Pwm4 = LPCG_TUPLE(SC_R_PWM_4, LSIO__LPCG_PWM4_BASE),
294 kCLOCK_LSIO_Pwm5 = LPCG_TUPLE(SC_R_PWM_5, LSIO__LPCG_PWM5_BASE),
295 kCLOCK_LSIO_Pwm6 = LPCG_TUPLE(SC_R_PWM_6, LSIO__LPCG_PWM6_BASE),
296 kCLOCK_LSIO_Pwm7 = LPCG_TUPLE(SC_R_PWM_7, LSIO__LPCG_PWM7_BASE),
297 kCLOCK_LSIO_Gpio0 = LPCG_TUPLE(SC_R_GPIO_0, LSIO__LPCG_GPIO0_BASE),
298 kCLOCK_LSIO_Gpio1 = LPCG_TUPLE(SC_R_GPIO_1, LSIO__LPCG_GPIO1_BASE),
299 kCLOCK_LSIO_Gpio2 = LPCG_TUPLE(SC_R_GPIO_2, LSIO__LPCG_GPIO2_BASE),
300 kCLOCK_LSIO_Gpio3 = LPCG_TUPLE(SC_R_GPIO_3, LSIO__LPCG_GPIO3_BASE),
301 kCLOCK_LSIO_Gpio4 = LPCG_TUPLE(SC_R_GPIO_4, LSIO__LPCG_GPIO4_BASE),
302 kCLOCK_LSIO_Gpio5 = LPCG_TUPLE(SC_R_GPIO_5, LSIO__LPCG_GPIO5_BASE),
303 kCLOCK_LSIO_Gpio6 = LPCG_TUPLE(SC_R_GPIO_6, LSIO__LPCG_GPIO6_BASE),
304 kCLOCK_LSIO_Gpio7 = LPCG_TUPLE(SC_R_GPIO_7, LSIO__LPCG_GPIO7_BASE),
305 kCLOCK_AUDIO_Gpt0 = LPCG_TUPLE(SC_R_GPT_5, ADMA__LPCG_GPT0_IPG_CLK_24M_BASE),
306 kCLOCK_AUDIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_6, ADMA__LPCG_GPT1_IPG_CLK_24M_BASE),
307 kCLOCK_AUDIO_Gpt2 = LPCG_TUPLE(SC_R_GPT_7, ADMA__LPCG_GPT2_IPG_CLK_24M_BASE),
308 kCLOCK_AUDIO_Gpt3 = LPCG_TUPLE(SC_R_GPT_8, ADMA__LPCG_GPT3_IPG_CLK_24M_BASE),
309 kCLOCK_AUDIO_Gpt4 = LPCG_TUPLE(SC_R_GPT_9, ADMA__LPCG_GPT4_IPG_CLK_24M_BASE),
310 kCLOCK_AUDIO_Gpt5 = LPCG_TUPLE(SC_R_GPT_10, ADMA__LPCG_GPT5_IPG_CLK_24M_BASE),
311 kCLOCK_LSIO_Gpt0 = LPCG_TUPLE(SC_R_GPT_0, LSIO__LPCG_GPT0_BASE),
312 kCLOCK_LSIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_1, LSIO__LPCG_GPT1_BASE),
313 kCLOCK_LSIO_Gpt2 = LPCG_TUPLE(SC_R_GPT_2, LSIO__LPCG_GPT2_BASE),
314 kCLOCK_LSIO_Gpt3 = LPCG_TUPLE(SC_R_GPT_3, LSIO__LPCG_GPT3_BASE),
315 kCLOCK_LSIO_Gpt4 = LPCG_TUPLE(SC_R_GPT_4, LSIO__LPCG_GPT4_BASE),
316 kCLOCK_LSIO_Mu0A = LPCG_TUPLE(SC_R_MU_0A, NV),
317 kCLOCK_LSIO_Mu1A = LPCG_TUPLE(SC_R_MU_1A, NV),
318 kCLOCK_LSIO_Mu2A = LPCG_TUPLE(SC_R_MU_2A, NV),
319 kCLOCK_LSIO_Mu3A = LPCG_TUPLE(SC_R_MU_3A, NV),
320 kCLOCK_LSIO_Mu4A = LPCG_TUPLE(SC_R_MU_4A, NV),
321 kCLOCK_LSIO_Mu5A = LPCG_TUPLE(SC_R_MU_5A, LSIO__LPCG_MU5_MCU_BASE),
322 kCLOCK_LSIO_Mu6A = LPCG_TUPLE(SC_R_MU_6A, LSIO__LPCG_MU6_MCU_BASE),
323 kCLOCK_LSIO_Mu7A = LPCG_TUPLE(SC_R_MU_7A, LSIO__LPCG_MU7_MCU_BASE),
324 kCLOCK_LSIO_Mu8A = LPCG_TUPLE(SC_R_MU_8A, LSIO__LPCG_MU8_MCU_BASE),
325 kCLOCK_LSIO_Mu9A = LPCG_TUPLE(SC_R_MU_9A, LSIO__LPCG_MU9_MCU_BASE),
326 kCLOCK_LSIO_Mu10A = LPCG_TUPLE(SC_R_MU_10A, LSIO__LPCG_MU10_MCU_BASE),
327 kCLOCK_LSIO_Mu11A = LPCG_TUPLE(SC_R_MU_11A, LSIO__LPCG_MU11_MCU_BASE),
328 kCLOCK_LSIO_Mu12A = LPCG_TUPLE(SC_R_MU_12A, LSIO__LPCG_MU12_MCU_BASE),
329 kCLOCK_LSIO_Mu13A = LPCG_TUPLE(SC_R_MU_13A, LSIO__LPCG_MU13_MCU_BASE),
330 kCLOCK_LSIO_Mu5B = LPCG_TUPLE(SC_R_MU_5B, LSIO__LPCG_MU5_DSP_BASE),
331 kCLOCK_LSIO_Mu6B = LPCG_TUPLE(SC_R_MU_6B, LSIO__LPCG_MU6_DSP_BASE),
332 kCLOCK_LSIO_Mu7B = LPCG_TUPLE(SC_R_MU_7B, LSIO__LPCG_MU7_DSP_BASE),
333 kCLOCK_LSIO_Mu8B = LPCG_TUPLE(SC_R_MU_8B, LSIO__LPCG_MU8_DSP_BASE),
334 kCLOCK_LSIO_Mu9B = LPCG_TUPLE(SC_R_MU_9B, LSIO__LPCG_MU9_DSP_BASE),
335 kCLOCK_LSIO_Mu10B = LPCG_TUPLE(SC_R_MU_10B, LSIO__LPCG_MU10_DSP_BASE),
336 kCLOCK_LSIO_Mu11B = LPCG_TUPLE(SC_R_MU_11B, LSIO__LPCG_MU11_DSP_BASE),
337 kCLOCK_LSIO_Mu12B = LPCG_TUPLE(SC_R_MU_12B, LSIO__LPCG_MU12_DSP_BASE),
338 kCLOCK_LSIO_Mu13B = LPCG_TUPLE(SC_R_MU_13B, LSIO__LPCG_MU13_DSP_BASE),
339 kCLOCK_SCU_Mu0B = LPCG_TUPLE(SC_R_SC_MU_0B, NV),
340 kCLOCK_SCU_Mu0A0 = LPCG_TUPLE(SC_R_SC_MU_0A0, NV),
341 kCLOCK_SCU_Mu0A1 = LPCG_TUPLE(SC_R_SC_MU_0A1, NV),
342 kCLOCK_SCU_Mu0A2 = LPCG_TUPLE(SC_R_SC_MU_0A2, NV),
343 kCLOCK_SCU_Mu0A3 = LPCG_TUPLE(SC_R_SC_MU_0A3, NV),
344 kCLOCK_SCU_Mu1A = LPCG_TUPLE(SC_R_SC_MU_1A, NV),
345 kCLOCK_LSIO_Flexspi0 = LPCG_TUPLE(SC_R_FSPI_0, LSIO__LPCG_QSPI0_BASE),
346 kCLOCK_LSIO_Flexspi1 = LPCG_TUPLE(SC_R_FSPI_1, LSIO__LPCG_QSPI1_BASE),
347 kCLOCK_M4_0_Rgpio = LPCG_TUPLE(SC_R_M4_0_RGPIO, NV),
348 kCLOCK_M4_0_Sema42 = LPCG_TUPLE(SC_R_M4_0_SEMA42, NV),
349 kCLOCK_M4_0_Tpm = LPCG_TUPLE(SC_R_M4_0_TPM, CM4__LPCG_TPM_BASE),
350 kCLOCK_M4_0_Lpit = LPCG_TUPLE(SC_R_M4_0_PIT, CM4__LPCG_LPIT_BASE),
351 kCLOCK_M4_0_Lpuart = LPCG_TUPLE(SC_R_M4_0_UART, CM4__LPCG_LPUART_BASE),
352 kCLOCK_M4_0_Lpi2c = LPCG_TUPLE(SC_R_M4_0_I2C, CM4__LPCG_LPI2C_BASE),
353 kCLOCK_M4_0_Intmux = LPCG_TUPLE(SC_R_M4_0_INTMUX, NV),
354 kCLOCK_M4_0_Mu0B = LPCG_TUPLE(SC_R_M4_0_MU_0B, NV),
355 kCLOCK_M4_0_Mu0A0 = LPCG_TUPLE(SC_R_M4_0_MU_0A0, NV),
356 kCLOCK_M4_0_Mu0A1 = LPCG_TUPLE(SC_R_M4_0_MU_0A1, NV),
357 kCLOCK_M4_0_Mu0A2 = LPCG_TUPLE(SC_R_M4_0_MU_0A2, NV),
358 kCLOCK_M4_0_Mu0A3 = LPCG_TUPLE(SC_R_M4_0_MU_0A3, NV),
359 kCLOCK_M4_0_Mu1A = LPCG_TUPLE(SC_R_M4_0_MU_1A, NV),
360 kCLOCK_SCU_Lpuart = LPCG_TUPLE(SC_R_SC_UART, SCU__LPCG_LPUART_BASE),
361 kCLOCK_ADMA_Lpadc0 = LPCG_TUPLE(SC_R_ADC_0, NV),
362 kCLOCK_SCU_Lpi2c = LPCG_TUPLE(SC_R_SC_I2C, SCU__LPCG_LPI2C_BASE),
363 kCLOCK_SCU_Sema42 = LPCG_TUPLE(SC_R_SC_SEMA42, NV),
364 kCLOCK_SCU_Lpit = LPCG_TUPLE(SC_R_SC_PIT, SCU__LPCG_LPIT_BASE),
365 kCLOCK_SCU_Tpm = LPCG_TUPLE(SC_R_SC_TPM, SCU__LPCG_TPM_BASE),
366 kCLOCK_SCU_Intmux = LPCG_TUPLE(SC_R_LAST, NV),
367 kCLOCK_AUDIO_Sai0 = LPCG_TUPLE(SC_R_SAI_0, ADMA__LPCG_SAI0_IPG_CLK_BASE),
368 kCLOCK_AUDIO_Sai1 = LPCG_TUPLE(SC_R_SAI_1, ADMA__LPCG_SAI1_IPG_CLK_BASE),
369 kCLOCK_AUDIO_Sai2 = LPCG_TUPLE(SC_R_SAI_2, ADMA__LPCG_SAI2_IPG_CLK_BASE),
370 kCLOCK_AUDIO_Sai3 = LPCG_TUPLE(SC_R_SAI_3, ADMA__LPCG_SAI3_IPG_CLK_BASE),
371 kCLOCK_AUDIO_Sai4 = LPCG_TUPLE(SC_R_SAI_4, ADMA__LPCG_SAI4_IPG_CLK_BASE),
372 kCLOCK_AUDIO_Sai5 = LPCG_TUPLE(SC_R_SAI_5, ADMA__LPCG_SAI5_IPG_CLK_BASE),
373 kCLOCK_AUDIO_Esai0 = LPCG_TUPLE(SC_R_ESAI_0, ADMA__LPCG_ESAI0_EXTAL_CLK_BASE),
374 kCLOCK_AUDIO_Esai1 = LPCG_TUPLE(SC_R_ESAI_0, NV),
375 kCLOCK_IMAGING_Isi0 = LPCG_TUPLE(SC_R_ISI_CH0, NV),
376 kCLOCK_IMAGING_Isi1 = LPCG_TUPLE(SC_R_ISI_CH1, NV),
377 kCLOCK_IMAGING_Isi2 = LPCG_TUPLE(SC_R_ISI_CH2, NV),
378 kCLOCK_IMAGING_Isi3 = LPCG_TUPLE(SC_R_ISI_CH3, NV),
379 kCLOCK_IMAGING_Isi4 = LPCG_TUPLE(SC_R_ISI_CH4, NV),
380 kCLOCK_IMAGING_Isi5 = LPCG_TUPLE(SC_R_ISI_CH5, NV),
381 kCLOCK_MipiCsi2Rx0 = LPCG_TUPLE(SC_R_CSI_0, NV),
382 kCLOCK_MipiCsi2Rx1 = LPCG_TUPLE(SC_R_CSI_1, NV),
383 kCLOCK_DiMiPiDsiLvds0Lpi2c0 = LPCG_TUPLE(SC_R_MIPI_0_I2C_0, DI_MIPI_DSI_LVDS_0__LPCG_LIS_IPG_CLK_BASE),
384 kCLOCK_DiMiPiDsiLvds0Lpi2c1 = LPCG_TUPLE(SC_R_MIPI_0_I2C_1, DI_MIPI_DSI_LVDS_0__LPCG_LIS_IPG_CLK_BASE),
385 kCLOCK_DiMiPiDsiLvds1Lpi2c0 = LPCG_TUPLE(SC_R_MIPI_1_I2C_0, DI_MIPI_DSI_LVDS_1__LPCG_LIS_IPG_CLK_BASE),
386 kCLOCK_DiMiPiDsiLvds1Lpi2c1 = LPCG_TUPLE(SC_R_MIPI_1_I2C_1, DI_MIPI_DSI_LVDS_1__LPCG_LIS_IPG_CLK_BASE),
387 kCLOCK_CiPiLpi2c = LPCG_TUPLE(SC_R_LAST, NV),
388 kCLOCK_MipiCsiLpi2c = LPCG_TUPLE(SC_R_CSI_0_I2C_0, NV),
389 kCLOCK_MipiDsiHost0 = LPCG_TUPLE(SC_R_MIPI_0, NV),
390 kCLOCK_MipiDsiHost1 = LPCG_TUPLE(SC_R_MIPI_1, NV),
391 kCLOCK_Dpu0 = LPCG_TUPLE(SC_R_DC_0, DC__LPCG_DSP0_CLK_BASE),
392 kCLOCK_Dpu1 = LPCG_TUPLE(SC_R_DC_1, NV),
393 kCLOCK_HDMI_Lpi2c0 = LPCG_TUPLE(SC_R_HDMI_I2C_0, NV),
394 kCLOCK_HDMI_RX_Lpi2c0 = LPCG_TUPLE(SC_R_HDMI_RX_I2C_0, NV),
395 kCLOCK_Ldb0 = LPCG_TUPLE(SC_R_LVDS_0, NV),
396 kCLOCK_Ldb1 = LPCG_TUPLE(SC_R_LVDS_1, NV),
397 kCLOCK_CONNECTIVITY_Enet0 = LPCG_TUPLE(SC_R_ENET_0, CONNECTIVITY__LPCG_ENET0_BASE),
398 kCLOCK_CONNECTIVITY_Enet1 = LPCG_TUPLE(SC_R_ENET_1, CONNECTIVITY__LPCG_ENET1_BASE),
399 kCLOCK_CONNECTIVITY_Usdhc0 = LPCG_TUPLE(SC_R_SDHC_0, CONNECTIVITY__LPCG_USDHC0_BASE),
400 kCLOCK_CONNECTIVITY_Usdhc1 = LPCG_TUPLE(SC_R_SDHC_1, CONNECTIVITY__LPCG_USDHC1_BASE),
401 kCLOCK_AUDIO_Pll0 = LPCG_TUPLE(SC_R_AUDIO_PLL_0, NV),
402 kCLOCK_AUDIO_Pll1 = LPCG_TUPLE(SC_R_AUDIO_PLL_1, NV),
403 kCLOCK_CAAM_JR1 = LPCG_TUPLE(SC_R_CAAM_JR1, NV),
404 kCLOCK_CAAM_JR2 = LPCG_TUPLE(SC_R_CAAM_JR2, NV),
405 kCLOCK_CAAM_JR3 = LPCG_TUPLE(SC_R_CAAM_JR3, NV),
406 kCLOCK_CiPi0 = LPCG_TUPLE(SC_R_PI_0, NV),
407 kCLOCK_Isi0 = LPCG_TUPLE(SC_R_ISI_CH0, NV),
408 kCLOCK_Isi1 = LPCG_TUPLE(SC_R_ISI_CH1, NV),
409 kCLOCK_Isi2 = LPCG_TUPLE(SC_R_ISI_CH2, NV),
410 kCLOCK_Isi3 = LPCG_TUPLE(SC_R_ISI_CH3, NV),
411 kCLOCK_Isi4 = LPCG_TUPLE(SC_R_ISI_CH4, NV),
412 kCLOCK_Isi5 = LPCG_TUPLE(SC_R_ISI_CH5, NV),
413 kCLOCK_Isi6 = LPCG_TUPLE(SC_R_ISI_CH6, NV),
414 kCLOCK_Isi7 = LPCG_TUPLE(SC_R_ISI_CH7, NV),
415 kCLOCK_IpInvalid = LPCG_TUPLE(SC_R_LAST, NV) /* The selected IP does not support clock control. */
416} clock_ip_name_t;
417
418#if defined(__cplusplus)
419extern "C" {
420#endif /* _cplusplus */
421
422/*!
423 * @brief Initialize Clock module.
424 *
425 * @param ipc IPC handle for communication with SCU.
426 */
427void CLOCK_Init(sc_ipc_t ipc);
428
429/*!
430 * @brief Deinitialize Clock module.
431 */
432void CLOCK_Deinit(void);
433
434/*!
435 * @brief Enable the clock for specific IP, with gate setting.
436 *
437 * @param name Which clock to enable, see \ref clock_ip_name_t.
438 * @param gate 0: clock always on, 1: HW auto clock gating.
439 * @return true if success, false if failure.
440 */
441bool CLOCK_EnableClockExt(clock_ip_name_t name, uint32_t gate);
442
443/*!
444 * @brief Enable the clock for specific IP.
445 *
446 * @param name Which clock to enable, see \ref clock_ip_name_t.
447 * @return true for success, false for failure.
448 */
449static inline bool CLOCK_EnableClock(clock_ip_name_t name)
450{
451 return CLOCK_EnableClockExt(name, 0);
452}
453
454/*!
455 * @brief Disable the clock for specific IP.
456 *
457 * @param name Which clock to disable, see \ref clock_ip_name_t.
458 * @return true for success, false for failure.
459 */
460bool CLOCK_DisableClock(clock_ip_name_t name);
461
462/*!
463 * @brief Set the clock frequency for specific IP module.
464 *
465 * This function sets the IP module clock frequency.
466 *
467 * @param name Which peripheral to check, see \ref clock_ip_name_t.
468 * @param freq Target clock frequency value in hertz.
469 * @return the Real clock frequency value in hertz, or 0 if failed
470 */
471uint32_t CLOCK_SetIpFreq(clock_ip_name_t name, uint32_t freq);
472
473/*!
474 * @brief Get the clock frequency for a specific IP module.
475 *
476 * This function gets the IP module clock frequency.
477 *
478 * @param name Which peripheral to get, see \ref clock_ip_name_t.
479 * @return Clock frequency value in hertz, or 0 if failed
480 */
481uint32_t CLOCK_GetIpFreq(clock_ip_name_t name);
482
483/*!
484 * @brief Gets the clock frequency for a specific clock name.
485 *
486 * This function checks the current clock configurations and then calculates
487 * the clock frequency for a specific clock name defined in clock_name_t.
488 *
489 * @param name Clock names defined in clock_name_t
490 * @return Clock frequency value in hertz
491 */
492uint32_t CLOCK_GetFreq(clock_name_t name);
493
494/*!
495 * @brief Get the core clock or system clock frequency.
496 *
497 * @return Clock frequency in Hz.
498 */
499uint32_t CLOCK_GetCoreSysClkFreq(void);
500
501/*!
502 * @brief Config the LPCG cell for specific IP.
503 *
504 * @param name Which clock to enable, see \ref clock_ip_name_t.
505 * @param swGate Software clock gating. 0: clock is gated; 1: clock is enabled
506 * @param hwGate Hardware auto gating. 0: disable the HW clock gate control; 1: HW clock gating is enabled
507 */
508void CLOCK_ConfigLPCG(clock_ip_name_t name, bool swGate, bool hwGate);
509
510/*!
511 * @brief Set LPCG gate for specific LPCG.
512 *
513 * @param regBase LPCG register base address.
514 * @param swGate Software clock gating. 0: clock is gated; 1: clock is enabled
515 * @param hwGate Hardware auto gating. 0: disable the HW clock gate control; 1: HW clock gating is enabled
516 * @param bitsMask The available bits in LPCG register. Each bit indicate the corresponding bit is available or not.
517 */
518void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask);
519
520#if defined(__cplusplus)
521}
522#endif /* __cplusplus */
523
524/*! @} */
525
526#endif /* _FSL_CLOCK_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/fsl_memory.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/fsl_memory.h
new file mode 100644
index 000000000..566dccb7d
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/fsl_memory.h
@@ -0,0 +1,108 @@
1/*
2 * Copyright 2017-2018 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef _FSL_MEMORY_H_
8#define _FSL_MEMORY_H_
9
10#include "fsl_common.h"
11
12/*******************************************************************************
13 * Definitions
14 ******************************************************************************/
15/* Component ID definition, used by tools. */
16#ifndef FSL_COMPONENT_ID
17#define FSL_COMPONENT_ID "platform.drivers.memory"
18#endif
19/* The CM4 subsystem local TCM start address, refer to Reference Manual for detailed information */
20#define FSL_MEM_M4_TCM_BEGIN 0x1FFE0000U
21/* The CM4 subsystem local TCM end address, refer to Reference Manual for detailed information */
22#define FSL_MEM_M4_TCM_END 0x2001FFFFU
23
24/* The alias start address for CM4 subsystem */
25#define FSL_MEM_M4_ALIAS_BEGIN 0x21000000U
26/* The alias end address for CM4 subsystem */
27#define FSL_MEM_M4_ALIAS_END 0x211FFFFFU
28/*
29 This alias allows the ROM and OCRAM to be mapped to the CM4 system address space without the need
30 to enable and configure SMMU.
31 System-level address 0x0000_0000 to 0x001F_FFFF is mapped to the CM4 system address space 0x2100_0000 to 0x211F_FFFF
32*/
33#define FSL_MEM_M4_ALIAS_OFFSET 0x21000000U
34
35#define FSL_MEM_M4_TCM_OFFSET 0x15000000U
36
37typedef enum _mem_direction
38{
39 kMEMORY_Local2DMA = 0,
40 kMEMORY_DMA2Local,
41} mem_direction_t;
42
43/*******************************************************************************
44 * API
45 ******************************************************************************/
46#if defined(__cplusplus)
47extern "C" {
48#endif
49/*!
50 * @brief Convert the memory map address.
51 *
52 * This function convert the address between system mapped address and native mapped address.
53 * There maybe offset between subsystem native address and system address for some memory,
54 * this funciton convert the address to different memory map.
55 * @param addr address need to be converted.
56 * @param direction convert direction.
57 * @return the converted address
58 */
59static inline uint32_t MEMORY_ConvertMemoryMapAddress(uint32_t addr, mem_direction_t direction)
60{
61 uint32_t dest;
62
63 switch (direction)
64 {
65 case kMEMORY_Local2DMA:
66 {
67 if ((addr >= FSL_MEM_M4_TCM_BEGIN) && (addr <= FSL_MEM_M4_TCM_END))
68 {
69 dest = addr + FSL_MEM_M4_TCM_OFFSET;
70 }
71 else if ((addr >= FSL_MEM_M4_ALIAS_BEGIN) && (addr <= FSL_MEM_M4_ALIAS_END))
72 {
73 dest = addr - FSL_MEM_M4_ALIAS_OFFSET;
74 }
75 else
76 {
77 dest = addr;
78 }
79 break;
80 }
81 case kMEMORY_DMA2Local:
82 {
83 if ((addr >= (FSL_MEM_M4_TCM_BEGIN + FSL_MEM_M4_TCM_OFFSET)) &&
84 (addr <= (FSL_MEM_M4_TCM_END + FSL_MEM_M4_TCM_OFFSET)))
85 {
86 dest = addr - FSL_MEM_M4_TCM_OFFSET;
87 }
88 else if (addr <= (FSL_MEM_M4_ALIAS_END - FSL_MEM_M4_ALIAS_OFFSET))
89 {
90 dest = addr + FSL_MEM_M4_ALIAS_OFFSET;
91 }
92 else
93 {
94 dest = addr;
95 }
96 break;
97 }
98 default:
99 dest = addr;
100 break;
101 }
102
103 return dest;
104}
105#if defined(__cplusplus)
106}
107#endif /* __cplusplus */
108#endif /* _FSL_MEMORY_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 13:27:39 +0100