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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_clock.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_iomuxc.cmake15
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_reset.cmake14
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_romapi.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_soc_flexram_allocate.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_clock.c1175
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_clock.h1431
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_flexram_allocate.c157
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_flexram_allocate.h99
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_iomuxc.h564
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_romapi.c170
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_romapi.h554
12 files changed, 4227 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_clock.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_clock.cmake
new file mode 100644
index 000000000..154d6a23a
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_clock.cmake
@@ -0,0 +1,16 @@
1if(NOT DRIVER_CLOCK_INCLUDED)
2
3 set(DRIVER_CLOCK_INCLUDED true CACHE BOOL "driver_clock component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 ${CMAKE_CURRENT_LIST_DIR}/fsl_clock.c
7 )
8
9 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
10 ${CMAKE_CURRENT_LIST_DIR}/.
11 )
12
13
14 include(driver_common)
15
16endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_iomuxc.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_iomuxc.cmake
new file mode 100644
index 000000000..1de06623a
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_iomuxc.cmake
@@ -0,0 +1,15 @@
1if(NOT DRIVER_IOMUXC_INCLUDED)
2
3 set(DRIVER_IOMUXC_INCLUDED true CACHE BOOL "driver_iomuxc component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 )
7
8 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
9 ${CMAKE_CURRENT_LIST_DIR}/.
10 )
11
12
13 include(driver_common)
14
15endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_reset.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_reset.cmake
new file mode 100644
index 000000000..989530f6f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_reset.cmake
@@ -0,0 +1,14 @@
1if(NOT DRIVER_RESET_INCLUDED)
2
3 set(DRIVER_RESET_INCLUDED true CACHE BOOL "driver_reset component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 )
7
8 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
9 ${CMAKE_CURRENT_LIST_DIR}/.
10 )
11
12
13
14endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_romapi.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_romapi.cmake
new file mode 100644
index 000000000..392bd6bc8
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_romapi.cmake
@@ -0,0 +1,16 @@
1if(NOT DRIVER_ROMAPI_INCLUDED)
2
3 set(DRIVER_ROMAPI_INCLUDED true CACHE BOOL "driver_romapi component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 ${CMAKE_CURRENT_LIST_DIR}/fsl_romapi.c
7 )
8
9 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
10 ${CMAKE_CURRENT_LIST_DIR}/.
11 )
12
13
14 include(driver_common)
15
16endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_soc_flexram_allocate.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_soc_flexram_allocate.cmake
new file mode 100644
index 000000000..9aa4d4706
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/driver_soc_flexram_allocate.cmake
@@ -0,0 +1,16 @@
1if(NOT DRIVER_SOC_FLEXRAM_ALLOCATE_INCLUDED)
2
3 set(DRIVER_SOC_FLEXRAM_ALLOCATE_INCLUDED true CACHE BOOL "driver_soc_flexram_allocate component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 ${CMAKE_CURRENT_LIST_DIR}/fsl_flexram_allocate.c
7 )
8
9 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
10 ${CMAKE_CURRENT_LIST_DIR}/.
11 )
12
13
14 include(driver_common)
15
16endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_clock.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_clock.c
new file mode 100644
index 000000000..f7077d032
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_clock.c
@@ -0,0 +1,1175 @@
1/*
2 * Copyright 2018-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_clock.h"
9/* Component ID definition, used by tools. */
10#ifndef FSL_COMPONENT_ID
11#define FSL_COMPONENT_ID "platform.drivers.clock"
12#endif
13
14/*******************************************************************************
15 * Definitions
16 ******************************************************************************/
17/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to
18achieve better performance, it is depend on the IDE Floating point settings, if double precision is selected
19in IDE, clock_64b_t will switch to double type automatically. only support IAR and MDK here */
20#if __FPU_USED
21
22#if (defined(__ICCARM__))
23
24#if (__ARMVFP__ >= __ARMFPV5__) && \
25 (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/
26typedef double clock_64b_t;
27#else
28typedef uint64_t clock_64b_t;
29#endif
30
31#elif (defined(__GNUC__))
32
33#if (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/
34typedef double clock_64b_t;
35#else
36typedef uint64_t clock_64b_t;
37#endif
38
39#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
40
41#if defined __TARGET_FPU_FPV5_D16
42typedef double clock_64b_t;
43#else
44typedef uint64_t clock_64b_t;
45#endif
46
47#else
48typedef uint64_t clock_64b_t;
49#endif
50
51#else
52typedef uint64_t clock_64b_t;
53#endif
54
55/*******************************************************************************
56 * Variables
57 ******************************************************************************/
58
59/* External XTAL (OSC) clock frequency. */
60volatile uint32_t g_xtalFreq;
61/* External RTC XTAL clock frequency. */
62volatile uint32_t g_rtcXtalFreq;
63
64/*******************************************************************************
65 * Prototypes
66 ******************************************************************************/
67
68/*!
69 * @brief Get the periph clock frequency.
70 *
71 * @return Periph clock frequency in Hz.
72 */
73static uint32_t CLOCK_GetPeriphClkFreq(void);
74
75/*!
76 * @brief Get the frequency of PLL USB1 software clock.
77 *
78 * @return The frequency of PLL USB1 software clock.
79 */
80static uint32_t CLOCK_GetPllUsb1SWFreq(void);
81
82/*******************************************************************************
83 * Code
84 ******************************************************************************/
85
86static uint32_t CLOCK_GetPeriphClkFreq(void)
87{
88 uint32_t freq;
89
90 /* Periph_clk2_clk ---> Periph_clk */
91 if ((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) != 0UL)
92 {
93 switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
94 {
95 /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */
96 case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
97 freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1);
98 break;
99
100 /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */
101 case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
102 freq = CLOCK_GetOscFreq();
103 break;
104
105 case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
106 freq = CLOCK_GetPllFreq(kCLOCK_PllSys);
107 break;
108
109 case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
110 default:
111 freq = 0U;
112 break;
113 }
114
115 freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U);
116 }
117 /* Pre_Periph_clk ---> Periph_clk */
118 else
119 {
120 switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
121 {
122 /* PLL2 */
123 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U):
124 freq = CLOCK_GetPllFreq(kCLOCK_PllSys);
125 break;
126
127 /* PLL3 PFD3 */
128 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U):
129 freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd3);
130 break;
131
132 /* PLL2 PFD3 */
133 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U):
134 freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd3);
135 break;
136
137 /* PLL6 divided(/1) */
138 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U):
139 freq = 500000000U;
140 break;
141
142 default:
143 freq = 0U;
144 break;
145 }
146 }
147
148 return freq;
149}
150
151static uint32_t CLOCK_GetPllUsb1SWFreq(void)
152{
153 uint32_t freq;
154
155 switch ((CCM->CCSR & CCM_CCSR_PLL3_SW_CLK_SEL_MASK) >> CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)
156 {
157 case 0:
158 {
159 freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1);
160 break;
161 }
162 case 1:
163 {
164 freq = 24000000UL;
165 break;
166 }
167 default:
168 freq = 0UL;
169 break;
170 }
171
172 return freq;
173}
174
175/*!
176 * brief Initialize the external 24MHz clock.
177 *
178 * This function supports two modes:
179 * 1. Use external crystal oscillator.
180 * 2. Bypass the external crystal oscillator, using input source clock directly.
181 *
182 * After this function, please call ref CLOCK_SetXtal0Freq to inform clock driver
183 * the external clock frequency.
184 *
185 * param bypassXtalOsc Pass in true to bypass the external crystal oscillator.
186 * note This device does not support bypass external crystal oscillator, so
187 * the input parameter should always be false.
188 */
189void CLOCK_InitExternalClk(bool bypassXtalOsc)
190{
191 /* This device does not support bypass XTAL OSC. */
192 assert(!bypassXtalOsc);
193
194 CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power up */
195 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0UL)
196 {
197 }
198 CCM_ANALOG->MISC0_SET = (uint32_t)CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; /* detect freq */
199 while ((CCM_ANALOG->MISC0 & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) == 0UL)
200 {
201 }
202 CCM_ANALOG->MISC0_CLR = (uint32_t)CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK;
203}
204
205/*!
206 * brief Deinitialize the external 24MHz clock.
207 *
208 * This function disables the external 24MHz clock.
209 *
210 * After this function, please call ref CLOCK_SetXtal0Freq to set external clock
211 * frequency to 0.
212 */
213void CLOCK_DeinitExternalClk(void)
214{
215 CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power down */
216}
217
218/*!
219 * brief Switch the OSC.
220 *
221 * This function switches the OSC source for SoC.
222 *
223 * param osc OSC source to switch to.
224 */
225void CLOCK_SwitchOsc(clock_osc_t osc)
226{
227 if (osc == kCLOCK_RcOsc)
228 {
229 XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK;
230 }
231 else
232 {
233 XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK;
234 }
235}
236
237/*!
238 * brief Initialize the RC oscillator 24MHz clock.
239 */
240void CLOCK_InitRcOsc24M(void)
241{
242 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK;
243}
244
245/*!
246 * brief Power down the RCOSC 24M clock.
247 */
248void CLOCK_DeinitRcOsc24M(void)
249{
250 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK;
251}
252
253/*!
254 * brief Gets the AHB clock frequency.
255 *
256 * return The AHB clock frequency value in hertz.
257 */
258uint32_t CLOCK_GetAhbFreq(void)
259{
260 return CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U);
261}
262
263/*!
264 * brief Gets the SEMC clock frequency.
265 *
266 * return The SEMC clock frequency value in hertz.
267 */
268uint32_t CLOCK_GetSemcFreq(void)
269{
270 uint32_t freq;
271
272 /* SEMC alternative clock ---> SEMC Clock */
273 if ((CCM->CBCDR & CCM_CBCDR_SEMC_CLK_SEL_MASK) != 0UL)
274 {
275 /* PLL3 PFD1 ---> SEMC alternative clock ---> SEMC Clock */
276 if ((CCM->CBCDR & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) != 0UL)
277 {
278 freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1);
279 }
280 /* PLL2 PFD2 ---> SEMC alternative clock ---> SEMC Clock */
281 else
282 {
283 freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2);
284 }
285 }
286 /* Periph_clk ---> SEMC Clock */
287 else
288 {
289 freq = CLOCK_GetPeriphClkFreq();
290 }
291
292 freq /= (((CCM->CBCDR & CCM_CBCDR_SEMC_PODF_MASK) >> CCM_CBCDR_SEMC_PODF_SHIFT) + 1U);
293
294 return freq;
295}
296
297/*!
298 * brief Gets the IPG clock frequency.
299 *
300 * return The IPG clock frequency value in hertz.
301 */
302uint32_t CLOCK_GetIpgFreq(void)
303{
304 return CLOCK_GetAhbFreq() / (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U);
305}
306
307/*!
308 * brief Gets the PER clock frequency.
309 *
310 * return The PER clock frequency value in hertz.
311 */
312uint32_t CLOCK_GetPerClkFreq(void)
313{
314 uint32_t freq;
315
316 /* Osc_clk ---> PER Clock*/
317 if ((CCM->CSCMR1 & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) != 0UL)
318 {
319 freq = CLOCK_GetOscFreq();
320 }
321 /* Periph_clk ---> AHB Clock ---> IPG Clock ---> PER Clock */
322 else
323 {
324 freq = CLOCK_GetIpgFreq();
325 }
326
327 freq /= (((CCM->CSCMR1 & CCM_CSCMR1_PERCLK_PODF_MASK) >> CCM_CSCMR1_PERCLK_PODF_SHIFT) + 1U);
328
329 return freq;
330}
331
332/*!
333 * brief Gets the clock frequency for a specific clock name.
334 *
335 * This function checks the current clock configurations and then calculates
336 * the clock frequency for a specific clock name defined in clock_name_t.
337 *
338 * param clockName Clock names defined in clock_name_t
339 * return Clock frequency value in hertz
340 */
341uint32_t CLOCK_GetFreq(clock_name_t name)
342{
343 uint32_t freq;
344
345 switch (name)
346 {
347 case kCLOCK_CpuClk:
348 case kCLOCK_AhbClk:
349 freq = CLOCK_GetAhbFreq();
350 break;
351
352 case kCLOCK_SemcClk:
353 freq = CLOCK_GetSemcFreq();
354 break;
355
356 case kCLOCK_IpgClk:
357 freq = CLOCK_GetIpgFreq();
358 break;
359
360 case kCLOCK_PerClk:
361 freq = CLOCK_GetPerClkFreq();
362 break;
363
364 case kCLOCK_OscClk:
365 freq = CLOCK_GetOscFreq();
366 break;
367 case kCLOCK_RtcClk:
368 freq = CLOCK_GetRtcFreq();
369 break;
370 case kCLOCK_Usb1PllClk:
371 freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1);
372 break;
373 case kCLOCK_Usb1PllPfd0Clk:
374 freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd0);
375 break;
376 case kCLOCK_Usb1PllPfd1Clk:
377 freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1);
378 break;
379 case kCLOCK_Usb1PllPfd2Clk:
380 freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd2);
381 break;
382 case kCLOCK_Usb1PllPfd3Clk:
383 freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd3);
384 break;
385 case kCLOCK_Usb1SwClk:
386 freq = CLOCK_GetPllUsb1SWFreq();
387 break;
388 case kCLOCK_Usb1Sw60MClk:
389 freq = CLOCK_GetPllUsb1SWFreq() / 8UL;
390 break;
391 case kCLOCK_Usb1Sw80MClk:
392 freq = CLOCK_GetPllUsb1SWFreq() / 6UL;
393 break;
394 case kCLOCK_SysPllClk:
395 freq = CLOCK_GetPllFreq(kCLOCK_PllSys);
396 break;
397 case kCLOCK_SysPllPfd0Clk:
398 freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0);
399 break;
400 case kCLOCK_SysPllPfd1Clk:
401 freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd1);
402 break;
403 case kCLOCK_SysPllPfd2Clk:
404 freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2);
405 break;
406 case kCLOCK_SysPllPfd3Clk:
407 freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd3);
408 break;
409 case kCLOCK_EnetPll500MClk:
410 freq = CLOCK_GetPllFreq(kCLOCK_PllEnet500M);
411 break;
412 case kCLOCK_AudioPllClk:
413 freq = CLOCK_GetPllFreq(kCLOCK_PllAudio);
414 break;
415 default:
416 freq = 0U;
417 break;
418 }
419
420 return freq;
421}
422
423/*!
424 * brief Gets the frequency of selected clock root.
425 *
426 * param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t.
427 * return The frequency of selected clock root.
428 */
429uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot)
430{
431 const clock_name_t clockRootSourceArray[][4] = CLOCK_ROOT_SOUCE;
432 const clock_mux_t clockRootMuxTupleArray[] = CLOCK_ROOT_MUX_TUPLE;
433 const clock_div_t clockRootDivTupleArray[][2] = CLOCK_ROOT_DIV_TUPLE;
434 uint32_t freq = 0UL;
435 clock_mux_t clockRootMuxTuple = clockRootMuxTupleArray[(uint8_t)clockRoot];
436 clock_div_t clockRootPreDivTuple = clockRootDivTupleArray[(uint8_t)clockRoot][0];
437 clock_div_t clockRootPostDivTuple = clockRootDivTupleArray[(uint8_t)clockRoot][1];
438 uint32_t clockRootMuxValue = (CCM_TUPLE_REG(CCM, clockRootMuxTuple) & CCM_TUPLE_MASK(clockRootMuxTuple)) >>
439 CCM_TUPLE_SHIFT(clockRootMuxTuple);
440 clock_name_t clockSourceName;
441
442 clockSourceName = clockRootSourceArray[(uint8_t)clockRoot][clockRootMuxValue];
443
444 assert(clockSourceName != kCLOCK_NoneName);
445
446 freq = CLOCK_GetFreq(clockSourceName);
447
448 if (clockRootPreDivTuple != kCLOCK_NonePreDiv)
449 {
450 freq /= ((CCM_TUPLE_REG(CCM, clockRootPreDivTuple) & CCM_TUPLE_MASK(clockRootPreDivTuple)) >>
451 CCM_TUPLE_SHIFT(clockRootPreDivTuple)) +
452 1UL;
453 }
454
455 freq /= ((CCM_TUPLE_REG(CCM, clockRootPostDivTuple) & CCM_TUPLE_MASK(clockRootPostDivTuple)) >>
456 CCM_TUPLE_SHIFT(clockRootPostDivTuple)) +
457 1UL;
458
459 return freq;
460}
461
462/*! brief Enable USB HS clock.
463 *
464 * This function only enables the access to USB HS prepheral, upper layer
465 * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
466 * clock to use USB HS.
467 *
468 * param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused.
469 * param freq USB HS does not care about the clock source, so this parameter is ignored.
470 * retval true The clock is set successfully.
471 * retval false The clock source is invalid to get proper USB HS clock.
472 */
473bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
474{
475 uint32_t i;
476 CCM->CCGR6 |= CCM_CCGR6_CG0_MASK;
477 USB->USBCMD |= USBHS_USBCMD_RST_MASK;
478
479 /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/
480 for (i = 0; i < 400000UL; i++)
481 {
482 __ASM("nop");
483 }
484 PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) |
485 (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK);
486 return true;
487}
488
489/*! brief Enable USB HS PHY PLL clock.
490 *
491 * This function enables the internal 480MHz USB PHY PLL clock.
492 *
493 * param src USB HS PHY PLL clock source.
494 * param freq The frequency specified by src.
495 * retval true The clock is set successfully.
496 * retval false The clock source is invalid to get proper USB HS clock.
497 */
498bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
499{
500 const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
501 if ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK) != 0UL)
502 {
503 CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
504 }
505 else
506 {
507 CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
508 }
509 USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */
510 USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK;
511
512 USBPHY->PWD = 0;
513 USBPHY->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK |
514 USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK;
515 return true;
516}
517
518/*! brief Disable USB HS PHY PLL clock.
519 *
520 * This function disables USB HS PHY PLL clock.
521 */
522void CLOCK_DisableUsbhs0PhyPllClock(void)
523{
524 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
525 USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
526}
527
528/*!
529 * brief Initialize the System PLL.
530 *
531 * This function initializes the System PLL with specific settings
532 *
533 * param config Configuration to set to PLL.
534 */
535void CLOCK_InitSysPll(const clock_sys_pll_config_t *config)
536{
537 /* Bypass PLL first */
538 CCM_ANALOG->PLL_SYS = (CCM_ANALOG->PLL_SYS & (~CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)) |
539 CCM_ANALOG_PLL_SYS_BYPASS_MASK | CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(config->src);
540
541 CCM_ANALOG->PLL_SYS =
542 (CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) |
543 CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider);
544
545 /* Initialize the fractional mode */
546 CCM_ANALOG->PLL_SYS_NUM = CCM_ANALOG_PLL_SYS_NUM_A(config->numerator);
547 CCM_ANALOG->PLL_SYS_DENOM = CCM_ANALOG_PLL_SYS_DENOM_B(config->denominator);
548
549 /* Initialize the spread spectrum mode */
550 CCM_ANALOG->PLL_SYS_SS = CCM_ANALOG_PLL_SYS_SS_STEP(config->ss_step) |
551 CCM_ANALOG_PLL_SYS_SS_ENABLE(config->ss_enable) |
552 CCM_ANALOG_PLL_SYS_SS_STOP(config->ss_stop);
553
554 while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0UL)
555 {
556 }
557
558 /* Disable Bypass */
559 CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_BYPASS_MASK;
560}
561
562/*!
563 * brief De-initialize the System PLL.
564 */
565void CLOCK_DeinitSysPll(void)
566{
567 CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_POWERDOWN_MASK;
568}
569
570/*!
571 * brief Initialize the USB1 PLL.
572 *
573 * This function initializes the USB1 PLL with specific settings
574 *
575 * param config Configuration to set to PLL.
576 */
577void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config)
578{
579 /* Bypass PLL first */
580 CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)) |
581 CCM_ANALOG_PLL_USB1_BYPASS_MASK | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(config->src);
582
583 CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)) |
584 CCM_ANALOG_PLL_USB1_ENABLE_MASK | CCM_ANALOG_PLL_USB1_POWER_MASK |
585 CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider);
586
587 while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0UL)
588 {
589 }
590
591 /* Disable Bypass */
592 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK;
593}
594
595/*!
596 * brief Deinitialize the USB1 PLL.
597 */
598void CLOCK_DeinitUsb1Pll(void)
599{
600 CCM_ANALOG->PLL_USB1 = 0U;
601}
602
603/*!
604 * brief Initializes the Audio PLL.
605 *
606 * This function initializes the Audio PLL with specific settings
607 *
608 * param config Configuration to set to PLL.
609 */
610void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)
611{
612 uint32_t pllAudio;
613 uint32_t misc2 = 0;
614
615 /* Bypass PLL first */
616 CCM_ANALOG->PLL_AUDIO = (CCM_ANALOG->PLL_AUDIO & (~CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)) |
617 CCM_ANALOG_PLL_AUDIO_BYPASS_MASK | CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(config->src);
618
619 CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator);
620 CCM_ANALOG->PLL_AUDIO_DENOM = CCM_ANALOG_PLL_AUDIO_DENOM_B(config->denominator);
621
622 /*
623 * Set post divider:
624 *
625 * ------------------------------------------------------------------------
626 * | config->postDivider | PLL_AUDIO[POST_DIV_SELECT] | MISC2[AUDIO_DIV] |
627 * ------------------------------------------------------------------------
628 * | 1 | 2 | 0 |
629 * ------------------------------------------------------------------------
630 * | 2 | 1 | 0 |
631 * ------------------------------------------------------------------------
632 * | 4 | 2 | 3 |
633 * ------------------------------------------------------------------------
634 * | 8 | 1 | 3 |
635 * ------------------------------------------------------------------------
636 * | 16 | 0 | 3 |
637 * ------------------------------------------------------------------------
638 */
639 pllAudio =
640 (CCM_ANALOG->PLL_AUDIO & (~(CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK | CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK))) |
641 CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(config->loopDivider);
642
643 switch (config->postDivider)
644 {
645 case 16:
646 pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0);
647 misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
648 break;
649
650 case 8:
651 pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1);
652 misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
653 break;
654
655 case 4:
656 pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2);
657 misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
658 break;
659
660 case 2:
661 pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1);
662 break;
663
664 default:
665 pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2);
666 break;
667 }
668
669 CCM_ANALOG->MISC2 =
670 (CCM_ANALOG->MISC2 & ~(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)) | misc2;
671
672 CCM_ANALOG->PLL_AUDIO = pllAudio;
673
674 while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0UL)
675 {
676 }
677
678 /* Disable Bypass */
679 CCM_ANALOG->PLL_AUDIO &= ~CCM_ANALOG_PLL_AUDIO_BYPASS_MASK;
680}
681
682/*!
683 * brief De-initialize the Audio PLL.
684 */
685void CLOCK_DeinitAudioPll(void)
686{
687 CCM_ANALOG->PLL_AUDIO = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK;
688}
689
690/*!
691 * brief Initialize the ENET PLL.
692 *
693 * This function initializes the ENET PLL with specific settings.
694 *
695 * param config Configuration to set to PLL.
696 */
697void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config)
698{
699 uint32_t enet_pll = 0;
700
701 CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)) |
702 CCM_ANALOG_PLL_ENET_BYPASS_MASK | CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(config->src);
703
704 if (config->enableClkOutput500M)
705 {
706 enet_pll |= CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK;
707 }
708
709 CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)) | enet_pll;
710
711 /* Wait for stable */
712 while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0UL)
713 {
714 }
715
716 /* Disable Bypass */
717 CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK;
718}
719
720/*!
721 * brief Deinitialize the ENET PLL.
722 *
723 * This function disables the ENET PLL.
724 */
725void CLOCK_DeinitEnetPll(void)
726{
727 CCM_ANALOG->PLL_ENET = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK;
728}
729
730/*!
731 * brief Get current PLL output frequency.
732 *
733 * This function get current output frequency of specific PLL
734 *
735 * param pll pll name to get frequency.
736 * return The PLL output frequency in hertz.
737 */
738uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
739{
740 uint32_t freq;
741 uint32_t divSelect;
742 clock_64b_t freqTmp;
743
744 /* check if PLL is enabled */
745 if (!CLOCK_IsPllEnabled(CCM_ANALOG, pll))
746 {
747 return 0U;
748 }
749
750 /* get pll reference clock */
751 freq = CLOCK_GetPllBypassRefClk(CCM_ANALOG, pll);
752
753 /* check if pll is bypassed */
754 if (CLOCK_IsPllBypassed(CCM_ANALOG, pll))
755 {
756 return freq;
757 }
758
759 switch (pll)
760 {
761 case kCLOCK_PllSys:
762 /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
763 freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_SYS_NUM)));
764 freqTmp /= ((clock_64b_t)(CCM_ANALOG->PLL_SYS_DENOM));
765
766 if ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) != 0UL)
767 {
768 freq *= 22U;
769 }
770 else
771 {
772 freq *= 20U;
773 }
774
775 freq += (uint32_t)freqTmp;
776 break;
777
778 case kCLOCK_PllUsb1:
779 freq = (freq * (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0UL) ? 22U : 20U));
780 break;
781
782 case kCLOCK_PllAudio:
783 /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
784 divSelect =
785 (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT;
786
787 freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_NUM)));
788 freqTmp /= ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_DENOM));
789
790 freq = freq * divSelect + (uint32_t)freqTmp;
791
792 /* AUDIO PLL output = PLL output frequency / POSTDIV. */
793
794 /*
795 * Post divider:
796 *
797 * PLL_AUDIO[POST_DIV_SELECT]:
798 * 0x00: 4
799 * 0x01: 2
800 * 0x02: 1
801 *
802 * MISC2[AUDO_DIV]:
803 * 0x00: 1
804 * 0x01: 2
805 * 0x02: 1
806 * 0x03: 4
807 */
808 switch (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
809 {
810 case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0U):
811 freq = freq >> 2U;
812 break;
813
814 case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1U):
815 freq = freq >> 1U;
816 break;
817
818 case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2U):
819 freq = freq >> 0U;
820 break;
821
822 default:
823 assert(false);
824 break;
825 }
826
827 switch (CCM_ANALOG->MISC2 & (CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK))
828 {
829 case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(1) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1):
830 freq >>= 2U;
831 break;
832
833 case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(0) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1):
834 freq >>= 1U;
835 break;
836
837 case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(0) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(0):
838 case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(1) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(0):
839 freq >>= 0U;
840 break;
841
842 default:
843 assert(false);
844 break;
845 }
846 break;
847
848 case kCLOCK_PllEnet500M:
849 /* PLL6 is fixed at 25MHz. */
850 freq = 500000000UL;
851 break;
852
853 default:
854 freq = 0U;
855 break;
856 }
857
858 return freq;
859}
860
861/*!
862 * brief Initialize the System PLL PFD.
863 *
864 * This function initializes the System PLL PFD. During new value setting,
865 * the clock output is disabled to prevent glitch.
866 *
867 * param pfd Which PFD clock to enable.
868 * param pfdFrac The PFD FRAC value.
869 * note It is recommended that PFD settings are kept between 12-35.
870 */
871void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac)
872{
873 uint32_t pfdIndex = (uint32_t)pfd;
874 uint32_t pfd528;
875
876 pfd528 = CCM_ANALOG->PFD_528 &
877 ~(((uint32_t)((uint32_t)CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK | (uint32_t)CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)
878 << (8UL * pfdIndex)));
879
880 /* Disable the clock output first. */
881 CCM_ANALOG->PFD_528 = pfd528 | ((uint32_t)CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8UL * pfdIndex));
882
883 /* Set the new value and enable output. */
884 CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_FRAC(pfdFrac) << (8UL * pfdIndex));
885}
886
887/*!
888 * brief De-initialize the System PLL PFD.
889 *
890 * This function disables the System PLL PFD.
891 *
892 * param pfd Which PFD clock to disable.
893 */
894void CLOCK_DeinitSysPfd(clock_pfd_t pfd)
895{
896 CCM_ANALOG->PFD_528 |= (uint32_t)CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8UL * (uint32_t)pfd);
897}
898
899/*!
900 * brief Initialize the USB1 PLL PFD.
901 *
902 * This function initializes the USB1 PLL PFD. During new value setting,
903 * the clock output is disabled to prevent glitch.
904 *
905 * param pfd Which PFD clock to enable.
906 * param pfdFrac The PFD FRAC value.
907 * note It is recommended that PFD settings are kept between 12-35.
908 */
909void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac)
910{
911 uint32_t pfdIndex = (uint32_t)pfd;
912 uint32_t pfd480;
913
914 pfd480 = CCM_ANALOG->PFD_480 &
915 ~((uint32_t)((uint32_t)CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK | (uint32_t)CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)
916 << (8UL * pfdIndex));
917
918 /* Disable the clock output first. */
919 CCM_ANALOG->PFD_480 = pfd480 | ((uint32_t)CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8UL * pfdIndex));
920
921 /* Set the new value and enable output. */
922 CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_FRAC(pfdFrac) << (8UL * pfdIndex));
923}
924
925/*!
926 * brief De-initialize the USB1 PLL PFD.
927 *
928 * This function disables the USB1 PLL PFD.
929 *
930 * param pfd Which PFD clock to disable.
931 */
932void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd)
933{
934 CCM_ANALOG->PFD_480 |= (uint32_t)CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8UL * (uint32_t)pfd);
935}
936
937/*!
938 * brief Get current System PLL PFD output frequency.
939 *
940 * This function get current output frequency of specific System PLL PFD
941 *
942 * param pfd pfd name to get frequency.
943 * return The PFD output frequency in hertz.
944 */
945uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd)
946{
947 uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllSys);
948
949 switch (pfd)
950 {
951 case kCLOCK_Pfd0:
952 freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT);
953 break;
954
955 case kCLOCK_Pfd1:
956 freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT);
957 break;
958
959 case kCLOCK_Pfd2:
960 freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT);
961 break;
962
963 case kCLOCK_Pfd3:
964 freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT);
965 break;
966
967 default:
968 freq = 0U;
969 break;
970 }
971 freq *= 18U;
972
973 return freq;
974}
975
976/*!
977 * brief Get current USB1 PLL PFD output frequency.
978 *
979 * This function get current output frequency of specific USB1 PLL PFD
980 *
981 * param pfd pfd name to get frequency.
982 * return The PFD output frequency in hertz.
983 */
984uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd)
985{
986 uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1);
987
988 switch (pfd)
989 {
990 case kCLOCK_Pfd0:
991 freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT);
992 break;
993
994 case kCLOCK_Pfd1:
995 freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT);
996 break;
997
998 case kCLOCK_Pfd2:
999 freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT);
1000 break;
1001
1002 case kCLOCK_Pfd3:
1003 freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT);
1004 break;
1005
1006 default:
1007 freq = 0U;
1008 break;
1009 }
1010 freq *= 18U;
1011
1012 return freq;
1013}
1014
1015/*!
1016 * brief Set the clock source and the divider of the clock output1.
1017 *
1018 * param selection The clock source to be output, please refer to clock_output1_selection_t.
1019 * param divider The divider of the output clock signal, please refer to clock_output_divider_t.
1020 */
1021void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider)
1022{
1023 uint32_t tmp32;
1024
1025 tmp32 = CCM->CCOSR;
1026 if (selection == kCLOCK_DisableClockOutput1)
1027 {
1028 tmp32 &= ~CCM_CCOSR_CLKO1_EN_MASK;
1029 }
1030 else
1031 {
1032 tmp32 |= CCM_CCOSR_CLKO1_EN_MASK;
1033 tmp32 &= ~(CCM_CCOSR_CLKO1_SEL_MASK | CCM_CCOSR_CLKO1_DIV_MASK);
1034 tmp32 |= CCM_CCOSR_CLKO1_SEL(selection) | CCM_CCOSR_CLKO1_DIV(divider);
1035 }
1036 CCM->CCOSR = tmp32;
1037}
1038
1039/*!
1040 * brief Set the clock source and the divider of the clock output2.
1041 *
1042 * param selection The clock source to be output, please refer to clock_output2_selection_t.
1043 * param divider The divider of the output clock signal, please refer to clock_output_divider_t.
1044 */
1045void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider)
1046{
1047 uint32_t tmp32;
1048
1049 tmp32 = CCM->CCOSR;
1050 if (selection == kCLOCK_DisableClockOutput2)
1051 {
1052 tmp32 &= CCM_CCOSR_CLKO2_EN_MASK;
1053 }
1054 else
1055 {
1056 tmp32 |= CCM_CCOSR_CLKO2_EN_MASK;
1057 tmp32 &= ~(CCM_CCOSR_CLKO2_SEL_MASK | CCM_CCOSR_CLKO2_DIV_MASK);
1058 tmp32 |= CCM_CCOSR_CLKO2_SEL(selection) | CCM_CCOSR_CLKO2_DIV(divider);
1059 }
1060
1061 CCM->CCOSR = tmp32;
1062}
1063
1064/*!
1065 * brief Get the frequency of clock output1 clock signal.
1066 *
1067 * return The frequency of clock output1 clock signal.
1068 */
1069uint32_t CLOCK_GetClockOutCLKO1Freq(void)
1070{
1071 uint32_t freq = 0U;
1072 uint32_t tmp32;
1073
1074 tmp32 = CCM->CCOSR;
1075
1076 if ((tmp32 & CCM_CCOSR_CLKO1_EN_MASK) != 0UL)
1077 {
1078 switch ((tmp32 & CCM_CCOSR_CLKO1_SEL_MASK) >> CCM_CCOSR_CLKO1_SEL_SHIFT)
1079 {
1080 case (uint32_t)kCLOCK_OutputPllUsb1Sw:
1081 freq = CLOCK_GetPllUsb1SWFreq() / 2UL;
1082 break;
1083 case (uint32_t)kCLOCK_OutputPllSys:
1084 freq = CLOCK_GetPllFreq(kCLOCK_PllSys) / 2UL;
1085 break;
1086 case (uint32_t)kCLOCK_OutputPllENET:
1087 freq = CLOCK_GetPllFreq(kCLOCK_PllEnet500M) / 2UL;
1088 break;
1089 case (uint32_t)kCLOCK_OutputAhbClk:
1090 freq = CLOCK_GetAhbFreq();
1091 break;
1092 case (uint32_t)kCLOCK_OutputIpgClk:
1093 freq = CLOCK_GetIpgFreq();
1094 break;
1095 case (uint32_t)kCLOCK_OutputPerClk:
1096 freq = CLOCK_GetPerClkFreq();
1097 break;
1098 case (uint32_t)kCLOCK_OutputPll4MainClk:
1099 freq = CLOCK_GetPllFreq(kCLOCK_PllAudio);
1100 break;
1101 default:
1102 /* This branch should never be hit. */
1103 break;
1104 }
1105
1106 freq /= (((tmp32 & CCM_CCOSR_CLKO1_DIV_MASK) >> CCM_CCOSR_CLKO1_DIV_SHIFT) + 1U);
1107 }
1108 else
1109 {
1110 freq = 0UL;
1111 }
1112
1113 return freq;
1114}
1115
1116/*!
1117 * brief Get the frequency of clock output2 clock signal.
1118 *
1119 * return The frequency of clock output2 clock signal.
1120 */
1121uint32_t CLOCK_GetClockOutClkO2Freq(void)
1122{
1123 uint32_t freq = 0U;
1124 uint32_t tmp32;
1125
1126 tmp32 = CCM->CCOSR;
1127
1128 if ((tmp32 & CCM_CCOSR_CLKO2_EN_MASK) != 0UL)
1129 {
1130 switch ((tmp32 & CCM_CCOSR_CLKO2_SEL_MASK) >> CCM_CCOSR_CLKO2_SEL_SHIFT)
1131 {
1132 case (uint32_t)kCLOCK_OutputLpi2cClk:
1133 freq = CLOCK_GetClockRootFreq(kCLOCK_Lpi2cClkRoot);
1134 break;
1135 case (uint32_t)kCLOCK_OutputOscClk:
1136 freq = CLOCK_GetOscFreq();
1137 break;
1138 case (uint32_t)kCLOCK_OutputLpspiClk:
1139 freq = CLOCK_GetClockRootFreq(kCLOCK_LpspiClkRoot);
1140 break;
1141 case (uint32_t)kCLOCK_OutputSai1Clk:
1142 freq = CLOCK_GetClockRootFreq(kCLOCK_Sai1ClkRoot);
1143 break;
1144 case (uint32_t)kCLOCK_OutputSai2Clk:
1145 freq = CLOCK_GetClockRootFreq(kCLOCK_Sai2ClkRoot);
1146 break;
1147 case (uint32_t)kCLOCK_OutputSai3Clk:
1148 freq = CLOCK_GetClockRootFreq(kCLOCK_Sai3ClkRoot);
1149 break;
1150 case (uint32_t)kCLOCK_OutputTraceClk:
1151 freq = CLOCK_GetClockRootFreq(kCLOCK_TraceClkRoot);
1152 break;
1153 case (uint32_t)kCLOCK_OutputFlexspiClk:
1154 freq = CLOCK_GetClockRootFreq(kCLOCK_FlexspiClkRoot);
1155 break;
1156 case (uint32_t)kCLOCK_OutputUartClk:
1157 freq = CLOCK_GetClockRootFreq(kCLOCK_UartClkRoot);
1158 break;
1159 case (uint32_t)kCLOCK_OutputSpdif0Clk:
1160 freq = CLOCK_GetClockRootFreq(kCLOCK_SpdifClkRoot);
1161 break;
1162 default:
1163 /* This branch should never be hit. */
1164 break;
1165 }
1166
1167 freq /= (((tmp32 & CCM_CCOSR_CLKO2_DIV_MASK) >> CCM_CCOSR_CLKO2_DIV_SHIFT) + 1U);
1168 }
1169 else
1170 {
1171 freq = 0UL;
1172 }
1173
1174 return freq;
1175}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_clock.h
new file mode 100644
index 000000000..90de181f2
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_clock.h
@@ -0,0 +1,1431 @@
1/*
2 * Copyright 2018-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_common.h"
12
13/*! @addtogroup clock */
14/*! @{ */
15
16/*! @file */
17
18/*******************************************************************************
19 * Configurations
20 ******************************************************************************/
21
22/*! @brief Configure whether driver controls clock
23 *
24 * When set to 0, peripheral drivers will enable clock in initialize function
25 * and disable clock in de-initialize function. When set to 1, peripheral
26 * driver will not control the clock, application could control the clock out of
27 * the driver.
28 *
29 * @note All drivers share this feature switcher. If it is set to 1, application
30 * should handle clock enable and disable for all drivers.
31 */
32#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
33#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
34#endif
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*! @name Driver version */
41/*@{*/
42/*! @brief CLOCK driver version 2.4.0. */
43#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
44
45/* analog pll definition */
46#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
47#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
48#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
49
50/* Definition for delay API in clock driver, users can redefine it to the real application. */
51#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
52#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (500000000UL)
53#endif
54
55/*@}*/
56
57/*!
58 * @brief CCM registers offset.
59 */
60#define CCSR_OFFSET 0x0C
61#define CBCDR_OFFSET 0x14
62#define CBCMR_OFFSET 0x18
63#define CSCMR1_OFFSET 0x1C
64#define CSCMR2_OFFSET 0x20
65#define CSCDR1_OFFSET 0x24
66#define CDCDR_OFFSET 0x30
67#define CSCDR2_OFFSET 0x38
68#define CACRR_OFFSET 0x10
69#define CS1CDR_OFFSET 0x28
70#define CS2CDR_OFFSET 0x2C
71
72/*!
73 * @brief CCM Analog registers offset.
74 */
75#define PLL_SYS_OFFSET 0x30
76#define PLL_USB1_OFFSET 0x10
77#define PLL_AUDIO_OFFSET 0x70
78#define PLL_ENET_OFFSET 0xE0
79
80#define CCM_TUPLE(reg, shift, mask, busyShift) \
81 (int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
82#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + (((uint32_t)tuple) & 0xFFU))))
83#define CCM_TUPLE_SHIFT(tuple) ((((uint32_t)tuple) >> 8U) & 0x1FU)
84#define CCM_TUPLE_MASK(tuple) \
85 ((uint32_t)(((((uint32_t)tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))
86#define CCM_TUPLE_BUSY_SHIFT(tuple) ((((uint32_t)tuple) >> 26U) & 0x3FU)
87
88#define CCM_NO_BUSY_WAIT (0x20U)
89
90/*!
91 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
92 */
93#define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFU) << 16U) | (shift))
94#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)(tuple)) & 0x1FU)
95#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
96 (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))
97#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
98
99#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
100#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
101#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
102
103/*!
104 * @brief clock1PN frequency.
105 */
106#define CLKPN_FREQ 0U
107
108/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency.
109 *
110 * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the
111 * function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
112 * if XTAL is 24MHz,
113 * @code
114 * CLOCK_InitExternalClk(false);
115 * CLOCK_SetXtalFreq(240000000);
116 * @endcode
117 */
118extern volatile uint32_t g_xtalFreq;
119
120/*! @brief External RTC XTAL (32K OSC) clock frequency.
121 *
122 * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the
123 * function CLOCK_SetRtcXtalFreq to set the value in to clock driver.
124 */
125extern volatile uint32_t g_rtcXtalFreq;
126
127/* For compatible with other platforms */
128#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq
129#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq
130
131/*! @brief Clock ip name array for ADC. */
132#define ADC_CLOCKS \
133 { \
134 kCLOCK_IpInvalid, kCLOCK_Adc1 \
135 }
136
137/*! @brief Clock ip name array for AOI. */
138#define AOI_CLOCKS \
139 { \
140 kCLOCK_Aoi \
141 }
142
143/*! @brief Clock ip name array for BEE. */
144#define BEE_CLOCKS \
145 { \
146 kCLOCK_Bee \
147 }
148
149/*! @brief Clock ip name array for DCDC. */
150#define DCDC_CLOCKS \
151 { \
152 kCLOCK_Dcdc \
153 }
154
155/*! @brief Clock ip name array for DCP. */
156#define DCP_CLOCKS \
157 { \
158 kCLOCK_Dcp \
159 }
160
161/*! @brief Clock ip name array for DMAMUX_CLOCKS. */
162#define DMAMUX_CLOCKS \
163 { \
164 kCLOCK_Dma \
165 }
166
167/*! @brief Clock ip name array for DMA. */
168#define EDMA_CLOCKS \
169 { \
170 kCLOCK_Dma \
171 }
172
173/*! @brief Clock ip name array for ENC. */
174#define ENC_CLOCKS \
175 { \
176 kCLOCK_IpInvalid, kCLOCK_Enc1 \
177 }
178
179/*! @brief Clock ip name array for EWM. */
180#define EWM_CLOCKS \
181 { \
182 kCLOCK_Ewm0 \
183 }
184
185/*! @brief Clock ip name array for FLEXIO. */
186#define FLEXIO_CLOCKS \
187 { \
188 kCLOCK_IpInvalid, kCLOCK_Flexio1 \
189 }
190
191/*! @brief Clock ip name array for FLEXRAM. */
192#define FLEXRAM_CLOCKS \
193 { \
194 kCLOCK_FlexRam \
195 }
196
197/*! @brief Clock ip name array for FLEXSPI. */
198#define FLEXSPI_CLOCKS \
199 { \
200 kCLOCK_FlexSpi \
201 }
202
203/*! @brief Clock ip name array for GPIO. */
204#define GPIO_CLOCKS \
205 { \
206 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_IpInvalid, kCLOCK_Gpio5 \
207 }
208
209/*! @brief Clock ip name array for GPT. */
210#define GPT_CLOCKS \
211 { \
212 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
213 }
214
215/*! @brief Clock ip name array for KPP. */
216#define KPP_CLOCKS \
217 { \
218 kCLOCK_Kpp \
219 }
220
221/*! @brief Clock ip name array for LPI2C. */
222#define LPI2C_CLOCKS \
223 { \
224 kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2 \
225 }
226
227/*! @brief Clock ip name array for LPSPI. */
228#define LPSPI_CLOCKS \
229 { \
230 kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2 \
231 }
232
233/*! @brief Clock ip name array for LPUART. */
234#define LPUART_CLOCKS \
235 { \
236 kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4 \
237 }
238
239/*! @brief Clock ip name array for OCRAM EXSC. */
240#define OCRAM_EXSC_CLOCKS \
241 { \
242 kCLOCK_OcramExsc \
243 }
244
245/*! @brief Clock ip name array for PIT. */
246#define PIT_CLOCKS \
247 { \
248 kCLOCK_Pit \
249 }
250
251/*! @brief Clock ip name array for PWM. */
252#define PWM_CLOCKS \
253 { \
254 {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
255 { \
256 kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1 \
257 } \
258 }
259
260/*! @brief Clock ip name array for RTWDOG. */
261#define RTWDOG_CLOCKS \
262 { \
263 kCLOCK_Wdog3 \
264 }
265
266/*! @brief Clock ip name array for SAI. */
267#define SAI_CLOCKS \
268 { \
269 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \
270 }
271
272/*! @brief Clock ip name array for QTIMER. */
273#define TMR_CLOCKS \
274 { \
275 kCLOCK_IpInvalid, kCLOCK_Timer1 \
276 }
277
278/*! @brief Clock ip name array for TRNG. */
279#define TRNG_CLOCKS \
280 { \
281 kCLOCK_Trng \
282 }
283
284/*! @brief Clock ip name array for WDOG. */
285#define WDOG_CLOCKS \
286 { \
287 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \
288 }
289
290/*! @brief Clock ip name array for SPDIF. */
291#define SPDIF_CLOCKS \
292 { \
293 kCLOCK_Spdif \
294 }
295
296/*! @brief Clock ip name array for XBARA. */
297#define XBARA_CLOCKS \
298 { \
299 kCLOCK_Xbar1 \
300 }
301
302/*! @brief Clock ip name array for XBARB. */
303#define XBARB_CLOCKS \
304 { \
305 kCLOCK_Xbar2 \
306 }
307
308#define CLOCK_SOURCE_NONE (0xFFU)
309
310#define CLOCK_ROOT_SOUCE \
311 { \
312 {kCLOCK_SemcClk, kCLOCK_Usb1SwClk, kCLOCK_SysPllPfd2Clk, kCLOCK_Usb1PllPfd0Clk}, /*!< FLEXSPI clock root */ \
313 {kCLOCK_Usb1PllPfd1Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_SysPllClk, \
314 kCLOCK_SysPllPfd2Clk}, /*!< LPSPI clock root. */ \
315 {kCLOCK_SysPllClk, kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, \
316 kCLOCK_SysPllPfd1Clk}, /*!< Trace clock root. */ \
317 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, kCLOCK_AudioPllClk, kCLOCK_NoneName}, /*!< SAI1 clock root. */ \
318 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, kCLOCK_AudioPllClk, kCLOCK_NoneName}, /*!< SAI2 clock root. */ \
319 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, kCLOCK_AudioPllClk, kCLOCK_NoneName}, /*!< SAI3 clock root. */ \
320 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_NoneName, kCLOCK_NoneName}, /*!< LPI2C clock root. */ \
321 {kCLOCK_Usb1Sw80MClk, kCLOCK_OscClk, kCLOCK_NoneName, kCLOCK_NoneName}, /*!< UART clock root. */ \
322 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, kCLOCK_Usb1SwClk}, /*!< SPDIF clock root. */ \
323 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, \
324 kCLOCK_Usb1SwClk}, /*!< FLEXIO1 clock root. */ \
325 }
326
327#define CLOCK_ROOT_MUX_TUPLE \
328 { \
329 kCLOCK_FlexspiMux, kCLOCK_LpspiMux, kCLOCK_TraceMux, kCLOCK_Sai1Mux, kCLOCK_Sai2Mux, kCLOCK_Sai3Mux, \
330 kCLOCK_Lpi2cMux, kCLOCK_UartMux, kCLOCK_SpdifMux, kCLOCK_Flexio1Mux, \
331 }
332
333#define CLOCK_ROOT_NONE_PRE_DIV 0UL
334
335#define CLOCK_ROOT_DIV_TUPLE \
336 { \
337 {kCLOCK_NonePreDiv, kCLOCK_FlexspiDiv}, /*!< FLEXSPI clock root */ \
338 {kCLOCK_NonePreDiv, kCLOCK_LpspiDiv}, /*!< LPSPI clock root. */ \
339 {kCLOCK_NonePreDiv, kCLOCK_TraceDiv}, /*!< Trace clock root. */ \
340 {kCLOCK_Sai1PreDiv, kCLOCK_Sai1Div}, /*!< SAI1 clock root. */ \
341 {kCLOCK_Sai2PreDiv, kCLOCK_Sai2Div}, /*!< SAI2 clock root. */ \
342 {kCLOCK_Sai3PreDiv, kCLOCK_Sai3Div}, /*!< SAI3 clock root. */ \
343 {kCLOCK_NonePreDiv, kCLOCK_Lpi2cDiv}, /*!< LPI2C clock root. */ \
344 {kCLOCK_NonePreDiv, kCLOCK_UartDiv}, /*!< UART clock root. */ \
345 {kCLOCK_Spdif0PreDiv, kCLOCK_Spdif0Div}, /*!< SPDIF clock root. */ \
346 {kCLOCK_Flexio1PreDiv, kCLOCK_Flexio1Div}, /*!< FLEXIO1 clock root. */ \
347 }
348
349/*! @brief Clock name used to get clock frequency. */
350typedef enum _clock_name
351{
352 kCLOCK_CpuClk = 0x0U, /*!< CPU clock */
353 kCLOCK_AhbClk = 0x1U, /*!< AHB clock */
354 kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */
355 kCLOCK_IpgClk = 0x3U, /*!< IPG clock */
356 kCLOCK_PerClk = 0x4U, /*!< PER clock */
357
358 kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */
359 kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */
360
361 kCLOCK_Usb1PllClk = 0x7U, /*!< USB1PLLCLK. */
362 kCLOCK_Usb1PllPfd0Clk = 0x8U, /*!< USB1PLLPDF0CLK. */
363 kCLOCK_Usb1PllPfd1Clk = 0x9U, /*!< USB1PLLPFD1CLK. */
364 kCLOCK_Usb1PllPfd2Clk = 0xAU, /*!< USB1PLLPFD2CLK. */
365 kCLOCK_Usb1PllPfd3Clk = 0xBU, /*!< USB1PLLPFD3CLK. */
366 kCLOCK_Usb1SwClk = 0x15U, /*!< USB1PLLSWCLK */
367 kCLOCK_Usb1Sw60MClk = 0x16U, /*!< USB1PLLSw60MCLK */
368 kCLOCK_Usb1Sw80MClk = 0x1BU, /*!< USB1PLLSw80MCLK */
369
370 kCLOCK_SysPllClk = 0xCU, /*!< SYSPLLCLK. */
371 kCLOCK_SysPllPfd0Clk = 0xDU, /*!< SYSPLLPDF0CLK. */
372 kCLOCK_SysPllPfd1Clk = 0xEU, /*!< SYSPLLPFD1CLK. */
373 kCLOCK_SysPllPfd2Clk = 0xFU, /*!< SYSPLLPFD2CLK. */
374 kCLOCK_SysPllPfd3Clk = 0x10U, /*!< SYSPLLPFD3CLK. */
375
376 kCLOCK_EnetPllClk = 0x11U, /*!< Enet PLLCLK ref_enetpll. */
377 kCLOCK_EnetPll25MClk = 0x12U, /*!< Enet PLLCLK ref_enetpll25M. */
378 kCLOCK_EnetPll500MClk = 0x13U, /*!< Enet PLLCLK ref_enetpll500M. */
379
380 kCLOCK_AudioPllClk = 0x14U, /*!< Audio PLLCLK. */
381
382 kCLOCK_NoneName = CLOCK_SOURCE_NONE, /*!< None Clock Name. */
383} clock_name_t;
384
385#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */
386#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */
387
388/*!
389 * @brief CCM CCGR gate control for each module independently.
390 */
391typedef enum _clock_ip_name
392{
393 kCLOCK_IpInvalid = -1,
394
395 /* CCM CCGR0 */
396 kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */
397 kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */
398 kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2, Reserved */
399 kCLOCK_Sim_m_clk_r = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */
400 kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */
401 kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */
402 kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */
403 kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */
404 kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */
405 kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */
406 kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */
407
408 /* CCM CCGR1 */
409 kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */
410 kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */
411 kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */
412 /*!< CCGR1, CG7, Reserved */
413 kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */
414 kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */
415 kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */
416 kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */
417 kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */
418 kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */
419 kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */
420
421 /* CCM CCGR2 */
422 kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */
423 /*!< CCGR2, CG1, Reserved */
424 kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */
425 kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */
426 kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */
427 kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */
428 /*!< CCGR2, CG7, Reserved */
429 /*!< CCGR2, CG8, Reserved */
430 /*!< CCGR2, CG9, Reserved */
431 /*!< CCGR2, CG10, Reserved */
432 kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */
433 kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */
434 kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */
435 /*!< CCGR2, CG14, Reserved */
436 /*!< CCGR2, CG15, Reserved */
437
438 /* CCM CCGR3 */
439 /*!< CCGR3, CG0, Reserved */
440 kCLOCK_Aoi = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */
441 /*!< CCGR3, CG5, Reserved */
442 /*!< CCGR3, CG6, Reserved */
443 kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */
444 kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */
445 kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */
446 /*!< CCGR3, CG14, Reserved */
447 kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */
448
449 /* CCM CCGR4 */
450 kCLOCK_Sim_m7_clk_r = (4U << 8U) | CCM_CCGR4_CG0_SHIFT, /*!< CCGR4, CG0 */
451 kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */
452 kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */
453 kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */
454 kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */
455 kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */
456 kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */
457 kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */
458 /*!< CCGR4, CG10, Reserved */
459 /*!< CCGR4, CG11, Reserved */
460 kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */
461 /*!< CCGR4, CG14, Reserved */
462 /*!< CCGR4, CG15, Reserved */
463
464 /* CCM CCGR5 */
465 kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */
466 kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */
467 kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */
468 kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */
469 kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */
470 kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */
471 kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */
472 kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */
473 /*!< CCGR5, CG8, Reserved */
474 kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */
475 kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */
476 kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */
477 kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */
478 kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */
479 kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */
480
481 /* CCM CCGR6 */
482 kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */
483 kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */
484 kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */
485 kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */
486 kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */
487 kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */
488 kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */
489 kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */
490 /*!< CCGR6, CG15, Reserved */
491
492} clock_ip_name_t;
493
494/*! @brief OSC 24M sorce select */
495typedef enum _clock_osc
496{
497 kCLOCK_RcOsc = 0U, /*!< On chip OSC. */
498 kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */
499} clock_osc_t;
500
501/*! @brief Clock gate value */
502typedef enum _clock_gate_value
503{
504 kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */
505 kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */
506 kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */
507} clock_gate_value_t;
508
509/*! @brief System clock mode */
510typedef enum _clock_mode_t
511{
512 kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */
513 kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */
514 kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */
515} clock_mode_t;
516
517/*!
518 * @brief MUX control names for clock mux setting.
519 *
520 * These constants define the mux control names for clock mux setting.\n
521 * - 0:7: REG offset to CCM_BASE in bytes.
522 * - 8:15: Root clock setting bit field shift.
523 * - 16:31: Root clock setting bit field width.
524 */
525typedef enum _clock_mux
526{
527 kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET,
528 CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT,
529 CCM_CCSR_PLL3_SW_CLK_SEL_MASK,
530 CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */
531
532 kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
533 CCM_CBCDR_PERIPH_CLK_SEL_SHIFT,
534 CCM_CBCDR_PERIPH_CLK_SEL_MASK,
535 CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */
536 kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET,
537 CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT,
538 CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK,
539 CCM_NO_BUSY_WAIT), /*!< semc mux name */
540 kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET,
541 CCM_CBCDR_SEMC_CLK_SEL_SHIFT,
542 CCM_CBCDR_SEMC_CLK_SEL_MASK,
543 CCM_NO_BUSY_WAIT), /*!< semc mux name */
544
545 kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
546 CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT,
547 CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK,
548 CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */
549 kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET,
550 CCM_CBCMR_TRACE_CLK_SEL_SHIFT,
551 CCM_CBCMR_TRACE_CLK_SEL_MASK,
552 CCM_NO_BUSY_WAIT), /*!< trace mux name */
553 kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
554 CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT,
555 CCM_CBCMR_PERIPH_CLK2_SEL_MASK,
556 CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */
557 kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET,
558 CCM_CBCMR_LPSPI_CLK_SEL_SHIFT,
559 CCM_CBCMR_LPSPI_CLK_SEL_MASK,
560 CCM_NO_BUSY_WAIT), /*!< lpspi mux name */
561
562 kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
563 CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT,
564 CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK,
565 CCM_NO_BUSY_WAIT), /*!< flexspi mux name */
566 kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1_OFFSET,
567 CCM_CSCMR1_SAI3_CLK_SEL_SHIFT,
568 CCM_CSCMR1_SAI3_CLK_SEL_MASK,
569 CCM_NO_BUSY_WAIT), /*!< sai3 mux name */
570 kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1_OFFSET,
571 CCM_CSCMR1_SAI2_CLK_SEL_SHIFT,
572 CCM_CSCMR1_SAI2_CLK_SEL_MASK,
573 CCM_NO_BUSY_WAIT), /*!< sai2 mux name */
574 kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1_OFFSET,
575 CCM_CSCMR1_SAI1_CLK_SEL_SHIFT,
576 CCM_CSCMR1_SAI1_CLK_SEL_MASK,
577 CCM_NO_BUSY_WAIT), /*!< sai1 mux name */
578 kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET,
579 CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT,
580 CCM_CSCMR1_PERCLK_CLK_SEL_MASK,
581 CCM_NO_BUSY_WAIT), /*!< perclk mux name */
582
583 kCLOCK_Flexio1Mux = CCM_TUPLE(CSCMR2_OFFSET,
584 CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT,
585 CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK,
586 CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */
587
588 kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET,
589 CCM_CSCDR1_UART_CLK_SEL_SHIFT,
590 CCM_CSCDR1_UART_CLK_SEL_MASK,
591 CCM_NO_BUSY_WAIT), /*!< uart mux name */
592
593 kCLOCK_SpdifMux = CCM_TUPLE(CDCDR_OFFSET,
594 CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT,
595 CCM_CDCDR_SPDIF0_CLK_SEL_MASK,
596 CCM_NO_BUSY_WAIT), /*!< spdif mux name */
597
598 kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2_OFFSET,
599 CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT,
600 CCM_CSCDR2_LPI2C_CLK_SEL_MASK,
601 CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */
602} clock_mux_t;
603
604/*!
605 * @brief DIV control names for clock div setting.
606 *
607 * These constants define div control names for clock div setting.\n
608 * - 0:7: REG offset to CCM_BASE in bytes.
609 * - 8:15: Root clock setting bit field shift.
610 * - 16:31: Root clock setting bit field width.
611 */
612typedef enum _clock_div
613{
614 kCLOCK_ArmDiv = CCM_TUPLE(CACRR_OFFSET,
615 CCM_CACRR_ARM_PODF_SHIFT,
616 CCM_CACRR_ARM_PODF_MASK,
617 CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */
618
619 kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET,
620 CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT,
621 CCM_CBCDR_PERIPH_CLK2_PODF_MASK,
622 CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */
623 kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET,
624 CCM_CBCDR_SEMC_PODF_SHIFT,
625 CCM_CBCDR_SEMC_PODF_MASK,
626 CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */
627 kCLOCK_AhbDiv = CCM_TUPLE(CBCDR_OFFSET,
628 CCM_CBCDR_AHB_PODF_SHIFT,
629 CCM_CBCDR_AHB_PODF_MASK,
630 CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */
631 kCLOCK_IpgDiv = CCM_TUPLE(
632 CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */
633
634 kCLOCK_LpspiDiv = CCM_TUPLE(
635 CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */
636
637 kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET,
638 CCM_CSCMR1_FLEXSPI_PODF_SHIFT,
639 CCM_CSCMR1_FLEXSPI_PODF_MASK,
640 CCM_NO_BUSY_WAIT), /*!< flexspi div name */
641 kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1_OFFSET,
642 CCM_CSCMR1_PERCLK_PODF_SHIFT,
643 CCM_CSCMR1_PERCLK_PODF_MASK,
644 CCM_NO_BUSY_WAIT), /*!< perclk div name */
645
646 kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1_OFFSET,
647 CCM_CSCDR1_TRACE_PODF_SHIFT,
648 CCM_CSCDR1_TRACE_PODF_MASK,
649 CCM_NO_BUSY_WAIT), /*!< trace div name */
650 kCLOCK_UartDiv = CCM_TUPLE(CSCDR1_OFFSET,
651 CCM_CSCDR1_UART_CLK_PODF_SHIFT,
652 CCM_CSCDR1_UART_CLK_PODF_MASK,
653 CCM_NO_BUSY_WAIT), /*!< uart div name */
654
655 kCLOCK_Flexio1Div = CCM_TUPLE(CS1CDR_OFFSET,
656 CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT,
657 CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK,
658 CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
659 kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
660 CCM_CS1CDR_SAI3_CLK_PRED_SHIFT,
661 CCM_CS1CDR_SAI3_CLK_PRED_MASK,
662 CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
663 kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR_OFFSET,
664 CCM_CS1CDR_SAI3_CLK_PODF_SHIFT,
665 CCM_CS1CDR_SAI3_CLK_PODF_MASK,
666 CCM_NO_BUSY_WAIT), /*!< sai3 div name */
667 kCLOCK_Flexio1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
668 CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT,
669 CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK,
670 CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
671 kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
672 CCM_CS1CDR_SAI1_CLK_PRED_SHIFT,
673 CCM_CS1CDR_SAI1_CLK_PRED_MASK,
674 CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */
675 kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR_OFFSET,
676 CCM_CS1CDR_SAI1_CLK_PODF_SHIFT,
677 CCM_CS1CDR_SAI1_CLK_PODF_MASK,
678 CCM_NO_BUSY_WAIT), /*!< sai1 div name */
679
680 kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET,
681 CCM_CS2CDR_SAI2_CLK_PRED_SHIFT,
682 CCM_CS2CDR_SAI2_CLK_PRED_MASK,
683 CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */
684 kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR_OFFSET,
685 CCM_CS2CDR_SAI2_CLK_PODF_SHIFT,
686 CCM_CS2CDR_SAI2_CLK_PODF_MASK,
687 CCM_NO_BUSY_WAIT), /*!< sai2 div name */
688
689 kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET,
690 CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT,
691 CCM_CDCDR_SPDIF0_CLK_PRED_MASK,
692 CCM_NO_BUSY_WAIT), /*!< spdif pre div name */
693 kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET,
694 CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT,
695 CCM_CDCDR_SPDIF0_CLK_PODF_MASK,
696 CCM_NO_BUSY_WAIT), /*!< spdif div name */
697
698 kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET,
699 CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT,
700 CCM_CSCDR2_LPI2C_CLK_PODF_MASK,
701 CCM_NO_BUSY_WAIT), /*!< lpi2c div name */
702 kCLOCK_NonePreDiv = CLOCK_ROOT_NONE_PRE_DIV, /*!< None Pre div. */
703} clock_div_t;
704
705/*! @brief USB clock source definition. */
706typedef enum _clock_usb_src
707{
708 kCLOCK_Usb480M = 0, /*!< Use 480M. */
709 kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
710 care the clock source. */
711} clock_usb_src_t;
712
713/*! @brief Source of the USB HS PHY. */
714typedef enum _clock_usb_phy_src
715{
716 kCLOCK_Usbphy480M = 0, /*!< Use 480M. */
717} clock_usb_phy_src_t;
718
719/*!@brief PLL clock source, bypass cloco source also */
720enum _clock_pll_clk_src
721{
722 kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */
723 kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */
724};
725
726/*! @brief PLL configuration for USB */
727typedef struct _clock_usb_pll_config
728{
729 uint8_t loopDivider; /*!< PLL loop divider.
730 0 - Fout=Fref*20;
731 1 - Fout=Fref*22 */
732 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
733
734} clock_usb_pll_config_t;
735
736/*! @brief PLL configuration for System */
737typedef struct _clock_sys_pll_config
738{
739 uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M).
740 0 - Fout=Fref*20;
741 1 - Fout=Fref*22 */
742 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
743 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
744 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
745 uint16_t ss_stop; /*!< Stop value to get frequency change. */
746 uint8_t ss_enable; /*!< Enable spread spectrum modulation */
747 uint16_t ss_step; /*!< Step value to get frequency change step. */
748
749} clock_sys_pll_config_t;
750
751/*! @brief PLL configuration for AUDIO and VIDEO */
752typedef struct _clock_audio_pll_config
753{
754 uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
755 uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */
756 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
757 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
758 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
759} clock_audio_pll_config_t;
760
761/*! @brief PLL configuration for ENET */
762typedef struct _clock_enet_pll_config
763{
764 bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */
765
766 bool enableClkOutput500M; /*!< Power on and enable PLL clock output for ENET (ref_enetpll500M). */
767
768 bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */
769 uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock.
770 b00 25MHz
771 b01 50MHz
772 b10 100MHz (not 50% duty cycle)
773 b11 125MHz */
774 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
775
776} clock_enet_pll_config_t;
777
778/*! @brief PLL name */
779typedef enum _clock_pll
780{
781 kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */
782 kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */
783 kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */
784 kCLOCK_PllEnet500M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT), /*!< PLL ENET */
785} clock_pll_t;
786
787/*! @brief PLL PFD name */
788typedef enum _clock_pfd
789{
790 kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */
791 kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */
792 kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */
793 kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
794} clock_pfd_t;
795
796/*!
797 * @brief The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on.
798 */
799typedef enum _clock_output1_selection
800{
801 kCLOCK_OutputPllUsb1Sw = 0U, /*!< Selects USB1 PLL SW clock(Divided by 2) output. */
802 kCLOCK_OutputPllSys = 1U, /*!< Selects SYS PLL clock(Divided by 2) output. */
803 kCLOCK_OutputPllENET = 2U, /*!< Selects ENET PLL clock(Divided by 2) output. */
804 kCLOCK_OutputAhbClk = 0xBU, /*!< Selects AHB clock root output. */
805 kCLOCK_OutputIpgClk = 0xCU, /*!< Selects IPG clock root output. */
806 kCLOCK_OutputPerClk = 0xDU, /*!< Selects PERCLK clock root output. */
807 kCLOCK_OutputPll4MainClk = 0xFU, /*!< Selects PLL4 main clock output. */
808 kCLOCK_DisableClockOutput1 = 0x10U, /*!< Disables CLKO1. */
809} clock_output1_selection_t;
810
811/*!
812 * @brief The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on.
813 *
814 */
815typedef enum _clock_output2_selection
816{
817 kCLOCK_OutputLpi2cClk = 6U, /*!< Selects LPI2C clock root output. */
818 kCLOCK_OutputOscClk = 0xEU, /*!< Selects OSC output. */
819 kCLOCK_OutputLpspiClk = 0x10U, /*!< Selects LPSPI clock root output. */
820 kCLOCK_OutputSai1Clk = 0x12U, /*!< Selects SAI1 clock root output. */
821 kCLOCK_OutputSai2Clk = 0x13U, /*!< Selects SAI2 clock root output. */
822 kCLOCK_OutputSai3Clk = 0x14U, /*!< Selects SAI3 clock root output. */
823 kCLOCK_OutputTraceClk = 0x16U, /*!< Selects Trace clock root output. */
824 kCLOCK_OutputFlexspiClk = 0x1BU, /*!< Selects FLEXSPI clock root output. */
825 kCLOCK_OutputUartClk = 0x1CU, /*!< Selects UART clock root output. */
826 kCLOCK_OutputSpdif0Clk = 0x1DU, /*!< Selects SPDIF0 clock root output. */
827 kCLOCK_DisableClockOutput2 = 0x1FU, /*!< Disables CLKO2. */
828} clock_output2_selection_t;
829
830/*!
831 * @brief The enumerator of clock output's divider.
832 */
833typedef enum _clock_output_divider
834{
835 kCLOCK_DivideBy1 = 0U, /*!< Output clock divided by 1. */
836 kCLOCK_DivideBy2, /*!< Output clock divided by 2. */
837 kCLOCK_DivideBy3, /*!< Output clock divided by 3. */
838 kCLOCK_DivideBy4, /*!< Output clock divided by 4. */
839 kCLOCK_DivideBy5, /*!< Output clock divided by 5. */
840 kCLOCK_DivideBy6, /*!< Output clock divided by 6. */
841 kCLOCK_DivideBy7, /*!< Output clock divided by 7. */
842 kCLOCK_DivideBy8, /*!< Output clock divided by 8. */
843} clock_output_divider_t;
844
845/*!
846 * @brief The enumerator of clock root.
847 */
848typedef enum _clock_root
849{
850 kCLOCK_FlexspiClkRoot = 0U, /*!< FLEXSPI clock root. */
851 kCLOCK_LpspiClkRoot, /*!< LPSPI clock root. */
852 kCLOCK_TraceClkRoot, /*!< Trace clock root. */
853 kCLOCK_Sai1ClkRoot, /*!< SAI1 clock root. */
854 kCLOCK_Sai2ClkRoot, /*!< SAI2 clock root. */
855 kCLOCK_Sai3ClkRoot, /*!< SAI3 clock root. */
856 kCLOCK_Lpi2cClkRoot, /*!< LPI2C clock root. */
857 kCLOCK_UartClkRoot, /*!< UART clock root. */
858 kCLOCK_SpdifClkRoot, /*!< SPDIF clock root. */
859 kCLOCK_Flexio1ClkRoot, /*!< FLEXIO1 clock root. */
860} clock_root_t;
861
862/*******************************************************************************
863 * API
864 ******************************************************************************/
865
866#if defined(__cplusplus)
867extern "C" {
868#endif /* __cplusplus */
869
870/*!
871 * @brief Set CCM MUX node to certain value.
872 *
873 * @param mux Which mux node to set, see \ref clock_mux_t.
874 * @param value Clock mux value to set, different mux has different value range.
875 */
876static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
877{
878 uint32_t busyShift;
879
880 busyShift = CCM_TUPLE_BUSY_SHIFT(mux);
881 CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) |
882 (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux));
883
884 assert(busyShift <= CCM_NO_BUSY_WAIT);
885
886 /* Clock switch need Handshake? */
887 if (CCM_NO_BUSY_WAIT != busyShift)
888 {
889 /* Wait until CCM internal handshake finish. */
890 while ((CCM->CDHIPR & (1UL << busyShift)) != 0UL)
891 {
892 }
893 }
894}
895
896/*!
897 * @brief Get CCM MUX value.
898 *
899 * @param mux Which mux node to get, see \ref clock_mux_t.
900 * @return Clock mux value.
901 */
902static inline uint32_t CLOCK_GetMux(clock_mux_t mux)
903{
904 return (CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux)) >> CCM_TUPLE_SHIFT(mux);
905}
906
907/*!
908 * @brief Set CCM DIV node to certain value.
909 *
910 * @param divider Which div node to set, see \ref clock_div_t.
911 * @param value Clock div value to set, different divider has different value range.
912 */
913static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
914{
915 uint32_t busyShift;
916
917 busyShift = CCM_TUPLE_BUSY_SHIFT((uint32_t)divider);
918 CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) |
919 (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider));
920
921 assert(busyShift <= CCM_NO_BUSY_WAIT);
922
923 /* Clock switch need Handshake? */
924 if (CCM_NO_BUSY_WAIT != busyShift)
925 {
926 /* Wait until CCM internal handshake finish. */
927 while ((CCM->CDHIPR & (1UL << busyShift)) != 0UL)
928 {
929 }
930 }
931}
932
933/*!
934 * @brief Get CCM DIV node value.
935 *
936 * @param divider Which div node to get, see \ref clock_div_t.
937 */
938static inline uint32_t CLOCK_GetDiv(clock_div_t divider)
939{
940 return ((CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider));
941}
942
943/*!
944 * @brief Control the clock gate for specific IP.
945 *
946 * @param name Which clock to enable, see \ref clock_ip_name_t.
947 * @param value Clock gate value to set, see \ref clock_gate_value_t.
948 */
949static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value)
950{
951 uint32_t index = ((uint32_t)name) >> 8U;
952 uint32_t shift = ((uint32_t)name) & 0x1FU;
953 volatile uint32_t *reg;
954
955 assert(index <= 6UL);
956
957 reg = (volatile uint32_t *)((uint32_t)((volatile uint32_t *)&CCM->CCGR0) + sizeof(volatile uint32_t *) * index);
958 *reg = ((*reg) & ~(3UL << shift)) | (((uint32_t)value) << shift);
959}
960
961/*!
962 * @brief Enable the clock for specific IP.
963 *
964 * @param name Which clock to enable, see \ref clock_ip_name_t.
965 */
966static inline void CLOCK_EnableClock(clock_ip_name_t name)
967{
968 CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait);
969}
970
971/*!
972 * @brief Disable the clock for specific IP.
973 *
974 * @param name Which clock to disable, see \ref clock_ip_name_t.
975 */
976static inline void CLOCK_DisableClock(clock_ip_name_t name)
977{
978 CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded);
979}
980
981/*!
982 * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal.
983 *
984 * @param mode Which mode to enter, see \ref clock_mode_t.
985 */
986static inline void CLOCK_SetMode(clock_mode_t mode)
987{
988 CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode);
989}
990
991/*!
992 * @brief Gets the OSC clock frequency.
993 *
994 * This function will return the external XTAL OSC frequency if it is selected as the source of OSC,
995 * otherwise internal 24MHz RC OSC frequency will be returned.
996 *
997 * @return Clock frequency; If the clock is invalid, returns 0.
998 */
999static inline uint32_t CLOCK_GetOscFreq(void)
1000{
1001 return ((XTALOSC24M->LOWPWR_CTRL & (uint32_t)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_xtalFreq;
1002}
1003
1004/*!
1005 * @brief Gets the AHB clock frequency.
1006 *
1007 * @return The AHB clock frequency value in hertz.
1008 */
1009uint32_t CLOCK_GetAhbFreq(void);
1010
1011/*!
1012 * @brief Gets the SEMC clock frequency.
1013 *
1014 * @return The SEMC clock frequency value in hertz.
1015 */
1016uint32_t CLOCK_GetSemcFreq(void);
1017
1018/*!
1019 * @brief Gets the IPG clock frequency.
1020 *
1021 * @return The IPG clock frequency value in hertz.
1022 */
1023uint32_t CLOCK_GetIpgFreq(void);
1024
1025/*!
1026 * @brief Gets the PER clock frequency.
1027 *
1028 * @return The PER clock frequency value in hertz.
1029 */
1030uint32_t CLOCK_GetPerClkFreq(void);
1031
1032/*!
1033 * @brief Gets the clock frequency for a specific clock name.
1034 *
1035 * This function checks the current clock configurations and then calculates
1036 * the clock frequency for a specific clock name defined in clock_name_t.
1037 *
1038 * @param name Clock names defined in clock_name_t
1039 * @return Clock frequency value in hertz
1040 */
1041uint32_t CLOCK_GetFreq(clock_name_t name);
1042
1043/*!
1044 * @brief Get the CCM CPU/core/system frequency.
1045 *
1046 * @return Clock frequency; If the clock is invalid, returns 0.
1047 */
1048static inline uint32_t CLOCK_GetCpuClkFreq(void)
1049{
1050 return CLOCK_GetFreq(kCLOCK_CpuClk);
1051}
1052
1053/*!
1054 * @brief Gets the frequency of selected clock root.
1055 *
1056 * @param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t.
1057 * @return The frequency of selected clock root.
1058 */
1059uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot);
1060
1061/*!
1062 * @name OSC operations
1063 * @{
1064 */
1065
1066/*!
1067 * @brief Initialize the external 24MHz clock.
1068 *
1069 * This function supports two modes:
1070 * 1. Use external crystal oscillator.
1071 * 2. Bypass the external crystal oscillator, using input source clock directly.
1072 *
1073 * After this function, please call CLOCK_SetXtal0Freq to inform clock driver
1074 * the external clock frequency.
1075 *
1076 * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator.
1077 * @note This device does not support bypass external crystal oscillator, so
1078 * the input parameter should always be false.
1079 */
1080void CLOCK_InitExternalClk(bool bypassXtalOsc);
1081
1082/*!
1083 * @brief Deinitialize the external 24MHz clock.
1084 *
1085 * This function disables the external 24MHz clock.
1086 *
1087 * After this function, please call CLOCK_SetXtal0Freq to set external clock
1088 * frequency to 0.
1089 */
1090void CLOCK_DeinitExternalClk(void);
1091
1092/*!
1093 * @brief Switch the OSC.
1094 *
1095 * This function switches the OSC source for SoC.
1096 *
1097 * @param osc OSC source to switch to.
1098 */
1099void CLOCK_SwitchOsc(clock_osc_t osc);
1100
1101/*!
1102 * @brief Gets the RTC clock frequency.
1103 *
1104 * @return Clock frequency; If the clock is invalid, returns 0.
1105 */
1106static inline uint32_t CLOCK_GetRtcFreq(void)
1107{
1108 return 32768U;
1109}
1110
1111/*!
1112 * @brief Set the XTAL (24M OSC) frequency based on board setting.
1113 *
1114 * @param freq The XTAL input clock frequency in Hz.
1115 */
1116static inline void CLOCK_SetXtalFreq(uint32_t freq)
1117{
1118 g_xtalFreq = freq;
1119}
1120
1121/*!
1122 * @brief Set the RTC XTAL (32K OSC) frequency based on board setting.
1123 *
1124 * @param freq The RTC XTAL input clock frequency in Hz.
1125 */
1126static inline void CLOCK_SetRtcXtalFreq(uint32_t freq)
1127{
1128 g_rtcXtalFreq = freq;
1129}
1130
1131/*!
1132 * @brief Initialize the RC oscillator 24MHz clock.
1133 */
1134void CLOCK_InitRcOsc24M(void);
1135
1136/*!
1137 * @brief Power down the RCOSC 24M clock.
1138 */
1139void CLOCK_DeinitRcOsc24M(void);
1140/* @} */
1141
1142/*! @brief Enable USB HS clock.
1143 *
1144 * This function only enables the access to USB HS prepheral, upper layer
1145 * should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
1146 * clock to use USB HS.
1147 *
1148 * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
1149 * @param freq USB HS does not care about the clock source, so this parameter is ignored.
1150 * @retval true The clock is set successfully.
1151 * @retval false The clock source is invalid to get proper USB HS clock.
1152 */
1153bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
1154
1155/* @} */
1156
1157/*!
1158 * @name PLL/PFD operations
1159 * @{
1160 */
1161/*!
1162 * @brief PLL bypass setting
1163 *
1164 * @param base CCM_ANALOG base pointer.
1165 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1166 * @param bypass Bypass the PLL.
1167 * - true: Bypass the PLL.
1168 * - false:Not bypass the PLL.
1169 */
1170static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass)
1171{
1172 if (bypass)
1173 {
1174 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1175 }
1176 else
1177 {
1178 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1179 }
1180}
1181
1182/*!
1183 * @brief Check if PLL is bypassed
1184 *
1185 * @param base CCM_ANALOG base pointer.
1186 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1187 * @return PLL bypass status.
1188 * - true: The PLL is bypassed.
1189 * - false: The PLL is not bypassed.
1190 */
1191static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll)
1192{
1193 return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_PLL_BYPASS_SHIFT));
1194}
1195
1196/*!
1197 * @brief Check if PLL is enabled
1198 *
1199 * @param base CCM_ANALOG base pointer.
1200 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1201 * @return PLL bypass status.
1202 * - true: The PLL is enabled.
1203 * - false: The PLL is not enabled.
1204 */
1205static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll)
1206{
1207 return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pll)));
1208}
1209
1210/*!
1211 * @brief PLL bypass clock source setting.
1212 * Note: change the bypass clock source also change the pll reference clock source.
1213 *
1214 * @param base CCM_ANALOG base pointer.
1215 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1216 * @param src Bypass clock source, reference _clock_pll_bypass_clk_src.
1217 */
1218static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src)
1219{
1220 CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src;
1221}
1222
1223/*!
1224 * @brief Get PLL bypass clock value, it is PLL reference clock actually.
1225 * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0
1226 * will be returned.
1227 * @param base CCM_ANALOG base pointer.
1228 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1229 * @retval bypass reference clock frequency value.
1230 */
1231static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll)
1232{
1233 return ((((uint32_t)(CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) >>
1234 CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == (uint32_t)kCLOCK_PllClkSrc24M) ?
1235 CLOCK_GetOscFreq() :
1236 CLKPN_FREQ;
1237}
1238
1239/*!
1240 * @brief Initialize the System PLL.
1241 *
1242 * This function initializes the System PLL with specific settings
1243 *
1244 * @param config Configuration to set to PLL.
1245 */
1246void CLOCK_InitSysPll(const clock_sys_pll_config_t *config);
1247
1248/*!
1249 * @brief De-initialize the System PLL.
1250 */
1251void CLOCK_DeinitSysPll(void);
1252
1253/*!
1254 * @brief Initialize the USB1 PLL.
1255 *
1256 * This function initializes the USB1 PLL with specific settings
1257 *
1258 * @param config Configuration to set to PLL.
1259 */
1260void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config);
1261
1262/*!
1263 * @brief Deinitialize the USB1 PLL.
1264 */
1265void CLOCK_DeinitUsb1Pll(void);
1266
1267/*!
1268 * @brief Initializes the Audio PLL.
1269 *
1270 * This function initializes the Audio PLL with specific settings
1271 *
1272 * @param config Configuration to set to PLL.
1273 */
1274void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
1275
1276/*!
1277 * @brief De-initialize the Audio PLL.
1278 */
1279void CLOCK_DeinitAudioPll(void);
1280
1281/*!
1282 * @brief Initialize the ENET PLL.
1283 *
1284 * This function initializes the ENET PLL with specific settings.
1285 *
1286 * @param config Configuration to set to PLL.
1287 */
1288void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config);
1289
1290/*!
1291 * @brief Deinitialize the ENET PLL.
1292 *
1293 * This function disables the ENET PLL.
1294 */
1295void CLOCK_DeinitEnetPll(void);
1296
1297/*!
1298 * @brief Get current PLL output frequency.
1299 *
1300 * This function get current output frequency of specific PLL
1301 *
1302 * @param pll pll name to get frequency.
1303 * @return The PLL output frequency in hertz.
1304 */
1305uint32_t CLOCK_GetPllFreq(clock_pll_t pll);
1306
1307/*!
1308 * @brief Initialize the System PLL PFD.
1309 *
1310 * This function initializes the System PLL PFD. During new value setting,
1311 * the clock output is disabled to prevent glitch.
1312 *
1313 * @param pfd Which PFD clock to enable.
1314 * @param pfdFrac The PFD FRAC value.
1315 * @note It is recommended that PFD settings are kept between 12-35.
1316 */
1317void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac);
1318
1319/*!
1320 * @brief De-initialize the System PLL PFD.
1321 *
1322 * This function disables the System PLL PFD.
1323 *
1324 * @param pfd Which PFD clock to disable.
1325 */
1326void CLOCK_DeinitSysPfd(clock_pfd_t pfd);
1327
1328/*!
1329 * @brief Initialize the USB1 PLL PFD.
1330 *
1331 * This function initializes the USB1 PLL PFD. During new value setting,
1332 * the clock output is disabled to prevent glitch.
1333 *
1334 * @param pfd Which PFD clock to enable.
1335 * @param pfdFrac The PFD FRAC value.
1336 * @note It is recommended that PFD settings are kept between 12-35.
1337 */
1338void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac);
1339
1340/*!
1341 * @brief De-initialize the USB1 PLL PFD.
1342 *
1343 * This function disables the USB1 PLL PFD.
1344 *
1345 * @param pfd Which PFD clock to disable.
1346 */
1347void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd);
1348
1349/*!
1350 * @brief Get current System PLL PFD output frequency.
1351 *
1352 * This function get current output frequency of specific System PLL PFD
1353 *
1354 * @param pfd pfd name to get frequency.
1355 * @return The PFD output frequency in hertz.
1356 */
1357uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
1358
1359/*!
1360 * @brief Get current USB1 PLL PFD output frequency.
1361 *
1362 * This function get current output frequency of specific USB1 PLL PFD
1363 *
1364 * @param pfd pfd name to get frequency.
1365 * @return The PFD output frequency in hertz.
1366 */
1367uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd);
1368
1369/*! @brief Enable USB HS PHY PLL clock.
1370 *
1371 * This function enables the internal 480MHz USB PHY PLL clock.
1372 *
1373 * @param src USB HS PHY PLL clock source.
1374 * @param freq The frequency specified by src.
1375 * @retval true The clock is set successfully.
1376 * @retval false The clock source is invalid to get proper USB HS clock.
1377 */
1378bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1379
1380/*! @brief Disable USB HS PHY PLL clock.
1381 *
1382 * This function disables USB HS PHY PLL clock.
1383 */
1384void CLOCK_DisableUsbhs0PhyPllClock(void);
1385
1386/* @} */
1387
1388/*!
1389 * @name Clock Output Inferfaces
1390 * @{
1391 */
1392
1393/*!
1394 * @brief Set the clock source and the divider of the clock output1.
1395 *
1396 * @param selection The clock source to be output, please refer to @ref clock_output1_selection_t.
1397 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1398 */
1399void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider);
1400
1401/*!
1402 * @brief Set the clock source and the divider of the clock output2.
1403 *
1404 * @param selection The clock source to be output, please refer to @ref clock_output2_selection_t.
1405 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1406 */
1407void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider);
1408
1409/*!
1410 * @brief Get the frequency of clock output1 clock signal.
1411 *
1412 * @return The frequency of clock output1 clock signal.
1413 */
1414uint32_t CLOCK_GetClockOutCLKO1Freq(void);
1415
1416/*!
1417 * @brief Get the frequency of clock output2 clock signal.
1418 *
1419 * @return The frequency of clock output2 clock signal.
1420 */
1421uint32_t CLOCK_GetClockOutClkO2Freq(void);
1422
1423/*! @} */
1424
1425#if defined(__cplusplus)
1426}
1427#endif /* __cplusplus */
1428
1429/*! @} */
1430
1431#endif /* _FSL_CLOCK_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_flexram_allocate.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_flexram_allocate.c
new file mode 100644
index 000000000..2aa958521
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_flexram_allocate.c
@@ -0,0 +1,157 @@
1/*
2 * Copyright 2019-2020 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#include "fsl_flexram_allocate.h"
10
11/*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14
15/* Component ID definition, used by tools. */
16#ifndef FSL_COMPONENT_ID
17#define FSL_COMPONENT_ID "driver.soc_flexram_allocate"
18#endif
19
20/*******************************************************************************
21 * Prototypes
22 ******************************************************************************/
23/*!
24 * @brief FLEXRAM map TCM size to register value
25 *
26 * @param tcmBankNum tcm banknumber
27 * @retval register value correspond to the tcm size
28 */
29static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum);
30
31/*******************************************************************************
32 * Variables
33 ******************************************************************************/
34
35/*******************************************************************************
36 * Code
37 ******************************************************************************/
38static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum)
39{
40 uint8_t tcmSizeConfig = 0U;
41 uint32_t totalTcmSize = 0U;
42
43 /* if bank number is a odd value, use a new bank number which bigger than target */
44 do
45 {
46 if ((tcmBankNum & (tcmBankNum - 1U)) == 0U)
47 {
48 break;
49 }
50 } while (++tcmBankNum < (uint8_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);
51
52 totalTcmSize = (uint32_t)tcmBankNum * ((uint32_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE >> 10U);
53 /* get bit '1' position */
54 while (totalTcmSize != 0x00U)
55 {
56 if ((totalTcmSize & 1U) == 0U)
57 {
58 tcmSizeConfig++;
59 }
60 else
61 {
62 break;
63 }
64 totalTcmSize >>= 1U;
65 }
66
67 return tcmSizeConfig + 1U;
68}
69
70void FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum)
71{
72 assert(itcmBankNum <= (uint8_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);
73 assert(dtcmBankNum <= (uint8_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);
74
75 /* dtcm configuration */
76 if (dtcmBankNum != 0U)
77 {
78 IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK;
79 IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(FLEXRAM_MapTcmSizeToRegister(dtcmBankNum));
80 IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK;
81 }
82 else
83 {
84 IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK;
85 }
86
87 /* itcm configuration */
88 if (itcmBankNum != 0U)
89 {
90 IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK;
91 IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(FLEXRAM_MapTcmSizeToRegister(itcmBankNum));
92 IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK;
93 }
94 else
95 {
96 IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK;
97 }
98}
99
100/*!
101 * brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM
102 * This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate
103 * is needed.
104 * param config allocate configuration.
105 * retval kStatus_InvalidArgument the argument is invalid
106 * kStatus_Success allocate success
107 */
108status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config)
109{
110 assert(config != NULL);
111
112 uint8_t dtcmBankNum = config->dtcmBankNum;
113 uint8_t itcmBankNum = config->itcmBankNum;
114 uint8_t ocramBankNum = config->ocramBankNum;
115 uint8_t i = 0U;
116 uint32_t bankCfg = 0U;
117 status_t status = kStatus_Success;
118
119 /* check the arguments */
120 if ((uint8_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS < (dtcmBankNum + itcmBankNum + ocramBankNum))
121 {
122 status = kStatus_InvalidArgument;
123 }
124 else
125 {
126 /* flexram bank config value */
127 for (i = 0U; i < (uint8_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS; i++)
128 {
129 if (i < ocramBankNum)
130 {
131 bankCfg |= ((uint32_t)kFLEXRAM_BankOCRAM) << (i * 2U);
132 continue;
133 }
134
135 if (i < (dtcmBankNum + ocramBankNum))
136 {
137 bankCfg |= ((uint32_t)kFLEXRAM_BankDTCM) << (i * 2U);
138 continue;
139 }
140
141 if (i < (dtcmBankNum + ocramBankNum + itcmBankNum))
142 {
143 bankCfg |= ((uint32_t)kFLEXRAM_BankITCM) << (i * 2U);
144 continue;
145 }
146 }
147
148 IOMUXC_GPR->GPR17 = bankCfg;
149
150 /* set TCM size */
151 FLEXRAM_SetTCMSize(itcmBankNum, dtcmBankNum);
152 /* select ram allocate source from FLEXRAM_BANK_CFG */
153 FLEXRAM_SetAllocateRamSrc(kFLEXRAM_BankAllocateThroughBankCfg);
154 }
155
156 return status;
157}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_flexram_allocate.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_flexram_allocate.h
new file mode 100644
index 000000000..e2310683a
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_flexram_allocate.h
@@ -0,0 +1,99 @@
1/*
2 * Copyright 2019-2020 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_FLEXRAM_ALLOCATE_H_
10#define _FSL_FLEXRAM_ALLOCATE_H_
11
12#include "fsl_common.h"
13
14/*!
15 * @addtogroup flexram
16 * @{
17 */
18
19/******************************************************************************
20 * Definitions.
21 *****************************************************************************/
22
23/*! @name Driver version */
24/*@{*/
25/*! @brief SOC_FLEXRAM_ALLOCATE driver version 2.0.1. */
26#define FSL_SOC_FLEXRAM_ALLOCATE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
27/*@}*/
28
29/*! @brief FLEXRAM bank type */
30enum
31{
32 kFLEXRAM_BankNotUsed = 0U, /*!< bank is not used */
33 kFLEXRAM_BankOCRAM = 1U, /*!< bank is OCRAM */
34 kFLEXRAM_BankDTCM = 2U, /*!< bank is DTCM */
35 kFLEXRAM_BankITCM = 3U, /*!< bank is ITCM */
36};
37
38/*! @brief FLEXRAM bank allocate source */
39typedef enum _flexram_bank_allocate_src
40{
41 kFLEXRAM_BankAllocateThroughHardwareFuse = 0U, /*!< allocate ram through hardware fuse value */
42 kFLEXRAM_BankAllocateThroughBankCfg = 1U, /*!< allocate ram through FLEXRAM_BANK_CFG */
43} flexram_bank_allocate_src_t;
44
45/*! @brief FLEXRAM allocate ocram, itcm, dtcm size */
46typedef struct _flexram_allocate_ram
47{
48 const uint8_t ocramBankNum; /*!< ocram banknumber which the SOC support */
49 const uint8_t dtcmBankNum; /*!< dtcm bank number to allocate, the number should be power of 2 */
50 const uint8_t itcmBankNum; /*!< itcm bank number to allocate, the number should be power of 2 */
51} flexram_allocate_ram_t;
52
53/*******************************************************************************
54 * APIs
55 ******************************************************************************/
56
57#if defined(__cplusplus)
58extern "C" {
59#endif
60
61/*!
62 * @brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM
63 * This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate
64 * is needed.
65 * @param config allocate configuration.
66 * @retval kStatus_InvalidArgument the argument is invalid
67 * kStatus_Success allocate success
68 */
69status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config);
70
71/*!
72 * @brief FLEXRAM set allocate on-chip ram source
73 * @param src bank config source select value.
74 */
75static inline void FLEXRAM_SetAllocateRamSrc(flexram_bank_allocate_src_t src)
76{
77 IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK;
78 IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(src);
79}
80
81/*!
82 * @brief FLEXRAM configure TCM size
83 * This function is used to set the TCM to the target size. If a odd bank number is used,
84 * a new banknumber will be used which is bigger than target value, application can set tcm
85 * size to the biggest bank number always, then boundary access error can be captured by flexram only.
86 * When access to the TCM memory boundary ,hardfault will raised by core.
87 * @param itcmBankNum itcm bank number to allocate
88 * @param dtcmBankNum dtcm bank number to allocate
89 *
90 */
91void FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum);
92
93#if defined(__cplusplus)
94}
95#endif
96
97/*! @}*/
98
99#endif
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_iomuxc.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_iomuxc.h
new file mode 100644
index 000000000..b193e69c3
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_iomuxc.h
@@ -0,0 +1,564 @@
1/*
2 * Copyright 2016 Freescale Semiconductor, Inc.
3 * Copyright 2016-2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_IOMUXC_H_
10#define _FSL_IOMUXC_H_
11
12#include "fsl_common.h"
13
14/*!
15 * @addtogroup iomuxc_driver
16 * @{
17 */
18
19/*! @file */
20
21/*******************************************************************************
22 * Definitions
23 ******************************************************************************/
24/* Component ID definition, used by tools. */
25#ifndef FSL_COMPONENT_ID
26#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
27#endif
28
29/*! @name Driver version */
30/*@{*/
31/*! @brief IOMUXC driver version 2.0.3. */
32#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
33/*@}*/
34
35/*!
36 * @name Pin function ID
37 * The pin function ID is a tuple of \<muxRegister muxMode inputRegister inputDaisy configRegister\>
38 *
39 * @{
40 */
41#define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ 0x400A8004U, 0x0U, 0, 0, 0x400A801CU
42#define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 0x400A8004U, 0x5U, 0, 0, 0x400A801CU
43
44#define IOMUXC_SNVS_TEST_MODE 0, 0, 0, 0, 0x400A800CU
45
46#define IOMUXC_SNVS_POR_B 0, 0, 0, 0, 0x400A8010U
47
48#define IOMUXC_SNVS_ONOFF 0, 0, 0, 0, 0x400A8014U
49
50#define IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT04 0x401F8024U, 0x1U, 0, 0, 0x401F8198U
51#define IOMUXC_GPIO_EMC_04_SPDIF_OUT 0x401F8024U, 0x2U, 0, 0, 0x401F8198U
52#define IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK 0x401F8024U, 0x3U, 0x401F8464U, 0x1U, 0x401F8198U
53#define IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16 0x401F8024U, 0x4U, 0, 0, 0x401F8198U
54#define IOMUXC_GPIO_EMC_04_GPIO2_IO04 0x401F8024U, 0x5U, 0, 0, 0x401F8198U
55#define IOMUXC_GPIO_EMC_04_SJC_JTAG_ACT 0x401F8024U, 0x7U, 0, 0, 0x401F8198U
56
57#define IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT05 0x401F8028U, 0x1U, 0, 0, 0x401F819CU
58#define IOMUXC_GPIO_EMC_05_SPDIF_IN 0x401F8028U, 0x2U, 0x401F8488U, 0x0U, 0x401F819CU
59#define IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x401F8028U, 0x3U, 0x401F8468U, 0x1U, 0x401F819CU
60#define IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17 0x401F8028U, 0x4U, 0, 0, 0x401F819CU
61#define IOMUXC_GPIO_EMC_05_GPIO2_IO05 0x401F8028U, 0x5U, 0, 0, 0x401F819CU
62#define IOMUXC_GPIO_EMC_05_SJC_DE_B 0x401F8028U, 0x7U, 0, 0, 0x401F819CU
63
64#define IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT06 0x401F802CU, 0x1U, 0, 0, 0x401F81A0U
65#define IOMUXC_GPIO_EMC_06_LPUART3_TX 0x401F802CU, 0x2U, 0x401F83DCU, 0x0U, 0x401F81A0U
66#define IOMUXC_GPIO_EMC_06_SAI2_TX_DATA 0x401F802CU, 0x3U, 0, 0, 0x401F81A0U
67#define IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18 0x401F802CU, 0x4U, 0, 0, 0x401F81A0U
68#define IOMUXC_GPIO_EMC_06_GPIO2_IO06 0x401F802CU, 0x5U, 0, 0, 0x401F81A0U
69
70#define IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT07 0x401F8030U, 0x1U, 0, 0, 0x401F81A4U
71#define IOMUXC_GPIO_EMC_07_LPUART3_RX 0x401F8030U, 0x2U, 0x401F83D8U, 0x0U, 0x401F81A4U
72#define IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC 0x401F8030U, 0x3U, 0x401F8460U, 0x1U, 0x401F81A4U
73#define IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19 0x401F8030U, 0x4U, 0, 0, 0x401F81A4U
74#define IOMUXC_GPIO_EMC_07_GPIO2_IO07 0x401F8030U, 0x5U, 0, 0, 0x401F81A4U
75
76#define IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT08 0x401F8034U, 0x1U, 0, 0, 0x401F81A8U
77#define IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x401F8034U, 0x3U, 0x401F845CU, 0x1U, 0x401F81A8U
78#define IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20 0x401F8034U, 0x4U, 0, 0, 0x401F81A8U
79#define IOMUXC_GPIO_EMC_08_GPIO2_IO08 0x401F8034U, 0x5U, 0, 0, 0x401F81A8U
80
81#define IOMUXC_GPIO_EMC_09_XBAR1_XBAR_INOUT09 0x401F8038U, 0x1U, 0, 0, 0x401F81ACU
82#define IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK 0x401F8038U, 0x3U, 0x401F8458U, 0x1U, 0x401F81ACU
83#define IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21 0x401F8038U, 0x4U, 0, 0, 0x401F81ACU
84#define IOMUXC_GPIO_EMC_09_GPIO2_IO09 0x401F8038U, 0x5U, 0, 0, 0x401F81ACU
85
86#define IOMUXC_GPIO_EMC_16_MQS_RIGHT 0x401F8054U, 0x2U, 0, 0, 0x401F81C8U
87#define IOMUXC_GPIO_EMC_16_SAI2_MCLK 0x401F8054U, 0x3U, 0x401F8454U, 0x1U, 0x401F81C8U
88#define IOMUXC_GPIO_EMC_16_GPIO2_IO16 0x401F8054U, 0x5U, 0, 0, 0x401F81C8U
89#define IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE00 0x401F8054U, 0x6U, 0, 0, 0x401F81C8U
90
91#define IOMUXC_GPIO_EMC_17_MQS_LEFT 0x401F8058U, 0x2U, 0, 0, 0x401F81CCU
92#define IOMUXC_GPIO_EMC_17_SAI3_MCLK 0x401F8058U, 0x3U, 0x401F846CU, 0x1U, 0x401F81CCU
93#define IOMUXC_GPIO_EMC_17_GPIO2_IO17 0x401F8058U, 0x5U, 0, 0, 0x401F81CCU
94#define IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE01 0x401F8058U, 0x6U, 0, 0, 0x401F81CCU
95
96#define IOMUXC_GPIO_EMC_18_XBAR1_XBAR_INOUT16 0x401F805CU, 0x1U, 0x401F84A8U, 0x1U, 0x401F81D0U
97#define IOMUXC_GPIO_EMC_18_LPI2C2_SDA 0x401F805CU, 0x2U, 0x401F8388U, 0x1U, 0x401F81D0U
98#define IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC 0x401F805CU, 0x3U, 0x401F8448U, 0x2U, 0x401F81D0U
99#define IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22 0x401F805CU, 0x4U, 0, 0, 0x401F81D0U
100#define IOMUXC_GPIO_EMC_18_GPIO2_IO18 0x401F805CU, 0x5U, 0, 0, 0x401F81D0U
101#define IOMUXC_GPIO_EMC_18_SRC_BT_CFG00 0x401F805CU, 0x6U, 0, 0, 0x401F81D0U
102
103#define IOMUXC_GPIO_EMC_19_XBAR1_XBAR_INOUT17 0x401F8060U, 0x1U, 0x401F84ACU, 0x1U, 0x401F81D4U
104#define IOMUXC_GPIO_EMC_19_LPI2C2_SCL 0x401F8060U, 0x2U, 0x401F8384U, 0x1U, 0x401F81D4U
105#define IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK 0x401F8060U, 0x3U, 0x401F8434U, 0x2U, 0x401F81D4U
106#define IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23 0x401F8060U, 0x4U, 0, 0, 0x401F81D4U
107#define IOMUXC_GPIO_EMC_19_GPIO2_IO19 0x401F8060U, 0x5U, 0, 0, 0x401F81D4U
108#define IOMUXC_GPIO_EMC_19_SRC_BT_CFG01 0x401F8060U, 0x6U, 0, 0, 0x401F81D4U
109
110#define IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA03 0x401F8064U, 0x1U, 0x401F8334U, 0x1U, 0x401F81D8U
111#define IOMUXC_GPIO_EMC_20_LPUART2_CTS_B 0x401F8064U, 0x2U, 0x401F83CCU, 0x1U, 0x401F81D8U
112#define IOMUXC_GPIO_EMC_20_SAI1_MCLK 0x401F8064U, 0x3U, 0x401F8430U, 0x3U, 0x401F81D8U
113#define IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24 0x401F8064U, 0x4U, 0, 0, 0x401F81D8U
114#define IOMUXC_GPIO_EMC_20_GPIO2_IO20 0x401F8064U, 0x5U, 0, 0, 0x401F81D8U
115#define IOMUXC_GPIO_EMC_20_SRC_BT_CFG02 0x401F8064U, 0x6U, 0, 0, 0x401F81D8U
116
117#define IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB03 0x401F8068U, 0x1U, 0x401F8344U, 0x1U, 0x401F81DCU
118#define IOMUXC_GPIO_EMC_21_LPUART2_RTS_B 0x401F8068U, 0x2U, 0, 0, 0x401F81DCU
119#define IOMUXC_GPIO_EMC_21_SAI1_RX_DATA00 0x401F8068U, 0x3U, 0x401F8438U, 0x2U, 0x401F81DCU
120#define IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25 0x401F8068U, 0x4U, 0, 0, 0x401F81DCU
121#define IOMUXC_GPIO_EMC_21_GPIO2_IO21 0x401F8068U, 0x5U, 0, 0, 0x401F81DCU
122#define IOMUXC_GPIO_EMC_21_SRC_BT_CFG03 0x401F8068U, 0x6U, 0, 0, 0x401F81DCU
123
124#define IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA02 0x401F806CU, 0x1U, 0x401F8330U, 0x1U, 0x401F81E0U
125#define IOMUXC_GPIO_EMC_22_LPUART2_TX 0x401F806CU, 0x2U, 0x401F83D4U, 0x1U, 0x401F81E0U
126#define IOMUXC_GPIO_EMC_22_SAI1_TX_DATA03 0x401F806CU, 0x3U, 0x401F843CU, 0x1U, 0x401F81E0U
127#define IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26 0x401F806CU, 0x4U, 0, 0, 0x401F81E0U
128#define IOMUXC_GPIO_EMC_22_GPIO2_IO22 0x401F806CU, 0x5U, 0, 0, 0x401F81E0U
129#define IOMUXC_GPIO_EMC_22_SRC_BT_CFG04 0x401F806CU, 0x6U, 0, 0, 0x401F81E0U
130
131#define IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB02 0x401F8070U, 0x1U, 0x401F8340U, 0x1U, 0x401F81E4U
132#define IOMUXC_GPIO_EMC_23_LPUART2_RX 0x401F8070U, 0x2U, 0x401F83D0U, 0x1U, 0x401F81E4U
133#define IOMUXC_GPIO_EMC_23_SAI1_TX_DATA02 0x401F8070U, 0x3U, 0x401F8440U, 0x1U, 0x401F81E4U
134#define IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27 0x401F8070U, 0x4U, 0, 0, 0x401F81E4U
135#define IOMUXC_GPIO_EMC_23_GPIO2_IO23 0x401F8070U, 0x5U, 0, 0, 0x401F81E4U
136#define IOMUXC_GPIO_EMC_23_SRC_BT_CFG05 0x401F8070U, 0x6U, 0, 0, 0x401F81E4U
137
138#define IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA01 0x401F8074U, 0x1U, 0x401F832CU, 0x1U, 0x401F81E8U
139#define IOMUXC_GPIO_EMC_24_SAI1_TX_DATA01 0x401F8074U, 0x3U, 0x401F8444U, 0x1U, 0x401F81E8U
140#define IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28 0x401F8074U, 0x4U, 0, 0, 0x401F81E8U
141#define IOMUXC_GPIO_EMC_24_GPIO2_IO24 0x401F8074U, 0x5U, 0, 0, 0x401F81E8U
142#define IOMUXC_GPIO_EMC_24_SRC_BT_CFG06 0x401F8074U, 0x6U, 0, 0, 0x401F81E8U
143
144#define IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB01 0x401F8078U, 0x1U, 0x401F833CU, 0x1U, 0x401F81ECU
145#define IOMUXC_GPIO_EMC_25_SAI1_TX_DATA00 0x401F8078U, 0x3U, 0, 0, 0x401F81ECU
146#define IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29 0x401F8078U, 0x4U, 0, 0, 0x401F81ECU
147#define IOMUXC_GPIO_EMC_25_GPIO2_IO25 0x401F8078U, 0x5U, 0, 0, 0x401F81ECU
148#define IOMUXC_GPIO_EMC_25_SRC_BT_CFG07 0x401F8078U, 0x6U, 0, 0, 0x401F81ECU
149
150#define IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA00 0x401F807CU, 0x1U, 0x401F8328U, 0x1U, 0x401F81F0U
151#define IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK 0x401F807CU, 0x3U, 0x401F844CU, 0x2U, 0x401F81F0U
152#define IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30 0x401F807CU, 0x4U, 0, 0, 0x401F81F0U
153#define IOMUXC_GPIO_EMC_26_GPIO2_IO26 0x401F807CU, 0x5U, 0, 0, 0x401F81F0U
154#define IOMUXC_GPIO_EMC_26_SRC_BT_CFG08 0x401F807CU, 0x6U, 0, 0, 0x401F81F0U
155
156#define IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB00 0x401F8080U, 0x1U, 0x401F8338U, 0x1U, 0x401F81F4U
157#define IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC 0x401F8080U, 0x3U, 0x401F8450U, 0x2U, 0x401F81F4U
158#define IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31 0x401F8080U, 0x4U, 0, 0, 0x401F81F4U
159#define IOMUXC_GPIO_EMC_27_GPIO2_IO27 0x401F8080U, 0x5U, 0, 0, 0x401F81F4U
160#define IOMUXC_GPIO_EMC_27_SRC_BT_CFG09 0x401F8080U, 0x6U, 0, 0, 0x401F81F4U
161
162#define IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0 0x401F8094U, 0x1U, 0x401F8410U, 0x1U, 0x401F8208U
163#define IOMUXC_GPIO_EMC_32_LPUART4_TX 0x401F8094U, 0x2U, 0x401F83E8U, 0x2U, 0x401F8208U
164#define IOMUXC_GPIO_EMC_32_SAI3_TX_DATA 0x401F8094U, 0x3U, 0, 0, 0x401F8208U
165#define IOMUXC_GPIO_EMC_32_GPIO3_IO00 0x401F8094U, 0x5U, 0, 0, 0x401F8208U
166#define IOMUXC_GPIO_EMC_32_REF_24M_OUT 0x401F8094U, 0x7U, 0, 0, 0x401F8208U
167
168#define IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1 0x401F8098U, 0x1U, 0x401F8414U, 0x1U, 0x401F820CU
169#define IOMUXC_GPIO_EMC_33_LPUART4_RX 0x401F8098U, 0x2U, 0x401F83E4U, 0x2U, 0x401F820CU
170#define IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK 0x401F8098U, 0x3U, 0x401F847CU, 0x1U, 0x401F820CU
171#define IOMUXC_GPIO_EMC_33_GPIO3_IO01 0x401F8098U, 0x5U, 0, 0, 0x401F820CU
172
173#define IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2 0x401F809CU, 0x1U, 0x401F8418U, 0x1U, 0x401F8210U
174#define IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC 0x401F809CU, 0x3U, 0x401F8480U, 0x1U, 0x401F8210U
175#define IOMUXC_GPIO_EMC_34_GPIO3_IO02 0x401F809CU, 0x5U, 0, 0, 0x401F8210U
176
177#define IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3 0x401F80A0U, 0x1U, 0x401F841CU, 0x1U, 0x401F8214U
178#define IOMUXC_GPIO_EMC_35_GPIO3_IO03 0x401F80A0U, 0x5U, 0, 0, 0x401F8214U
179
180#define IOMUXC_GPIO_AD_B0_00_JTAG_MUX_TMS 0x401F80BCU, 0x0U, 0, 0, 0x401F8230U
181#define IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x401F80BCU, 0x5U, 0, 0, 0x401F8230U
182#define IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1 0x401F80BCU, 0x7U, 0, 0, 0x401F8230U
183
184#define IOMUXC_GPIO_AD_B0_01_JTAG_MUX_TCK 0x401F80C0U, 0x0U, 0, 0, 0x401F8234U
185#define IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x401F80C0U, 0x5U, 0, 0, 0x401F8234U
186#define IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2 0x401F80C0U, 0x7U, 0, 0, 0x401F8234U
187
188#define IOMUXC_GPIO_AD_B0_02_JTAG_MUX_MOD 0x401F80C4U, 0x0U, 0, 0, 0x401F8238U
189#define IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x401F80C4U, 0x5U, 0, 0, 0x401F8238U
190#define IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1 0x401F80C4U, 0x7U, 0, 0, 0x401F8238U
191
192#define IOMUXC_GPIO_AD_B0_03_JTAG_MUX_TDI 0x401F80C8U, 0x0U, 0, 0, 0x401F823CU
193#define IOMUXC_GPIO_AD_B0_03_WDOG1_WDOG_B 0x401F80C8U, 0x2U, 0, 0, 0x401F823CU
194#define IOMUXC_GPIO_AD_B0_03_SAI1_MCLK 0x401F80C8U, 0x3U, 0x401F8430U, 0x1U, 0x401F823CU
195#define IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x401F80C8U, 0x5U, 0, 0, 0x401F823CU
196#define IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x401F80C8U, 0x6U, 0x401F848CU, 0x0U, 0x401F823CU
197#define IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY 0x401F80C8U, 0x7U, 0x401F8300U, 0x2U, 0x401F823CU
198
199#define IOMUXC_GPIO_AD_B0_04_JTAG_MUX_TDO 0x401F80CCU, 0x0U, 0, 0, 0x401F8240U
200#define IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x401F80CCU, 0x5U, 0, 0, 0x401F8240U
201#define IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR 0x401F80CCU, 0x6U, 0, 0, 0x401F8240U
202#define IOMUXC_GPIO_AD_B0_04_EWM_EWM_OUT_B 0x401F80CCU, 0x7U, 0, 0, 0x401F8240U
203
204#define IOMUXC_GPIO_AD_B0_05_JTAG_MUX_TRSTB 0x401F80D0U, 0x0U, 0, 0, 0x401F8244U
205#define IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x401F80D0U, 0x5U, 0, 0, 0x401F8244U
206#define IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID 0x401F80D0U, 0x6U, 0x401F82FCU, 0x0U, 0x401F8244U
207#define IOMUXC_GPIO_AD_B0_05_NMI_GLUE_NMI 0x401F80D0U, 0x7U, 0x401F840CU, 0x0U, 0x401F8244U
208
209#define IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER00 0x401F80D4U, 0x0U, 0, 0, 0x401F8248U
210#define IOMUXC_GPIO_AD_B0_06_MQS_RIGHT 0x401F80D4U, 0x1U, 0, 0, 0x401F8248U
211#define IOMUXC_GPIO_AD_B0_06_LPUART1_TX 0x401F80D4U, 0x2U, 0, 0, 0x401F8248U
212#define IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x401F80D4U, 0x5U, 0, 0, 0x401F8248U
213#define IOMUXC_GPIO_AD_B0_06_REF_32K_OUT 0x401F80D4U, 0x6U, 0, 0, 0x401F8248U
214
215#define IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER01 0x401F80D8U, 0x0U, 0, 0, 0x401F824CU
216#define IOMUXC_GPIO_AD_B0_07_MQS_LEFT 0x401F80D8U, 0x1U, 0, 0, 0x401F824CU
217#define IOMUXC_GPIO_AD_B0_07_LPUART1_RX 0x401F80D8U, 0x2U, 0, 0, 0x401F824CU
218#define IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x401F80D8U, 0x5U, 0, 0, 0x401F824CU
219#define IOMUXC_GPIO_AD_B0_07_REF_24M_OUT 0x401F80D8U, 0x6U, 0, 0, 0x401F824CU
220
221#define IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B 0x401F80DCU, 0x2U, 0, 0, 0x401F8250U
222#define IOMUXC_GPIO_AD_B0_08_KPP_COL00 0x401F80DCU, 0x3U, 0, 0, 0x401F8250U
223#define IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x401F80DCU, 0x5U, 0, 0, 0x401F8250U
224#define IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV 0x401F80DCU, 0x6U, 0, 0, 0x401F8250U
225
226#define IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B 0x401F80E0U, 0x2U, 0, 0, 0x401F8254U
227#define IOMUXC_GPIO_AD_B0_09_KPP_ROW00 0x401F80E0U, 0x3U, 0, 0, 0x401F8254U
228#define IOMUXC_GPIO_AD_B0_09_CSU_CSU_INT_DEB 0x401F80E0U, 0x4U, 0, 0, 0x401F8254U
229#define IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x401F80E0U, 0x5U, 0, 0, 0x401F8254U
230#define IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV 0x401F80E0U, 0x6U, 0, 0, 0x401F8254U
231
232#define IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK 0x401F80E4U, 0x1U, 0x401F83A0U, 0x1U, 0x401F8258U
233#define IOMUXC_GPIO_AD_B0_10_KPP_COL01 0x401F80E4U, 0x3U, 0, 0, 0x401F8258U
234#define IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x401F80E4U, 0x5U, 0, 0, 0x401F8258U
235
236#define IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 0x401F80E8U, 0x1U, 0x401F839CU, 0x1U, 0x401F825CU
237#define IOMUXC_GPIO_AD_B0_11_KPP_ROW01 0x401F80E8U, 0x3U, 0, 0, 0x401F825CU
238#define IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x401F80E8U, 0x5U, 0, 0, 0x401F825CU
239
240#define IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO 0x401F80ECU, 0x1U, 0x401F83A8U, 0x1U, 0x401F8260U
241#define IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B 0x401F80ECU, 0x2U, 0, 0, 0x401F8260U
242#define IOMUXC_GPIO_AD_B0_12_KPP_COL02 0x401F80ECU, 0x3U, 0, 0, 0x401F8260U
243#define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x401F80ECU, 0x5U, 0, 0, 0x401F8260U
244#define IOMUXC_GPIO_AD_B0_12_SNVS_HP_VIO_5_CTL 0x401F80ECU, 0x7U, 0, 0, 0x401F8260U
245
246#define IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI 0x401F80F0U, 0x1U, 0x401F83A4U, 0x1U, 0x401F8264U
247#define IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B 0x401F80F0U, 0x2U, 0, 0, 0x401F8264U
248#define IOMUXC_GPIO_AD_B0_13_KPP_ROW02 0x401F80F0U, 0x3U, 0, 0, 0x401F8264U
249#define IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x401F80F0U, 0x5U, 0, 0, 0x401F8264U
250#define IOMUXC_GPIO_AD_B0_13_SNVS_HP_VIO_5_B 0x401F80F0U, 0x7U, 0, 0, 0x401F8264U
251
252#define IOMUXC_GPIO_AD_B0_14_LPUART3_TX 0x401F80F4U, 0x2U, 0x401F83DCU, 0x1U, 0x401F8268U
253#define IOMUXC_GPIO_AD_B0_14_KPP_COL03 0x401F80F4U, 0x3U, 0, 0, 0x401F8268U
254#define IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x401F80F4U, 0x5U, 0, 0, 0x401F8268U
255#define IOMUXC_GPIO_AD_B0_14_WDOG1_WDOG_ANY 0x401F80F4U, 0x7U, 0, 0, 0x401F8268U
256
257#define IOMUXC_GPIO_AD_B0_15_LPUART3_RX 0x401F80F8U, 0x2U, 0x401F83D8U, 0x1U, 0x401F826CU
258#define IOMUXC_GPIO_AD_B0_15_KPP_ROW03 0x401F80F8U, 0x3U, 0, 0, 0x401F826CU
259#define IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x401F80F8U, 0x5U, 0, 0, 0x401F826CU
260
261#define IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR 0x401F8124U, 0x0U, 0, 0, 0x401F8298U
262#define IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA02 0x401F8124U, 0x1U, 0x401F8330U, 0x0U, 0x401F8298U
263#define IOMUXC_GPIO_AD_B1_10_LPUART4_TX 0x401F8124U, 0x2U, 0x401F83E8U, 0x1U, 0x401F8298U
264#define IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05 0x401F8124U, 0x4U, 0, 0, 0x401F8298U
265#define IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x401F8124U, 0x5U, 0, 0, 0x401F8298U
266#define IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1 0x401F8124U, 0x6U, 0, 0, 0x401F8298U
267
268#define IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID 0x401F8128U, 0x0U, 0x401F82FCU, 0x1U, 0x401F829CU
269#define IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB02 0x401F8128U, 0x1U, 0x401F8340U, 0x0U, 0x401F829CU
270#define IOMUXC_GPIO_AD_B1_11_LPUART4_RX 0x401F8128U, 0x2U, 0x401F83E4U, 0x1U, 0x401F829CU
271#define IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04 0x401F8128U, 0x4U, 0, 0, 0x401F829CU
272#define IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x401F8128U, 0x5U, 0, 0, 0x401F829CU
273#define IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1 0x401F8128U, 0x6U, 0, 0, 0x401F829CU
274
275#define IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC 0x401F812CU, 0x0U, 0x401F848CU, 0x1U, 0x401F82A0U
276#define IOMUXC_GPIO_AD_B1_12_ACMP_OUT00 0x401F812CU, 0x1U, 0, 0, 0x401F82A0U
277#define IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03 0x401F812CU, 0x4U, 0, 0, 0x401F82A0U
278#define IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x401F812CU, 0x5U, 0, 0, 0x401F82A0U
279#define IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA03 0x401F812CU, 0x6U, 0x401F8334U, 0x0U, 0x401F82A0U
280
281#define IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ 0x401F8130U, 0x0U, 0, 0, 0x401F82A4U
282#define IOMUXC_GPIO_AD_B1_13_ACMP_OUT01 0x401F8130U, 0x1U, 0, 0, 0x401F82A4U
283#define IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02 0x401F8130U, 0x4U, 0, 0, 0x401F82A4U
284#define IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x401F8130U, 0x5U, 0, 0, 0x401F82A4U
285#define IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB03 0x401F8130U, 0x6U, 0x401F8344U, 0x0U, 0x401F82A4U
286
287#define IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL 0x401F8134U, 0x0U, 0x401F837CU, 0x1U, 0x401F82A8U
288#define IOMUXC_GPIO_AD_B1_14_ACMP_OUT02 0x401F8134U, 0x1U, 0, 0, 0x401F82A8U
289#define IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01 0x401F8134U, 0x4U, 0, 0, 0x401F82A8U
290#define IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x401F8134U, 0x5U, 0, 0, 0x401F82A8U
291
292#define IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA 0x401F8138U, 0x0U, 0x401F8380U, 0x1U, 0x401F82ACU
293#define IOMUXC_GPIO_AD_B1_15_ACMP_OUT03 0x401F8138U, 0x1U, 0, 0, 0x401F82ACU
294#define IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00 0x401F8138U, 0x4U, 0, 0, 0x401F82ACU
295#define IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x401F8138U, 0x5U, 0, 0, 0x401F82ACU
296#define IOMUXC_GPIO_AD_B1_15_CCM_DI0_EXT_CLK 0x401F8138U, 0x6U, 0, 0, 0x401F82ACU
297
298#define IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA03 0x401F8158U, 0x1U, 0, 0, 0x401F82CCU
299#define IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT10 0x401F8158U, 0x3U, 0x401F84B0U, 0x1U, 0x401F82CCU
300#define IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 0x401F8158U, 0x5U, 0, 0, 0x401F82CCU
301
302#define IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK 0x401F815CU, 0x1U, 0, 0, 0x401F82D0U
303#define IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B 0x401F815CU, 0x3U, 0, 0, 0x401F82D0U
304#define IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 0x401F815CU, 0x5U, 0, 0, 0x401F82D0U
305
306#define IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA00 0x401F8160U, 0x1U, 0, 0, 0x401F82D4U
307#define IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 0x401F8160U, 0x5U, 0, 0, 0x401F82D4U
308#define IOMUXC_GPIO_SD_B1_02_CCM_CLKO1 0x401F8160U, 0x6U, 0, 0, 0x401F82D4U
309
310#define IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA02 0x401F8164U, 0x1U, 0, 0, 0x401F82D8U
311#define IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 0x401F8164U, 0x5U, 0, 0, 0x401F82D8U
312#define IOMUXC_GPIO_SD_B1_03_CCM_CLKO2 0x401F8164U, 0x6U, 0, 0, 0x401F82D8U
313
314#define IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA01 0x401F8168U, 0x1U, 0, 0, 0x401F82DCU
315#define IOMUXC_GPIO_SD_B1_04_EWM_EWM_OUT_B 0x401F8168U, 0x4U, 0, 0, 0x401F82DCU
316#define IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 0x401F8168U, 0x5U, 0, 0, 0x401F82DCU
317#define IOMUXC_GPIO_SD_B1_04_CCM_WAIT 0x401F8168U, 0x6U, 0, 0, 0x401F82DCU
318
319#define IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x401F816CU, 0x1U, 0, 0, 0x401F82E0U
320#define IOMUXC_GPIO_SD_B1_05_SAI3_MCLK 0x401F816CU, 0x3U, 0x401F846CU, 0x0U, 0x401F82E0U
321#define IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B 0x401F816CU, 0x4U, 0, 0, 0x401F82E0U
322#define IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 0x401F816CU, 0x5U, 0, 0, 0x401F82E0U
323#define IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY 0x401F816CU, 0x6U, 0x401F8300U, 0x1U, 0x401F82E0U
324
325#define IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03 0x401F8170U, 0x1U, 0x401F8374U, 0x0U, 0x401F82E4U
326#define IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK 0x401F8170U, 0x3U, 0x401F847CU, 0x0U, 0x401F82E4U
327#define IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x401F8170U, 0x4U, 0x401F83ACU, 0x2U, 0x401F82E4U
328#define IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 0x401F8170U, 0x5U, 0, 0, 0x401F82E4U
329#define IOMUXC_GPIO_SD_B1_06_CCM_STOP 0x401F8170U, 0x6U, 0, 0, 0x401F82E4U
330
331#define IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x401F8174U, 0x1U, 0x401F8378U, 0x0U, 0x401F82E8U
332#define IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC 0x401F8174U, 0x3U, 0x401F8480U, 0x0U, 0x401F82E8U
333#define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x401F8174U, 0x4U, 0x401F83B0U, 0x2U, 0x401F82E8U
334#define IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 0x401F8174U, 0x5U, 0, 0, 0x401F82E8U
335
336#define IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00 0x401F8178U, 0x1U, 0x401F8368U, 0x0U, 0x401F82ECU
337#define IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA 0x401F8178U, 0x3U, 0, 0, 0x401F82ECU
338#define IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x401F8178U, 0x4U, 0x401F83B8U, 0x2U, 0x401F82ECU
339#define IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 0x401F8178U, 0x5U, 0, 0, 0x401F82ECU
340
341#define IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02 0x401F817CU, 0x1U, 0x401F8370U, 0x0U, 0x401F82F0U
342#define IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK 0x401F817CU, 0x3U, 0x401F8470U, 0x0U, 0x401F82F0U
343#define IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x401F817CU, 0x4U, 0x401F83B4U, 0x2U, 0x401F82F0U
344#define IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 0x401F817CU, 0x5U, 0, 0, 0x401F82F0U
345#define IOMUXC_GPIO_SD_B1_09_CCM_REF_EN_B 0x401F817CU, 0x6U, 0, 0, 0x401F82F0U
346
347#define IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01 0x401F8180U, 0x1U, 0x401F836CU, 0x0U, 0x401F82F4U
348#define IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC 0x401F8180U, 0x3U, 0x401F8478U, 0x0U, 0x401F82F4U
349#define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x401F8180U, 0x4U, 0, 0, 0x401F82F4U
350#define IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 0x401F8180U, 0x5U, 0, 0, 0x401F82F4U
351
352#define IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B 0x401F8184U, 0x1U, 0, 0, 0x401F82F8U
353#define IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA 0x401F8184U, 0x3U, 0x401F8474U, 0x0U, 0x401F82F8U
354#define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8184U, 0x4U, 0, 0, 0x401F82F8U
355#define IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 0x401F8184U, 0x5U, 0, 0, 0x401F82F8U
356
357/*@}*/
358
359#define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U)
360#define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U)
361
362typedef enum _iomuxc_gpr_mode
363{
364 kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK,
365 kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK,
366 kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK,
367 kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK,
368 kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK,
369 kIOMUXC_GPR_AHBClockEnable = (int)IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK,
370} iomuxc_gpr_mode_t;
371
372typedef enum _iomuxc_gpr_saimclk
373{
374 kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT,
375 kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT,
376 kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT,
377 kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT,
378 kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT,
379} iomuxc_gpr_saimclk_t;
380
381typedef enum _iomuxc_mqs_pwm_oversample_rate
382{
383 kIOMUXC_MqsPwmOverSampleRate32 = 0, /* MQS PWM over sampling rate 32. */
384 kIOMUXC_MqsPwmOverSampleRate64 = 1 /* MQS PWM over sampling rate 64. */
385} iomuxc_mqs_pwm_oversample_rate_t;
386
387#if defined(__cplusplus)
388extern "C" {
389#endif /*_cplusplus */
390
391/*! @name Configuration */
392/*@{*/
393
394/*!
395 * @brief Sets the IOMUXC pin mux mode.
396 * @note The first five parameters can be filled with the pin function ID macros.
397 *
398 * This is an example to set the PTA6 as the lpuart0_tx:
399 * @code
400 * IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0);
401 * @endcode
402 *
403 * This is an example to set the PTA0 as GPIOA0:
404 * @code
405 * IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0);
406 * @endcode
407 *
408 * @param muxRegister The pin mux register.
409 * @param muxMode The pin mux mode.
410 * @param inputRegister The select input register.
411 * @param inputDaisy The input daisy.
412 * @param configRegister The config register.
413 * @param inputOnfield Software input on field.
414 */
415static inline void IOMUXC_SetPinMux(uint32_t muxRegister,
416 uint32_t muxMode,
417 uint32_t inputRegister,
418 uint32_t inputDaisy,
419 uint32_t configRegister,
420 uint32_t inputOnfield)
421{
422 *((volatile uint32_t *)muxRegister) =
423 IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
424
425 if (inputRegister != 0UL)
426 {
427 *((volatile uint32_t *)inputRegister) = inputDaisy;
428 }
429}
430
431/*!
432 * @brief Sets the IOMUXC pin configuration.
433 * @note The previous five parameters can be filled with the pin function ID macros.
434 *
435 * This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS:
436 * @code
437 * IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U))
438 * @endcode
439 *
440 * @param muxRegister The pin mux register.
441 * @param muxMode The pin mux mode.
442 * @param inputRegister The select input register.
443 * @param inputDaisy The input daisy.
444 * @param configRegister The config register.
445 * @param configValue The pin config value.
446 */
447static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
448 uint32_t muxMode,
449 uint32_t inputRegister,
450 uint32_t inputDaisy,
451 uint32_t configRegister,
452 uint32_t configValue)
453{
454 if (configRegister != 0UL)
455 {
456 *((volatile uint32_t *)configRegister) = configValue;
457 }
458}
459
460/*!
461 * @brief Sets IOMUXC general configuration for some mode.
462 *
463 * @param base The IOMUXC GPR base address.
464 * @param mode The mode for setting. the mode is the logical OR of "iomuxc_gpr_mode"
465 * @param enable True enable false disable.
466 */
467static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable)
468{
469 mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK |
470 IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK |
471 IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK);
472
473 if (enable)
474 {
475 base->GPR1 |= mode;
476 }
477 else
478 {
479 base->GPR1 &= ~mode;
480 }
481}
482
483/*!
484 * @brief Sets IOMUXC general configuration for SAI MCLK selection.
485 *
486 * @param base The IOMUXC GPR base address.
487 * @param mclk The SAI MCLK.
488 * @param clkSrc The clock source. Take refer to register setting details for the clock source in RM.
489 */
490static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc)
491{
492 uint32_t gpr;
493
494 if (mclk > kIOMUXC_GPR_SAI1MClk2Sel)
495 {
496 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk);
497 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr;
498 }
499 else
500 {
501 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk);
502 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr;
503 }
504}
505
506/*!
507 * @brief Enters or exit MQS software reset.
508 *
509 * @param base The IOMUXC GPR base address.
510 * @param enable Enter or exit MQS software reset.
511 */
512static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enable)
513{
514 if (enable)
515 {
516 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
517 }
518 else
519 {
520 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
521 }
522}
523
524/*!
525 * @brief Enables or disables MQS.
526 *
527 * @param base The IOMUXC GPR base address.
528 * @param enable Enable or disable the MQS.
529 */
530static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable)
531{
532 if (enable)
533 {
534 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK;
535 }
536 else
537 {
538 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK;
539 }
540}
541
542/*!
543 * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk.
544 *
545 * @param base The IOMUXC GPR base address.
546 * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t".
547 * @param divider The divider ratio control for mclk from hmclk. mclk freq = 1 /(divider + 1) * hmclk freq.
548 */
549
550static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider)
551{
552 uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK);
553 base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider);
554}
555
556/*@}*/
557
558#if defined(__cplusplus)
559}
560#endif /*_cplusplus */
561
562/*! @}*/
563
564#endif /* _FSL_IOMUXC_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_romapi.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_romapi.c
new file mode 100644
index 000000000..b8997d205
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_romapi.c
@@ -0,0 +1,170 @@
1/*
2 * Copyright 2017-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_romapi.h"
9
10/*******************************************************************************
11 * Definitions
12 ******************************************************************************/
13
14/* Component ID definition, used by tools. */
15#ifndef FSL_COMPONENT_ID
16#define FSL_COMPONENT_ID "driver.romapi"
17#endif
18
19/*******************************************************************************
20 * Prototypes
21 ******************************************************************************/
22
23/*!
24 * @brief Interface for the ROM FLEXSPI NOR flash driver.
25 */
26typedef struct
27{
28 uint32_t version;
29 status_t (*init)(uint32_t instance, flexspi_nor_config_t *config);
30 status_t (*program)(uint32_t instance, flexspi_nor_config_t *config, uint32_t dst_addr, const uint32_t *src);
31 uint32_t reserved0;
32 status_t (*erase)(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t lengthInBytes);
33 uint32_t reserved1;
34 void (*clear_cache)(uint32_t instance);
35 status_t (*xfer)(uint32_t instance, flexspi_xfer_t *xfer);
36 status_t (*update_lut)(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t seqNumber);
37 uint32_t reserved2;
38} flexspi_nor_driver_interface_t;
39
40/*!
41 * @brief Root of the bootloader api tree.
42 *
43 * An instance of this struct resides in read-only memory in the bootloader. It
44 * provides a user application access to APIs exported by the bootloader.
45 *
46 * @note The order of existing fields must not be changed.
47 */
48typedef struct
49{
50 void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing */
51 const uint32_t version; /*!< Bootloader version number */
52 const uint8_t *copyright; /*!< Bootloader Copyright */
53 const uint32_t reserved0;
54 flexspi_nor_driver_interface_t *flexSpiNorDriver; /*!< FLEXSPI NOR flash api */
55} bootloader_api_entry_t;
56
57/*******************************************************************************
58 * Variables
59 ******************************************************************************/
60
61#define g_bootloaderTree ((bootloader_api_entry_t *)*(uint32_t *)0x0020001cU)
62
63#define api_flexspi_nor_erase_sector \
64 ((status_t(*)(uint32_t instance, flexspi_nor_config_t * config, uint32_t address))0x0021055dU)
65#define api_flexspi_nor_erase_block \
66 ((status_t(*)(uint32_t instance, flexspi_nor_config_t * config, uint32_t address))0x002104a9U)
67/*******************************************************************************
68 * Codes
69 ******************************************************************************/
70
71/*******************************************************************************
72 * ROM FLEXSPI NOR driver
73 ******************************************************************************/
74#if defined(FSL_FEATURE_BOOT_ROM_HAS_ROMAPI) && FSL_FEATURE_BOOT_ROM_HAS_ROMAPI
75
76/*!
77 * @brief Initialize Serial NOR devices via FLEXSPI.
78 *
79 * @param instance storge the instance of FLEXSPI.
80 * @param config A pointer to the storage for the driver runtime state.
81 */
82status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config)
83{
84 return g_bootloaderTree->flexSpiNorDriver->init(instance, config);
85}
86
87/*!
88 * @brief Program data to Serial NOR via FLEXSPI.
89 *
90 * @param instance storge the instance of FLEXSPI.
91 * @param config A pointer to the storage for the driver runtime state.
92 * @param dstAddr A pointer to the desired flash memory to be programmed.
93 * @param src A pointer to the source buffer of data that is to be programmed
94 * into the NOR flash.
95 */
96status_t ROM_FLEXSPI_NorFlash_ProgramPage(uint32_t instance,
97 flexspi_nor_config_t *config,
98 uint32_t dstAddr,
99 const uint32_t *src)
100{
101 return g_bootloaderTree->flexSpiNorDriver->program(instance, config, dstAddr, src);
102}
103
104/*!
105 * @brief Erase Flash Region specified by address and length.
106 *
107 * @param instance storge the index of FLEXSPI.
108 * @param config A pointer to the storage for the driver runtime state.
109 * @param start The start address of the desired NOR flash memory to be erased.
110 * @param length The length, given in bytes to be erased.
111 */
112status_t ROM_FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length)
113{
114 return g_bootloaderTree->flexSpiNorDriver->erase(instance, config, start, length);
115}
116
117#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR
118/*!
119 * @brief Erase one sector specified by address.
120 *
121 * @param instance storge the index of FLEXSPI.
122 * @param config A pointer to the storage for the driver runtime state.
123 * @param start The start address of the desired NOR flash memory to be erased.
124 */
125status_t ROM_FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t start)
126{
127 return api_flexspi_nor_erase_sector(instance, config, start);
128}
129#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR */
130
131#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK
132/*!
133 * @brief Erase one block specified by address.
134 *
135 * @param instance storge the index of FLEXSPI.
136 * @param config A pointer to the storage for the driver runtime state.
137 * @param start The start address of the desired NOR flash memory to be erased.
138 */
139status_t ROM_FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t start)
140{
141 return api_flexspi_nor_erase_block(instance, config, start);
142}
143#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK */
144
145#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER
146/*! @brief FLEXSPI command */
147status_t ROM_FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer)
148{
149 return g_bootloaderTree->flexSpiNorDriver->xfer(instance, xfer);
150}
151#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER */
152
153#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT
154/*! @brief Configure FLEXSPI Lookup table. */
155status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance,
156 uint32_t seqIndex,
157 const uint32_t *lutBase,
158 uint32_t seqNumber)
159{
160 return g_bootloaderTree->flexSpiNorDriver->update_lut(instance, seqIndex, lutBase, seqNumber);
161}
162#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT */
163
164/*! @brief Software reset for the FLEXSPI logic. */
165void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance)
166{
167 g_bootloaderTree->flexSpiNorDriver->clear_cache(instance);
168}
169
170#endif /* FSL_FEATURE_BOOT_ROM_HAS_ROMAPI */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_romapi.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_romapi.h
new file mode 100644
index 000000000..75650b626
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_romapi.h
@@ -0,0 +1,554 @@
1/*
2 * Copyright 2017-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_ROMAPI_H_
9#define _FSL_ROMAPI_H_
10
11#include "fsl_common.h"
12
13/*!
14 * @addtogroup romapi
15 * @{
16 */
17
18/*! @brief ROMAPI version 1.1.0. */
19#define FSL_ROM_ROMAPI_VERSION (MAKE_VERSION(1U, 1U, 0U))
20/*! @brief ROM FLEXSPI NOR driver version 1.4.0. */
21#define FSL_ROM_FLEXSPINOR_DRIVER_VERSION (MAKE_VERSION(1U, 4U, 0U))
22
23/*!
24 * @name Common ROMAPI fearures info defines
25 * @{
26 */
27/* @brief ROM has FLEXSPI NOR API. */
28#define FSL_ROM_HAS_FLEXSPINOR_API (1)
29/* @brief ROM has run bootloader API. */
30#define FSL_ROM_HAS_RUNBOOTLOADER_API (0)
31/* @brief ROM has FLEXSPI NOR get config API. */
32#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_GET_CONFIG (0)
33/* @brief ROM has flash init API. */
34#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_FLASH_INIT (1)
35/* @brief ROM has erase API. */
36#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE (1)
37/* @brief ROM has erase sector API. */
38#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR (1)
39/* @brief ROM has erase block API. */
40#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK (1)
41/* @brief ROM has erase all API. */
42#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL (0)
43/* @brief ROM has page program API. */
44#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_PAGE_PROGRAM (1)
45/* @brief ROM has update lut API. */
46#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT (1)
47/* @brief ROM has FLEXSPI command API. */
48#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER (1)
49
50/*@}*/
51
52#define kROM_StatusGroup_FLEXSPI 60U /*!< ROM FLEXSPI status group number.*/
53#define kROM_StatusGroup_FLEXSPINOR 200U /*!< ROM FLEXSPI NOR status group number.*/
54
55#define FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
56 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
57 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
58
59/*! @brief Generate bit mask */
60#define FSL_ROM_FLEXSPI_BITMASK(bit_offset) (1U << (bit_offset))
61
62/*! @brief FLEXSPI memory config block related defintions */
63#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) /*!< ascii "FCFB" Big Endian */
64#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) /*!< V1.4.0 */
65
66#define CMD_SDR 0x01U
67#define CMD_DDR 0x21U
68#define RADDR_SDR 0x02U
69#define RADDR_DDR 0x22U
70#define CADDR_SDR 0x03U
71#define CADDR_DDR 0x23U
72#define MODE1_SDR 0x04U
73#define MODE1_DDR 0x24U
74#define MODE2_SDR 0x05U
75#define MODE2_DDR 0x25U
76#define MODE4_SDR 0x06U
77#define MODE4_DDR 0x26U
78#define MODE8_SDR 0x07U
79#define MODE8_DDR 0x27U
80#define WRITE_SDR 0x08U
81#define WRITE_DDR 0x28U
82#define READ_SDR 0x09U
83#define READ_DDR 0x29U
84#define LEARN_SDR 0x0AU
85#define LEARN_DDR 0x2AU
86#define DATSZ_SDR 0x0BU
87#define DATSZ_DDR 0x2BU
88#define DUMMY_SDR 0x0CU
89#define DUMMY_DDR 0x2CU
90#define DUMMY_RWDS_SDR 0x0DU
91#define DUMMY_RWDS_DDR 0x2DU
92#define JMP_ON_CS 0x1FU
93#define STOP 0U
94
95#define FLEXSPI_1PAD 0U
96#define FLEXSPI_2PAD 1U
97#define FLEXSPI_4PAD 2U
98#define FLEXSPI_8PAD 3U
99
100/*!
101 * NOR LUT sequence index used for default LUT assignment
102 * NOTE:
103 * The will take effect if the lut sequences are not customized.
104 */
105#define NOR_CMD_LUT_SEQ_IDX_READ 0U /*!< READ LUT sequence id in lookupTable stored in config block */
106#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1U /*!< Read Status LUT sequence id in lookupTable stored in config block */
107#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
108 2U /*!< Read status DPI/QPI/OPI sequence id in lookupTable stored in config block */
109#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3U /*!< Write Enable sequence id in lookupTable stored in config block */
110#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
111 4U /*!< Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block */
112#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5U /*!< Erase Sector sequence id in lookupTable stored in config block */
113#define NOR_CMD_LUT_SEQ_IDX_READID 7U
114#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8U /*!< Erase Block sequence id in lookupTable stored in config block */
115#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9U /*!< Program sequence id in lookupTable stored in config block */
116#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11U /*!< Chip Erase sequence in lookupTable id stored in config block */
117#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13U /*!< Read SFDP sequence in lookupTable id stored in config block */
118#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
119 14U /*!< Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block */
120#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
121 15U /*!< Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk */
122
123/*!
124 * @name Support for init FLEXSPI NOR configuration
125 * @{
126 */
127/*! @brief Flash Pad Definitions */
128enum
129{
130 kSerialFlash_1Pad = 1U,
131 kSerialFlash_2Pads = 2U,
132 kSerialFlash_4Pads = 4U,
133 kSerialFlash_8Pads = 8U,
134};
135
136/*! @brief FLEXSPI clock configuration type */
137enum
138{
139 kFLEXSPIClk_SDR, /*!< Clock configure for SDR mode */
140 kFLEXSPIClk_DDR, /*!< Clock configurat for DDR mode */
141};
142
143/*! @brief FLEXSPI Read Sample Clock Source definition */
144typedef enum _flexspi_read_sample_clk
145{
146 kFLEXSPIReadSampleClk_LoopbackInternally = 0U,
147 kFLEXSPIReadSampleClk_LoopbackFromDqsPad = 1U,
148 kFLEXSPIReadSampleClk_LoopbackFromSckPad = 2U,
149 kFLEXSPIReadSampleClk_ExternalInputFromDqsPad = 3U,
150} flexspi_read_sample_clk_t;
151
152/*! @brief Flash Type Definition */
153enum
154{
155 kFLEXSPIDeviceType_SerialNOR = 1U, /*!< Flash device is Serial NOR */
156};
157
158/*! @brief Flash Configuration Command Type */
159enum
160{
161 kDeviceConfigCmdType_Generic, /*!< Generic command, for example: configure dummy cycles, drive strength, etc */
162 kDeviceConfigCmdType_QuadEnable, /*!< Quad Enable command */
163 kDeviceConfigCmdType_Spi2Xpi, /*!< Switch from SPI to DPI/QPI/OPI mode */
164 kDeviceConfigCmdType_Xpi2Spi, /*!< Switch from DPI/QPI/OPI to SPI mode */
165 kDeviceConfigCmdType_Spi2NoCmd, /*!< Switch to 0-4-4/0-8-8 mode */
166 kDeviceConfigCmdType_Reset, /*!< Reset device command */
167};
168
169/*! @brief Defintions for FLEXSPI Serial Clock Frequency */
170typedef enum _flexspi_serial_clk_freq
171{
172 kFLEXSPISerialClk_NoChange = 0U,
173 kFLEXSPISerialClk_30MHz = 1U,
174 kFLEXSPISerialClk_50MHz = 2U,
175 kFLEXSPISerialClk_60MHz = 3U,
176 kFLEXSPISerialClk_75MHz = 4U,
177 kFLEXSPISerialClk_80MHz = 5U,
178 kFLEXSPISerialClk_100MHz = 6U,
179 kFLEXSPISerialClk_133MHz = 7U,
180 kFLEXSPISerialClk_166MHz = 8U,
181 kFLEXSPISerialClk_200MHz = 9U,
182} flexspi_serial_clk_freq_t;
183
184/*! @brief Misc feature bit definitions */
185enum
186{
187 kFLEXSPIMiscOffset_DiffClkEnable = 0U, /*!< Bit for Differential clock enable */
188 kFLEXSPIMiscOffset_Ck2Enable = 1U, /*!< Bit for CK2 enable */
189 kFLEXSPIMiscOffset_ParallelEnable = 2U, /*!< Bit for Parallel mode enable */
190 kFLEXSPIMiscOffset_WordAddressableEnable = 3U, /*!< Bit for Word Addressable enable */
191 kFLEXSPIMiscOffset_SafeConfigFreqEnable = 4U, /*!< Bit for Safe Configuration Frequency enable */
192 kFLEXSPIMiscOffset_PadSettingOverrideEnable = 5U, /*!< Bit for Pad setting override enable */
193 kFLEXSPIMiscOffset_DdrModeEnable = 6U, /*!< Bit for DDR clock confiuration indication. */
194 kFLEXSPIMiscOffset_UseValidTimeForAllFreq = 7U, /*!< Bit for DLLCR settings under all modes */
195};
196
197/*@}*/
198
199/*!
200 * @name FLEXSPI NOR Configuration
201 * @{
202 */
203
204/*! @brief FLEXSPI LUT Sequence structure */
205typedef struct _flexspi_lut_seq
206{
207 uint8_t seqNum; /*!< Sequence Number, valid number: 1-16 */
208 uint8_t seqId; /*!< Sequence Index, valid number: 0-15 */
209 uint16_t reserved;
210} flexspi_lut_seq_t;
211
212typedef struct
213{
214 uint8_t time_100ps; /*!< Data valid time, in terms of 100ps */
215 uint8_t delay_cells; /*!< Data valid time, in terms of delay cells */
216} flexspi_dll_time_t;
217
218/*! @brief FLEXSPI Memory Configuration Block */
219typedef struct _flexspi_mem_config
220{
221 uint32_t tag; /*!< [0x000-0x003] Tag, fixed value 0x42464346UL */
222 uint32_t version; /*!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */
223 uint32_t reserved0; /*!< [0x008-0x00b] Reserved for future use */
224 uint8_t readSampleClkSrc; /*!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */
225 uint8_t csHoldTime; /*!< [0x00d-0x00d] Data hold time, default value: 3 */
226 uint8_t csSetupTime; /*!< [0x00e-0x00e] Date setup time, default value: 3 */
227 uint8_t columnAddressWidth; /*!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
228 Serial NAND, need to refer to datasheet */
229 uint8_t deviceModeCfgEnable; /*!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */
230 uint8_t deviceModeType; /*!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
231 Generic configuration, etc. */
232 uint16_t waitTimeCfgCommands; /*!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
233 DPI/QPI/OPI switch or reset command */
234 flexspi_lut_seq_t deviceModeSeq; /*!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
235 sequence number, [31:16] Reserved */
236 uint32_t deviceModeArg; /*!< [0x018-0x01b] Argument/Parameter for device configuration */
237 uint8_t configCmdEnable; /*!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */
238 uint8_t configModeType[3]; /*!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */
239 flexspi_lut_seq_t
240 configCmdSeqs[3]; /*!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq */
241 uint32_t reserved1; /*!< [0x02c-0x02f] Reserved for future use */
242 uint32_t configCmdArgs[3]; /*!< [0x030-0x03b] Arguments/Parameters for device Configuration commands */
243 uint32_t reserved2; /*!< [0x03c-0x03f] Reserved for future use */
244 uint32_t controllerMiscOption; /*!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
245 details */
246 uint8_t deviceType; /*!< [0x044-0x044] Device Type: See Flash Type Definition for more details */
247 uint8_t sflashPadType; /*!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */
248 uint8_t serialClkFreq; /*!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
249 Chapter for more details */
250 uint8_t
251 lutCustomSeqEnable; /*!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
252 be done using 1 LUT sequence, currently, only applicable to HyperFLASH */
253 uint32_t reserved3[2]; /*!< [0x048-0x04f] Reserved for future use */
254 uint32_t sflashA1Size; /*!< [0x050-0x053] Size of Flash connected to A1 */
255 uint32_t sflashA2Size; /*!< [0x054-0x057] Size of Flash connected to A2 */
256 uint32_t sflashB1Size; /*!< [0x058-0x05b] Size of Flash connected to B1 */
257 uint32_t sflashB2Size; /*!< [0x05c-0x05f] Size of Flash connected to B2 */
258 uint32_t csPadSettingOverride; /*!< [0x060-0x063] CS pad setting override value */
259 uint32_t sclkPadSettingOverride; /*!< [0x064-0x067] SCK pad setting override value */
260 uint32_t dataPadSettingOverride; /*!< [0x068-0x06b] data pad setting override value */
261 uint32_t dqsPadSettingOverride; /*!< [0x06c-0x06f] DQS pad setting override value */
262 uint32_t timeoutInMs; /*!< [0x070-0x073] Timeout threshold for read status command */
263 uint32_t commandInterval; /*!< [0x074-0x077] CS deselect interval between two commands */
264 flexspi_dll_time_t dataValidTime[2]; /*!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B */
265 uint16_t busyOffset; /*!< [0x07c-0x07d] Busy offset, valid value: 0-31 */
266 uint16_t busyBitPolarity; /*!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
267 busy flag is 0 when flash device is busy */
268 uint32_t lookupTable[64]; /*!< [0x080-0x17f] Lookup table holds Flash command sequences */
269 flexspi_lut_seq_t lutCustomSeq[12]; /*!< [0x180-0x1af] Customizable LUT Sequences */
270 uint32_t reserved4[4]; /*!< [0x1b0-0x1bf] Reserved for future use */
271} flexspi_mem_config_t;
272
273/*! @brief Serial NOR configuration block */
274typedef struct _flexspi_nor_config
275{
276 flexspi_mem_config_t memConfig; /*!< Common memory configuration info via FLEXSPI */
277 uint32_t pageSize; /*!< Page size of Serial NOR */
278 uint32_t sectorSize; /*!< Sector size of Serial NOR */
279 uint8_t ipcmdSerialClkFreq; /*!< Clock frequency for IP command */
280 uint8_t isUniformBlockSize; /*!< Sector/Block size is the same */
281 uint8_t isDataOrderSwapped; /*!< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */
282 uint8_t reserved0[1]; /*!< Reserved for future use */
283 uint8_t serialNorType; /*!< Serial NOR Flash type: 0/1/2/3 */
284 uint8_t needExitNoCmdMode; /*!< Need to exit NoCmd mode before other IP command */
285 uint8_t halfClkForNonReadCmd; /*!< Half the Serial Clock for non-read command: true/false */
286 uint8_t needRestoreNoCmdMode; /*!< Need to Restore NoCmd mode after IP commmand execution */
287 uint32_t blockSize; /*!< Block size */
288 uint32_t reserve2[11]; /*!< Reserved for future use */
289} flexspi_nor_config_t;
290
291/*@}*/
292
293/*! @brief Manufacturer ID */
294enum
295{
296 kSerialFlash_ISSI_ManufacturerID = 0x9DU, /*!< Manufacturer ID of the ISSI serial flash */
297 kSerialFlash_Adesto_ManufacturerID = 0x1F, /*!< Manufacturer ID of the Adesto Technologies serial flash*/
298 kSerialFlash_Winbond_ManufacturerID = 0xEFU, /*!< Manufacturer ID of the Winbond serial flash */
299 kSerialFlash_Cypress_ManufacturerID = 0x01U, /*!< Manufacturer ID for Cypress */
300};
301
302/*! @brief ROM FLEXSPI NOR flash status */
303enum _flexspi_nor_status
304{
305 kStatus_ROM_FLEXSPI_SequenceExecutionTimeout =
306 MAKE_STATUS(kROM_StatusGroup_FLEXSPI, 0), /*!< Status for Sequence Execution timeout */
307 kStatus_ROM_FLEXSPI_InvalidSequence = MAKE_STATUS(kROM_StatusGroup_FLEXSPI, 1), /*!< Status for Invalid Sequence */
308 kStatus_ROM_FLEXSPI_DeviceTimeout = MAKE_STATUS(kROM_StatusGroup_FLEXSPI, 2), /*!< Status for Device timeout */
309 kStatus_FLEXSPINOR_DTRRead_DummyProbeFailed =
310 MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 10), /*!< Status for DDR Read dummy probe failure */
311 kStatus_ROM_FLEXSPINOR_SFDP_NotFound =
312 MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 7), /*!< Status for SFDP read failure */
313 kStatus_ROM_FLEXSPINOR_Flash_NotFound =
314 MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 9), /*!< Status for Flash detection failure */
315};
316
317typedef enum _flexspi_operation
318{
319 kFLEXSPIOperation_Command, /*!< FLEXSPI operation: Only command, both TX and RX buffer are ignored. */
320 kFLEXSPIOperation_Config, /*!< FLEXSPI operation: Configure device mode, the TX FIFO size is fixed in LUT. */
321 kFLEXSPIOperation_Write, /*!< FLEXSPI operation: Write, only TX buffer is effective */
322 kFLEXSPIOperation_Read, /*!< FLEXSPI operation: Read, only Rx Buffer is effective. */
323 kFLEXSPIOperation_End = kFLEXSPIOperation_Read,
324} flexspi_operation_t;
325
326/*! @brief FLEXSPI Transfer Context */
327typedef struct _flexspi_xfer
328{
329 flexspi_operation_t operation; /*!< FLEXSPI operation */
330 uint32_t baseAddress; /*!< FLEXSPI operation base address */
331 uint32_t seqId; /*!< Sequence Id */
332 uint32_t seqNum; /*!< Sequence Number */
333 bool isParallelModeEnable; /*!< Is a parallel transfer */
334 uint32_t *txBuffer; /*!< Tx buffer */
335 uint32_t txSize; /*!< Tx size in bytes */
336 uint32_t *rxBuffer; /*!< Rx buffer */
337 uint32_t rxSize; /*!< Rx size in bytes */
338} flexspi_xfer_t;
339
340#ifdef __cplusplus
341extern "C" {
342#endif
343
344#if defined(FSL_FEATURE_BOOT_ROM_HAS_ROMAPI) && FSL_FEATURE_BOOT_ROM_HAS_ROMAPI
345
346/*!
347 * @name Initialization
348 * @{
349 */
350
351/*!
352 * @brief Initialize Serial NOR devices via FLEXSPI
353 *
354 * This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs.
355 *
356 * @param instance storge the instance of FLEXSPI.
357 * @param config A pointer to the storage for the driver runtime state.
358 *
359 * @retval kStatus_Success Api was executed succesfuly.
360 * @retval kStatus_InvalidArgument A invalid argument is provided.
361 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
362 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
363 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
364 */
365status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config);
366
367/*@}*/
368
369/*!
370 * @name Programming
371 * @{
372 */
373/*!
374 * @brief Program data to Serial NOR via FLEXSPI.
375 *
376 * This function programs the NOR flash memory with the dest address for a given
377 * flash area as determined by the dst address and the length.
378 *
379 * @param instance storge the instance of FLEXSPI.
380 * @param config A pointer to the storage for the driver runtime state.
381 * @param dstAddr A pointer to the desired flash memory to be programmed.
382 * NOTE:
383 * It is recommended that use page aligned access;
384 * If the dstAddr is not aligned to page,the driver automatically
385 * aligns address down with the page address.
386 * @param src A pointer to the source buffer of data that is to be programmed
387 * into the NOR flash.
388 *
389 * @retval kStatus_Success Api was executed succesfuly.
390 * @retval kStatus_InvalidArgument A invalid argument is provided.
391 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
392 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
393 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
394 */
395status_t ROM_FLEXSPI_NorFlash_ProgramPage(uint32_t instance,
396 flexspi_nor_config_t *config,
397 uint32_t dstAddr,
398 const uint32_t *src);
399
400/*@}*/
401
402/*!
403 * @name Erasing
404 * @{
405 */
406#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR
407/*!
408 * @brief Erase one sector specified by address
409 *
410 * This function erases one of NOR flash sectors based on the desired address.
411 *
412 * @param instance storge the index of FLEXSPI.
413 * @param config A pointer to the storage for the driver runtime state.
414 * @param address The start address of the desired NOR flash memory to be erased.
415 * NOTE:
416 * It is recommended that use sector-aligned access nor device;
417 * If dstAddr is not aligned with the sector,The driver automatically
418 * aligns address down with the sector address.
419 *
420 * @retval kStatus_Success Api was executed succesfuly.
421 * @retval kStatus_InvalidArgument A invalid argument is provided.
422 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
423 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
424 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
425 */
426status_t ROM_FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address);
427#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR */
428
429#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK
430/*!
431 * @brief Erase one block specified by address
432 *
433 * This function erases one block of NOR flash based on the desired address.
434 *
435 * @param instance storge the index of FLEXSPI.
436 * @param config A pointer to the storage for the driver runtime state.
437 * @param start The start address of the desired NOR flash memory to be erased.
438 * NOTE:
439 * It is recommended that use block-aligned access nor device;
440 * If dstAddr is not aligned with the block,The driver automatically
441 * aligns address down with the block address.
442 *
443 * @retval kStatus_Success Api was executed succesfuly.
444 * @retval kStatus_InvalidArgument A invalid argument is provided.
445 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
446 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
447 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
448 */
449status_t ROM_FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t start);
450#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK */
451
452/*!
453 * @brief Erase Flash Region specified by address and length
454 *
455 * This function erases the appropriate number of flash sectors based on the
456 * desired start address and length.
457 *
458 * @param instance storge the index of FLEXSPI.
459 * @param config A pointer to the storage for the driver runtime state.
460 * @param start The start address of the desired NOR flash memory to be erased.
461 * NOTE:
462 * It is recommended that use sector-aligned access nor device;
463 * If dstAddr is not aligned with the sector,the driver automatically
464 * aligns address down with the sector address.
465 * @param length The length, given in bytes to be erased.
466 * NOTE:
467 * It is recommended that use sector-aligned access nor device;
468 * If length is not aligned with the sector,the driver automatically
469 * aligns up with the sector.
470 * @retval kStatus_Success Api was executed succesfuly.
471 * @retval kStatus_InvalidArgument A invalid argument is provided.
472 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
473 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
474 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
475 */
476status_t ROM_FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length);
477
478/*@}*/
479
480/*!
481 * @name Command
482 * @{
483 */
484
485#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER
486/*!
487 * @brief FLEXSPI command
488 *
489 * This function is used to perform the command write sequence to the NOR device.
490 *
491 * @param instance storge the index of FLEXSPI.
492 * @param xfer A pointer to the storage FLEXSPI Transfer Context.
493 *
494 * @retval kStatus_Success Api was executed succesfuly.
495 * @retval kStatus_InvalidArgument A invalid argument is provided.
496 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
497 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
498 */
499status_t ROM_FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer);
500#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER */
501/*@}*/
502
503/*!
504 * @name UpdateLut
505 * @{
506 */
507#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT
508/*!
509 * @brief Configure FLEXSPI Lookup table
510 *
511 * @param instance storge the index of FLEXSPI.
512 * @param seqIndex storge the sequence Id.
513 * @param lutBase A pointer to the look-up-table for command sequences.
514 * @param seqNumber storge sequence number.
515 *
516 * @retval kStatus_Success Api was executed succesfuly.
517 * @retval kStatus_InvalidArgument A invalid argument is provided.
518 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
519 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
520 */
521status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance,
522 uint32_t seqIndex,
523 const uint32_t *lutBase,
524 uint32_t seqNumber);
525#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT */
526
527/*@}*/
528
529/*!
530 * @name ClearCache
531 * @{
532 */
533
534/*!
535 * @brief Software reset for the FLEXSPI logic.
536 *
537 * This function sets the software reset flags for both AHB and buffer domain and
538 * resets both AHB buffer and also IP FIFOs.
539 *
540 * @param instance storge the index of FLEXSPI.
541 */
542void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance);
543
544/*@}*/
545
546#endif /* FSL_FEATURE_BOOT_ROM_HAS_ROMAPI */
547
548#ifdef __cplusplus
549}
550#endif
551
552/*! @}*/
553
554#endif /* _FSL_ROMAPI_H_ */
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