aboutsummaryrefslogtreecommitdiff
path: root/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_clock.h
diff options
context:
space:
mode:
Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_clock.h')
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_clock.h1431
1 files changed, 1431 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_clock.h
new file mode 100644
index 000000000..90de181f2
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/drivers/fsl_clock.h
@@ -0,0 +1,1431 @@
1/*
2 * Copyright 2018-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_common.h"
12
13/*! @addtogroup clock */
14/*! @{ */
15
16/*! @file */
17
18/*******************************************************************************
19 * Configurations
20 ******************************************************************************/
21
22/*! @brief Configure whether driver controls clock
23 *
24 * When set to 0, peripheral drivers will enable clock in initialize function
25 * and disable clock in de-initialize function. When set to 1, peripheral
26 * driver will not control the clock, application could control the clock out of
27 * the driver.
28 *
29 * @note All drivers share this feature switcher. If it is set to 1, application
30 * should handle clock enable and disable for all drivers.
31 */
32#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
33#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
34#endif
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*! @name Driver version */
41/*@{*/
42/*! @brief CLOCK driver version 2.4.0. */
43#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
44
45/* analog pll definition */
46#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
47#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
48#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
49
50/* Definition for delay API in clock driver, users can redefine it to the real application. */
51#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
52#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (500000000UL)
53#endif
54
55/*@}*/
56
57/*!
58 * @brief CCM registers offset.
59 */
60#define CCSR_OFFSET 0x0C
61#define CBCDR_OFFSET 0x14
62#define CBCMR_OFFSET 0x18
63#define CSCMR1_OFFSET 0x1C
64#define CSCMR2_OFFSET 0x20
65#define CSCDR1_OFFSET 0x24
66#define CDCDR_OFFSET 0x30
67#define CSCDR2_OFFSET 0x38
68#define CACRR_OFFSET 0x10
69#define CS1CDR_OFFSET 0x28
70#define CS2CDR_OFFSET 0x2C
71
72/*!
73 * @brief CCM Analog registers offset.
74 */
75#define PLL_SYS_OFFSET 0x30
76#define PLL_USB1_OFFSET 0x10
77#define PLL_AUDIO_OFFSET 0x70
78#define PLL_ENET_OFFSET 0xE0
79
80#define CCM_TUPLE(reg, shift, mask, busyShift) \
81 (int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
82#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + (((uint32_t)tuple) & 0xFFU))))
83#define CCM_TUPLE_SHIFT(tuple) ((((uint32_t)tuple) >> 8U) & 0x1FU)
84#define CCM_TUPLE_MASK(tuple) \
85 ((uint32_t)(((((uint32_t)tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))
86#define CCM_TUPLE_BUSY_SHIFT(tuple) ((((uint32_t)tuple) >> 26U) & 0x3FU)
87
88#define CCM_NO_BUSY_WAIT (0x20U)
89
90/*!
91 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
92 */
93#define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFU) << 16U) | (shift))
94#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)(tuple)) & 0x1FU)
95#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
96 (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))
97#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
98
99#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
100#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
101#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
102
103/*!
104 * @brief clock1PN frequency.
105 */
106#define CLKPN_FREQ 0U
107
108/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency.
109 *
110 * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the
111 * function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
112 * if XTAL is 24MHz,
113 * @code
114 * CLOCK_InitExternalClk(false);
115 * CLOCK_SetXtalFreq(240000000);
116 * @endcode
117 */
118extern volatile uint32_t g_xtalFreq;
119
120/*! @brief External RTC XTAL (32K OSC) clock frequency.
121 *
122 * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the
123 * function CLOCK_SetRtcXtalFreq to set the value in to clock driver.
124 */
125extern volatile uint32_t g_rtcXtalFreq;
126
127/* For compatible with other platforms */
128#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq
129#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq
130
131/*! @brief Clock ip name array for ADC. */
132#define ADC_CLOCKS \
133 { \
134 kCLOCK_IpInvalid, kCLOCK_Adc1 \
135 }
136
137/*! @brief Clock ip name array for AOI. */
138#define AOI_CLOCKS \
139 { \
140 kCLOCK_Aoi \
141 }
142
143/*! @brief Clock ip name array for BEE. */
144#define BEE_CLOCKS \
145 { \
146 kCLOCK_Bee \
147 }
148
149/*! @brief Clock ip name array for DCDC. */
150#define DCDC_CLOCKS \
151 { \
152 kCLOCK_Dcdc \
153 }
154
155/*! @brief Clock ip name array for DCP. */
156#define DCP_CLOCKS \
157 { \
158 kCLOCK_Dcp \
159 }
160
161/*! @brief Clock ip name array for DMAMUX_CLOCKS. */
162#define DMAMUX_CLOCKS \
163 { \
164 kCLOCK_Dma \
165 }
166
167/*! @brief Clock ip name array for DMA. */
168#define EDMA_CLOCKS \
169 { \
170 kCLOCK_Dma \
171 }
172
173/*! @brief Clock ip name array for ENC. */
174#define ENC_CLOCKS \
175 { \
176 kCLOCK_IpInvalid, kCLOCK_Enc1 \
177 }
178
179/*! @brief Clock ip name array for EWM. */
180#define EWM_CLOCKS \
181 { \
182 kCLOCK_Ewm0 \
183 }
184
185/*! @brief Clock ip name array for FLEXIO. */
186#define FLEXIO_CLOCKS \
187 { \
188 kCLOCK_IpInvalid, kCLOCK_Flexio1 \
189 }
190
191/*! @brief Clock ip name array for FLEXRAM. */
192#define FLEXRAM_CLOCKS \
193 { \
194 kCLOCK_FlexRam \
195 }
196
197/*! @brief Clock ip name array for FLEXSPI. */
198#define FLEXSPI_CLOCKS \
199 { \
200 kCLOCK_FlexSpi \
201 }
202
203/*! @brief Clock ip name array for GPIO. */
204#define GPIO_CLOCKS \
205 { \
206 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_IpInvalid, kCLOCK_Gpio5 \
207 }
208
209/*! @brief Clock ip name array for GPT. */
210#define GPT_CLOCKS \
211 { \
212 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
213 }
214
215/*! @brief Clock ip name array for KPP. */
216#define KPP_CLOCKS \
217 { \
218 kCLOCK_Kpp \
219 }
220
221/*! @brief Clock ip name array for LPI2C. */
222#define LPI2C_CLOCKS \
223 { \
224 kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2 \
225 }
226
227/*! @brief Clock ip name array for LPSPI. */
228#define LPSPI_CLOCKS \
229 { \
230 kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2 \
231 }
232
233/*! @brief Clock ip name array for LPUART. */
234#define LPUART_CLOCKS \
235 { \
236 kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4 \
237 }
238
239/*! @brief Clock ip name array for OCRAM EXSC. */
240#define OCRAM_EXSC_CLOCKS \
241 { \
242 kCLOCK_OcramExsc \
243 }
244
245/*! @brief Clock ip name array for PIT. */
246#define PIT_CLOCKS \
247 { \
248 kCLOCK_Pit \
249 }
250
251/*! @brief Clock ip name array for PWM. */
252#define PWM_CLOCKS \
253 { \
254 {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
255 { \
256 kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1 \
257 } \
258 }
259
260/*! @brief Clock ip name array for RTWDOG. */
261#define RTWDOG_CLOCKS \
262 { \
263 kCLOCK_Wdog3 \
264 }
265
266/*! @brief Clock ip name array for SAI. */
267#define SAI_CLOCKS \
268 { \
269 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \
270 }
271
272/*! @brief Clock ip name array for QTIMER. */
273#define TMR_CLOCKS \
274 { \
275 kCLOCK_IpInvalid, kCLOCK_Timer1 \
276 }
277
278/*! @brief Clock ip name array for TRNG. */
279#define TRNG_CLOCKS \
280 { \
281 kCLOCK_Trng \
282 }
283
284/*! @brief Clock ip name array for WDOG. */
285#define WDOG_CLOCKS \
286 { \
287 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \
288 }
289
290/*! @brief Clock ip name array for SPDIF. */
291#define SPDIF_CLOCKS \
292 { \
293 kCLOCK_Spdif \
294 }
295
296/*! @brief Clock ip name array for XBARA. */
297#define XBARA_CLOCKS \
298 { \
299 kCLOCK_Xbar1 \
300 }
301
302/*! @brief Clock ip name array for XBARB. */
303#define XBARB_CLOCKS \
304 { \
305 kCLOCK_Xbar2 \
306 }
307
308#define CLOCK_SOURCE_NONE (0xFFU)
309
310#define CLOCK_ROOT_SOUCE \
311 { \
312 {kCLOCK_SemcClk, kCLOCK_Usb1SwClk, kCLOCK_SysPllPfd2Clk, kCLOCK_Usb1PllPfd0Clk}, /*!< FLEXSPI clock root */ \
313 {kCLOCK_Usb1PllPfd1Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_SysPllClk, \
314 kCLOCK_SysPllPfd2Clk}, /*!< LPSPI clock root. */ \
315 {kCLOCK_SysPllClk, kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, \
316 kCLOCK_SysPllPfd1Clk}, /*!< Trace clock root. */ \
317 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, kCLOCK_AudioPllClk, kCLOCK_NoneName}, /*!< SAI1 clock root. */ \
318 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, kCLOCK_AudioPllClk, kCLOCK_NoneName}, /*!< SAI2 clock root. */ \
319 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, kCLOCK_AudioPllClk, kCLOCK_NoneName}, /*!< SAI3 clock root. */ \
320 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_NoneName, kCLOCK_NoneName}, /*!< LPI2C clock root. */ \
321 {kCLOCK_Usb1Sw80MClk, kCLOCK_OscClk, kCLOCK_NoneName, kCLOCK_NoneName}, /*!< UART clock root. */ \
322 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, kCLOCK_Usb1SwClk}, /*!< SPDIF clock root. */ \
323 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, \
324 kCLOCK_Usb1SwClk}, /*!< FLEXIO1 clock root. */ \
325 }
326
327#define CLOCK_ROOT_MUX_TUPLE \
328 { \
329 kCLOCK_FlexspiMux, kCLOCK_LpspiMux, kCLOCK_TraceMux, kCLOCK_Sai1Mux, kCLOCK_Sai2Mux, kCLOCK_Sai3Mux, \
330 kCLOCK_Lpi2cMux, kCLOCK_UartMux, kCLOCK_SpdifMux, kCLOCK_Flexio1Mux, \
331 }
332
333#define CLOCK_ROOT_NONE_PRE_DIV 0UL
334
335#define CLOCK_ROOT_DIV_TUPLE \
336 { \
337 {kCLOCK_NonePreDiv, kCLOCK_FlexspiDiv}, /*!< FLEXSPI clock root */ \
338 {kCLOCK_NonePreDiv, kCLOCK_LpspiDiv}, /*!< LPSPI clock root. */ \
339 {kCLOCK_NonePreDiv, kCLOCK_TraceDiv}, /*!< Trace clock root. */ \
340 {kCLOCK_Sai1PreDiv, kCLOCK_Sai1Div}, /*!< SAI1 clock root. */ \
341 {kCLOCK_Sai2PreDiv, kCLOCK_Sai2Div}, /*!< SAI2 clock root. */ \
342 {kCLOCK_Sai3PreDiv, kCLOCK_Sai3Div}, /*!< SAI3 clock root. */ \
343 {kCLOCK_NonePreDiv, kCLOCK_Lpi2cDiv}, /*!< LPI2C clock root. */ \
344 {kCLOCK_NonePreDiv, kCLOCK_UartDiv}, /*!< UART clock root. */ \
345 {kCLOCK_Spdif0PreDiv, kCLOCK_Spdif0Div}, /*!< SPDIF clock root. */ \
346 {kCLOCK_Flexio1PreDiv, kCLOCK_Flexio1Div}, /*!< FLEXIO1 clock root. */ \
347 }
348
349/*! @brief Clock name used to get clock frequency. */
350typedef enum _clock_name
351{
352 kCLOCK_CpuClk = 0x0U, /*!< CPU clock */
353 kCLOCK_AhbClk = 0x1U, /*!< AHB clock */
354 kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */
355 kCLOCK_IpgClk = 0x3U, /*!< IPG clock */
356 kCLOCK_PerClk = 0x4U, /*!< PER clock */
357
358 kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */
359 kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */
360
361 kCLOCK_Usb1PllClk = 0x7U, /*!< USB1PLLCLK. */
362 kCLOCK_Usb1PllPfd0Clk = 0x8U, /*!< USB1PLLPDF0CLK. */
363 kCLOCK_Usb1PllPfd1Clk = 0x9U, /*!< USB1PLLPFD1CLK. */
364 kCLOCK_Usb1PllPfd2Clk = 0xAU, /*!< USB1PLLPFD2CLK. */
365 kCLOCK_Usb1PllPfd3Clk = 0xBU, /*!< USB1PLLPFD3CLK. */
366 kCLOCK_Usb1SwClk = 0x15U, /*!< USB1PLLSWCLK */
367 kCLOCK_Usb1Sw60MClk = 0x16U, /*!< USB1PLLSw60MCLK */
368 kCLOCK_Usb1Sw80MClk = 0x1BU, /*!< USB1PLLSw80MCLK */
369
370 kCLOCK_SysPllClk = 0xCU, /*!< SYSPLLCLK. */
371 kCLOCK_SysPllPfd0Clk = 0xDU, /*!< SYSPLLPDF0CLK. */
372 kCLOCK_SysPllPfd1Clk = 0xEU, /*!< SYSPLLPFD1CLK. */
373 kCLOCK_SysPllPfd2Clk = 0xFU, /*!< SYSPLLPFD2CLK. */
374 kCLOCK_SysPllPfd3Clk = 0x10U, /*!< SYSPLLPFD3CLK. */
375
376 kCLOCK_EnetPllClk = 0x11U, /*!< Enet PLLCLK ref_enetpll. */
377 kCLOCK_EnetPll25MClk = 0x12U, /*!< Enet PLLCLK ref_enetpll25M. */
378 kCLOCK_EnetPll500MClk = 0x13U, /*!< Enet PLLCLK ref_enetpll500M. */
379
380 kCLOCK_AudioPllClk = 0x14U, /*!< Audio PLLCLK. */
381
382 kCLOCK_NoneName = CLOCK_SOURCE_NONE, /*!< None Clock Name. */
383} clock_name_t;
384
385#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */
386#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */
387
388/*!
389 * @brief CCM CCGR gate control for each module independently.
390 */
391typedef enum _clock_ip_name
392{
393 kCLOCK_IpInvalid = -1,
394
395 /* CCM CCGR0 */
396 kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */
397 kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */
398 kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2, Reserved */
399 kCLOCK_Sim_m_clk_r = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */
400 kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */
401 kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */
402 kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */
403 kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */
404 kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */
405 kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */
406 kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */
407
408 /* CCM CCGR1 */
409 kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */
410 kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */
411 kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */
412 /*!< CCGR1, CG7, Reserved */
413 kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */
414 kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */
415 kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */
416 kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */
417 kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */
418 kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */
419 kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */
420
421 /* CCM CCGR2 */
422 kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */
423 /*!< CCGR2, CG1, Reserved */
424 kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */
425 kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */
426 kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */
427 kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */
428 /*!< CCGR2, CG7, Reserved */
429 /*!< CCGR2, CG8, Reserved */
430 /*!< CCGR2, CG9, Reserved */
431 /*!< CCGR2, CG10, Reserved */
432 kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */
433 kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */
434 kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */
435 /*!< CCGR2, CG14, Reserved */
436 /*!< CCGR2, CG15, Reserved */
437
438 /* CCM CCGR3 */
439 /*!< CCGR3, CG0, Reserved */
440 kCLOCK_Aoi = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */
441 /*!< CCGR3, CG5, Reserved */
442 /*!< CCGR3, CG6, Reserved */
443 kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */
444 kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */
445 kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */
446 /*!< CCGR3, CG14, Reserved */
447 kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */
448
449 /* CCM CCGR4 */
450 kCLOCK_Sim_m7_clk_r = (4U << 8U) | CCM_CCGR4_CG0_SHIFT, /*!< CCGR4, CG0 */
451 kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */
452 kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */
453 kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */
454 kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */
455 kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */
456 kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */
457 kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */
458 /*!< CCGR4, CG10, Reserved */
459 /*!< CCGR4, CG11, Reserved */
460 kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */
461 /*!< CCGR4, CG14, Reserved */
462 /*!< CCGR4, CG15, Reserved */
463
464 /* CCM CCGR5 */
465 kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */
466 kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */
467 kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */
468 kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */
469 kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */
470 kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */
471 kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */
472 kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */
473 /*!< CCGR5, CG8, Reserved */
474 kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */
475 kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */
476 kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */
477 kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */
478 kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */
479 kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */
480
481 /* CCM CCGR6 */
482 kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */
483 kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */
484 kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */
485 kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */
486 kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */
487 kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */
488 kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */
489 kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */
490 /*!< CCGR6, CG15, Reserved */
491
492} clock_ip_name_t;
493
494/*! @brief OSC 24M sorce select */
495typedef enum _clock_osc
496{
497 kCLOCK_RcOsc = 0U, /*!< On chip OSC. */
498 kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */
499} clock_osc_t;
500
501/*! @brief Clock gate value */
502typedef enum _clock_gate_value
503{
504 kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */
505 kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */
506 kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */
507} clock_gate_value_t;
508
509/*! @brief System clock mode */
510typedef enum _clock_mode_t
511{
512 kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */
513 kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */
514 kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */
515} clock_mode_t;
516
517/*!
518 * @brief MUX control names for clock mux setting.
519 *
520 * These constants define the mux control names for clock mux setting.\n
521 * - 0:7: REG offset to CCM_BASE in bytes.
522 * - 8:15: Root clock setting bit field shift.
523 * - 16:31: Root clock setting bit field width.
524 */
525typedef enum _clock_mux
526{
527 kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET,
528 CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT,
529 CCM_CCSR_PLL3_SW_CLK_SEL_MASK,
530 CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */
531
532 kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
533 CCM_CBCDR_PERIPH_CLK_SEL_SHIFT,
534 CCM_CBCDR_PERIPH_CLK_SEL_MASK,
535 CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */
536 kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET,
537 CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT,
538 CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK,
539 CCM_NO_BUSY_WAIT), /*!< semc mux name */
540 kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET,
541 CCM_CBCDR_SEMC_CLK_SEL_SHIFT,
542 CCM_CBCDR_SEMC_CLK_SEL_MASK,
543 CCM_NO_BUSY_WAIT), /*!< semc mux name */
544
545 kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
546 CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT,
547 CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK,
548 CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */
549 kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET,
550 CCM_CBCMR_TRACE_CLK_SEL_SHIFT,
551 CCM_CBCMR_TRACE_CLK_SEL_MASK,
552 CCM_NO_BUSY_WAIT), /*!< trace mux name */
553 kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
554 CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT,
555 CCM_CBCMR_PERIPH_CLK2_SEL_MASK,
556 CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */
557 kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET,
558 CCM_CBCMR_LPSPI_CLK_SEL_SHIFT,
559 CCM_CBCMR_LPSPI_CLK_SEL_MASK,
560 CCM_NO_BUSY_WAIT), /*!< lpspi mux name */
561
562 kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
563 CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT,
564 CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK,
565 CCM_NO_BUSY_WAIT), /*!< flexspi mux name */
566 kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1_OFFSET,
567 CCM_CSCMR1_SAI3_CLK_SEL_SHIFT,
568 CCM_CSCMR1_SAI3_CLK_SEL_MASK,
569 CCM_NO_BUSY_WAIT), /*!< sai3 mux name */
570 kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1_OFFSET,
571 CCM_CSCMR1_SAI2_CLK_SEL_SHIFT,
572 CCM_CSCMR1_SAI2_CLK_SEL_MASK,
573 CCM_NO_BUSY_WAIT), /*!< sai2 mux name */
574 kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1_OFFSET,
575 CCM_CSCMR1_SAI1_CLK_SEL_SHIFT,
576 CCM_CSCMR1_SAI1_CLK_SEL_MASK,
577 CCM_NO_BUSY_WAIT), /*!< sai1 mux name */
578 kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET,
579 CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT,
580 CCM_CSCMR1_PERCLK_CLK_SEL_MASK,
581 CCM_NO_BUSY_WAIT), /*!< perclk mux name */
582
583 kCLOCK_Flexio1Mux = CCM_TUPLE(CSCMR2_OFFSET,
584 CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT,
585 CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK,
586 CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */
587
588 kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET,
589 CCM_CSCDR1_UART_CLK_SEL_SHIFT,
590 CCM_CSCDR1_UART_CLK_SEL_MASK,
591 CCM_NO_BUSY_WAIT), /*!< uart mux name */
592
593 kCLOCK_SpdifMux = CCM_TUPLE(CDCDR_OFFSET,
594 CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT,
595 CCM_CDCDR_SPDIF0_CLK_SEL_MASK,
596 CCM_NO_BUSY_WAIT), /*!< spdif mux name */
597
598 kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2_OFFSET,
599 CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT,
600 CCM_CSCDR2_LPI2C_CLK_SEL_MASK,
601 CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */
602} clock_mux_t;
603
604/*!
605 * @brief DIV control names for clock div setting.
606 *
607 * These constants define div control names for clock div setting.\n
608 * - 0:7: REG offset to CCM_BASE in bytes.
609 * - 8:15: Root clock setting bit field shift.
610 * - 16:31: Root clock setting bit field width.
611 */
612typedef enum _clock_div
613{
614 kCLOCK_ArmDiv = CCM_TUPLE(CACRR_OFFSET,
615 CCM_CACRR_ARM_PODF_SHIFT,
616 CCM_CACRR_ARM_PODF_MASK,
617 CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */
618
619 kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET,
620 CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT,
621 CCM_CBCDR_PERIPH_CLK2_PODF_MASK,
622 CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */
623 kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET,
624 CCM_CBCDR_SEMC_PODF_SHIFT,
625 CCM_CBCDR_SEMC_PODF_MASK,
626 CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */
627 kCLOCK_AhbDiv = CCM_TUPLE(CBCDR_OFFSET,
628 CCM_CBCDR_AHB_PODF_SHIFT,
629 CCM_CBCDR_AHB_PODF_MASK,
630 CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */
631 kCLOCK_IpgDiv = CCM_TUPLE(
632 CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */
633
634 kCLOCK_LpspiDiv = CCM_TUPLE(
635 CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */
636
637 kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET,
638 CCM_CSCMR1_FLEXSPI_PODF_SHIFT,
639 CCM_CSCMR1_FLEXSPI_PODF_MASK,
640 CCM_NO_BUSY_WAIT), /*!< flexspi div name */
641 kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1_OFFSET,
642 CCM_CSCMR1_PERCLK_PODF_SHIFT,
643 CCM_CSCMR1_PERCLK_PODF_MASK,
644 CCM_NO_BUSY_WAIT), /*!< perclk div name */
645
646 kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1_OFFSET,
647 CCM_CSCDR1_TRACE_PODF_SHIFT,
648 CCM_CSCDR1_TRACE_PODF_MASK,
649 CCM_NO_BUSY_WAIT), /*!< trace div name */
650 kCLOCK_UartDiv = CCM_TUPLE(CSCDR1_OFFSET,
651 CCM_CSCDR1_UART_CLK_PODF_SHIFT,
652 CCM_CSCDR1_UART_CLK_PODF_MASK,
653 CCM_NO_BUSY_WAIT), /*!< uart div name */
654
655 kCLOCK_Flexio1Div = CCM_TUPLE(CS1CDR_OFFSET,
656 CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT,
657 CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK,
658 CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
659 kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
660 CCM_CS1CDR_SAI3_CLK_PRED_SHIFT,
661 CCM_CS1CDR_SAI3_CLK_PRED_MASK,
662 CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
663 kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR_OFFSET,
664 CCM_CS1CDR_SAI3_CLK_PODF_SHIFT,
665 CCM_CS1CDR_SAI3_CLK_PODF_MASK,
666 CCM_NO_BUSY_WAIT), /*!< sai3 div name */
667 kCLOCK_Flexio1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
668 CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT,
669 CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK,
670 CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
671 kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
672 CCM_CS1CDR_SAI1_CLK_PRED_SHIFT,
673 CCM_CS1CDR_SAI1_CLK_PRED_MASK,
674 CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */
675 kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR_OFFSET,
676 CCM_CS1CDR_SAI1_CLK_PODF_SHIFT,
677 CCM_CS1CDR_SAI1_CLK_PODF_MASK,
678 CCM_NO_BUSY_WAIT), /*!< sai1 div name */
679
680 kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET,
681 CCM_CS2CDR_SAI2_CLK_PRED_SHIFT,
682 CCM_CS2CDR_SAI2_CLK_PRED_MASK,
683 CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */
684 kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR_OFFSET,
685 CCM_CS2CDR_SAI2_CLK_PODF_SHIFT,
686 CCM_CS2CDR_SAI2_CLK_PODF_MASK,
687 CCM_NO_BUSY_WAIT), /*!< sai2 div name */
688
689 kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET,
690 CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT,
691 CCM_CDCDR_SPDIF0_CLK_PRED_MASK,
692 CCM_NO_BUSY_WAIT), /*!< spdif pre div name */
693 kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET,
694 CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT,
695 CCM_CDCDR_SPDIF0_CLK_PODF_MASK,
696 CCM_NO_BUSY_WAIT), /*!< spdif div name */
697
698 kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET,
699 CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT,
700 CCM_CSCDR2_LPI2C_CLK_PODF_MASK,
701 CCM_NO_BUSY_WAIT), /*!< lpi2c div name */
702 kCLOCK_NonePreDiv = CLOCK_ROOT_NONE_PRE_DIV, /*!< None Pre div. */
703} clock_div_t;
704
705/*! @brief USB clock source definition. */
706typedef enum _clock_usb_src
707{
708 kCLOCK_Usb480M = 0, /*!< Use 480M. */
709 kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
710 care the clock source. */
711} clock_usb_src_t;
712
713/*! @brief Source of the USB HS PHY. */
714typedef enum _clock_usb_phy_src
715{
716 kCLOCK_Usbphy480M = 0, /*!< Use 480M. */
717} clock_usb_phy_src_t;
718
719/*!@brief PLL clock source, bypass cloco source also */
720enum _clock_pll_clk_src
721{
722 kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */
723 kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */
724};
725
726/*! @brief PLL configuration for USB */
727typedef struct _clock_usb_pll_config
728{
729 uint8_t loopDivider; /*!< PLL loop divider.
730 0 - Fout=Fref*20;
731 1 - Fout=Fref*22 */
732 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
733
734} clock_usb_pll_config_t;
735
736/*! @brief PLL configuration for System */
737typedef struct _clock_sys_pll_config
738{
739 uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M).
740 0 - Fout=Fref*20;
741 1 - Fout=Fref*22 */
742 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
743 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
744 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
745 uint16_t ss_stop; /*!< Stop value to get frequency change. */
746 uint8_t ss_enable; /*!< Enable spread spectrum modulation */
747 uint16_t ss_step; /*!< Step value to get frequency change step. */
748
749} clock_sys_pll_config_t;
750
751/*! @brief PLL configuration for AUDIO and VIDEO */
752typedef struct _clock_audio_pll_config
753{
754 uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
755 uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */
756 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
757 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
758 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
759} clock_audio_pll_config_t;
760
761/*! @brief PLL configuration for ENET */
762typedef struct _clock_enet_pll_config
763{
764 bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */
765
766 bool enableClkOutput500M; /*!< Power on and enable PLL clock output for ENET (ref_enetpll500M). */
767
768 bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */
769 uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock.
770 b00 25MHz
771 b01 50MHz
772 b10 100MHz (not 50% duty cycle)
773 b11 125MHz */
774 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
775
776} clock_enet_pll_config_t;
777
778/*! @brief PLL name */
779typedef enum _clock_pll
780{
781 kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */
782 kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */
783 kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */
784 kCLOCK_PllEnet500M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT), /*!< PLL ENET */
785} clock_pll_t;
786
787/*! @brief PLL PFD name */
788typedef enum _clock_pfd
789{
790 kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */
791 kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */
792 kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */
793 kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
794} clock_pfd_t;
795
796/*!
797 * @brief The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on.
798 */
799typedef enum _clock_output1_selection
800{
801 kCLOCK_OutputPllUsb1Sw = 0U, /*!< Selects USB1 PLL SW clock(Divided by 2) output. */
802 kCLOCK_OutputPllSys = 1U, /*!< Selects SYS PLL clock(Divided by 2) output. */
803 kCLOCK_OutputPllENET = 2U, /*!< Selects ENET PLL clock(Divided by 2) output. */
804 kCLOCK_OutputAhbClk = 0xBU, /*!< Selects AHB clock root output. */
805 kCLOCK_OutputIpgClk = 0xCU, /*!< Selects IPG clock root output. */
806 kCLOCK_OutputPerClk = 0xDU, /*!< Selects PERCLK clock root output. */
807 kCLOCK_OutputPll4MainClk = 0xFU, /*!< Selects PLL4 main clock output. */
808 kCLOCK_DisableClockOutput1 = 0x10U, /*!< Disables CLKO1. */
809} clock_output1_selection_t;
810
811/*!
812 * @brief The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on.
813 *
814 */
815typedef enum _clock_output2_selection
816{
817 kCLOCK_OutputLpi2cClk = 6U, /*!< Selects LPI2C clock root output. */
818 kCLOCK_OutputOscClk = 0xEU, /*!< Selects OSC output. */
819 kCLOCK_OutputLpspiClk = 0x10U, /*!< Selects LPSPI clock root output. */
820 kCLOCK_OutputSai1Clk = 0x12U, /*!< Selects SAI1 clock root output. */
821 kCLOCK_OutputSai2Clk = 0x13U, /*!< Selects SAI2 clock root output. */
822 kCLOCK_OutputSai3Clk = 0x14U, /*!< Selects SAI3 clock root output. */
823 kCLOCK_OutputTraceClk = 0x16U, /*!< Selects Trace clock root output. */
824 kCLOCK_OutputFlexspiClk = 0x1BU, /*!< Selects FLEXSPI clock root output. */
825 kCLOCK_OutputUartClk = 0x1CU, /*!< Selects UART clock root output. */
826 kCLOCK_OutputSpdif0Clk = 0x1DU, /*!< Selects SPDIF0 clock root output. */
827 kCLOCK_DisableClockOutput2 = 0x1FU, /*!< Disables CLKO2. */
828} clock_output2_selection_t;
829
830/*!
831 * @brief The enumerator of clock output's divider.
832 */
833typedef enum _clock_output_divider
834{
835 kCLOCK_DivideBy1 = 0U, /*!< Output clock divided by 1. */
836 kCLOCK_DivideBy2, /*!< Output clock divided by 2. */
837 kCLOCK_DivideBy3, /*!< Output clock divided by 3. */
838 kCLOCK_DivideBy4, /*!< Output clock divided by 4. */
839 kCLOCK_DivideBy5, /*!< Output clock divided by 5. */
840 kCLOCK_DivideBy6, /*!< Output clock divided by 6. */
841 kCLOCK_DivideBy7, /*!< Output clock divided by 7. */
842 kCLOCK_DivideBy8, /*!< Output clock divided by 8. */
843} clock_output_divider_t;
844
845/*!
846 * @brief The enumerator of clock root.
847 */
848typedef enum _clock_root
849{
850 kCLOCK_FlexspiClkRoot = 0U, /*!< FLEXSPI clock root. */
851 kCLOCK_LpspiClkRoot, /*!< LPSPI clock root. */
852 kCLOCK_TraceClkRoot, /*!< Trace clock root. */
853 kCLOCK_Sai1ClkRoot, /*!< SAI1 clock root. */
854 kCLOCK_Sai2ClkRoot, /*!< SAI2 clock root. */
855 kCLOCK_Sai3ClkRoot, /*!< SAI3 clock root. */
856 kCLOCK_Lpi2cClkRoot, /*!< LPI2C clock root. */
857 kCLOCK_UartClkRoot, /*!< UART clock root. */
858 kCLOCK_SpdifClkRoot, /*!< SPDIF clock root. */
859 kCLOCK_Flexio1ClkRoot, /*!< FLEXIO1 clock root. */
860} clock_root_t;
861
862/*******************************************************************************
863 * API
864 ******************************************************************************/
865
866#if defined(__cplusplus)
867extern "C" {
868#endif /* __cplusplus */
869
870/*!
871 * @brief Set CCM MUX node to certain value.
872 *
873 * @param mux Which mux node to set, see \ref clock_mux_t.
874 * @param value Clock mux value to set, different mux has different value range.
875 */
876static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
877{
878 uint32_t busyShift;
879
880 busyShift = CCM_TUPLE_BUSY_SHIFT(mux);
881 CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) |
882 (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux));
883
884 assert(busyShift <= CCM_NO_BUSY_WAIT);
885
886 /* Clock switch need Handshake? */
887 if (CCM_NO_BUSY_WAIT != busyShift)
888 {
889 /* Wait until CCM internal handshake finish. */
890 while ((CCM->CDHIPR & (1UL << busyShift)) != 0UL)
891 {
892 }
893 }
894}
895
896/*!
897 * @brief Get CCM MUX value.
898 *
899 * @param mux Which mux node to get, see \ref clock_mux_t.
900 * @return Clock mux value.
901 */
902static inline uint32_t CLOCK_GetMux(clock_mux_t mux)
903{
904 return (CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux)) >> CCM_TUPLE_SHIFT(mux);
905}
906
907/*!
908 * @brief Set CCM DIV node to certain value.
909 *
910 * @param divider Which div node to set, see \ref clock_div_t.
911 * @param value Clock div value to set, different divider has different value range.
912 */
913static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
914{
915 uint32_t busyShift;
916
917 busyShift = CCM_TUPLE_BUSY_SHIFT((uint32_t)divider);
918 CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) |
919 (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider));
920
921 assert(busyShift <= CCM_NO_BUSY_WAIT);
922
923 /* Clock switch need Handshake? */
924 if (CCM_NO_BUSY_WAIT != busyShift)
925 {
926 /* Wait until CCM internal handshake finish. */
927 while ((CCM->CDHIPR & (1UL << busyShift)) != 0UL)
928 {
929 }
930 }
931}
932
933/*!
934 * @brief Get CCM DIV node value.
935 *
936 * @param divider Which div node to get, see \ref clock_div_t.
937 */
938static inline uint32_t CLOCK_GetDiv(clock_div_t divider)
939{
940 return ((CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider));
941}
942
943/*!
944 * @brief Control the clock gate for specific IP.
945 *
946 * @param name Which clock to enable, see \ref clock_ip_name_t.
947 * @param value Clock gate value to set, see \ref clock_gate_value_t.
948 */
949static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value)
950{
951 uint32_t index = ((uint32_t)name) >> 8U;
952 uint32_t shift = ((uint32_t)name) & 0x1FU;
953 volatile uint32_t *reg;
954
955 assert(index <= 6UL);
956
957 reg = (volatile uint32_t *)((uint32_t)((volatile uint32_t *)&CCM->CCGR0) + sizeof(volatile uint32_t *) * index);
958 *reg = ((*reg) & ~(3UL << shift)) | (((uint32_t)value) << shift);
959}
960
961/*!
962 * @brief Enable the clock for specific IP.
963 *
964 * @param name Which clock to enable, see \ref clock_ip_name_t.
965 */
966static inline void CLOCK_EnableClock(clock_ip_name_t name)
967{
968 CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait);
969}
970
971/*!
972 * @brief Disable the clock for specific IP.
973 *
974 * @param name Which clock to disable, see \ref clock_ip_name_t.
975 */
976static inline void CLOCK_DisableClock(clock_ip_name_t name)
977{
978 CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded);
979}
980
981/*!
982 * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal.
983 *
984 * @param mode Which mode to enter, see \ref clock_mode_t.
985 */
986static inline void CLOCK_SetMode(clock_mode_t mode)
987{
988 CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode);
989}
990
991/*!
992 * @brief Gets the OSC clock frequency.
993 *
994 * This function will return the external XTAL OSC frequency if it is selected as the source of OSC,
995 * otherwise internal 24MHz RC OSC frequency will be returned.
996 *
997 * @return Clock frequency; If the clock is invalid, returns 0.
998 */
999static inline uint32_t CLOCK_GetOscFreq(void)
1000{
1001 return ((XTALOSC24M->LOWPWR_CTRL & (uint32_t)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_xtalFreq;
1002}
1003
1004/*!
1005 * @brief Gets the AHB clock frequency.
1006 *
1007 * @return The AHB clock frequency value in hertz.
1008 */
1009uint32_t CLOCK_GetAhbFreq(void);
1010
1011/*!
1012 * @brief Gets the SEMC clock frequency.
1013 *
1014 * @return The SEMC clock frequency value in hertz.
1015 */
1016uint32_t CLOCK_GetSemcFreq(void);
1017
1018/*!
1019 * @brief Gets the IPG clock frequency.
1020 *
1021 * @return The IPG clock frequency value in hertz.
1022 */
1023uint32_t CLOCK_GetIpgFreq(void);
1024
1025/*!
1026 * @brief Gets the PER clock frequency.
1027 *
1028 * @return The PER clock frequency value in hertz.
1029 */
1030uint32_t CLOCK_GetPerClkFreq(void);
1031
1032/*!
1033 * @brief Gets the clock frequency for a specific clock name.
1034 *
1035 * This function checks the current clock configurations and then calculates
1036 * the clock frequency for a specific clock name defined in clock_name_t.
1037 *
1038 * @param name Clock names defined in clock_name_t
1039 * @return Clock frequency value in hertz
1040 */
1041uint32_t CLOCK_GetFreq(clock_name_t name);
1042
1043/*!
1044 * @brief Get the CCM CPU/core/system frequency.
1045 *
1046 * @return Clock frequency; If the clock is invalid, returns 0.
1047 */
1048static inline uint32_t CLOCK_GetCpuClkFreq(void)
1049{
1050 return CLOCK_GetFreq(kCLOCK_CpuClk);
1051}
1052
1053/*!
1054 * @brief Gets the frequency of selected clock root.
1055 *
1056 * @param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t.
1057 * @return The frequency of selected clock root.
1058 */
1059uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot);
1060
1061/*!
1062 * @name OSC operations
1063 * @{
1064 */
1065
1066/*!
1067 * @brief Initialize the external 24MHz clock.
1068 *
1069 * This function supports two modes:
1070 * 1. Use external crystal oscillator.
1071 * 2. Bypass the external crystal oscillator, using input source clock directly.
1072 *
1073 * After this function, please call CLOCK_SetXtal0Freq to inform clock driver
1074 * the external clock frequency.
1075 *
1076 * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator.
1077 * @note This device does not support bypass external crystal oscillator, so
1078 * the input parameter should always be false.
1079 */
1080void CLOCK_InitExternalClk(bool bypassXtalOsc);
1081
1082/*!
1083 * @brief Deinitialize the external 24MHz clock.
1084 *
1085 * This function disables the external 24MHz clock.
1086 *
1087 * After this function, please call CLOCK_SetXtal0Freq to set external clock
1088 * frequency to 0.
1089 */
1090void CLOCK_DeinitExternalClk(void);
1091
1092/*!
1093 * @brief Switch the OSC.
1094 *
1095 * This function switches the OSC source for SoC.
1096 *
1097 * @param osc OSC source to switch to.
1098 */
1099void CLOCK_SwitchOsc(clock_osc_t osc);
1100
1101/*!
1102 * @brief Gets the RTC clock frequency.
1103 *
1104 * @return Clock frequency; If the clock is invalid, returns 0.
1105 */
1106static inline uint32_t CLOCK_GetRtcFreq(void)
1107{
1108 return 32768U;
1109}
1110
1111/*!
1112 * @brief Set the XTAL (24M OSC) frequency based on board setting.
1113 *
1114 * @param freq The XTAL input clock frequency in Hz.
1115 */
1116static inline void CLOCK_SetXtalFreq(uint32_t freq)
1117{
1118 g_xtalFreq = freq;
1119}
1120
1121/*!
1122 * @brief Set the RTC XTAL (32K OSC) frequency based on board setting.
1123 *
1124 * @param freq The RTC XTAL input clock frequency in Hz.
1125 */
1126static inline void CLOCK_SetRtcXtalFreq(uint32_t freq)
1127{
1128 g_rtcXtalFreq = freq;
1129}
1130
1131/*!
1132 * @brief Initialize the RC oscillator 24MHz clock.
1133 */
1134void CLOCK_InitRcOsc24M(void);
1135
1136/*!
1137 * @brief Power down the RCOSC 24M clock.
1138 */
1139void CLOCK_DeinitRcOsc24M(void);
1140/* @} */
1141
1142/*! @brief Enable USB HS clock.
1143 *
1144 * This function only enables the access to USB HS prepheral, upper layer
1145 * should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
1146 * clock to use USB HS.
1147 *
1148 * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
1149 * @param freq USB HS does not care about the clock source, so this parameter is ignored.
1150 * @retval true The clock is set successfully.
1151 * @retval false The clock source is invalid to get proper USB HS clock.
1152 */
1153bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
1154
1155/* @} */
1156
1157/*!
1158 * @name PLL/PFD operations
1159 * @{
1160 */
1161/*!
1162 * @brief PLL bypass setting
1163 *
1164 * @param base CCM_ANALOG base pointer.
1165 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1166 * @param bypass Bypass the PLL.
1167 * - true: Bypass the PLL.
1168 * - false:Not bypass the PLL.
1169 */
1170static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass)
1171{
1172 if (bypass)
1173 {
1174 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1175 }
1176 else
1177 {
1178 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1179 }
1180}
1181
1182/*!
1183 * @brief Check if PLL is bypassed
1184 *
1185 * @param base CCM_ANALOG base pointer.
1186 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1187 * @return PLL bypass status.
1188 * - true: The PLL is bypassed.
1189 * - false: The PLL is not bypassed.
1190 */
1191static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll)
1192{
1193 return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_PLL_BYPASS_SHIFT));
1194}
1195
1196/*!
1197 * @brief Check if PLL is enabled
1198 *
1199 * @param base CCM_ANALOG base pointer.
1200 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1201 * @return PLL bypass status.
1202 * - true: The PLL is enabled.
1203 * - false: The PLL is not enabled.
1204 */
1205static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll)
1206{
1207 return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pll)));
1208}
1209
1210/*!
1211 * @brief PLL bypass clock source setting.
1212 * Note: change the bypass clock source also change the pll reference clock source.
1213 *
1214 * @param base CCM_ANALOG base pointer.
1215 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1216 * @param src Bypass clock source, reference _clock_pll_bypass_clk_src.
1217 */
1218static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src)
1219{
1220 CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src;
1221}
1222
1223/*!
1224 * @brief Get PLL bypass clock value, it is PLL reference clock actually.
1225 * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0
1226 * will be returned.
1227 * @param base CCM_ANALOG base pointer.
1228 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1229 * @retval bypass reference clock frequency value.
1230 */
1231static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll)
1232{
1233 return ((((uint32_t)(CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) >>
1234 CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == (uint32_t)kCLOCK_PllClkSrc24M) ?
1235 CLOCK_GetOscFreq() :
1236 CLKPN_FREQ;
1237}
1238
1239/*!
1240 * @brief Initialize the System PLL.
1241 *
1242 * This function initializes the System PLL with specific settings
1243 *
1244 * @param config Configuration to set to PLL.
1245 */
1246void CLOCK_InitSysPll(const clock_sys_pll_config_t *config);
1247
1248/*!
1249 * @brief De-initialize the System PLL.
1250 */
1251void CLOCK_DeinitSysPll(void);
1252
1253/*!
1254 * @brief Initialize the USB1 PLL.
1255 *
1256 * This function initializes the USB1 PLL with specific settings
1257 *
1258 * @param config Configuration to set to PLL.
1259 */
1260void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config);
1261
1262/*!
1263 * @brief Deinitialize the USB1 PLL.
1264 */
1265void CLOCK_DeinitUsb1Pll(void);
1266
1267/*!
1268 * @brief Initializes the Audio PLL.
1269 *
1270 * This function initializes the Audio PLL with specific settings
1271 *
1272 * @param config Configuration to set to PLL.
1273 */
1274void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
1275
1276/*!
1277 * @brief De-initialize the Audio PLL.
1278 */
1279void CLOCK_DeinitAudioPll(void);
1280
1281/*!
1282 * @brief Initialize the ENET PLL.
1283 *
1284 * This function initializes the ENET PLL with specific settings.
1285 *
1286 * @param config Configuration to set to PLL.
1287 */
1288void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config);
1289
1290/*!
1291 * @brief Deinitialize the ENET PLL.
1292 *
1293 * This function disables the ENET PLL.
1294 */
1295void CLOCK_DeinitEnetPll(void);
1296
1297/*!
1298 * @brief Get current PLL output frequency.
1299 *
1300 * This function get current output frequency of specific PLL
1301 *
1302 * @param pll pll name to get frequency.
1303 * @return The PLL output frequency in hertz.
1304 */
1305uint32_t CLOCK_GetPllFreq(clock_pll_t pll);
1306
1307/*!
1308 * @brief Initialize the System PLL PFD.
1309 *
1310 * This function initializes the System PLL PFD. During new value setting,
1311 * the clock output is disabled to prevent glitch.
1312 *
1313 * @param pfd Which PFD clock to enable.
1314 * @param pfdFrac The PFD FRAC value.
1315 * @note It is recommended that PFD settings are kept between 12-35.
1316 */
1317void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac);
1318
1319/*!
1320 * @brief De-initialize the System PLL PFD.
1321 *
1322 * This function disables the System PLL PFD.
1323 *
1324 * @param pfd Which PFD clock to disable.
1325 */
1326void CLOCK_DeinitSysPfd(clock_pfd_t pfd);
1327
1328/*!
1329 * @brief Initialize the USB1 PLL PFD.
1330 *
1331 * This function initializes the USB1 PLL PFD. During new value setting,
1332 * the clock output is disabled to prevent glitch.
1333 *
1334 * @param pfd Which PFD clock to enable.
1335 * @param pfdFrac The PFD FRAC value.
1336 * @note It is recommended that PFD settings are kept between 12-35.
1337 */
1338void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac);
1339
1340/*!
1341 * @brief De-initialize the USB1 PLL PFD.
1342 *
1343 * This function disables the USB1 PLL PFD.
1344 *
1345 * @param pfd Which PFD clock to disable.
1346 */
1347void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd);
1348
1349/*!
1350 * @brief Get current System PLL PFD output frequency.
1351 *
1352 * This function get current output frequency of specific System PLL PFD
1353 *
1354 * @param pfd pfd name to get frequency.
1355 * @return The PFD output frequency in hertz.
1356 */
1357uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
1358
1359/*!
1360 * @brief Get current USB1 PLL PFD output frequency.
1361 *
1362 * This function get current output frequency of specific USB1 PLL PFD
1363 *
1364 * @param pfd pfd name to get frequency.
1365 * @return The PFD output frequency in hertz.
1366 */
1367uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd);
1368
1369/*! @brief Enable USB HS PHY PLL clock.
1370 *
1371 * This function enables the internal 480MHz USB PHY PLL clock.
1372 *
1373 * @param src USB HS PHY PLL clock source.
1374 * @param freq The frequency specified by src.
1375 * @retval true The clock is set successfully.
1376 * @retval false The clock source is invalid to get proper USB HS clock.
1377 */
1378bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1379
1380/*! @brief Disable USB HS PHY PLL clock.
1381 *
1382 * This function disables USB HS PHY PLL clock.
1383 */
1384void CLOCK_DisableUsbhs0PhyPllClock(void);
1385
1386/* @} */
1387
1388/*!
1389 * @name Clock Output Inferfaces
1390 * @{
1391 */
1392
1393/*!
1394 * @brief Set the clock source and the divider of the clock output1.
1395 *
1396 * @param selection The clock source to be output, please refer to @ref clock_output1_selection_t.
1397 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1398 */
1399void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider);
1400
1401/*!
1402 * @brief Set the clock source and the divider of the clock output2.
1403 *
1404 * @param selection The clock source to be output, please refer to @ref clock_output2_selection_t.
1405 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1406 */
1407void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider);
1408
1409/*!
1410 * @brief Get the frequency of clock output1 clock signal.
1411 *
1412 * @return The frequency of clock output1 clock signal.
1413 */
1414uint32_t CLOCK_GetClockOutCLKO1Freq(void);
1415
1416/*!
1417 * @brief Get the frequency of clock output2 clock signal.
1418 *
1419 * @return The frequency of clock output2 clock signal.
1420 */
1421uint32_t CLOCK_GetClockOutClkO2Freq(void);
1422
1423/*! @} */
1424
1425#if defined(__cplusplus)
1426}
1427#endif /* __cplusplus */
1428
1429/*! @} */
1430
1431#endif /* _FSL_CLOCK_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 17:02:12 +0100