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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_clock.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_iomuxc.cmake15
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_reset.cmake14
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_romapi.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_soc_flexram_allocate.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_clock.c1223
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_clock.h1567
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_flexram_allocate.c157
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_flexram_allocate.h99
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_iomuxc.h1008
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_romapi.c170
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_romapi.h554
12 files changed, 4855 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_clock.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_clock.cmake
new file mode 100644
index 000000000..154d6a23a
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_clock.cmake
@@ -0,0 +1,16 @@
1if(NOT DRIVER_CLOCK_INCLUDED)
2
3 set(DRIVER_CLOCK_INCLUDED true CACHE BOOL "driver_clock component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 ${CMAKE_CURRENT_LIST_DIR}/fsl_clock.c
7 )
8
9 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
10 ${CMAKE_CURRENT_LIST_DIR}/.
11 )
12
13
14 include(driver_common)
15
16endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_iomuxc.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_iomuxc.cmake
new file mode 100644
index 000000000..1de06623a
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_iomuxc.cmake
@@ -0,0 +1,15 @@
1if(NOT DRIVER_IOMUXC_INCLUDED)
2
3 set(DRIVER_IOMUXC_INCLUDED true CACHE BOOL "driver_iomuxc component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 )
7
8 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
9 ${CMAKE_CURRENT_LIST_DIR}/.
10 )
11
12
13 include(driver_common)
14
15endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_reset.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_reset.cmake
new file mode 100644
index 000000000..989530f6f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_reset.cmake
@@ -0,0 +1,14 @@
1if(NOT DRIVER_RESET_INCLUDED)
2
3 set(DRIVER_RESET_INCLUDED true CACHE BOOL "driver_reset component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 )
7
8 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
9 ${CMAKE_CURRENT_LIST_DIR}/.
10 )
11
12
13
14endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_romapi.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_romapi.cmake
new file mode 100644
index 000000000..392bd6bc8
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_romapi.cmake
@@ -0,0 +1,16 @@
1if(NOT DRIVER_ROMAPI_INCLUDED)
2
3 set(DRIVER_ROMAPI_INCLUDED true CACHE BOOL "driver_romapi component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 ${CMAKE_CURRENT_LIST_DIR}/fsl_romapi.c
7 )
8
9 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
10 ${CMAKE_CURRENT_LIST_DIR}/.
11 )
12
13
14 include(driver_common)
15
16endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_soc_flexram_allocate.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_soc_flexram_allocate.cmake
new file mode 100644
index 000000000..9aa4d4706
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/driver_soc_flexram_allocate.cmake
@@ -0,0 +1,16 @@
1if(NOT DRIVER_SOC_FLEXRAM_ALLOCATE_INCLUDED)
2
3 set(DRIVER_SOC_FLEXRAM_ALLOCATE_INCLUDED true CACHE BOOL "driver_soc_flexram_allocate component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 ${CMAKE_CURRENT_LIST_DIR}/fsl_flexram_allocate.c
7 )
8
9 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
10 ${CMAKE_CURRENT_LIST_DIR}/.
11 )
12
13
14 include(driver_common)
15
16endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_clock.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_clock.c
new file mode 100644
index 000000000..beae64276
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_clock.c
@@ -0,0 +1,1223 @@
1/*
2 * Copyright 2018 - 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_clock.h"
9/* Component ID definition, used by tools. */
10#ifndef FSL_COMPONENT_ID
11#define FSL_COMPONENT_ID "platform.drivers.clock"
12#endif
13
14/*******************************************************************************
15 * Definitions
16 ******************************************************************************/
17/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to
18achieve better performance, it is depend on the IDE Floating point settings, if double precision is selected
19in IDE, clock_64b_t will switch to double type automatically. only support IAR and MDK here */
20#if __FPU_USED
21
22#if (defined(__ICCARM__))
23
24#if (__ARMVFP__ >= __ARMFPV5__) && \
25 (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/
26typedef double clock_64b_t;
27#else
28typedef uint64_t clock_64b_t;
29#endif
30
31#elif (defined(__GNUC__))
32
33#if (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/
34typedef double clock_64b_t;
35#else
36typedef uint64_t clock_64b_t;
37#endif
38
39#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
40
41#if defined __TARGET_FPU_FPV5_D16
42typedef double clock_64b_t;
43#else
44typedef uint64_t clock_64b_t;
45#endif
46
47#else
48typedef uint64_t clock_64b_t;
49#endif
50
51#else
52typedef uint64_t clock_64b_t;
53#endif
54
55/*******************************************************************************
56 * Variables
57 ******************************************************************************/
58
59/* External XTAL (OSC) clock frequency. */
60volatile uint32_t g_xtalFreq;
61/* External RTC XTAL clock frequency. */
62volatile uint32_t g_rtcXtalFreq;
63
64/*******************************************************************************
65 * Prototypes
66 ******************************************************************************/
67
68/*!
69 * @brief Get the periph clock frequency.
70 *
71 * @return Periph clock frequency in Hz.
72 */
73static uint32_t CLOCK_GetPeriphClkFreq(void);
74
75/*!
76 * @brief Get the frequency of PLL USB1 software clock.
77 *
78 * @return The frequency of PLL USB1 software clock.
79 */
80static uint32_t CLOCK_GetPllUsb1SWFreq(void);
81
82/*******************************************************************************
83 * Code
84 ******************************************************************************/
85
86static uint32_t CLOCK_GetPeriphClkFreq(void)
87{
88 uint32_t freq;
89
90 /* Periph_clk2_clk ---> Periph_clk */
91 if ((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) != 0UL)
92 {
93 switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
94 {
95 /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */
96 case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
97 freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1);
98 break;
99
100 /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */
101 case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
102 freq = CLOCK_GetOscFreq();
103 break;
104
105 case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
106 freq = CLOCK_GetPllFreq(kCLOCK_PllSys);
107 break;
108
109 case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
110 default:
111 freq = 0U;
112 break;
113 }
114
115 freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U);
116 }
117 /* Pre_Periph_clk ---> Periph_clk */
118 else
119 {
120 switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
121 {
122 /* PLL2 */
123 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U):
124 freq = CLOCK_GetPllFreq(kCLOCK_PllSys);
125 break;
126
127 /* PLL3 PFD3 */
128 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U):
129 freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd3);
130 break;
131
132 /* PLL2 PFD3 */
133 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U):
134 freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd3);
135 break;
136
137 /* PLL6 divided(/1) */
138 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U):
139 freq = 500000000U;
140 break;
141
142 default:
143 freq = 0U;
144 break;
145 }
146 }
147
148 return freq;
149}
150
151static uint32_t CLOCK_GetPllUsb1SWFreq(void)
152{
153 uint32_t freq;
154
155 switch ((CCM->CCSR & CCM_CCSR_PLL3_SW_CLK_SEL_MASK) >> CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)
156 {
157 case 0:
158 {
159 freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1);
160 break;
161 }
162 case 1:
163 {
164 freq = 24000000UL;
165 break;
166 }
167 default:
168 freq = 0UL;
169 break;
170 }
171
172 return freq;
173}
174/*!
175 * brief Initialize the external 24MHz clock.
176 *
177 * This function supports two modes:
178 * 1. Use external crystal oscillator.
179 * 2. Bypass the external crystal oscillator, using input source clock directly.
180 *
181 * After this function, please call ref CLOCK_SetXtal0Freq to inform clock driver
182 * the external clock frequency.
183 *
184 * param bypassXtalOsc Pass in true to bypass the external crystal oscillator.
185 * note This device does not support bypass external crystal oscillator, so
186 * the input parameter should always be false.
187 */
188void CLOCK_InitExternalClk(bool bypassXtalOsc)
189{
190 /* This device does not support bypass XTAL OSC. */
191 assert(!bypassXtalOsc);
192
193 CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power up */
194 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0UL)
195 {
196 }
197 CCM_ANALOG->MISC0_SET = (uint32_t)CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; /* detect freq */
198 while ((CCM_ANALOG->MISC0 & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) == 0UL)
199 {
200 }
201 CCM_ANALOG->MISC0_CLR = (uint32_t)CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK;
202}
203
204/*!
205 * brief Deinitialize the external 24MHz clock.
206 *
207 * This function disables the external 24MHz clock.
208 *
209 * After this function, please call ref CLOCK_SetXtal0Freq to set external clock
210 * frequency to 0.
211 */
212void CLOCK_DeinitExternalClk(void)
213{
214 CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power down */
215}
216
217/*!
218 * brief Switch the OSC.
219 *
220 * This function switches the OSC source for SoC.
221 *
222 * param osc OSC source to switch to.
223 */
224void CLOCK_SwitchOsc(clock_osc_t osc)
225{
226 if (osc == kCLOCK_RcOsc)
227 {
228 XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK;
229 }
230 else
231 {
232 XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK;
233 }
234}
235
236/*!
237 * brief Initialize the RC oscillator 24MHz clock.
238 */
239void CLOCK_InitRcOsc24M(void)
240{
241 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK;
242}
243
244/*!
245 * brief Power down the RCOSC 24M clock.
246 */
247void CLOCK_DeinitRcOsc24M(void)
248{
249 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK;
250}
251
252/*!
253 * brief Gets the AHB clock frequency.
254 *
255 * return The AHB clock frequency value in hertz.
256 */
257uint32_t CLOCK_GetAhbFreq(void)
258{
259 return CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U);
260}
261
262/*!
263 * brief Gets the SEMC clock frequency.
264 *
265 * return The SEMC clock frequency value in hertz.
266 */
267uint32_t CLOCK_GetSemcFreq(void)
268{
269 uint32_t freq;
270
271 /* SEMC alternative clock ---> SEMC Clock */
272 if ((CCM->CBCDR & CCM_CBCDR_SEMC_CLK_SEL_MASK) != 0UL)
273 {
274 /* PLL3 PFD1 ---> SEMC alternative clock ---> SEMC Clock */
275 if ((CCM->CBCDR & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) != 0UL)
276 {
277 freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1);
278 }
279 /* PLL2 PFD2 ---> SEMC alternative clock ---> SEMC Clock */
280 else
281 {
282 freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2);
283 }
284 }
285 /* Periph_clk ---> SEMC Clock */
286 else
287 {
288 freq = CLOCK_GetPeriphClkFreq();
289 }
290
291 freq /= (((CCM->CBCDR & CCM_CBCDR_SEMC_PODF_MASK) >> CCM_CBCDR_SEMC_PODF_SHIFT) + 1U);
292
293 return freq;
294}
295
296/*!
297 * brief Gets the IPG clock frequency.
298 *
299 * return The IPG clock frequency value in hertz.
300 */
301uint32_t CLOCK_GetIpgFreq(void)
302{
303 return CLOCK_GetAhbFreq() / (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U);
304}
305
306/*!
307 * brief Gets the PER clock frequency.
308 *
309 * return The PER clock frequency value in hertz.
310 */
311uint32_t CLOCK_GetPerClkFreq(void)
312{
313 uint32_t freq;
314
315 /* Osc_clk ---> PER Clock*/
316 if ((CCM->CSCMR1 & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) != 0UL)
317 {
318 freq = CLOCK_GetOscFreq();
319 }
320 /* Periph_clk ---> AHB Clock ---> IPG Clock ---> PER Clock */
321 else
322 {
323 freq = CLOCK_GetIpgFreq();
324 }
325
326 freq /= (((CCM->CSCMR1 & CCM_CSCMR1_PERCLK_PODF_MASK) >> CCM_CSCMR1_PERCLK_PODF_SHIFT) + 1U);
327
328 return freq;
329}
330
331/*!
332 * brief Gets the clock frequency for a specific clock name.
333 *
334 * This function checks the current clock configurations and then calculates
335 * the clock frequency for a specific clock name defined in clock_name_t.
336 *
337 * param clockName Clock names defined in clock_name_t
338 * return Clock frequency value in hertz
339 */
340uint32_t CLOCK_GetFreq(clock_name_t name)
341{
342 uint32_t freq;
343
344 switch (name)
345 {
346 case kCLOCK_CpuClk:
347 case kCLOCK_AhbClk:
348 freq = CLOCK_GetAhbFreq();
349 break;
350
351 case kCLOCK_SemcClk:
352 freq = CLOCK_GetSemcFreq();
353 break;
354
355 case kCLOCK_IpgClk:
356 freq = CLOCK_GetIpgFreq();
357 break;
358
359 case kCLOCK_PerClk:
360 freq = CLOCK_GetPerClkFreq();
361 break;
362
363 case kCLOCK_OscClk:
364 freq = CLOCK_GetOscFreq();
365 break;
366 case kCLOCK_RtcClk:
367 freq = CLOCK_GetRtcFreq();
368 break;
369 case kCLOCK_Usb1PllClk:
370 freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1);
371 break;
372 case kCLOCK_Usb1PllPfd0Clk:
373 freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd0);
374 break;
375 case kCLOCK_Usb1PllPfd1Clk:
376 freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1);
377 break;
378 case kCLOCK_Usb1PllPfd2Clk:
379 freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd2);
380 break;
381 case kCLOCK_Usb1PllPfd3Clk:
382 freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd3);
383 break;
384 case kCLOCK_Usb1SwClk:
385 freq = CLOCK_GetPllUsb1SWFreq();
386 break;
387 case kCLOCK_Usb1Sw60MClk:
388 freq = CLOCK_GetPllUsb1SWFreq() / 8UL;
389 break;
390 case kCLOCK_Usb1Sw80MClk:
391 freq = CLOCK_GetPllUsb1SWFreq() / 6UL;
392 break;
393
394 case kCLOCK_SysPllClk:
395 freq = CLOCK_GetPllFreq(kCLOCK_PllSys);
396 break;
397 case kCLOCK_SysPllPfd0Clk:
398 freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0);
399 break;
400 case kCLOCK_SysPllPfd1Clk:
401 freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd1);
402 break;
403 case kCLOCK_SysPllPfd2Clk:
404 freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2);
405 break;
406 case kCLOCK_SysPllPfd3Clk:
407 freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd3);
408 break;
409 case kCLOCK_EnetPllClk:
410 freq = CLOCK_GetPllFreq(kCLOCK_PllEnet);
411 break;
412 case kCLOCK_EnetPll25MClk:
413 freq = CLOCK_GetPllFreq(kCLOCK_PllEnet25M);
414 break;
415 case kCLOCK_EnetPll500MClk:
416 freq = CLOCK_GetPllFreq(kCLOCK_PllEnet500M);
417 break;
418 case kCLOCK_AudioPllClk:
419 freq = CLOCK_GetPllFreq(kCLOCK_PllAudio);
420 break;
421 default:
422 freq = 0U;
423 break;
424 }
425
426 return freq;
427}
428
429/*!
430 * brief Gets the frequency of selected clock root.
431 *
432 * param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t.
433 * return The frequency of selected clock root.
434 */
435uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot)
436{
437 const clock_name_t clockRootSourceArray[][4] = CLOCK_ROOT_SOUCE;
438 const clock_mux_t clockRootMuxTupleArray[] = CLOCK_ROOT_MUX_TUPLE;
439 const clock_div_t clockRootDivTupleArray[][2] = CLOCK_ROOT_DIV_TUPLE;
440 uint32_t freq = 0UL;
441 clock_mux_t clockRootMuxTuple = clockRootMuxTupleArray[(uint8_t)clockRoot];
442 clock_div_t clockRootPreDivTuple = clockRootDivTupleArray[(uint8_t)clockRoot][0];
443 clock_div_t clockRootPostDivTuple = clockRootDivTupleArray[(uint8_t)clockRoot][1];
444 uint32_t clockRootMuxValue = (CCM_TUPLE_REG(CCM, clockRootMuxTuple) & CCM_TUPLE_MASK(clockRootMuxTuple)) >>
445 CCM_TUPLE_SHIFT(clockRootMuxTuple);
446 clock_name_t clockSourceName;
447
448 clockSourceName = clockRootSourceArray[(uint8_t)clockRoot][clockRootMuxValue];
449
450 assert(clockSourceName != kCLOCK_NoneName);
451
452 freq = CLOCK_GetFreq(clockSourceName);
453
454 if (clockRootPreDivTuple != kCLOCK_NonePreDiv)
455 {
456 freq /= ((CCM_TUPLE_REG(CCM, clockRootPreDivTuple) & CCM_TUPLE_MASK(clockRootPreDivTuple)) >>
457 CCM_TUPLE_SHIFT(clockRootPreDivTuple)) +
458 1UL;
459 }
460
461 freq /= ((CCM_TUPLE_REG(CCM, clockRootPostDivTuple) & CCM_TUPLE_MASK(clockRootPostDivTuple)) >>
462 CCM_TUPLE_SHIFT(clockRootPostDivTuple)) +
463 1UL;
464
465 return freq;
466}
467
468/*! brief Enable USB HS clock.
469 *
470 * This function only enables the access to USB HS prepheral, upper layer
471 * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
472 * clock to use USB HS.
473 *
474 * param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused.
475 * param freq USB HS does not care about the clock source, so this parameter is ignored.
476 * retval true The clock is set successfully.
477 * retval false The clock source is invalid to get proper USB HS clock.
478 */
479bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
480{
481 uint32_t i;
482 CCM->CCGR6 |= CCM_CCGR6_CG0_MASK;
483 USB->USBCMD |= USBHS_USBCMD_RST_MASK;
484
485 /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/
486 for (i = 0; i < 400000UL; i++)
487 {
488 __ASM("nop");
489 }
490 PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) |
491 (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK);
492 return true;
493}
494
495/*! brief Enable USB HS PHY PLL clock.
496 *
497 * This function enables the internal 480MHz USB PHY PLL clock.
498 *
499 * param src USB HS PHY PLL clock source.
500 * param freq The frequency specified by src.
501 * retval true The clock is set successfully.
502 * retval false The clock source is invalid to get proper USB HS clock.
503 */
504bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
505{
506 const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
507 if ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK) != 0UL)
508 {
509 CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
510 }
511 else
512 {
513 CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
514 }
515 USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */
516 USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK;
517
518 USBPHY->PWD = 0;
519 USBPHY->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK |
520 USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK;
521 return true;
522}
523
524/*! brief Disable USB HS PHY PLL clock.
525 *
526 * This function disables USB HS PHY PLL clock.
527 */
528void CLOCK_DisableUsbhs0PhyPllClock(void)
529{
530 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
531 USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
532}
533
534/*!
535 * brief Initialize the System PLL.
536 *
537 * This function initializes the System PLL with specific settings
538 *
539 * param config Configuration to set to PLL.
540 */
541void CLOCK_InitSysPll(const clock_sys_pll_config_t *config)
542{
543 /* Bypass PLL first */
544 CCM_ANALOG->PLL_SYS = (CCM_ANALOG->PLL_SYS & (~CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)) |
545 CCM_ANALOG_PLL_SYS_BYPASS_MASK | CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(config->src);
546
547 CCM_ANALOG->PLL_SYS =
548 (CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) |
549 CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider);
550
551 /* Initialize the fractional mode */
552 CCM_ANALOG->PLL_SYS_NUM = CCM_ANALOG_PLL_SYS_NUM_A(config->numerator);
553 CCM_ANALOG->PLL_SYS_DENOM = CCM_ANALOG_PLL_SYS_DENOM_B(config->denominator);
554
555 /* Initialize the spread spectrum mode */
556 CCM_ANALOG->PLL_SYS_SS = CCM_ANALOG_PLL_SYS_SS_STEP(config->ss_step) |
557 CCM_ANALOG_PLL_SYS_SS_ENABLE(config->ss_enable) |
558 CCM_ANALOG_PLL_SYS_SS_STOP(config->ss_stop);
559
560 while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0UL)
561 {
562 }
563
564 /* Disable Bypass */
565 CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_BYPASS_MASK;
566}
567
568/*!
569 * brief De-initialize the System PLL.
570 */
571void CLOCK_DeinitSysPll(void)
572{
573 CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_POWERDOWN_MASK;
574}
575
576/*!
577 * brief Initialize the USB1 PLL.
578 *
579 * This function initializes the USB1 PLL with specific settings
580 *
581 * param config Configuration to set to PLL.
582 */
583void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config)
584{
585 /* Bypass PLL first */
586 CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)) |
587 CCM_ANALOG_PLL_USB1_BYPASS_MASK | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(config->src);
588
589 CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)) |
590 CCM_ANALOG_PLL_USB1_ENABLE_MASK | CCM_ANALOG_PLL_USB1_POWER_MASK |
591 CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider);
592
593 while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0UL)
594 {
595 }
596
597 /* Disable Bypass */
598 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK;
599}
600
601/*!
602 * brief Deinitialize the USB1 PLL.
603 */
604void CLOCK_DeinitUsb1Pll(void)
605{
606 CCM_ANALOG->PLL_USB1 = 0U;
607}
608
609/*!
610 * brief Initializes the Audio PLL.
611 *
612 * This function initializes the Audio PLL with specific settings
613 *
614 * param config Configuration to set to PLL.
615 */
616void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)
617{
618 uint32_t pllAudio;
619 uint32_t misc2 = 0;
620
621 /* Bypass PLL first */
622 CCM_ANALOG->PLL_AUDIO = (CCM_ANALOG->PLL_AUDIO & (~CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)) |
623 CCM_ANALOG_PLL_AUDIO_BYPASS_MASK | CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(config->src);
624
625 CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator);
626 CCM_ANALOG->PLL_AUDIO_DENOM = CCM_ANALOG_PLL_AUDIO_DENOM_B(config->denominator);
627
628 /*
629 * Set post divider:
630 *
631 * ------------------------------------------------------------------------
632 * | config->postDivider | PLL_AUDIO[POST_DIV_SELECT] | MISC2[AUDIO_DIV] |
633 * ------------------------------------------------------------------------
634 * | 1 | 2 | 0 |
635 * ------------------------------------------------------------------------
636 * | 2 | 1 | 0 |
637 * ------------------------------------------------------------------------
638 * | 4 | 2 | 3 |
639 * ------------------------------------------------------------------------
640 * | 8 | 1 | 3 |
641 * ------------------------------------------------------------------------
642 * | 16 | 0 | 3 |
643 * ------------------------------------------------------------------------
644 */
645 pllAudio =
646 (CCM_ANALOG->PLL_AUDIO & (~(CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK | CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK))) |
647 CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(config->loopDivider);
648
649 switch (config->postDivider)
650 {
651 case 16:
652 pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0);
653 misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
654 break;
655
656 case 8:
657 pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1);
658 misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
659 break;
660
661 case 4:
662 pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2);
663 misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
664 break;
665
666 case 2:
667 pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1);
668 break;
669
670 default:
671 pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2);
672 break;
673 }
674
675 CCM_ANALOG->MISC2 =
676 (CCM_ANALOG->MISC2 & ~(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)) | misc2;
677
678 CCM_ANALOG->PLL_AUDIO = pllAudio;
679
680 while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0UL)
681 {
682 }
683
684 /* Disable Bypass */
685 CCM_ANALOG->PLL_AUDIO &= ~CCM_ANALOG_PLL_AUDIO_BYPASS_MASK;
686}
687
688/*!
689 * brief De-initialize the Audio PLL.
690 */
691void CLOCK_DeinitAudioPll(void)
692{
693 CCM_ANALOG->PLL_AUDIO = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK;
694}
695
696/*!
697 * brief Initialize the ENET PLL.
698 *
699 * This function initializes the ENET PLL with specific settings.
700 *
701 * param config Configuration to set to PLL.
702 */
703void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config)
704{
705 uint32_t enet_pll = CCM_ANALOG_PLL_ENET_DIV_SELECT(config->loopDivider);
706
707 CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)) |
708 CCM_ANALOG_PLL_ENET_BYPASS_MASK | CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(config->src);
709
710 if (config->enableClkOutput)
711 {
712 enet_pll |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
713 }
714
715 if (config->enableClkOutput25M)
716 {
717 enet_pll |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
718 }
719
720 if (config->enableClkOutput500M)
721 {
722 enet_pll |= CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK;
723 }
724
725 CCM_ANALOG->PLL_ENET =
726 (CCM_ANALOG->PLL_ENET & (~(CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) |
727 enet_pll;
728
729 /* Wait for stable */
730 while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0UL)
731 {
732 }
733
734 /* Disable Bypass */
735 CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK;
736}
737
738/*!
739 * brief Deinitialize the ENET PLL.
740 *
741 * This function disables the ENET PLL.
742 */
743void CLOCK_DeinitEnetPll(void)
744{
745 CCM_ANALOG->PLL_ENET = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK;
746}
747
748/*!
749 * brief Get current PLL output frequency.
750 *
751 * This function get current output frequency of specific PLL
752 *
753 * param pll pll name to get frequency.
754 * return The PLL output frequency in hertz.
755 */
756uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
757{
758 uint32_t freq;
759 uint32_t divSelect;
760 clock_64b_t freqTmp;
761
762 const uint32_t enetRefClkFreq[] = {
763 25000000U, /* 25M */
764 50000000U, /* 50M */
765 100000000U, /* 100M */
766 125000000U /* 125M */
767 };
768
769 /* check if PLL is enabled */
770 if (!CLOCK_IsPllEnabled(CCM_ANALOG, pll))
771 {
772 return 0U;
773 }
774
775 /* get pll reference clock */
776 freq = CLOCK_GetPllBypassRefClk(CCM_ANALOG, pll);
777
778 /* check if pll is bypassed */
779 if (CLOCK_IsPllBypassed(CCM_ANALOG, pll))
780 {
781 return freq;
782 }
783
784 switch (pll)
785 {
786 case kCLOCK_PllSys:
787 /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
788 freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_SYS_NUM)));
789 freqTmp /= ((clock_64b_t)(CCM_ANALOG->PLL_SYS_DENOM));
790
791 if ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) != 0UL)
792 {
793 freq *= 22U;
794 }
795 else
796 {
797 freq *= 20U;
798 }
799
800 freq += (uint32_t)freqTmp;
801 break;
802
803 case kCLOCK_PllUsb1:
804 freq = (freq * (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0UL) ? 22U : 20U));
805 break;
806
807 case kCLOCK_PllAudio:
808 /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
809 divSelect =
810 (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT;
811
812 freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_NUM)));
813 freqTmp /= ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_DENOM));
814
815 freq = freq * divSelect + (uint32_t)freqTmp;
816
817 /* AUDIO PLL output = PLL output frequency / POSTDIV. */
818
819 /*
820 * Post divider:
821 *
822 * PLL_AUDIO[POST_DIV_SELECT]:
823 * 0x00: 4
824 * 0x01: 2
825 * 0x02: 1
826 *
827 * MISC2[AUDO_DIV]:
828 * 0x00: 1
829 * 0x01: 2
830 * 0x02: 1
831 * 0x03: 4
832 */
833 switch (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
834 {
835 case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0U):
836 freq = freq >> 2U;
837 break;
838
839 case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1U):
840 freq = freq >> 1U;
841 break;
842
843 case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2U):
844 freq = freq >> 0U;
845 break;
846
847 default:
848 assert(false);
849 break;
850 }
851
852 switch (CCM_ANALOG->MISC2 & (CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK))
853 {
854 case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(1) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1):
855 freq >>= 2U;
856 break;
857
858 case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(0) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1):
859 freq >>= 1U;
860 break;
861
862 case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(0) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(0):
863 case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(1) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(0):
864 freq >>= 0U;
865 break;
866
867 default:
868 assert(false);
869 break;
870 }
871 break;
872
873 case kCLOCK_PllEnet:
874 divSelect =
875 (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT;
876 freq = enetRefClkFreq[divSelect];
877 break;
878
879 case kCLOCK_PllEnet25M:
880 /* ref_enetpll1 if fixed at 25MHz. */
881 freq = 25000000UL;
882 break;
883
884 case kCLOCK_PllEnet500M:
885 /* PLL6 is fixed at 25MHz. */
886 freq = 500000000UL;
887 break;
888
889 default:
890 freq = 0U;
891 break;
892 }
893
894 return freq;
895}
896
897/*!
898 * brief Initialize the System PLL PFD.
899 *
900 * This function initializes the System PLL PFD. During new value setting,
901 * the clock output is disabled to prevent glitch.
902 *
903 * param pfd Which PFD clock to enable.
904 * param pfdFrac The PFD FRAC value.
905 * note It is recommended that PFD settings are kept between 12-35.
906 */
907void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac)
908{
909 uint32_t pfdIndex = (uint32_t)pfd;
910 uint32_t pfd528;
911
912 pfd528 = CCM_ANALOG->PFD_528 &
913 ~(((uint32_t)((uint32_t)CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK | (uint32_t)CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)
914 << (8UL * pfdIndex)));
915
916 /* Disable the clock output first. */
917 CCM_ANALOG->PFD_528 = pfd528 | ((uint32_t)CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8UL * pfdIndex));
918
919 /* Set the new value and enable output. */
920 CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_FRAC(pfdFrac) << (8UL * pfdIndex));
921}
922
923/*!
924 * brief De-initialize the System PLL PFD.
925 *
926 * This function disables the System PLL PFD.
927 *
928 * param pfd Which PFD clock to disable.
929 */
930void CLOCK_DeinitSysPfd(clock_pfd_t pfd)
931{
932 CCM_ANALOG->PFD_528 |= (uint32_t)CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8UL * (uint32_t)pfd);
933}
934
935/*!
936 * brief Initialize the USB1 PLL PFD.
937 *
938 * This function initializes the USB1 PLL PFD. During new value setting,
939 * the clock output is disabled to prevent glitch.
940 *
941 * param pfd Which PFD clock to enable.
942 * param pfdFrac The PFD FRAC value.
943 * note It is recommended that PFD settings are kept between 12-35.
944 */
945void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac)
946{
947 uint32_t pfdIndex = (uint32_t)pfd;
948 uint32_t pfd480;
949
950 pfd480 = CCM_ANALOG->PFD_480 &
951 ~((uint32_t)((uint32_t)CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK | (uint32_t)CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)
952 << (8UL * pfdIndex));
953
954 /* Disable the clock output first. */
955 CCM_ANALOG->PFD_480 = pfd480 | ((uint32_t)CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8UL * pfdIndex));
956
957 /* Set the new value and enable output. */
958 CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_FRAC(pfdFrac) << (8UL * pfdIndex));
959}
960
961/*!
962 * brief De-initialize the USB1 PLL PFD.
963 *
964 * This function disables the USB1 PLL PFD.
965 *
966 * param pfd Which PFD clock to disable.
967 */
968void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd)
969{
970 CCM_ANALOG->PFD_480 |= (uint32_t)CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8UL * (uint32_t)pfd);
971}
972
973/*!
974 * brief Get current System PLL PFD output frequency.
975 *
976 * This function get current output frequency of specific System PLL PFD
977 *
978 * param pfd pfd name to get frequency.
979 * return The PFD output frequency in hertz.
980 */
981uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd)
982{
983 uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllSys);
984
985 switch (pfd)
986 {
987 case kCLOCK_Pfd0:
988 freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT);
989 break;
990
991 case kCLOCK_Pfd1:
992 freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT);
993 break;
994
995 case kCLOCK_Pfd2:
996 freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT);
997 break;
998
999 case kCLOCK_Pfd3:
1000 freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT);
1001 break;
1002
1003 default:
1004 freq = 0U;
1005 break;
1006 }
1007 freq *= 18U;
1008
1009 return freq;
1010}
1011
1012/*!
1013 * brief Get current USB1 PLL PFD output frequency.
1014 *
1015 * This function get current output frequency of specific USB1 PLL PFD
1016 *
1017 * param pfd pfd name to get frequency.
1018 * return The PFD output frequency in hertz.
1019 */
1020uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd)
1021{
1022 uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1);
1023
1024 switch (pfd)
1025 {
1026 case kCLOCK_Pfd0:
1027 freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT);
1028 break;
1029
1030 case kCLOCK_Pfd1:
1031 freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT);
1032 break;
1033
1034 case kCLOCK_Pfd2:
1035 freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT);
1036 break;
1037
1038 case kCLOCK_Pfd3:
1039 freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT);
1040 break;
1041
1042 default:
1043 freq = 0U;
1044 break;
1045 }
1046 freq *= 18U;
1047
1048 return freq;
1049}
1050
1051/*!
1052 * brief Set the clock source and the divider of the clock output1.
1053 *
1054 * param selection The clock source to be output, please refer to clock_output1_selection_t.
1055 * param divider The divider of the output clock signal, please refer to clock_output_divider_t.
1056 */
1057void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider)
1058{
1059 uint32_t tmp32;
1060
1061 tmp32 = CCM->CCOSR;
1062 if (selection == kCLOCK_DisableClockOutput1)
1063 {
1064 tmp32 &= ~CCM_CCOSR_CLKO1_EN_MASK;
1065 }
1066 else
1067 {
1068 tmp32 |= CCM_CCOSR_CLKO1_EN_MASK;
1069 tmp32 &= ~(CCM_CCOSR_CLKO1_SEL_MASK | CCM_CCOSR_CLKO1_DIV_MASK);
1070 tmp32 |= CCM_CCOSR_CLKO1_SEL(selection) | CCM_CCOSR_CLKO1_DIV(divider);
1071 }
1072 CCM->CCOSR = tmp32;
1073}
1074
1075/*!
1076 * brief Set the clock source and the divider of the clock output2.
1077 *
1078 * param selection The clock source to be output, please refer to clock_output2_selection_t.
1079 * param divider The divider of the output clock signal, please refer to clock_output_divider_t.
1080 */
1081void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider)
1082{
1083 uint32_t tmp32;
1084
1085 tmp32 = CCM->CCOSR;
1086 if (selection == kCLOCK_DisableClockOutput2)
1087 {
1088 tmp32 &= CCM_CCOSR_CLKO2_EN_MASK;
1089 }
1090 else
1091 {
1092 tmp32 |= CCM_CCOSR_CLKO2_EN_MASK;
1093 tmp32 &= ~(CCM_CCOSR_CLKO2_SEL_MASK | CCM_CCOSR_CLKO2_DIV_MASK);
1094 tmp32 |= CCM_CCOSR_CLKO2_SEL(selection) | CCM_CCOSR_CLKO2_DIV(divider);
1095 }
1096
1097 CCM->CCOSR = tmp32;
1098}
1099
1100/*!
1101 * brief Get the frequency of clock output1 clock signal.
1102 *
1103 * return The frequency of clock output1 clock signal.
1104 */
1105uint32_t CLOCK_GetClockOutCLKO1Freq(void)
1106{
1107 uint32_t freq = 0U;
1108 uint32_t tmp32;
1109
1110 tmp32 = CCM->CCOSR;
1111
1112 if ((tmp32 & CCM_CCOSR_CLKO1_EN_MASK) != 0UL)
1113 {
1114 switch ((tmp32 & CCM_CCOSR_CLKO1_SEL_MASK) >> CCM_CCOSR_CLKO1_SEL_SHIFT)
1115 {
1116 case (uint32_t)kCLOCK_OutputPllUsb1Sw:
1117 freq = CLOCK_GetPllUsb1SWFreq() / 2UL;
1118 break;
1119 case (uint32_t)kCLOCK_OutputPllSys:
1120 freq = CLOCK_GetPllFreq(kCLOCK_PllSys) / 2UL;
1121 break;
1122 case (uint32_t)kCLOCK_OutputPllENET500M:
1123 freq = CLOCK_GetPllFreq(kCLOCK_PllEnet500M) / 2UL;
1124 break;
1125 case (uint32_t)kCLOCK_OutputSemcClk:
1126 freq = CLOCK_GetSemcFreq();
1127 break;
1128 case (uint32_t)kCLOCK_OutputAhbClk:
1129 freq = CLOCK_GetAhbFreq();
1130 break;
1131 case (uint32_t)kCLOCK_OutputIpgClk:
1132 freq = CLOCK_GetIpgFreq();
1133 break;
1134 case (uint32_t)kCLOCK_OutputPerClk:
1135 freq = CLOCK_GetPerClkFreq();
1136 break;
1137 case (uint32_t)kCLOCK_OutputPll4MainClk:
1138 freq = CLOCK_GetPllFreq(kCLOCK_PllAudio);
1139 break;
1140 default:
1141 /* This branch should never be hit. */
1142 break;
1143 }
1144
1145 freq /= (((tmp32 & CCM_CCOSR_CLKO1_DIV_MASK) >> CCM_CCOSR_CLKO1_DIV_SHIFT) + 1U);
1146 }
1147 else
1148 {
1149 freq = 0UL;
1150 }
1151
1152 return freq;
1153}
1154
1155/*!
1156 * brief Get the frequency of clock output2 clock signal.
1157 *
1158 * return The frequency of clock output2 clock signal.
1159 */
1160uint32_t CLOCK_GetClockOutClkO2Freq(void)
1161{
1162 uint32_t freq = 0U;
1163 uint32_t tmp32;
1164
1165 tmp32 = CCM->CCOSR;
1166
1167 if ((tmp32 & CCM_CCOSR_CLKO2_EN_MASK) != 0UL)
1168 {
1169 switch ((tmp32 & CCM_CCOSR_CLKO2_SEL_MASK) >> CCM_CCOSR_CLKO2_SEL_SHIFT)
1170 {
1171 case (uint32_t)kCLOCK_OutputUsdhc1Clk:
1172 freq = CLOCK_GetClockRootFreq(kCLOCK_Usdhc1ClkRoot);
1173 break;
1174 case (uint32_t)kCLOCK_OutputLpi2cClk:
1175 freq = CLOCK_GetClockRootFreq(kCLOCK_Lpi2cClkRoot);
1176 break;
1177 case (uint32_t)kCLOCK_OutputOscClk:
1178 freq = CLOCK_GetOscFreq();
1179 break;
1180 case (uint32_t)kCLOCK_OutputLpspiClk:
1181 freq = CLOCK_GetClockRootFreq(kCLOCK_LpspiClkRoot);
1182 break;
1183 case (uint32_t)kCLOCK_OutputUsdhc2Clk:
1184 freq = CLOCK_GetClockRootFreq(kCLOCK_Usdhc2ClkRoot);
1185 break;
1186 case (uint32_t)kCLOCK_OutputSai1Clk:
1187 freq = CLOCK_GetClockRootFreq(kCLOCK_Sai1ClkRoot);
1188 break;
1189 case (uint32_t)kCLOCK_OutputSai2Clk:
1190 freq = CLOCK_GetClockRootFreq(kCLOCK_Sai2ClkRoot);
1191 break;
1192 case (uint32_t)kCLOCK_OutputSai3Clk:
1193 freq = CLOCK_GetClockRootFreq(kCLOCK_Sai3ClkRoot);
1194 break;
1195 case (uint32_t)kCLOCK_OutputTraceClk:
1196 freq = CLOCK_GetClockRootFreq(kCLOCK_TraceClkRoot);
1197 break;
1198 case (uint32_t)kCLOCK_OutputCanClk:
1199 freq = CLOCK_GetClockRootFreq(kCLOCK_CanClkRoot);
1200 break;
1201 case (uint32_t)kCLOCK_OutputFlexspiClk:
1202 freq = CLOCK_GetClockRootFreq(kCLOCK_FlexspiClkRoot);
1203 break;
1204 case (uint32_t)kCLOCK_OutputUartClk:
1205 freq = CLOCK_GetClockRootFreq(kCLOCK_UartClkRoot);
1206 break;
1207 case (uint32_t)kCLOCK_OutputSpdif0Clk:
1208 freq = CLOCK_GetClockRootFreq(kCLOCK_SpdifClkRoot);
1209 break;
1210 default:
1211 /* This branch should never be hit. */
1212 break;
1213 }
1214
1215 freq /= (((tmp32 & CCM_CCOSR_CLKO2_DIV_MASK) >> CCM_CCOSR_CLKO2_DIV_SHIFT) + 1U);
1216 }
1217 else
1218 {
1219 freq = 0UL;
1220 }
1221
1222 return freq;
1223}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_clock.h
new file mode 100644
index 000000000..3e7ba39ef
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_clock.h
@@ -0,0 +1,1567 @@
1/*
2 * Copyright 2018 - 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_common.h"
12
13/*! @addtogroup clock */
14/*! @{ */
15
16/*! @file */
17
18/*******************************************************************************
19 * Configurations
20 ******************************************************************************/
21
22/*! @brief Configure whether driver controls clock
23 *
24 * When set to 0, peripheral drivers will enable clock in initialize function
25 * and disable clock in de-initialize function. When set to 1, peripheral
26 * driver will not control the clock, application could control the clock out of
27 * the driver.
28 *
29 * @note All drivers share this feature switcher. If it is set to 1, application
30 * should handle clock enable and disable for all drivers.
31 */
32#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
33#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
34#endif
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*! @name Driver version */
41/*@{*/
42/*! @brief CLOCK driver version 2.4.0. */
43#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
44
45/* Definition for delay API in clock driver, users can redefine it to the real application. */
46#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
47#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (500000000UL)
48#endif
49
50/* analog pll definition */
51#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
52#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
53#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
54
55/*@}*/
56
57/*!
58 * @brief CCM registers offset.
59 */
60#define CCSR_OFFSET 0x0C
61#define CBCDR_OFFSET 0x14
62#define CBCMR_OFFSET 0x18
63#define CSCMR1_OFFSET 0x1C
64#define CSCMR2_OFFSET 0x20
65#define CSCDR1_OFFSET 0x24
66#define CDCDR_OFFSET 0x30
67#define CSCDR2_OFFSET 0x38
68#define CACRR_OFFSET 0x10
69#define CS1CDR_OFFSET 0x28
70#define CS2CDR_OFFSET 0x2C
71
72/*!
73 * @brief CCM Analog registers offset.
74 */
75#define PLL_SYS_OFFSET 0x30
76#define PLL_USB1_OFFSET 0x10
77#define PLL_AUDIO_OFFSET 0x70
78#define PLL_ENET_OFFSET 0xE0
79
80#define CCM_TUPLE(reg, shift, mask, busyShift) \
81 (int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
82#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + (((uint32_t)tuple) & 0xFFU))))
83#define CCM_TUPLE_SHIFT(tuple) ((((uint32_t)tuple) >> 8U) & 0x1FU)
84#define CCM_TUPLE_MASK(tuple) \
85 ((uint32_t)(((((uint32_t)tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))
86#define CCM_TUPLE_BUSY_SHIFT(tuple) ((((uint32_t)tuple) >> 26U) & 0x3FU)
87
88#define CCM_NO_BUSY_WAIT (0x20U)
89
90/*!
91 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
92 */
93#define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFU) << 16U) | (shift))
94#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)(tuple)) & 0x1FU)
95#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
96 (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))
97#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
98
99#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
100#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
101#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
102
103/* Definition for delay API in clock driver, users can redefine it to the real application. */
104#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
105#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (500000000UL)
106#endif
107
108/* Definition for ERRATA 50235 check */
109#if (defined(FSL_FEATURE_CCM_HAS_ERRATA_50235) && FSL_FEATURE_CCM_HAS_ERRATA_50235)
110#define CAN_CLOCK_CHECK_NO_AFFECTS \
111 ((CCM_CSCMR2_CAN_CLK_SEL(2U) != (CCM->CSCMR2 & CCM_CSCMR2_CAN_CLK_SEL_MASK)) || \
112 (CCM_CCGR5_CG12(0) != (CCM->CCGR5 & CCM_CCGR5_CG12_MASK)))
113#endif /* FSL_FEATURE_CCM_HAS_ERRATA_50235 */
114/*!
115 * @brief clock1PN frequency.
116 */
117#define CLKPN_FREQ 0U
118
119/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency.
120 *
121 * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the
122 * function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
123 * if XTAL is 24MHz,
124 * @code
125 * CLOCK_InitExternalClk(false);
126 * CLOCK_SetXtalFreq(240000000);
127 * @endcode
128 */
129extern volatile uint32_t g_xtalFreq;
130
131/*! @brief External RTC XTAL (32K OSC) clock frequency.
132 *
133 * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the
134 * function CLOCK_SetRtcXtalFreq to set the value in to clock driver.
135 */
136extern volatile uint32_t g_rtcXtalFreq;
137
138/* For compatible with other platforms */
139#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq
140#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq
141
142/*! @brief Clock ip name array for ADC. */
143#define ADC_CLOCKS \
144 { \
145 kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \
146 }
147
148/*! @brief Clock ip name array for AOI. */
149#define AOI_CLOCKS \
150 { \
151 kCLOCK_Aoi \
152 }
153
154/*! @brief Clock ip name array for BEE. */
155#define BEE_CLOCKS \
156 { \
157 kCLOCK_Bee \
158 }
159
160/*! @brief Clock ip name array for CMP. */
161#define CMP_CLOCKS \
162 { \
163 kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
164 }
165
166/*! @brief Clock ip name array for DCDC. */
167#define DCDC_CLOCKS \
168 { \
169 kCLOCK_Dcdc \
170 }
171
172/*! @brief Clock ip name array for DCP. */
173#define DCP_CLOCKS \
174 { \
175 kCLOCK_Dcp \
176 }
177
178/*! @brief Clock ip name array for DMAMUX_CLOCKS. */
179#define DMAMUX_CLOCKS \
180 { \
181 kCLOCK_Dma \
182 }
183
184/*! @brief Clock ip name array for DMA. */
185#define EDMA_CLOCKS \
186 { \
187 kCLOCK_Dma \
188 }
189
190/*! @brief Clock ip name array for ENC. */
191#define ENC_CLOCKS \
192 { \
193 kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2 \
194 }
195
196/*! @brief Clock ip name array for ENET. */
197#define ENET_CLOCKS \
198 { \
199 kCLOCK_Enet \
200 }
201
202/*! @brief Clock ip name array for EWM. */
203#define EWM_CLOCKS \
204 { \
205 kCLOCK_Ewm0 \
206 }
207
208/*! @brief Clock ip name array for FLEXCAN. */
209#define FLEXCAN_CLOCKS \
210 { \
211 kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \
212 }
213
214/*! @brief Clock ip name array for FLEXCAN Peripheral clock. */
215#define FLEXCAN_PERIPH_CLOCKS \
216 { \
217 kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \
218 }
219
220/*! @brief Clock ip name array for FLEXIO. */
221#define FLEXIO_CLOCKS \
222 { \
223 kCLOCK_IpInvalid, kCLOCK_Flexio1 \
224 }
225
226/*! @brief Clock ip name array for FLEXRAM. */
227#define FLEXRAM_CLOCKS \
228 { \
229 kCLOCK_FlexRam \
230 }
231
232/*! @brief Clock ip name array for FLEXSPI. */
233#define FLEXSPI_CLOCKS \
234 { \
235 kCLOCK_FlexSpi \
236 }
237
238/*! @brief Clock ip name array for FLEXSPI EXSC. */
239#define FLEXSPI_EXSC_CLOCKS \
240 { \
241 kCLOCK_FlexSpiExsc \
242 }
243
244/*! @brief Clock ip name array for GPIO. */
245#define GPIO_CLOCKS \
246 { \
247 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_IpInvalid, kCLOCK_Gpio5 \
248 }
249
250/*! @brief Clock ip name array for GPT. */
251#define GPT_CLOCKS \
252 { \
253 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
254 }
255
256/*! @brief Clock ip name array for KPP. */
257#define KPP_CLOCKS \
258 { \
259 kCLOCK_Kpp \
260 }
261
262/*! @brief Clock ip name array for LPI2C. */
263#define LPI2C_CLOCKS \
264 { \
265 kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \
266 }
267
268/*! @brief Clock ip name array for LPSPI. */
269#define LPSPI_CLOCKS \
270 { \
271 kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \
272 }
273
274/*! @brief Clock ip name array for LPUART. */
275#define LPUART_CLOCKS \
276 { \
277 kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \
278 kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \
279 }
280
281/*! @brief Clock ip name array for OCRAM EXSC. */
282#define OCRAM_EXSC_CLOCKS \
283 { \
284 kCLOCK_OcramExsc \
285 }
286
287/*! @brief Clock ip name array for PIT. */
288#define PIT_CLOCKS \
289 { \
290 kCLOCK_Pit \
291 }
292
293/*! @brief Clock ip name array for PWM. */
294#define PWM_CLOCKS \
295 { \
296 {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
297 {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, \
298 { \
299 kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2 \
300 } \
301 }
302
303/*! @brief Clock ip name array for RTWDOG. */
304#define RTWDOG_CLOCKS \
305 { \
306 kCLOCK_Wdog3 \
307 }
308
309/*! @brief Clock ip name array for SAI. */
310#define SAI_CLOCKS \
311 { \
312 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \
313 }
314
315/*! @brief Clock ip name array for SEMC. */
316#define SEMC_CLOCKS \
317 { \
318 kCLOCK_Semc \
319 }
320
321/*! @brief Clock ip name array for SEMC EXSC. */
322#define SEMC_EXSC_CLOCKS \
323 { \
324 kCLOCK_SemcExsc \
325 }
326
327/*! @brief Clock ip name array for QTIMER. */
328#define TMR_CLOCKS \
329 { \
330 kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2 \
331 }
332
333/*! @brief Clock ip name array for TRNG. */
334#define TRNG_CLOCKS \
335 { \
336 kCLOCK_Trng \
337 }
338
339/*! @brief Clock ip name array for WDOG. */
340#define WDOG_CLOCKS \
341 { \
342 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \
343 }
344
345/*! @brief Clock ip name array for USDHC. */
346#define USDHC_CLOCKS \
347 { \
348 kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
349 }
350
351/*! @brief Clock ip name array for SPDIF. */
352#define SPDIF_CLOCKS \
353 { \
354 kCLOCK_Spdif \
355 }
356
357/*! @brief Clock ip name array for XBARA. */
358#define XBARA_CLOCKS \
359 { \
360 kCLOCK_Xbar1 \
361 }
362
363/*! @brief Clock ip name array for XBARB. */
364#define XBARB_CLOCKS \
365 { \
366 kCLOCK_Xbar2 \
367 }
368
369#define CLOCK_SOURCE_NONE (0xFFU)
370
371#define CLOCK_ROOT_SOUCE \
372 { \
373 {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /*!< USDHC1 clock root. */ \
374 {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /*!< USDHC2 clock root. */ \
375 {kCLOCK_SemcClk, kCLOCK_Usb1SwClk, kCLOCK_SysPllPfd2Clk, \
376 kCLOCK_Usb1PllPfd0Clk}, /*!< FLEXSPI clock root. */ \
377 {kCLOCK_Usb1PllPfd1Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_SysPllClk, \
378 kCLOCK_SysPllPfd2Clk}, /*!< LPSPI clock root. */ \
379 {kCLOCK_SysPllClk, kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, \
380 kCLOCK_SysPllPfd1Clk}, /*!< Trace clock root. */ \
381 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, kCLOCK_AudioPllClk, kCLOCK_NoneName}, /*!< SAI1 clock root. */ \
382 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, kCLOCK_AudioPllClk, kCLOCK_NoneName}, /*!< SAI2 clock root. */ \
383 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, kCLOCK_AudioPllClk, kCLOCK_NoneName}, /*!< SAI3 clock root. */ \
384 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_NoneName, kCLOCK_NoneName}, /*!< LPI2C clock root. */ \
385 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_Usb1Sw80MClk, kCLOCK_NoneName}, /*!< CAN clock root. */ \
386 {kCLOCK_Usb1Sw80MClk, kCLOCK_OscClk, kCLOCK_NoneName, kCLOCK_NoneName}, /*!< UART clock root. */ \
387 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, kCLOCK_Usb1SwClk}, /*!< SPDIF clock root. */ \
388 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, \
389 kCLOCK_Usb1SwClk}, /*!< FLEXIO1 clock root. */ \
390 }
391
392#define CLOCK_ROOT_MUX_TUPLE \
393 { \
394 kCLOCK_Usdhc1Mux, kCLOCK_Usdhc2Mux, kCLOCK_FlexspiMux, kCLOCK_LpspiMux, kCLOCK_TraceMux, kCLOCK_Sai1Mux, \
395 kCLOCK_Sai2Mux, kCLOCK_Sai3Mux, kCLOCK_Lpi2cMux, kCLOCK_CanMux, kCLOCK_UartMux, kCLOCK_SpdifMux, \
396 kCLOCK_Flexio1Mux, \
397 }
398
399#define CLOCK_ROOT_NONE_PRE_DIV 0UL
400
401#define CLOCK_ROOT_DIV_TUPLE \
402 { \
403 {kCLOCK_NonePreDiv, kCLOCK_Usdhc1Div}, /*!< USDHC1 clock root. */ \
404 {kCLOCK_NonePreDiv, kCLOCK_Usdhc2Div}, /*!< USDHC2 clock root. */ \
405 {kCLOCK_NonePreDiv, kCLOCK_FlexspiDiv}, /*!< FLEXSPI clock root. */ \
406 {kCLOCK_NonePreDiv, kCLOCK_LpspiDiv}, /*!< LPSPI clock root. */ \
407 {kCLOCK_NonePreDiv, kCLOCK_TraceDiv}, /*!< Trace clock root. */ \
408 {kCLOCK_Sai1PreDiv, kCLOCK_Sai1Div}, /*!< SAI1 clock root. */ \
409 {kCLOCK_Sai2PreDiv, kCLOCK_Sai2Div}, /*!< SAI2 clock root. */ \
410 {kCLOCK_Sai3PreDiv, kCLOCK_Sai3Div}, /*!< SAI3 clock root. */ \
411 {kCLOCK_NonePreDiv, kCLOCK_Lpi2cDiv}, /*!< LPI2C clock root. */ \
412 {kCLOCK_NonePreDiv, kCLOCK_CanDiv}, /*!< CAN clock root. */ \
413 {kCLOCK_NonePreDiv, kCLOCK_UartDiv}, /*!< UART clock root. */ \
414 {kCLOCK_Spdif0PreDiv, kCLOCK_Spdif0Div}, /*!< SPDIF clock root. */ \
415 {kCLOCK_Flexio1PreDiv, kCLOCK_Flexio1Div}, /*!< FLEXIO1 clock root. */ \
416 }
417
418/*! @brief Clock name used to get clock frequency. */
419typedef enum _clock_name
420{
421 kCLOCK_CpuClk = 0x0U, /*!< CPU clock */
422 kCLOCK_AhbClk = 0x1U, /*!< AHB clock */
423 kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */
424 kCLOCK_IpgClk = 0x3U, /*!< IPG clock */
425 kCLOCK_PerClk = 0x4U, /*!< PER clock */
426
427 kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */
428 kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */
429
430 kCLOCK_Usb1PllClk = 0x7U, /*!< USB1PLLCLK. */
431 kCLOCK_Usb1PllPfd0Clk = 0x8U, /*!< USB1PLLPDF0CLK. */
432 kCLOCK_Usb1PllPfd1Clk = 0x9U, /*!< USB1PLLPFD1CLK. */
433 kCLOCK_Usb1PllPfd2Clk = 0xAU, /*!< USB1PLLPFD2CLK. */
434 kCLOCK_Usb1PllPfd3Clk = 0xBU, /*!< USB1PLLPFD3CLK. */
435 kCLOCK_Usb1SwClk = 0x15U, /*!< USB1PLLSWCLK */
436 kCLOCK_Usb1Sw60MClk = 0x16U, /*!< USB1PLLSw60MCLK */
437 kCLOCK_Usb1Sw80MClk = 0x1BU, /*!< USB1PLLSw80MCLK */
438
439 kCLOCK_SysPllClk = 0xCU, /*!< SYSPLLCLK. */
440 kCLOCK_SysPllPfd0Clk = 0xDU, /*!< SYSPLLPDF0CLK. */
441 kCLOCK_SysPllPfd1Clk = 0xEU, /*!< SYSPLLPFD1CLK. */
442 kCLOCK_SysPllPfd2Clk = 0xFU, /*!< SYSPLLPFD2CLK. */
443 kCLOCK_SysPllPfd3Clk = 0x10U, /*!< SYSPLLPFD3CLK. */
444
445 kCLOCK_EnetPllClk = 0x11U, /*!< Enet PLLCLK ref_enetpll. */
446 kCLOCK_EnetPll25MClk = 0x12U, /*!< Enet PLLCLK ref_enetpll25M. */
447 kCLOCK_EnetPll500MClk = 0x13U, /*!< Enet PLLCLK ref_enetpll500M. */
448
449 kCLOCK_AudioPllClk = 0x14U, /*!< Audio PLLCLK. */
450
451 kCLOCK_NoneName = CLOCK_SOURCE_NONE, /*!< None Clock Name. */
452} clock_name_t;
453
454#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */
455#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */
456
457/*!
458 * @brief CCM CCGR gate control for each module independently.
459 */
460typedef enum _clock_ip_name
461{
462 kCLOCK_IpInvalid = -1,
463
464 /* CCM CCGR0 */
465 kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */
466 kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */
467 kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2, Reserved */
468 kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */
469 kCLOCK_Sim_m_clk_r = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */
470 kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */
471 kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */
472 kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */
473 kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */
474 kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */
475 kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */
476 kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */
477 kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */
478 kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */
479 kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */
480 kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */
481
482 /* CCM CCGR1 */
483 kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */
484 kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */
485 kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*!< CCGR1, CG2 */
486 kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */
487 kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */
488 kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */
489 kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */
490 /*!< CCGR1, CG7, Reserved */
491 kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */
492 kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*!< CCGR1, CG9 */
493 kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */
494 kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */
495 kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */
496 kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */
497 kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */
498 kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */
499
500 /* CCM CCGR2 */
501 kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */
502 /*!< CCGR2, CG1, Reserved */
503 kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */
504 kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */
505 kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */
506 kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */
507 kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */
508 /*!< CCGR2, CG7, Reserved */
509 /*!< CCGR2, CG8, Reserved */
510 /*!< CCGR2, CG9, Reserved */
511 /*!< CCGR2, CG10, Reserved */
512 kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */
513 kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */
514 kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */
515 /*!< CCGR2, CG14, Reserved */
516 /*!< CCGR2, CG15, Reserved */
517
518 /* CCM CCGR3 */
519 /*!< CCGR3, CG0, Reserved */
520 kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */
521 kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */
522 kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */
523 kCLOCK_Aoi = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */
524 /*!< CCGR3, CG5, Reserved */
525 /*!< CCGR3, CG6, Reserved */
526 kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */
527 kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */
528 kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */
529 kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */
530 kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */
531 kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */
532 kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */
533 /*!< CCGR3, CG14, Reserved */
534 kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */
535
536 /* CCM CCGR4 */
537 kCLOCK_Sim_m7_clk_r = (4U << 8U) | CCM_CCGR4_CG0_SHIFT, /*!< CCGR4, CG0 */
538 kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */
539 kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */
540 kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */
541 kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */
542 kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5, Reserved */
543 kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */
544 kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */
545 kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */
546 kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */
547 /*!< CCGR4, CG10, Reserved */
548 /*!< CCGR4, CG11, Reserved */
549 kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */
550 kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */
551 /*!< CCGR4, CG14, Reserved */
552 /*!< CCGR4, CG15, Reserved */
553
554 /* CCM CCGR5 */
555 kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */
556 kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */
557 kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */
558 kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */
559 kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */
560 kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */
561 kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */
562 kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */
563 /*!< CCGR5, CG8, Reserved */
564 kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */
565 kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */
566 kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */
567 kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */
568 kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */
569 kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */
570 kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */
571
572 /* CCM CCGR6 */
573 kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */
574 kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */
575 kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */
576 kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */
577 kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */
578 kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */
579 kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */
580 kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */
581 kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */
582 kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */
583 kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */
584 kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */
585 kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */
586 kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */
587 kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */
588 /*!< CCGR6, CG15, Reserved */
589
590} clock_ip_name_t;
591
592/*! @brief OSC 24M sorce select */
593typedef enum _clock_osc
594{
595 kCLOCK_RcOsc = 0U, /*!< On chip OSC. */
596 kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */
597} clock_osc_t;
598
599/*! @brief Clock gate value */
600typedef enum _clock_gate_value
601{
602 kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */
603 kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */
604 kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */
605} clock_gate_value_t;
606
607/*! @brief System clock mode */
608typedef enum _clock_mode_t
609{
610 kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */
611 kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */
612 kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */
613} clock_mode_t;
614
615/*!
616 * @brief MUX control names for clock mux setting.
617 *
618 * These constants define the mux control names for clock mux setting.\n
619 * - 0:7: REG offset to CCM_BASE in bytes.
620 * - 8:15: Root clock setting bit field shift.
621 * - 16:31: Root clock setting bit field width.
622 */
623typedef enum _clock_mux
624{
625 kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET,
626 CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT,
627 CCM_CCSR_PLL3_SW_CLK_SEL_MASK,
628 CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */
629
630 kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
631 CCM_CBCDR_PERIPH_CLK_SEL_SHIFT,
632 CCM_CBCDR_PERIPH_CLK_SEL_MASK,
633 CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */
634 kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET,
635 CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT,
636 CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK,
637 CCM_NO_BUSY_WAIT), /*!< semc mux name */
638 kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET,
639 CCM_CBCDR_SEMC_CLK_SEL_SHIFT,
640 CCM_CBCDR_SEMC_CLK_SEL_MASK,
641 CCM_NO_BUSY_WAIT), /*!< semc mux name */
642
643 kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
644 CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT,
645 CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK,
646 CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */
647 kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET,
648 CCM_CBCMR_TRACE_CLK_SEL_SHIFT,
649 CCM_CBCMR_TRACE_CLK_SEL_MASK,
650 CCM_NO_BUSY_WAIT), /*!< trace mux name */
651 kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
652 CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT,
653 CCM_CBCMR_PERIPH_CLK2_SEL_MASK,
654 CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */
655 kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET,
656 CCM_CBCMR_LPSPI_CLK_SEL_SHIFT,
657 CCM_CBCMR_LPSPI_CLK_SEL_MASK,
658 CCM_NO_BUSY_WAIT), /*!< lpspi mux name */
659
660 kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
661 CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT,
662 CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK,
663 CCM_NO_BUSY_WAIT), /*!< flexspi mux name */
664 kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1_OFFSET,
665 CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT,
666 CCM_CSCMR1_USDHC2_CLK_SEL_MASK,
667 CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */
668 kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1_OFFSET,
669 CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT,
670 CCM_CSCMR1_USDHC1_CLK_SEL_MASK,
671 CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */
672 kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1_OFFSET,
673 CCM_CSCMR1_SAI3_CLK_SEL_SHIFT,
674 CCM_CSCMR1_SAI3_CLK_SEL_MASK,
675 CCM_NO_BUSY_WAIT), /*!< sai3 mux name */
676 kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1_OFFSET,
677 CCM_CSCMR1_SAI2_CLK_SEL_SHIFT,
678 CCM_CSCMR1_SAI2_CLK_SEL_MASK,
679 CCM_NO_BUSY_WAIT), /*!< sai2 mux name */
680 kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1_OFFSET,
681 CCM_CSCMR1_SAI1_CLK_SEL_SHIFT,
682 CCM_CSCMR1_SAI1_CLK_SEL_MASK,
683 CCM_NO_BUSY_WAIT), /*!< sai1 mux name */
684 kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET,
685 CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT,
686 CCM_CSCMR1_PERCLK_CLK_SEL_MASK,
687 CCM_NO_BUSY_WAIT), /*!< perclk mux name */
688
689 kCLOCK_Flexio1Mux = CCM_TUPLE(CSCMR2_OFFSET,
690 CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT,
691 CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK,
692 CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */
693 kCLOCK_CanMux = CCM_TUPLE(CSCMR2_OFFSET,
694 CCM_CSCMR2_CAN_CLK_SEL_SHIFT,
695 CCM_CSCMR2_CAN_CLK_SEL_MASK,
696 CCM_NO_BUSY_WAIT), /*!< can mux name */
697
698 kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET,
699 CCM_CSCDR1_UART_CLK_SEL_SHIFT,
700 CCM_CSCDR1_UART_CLK_SEL_MASK,
701 CCM_NO_BUSY_WAIT), /*!< uart mux name */
702
703 kCLOCK_SpdifMux = CCM_TUPLE(CDCDR_OFFSET,
704 CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT,
705 CCM_CDCDR_SPDIF0_CLK_SEL_MASK,
706 CCM_NO_BUSY_WAIT), /*!< spdif mux name */
707
708 kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2_OFFSET,
709 CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT,
710 CCM_CSCDR2_LPI2C_CLK_SEL_MASK,
711 CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */
712} clock_mux_t;
713
714/*!
715 * @brief DIV control names for clock div setting.
716 *
717 * These constants define div control names for clock div setting.\n
718 * - 0:7: REG offset to CCM_BASE in bytes.
719 * - 8:15: Root clock setting bit field shift.
720 * - 16:31: Root clock setting bit field width.
721 */
722typedef enum _clock_div
723{
724 kCLOCK_ArmDiv = CCM_TUPLE(CACRR_OFFSET,
725 CCM_CACRR_ARM_PODF_SHIFT,
726 CCM_CACRR_ARM_PODF_MASK,
727 CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */
728
729 kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET,
730 CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT,
731 CCM_CBCDR_PERIPH_CLK2_PODF_MASK,
732 CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */
733 kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET,
734 CCM_CBCDR_SEMC_PODF_SHIFT,
735 CCM_CBCDR_SEMC_PODF_MASK,
736 CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */
737 kCLOCK_AhbDiv = CCM_TUPLE(CBCDR_OFFSET,
738 CCM_CBCDR_AHB_PODF_SHIFT,
739 CCM_CBCDR_AHB_PODF_MASK,
740 CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */
741 kCLOCK_IpgDiv = CCM_TUPLE(
742 CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */
743
744 kCLOCK_LpspiDiv = CCM_TUPLE(
745 CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */
746
747 kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET,
748 CCM_CSCMR1_FLEXSPI_PODF_SHIFT,
749 CCM_CSCMR1_FLEXSPI_PODF_MASK,
750 CCM_NO_BUSY_WAIT), /*!< flexspi div name */
751 kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1_OFFSET,
752 CCM_CSCMR1_PERCLK_PODF_SHIFT,
753 CCM_CSCMR1_PERCLK_PODF_MASK,
754 CCM_NO_BUSY_WAIT), /*!< perclk div name */
755
756 kCLOCK_CanDiv = CCM_TUPLE(CSCMR2_OFFSET,
757 CCM_CSCMR2_CAN_CLK_PODF_SHIFT,
758 CCM_CSCMR2_CAN_CLK_PODF_MASK,
759 CCM_NO_BUSY_WAIT), /*!< can div name */
760
761 kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1_OFFSET,
762 CCM_CSCDR1_TRACE_PODF_SHIFT,
763 CCM_CSCDR1_TRACE_PODF_MASK,
764 CCM_NO_BUSY_WAIT), /*!< trace div name */
765 kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1_OFFSET,
766 CCM_CSCDR1_USDHC2_PODF_SHIFT,
767 CCM_CSCDR1_USDHC2_PODF_MASK,
768 CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */
769 kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1_OFFSET,
770 CCM_CSCDR1_USDHC1_PODF_SHIFT,
771 CCM_CSCDR1_USDHC1_PODF_MASK,
772 CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */
773 kCLOCK_UartDiv = CCM_TUPLE(CSCDR1_OFFSET,
774 CCM_CSCDR1_UART_CLK_PODF_SHIFT,
775 CCM_CSCDR1_UART_CLK_PODF_MASK,
776 CCM_NO_BUSY_WAIT), /*!< uart div name */
777
778 kCLOCK_Flexio1Div = CCM_TUPLE(CS1CDR_OFFSET,
779 CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT,
780 CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK,
781 CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
782 kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
783 CCM_CS1CDR_SAI3_CLK_PRED_SHIFT,
784 CCM_CS1CDR_SAI3_CLK_PRED_MASK,
785 CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
786 kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR_OFFSET,
787 CCM_CS1CDR_SAI3_CLK_PODF_SHIFT,
788 CCM_CS1CDR_SAI3_CLK_PODF_MASK,
789 CCM_NO_BUSY_WAIT), /*!< sai3 div name */
790 kCLOCK_Flexio1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
791 CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT,
792 CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK,
793 CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
794 kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
795 CCM_CS1CDR_SAI1_CLK_PRED_SHIFT,
796 CCM_CS1CDR_SAI1_CLK_PRED_MASK,
797 CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */
798 kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR_OFFSET,
799 CCM_CS1CDR_SAI1_CLK_PODF_SHIFT,
800 CCM_CS1CDR_SAI1_CLK_PODF_MASK,
801 CCM_NO_BUSY_WAIT), /*!< sai1 div name */
802
803 kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET,
804 CCM_CS2CDR_SAI2_CLK_PRED_SHIFT,
805 CCM_CS2CDR_SAI2_CLK_PRED_MASK,
806 CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */
807 kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR_OFFSET,
808 CCM_CS2CDR_SAI2_CLK_PODF_SHIFT,
809 CCM_CS2CDR_SAI2_CLK_PODF_MASK,
810 CCM_NO_BUSY_WAIT), /*!< sai2 div name */
811
812 kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET,
813 CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT,
814 CCM_CDCDR_SPDIF0_CLK_PRED_MASK,
815 CCM_NO_BUSY_WAIT), /*!< spdif pre div name */
816 kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET,
817 CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT,
818 CCM_CDCDR_SPDIF0_CLK_PODF_MASK,
819 CCM_NO_BUSY_WAIT), /*!< spdif div name */
820
821 kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET,
822 CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT,
823 CCM_CSCDR2_LPI2C_CLK_PODF_MASK,
824 CCM_NO_BUSY_WAIT), /*!< lpi2c div name */
825 kCLOCK_NonePreDiv = CLOCK_ROOT_NONE_PRE_DIV, /*!< None Pre div. */
826} clock_div_t;
827
828/*! @brief USB clock source definition. */
829typedef enum _clock_usb_src
830{
831 kCLOCK_Usb480M = 0, /*!< Use 480M. */
832 kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
833 care the clock source. */
834} clock_usb_src_t;
835
836/*! @brief Source of the USB HS PHY. */
837typedef enum _clock_usb_phy_src
838{
839 kCLOCK_Usbphy480M = 0, /*!< Use 480M. */
840} clock_usb_phy_src_t;
841
842/*!@brief PLL clock source, bypass cloco source also */
843enum _clock_pll_clk_src
844{
845 kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */
846 kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */
847};
848
849/*! @brief PLL configuration for USB */
850typedef struct _clock_usb_pll_config
851{
852 uint8_t loopDivider; /*!< PLL loop divider.
853 0 - Fout=Fref*20;
854 1 - Fout=Fref*22 */
855 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
856
857} clock_usb_pll_config_t;
858
859/*! @brief PLL configuration for System */
860typedef struct _clock_sys_pll_config
861{
862 uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M).
863 0 - Fout=Fref*20;
864 1 - Fout=Fref*22 */
865 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
866 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
867 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
868 uint16_t ss_stop; /*!< Stop value to get frequency change. */
869 uint8_t ss_enable; /*!< Enable spread spectrum modulation */
870 uint16_t ss_step; /*!< Step value to get frequency change step. */
871
872} clock_sys_pll_config_t;
873
874/*! @brief PLL configuration for AUDIO and VIDEO */
875typedef struct _clock_audio_pll_config
876{
877 uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
878 uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */
879 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
880 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
881 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
882} clock_audio_pll_config_t;
883
884/*! @brief PLL configuration for ENET */
885typedef struct _clock_enet_pll_config
886{
887 bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */
888
889 bool enableClkOutput500M; /*!< Power on and enable PLL clock output for ENET (ref_enetpll500M). */
890
891 bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */
892 uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock.
893 b00 25MHz
894 b01 50MHz
895 b10 100MHz (not 50% duty cycle)
896 b11 125MHz */
897 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
898
899} clock_enet_pll_config_t;
900
901/*! @brief PLL name */
902typedef enum _clock_pll
903{
904 kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */
905 kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */
906 kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */
907
908 kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /*!< PLL Enet0 */
909
910 kCLOCK_PllEnet500M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT), /*!< PLL ENET */
911
912 kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< PLL Enet1 */
913
914} clock_pll_t;
915
916/*! @brief PLL PFD name */
917typedef enum _clock_pfd
918{
919 kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */
920 kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */
921 kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */
922 kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
923} clock_pfd_t;
924
925/*!
926 * @brief The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on.
927 */
928typedef enum _clock_output1_selection
929{
930 kCLOCK_OutputPllUsb1Sw = 0U, /*!< Selects USB1 PLL SW clock(Divided by 2) output. */
931 kCLOCK_OutputPllSys = 1U, /*!< Selects SYS PLL clock(Divided by 2) output. */
932 kCLOCK_OutputPllENET500M = 2U, /*!< Selects ENET PLL clock(Divided by 2) output. */
933 kCLOCK_OutputSemcClk = 5U, /*!< Selects semc clock root output. */
934 kCLOCK_OutputAhbClk = 0xBU, /*!< Selects AHB clock root output. */
935 kCLOCK_OutputIpgClk = 0xCU, /*!< Selects IPG clock root output. */
936 kCLOCK_OutputPerClk = 0xDU, /*!< Selects PERCLK clock root output. */
937 kCLOCK_OutputPll4MainClk = 0xFU, /*!< Selects PLL4 main clock output. */
938 kCLOCK_DisableClockOutput1 = 0x10U, /*!< Disables CLKO1. */
939} clock_output1_selection_t;
940
941/*!
942 * @brief The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on.
943 *
944 */
945typedef enum _clock_output2_selection
946{
947 kCLOCK_OutputUsdhc1Clk = 3U, /*!< Selects USDHC1 clock root output. */
948 kCLOCK_OutputLpi2cClk = 6U, /*!< Selects LPI2C clock root output. */
949 kCLOCK_OutputOscClk = 0xEU, /*!< Selects OSC output. */
950 kCLOCK_OutputLpspiClk = 0x10U, /*!< Selects LPSPI clock root output. */
951 kCLOCK_OutputUsdhc2Clk = 0x11U, /*!< Selects USDHC2 clock root output. */
952 kCLOCK_OutputSai1Clk = 0x12U, /*!< Selects SAI1 clock root output. */
953 kCLOCK_OutputSai2Clk = 0x13U, /*!< Selects SAI2 clock root output. */
954 kCLOCK_OutputSai3Clk = 0x14U, /*!< Selects SAI3 clock root output. */
955 kCLOCK_OutputTraceClk = 0x16U, /*!< Selects Trace clock root output. */
956 kCLOCK_OutputCanClk = 0x17U, /*!< Selects CAN clock root output. */
957 kCLOCK_OutputFlexspiClk = 0x1BU, /*!< Selects FLEXSPI clock root output. */
958 kCLOCK_OutputUartClk = 0x1CU, /*!< Selects UART clock root output. */
959 kCLOCK_OutputSpdif0Clk = 0x1DU, /*!< Selects SPDIF0 clock root output. */
960 kCLOCK_DisableClockOutput2 = 0x1FU, /*!< Disables CLKO2. */
961} clock_output2_selection_t;
962
963/*!
964 * @brief The enumerator of clock output's divider.
965 */
966typedef enum _clock_output_divider
967{
968 kCLOCK_DivideBy1 = 0U, /*!< Output clock divided by 1. */
969 kCLOCK_DivideBy2, /*!< Output clock divided by 2. */
970 kCLOCK_DivideBy3, /*!< Output clock divided by 3. */
971 kCLOCK_DivideBy4, /*!< Output clock divided by 4. */
972 kCLOCK_DivideBy5, /*!< Output clock divided by 5. */
973 kCLOCK_DivideBy6, /*!< Output clock divided by 6. */
974 kCLOCK_DivideBy7, /*!< Output clock divided by 7. */
975 kCLOCK_DivideBy8, /*!< Output clock divided by 8. */
976} clock_output_divider_t;
977
978/*!
979 * @brief The enumerator of clock root.
980 */
981typedef enum _clock_root
982{
983 kCLOCK_Usdhc1ClkRoot = 0U, /*!< USDHC1 clock root. */
984 kCLOCK_Usdhc2ClkRoot, /*!< USDHC2 clock root. */
985 kCLOCK_FlexspiClkRoot, /*!< FLEXSPI clock root. */
986 kCLOCK_LpspiClkRoot, /*!< LPSPI clock root. */
987 kCLOCK_TraceClkRoot, /*!< Trace clock root. */
988 kCLOCK_Sai1ClkRoot, /*!< SAI1 clock root. */
989 kCLOCK_Sai2ClkRoot, /*!< SAI2 clock root. */
990 kCLOCK_Sai3ClkRoot, /*!< SAI3 clock root. */
991 kCLOCK_Lpi2cClkRoot, /*!< LPI2C clock root. */
992 kCLOCK_CanClkRoot, /*!< CAN clock root. */
993 kCLOCK_UartClkRoot, /*!< UART clock root. */
994 kCLOCK_SpdifClkRoot, /*!< SPDIF clock root. */
995 kCLOCK_Flexio1ClkRoot, /*!< FLEXIO1 clock root. */
996} clock_root_t;
997
998/*******************************************************************************
999 * API
1000 ******************************************************************************/
1001
1002#if defined(__cplusplus)
1003extern "C" {
1004#endif /* __cplusplus */
1005
1006/*!
1007 * @brief Set CCM MUX node to certain value.
1008 *
1009 * @param mux Which mux node to set, see \ref clock_mux_t.
1010 * @param value Clock mux value to set, different mux has different value range.
1011 */
1012static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
1013{
1014 uint32_t busyShift;
1015
1016 busyShift = CCM_TUPLE_BUSY_SHIFT(mux);
1017 CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) |
1018 (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux));
1019
1020 assert(busyShift <= CCM_NO_BUSY_WAIT);
1021
1022 /* Clock switch need Handshake? */
1023 if (CCM_NO_BUSY_WAIT != busyShift)
1024 {
1025 /* Wait until CCM internal handshake finish. */
1026 while ((CCM->CDHIPR & (1UL << busyShift)) != 0UL)
1027 {
1028 }
1029 }
1030}
1031
1032/*!
1033 * @brief Get CCM MUX value.
1034 *
1035 * @param mux Which mux node to get, see \ref clock_mux_t.
1036 * @return Clock mux value.
1037 */
1038static inline uint32_t CLOCK_GetMux(clock_mux_t mux)
1039{
1040 return (CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux)) >> CCM_TUPLE_SHIFT(mux);
1041}
1042
1043/*!
1044 * @brief Set CCM DIV node to certain value.
1045 *
1046 * @param divider Which div node to set, see \ref clock_div_t.
1047 * @param value Clock div value to set, different divider has different value range.
1048 */
1049static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
1050{
1051 uint32_t busyShift;
1052
1053 busyShift = CCM_TUPLE_BUSY_SHIFT((uint32_t)divider);
1054 CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) |
1055 (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider));
1056
1057 assert(busyShift <= CCM_NO_BUSY_WAIT);
1058
1059 /* Clock switch need Handshake? */
1060 if (CCM_NO_BUSY_WAIT != busyShift)
1061 {
1062 /* Wait until CCM internal handshake finish. */
1063 while ((CCM->CDHIPR & (1UL << busyShift)) != 0UL)
1064 {
1065 }
1066 }
1067}
1068
1069/*!
1070 * @brief Get CCM DIV node value.
1071 *
1072 * @param divider Which div node to get, see \ref clock_div_t.
1073 */
1074static inline uint32_t CLOCK_GetDiv(clock_div_t divider)
1075{
1076 return ((CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider));
1077}
1078
1079/*!
1080 * @brief Control the clock gate for specific IP.
1081 *
1082 * @param name Which clock to enable, see \ref clock_ip_name_t.
1083 * @param value Clock gate value to set, see \ref clock_gate_value_t.
1084 */
1085static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value)
1086{
1087 uint32_t index = ((uint32_t)name) >> 8U;
1088 uint32_t shift = ((uint32_t)name) & 0x1FU;
1089 volatile uint32_t *reg;
1090
1091 assert(index <= 6UL);
1092
1093 reg = (volatile uint32_t *)((uint32_t)((volatile uint32_t *)&CCM->CCGR0) + sizeof(volatile uint32_t *) * index);
1094 *reg = ((*reg) & ~(3UL << shift)) | (((uint32_t)value) << shift);
1095}
1096
1097/*!
1098 * @brief Enable the clock for specific IP.
1099 *
1100 * @param name Which clock to enable, see \ref clock_ip_name_t.
1101 */
1102static inline void CLOCK_EnableClock(clock_ip_name_t name)
1103{
1104 CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait);
1105}
1106
1107/*!
1108 * @brief Disable the clock for specific IP.
1109 *
1110 * @param name Which clock to disable, see \ref clock_ip_name_t.
1111 */
1112static inline void CLOCK_DisableClock(clock_ip_name_t name)
1113{
1114 CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded);
1115}
1116
1117/*!
1118 * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal.
1119 *
1120 * @param mode Which mode to enter, see \ref clock_mode_t.
1121 */
1122static inline void CLOCK_SetMode(clock_mode_t mode)
1123{
1124 CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode);
1125}
1126
1127/*!
1128 * @brief Gets the OSC clock frequency.
1129 *
1130 * This function will return the external XTAL OSC frequency if it is selected as the source of OSC,
1131 * otherwise internal 24MHz RC OSC frequency will be returned.
1132 *
1133 * @return Clock frequency; If the clock is invalid, returns 0.
1134 */
1135static inline uint32_t CLOCK_GetOscFreq(void)
1136{
1137 return ((XTALOSC24M->LOWPWR_CTRL & (uint32_t)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_xtalFreq;
1138}
1139
1140/*!
1141 * @brief Gets the AHB clock frequency.
1142 *
1143 * @return The AHB clock frequency value in hertz.
1144 */
1145uint32_t CLOCK_GetAhbFreq(void);
1146
1147/*!
1148 * @brief Gets the SEMC clock frequency.
1149 *
1150 * @return The SEMC clock frequency value in hertz.
1151 */
1152uint32_t CLOCK_GetSemcFreq(void);
1153
1154/*!
1155 * @brief Gets the IPG clock frequency.
1156 *
1157 * @return The IPG clock frequency value in hertz.
1158 */
1159uint32_t CLOCK_GetIpgFreq(void);
1160
1161/*!
1162 * @brief Gets the PER clock frequency.
1163 *
1164 * @return The PER clock frequency value in hertz.
1165 */
1166uint32_t CLOCK_GetPerClkFreq(void);
1167
1168/*!
1169 * @brief Gets the clock frequency for a specific clock name.
1170 *
1171 * This function checks the current clock configurations and then calculates
1172 * the clock frequency for a specific clock name defined in clock_name_t.
1173 *
1174 * @param name Clock names defined in clock_name_t
1175 * @return Clock frequency value in hertz
1176 */
1177uint32_t CLOCK_GetFreq(clock_name_t name);
1178
1179/*!
1180 * @brief Get the CCM CPU/core/system frequency.
1181 *
1182 * @return Clock frequency; If the clock is invalid, returns 0.
1183 */
1184static inline uint32_t CLOCK_GetCpuClkFreq(void)
1185{
1186 return CLOCK_GetFreq(kCLOCK_CpuClk);
1187}
1188
1189/*!
1190 * @brief Gets the frequency of selected clock root.
1191 *
1192 * @param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t.
1193 * @return The frequency of selected clock root.
1194 */
1195uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot);
1196
1197/*!
1198 * @name OSC operations
1199 * @{
1200 */
1201
1202/*!
1203 * @brief Initialize the external 24MHz clock.
1204 *
1205 * This function supports two modes:
1206 * 1. Use external crystal oscillator.
1207 * 2. Bypass the external crystal oscillator, using input source clock directly.
1208 *
1209 * After this function, please call CLOCK_SetXtal0Freq to inform clock driver
1210 * the external clock frequency.
1211 *
1212 * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator.
1213 * @note This device does not support bypass external crystal oscillator, so
1214 * the input parameter should always be false.
1215 */
1216void CLOCK_InitExternalClk(bool bypassXtalOsc);
1217
1218/*!
1219 * @brief Deinitialize the external 24MHz clock.
1220 *
1221 * This function disables the external 24MHz clock.
1222 *
1223 * After this function, please call CLOCK_SetXtal0Freq to set external clock
1224 * frequency to 0.
1225 */
1226void CLOCK_DeinitExternalClk(void);
1227
1228/*!
1229 * @brief Switch the OSC.
1230 *
1231 * This function switches the OSC source for SoC.
1232 *
1233 * @param osc OSC source to switch to.
1234 */
1235void CLOCK_SwitchOsc(clock_osc_t osc);
1236
1237/*!
1238 * @brief Gets the RTC clock frequency.
1239 *
1240 * @return Clock frequency; If the clock is invalid, returns 0.
1241 */
1242static inline uint32_t CLOCK_GetRtcFreq(void)
1243{
1244 return 32768U;
1245}
1246
1247/*!
1248 * @brief Set the XTAL (24M OSC) frequency based on board setting.
1249 *
1250 * @param freq The XTAL input clock frequency in Hz.
1251 */
1252static inline void CLOCK_SetXtalFreq(uint32_t freq)
1253{
1254 g_xtalFreq = freq;
1255}
1256
1257/*!
1258 * @brief Set the RTC XTAL (32K OSC) frequency based on board setting.
1259 *
1260 * @param freq The RTC XTAL input clock frequency in Hz.
1261 */
1262static inline void CLOCK_SetRtcXtalFreq(uint32_t freq)
1263{
1264 g_rtcXtalFreq = freq;
1265}
1266
1267/*!
1268 * @brief Initialize the RC oscillator 24MHz clock.
1269 */
1270void CLOCK_InitRcOsc24M(void);
1271
1272/*!
1273 * @brief Power down the RCOSC 24M clock.
1274 */
1275void CLOCK_DeinitRcOsc24M(void);
1276/* @} */
1277
1278/*! @brief Enable USB HS clock.
1279 *
1280 * This function only enables the access to USB HS prepheral, upper layer
1281 * should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
1282 * clock to use USB HS.
1283 *
1284 * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
1285 * @param freq USB HS does not care about the clock source, so this parameter is ignored.
1286 * @retval true The clock is set successfully.
1287 * @retval false The clock source is invalid to get proper USB HS clock.
1288 */
1289bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
1290
1291/* @} */
1292
1293/*!
1294 * @name PLL/PFD operations
1295 * @{
1296 */
1297/*!
1298 * @brief PLL bypass setting
1299 *
1300 * @param base CCM_ANALOG base pointer.
1301 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1302 * @param bypass Bypass the PLL.
1303 * - true: Bypass the PLL.
1304 * - false:Not bypass the PLL.
1305 */
1306static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass)
1307{
1308 if (bypass)
1309 {
1310 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1311 }
1312 else
1313 {
1314 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1315 }
1316}
1317
1318/*!
1319 * @brief Check if PLL is bypassed
1320 *
1321 * @param base CCM_ANALOG base pointer.
1322 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1323 * @return PLL bypass status.
1324 * - true: The PLL is bypassed.
1325 * - false: The PLL is not bypassed.
1326 */
1327static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll)
1328{
1329 return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_PLL_BYPASS_SHIFT));
1330}
1331
1332/*!
1333 * @brief Check if PLL is enabled
1334 *
1335 * @param base CCM_ANALOG base pointer.
1336 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1337 * @return PLL bypass status.
1338 * - true: The PLL is enabled.
1339 * - false: The PLL is not enabled.
1340 */
1341static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll)
1342{
1343 return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pll)));
1344}
1345
1346/*!
1347 * @brief PLL bypass clock source setting.
1348 * Note: change the bypass clock source also change the pll reference clock source.
1349 *
1350 * @param base CCM_ANALOG base pointer.
1351 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1352 * @param src Bypass clock source, reference _clock_pll_bypass_clk_src.
1353 */
1354static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src)
1355{
1356 CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src;
1357}
1358
1359/*!
1360 * @brief Get PLL bypass clock value, it is PLL reference clock actually.
1361 * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0
1362 * will be returned.
1363 * @param base CCM_ANALOG base pointer.
1364 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1365 * @retval bypass reference clock frequency value.
1366 */
1367static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll)
1368{
1369 return ((((uint32_t)(CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) >>
1370 CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == (uint32_t)kCLOCK_PllClkSrc24M) ?
1371 CLOCK_GetOscFreq() :
1372 CLKPN_FREQ;
1373}
1374
1375/*!
1376 * @brief Initialize the System PLL.
1377 *
1378 * This function initializes the System PLL with specific settings
1379 *
1380 * @param config Configuration to set to PLL.
1381 */
1382void CLOCK_InitSysPll(const clock_sys_pll_config_t *config);
1383
1384/*!
1385 * @brief De-initialize the System PLL.
1386 */
1387void CLOCK_DeinitSysPll(void);
1388
1389/*!
1390 * @brief Initialize the USB1 PLL.
1391 *
1392 * This function initializes the USB1 PLL with specific settings
1393 *
1394 * @param config Configuration to set to PLL.
1395 */
1396void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config);
1397
1398/*!
1399 * @brief Deinitialize the USB1 PLL.
1400 */
1401void CLOCK_DeinitUsb1Pll(void);
1402
1403/*!
1404 * @brief Initializes the Audio PLL.
1405 *
1406 * This function initializes the Audio PLL with specific settings
1407 *
1408 * @param config Configuration to set to PLL.
1409 */
1410void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
1411
1412/*!
1413 * @brief De-initialize the Audio PLL.
1414 */
1415void CLOCK_DeinitAudioPll(void);
1416
1417/*!
1418 * @brief Initialize the ENET PLL.
1419 *
1420 * This function initializes the ENET PLL with specific settings.
1421 *
1422 * @param config Configuration to set to PLL.
1423 */
1424void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config);
1425
1426/*!
1427 * @brief Deinitialize the ENET PLL.
1428 *
1429 * This function disables the ENET PLL.
1430 */
1431void CLOCK_DeinitEnetPll(void);
1432
1433/*!
1434 * @brief Get current PLL output frequency.
1435 *
1436 * This function get current output frequency of specific PLL
1437 *
1438 * @param pll pll name to get frequency.
1439 * @return The PLL output frequency in hertz.
1440 */
1441uint32_t CLOCK_GetPllFreq(clock_pll_t pll);
1442
1443/*!
1444 * @brief Initialize the System PLL PFD.
1445 *
1446 * This function initializes the System PLL PFD. During new value setting,
1447 * the clock output is disabled to prevent glitch.
1448 *
1449 * @param pfd Which PFD clock to enable.
1450 * @param pfdFrac The PFD FRAC value.
1451 * @note It is recommended that PFD settings are kept between 12-35.
1452 */
1453void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac);
1454
1455/*!
1456 * @brief De-initialize the System PLL PFD.
1457 *
1458 * This function disables the System PLL PFD.
1459 *
1460 * @param pfd Which PFD clock to disable.
1461 */
1462void CLOCK_DeinitSysPfd(clock_pfd_t pfd);
1463
1464/*!
1465 * @brief Initialize the USB1 PLL PFD.
1466 *
1467 * This function initializes the USB1 PLL PFD. During new value setting,
1468 * the clock output is disabled to prevent glitch.
1469 *
1470 * @param pfd Which PFD clock to enable.
1471 * @param pfdFrac The PFD FRAC value.
1472 * @note It is recommended that PFD settings are kept between 12-35.
1473 */
1474void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac);
1475
1476/*!
1477 * @brief De-initialize the USB1 PLL PFD.
1478 *
1479 * This function disables the USB1 PLL PFD.
1480 *
1481 * @param pfd Which PFD clock to disable.
1482 */
1483void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd);
1484
1485/*!
1486 * @brief Get current System PLL PFD output frequency.
1487 *
1488 * This function get current output frequency of specific System PLL PFD
1489 *
1490 * @param pfd pfd name to get frequency.
1491 * @return The PFD output frequency in hertz.
1492 */
1493uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
1494
1495/*!
1496 * @brief Get current USB1 PLL PFD output frequency.
1497 *
1498 * This function get current output frequency of specific USB1 PLL PFD
1499 *
1500 * @param pfd pfd name to get frequency.
1501 * @return The PFD output frequency in hertz.
1502 */
1503uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd);
1504
1505/*! @brief Enable USB HS PHY PLL clock.
1506 *
1507 * This function enables the internal 480MHz USB PHY PLL clock.
1508 *
1509 * @param src USB HS PHY PLL clock source.
1510 * @param freq The frequency specified by src.
1511 * @retval true The clock is set successfully.
1512 * @retval false The clock source is invalid to get proper USB HS clock.
1513 */
1514bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1515
1516/*! @brief Disable USB HS PHY PLL clock.
1517 *
1518 * This function disables USB HS PHY PLL clock.
1519 */
1520void CLOCK_DisableUsbhs0PhyPllClock(void);
1521
1522/* @} */
1523
1524/*!
1525 * @name Clock Output Inferfaces
1526 * @{
1527 */
1528
1529/*!
1530 * @brief Set the clock source and the divider of the clock output1.
1531 *
1532 * @param selection The clock source to be output, please refer to @ref clock_output1_selection_t.
1533 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1534 */
1535void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider);
1536
1537/*!
1538 * @brief Set the clock source and the divider of the clock output2.
1539 *
1540 * @param selection The clock source to be output, please refer to @ref clock_output2_selection_t.
1541 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1542 */
1543void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider);
1544
1545/*!
1546 * @brief Get the frequency of clock output1 clock signal.
1547 *
1548 * @return The frequency of clock output1 clock signal.
1549 */
1550uint32_t CLOCK_GetClockOutCLKO1Freq(void);
1551
1552/*!
1553 * @brief Get the frequency of clock output2 clock signal.
1554 *
1555 * @return The frequency of clock output2 clock signal.
1556 */
1557uint32_t CLOCK_GetClockOutClkO2Freq(void);
1558
1559/*! @} */
1560
1561#if defined(__cplusplus)
1562}
1563#endif /* __cplusplus */
1564
1565/*! @} */
1566
1567#endif /* _FSL_CLOCK_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_flexram_allocate.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_flexram_allocate.c
new file mode 100644
index 000000000..2aa958521
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_flexram_allocate.c
@@ -0,0 +1,157 @@
1/*
2 * Copyright 2019-2020 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#include "fsl_flexram_allocate.h"
10
11/*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14
15/* Component ID definition, used by tools. */
16#ifndef FSL_COMPONENT_ID
17#define FSL_COMPONENT_ID "driver.soc_flexram_allocate"
18#endif
19
20/*******************************************************************************
21 * Prototypes
22 ******************************************************************************/
23/*!
24 * @brief FLEXRAM map TCM size to register value
25 *
26 * @param tcmBankNum tcm banknumber
27 * @retval register value correspond to the tcm size
28 */
29static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum);
30
31/*******************************************************************************
32 * Variables
33 ******************************************************************************/
34
35/*******************************************************************************
36 * Code
37 ******************************************************************************/
38static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum)
39{
40 uint8_t tcmSizeConfig = 0U;
41 uint32_t totalTcmSize = 0U;
42
43 /* if bank number is a odd value, use a new bank number which bigger than target */
44 do
45 {
46 if ((tcmBankNum & (tcmBankNum - 1U)) == 0U)
47 {
48 break;
49 }
50 } while (++tcmBankNum < (uint8_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);
51
52 totalTcmSize = (uint32_t)tcmBankNum * ((uint32_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE >> 10U);
53 /* get bit '1' position */
54 while (totalTcmSize != 0x00U)
55 {
56 if ((totalTcmSize & 1U) == 0U)
57 {
58 tcmSizeConfig++;
59 }
60 else
61 {
62 break;
63 }
64 totalTcmSize >>= 1U;
65 }
66
67 return tcmSizeConfig + 1U;
68}
69
70void FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum)
71{
72 assert(itcmBankNum <= (uint8_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);
73 assert(dtcmBankNum <= (uint8_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);
74
75 /* dtcm configuration */
76 if (dtcmBankNum != 0U)
77 {
78 IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK;
79 IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(FLEXRAM_MapTcmSizeToRegister(dtcmBankNum));
80 IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK;
81 }
82 else
83 {
84 IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK;
85 }
86
87 /* itcm configuration */
88 if (itcmBankNum != 0U)
89 {
90 IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK;
91 IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(FLEXRAM_MapTcmSizeToRegister(itcmBankNum));
92 IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK;
93 }
94 else
95 {
96 IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK;
97 }
98}
99
100/*!
101 * brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM
102 * This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate
103 * is needed.
104 * param config allocate configuration.
105 * retval kStatus_InvalidArgument the argument is invalid
106 * kStatus_Success allocate success
107 */
108status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config)
109{
110 assert(config != NULL);
111
112 uint8_t dtcmBankNum = config->dtcmBankNum;
113 uint8_t itcmBankNum = config->itcmBankNum;
114 uint8_t ocramBankNum = config->ocramBankNum;
115 uint8_t i = 0U;
116 uint32_t bankCfg = 0U;
117 status_t status = kStatus_Success;
118
119 /* check the arguments */
120 if ((uint8_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS < (dtcmBankNum + itcmBankNum + ocramBankNum))
121 {
122 status = kStatus_InvalidArgument;
123 }
124 else
125 {
126 /* flexram bank config value */
127 for (i = 0U; i < (uint8_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS; i++)
128 {
129 if (i < ocramBankNum)
130 {
131 bankCfg |= ((uint32_t)kFLEXRAM_BankOCRAM) << (i * 2U);
132 continue;
133 }
134
135 if (i < (dtcmBankNum + ocramBankNum))
136 {
137 bankCfg |= ((uint32_t)kFLEXRAM_BankDTCM) << (i * 2U);
138 continue;
139 }
140
141 if (i < (dtcmBankNum + ocramBankNum + itcmBankNum))
142 {
143 bankCfg |= ((uint32_t)kFLEXRAM_BankITCM) << (i * 2U);
144 continue;
145 }
146 }
147
148 IOMUXC_GPR->GPR17 = bankCfg;
149
150 /* set TCM size */
151 FLEXRAM_SetTCMSize(itcmBankNum, dtcmBankNum);
152 /* select ram allocate source from FLEXRAM_BANK_CFG */
153 FLEXRAM_SetAllocateRamSrc(kFLEXRAM_BankAllocateThroughBankCfg);
154 }
155
156 return status;
157}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_flexram_allocate.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_flexram_allocate.h
new file mode 100644
index 000000000..e2310683a
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_flexram_allocate.h
@@ -0,0 +1,99 @@
1/*
2 * Copyright 2019-2020 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_FLEXRAM_ALLOCATE_H_
10#define _FSL_FLEXRAM_ALLOCATE_H_
11
12#include "fsl_common.h"
13
14/*!
15 * @addtogroup flexram
16 * @{
17 */
18
19/******************************************************************************
20 * Definitions.
21 *****************************************************************************/
22
23/*! @name Driver version */
24/*@{*/
25/*! @brief SOC_FLEXRAM_ALLOCATE driver version 2.0.1. */
26#define FSL_SOC_FLEXRAM_ALLOCATE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
27/*@}*/
28
29/*! @brief FLEXRAM bank type */
30enum
31{
32 kFLEXRAM_BankNotUsed = 0U, /*!< bank is not used */
33 kFLEXRAM_BankOCRAM = 1U, /*!< bank is OCRAM */
34 kFLEXRAM_BankDTCM = 2U, /*!< bank is DTCM */
35 kFLEXRAM_BankITCM = 3U, /*!< bank is ITCM */
36};
37
38/*! @brief FLEXRAM bank allocate source */
39typedef enum _flexram_bank_allocate_src
40{
41 kFLEXRAM_BankAllocateThroughHardwareFuse = 0U, /*!< allocate ram through hardware fuse value */
42 kFLEXRAM_BankAllocateThroughBankCfg = 1U, /*!< allocate ram through FLEXRAM_BANK_CFG */
43} flexram_bank_allocate_src_t;
44
45/*! @brief FLEXRAM allocate ocram, itcm, dtcm size */
46typedef struct _flexram_allocate_ram
47{
48 const uint8_t ocramBankNum; /*!< ocram banknumber which the SOC support */
49 const uint8_t dtcmBankNum; /*!< dtcm bank number to allocate, the number should be power of 2 */
50 const uint8_t itcmBankNum; /*!< itcm bank number to allocate, the number should be power of 2 */
51} flexram_allocate_ram_t;
52
53/*******************************************************************************
54 * APIs
55 ******************************************************************************/
56
57#if defined(__cplusplus)
58extern "C" {
59#endif
60
61/*!
62 * @brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM
63 * This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate
64 * is needed.
65 * @param config allocate configuration.
66 * @retval kStatus_InvalidArgument the argument is invalid
67 * kStatus_Success allocate success
68 */
69status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config);
70
71/*!
72 * @brief FLEXRAM set allocate on-chip ram source
73 * @param src bank config source select value.
74 */
75static inline void FLEXRAM_SetAllocateRamSrc(flexram_bank_allocate_src_t src)
76{
77 IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK;
78 IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(src);
79}
80
81/*!
82 * @brief FLEXRAM configure TCM size
83 * This function is used to set the TCM to the target size. If a odd bank number is used,
84 * a new banknumber will be used which is bigger than target value, application can set tcm
85 * size to the biggest bank number always, then boundary access error can be captured by flexram only.
86 * When access to the TCM memory boundary ,hardfault will raised by core.
87 * @param itcmBankNum itcm bank number to allocate
88 * @param dtcmBankNum dtcm bank number to allocate
89 *
90 */
91void FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum);
92
93#if defined(__cplusplus)
94}
95#endif
96
97/*! @}*/
98
99#endif
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_iomuxc.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_iomuxc.h
new file mode 100644
index 000000000..b7b110b04
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_iomuxc.h
@@ -0,0 +1,1008 @@
1/*
2 * Copyright 2016 Freescale Semiconductor, Inc.
3 * Copyright 2016-2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_IOMUXC_H_
10#define _FSL_IOMUXC_H_
11
12#include "fsl_common.h"
13
14/*!
15 * @addtogroup iomuxc_driver
16 * @{
17 */
18
19/*! @file */
20
21/*******************************************************************************
22 * Definitions
23 ******************************************************************************/
24/* Component ID definition, used by tools. */
25#ifndef FSL_COMPONENT_ID
26#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
27#endif
28
29/*! @name Driver version */
30/*@{*/
31/*! @brief IOMUXC driver version 2.0.2. */
32#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
33/*@}*/
34
35/*!
36 * @name Pin function ID
37 * The pin function ID is a tuple of \<muxRegister muxMode inputRegister inputDaisy configRegister\>
38 *
39 * @{
40 */
41#define IOMUXC_GPIO_EMC_00_SEMC_DATA00 0x401F8014U, 0x0U, 0, 0, 0x401F8188U
42#define IOMUXC_GPIO_EMC_00_QTIMER2_TIMER0 0x401F8014U, 0x1U, 0x401F8420U, 0x0U, 0x401F8188U
43#define IOMUXC_GPIO_EMC_00_LPUART4_CTS_B 0x401F8014U, 0x2U, 0x401F83E0U, 0x0U, 0x401F8188U
44#define IOMUXC_GPIO_EMC_00_SPDIF_SR_CLK 0x401F8014U, 0x3U, 0, 0, 0x401F8188U
45#define IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x401F8014U, 0x4U, 0, 0, 0x401F8188U
46#define IOMUXC_GPIO_EMC_00_GPIO2_IO00 0x401F8014U, 0x5U, 0, 0, 0x401F8188U
47#define IOMUXC_GPIO_EMC_00_FLEXCAN1_TX 0x401F8014U, 0x6U, 0, 0, 0x401F8188U
48#define IOMUXC_GPIO_EMC_00_PIT_TRIGGER02 0x401F8014U, 0x7U, 0, 0, 0x401F8188U
49
50#define IOMUXC_GPIO_EMC_01_SEMC_DATA01 0x401F8018U, 0x0U, 0, 0, 0x401F818CU
51#define IOMUXC_GPIO_EMC_01_QTIMER2_TIMER1 0x401F8018U, 0x1U, 0x401F8424U, 0x0U, 0x401F818CU
52#define IOMUXC_GPIO_EMC_01_LPUART4_RTS_B 0x401F8018U, 0x2U, 0, 0, 0x401F818CU
53#define IOMUXC_GPIO_EMC_01_SPDIF_OUT 0x401F8018U, 0x3U, 0, 0, 0x401F818CU
54#define IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x401F8018U, 0x4U, 0x401F83ACU, 0x0U, 0x401F818CU
55#define IOMUXC_GPIO_EMC_01_GPIO2_IO01 0x401F8018U, 0x5U, 0, 0, 0x401F818CU
56#define IOMUXC_GPIO_EMC_01_FLEXCAN1_RX 0x401F8018U, 0x6U, 0x401F8320U, 0x0U, 0x401F818CU
57#define IOMUXC_GPIO_EMC_01_PIT_TRIGGER03 0x401F8018U, 0x7U, 0, 0, 0x401F818CU
58
59#define IOMUXC_GPIO_EMC_02_SEMC_DATA02 0x401F801CU, 0x0U, 0, 0, 0x401F8190U
60#define IOMUXC_GPIO_EMC_02_QTIMER2_TIMER2 0x401F801CU, 0x1U, 0x401F8428U, 0x0U, 0x401F8190U
61#define IOMUXC_GPIO_EMC_02_LPUART4_TX 0x401F801CU, 0x2U, 0x401F83E8U, 0x0U, 0x401F8190U
62#define IOMUXC_GPIO_EMC_02_SPDIF_LOCK 0x401F801CU, 0x3U, 0, 0, 0x401F8190U
63#define IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x401F801CU, 0x4U, 0x401F83B8U, 0x0U, 0x401F8190U
64#define IOMUXC_GPIO_EMC_02_GPIO2_IO02 0x401F801CU, 0x5U, 0, 0, 0x401F8190U
65#define IOMUXC_GPIO_EMC_02_LPI2C1_SCL 0x401F801CU, 0x6U, 0x401F837CU, 0x0U, 0x401F8190U
66
67#define IOMUXC_GPIO_EMC_03_SEMC_DATA03 0x401F8020U, 0x0U, 0, 0, 0x401F8194U
68#define IOMUXC_GPIO_EMC_03_QTIMER2_TIMER3 0x401F8020U, 0x1U, 0x401F842CU, 0x0U, 0x401F8194U
69#define IOMUXC_GPIO_EMC_03_LPUART4_RX 0x401F8020U, 0x2U, 0x401F83E4U, 0x0U, 0x401F8194U
70#define IOMUXC_GPIO_EMC_03_SPDIF_EXT_CLK 0x401F8020U, 0x3U, 0, 0, 0x401F8194U
71#define IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x401F8020U, 0x4U, 0x401F83B4U, 0x0U, 0x401F8194U
72#define IOMUXC_GPIO_EMC_03_GPIO2_IO03 0x401F8020U, 0x5U, 0, 0, 0x401F8194U
73#define IOMUXC_GPIO_EMC_03_LPI2C1_SDA 0x401F8020U, 0x6U, 0x401F8380U, 0x0U, 0x401F8194U
74
75#define IOMUXC_GPIO_EMC_04_SEMC_DATA04 0x401F8024U, 0x0U, 0, 0, 0x401F8198U
76#define IOMUXC_GPIO_EMC_04_XBAR1_INOUT04 0x401F8024U, 0x1U, 0, 0, 0x401F8198U
77#define IOMUXC_GPIO_EMC_04_SPDIF_OUT 0x401F8024U, 0x2U, 0, 0, 0x401F8198U
78#define IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK 0x401F8024U, 0x3U, 0x401F8464U, 0x1U, 0x401F8198U
79#define IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16 0x401F8024U, 0x4U, 0, 0, 0x401F8198U
80#define IOMUXC_GPIO_EMC_04_GPIO2_IO04 0x401F8024U, 0x5U, 0, 0, 0x401F8198U
81
82#define IOMUXC_GPIO_EMC_05_SEMC_DATA05 0x401F8028U, 0x0U, 0, 0, 0x401F819CU
83#define IOMUXC_GPIO_EMC_05_XBAR1_INOUT05 0x401F8028U, 0x1U, 0, 0, 0x401F819CU
84#define IOMUXC_GPIO_EMC_05_SPDIF_IN 0x401F8028U, 0x2U, 0x401F8488U, 0x0U, 0x401F819CU
85#define IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x401F8028U, 0x3U, 0x401F8468U, 0x1U, 0x401F819CU
86#define IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17 0x401F8028U, 0x4U, 0, 0, 0x401F819CU
87#define IOMUXC_GPIO_EMC_05_GPIO2_IO05 0x401F8028U, 0x5U, 0, 0, 0x401F819CU
88
89#define IOMUXC_GPIO_EMC_06_SEMC_DATA06 0x401F802CU, 0x0U, 0, 0, 0x401F81A0U
90#define IOMUXC_GPIO_EMC_06_XBAR1_INOUT06 0x401F802CU, 0x1U, 0, 0, 0x401F81A0U
91#define IOMUXC_GPIO_EMC_06_LPUART3_TX 0x401F802CU, 0x2U, 0x401F83DCU, 0x0U, 0x401F81A0U
92#define IOMUXC_GPIO_EMC_06_SAI2_TX_DATA 0x401F802CU, 0x3U, 0, 0, 0x401F81A0U
93#define IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18 0x401F802CU, 0x4U, 0, 0, 0x401F81A0U
94#define IOMUXC_GPIO_EMC_06_GPIO2_IO06 0x401F802CU, 0x5U, 0, 0, 0x401F81A0U
95
96#define IOMUXC_GPIO_EMC_07_SEMC_DATA07 0x401F8030U, 0x0U, 0, 0, 0x401F81A4U
97#define IOMUXC_GPIO_EMC_07_XBAR1_INOUT07 0x401F8030U, 0x1U, 0, 0, 0x401F81A4U
98#define IOMUXC_GPIO_EMC_07_LPUART3_RX 0x401F8030U, 0x2U, 0x401F83D8U, 0x0U, 0x401F81A4U
99#define IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC 0x401F8030U, 0x3U, 0x401F8460U, 0x1U, 0x401F81A4U
100#define IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19 0x401F8030U, 0x4U, 0, 0, 0x401F81A4U
101#define IOMUXC_GPIO_EMC_07_GPIO2_IO07 0x401F8030U, 0x5U, 0, 0, 0x401F81A4U
102
103#define IOMUXC_GPIO_EMC_08_SEMC_DM00 0x401F8034U, 0x0U, 0, 0, 0x401F81A8U
104#define IOMUXC_GPIO_EMC_08_XBAR1_INOUT08 0x401F8034U, 0x1U, 0, 0, 0x401F81A8U
105#define IOMUXC_GPIO_EMC_08_FLEXCAN2_TX 0x401F8034U, 0x2U, 0, 0, 0x401F81A8U
106#define IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x401F8034U, 0x3U, 0x401F845CU, 0x1U, 0x401F81A8U
107#define IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20 0x401F8034U, 0x4U, 0, 0, 0x401F81A8U
108#define IOMUXC_GPIO_EMC_08_GPIO2_IO08 0x401F8034U, 0x5U, 0, 0, 0x401F81A8U
109
110#define IOMUXC_GPIO_EMC_09_SEMC_WE 0x401F8038U, 0x0U, 0, 0, 0x401F81ACU
111#define IOMUXC_GPIO_EMC_09_XBAR1_INOUT09 0x401F8038U, 0x1U, 0, 0, 0x401F81ACU
112#define IOMUXC_GPIO_EMC_09_FLEXCAN2_RX 0x401F8038U, 0x2U, 0x401F8324U, 0x1U, 0x401F81ACU
113#define IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK 0x401F8038U, 0x3U, 0x401F8458U, 0x1U, 0x401F81ACU
114#define IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21 0x401F8038U, 0x4U, 0, 0, 0x401F81ACU
115#define IOMUXC_GPIO_EMC_09_GPIO2_IO09 0x401F8038U, 0x5U, 0, 0, 0x401F81ACU
116
117#define IOMUXC_GPIO_EMC_10_SEMC_CAS 0x401F803CU, 0x0U, 0, 0, 0x401F81B0U
118#define IOMUXC_GPIO_EMC_10_XBAR1_INOUT10 0x401F803CU, 0x1U, 0x401F84B0U, 0x0U, 0x401F81B0U
119#define IOMUXC_GPIO_EMC_10_LPI2C4_SDA 0x401F803CU, 0x2U, 0x401F8398U, 0x0U, 0x401F81B0U
120#define IOMUXC_GPIO_EMC_10_SAI1_TX_SYNC 0x401F803CU, 0x3U, 0x401F8450U, 0x0U, 0x401F81B0U
121#define IOMUXC_GPIO_EMC_10_LPSPI2_SCK 0x401F803CU, 0x4U, 0, 0, 0x401F81B0U
122#define IOMUXC_GPIO_EMC_10_GPIO2_IO10 0x401F803CU, 0x5U, 0, 0, 0x401F81B0U
123#define IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMX00 0x401F803CU, 0x6U, 0, 0, 0x401F81B0U
124
125#define IOMUXC_GPIO_EMC_11_SEMC_RAS 0x401F8040U, 0x0U, 0, 0, 0x401F81B4U
126#define IOMUXC_GPIO_EMC_11_XBAR1_INOUT11 0x401F8040U, 0x1U, 0, 0, 0x401F81B4U
127#define IOMUXC_GPIO_EMC_11_LPI2C4_SCL 0x401F8040U, 0x2U, 0x401F8394U, 0x0U, 0x401F81B4U
128#define IOMUXC_GPIO_EMC_11_SAI1_TX_BCLK 0x401F8040U, 0x3U, 0x401F844CU, 0x0U, 0x401F81B4U
129#define IOMUXC_GPIO_EMC_11_LPSPI2_PCS0 0x401F8040U, 0x4U, 0x401F83ACU, 0x1U, 0x401F81B4U
130#define IOMUXC_GPIO_EMC_11_GPIO2_IO11 0x401F8040U, 0x5U, 0, 0, 0x401F81B4U
131#define IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMX01 0x401F8040U, 0x6U, 0, 0, 0x401F81B4U
132
133#define IOMUXC_GPIO_EMC_12_SEMC_CS0 0x401F8044U, 0x0U, 0, 0, 0x401F81B8U
134#define IOMUXC_GPIO_EMC_12_XBAR1_INOUT12 0x401F8044U, 0x1U, 0x401F84B4U, 0x0U, 0x401F81B8U
135#define IOMUXC_GPIO_EMC_12_LPUART6_TX 0x401F8044U, 0x2U, 0x401F83F8U, 0x0U, 0x401F81B8U
136#define IOMUXC_GPIO_EMC_12_SAI1_TX_DATA00 0x401F8044U, 0x3U, 0, 0, 0x401F81B8U
137#define IOMUXC_GPIO_EMC_12_LPSPI2_SDO 0x401F8044U, 0x4U, 0x401F83B8U, 0x1U, 0x401F81B8U
138#define IOMUXC_GPIO_EMC_12_GPIO2_IO12 0x401F8044U, 0x5U, 0, 0, 0x401F81B8U
139#define IOMUXC_GPIO_EMC_12_FLEXPWM2_PWMX02 0x401F8044U, 0x6U, 0, 0, 0x401F81B8U
140
141#define IOMUXC_GPIO_EMC_13_SEMC_BA0 0x401F8048U, 0x0U, 0, 0, 0x401F81BCU
142#define IOMUXC_GPIO_EMC_13_XBAR1_INOUT13 0x401F8048U, 0x1U, 0x401F84B8U, 0x0U, 0x401F81BCU
143#define IOMUXC_GPIO_EMC_13_LPUART6_RX 0x401F8048U, 0x2U, 0x401F83F4U, 0x0U, 0x401F81BCU
144#define IOMUXC_GPIO_EMC_13_SAI1_RX_DATA00 0x401F8048U, 0x3U, 0x401F8438U, 0x0U, 0x401F81BCU
145#define IOMUXC_GPIO_EMC_13_LPSPI2_SDI 0x401F8048U, 0x4U, 0x401F83B4U, 0x1U, 0x401F81BCU
146#define IOMUXC_GPIO_EMC_13_GPIO2_IO13 0x401F8048U, 0x5U, 0, 0, 0x401F81BCU
147#define IOMUXC_GPIO_EMC_13_FLEXPWM2_PWMX03 0x401F8048U, 0x6U, 0, 0, 0x401F81BCU
148#define IOMUXC_GPIO_EMC_13_CCM_PMIC_RDY 0x401F8048U, 0x7U, 0x401F8300U, 0x0U, 0x401F81BCU
149
150#define IOMUXC_GPIO_EMC_14_SEMC_BA1 0x401F804CU, 0x0U, 0, 0, 0x401F81C0U
151#define IOMUXC_GPIO_EMC_14_XBAR1_INOUT14 0x401F804CU, 0x1U, 0x401F84A0U, 0x1U, 0x401F81C0U
152#define IOMUXC_GPIO_EMC_14_LPUART6_CTS_B 0x401F804CU, 0x2U, 0, 0, 0x401F81C0U
153#define IOMUXC_GPIO_EMC_14_SAI1_RX_BCLK 0x401F804CU, 0x3U, 0x401F8434U, 0x1U, 0x401F81C0U
154#define IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x401F804CU, 0x4U, 0, 0, 0x401F81C0U
155#define IOMUXC_GPIO_EMC_14_GPIO2_IO14 0x401F804CU, 0x5U, 0, 0, 0x401F81C0U
156#define IOMUXC_GPIO_EMC_14_FLEXCAN1_TX 0x401F804CU, 0x6U, 0, 0, 0x401F81C0U
157
158#define IOMUXC_GPIO_EMC_15_SEMC_ADDR10 0x401F8050U, 0x0U, 0, 0, 0x401F81C4U
159#define IOMUXC_GPIO_EMC_15_XBAR1_INOUT15 0x401F8050U, 0x1U, 0x401F84A4U, 0x1U, 0x401F81C4U
160#define IOMUXC_GPIO_EMC_15_LPUART6_RTS_B 0x401F8050U, 0x2U, 0, 0, 0x401F81C4U
161#define IOMUXC_GPIO_EMC_15_SAI1_RX_SYNC 0x401F8050U, 0x3U, 0x401F8448U, 0x1U, 0x401F81C4U
162#define IOMUXC_GPIO_EMC_15_WDOG1_B 0x401F8050U, 0x4U, 0, 0, 0x401F81C4U
163#define IOMUXC_GPIO_EMC_15_GPIO2_IO15 0x401F8050U, 0x5U, 0, 0, 0x401F81C4U
164#define IOMUXC_GPIO_EMC_15_FLEXCAN1_RX 0x401F8050U, 0x6U, 0x401F8320U, 0x3U, 0x401F81C4U
165
166#define IOMUXC_GPIO_EMC_16_SEMC_ADDR00 0x401F8054U, 0x0U, 0, 0, 0x401F81C8U
167#define IOMUXC_GPIO_EMC_16_MQS_RIGHT 0x401F8054U, 0x2U, 0, 0, 0x401F81C8U
168#define IOMUXC_GPIO_EMC_16_SAI2_MCLK 0x401F8054U, 0x3U, 0x401F8454U, 0x1U, 0x401F81C8U
169#define IOMUXC_GPIO_EMC_16_GPIO2_IO16 0x401F8054U, 0x5U, 0, 0, 0x401F81C8U
170#define IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE00 0x401F8054U, 0x6U, 0, 0, 0x401F81C8U
171
172#define IOMUXC_GPIO_EMC_17_SEMC_ADDR01 0x401F8058U, 0x0U, 0, 0, 0x401F81CCU
173#define IOMUXC_GPIO_EMC_17_MQS_LEFT 0x401F8058U, 0x2U, 0, 0, 0x401F81CCU
174#define IOMUXC_GPIO_EMC_17_SAI3_MCLK 0x401F8058U, 0x3U, 0x401F846CU, 0x1U, 0x401F81CCU
175#define IOMUXC_GPIO_EMC_17_GPIO2_IO17 0x401F8058U, 0x5U, 0, 0, 0x401F81CCU
176#define IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE01 0x401F8058U, 0x6U, 0, 0, 0x401F81CCU
177
178#define IOMUXC_GPIO_EMC_18_SEMC_ADDR02 0x401F805CU, 0x0U, 0, 0, 0x401F81D0U
179#define IOMUXC_GPIO_EMC_18_XBAR1_INOUT16 0x401F805CU, 0x1U, 0x401F84A8U, 0x1U, 0x401F81D0U
180#define IOMUXC_GPIO_EMC_18_LPI2C2_SDA 0x401F805CU, 0x2U, 0x401F8388U, 0x1U, 0x401F81D0U
181#define IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC 0x401F805CU, 0x3U, 0x401F8448U, 0x2U, 0x401F81D0U
182#define IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22 0x401F805CU, 0x4U, 0, 0, 0x401F81D0U
183#define IOMUXC_GPIO_EMC_18_GPIO2_IO18 0x401F805CU, 0x5U, 0, 0, 0x401F81D0U
184#define IOMUXC_GPIO_EMC_18_SRC_BT_CFG00 0x401F805CU, 0x6U, 0, 0, 0x401F81D0U
185
186#define IOMUXC_GPIO_EMC_19_SEMC_ADDR03 0x401F8060U, 0x0U, 0, 0, 0x401F81D4U
187#define IOMUXC_GPIO_EMC_19_XBAR1_INOUT17 0x401F8060U, 0x1U, 0x401F84ACU, 0x1U, 0x401F81D4U
188#define IOMUXC_GPIO_EMC_19_LPI2C2_SCL 0x401F8060U, 0x2U, 0x401F8384U, 0x1U, 0x401F81D4U
189#define IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK 0x401F8060U, 0x3U, 0x401F8434U, 0x2U, 0x401F81D4U
190#define IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23 0x401F8060U, 0x4U, 0, 0, 0x401F81D4U
191#define IOMUXC_GPIO_EMC_19_GPIO2_IO19 0x401F8060U, 0x5U, 0, 0, 0x401F81D4U
192#define IOMUXC_GPIO_EMC_19_SRC_BT_CFG01 0x401F8060U, 0x6U, 0, 0, 0x401F81D4U
193
194#define IOMUXC_GPIO_EMC_20_SEMC_ADDR04 0x401F8064U, 0x0U, 0, 0, 0x401F81D8U
195#define IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA03 0x401F8064U, 0x1U, 0x401F8334U, 0x1U, 0x401F81D8U
196#define IOMUXC_GPIO_EMC_20_LPUART2_CTS_B 0x401F8064U, 0x2U, 0x401F83CCU, 0x1U, 0x401F81D8U
197#define IOMUXC_GPIO_EMC_20_SAI1_MCLK 0x401F8064U, 0x3U, 0x401F8430U, 0x3U, 0x401F81D8U
198#define IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24 0x401F8064U, 0x4U, 0, 0, 0x401F81D8U
199#define IOMUXC_GPIO_EMC_20_GPIO2_IO20 0x401F8064U, 0x5U, 0, 0, 0x401F81D8U
200#define IOMUXC_GPIO_EMC_20_SRC_BT_CFG02 0x401F8064U, 0x6U, 0, 0, 0x401F81D8U
201
202#define IOMUXC_GPIO_EMC_21_SEMC_ADDR05 0x401F8068U, 0x0U, 0, 0, 0x401F81DCU
203#define IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB03 0x401F8068U, 0x1U, 0x401F8344U, 0x1U, 0x401F81DCU
204#define IOMUXC_GPIO_EMC_21_LPUART2_RTS_B 0x401F8068U, 0x2U, 0, 0, 0x401F81DCU
205#define IOMUXC_GPIO_EMC_21_SAI1_RX_DATA00 0x401F8068U, 0x3U, 0x401F8438U, 0x2U, 0x401F81DCU
206#define IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25 0x401F8068U, 0x4U, 0, 0, 0x401F81DCU
207#define IOMUXC_GPIO_EMC_21_GPIO2_IO21 0x401F8068U, 0x5U, 0, 0, 0x401F81DCU
208#define IOMUXC_GPIO_EMC_21_SRC_BT_CFG03 0x401F8068U, 0x6U, 0, 0, 0x401F81DCU
209
210#define IOMUXC_GPIO_EMC_22_SEMC_ADDR06 0x401F806CU, 0x0U, 0, 0, 0x401F81E0U
211#define IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA02 0x401F806CU, 0x1U, 0x401F8330U, 0x1U, 0x401F81E0U
212#define IOMUXC_GPIO_EMC_22_LPUART2_TX 0x401F806CU, 0x2U, 0x401F83D4U, 0x1U, 0x401F81E0U
213#define IOMUXC_GPIO_EMC_22_SAI1_TX_DATA03 0x401F806CU, 0x3U, 0x401F843CU, 0x1U, 0x401F81E0U
214#define IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26 0x401F806CU, 0x4U, 0, 0, 0x401F81E0U
215#define IOMUXC_GPIO_EMC_22_GPIO2_IO22 0x401F806CU, 0x5U, 0, 0, 0x401F81E0U
216#define IOMUXC_GPIO_EMC_22_SRC_BT_CFG04 0x401F806CU, 0x6U, 0, 0, 0x401F81E0U
217
218#define IOMUXC_GPIO_EMC_23_SEMC_ADDR07 0x401F8070U, 0x0U, 0, 0, 0x401F81E4U
219#define IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB02 0x401F8070U, 0x1U, 0x401F8340U, 0x1U, 0x401F81E4U
220#define IOMUXC_GPIO_EMC_23_LPUART2_RX 0x401F8070U, 0x2U, 0x401F83D0U, 0x1U, 0x401F81E4U
221#define IOMUXC_GPIO_EMC_23_SAI1_TX_DATA02 0x401F8070U, 0x3U, 0x401F8440U, 0x1U, 0x401F81E4U
222#define IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27 0x401F8070U, 0x4U, 0, 0, 0x401F81E4U
223#define IOMUXC_GPIO_EMC_23_GPIO2_IO23 0x401F8070U, 0x5U, 0, 0, 0x401F81E4U
224#define IOMUXC_GPIO_EMC_23_SRC_BT_CFG05 0x401F8070U, 0x6U, 0, 0, 0x401F81E4U
225
226#define IOMUXC_GPIO_EMC_24_SEMC_ADDR08 0x401F8074U, 0x0U, 0, 0, 0x401F81E8U
227#define IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA01 0x401F8074U, 0x1U, 0x401F832CU, 0x1U, 0x401F81E8U
228#define IOMUXC_GPIO_EMC_24_LPUART8_CTS_B 0x401F8074U, 0x2U, 0, 0, 0x401F81E8U
229#define IOMUXC_GPIO_EMC_24_SAI1_TX_DATA01 0x401F8074U, 0x3U, 0x401F8444U, 0x1U, 0x401F81E8U
230#define IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28 0x401F8074U, 0x4U, 0, 0, 0x401F81E8U
231#define IOMUXC_GPIO_EMC_24_GPIO2_IO24 0x401F8074U, 0x5U, 0, 0, 0x401F81E8U
232#define IOMUXC_GPIO_EMC_24_SRC_BT_CFG06 0x401F8074U, 0x6U, 0, 0, 0x401F81E8U
233
234#define IOMUXC_GPIO_EMC_25_SEMC_ADDR09 0x401F8078U, 0x0U, 0, 0, 0x401F81ECU
235#define IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB01 0x401F8078U, 0x1U, 0x401F833CU, 0x1U, 0x401F81ECU
236#define IOMUXC_GPIO_EMC_25_LPUART8_RTS_B 0x401F8078U, 0x2U, 0, 0, 0x401F81ECU
237#define IOMUXC_GPIO_EMC_25_SAI1_TX_DATA00 0x401F8078U, 0x3U, 0, 0, 0x401F81ECU
238#define IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29 0x401F8078U, 0x4U, 0, 0, 0x401F81ECU
239#define IOMUXC_GPIO_EMC_25_GPIO2_IO25 0x401F8078U, 0x5U, 0, 0, 0x401F81ECU
240#define IOMUXC_GPIO_EMC_25_SRC_BT_CFG07 0x401F8078U, 0x6U, 0, 0, 0x401F81ECU
241
242#define IOMUXC_GPIO_EMC_26_SEMC_ADDR11 0x401F807CU, 0x0U, 0, 0, 0x401F81F0U
243#define IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA00 0x401F807CU, 0x1U, 0x401F8328U, 0x1U, 0x401F81F0U
244#define IOMUXC_GPIO_EMC_26_LPUART8_TX 0x401F807CU, 0x2U, 0x401F8408U, 0x1U, 0x401F81F0U
245#define IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK 0x401F807CU, 0x3U, 0x401F844CU, 0x2U, 0x401F81F0U
246#define IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30 0x401F807CU, 0x4U, 0, 0, 0x401F81F0U
247#define IOMUXC_GPIO_EMC_26_GPIO2_IO26 0x401F807CU, 0x5U, 0, 0, 0x401F81F0U
248#define IOMUXC_GPIO_EMC_26_SRC_BT_CFG08 0x401F807CU, 0x6U, 0, 0, 0x401F81F0U
249
250#define IOMUXC_GPIO_EMC_27_SEMC_ADDR12 0x401F8080U, 0x0U, 0, 0, 0x401F81F4U
251#define IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB00 0x401F8080U, 0x1U, 0x401F8338U, 0x1U, 0x401F81F4U
252#define IOMUXC_GPIO_EMC_27_LPUART8_RX 0x401F8080U, 0x2U, 0x401F8404U, 0x1U, 0x401F81F4U
253#define IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC 0x401F8080U, 0x3U, 0x401F8450U, 0x2U, 0x401F81F4U
254#define IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31 0x401F8080U, 0x4U, 0, 0, 0x401F81F4U
255#define IOMUXC_GPIO_EMC_27_GPIO2_IO27 0x401F8080U, 0x5U, 0, 0, 0x401F81F4U
256#define IOMUXC_GPIO_EMC_27_SRC_BT_CFG09 0x401F8080U, 0x6U, 0, 0, 0x401F81F4U
257
258#define IOMUXC_GPIO_EMC_28_SEMC_DQS 0x401F8084U, 0x0U, 0, 0, 0x401F81F8U
259#define IOMUXC_GPIO_EMC_28_FLEXPWM2_PWMA03 0x401F8084U, 0x1U, 0x401F8354U, 0x1U, 0x401F81F8U
260#define IOMUXC_GPIO_EMC_28_XBAR1_INOUT18 0x401F8084U, 0x2U, 0x401F84BCU, 0x0U, 0x401F81F8U
261#define IOMUXC_GPIO_EMC_28_SAI3_MCLK 0x401F8084U, 0x3U, 0x401F846CU, 0x2U, 0x401F81F8U
262#define IOMUXC_GPIO_EMC_28_EWM_OUT_B 0x401F8084U, 0x4U, 0, 0, 0x401F81F8U
263#define IOMUXC_GPIO_EMC_28_GPIO2_IO28 0x401F8084U, 0x5U, 0, 0, 0x401F81F8U
264#define IOMUXC_GPIO_EMC_28_GPT2_CAPTURE2 0x401F8084U, 0x6U, 0, 0, 0x401F81F8U
265#define IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMX00 0x401F8084U, 0x7U, 0, 0, 0x401F81F8U
266
267#define IOMUXC_GPIO_EMC_29_SEMC_CKE 0x401F8088U, 0x0U, 0, 0, 0x401F81FCU
268#define IOMUXC_GPIO_EMC_29_FLEXPWM2_PWMB03 0x401F8088U, 0x1U, 0x401F8364U, 0x1U, 0x401F81FCU
269#define IOMUXC_GPIO_EMC_29_XBAR1_INOUT19 0x401F8088U, 0x2U, 0x401F84C0U, 0x0U, 0x401F81FCU
270#define IOMUXC_GPIO_EMC_29_SAI3_RX_BCLK 0x401F8088U, 0x3U, 0x401F8470U, 0x1U, 0x401F81FCU
271#define IOMUXC_GPIO_EMC_29_WDOG2_RST_B_DEB 0x401F8088U, 0x4U, 0, 0, 0x401F81FCU
272#define IOMUXC_GPIO_EMC_29_GPIO2_IO29 0x401F8088U, 0x5U, 0, 0, 0x401F81FCU
273#define IOMUXC_GPIO_EMC_29_GPT2_COMPARE2 0x401F8088U, 0x6U, 0, 0, 0x401F81FCU
274#define IOMUXC_GPIO_EMC_29_FLEXPWM1_PWMX01 0x401F8088U, 0x7U, 0, 0, 0x401F81FCU
275
276#define IOMUXC_GPIO_EMC_30_SEMC_CLK 0x401F808CU, 0x0U, 0, 0, 0x401F8200U
277#define IOMUXC_GPIO_EMC_30_FLEXPWM2_PWMA02 0x401F808CU, 0x1U, 0x401F8350U, 0x1U, 0x401F8200U
278#define IOMUXC_GPIO_EMC_30_LPUART4_CTS_B 0x401F808CU, 0x2U, 0x401F83E0U, 0x1U, 0x401F8200U
279#define IOMUXC_GPIO_EMC_30_SAI3_RX_SYNC 0x401F808CU, 0x3U, 0x401F8478U, 0x1U, 0x401F8200U
280#define IOMUXC_GPIO_EMC_30_WDOG1_RST_B_DEB 0x401F808CU, 0x4U, 0, 0, 0x401F8200U
281#define IOMUXC_GPIO_EMC_30_GPIO2_IO30 0x401F808CU, 0x5U, 0, 0, 0x401F8200U
282#define IOMUXC_GPIO_EMC_30_GPT2_COMPARE3 0x401F808CU, 0x6U, 0, 0, 0x401F8200U
283#define IOMUXC_GPIO_EMC_30_FLEXPWM1_PWMX02 0x401F808CU, 0x7U, 0, 0, 0x401F8200U
284
285#define IOMUXC_GPIO_EMC_31_SEMC_DM01 0x401F8090U, 0x0U, 0, 0, 0x401F8204U
286#define IOMUXC_GPIO_EMC_31_FLEXPWM2_PWMB02 0x401F8090U, 0x1U, 0x401F8360U, 0x1U, 0x401F8204U
287#define IOMUXC_GPIO_EMC_31_LPUART4_RTS_B 0x401F8090U, 0x2U, 0, 0, 0x401F8204U
288#define IOMUXC_GPIO_EMC_31_SAI3_RX_DATA 0x401F8090U, 0x3U, 0x401F8474U, 0x1U, 0x401F8204U
289#define IOMUXC_GPIO_EMC_31_WDOG2_B 0x401F8090U, 0x4U, 0, 0, 0x401F8204U
290#define IOMUXC_GPIO_EMC_31_GPIO2_IO31 0x401F8090U, 0x5U, 0, 0, 0x401F8204U
291#define IOMUXC_GPIO_EMC_31_GPT2_CLK 0x401F8090U, 0x6U, 0, 0, 0x401F8204U
292#define IOMUXC_GPIO_EMC_31_FLEXPWM1_PWMX03 0x401F8090U, 0x7U, 0, 0, 0x401F8204U
293
294#define IOMUXC_GPIO_EMC_32_SEMC_DATA08 0x401F8094U, 0x0U, 0, 0, 0x401F8208U
295#define IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0 0x401F8094U, 0x1U, 0x401F8410U, 0x1U, 0x401F8208U
296#define IOMUXC_GPIO_EMC_32_LPUART4_TX 0x401F8094U, 0x2U, 0x401F83E8U, 0x2U, 0x401F8208U
297#define IOMUXC_GPIO_EMC_32_SAI3_TX_DATA 0x401F8094U, 0x3U, 0, 0, 0x401F8208U
298#define IOMUXC_GPIO_EMC_32_LPSPI4_SCK 0x401F8094U, 0x4U, 0x401F83C0U, 0x1U, 0x401F8208U
299#define IOMUXC_GPIO_EMC_32_GPIO3_IO00 0x401F8094U, 0x5U, 0, 0, 0x401F8208U
300#define IOMUXC_GPIO_EMC_32_REF_24M_OUT 0x401F8094U, 0x7U, 0, 0, 0x401F8208U
301
302#define IOMUXC_GPIO_EMC_33_SEMC_DATA09 0x401F8098U, 0x0U, 0, 0, 0x401F820CU
303#define IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1 0x401F8098U, 0x1U, 0x401F8414U, 0x1U, 0x401F820CU
304#define IOMUXC_GPIO_EMC_33_LPUART4_RX 0x401F8098U, 0x2U, 0x401F83E4U, 0x2U, 0x401F820CU
305#define IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK 0x401F8098U, 0x3U, 0x401F847CU, 0x1U, 0x401F820CU
306#define IOMUXC_GPIO_EMC_33_LPSPI4_PCS0 0x401F8098U, 0x4U, 0x401F83BCU, 0x1U, 0x401F820CU
307#define IOMUXC_GPIO_EMC_33_GPIO3_IO01 0x401F8098U, 0x5U, 0, 0, 0x401F820CU
308
309#define IOMUXC_GPIO_EMC_34_SEMC_DATA10 0x401F809CU, 0x0U, 0, 0, 0x401F8210U
310#define IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2 0x401F809CU, 0x1U, 0x401F8418U, 0x1U, 0x401F8210U
311#define IOMUXC_GPIO_EMC_34_LPUART7_TX 0x401F809CU, 0x2U, 0x401F8400U, 0x1U, 0x401F8210U
312#define IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC 0x401F809CU, 0x3U, 0x401F8480U, 0x1U, 0x401F8210U
313#define IOMUXC_GPIO_EMC_34_LPSPI4_SDO 0x401F809CU, 0x4U, 0x401F83C8U, 0x1U, 0x401F8210U
314#define IOMUXC_GPIO_EMC_34_GPIO3_IO02 0x401F809CU, 0x5U, 0, 0, 0x401F8210U
315#define IOMUXC_GPIO_EMC_34_ENET_CRS 0x401F809CU, 0x6U, 0, 0, 0x401F8210U
316
317#define IOMUXC_GPIO_EMC_35_SEMC_DATA11 0x401F80A0U, 0x0U, 0, 0, 0x401F8214U
318#define IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3 0x401F80A0U, 0x1U, 0x401F841CU, 0x1U, 0x401F8214U
319#define IOMUXC_GPIO_EMC_35_LPUART7_RX 0x401F80A0U, 0x2U, 0x401F83FCU, 0x1U, 0x401F8214U
320#define IOMUXC_GPIO_EMC_35_USDHC2_WP 0x401F80A0U, 0x3U, 0x401F849CU, 0x1U, 0x401F8214U
321#define IOMUXC_GPIO_EMC_35_LPSPI4_SDI 0x401F80A0U, 0x4U, 0x401F83C4U, 0x1U, 0x401F8214U
322#define IOMUXC_GPIO_EMC_35_GPIO3_IO03 0x401F80A0U, 0x5U, 0, 0, 0x401F8214U
323#define IOMUXC_GPIO_EMC_35_ENET_COL 0x401F80A0U, 0x6U, 0, 0, 0x401F8214U
324
325#define IOMUXC_GPIO_EMC_36_SEMC_DATA12 0x401F80A4U, 0x0U, 0, 0, 0x401F8218U
326#define IOMUXC_GPIO_EMC_36_FLEXPWM2_PWMA01 0x401F80A4U, 0x1U, 0x401F834CU, 0x1U, 0x401F8218U
327#define IOMUXC_GPIO_EMC_36_LPUART5_CTS_B 0x401F80A4U, 0x2U, 0, 0, 0x401F8218U
328#define IOMUXC_GPIO_EMC_36_CCM_PMIC_RDY 0x401F80A4U, 0x3U, 0x401F8300U, 0x3U, 0x401F8218U
329#define IOMUXC_GPIO_EMC_36_LPSPI4_PCS1 0x401F80A4U, 0x4U, 0, 0, 0x401F8218U
330#define IOMUXC_GPIO_EMC_36_GPIO3_IO04 0x401F80A4U, 0x5U, 0, 0, 0x401F8218U
331#define IOMUXC_GPIO_EMC_36_ENET_RX_CLK 0x401F80A4U, 0x6U, 0, 0, 0x401F8218U
332#define IOMUXC_GPIO_EMC_36_USDHC1_WP 0x401F80A4U, 0x7U, 0x401F8494U, 0x4U, 0x401F8218U
333
334#define IOMUXC_GPIO_EMC_37_SEMC_DATA13 0x401F80A8U, 0x0U, 0, 0, 0x401F821CU
335#define IOMUXC_GPIO_EMC_37_FLEXPWM2_PWMB01 0x401F80A8U, 0x1U, 0x401F835CU, 0x1U, 0x401F821CU
336#define IOMUXC_GPIO_EMC_37_LPUART5_RTS_B 0x401F80A8U, 0x2U, 0, 0, 0x401F821CU
337#define IOMUXC_GPIO_EMC_37_MQS_RIGHT 0x401F80A8U, 0x3U, 0, 0, 0x401F821CU
338#define IOMUXC_GPIO_EMC_37_LPSPI4_PCS2 0x401F80A8U, 0x4U, 0, 0, 0x401F821CU
339#define IOMUXC_GPIO_EMC_37_GPIO3_IO05 0x401F80A8U, 0x5U, 0, 0, 0x401F821CU
340#define IOMUXC_GPIO_EMC_37_ENET_RDATA03 0x401F80A8U, 0x6U, 0, 0, 0x401F821CU
341#define IOMUXC_GPIO_EMC_37_USDHC1_VSELECT 0x401F80A8U, 0x7U, 0, 0, 0x401F821CU
342
343#define IOMUXC_GPIO_EMC_38_SEMC_DATA14 0x401F80ACU, 0x0U, 0, 0, 0x401F8220U
344#define IOMUXC_GPIO_EMC_38_FLEXPWM2_PWMA00 0x401F80ACU, 0x1U, 0x401F8348U, 0x1U, 0x401F8220U
345#define IOMUXC_GPIO_EMC_38_LPUART5_TX 0x401F80ACU, 0x2U, 0x401F83F0U, 0x1U, 0x401F8220U
346#define IOMUXC_GPIO_EMC_38_MQS_LEFT 0x401F80ACU, 0x3U, 0, 0, 0x401F8220U
347#define IOMUXC_GPIO_EMC_38_LPSPI4_PCS3 0x401F80ACU, 0x4U, 0, 0, 0x401F8220U
348#define IOMUXC_GPIO_EMC_38_GPIO3_IO06 0x401F80ACU, 0x5U, 0, 0, 0x401F8220U
349#define IOMUXC_GPIO_EMC_38_ENET_RDATA02 0x401F80ACU, 0x6U, 0, 0, 0x401F8220U
350#define IOMUXC_GPIO_EMC_38_USDHC1_CD_B 0x401F80ACU, 0x7U, 0x401F8490U, 0x3U, 0x401F8220U
351
352#define IOMUXC_GPIO_EMC_39_SEMC_DATA15 0x401F80B0U, 0x0U, 0, 0, 0x401F8224U
353#define IOMUXC_GPIO_EMC_39_FLEXPWM2_PWMB00 0x401F80B0U, 0x1U, 0x401F8358U, 0x1U, 0x401F8224U
354#define IOMUXC_GPIO_EMC_39_LPUART5_RX 0x401F80B0U, 0x2U, 0x401F83ECU, 0x1U, 0x401F8224U
355#define IOMUXC_GPIO_EMC_39_USB_OTG1_OC 0x401F80B0U, 0x3U, 0x401F848CU, 0x2U, 0x401F8224U
356#define IOMUXC_GPIO_EMC_39_WDOG1_B 0x401F80B0U, 0x4U, 0, 0, 0x401F8224U
357#define IOMUXC_GPIO_EMC_39_GPIO3_IO07 0x401F80B0U, 0x5U, 0, 0, 0x401F8224U
358#define IOMUXC_GPIO_EMC_39_ENET_TX_ER 0x401F80B0U, 0x6U, 0, 0, 0x401F8224U
359#define IOMUXC_GPIO_EMC_39_GPT1_CLK 0x401F80B0U, 0x7U, 0, 0, 0x401F8224U
360
361#define IOMUXC_GPIO_EMC_40_SEMC_CSX00 0x401F80B4U, 0x0U, 0, 0, 0x401F8228U
362#define IOMUXC_GPIO_EMC_40_XBAR1_INOUT18 0x401F80B4U, 0x1U, 0x401F84BCU, 0x1U, 0x401F8228U
363#define IOMUXC_GPIO_EMC_40_SPDIF_OUT 0x401F80B4U, 0x2U, 0, 0, 0x401F8228U
364#define IOMUXC_GPIO_EMC_40_USB_OTG1_ID 0x401F80B4U, 0x3U, 0x401F82FCU, 0x2U, 0x401F8228U
365#define IOMUXC_GPIO_EMC_40_ENET_MDIO 0x401F80B4U, 0x4U, 0x401F8308U, 0x2U, 0x401F8228U
366#define IOMUXC_GPIO_EMC_40_GPIO3_IO08 0x401F80B4U, 0x5U, 0, 0, 0x401F8228U
367#define IOMUXC_GPIO_EMC_40_ENET_TDATA03 0x401F80B4U, 0x6U, 0, 0, 0x401F8228U
368#define IOMUXC_GPIO_EMC_40_GPT1_COMPARE3 0x401F80B4U, 0x7U, 0, 0, 0x401F8228U
369
370#define IOMUXC_GPIO_EMC_41_SEMC_READY 0x401F80B8U, 0x0U, 0x401F8484U, 0x1U, 0x401F822CU
371#define IOMUXC_GPIO_EMC_41_XBAR1_INOUT19 0x401F80B8U, 0x1U, 0x401F84C0U, 0x1U, 0x401F822CU
372#define IOMUXC_GPIO_EMC_41_SPDIF_IN 0x401F80B8U, 0x2U, 0x401F8488U, 0x1U, 0x401F822CU
373#define IOMUXC_GPIO_EMC_41_USB_OTG1_PWR 0x401F80B8U, 0x3U, 0, 0, 0x401F822CU
374#define IOMUXC_GPIO_EMC_41_ENET_MDC 0x401F80B8U, 0x4U, 0, 0, 0x401F822CU
375#define IOMUXC_GPIO_EMC_41_GPIO3_IO09 0x401F80B8U, 0x5U, 0, 0, 0x401F822CU
376#define IOMUXC_GPIO_EMC_41_ENET_TDATA02 0x401F80B8U, 0x6U, 0, 0, 0x401F822CU
377#define IOMUXC_GPIO_EMC_41_GPT1_COMPARE2 0x401F80B8U, 0x7U, 0, 0, 0x401F822CU
378
379#define IOMUXC_GPIO_AD_B0_00_JTAG_TMS 0x401F80BCU, 0x0U, 0, 0, 0x401F8230U
380#define IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x401F80BCU, 0x5U, 0, 0, 0x401F8230U
381#define IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1 0x401F80BCU, 0x7U, 0, 0, 0x401F8230U
382
383#define IOMUXC_GPIO_AD_B0_01_JTAG_TCK 0x401F80C0U, 0x0U, 0, 0, 0x401F8234U
384#define IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x401F80C0U, 0x5U, 0, 0, 0x401F8234U
385#define IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2 0x401F80C0U, 0x7U, 0, 0, 0x401F8234U
386
387#define IOMUXC_GPIO_AD_B0_02_JTAG_MOD 0x401F80C4U, 0x0U, 0, 0, 0x401F8238U
388#define IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x401F80C4U, 0x5U, 0, 0, 0x401F8238U
389#define IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1 0x401F80C4U, 0x7U, 0, 0, 0x401F8238U
390
391#define IOMUXC_GPIO_AD_B0_03_JTAG_TDI 0x401F80C8U, 0x0U, 0, 0, 0x401F823CU
392#define IOMUXC_GPIO_AD_B0_03_USDHC2_CD_B 0x401F80C8U, 0x1U, 0x401F8498U, 0x1U, 0x401F823CU
393#define IOMUXC_GPIO_AD_B0_03_WDOG1_B 0x401F80C8U, 0x2U, 0, 0, 0x401F823CU
394#define IOMUXC_GPIO_AD_B0_03_SAI1_MCLK 0x401F80C8U, 0x3U, 0x401F8430U, 0x1U, 0x401F823CU
395#define IOMUXC_GPIO_AD_B0_03_USDHC1_WP 0x401F80C8U, 0x4U, 0x401F8494U, 0x0U, 0x401F823CU
396#define IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x401F80C8U, 0x5U, 0, 0, 0x401F823CU
397#define IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x401F80C8U, 0x6U, 0x401F848CU, 0x0U, 0x401F823CU
398#define IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY 0x401F80C8U, 0x7U, 0x401F8300U, 0x2U, 0x401F823CU
399
400#define IOMUXC_GPIO_AD_B0_04_JTAG_TDO 0x401F80CCU, 0x0U, 0, 0, 0x401F8240U
401#define IOMUXC_GPIO_AD_B0_04_FLEXCAN1_TX 0x401F80CCU, 0x1U, 0, 0, 0x401F8240U
402#define IOMUXC_GPIO_AD_B0_04_USDHC1_WP 0x401F80CCU, 0x2U, 0x401F8494U, 0x1U, 0x401F8240U
403#define IOMUXC_GPIO_AD_B0_04_QTIMER2_TIMER0 0x401F80CCU, 0x3U, 0x401F8420U, 0x1U, 0x401F8240U
404#define IOMUXC_GPIO_AD_B0_04_ENET_MDIO 0x401F80CCU, 0x4U, 0x401F8308U, 0x1U, 0x401F8240U
405#define IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x401F80CCU, 0x5U, 0, 0, 0x401F8240U
406#define IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR 0x401F80CCU, 0x6U, 0, 0, 0x401F8240U
407#define IOMUXC_GPIO_AD_B0_04_EWM_OUT_B 0x401F80CCU, 0x7U, 0, 0, 0x401F8240U
408
409#define IOMUXC_GPIO_AD_B0_05_JTAG_TRSTB 0x401F80D0U, 0x0U, 0, 0, 0x401F8244U
410#define IOMUXC_GPIO_AD_B0_05_FLEXCAN1_RX 0x401F80D0U, 0x1U, 0x401F8320U, 0x2U, 0x401F8244U
411#define IOMUXC_GPIO_AD_B0_05_USDHC1_CD_B 0x401F80D0U, 0x2U, 0x401F8490U, 0x1U, 0x401F8244U
412#define IOMUXC_GPIO_AD_B0_05_QTIMER2_TIMER1 0x401F80D0U, 0x3U, 0x401F8424U, 0x1U, 0x401F8244U
413#define IOMUXC_GPIO_AD_B0_05_ENET_MDC 0x401F80D0U, 0x4U, 0, 0, 0x401F8244U
414#define IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x401F80D0U, 0x5U, 0, 0, 0x401F8244U
415#define IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID 0x401F80D0U, 0x6U, 0x401F82FCU, 0x0U, 0x401F8244U
416#define IOMUXC_GPIO_AD_B0_05_NMI_GLUE_NMI 0x401F80D0U, 0x7U, 0x401F840CU, 0x0U, 0x401F8244U
417
418#define IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER00 0x401F80D4U, 0x0U, 0, 0, 0x401F8248U
419#define IOMUXC_GPIO_AD_B0_06_MQS_RIGHT 0x401F80D4U, 0x1U, 0, 0, 0x401F8248U
420#define IOMUXC_GPIO_AD_B0_06_LPUART1_TX 0x401F80D4U, 0x2U, 0, 0, 0x401F8248U
421#define IOMUXC_GPIO_AD_B0_06_QTIMER2_TIMER2 0x401F80D4U, 0x3U, 0x401F8428U, 0x1U, 0x401F8248U
422#define IOMUXC_GPIO_AD_B0_06_FLEXPWM2_PWMA03 0x401F80D4U, 0x4U, 0x401F8354U, 0x0U, 0x401F8248U
423#define IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x401F80D4U, 0x5U, 0, 0, 0x401F8248U
424#define IOMUXC_GPIO_AD_B0_06_REF_32K_OUT 0x401F80D4U, 0x6U, 0, 0, 0x401F8248U
425
426#define IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER01 0x401F80D8U, 0x0U, 0, 0, 0x401F824CU
427#define IOMUXC_GPIO_AD_B0_07_MQS_LEFT 0x401F80D8U, 0x1U, 0, 0, 0x401F824CU
428#define IOMUXC_GPIO_AD_B0_07_LPUART1_RX 0x401F80D8U, 0x2U, 0, 0, 0x401F824CU
429#define IOMUXC_GPIO_AD_B0_07_QTIMER2_TIMER3 0x401F80D8U, 0x3U, 0x401F842CU, 0x1U, 0x401F824CU
430#define IOMUXC_GPIO_AD_B0_07_FLEXPWM2_PWMB03 0x401F80D8U, 0x4U, 0x401F8364U, 0x0U, 0x401F824CU
431#define IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x401F80D8U, 0x5U, 0, 0, 0x401F824CU
432#define IOMUXC_GPIO_AD_B0_07_REF_24M_OUT 0x401F80D8U, 0x6U, 0, 0, 0x401F824CU
433
434#define IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK 0x401F80DCU, 0x0U, 0x401F831CU, 0x1U, 0x401F8250U
435#define IOMUXC_GPIO_AD_B0_08_LPI2C3_SCL 0x401F80DCU, 0x1U, 0x401F838CU, 0x1U, 0x401F8250U
436#define IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B 0x401F80DCU, 0x2U, 0, 0, 0x401F8250U
437#define IOMUXC_GPIO_AD_B0_08_KPP_COL00 0x401F80DCU, 0x3U, 0, 0, 0x401F8250U
438#define IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1 0x401F80DCU, 0x4U, 0x401F8304U, 0x1U, 0x401F8250U
439#define IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x401F80DCU, 0x5U, 0, 0, 0x401F8250U
440#define IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV 0x401F80DCU, 0x6U, 0, 0, 0x401F8250U
441
442#define IOMUXC_GPIO_AD_B0_09_ENET_RDATA01 0x401F80E0U, 0x0U, 0x401F8310U, 0x1U, 0x401F8254U
443#define IOMUXC_GPIO_AD_B0_09_LPI2C3_SDA 0x401F80E0U, 0x1U, 0x401F8390U, 0x1U, 0x401F8254U
444#define IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B 0x401F80E0U, 0x2U, 0, 0, 0x401F8254U
445#define IOMUXC_GPIO_AD_B0_09_KPP_ROW00 0x401F80E0U, 0x3U, 0, 0, 0x401F8254U
446#define IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x401F80E0U, 0x5U, 0, 0, 0x401F8254U
447#define IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV 0x401F80E0U, 0x6U, 0, 0, 0x401F8254U
448
449#define IOMUXC_GPIO_AD_B0_10_ENET_RDATA00 0x401F80E4U, 0x0U, 0x401F830CU, 0x1U, 0x401F8258U
450#define IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK 0x401F80E4U, 0x1U, 0x401F83A0U, 0x1U, 0x401F8258U
451#define IOMUXC_GPIO_AD_B0_10_LPUART5_TX 0x401F80E4U, 0x2U, 0x401F83F0U, 0x0U, 0x401F8258U
452#define IOMUXC_GPIO_AD_B0_10_KPP_COL01 0x401F80E4U, 0x3U, 0, 0, 0x401F8258U
453#define IOMUXC_GPIO_AD_B0_10_FLEXPWM2_PWMA02 0x401F80E4U, 0x4U, 0x401F8350U, 0x0U, 0x401F8258U
454#define IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x401F80E4U, 0x5U, 0, 0, 0x401F8258U
455#define IOMUXC_GPIO_AD_B0_10_ARM_CM7_TRACE_CLK 0x401F80E4U, 0x6U, 0, 0, 0x401F8258U
456
457#define IOMUXC_GPIO_AD_B0_11_ENET_RX_EN 0x401F80E8U, 0x0U, 0x401F8314U, 0x1U, 0x401F825CU
458#define IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 0x401F80E8U, 0x1U, 0x401F839CU, 0x1U, 0x401F825CU
459#define IOMUXC_GPIO_AD_B0_11_LPUART5_RX 0x401F80E8U, 0x2U, 0x401F83ECU, 0x0U, 0x401F825CU
460#define IOMUXC_GPIO_AD_B0_11_KPP_ROW01 0x401F80E8U, 0x3U, 0, 0, 0x401F825CU
461#define IOMUXC_GPIO_AD_B0_11_FLEXPWM2_PWMB02 0x401F80E8U, 0x4U, 0x401F8360U, 0x0U, 0x401F825CU
462#define IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x401F80E8U, 0x5U, 0, 0, 0x401F825CU
463#define IOMUXC_GPIO_AD_B0_11_ARM_CM7_TRACE_SWO 0x401F80E8U, 0x6U, 0, 0, 0x401F825CU
464
465#define IOMUXC_GPIO_AD_B0_12_ENET_RX_ER 0x401F80ECU, 0x0U, 0x401F8318U, 0x1U, 0x401F8260U
466#define IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO 0x401F80ECU, 0x1U, 0x401F83A8U, 0x1U, 0x401F8260U
467#define IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B 0x401F80ECU, 0x2U, 0, 0, 0x401F8260U
468#define IOMUXC_GPIO_AD_B0_12_KPP_COL02 0x401F80ECU, 0x3U, 0, 0, 0x401F8260U
469#define IOMUXC_GPIO_AD_B0_12_FLEXPWM2_PWMA01 0x401F80ECU, 0x4U, 0x401F834CU, 0x0U, 0x401F8260U
470#define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x401F80ECU, 0x5U, 0, 0, 0x401F8260U
471#define IOMUXC_GPIO_AD_B0_12_ARM_CM7_TRACE00 0x401F80ECU, 0x6U, 0, 0, 0x401F8260U
472#define IOMUXC_GPIO_AD_B0_12_SNVS_HP_VIO_5_CTL 0x401F80ECU, 0x7U, 0, 0, 0x401F8260U
473
474#define IOMUXC_GPIO_AD_B0_13_ENET_TX_EN 0x401F80F0U, 0x0U, 0, 0, 0x401F8264U
475#define IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI 0x401F80F0U, 0x1U, 0x401F83A4U, 0x1U, 0x401F8264U
476#define IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B 0x401F80F0U, 0x2U, 0, 0, 0x401F8264U
477#define IOMUXC_GPIO_AD_B0_13_KPP_ROW02 0x401F80F0U, 0x3U, 0, 0, 0x401F8264U
478#define IOMUXC_GPIO_AD_B0_13_FLEXPWM2_PWMB01 0x401F80F0U, 0x4U, 0x401F835CU, 0x0U, 0x401F8264U
479#define IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x401F80F0U, 0x5U, 0, 0, 0x401F8264U
480#define IOMUXC_GPIO_AD_B0_13_ARM_CM7_TRACE01 0x401F80F0U, 0x6U, 0, 0, 0x401F8264U
481#define IOMUXC_GPIO_AD_B0_13_SNVS_HP_VIO_5_B 0x401F80F0U, 0x7U, 0, 0, 0x401F8264U
482
483#define IOMUXC_GPIO_AD_B0_14_ENET_TDATA00 0x401F80F4U, 0x0U, 0, 0, 0x401F8268U
484#define IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x401F80F4U, 0x1U, 0, 0, 0x401F8268U
485#define IOMUXC_GPIO_AD_B0_14_LPUART3_TX 0x401F80F4U, 0x2U, 0x401F83DCU, 0x1U, 0x401F8268U
486#define IOMUXC_GPIO_AD_B0_14_KPP_COL03 0x401F80F4U, 0x3U, 0, 0, 0x401F8268U
487#define IOMUXC_GPIO_AD_B0_14_FLEXPWM2_PWMA00 0x401F80F4U, 0x4U, 0x401F8348U, 0x0U, 0x401F8268U
488#define IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x401F80F4U, 0x5U, 0, 0, 0x401F8268U
489#define IOMUXC_GPIO_AD_B0_14_ARM_CM7_TRACE02 0x401F80F4U, 0x6U, 0, 0, 0x401F8268U
490#define IOMUXC_GPIO_AD_B0_14_WDOG1_ANY 0x401F80F4U, 0x7U, 0, 0, 0x401F8268U
491
492#define IOMUXC_GPIO_AD_B0_15_ENET_TDATA01 0x401F80F8U, 0x0U, 0, 0, 0x401F826CU
493#define IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x401F80F8U, 0x1U, 0x401F8324U, 0x2U, 0x401F826CU
494#define IOMUXC_GPIO_AD_B0_15_LPUART3_RX 0x401F80F8U, 0x2U, 0x401F83D8U, 0x1U, 0x401F826CU
495#define IOMUXC_GPIO_AD_B0_15_KPP_ROW03 0x401F80F8U, 0x3U, 0, 0, 0x401F826CU
496#define IOMUXC_GPIO_AD_B0_15_FLEXPWM2_PWMB00 0x401F80F8U, 0x4U, 0x401F8358U, 0x0U, 0x401F826CU
497#define IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x401F80F8U, 0x5U, 0, 0, 0x401F826CU
498#define IOMUXC_GPIO_AD_B0_15_ARM_CM7_TRACE03 0x401F80F8U, 0x6U, 0, 0, 0x401F826CU
499
500#define IOMUXC_GPIO_AD_B1_00_SEMC_READY 0x401F80FCU, 0x0U, 0x401F8484U, 0x0U, 0x401F8270U
501#define IOMUXC_GPIO_AD_B1_00_FLEXSPI_A_DATA03 0x401F80FCU, 0x1U, 0x401F8374U, 0x1U, 0x401F8270U
502#define IOMUXC_GPIO_AD_B1_00_FLEXCAN2_TX 0x401F80FCU, 0x2U, 0, 0, 0x401F8270U
503#define IOMUXC_GPIO_AD_B1_00_SAI1_MCLK 0x401F80FCU, 0x3U, 0x401F8430U, 0x2U, 0x401F8270U
504#define IOMUXC_GPIO_AD_B1_00_FLEXIO1_FLEXIO15 0x401F80FCU, 0x4U, 0, 0, 0x401F8270U
505#define IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x401F80FCU, 0x5U, 0, 0, 0x401F8270U
506#define IOMUXC_GPIO_AD_B1_00_ENET_1588_EVENT2_OUT 0x401F80FCU, 0x6U, 0, 0, 0x401F8270U
507#define IOMUXC_GPIO_AD_B1_00_KPP_COL04 0x401F80FCU, 0x7U, 0, 0, 0x401F8270U
508
509#define IOMUXC_GPIO_AD_B1_01_SEMC_CSX00 0x401F8100U, 0x0U, 0, 0, 0x401F8274U
510#define IOMUXC_GPIO_AD_B1_01_FLEXSPI_A_SCLK 0x401F8100U, 0x1U, 0x401F8378U, 0x1U, 0x401F8274U
511#define IOMUXC_GPIO_AD_B1_01_FLEXCAN2_RX 0x401F8100U, 0x2U, 0x401F8324U, 0x3U, 0x401F8274U
512#define IOMUXC_GPIO_AD_B1_01_SAI1_TX_BCLK 0x401F8100U, 0x3U, 0x401F844CU, 0x1U, 0x401F8274U
513#define IOMUXC_GPIO_AD_B1_01_FLEXIO1_FLEXIO14 0x401F8100U, 0x4U, 0, 0, 0x401F8274U
514#define IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x401F8100U, 0x5U, 0, 0, 0x401F8274U
515#define IOMUXC_GPIO_AD_B1_01_ENET_1588_EVENT2_IN 0x401F8100U, 0x6U, 0, 0, 0x401F8274U
516#define IOMUXC_GPIO_AD_B1_01_KPP_ROW04 0x401F8100U, 0x7U, 0, 0, 0x401F8274U
517
518#define IOMUXC_GPIO_AD_B1_02_SEMC_CSX01 0x401F8104U, 0x0U, 0, 0, 0x401F8278U
519#define IOMUXC_GPIO_AD_B1_02_FLEXSPI_A_DATA00 0x401F8104U, 0x1U, 0x401F8368U, 0x1U, 0x401F8278U
520#define IOMUXC_GPIO_AD_B1_02_LPSPI4_SCK 0x401F8104U, 0x2U, 0x401F83C0U, 0x0U, 0x401F8278U
521#define IOMUXC_GPIO_AD_B1_02_SAI1_TX_SYNC 0x401F8104U, 0x3U, 0x401F8450U, 0x1U, 0x401F8278U
522#define IOMUXC_GPIO_AD_B1_02_FLEXIO1_FLEXIO13 0x401F8104U, 0x4U, 0, 0, 0x401F8278U
523#define IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x401F8104U, 0x5U, 0, 0, 0x401F8278U
524#define IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT3_OUT 0x401F8104U, 0x6U, 0, 0, 0x401F8278U
525#define IOMUXC_GPIO_AD_B1_02_KPP_COL05 0x401F8104U, 0x7U, 0, 0, 0x401F8278U
526
527#define IOMUXC_GPIO_AD_B1_03_SEMC_CSX02 0x401F8108U, 0x0U, 0, 0, 0x401F827CU
528#define IOMUXC_GPIO_AD_B1_03_FLEXSPI_A_DATA02 0x401F8108U, 0x1U, 0x401F8370U, 0x1U, 0x401F827CU
529#define IOMUXC_GPIO_AD_B1_03_LPSPI4_PCS0 0x401F8108U, 0x2U, 0x401F83BCU, 0x0U, 0x401F827CU
530#define IOMUXC_GPIO_AD_B1_03_SAI1_TX_DATA00 0x401F8108U, 0x3U, 0, 0, 0x401F827CU
531#define IOMUXC_GPIO_AD_B1_03_FLEXIO1_FLEXIO12 0x401F8108U, 0x4U, 0, 0, 0x401F827CU
532#define IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x401F8108U, 0x5U, 0, 0, 0x401F827CU
533#define IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT3_IN 0x401F8108U, 0x6U, 0, 0, 0x401F827CU
534#define IOMUXC_GPIO_AD_B1_03_KPP_ROW05 0x401F8108U, 0x7U, 0, 0, 0x401F827CU
535
536#define IOMUXC_GPIO_AD_B1_04_SEMC_CSX03 0x401F810CU, 0x0U, 0, 0, 0x401F8280U
537#define IOMUXC_GPIO_AD_B1_04_FLEXSPI_A_DATA01 0x401F810CU, 0x1U, 0x401F836CU, 0x1U, 0x401F8280U
538#define IOMUXC_GPIO_AD_B1_04_LPSPI4_SDO 0x401F810CU, 0x2U, 0x401F83C8U, 0x0U, 0x401F8280U
539#define IOMUXC_GPIO_AD_B1_04_SAI1_RX_SYNC 0x401F810CU, 0x3U, 0x401F8448U, 0x0U, 0x401F8280U
540#define IOMUXC_GPIO_AD_B1_04_FLEXIO1_FLEXIO11 0x401F810CU, 0x4U, 0, 0, 0x401F8280U
541#define IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x401F810CU, 0x5U, 0, 0, 0x401F8280U
542#define IOMUXC_GPIO_AD_B1_04_LPSPI1_PCS1 0x401F810CU, 0x6U, 0, 0, 0x401F8280U
543#define IOMUXC_GPIO_AD_B1_04_KPP_COL06 0x401F810CU, 0x7U, 0, 0, 0x401F8280U
544
545#define IOMUXC_GPIO_AD_B1_05_USDHC1_WP 0x401F8110U, 0x0U, 0x401F8494U, 0x2U, 0x401F8284U
546#define IOMUXC_GPIO_AD_B1_05_FLEXSPI_A_SS0_B 0x401F8110U, 0x1U, 0, 0, 0x401F8284U
547#define IOMUXC_GPIO_AD_B1_05_LPSPI4_SDI 0x401F8110U, 0x2U, 0x401F83C4U, 0x0U, 0x401F8284U
548#define IOMUXC_GPIO_AD_B1_05_SAI1_RX_DATA00 0x401F8110U, 0x3U, 0x401F8438U, 0x1U, 0x401F8284U
549#define IOMUXC_GPIO_AD_B1_05_FLEXIO1_FLEXIO10 0x401F8110U, 0x4U, 0, 0, 0x401F8284U
550#define IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x401F8110U, 0x5U, 0, 0, 0x401F8284U
551#define IOMUXC_GPIO_AD_B1_05_LPSPI1_PCS2 0x401F8110U, 0x6U, 0, 0, 0x401F8284U
552#define IOMUXC_GPIO_AD_B1_05_KPP_ROW06 0x401F8110U, 0x7U, 0, 0, 0x401F8284U
553
554#define IOMUXC_GPIO_AD_B1_06_USDHC1_RESET_B 0x401F8114U, 0x0U, 0, 0, 0x401F8288U
555#define IOMUXC_GPIO_AD_B1_06_FLEXPWM1_PWMA00 0x401F8114U, 0x1U, 0x401F8328U, 0x0U, 0x401F8288U
556#define IOMUXC_GPIO_AD_B1_06_LPUART2_CTS_B 0x401F8114U, 0x2U, 0x401F83CCU, 0x0U, 0x401F8288U
557#define IOMUXC_GPIO_AD_B1_06_SAI1_RX_BCLK 0x401F8114U, 0x3U, 0x401F8434U, 0x0U, 0x401F8288U
558#define IOMUXC_GPIO_AD_B1_06_FLEXIO1_FLEXIO09 0x401F8114U, 0x4U, 0, 0, 0x401F8288U
559#define IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x401F8114U, 0x5U, 0, 0, 0x401F8288U
560#define IOMUXC_GPIO_AD_B1_06_LPSPI1_PCS3 0x401F8114U, 0x6U, 0, 0, 0x401F8288U
561#define IOMUXC_GPIO_AD_B1_06_KPP_COL07 0x401F8114U, 0x7U, 0, 0, 0x401F8288U
562
563#define IOMUXC_GPIO_AD_B1_07_USDHC1_VSELECT 0x401F8118U, 0x0U, 0, 0, 0x401F828CU
564#define IOMUXC_GPIO_AD_B1_07_FLEXPWM1_PWMB00 0x401F8118U, 0x1U, 0x401F8338U, 0x0U, 0x401F828CU
565#define IOMUXC_GPIO_AD_B1_07_LPUART2_RTS_B 0x401F8118U, 0x2U, 0, 0, 0x401F828CU
566#define IOMUXC_GPIO_AD_B1_07_SAI1_TX_DATA01 0x401F8118U, 0x3U, 0x401F8444U, 0x0U, 0x401F828CU
567#define IOMUXC_GPIO_AD_B1_07_FLEXIO1_FLEXIO08 0x401F8118U, 0x4U, 0, 0, 0x401F828CU
568#define IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x401F8118U, 0x5U, 0, 0, 0x401F828CU
569#define IOMUXC_GPIO_AD_B1_07_LPSPI3_PCS3 0x401F8118U, 0x6U, 0, 0, 0x401F828CU
570#define IOMUXC_GPIO_AD_B1_07_KPP_ROW07 0x401F8118U, 0x7U, 0, 0, 0x401F828CU
571
572#define IOMUXC_GPIO_AD_B1_08_LPI2C2_SCL 0x401F811CU, 0x0U, 0x401F8384U, 0x0U, 0x401F8290U
573#define IOMUXC_GPIO_AD_B1_08_FLEXPWM1_PWMA01 0x401F811CU, 0x1U, 0x401F832CU, 0x0U, 0x401F8290U
574#define IOMUXC_GPIO_AD_B1_08_LPUART2_TX 0x401F811CU, 0x2U, 0x401F83D4U, 0x0U, 0x401F8290U
575#define IOMUXC_GPIO_AD_B1_08_SAI1_TX_DATA02 0x401F811CU, 0x3U, 0x401F8440U, 0x0U, 0x401F8290U
576#define IOMUXC_GPIO_AD_B1_08_FLEXIO1_FLEXIO07 0x401F811CU, 0x4U, 0, 0, 0x401F8290U
577#define IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x401F811CU, 0x5U, 0, 0, 0x401F8290U
578#define IOMUXC_GPIO_AD_B1_08_LPSPI3_PCS2 0x401F811CU, 0x6U, 0, 0, 0x401F8290U
579#define IOMUXC_GPIO_AD_B1_08_XBAR1_INOUT12 0x401F811CU, 0x7U, 0x401F84B4U, 0x1U, 0x401F8290U
580
581#define IOMUXC_GPIO_AD_B1_09_LPI2C2_SDA 0x401F8120U, 0x0U, 0x401F8388U, 0x0U, 0x401F8294U
582#define IOMUXC_GPIO_AD_B1_09_FLEXPWM1_PWMB01 0x401F8120U, 0x1U, 0x401F833CU, 0x0U, 0x401F8294U
583#define IOMUXC_GPIO_AD_B1_09_LPUART2_RX 0x401F8120U, 0x2U, 0x401F83D0U, 0x0U, 0x401F8294U
584#define IOMUXC_GPIO_AD_B1_09_SAI1_TX_DATA03 0x401F8120U, 0x3U, 0x401F843CU, 0x0U, 0x401F8294U
585#define IOMUXC_GPIO_AD_B1_09_FLEXIO1_FLEXIO06 0x401F8120U, 0x4U, 0, 0, 0x401F8294U
586#define IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x401F8120U, 0x5U, 0, 0, 0x401F8294U
587#define IOMUXC_GPIO_AD_B1_09_LPSPI3_PCS1 0x401F8120U, 0x6U, 0, 0, 0x401F8294U
588#define IOMUXC_GPIO_AD_B1_09_XBAR1_INOUT13 0x401F8120U, 0x7U, 0x401F84B8U, 0x1U, 0x401F8294U
589
590#define IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR 0x401F8124U, 0x0U, 0, 0, 0x401F8298U
591#define IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA02 0x401F8124U, 0x1U, 0x401F8330U, 0x0U, 0x401F8298U
592#define IOMUXC_GPIO_AD_B1_10_LPUART4_TX 0x401F8124U, 0x2U, 0x401F83E8U, 0x1U, 0x401F8298U
593#define IOMUXC_GPIO_AD_B1_10_USDHC1_CD_B 0x401F8124U, 0x3U, 0x401F8490U, 0x2U, 0x401F8298U
594#define IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05 0x401F8124U, 0x4U, 0, 0, 0x401F8298U
595#define IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x401F8124U, 0x5U, 0, 0, 0x401F8298U
596#define IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1 0x401F8124U, 0x6U, 0, 0, 0x401F8298U
597
598#define IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID 0x401F8128U, 0x0U, 0x401F82FCU, 0x1U, 0x401F829CU
599#define IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB02 0x401F8128U, 0x1U, 0x401F8340U, 0x0U, 0x401F829CU
600#define IOMUXC_GPIO_AD_B1_11_LPUART4_RX 0x401F8128U, 0x2U, 0x401F83E4U, 0x1U, 0x401F829CU
601#define IOMUXC_GPIO_AD_B1_11_USDHC1_WP 0x401F8128U, 0x3U, 0x401F8494U, 0x3U, 0x401F829CU
602#define IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04 0x401F8128U, 0x4U, 0, 0, 0x401F829CU
603#define IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x401F8128U, 0x5U, 0, 0, 0x401F829CU
604#define IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1 0x401F8128U, 0x6U, 0, 0, 0x401F829CU
605
606#define IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC 0x401F812CU, 0x0U, 0x401F848CU, 0x1U, 0x401F82A0U
607#define IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x401F812CU, 0x1U, 0, 0, 0x401F82A0U
608#define IOMUXC_GPIO_AD_B1_12_LPSPI3_SCK 0x401F812CU, 0x2U, 0, 0, 0x401F82A0U
609#define IOMUXC_GPIO_AD_B1_12_USDHC2_CD_B 0x401F812CU, 0x3U, 0x401F8498U, 0x2U, 0x401F82A0U
610#define IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03 0x401F812CU, 0x4U, 0, 0, 0x401F82A0U
611#define IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x401F812CU, 0x5U, 0, 0, 0x401F82A0U
612#define IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA03 0x401F812CU, 0x6U, 0x401F8334U, 0x0U, 0x401F82A0U
613
614#define IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ 0x401F8130U, 0x0U, 0, 0, 0x401F82A4U
615#define IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x401F8130U, 0x1U, 0, 0, 0x401F82A4U
616#define IOMUXC_GPIO_AD_B1_13_LPSPI3_PCS0 0x401F8130U, 0x2U, 0, 0, 0x401F82A4U
617#define IOMUXC_GPIO_AD_B1_13_USDHC2_WP 0x401F8130U, 0x3U, 0x401F849CU, 0x0U, 0x401F82A4U
618#define IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02 0x401F8130U, 0x4U, 0, 0, 0x401F82A4U
619#define IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x401F8130U, 0x5U, 0, 0, 0x401F82A4U
620#define IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB03 0x401F8130U, 0x6U, 0x401F8344U, 0x0U, 0x401F82A4U
621
622#define IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL 0x401F8134U, 0x0U, 0x401F837CU, 0x1U, 0x401F82A8U
623#define IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x401F8134U, 0x1U, 0, 0, 0x401F82A8U
624#define IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x401F8134U, 0x2U, 0, 0, 0x401F82A8U
625#define IOMUXC_GPIO_AD_B1_14_ENET_1588_EVENT0_OUT 0x401F8134U, 0x3U, 0, 0, 0x401F82A8U
626#define IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01 0x401F8134U, 0x4U, 0, 0, 0x401F82A8U
627#define IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x401F8134U, 0x5U, 0, 0, 0x401F82A8U
628
629#define IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA 0x401F8138U, 0x0U, 0x401F8380U, 0x1U, 0x401F82ACU
630#define IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x401F8138U, 0x1U, 0, 0, 0x401F82ACU
631#define IOMUXC_GPIO_AD_B1_15_LPSPI3_SDI 0x401F8138U, 0x2U, 0, 0, 0x401F82ACU
632#define IOMUXC_GPIO_AD_B1_15_ENET_1588_EVENT0_IN 0x401F8138U, 0x3U, 0, 0, 0x401F82ACU
633#define IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00 0x401F8138U, 0x4U, 0, 0, 0x401F82ACU
634#define IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x401F8138U, 0x5U, 0, 0, 0x401F82ACU
635
636#define IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2 0x401F813CU, 0x0U, 0, 0, 0x401F82B0U
637#define IOMUXC_GPIO_SD_B0_00_QTIMER1_TIMER0 0x401F813CU, 0x1U, 0x401F8410U, 0x0U, 0x401F82B0U
638#define IOMUXC_GPIO_SD_B0_00_SAI1_MCLK 0x401F813CU, 0x2U, 0x401F8430U, 0x0U, 0x401F82B0U
639#define IOMUXC_GPIO_SD_B0_00_SAI2_MCLK 0x401F813CU, 0x3U, 0x401F8454U, 0x0U, 0x401F82B0U
640#define IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x401F813CU, 0x4U, 0x401F838CU, 0x0U, 0x401F82B0U
641#define IOMUXC_GPIO_SD_B0_00_GPIO3_IO13 0x401F813CU, 0x5U, 0, 0, 0x401F82B0U
642#define IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x401F813CU, 0x6U, 0, 0, 0x401F82B0U
643#define IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT14 0x401F813CU, 0x7U, 0x401F84A0U, 0x0U, 0x401F82B0U
644
645#define IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3 0x401F8140U, 0x0U, 0, 0, 0x401F82B4U
646#define IOMUXC_GPIO_SD_B0_01_QTIMER1_TIMER1 0x401F8140U, 0x1U, 0x401F8414U, 0x0U, 0x401F82B4U
647#define IOMUXC_GPIO_SD_B0_01_REF_24M_OUT 0x401F8140U, 0x2U, 0, 0, 0x401F82B4U
648#define IOMUXC_GPIO_SD_B0_01_SAI2_RX_SYNC 0x401F8140U, 0x3U, 0x401F8460U, 0x0U, 0x401F82B4U
649#define IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x401F8140U, 0x4U, 0x401F8390U, 0x0U, 0x401F82B4U
650#define IOMUXC_GPIO_SD_B0_01_GPIO3_IO14 0x401F8140U, 0x5U, 0, 0, 0x401F82B4U
651#define IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x401F8140U, 0x6U, 0, 0, 0x401F82B4U
652#define IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT15 0x401F8140U, 0x7U, 0x401F84A4U, 0x0U, 0x401F82B4U
653
654#define IOMUXC_GPIO_SD_B0_02_USDHC1_CMD 0x401F8144U, 0x0U, 0, 0, 0x401F82B8U
655#define IOMUXC_GPIO_SD_B0_02_QTIMER1_TIMER2 0x401F8144U, 0x1U, 0x401F8418U, 0x0U, 0x401F82B8U
656#define IOMUXC_GPIO_SD_B0_02_LPUART7_CTS_B 0x401F8144U, 0x2U, 0, 0, 0x401F82B8U
657#define IOMUXC_GPIO_SD_B0_02_SAI2_RX_BCLK 0x401F8144U, 0x3U, 0x401F8458U, 0x0U, 0x401F82B8U
658#define IOMUXC_GPIO_SD_B0_02_LPSPI1_SCK 0x401F8144U, 0x4U, 0x401F83A0U, 0x0U, 0x401F82B8U
659#define IOMUXC_GPIO_SD_B0_02_GPIO3_IO15 0x401F8144U, 0x5U, 0, 0, 0x401F82B8U
660#define IOMUXC_GPIO_SD_B0_02_ENET_MDIO 0x401F8144U, 0x6U, 0x401F8308U, 0x0U, 0x401F82B8U
661#define IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT16 0x401F8144U, 0x7U, 0x401F84A8U, 0x0U, 0x401F82B8U
662
663#define IOMUXC_GPIO_SD_B0_03_USDHC1_CLK 0x401F8148U, 0x0U, 0, 0, 0x401F82BCU
664#define IOMUXC_GPIO_SD_B0_03_QTIMER1_TIMER3 0x401F8148U, 0x1U, 0x401F841CU, 0x0U, 0x401F82BCU
665#define IOMUXC_GPIO_SD_B0_03_LPUART7_RTS_B 0x401F8148U, 0x2U, 0, 0, 0x401F82BCU
666#define IOMUXC_GPIO_SD_B0_03_SAI2_RX_DATA 0x401F8148U, 0x3U, 0x401F845CU, 0x0U, 0x401F82BCU
667#define IOMUXC_GPIO_SD_B0_03_LPSPI1_PCS0 0x401F8148U, 0x4U, 0x401F839CU, 0x0U, 0x401F82BCU
668#define IOMUXC_GPIO_SD_B0_03_GPIO3_IO16 0x401F8148U, 0x5U, 0, 0, 0x401F82BCU
669#define IOMUXC_GPIO_SD_B0_03_ENET_MDC 0x401F8148U, 0x6U, 0, 0, 0x401F82BCU
670
671#define IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0 0x401F814CU, 0x0U, 0, 0, 0x401F82C0U
672#define IOMUXC_GPIO_SD_B0_04_FLEXCAN2_TX 0x401F814CU, 0x1U, 0, 0, 0x401F82C0U
673#define IOMUXC_GPIO_SD_B0_04_LPUART7_TX 0x401F814CU, 0x2U, 0x401F8400U, 0x0U, 0x401F82C0U
674#define IOMUXC_GPIO_SD_B0_04_SAI2_TX_DATA 0x401F814CU, 0x3U, 0, 0, 0x401F82C0U
675#define IOMUXC_GPIO_SD_B0_04_LPSPI1_SDO 0x401F814CU, 0x4U, 0x401F83A8U, 0x0U, 0x401F82C0U
676#define IOMUXC_GPIO_SD_B0_04_GPIO3_IO17 0x401F814CU, 0x5U, 0, 0, 0x401F82C0U
677#define IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x401F814CU, 0x6U, 0, 0, 0x401F82C0U
678
679#define IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1 0x401F8150U, 0x0U, 0, 0, 0x401F82C4U
680#define IOMUXC_GPIO_SD_B0_05_FLEXCAN2_RX 0x401F8150U, 0x1U, 0x401F8324U, 0x0U, 0x401F82C4U
681#define IOMUXC_GPIO_SD_B0_05_LPUART7_RX 0x401F8150U, 0x2U, 0x401F83FCU, 0x0U, 0x401F82C4U
682#define IOMUXC_GPIO_SD_B0_05_SAI2_TX_BCLK 0x401F8150U, 0x3U, 0x401F8464U, 0x0U, 0x401F82C4U
683#define IOMUXC_GPIO_SD_B0_05_LPSPI1_SDI 0x401F8150U, 0x4U, 0x401F83A4U, 0x0U, 0x401F82C4U
684#define IOMUXC_GPIO_SD_B0_05_GPIO3_IO18 0x401F8150U, 0x5U, 0, 0, 0x401F82C4U
685#define IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x401F8150U, 0x6U, 0, 0, 0x401F82C4U
686
687#define IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B 0x401F8154U, 0x0U, 0x401F8490U, 0x0U, 0x401F82C8U
688#define IOMUXC_GPIO_SD_B0_06_USDHC1_RESET_B 0x401F8154U, 0x1U, 0, 0, 0x401F82C8U
689#define IOMUXC_GPIO_SD_B0_06_REF_32K_OUT 0x401F8154U, 0x2U, 0, 0, 0x401F82C8U
690#define IOMUXC_GPIO_SD_B0_06_SAI2_TX_SYNC 0x401F8154U, 0x3U, 0x401F8468U, 0x0U, 0x401F82C8U
691#define IOMUXC_GPIO_SD_B0_06_WDOG1_B 0x401F8154U, 0x4U, 0, 0, 0x401F82C8U
692#define IOMUXC_GPIO_SD_B0_06_GPIO3_IO19 0x401F8154U, 0x5U, 0, 0, 0x401F82C8U
693#define IOMUXC_GPIO_SD_B0_06_XBAR1_INOUT17 0x401F8154U, 0x6U, 0x401F84ACU, 0x0U, 0x401F82C8U
694
695#define IOMUXC_GPIO_SD_B1_00_USDHC2_DATA2 0x401F8158U, 0x0U, 0, 0, 0x401F82CCU
696#define IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA03 0x401F8158U, 0x1U, 0, 0, 0x401F82CCU
697#define IOMUXC_GPIO_SD_B1_00_LPUART6_TX 0x401F8158U, 0x2U, 0x401F83F8U, 0x1U, 0x401F82CCU
698#define IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT10 0x401F8158U, 0x3U, 0x401F84B0U, 0x1U, 0x401F82CCU
699#define IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX 0x401F8158U, 0x4U, 0, 0, 0x401F82CCU
700#define IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 0x401F8158U, 0x5U, 0, 0, 0x401F82CCU
701
702#define IOMUXC_GPIO_SD_B1_01_USDHC2_DATA3 0x401F815CU, 0x0U, 0, 0, 0x401F82D0U
703#define IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK 0x401F815CU, 0x1U, 0, 0, 0x401F82D0U
704#define IOMUXC_GPIO_SD_B1_01_LPUART6_RX 0x401F815CU, 0x2U, 0x401F83F4U, 0x1U, 0x401F82D0U
705#define IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B 0x401F815CU, 0x3U, 0, 0, 0x401F82D0U
706#define IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX 0x401F815CU, 0x4U, 0x401F8320U, 0x1U, 0x401F82D0U
707#define IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 0x401F815CU, 0x5U, 0, 0, 0x401F82D0U
708
709#define IOMUXC_GPIO_SD_B1_02_USDHC2_CMD 0x401F8160U, 0x0U, 0, 0, 0x401F82D4U
710#define IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA00 0x401F8160U, 0x1U, 0, 0, 0x401F82D4U
711#define IOMUXC_GPIO_SD_B1_02_LPUART8_TX 0x401F8160U, 0x2U, 0x401F8408U, 0x0U, 0x401F82D4U
712#define IOMUXC_GPIO_SD_B1_02_LPI2C4_SCL 0x401F8160U, 0x3U, 0x401F8394U, 0x1U, 0x401F82D4U
713#define IOMUXC_GPIO_SD_B1_02_ENET_1588_EVENT1_OUT 0x401F8160U, 0x4U, 0, 0, 0x401F82D4U
714#define IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 0x401F8160U, 0x5U, 0, 0, 0x401F82D4U
715#define IOMUXC_GPIO_SD_B1_02_CCM_CLKO1 0x401F8160U, 0x6U, 0, 0, 0x401F82D4U
716
717#define IOMUXC_GPIO_SD_B1_03_USDHC2_CLK 0x401F8164U, 0x0U, 0, 0, 0x401F82D8U
718#define IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA02 0x401F8164U, 0x1U, 0, 0, 0x401F82D8U
719#define IOMUXC_GPIO_SD_B1_03_LPUART8_RX 0x401F8164U, 0x2U, 0x401F8404U, 0x0U, 0x401F82D8U
720#define IOMUXC_GPIO_SD_B1_03_LPI2C4_SDA 0x401F8164U, 0x3U, 0x401F8398U, 0x1U, 0x401F82D8U
721#define IOMUXC_GPIO_SD_B1_03_ENET_1588_EVENT1_IN 0x401F8164U, 0x4U, 0, 0, 0x401F82D8U
722#define IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 0x401F8164U, 0x5U, 0, 0, 0x401F82D8U
723#define IOMUXC_GPIO_SD_B1_03_CCM_CLKO2 0x401F8164U, 0x6U, 0, 0, 0x401F82D8U
724
725#define IOMUXC_GPIO_SD_B1_04_USDHC2_DATA0 0x401F8168U, 0x0U, 0, 0, 0x401F82DCU
726#define IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA01 0x401F8168U, 0x1U, 0, 0, 0x401F82DCU
727#define IOMUXC_GPIO_SD_B1_04_ENET_TX_CLK 0x401F8168U, 0x2U, 0x401F831CU, 0x0U, 0x401F82DCU
728#define IOMUXC_GPIO_SD_B1_04_ENET_REF_CLK1 0x401F8168U, 0x3U, 0x401F8304U, 0x0U, 0x401F82DCU
729#define IOMUXC_GPIO_SD_B1_04_EWM_OUT_B 0x401F8168U, 0x4U, 0, 0, 0x401F82DCU
730#define IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 0x401F8168U, 0x5U, 0, 0, 0x401F82DCU
731#define IOMUXC_GPIO_SD_B1_04_CCM_WAIT 0x401F8168U, 0x6U, 0, 0, 0x401F82DCU
732
733#define IOMUXC_GPIO_SD_B1_05_USDHC2_DATA1 0x401F816CU, 0x0U, 0, 0, 0x401F82E0U
734#define IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x401F816CU, 0x1U, 0, 0, 0x401F82E0U
735#define IOMUXC_GPIO_SD_B1_05_ENET_RDATA01 0x401F816CU, 0x2U, 0x401F8310U, 0x0U, 0x401F82E0U
736#define IOMUXC_GPIO_SD_B1_05_SAI3_MCLK 0x401F816CU, 0x3U, 0x401F846CU, 0x0U, 0x401F82E0U
737#define IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B 0x401F816CU, 0x4U, 0, 0, 0x401F82E0U
738#define IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 0x401F816CU, 0x5U, 0, 0, 0x401F82E0U
739#define IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY 0x401F816CU, 0x6U, 0x401F8300U, 0x1U, 0x401F82E0U
740
741#define IOMUXC_GPIO_SD_B1_06_USDHC2_CD_B 0x401F8170U, 0x0U, 0x401F8498U, 0x0U, 0x401F82E4U
742#define IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03 0x401F8170U, 0x1U, 0x401F8374U, 0x0U, 0x401F82E4U
743#define IOMUXC_GPIO_SD_B1_06_ENET_RDATA00 0x401F8170U, 0x2U, 0x401F830CU, 0x0U, 0x401F82E4U
744#define IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK 0x401F8170U, 0x3U, 0x401F847CU, 0x0U, 0x401F82E4U
745#define IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x401F8170U, 0x4U, 0x401F83ACU, 0x2U, 0x401F82E4U
746#define IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 0x401F8170U, 0x5U, 0, 0, 0x401F82E4U
747#define IOMUXC_GPIO_SD_B1_06_CCM_STOP 0x401F8170U, 0x6U, 0, 0, 0x401F82E4U
748
749#define IOMUXC_GPIO_SD_B1_07_USDHC2_RESET_B 0x401F8174U, 0x0U, 0, 0, 0x401F82E8U
750#define IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x401F8174U, 0x1U, 0x401F8378U, 0x0U, 0x401F82E8U
751#define IOMUXC_GPIO_SD_B1_07_ENET_RX_EN 0x401F8174U, 0x2U, 0x401F8314U, 0x0U, 0x401F82E8U
752#define IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC 0x401F8174U, 0x3U, 0x401F8480U, 0x0U, 0x401F82E8U
753#define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x401F8174U, 0x4U, 0, 0, 0x401F82E8U
754#define IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 0x401F8174U, 0x5U, 0, 0, 0x401F82E8U
755
756#define IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x401F8178U, 0x0U, 0, 0, 0x401F82ECU
757#define IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00 0x401F8178U, 0x1U, 0x401F8368U, 0x0U, 0x401F82ECU
758#define IOMUXC_GPIO_SD_B1_08_ENET_RX_ER 0x401F8178U, 0x2U, 0x401F8318U, 0x0U, 0x401F82ECU
759#define IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA 0x401F8178U, 0x3U, 0, 0, 0x401F82ECU
760#define IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x401F8178U, 0x4U, 0x401F83B8U, 0x2U, 0x401F82ECU
761#define IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 0x401F8178U, 0x5U, 0, 0, 0x401F82ECU
762
763#define IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x401F817CU, 0x0U, 0, 0, 0x401F82F0U
764#define IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02 0x401F817CU, 0x1U, 0x401F8370U, 0x0U, 0x401F82F0U
765#define IOMUXC_GPIO_SD_B1_09_ENET_TX_EN 0x401F817CU, 0x2U, 0, 0, 0x401F82F0U
766#define IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK 0x401F817CU, 0x3U, 0x401F8470U, 0x0U, 0x401F82F0U
767#define IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x401F817CU, 0x4U, 0x401F83B4U, 0x2U, 0x401F82F0U
768#define IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 0x401F817CU, 0x5U, 0, 0, 0x401F82F0U
769
770#define IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x401F8180U, 0x0U, 0, 0, 0x401F82F4U
771#define IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01 0x401F8180U, 0x1U, 0x401F836CU, 0x0U, 0x401F82F4U
772#define IOMUXC_GPIO_SD_B1_10_ENET_TDATA00 0x401F8180U, 0x2U, 0, 0, 0x401F82F4U
773#define IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC 0x401F8180U, 0x3U, 0x401F8478U, 0x0U, 0x401F82F4U
774#define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x401F8180U, 0x4U, 0, 0, 0x401F82F4U
775#define IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 0x401F8180U, 0x5U, 0, 0, 0x401F82F4U
776
777#define IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x401F8184U, 0x0U, 0, 0, 0x401F82F8U
778#define IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B 0x401F8184U, 0x1U, 0, 0, 0x401F82F8U
779#define IOMUXC_GPIO_SD_B1_11_ENET_TDATA01 0x401F8184U, 0x2U, 0, 0, 0x401F82F8U
780#define IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA 0x401F8184U, 0x3U, 0x401F8474U, 0x0U, 0x401F82F8U
781#define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8184U, 0x4U, 0, 0, 0x401F82F8U
782#define IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 0x401F8184U, 0x5U, 0, 0, 0x401F82F8U
783
784#define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U
785#define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI 0x400A8000U, 0x7U, 0x401F840CU, 0x1U, 0x400A8018U
786
787#define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ 0x400A8004U, 0x0U, 0, 0, 0x400A801CU
788#define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 0x400A8004U, 0x5U, 0, 0, 0x400A801CU
789
790#define IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ 0x400A8008U, 0x0U, 0, 0, 0x400A8020U
791#define IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 0x400A8008U, 0x5U, 0, 0, 0x400A8020U
792
793#define IOMUXC_SNVS_TEST_MODE 0, 0, 0, 0, 0x400A800CU
794
795#define IOMUXC_SNVS_POR_B 0, 0, 0, 0, 0x400A8010U
796
797#define IOMUXC_SNVS_ONOFF 0, 0, 0, 0, 0x400A8014U
798
799/*@}*/
800
801#define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U)
802#define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U)
803
804typedef enum _iomuxc_gpr_mode
805{
806 kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK,
807 kIOMUXC_GPR_ENET1RefClkMode = IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_MASK,
808 kIOMUXC_GPR_ENET1TxClkOutputDir = IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK,
809 kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK,
810 kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK,
811 kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK,
812 kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK,
813 kIOMUXC_GPR_AHBClockEnable = (int)IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK,
814} iomuxc_gpr_mode_t;
815
816typedef enum _iomuxc_gpr_saimclk
817{
818 kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT,
819 kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT,
820 kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT,
821 kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT,
822 kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT,
823} iomuxc_gpr_saimclk_t;
824
825typedef enum _iomuxc_mqs_pwm_oversample_rate
826{
827 kIOMUXC_MqsPwmOverSampleRate32 = 0, /* MQS PWM over sampling rate 32. */
828 kIOMUXC_MqsPwmOverSampleRate64 = 1 /* MQS PWM over sampling rate 64. */
829} iomuxc_mqs_pwm_oversample_rate_t;
830
831#if defined(__cplusplus)
832extern "C" {
833#endif /*_cplusplus */
834
835/*! @name Configuration */
836/*@{*/
837
838/*!
839 * @brief Sets the IOMUXC pin mux mode.
840 * @note The first five parameters can be filled with the pin function ID macros.
841 *
842 * This is an example to set the PTA6 as the lpuart0_tx:
843 * @code
844 * IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0);
845 * @endcode
846 *
847 * This is an example to set the PTA0 as GPIOA0:
848 * @code
849 * IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0);
850 * @endcode
851 *
852 * @param muxRegister The pin mux register.
853 * @param muxMode The pin mux mode.
854 * @param inputRegister The select input register.
855 * @param inputDaisy The input daisy.
856 * @param configRegister The config register.
857 * @param inputOnfield Software input on field.
858 */
859static inline void IOMUXC_SetPinMux(uint32_t muxRegister,
860 uint32_t muxMode,
861 uint32_t inputRegister,
862 uint32_t inputDaisy,
863 uint32_t configRegister,
864 uint32_t inputOnfield)
865{
866 *((volatile uint32_t *)muxRegister) =
867 IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
868
869 if (inputRegister != 0UL)
870 {
871 *((volatile uint32_t *)inputRegister) = inputDaisy;
872 }
873}
874
875/*!
876 * @brief Sets the IOMUXC pin configuration.
877 * @note The previous five parameters can be filled with the pin function ID macros.
878 *
879 * This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS:
880 * @code
881 * IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U))
882 * @endcode
883 *
884 * @param muxRegister The pin mux register.
885 * @param muxMode The pin mux mode.
886 * @param inputRegister The select input register.
887 * @param inputDaisy The input daisy.
888 * @param configRegister The config register.
889 * @param configValue The pin config value.
890 */
891static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
892 uint32_t muxMode,
893 uint32_t inputRegister,
894 uint32_t inputDaisy,
895 uint32_t configRegister,
896 uint32_t configValue)
897{
898 if (configRegister != 0UL)
899 {
900 *((volatile uint32_t *)configRegister) = configValue;
901 }
902}
903
904/*!
905 * @brief Sets IOMUXC general configuration for some mode.
906 *
907 * @param base The IOMUXC GPR base address.
908 * @param mode The mode for setting. the mode is the logical OR of "iomuxc_gpr_mode"
909 * @param enable True enable false disable.
910 */
911static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable)
912{
913 mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK |
914 IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK |
915 IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK);
916
917 if (enable)
918 {
919 base->GPR1 |= mode;
920 }
921 else
922 {
923 base->GPR1 &= ~mode;
924 }
925}
926
927/*!
928 * @brief Sets IOMUXC general configuration for SAI MCLK selection.
929 *
930 * @param base The IOMUXC GPR base address.
931 * @param mclk The SAI MCLK.
932 * @param clkSrc The clock source. Take refer to register setting details for the clock source in RM.
933 */
934static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc)
935{
936 uint32_t gpr;
937
938 if (mclk > kIOMUXC_GPR_SAI1MClk2Sel)
939 {
940 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk);
941 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr;
942 }
943 else
944 {
945 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk);
946 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr;
947 }
948}
949
950/*!
951 * @brief Enters or exit MQS software reset.
952 *
953 * @param base The IOMUXC GPR base address.
954 * @param enable Enter or exit MQS software reset.
955 */
956static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enable)
957{
958 if (enable)
959 {
960 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
961 }
962 else
963 {
964 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
965 }
966}
967
968/*!
969 * @brief Enables or disables MQS.
970 *
971 * @param base The IOMUXC GPR base address.
972 * @param enable Enable or disable the MQS.
973 */
974static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable)
975{
976 if (enable)
977 {
978 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK;
979 }
980 else
981 {
982 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK;
983 }
984}
985
986/*!
987 * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk.
988 *
989 * @param base The IOMUXC GPR base address.
990 * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t".
991 * @param divider The divider ratio control for mclk from hmclk. mclk freq = 1 /(divider + 1) * hmclk freq.
992 */
993
994static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider)
995{
996 uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK);
997 base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider);
998}
999
1000/*@}*/
1001
1002#if defined(__cplusplus)
1003}
1004#endif /*_cplusplus */
1005
1006/*! @}*/
1007
1008#endif /* _FSL_IOMUXC_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_romapi.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_romapi.c
new file mode 100644
index 000000000..b8997d205
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_romapi.c
@@ -0,0 +1,170 @@
1/*
2 * Copyright 2017-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_romapi.h"
9
10/*******************************************************************************
11 * Definitions
12 ******************************************************************************/
13
14/* Component ID definition, used by tools. */
15#ifndef FSL_COMPONENT_ID
16#define FSL_COMPONENT_ID "driver.romapi"
17#endif
18
19/*******************************************************************************
20 * Prototypes
21 ******************************************************************************/
22
23/*!
24 * @brief Interface for the ROM FLEXSPI NOR flash driver.
25 */
26typedef struct
27{
28 uint32_t version;
29 status_t (*init)(uint32_t instance, flexspi_nor_config_t *config);
30 status_t (*program)(uint32_t instance, flexspi_nor_config_t *config, uint32_t dst_addr, const uint32_t *src);
31 uint32_t reserved0;
32 status_t (*erase)(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t lengthInBytes);
33 uint32_t reserved1;
34 void (*clear_cache)(uint32_t instance);
35 status_t (*xfer)(uint32_t instance, flexspi_xfer_t *xfer);
36 status_t (*update_lut)(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t seqNumber);
37 uint32_t reserved2;
38} flexspi_nor_driver_interface_t;
39
40/*!
41 * @brief Root of the bootloader api tree.
42 *
43 * An instance of this struct resides in read-only memory in the bootloader. It
44 * provides a user application access to APIs exported by the bootloader.
45 *
46 * @note The order of existing fields must not be changed.
47 */
48typedef struct
49{
50 void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing */
51 const uint32_t version; /*!< Bootloader version number */
52 const uint8_t *copyright; /*!< Bootloader Copyright */
53 const uint32_t reserved0;
54 flexspi_nor_driver_interface_t *flexSpiNorDriver; /*!< FLEXSPI NOR flash api */
55} bootloader_api_entry_t;
56
57/*******************************************************************************
58 * Variables
59 ******************************************************************************/
60
61#define g_bootloaderTree ((bootloader_api_entry_t *)*(uint32_t *)0x0020001cU)
62
63#define api_flexspi_nor_erase_sector \
64 ((status_t(*)(uint32_t instance, flexspi_nor_config_t * config, uint32_t address))0x0021055dU)
65#define api_flexspi_nor_erase_block \
66 ((status_t(*)(uint32_t instance, flexspi_nor_config_t * config, uint32_t address))0x002104a9U)
67/*******************************************************************************
68 * Codes
69 ******************************************************************************/
70
71/*******************************************************************************
72 * ROM FLEXSPI NOR driver
73 ******************************************************************************/
74#if defined(FSL_FEATURE_BOOT_ROM_HAS_ROMAPI) && FSL_FEATURE_BOOT_ROM_HAS_ROMAPI
75
76/*!
77 * @brief Initialize Serial NOR devices via FLEXSPI.
78 *
79 * @param instance storge the instance of FLEXSPI.
80 * @param config A pointer to the storage for the driver runtime state.
81 */
82status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config)
83{
84 return g_bootloaderTree->flexSpiNorDriver->init(instance, config);
85}
86
87/*!
88 * @brief Program data to Serial NOR via FLEXSPI.
89 *
90 * @param instance storge the instance of FLEXSPI.
91 * @param config A pointer to the storage for the driver runtime state.
92 * @param dstAddr A pointer to the desired flash memory to be programmed.
93 * @param src A pointer to the source buffer of data that is to be programmed
94 * into the NOR flash.
95 */
96status_t ROM_FLEXSPI_NorFlash_ProgramPage(uint32_t instance,
97 flexspi_nor_config_t *config,
98 uint32_t dstAddr,
99 const uint32_t *src)
100{
101 return g_bootloaderTree->flexSpiNorDriver->program(instance, config, dstAddr, src);
102}
103
104/*!
105 * @brief Erase Flash Region specified by address and length.
106 *
107 * @param instance storge the index of FLEXSPI.
108 * @param config A pointer to the storage for the driver runtime state.
109 * @param start The start address of the desired NOR flash memory to be erased.
110 * @param length The length, given in bytes to be erased.
111 */
112status_t ROM_FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length)
113{
114 return g_bootloaderTree->flexSpiNorDriver->erase(instance, config, start, length);
115}
116
117#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR
118/*!
119 * @brief Erase one sector specified by address.
120 *
121 * @param instance storge the index of FLEXSPI.
122 * @param config A pointer to the storage for the driver runtime state.
123 * @param start The start address of the desired NOR flash memory to be erased.
124 */
125status_t ROM_FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t start)
126{
127 return api_flexspi_nor_erase_sector(instance, config, start);
128}
129#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR */
130
131#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK
132/*!
133 * @brief Erase one block specified by address.
134 *
135 * @param instance storge the index of FLEXSPI.
136 * @param config A pointer to the storage for the driver runtime state.
137 * @param start The start address of the desired NOR flash memory to be erased.
138 */
139status_t ROM_FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t start)
140{
141 return api_flexspi_nor_erase_block(instance, config, start);
142}
143#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK */
144
145#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER
146/*! @brief FLEXSPI command */
147status_t ROM_FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer)
148{
149 return g_bootloaderTree->flexSpiNorDriver->xfer(instance, xfer);
150}
151#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER */
152
153#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT
154/*! @brief Configure FLEXSPI Lookup table. */
155status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance,
156 uint32_t seqIndex,
157 const uint32_t *lutBase,
158 uint32_t seqNumber)
159{
160 return g_bootloaderTree->flexSpiNorDriver->update_lut(instance, seqIndex, lutBase, seqNumber);
161}
162#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT */
163
164/*! @brief Software reset for the FLEXSPI logic. */
165void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance)
166{
167 g_bootloaderTree->flexSpiNorDriver->clear_cache(instance);
168}
169
170#endif /* FSL_FEATURE_BOOT_ROM_HAS_ROMAPI */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_romapi.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_romapi.h
new file mode 100644
index 000000000..75650b626
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/drivers/fsl_romapi.h
@@ -0,0 +1,554 @@
1/*
2 * Copyright 2017-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_ROMAPI_H_
9#define _FSL_ROMAPI_H_
10
11#include "fsl_common.h"
12
13/*!
14 * @addtogroup romapi
15 * @{
16 */
17
18/*! @brief ROMAPI version 1.1.0. */
19#define FSL_ROM_ROMAPI_VERSION (MAKE_VERSION(1U, 1U, 0U))
20/*! @brief ROM FLEXSPI NOR driver version 1.4.0. */
21#define FSL_ROM_FLEXSPINOR_DRIVER_VERSION (MAKE_VERSION(1U, 4U, 0U))
22
23/*!
24 * @name Common ROMAPI fearures info defines
25 * @{
26 */
27/* @brief ROM has FLEXSPI NOR API. */
28#define FSL_ROM_HAS_FLEXSPINOR_API (1)
29/* @brief ROM has run bootloader API. */
30#define FSL_ROM_HAS_RUNBOOTLOADER_API (0)
31/* @brief ROM has FLEXSPI NOR get config API. */
32#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_GET_CONFIG (0)
33/* @brief ROM has flash init API. */
34#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_FLASH_INIT (1)
35/* @brief ROM has erase API. */
36#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE (1)
37/* @brief ROM has erase sector API. */
38#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR (1)
39/* @brief ROM has erase block API. */
40#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK (1)
41/* @brief ROM has erase all API. */
42#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL (0)
43/* @brief ROM has page program API. */
44#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_PAGE_PROGRAM (1)
45/* @brief ROM has update lut API. */
46#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT (1)
47/* @brief ROM has FLEXSPI command API. */
48#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER (1)
49
50/*@}*/
51
52#define kROM_StatusGroup_FLEXSPI 60U /*!< ROM FLEXSPI status group number.*/
53#define kROM_StatusGroup_FLEXSPINOR 200U /*!< ROM FLEXSPI NOR status group number.*/
54
55#define FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
56 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
57 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
58
59/*! @brief Generate bit mask */
60#define FSL_ROM_FLEXSPI_BITMASK(bit_offset) (1U << (bit_offset))
61
62/*! @brief FLEXSPI memory config block related defintions */
63#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) /*!< ascii "FCFB" Big Endian */
64#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) /*!< V1.4.0 */
65
66#define CMD_SDR 0x01U
67#define CMD_DDR 0x21U
68#define RADDR_SDR 0x02U
69#define RADDR_DDR 0x22U
70#define CADDR_SDR 0x03U
71#define CADDR_DDR 0x23U
72#define MODE1_SDR 0x04U
73#define MODE1_DDR 0x24U
74#define MODE2_SDR 0x05U
75#define MODE2_DDR 0x25U
76#define MODE4_SDR 0x06U
77#define MODE4_DDR 0x26U
78#define MODE8_SDR 0x07U
79#define MODE8_DDR 0x27U
80#define WRITE_SDR 0x08U
81#define WRITE_DDR 0x28U
82#define READ_SDR 0x09U
83#define READ_DDR 0x29U
84#define LEARN_SDR 0x0AU
85#define LEARN_DDR 0x2AU
86#define DATSZ_SDR 0x0BU
87#define DATSZ_DDR 0x2BU
88#define DUMMY_SDR 0x0CU
89#define DUMMY_DDR 0x2CU
90#define DUMMY_RWDS_SDR 0x0DU
91#define DUMMY_RWDS_DDR 0x2DU
92#define JMP_ON_CS 0x1FU
93#define STOP 0U
94
95#define FLEXSPI_1PAD 0U
96#define FLEXSPI_2PAD 1U
97#define FLEXSPI_4PAD 2U
98#define FLEXSPI_8PAD 3U
99
100/*!
101 * NOR LUT sequence index used for default LUT assignment
102 * NOTE:
103 * The will take effect if the lut sequences are not customized.
104 */
105#define NOR_CMD_LUT_SEQ_IDX_READ 0U /*!< READ LUT sequence id in lookupTable stored in config block */
106#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1U /*!< Read Status LUT sequence id in lookupTable stored in config block */
107#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
108 2U /*!< Read status DPI/QPI/OPI sequence id in lookupTable stored in config block */
109#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3U /*!< Write Enable sequence id in lookupTable stored in config block */
110#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
111 4U /*!< Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block */
112#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5U /*!< Erase Sector sequence id in lookupTable stored in config block */
113#define NOR_CMD_LUT_SEQ_IDX_READID 7U
114#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8U /*!< Erase Block sequence id in lookupTable stored in config block */
115#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9U /*!< Program sequence id in lookupTable stored in config block */
116#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11U /*!< Chip Erase sequence in lookupTable id stored in config block */
117#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13U /*!< Read SFDP sequence in lookupTable id stored in config block */
118#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
119 14U /*!< Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block */
120#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
121 15U /*!< Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk */
122
123/*!
124 * @name Support for init FLEXSPI NOR configuration
125 * @{
126 */
127/*! @brief Flash Pad Definitions */
128enum
129{
130 kSerialFlash_1Pad = 1U,
131 kSerialFlash_2Pads = 2U,
132 kSerialFlash_4Pads = 4U,
133 kSerialFlash_8Pads = 8U,
134};
135
136/*! @brief FLEXSPI clock configuration type */
137enum
138{
139 kFLEXSPIClk_SDR, /*!< Clock configure for SDR mode */
140 kFLEXSPIClk_DDR, /*!< Clock configurat for DDR mode */
141};
142
143/*! @brief FLEXSPI Read Sample Clock Source definition */
144typedef enum _flexspi_read_sample_clk
145{
146 kFLEXSPIReadSampleClk_LoopbackInternally = 0U,
147 kFLEXSPIReadSampleClk_LoopbackFromDqsPad = 1U,
148 kFLEXSPIReadSampleClk_LoopbackFromSckPad = 2U,
149 kFLEXSPIReadSampleClk_ExternalInputFromDqsPad = 3U,
150} flexspi_read_sample_clk_t;
151
152/*! @brief Flash Type Definition */
153enum
154{
155 kFLEXSPIDeviceType_SerialNOR = 1U, /*!< Flash device is Serial NOR */
156};
157
158/*! @brief Flash Configuration Command Type */
159enum
160{
161 kDeviceConfigCmdType_Generic, /*!< Generic command, for example: configure dummy cycles, drive strength, etc */
162 kDeviceConfigCmdType_QuadEnable, /*!< Quad Enable command */
163 kDeviceConfigCmdType_Spi2Xpi, /*!< Switch from SPI to DPI/QPI/OPI mode */
164 kDeviceConfigCmdType_Xpi2Spi, /*!< Switch from DPI/QPI/OPI to SPI mode */
165 kDeviceConfigCmdType_Spi2NoCmd, /*!< Switch to 0-4-4/0-8-8 mode */
166 kDeviceConfigCmdType_Reset, /*!< Reset device command */
167};
168
169/*! @brief Defintions for FLEXSPI Serial Clock Frequency */
170typedef enum _flexspi_serial_clk_freq
171{
172 kFLEXSPISerialClk_NoChange = 0U,
173 kFLEXSPISerialClk_30MHz = 1U,
174 kFLEXSPISerialClk_50MHz = 2U,
175 kFLEXSPISerialClk_60MHz = 3U,
176 kFLEXSPISerialClk_75MHz = 4U,
177 kFLEXSPISerialClk_80MHz = 5U,
178 kFLEXSPISerialClk_100MHz = 6U,
179 kFLEXSPISerialClk_133MHz = 7U,
180 kFLEXSPISerialClk_166MHz = 8U,
181 kFLEXSPISerialClk_200MHz = 9U,
182} flexspi_serial_clk_freq_t;
183
184/*! @brief Misc feature bit definitions */
185enum
186{
187 kFLEXSPIMiscOffset_DiffClkEnable = 0U, /*!< Bit for Differential clock enable */
188 kFLEXSPIMiscOffset_Ck2Enable = 1U, /*!< Bit for CK2 enable */
189 kFLEXSPIMiscOffset_ParallelEnable = 2U, /*!< Bit for Parallel mode enable */
190 kFLEXSPIMiscOffset_WordAddressableEnable = 3U, /*!< Bit for Word Addressable enable */
191 kFLEXSPIMiscOffset_SafeConfigFreqEnable = 4U, /*!< Bit for Safe Configuration Frequency enable */
192 kFLEXSPIMiscOffset_PadSettingOverrideEnable = 5U, /*!< Bit for Pad setting override enable */
193 kFLEXSPIMiscOffset_DdrModeEnable = 6U, /*!< Bit for DDR clock confiuration indication. */
194 kFLEXSPIMiscOffset_UseValidTimeForAllFreq = 7U, /*!< Bit for DLLCR settings under all modes */
195};
196
197/*@}*/
198
199/*!
200 * @name FLEXSPI NOR Configuration
201 * @{
202 */
203
204/*! @brief FLEXSPI LUT Sequence structure */
205typedef struct _flexspi_lut_seq
206{
207 uint8_t seqNum; /*!< Sequence Number, valid number: 1-16 */
208 uint8_t seqId; /*!< Sequence Index, valid number: 0-15 */
209 uint16_t reserved;
210} flexspi_lut_seq_t;
211
212typedef struct
213{
214 uint8_t time_100ps; /*!< Data valid time, in terms of 100ps */
215 uint8_t delay_cells; /*!< Data valid time, in terms of delay cells */
216} flexspi_dll_time_t;
217
218/*! @brief FLEXSPI Memory Configuration Block */
219typedef struct _flexspi_mem_config
220{
221 uint32_t tag; /*!< [0x000-0x003] Tag, fixed value 0x42464346UL */
222 uint32_t version; /*!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */
223 uint32_t reserved0; /*!< [0x008-0x00b] Reserved for future use */
224 uint8_t readSampleClkSrc; /*!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */
225 uint8_t csHoldTime; /*!< [0x00d-0x00d] Data hold time, default value: 3 */
226 uint8_t csSetupTime; /*!< [0x00e-0x00e] Date setup time, default value: 3 */
227 uint8_t columnAddressWidth; /*!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
228 Serial NAND, need to refer to datasheet */
229 uint8_t deviceModeCfgEnable; /*!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */
230 uint8_t deviceModeType; /*!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
231 Generic configuration, etc. */
232 uint16_t waitTimeCfgCommands; /*!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
233 DPI/QPI/OPI switch or reset command */
234 flexspi_lut_seq_t deviceModeSeq; /*!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
235 sequence number, [31:16] Reserved */
236 uint32_t deviceModeArg; /*!< [0x018-0x01b] Argument/Parameter for device configuration */
237 uint8_t configCmdEnable; /*!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */
238 uint8_t configModeType[3]; /*!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */
239 flexspi_lut_seq_t
240 configCmdSeqs[3]; /*!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq */
241 uint32_t reserved1; /*!< [0x02c-0x02f] Reserved for future use */
242 uint32_t configCmdArgs[3]; /*!< [0x030-0x03b] Arguments/Parameters for device Configuration commands */
243 uint32_t reserved2; /*!< [0x03c-0x03f] Reserved for future use */
244 uint32_t controllerMiscOption; /*!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
245 details */
246 uint8_t deviceType; /*!< [0x044-0x044] Device Type: See Flash Type Definition for more details */
247 uint8_t sflashPadType; /*!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */
248 uint8_t serialClkFreq; /*!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
249 Chapter for more details */
250 uint8_t
251 lutCustomSeqEnable; /*!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
252 be done using 1 LUT sequence, currently, only applicable to HyperFLASH */
253 uint32_t reserved3[2]; /*!< [0x048-0x04f] Reserved for future use */
254 uint32_t sflashA1Size; /*!< [0x050-0x053] Size of Flash connected to A1 */
255 uint32_t sflashA2Size; /*!< [0x054-0x057] Size of Flash connected to A2 */
256 uint32_t sflashB1Size; /*!< [0x058-0x05b] Size of Flash connected to B1 */
257 uint32_t sflashB2Size; /*!< [0x05c-0x05f] Size of Flash connected to B2 */
258 uint32_t csPadSettingOverride; /*!< [0x060-0x063] CS pad setting override value */
259 uint32_t sclkPadSettingOverride; /*!< [0x064-0x067] SCK pad setting override value */
260 uint32_t dataPadSettingOverride; /*!< [0x068-0x06b] data pad setting override value */
261 uint32_t dqsPadSettingOverride; /*!< [0x06c-0x06f] DQS pad setting override value */
262 uint32_t timeoutInMs; /*!< [0x070-0x073] Timeout threshold for read status command */
263 uint32_t commandInterval; /*!< [0x074-0x077] CS deselect interval between two commands */
264 flexspi_dll_time_t dataValidTime[2]; /*!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B */
265 uint16_t busyOffset; /*!< [0x07c-0x07d] Busy offset, valid value: 0-31 */
266 uint16_t busyBitPolarity; /*!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
267 busy flag is 0 when flash device is busy */
268 uint32_t lookupTable[64]; /*!< [0x080-0x17f] Lookup table holds Flash command sequences */
269 flexspi_lut_seq_t lutCustomSeq[12]; /*!< [0x180-0x1af] Customizable LUT Sequences */
270 uint32_t reserved4[4]; /*!< [0x1b0-0x1bf] Reserved for future use */
271} flexspi_mem_config_t;
272
273/*! @brief Serial NOR configuration block */
274typedef struct _flexspi_nor_config
275{
276 flexspi_mem_config_t memConfig; /*!< Common memory configuration info via FLEXSPI */
277 uint32_t pageSize; /*!< Page size of Serial NOR */
278 uint32_t sectorSize; /*!< Sector size of Serial NOR */
279 uint8_t ipcmdSerialClkFreq; /*!< Clock frequency for IP command */
280 uint8_t isUniformBlockSize; /*!< Sector/Block size is the same */
281 uint8_t isDataOrderSwapped; /*!< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */
282 uint8_t reserved0[1]; /*!< Reserved for future use */
283 uint8_t serialNorType; /*!< Serial NOR Flash type: 0/1/2/3 */
284 uint8_t needExitNoCmdMode; /*!< Need to exit NoCmd mode before other IP command */
285 uint8_t halfClkForNonReadCmd; /*!< Half the Serial Clock for non-read command: true/false */
286 uint8_t needRestoreNoCmdMode; /*!< Need to Restore NoCmd mode after IP commmand execution */
287 uint32_t blockSize; /*!< Block size */
288 uint32_t reserve2[11]; /*!< Reserved for future use */
289} flexspi_nor_config_t;
290
291/*@}*/
292
293/*! @brief Manufacturer ID */
294enum
295{
296 kSerialFlash_ISSI_ManufacturerID = 0x9DU, /*!< Manufacturer ID of the ISSI serial flash */
297 kSerialFlash_Adesto_ManufacturerID = 0x1F, /*!< Manufacturer ID of the Adesto Technologies serial flash*/
298 kSerialFlash_Winbond_ManufacturerID = 0xEFU, /*!< Manufacturer ID of the Winbond serial flash */
299 kSerialFlash_Cypress_ManufacturerID = 0x01U, /*!< Manufacturer ID for Cypress */
300};
301
302/*! @brief ROM FLEXSPI NOR flash status */
303enum _flexspi_nor_status
304{
305 kStatus_ROM_FLEXSPI_SequenceExecutionTimeout =
306 MAKE_STATUS(kROM_StatusGroup_FLEXSPI, 0), /*!< Status for Sequence Execution timeout */
307 kStatus_ROM_FLEXSPI_InvalidSequence = MAKE_STATUS(kROM_StatusGroup_FLEXSPI, 1), /*!< Status for Invalid Sequence */
308 kStatus_ROM_FLEXSPI_DeviceTimeout = MAKE_STATUS(kROM_StatusGroup_FLEXSPI, 2), /*!< Status for Device timeout */
309 kStatus_FLEXSPINOR_DTRRead_DummyProbeFailed =
310 MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 10), /*!< Status for DDR Read dummy probe failure */
311 kStatus_ROM_FLEXSPINOR_SFDP_NotFound =
312 MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 7), /*!< Status for SFDP read failure */
313 kStatus_ROM_FLEXSPINOR_Flash_NotFound =
314 MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 9), /*!< Status for Flash detection failure */
315};
316
317typedef enum _flexspi_operation
318{
319 kFLEXSPIOperation_Command, /*!< FLEXSPI operation: Only command, both TX and RX buffer are ignored. */
320 kFLEXSPIOperation_Config, /*!< FLEXSPI operation: Configure device mode, the TX FIFO size is fixed in LUT. */
321 kFLEXSPIOperation_Write, /*!< FLEXSPI operation: Write, only TX buffer is effective */
322 kFLEXSPIOperation_Read, /*!< FLEXSPI operation: Read, only Rx Buffer is effective. */
323 kFLEXSPIOperation_End = kFLEXSPIOperation_Read,
324} flexspi_operation_t;
325
326/*! @brief FLEXSPI Transfer Context */
327typedef struct _flexspi_xfer
328{
329 flexspi_operation_t operation; /*!< FLEXSPI operation */
330 uint32_t baseAddress; /*!< FLEXSPI operation base address */
331 uint32_t seqId; /*!< Sequence Id */
332 uint32_t seqNum; /*!< Sequence Number */
333 bool isParallelModeEnable; /*!< Is a parallel transfer */
334 uint32_t *txBuffer; /*!< Tx buffer */
335 uint32_t txSize; /*!< Tx size in bytes */
336 uint32_t *rxBuffer; /*!< Rx buffer */
337 uint32_t rxSize; /*!< Rx size in bytes */
338} flexspi_xfer_t;
339
340#ifdef __cplusplus
341extern "C" {
342#endif
343
344#if defined(FSL_FEATURE_BOOT_ROM_HAS_ROMAPI) && FSL_FEATURE_BOOT_ROM_HAS_ROMAPI
345
346/*!
347 * @name Initialization
348 * @{
349 */
350
351/*!
352 * @brief Initialize Serial NOR devices via FLEXSPI
353 *
354 * This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs.
355 *
356 * @param instance storge the instance of FLEXSPI.
357 * @param config A pointer to the storage for the driver runtime state.
358 *
359 * @retval kStatus_Success Api was executed succesfuly.
360 * @retval kStatus_InvalidArgument A invalid argument is provided.
361 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
362 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
363 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
364 */
365status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config);
366
367/*@}*/
368
369/*!
370 * @name Programming
371 * @{
372 */
373/*!
374 * @brief Program data to Serial NOR via FLEXSPI.
375 *
376 * This function programs the NOR flash memory with the dest address for a given
377 * flash area as determined by the dst address and the length.
378 *
379 * @param instance storge the instance of FLEXSPI.
380 * @param config A pointer to the storage for the driver runtime state.
381 * @param dstAddr A pointer to the desired flash memory to be programmed.
382 * NOTE:
383 * It is recommended that use page aligned access;
384 * If the dstAddr is not aligned to page,the driver automatically
385 * aligns address down with the page address.
386 * @param src A pointer to the source buffer of data that is to be programmed
387 * into the NOR flash.
388 *
389 * @retval kStatus_Success Api was executed succesfuly.
390 * @retval kStatus_InvalidArgument A invalid argument is provided.
391 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
392 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
393 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
394 */
395status_t ROM_FLEXSPI_NorFlash_ProgramPage(uint32_t instance,
396 flexspi_nor_config_t *config,
397 uint32_t dstAddr,
398 const uint32_t *src);
399
400/*@}*/
401
402/*!
403 * @name Erasing
404 * @{
405 */
406#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR
407/*!
408 * @brief Erase one sector specified by address
409 *
410 * This function erases one of NOR flash sectors based on the desired address.
411 *
412 * @param instance storge the index of FLEXSPI.
413 * @param config A pointer to the storage for the driver runtime state.
414 * @param address The start address of the desired NOR flash memory to be erased.
415 * NOTE:
416 * It is recommended that use sector-aligned access nor device;
417 * If dstAddr is not aligned with the sector,The driver automatically
418 * aligns address down with the sector address.
419 *
420 * @retval kStatus_Success Api was executed succesfuly.
421 * @retval kStatus_InvalidArgument A invalid argument is provided.
422 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
423 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
424 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
425 */
426status_t ROM_FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address);
427#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR */
428
429#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK
430/*!
431 * @brief Erase one block specified by address
432 *
433 * This function erases one block of NOR flash based on the desired address.
434 *
435 * @param instance storge the index of FLEXSPI.
436 * @param config A pointer to the storage for the driver runtime state.
437 * @param start The start address of the desired NOR flash memory to be erased.
438 * NOTE:
439 * It is recommended that use block-aligned access nor device;
440 * If dstAddr is not aligned with the block,The driver automatically
441 * aligns address down with the block address.
442 *
443 * @retval kStatus_Success Api was executed succesfuly.
444 * @retval kStatus_InvalidArgument A invalid argument is provided.
445 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
446 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
447 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
448 */
449status_t ROM_FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t start);
450#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK */
451
452/*!
453 * @brief Erase Flash Region specified by address and length
454 *
455 * This function erases the appropriate number of flash sectors based on the
456 * desired start address and length.
457 *
458 * @param instance storge the index of FLEXSPI.
459 * @param config A pointer to the storage for the driver runtime state.
460 * @param start The start address of the desired NOR flash memory to be erased.
461 * NOTE:
462 * It is recommended that use sector-aligned access nor device;
463 * If dstAddr is not aligned with the sector,the driver automatically
464 * aligns address down with the sector address.
465 * @param length The length, given in bytes to be erased.
466 * NOTE:
467 * It is recommended that use sector-aligned access nor device;
468 * If length is not aligned with the sector,the driver automatically
469 * aligns up with the sector.
470 * @retval kStatus_Success Api was executed succesfuly.
471 * @retval kStatus_InvalidArgument A invalid argument is provided.
472 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
473 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
474 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
475 */
476status_t ROM_FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length);
477
478/*@}*/
479
480/*!
481 * @name Command
482 * @{
483 */
484
485#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER
486/*!
487 * @brief FLEXSPI command
488 *
489 * This function is used to perform the command write sequence to the NOR device.
490 *
491 * @param instance storge the index of FLEXSPI.
492 * @param xfer A pointer to the storage FLEXSPI Transfer Context.
493 *
494 * @retval kStatus_Success Api was executed succesfuly.
495 * @retval kStatus_InvalidArgument A invalid argument is provided.
496 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
497 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
498 */
499status_t ROM_FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer);
500#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER */
501/*@}*/
502
503/*!
504 * @name UpdateLut
505 * @{
506 */
507#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT
508/*!
509 * @brief Configure FLEXSPI Lookup table
510 *
511 * @param instance storge the index of FLEXSPI.
512 * @param seqIndex storge the sequence Id.
513 * @param lutBase A pointer to the look-up-table for command sequences.
514 * @param seqNumber storge sequence number.
515 *
516 * @retval kStatus_Success Api was executed succesfuly.
517 * @retval kStatus_InvalidArgument A invalid argument is provided.
518 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
519 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
520 */
521status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance,
522 uint32_t seqIndex,
523 const uint32_t *lutBase,
524 uint32_t seqNumber);
525#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT */
526
527/*@}*/
528
529/*!
530 * @name ClearCache
531 * @{
532 */
533
534/*!
535 * @brief Software reset for the FLEXSPI logic.
536 *
537 * This function sets the software reset flags for both AHB and buffer domain and
538 * resets both AHB buffer and also IP FIFOs.
539 *
540 * @param instance storge the index of FLEXSPI.
541 */
542void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance);
543
544/*@}*/
545
546#endif /* FSL_FEATURE_BOOT_ROM_HAS_ROMAPI */
547
548#ifdef __cplusplus
549}
550#endif
551
552/*! @}*/
553
554#endif /* _FSL_ROMAPI_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 21:50:10 +0100