diff options
Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1024')
47 files changed, 55683 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1024/MIMXRT1024.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1024/MIMXRT1024.h new file mode 100644 index 000000000..f4612bff1 --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1024/MIMXRT1024.h | |||
| @@ -0,0 +1,41256 @@ | |||
| 1 | /* | ||
| 2 | ** ################################################################### | ||
| 3 | ** Processors: MIMXRT1024CAG4A | ||
| 4 | ** MIMXRT1024DAG5A | ||
| 5 | ** | ||
| 6 | ** Compilers: Freescale C/C++ for Embedded ARM | ||
| 7 | ** GNU C Compiler | ||
| 8 | ** IAR ANSI C/C++ Compiler for ARM | ||
| 9 | ** Keil ARM C/C++ Compiler | ||
| 10 | ** MCUXpresso Compiler | ||
| 11 | ** | ||
| 12 | ** Reference manual: IMXRT1024RM Rev.0, 09/2020 | IMXRT102xSRM Rev.0 | ||
| 13 | ** Version: rev. 0.1, 2020-01-15 | ||
| 14 | ** Build: b200709 | ||
| 15 | ** | ||
| 16 | ** Abstract: | ||
| 17 | ** CMSIS Peripheral Access Layer for MIMXRT1024 | ||
| 18 | ** | ||
| 19 | ** Copyright 1997-2016 Freescale Semiconductor, Inc. | ||
| 20 | ** Copyright 2016-2020 NXP | ||
| 21 | ** All rights reserved. | ||
| 22 | ** | ||
| 23 | ** SPDX-License-Identifier: BSD-3-Clause | ||
| 24 | ** | ||
| 25 | ** http: www.nxp.com | ||
| 26 | ** mail: [email protected] | ||
| 27 | ** | ||
| 28 | ** Revisions: | ||
| 29 | ** - rev. 0.1 (2020-01-15) | ||
| 30 | ** Initial version. | ||
| 31 | ** | ||
| 32 | ** ################################################################### | ||
| 33 | */ | ||
| 34 | |||
| 35 | /*! | ||
| 36 | * @file MIMXRT1024.h | ||
| 37 | * @version 0.1 | ||
| 38 | * @date 2020-01-15 | ||
| 39 | * @brief CMSIS Peripheral Access Layer for MIMXRT1024 | ||
| 40 | * | ||
| 41 | * CMSIS Peripheral Access Layer for MIMXRT1024 | ||
| 42 | */ | ||
| 43 | |||
| 44 | #ifndef _MIMXRT1024_H_ | ||
| 45 | #define _MIMXRT1024_H_ /**< Symbol preventing repeated inclusion */ | ||
| 46 | |||
| 47 | /** Memory map major version (memory maps with equal major version number are | ||
| 48 | * compatible) */ | ||
| 49 | #define MCU_MEM_MAP_VERSION 0x0000U | ||
| 50 | /** Memory map minor version */ | ||
| 51 | #define MCU_MEM_MAP_VERSION_MINOR 0x0001U | ||
| 52 | |||
| 53 | |||
| 54 | /* ---------------------------------------------------------------------------- | ||
| 55 | -- Interrupt vector numbers | ||
| 56 | ---------------------------------------------------------------------------- */ | ||
| 57 | |||
| 58 | /*! | ||
| 59 | * @addtogroup Interrupt_vector_numbers Interrupt vector numbers | ||
| 60 | * @{ | ||
| 61 | */ | ||
| 62 | |||
| 63 | /** Interrupt Number Definitions */ | ||
| 64 | #define NUMBER_OF_INT_VECTORS 158 /**< Number of interrupts in the Vector table */ | ||
| 65 | |||
| 66 | typedef enum IRQn { | ||
| 67 | /* Auxiliary constants */ | ||
| 68 | NotAvail_IRQn = -128, /**< Not available device specific interrupt */ | ||
| 69 | |||
| 70 | /* Core interrupts */ | ||
| 71 | NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ | ||
| 72 | HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */ | ||
| 73 | MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */ | ||
| 74 | BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */ | ||
| 75 | UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */ | ||
| 76 | SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */ | ||
| 77 | DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */ | ||
| 78 | PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */ | ||
| 79 | SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */ | ||
| 80 | |||
| 81 | /* Device specific interrupts */ | ||
| 82 | DMA0_DMA16_IRQn = 0, /**< DMA channel 0/16 transfer complete */ | ||
| 83 | DMA1_DMA17_IRQn = 1, /**< DMA channel 1/17 transfer complete */ | ||
| 84 | DMA2_DMA18_IRQn = 2, /**< DMA channel 2/18 transfer complete */ | ||
| 85 | DMA3_DMA19_IRQn = 3, /**< DMA channel 3/19 transfer complete */ | ||
| 86 | DMA4_DMA20_IRQn = 4, /**< DMA channel 4/20 transfer complete */ | ||
| 87 | DMA5_DMA21_IRQn = 5, /**< DMA channel 5/21 transfer complete */ | ||
| 88 | DMA6_DMA22_IRQn = 6, /**< DMA channel 6/22 transfer complete */ | ||
| 89 | DMA7_DMA23_IRQn = 7, /**< DMA channel 7/23 transfer complete */ | ||
| 90 | DMA8_DMA24_IRQn = 8, /**< DMA channel 8/24 transfer complete */ | ||
| 91 | DMA9_DMA25_IRQn = 9, /**< DMA channel 9/25 transfer complete */ | ||
| 92 | DMA10_DMA26_IRQn = 10, /**< DMA channel 10/26 transfer complete */ | ||
| 93 | DMA11_DMA27_IRQn = 11, /**< DMA channel 11/27 transfer complete */ | ||
| 94 | DMA12_DMA28_IRQn = 12, /**< DMA channel 12/28 transfer complete */ | ||
| 95 | DMA13_DMA29_IRQn = 13, /**< DMA channel 13/29 transfer complete */ | ||
| 96 | DMA14_DMA30_IRQn = 14, /**< DMA channel 14/30 transfer complete */ | ||
| 97 | DMA15_DMA31_IRQn = 15, /**< DMA channel 15/31 transfer complete */ | ||
| 98 | DMA_ERROR_IRQn = 16, /**< DMA error interrupt channels 0-15 / 16-31 */ | ||
| 99 | CTI0_ERROR_IRQn = 17, /**< CTI trigger outputs */ | ||
| 100 | CTI1_ERROR_IRQn = 18, /**< CTI trigger outputs */ | ||
| 101 | CORE_IRQn = 19, /**< CorePlatform exception IRQ */ | ||
| 102 | LPUART1_IRQn = 20, /**< LPUART1 TX interrupt and RX interrupt */ | ||
| 103 | LPUART2_IRQn = 21, /**< LPUART2 TX interrupt and RX interrupt */ | ||
| 104 | LPUART3_IRQn = 22, /**< LPUART3 TX interrupt and RX interrupt */ | ||
| 105 | LPUART4_IRQn = 23, /**< LPUART4 TX interrupt and RX interrupt */ | ||
| 106 | LPUART5_IRQn = 24, /**< LPUART5 TX interrupt and RX interrupt */ | ||
| 107 | LPUART6_IRQn = 25, /**< LPUART6 TX interrupt and RX interrupt */ | ||
| 108 | LPUART7_IRQn = 26, /**< LPUART7 TX interrupt and RX interrupt */ | ||
| 109 | LPUART8_IRQn = 27, /**< LPUART8 TX interrupt and RX interrupt */ | ||
| 110 | LPI2C1_IRQn = 28, /**< LPI2C1 interrupt */ | ||
| 111 | LPI2C2_IRQn = 29, /**< LPI2C2 interrupt */ | ||
| 112 | LPI2C3_IRQn = 30, /**< LPI2C3 interrupt */ | ||
| 113 | LPI2C4_IRQn = 31, /**< LPI2C4 interrupt */ | ||
| 114 | LPSPI1_IRQn = 32, /**< LPSPI1 single interrupt vector for all sources */ | ||
| 115 | LPSPI2_IRQn = 33, /**< LPSPI2 single interrupt vector for all sources */ | ||
| 116 | LPSPI3_IRQn = 34, /**< LPSPI3 single interrupt vector for all sources */ | ||
| 117 | LPSPI4_IRQn = 35, /**< LPSPI4 single interrupt vector for all sources */ | ||
| 118 | CAN1_IRQn = 36, /**< CAN1 interrupt */ | ||
| 119 | CAN2_IRQn = 37, /**< CAN2 interrupt */ | ||
| 120 | FLEXRAM_IRQn = 38, /**< FlexRAM address out of range Or access hit IRQ */ | ||
| 121 | KPP_IRQn = 39, /**< Keypad nterrupt */ | ||
| 122 | Reserved56_IRQn = 40, /**< Reserved interrupt */ | ||
| 123 | GPR_IRQ_IRQn = 41, /**< Used to notify cores on exception condition while boot */ | ||
| 124 | Reserved58_IRQn = 42, /**< Reserved interrupt */ | ||
| 125 | Reserved59_IRQn = 43, /**< Reserved interrupt */ | ||
| 126 | Reserved60_IRQn = 44, /**< Reserved interrupt */ | ||
| 127 | WDOG2_IRQn = 45, /**< WDOG2 interrupt */ | ||
| 128 | SNVS_HP_WRAPPER_IRQn = 46, /**< SNVS Functional Interrupt */ | ||
| 129 | SNVS_HP_WRAPPER_TZ_IRQn = 47, /**< SNVS Security Interrupt */ | ||
| 130 | SNVS_LP_HP_WRAPPER_IRQn = 48, /**< ON-OFF button press shorter than 5 secs (pulse event) */ | ||
| 131 | CSU_IRQn = 49, /**< CSU interrupt */ | ||
| 132 | DCP_IRQn = 50, /**< Combined DCP channel interrupts(except channel 0) and CRC interrupt */ | ||
| 133 | DCP_VMI_IRQn = 51, /**< IRQ of DCP channel 0 */ | ||
| 134 | Reserved68_IRQn = 52, /**< Reserved interrupt */ | ||
| 135 | TRNG_IRQn = 53, /**< TRNG interrupt */ | ||
| 136 | Reserved70_IRQn = 54, /**< Reserved interrupt */ | ||
| 137 | BEE_IRQn = 55, /**< BEE interrupt */ | ||
| 138 | SAI1_IRQn = 56, /**< SAI1 interrupt */ | ||
| 139 | SAI2_IRQn = 57, /**< SAI1 interrupt */ | ||
| 140 | SAI3_RX_IRQn = 58, /**< SAI3 interrupt */ | ||
| 141 | SAI3_TX_IRQn = 59, /**< SAI3 interrupt */ | ||
| 142 | SPDIF_IRQn = 60, /**< SPDIF interrupt */ | ||
| 143 | PMU_IRQn = 61, /**< PMU interrupt */ | ||
| 144 | Reserved78_IRQn = 62, /**< Reserved interrupt */ | ||
| 145 | TEMP_LOW_HIGH_IRQn = 63, /**< TEMPMON interrupt */ | ||
| 146 | TEMP_PANIC_IRQn = 64, /**< TEMPMON interrupt */ | ||
| 147 | USB_PHY_IRQn = 65, /**< USBPHY (OTG1 UTMI), Interrupt */ | ||
| 148 | Reserved82_IRQn = 66, /**< Reserved interrupt */ | ||
| 149 | ADC1_IRQn = 67, /**< ADC1 interrupt */ | ||
| 150 | ADC2_IRQn = 68, /**< ADC2 interrupt */ | ||
| 151 | DCDC_IRQn = 69, /**< DCDC interrupt */ | ||
| 152 | Reserved86_IRQn = 70, /**< Reserved interrupt */ | ||
| 153 | Reserved87_IRQn = 71, /**< Reserved interrupt */ | ||
| 154 | GPIO1_INT0_IRQn = 72, /**< Active HIGH Interrupt from INT0 from GPIO */ | ||
| 155 | GPIO1_INT1_IRQn = 73, /**< Active HIGH Interrupt from INT1 from GPIO */ | ||
| 156 | GPIO1_INT2_IRQn = 74, /**< Active HIGH Interrupt from INT2 from GPIO */ | ||
| 157 | GPIO1_INT3_IRQn = 75, /**< Active HIGH Interrupt from INT3 from GPIO */ | ||
| 158 | GPIO1_INT4_IRQn = 76, /**< Active HIGH Interrupt from INT4 from GPIO */ | ||
| 159 | GPIO1_INT5_IRQn = 77, /**< Active HIGH Interrupt from INT5 from GPIO */ | ||
| 160 | GPIO1_INT6_IRQn = 78, /**< Active HIGH Interrupt from INT6 from GPIO */ | ||
| 161 | GPIO1_INT7_IRQn = 79, /**< Active HIGH Interrupt from INT7 from GPIO */ | ||
| 162 | GPIO1_Combined_0_15_IRQn = 80, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */ | ||
| 163 | GPIO1_Combined_16_31_IRQn = 81, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */ | ||
| 164 | GPIO2_Combined_0_15_IRQn = 82, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */ | ||
| 165 | GPIO2_Combined_16_31_IRQn = 83, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */ | ||
| 166 | GPIO3_Combined_0_15_IRQn = 84, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */ | ||
| 167 | GPIO3_Combined_16_31_IRQn = 85, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */ | ||
| 168 | Reserved102_IRQn = 86, /**< Reserved interrupt */ | ||
| 169 | Reserved103_IRQn = 87, /**< Reserved interrupt */ | ||
| 170 | GPIO5_Combined_0_15_IRQn = 88, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */ | ||
| 171 | GPIO5_Combined_16_31_IRQn = 89, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */ | ||
| 172 | FLEXIO1_IRQn = 90, /**< FLEXIO1 interrupt */ | ||
| 173 | Reserved107_IRQn = 91, /**< Reserved interrupt */ | ||
| 174 | WDOG1_IRQn = 92, /**< WDOG1 interrupt */ | ||
| 175 | RTWDOG_IRQn = 93, /**< RTWDOG interrupt */ | ||
| 176 | EWM_IRQn = 94, /**< EWM interrupt */ | ||
| 177 | CCM_1_IRQn = 95, /**< CCM IRQ1 interrupt */ | ||
| 178 | CCM_2_IRQn = 96, /**< CCM IRQ2 interrupt */ | ||
| 179 | GPC_IRQn = 97, /**< GPC interrupt */ | ||
| 180 | SRC_IRQn = 98, /**< SRC interrupt */ | ||
| 181 | Reserved115_IRQn = 99, /**< Reserved interrupt */ | ||
| 182 | GPT1_IRQn = 100, /**< GPT1 interrupt */ | ||
| 183 | GPT2_IRQn = 101, /**< GPT2 interrupt */ | ||
| 184 | PWM1_0_IRQn = 102, /**< PWM1 capture 0, compare 0, or reload 0 interrupt */ | ||
| 185 | PWM1_1_IRQn = 103, /**< PWM1 capture 1, compare 1, or reload 0 interrupt */ | ||
| 186 | PWM1_2_IRQn = 104, /**< PWM1 capture 2, compare 2, or reload 0 interrupt */ | ||
| 187 | PWM1_3_IRQn = 105, /**< PWM1 capture 3, compare 3, or reload 0 interrupt */ | ||
| 188 | PWM1_FAULT_IRQn = 106, /**< PWM1 fault or reload error interrupt */ | ||
| 189 | Reserved123_IRQn = 107, /**< Reserved interrupt */ | ||
| 190 | FLEXSPI_IRQn = 108, /**< FlexSPI0 interrupt */ | ||
| 191 | SEMC_IRQn = 109, /**< Reserved interrupt */ | ||
| 192 | USDHC1_IRQn = 110, /**< USDHC1 interrupt */ | ||
| 193 | USDHC2_IRQn = 111, /**< USDHC2 interrupt */ | ||
| 194 | Reserved128_IRQn = 112, /**< Reserved interrupt */ | ||
| 195 | USB_OTG1_IRQn = 113, /**< USBO2 USB OTG1 */ | ||
| 196 | ENET_IRQn = 114, /**< ENET interrupt */ | ||
| 197 | ENET_1588_Timer_IRQn = 115, /**< ENET_1588_Timer interrupt */ | ||
| 198 | XBAR1_IRQ_0_1_IRQn = 116, /**< XBAR1 interrupt */ | ||
| 199 | XBAR1_IRQ_2_3_IRQn = 117, /**< XBAR1 interrupt */ | ||
| 200 | ADC_ETC_IRQ0_IRQn = 118, /**< ADCETC IRQ0 interrupt */ | ||
| 201 | ADC_ETC_IRQ1_IRQn = 119, /**< ADCETC IRQ1 interrupt */ | ||
| 202 | ADC_ETC_IRQ2_IRQn = 120, /**< ADCETC IRQ2 interrupt */ | ||
| 203 | ADC_ETC_ERROR_IRQ_IRQn = 121, /**< ADCETC Error IRQ interrupt */ | ||
| 204 | PIT_IRQn = 122, /**< PIT interrupt */ | ||
| 205 | ACMP1_IRQn = 123, /**< ACMP interrupt */ | ||
| 206 | ACMP2_IRQn = 124, /**< ACMP interrupt */ | ||
| 207 | ACMP3_IRQn = 125, /**< ACMP interrupt */ | ||
| 208 | ACMP4_IRQn = 126, /**< ACMP interrupt */ | ||
| 209 | Reserved143_IRQn = 127, /**< Reserved interrupt */ | ||
| 210 | Reserved144_IRQn = 128, /**< Reserved interrupt */ | ||
| 211 | ENC1_IRQn = 129, /**< ENC1 interrupt */ | ||
| 212 | ENC2_IRQn = 130, /**< ENC2 interrupt */ | ||
| 213 | Reserved147_IRQn = 131, /**< Reserved interrupt */ | ||
| 214 | Reserved148_IRQn = 132, /**< Reserved interrupt */ | ||
| 215 | TMR1_IRQn = 133, /**< TMR1 interrupt */ | ||
| 216 | TMR2_IRQn = 134, /**< TMR2 interrupt */ | ||
| 217 | Reserved151_IRQn = 135, /**< Reserved interrupt */ | ||
| 218 | Reserved152_IRQn = 136, /**< Reserved interrupt */ | ||
| 219 | PWM2_0_IRQn = 137, /**< PWM2 capture 0, compare 0, or reload 0 interrupt */ | ||
| 220 | PWM2_1_IRQn = 138, /**< PWM2 capture 1, compare 1, or reload 0 interrupt */ | ||
| 221 | PWM2_2_IRQn = 139, /**< PWM2 capture 2, compare 2, or reload 0 interrupt */ | ||
| 222 | PWM2_3_IRQn = 140, /**< PWM2 capture 3, compare 3, or reload 0 interrupt */ | ||
| 223 | PWM2_FAULT_IRQn = 141 /**< PWM2 fault or reload error interrupt */ | ||
| 224 | } IRQn_Type; | ||
| 225 | |||
| 226 | /*! | ||
| 227 | * @} | ||
| 228 | */ /* end of group Interrupt_vector_numbers */ | ||
| 229 | |||
| 230 | |||
| 231 | /* ---------------------------------------------------------------------------- | ||
| 232 | -- Cortex M7 Core Configuration | ||
| 233 | ---------------------------------------------------------------------------- */ | ||
| 234 | |||
| 235 | /*! | ||
| 236 | * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration | ||
| 237 | * @{ | ||
| 238 | */ | ||
| 239 | |||
| 240 | #define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ | ||
| 241 | #define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */ | ||
| 242 | #define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */ | ||
| 243 | #define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */ | ||
| 244 | #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ | ||
| 245 | #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ | ||
| 246 | #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ | ||
| 247 | |||
| 248 | #include "core_cm7.h" /* Core Peripheral Access Layer */ | ||
| 249 | #include "system_MIMXRT1024.h" /* Device specific configuration file */ | ||
| 250 | |||
| 251 | /*! | ||
| 252 | * @} | ||
| 253 | */ /* end of group Cortex_Core_Configuration */ | ||
| 254 | |||
| 255 | |||
| 256 | /* ---------------------------------------------------------------------------- | ||
| 257 | -- Mapping Information | ||
| 258 | ---------------------------------------------------------------------------- */ | ||
| 259 | |||
| 260 | /*! | ||
| 261 | * @addtogroup Mapping_Information Mapping Information | ||
| 262 | * @{ | ||
| 263 | */ | ||
| 264 | |||
| 265 | /** Mapping Information */ | ||
| 266 | /*! | ||
| 267 | * @addtogroup edma_request | ||
| 268 | * @{ | ||
| 269 | */ | ||
| 270 | |||
| 271 | /******************************************************************************* | ||
| 272 | * Definitions | ||
| 273 | ******************************************************************************/ | ||
| 274 | |||
| 275 | /*! | ||
| 276 | * @brief Structure for the DMA hardware request | ||
| 277 | * | ||
| 278 | * Defines the structure for the DMA hardware request collections. The user can configure the | ||
| 279 | * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index | ||
| 280 | * of the hardware request varies according to the to SoC. | ||
| 281 | */ | ||
| 282 | typedef enum _dma_request_source | ||
| 283 | { | ||
| 284 | kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */ | ||
| 285 | kDmaRequestMuxFlexIO1Request4Request5 = 1|0x100U, /**< FlexIO1 Request4 and Request5 */ | ||
| 286 | kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */ | ||
| 287 | kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */ | ||
| 288 | kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */ | ||
| 289 | kDmaRequestMuxLPUART3Rx = 5|0x100U, /**< LPUART3 Receive */ | ||
| 290 | kDmaRequestMuxLPUART5Tx = 6|0x100U, /**< LPUART5 Transmit */ | ||
| 291 | kDmaRequestMuxLPUART5Rx = 7|0x100U, /**< LPUART5 Receive */ | ||
| 292 | kDmaRequestMuxLPUART7Tx = 8|0x100U, /**< LPUART7 Transmit */ | ||
| 293 | kDmaRequestMuxLPUART7Rx = 9|0x100U, /**< LPUART7 Receive */ | ||
| 294 | kDmaRequestMuxLPSPI1Rx = 13|0x100U, /**< LPSPI1 Receive */ | ||
| 295 | kDmaRequestMuxLPSPI1Tx = 14|0x100U, /**< LPSPI1 Transmit */ | ||
| 296 | kDmaRequestMuxLPSPI3Rx = 15|0x100U, /**< LPSPI3 Receive */ | ||
| 297 | kDmaRequestMuxLPSPI3Tx = 16|0x100U, /**< LPSPI3 Transmit */ | ||
| 298 | kDmaRequestMuxLPI2C1 = 17|0x100U, /**< LPI2C1 */ | ||
| 299 | kDmaRequestMuxLPI2C3 = 18|0x100U, /**< LPI2C3 */ | ||
| 300 | kDmaRequestMuxSai1Rx = 19|0x100U, /**< SAI1 Receive */ | ||
| 301 | kDmaRequestMuxSai1Tx = 20|0x100U, /**< SAI1 Transmit */ | ||
| 302 | kDmaRequestMuxSai2Rx = 21|0x100U, /**< SAI2 Receive */ | ||
| 303 | kDmaRequestMuxSai2Tx = 22|0x100U, /**< SAI2 Transmit */ | ||
| 304 | kDmaRequestMuxADC_ETC = 23|0x100U, /**< ADC_ETC */ | ||
| 305 | kDmaRequestMuxADC1 = 24|0x100U, /**< ADC1 */ | ||
| 306 | kDmaRequestMuxACMP1 = 25|0x100U, /**< ACMP1 */ | ||
| 307 | kDmaRequestMuxACMP3 = 26|0x100U, /**< ACMP3 */ | ||
| 308 | kDmaRequestMuxFlexSPIRx = 28|0x100U, /**< FlexSPI Receive */ | ||
| 309 | kDmaRequestMuxFlexSPITx = 29|0x100U, /**< FlexSPI Transmit */ | ||
| 310 | kDmaRequestMuxXBAR1Request0 = 30|0x100U, /**< XBAR1 Request 0 */ | ||
| 311 | kDmaRequestMuxXBAR1Request1 = 31|0x100U, /**< XBAR1 Request 1 */ | ||
| 312 | kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, /**< FlexPWM1 Capture sub-module0 */ | ||
| 313 | kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U, /**< FlexPWM1 Capture sub-module1 */ | ||
| 314 | kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, /**< FlexPWM1 Capture sub-module2 */ | ||
| 315 | kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, /**< FlexPWM1 Capture sub-module3 */ | ||
| 316 | kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U, /**< FlexPWM1 Value sub-module0 */ | ||
| 317 | kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U, /**< FlexPWM1 Value sub-module1 */ | ||
| 318 | kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U, /**< FlexPWM1 Value sub-module2 */ | ||
| 319 | kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U, /**< FlexPWM1 Value sub-module3 */ | ||
| 320 | kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< TMR1 Capture timer 0 */ | ||
| 321 | kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< TMR1 Capture timer 1 */ | ||
| 322 | kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< TMR1 Capture timer 2 */ | ||
| 323 | kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< TMR1 Capture timer 3 */ | ||
| 324 | kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */ | ||
| 325 | kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */ | ||
| 326 | kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */ | ||
| 327 | kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */ | ||
| 328 | kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */ | ||
| 329 | kDmaRequestMuxFlexIO1Request6Request7 = 65|0x100U, /**< FlexIO1 Request6 and Request7 */ | ||
| 330 | kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */ | ||
| 331 | kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */ | ||
| 332 | kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */ | ||
| 333 | kDmaRequestMuxLPUART4Rx = 69|0x100U, /**< LPUART4 Receive */ | ||
| 334 | kDmaRequestMuxLPUART6Tx = 70|0x100U, /**< LPUART6 Transmit */ | ||
| 335 | kDmaRequestMuxLPUART6Rx = 71|0x100U, /**< LPUART6 Receive */ | ||
| 336 | kDmaRequestMuxLPUART8Tx = 72|0x100U, /**< LPUART8 Transmit */ | ||
| 337 | kDmaRequestMuxLPUART8Rx = 73|0x100U, /**< LPUART8 Receive */ | ||
| 338 | kDmaRequestMuxLPSPI2Rx = 77|0x100U, /**< LPSPI2 Receive */ | ||
| 339 | kDmaRequestMuxLPSPI2Tx = 78|0x100U, /**< LPSPI2 Transmit */ | ||
| 340 | kDmaRequestMuxLPSPI4Rx = 79|0x100U, /**< LPSPI4 Receive */ | ||
| 341 | kDmaRequestMuxLPSPI4Tx = 80|0x100U, /**< LPSPI4 Transmit */ | ||
| 342 | kDmaRequestMuxLPI2C2 = 81|0x100U, /**< LPI2C2 */ | ||
| 343 | kDmaRequestMuxLPI2C4 = 82|0x100U, /**< LPI2C4 */ | ||
| 344 | kDmaRequestMuxSai3Rx = 83|0x100U, /**< SAI3 Receive */ | ||
| 345 | kDmaRequestMuxSai3Tx = 84|0x100U, /**< SAI3 Transmit */ | ||
| 346 | kDmaRequestMuxSpdifRx = 85|0x100U, /**< SPDIF Receive */ | ||
| 347 | kDmaRequestMuxSpdifTx = 86|0x100U, /**< SPDIF Transmit */ | ||
| 348 | kDmaRequestMuxADC2 = 88|0x100U, /**< ADC2 */ | ||
| 349 | kDmaRequestMuxACMP2 = 89|0x100U, /**< ACMP2 */ | ||
| 350 | kDmaRequestMuxACMP4 = 90|0x100U, /**< ACMP4 */ | ||
| 351 | kDmaRequestMuxEnetTimer0 = 92|0x100U, /**< ENET Timer0 */ | ||
| 352 | kDmaRequestMuxEnetTimer1 = 93|0x100U, /**< ENET Timer1 */ | ||
| 353 | kDmaRequestMuxXBAR1Request2 = 94|0x100U, /**< XBAR1 Request 2 */ | ||
| 354 | kDmaRequestMuxXBAR1Request3 = 95|0x100U, /**< XBAR1 Request 3 */ | ||
| 355 | kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, /**< FlexPWM2 Capture sub-module0 */ | ||
| 356 | kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U, /**< FlexPWM2 Capture sub-module1 */ | ||
| 357 | kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U, /**< FlexPWM2 Capture sub-module2 */ | ||
| 358 | kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U, /**< FlexPWM2 Capture sub-module3 */ | ||
| 359 | kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U, /**< FlexPWM2 Value sub-module0 */ | ||
| 360 | kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U, /**< FlexPWM2 Value sub-module1 */ | ||
| 361 | kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U, /**< FlexPWM2 Value sub-module2 */ | ||
| 362 | kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U, /**< FlexPWM2 Value sub-module3 */ | ||
| 363 | kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, /**< TMR2 Capture timer 0 */ | ||
| 364 | kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, /**< TMR2 Capture timer 1 */ | ||
| 365 | kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U, /**< TMR2 Capture timer 2 */ | ||
| 366 | kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, /**< TMR2 Capture timer 3 */ | ||
| 367 | kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */ | ||
| 368 | kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */ | ||
| 369 | kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */ | ||
| 370 | kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */ | ||
| 371 | } dma_request_source_t; | ||
| 372 | |||
| 373 | /* @} */ | ||
| 374 | |||
| 375 | /*! | ||
| 376 | * @addtogroup iomuxc_pads | ||
| 377 | * @{ */ | ||
| 378 | |||
| 379 | /******************************************************************************* | ||
| 380 | * Definitions | ||
| 381 | *******************************************************************************/ | ||
| 382 | |||
| 383 | /*! | ||
| 384 | * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD | ||
| 385 | * | ||
| 386 | * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections. | ||
| 387 | */ | ||
| 388 | typedef enum _iomuxc_sw_mux_ctl_pad | ||
| 389 | { | ||
| 390 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 391 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 392 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 393 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 394 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 395 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 396 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 397 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 398 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 399 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 400 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 401 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 402 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 403 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 404 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 405 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 406 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 407 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 408 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 409 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 410 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 411 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 412 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 413 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 414 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 415 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 416 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 417 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 418 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 419 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 420 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 421 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 422 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 423 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 424 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 425 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 426 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 427 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 428 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 429 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 430 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 431 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 432 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 433 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 434 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 435 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 436 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 437 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 438 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 439 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 440 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 441 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 442 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 443 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 444 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 445 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 446 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 447 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 448 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 449 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 450 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 451 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 452 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 453 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 454 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 455 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 456 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 457 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 458 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 459 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 460 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 461 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 462 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 463 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 464 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_06 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 465 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 466 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 467 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 468 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 469 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 470 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 471 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 472 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 473 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 474 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 475 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 476 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 477 | } iomuxc_sw_mux_ctl_pad_t; | ||
| 478 | |||
| 479 | /* @} */ | ||
| 480 | |||
| 481 | /*! | ||
| 482 | * @addtogroup iomuxc_pads | ||
| 483 | * @{ */ | ||
| 484 | |||
| 485 | /******************************************************************************* | ||
| 486 | * Definitions | ||
| 487 | *******************************************************************************/ | ||
| 488 | |||
| 489 | /*! | ||
| 490 | * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD | ||
| 491 | * | ||
| 492 | * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections. | ||
| 493 | */ | ||
| 494 | typedef enum _iomuxc_sw_pad_ctl_pad | ||
| 495 | { | ||
| 496 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 497 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 498 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 499 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 500 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 501 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 502 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 503 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 504 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 505 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 506 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 507 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 508 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 509 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 510 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 511 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 512 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 513 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 514 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 515 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 516 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 517 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 518 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 519 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 520 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 521 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 522 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 523 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 524 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 525 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 526 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 527 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 528 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 529 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 530 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 531 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 532 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 533 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 534 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 535 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 536 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 537 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 538 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 539 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 540 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 541 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 542 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 543 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 544 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 545 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 546 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 547 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 548 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 549 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 550 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 551 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 552 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 553 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 554 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 555 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 556 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 557 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 558 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 559 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 560 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 561 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 562 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 563 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 564 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 565 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 566 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 567 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 568 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 569 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 570 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_06 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 571 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 572 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 573 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 574 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 575 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 576 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 577 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 578 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 579 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 580 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 581 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 582 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 583 | } iomuxc_sw_pad_ctl_pad_t; | ||
| 584 | |||
| 585 | /* @} */ | ||
| 586 | |||
| 587 | /*! | ||
| 588 | * @brief Enumeration for the IOMUXC select input | ||
| 589 | * | ||
| 590 | * Defines the enumeration for the IOMUXC select input collections. | ||
| 591 | */ | ||
| 592 | typedef enum _iomuxc_select_input | ||
| 593 | { | ||
| 594 | kIOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */ | ||
| 595 | kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 1U, /**< IOMUXC select input index */ | ||
| 596 | kIOMUXC_ENET_RMII_SELECT_INPUT = 2U, /**< IOMUXC select input index */ | ||
| 597 | kIOMUXC_ENET_MDIO_SELECT_INPUT = 3U, /**< IOMUXC select input index */ | ||
| 598 | kIOMUXC_ENET_RX_DATA0_SELECT_INPUT = 4U, /**< IOMUXC select input index */ | ||
| 599 | kIOMUXC_ENET_RX_DATA1_SELECT_INPUT = 5U, /**< IOMUXC select input index */ | ||
| 600 | kIOMUXC_ENET_RX_EN_SELECT_INPUT = 6U, /**< IOMUXC select input index */ | ||
| 601 | kIOMUXC_ENET_RX_ERR_SELECT_INPUT = 7U, /**< IOMUXC select input index */ | ||
| 602 | kIOMUXC_ENET_TX_CLK_SELECT_INPUT = 8U, /**< IOMUXC select input index */ | ||
| 603 | kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 9U, /**< IOMUXC select input index */ | ||
| 604 | kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 10U, /**< IOMUXC select input index */ | ||
| 605 | kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 11U, /**< IOMUXC select input index */ | ||
| 606 | kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 12U, /**< IOMUXC select input index */ | ||
| 607 | kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 13U, /**< IOMUXC select input index */ | ||
| 608 | kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 14U, /**< IOMUXC select input index */ | ||
| 609 | kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 15U, /**< IOMUXC select input index */ | ||
| 610 | kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 16U, /**< IOMUXC select input index */ | ||
| 611 | kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 17U, /**< IOMUXC select input index */ | ||
| 612 | kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 18U, /**< IOMUXC select input index */ | ||
| 613 | kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 19U, /**< IOMUXC select input index */ | ||
| 614 | kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 20U, /**< IOMUXC select input index */ | ||
| 615 | kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 21U, /**< IOMUXC select input index */ | ||
| 616 | kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 22U, /**< IOMUXC select input index */ | ||
| 617 | kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 23U, /**< IOMUXC select input index */ | ||
| 618 | kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 24U, /**< IOMUXC select input index */ | ||
| 619 | kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 25U, /**< IOMUXC select input index */ | ||
| 620 | kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 26U, /**< IOMUXC select input index */ | ||
| 621 | kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT = 27U, /**< IOMUXC select input index */ | ||
| 622 | kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT = 28U, /**< IOMUXC select input index */ | ||
| 623 | kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT = 29U, /**< IOMUXC select input index */ | ||
| 624 | kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT = 30U, /**< IOMUXC select input index */ | ||
| 625 | kIOMUXC_FLEXSPI_A_SCLK_SELECT_INPUT = 31U, /**< IOMUXC select input index */ | ||
| 626 | kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 32U, /**< IOMUXC select input index */ | ||
| 627 | kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 33U, /**< IOMUXC select input index */ | ||
| 628 | kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 34U, /**< IOMUXC select input index */ | ||
| 629 | kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 35U, /**< IOMUXC select input index */ | ||
| 630 | kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 36U, /**< IOMUXC select input index */ | ||
| 631 | kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 37U, /**< IOMUXC select input index */ | ||
| 632 | kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 38U, /**< IOMUXC select input index */ | ||
| 633 | kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 39U, /**< IOMUXC select input index */ | ||
| 634 | kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 40U, /**< IOMUXC select input index */ | ||
| 635 | kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 41U, /**< IOMUXC select input index */ | ||
| 636 | kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 42U, /**< IOMUXC select input index */ | ||
| 637 | kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 43U, /**< IOMUXC select input index */ | ||
| 638 | kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 44U, /**< IOMUXC select input index */ | ||
| 639 | kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 45U, /**< IOMUXC select input index */ | ||
| 640 | kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 46U, /**< IOMUXC select input index */ | ||
| 641 | kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 47U, /**< IOMUXC select input index */ | ||
| 642 | kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 48U, /**< IOMUXC select input index */ | ||
| 643 | kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 49U, /**< IOMUXC select input index */ | ||
| 644 | kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 50U, /**< IOMUXC select input index */ | ||
| 645 | kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 51U, /**< IOMUXC select input index */ | ||
| 646 | kIOMUXC_LPUART2_CTS_B_SELECT_INPUT = 52U, /**< IOMUXC select input index */ | ||
| 647 | kIOMUXC_LPUART2_RX_SELECT_INPUT = 53U, /**< IOMUXC select input index */ | ||
| 648 | kIOMUXC_LPUART2_TX_SELECT_INPUT = 54U, /**< IOMUXC select input index */ | ||
| 649 | kIOMUXC_LPUART3_RX_SELECT_INPUT = 55U, /**< IOMUXC select input index */ | ||
| 650 | kIOMUXC_LPUART3_TX_SELECT_INPUT = 56U, /**< IOMUXC select input index */ | ||
| 651 | kIOMUXC_LPUART4_CTS_B_SELECT_INPUT = 57U, /**< IOMUXC select input index */ | ||
| 652 | kIOMUXC_LPUART4_RX_SELECT_INPUT = 58U, /**< IOMUXC select input index */ | ||
| 653 | kIOMUXC_LPUART4_TX_SELECT_INPUT = 59U, /**< IOMUXC select input index */ | ||
| 654 | kIOMUXC_LPUART5_RX_SELECT_INPUT = 60U, /**< IOMUXC select input index */ | ||
| 655 | kIOMUXC_LPUART5_TX_SELECT_INPUT = 61U, /**< IOMUXC select input index */ | ||
| 656 | kIOMUXC_LPUART6_RX_SELECT_INPUT = 62U, /**< IOMUXC select input index */ | ||
| 657 | kIOMUXC_LPUART6_TX_SELECT_INPUT = 63U, /**< IOMUXC select input index */ | ||
| 658 | kIOMUXC_LPUART7_RX_SELECT_INPUT = 64U, /**< IOMUXC select input index */ | ||
| 659 | kIOMUXC_LPUART7_TX_SELECT_INPUT = 65U, /**< IOMUXC select input index */ | ||
| 660 | kIOMUXC_LPUART8_RX_SELECT_INPUT = 66U, /**< IOMUXC select input index */ | ||
| 661 | kIOMUXC_LPUART8_TX_SELECT_INPUT = 67U, /**< IOMUXC select input index */ | ||
| 662 | kIOMUXC_NMI_SELECT_INPUT = 68U, /**< IOMUXC select input index */ | ||
| 663 | kIOMUXC_QTIMER1_TIMER0_INPUT_SELECT_INPUT = 69U, /**< IOMUXC select input index */ | ||
| 664 | kIOMUXC_QTIMER1_TIMER1_INPUT_SELECT_INPUT = 70U, /**< IOMUXC select input index */ | ||
| 665 | kIOMUXC_QTIMER1_TIMER2_INPUT_SELECT_INPUT = 71U, /**< IOMUXC select input index */ | ||
| 666 | kIOMUXC_QTIMER1_TIMER3_INPUT_SELECT_INPUT = 72U, /**< IOMUXC select input index */ | ||
| 667 | kIOMUXC_QTIMER2_TIMER0_INPUT_SELECT_INPUT = 73U, /**< IOMUXC select input index */ | ||
| 668 | kIOMUXC_QTIMER2_TIMER1_INPUT_SELECT_INPUT = 74U, /**< IOMUXC select input index */ | ||
| 669 | kIOMUXC_QTIMER2_TIMER2_INPUT_SELECT_INPUT = 75U, /**< IOMUXC select input index */ | ||
| 670 | kIOMUXC_QTIMER2_TIMER3_INPUT_SELECT_INPUT = 76U, /**< IOMUXC select input index */ | ||
| 671 | kIOMUXC_SAI1_MCLK_SELECT_INPUT = 77U, /**< IOMUXC select input index */ | ||
| 672 | kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 78U, /**< IOMUXC select input index */ | ||
| 673 | kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 79U, /**< IOMUXC select input index */ | ||
| 674 | kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 80U, /**< IOMUXC select input index */ | ||
| 675 | kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 81U, /**< IOMUXC select input index */ | ||
| 676 | kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 82U, /**< IOMUXC select input index */ | ||
| 677 | kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 83U, /**< IOMUXC select input index */ | ||
| 678 | kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 84U, /**< IOMUXC select input index */ | ||
| 679 | kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 85U, /**< IOMUXC select input index */ | ||
| 680 | kIOMUXC_SAI2_MCLK_SELECT_INPUT = 86U, /**< IOMUXC select input index */ | ||
| 681 | kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 87U, /**< IOMUXC select input index */ | ||
| 682 | kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 88U, /**< IOMUXC select input index */ | ||
| 683 | kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 89U, /**< IOMUXC select input index */ | ||
| 684 | kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 90U, /**< IOMUXC select input index */ | ||
| 685 | kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 91U, /**< IOMUXC select input index */ | ||
| 686 | kIOMUXC_SAI3_MCLK_SELECT_INPUT = 92U, /**< IOMUXC select input index */ | ||
| 687 | kIOMUXC_SAI3_RX_BCLK_SELECT_INPUT = 93U, /**< IOMUXC select input index */ | ||
| 688 | kIOMUXC_SAI3_RX_DATA0_SELECT_INPUT = 94U, /**< IOMUXC select input index */ | ||
| 689 | kIOMUXC_SAI3_RX_SYNC_SELECT_INPUT = 95U, /**< IOMUXC select input index */ | ||
| 690 | kIOMUXC_SAI3_TX_BCLK_SELECT_INPUT = 96U, /**< IOMUXC select input index */ | ||
| 691 | kIOMUXC_SAI3_TX_SYNC_SELECT_INPUT = 97U, /**< IOMUXC select input index */ | ||
| 692 | kIOMUXC_SEMC_READY_SELECT_INPUT = 98U, /**< IOMUXC select input index */ | ||
| 693 | kIOMUXC_SPDIF_IN_SELECT_INPUT = 99U, /**< IOMUXC select input index */ | ||
| 694 | kIOMUXC_USB_OTG_OC_SELECT_INPUT = 100U, /**< IOMUXC select input index */ | ||
| 695 | kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 101U, /**< IOMUXC select input index */ | ||
| 696 | kIOMUXC_USDHC1_WP_SELECT_INPUT = 102U, /**< IOMUXC select input index */ | ||
| 697 | kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 103U, /**< IOMUXC select input index */ | ||
| 698 | kIOMUXC_USDHC2_WP_SELECT_INPUT = 104U, /**< IOMUXC select input index */ | ||
| 699 | kIOMUXC_XBAR1_IN14_SELECT_INPUT = 105U, /**< IOMUXC select input index */ | ||
| 700 | kIOMUXC_XBAR1_IN15_SELECT_INPUT = 106U, /**< IOMUXC select input index */ | ||
| 701 | kIOMUXC_XBAR1_IN16_SELECT_INPUT = 107U, /**< IOMUXC select input index */ | ||
| 702 | kIOMUXC_XBAR1_IN17_SELECT_INPUT = 108U, /**< IOMUXC select input index */ | ||
| 703 | kIOMUXC_XBAR1_IN10_SELECT_INPUT = 109U, /**< IOMUXC select input index */ | ||
| 704 | kIOMUXC_XBAR1_IN12_SELECT_INPUT = 110U, /**< IOMUXC select input index */ | ||
| 705 | kIOMUXC_XBAR1_IN13_SELECT_INPUT = 111U, /**< IOMUXC select input index */ | ||
| 706 | kIOMUXC_XBAR1_IN18_SELECT_INPUT = 112U, /**< IOMUXC select input index */ | ||
| 707 | kIOMUXC_XBAR1_IN19_SELECT_INPUT = 113U, /**< IOMUXC select input index */ | ||
| 708 | } iomuxc_select_input_t; | ||
| 709 | |||
| 710 | typedef enum _xbar_input_signal | ||
| 711 | { | ||
| 712 | kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA_IN0 input. */ | ||
| 713 | kXBARA1_InputLogicHigh = 1|0x100U, /**< LOGIC_HIGH output assigned to XBARA_IN1 input. */ | ||
| 714 | kXBARA1_InputRESERVED2 = 2|0x100U, /**< XBARA_IN2 input is reserved. */ | ||
| 715 | kXBARA1_InputRESERVED3 = 3|0x100U, /**< XBARA_IN3 input is reserved. */ | ||
| 716 | kXBARA1_InputIomuxXbarInout04 = 4|0x100U, /**< IOMUX_XBAR_INOUT04 output assigned to XBARA_IN4 input. */ | ||
| 717 | kXBARA1_InputIomuxXbarInout05 = 5|0x100U, /**< IOMUX_XBAR_INOUT05 output assigned to XBARA_IN5 input. */ | ||
| 718 | kXBARA1_InputIomuxXbarInout06 = 6|0x100U, /**< IOMUX_XBAR_INOUT06 output assigned to XBARA_IN6 input. */ | ||
| 719 | kXBARA1_InputIomuxXbarInout07 = 7|0x100U, /**< IOMUX_XBAR_INOUT07 output assigned to XBARA_IN7 input. */ | ||
| 720 | kXBARA1_InputIomuxXbarInout08 = 8|0x100U, /**< IOMUX_XBAR_INOUT08 output assigned to XBARA_IN8 input. */ | ||
| 721 | kXBARA1_InputIomuxXbarInout09 = 9|0x100U, /**< IOMUX_XBAR_INOUT09 output assigned to XBARA_IN9 input. */ | ||
| 722 | kXBARA1_InputIomuxXbarInout10 = 10|0x100U, /**< IOMUX_XBAR_INOUT10 output assigned to XBARA_IN10 input. */ | ||
| 723 | kXBARA1_InputIomuxXbarInout11 = 11|0x100U, /**< IOMUX_XBAR_INOUT11 output assigned to XBARA_IN11 input. */ | ||
| 724 | kXBARA1_InputIomuxXbarInout12 = 12|0x100U, /**< IOMUX_XBAR_INOUT12 output assigned to XBARA_IN12 input. */ | ||
| 725 | kXBARA1_InputIomuxXbarInout13 = 13|0x100U, /**< IOMUX_XBAR_INOUT13 output assigned to XBARA_IN13 input. */ | ||
| 726 | kXBARA1_InputIomuxXbarInout14 = 14|0x100U, /**< IOMUX_XBAR_INOUT14 output assigned to XBARA_IN14 input. */ | ||
| 727 | kXBARA1_InputIomuxXbarInout15 = 15|0x100U, /**< IOMUX_XBAR_INOUT15 output assigned to XBARA_IN15 input. */ | ||
| 728 | kXBARA1_InputIomuxXbarInout16 = 16|0x100U, /**< IOMUX_XBAR_INOUT16 output assigned to XBARA_IN16 input. */ | ||
| 729 | kXBARA1_InputIomuxXbarInout17 = 17|0x100U, /**< IOMUX_XBAR_INOUT17 output assigned to XBARA_IN17 input. */ | ||
| 730 | kXBARA1_InputIomuxXbarInout18 = 18|0x100U, /**< IOMUX_XBAR_INOUT18 output assigned to XBARA_IN18 input. */ | ||
| 731 | kXBARA1_InputIomuxXbarInout19 = 19|0x100U, /**< IOMUX_XBAR_INOUT19 output assigned to XBARA_IN19 input. */ | ||
| 732 | kXBARA1_InputRESERVED20 = 20|0x100U, /**< XBARA_IN20 input is reserved. */ | ||
| 733 | kXBARA1_InputRESERVED21 = 21|0x100U, /**< XBARA_IN21 input is reserved. */ | ||
| 734 | kXBARA1_InputRESERVED22 = 22|0x100U, /**< XBARA_IN22 input is reserved. */ | ||
| 735 | kXBARA1_InputRESERVED23 = 23|0x100U, /**< XBARA_IN23 input is reserved. */ | ||
| 736 | kXBARA1_InputRESERVED24 = 24|0x100U, /**< XBARA_IN24 input is reserved. */ | ||
| 737 | kXBARA1_InputRESERVED25 = 25|0x100U, /**< XBARA_IN25 input is reserved. */ | ||
| 738 | kXBARA1_InputAcmp1Out = 26|0x100U, /**< ACMP1_OUT output assigned to XBARA_IN26 input. */ | ||
| 739 | kXBARA1_InputAcmp2Out = 27|0x100U, /**< ACMP2_OUT output assigned to XBARA_IN27 input. */ | ||
| 740 | kXBARA1_InputAcmp3Out = 28|0x100U, /**< ACMP3_OUT output assigned to XBARA_IN28 input. */ | ||
| 741 | kXBARA1_InputAcmp4Out = 29|0x100U, /**< ACMP4_OUT output assigned to XBARA_IN29 input. */ | ||
| 742 | kXBARA1_InputRESERVED30 = 30|0x100U, /**< XBARA_IN30 input is reserved. */ | ||
| 743 | kXBARA1_InputRESERVED31 = 31|0x100U, /**< XBARA_IN31 input is reserved. */ | ||
| 744 | kXBARA1_InputQtimer1Tmr0 = 32|0x100U, /**< QTIMER1_TMR0 output assigned to XBARA_IN32 input. */ | ||
| 745 | kXBARA1_InputQtimer1Tmr1 = 33|0x100U, /**< QTIMER1_TMR1 output assigned to XBARA_IN33 input. */ | ||
| 746 | kXBARA1_InputQtimer1Tmr2 = 34|0x100U, /**< QTIMER1_TMR2 output assigned to XBARA_IN34 input. */ | ||
| 747 | kXBARA1_InputQtimer1Tmr3 = 35|0x100U, /**< QTIMER1_TMR3 output assigned to XBARA_IN35 input. */ | ||
| 748 | kXBARA1_InputQtimer2Tmr0 = 36|0x100U, /**< QTIMER2_TMR0 output assigned to XBARA_IN36 input. */ | ||
| 749 | kXBARA1_InputQtimer2Tmr1 = 37|0x100U, /**< QTIMER2_TMR1 output assigned to XBARA_IN37 input. */ | ||
| 750 | kXBARA1_InputQtimer2Tmr2 = 38|0x100U, /**< QTIMER2_TMR2 output assigned to XBARA_IN38 input. */ | ||
| 751 | kXBARA1_InputQtimer2Tmr3 = 39|0x100U, /**< QTIMER2_TMR3 output assigned to XBARA_IN39 input. */ | ||
| 752 | kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA_IN40 input. */ | ||
| 753 | kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA_IN41 input. */ | ||
| 754 | kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA_IN42 input. */ | ||
| 755 | kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA_IN43 input. */ | ||
| 756 | kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA_IN44 input. */ | ||
| 757 | kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA_IN45 input. */ | ||
| 758 | kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA_IN46 input. */ | ||
| 759 | kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA_IN47 input. */ | ||
| 760 | kXBARA1_InputRESERVED48 = 48|0x100U, /**< XBARA_IN48 input is reserved. */ | ||
| 761 | kXBARA1_InputRESERVED49 = 49|0x100U, /**< XBARA_IN49 input is reserved. */ | ||
| 762 | kXBARA1_InputRESERVED50 = 50|0x100U, /**< XBARA_IN50 input is reserved. */ | ||
| 763 | kXBARA1_InputRESERVED51 = 51|0x100U, /**< XBARA_IN51 input is reserved. */ | ||
| 764 | kXBARA1_InputRESERVED52 = 52|0x100U, /**< XBARA_IN52 input is reserved. */ | ||
| 765 | kXBARA1_InputRESERVED53 = 53|0x100U, /**< XBARA_IN53 input is reserved. */ | ||
| 766 | kXBARA1_InputRESERVED54 = 54|0x100U, /**< XBARA_IN54 input is reserved. */ | ||
| 767 | kXBARA1_InputRESERVED55 = 55|0x100U, /**< XBARA_IN55 input is reserved. */ | ||
| 768 | kXBARA1_InputPitTrigger0 = 56|0x100U, /**< PIT_TRIGGER0 output assigned to XBARA_IN56 input. */ | ||
| 769 | kXBARA1_InputPitTrigger1 = 57|0x100U, /**< PIT_TRIGGER1 output assigned to XBARA_IN57 input. */ | ||
| 770 | kXBARA1_InputPitTrigger2 = 58|0x100U, /**< PIT_TRIGGER2 output assigned to XBARA_IN58 input. */ | ||
| 771 | kXBARA1_InputPitTrigger3 = 59|0x100U, /**< PIT_TRIGGER3 output assigned to XBARA_IN59 input. */ | ||
| 772 | kXBARA1_InputEnc1PosMatch = 60|0x100U, /**< ENC1_POS_MATCH output assigned to XBARA_IN60 input. */ | ||
| 773 | kXBARA1_InputEnc2PosMatch = 61|0x100U, /**< ENC2_POS_MATCH output assigned to XBARA_IN61 input. */ | ||
| 774 | kXBARA1_InputRESERVED62 = 62|0x100U, /**< XBARA_IN62 input is reserved. */ | ||
| 775 | kXBARA1_InputRESERVED63 = 63|0x100U, /**< XBARA_IN63 input is reserved. */ | ||
| 776 | kXBARA1_InputDmaDone0 = 64|0x100U, /**< DMA_DONE0 output assigned to XBARA_IN64 input. */ | ||
| 777 | kXBARA1_InputDmaDone1 = 65|0x100U, /**< DMA_DONE1 output assigned to XBARA_IN65 input. */ | ||
| 778 | kXBARA1_InputDmaDone2 = 66|0x100U, /**< DMA_DONE2 output assigned to XBARA_IN66 input. */ | ||
| 779 | kXBARA1_InputDmaDone3 = 67|0x100U, /**< DMA_DONE3 output assigned to XBARA_IN67 input. */ | ||
| 780 | kXBARA1_InputDmaDone4 = 68|0x100U, /**< DMA_DONE4 output assigned to XBARA_IN68 input. */ | ||
| 781 | kXBARA1_InputDmaDone5 = 69|0x100U, /**< DMA_DONE5 output assigned to XBARA_IN69 input. */ | ||
| 782 | kXBARA1_InputDmaDone6 = 70|0x100U, /**< DMA_DONE6 output assigned to XBARA_IN70 input. */ | ||
| 783 | kXBARA1_InputDmaDone7 = 71|0x100U, /**< DMA_DONE7 output assigned to XBARA_IN71 input. */ | ||
| 784 | kXBARA1_InputAoi1Out0 = 72|0x100U, /**< AOI1_OUT0 output assigned to XBARA_IN72 input. */ | ||
| 785 | kXBARA1_InputAoi1Out1 = 73|0x100U, /**< AOI1_OUT1 output assigned to XBARA_IN73 input. */ | ||
| 786 | kXBARA1_InputAoi1Out2 = 74|0x100U, /**< AOI1_OUT2 output assigned to XBARA_IN74 input. */ | ||
| 787 | kXBARA1_InputAoi1Out3 = 75|0x100U, /**< AOI1_OUT3 output assigned to XBARA_IN75 input. */ | ||
| 788 | kXBARA1_InputRESERVED76 = 76|0x100U, /**< XBARA_IN76 input is reserved. */ | ||
| 789 | kXBARA1_InputRESERVED77 = 77|0x100U, /**< XBARA_IN77 input is reserved. */ | ||
| 790 | kXBARA1_InputRESERVED78 = 78|0x100U, /**< XBARA_IN78 input is reserved. */ | ||
| 791 | kXBARA1_InputRESERVED79 = 79|0x100U, /**< XBARA_IN79 input is reserved. */ | ||
| 792 | kXBARA1_InputAdcEtc0Coco0 = 80|0x100U, /**< ADC_ETC0_COCO0 output assigned to XBARA_IN80 input. */ | ||
| 793 | kXBARA1_InputAdcEtc0Coco1 = 81|0x100U, /**< ADC_ETC0_COCO1 output assigned to XBARA_IN81 input. */ | ||
| 794 | kXBARA1_InputAdcEtc0Coco2 = 82|0x100U, /**< ADC_ETC0_COCO2 output assigned to XBARA_IN82 input. */ | ||
| 795 | kXBARA1_InputAdcEtc0Coco3 = 83|0x100U, /**< ADC_ETC0_COCO3 output assigned to XBARA_IN83 input. */ | ||
| 796 | kXBARA1_InputAdcEtc1Coco0 = 84|0x100U, /**< ADC_ETC1_COCO0 output assigned to XBARA_IN84 input. */ | ||
| 797 | kXBARA1_InputAdcEtc1Coco1 = 85|0x100U, /**< ADC_ETC1_COCO1 output assigned to XBARA_IN85 input. */ | ||
| 798 | kXBARA1_InputAdcEtc1Coco2 = 86|0x100U, /**< ADC_ETC1_COCO2 output assigned to XBARA_IN86 input. */ | ||
| 799 | kXBARA1_InputAdcEtc1Coco3 = 87|0x100U, /**< ADC_ETC1_COCO3 output assigned to XBARA_IN87 input. */ | ||
| 800 | kXBARB2_InputLogicLow = 0|0x200U, /**< LOGIC_LOW output assigned to XBARB_IN0 input. */ | ||
| 801 | kXBARB2_InputLogicHigh = 1|0x200U, /**< LOGIC_HIGH output assigned to XBARB_IN1 input. */ | ||
| 802 | kXBARB2_InputRESERVED2 = 2|0x200U, /**< XBARB_IN2 input is reserved. */ | ||
| 803 | kXBARB2_InputRESERVED3 = 3|0x200U, /**< XBARB_IN3 input is reserved. */ | ||
| 804 | kXBARB2_InputRESERVED4 = 4|0x200U, /**< XBARB_IN4 input is reserved. */ | ||
| 805 | kXBARB2_InputRESERVED5 = 5|0x200U, /**< XBARB_IN5 input is reserved. */ | ||
| 806 | kXBARB2_InputAcmp1Out = 6|0x200U, /**< ACMP1_OUT output assigned to XBARB_IN6 input. */ | ||
| 807 | kXBARB2_InputAcmp2Out = 7|0x200U, /**< ACMP2_OUT output assigned to XBARB_IN7 input. */ | ||
| 808 | kXBARB2_InputAcmp3Out = 8|0x200U, /**< ACMP3_OUT output assigned to XBARB_IN8 input. */ | ||
| 809 | kXBARB2_InputAcmp4Out = 9|0x200U, /**< ACMP4_OUT output assigned to XBARB_IN9 input. */ | ||
| 810 | kXBARB2_InputRESERVED10 = 10|0x200U, /**< XBARB_IN10 input is reserved. */ | ||
| 811 | kXBARB2_InputRESERVED11 = 11|0x200U, /**< XBARB_IN11 input is reserved. */ | ||
| 812 | kXBARB2_InputQtimer1Tmr0 = 12|0x200U, /**< QTIMER1_TMR0 output assigned to XBARB_IN12 input. */ | ||
| 813 | kXBARB2_InputQtimer1Tmr1 = 13|0x200U, /**< QTIMER1_TMR1 output assigned to XBARB_IN13 input. */ | ||
| 814 | kXBARB2_InputQtimer1Tmr2 = 14|0x200U, /**< QTIMER1_TMR2 output assigned to XBARB_IN14 input. */ | ||
| 815 | kXBARB2_InputQtimer1Tmr3 = 15|0x200U, /**< QTIMER1_TMR3 output assigned to XBARB_IN15 input. */ | ||
| 816 | kXBARB2_InputQtimer2Tmr0 = 16|0x200U, /**< QTIMER2_TMR0 output assigned to XBARB_IN16 input. */ | ||
| 817 | kXBARB2_InputQtimer2Tmr1 = 17|0x200U, /**< QTIMER2_TMR1 output assigned to XBARB_IN17 input. */ | ||
| 818 | kXBARB2_InputQtimer2Tmr2 = 18|0x200U, /**< QTIMER2_TMR2 output assigned to XBARB_IN18 input. */ | ||
| 819 | kXBARB2_InputQtimer2Tmr3 = 19|0x200U, /**< QTIMER2_TMR3 output assigned to XBARB_IN19 input. */ | ||
| 820 | kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB_IN20 input. */ | ||
| 821 | kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB_IN21 input. */ | ||
| 822 | kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB_IN22 input. */ | ||
| 823 | kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB_IN23 input. */ | ||
| 824 | kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB_IN24 input. */ | ||
| 825 | kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB_IN25 input. */ | ||
| 826 | kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB_IN26 input. */ | ||
| 827 | kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB_IN27 input. */ | ||
| 828 | kXBARB2_InputRESERVED28 = 28|0x200U, /**< XBARB_IN28 input is reserved. */ | ||
| 829 | kXBARB2_InputRESERVED29 = 29|0x200U, /**< XBARB_IN29 input is reserved. */ | ||
| 830 | kXBARB2_InputRESERVED30 = 30|0x200U, /**< XBARB_IN30 input is reserved. */ | ||
| 831 | kXBARB2_InputRESERVED31 = 31|0x200U, /**< XBARB_IN31 input is reserved. */ | ||
| 832 | kXBARB2_InputRESERVED32 = 32|0x200U, /**< XBARB_IN32 input is reserved. */ | ||
| 833 | kXBARB2_InputRESERVED33 = 33|0x200U, /**< XBARB_IN33 input is reserved. */ | ||
| 834 | kXBARB2_InputRESERVED34 = 34|0x200U, /**< XBARB_IN34 input is reserved. */ | ||
| 835 | kXBARB2_InputRESERVED35 = 35|0x200U, /**< XBARB_IN35 input is reserved. */ | ||
| 836 | kXBARB2_InputPitTrigger0 = 36|0x200U, /**< PIT_TRIGGER0 output assigned to XBARB_IN36 input. */ | ||
| 837 | kXBARB2_InputPitTrigger1 = 37|0x200U, /**< PIT_TRIGGER1 output assigned to XBARB_IN37 input. */ | ||
| 838 | kXBARB2_InputAdcEtc0Coco0 = 38|0x200U, /**< ADC_ETC0_COCO0 output assigned to XBARB_IN38 input. */ | ||
| 839 | kXBARB2_InputAdcEtc0Coco1 = 39|0x200U, /**< ADC_ETC0_COCO1 output assigned to XBARB_IN39 input. */ | ||
| 840 | kXBARB2_InputAdcEtc0Coco2 = 40|0x200U, /**< ADC_ETC0_COCO2 output assigned to XBARB_IN40 input. */ | ||
| 841 | kXBARB2_InputAdcEtc0Coco3 = 41|0x200U, /**< ADC_ETC0_COCO3 output assigned to XBARB_IN41 input. */ | ||
| 842 | kXBARB2_InputAdcEtc1Coco0 = 42|0x200U, /**< ADC_ETC1_COCO0 output assigned to XBARB_IN42 input. */ | ||
| 843 | kXBARB2_InputAdcEtc1Coco1 = 43|0x200U, /**< ADC_ETC1_COCO1 output assigned to XBARB_IN43 input. */ | ||
| 844 | kXBARB2_InputAdcEtc1Coco2 = 44|0x200U, /**< ADC_ETC1_COCO2 output assigned to XBARB_IN44 input. */ | ||
| 845 | kXBARB2_InputAdcEtc1Coco3 = 45|0x200U, /**< ADC_ETC1_COCO3 output assigned to XBARB_IN45 input. */ | ||
| 846 | kXBARB2_InputEnc1PosMatch = 46|0x200U, /**< ENC1_POS_MATCH output assigned to XBARB_IN46 input. */ | ||
| 847 | kXBARB2_InputEnc2PosMatch = 47|0x200U, /**< ENC2_POS_MATCH output assigned to XBARB_IN47 input. */ | ||
| 848 | kXBARB2_InputRESERVED48 = 48|0x200U, /**< XBARB_IN48 input is reserved. */ | ||
| 849 | kXBARB2_InputRESERVED49 = 49|0x200U, /**< XBARB_IN49 input is reserved. */ | ||
| 850 | kXBARB2_InputDmaDone0 = 50|0x200U, /**< DMA_DONE0 output assigned to XBARB_IN50 input. */ | ||
| 851 | kXBARB2_InputDmaDone1 = 51|0x200U, /**< DMA_DONE1 output assigned to XBARB_IN51 input. */ | ||
| 852 | kXBARB2_InputDmaDone2 = 52|0x200U, /**< DMA_DONE2 output assigned to XBARB_IN52 input. */ | ||
| 853 | kXBARB2_InputDmaDone3 = 53|0x200U, /**< DMA_DONE3 output assigned to XBARB_IN53 input. */ | ||
| 854 | kXBARB2_InputDmaDone4 = 54|0x200U, /**< DMA_DONE4 output assigned to XBARB_IN54 input. */ | ||
| 855 | kXBARB2_InputDmaDone5 = 55|0x200U, /**< DMA_DONE5 output assigned to XBARB_IN55 input. */ | ||
| 856 | kXBARB2_InputDmaDone6 = 56|0x200U, /**< DMA_DONE6 output assigned to XBARB_IN56 input. */ | ||
| 857 | kXBARB2_InputDmaDone7 = 57|0x200U, /**< DMA_DONE7 output assigned to XBARB_IN57 input. */ | ||
| 858 | } xbar_input_signal_t; | ||
| 859 | |||
| 860 | typedef enum _xbar_output_signal | ||
| 861 | { | ||
| 862 | kXBARA1_OutputDmaChMuxReq30 = 0|0x100U, /**< XBARA_OUT0 output assigned to DMA_CH_MUX_REQ30 */ | ||
| 863 | kXBARA1_OutputDmaChMuxReq31 = 1|0x100U, /**< XBARA_OUT1 output assigned to DMA_CH_MUX_REQ31 */ | ||
| 864 | kXBARA1_OutputDmaChMuxReq94 = 2|0x100U, /**< XBARA_OUT2 output assigned to DMA_CH_MUX_REQ94 */ | ||
| 865 | kXBARA1_OutputDmaChMuxReq95 = 3|0x100U, /**< XBARA_OUT3 output assigned to DMA_CH_MUX_REQ95 */ | ||
| 866 | kXBARA1_OutputIomuxXbarInout04 = 4|0x100U, /**< XBARA_OUT4 output assigned to IOMUX_XBAR_INOUT04 */ | ||
| 867 | kXBARA1_OutputIomuxXbarInout05 = 5|0x100U, /**< XBARA_OUT5 output assigned to IOMUX_XBAR_INOUT05 */ | ||
| 868 | kXBARA1_OutputIomuxXbarInout06 = 6|0x100U, /**< XBARA_OUT6 output assigned to IOMUX_XBAR_INOUT06 */ | ||
| 869 | kXBARA1_OutputIomuxXbarInout07 = 7|0x100U, /**< XBARA_OUT7 output assigned to IOMUX_XBAR_INOUT07 */ | ||
| 870 | kXBARA1_OutputIomuxXbarInout08 = 8|0x100U, /**< XBARA_OUT8 output assigned to IOMUX_XBAR_INOUT08 */ | ||
| 871 | kXBARA1_OutputIomuxXbarInout09 = 9|0x100U, /**< XBARA_OUT9 output assigned to IOMUX_XBAR_INOUT09 */ | ||
| 872 | kXBARA1_OutputIomuxXbarInout10 = 10|0x100U, /**< XBARA_OUT10 output assigned to IOMUX_XBAR_INOUT10 */ | ||
| 873 | kXBARA1_OutputIomuxXbarInout11 = 11|0x100U, /**< XBARA_OUT11 output assigned to IOMUX_XBAR_INOUT11 */ | ||
| 874 | kXBARA1_OutputIomuxXbarInout12 = 12|0x100U, /**< XBARA_OUT12 output assigned to IOMUX_XBAR_INOUT12 */ | ||
| 875 | kXBARA1_OutputIomuxXbarInout13 = 13|0x100U, /**< XBARA_OUT13 output assigned to IOMUX_XBAR_INOUT13 */ | ||
| 876 | kXBARA1_OutputIomuxXbarInout14 = 14|0x100U, /**< XBARA_OUT14 output assigned to IOMUX_XBAR_INOUT14 */ | ||
| 877 | kXBARA1_OutputIomuxXbarInout15 = 15|0x100U, /**< XBARA_OUT15 output assigned to IOMUX_XBAR_INOUT15 */ | ||
| 878 | kXBARA1_OutputIomuxXbarInout16 = 16|0x100U, /**< XBARA_OUT16 output assigned to IOMUX_XBAR_INOUT16 */ | ||
| 879 | kXBARA1_OutputIomuxXbarInout17 = 17|0x100U, /**< XBARA_OUT17 output assigned to IOMUX_XBAR_INOUT17 */ | ||
| 880 | kXBARA1_OutputIomuxXbarInout18 = 18|0x100U, /**< XBARA_OUT18 output assigned to IOMUX_XBAR_INOUT18 */ | ||
| 881 | kXBARA1_OutputIomuxXbarInout19 = 19|0x100U, /**< XBARA_OUT19 output assigned to IOMUX_XBAR_INOUT19 */ | ||
| 882 | kXBARA1_OutputAcmp1Sample = 20|0x100U, /**< XBARA_OUT20 output assigned to ACMP1_SAMPLE */ | ||
| 883 | kXBARA1_OutputAcmp2Sample = 21|0x100U, /**< XBARA_OUT21 output assigned to ACMP2_SAMPLE */ | ||
| 884 | kXBARA1_OutputAcmp3Sample = 22|0x100U, /**< XBARA_OUT22 output assigned to ACMP3_SAMPLE */ | ||
| 885 | kXBARA1_OutputAcmp4Sample = 23|0x100U, /**< XBARA_OUT23 output assigned to ACMP4_SAMPLE */ | ||
| 886 | kXBARA1_OutputRESERVED24 = 24|0x100U, /**< XBARA_OUT24 output is reserved. */ | ||
| 887 | kXBARA1_OutputRESERVED25 = 25|0x100U, /**< XBARA_OUT25 output is reserved. */ | ||
| 888 | kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U, /**< XBARA_OUT26 output assigned to FLEXPWM1_EXTA0 */ | ||
| 889 | kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U, /**< XBARA_OUT27 output assigned to FLEXPWM1_EXTA1 */ | ||
| 890 | kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U, /**< XBARA_OUT28 output assigned to FLEXPWM1_EXTA2 */ | ||
| 891 | kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U, /**< XBARA_OUT29 output assigned to FLEXPWM1_EXTA3 */ | ||
| 892 | kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U, /**< XBARA_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */ | ||
| 893 | kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U, /**< XBARA_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */ | ||
| 894 | kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U, /**< XBARA_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */ | ||
| 895 | kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U, /**< XBARA_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */ | ||
| 896 | kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U, /**< XBARA_OUT34 output assigned to FLEXPWM1_EXT_CLK */ | ||
| 897 | kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U, /**< XBARA_OUT35 output assigned to FLEXPWM1_FAULT0 */ | ||
| 898 | kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U, /**< XBARA_OUT36 output assigned to FLEXPWM1_FAULT1 */ | ||
| 899 | kXBARA1_OutputFlexpwm12Fault2 = 37|0x100U, /**< XBARA_OUT37 output assigned to FLEXPWM1_2_FAULT2 */ | ||
| 900 | kXBARA1_OutputFlexpwm12Fault3 = 38|0x100U, /**< XBARA_OUT38 output assigned to FLEXPWM1_2_FAULT3 */ | ||
| 901 | kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U, /**< XBARA_OUT39 output assigned to FLEXPWM1_EXT_FORCE */ | ||
| 902 | kXBARA1_OutputFlexpwm2Exta0 = 40|0x100U, /**< XBARA_OUT40 output assigned to FLEXPWM2_EXTA0 */ | ||
| 903 | kXBARA1_OutputFlexpwm2Exta1 = 41|0x100U, /**< XBARA_OUT41 output assigned to FLEXPWM2_EXTA1 */ | ||
| 904 | kXBARA1_OutputFlexpwm2Exta2 = 42|0x100U, /**< XBARA_OUT42 output assigned to FLEXPWM2_EXTA2 */ | ||
| 905 | kXBARA1_OutputFlexpwm2Exta3 = 43|0x100U, /**< XBARA_OUT43 output assigned to FLEXPWM2_EXTA3 */ | ||
| 906 | kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U, /**< XBARA_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */ | ||
| 907 | kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U, /**< XBARA_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */ | ||
| 908 | kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U, /**< XBARA_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */ | ||
| 909 | kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U, /**< XBARA_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */ | ||
| 910 | kXBARA1_OutputFlexpwm2ExtClk = 48|0x100U, /**< XBARA_OUT48 output assigned to FLEXPWM2_EXT_CLK */ | ||
| 911 | kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U, /**< XBARA_OUT49 output assigned to FLEXPWM2_FAULT0 */ | ||
| 912 | kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U, /**< XBARA_OUT50 output assigned to FLEXPWM2_FAULT1 */ | ||
| 913 | kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U, /**< XBARA_OUT51 output assigned to FLEXPWM2_EXT_FORCE */ | ||
| 914 | kXBARA1_OutputRESERVED52 = 52|0x100U, /**< XBARA_OUT52 output is reserved. */ | ||
| 915 | kXBARA1_OutputRESERVED53 = 53|0x100U, /**< XBARA_OUT53 output is reserved. */ | ||
| 916 | kXBARA1_OutputRESERVED54 = 54|0x100U, /**< XBARA_OUT54 output is reserved. */ | ||
| 917 | kXBARA1_OutputRESERVED55 = 55|0x100U, /**< XBARA_OUT55 output is reserved. */ | ||
| 918 | kXBARA1_OutputRESERVED56 = 56|0x100U, /**< XBARA_OUT56 output is reserved. */ | ||
| 919 | kXBARA1_OutputRESERVED57 = 57|0x100U, /**< XBARA_OUT57 output is reserved. */ | ||
| 920 | kXBARA1_OutputRESERVED58 = 58|0x100U, /**< XBARA_OUT58 output is reserved. */ | ||
| 921 | kXBARA1_OutputRESERVED59 = 59|0x100U, /**< XBARA_OUT59 output is reserved. */ | ||
| 922 | kXBARA1_OutputRESERVED60 = 60|0x100U, /**< XBARA_OUT60 output is reserved. */ | ||
| 923 | kXBARA1_OutputRESERVED61 = 61|0x100U, /**< XBARA_OUT61 output is reserved. */ | ||
| 924 | kXBARA1_OutputRESERVED62 = 62|0x100U, /**< XBARA_OUT62 output is reserved. */ | ||
| 925 | kXBARA1_OutputRESERVED63 = 63|0x100U, /**< XBARA_OUT63 output is reserved. */ | ||
| 926 | kXBARA1_OutputRESERVED64 = 64|0x100U, /**< XBARA_OUT64 output is reserved. */ | ||
| 927 | kXBARA1_OutputRESERVED65 = 65|0x100U, /**< XBARA_OUT65 output is reserved. */ | ||
| 928 | kXBARA1_OutputEnc1PhaseAInput = 66|0x100U, /**< XBARA_OUT66 output assigned to ENC1_PHASE_A_INPUT */ | ||
| 929 | kXBARA1_OutputEnc1PhaseBInput = 67|0x100U, /**< XBARA_OUT67 output assigned to ENC1_PHASE_B_INPUT */ | ||
| 930 | kXBARA1_OutputEnc1Index = 68|0x100U, /**< XBARA_OUT68 output assigned to ENC1_INDEX */ | ||
| 931 | kXBARA1_OutputEnc1Home = 69|0x100U, /**< XBARA_OUT69 output assigned to ENC1_HOME */ | ||
| 932 | kXBARA1_OutputEnc1Trigger = 70|0x100U, /**< XBARA_OUT70 output assigned to ENC1_TRIGGER */ | ||
| 933 | kXBARA1_OutputEnc2PhaseAInput = 71|0x100U, /**< XBARA_OUT71 output assigned to ENC2_PHASE_A_INPUT */ | ||
| 934 | kXBARA1_OutputEnc2PhaseBInput = 72|0x100U, /**< XBARA_OUT72 output assigned to ENC2_PHASE_B_INPUT */ | ||
| 935 | kXBARA1_OutputEnc2Index = 73|0x100U, /**< XBARA_OUT73 output assigned to ENC2_INDEX */ | ||
| 936 | kXBARA1_OutputEnc2Home = 74|0x100U, /**< XBARA_OUT74 output assigned to ENC2_HOME */ | ||
| 937 | kXBARA1_OutputEnc2Trigger = 75|0x100U, /**< XBARA_OUT75 output assigned to ENC2_TRIGGER */ | ||
| 938 | kXBARA1_OutputRESERVED76 = 76|0x100U, /**< XBARA_OUT76 output is reserved. */ | ||
| 939 | kXBARA1_OutputRESERVED77 = 77|0x100U, /**< XBARA_OUT77 output is reserved. */ | ||
| 940 | kXBARA1_OutputRESERVED78 = 78|0x100U, /**< XBARA_OUT78 output is reserved. */ | ||
| 941 | kXBARA1_OutputRESERVED79 = 79|0x100U, /**< XBARA_OUT79 output is reserved. */ | ||
| 942 | kXBARA1_OutputRESERVED80 = 80|0x100U, /**< XBARA_OUT80 output is reserved. */ | ||
| 943 | kXBARA1_OutputRESERVED81 = 81|0x100U, /**< XBARA_OUT81 output is reserved. */ | ||
| 944 | kXBARA1_OutputRESERVED82 = 82|0x100U, /**< XBARA_OUT82 output is reserved. */ | ||
| 945 | kXBARA1_OutputRESERVED83 = 83|0x100U, /**< XBARA_OUT83 output is reserved. */ | ||
| 946 | kXBARA1_OutputRESERVED84 = 84|0x100U, /**< XBARA_OUT84 output is reserved. */ | ||
| 947 | kXBARA1_OutputRESERVED85 = 85|0x100U, /**< XBARA_OUT85 output is reserved. */ | ||
| 948 | kXBARA1_OutputQtimer1Tmr0 = 86|0x100U, /**< XBARA_OUT86 output assigned to QTIMER1_TMR0 */ | ||
| 949 | kXBARA1_OutputQtimer1Tmr1 = 87|0x100U, /**< XBARA_OUT87 output assigned to QTIMER1_TMR1 */ | ||
| 950 | kXBARA1_OutputQtimer1Tmr2 = 88|0x100U, /**< XBARA_OUT88 output assigned to QTIMER1_TMR2 */ | ||
| 951 | kXBARA1_OutputQtimer1Tmr3 = 89|0x100U, /**< XBARA_OUT89 output assigned to QTIMER1_TMR3 */ | ||
| 952 | kXBARA1_OutputQtimer2Tmr0 = 90|0x100U, /**< XBARA_OUT90 output assigned to QTIMER2_TMR0 */ | ||
| 953 | kXBARA1_OutputQtimer2Tmr1 = 91|0x100U, /**< XBARA_OUT91 output assigned to QTIMER2_TMR1 */ | ||
| 954 | kXBARA1_OutputQtimer2Tmr2 = 92|0x100U, /**< XBARA_OUT92 output assigned to QTIMER2_TMR2 */ | ||
| 955 | kXBARA1_OutputQtimer2Tmr3 = 93|0x100U, /**< XBARA_OUT93 output assigned to QTIMER2_TMR3 */ | ||
| 956 | kXBARA1_OutputRESERVED94 = 94|0x100U, /**< XBARA_OUT94 output is reserved. */ | ||
| 957 | kXBARA1_OutputRESERVED95 = 95|0x100U, /**< XBARA_OUT95 output is reserved. */ | ||
| 958 | kXBARA1_OutputRESERVED96 = 96|0x100U, /**< XBARA_OUT96 output is reserved. */ | ||
| 959 | kXBARA1_OutputRESERVED97 = 97|0x100U, /**< XBARA_OUT97 output is reserved. */ | ||
| 960 | kXBARA1_OutputRESERVED98 = 98|0x100U, /**< XBARA_OUT98 output is reserved. */ | ||
| 961 | kXBARA1_OutputRESERVED99 = 99|0x100U, /**< XBARA_OUT99 output is reserved. */ | ||
| 962 | kXBARA1_OutputRESERVED100 = 100|0x100U, /**< XBARA_OUT100 output is reserved. */ | ||
| 963 | kXBARA1_OutputRESERVED101 = 101|0x100U, /**< XBARA_OUT101 output is reserved. */ | ||
| 964 | kXBARA1_OutputEwmEwmIn = 102|0x100U, /**< XBARA_OUT102 output assigned to EWM_EWM_IN */ | ||
| 965 | kXBARA1_OutputAdcEtcTrig00 = 103|0x100U, /**< XBARA_OUT103 output assigned to ADC_ETC_TRIG00 */ | ||
| 966 | kXBARA1_OutputAdcEtcTrig01 = 104|0x100U, /**< XBARA_OUT104 output assigned to ADC_ETC_TRIG01 */ | ||
| 967 | kXBARA1_OutputAdcEtcTrig02 = 105|0x100U, /**< XBARA_OUT105 output assigned to ADC_ETC_TRIG02 */ | ||
| 968 | kXBARA1_OutputAdcEtcTrig03 = 106|0x100U, /**< XBARA_OUT106 output assigned to ADC_ETC_TRIG03 */ | ||
| 969 | kXBARA1_OutputAdcEtcTrig10 = 107|0x100U, /**< XBARA_OUT107 output assigned to ADC_ETC_TRIG10 */ | ||
| 970 | kXBARA1_OutputAdcEtcTrig11 = 108|0x100U, /**< XBARA_OUT108 output assigned to ADC_ETC_TRIG11 */ | ||
| 971 | kXBARA1_OutputAdcEtcTrig12 = 109|0x100U, /**< XBARA_OUT109 output assigned to ADC_ETC_TRIG12 */ | ||
| 972 | kXBARA1_OutputAdcEtcTrig13 = 110|0x100U, /**< XBARA_OUT110 output assigned to ADC_ETC_TRIG13 */ | ||
| 973 | kXBARA1_OutputLpi2c1TrgInput = 111|0x100U, /**< XBARA_OUT111 output assigned to LPI2C1_TRG_INPUT */ | ||
| 974 | kXBARA1_OutputLpi2c2TrgInput = 112|0x100U, /**< XBARA_OUT112 output assigned to LPI2C2_TRG_INPUT */ | ||
| 975 | kXBARA1_OutputLpi2c3TrgInput = 113|0x100U, /**< XBARA_OUT113 output assigned to LPI2C3_TRG_INPUT */ | ||
| 976 | kXBARA1_OutputLpi2c4TrgInput = 114|0x100U, /**< XBARA_OUT114 output assigned to LPI2C4_TRG_INPUT */ | ||
| 977 | kXBARA1_OutputLpspi1TrgInput = 115|0x100U, /**< XBARA_OUT115 output assigned to LPSPI1_TRG_INPUT */ | ||
| 978 | kXBARA1_OutputLpspi2TrgInput = 116|0x100U, /**< XBARA_OUT116 output assigned to LPSPI2_TRG_INPUT */ | ||
| 979 | kXBARA1_OutputLpspi3TrgInput = 117|0x100U, /**< XBARA_OUT117 output assigned to LPSPI3_TRG_INPUT */ | ||
| 980 | kXBARA1_OutputLpspi4TrgInput = 118|0x100U, /**< XBARA_OUT118 output assigned to LPSPI4_TRG_INPUT */ | ||
| 981 | kXBARA1_OutputLpuart1TrgInput = 119|0x100U, /**< XBARA_OUT119 output assigned to LPUART1_TRG_INPUT */ | ||
| 982 | kXBARA1_OutputLpuart2TrgInput = 120|0x100U, /**< XBARA_OUT120 output assigned to LPUART2_TRG_INPUT */ | ||
| 983 | kXBARA1_OutputLpuart3TrgInput = 121|0x100U, /**< XBARA_OUT121 output assigned to LPUART3_TRG_INPUT */ | ||
| 984 | kXBARA1_OutputLpuart4TrgInput = 122|0x100U, /**< XBARA_OUT122 output assigned to LPUART4_TRG_INPUT */ | ||
| 985 | kXBARA1_OutputLpuart5TrgInput = 123|0x100U, /**< XBARA_OUT123 output assigned to LPUART5_TRG_INPUT */ | ||
| 986 | kXBARA1_OutputLpuart6TrgInput = 124|0x100U, /**< XBARA_OUT124 output assigned to LPUART6_TRG_INPUT */ | ||
| 987 | kXBARA1_OutputLpuart7TrgInput = 125|0x100U, /**< XBARA_OUT125 output assigned to LPUART7_TRG_INPUT */ | ||
| 988 | kXBARA1_OutputLpuart8TrgInput = 126|0x100U, /**< XBARA_OUT126 output assigned to LPUART8_TRG_INPUT */ | ||
| 989 | kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U, /**< XBARA_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */ | ||
| 990 | kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U, /**< XBARA_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */ | ||
| 991 | kXBARA1_OutputRESERVED129 = 129|0x100U, /**< XBARA_OUT129 output is reserved. */ | ||
| 992 | kXBARA1_OutputRESERVED130 = 130|0x100U, /**< XBARA_OUT130 output is reserved. */ | ||
| 993 | kXBARA1_OutputRESERVED131 = 131|0x100U, /**< XBARA_OUT131 output is reserved. */ | ||
| 994 | kXBARB2_OutputAoi1In00 = 0|0x200U, /**< XBARB_OUT0 output assigned to AOI1_IN00 */ | ||
| 995 | kXBARB2_OutputAoi1In01 = 1|0x200U, /**< XBARB_OUT1 output assigned to AOI1_IN01 */ | ||
| 996 | kXBARB2_OutputAoi1In02 = 2|0x200U, /**< XBARB_OUT2 output assigned to AOI1_IN02 */ | ||
| 997 | kXBARB2_OutputAoi1In03 = 3|0x200U, /**< XBARB_OUT3 output assigned to AOI1_IN03 */ | ||
| 998 | kXBARB2_OutputAoi1In04 = 4|0x200U, /**< XBARB_OUT4 output assigned to AOI1_IN04 */ | ||
| 999 | kXBARB2_OutputAoi1In05 = 5|0x200U, /**< XBARB_OUT5 output assigned to AOI1_IN05 */ | ||
| 1000 | kXBARB2_OutputAoi1In06 = 6|0x200U, /**< XBARB_OUT6 output assigned to AOI1_IN06 */ | ||
| 1001 | kXBARB2_OutputAoi1In07 = 7|0x200U, /**< XBARB_OUT7 output assigned to AOI1_IN07 */ | ||
| 1002 | kXBARB2_OutputAoi1In08 = 8|0x200U, /**< XBARB_OUT8 output assigned to AOI1_IN08 */ | ||
| 1003 | kXBARB2_OutputAoi1In09 = 9|0x200U, /**< XBARB_OUT9 output assigned to AOI1_IN09 */ | ||
| 1004 | kXBARB2_OutputAoi1In10 = 10|0x200U, /**< XBARB_OUT10 output assigned to AOI1_IN10 */ | ||
| 1005 | kXBARB2_OutputAoi1In11 = 11|0x200U, /**< XBARB_OUT11 output assigned to AOI1_IN11 */ | ||
| 1006 | kXBARB2_OutputAoi1In12 = 12|0x200U, /**< XBARB_OUT12 output assigned to AOI1_IN12 */ | ||
| 1007 | kXBARB2_OutputAoi1In13 = 13|0x200U, /**< XBARB_OUT13 output assigned to AOI1_IN13 */ | ||
| 1008 | kXBARB2_OutputAoi1In14 = 14|0x200U, /**< XBARB_OUT14 output assigned to AOI1_IN14 */ | ||
| 1009 | kXBARB2_OutputAoi1In15 = 15|0x200U, /**< XBARB_OUT15 output assigned to AOI1_IN15 */ | ||
| 1010 | } xbar_output_signal_t; | ||
| 1011 | |||
| 1012 | |||
| 1013 | /*! | ||
| 1014 | * @} | ||
| 1015 | */ /* end of group Mapping_Information */ | ||
| 1016 | |||
| 1017 | |||
| 1018 | /* ---------------------------------------------------------------------------- | ||
| 1019 | -- Device Peripheral Access Layer | ||
| 1020 | ---------------------------------------------------------------------------- */ | ||
| 1021 | |||
| 1022 | /*! | ||
| 1023 | * @addtogroup Peripheral_access_layer Device Peripheral Access Layer | ||
| 1024 | * @{ | ||
| 1025 | */ | ||
| 1026 | |||
| 1027 | |||
| 1028 | /* | ||
| 1029 | ** Start of section using anonymous unions | ||
| 1030 | */ | ||
| 1031 | |||
| 1032 | #if defined(__ARMCC_VERSION) | ||
| 1033 | #if (__ARMCC_VERSION >= 6010050) | ||
| 1034 | #pragma clang diagnostic push | ||
| 1035 | #else | ||
| 1036 | #pragma push | ||
| 1037 | #pragma anon_unions | ||
| 1038 | #endif | ||
| 1039 | #elif defined(__CWCC__) | ||
| 1040 | #pragma push | ||
| 1041 | #pragma cpp_extensions on | ||
| 1042 | #elif defined(__GNUC__) | ||
| 1043 | /* anonymous unions are enabled by default */ | ||
| 1044 | #elif defined(__IAR_SYSTEMS_ICC__) | ||
| 1045 | #pragma language=extended | ||
| 1046 | #else | ||
| 1047 | #error Not supported compiler type | ||
| 1048 | #endif | ||
| 1049 | |||
| 1050 | /* ---------------------------------------------------------------------------- | ||
| 1051 | -- ADC Peripheral Access Layer | ||
| 1052 | ---------------------------------------------------------------------------- */ | ||
| 1053 | |||
| 1054 | /*! | ||
| 1055 | * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer | ||
| 1056 | * @{ | ||
| 1057 | */ | ||
| 1058 | |||
| 1059 | /** ADC - Register Layout Typedef */ | ||
| 1060 | typedef struct { | ||
| 1061 | __IO uint32_t HC[8]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */ | ||
| 1062 | __I uint32_t HS; /**< Status register for HW triggers, offset: 0x20 */ | ||
| 1063 | __I uint32_t R[8]; /**< Data result register for HW triggers, array offset: 0x24, array step: 0x4 */ | ||
| 1064 | __IO uint32_t CFG; /**< Configuration register, offset: 0x44 */ | ||
| 1065 | __IO uint32_t GC; /**< General control register, offset: 0x48 */ | ||
| 1066 | __IO uint32_t GS; /**< General status register, offset: 0x4C */ | ||
| 1067 | __IO uint32_t CV; /**< Compare value register, offset: 0x50 */ | ||
| 1068 | __IO uint32_t OFS; /**< Offset correction value register, offset: 0x54 */ | ||
| 1069 | __IO uint32_t CAL; /**< Calibration value register, offset: 0x58 */ | ||
| 1070 | } ADC_Type; | ||
| 1071 | |||
| 1072 | /* ---------------------------------------------------------------------------- | ||
| 1073 | -- ADC Register Masks | ||
| 1074 | ---------------------------------------------------------------------------- */ | ||
| 1075 | |||
| 1076 | /*! | ||
| 1077 | * @addtogroup ADC_Register_Masks ADC Register Masks | ||
| 1078 | * @{ | ||
| 1079 | */ | ||
| 1080 | |||
| 1081 | /*! @name HC - Control register for hardware triggers */ | ||
| 1082 | /*! @{ */ | ||
| 1083 | #define ADC_HC_ADCH_MASK (0x1FU) | ||
| 1084 | #define ADC_HC_ADCH_SHIFT (0U) | ||
| 1085 | /*! ADCH - Input Channel Select | ||
| 1086 | * 0b10000..External channel selection from ADC_ETC | ||
| 1087 | * 0b11000..Reserved. | ||
| 1088 | * 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally | ||
| 1089 | * 0b11010..Reserved. | ||
| 1090 | * 0b11011..Reserved. | ||
| 1091 | * 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion. | ||
| 1092 | */ | ||
| 1093 | #define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) | ||
| 1094 | #define ADC_HC_AIEN_MASK (0x80U) | ||
| 1095 | #define ADC_HC_AIEN_SHIFT (7U) | ||
| 1096 | /*! AIEN - Conversion Complete Interrupt Enable/Disable Control | ||
| 1097 | * 0b1..Conversion complete interrupt enabled | ||
| 1098 | * 0b0..Conversion complete interrupt disabled | ||
| 1099 | */ | ||
| 1100 | #define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK) | ||
| 1101 | /*! @} */ | ||
| 1102 | |||
| 1103 | /* The count of ADC_HC */ | ||
| 1104 | #define ADC_HC_COUNT (8U) | ||
| 1105 | |||
| 1106 | /*! @name HS - Status register for HW triggers */ | ||
| 1107 | /*! @{ */ | ||
| 1108 | #define ADC_HS_COCO0_MASK (0x1U) | ||
| 1109 | #define ADC_HS_COCO0_SHIFT (0U) | ||
| 1110 | /*! COCO0 - Conversion Complete Flag | ||
| 1111 | */ | ||
| 1112 | #define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK) | ||
| 1113 | #define ADC_HS_COCO1_MASK (0x2U) | ||
| 1114 | #define ADC_HS_COCO1_SHIFT (1U) | ||
| 1115 | /*! COCO1 - Conversion Complete Flag | ||
| 1116 | */ | ||
| 1117 | #define ADC_HS_COCO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO1_SHIFT)) & ADC_HS_COCO1_MASK) | ||
| 1118 | #define ADC_HS_COCO2_MASK (0x4U) | ||
| 1119 | #define ADC_HS_COCO2_SHIFT (2U) | ||
| 1120 | #define ADC_HS_COCO2(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO2_SHIFT)) & ADC_HS_COCO2_MASK) | ||
| 1121 | #define ADC_HS_COCO3_MASK (0x8U) | ||
| 1122 | #define ADC_HS_COCO3_SHIFT (3U) | ||
| 1123 | #define ADC_HS_COCO3(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO3_SHIFT)) & ADC_HS_COCO3_MASK) | ||
| 1124 | #define ADC_HS_COCO4_MASK (0x10U) | ||
| 1125 | #define ADC_HS_COCO4_SHIFT (4U) | ||
| 1126 | #define ADC_HS_COCO4(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO4_SHIFT)) & ADC_HS_COCO4_MASK) | ||
| 1127 | #define ADC_HS_COCO5_MASK (0x20U) | ||
| 1128 | #define ADC_HS_COCO5_SHIFT (5U) | ||
| 1129 | #define ADC_HS_COCO5(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO5_SHIFT)) & ADC_HS_COCO5_MASK) | ||
| 1130 | #define ADC_HS_COCO6_MASK (0x40U) | ||
| 1131 | #define ADC_HS_COCO6_SHIFT (6U) | ||
| 1132 | #define ADC_HS_COCO6(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO6_SHIFT)) & ADC_HS_COCO6_MASK) | ||
| 1133 | #define ADC_HS_COCO7_MASK (0x80U) | ||
| 1134 | #define ADC_HS_COCO7_SHIFT (7U) | ||
| 1135 | #define ADC_HS_COCO7(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO7_SHIFT)) & ADC_HS_COCO7_MASK) | ||
| 1136 | /*! @} */ | ||
| 1137 | |||
| 1138 | /*! @name R - Data result register for HW triggers */ | ||
| 1139 | /*! @{ */ | ||
| 1140 | #define ADC_R_CDATA_MASK (0xFFFU) | ||
| 1141 | #define ADC_R_CDATA_SHIFT (0U) | ||
| 1142 | /*! CDATA - Data (result of an ADC conversion) | ||
| 1143 | */ | ||
| 1144 | #define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK) | ||
| 1145 | /*! @} */ | ||
| 1146 | |||
| 1147 | /* The count of ADC_R */ | ||
| 1148 | #define ADC_R_COUNT (8U) | ||
| 1149 | |||
| 1150 | /*! @name CFG - Configuration register */ | ||
| 1151 | /*! @{ */ | ||
| 1152 | #define ADC_CFG_ADICLK_MASK (0x3U) | ||
| 1153 | #define ADC_CFG_ADICLK_SHIFT (0U) | ||
| 1154 | /*! ADICLK - Input Clock Select | ||
| 1155 | * 0b00..IPG clock | ||
| 1156 | * 0b01..IPG clock divided by 2 | ||
| 1157 | * 0b10..Reserved | ||
| 1158 | * 0b11..Asynchronous clock (ADACK) | ||
| 1159 | */ | ||
| 1160 | #define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) | ||
| 1161 | #define ADC_CFG_MODE_MASK (0xCU) | ||
| 1162 | #define ADC_CFG_MODE_SHIFT (2U) | ||
| 1163 | /*! MODE - Conversion Mode Selection | ||
| 1164 | * 0b00..8-bit conversion | ||
| 1165 | * 0b01..10-bit conversion | ||
| 1166 | * 0b10..12-bit conversion | ||
| 1167 | * 0b11..Reserved | ||
| 1168 | */ | ||
| 1169 | #define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) | ||
| 1170 | #define ADC_CFG_ADLSMP_MASK (0x10U) | ||
| 1171 | #define ADC_CFG_ADLSMP_SHIFT (4U) | ||
| 1172 | /*! ADLSMP - Long Sample Time Configuration | ||
| 1173 | * 0b0..Short sample mode. | ||
| 1174 | * 0b1..Long sample mode. | ||
| 1175 | */ | ||
| 1176 | #define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) | ||
| 1177 | #define ADC_CFG_ADIV_MASK (0x60U) | ||
| 1178 | #define ADC_CFG_ADIV_SHIFT (5U) | ||
| 1179 | /*! ADIV - Clock Divide Select | ||
| 1180 | * 0b00..Input clock | ||
| 1181 | * 0b01..Input clock / 2 | ||
| 1182 | * 0b10..Input clock / 4 | ||
| 1183 | * 0b11..Input clock / 8 | ||
| 1184 | */ | ||
| 1185 | #define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) | ||
| 1186 | #define ADC_CFG_ADLPC_MASK (0x80U) | ||
| 1187 | #define ADC_CFG_ADLPC_SHIFT (7U) | ||
| 1188 | /*! ADLPC - Low-Power Configuration | ||
| 1189 | * 0b0..ADC hard block not in low power mode. | ||
| 1190 | * 0b1..ADC hard block in low power mode. | ||
| 1191 | */ | ||
| 1192 | #define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) | ||
| 1193 | #define ADC_CFG_ADSTS_MASK (0x300U) | ||
| 1194 | #define ADC_CFG_ADSTS_SHIFT (8U) | ||
| 1195 | /*! ADSTS | ||
| 1196 | * 0b00..Sample period (ADC clocks) = 3 if ADLSMP=0b Sample period (ADC clocks) = 13 if ADLSMP=1b | ||
| 1197 | * 0b01..Sample period (ADC clocks) = 5 if ADLSMP=0b Sample period (ADC clocks) = 17 if ADLSMP=1b | ||
| 1198 | * 0b10..Sample period (ADC clocks) = 7 if ADLSMP=0b Sample period (ADC clocks) = 21 if ADLSMP=1b | ||
| 1199 | * 0b11..Sample period (ADC clocks) = 9 if ADLSMP=0b Sample period (ADC clocks) = 25 if ADLSMP=1b | ||
| 1200 | */ | ||
| 1201 | #define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) | ||
| 1202 | #define ADC_CFG_ADHSC_MASK (0x400U) | ||
| 1203 | #define ADC_CFG_ADHSC_SHIFT (10U) | ||
| 1204 | /*! ADHSC - High Speed Configuration | ||
| 1205 | * 0b0..Normal conversion selected. | ||
| 1206 | * 0b1..High speed conversion selected. | ||
| 1207 | */ | ||
| 1208 | #define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) | ||
| 1209 | #define ADC_CFG_REFSEL_MASK (0x1800U) | ||
| 1210 | #define ADC_CFG_REFSEL_SHIFT (11U) | ||
| 1211 | /*! REFSEL - Voltage Reference Selection | ||
| 1212 | * 0b00..Selects VREFH/VREFL as reference voltage. | ||
| 1213 | * 0b01..Reserved | ||
| 1214 | * 0b10..Reserved | ||
| 1215 | * 0b11..Reserved | ||
| 1216 | */ | ||
| 1217 | #define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) | ||
| 1218 | #define ADC_CFG_ADTRG_MASK (0x2000U) | ||
| 1219 | #define ADC_CFG_ADTRG_SHIFT (13U) | ||
| 1220 | /*! ADTRG - Conversion Trigger Select | ||
| 1221 | * 0b0..Software trigger selected | ||
| 1222 | * 0b1..Hardware trigger selected | ||
| 1223 | */ | ||
| 1224 | #define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) | ||
| 1225 | #define ADC_CFG_AVGS_MASK (0xC000U) | ||
| 1226 | #define ADC_CFG_AVGS_SHIFT (14U) | ||
| 1227 | /*! AVGS - Hardware Average select | ||
| 1228 | * 0b00..4 samples averaged | ||
| 1229 | * 0b01..8 samples averaged | ||
| 1230 | * 0b10..16 samples averaged | ||
| 1231 | * 0b11..32 samples averaged | ||
| 1232 | */ | ||
| 1233 | #define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) | ||
| 1234 | #define ADC_CFG_OVWREN_MASK (0x10000U) | ||
| 1235 | #define ADC_CFG_OVWREN_SHIFT (16U) | ||
| 1236 | /*! OVWREN - Data Overwrite Enable | ||
| 1237 | * 0b1..Enable the overwriting. | ||
| 1238 | * 0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data. | ||
| 1239 | */ | ||
| 1240 | #define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) | ||
| 1241 | /*! @} */ | ||
| 1242 | |||
| 1243 | /*! @name GC - General control register */ | ||
| 1244 | /*! @{ */ | ||
| 1245 | #define ADC_GC_ADACKEN_MASK (0x1U) | ||
| 1246 | #define ADC_GC_ADACKEN_SHIFT (0U) | ||
| 1247 | /*! ADACKEN - Asynchronous clock output enable | ||
| 1248 | * 0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. | ||
| 1249 | * 0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC | ||
| 1250 | */ | ||
| 1251 | #define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) | ||
| 1252 | #define ADC_GC_DMAEN_MASK (0x2U) | ||
| 1253 | #define ADC_GC_DMAEN_SHIFT (1U) | ||
| 1254 | /*! DMAEN - DMA Enable | ||
| 1255 | * 0b0..DMA disabled (default) | ||
| 1256 | * 0b1..DMA enabled | ||
| 1257 | */ | ||
| 1258 | #define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) | ||
| 1259 | #define ADC_GC_ACREN_MASK (0x4U) | ||
| 1260 | #define ADC_GC_ACREN_SHIFT (2U) | ||
| 1261 | /*! ACREN - Compare Function Range Enable | ||
| 1262 | * 0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. | ||
| 1263 | * 0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared. | ||
| 1264 | */ | ||
| 1265 | #define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) | ||
| 1266 | #define ADC_GC_ACFGT_MASK (0x8U) | ||
| 1267 | #define ADC_GC_ACFGT_SHIFT (3U) | ||
| 1268 | /*! ACFGT - Compare Function Greater Than Enable | ||
| 1269 | * 0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" | ||
| 1270 | * functionality based on the values placed in the ADC_CV register. | ||
| 1271 | * 0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" | ||
| 1272 | * functionality based on the values placed in the ADC_CV registers. | ||
| 1273 | */ | ||
| 1274 | #define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) | ||
| 1275 | #define ADC_GC_ACFE_MASK (0x10U) | ||
| 1276 | #define ADC_GC_ACFE_SHIFT (4U) | ||
| 1277 | /*! ACFE - Compare Function Enable | ||
| 1278 | * 0b0..Compare function disabled | ||
| 1279 | * 0b1..Compare function enabled | ||
| 1280 | */ | ||
| 1281 | #define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) | ||
| 1282 | #define ADC_GC_AVGE_MASK (0x20U) | ||
| 1283 | #define ADC_GC_AVGE_SHIFT (5U) | ||
| 1284 | /*! AVGE - Hardware average enable | ||
| 1285 | * 0b0..Hardware average function disabled | ||
| 1286 | * 0b1..Hardware average function enabled | ||
| 1287 | */ | ||
| 1288 | #define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) | ||
| 1289 | #define ADC_GC_ADCO_MASK (0x40U) | ||
| 1290 | #define ADC_GC_ADCO_SHIFT (6U) | ||
| 1291 | /*! ADCO - Continuous Conversion Enable | ||
| 1292 | * 0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. | ||
| 1293 | * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. | ||
| 1294 | */ | ||
| 1295 | #define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) | ||
| 1296 | #define ADC_GC_CAL_MASK (0x80U) | ||
| 1297 | #define ADC_GC_CAL_SHIFT (7U) | ||
| 1298 | /*! CAL - Calibration | ||
| 1299 | */ | ||
| 1300 | #define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) | ||
| 1301 | /*! @} */ | ||
| 1302 | |||
| 1303 | /*! @name GS - General status register */ | ||
| 1304 | /*! @{ */ | ||
| 1305 | #define ADC_GS_ADACT_MASK (0x1U) | ||
| 1306 | #define ADC_GS_ADACT_SHIFT (0U) | ||
| 1307 | /*! ADACT - Conversion Active | ||
| 1308 | * 0b0..Conversion not in progress. | ||
| 1309 | * 0b1..Conversion in progress. | ||
| 1310 | */ | ||
| 1311 | #define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) | ||
| 1312 | #define ADC_GS_CALF_MASK (0x2U) | ||
| 1313 | #define ADC_GS_CALF_SHIFT (1U) | ||
| 1314 | /*! CALF - Calibration Failed Flag | ||
| 1315 | * 0b0..Calibration completed normally. | ||
| 1316 | * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed. | ||
| 1317 | */ | ||
| 1318 | #define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) | ||
| 1319 | #define ADC_GS_AWKST_MASK (0x4U) | ||
| 1320 | #define ADC_GS_AWKST_SHIFT (2U) | ||
| 1321 | /*! AWKST - Asynchronous wakeup interrupt status | ||
| 1322 | * 0b1..Asynchronous wake up interrupt occurred in stop mode. | ||
| 1323 | * 0b0..No asynchronous interrupt. | ||
| 1324 | */ | ||
| 1325 | #define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) | ||
| 1326 | /*! @} */ | ||
| 1327 | |||
| 1328 | /*! @name CV - Compare value register */ | ||
| 1329 | /*! @{ */ | ||
| 1330 | #define ADC_CV_CV1_MASK (0xFFFU) | ||
| 1331 | #define ADC_CV_CV1_SHIFT (0U) | ||
| 1332 | /*! CV1 - Compare Value 1 | ||
| 1333 | */ | ||
| 1334 | #define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) | ||
| 1335 | #define ADC_CV_CV2_MASK (0xFFF0000U) | ||
| 1336 | #define ADC_CV_CV2_SHIFT (16U) | ||
| 1337 | /*! CV2 - Compare Value 2 | ||
| 1338 | */ | ||
| 1339 | #define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) | ||
| 1340 | /*! @} */ | ||
| 1341 | |||
| 1342 | /*! @name OFS - Offset correction value register */ | ||
| 1343 | /*! @{ */ | ||
| 1344 | #define ADC_OFS_OFS_MASK (0xFFFU) | ||
| 1345 | #define ADC_OFS_OFS_SHIFT (0U) | ||
| 1346 | /*! OFS - Offset value | ||
| 1347 | */ | ||
| 1348 | #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) | ||
| 1349 | #define ADC_OFS_SIGN_MASK (0x1000U) | ||
| 1350 | #define ADC_OFS_SIGN_SHIFT (12U) | ||
| 1351 | /*! SIGN - Sign bit | ||
| 1352 | * 0b0..The offset value is added with the raw result | ||
| 1353 | * 0b1..The offset value is subtracted from the raw converted value | ||
| 1354 | */ | ||
| 1355 | #define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) | ||
| 1356 | /*! @} */ | ||
| 1357 | |||
| 1358 | /*! @name CAL - Calibration value register */ | ||
| 1359 | /*! @{ */ | ||
| 1360 | #define ADC_CAL_CAL_CODE_MASK (0xFU) | ||
| 1361 | #define ADC_CAL_CAL_CODE_SHIFT (0U) | ||
| 1362 | /*! CAL_CODE - Calibration Result Value | ||
| 1363 | */ | ||
| 1364 | #define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) | ||
| 1365 | /*! @} */ | ||
| 1366 | |||
| 1367 | |||
| 1368 | /*! | ||
| 1369 | * @} | ||
| 1370 | */ /* end of group ADC_Register_Masks */ | ||
| 1371 | |||
| 1372 | |||
| 1373 | /* ADC - Peripheral instance base addresses */ | ||
| 1374 | /** Peripheral ADC1 base address */ | ||
| 1375 | #define ADC1_BASE (0x400C4000u) | ||
| 1376 | /** Peripheral ADC1 base pointer */ | ||
| 1377 | #define ADC1 ((ADC_Type *)ADC1_BASE) | ||
| 1378 | /** Peripheral ADC2 base address */ | ||
| 1379 | #define ADC2_BASE (0x400C8000u) | ||
| 1380 | /** Peripheral ADC2 base pointer */ | ||
| 1381 | #define ADC2 ((ADC_Type *)ADC2_BASE) | ||
| 1382 | /** Array initializer of ADC peripheral base addresses */ | ||
| 1383 | #define ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE } | ||
| 1384 | /** Array initializer of ADC peripheral base pointers */ | ||
| 1385 | #define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 } | ||
| 1386 | /** Interrupt vectors for the ADC peripheral type */ | ||
| 1387 | #define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn } | ||
| 1388 | |||
| 1389 | /*! | ||
| 1390 | * @} | ||
| 1391 | */ /* end of group ADC_Peripheral_Access_Layer */ | ||
| 1392 | |||
| 1393 | |||
| 1394 | /* ---------------------------------------------------------------------------- | ||
| 1395 | -- ADC_ETC Peripheral Access Layer | ||
| 1396 | ---------------------------------------------------------------------------- */ | ||
| 1397 | |||
| 1398 | /*! | ||
| 1399 | * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer | ||
| 1400 | * @{ | ||
| 1401 | */ | ||
| 1402 | |||
| 1403 | /** ADC_ETC - Register Layout Typedef */ | ||
| 1404 | typedef struct { | ||
| 1405 | __IO uint32_t CTRL; /**< ADC_ETC Global Control Register, offset: 0x0 */ | ||
| 1406 | __IO uint32_t DONE0_1_IRQ; /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */ | ||
| 1407 | __IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */ | ||
| 1408 | __IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */ | ||
| 1409 | struct { /* offset: 0x10, array step: 0x28 */ | ||
| 1410 | __IO uint32_t TRIGn_CTRL; /**< ETC_TRIG Control Register, array offset: 0x10, array step: 0x28 */ | ||
| 1411 | __IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG Counter Register, array offset: 0x14, array step: 0x28 */ | ||
| 1412 | __IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */ | ||
| 1413 | __IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */ | ||
| 1414 | __IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */ | ||
| 1415 | __IO uint32_t TRIGn_CHAIN_7_6; /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */ | ||
| 1416 | __I uint32_t TRIGn_RESULT_1_0; /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */ | ||
| 1417 | __I uint32_t TRIGn_RESULT_3_2; /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */ | ||
| 1418 | __I uint32_t TRIGn_RESULT_5_4; /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */ | ||
| 1419 | __I uint32_t TRIGn_RESULT_7_6; /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */ | ||
| 1420 | } TRIG[8]; | ||
| 1421 | } ADC_ETC_Type; | ||
| 1422 | |||
| 1423 | /* ---------------------------------------------------------------------------- | ||
| 1424 | -- ADC_ETC Register Masks | ||
| 1425 | ---------------------------------------------------------------------------- */ | ||
| 1426 | |||
| 1427 | /*! | ||
| 1428 | * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks | ||
| 1429 | * @{ | ||
| 1430 | */ | ||
| 1431 | |||
| 1432 | /*! @name CTRL - ADC_ETC Global Control Register */ | ||
| 1433 | /*! @{ */ | ||
| 1434 | #define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) | ||
| 1435 | #define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) | ||
| 1436 | #define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) | ||
| 1437 | #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U) | ||
| 1438 | #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U) | ||
| 1439 | #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK) | ||
| 1440 | #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U) | ||
| 1441 | #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U) | ||
| 1442 | #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK) | ||
| 1443 | #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U) | ||
| 1444 | #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U) | ||
| 1445 | #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK) | ||
| 1446 | #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U) | ||
| 1447 | #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U) | ||
| 1448 | #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK) | ||
| 1449 | #define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) | ||
| 1450 | #define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) | ||
| 1451 | #define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) | ||
| 1452 | #define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U) | ||
| 1453 | #define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U) | ||
| 1454 | #define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK) | ||
| 1455 | #define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U) | ||
| 1456 | #define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U) | ||
| 1457 | #define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK) | ||
| 1458 | #define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) | ||
| 1459 | #define ADC_ETC_CTRL_SOFTRST_SHIFT (31U) | ||
| 1460 | #define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) | ||
| 1461 | /*! @} */ | ||
| 1462 | |||
| 1463 | /*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */ | ||
| 1464 | /*! @{ */ | ||
| 1465 | #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) | ||
| 1466 | #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) | ||
| 1467 | #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) | ||
| 1468 | #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U) | ||
| 1469 | #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U) | ||
| 1470 | #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK) | ||
| 1471 | #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U) | ||
| 1472 | #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U) | ||
| 1473 | #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK) | ||
| 1474 | #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U) | ||
| 1475 | #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U) | ||
| 1476 | #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK) | ||
| 1477 | #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U) | ||
| 1478 | #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U) | ||
| 1479 | #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK) | ||
| 1480 | #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U) | ||
| 1481 | #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U) | ||
| 1482 | #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK) | ||
| 1483 | #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U) | ||
| 1484 | #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U) | ||
| 1485 | #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK) | ||
| 1486 | #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U) | ||
| 1487 | #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U) | ||
| 1488 | #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK) | ||
| 1489 | #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U) | ||
| 1490 | #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U) | ||
| 1491 | #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK) | ||
| 1492 | #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U) | ||
| 1493 | #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U) | ||
| 1494 | #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK) | ||
| 1495 | #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U) | ||
| 1496 | #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U) | ||
| 1497 | #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK) | ||
| 1498 | #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U) | ||
| 1499 | #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U) | ||
| 1500 | #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK) | ||
| 1501 | #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U) | ||
| 1502 | #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U) | ||
| 1503 | #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK) | ||
| 1504 | #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U) | ||
| 1505 | #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U) | ||
| 1506 | #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK) | ||
| 1507 | #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U) | ||
| 1508 | #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U) | ||
| 1509 | #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK) | ||
| 1510 | #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) | ||
| 1511 | #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) | ||
| 1512 | #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) | ||
| 1513 | /*! @} */ | ||
| 1514 | |||
| 1515 | /*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */ | ||
| 1516 | /*! @{ */ | ||
| 1517 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) | ||
| 1518 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) | ||
| 1519 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK) | ||
| 1520 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U) | ||
| 1521 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U) | ||
| 1522 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK) | ||
| 1523 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U) | ||
| 1524 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U) | ||
| 1525 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK) | ||
| 1526 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U) | ||
| 1527 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U) | ||
| 1528 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK) | ||
| 1529 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U) | ||
| 1530 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U) | ||
| 1531 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK) | ||
| 1532 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U) | ||
| 1533 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U) | ||
| 1534 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK) | ||
| 1535 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U) | ||
| 1536 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U) | ||
| 1537 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK) | ||
| 1538 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U) | ||
| 1539 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U) | ||
| 1540 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK) | ||
| 1541 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U) | ||
| 1542 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U) | ||
| 1543 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK) | ||
| 1544 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U) | ||
| 1545 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U) | ||
| 1546 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK) | ||
| 1547 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U) | ||
| 1548 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U) | ||
| 1549 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK) | ||
| 1550 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U) | ||
| 1551 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U) | ||
| 1552 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK) | ||
| 1553 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U) | ||
| 1554 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U) | ||
| 1555 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK) | ||
| 1556 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U) | ||
| 1557 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U) | ||
| 1558 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK) | ||
| 1559 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U) | ||
| 1560 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U) | ||
| 1561 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK) | ||
| 1562 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) | ||
| 1563 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U) | ||
| 1564 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK) | ||
| 1565 | /*! @} */ | ||
| 1566 | |||
| 1567 | /*! @name DMA_CTRL - ETC DMA control Register */ | ||
| 1568 | /*! @{ */ | ||
| 1569 | #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) | ||
| 1570 | #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) | ||
| 1571 | #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) | ||
| 1572 | #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U) | ||
| 1573 | #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U) | ||
| 1574 | #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK) | ||
| 1575 | #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U) | ||
| 1576 | #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U) | ||
| 1577 | #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK) | ||
| 1578 | #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U) | ||
| 1579 | #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U) | ||
| 1580 | #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK) | ||
| 1581 | #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U) | ||
| 1582 | #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U) | ||
| 1583 | #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK) | ||
| 1584 | #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U) | ||
| 1585 | #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U) | ||
| 1586 | #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK) | ||
| 1587 | #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U) | ||
| 1588 | #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U) | ||
| 1589 | #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK) | ||
| 1590 | #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U) | ||
| 1591 | #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U) | ||
| 1592 | #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK) | ||
| 1593 | #define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U) | ||
| 1594 | #define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U) | ||
| 1595 | #define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK) | ||
| 1596 | #define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U) | ||
| 1597 | #define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U) | ||
| 1598 | #define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK) | ||
| 1599 | #define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U) | ||
| 1600 | #define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U) | ||
| 1601 | #define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK) | ||
| 1602 | #define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U) | ||
| 1603 | #define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U) | ||
| 1604 | #define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK) | ||
| 1605 | #define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U) | ||
| 1606 | #define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U) | ||
| 1607 | #define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK) | ||
| 1608 | #define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U) | ||
| 1609 | #define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U) | ||
| 1610 | #define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK) | ||
| 1611 | #define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U) | ||
| 1612 | #define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U) | ||
| 1613 | #define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK) | ||
| 1614 | #define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) | ||
| 1615 | #define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) | ||
| 1616 | #define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) | ||
| 1617 | /*! @} */ | ||
| 1618 | |||
| 1619 | /*! @name TRIGn_CTRL - ETC_TRIG Control Register */ | ||
| 1620 | /*! @{ */ | ||
| 1621 | #define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) | ||
| 1622 | #define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) | ||
| 1623 | #define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) | ||
| 1624 | #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U) | ||
| 1625 | #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U) | ||
| 1626 | #define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK) | ||
| 1627 | #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U) | ||
| 1628 | #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U) | ||
| 1629 | #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK) | ||
| 1630 | #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U) | ||
| 1631 | #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U) | ||
| 1632 | #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK) | ||
| 1633 | #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) | ||
| 1634 | #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) | ||
| 1635 | #define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) | ||
| 1636 | /*! @} */ | ||
| 1637 | |||
| 1638 | /* The count of ADC_ETC_TRIGn_CTRL */ | ||
| 1639 | #define ADC_ETC_TRIGn_CTRL_COUNT (8U) | ||
| 1640 | |||
| 1641 | /*! @name TRIGn_COUNTER - ETC_TRIG Counter Register */ | ||
| 1642 | /*! @{ */ | ||
| 1643 | #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) | ||
| 1644 | #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) | ||
| 1645 | #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) | ||
| 1646 | #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) | ||
| 1647 | #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) | ||
| 1648 | #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) | ||
| 1649 | /*! @} */ | ||
| 1650 | |||
| 1651 | /* The count of ADC_ETC_TRIGn_COUNTER */ | ||
| 1652 | #define ADC_ETC_TRIGn_COUNTER_COUNT (8U) | ||
| 1653 | |||
| 1654 | /*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */ | ||
| 1655 | /*! @{ */ | ||
| 1656 | #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) | ||
| 1657 | #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) | ||
| 1658 | #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) | ||
| 1659 | #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U) | ||
| 1660 | #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U) | ||
| 1661 | #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK) | ||
| 1662 | #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U) | ||
| 1663 | #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U) | ||
| 1664 | #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK) | ||
| 1665 | #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U) | ||
| 1666 | #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U) | ||
| 1667 | #define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK) | ||
| 1668 | #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U) | ||
| 1669 | #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U) | ||
| 1670 | #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK) | ||
| 1671 | #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U) | ||
| 1672 | #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U) | ||
| 1673 | #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK) | ||
| 1674 | #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U) | ||
| 1675 | #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U) | ||
| 1676 | #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK) | ||
| 1677 | #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) | ||
| 1678 | #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) | ||
| 1679 | #define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) | ||
| 1680 | /*! @} */ | ||
| 1681 | |||
| 1682 | /* The count of ADC_ETC_TRIGn_CHAIN_1_0 */ | ||
| 1683 | #define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U) | ||
| 1684 | |||
| 1685 | /*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */ | ||
| 1686 | /*! @{ */ | ||
| 1687 | #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) | ||
| 1688 | #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) | ||
| 1689 | #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) | ||
| 1690 | #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U) | ||
| 1691 | #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U) | ||
| 1692 | #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK) | ||
| 1693 | #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U) | ||
| 1694 | #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U) | ||
| 1695 | #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK) | ||
| 1696 | #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U) | ||
| 1697 | #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U) | ||
| 1698 | #define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK) | ||
| 1699 | #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U) | ||
| 1700 | #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U) | ||
| 1701 | #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK) | ||
| 1702 | #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U) | ||
| 1703 | #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U) | ||
| 1704 | #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK) | ||
| 1705 | #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U) | ||
| 1706 | #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U) | ||
| 1707 | #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK) | ||
| 1708 | #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) | ||
| 1709 | #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) | ||
| 1710 | #define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) | ||
| 1711 | /*! @} */ | ||
| 1712 | |||
| 1713 | /* The count of ADC_ETC_TRIGn_CHAIN_3_2 */ | ||
| 1714 | #define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U) | ||
| 1715 | |||
| 1716 | /*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */ | ||
| 1717 | /*! @{ */ | ||
| 1718 | #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) | ||
| 1719 | #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) | ||
| 1720 | #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) | ||
| 1721 | #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U) | ||
| 1722 | #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U) | ||
| 1723 | #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK) | ||
| 1724 | #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U) | ||
| 1725 | #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U) | ||
| 1726 | #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK) | ||
| 1727 | #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U) | ||
| 1728 | #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U) | ||
| 1729 | #define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK) | ||
| 1730 | #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U) | ||
| 1731 | #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U) | ||
| 1732 | #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK) | ||
| 1733 | #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U) | ||
| 1734 | #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U) | ||
| 1735 | #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK) | ||
| 1736 | #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U) | ||
| 1737 | #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U) | ||
| 1738 | #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK) | ||
| 1739 | #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U) | ||
| 1740 | #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U) | ||
| 1741 | #define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK) | ||
| 1742 | /*! @} */ | ||
| 1743 | |||
| 1744 | /* The count of ADC_ETC_TRIGn_CHAIN_5_4 */ | ||
| 1745 | #define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U) | ||
| 1746 | |||
| 1747 | /*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */ | ||
| 1748 | /*! @{ */ | ||
| 1749 | #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU) | ||
| 1750 | #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U) | ||
| 1751 | #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK) | ||
| 1752 | #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U) | ||
| 1753 | #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U) | ||
| 1754 | #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK) | ||
| 1755 | #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U) | ||
| 1756 | #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U) | ||
| 1757 | #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK) | ||
| 1758 | #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U) | ||
| 1759 | #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U) | ||
| 1760 | #define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK) | ||
| 1761 | #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U) | ||
| 1762 | #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U) | ||
| 1763 | #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK) | ||
| 1764 | #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U) | ||
| 1765 | #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U) | ||
| 1766 | #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK) | ||
| 1767 | #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U) | ||
| 1768 | #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U) | ||
| 1769 | #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK) | ||
| 1770 | #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U) | ||
| 1771 | #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U) | ||
| 1772 | #define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK) | ||
| 1773 | /*! @} */ | ||
| 1774 | |||
| 1775 | /* The count of ADC_ETC_TRIGn_CHAIN_7_6 */ | ||
| 1776 | #define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U) | ||
| 1777 | |||
| 1778 | /*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */ | ||
| 1779 | /*! @{ */ | ||
| 1780 | #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU) | ||
| 1781 | #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U) | ||
| 1782 | #define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK) | ||
| 1783 | #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U) | ||
| 1784 | #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U) | ||
| 1785 | #define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK) | ||
| 1786 | /*! @} */ | ||
| 1787 | |||
| 1788 | /* The count of ADC_ETC_TRIGn_RESULT_1_0 */ | ||
| 1789 | #define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U) | ||
| 1790 | |||
| 1791 | /*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */ | ||
| 1792 | /*! @{ */ | ||
| 1793 | #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU) | ||
| 1794 | #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U) | ||
| 1795 | #define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK) | ||
| 1796 | #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U) | ||
| 1797 | #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U) | ||
| 1798 | #define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK) | ||
| 1799 | /*! @} */ | ||
| 1800 | |||
| 1801 | /* The count of ADC_ETC_TRIGn_RESULT_3_2 */ | ||
| 1802 | #define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U) | ||
| 1803 | |||
| 1804 | /*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */ | ||
| 1805 | /*! @{ */ | ||
| 1806 | #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU) | ||
| 1807 | #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U) | ||
| 1808 | #define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK) | ||
| 1809 | #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U) | ||
| 1810 | #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U) | ||
| 1811 | #define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK) | ||
| 1812 | /*! @} */ | ||
| 1813 | |||
| 1814 | /* The count of ADC_ETC_TRIGn_RESULT_5_4 */ | ||
| 1815 | #define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U) | ||
| 1816 | |||
| 1817 | /*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */ | ||
| 1818 | /*! @{ */ | ||
| 1819 | #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU) | ||
| 1820 | #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U) | ||
| 1821 | #define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK) | ||
| 1822 | #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U) | ||
| 1823 | #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U) | ||
| 1824 | #define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK) | ||
| 1825 | /*! @} */ | ||
| 1826 | |||
| 1827 | /* The count of ADC_ETC_TRIGn_RESULT_7_6 */ | ||
| 1828 | #define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U) | ||
| 1829 | |||
| 1830 | |||
| 1831 | /*! | ||
| 1832 | * @} | ||
| 1833 | */ /* end of group ADC_ETC_Register_Masks */ | ||
| 1834 | |||
| 1835 | |||
| 1836 | /* ADC_ETC - Peripheral instance base addresses */ | ||
| 1837 | /** Peripheral ADC_ETC base address */ | ||
| 1838 | #define ADC_ETC_BASE (0x403B0000u) | ||
| 1839 | /** Peripheral ADC_ETC base pointer */ | ||
| 1840 | #define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE) | ||
| 1841 | /** Array initializer of ADC_ETC peripheral base addresses */ | ||
| 1842 | #define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE } | ||
| 1843 | /** Array initializer of ADC_ETC peripheral base pointers */ | ||
| 1844 | #define ADC_ETC_BASE_PTRS { ADC_ETC } | ||
| 1845 | /** Interrupt vectors for the ADC_ETC peripheral type */ | ||
| 1846 | #define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } } | ||
| 1847 | #define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn } | ||
| 1848 | |||
| 1849 | /*! | ||
| 1850 | * @} | ||
| 1851 | */ /* end of group ADC_ETC_Peripheral_Access_Layer */ | ||
| 1852 | |||
| 1853 | |||
| 1854 | /* ---------------------------------------------------------------------------- | ||
| 1855 | -- AIPSTZ Peripheral Access Layer | ||
| 1856 | ---------------------------------------------------------------------------- */ | ||
| 1857 | |||
| 1858 | /*! | ||
| 1859 | * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer | ||
| 1860 | * @{ | ||
| 1861 | */ | ||
| 1862 | |||
| 1863 | /** AIPSTZ - Register Layout Typedef */ | ||
| 1864 | typedef struct { | ||
| 1865 | __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ | ||
| 1866 | uint8_t RESERVED_0[60]; | ||
| 1867 | __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */ | ||
| 1868 | __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */ | ||
| 1869 | __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */ | ||
| 1870 | __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */ | ||
| 1871 | __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */ | ||
| 1872 | } AIPSTZ_Type; | ||
| 1873 | |||
| 1874 | /* ---------------------------------------------------------------------------- | ||
| 1875 | -- AIPSTZ Register Masks | ||
| 1876 | ---------------------------------------------------------------------------- */ | ||
| 1877 | |||
| 1878 | /*! | ||
| 1879 | * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks | ||
| 1880 | * @{ | ||
| 1881 | */ | ||
| 1882 | |||
| 1883 | /*! @name MPR - Master Priviledge Registers */ | ||
| 1884 | /*! @{ */ | ||
| 1885 | #define AIPSTZ_MPR_MPROT3_MASK (0xF0000U) | ||
| 1886 | #define AIPSTZ_MPR_MPROT3_SHIFT (16U) | ||
| 1887 | /*! MPROT3 | ||
| 1888 | * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. | ||
| 1889 | * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. | ||
| 1890 | * 0bxx0x..This master is not trusted for write accesses. | ||
| 1891 | * 0bxx1x..This master is trusted for write accesses. | ||
| 1892 | * 0bx0xx..This master is not trusted for read accesses. | ||
| 1893 | * 0bx1xx..This master is trusted for read accesses. | ||
| 1894 | * 0b1xxx..Write accesses from this master are allowed to be buffered | ||
| 1895 | */ | ||
| 1896 | #define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) | ||
| 1897 | #define AIPSTZ_MPR_MPROT2_MASK (0xF00000U) | ||
| 1898 | #define AIPSTZ_MPR_MPROT2_SHIFT (20U) | ||
| 1899 | /*! MPROT2 | ||
| 1900 | * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. | ||
| 1901 | * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. | ||
| 1902 | * 0bxx0x..This master is not trusted for write accesses. | ||
| 1903 | * 0bxx1x..This master is trusted for write accesses. | ||
| 1904 | * 0bx0xx..This master is not trusted for read accesses. | ||
| 1905 | * 0bx1xx..This master is trusted for read accesses. | ||
| 1906 | * 0b1xxx..Write accesses from this master are allowed to be buffered | ||
| 1907 | */ | ||
| 1908 | #define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) | ||
| 1909 | #define AIPSTZ_MPR_MPROT1_MASK (0xF000000U) | ||
| 1910 | #define AIPSTZ_MPR_MPROT1_SHIFT (24U) | ||
| 1911 | /*! MPROT1 | ||
| 1912 | * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. | ||
| 1913 | * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. | ||
| 1914 | * 0bxx0x..This master is not trusted for write accesses. | ||
| 1915 | * 0bxx1x..This master is trusted for write accesses. | ||
| 1916 | * 0bx0xx..This master is not trusted for read accesses. | ||
| 1917 | * 0bx1xx..This master is trusted for read accesses. | ||
| 1918 | * 0b1xxx..Write accesses from this master are allowed to be buffered | ||
| 1919 | */ | ||
| 1920 | #define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) | ||
| 1921 | #define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) | ||
| 1922 | #define AIPSTZ_MPR_MPROT0_SHIFT (28U) | ||
| 1923 | /*! MPROT0 | ||
| 1924 | * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. | ||
| 1925 | * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. | ||
| 1926 | * 0bxx0x..This master is not trusted for write accesses. | ||
| 1927 | * 0bxx1x..This master is trusted for write accesses. | ||
| 1928 | * 0bx0xx..This master is not trusted for read accesses. | ||
| 1929 | * 0bx1xx..This master is trusted for read accesses. | ||
| 1930 | * 0b1xxx..Write accesses from this master are allowed to be buffered | ||
| 1931 | */ | ||
| 1932 | #define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) | ||
| 1933 | /*! @} */ | ||
| 1934 | |||
| 1935 | /*! @name OPACR - Off-Platform Peripheral Access Control Registers */ | ||
| 1936 | /*! @{ */ | ||
| 1937 | #define AIPSTZ_OPACR_OPAC7_MASK (0xFU) | ||
| 1938 | #define AIPSTZ_OPACR_OPAC7_SHIFT (0U) | ||
| 1939 | /*! OPAC7 | ||
| 1940 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 1941 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 1942 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 1943 | * 0bxx0x..This peripheral allows write accesses. | ||
| 1944 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 1945 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 1946 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 1947 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 1948 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 1949 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 1950 | * on the IPS bus. | ||
| 1951 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 1952 | */ | ||
| 1953 | #define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) | ||
| 1954 | #define AIPSTZ_OPACR_OPAC6_MASK (0xF0U) | ||
| 1955 | #define AIPSTZ_OPACR_OPAC6_SHIFT (4U) | ||
| 1956 | /*! OPAC6 | ||
| 1957 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 1958 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 1959 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 1960 | * 0bxx0x..This peripheral allows write accesses. | ||
| 1961 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 1962 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 1963 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 1964 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 1965 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 1966 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 1967 | * on the IPS bus. | ||
| 1968 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 1969 | */ | ||
| 1970 | #define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK) | ||
| 1971 | #define AIPSTZ_OPACR_OPAC5_MASK (0xF00U) | ||
| 1972 | #define AIPSTZ_OPACR_OPAC5_SHIFT (8U) | ||
| 1973 | /*! OPAC5 | ||
| 1974 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 1975 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 1976 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 1977 | * 0bxx0x..This peripheral allows write accesses. | ||
| 1978 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 1979 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 1980 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 1981 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 1982 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 1983 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 1984 | * on the IPS bus. | ||
| 1985 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 1986 | */ | ||
| 1987 | #define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK) | ||
| 1988 | #define AIPSTZ_OPACR_OPAC4_MASK (0xF000U) | ||
| 1989 | #define AIPSTZ_OPACR_OPAC4_SHIFT (12U) | ||
| 1990 | /*! OPAC4 | ||
| 1991 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 1992 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 1993 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 1994 | * 0bxx0x..This peripheral allows write accesses. | ||
| 1995 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 1996 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 1997 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 1998 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 1999 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2000 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2001 | * on the IPS bus. | ||
| 2002 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2003 | */ | ||
| 2004 | #define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK) | ||
| 2005 | #define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U) | ||
| 2006 | #define AIPSTZ_OPACR_OPAC3_SHIFT (16U) | ||
| 2007 | /*! OPAC3 | ||
| 2008 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2009 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2010 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2011 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2012 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2013 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2014 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2015 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2016 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2017 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2018 | * on the IPS bus. | ||
| 2019 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2020 | */ | ||
| 2021 | #define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK) | ||
| 2022 | #define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U) | ||
| 2023 | #define AIPSTZ_OPACR_OPAC2_SHIFT (20U) | ||
| 2024 | /*! OPAC2 | ||
| 2025 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2026 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2027 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2028 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2029 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2030 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2031 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2032 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2033 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2034 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2035 | * on the IPS bus. | ||
| 2036 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2037 | */ | ||
| 2038 | #define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK) | ||
| 2039 | #define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U) | ||
| 2040 | #define AIPSTZ_OPACR_OPAC1_SHIFT (24U) | ||
| 2041 | /*! OPAC1 | ||
| 2042 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2043 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2044 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2045 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2046 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2047 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2048 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2049 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2050 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2051 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2052 | * on the IPS bus. | ||
| 2053 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2054 | */ | ||
| 2055 | #define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK) | ||
| 2056 | #define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) | ||
| 2057 | #define AIPSTZ_OPACR_OPAC0_SHIFT (28U) | ||
| 2058 | /*! OPAC0 | ||
| 2059 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2060 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2061 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2062 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2063 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2064 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2065 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2066 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2067 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2068 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2069 | * on the IPS bus. | ||
| 2070 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2071 | */ | ||
| 2072 | #define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) | ||
| 2073 | /*! @} */ | ||
| 2074 | |||
| 2075 | /*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */ | ||
| 2076 | /*! @{ */ | ||
| 2077 | #define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) | ||
| 2078 | #define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) | ||
| 2079 | /*! OPAC15 | ||
| 2080 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2081 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2082 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2083 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2084 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2085 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2086 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2087 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2088 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2089 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2090 | * on the IPS bus. | ||
| 2091 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2092 | */ | ||
| 2093 | #define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) | ||
| 2094 | #define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U) | ||
| 2095 | #define AIPSTZ_OPACR1_OPAC14_SHIFT (4U) | ||
| 2096 | /*! OPAC14 | ||
| 2097 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2098 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2099 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2100 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2101 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2102 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2103 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2104 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2105 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2106 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2107 | * on the IPS bus. | ||
| 2108 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2109 | */ | ||
| 2110 | #define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK) | ||
| 2111 | #define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U) | ||
| 2112 | #define AIPSTZ_OPACR1_OPAC13_SHIFT (8U) | ||
| 2113 | /*! OPAC13 | ||
| 2114 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2115 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2116 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2117 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2118 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2119 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2120 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2121 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2122 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2123 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2124 | * on the IPS bus. | ||
| 2125 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2126 | */ | ||
| 2127 | #define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK) | ||
| 2128 | #define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U) | ||
| 2129 | #define AIPSTZ_OPACR1_OPAC12_SHIFT (12U) | ||
| 2130 | /*! OPAC12 | ||
| 2131 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2132 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2133 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2134 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2135 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2136 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2137 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2138 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2139 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2140 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2141 | * on the IPS bus. | ||
| 2142 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2143 | */ | ||
| 2144 | #define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK) | ||
| 2145 | #define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U) | ||
| 2146 | #define AIPSTZ_OPACR1_OPAC11_SHIFT (16U) | ||
| 2147 | /*! OPAC11 | ||
| 2148 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2149 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2150 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2151 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2152 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2153 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2154 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2155 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2156 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2157 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2158 | * on the IPS bus. | ||
| 2159 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2160 | */ | ||
| 2161 | #define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK) | ||
| 2162 | #define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U) | ||
| 2163 | #define AIPSTZ_OPACR1_OPAC10_SHIFT (20U) | ||
| 2164 | /*! OPAC10 | ||
| 2165 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2166 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2167 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2168 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2169 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2170 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2171 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2172 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2173 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2174 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2175 | * on the IPS bus. | ||
| 2176 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2177 | */ | ||
| 2178 | #define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK) | ||
| 2179 | #define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U) | ||
| 2180 | #define AIPSTZ_OPACR1_OPAC9_SHIFT (24U) | ||
| 2181 | /*! OPAC9 | ||
| 2182 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2183 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2184 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2185 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2186 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2187 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2188 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2189 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2190 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2191 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2192 | * on the IPS bus. | ||
| 2193 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2194 | */ | ||
| 2195 | #define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK) | ||
| 2196 | #define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) | ||
| 2197 | #define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) | ||
| 2198 | /*! OPAC8 | ||
| 2199 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2200 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2201 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2202 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2203 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2204 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2205 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2206 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2207 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2208 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2209 | * on the IPS bus. | ||
| 2210 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2211 | */ | ||
| 2212 | #define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) | ||
| 2213 | /*! @} */ | ||
| 2214 | |||
| 2215 | /*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */ | ||
| 2216 | /*! @{ */ | ||
| 2217 | #define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) | ||
| 2218 | #define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) | ||
| 2219 | /*! OPAC23 | ||
| 2220 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2221 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2222 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2223 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2224 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2225 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2226 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2227 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2228 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2229 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2230 | * on the IPS bus. | ||
| 2231 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2232 | */ | ||
| 2233 | #define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) | ||
| 2234 | #define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U) | ||
| 2235 | #define AIPSTZ_OPACR2_OPAC22_SHIFT (4U) | ||
| 2236 | /*! OPAC22 | ||
| 2237 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2238 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2239 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2240 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2241 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2242 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2243 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2244 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2245 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2246 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2247 | * on the IPS bus. | ||
| 2248 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2249 | */ | ||
| 2250 | #define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK) | ||
| 2251 | #define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U) | ||
| 2252 | #define AIPSTZ_OPACR2_OPAC21_SHIFT (8U) | ||
| 2253 | /*! OPAC21 | ||
| 2254 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2255 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2256 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2257 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2258 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2259 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2260 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2261 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2262 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2263 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2264 | * on the IPS bus. | ||
| 2265 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2266 | */ | ||
| 2267 | #define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK) | ||
| 2268 | #define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U) | ||
| 2269 | #define AIPSTZ_OPACR2_OPAC20_SHIFT (12U) | ||
| 2270 | /*! OPAC20 | ||
| 2271 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2272 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2273 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2274 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2275 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2276 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2277 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2278 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2279 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2280 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2281 | * on the IPS bus. | ||
| 2282 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2283 | */ | ||
| 2284 | #define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK) | ||
| 2285 | #define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U) | ||
| 2286 | #define AIPSTZ_OPACR2_OPAC19_SHIFT (16U) | ||
| 2287 | /*! OPAC19 | ||
| 2288 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2289 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2290 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2291 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2292 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2293 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2294 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2295 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2296 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2297 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2298 | * on the IPS bus. | ||
| 2299 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2300 | */ | ||
| 2301 | #define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK) | ||
| 2302 | #define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U) | ||
| 2303 | #define AIPSTZ_OPACR2_OPAC18_SHIFT (20U) | ||
| 2304 | /*! OPAC18 | ||
| 2305 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2306 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2307 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2308 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2309 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2310 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2311 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2312 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2313 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2314 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2315 | * on the IPS bus. | ||
| 2316 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2317 | */ | ||
| 2318 | #define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK) | ||
| 2319 | #define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U) | ||
| 2320 | #define AIPSTZ_OPACR2_OPAC17_SHIFT (24U) | ||
| 2321 | /*! OPAC17 | ||
| 2322 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2323 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2324 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2325 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2326 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2327 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2328 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2329 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2330 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2331 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2332 | * on the IPS bus. | ||
| 2333 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2334 | */ | ||
| 2335 | #define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK) | ||
| 2336 | #define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) | ||
| 2337 | #define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) | ||
| 2338 | /*! OPAC16 | ||
| 2339 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2340 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2341 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2342 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2343 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2344 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2345 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2346 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2347 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2348 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2349 | * on the IPS bus. | ||
| 2350 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2351 | */ | ||
| 2352 | #define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) | ||
| 2353 | /*! @} */ | ||
| 2354 | |||
| 2355 | /*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */ | ||
| 2356 | /*! @{ */ | ||
| 2357 | #define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) | ||
| 2358 | #define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) | ||
| 2359 | /*! OPAC31 | ||
| 2360 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2361 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2362 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2363 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2364 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2365 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2366 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2367 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2368 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2369 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2370 | * on the IPS bus. | ||
| 2371 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2372 | */ | ||
| 2373 | #define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) | ||
| 2374 | #define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U) | ||
| 2375 | #define AIPSTZ_OPACR3_OPAC30_SHIFT (4U) | ||
| 2376 | /*! OPAC30 | ||
| 2377 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2378 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2379 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2380 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2381 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2382 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2383 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2384 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2385 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2386 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2387 | * on the IPS bus. | ||
| 2388 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2389 | */ | ||
| 2390 | #define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK) | ||
| 2391 | #define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U) | ||
| 2392 | #define AIPSTZ_OPACR3_OPAC29_SHIFT (8U) | ||
| 2393 | /*! OPAC29 | ||
| 2394 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2395 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2396 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2397 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2398 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2399 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2400 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2401 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2402 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2403 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2404 | * on the IPS bus. | ||
| 2405 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2406 | */ | ||
| 2407 | #define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK) | ||
| 2408 | #define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U) | ||
| 2409 | #define AIPSTZ_OPACR3_OPAC28_SHIFT (12U) | ||
| 2410 | /*! OPAC28 | ||
| 2411 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2412 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2413 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2414 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2415 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2416 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2417 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2418 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2419 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2420 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2421 | * on the IPS bus. | ||
| 2422 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2423 | */ | ||
| 2424 | #define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK) | ||
| 2425 | #define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U) | ||
| 2426 | #define AIPSTZ_OPACR3_OPAC27_SHIFT (16U) | ||
| 2427 | /*! OPAC27 | ||
| 2428 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2429 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2430 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2431 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2432 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2433 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2434 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2435 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2436 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2437 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2438 | * on the IPS bus. | ||
| 2439 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2440 | */ | ||
| 2441 | #define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK) | ||
| 2442 | #define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U) | ||
| 2443 | #define AIPSTZ_OPACR3_OPAC26_SHIFT (20U) | ||
| 2444 | /*! OPAC26 | ||
| 2445 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2446 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2447 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2448 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2449 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2450 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2451 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2452 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2453 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2454 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2455 | * on the IPS bus. | ||
| 2456 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2457 | */ | ||
| 2458 | #define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK) | ||
| 2459 | #define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U) | ||
| 2460 | #define AIPSTZ_OPACR3_OPAC25_SHIFT (24U) | ||
| 2461 | /*! OPAC25 | ||
| 2462 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2463 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2464 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2465 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2466 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2467 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2468 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2469 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2470 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2471 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2472 | * on the IPS bus. | ||
| 2473 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2474 | */ | ||
| 2475 | #define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK) | ||
| 2476 | #define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) | ||
| 2477 | #define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) | ||
| 2478 | /*! OPAC24 | ||
| 2479 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2480 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2481 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2482 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2483 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2484 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2485 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2486 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2487 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2488 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2489 | * on the IPS bus. | ||
| 2490 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2491 | */ | ||
| 2492 | #define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) | ||
| 2493 | /*! @} */ | ||
| 2494 | |||
| 2495 | /*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */ | ||
| 2496 | /*! @{ */ | ||
| 2497 | #define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) | ||
| 2498 | #define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) | ||
| 2499 | /*! OPAC33 | ||
| 2500 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2501 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2502 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2503 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2504 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2505 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2506 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2507 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2508 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2509 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2510 | * on the IPS bus. | ||
| 2511 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2512 | */ | ||
| 2513 | #define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) | ||
| 2514 | #define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) | ||
| 2515 | #define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) | ||
| 2516 | /*! OPAC32 | ||
| 2517 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2518 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2519 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2520 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2521 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2522 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2523 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2524 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2525 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2526 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2527 | * on the IPS bus. | ||
| 2528 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2529 | */ | ||
| 2530 | #define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) | ||
| 2531 | /*! @} */ | ||
| 2532 | |||
| 2533 | |||
| 2534 | /*! | ||
| 2535 | * @} | ||
| 2536 | */ /* end of group AIPSTZ_Register_Masks */ | ||
| 2537 | |||
| 2538 | |||
| 2539 | /* AIPSTZ - Peripheral instance base addresses */ | ||
| 2540 | /** Peripheral AIPSTZ1 base address */ | ||
| 2541 | #define AIPSTZ1_BASE (0x4007C000u) | ||
| 2542 | /** Peripheral AIPSTZ1 base pointer */ | ||
| 2543 | #define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE) | ||
| 2544 | /** Peripheral AIPSTZ2 base address */ | ||
| 2545 | #define AIPSTZ2_BASE (0x4017C000u) | ||
| 2546 | /** Peripheral AIPSTZ2 base pointer */ | ||
| 2547 | #define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE) | ||
| 2548 | /** Peripheral AIPSTZ3 base address */ | ||
| 2549 | #define AIPSTZ3_BASE (0x4027C000u) | ||
| 2550 | /** Peripheral AIPSTZ3 base pointer */ | ||
| 2551 | #define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE) | ||
| 2552 | /** Peripheral AIPSTZ4 base address */ | ||
| 2553 | #define AIPSTZ4_BASE (0x4037C000u) | ||
| 2554 | /** Peripheral AIPSTZ4 base pointer */ | ||
| 2555 | #define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE) | ||
| 2556 | /** Array initializer of AIPSTZ peripheral base addresses */ | ||
| 2557 | #define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE } | ||
| 2558 | /** Array initializer of AIPSTZ peripheral base pointers */ | ||
| 2559 | #define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 } | ||
| 2560 | |||
| 2561 | /*! | ||
| 2562 | * @} | ||
| 2563 | */ /* end of group AIPSTZ_Peripheral_Access_Layer */ | ||
| 2564 | |||
| 2565 | |||
| 2566 | /* ---------------------------------------------------------------------------- | ||
| 2567 | -- AOI Peripheral Access Layer | ||
| 2568 | ---------------------------------------------------------------------------- */ | ||
| 2569 | |||
| 2570 | /*! | ||
| 2571 | * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer | ||
| 2572 | * @{ | ||
| 2573 | */ | ||
| 2574 | |||
| 2575 | /** AOI - Register Layout Typedef */ | ||
| 2576 | typedef struct { | ||
| 2577 | struct { /* offset: 0x0, array step: 0x4 */ | ||
| 2578 | __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */ | ||
| 2579 | __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */ | ||
| 2580 | } BFCRT[4]; | ||
| 2581 | } AOI_Type; | ||
| 2582 | |||
| 2583 | /* ---------------------------------------------------------------------------- | ||
| 2584 | -- AOI Register Masks | ||
| 2585 | ---------------------------------------------------------------------------- */ | ||
| 2586 | |||
| 2587 | /*! | ||
| 2588 | * @addtogroup AOI_Register_Masks AOI Register Masks | ||
| 2589 | * @{ | ||
| 2590 | */ | ||
| 2591 | |||
| 2592 | /*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */ | ||
| 2593 | /*! @{ */ | ||
| 2594 | #define AOI_BFCRT01_PT1_DC_MASK (0x3U) | ||
| 2595 | #define AOI_BFCRT01_PT1_DC_SHIFT (0U) | ||
| 2596 | /*! PT1_DC - Product term 1, D input configuration | ||
| 2597 | * 0b00..Force the D input in this product term to a logical zero | ||
| 2598 | * 0b01..Pass the D input in this product term | ||
| 2599 | * 0b10..Complement the D input in this product term | ||
| 2600 | * 0b11..Force the D input in this product term to a logical one | ||
| 2601 | */ | ||
| 2602 | #define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK) | ||
| 2603 | #define AOI_BFCRT01_PT1_CC_MASK (0xCU) | ||
| 2604 | #define AOI_BFCRT01_PT1_CC_SHIFT (2U) | ||
| 2605 | /*! PT1_CC - Product term 1, C input configuration | ||
| 2606 | * 0b00..Force the C input in this product term to a logical zero | ||
| 2607 | * 0b01..Pass the C input in this product term | ||
| 2608 | * 0b10..Complement the C input in this product term | ||
| 2609 | * 0b11..Force the C input in this product term to a logical one | ||
| 2610 | */ | ||
| 2611 | #define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK) | ||
| 2612 | #define AOI_BFCRT01_PT1_BC_MASK (0x30U) | ||
| 2613 | #define AOI_BFCRT01_PT1_BC_SHIFT (4U) | ||
| 2614 | /*! PT1_BC - Product term 1, B input configuration | ||
| 2615 | * 0b00..Force the B input in this product term to a logical zero | ||
| 2616 | * 0b01..Pass the B input in this product term | ||
| 2617 | * 0b10..Complement the B input in this product term | ||
| 2618 | * 0b11..Force the B input in this product term to a logical one | ||
| 2619 | */ | ||
| 2620 | #define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK) | ||
| 2621 | #define AOI_BFCRT01_PT1_AC_MASK (0xC0U) | ||
| 2622 | #define AOI_BFCRT01_PT1_AC_SHIFT (6U) | ||
| 2623 | /*! PT1_AC - Product term 1, A input configuration | ||
| 2624 | * 0b00..Force the A input in this product term to a logical zero | ||
| 2625 | * 0b01..Pass the A input in this product term | ||
| 2626 | * 0b10..Complement the A input in this product term | ||
| 2627 | * 0b11..Force the A input in this product term to a logical one | ||
| 2628 | */ | ||
| 2629 | #define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK) | ||
| 2630 | #define AOI_BFCRT01_PT0_DC_MASK (0x300U) | ||
| 2631 | #define AOI_BFCRT01_PT0_DC_SHIFT (8U) | ||
| 2632 | /*! PT0_DC - Product term 0, D input configuration | ||
| 2633 | * 0b00..Force the D input in this product term to a logical zero | ||
| 2634 | * 0b01..Pass the D input in this product term | ||
| 2635 | * 0b10..Complement the D input in this product term | ||
| 2636 | * 0b11..Force the D input in this product term to a logical one | ||
| 2637 | */ | ||
| 2638 | #define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK) | ||
| 2639 | #define AOI_BFCRT01_PT0_CC_MASK (0xC00U) | ||
| 2640 | #define AOI_BFCRT01_PT0_CC_SHIFT (10U) | ||
| 2641 | /*! PT0_CC - Product term 0, C input configuration | ||
| 2642 | * 0b00..Force the C input in this product term to a logical zero | ||
| 2643 | * 0b01..Pass the C input in this product term | ||
| 2644 | * 0b10..Complement the C input in this product term | ||
| 2645 | * 0b11..Force the C input in this product term to a logical one | ||
| 2646 | */ | ||
| 2647 | #define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK) | ||
| 2648 | #define AOI_BFCRT01_PT0_BC_MASK (0x3000U) | ||
| 2649 | #define AOI_BFCRT01_PT0_BC_SHIFT (12U) | ||
| 2650 | /*! PT0_BC - Product term 0, B input configuration | ||
| 2651 | * 0b00..Force the B input in this product term to a logical zero | ||
| 2652 | * 0b01..Pass the B input in this product term | ||
| 2653 | * 0b10..Complement the B input in this product term | ||
| 2654 | * 0b11..Force the B input in this product term to a logical one | ||
| 2655 | */ | ||
| 2656 | #define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK) | ||
| 2657 | #define AOI_BFCRT01_PT0_AC_MASK (0xC000U) | ||
| 2658 | #define AOI_BFCRT01_PT0_AC_SHIFT (14U) | ||
| 2659 | /*! PT0_AC - Product term 0, A input configuration | ||
| 2660 | * 0b00..Force the A input in this product term to a logical zero | ||
| 2661 | * 0b01..Pass the A input in this product term | ||
| 2662 | * 0b10..Complement the A input in this product term | ||
| 2663 | * 0b11..Force the A input in this product term to a logical one | ||
| 2664 | */ | ||
| 2665 | #define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK) | ||
| 2666 | /*! @} */ | ||
| 2667 | |||
| 2668 | /* The count of AOI_BFCRT01 */ | ||
| 2669 | #define AOI_BFCRT01_COUNT (4U) | ||
| 2670 | |||
| 2671 | /*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */ | ||
| 2672 | /*! @{ */ | ||
| 2673 | #define AOI_BFCRT23_PT3_DC_MASK (0x3U) | ||
| 2674 | #define AOI_BFCRT23_PT3_DC_SHIFT (0U) | ||
| 2675 | /*! PT3_DC - Product term 3, D input configuration | ||
| 2676 | * 0b00..Force the D input in this product term to a logical zero | ||
| 2677 | * 0b01..Pass the D input in this product term | ||
| 2678 | * 0b10..Complement the D input in this product term | ||
| 2679 | * 0b11..Force the D input in this product term to a logical one | ||
| 2680 | */ | ||
| 2681 | #define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK) | ||
| 2682 | #define AOI_BFCRT23_PT3_CC_MASK (0xCU) | ||
| 2683 | #define AOI_BFCRT23_PT3_CC_SHIFT (2U) | ||
| 2684 | /*! PT3_CC - Product term 3, C input configuration | ||
| 2685 | * 0b00..Force the C input in this product term to a logical zero | ||
| 2686 | * 0b01..Pass the C input in this product term | ||
| 2687 | * 0b10..Complement the C input in this product term | ||
| 2688 | * 0b11..Force the C input in this product term to a logical one | ||
| 2689 | */ | ||
| 2690 | #define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK) | ||
| 2691 | #define AOI_BFCRT23_PT3_BC_MASK (0x30U) | ||
| 2692 | #define AOI_BFCRT23_PT3_BC_SHIFT (4U) | ||
| 2693 | /*! PT3_BC - Product term 3, B input configuration | ||
| 2694 | * 0b00..Force the B input in this product term to a logical zero | ||
| 2695 | * 0b01..Pass the B input in this product term | ||
| 2696 | * 0b10..Complement the B input in this product term | ||
| 2697 | * 0b11..Force the B input in this product term to a logical one | ||
| 2698 | */ | ||
| 2699 | #define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK) | ||
| 2700 | #define AOI_BFCRT23_PT3_AC_MASK (0xC0U) | ||
| 2701 | #define AOI_BFCRT23_PT3_AC_SHIFT (6U) | ||
| 2702 | /*! PT3_AC - Product term 3, A input configuration | ||
| 2703 | * 0b00..Force the A input in this product term to a logical zero | ||
| 2704 | * 0b01..Pass the A input in this product term | ||
| 2705 | * 0b10..Complement the A input in this product term | ||
| 2706 | * 0b11..Force the A input in this product term to a logical one | ||
| 2707 | */ | ||
| 2708 | #define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK) | ||
| 2709 | #define AOI_BFCRT23_PT2_DC_MASK (0x300U) | ||
| 2710 | #define AOI_BFCRT23_PT2_DC_SHIFT (8U) | ||
| 2711 | /*! PT2_DC - Product term 2, D input configuration | ||
| 2712 | * 0b00..Force the D input in this product term to a logical zero | ||
| 2713 | * 0b01..Pass the D input in this product term | ||
| 2714 | * 0b10..Complement the D input in this product term | ||
| 2715 | * 0b11..Force the D input in this product term to a logical one | ||
| 2716 | */ | ||
| 2717 | #define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK) | ||
| 2718 | #define AOI_BFCRT23_PT2_CC_MASK (0xC00U) | ||
| 2719 | #define AOI_BFCRT23_PT2_CC_SHIFT (10U) | ||
| 2720 | /*! PT2_CC - Product term 2, C input configuration | ||
| 2721 | * 0b00..Force the C input in this product term to a logical zero | ||
| 2722 | * 0b01..Pass the C input in this product term | ||
| 2723 | * 0b10..Complement the C input in this product term | ||
| 2724 | * 0b11..Force the C input in this product term to a logical one | ||
| 2725 | */ | ||
| 2726 | #define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK) | ||
| 2727 | #define AOI_BFCRT23_PT2_BC_MASK (0x3000U) | ||
| 2728 | #define AOI_BFCRT23_PT2_BC_SHIFT (12U) | ||
| 2729 | /*! PT2_BC - Product term 2, B input configuration | ||
| 2730 | * 0b00..Force the B input in this product term to a logical zero | ||
| 2731 | * 0b01..Pass the B input in this product term | ||
| 2732 | * 0b10..Complement the B input in this product term | ||
| 2733 | * 0b11..Force the B input in this product term to a logical one | ||
| 2734 | */ | ||
| 2735 | #define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK) | ||
| 2736 | #define AOI_BFCRT23_PT2_AC_MASK (0xC000U) | ||
| 2737 | #define AOI_BFCRT23_PT2_AC_SHIFT (14U) | ||
| 2738 | /*! PT2_AC - Product term 2, A input configuration | ||
| 2739 | * 0b00..Force the A input in this product term to a logical zero | ||
| 2740 | * 0b01..Pass the A input in this product term | ||
| 2741 | * 0b10..Complement the A input in this product term | ||
| 2742 | * 0b11..Force the A input in this product term to a logical one | ||
| 2743 | */ | ||
| 2744 | #define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK) | ||
| 2745 | /*! @} */ | ||
| 2746 | |||
| 2747 | /* The count of AOI_BFCRT23 */ | ||
| 2748 | #define AOI_BFCRT23_COUNT (4U) | ||
| 2749 | |||
| 2750 | |||
| 2751 | /*! | ||
| 2752 | * @} | ||
| 2753 | */ /* end of group AOI_Register_Masks */ | ||
| 2754 | |||
| 2755 | |||
| 2756 | /* AOI - Peripheral instance base addresses */ | ||
| 2757 | /** Peripheral AOI base address */ | ||
| 2758 | #define AOI_BASE (0x403B4000u) | ||
| 2759 | /** Peripheral AOI base pointer */ | ||
| 2760 | #define AOI ((AOI_Type *)AOI_BASE) | ||
| 2761 | /** Array initializer of AOI peripheral base addresses */ | ||
| 2762 | #define AOI_BASE_ADDRS { AOI_BASE } | ||
| 2763 | /** Array initializer of AOI peripheral base pointers */ | ||
| 2764 | #define AOI_BASE_PTRS { AOI } | ||
| 2765 | |||
| 2766 | /*! | ||
| 2767 | * @} | ||
| 2768 | */ /* end of group AOI_Peripheral_Access_Layer */ | ||
| 2769 | |||
| 2770 | |||
| 2771 | /* ---------------------------------------------------------------------------- | ||
| 2772 | -- BEE Peripheral Access Layer | ||
| 2773 | ---------------------------------------------------------------------------- */ | ||
| 2774 | |||
| 2775 | /*! | ||
| 2776 | * @addtogroup BEE_Peripheral_Access_Layer BEE Peripheral Access Layer | ||
| 2777 | * @{ | ||
| 2778 | */ | ||
| 2779 | |||
| 2780 | /** BEE - Register Layout Typedef */ | ||
| 2781 | typedef struct { | ||
| 2782 | __IO uint32_t CTRL; /**< Control Register, offset: 0x0 */ | ||
| 2783 | __IO uint32_t ADDR_OFFSET0; /**< Offset region 0 Register, offset: 0x4 */ | ||
| 2784 | __IO uint32_t ADDR_OFFSET1; /**< Offset region 1 Register, offset: 0x8 */ | ||
| 2785 | __O uint32_t AES_KEY0_W0; /**< AES Key 0 Register, offset: 0xC */ | ||
| 2786 | __O uint32_t AES_KEY0_W1; /**< AES Key 1 Register, offset: 0x10 */ | ||
| 2787 | __O uint32_t AES_KEY0_W2; /**< AES Key 2 Register, offset: 0x14 */ | ||
| 2788 | __O uint32_t AES_KEY0_W3; /**< AES Key 3 Register, offset: 0x18 */ | ||
| 2789 | __IO uint32_t STATUS; /**< Status Register, offset: 0x1C */ | ||
| 2790 | __O uint32_t CTR_NONCE0_W0; /**< NONCE00 Register, offset: 0x20 */ | ||
| 2791 | __O uint32_t CTR_NONCE0_W1; /**< NONCE01 Register, offset: 0x24 */ | ||
| 2792 | __O uint32_t CTR_NONCE0_W2; /**< NONCE02 Register, offset: 0x28 */ | ||
| 2793 | __O uint32_t CTR_NONCE0_W3; /**< NONCE03 Register, offset: 0x2C */ | ||
| 2794 | __O uint32_t CTR_NONCE1_W0; /**< NONCE10 Register, offset: 0x30 */ | ||
| 2795 | __O uint32_t CTR_NONCE1_W1; /**< NONCE11 Register, offset: 0x34 */ | ||
| 2796 | __O uint32_t CTR_NONCE1_W2; /**< NONCE12 Register, offset: 0x38 */ | ||
| 2797 | __O uint32_t CTR_NONCE1_W3; /**< NONCE13 Register, offset: 0x3C */ | ||
| 2798 | __IO uint32_t REGION1_TOP; /**< Region1 Top Address Register, offset: 0x40 */ | ||
| 2799 | __IO uint32_t REGION1_BOT; /**< Region1 Bottom Address Register, offset: 0x44 */ | ||
| 2800 | } BEE_Type; | ||
| 2801 | |||
| 2802 | /* ---------------------------------------------------------------------------- | ||
| 2803 | -- BEE Register Masks | ||
| 2804 | ---------------------------------------------------------------------------- */ | ||
| 2805 | |||
| 2806 | /*! | ||
| 2807 | * @addtogroup BEE_Register_Masks BEE Register Masks | ||
| 2808 | * @{ | ||
| 2809 | */ | ||
| 2810 | |||
| 2811 | /*! @name CTRL - Control Register */ | ||
| 2812 | /*! @{ */ | ||
| 2813 | #define BEE_CTRL_BEE_ENABLE_MASK (0x1U) | ||
| 2814 | #define BEE_CTRL_BEE_ENABLE_SHIFT (0U) | ||
| 2815 | /*! BEE_ENABLE | ||
| 2816 | * 0b0..Disable BEE | ||
| 2817 | * 0b1..Enable BEE | ||
| 2818 | */ | ||
| 2819 | #define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK) | ||
| 2820 | #define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U) | ||
| 2821 | #define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U) | ||
| 2822 | #define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK) | ||
| 2823 | #define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U) | ||
| 2824 | #define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U) | ||
| 2825 | #define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK) | ||
| 2826 | #define BEE_CTRL_KEY_VALID_MASK (0x10U) | ||
| 2827 | #define BEE_CTRL_KEY_VALID_SHIFT (4U) | ||
| 2828 | #define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK) | ||
| 2829 | #define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U) | ||
| 2830 | #define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U) | ||
| 2831 | /*! KEY_REGION_SEL | ||
| 2832 | * 0b0..Load AES key for region0 | ||
| 2833 | * 0b1..Load AES key for region1 | ||
| 2834 | */ | ||
| 2835 | #define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK) | ||
| 2836 | #define BEE_CTRL_AC_PROT_EN_MASK (0x40U) | ||
| 2837 | #define BEE_CTRL_AC_PROT_EN_SHIFT (6U) | ||
| 2838 | #define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK) | ||
| 2839 | #define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U) | ||
| 2840 | #define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U) | ||
| 2841 | /*! LITTLE_ENDIAN | ||
| 2842 | * 0b0..The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8, | ||
| 2843 | * B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to | ||
| 2844 | * Byte0 to Byte15. | ||
| 2845 | * 0b1..The input and output data of AES core is not swapped. | ||
| 2846 | */ | ||
| 2847 | #define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK) | ||
| 2848 | #define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U) | ||
| 2849 | #define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U) | ||
| 2850 | #define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK) | ||
| 2851 | #define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U) | ||
| 2852 | #define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U) | ||
| 2853 | /*! CTRL_AES_MODE_R0 | ||
| 2854 | * 0b0..ECB | ||
| 2855 | * 0b1..CTR | ||
| 2856 | */ | ||
| 2857 | #define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK) | ||
| 2858 | #define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U) | ||
| 2859 | #define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U) | ||
| 2860 | #define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK) | ||
| 2861 | #define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U) | ||
| 2862 | #define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U) | ||
| 2863 | /*! CTRL_AES_MODE_R1 | ||
| 2864 | * 0b0..ECB | ||
| 2865 | * 0b1..CTR | ||
| 2866 | */ | ||
| 2867 | #define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK) | ||
| 2868 | #define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U) | ||
| 2869 | #define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U) | ||
| 2870 | #define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK) | ||
| 2871 | #define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U) | ||
| 2872 | #define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U) | ||
| 2873 | #define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK) | ||
| 2874 | #define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U) | ||
| 2875 | #define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U) | ||
| 2876 | #define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK) | ||
| 2877 | #define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U) | ||
| 2878 | #define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U) | ||
| 2879 | #define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK) | ||
| 2880 | #define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U) | ||
| 2881 | #define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U) | ||
| 2882 | #define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK) | ||
| 2883 | #define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U) | ||
| 2884 | #define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U) | ||
| 2885 | #define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK) | ||
| 2886 | #define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U) | ||
| 2887 | #define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U) | ||
| 2888 | #define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK) | ||
| 2889 | #define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U) | ||
| 2890 | #define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U) | ||
| 2891 | #define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK) | ||
| 2892 | #define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U) | ||
| 2893 | #define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U) | ||
| 2894 | #define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK) | ||
| 2895 | #define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U) | ||
| 2896 | #define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U) | ||
| 2897 | #define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK) | ||
| 2898 | #define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U) | ||
| 2899 | #define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U) | ||
| 2900 | #define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK) | ||
| 2901 | #define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U) | ||
| 2902 | #define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U) | ||
| 2903 | #define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK) | ||
| 2904 | #define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U) | ||
| 2905 | #define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U) | ||
| 2906 | #define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK) | ||
| 2907 | #define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U) | ||
| 2908 | #define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U) | ||
| 2909 | #define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK) | ||
| 2910 | /*! @} */ | ||
| 2911 | |||
| 2912 | /*! @name ADDR_OFFSET0 - Offset region 0 Register */ | ||
| 2913 | /*! @{ */ | ||
| 2914 | #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU) | ||
| 2915 | #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U) | ||
| 2916 | #define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK) | ||
| 2917 | #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U) | ||
| 2918 | #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U) | ||
| 2919 | #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK) | ||
| 2920 | /*! @} */ | ||
| 2921 | |||
| 2922 | /*! @name ADDR_OFFSET1 - Offset region 1 Register */ | ||
| 2923 | /*! @{ */ | ||
| 2924 | #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU) | ||
| 2925 | #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U) | ||
| 2926 | #define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK) | ||
| 2927 | #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U) | ||
| 2928 | #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U) | ||
| 2929 | #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK) | ||
| 2930 | /*! @} */ | ||
| 2931 | |||
| 2932 | /*! @name AES_KEY0_W0 - AES Key 0 Register */ | ||
| 2933 | /*! @{ */ | ||
| 2934 | #define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU) | ||
| 2935 | #define BEE_AES_KEY0_W0_KEY0_SHIFT (0U) | ||
| 2936 | /*! KEY0 - AES 128 key from software | ||
| 2937 | */ | ||
| 2938 | #define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK) | ||
| 2939 | /*! @} */ | ||
| 2940 | |||
| 2941 | /*! @name AES_KEY0_W1 - AES Key 1 Register */ | ||
| 2942 | /*! @{ */ | ||
| 2943 | #define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU) | ||
| 2944 | #define BEE_AES_KEY0_W1_KEY1_SHIFT (0U) | ||
| 2945 | /*! KEY1 - AES 128 key from software | ||
| 2946 | */ | ||
| 2947 | #define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK) | ||
| 2948 | /*! @} */ | ||
| 2949 | |||
| 2950 | /*! @name AES_KEY0_W2 - AES Key 2 Register */ | ||
| 2951 | /*! @{ */ | ||
| 2952 | #define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU) | ||
| 2953 | #define BEE_AES_KEY0_W2_KEY2_SHIFT (0U) | ||
| 2954 | /*! KEY2 - AES 128 key from software | ||
| 2955 | */ | ||
| 2956 | #define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK) | ||
| 2957 | /*! @} */ | ||
| 2958 | |||
| 2959 | /*! @name AES_KEY0_W3 - AES Key 3 Register */ | ||
| 2960 | /*! @{ */ | ||
| 2961 | #define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU) | ||
| 2962 | #define BEE_AES_KEY0_W3_KEY3_SHIFT (0U) | ||
| 2963 | /*! KEY3 - AES 128 key from software | ||
| 2964 | */ | ||
| 2965 | #define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK) | ||
| 2966 | /*! @} */ | ||
| 2967 | |||
| 2968 | /*! @name STATUS - Status Register */ | ||
| 2969 | /*! @{ */ | ||
| 2970 | #define BEE_STATUS_IRQ_VEC_MASK (0xFFU) | ||
| 2971 | #define BEE_STATUS_IRQ_VEC_SHIFT (0U) | ||
| 2972 | #define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK) | ||
| 2973 | #define BEE_STATUS_BEE_IDLE_MASK (0x100U) | ||
| 2974 | #define BEE_STATUS_BEE_IDLE_SHIFT (8U) | ||
| 2975 | #define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK) | ||
| 2976 | /*! @} */ | ||
| 2977 | |||
| 2978 | /*! @name CTR_NONCE0_W0 - NONCE00 Register */ | ||
| 2979 | /*! @{ */ | ||
| 2980 | #define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU) | ||
| 2981 | #define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U) | ||
| 2982 | #define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK) | ||
| 2983 | /*! @} */ | ||
| 2984 | |||
| 2985 | /*! @name CTR_NONCE0_W1 - NONCE01 Register */ | ||
| 2986 | /*! @{ */ | ||
| 2987 | #define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU) | ||
| 2988 | #define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U) | ||
| 2989 | #define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK) | ||
| 2990 | /*! @} */ | ||
| 2991 | |||
| 2992 | /*! @name CTR_NONCE0_W2 - NONCE02 Register */ | ||
| 2993 | /*! @{ */ | ||
| 2994 | #define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU) | ||
| 2995 | #define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U) | ||
| 2996 | #define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK) | ||
| 2997 | /*! @} */ | ||
| 2998 | |||
| 2999 | /*! @name CTR_NONCE0_W3 - NONCE03 Register */ | ||
| 3000 | /*! @{ */ | ||
| 3001 | #define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU) | ||
| 3002 | #define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U) | ||
| 3003 | #define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK) | ||
| 3004 | /*! @} */ | ||
| 3005 | |||
| 3006 | /*! @name CTR_NONCE1_W0 - NONCE10 Register */ | ||
| 3007 | /*! @{ */ | ||
| 3008 | #define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU) | ||
| 3009 | #define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U) | ||
| 3010 | #define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK) | ||
| 3011 | /*! @} */ | ||
| 3012 | |||
| 3013 | /*! @name CTR_NONCE1_W1 - NONCE11 Register */ | ||
| 3014 | /*! @{ */ | ||
| 3015 | #define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU) | ||
| 3016 | #define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U) | ||
| 3017 | #define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK) | ||
| 3018 | /*! @} */ | ||
| 3019 | |||
| 3020 | /*! @name CTR_NONCE1_W2 - NONCE12 Register */ | ||
| 3021 | /*! @{ */ | ||
| 3022 | #define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU) | ||
| 3023 | #define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U) | ||
| 3024 | #define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK) | ||
| 3025 | /*! @} */ | ||
| 3026 | |||
| 3027 | /*! @name CTR_NONCE1_W3 - NONCE13 Register */ | ||
| 3028 | /*! @{ */ | ||
| 3029 | #define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU) | ||
| 3030 | #define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U) | ||
| 3031 | #define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK) | ||
| 3032 | /*! @} */ | ||
| 3033 | |||
| 3034 | /*! @name REGION1_TOP - Region1 Top Address Register */ | ||
| 3035 | /*! @{ */ | ||
| 3036 | #define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU) | ||
| 3037 | #define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U) | ||
| 3038 | /*! REGION1_TOP - Address upper limit of region1 | ||
| 3039 | */ | ||
| 3040 | #define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK) | ||
| 3041 | /*! @} */ | ||
| 3042 | |||
| 3043 | /*! @name REGION1_BOT - Region1 Bottom Address Register */ | ||
| 3044 | /*! @{ */ | ||
| 3045 | #define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU) | ||
| 3046 | #define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U) | ||
| 3047 | /*! REGION1_BOT - Address lower limit of region1 | ||
| 3048 | */ | ||
| 3049 | #define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK) | ||
| 3050 | /*! @} */ | ||
| 3051 | |||
| 3052 | |||
| 3053 | /*! | ||
| 3054 | * @} | ||
| 3055 | */ /* end of group BEE_Register_Masks */ | ||
| 3056 | |||
| 3057 | |||
| 3058 | /* BEE - Peripheral instance base addresses */ | ||
| 3059 | /** Peripheral BEE base address */ | ||
| 3060 | #define BEE_BASE (0x403EC000u) | ||
| 3061 | /** Peripheral BEE base pointer */ | ||
| 3062 | #define BEE ((BEE_Type *)BEE_BASE) | ||
| 3063 | /** Array initializer of BEE peripheral base addresses */ | ||
| 3064 | #define BEE_BASE_ADDRS { BEE_BASE } | ||
| 3065 | /** Array initializer of BEE peripheral base pointers */ | ||
| 3066 | #define BEE_BASE_PTRS { BEE } | ||
| 3067 | |||
| 3068 | /*! | ||
| 3069 | * @} | ||
| 3070 | */ /* end of group BEE_Peripheral_Access_Layer */ | ||
| 3071 | |||
| 3072 | |||
| 3073 | /* ---------------------------------------------------------------------------- | ||
| 3074 | -- CAN Peripheral Access Layer | ||
| 3075 | ---------------------------------------------------------------------------- */ | ||
| 3076 | |||
| 3077 | /*! | ||
| 3078 | * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer | ||
| 3079 | * @{ | ||
| 3080 | */ | ||
| 3081 | |||
| 3082 | /** CAN - Register Layout Typedef */ | ||
| 3083 | typedef struct { | ||
| 3084 | __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ | ||
| 3085 | __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ | ||
| 3086 | __IO uint32_t TIMER; /**< Free Running Timer Register, offset: 0x8 */ | ||
| 3087 | uint8_t RESERVED_0[4]; | ||
| 3088 | __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ | ||
| 3089 | __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register, offset: 0x14 */ | ||
| 3090 | __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register, offset: 0x18 */ | ||
| 3091 | __IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */ | ||
| 3092 | __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ | ||
| 3093 | __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ | ||
| 3094 | __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ | ||
| 3095 | __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */ | ||
| 3096 | __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ | ||
| 3097 | __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ | ||
| 3098 | __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ | ||
| 3099 | uint8_t RESERVED_1[8]; | ||
| 3100 | __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ | ||
| 3101 | __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */ | ||
| 3102 | __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ | ||
| 3103 | uint8_t RESERVED_2[8]; | ||
| 3104 | __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */ | ||
| 3105 | __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */ | ||
| 3106 | uint8_t RESERVED_3[32]; | ||
| 3107 | struct { /* offset: 0x80, array step: 0x10 */ | ||
| 3108 | __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ | ||
| 3109 | __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ | ||
| 3110 | __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ | ||
| 3111 | __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ | ||
| 3112 | } MB[64]; | ||
| 3113 | uint8_t RESERVED_4[1024]; | ||
| 3114 | __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ | ||
| 3115 | uint8_t RESERVED_5[96]; | ||
| 3116 | __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */ | ||
| 3117 | } CAN_Type; | ||
| 3118 | |||
| 3119 | /* ---------------------------------------------------------------------------- | ||
| 3120 | -- CAN Register Masks | ||
| 3121 | ---------------------------------------------------------------------------- */ | ||
| 3122 | |||
| 3123 | /*! | ||
| 3124 | * @addtogroup CAN_Register_Masks CAN Register Masks | ||
| 3125 | * @{ | ||
| 3126 | */ | ||
| 3127 | |||
| 3128 | /*! @name MCR - Module Configuration Register */ | ||
| 3129 | /*! @{ */ | ||
| 3130 | #define CAN_MCR_MAXMB_MASK (0x7FU) | ||
| 3131 | #define CAN_MCR_MAXMB_SHIFT (0U) | ||
| 3132 | #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) | ||
| 3133 | #define CAN_MCR_IDAM_MASK (0x300U) | ||
| 3134 | #define CAN_MCR_IDAM_SHIFT (8U) | ||
| 3135 | /*! IDAM | ||
| 3136 | * 0b00..Format A One full ID (standard or extended) per ID filter Table element. | ||
| 3137 | * 0b01..Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element. | ||
| 3138 | * 0b10..Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element. | ||
| 3139 | * 0b11..Format D All frames rejected. | ||
| 3140 | */ | ||
| 3141 | #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) | ||
| 3142 | #define CAN_MCR_AEN_MASK (0x1000U) | ||
| 3143 | #define CAN_MCR_AEN_SHIFT (12U) | ||
| 3144 | /*! AEN | ||
| 3145 | * 0b1..Abort enabled | ||
| 3146 | * 0b0..Abort disabled | ||
| 3147 | */ | ||
| 3148 | #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) | ||
| 3149 | #define CAN_MCR_LPRIOEN_MASK (0x2000U) | ||
| 3150 | #define CAN_MCR_LPRIOEN_SHIFT (13U) | ||
| 3151 | /*! LPRIOEN | ||
| 3152 | * 0b1..Local Priority enabled | ||
| 3153 | * 0b0..Local Priority disabled | ||
| 3154 | */ | ||
| 3155 | #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) | ||
| 3156 | #define CAN_MCR_IRMQ_MASK (0x10000U) | ||
| 3157 | #define CAN_MCR_IRMQ_SHIFT (16U) | ||
| 3158 | /*! IRMQ | ||
| 3159 | * 0b1..Individual Rx masking and queue feature are enabled. | ||
| 3160 | * 0b0..Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY. | ||
| 3161 | */ | ||
| 3162 | #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) | ||
| 3163 | #define CAN_MCR_SRXDIS_MASK (0x20000U) | ||
| 3164 | #define CAN_MCR_SRXDIS_SHIFT (17U) | ||
| 3165 | /*! SRXDIS | ||
| 3166 | * 0b1..Self reception disabled | ||
| 3167 | * 0b0..Self reception enabled | ||
| 3168 | */ | ||
| 3169 | #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) | ||
| 3170 | #define CAN_MCR_WAKSRC_MASK (0x80000U) | ||
| 3171 | #define CAN_MCR_WAKSRC_SHIFT (19U) | ||
| 3172 | /*! WAKSRC | ||
| 3173 | * 0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus | ||
| 3174 | * 0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus. | ||
| 3175 | */ | ||
| 3176 | #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) | ||
| 3177 | #define CAN_MCR_LPMACK_MASK (0x100000U) | ||
| 3178 | #define CAN_MCR_LPMACK_SHIFT (20U) | ||
| 3179 | /*! LPMACK | ||
| 3180 | * 0b1..FLEXCAN is either in Disable Mode, or Stop mode | ||
| 3181 | * 0b0..FLEXCAN not in any of the low power modes | ||
| 3182 | */ | ||
| 3183 | #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) | ||
| 3184 | #define CAN_MCR_WRNEN_MASK (0x200000U) | ||
| 3185 | #define CAN_MCR_WRNEN_SHIFT (21U) | ||
| 3186 | /*! WRNEN | ||
| 3187 | * 0b1..TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96. | ||
| 3188 | * 0b0..TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters. | ||
| 3189 | */ | ||
| 3190 | #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) | ||
| 3191 | #define CAN_MCR_SLFWAK_MASK (0x400000U) | ||
| 3192 | #define CAN_MCR_SLFWAK_SHIFT (22U) | ||
| 3193 | /*! SLFWAK | ||
| 3194 | * 0b1..FLEXCAN Self Wake Up feature is enabled | ||
| 3195 | * 0b0..FLEXCAN Self Wake Up feature is disabled | ||
| 3196 | */ | ||
| 3197 | #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) | ||
| 3198 | #define CAN_MCR_SUPV_MASK (0x800000U) | ||
| 3199 | #define CAN_MCR_SUPV_SHIFT (23U) | ||
| 3200 | /*! SUPV | ||
| 3201 | * 0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access | ||
| 3202 | * behaves as though the access was done to an unimplemented register location | ||
| 3203 | * 0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses | ||
| 3204 | */ | ||
| 3205 | #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) | ||
| 3206 | #define CAN_MCR_FRZACK_MASK (0x1000000U) | ||
| 3207 | #define CAN_MCR_FRZACK_SHIFT (24U) | ||
| 3208 | /*! FRZACK | ||
| 3209 | * 0b1..FLEXCAN in Freeze Mode, prescaler stopped | ||
| 3210 | * 0b0..FLEXCAN not in Freeze Mode, prescaler running | ||
| 3211 | */ | ||
| 3212 | #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) | ||
| 3213 | #define CAN_MCR_SOFTRST_MASK (0x2000000U) | ||
| 3214 | #define CAN_MCR_SOFTRST_SHIFT (25U) | ||
| 3215 | /*! SOFTRST | ||
| 3216 | * 0b1..Reset the registers | ||
| 3217 | * 0b0..No reset request | ||
| 3218 | */ | ||
| 3219 | #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) | ||
| 3220 | #define CAN_MCR_WAKMSK_MASK (0x4000000U) | ||
| 3221 | #define CAN_MCR_WAKMSK_SHIFT (26U) | ||
| 3222 | /*! WAKMSK | ||
| 3223 | * 0b1..Wake Up Interrupt is enabled | ||
| 3224 | * 0b0..Wake Up Interrupt is disabled | ||
| 3225 | */ | ||
| 3226 | #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) | ||
| 3227 | #define CAN_MCR_NOTRDY_MASK (0x8000000U) | ||
| 3228 | #define CAN_MCR_NOTRDY_SHIFT (27U) | ||
| 3229 | /*! NOTRDY | ||
| 3230 | * 0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode | ||
| 3231 | * 0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode | ||
| 3232 | */ | ||
| 3233 | #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) | ||
| 3234 | #define CAN_MCR_HALT_MASK (0x10000000U) | ||
| 3235 | #define CAN_MCR_HALT_SHIFT (28U) | ||
| 3236 | /*! HALT | ||
| 3237 | * 0b1..Enters Freeze Mode if the FRZ bit is asserted. | ||
| 3238 | * 0b0..No Freeze Mode request. | ||
| 3239 | */ | ||
| 3240 | #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) | ||
| 3241 | #define CAN_MCR_RFEN_MASK (0x20000000U) | ||
| 3242 | #define CAN_MCR_RFEN_SHIFT (29U) | ||
| 3243 | /*! RFEN | ||
| 3244 | * 0b1..FIFO enabled | ||
| 3245 | * 0b0..FIFO not enabled | ||
| 3246 | */ | ||
| 3247 | #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) | ||
| 3248 | #define CAN_MCR_FRZ_MASK (0x40000000U) | ||
| 3249 | #define CAN_MCR_FRZ_SHIFT (30U) | ||
| 3250 | /*! FRZ | ||
| 3251 | * 0b1..Enabled to enter Freeze Mode | ||
| 3252 | * 0b0..Not enabled to enter Freeze Mode | ||
| 3253 | */ | ||
| 3254 | #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) | ||
| 3255 | #define CAN_MCR_MDIS_MASK (0x80000000U) | ||
| 3256 | #define CAN_MCR_MDIS_SHIFT (31U) | ||
| 3257 | /*! MDIS | ||
| 3258 | * 0b1..Disable the FLEXCAN module | ||
| 3259 | * 0b0..Enable the FLEXCAN module | ||
| 3260 | */ | ||
| 3261 | #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) | ||
| 3262 | /*! @} */ | ||
| 3263 | |||
| 3264 | /*! @name CTRL1 - Control 1 Register */ | ||
| 3265 | /*! @{ */ | ||
| 3266 | #define CAN_CTRL1_PROPSEG_MASK (0x7U) | ||
| 3267 | #define CAN_CTRL1_PROPSEG_SHIFT (0U) | ||
| 3268 | #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) | ||
| 3269 | #define CAN_CTRL1_LOM_MASK (0x8U) | ||
| 3270 | #define CAN_CTRL1_LOM_SHIFT (3U) | ||
| 3271 | /*! LOM | ||
| 3272 | * 0b1..FLEXCAN module operates in Listen Only Mode | ||
| 3273 | * 0b0..Listen Only Mode is deactivated | ||
| 3274 | */ | ||
| 3275 | #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) | ||
| 3276 | #define CAN_CTRL1_LBUF_MASK (0x10U) | ||
| 3277 | #define CAN_CTRL1_LBUF_SHIFT (4U) | ||
| 3278 | /*! LBUF | ||
| 3279 | * 0b1..Lowest number buffer is transmitted first | ||
| 3280 | * 0b0..Buffer with highest priority is transmitted first | ||
| 3281 | */ | ||
| 3282 | #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) | ||
| 3283 | #define CAN_CTRL1_TSYN_MASK (0x20U) | ||
| 3284 | #define CAN_CTRL1_TSYN_SHIFT (5U) | ||
| 3285 | /*! TSYN | ||
| 3286 | * 0b1..Timer Sync feature enabled | ||
| 3287 | * 0b0..Timer Sync feature disabled | ||
| 3288 | */ | ||
| 3289 | #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) | ||
| 3290 | #define CAN_CTRL1_BOFFREC_MASK (0x40U) | ||
| 3291 | #define CAN_CTRL1_BOFFREC_SHIFT (6U) | ||
| 3292 | /*! BOFFREC | ||
| 3293 | * 0b1..Automatic recovering from Bus Off state disabled | ||
| 3294 | * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B | ||
| 3295 | */ | ||
| 3296 | #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) | ||
| 3297 | #define CAN_CTRL1_SMP_MASK (0x80U) | ||
| 3298 | #define CAN_CTRL1_SMP_SHIFT (7U) | ||
| 3299 | /*! SMP | ||
| 3300 | * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 | ||
| 3301 | * preceding samples, a majority rule is used | ||
| 3302 | * 0b0..Just one sample is used to determine the bit value | ||
| 3303 | */ | ||
| 3304 | #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) | ||
| 3305 | #define CAN_CTRL1_RWRNMSK_MASK (0x400U) | ||
| 3306 | #define CAN_CTRL1_RWRNMSK_SHIFT (10U) | ||
| 3307 | /*! RWRNMSK | ||
| 3308 | * 0b1..Rx Warning Interrupt enabled | ||
| 3309 | * 0b0..Rx Warning Interrupt disabled | ||
| 3310 | */ | ||
| 3311 | #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) | ||
| 3312 | #define CAN_CTRL1_TWRNMSK_MASK (0x800U) | ||
| 3313 | #define CAN_CTRL1_TWRNMSK_SHIFT (11U) | ||
| 3314 | /*! TWRNMSK | ||
| 3315 | * 0b1..Tx Warning Interrupt enabled | ||
| 3316 | * 0b0..Tx Warning Interrupt disabled | ||
| 3317 | */ | ||
| 3318 | #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) | ||
| 3319 | #define CAN_CTRL1_LPB_MASK (0x1000U) | ||
| 3320 | #define CAN_CTRL1_LPB_SHIFT (12U) | ||
| 3321 | /*! LPB | ||
| 3322 | * 0b1..Loop Back enabled | ||
| 3323 | * 0b0..Loop Back disabled | ||
| 3324 | */ | ||
| 3325 | #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) | ||
| 3326 | #define CAN_CTRL1_ERRMSK_MASK (0x4000U) | ||
| 3327 | #define CAN_CTRL1_ERRMSK_SHIFT (14U) | ||
| 3328 | /*! ERRMSK | ||
| 3329 | * 0b1..Error interrupt enabled | ||
| 3330 | * 0b0..Error interrupt disabled | ||
| 3331 | */ | ||
| 3332 | #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) | ||
| 3333 | #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) | ||
| 3334 | #define CAN_CTRL1_BOFFMSK_SHIFT (15U) | ||
| 3335 | /*! BOFFMSK | ||
| 3336 | * 0b1..Bus Off interrupt enabled | ||
| 3337 | * 0b0..Bus Off interrupt disabled | ||
| 3338 | */ | ||
| 3339 | #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) | ||
| 3340 | #define CAN_CTRL1_PSEG2_MASK (0x70000U) | ||
| 3341 | #define CAN_CTRL1_PSEG2_SHIFT (16U) | ||
| 3342 | #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) | ||
| 3343 | #define CAN_CTRL1_PSEG1_MASK (0x380000U) | ||
| 3344 | #define CAN_CTRL1_PSEG1_SHIFT (19U) | ||
| 3345 | #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) | ||
| 3346 | #define CAN_CTRL1_RJW_MASK (0xC00000U) | ||
| 3347 | #define CAN_CTRL1_RJW_SHIFT (22U) | ||
| 3348 | #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) | ||
| 3349 | #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) | ||
| 3350 | #define CAN_CTRL1_PRESDIV_SHIFT (24U) | ||
| 3351 | #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) | ||
| 3352 | /*! @} */ | ||
| 3353 | |||
| 3354 | /*! @name TIMER - Free Running Timer Register */ | ||
| 3355 | /*! @{ */ | ||
| 3356 | #define CAN_TIMER_TIMER_MASK (0xFFFFU) | ||
| 3357 | #define CAN_TIMER_TIMER_SHIFT (0U) | ||
| 3358 | #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) | ||
| 3359 | /*! @} */ | ||
| 3360 | |||
| 3361 | /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ | ||
| 3362 | /*! @{ */ | ||
| 3363 | #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) | ||
| 3364 | #define CAN_RXMGMASK_MG_SHIFT (0U) | ||
| 3365 | /*! MG | ||
| 3366 | * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received | ||
| 3367 | * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" | ||
| 3368 | */ | ||
| 3369 | #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) | ||
| 3370 | /*! @} */ | ||
| 3371 | |||
| 3372 | /*! @name RX14MASK - Rx Buffer 14 Mask Register */ | ||
| 3373 | /*! @{ */ | ||
| 3374 | #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) | ||
| 3375 | #define CAN_RX14MASK_RX14M_SHIFT (0U) | ||
| 3376 | /*! RX14M | ||
| 3377 | * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked | ||
| 3378 | * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" | ||
| 3379 | */ | ||
| 3380 | #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) | ||
| 3381 | /*! @} */ | ||
| 3382 | |||
| 3383 | /*! @name RX15MASK - Rx Buffer 15 Mask Register */ | ||
| 3384 | /*! @{ */ | ||
| 3385 | #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) | ||
| 3386 | #define CAN_RX15MASK_RX15M_SHIFT (0U) | ||
| 3387 | /*! RX15M | ||
| 3388 | * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked | ||
| 3389 | * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" | ||
| 3390 | */ | ||
| 3391 | #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) | ||
| 3392 | /*! @} */ | ||
| 3393 | |||
| 3394 | /*! @name ECR - Error Counter Register */ | ||
| 3395 | /*! @{ */ | ||
| 3396 | #define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU) | ||
| 3397 | #define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U) | ||
| 3398 | #define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK) | ||
| 3399 | #define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U) | ||
| 3400 | #define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U) | ||
| 3401 | #define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK) | ||
| 3402 | /*! @} */ | ||
| 3403 | |||
| 3404 | /*! @name ESR1 - Error and Status 1 Register */ | ||
| 3405 | /*! @{ */ | ||
| 3406 | #define CAN_ESR1_WAKINT_MASK (0x1U) | ||
| 3407 | #define CAN_ESR1_WAKINT_SHIFT (0U) | ||
| 3408 | /*! WAKINT | ||
| 3409 | * 0b1..Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode | ||
| 3410 | * 0b0..No such occurrence | ||
| 3411 | */ | ||
| 3412 | #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) | ||
| 3413 | #define CAN_ESR1_ERRINT_MASK (0x2U) | ||
| 3414 | #define CAN_ESR1_ERRINT_SHIFT (1U) | ||
| 3415 | /*! ERRINT | ||
| 3416 | * 0b1..Indicates setting of any Error Bit in the Error and Status Register | ||
| 3417 | * 0b0..No such occurrence | ||
| 3418 | */ | ||
| 3419 | #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) | ||
| 3420 | #define CAN_ESR1_BOFFINT_MASK (0x4U) | ||
| 3421 | #define CAN_ESR1_BOFFINT_SHIFT (2U) | ||
| 3422 | /*! BOFFINT | ||
| 3423 | * 0b1..FLEXCAN module entered 'Bus Off' state | ||
| 3424 | * 0b0..No such occurrence | ||
| 3425 | */ | ||
| 3426 | #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) | ||
| 3427 | #define CAN_ESR1_RX_MASK (0x8U) | ||
| 3428 | #define CAN_ESR1_RX_SHIFT (3U) | ||
| 3429 | /*! RX | ||
| 3430 | * 0b1..FLEXCAN is transmitting a message | ||
| 3431 | * 0b0..FLEXCAN is receiving a message | ||
| 3432 | */ | ||
| 3433 | #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) | ||
| 3434 | #define CAN_ESR1_FLTCONF_MASK (0x30U) | ||
| 3435 | #define CAN_ESR1_FLTCONF_SHIFT (4U) | ||
| 3436 | /*! FLTCONF | ||
| 3437 | * 0b00..Error Active | ||
| 3438 | * 0b01..Error Passive | ||
| 3439 | * 0b1x..Bus off | ||
| 3440 | */ | ||
| 3441 | #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) | ||
| 3442 | #define CAN_ESR1_TX_MASK (0x40U) | ||
| 3443 | #define CAN_ESR1_TX_SHIFT (6U) | ||
| 3444 | /*! TX | ||
| 3445 | * 0b1..FLEXCAN is transmitting a message | ||
| 3446 | * 0b0..FLEXCAN is receiving a message | ||
| 3447 | */ | ||
| 3448 | #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) | ||
| 3449 | #define CAN_ESR1_IDLE_MASK (0x80U) | ||
| 3450 | #define CAN_ESR1_IDLE_SHIFT (7U) | ||
| 3451 | /*! IDLE | ||
| 3452 | * 0b1..CAN bus is now IDLE | ||
| 3453 | * 0b0..No such occurrence | ||
| 3454 | */ | ||
| 3455 | #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) | ||
| 3456 | #define CAN_ESR1_RXWRN_MASK (0x100U) | ||
| 3457 | #define CAN_ESR1_RXWRN_SHIFT (8U) | ||
| 3458 | /*! RXWRN | ||
| 3459 | * 0b1..Rx_Err_Counter >= 96 | ||
| 3460 | * 0b0..No such occurrence | ||
| 3461 | */ | ||
| 3462 | #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) | ||
| 3463 | #define CAN_ESR1_TXWRN_MASK (0x200U) | ||
| 3464 | #define CAN_ESR1_TXWRN_SHIFT (9U) | ||
| 3465 | /*! TXWRN | ||
| 3466 | * 0b1..TX_Err_Counter >= 96 | ||
| 3467 | * 0b0..No such occurrence | ||
| 3468 | */ | ||
| 3469 | #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) | ||
| 3470 | #define CAN_ESR1_STFERR_MASK (0x400U) | ||
| 3471 | #define CAN_ESR1_STFERR_SHIFT (10U) | ||
| 3472 | /*! STFERR | ||
| 3473 | * 0b1..A Stuffing Error occurred since last read of this register. | ||
| 3474 | * 0b0..No such occurrence. | ||
| 3475 | */ | ||
| 3476 | #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) | ||
| 3477 | #define CAN_ESR1_FRMERR_MASK (0x800U) | ||
| 3478 | #define CAN_ESR1_FRMERR_SHIFT (11U) | ||
| 3479 | /*! FRMERR | ||
| 3480 | * 0b1..A Form Error occurred since last read of this register | ||
| 3481 | * 0b0..No such occurrence | ||
| 3482 | */ | ||
| 3483 | #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) | ||
| 3484 | #define CAN_ESR1_CRCERR_MASK (0x1000U) | ||
| 3485 | #define CAN_ESR1_CRCERR_SHIFT (12U) | ||
| 3486 | /*! CRCERR | ||
| 3487 | * 0b1..A CRC error occurred since last read of this register. | ||
| 3488 | * 0b0..No such occurrence | ||
| 3489 | */ | ||
| 3490 | #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) | ||
| 3491 | #define CAN_ESR1_ACKERR_MASK (0x2000U) | ||
| 3492 | #define CAN_ESR1_ACKERR_SHIFT (13U) | ||
| 3493 | /*! ACKERR | ||
| 3494 | * 0b1..An ACK error occurred since last read of this register | ||
| 3495 | * 0b0..No such occurrence | ||
| 3496 | */ | ||
| 3497 | #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) | ||
| 3498 | #define CAN_ESR1_BIT0ERR_MASK (0x4000U) | ||
| 3499 | #define CAN_ESR1_BIT0ERR_SHIFT (14U) | ||
| 3500 | /*! BIT0ERR | ||
| 3501 | * 0b1..At least one bit sent as dominant is received as recessive | ||
| 3502 | * 0b0..No such occurrence | ||
| 3503 | */ | ||
| 3504 | #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) | ||
| 3505 | #define CAN_ESR1_BIT1ERR_MASK (0x8000U) | ||
| 3506 | #define CAN_ESR1_BIT1ERR_SHIFT (15U) | ||
| 3507 | /*! BIT1ERR | ||
| 3508 | * 0b1..At least one bit sent as recessive is received as dominant | ||
| 3509 | * 0b0..No such occurrence | ||
| 3510 | */ | ||
| 3511 | #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) | ||
| 3512 | #define CAN_ESR1_RWRNINT_MASK (0x10000U) | ||
| 3513 | #define CAN_ESR1_RWRNINT_SHIFT (16U) | ||
| 3514 | /*! RWRNINT | ||
| 3515 | * 0b1..The Rx error counter transition from < 96 to >= 96 | ||
| 3516 | * 0b0..No such occurrence | ||
| 3517 | */ | ||
| 3518 | #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) | ||
| 3519 | #define CAN_ESR1_TWRNINT_MASK (0x20000U) | ||
| 3520 | #define CAN_ESR1_TWRNINT_SHIFT (17U) | ||
| 3521 | /*! TWRNINT | ||
| 3522 | * 0b1..The Tx error counter transition from < 96 to >= 96 | ||
| 3523 | * 0b0..No such occurrence | ||
| 3524 | */ | ||
| 3525 | #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) | ||
| 3526 | #define CAN_ESR1_SYNCH_MASK (0x40000U) | ||
| 3527 | #define CAN_ESR1_SYNCH_SHIFT (18U) | ||
| 3528 | /*! SYNCH | ||
| 3529 | * 0b1..FlexCAN is synchronized to the CAN bus | ||
| 3530 | * 0b0..FlexCAN is not synchronized to the CAN bus | ||
| 3531 | */ | ||
| 3532 | #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) | ||
| 3533 | /*! @} */ | ||
| 3534 | |||
| 3535 | /*! @name IMASK2 - Interrupt Masks 2 Register */ | ||
| 3536 | /*! @{ */ | ||
| 3537 | #define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU) | ||
| 3538 | #define CAN_IMASK2_BUFHM_SHIFT (0U) | ||
| 3539 | /*! BUFHM | ||
| 3540 | * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled | ||
| 3541 | * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled | ||
| 3542 | */ | ||
| 3543 | #define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK) | ||
| 3544 | /*! @} */ | ||
| 3545 | |||
| 3546 | /*! @name IMASK1 - Interrupt Masks 1 Register */ | ||
| 3547 | /*! @{ */ | ||
| 3548 | #define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) | ||
| 3549 | #define CAN_IMASK1_BUFLM_SHIFT (0U) | ||
| 3550 | /*! BUFLM | ||
| 3551 | * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled | ||
| 3552 | * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled | ||
| 3553 | */ | ||
| 3554 | #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) | ||
| 3555 | /*! @} */ | ||
| 3556 | |||
| 3557 | /*! @name IFLAG2 - Interrupt Flags 2 Register */ | ||
| 3558 | /*! @{ */ | ||
| 3559 | #define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU) | ||
| 3560 | #define CAN_IFLAG2_BUFHI_SHIFT (0U) | ||
| 3561 | /*! BUFHI | ||
| 3562 | * 0b00000000000000000000000000000001..The corresponding buffer has successfully completed transmission or reception | ||
| 3563 | * 0b00000000000000000000000000000000..No such occurrence | ||
| 3564 | */ | ||
| 3565 | #define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK) | ||
| 3566 | /*! @} */ | ||
| 3567 | |||
| 3568 | /*! @name IFLAG1 - Interrupt Flags 1 Register */ | ||
| 3569 | /*! @{ */ | ||
| 3570 | #define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU) | ||
| 3571 | #define CAN_IFLAG1_BUF4TO0I_SHIFT (0U) | ||
| 3572 | /*! BUF4TO0I | ||
| 3573 | * 0b00001..Corresponding MB completed transmission/reception | ||
| 3574 | * 0b00000..No such occurrence | ||
| 3575 | */ | ||
| 3576 | #define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK) | ||
| 3577 | #define CAN_IFLAG1_BUF5I_MASK (0x20U) | ||
| 3578 | #define CAN_IFLAG1_BUF5I_SHIFT (5U) | ||
| 3579 | /*! BUF5I | ||
| 3580 | * 0b1..MB5 completed transmission/reception or frames available in the FIFO | ||
| 3581 | * 0b0..No such occurrence | ||
| 3582 | */ | ||
| 3583 | #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) | ||
| 3584 | #define CAN_IFLAG1_BUF6I_MASK (0x40U) | ||
| 3585 | #define CAN_IFLAG1_BUF6I_SHIFT (6U) | ||
| 3586 | /*! BUF6I | ||
| 3587 | * 0b1..MB6 completed transmission/reception or FIFO almost full | ||
| 3588 | * 0b0..No such occurrence | ||
| 3589 | */ | ||
| 3590 | #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) | ||
| 3591 | #define CAN_IFLAG1_BUF7I_MASK (0x80U) | ||
| 3592 | #define CAN_IFLAG1_BUF7I_SHIFT (7U) | ||
| 3593 | /*! BUF7I | ||
| 3594 | * 0b1..MB7 completed transmission/reception or FIFO overflow | ||
| 3595 | * 0b0..No such occurrence | ||
| 3596 | */ | ||
| 3597 | #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) | ||
| 3598 | #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) | ||
| 3599 | #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) | ||
| 3600 | /*! BUF31TO8I | ||
| 3601 | * 0b000000000000000000000001..The corresponding MB has successfully completed transmission or reception | ||
| 3602 | * 0b000000000000000000000000..No such occurrence | ||
| 3603 | */ | ||
| 3604 | #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) | ||
| 3605 | /*! @} */ | ||
| 3606 | |||
| 3607 | /*! @name CTRL2 - Control 2 Register */ | ||
| 3608 | /*! @{ */ | ||
| 3609 | #define CAN_CTRL2_EACEN_MASK (0x10000U) | ||
| 3610 | #define CAN_CTRL2_EACEN_SHIFT (16U) | ||
| 3611 | /*! EACEN | ||
| 3612 | * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within | ||
| 3613 | * the incoming frame. Mask bits do apply. | ||
| 3614 | * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. | ||
| 3615 | */ | ||
| 3616 | #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) | ||
| 3617 | #define CAN_CTRL2_RRS_MASK (0x20000U) | ||
| 3618 | #define CAN_CTRL2_RRS_SHIFT (17U) | ||
| 3619 | /*! RRS | ||
| 3620 | * 0b1..Remote Request Frame is stored | ||
| 3621 | * 0b0..Remote Response Frame is generated | ||
| 3622 | */ | ||
| 3623 | #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) | ||
| 3624 | #define CAN_CTRL2_MRP_MASK (0x40000U) | ||
| 3625 | #define CAN_CTRL2_MRP_SHIFT (18U) | ||
| 3626 | /*! MRP | ||
| 3627 | * 0b1..Matching starts from Mailboxes and continues on Rx FIFO | ||
| 3628 | * 0b0..Matching starts from Rx FIFO and continues on Mailboxes | ||
| 3629 | */ | ||
| 3630 | #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) | ||
| 3631 | #define CAN_CTRL2_TASD_MASK (0xF80000U) | ||
| 3632 | #define CAN_CTRL2_TASD_SHIFT (19U) | ||
| 3633 | #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) | ||
| 3634 | #define CAN_CTRL2_RFFN_MASK (0xF000000U) | ||
| 3635 | #define CAN_CTRL2_RFFN_SHIFT (24U) | ||
| 3636 | #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) | ||
| 3637 | #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) | ||
| 3638 | #define CAN_CTRL2_WRMFRZ_SHIFT (28U) | ||
| 3639 | /*! WRMFRZ | ||
| 3640 | * 0b1..Enable unrestricted write access to FlexCAN memory | ||
| 3641 | * 0b0..Keep the write access restricted in some regions of FlexCAN memory | ||
| 3642 | */ | ||
| 3643 | #define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) | ||
| 3644 | /*! @} */ | ||
| 3645 | |||
| 3646 | /*! @name ESR2 - Error and Status 2 Register */ | ||
| 3647 | /*! @{ */ | ||
| 3648 | #define CAN_ESR2_IMB_MASK (0x2000U) | ||
| 3649 | #define CAN_ESR2_IMB_SHIFT (13U) | ||
| 3650 | /*! IMB | ||
| 3651 | * 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. | ||
| 3652 | * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. | ||
| 3653 | */ | ||
| 3654 | #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) | ||
| 3655 | #define CAN_ESR2_VPS_MASK (0x4000U) | ||
| 3656 | #define CAN_ESR2_VPS_SHIFT (14U) | ||
| 3657 | /*! VPS | ||
| 3658 | * 0b1..Contents of IMB and LPTM are valid | ||
| 3659 | * 0b0..Contents of IMB and LPTM are invalid | ||
| 3660 | */ | ||
| 3661 | #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) | ||
| 3662 | #define CAN_ESR2_LPTM_MASK (0x7F0000U) | ||
| 3663 | #define CAN_ESR2_LPTM_SHIFT (16U) | ||
| 3664 | #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) | ||
| 3665 | /*! @} */ | ||
| 3666 | |||
| 3667 | /*! @name CRCR - CRC Register */ | ||
| 3668 | /*! @{ */ | ||
| 3669 | #define CAN_CRCR_TXCRC_MASK (0x7FFFU) | ||
| 3670 | #define CAN_CRCR_TXCRC_SHIFT (0U) | ||
| 3671 | #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) | ||
| 3672 | #define CAN_CRCR_MBCRC_MASK (0x7F0000U) | ||
| 3673 | #define CAN_CRCR_MBCRC_SHIFT (16U) | ||
| 3674 | #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) | ||
| 3675 | /*! @} */ | ||
| 3676 | |||
| 3677 | /*! @name RXFGMASK - Rx FIFO Global Mask Register */ | ||
| 3678 | /*! @{ */ | ||
| 3679 | #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) | ||
| 3680 | #define CAN_RXFGMASK_FGM_SHIFT (0U) | ||
| 3681 | /*! FGM | ||
| 3682 | * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked | ||
| 3683 | * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care" | ||
| 3684 | */ | ||
| 3685 | #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) | ||
| 3686 | /*! @} */ | ||
| 3687 | |||
| 3688 | /*! @name RXFIR - Rx FIFO Information Register */ | ||
| 3689 | /*! @{ */ | ||
| 3690 | #define CAN_RXFIR_IDHIT_MASK (0x1FFU) | ||
| 3691 | #define CAN_RXFIR_IDHIT_SHIFT (0U) | ||
| 3692 | #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) | ||
| 3693 | /*! @} */ | ||
| 3694 | |||
| 3695 | /*! @name DBG1 - Debug 1 register */ | ||
| 3696 | /*! @{ */ | ||
| 3697 | #define CAN_DBG1_CFSM_MASK (0x3FU) | ||
| 3698 | #define CAN_DBG1_CFSM_SHIFT (0U) | ||
| 3699 | /*! CFSM - CAN Finite State Machine | ||
| 3700 | */ | ||
| 3701 | #define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK) | ||
| 3702 | #define CAN_DBG1_CBN_MASK (0x1F000000U) | ||
| 3703 | #define CAN_DBG1_CBN_SHIFT (24U) | ||
| 3704 | /*! CBN - CAN Bit Number | ||
| 3705 | */ | ||
| 3706 | #define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK) | ||
| 3707 | /*! @} */ | ||
| 3708 | |||
| 3709 | /*! @name DBG2 - Debug 2 register */ | ||
| 3710 | /*! @{ */ | ||
| 3711 | #define CAN_DBG2_RMP_MASK (0x7FU) | ||
| 3712 | #define CAN_DBG2_RMP_SHIFT (0U) | ||
| 3713 | /*! RMP - Rx Matching Pointer | ||
| 3714 | */ | ||
| 3715 | #define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK) | ||
| 3716 | #define CAN_DBG2_MPP_MASK (0x80U) | ||
| 3717 | #define CAN_DBG2_MPP_SHIFT (7U) | ||
| 3718 | /*! MPP - Matching Process in Progress | ||
| 3719 | * 0b0..No matching process ongoing. | ||
| 3720 | * 0b1..Matching process is in progress. | ||
| 3721 | */ | ||
| 3722 | #define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK) | ||
| 3723 | #define CAN_DBG2_TAP_MASK (0x7F00U) | ||
| 3724 | #define CAN_DBG2_TAP_SHIFT (8U) | ||
| 3725 | /*! TAP - Tx Arbitration Pointer | ||
| 3726 | */ | ||
| 3727 | #define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK) | ||
| 3728 | #define CAN_DBG2_APP_MASK (0x8000U) | ||
| 3729 | #define CAN_DBG2_APP_SHIFT (15U) | ||
| 3730 | /*! APP - Arbitration Process in Progress | ||
| 3731 | * 0b0..No matching process ongoing. | ||
| 3732 | * 0b1..Matching process is in progress. | ||
| 3733 | */ | ||
| 3734 | #define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK) | ||
| 3735 | /*! @} */ | ||
| 3736 | |||
| 3737 | /*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */ | ||
| 3738 | /*! @{ */ | ||
| 3739 | #define CAN_CS_TIME_STAMP_MASK (0xFFFFU) | ||
| 3740 | #define CAN_CS_TIME_STAMP_SHIFT (0U) | ||
| 3741 | /*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running | ||
| 3742 | * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field | ||
| 3743 | * appears on the CAN bus. | ||
| 3744 | */ | ||
| 3745 | #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) | ||
| 3746 | #define CAN_CS_DLC_MASK (0xF0000U) | ||
| 3747 | #define CAN_CS_DLC_SHIFT (16U) | ||
| 3748 | /*! DLC - Length of the data to be stored/transmitted. | ||
| 3749 | */ | ||
| 3750 | #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) | ||
| 3751 | #define CAN_CS_RTR_MASK (0x100000U) | ||
| 3752 | #define CAN_CS_RTR_SHIFT (20U) | ||
| 3753 | /*! RTR - Remote Transmission Request. One/zero for remote/data frame. | ||
| 3754 | */ | ||
| 3755 | #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) | ||
| 3756 | #define CAN_CS_IDE_MASK (0x200000U) | ||
| 3757 | #define CAN_CS_IDE_SHIFT (21U) | ||
| 3758 | /*! IDE - ID Extended. One/zero for extended/standard format frame. | ||
| 3759 | */ | ||
| 3760 | #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) | ||
| 3761 | #define CAN_CS_SRR_MASK (0x400000U) | ||
| 3762 | #define CAN_CS_SRR_SHIFT (22U) | ||
| 3763 | /*! SRR - Substitute Remote Request. Contains a fixed recessive bit. | ||
| 3764 | */ | ||
| 3765 | #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) | ||
| 3766 | #define CAN_CS_CODE_MASK (0xF000000U) | ||
| 3767 | #define CAN_CS_CODE_SHIFT (24U) | ||
| 3768 | /*! CODE - Reserved | ||
| 3769 | */ | ||
| 3770 | #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) | ||
| 3771 | /*! @} */ | ||
| 3772 | |||
| 3773 | /* The count of CAN_CS */ | ||
| 3774 | #define CAN_CS_COUNT (64U) | ||
| 3775 | |||
| 3776 | /*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */ | ||
| 3777 | /*! @{ */ | ||
| 3778 | #define CAN_ID_EXT_MASK (0x3FFFFU) | ||
| 3779 | #define CAN_ID_EXT_SHIFT (0U) | ||
| 3780 | /*! EXT - Contains extended (LOW word) identifier of message buffer. | ||
| 3781 | */ | ||
| 3782 | #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) | ||
| 3783 | #define CAN_ID_STD_MASK (0x1FFC0000U) | ||
| 3784 | #define CAN_ID_STD_SHIFT (18U) | ||
| 3785 | /*! STD - Contains standard/extended (HIGH word) identifier of message buffer. | ||
| 3786 | */ | ||
| 3787 | #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) | ||
| 3788 | #define CAN_ID_PRIO_MASK (0xE0000000U) | ||
| 3789 | #define CAN_ID_PRIO_SHIFT (29U) | ||
| 3790 | /*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only | ||
| 3791 | * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular | ||
| 3792 | * ID to define the transmission priority. | ||
| 3793 | */ | ||
| 3794 | #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) | ||
| 3795 | /*! @} */ | ||
| 3796 | |||
| 3797 | /* The count of CAN_ID */ | ||
| 3798 | #define CAN_ID_COUNT (64U) | ||
| 3799 | |||
| 3800 | /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */ | ||
| 3801 | /*! @{ */ | ||
| 3802 | #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) | ||
| 3803 | #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) | ||
| 3804 | /*! DATA_BYTE_3 - Data byte 3 of Rx/Tx frame. | ||
| 3805 | */ | ||
| 3806 | #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) | ||
| 3807 | #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) | ||
| 3808 | #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) | ||
| 3809 | /*! DATA_BYTE_2 - Data byte 2 of Rx/Tx frame. | ||
| 3810 | */ | ||
| 3811 | #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) | ||
| 3812 | #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) | ||
| 3813 | #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) | ||
| 3814 | /*! DATA_BYTE_1 - Data byte 1 of Rx/Tx frame. | ||
| 3815 | */ | ||
| 3816 | #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) | ||
| 3817 | #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) | ||
| 3818 | #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) | ||
| 3819 | /*! DATA_BYTE_0 - Data byte 0 of Rx/Tx frame. | ||
| 3820 | */ | ||
| 3821 | #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) | ||
| 3822 | /*! @} */ | ||
| 3823 | |||
| 3824 | /* The count of CAN_WORD0 */ | ||
| 3825 | #define CAN_WORD0_COUNT (64U) | ||
| 3826 | |||
| 3827 | /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */ | ||
| 3828 | /*! @{ */ | ||
| 3829 | #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) | ||
| 3830 | #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) | ||
| 3831 | /*! DATA_BYTE_7 - Data byte 7 of Rx/Tx frame. | ||
| 3832 | */ | ||
| 3833 | #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) | ||
| 3834 | #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) | ||
| 3835 | #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) | ||
| 3836 | /*! DATA_BYTE_6 - Data byte 6 of Rx/Tx frame. | ||
| 3837 | */ | ||
| 3838 | #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) | ||
| 3839 | #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) | ||
| 3840 | #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) | ||
| 3841 | /*! DATA_BYTE_5 - Data byte 5 of Rx/Tx frame. | ||
| 3842 | */ | ||
| 3843 | #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) | ||
| 3844 | #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) | ||
| 3845 | #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) | ||
| 3846 | /*! DATA_BYTE_4 - Data byte 4 of Rx/Tx frame. | ||
| 3847 | */ | ||
| 3848 | #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) | ||
| 3849 | /*! @} */ | ||
| 3850 | |||
| 3851 | /* The count of CAN_WORD1 */ | ||
| 3852 | #define CAN_WORD1_COUNT (64U) | ||
| 3853 | |||
| 3854 | /*! @name RXIMR - Rx Individual Mask Registers */ | ||
| 3855 | /*! @{ */ | ||
| 3856 | #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) | ||
| 3857 | #define CAN_RXIMR_MI_SHIFT (0U) | ||
| 3858 | /*! MI | ||
| 3859 | * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked | ||
| 3860 | * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" | ||
| 3861 | */ | ||
| 3862 | #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) | ||
| 3863 | /*! @} */ | ||
| 3864 | |||
| 3865 | /* The count of CAN_RXIMR */ | ||
| 3866 | #define CAN_RXIMR_COUNT (64U) | ||
| 3867 | |||
| 3868 | /*! @name GFWR - Glitch Filter Width Registers */ | ||
| 3869 | /*! @{ */ | ||
| 3870 | #define CAN_GFWR_GFWR_MASK (0xFFU) | ||
| 3871 | #define CAN_GFWR_GFWR_SHIFT (0U) | ||
| 3872 | #define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK) | ||
| 3873 | /*! @} */ | ||
| 3874 | |||
| 3875 | |||
| 3876 | /*! | ||
| 3877 | * @} | ||
| 3878 | */ /* end of group CAN_Register_Masks */ | ||
| 3879 | |||
| 3880 | |||
| 3881 | /* CAN - Peripheral instance base addresses */ | ||
| 3882 | /** Peripheral CAN1 base address */ | ||
| 3883 | #define CAN1_BASE (0x401D0000u) | ||
| 3884 | /** Peripheral CAN1 base pointer */ | ||
| 3885 | #define CAN1 ((CAN_Type *)CAN1_BASE) | ||
| 3886 | /** Peripheral CAN2 base address */ | ||
| 3887 | #define CAN2_BASE (0x401D4000u) | ||
| 3888 | /** Peripheral CAN2 base pointer */ | ||
| 3889 | #define CAN2 ((CAN_Type *)CAN2_BASE) | ||
| 3890 | /** Array initializer of CAN peripheral base addresses */ | ||
| 3891 | #define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE } | ||
| 3892 | /** Array initializer of CAN peripheral base pointers */ | ||
| 3893 | #define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 } | ||
| 3894 | /** Interrupt vectors for the CAN peripheral type */ | ||
| 3895 | #define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } | ||
| 3896 | #define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } | ||
| 3897 | #define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } | ||
| 3898 | #define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } | ||
| 3899 | #define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } | ||
| 3900 | #define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } | ||
| 3901 | /* Backward compatibility */ | ||
| 3902 | #define CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASK | ||
| 3903 | #define CAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFT | ||
| 3904 | #define CAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x) | ||
| 3905 | #define CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASK | ||
| 3906 | #define CAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFT | ||
| 3907 | #define CAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x) | ||
| 3908 | |||
| 3909 | |||
| 3910 | /*! | ||
| 3911 | * @} | ||
| 3912 | */ /* end of group CAN_Peripheral_Access_Layer */ | ||
| 3913 | |||
| 3914 | |||
| 3915 | /* ---------------------------------------------------------------------------- | ||
| 3916 | -- CCM Peripheral Access Layer | ||
| 3917 | ---------------------------------------------------------------------------- */ | ||
| 3918 | |||
| 3919 | /*! | ||
| 3920 | * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer | ||
| 3921 | * @{ | ||
| 3922 | */ | ||
| 3923 | |||
| 3924 | /** CCM - Register Layout Typedef */ | ||
| 3925 | typedef struct { | ||
| 3926 | __IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */ | ||
| 3927 | uint8_t RESERVED_0[4]; | ||
| 3928 | __I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */ | ||
| 3929 | __IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */ | ||
| 3930 | __IO uint32_t CACRR; /**< CCM Arm Clock Root Register, offset: 0x10 */ | ||
| 3931 | __IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */ | ||
| 3932 | __IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */ | ||
| 3933 | __IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */ | ||
| 3934 | __IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */ | ||
| 3935 | __IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */ | ||
| 3936 | __IO uint32_t CS1CDR; /**< CCM Clock Divider Register, offset: 0x28 */ | ||
| 3937 | __IO uint32_t CS2CDR; /**< CCM Clock Divider Register, offset: 0x2C */ | ||
| 3938 | __IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */ | ||
| 3939 | uint8_t RESERVED_1[4]; | ||
| 3940 | __IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */ | ||
| 3941 | uint32_t CSCDR3; /**< CCM Serial Clock Divider Register 3, offset: 0x3C */ | ||
| 3942 | uint8_t RESERVED_2[8]; | ||
| 3943 | __I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */ | ||
| 3944 | uint8_t RESERVED_3[8]; | ||
| 3945 | __IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */ | ||
| 3946 | __IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */ | ||
| 3947 | __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ | ||
| 3948 | __IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */ | ||
| 3949 | __IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */ | ||
| 3950 | __IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */ | ||
| 3951 | __IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */ | ||
| 3952 | __IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */ | ||
| 3953 | __IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */ | ||
| 3954 | __IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */ | ||
| 3955 | __IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */ | ||
| 3956 | __IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */ | ||
| 3957 | uint8_t RESERVED_4[4]; | ||
| 3958 | __IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */ | ||
| 3959 | } CCM_Type; | ||
| 3960 | |||
| 3961 | /* ---------------------------------------------------------------------------- | ||
| 3962 | -- CCM Register Masks | ||
| 3963 | ---------------------------------------------------------------------------- */ | ||
| 3964 | |||
| 3965 | /*! | ||
| 3966 | * @addtogroup CCM_Register_Masks CCM Register Masks | ||
| 3967 | * @{ | ||
| 3968 | */ | ||
| 3969 | |||
| 3970 | /*! @name CCR - CCM Control Register */ | ||
| 3971 | /*! @{ */ | ||
| 3972 | #define CCM_CCR_OSCNT_MASK (0xFFU) | ||
| 3973 | #define CCM_CCR_OSCNT_SHIFT (0U) | ||
| 3974 | /*! OSCNT - Oscillator ready counter value. These bits define value of 32KHz counter, that serve as | ||
| 3975 | * counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time. | ||
| 3976 | * Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from | ||
| 3977 | * stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for | ||
| 3978 | * the dpll_ip to use and only then the gate in dpll_ip can be opened. | ||
| 3979 | */ | ||
| 3980 | #define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK) | ||
| 3981 | #define CCM_CCR_COSC_EN_MASK (0x1000U) | ||
| 3982 | #define CCM_CCR_COSC_EN_SHIFT (12U) | ||
| 3983 | /*! COSC_EN | ||
| 3984 | * 0b0..disable on chip oscillator | ||
| 3985 | * 0b1..enable on chip oscillator | ||
| 3986 | */ | ||
| 3987 | #define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK) | ||
| 3988 | #define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U) | ||
| 3989 | #define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U) | ||
| 3990 | /*! REG_BYPASS_COUNT | ||
| 3991 | * 0b000000..no delay | ||
| 3992 | * 0b000001..1 CKIL clock period delay | ||
| 3993 | * 0b111111..63 CKIL clock periods delay | ||
| 3994 | */ | ||
| 3995 | #define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK) | ||
| 3996 | #define CCM_CCR_RBC_EN_MASK (0x8000000U) | ||
| 3997 | #define CCM_CCR_RBC_EN_SHIFT (27U) | ||
| 3998 | /*! RBC_EN | ||
| 3999 | * 0b1..REG_BYPASS_COUNTER enabled. | ||
| 4000 | * 0b0..REG_BYPASS_COUNTER disabled | ||
| 4001 | */ | ||
| 4002 | #define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK) | ||
| 4003 | /*! @} */ | ||
| 4004 | |||
| 4005 | /*! @name CSR - CCM Status Register */ | ||
| 4006 | /*! @{ */ | ||
| 4007 | #define CCM_CSR_REF_EN_B_MASK (0x1U) | ||
| 4008 | #define CCM_CSR_REF_EN_B_SHIFT (0U) | ||
| 4009 | /*! REF_EN_B | ||
| 4010 | * 0b0..value of CCM_REF_EN_B is '0' | ||
| 4011 | * 0b1..value of CCM_REF_EN_B is '1' | ||
| 4012 | */ | ||
| 4013 | #define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK) | ||
| 4014 | #define CCM_CSR_CAMP2_READY_MASK (0x8U) | ||
| 4015 | #define CCM_CSR_CAMP2_READY_SHIFT (3U) | ||
| 4016 | /*! CAMP2_READY | ||
| 4017 | * 0b0..CAMP2 is not ready. | ||
| 4018 | * 0b1..CAMP2 is ready. | ||
| 4019 | */ | ||
| 4020 | #define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK) | ||
| 4021 | #define CCM_CSR_COSC_READY_MASK (0x20U) | ||
| 4022 | #define CCM_CSR_COSC_READY_SHIFT (5U) | ||
| 4023 | /*! COSC_READY | ||
| 4024 | * 0b0..on board oscillator is not ready. | ||
| 4025 | * 0b1..on board oscillator is ready. | ||
| 4026 | */ | ||
| 4027 | #define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK) | ||
| 4028 | /*! @} */ | ||
| 4029 | |||
| 4030 | /*! @name CCSR - CCM Clock Switcher Register */ | ||
| 4031 | /*! @{ */ | ||
| 4032 | #define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U) | ||
| 4033 | #define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U) | ||
| 4034 | /*! PLL3_SW_CLK_SEL | ||
| 4035 | * 0b0..pll3_main_clk | ||
| 4036 | * 0b1..pll3 bypass clock | ||
| 4037 | */ | ||
| 4038 | #define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK) | ||
| 4039 | /*! @} */ | ||
| 4040 | |||
| 4041 | /*! @name CACRR - CCM Arm Clock Root Register */ | ||
| 4042 | /*! @{ */ | ||
| 4043 | #define CCM_CACRR_ARM_PODF_MASK (0x7U) | ||
| 4044 | #define CCM_CACRR_ARM_PODF_SHIFT (0U) | ||
| 4045 | /*! ARM_PODF | ||
| 4046 | * 0b000..divide by 1 | ||
| 4047 | * 0b001..divide by 2 | ||
| 4048 | * 0b010..divide by 3 | ||
| 4049 | * 0b011..divide by 4 | ||
| 4050 | * 0b100..divide by 5 | ||
| 4051 | * 0b101..divide by 6 | ||
| 4052 | * 0b110..divide by 7 | ||
| 4053 | * 0b111..divide by 8 | ||
| 4054 | */ | ||
| 4055 | #define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK) | ||
| 4056 | /*! @} */ | ||
| 4057 | |||
| 4058 | /*! @name CBCDR - CCM Bus Clock Divider Register */ | ||
| 4059 | /*! @{ */ | ||
| 4060 | #define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U) | ||
| 4061 | #define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U) | ||
| 4062 | /*! SEMC_CLK_SEL | ||
| 4063 | * 0b0..Periph_clk output will be used as SEMC clock root | ||
| 4064 | * 0b1..SEMC alternative clock will be used as SEMC clock root | ||
| 4065 | */ | ||
| 4066 | #define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK) | ||
| 4067 | #define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U) | ||
| 4068 | #define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U) | ||
| 4069 | /*! SEMC_ALT_CLK_SEL | ||
| 4070 | * 0b0..PLL2 PFD2 will be selected as alternative clock for SEMC root clock | ||
| 4071 | * 0b1..PLL3 PFD1 will be selected as alternative clock for SEMC root clock | ||
| 4072 | */ | ||
| 4073 | #define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) | ||
| 4074 | #define CCM_CBCDR_IPG_PODF_MASK (0x300U) | ||
| 4075 | #define CCM_CBCDR_IPG_PODF_SHIFT (8U) | ||
| 4076 | /*! IPG_PODF | ||
| 4077 | * 0b00..divide by 1 | ||
| 4078 | * 0b01..divide by 2 | ||
| 4079 | * 0b10..divide by 3 | ||
| 4080 | * 0b11..divide by 4 | ||
| 4081 | */ | ||
| 4082 | #define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK) | ||
| 4083 | #define CCM_CBCDR_AHB_PODF_MASK (0x1C00U) | ||
| 4084 | #define CCM_CBCDR_AHB_PODF_SHIFT (10U) | ||
| 4085 | /*! AHB_PODF | ||
| 4086 | * 0b000..divide by 1 | ||
| 4087 | * 0b001..divide by 2 | ||
| 4088 | * 0b010..divide by 3 | ||
| 4089 | * 0b011..divide by 4 | ||
| 4090 | * 0b100..divide by 5 | ||
| 4091 | * 0b101..divide by 6 | ||
| 4092 | * 0b110..divide by 7 | ||
| 4093 | * 0b111..divide by 8 | ||
| 4094 | */ | ||
| 4095 | #define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK) | ||
| 4096 | #define CCM_CBCDR_SEMC_PODF_MASK (0x70000U) | ||
| 4097 | #define CCM_CBCDR_SEMC_PODF_SHIFT (16U) | ||
| 4098 | /*! SEMC_PODF | ||
| 4099 | * 0b000..divide by 1 | ||
| 4100 | * 0b001..divide by 2 | ||
| 4101 | * 0b010..divide by 3 | ||
| 4102 | * 0b011..divide by 4 | ||
| 4103 | * 0b100..divide by 5 | ||
| 4104 | * 0b101..divide by 6 | ||
| 4105 | * 0b110..divide by 7 | ||
| 4106 | * 0b111..divide by 8 | ||
| 4107 | */ | ||
| 4108 | #define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK) | ||
| 4109 | #define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U) | ||
| 4110 | #define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U) | ||
| 4111 | /*! PERIPH_CLK_SEL | ||
| 4112 | * 0b0..derive clock from pre_periph_clk_sel | ||
| 4113 | * 0b1..derive clock from periph_clk2_clk_divided | ||
| 4114 | */ | ||
| 4115 | #define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK) | ||
| 4116 | #define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U) | ||
| 4117 | #define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U) | ||
| 4118 | /*! PERIPH_CLK2_PODF | ||
| 4119 | * 0b000..divide by 1 | ||
| 4120 | * 0b001..divide by 2 | ||
| 4121 | * 0b010..divide by 3 | ||
| 4122 | * 0b011..divide by 4 | ||
| 4123 | * 0b100..divide by 5 | ||
| 4124 | * 0b101..divide by 6 | ||
| 4125 | * 0b110..divide by 7 | ||
| 4126 | * 0b111..divide by 8 | ||
| 4127 | */ | ||
| 4128 | #define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) | ||
| 4129 | /*! @} */ | ||
| 4130 | |||
| 4131 | /*! @name CBCMR - CCM Bus Clock Multiplexer Register */ | ||
| 4132 | /*! @{ */ | ||
| 4133 | #define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U) | ||
| 4134 | #define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U) | ||
| 4135 | /*! LPSPI_CLK_SEL | ||
| 4136 | * 0b00..derive clock from PLL3 PFD1 clk | ||
| 4137 | * 0b01..derive clock from PLL3 PFD0 | ||
| 4138 | * 0b10..derive clock from PLL2 | ||
| 4139 | * 0b11..derive clock from PLL2 PFD2 | ||
| 4140 | */ | ||
| 4141 | #define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK) | ||
| 4142 | #define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U) | ||
| 4143 | #define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U) | ||
| 4144 | /*! PERIPH_CLK2_SEL | ||
| 4145 | * 0b00..derive clock from pll3_sw_clk | ||
| 4146 | * 0b01..derive clock from osc_clk | ||
| 4147 | * 0b10..derive clock from pll2_bypass_clk | ||
| 4148 | * 0b11..reserved | ||
| 4149 | */ | ||
| 4150 | #define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) | ||
| 4151 | #define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U) | ||
| 4152 | #define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U) | ||
| 4153 | /*! TRACE_CLK_SEL | ||
| 4154 | * 0b00..derive clock from PLL2 | ||
| 4155 | * 0b01..derive clock from PLL2 PFD2 | ||
| 4156 | * 0b10..derive clock from PLL2 PFD0 | ||
| 4157 | * 0b11..derive clock from PLL2 PFD1 | ||
| 4158 | */ | ||
| 4159 | #define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK) | ||
| 4160 | #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U) | ||
| 4161 | #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U) | ||
| 4162 | /*! PRE_PERIPH_CLK_SEL | ||
| 4163 | * 0b00..derive clock from PLL2 | ||
| 4164 | * 0b01..derive clock from PLL3 PFD3 | ||
| 4165 | * 0b10..derive clock from PLL2 PFD3 | ||
| 4166 | * 0b11..derive clock from divided PLL6 | ||
| 4167 | */ | ||
| 4168 | #define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) | ||
| 4169 | #define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U) | ||
| 4170 | #define CCM_CBCMR_LPSPI_PODF_SHIFT (26U) | ||
| 4171 | /*! LPSPI_PODF | ||
| 4172 | * 0b000..divide by 1 | ||
| 4173 | * 0b001..divide by 2 | ||
| 4174 | * 0b010..divide by 3 | ||
| 4175 | * 0b011..divide by 4 | ||
| 4176 | * 0b100..divide by 5 | ||
| 4177 | * 0b101..divide by 6 | ||
| 4178 | * 0b110..divide by 7 | ||
| 4179 | * 0b111..divide by 8 | ||
| 4180 | */ | ||
| 4181 | #define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK) | ||
| 4182 | /*! @} */ | ||
| 4183 | |||
| 4184 | /*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */ | ||
| 4185 | /*! @{ */ | ||
| 4186 | #define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU) | ||
| 4187 | #define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U) | ||
| 4188 | /*! PERCLK_PODF - Divider for perclk podf. | ||
| 4189 | * 0b000000..Divide by 1 | ||
| 4190 | * 0b000001..Divide by 2 | ||
| 4191 | * 0b000010..Divide by 3 | ||
| 4192 | * 0b000011..Divide by 4 | ||
| 4193 | * 0b000100..Divide by 5 | ||
| 4194 | * 0b000101..Divide by 6 | ||
| 4195 | * 0b000110..Divide by 7 | ||
| 4196 | * 0b000111..Divide by 8 | ||
| 4197 | * 0b001000..Divide by 9 | ||
| 4198 | * 0b001001..Divide by 10 | ||
| 4199 | * 0b001010..Divide by 11 | ||
| 4200 | * 0b001011..Divide by 12 | ||
| 4201 | * 0b001100..Divide by 13 | ||
| 4202 | * 0b001101..Divide by 14 | ||
| 4203 | * 0b001110..Divide by 15 | ||
| 4204 | * 0b001111..Divide by 16 | ||
| 4205 | * 0b010000..Divide by 17 | ||
| 4206 | * 0b010001..Divide by 18 | ||
| 4207 | * 0b010010..Divide by 19 | ||
| 4208 | * 0b010011..Divide by 20 | ||
| 4209 | * 0b010100..Divide by 21 | ||
| 4210 | * 0b010101..Divide by 22 | ||
| 4211 | * 0b010110..Divide by 23 | ||
| 4212 | * 0b010111..Divide by 24 | ||
| 4213 | * 0b011000..Divide by 25 | ||
| 4214 | * 0b011001..Divide by 26 | ||
| 4215 | * 0b011010..Divide by 27 | ||
| 4216 | * 0b011011..Divide by 28 | ||
| 4217 | * 0b011100..Divide by 29 | ||
| 4218 | * 0b011101..Divide by 30 | ||
| 4219 | * 0b011110..Divide by 31 | ||
| 4220 | * 0b011111..Divide by 32 | ||
| 4221 | * 0b100000..Divide by 33 | ||
| 4222 | * 0b100001..Divide by 34 | ||
| 4223 | * 0b100010..Divide by 35 | ||
| 4224 | * 0b100011..Divide by 36 | ||
| 4225 | * 0b100100..Divide by 37 | ||
| 4226 | * 0b100101..Divide by 38 | ||
| 4227 | * 0b100110..Divide by 39 | ||
| 4228 | * 0b100111..Divide by 40 | ||
| 4229 | * 0b101000..Divide by 41 | ||
| 4230 | * 0b101001..Divide by 42 | ||
| 4231 | * 0b101010..Divide by 43 | ||
| 4232 | * 0b101011..Divide by 44 | ||
| 4233 | * 0b101100..Divide by 45 | ||
| 4234 | * 0b101101..Divide by 46 | ||
| 4235 | * 0b101110..Divide by 47 | ||
| 4236 | * 0b101111..Divide by 48 | ||
| 4237 | * 0b110000..Divide by 49 | ||
| 4238 | * 0b110001..Divide by 50 | ||
| 4239 | * 0b110010..Divide by 51 | ||
| 4240 | * 0b110011..Divide by 52 | ||
| 4241 | * 0b110100..Divide by 53 | ||
| 4242 | * 0b110101..Divide by 54 | ||
| 4243 | * 0b110110..Divide by 55 | ||
| 4244 | * 0b110111..Divide by 56 | ||
| 4245 | * 0b111000..Divide by 57 | ||
| 4246 | * 0b111001..Divide by 58 | ||
| 4247 | * 0b111010..Divide by 59 | ||
| 4248 | * 0b111011..Divide by 60 | ||
| 4249 | * 0b111100..Divide by 61 | ||
| 4250 | * 0b111101..Divide by 62 | ||
| 4251 | * 0b111110..Divide by 63 | ||
| 4252 | * 0b111111..Divide by 64 | ||
| 4253 | */ | ||
| 4254 | #define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK) | ||
| 4255 | #define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U) | ||
| 4256 | #define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U) | ||
| 4257 | /*! PERCLK_CLK_SEL | ||
| 4258 | * 0b0..derive clock from ipg clk root | ||
| 4259 | * 0b1..derive clock from osc_clk | ||
| 4260 | */ | ||
| 4261 | #define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) | ||
| 4262 | #define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U) | ||
| 4263 | #define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U) | ||
| 4264 | /*! SAI1_CLK_SEL | ||
| 4265 | * 0b00..derive clock from PLL3 PFD2 | ||
| 4266 | * 0b01..Reserved | ||
| 4267 | * 0b10..derive clock from PLL4 | ||
| 4268 | * 0b11..Reserved | ||
| 4269 | */ | ||
| 4270 | #define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK) | ||
| 4271 | #define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U) | ||
| 4272 | #define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U) | ||
| 4273 | /*! SAI2_CLK_SEL | ||
| 4274 | * 0b00..derive clock from PLL3 PFD2 | ||
| 4275 | * 0b01..Reserved | ||
| 4276 | * 0b10..derive clock from PLL4 | ||
| 4277 | * 0b11..Reserved | ||
| 4278 | */ | ||
| 4279 | #define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK) | ||
| 4280 | #define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U) | ||
| 4281 | #define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U) | ||
| 4282 | /*! SAI3_CLK_SEL | ||
| 4283 | * 0b00..derive clock from PLL3 PFD2 | ||
| 4284 | * 0b01..Reserved | ||
| 4285 | * 0b10..derive clock from PLL4 | ||
| 4286 | * 0b11..Reserved | ||
| 4287 | */ | ||
| 4288 | #define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK) | ||
| 4289 | #define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U) | ||
| 4290 | #define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U) | ||
| 4291 | /*! USDHC1_CLK_SEL | ||
| 4292 | * 0b0..derive clock from PLL2 PFD2 | ||
| 4293 | * 0b1..derive clock from PLL2 PFD0 | ||
| 4294 | */ | ||
| 4295 | #define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK) | ||
| 4296 | #define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U) | ||
| 4297 | #define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U) | ||
| 4298 | /*! USDHC2_CLK_SEL | ||
| 4299 | * 0b0..derive clock from PLL2 PFD2 | ||
| 4300 | * 0b1..derive clock from PLL2 PFD0 | ||
| 4301 | */ | ||
| 4302 | #define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK) | ||
| 4303 | #define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U) | ||
| 4304 | #define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U) | ||
| 4305 | /*! FLEXSPI_PODF | ||
| 4306 | * 0b000..divide by 1 | ||
| 4307 | * 0b001..divide by 2 | ||
| 4308 | * 0b010..divide by 3 | ||
| 4309 | * 0b011..divide by 4 | ||
| 4310 | * 0b100..divide by 5 | ||
| 4311 | * 0b101..divide by 6 | ||
| 4312 | * 0b110..divide by 7 | ||
| 4313 | * 0b111..divide by 8 | ||
| 4314 | */ | ||
| 4315 | #define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK) | ||
| 4316 | #define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U) | ||
| 4317 | #define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U) | ||
| 4318 | /*! FLEXSPI_CLK_SEL | ||
| 4319 | * 0b00..derive clock from semc_clk_root_pre | ||
| 4320 | * 0b01..derive clock from pll3_sw_clk | ||
| 4321 | * 0b10..derive clock from PLL2 PFD2 | ||
| 4322 | * 0b11..derive clock from PLL3 PFD0 | ||
| 4323 | */ | ||
| 4324 | #define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK) | ||
| 4325 | /*! @} */ | ||
| 4326 | |||
| 4327 | /*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */ | ||
| 4328 | /*! @{ */ | ||
| 4329 | #define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU) | ||
| 4330 | #define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U) | ||
| 4331 | /*! CAN_CLK_PODF - Divider for CAN clock podf. | ||
| 4332 | * 0b000000..Divide by 1 | ||
| 4333 | * 0b000001..Divide by 2 | ||
| 4334 | * 0b000010..Divide by 3 | ||
| 4335 | * 0b000011..Divide by 4 | ||
| 4336 | * 0b000100..Divide by 5 | ||
| 4337 | * 0b000101..Divide by 6 | ||
| 4338 | * 0b000110..Divide by 7 | ||
| 4339 | * 0b000111..Divide by 8 | ||
| 4340 | * 0b001000..Divide by 9 | ||
| 4341 | * 0b001001..Divide by 10 | ||
| 4342 | * 0b001010..Divide by 11 | ||
| 4343 | * 0b001011..Divide by 12 | ||
| 4344 | * 0b001100..Divide by 13 | ||
| 4345 | * 0b001101..Divide by 14 | ||
| 4346 | * 0b001110..Divide by 15 | ||
| 4347 | * 0b001111..Divide by 16 | ||
| 4348 | * 0b010000..Divide by 17 | ||
| 4349 | * 0b010001..Divide by 18 | ||
| 4350 | * 0b010010..Divide by 19 | ||
| 4351 | * 0b010011..Divide by 20 | ||
| 4352 | * 0b010100..Divide by 21 | ||
| 4353 | * 0b010101..Divide by 22 | ||
| 4354 | * 0b010110..Divide by 23 | ||
| 4355 | * 0b010111..Divide by 24 | ||
| 4356 | * 0b011000..Divide by 25 | ||
| 4357 | * 0b011001..Divide by 26 | ||
| 4358 | * 0b011010..Divide by 27 | ||
| 4359 | * 0b011011..Divide by 28 | ||
| 4360 | * 0b011100..Divide by 29 | ||
| 4361 | * 0b011101..Divide by 30 | ||
| 4362 | * 0b011110..Divide by 31 | ||
| 4363 | * 0b011111..Divide by 32 | ||
| 4364 | * 0b100000..Divide by 33 | ||
| 4365 | * 0b100001..Divide by 34 | ||
| 4366 | * 0b100010..Divide by 35 | ||
| 4367 | * 0b100011..Divide by 36 | ||
| 4368 | * 0b100100..Divide by 37 | ||
| 4369 | * 0b100101..Divide by 38 | ||
| 4370 | * 0b100110..Divide by 39 | ||
| 4371 | * 0b100111..Divide by 40 | ||
| 4372 | * 0b101000..Divide by 41 | ||
| 4373 | * 0b101001..Divide by 42 | ||
| 4374 | * 0b101010..Divide by 43 | ||
| 4375 | * 0b101011..Divide by 44 | ||
| 4376 | * 0b101100..Divide by 45 | ||
| 4377 | * 0b101101..Divide by 46 | ||
| 4378 | * 0b101110..Divide by 47 | ||
| 4379 | * 0b101111..Divide by 48 | ||
| 4380 | * 0b110000..Divide by 49 | ||
| 4381 | * 0b110001..Divide by 50 | ||
| 4382 | * 0b110010..Divide by 51 | ||
| 4383 | * 0b110011..Divide by 52 | ||
| 4384 | * 0b110100..Divide by 53 | ||
| 4385 | * 0b110101..Divide by 54 | ||
| 4386 | * 0b110110..Divide by 55 | ||
| 4387 | * 0b110111..Divide by 56 | ||
| 4388 | * 0b111000..Divide by 57 | ||
| 4389 | * 0b111001..Divide by 58 | ||
| 4390 | * 0b111010..Divide by 59 | ||
| 4391 | * 0b111011..Divide by 60 | ||
| 4392 | * 0b111100..Divide by 61 | ||
| 4393 | * 0b111101..Divide by 62 | ||
| 4394 | * 0b111110..Divide by 63 | ||
| 4395 | * 0b111111..Divide by 64 | ||
| 4396 | */ | ||
| 4397 | #define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK) | ||
| 4398 | #define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U) | ||
| 4399 | #define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U) | ||
| 4400 | /*! CAN_CLK_SEL | ||
| 4401 | * 0b00..derive clock from pll3_sw_clk divided clock (60M) | ||
| 4402 | * 0b01..derive clock from osc_clk (24M) | ||
| 4403 | * 0b10..derive clock from pll3_sw_clk divided clock (80M) | ||
| 4404 | */ | ||
| 4405 | #define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK) | ||
| 4406 | #define CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK (0x180000U) | ||
| 4407 | #define CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT (19U) | ||
| 4408 | /*! FLEXIO1_CLK_SEL | ||
| 4409 | * 0b00..derive clock from PLL4 divided clock | ||
| 4410 | * 0b01..derive clock from PLL3 PFD2 clock | ||
| 4411 | * 0b10..Reserved | ||
| 4412 | * 0b11..derive clock from pll3_sw_clk | ||
| 4413 | */ | ||
| 4414 | #define CCM_CSCMR2_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK) | ||
| 4415 | /*! @} */ | ||
| 4416 | |||
| 4417 | /*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */ | ||
| 4418 | /*! @{ */ | ||
| 4419 | #define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU) | ||
| 4420 | #define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U) | ||
| 4421 | /*! UART_CLK_PODF - Divider for uart clock podf. | ||
| 4422 | * 0b000000..Divide by 1 | ||
| 4423 | * 0b000001..Divide by 2 | ||
| 4424 | * 0b000010..Divide by 3 | ||
| 4425 | * 0b000011..Divide by 4 | ||
| 4426 | * 0b000100..Divide by 5 | ||
| 4427 | * 0b000101..Divide by 6 | ||
| 4428 | * 0b000110..Divide by 7 | ||
| 4429 | * 0b000111..Divide by 8 | ||
| 4430 | * 0b001000..Divide by 9 | ||
| 4431 | * 0b001001..Divide by 10 | ||
| 4432 | * 0b001010..Divide by 11 | ||
| 4433 | * 0b001011..Divide by 12 | ||
| 4434 | * 0b001100..Divide by 13 | ||
| 4435 | * 0b001101..Divide by 14 | ||
| 4436 | * 0b001110..Divide by 15 | ||
| 4437 | * 0b001111..Divide by 16 | ||
| 4438 | * 0b010000..Divide by 17 | ||
| 4439 | * 0b010001..Divide by 18 | ||
| 4440 | * 0b010010..Divide by 19 | ||
| 4441 | * 0b010011..Divide by 20 | ||
| 4442 | * 0b010100..Divide by 21 | ||
| 4443 | * 0b010101..Divide by 22 | ||
| 4444 | * 0b010110..Divide by 23 | ||
| 4445 | * 0b010111..Divide by 24 | ||
| 4446 | * 0b011000..Divide by 25 | ||
| 4447 | * 0b011001..Divide by 26 | ||
| 4448 | * 0b011010..Divide by 27 | ||
| 4449 | * 0b011011..Divide by 28 | ||
| 4450 | * 0b011100..Divide by 29 | ||
| 4451 | * 0b011101..Divide by 30 | ||
| 4452 | * 0b011110..Divide by 31 | ||
| 4453 | * 0b011111..Divide by 32 | ||
| 4454 | * 0b100000..Divide by 33 | ||
| 4455 | * 0b100001..Divide by 34 | ||
| 4456 | * 0b100010..Divide by 35 | ||
| 4457 | * 0b100011..Divide by 36 | ||
| 4458 | * 0b100100..Divide by 37 | ||
| 4459 | * 0b100101..Divide by 38 | ||
| 4460 | * 0b100110..Divide by 39 | ||
| 4461 | * 0b100111..Divide by 40 | ||
| 4462 | * 0b101000..Divide by 41 | ||
| 4463 | * 0b101001..Divide by 42 | ||
| 4464 | * 0b101010..Divide by 43 | ||
| 4465 | * 0b101011..Divide by 44 | ||
| 4466 | * 0b101100..Divide by 45 | ||
| 4467 | * 0b101101..Divide by 46 | ||
| 4468 | * 0b101110..Divide by 47 | ||
| 4469 | * 0b101111..Divide by 48 | ||
| 4470 | * 0b110000..Divide by 49 | ||
| 4471 | * 0b110001..Divide by 50 | ||
| 4472 | * 0b110010..Divide by 51 | ||
| 4473 | * 0b110011..Divide by 52 | ||
| 4474 | * 0b110100..Divide by 53 | ||
| 4475 | * 0b110101..Divide by 54 | ||
| 4476 | * 0b110110..Divide by 55 | ||
| 4477 | * 0b110111..Divide by 56 | ||
| 4478 | * 0b111000..Divide by 57 | ||
| 4479 | * 0b111001..Divide by 58 | ||
| 4480 | * 0b111010..Divide by 59 | ||
| 4481 | * 0b111011..Divide by 60 | ||
| 4482 | * 0b111100..Divide by 61 | ||
| 4483 | * 0b111101..Divide by 62 | ||
| 4484 | * 0b111110..Divide by 63 | ||
| 4485 | * 0b111111..Divide by 64 | ||
| 4486 | */ | ||
| 4487 | #define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK) | ||
| 4488 | #define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U) | ||
| 4489 | #define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U) | ||
| 4490 | /*! UART_CLK_SEL | ||
| 4491 | * 0b0..derive clock from pll3_80m | ||
| 4492 | * 0b1..derive clock from osc_clk | ||
| 4493 | */ | ||
| 4494 | #define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK) | ||
| 4495 | #define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U) | ||
| 4496 | #define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U) | ||
| 4497 | /*! USDHC1_PODF | ||
| 4498 | * 0b000..divide by 1 | ||
| 4499 | * 0b001..divide by 2 | ||
| 4500 | * 0b010..divide by 3 | ||
| 4501 | * 0b011..divide by 4 | ||
| 4502 | * 0b100..divide by 5 | ||
| 4503 | * 0b101..divide by 6 | ||
| 4504 | * 0b110..divide by 7 | ||
| 4505 | * 0b111..divide by 8 | ||
| 4506 | */ | ||
| 4507 | #define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK) | ||
| 4508 | #define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U) | ||
| 4509 | #define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U) | ||
| 4510 | /*! USDHC2_PODF | ||
| 4511 | * 0b000..divide by 1 | ||
| 4512 | * 0b001..divide by 2 | ||
| 4513 | * 0b010..divide by 3 | ||
| 4514 | * 0b011..divide by 4 | ||
| 4515 | * 0b100..divide by 5 | ||
| 4516 | * 0b101..divide by 6 | ||
| 4517 | * 0b110..divide by 7 | ||
| 4518 | * 0b111..divide by 8 | ||
| 4519 | */ | ||
| 4520 | #define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK) | ||
| 4521 | #define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U) | ||
| 4522 | #define CCM_CSCDR1_TRACE_PODF_SHIFT (25U) | ||
| 4523 | /*! TRACE_PODF | ||
| 4524 | * 0b00..divide by 1 | ||
| 4525 | * 0b01..divide by 2 | ||
| 4526 | * 0b10..divide by 3 | ||
| 4527 | * 0b11..divide by 4 | ||
| 4528 | */ | ||
| 4529 | #define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK) | ||
| 4530 | /*! @} */ | ||
| 4531 | |||
| 4532 | /*! @name CS1CDR - CCM Clock Divider Register */ | ||
| 4533 | /*! @{ */ | ||
| 4534 | #define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU) | ||
| 4535 | #define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U) | ||
| 4536 | /*! SAI1_CLK_PODF - Divider for sai1 clock podf. The input clock to this divider should be lower | ||
| 4537 | * than 300Mhz, the predivider can be used to achieve this. | ||
| 4538 | * 0b000000..Divide by 1 | ||
| 4539 | * 0b000001..Divide by 2 | ||
| 4540 | * 0b000010..Divide by 3 | ||
| 4541 | * 0b000011..Divide by 4 | ||
| 4542 | * 0b000100..Divide by 5 | ||
| 4543 | * 0b000101..Divide by 6 | ||
| 4544 | * 0b000110..Divide by 7 | ||
| 4545 | * 0b000111..Divide by 8 | ||
| 4546 | * 0b001000..Divide by 9 | ||
| 4547 | * 0b001001..Divide by 10 | ||
| 4548 | * 0b001010..Divide by 11 | ||
| 4549 | * 0b001011..Divide by 12 | ||
| 4550 | * 0b001100..Divide by 13 | ||
| 4551 | * 0b001101..Divide by 14 | ||
| 4552 | * 0b001110..Divide by 15 | ||
| 4553 | * 0b001111..Divide by 16 | ||
| 4554 | * 0b010000..Divide by 17 | ||
| 4555 | * 0b010001..Divide by 18 | ||
| 4556 | * 0b010010..Divide by 19 | ||
| 4557 | * 0b010011..Divide by 20 | ||
| 4558 | * 0b010100..Divide by 21 | ||
| 4559 | * 0b010101..Divide by 22 | ||
| 4560 | * 0b010110..Divide by 23 | ||
| 4561 | * 0b010111..Divide by 24 | ||
| 4562 | * 0b011000..Divide by 25 | ||
| 4563 | * 0b011001..Divide by 26 | ||
| 4564 | * 0b011010..Divide by 27 | ||
| 4565 | * 0b011011..Divide by 28 | ||
| 4566 | * 0b011100..Divide by 29 | ||
| 4567 | * 0b011101..Divide by 30 | ||
| 4568 | * 0b011110..Divide by 31 | ||
| 4569 | * 0b011111..Divide by 32 | ||
| 4570 | * 0b100000..Divide by 33 | ||
| 4571 | * 0b100001..Divide by 34 | ||
| 4572 | * 0b100010..Divide by 35 | ||
| 4573 | * 0b100011..Divide by 36 | ||
| 4574 | * 0b100100..Divide by 37 | ||
| 4575 | * 0b100101..Divide by 38 | ||
| 4576 | * 0b100110..Divide by 39 | ||
| 4577 | * 0b100111..Divide by 40 | ||
| 4578 | * 0b101000..Divide by 41 | ||
| 4579 | * 0b101001..Divide by 42 | ||
| 4580 | * 0b101010..Divide by 43 | ||
| 4581 | * 0b101011..Divide by 44 | ||
| 4582 | * 0b101100..Divide by 45 | ||
| 4583 | * 0b101101..Divide by 46 | ||
| 4584 | * 0b101110..Divide by 47 | ||
| 4585 | * 0b101111..Divide by 48 | ||
| 4586 | * 0b110000..Divide by 49 | ||
| 4587 | * 0b110001..Divide by 50 | ||
| 4588 | * 0b110010..Divide by 51 | ||
| 4589 | * 0b110011..Divide by 52 | ||
| 4590 | * 0b110100..Divide by 53 | ||
| 4591 | * 0b110101..Divide by 54 | ||
| 4592 | * 0b110110..Divide by 55 | ||
| 4593 | * 0b110111..Divide by 56 | ||
| 4594 | * 0b111000..Divide by 57 | ||
| 4595 | * 0b111001..Divide by 58 | ||
| 4596 | * 0b111010..Divide by 59 | ||
| 4597 | * 0b111011..Divide by 60 | ||
| 4598 | * 0b111100..Divide by 61 | ||
| 4599 | * 0b111101..Divide by 62 | ||
| 4600 | * 0b111110..Divide by 63 | ||
| 4601 | * 0b111111..Divide by 64 | ||
| 4602 | */ | ||
| 4603 | #define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK) | ||
| 4604 | #define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U) | ||
| 4605 | #define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U) | ||
| 4606 | /*! SAI1_CLK_PRED | ||
| 4607 | * 0b000..divide by 1 | ||
| 4608 | * 0b001..divide by 2 | ||
| 4609 | * 0b010..divide by 3 | ||
| 4610 | * 0b011..divide by 4 | ||
| 4611 | * 0b100..divide by 5 | ||
| 4612 | * 0b101..divide by 6 | ||
| 4613 | * 0b110..divide by 7 | ||
| 4614 | * 0b111..divide by 8 | ||
| 4615 | */ | ||
| 4616 | #define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK) | ||
| 4617 | #define CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK (0xE00U) | ||
| 4618 | #define CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT (9U) | ||
| 4619 | /*! FLEXIO1_CLK_PRED | ||
| 4620 | * 0b000..divide by 1 | ||
| 4621 | * 0b001..divide by 2 | ||
| 4622 | * 0b010..divide by 3 | ||
| 4623 | * 0b011..divide by 4 | ||
| 4624 | * 0b100..divide by 5 | ||
| 4625 | * 0b101..divide by 6 | ||
| 4626 | * 0b110..divide by 7 | ||
| 4627 | * 0b111..divide by 8 | ||
| 4628 | */ | ||
| 4629 | #define CCM_CS1CDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK) | ||
| 4630 | #define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U) | ||
| 4631 | #define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U) | ||
| 4632 | /*! SAI3_CLK_PODF - Divider for sai3 clock podf. The input clock to this divider should be lower | ||
| 4633 | * than 300Mhz, the predivider can be used to achieve this. | ||
| 4634 | * 0b000000..Divide by 1 | ||
| 4635 | * 0b000001..Divide by 2 | ||
| 4636 | * 0b000010..Divide by 3 | ||
| 4637 | * 0b000011..Divide by 4 | ||
| 4638 | * 0b000100..Divide by 5 | ||
| 4639 | * 0b000101..Divide by 6 | ||
| 4640 | * 0b000110..Divide by 7 | ||
| 4641 | * 0b000111..Divide by 8 | ||
| 4642 | * 0b001000..Divide by 9 | ||
| 4643 | * 0b001001..Divide by 10 | ||
| 4644 | * 0b001010..Divide by 11 | ||
| 4645 | * 0b001011..Divide by 12 | ||
| 4646 | * 0b001100..Divide by 13 | ||
| 4647 | * 0b001101..Divide by 14 | ||
| 4648 | * 0b001110..Divide by 15 | ||
| 4649 | * 0b001111..Divide by 16 | ||
| 4650 | * 0b010000..Divide by 17 | ||
| 4651 | * 0b010001..Divide by 18 | ||
| 4652 | * 0b010010..Divide by 19 | ||
| 4653 | * 0b010011..Divide by 20 | ||
| 4654 | * 0b010100..Divide by 21 | ||
| 4655 | * 0b010101..Divide by 22 | ||
| 4656 | * 0b010110..Divide by 23 | ||
| 4657 | * 0b010111..Divide by 24 | ||
| 4658 | * 0b011000..Divide by 25 | ||
| 4659 | * 0b011001..Divide by 26 | ||
| 4660 | * 0b011010..Divide by 27 | ||
| 4661 | * 0b011011..Divide by 28 | ||
| 4662 | * 0b011100..Divide by 29 | ||
| 4663 | * 0b011101..Divide by 30 | ||
| 4664 | * 0b011110..Divide by 31 | ||
| 4665 | * 0b011111..Divide by 32 | ||
| 4666 | * 0b100000..Divide by 33 | ||
| 4667 | * 0b100001..Divide by 34 | ||
| 4668 | * 0b100010..Divide by 35 | ||
| 4669 | * 0b100011..Divide by 36 | ||
| 4670 | * 0b100100..Divide by 37 | ||
| 4671 | * 0b100101..Divide by 38 | ||
| 4672 | * 0b100110..Divide by 39 | ||
| 4673 | * 0b100111..Divide by 40 | ||
| 4674 | * 0b101000..Divide by 41 | ||
| 4675 | * 0b101001..Divide by 42 | ||
| 4676 | * 0b101010..Divide by 43 | ||
| 4677 | * 0b101011..Divide by 44 | ||
| 4678 | * 0b101100..Divide by 45 | ||
| 4679 | * 0b101101..Divide by 46 | ||
| 4680 | * 0b101110..Divide by 47 | ||
| 4681 | * 0b101111..Divide by 48 | ||
| 4682 | * 0b110000..Divide by 49 | ||
| 4683 | * 0b110001..Divide by 50 | ||
| 4684 | * 0b110010..Divide by 51 | ||
| 4685 | * 0b110011..Divide by 52 | ||
| 4686 | * 0b110100..Divide by 53 | ||
| 4687 | * 0b110101..Divide by 54 | ||
| 4688 | * 0b110110..Divide by 55 | ||
| 4689 | * 0b110111..Divide by 56 | ||
| 4690 | * 0b111000..Divide by 57 | ||
| 4691 | * 0b111001..Divide by 58 | ||
| 4692 | * 0b111010..Divide by 59 | ||
| 4693 | * 0b111011..Divide by 60 | ||
| 4694 | * 0b111100..Divide by 61 | ||
| 4695 | * 0b111101..Divide by 62 | ||
| 4696 | * 0b111110..Divide by 63 | ||
| 4697 | * 0b111111..Divide by 64 | ||
| 4698 | */ | ||
| 4699 | #define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK) | ||
| 4700 | #define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U) | ||
| 4701 | #define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U) | ||
| 4702 | /*! SAI3_CLK_PRED | ||
| 4703 | * 0b000..divide by 1 | ||
| 4704 | * 0b001..divide by 2 | ||
| 4705 | * 0b010..divide by 3 | ||
| 4706 | * 0b011..divide by 4 | ||
| 4707 | * 0b100..divide by 5 | ||
| 4708 | * 0b101..divide by 6 | ||
| 4709 | * 0b110..divide by 7 | ||
| 4710 | * 0b111..divide by 8 | ||
| 4711 | */ | ||
| 4712 | #define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK) | ||
| 4713 | #define CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK (0xE000000U) | ||
| 4714 | #define CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT (25U) | ||
| 4715 | /*! FLEXIO1_CLK_PODF - Divider for flexio1 clock. Divider should be updated when output clock is gated. | ||
| 4716 | * 0b000..Divide by 1 | ||
| 4717 | * 0b001..Divide by 2 | ||
| 4718 | * 0b010..Divide by 3 | ||
| 4719 | * 0b011..Divide by 4 | ||
| 4720 | * 0b100..Divide by 5 | ||
| 4721 | * 0b101..Divide by 6 | ||
| 4722 | * 0b110..Divide by 7 | ||
| 4723 | * 0b111..Divide by 8 | ||
| 4724 | */ | ||
| 4725 | #define CCM_CS1CDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK) | ||
| 4726 | /*! @} */ | ||
| 4727 | |||
| 4728 | /*! @name CS2CDR - CCM Clock Divider Register */ | ||
| 4729 | /*! @{ */ | ||
| 4730 | #define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU) | ||
| 4731 | #define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U) | ||
| 4732 | /*! SAI2_CLK_PODF - Divider for sai2 clock podf. The input clock to this divider should be lower | ||
| 4733 | * than 300Mhz, the predivider can be used to achieve this. | ||
| 4734 | * 0b000000..Divide by 1 | ||
| 4735 | * 0b000001..Divide by 2 | ||
| 4736 | * 0b000010..Divide by 3 | ||
| 4737 | * 0b000011..Divide by 4 | ||
| 4738 | * 0b000100..Divide by 5 | ||
| 4739 | * 0b000101..Divide by 6 | ||
| 4740 | * 0b000110..Divide by 7 | ||
| 4741 | * 0b000111..Divide by 8 | ||
| 4742 | * 0b001000..Divide by 9 | ||
| 4743 | * 0b001001..Divide by 10 | ||
| 4744 | * 0b001010..Divide by 11 | ||
| 4745 | * 0b001011..Divide by 12 | ||
| 4746 | * 0b001100..Divide by 13 | ||
| 4747 | * 0b001101..Divide by 14 | ||
| 4748 | * 0b001110..Divide by 15 | ||
| 4749 | * 0b001111..Divide by 16 | ||
| 4750 | * 0b010000..Divide by 17 | ||
| 4751 | * 0b010001..Divide by 18 | ||
| 4752 | * 0b010010..Divide by 19 | ||
| 4753 | * 0b010011..Divide by 20 | ||
| 4754 | * 0b010100..Divide by 21 | ||
| 4755 | * 0b010101..Divide by 22 | ||
| 4756 | * 0b010110..Divide by 23 | ||
| 4757 | * 0b010111..Divide by 24 | ||
| 4758 | * 0b011000..Divide by 25 | ||
| 4759 | * 0b011001..Divide by 26 | ||
| 4760 | * 0b011010..Divide by 27 | ||
| 4761 | * 0b011011..Divide by 28 | ||
| 4762 | * 0b011100..Divide by 29 | ||
| 4763 | * 0b011101..Divide by 30 | ||
| 4764 | * 0b011110..Divide by 31 | ||
| 4765 | * 0b011111..Divide by 32 | ||
| 4766 | * 0b100000..Divide by 33 | ||
| 4767 | * 0b100001..Divide by 34 | ||
| 4768 | * 0b100010..Divide by 35 | ||
| 4769 | * 0b100011..Divide by 36 | ||
| 4770 | * 0b100100..Divide by 37 | ||
| 4771 | * 0b100101..Divide by 38 | ||
| 4772 | * 0b100110..Divide by 39 | ||
| 4773 | * 0b100111..Divide by 40 | ||
| 4774 | * 0b101000..Divide by 41 | ||
| 4775 | * 0b101001..Divide by 42 | ||
| 4776 | * 0b101010..Divide by 43 | ||
| 4777 | * 0b101011..Divide by 44 | ||
| 4778 | * 0b101100..Divide by 45 | ||
| 4779 | * 0b101101..Divide by 46 | ||
| 4780 | * 0b101110..Divide by 47 | ||
| 4781 | * 0b101111..Divide by 48 | ||
| 4782 | * 0b110000..Divide by 49 | ||
| 4783 | * 0b110001..Divide by 50 | ||
| 4784 | * 0b110010..Divide by 51 | ||
| 4785 | * 0b110011..Divide by 52 | ||
| 4786 | * 0b110100..Divide by 53 | ||
| 4787 | * 0b110101..Divide by 54 | ||
| 4788 | * 0b110110..Divide by 55 | ||
| 4789 | * 0b110111..Divide by 56 | ||
| 4790 | * 0b111000..Divide by 57 | ||
| 4791 | * 0b111001..Divide by 58 | ||
| 4792 | * 0b111010..Divide by 59 | ||
| 4793 | * 0b111011..Divide by 60 | ||
| 4794 | * 0b111100..Divide by 61 | ||
| 4795 | * 0b111101..Divide by 62 | ||
| 4796 | * 0b111110..Divide by 63 | ||
| 4797 | * 0b111111..Divide by 64 | ||
| 4798 | */ | ||
| 4799 | #define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK) | ||
| 4800 | #define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U) | ||
| 4801 | #define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U) | ||
| 4802 | /*! SAI2_CLK_PRED | ||
| 4803 | * 0b000..divide by 1 | ||
| 4804 | * 0b001..divide by 2 | ||
| 4805 | * 0b010..divide by 3 | ||
| 4806 | * 0b011..divide by 4 | ||
| 4807 | * 0b100..divide by 5 | ||
| 4808 | * 0b101..divide by 6 | ||
| 4809 | * 0b110..divide by 7 | ||
| 4810 | * 0b111..divide by 8 | ||
| 4811 | */ | ||
| 4812 | #define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK) | ||
| 4813 | /*! @} */ | ||
| 4814 | |||
| 4815 | /*! @name CDCDR - CCM D1 Clock Divider Register */ | ||
| 4816 | /*! @{ */ | ||
| 4817 | #define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U) | ||
| 4818 | #define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U) | ||
| 4819 | /*! SPDIF0_CLK_SEL | ||
| 4820 | * 0b00..derive clock from PLL4 | ||
| 4821 | * 0b01..derive clock from PLL3 PFD2 | ||
| 4822 | * 0b10..Reserved | ||
| 4823 | * 0b11..derive clock from pll3_sw_clk | ||
| 4824 | */ | ||
| 4825 | #define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK) | ||
| 4826 | #define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U) | ||
| 4827 | #define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U) | ||
| 4828 | /*! SPDIF0_CLK_PODF - Divider for spdif0 clock podf. Divider should be updated when output clock is gated. | ||
| 4829 | * 0b000..Divide by 1 | ||
| 4830 | * 0b001..Divide by 2 | ||
| 4831 | * 0b010..Divide by 3 | ||
| 4832 | * 0b011..Divide by 4 | ||
| 4833 | * 0b100..Divide by 5 | ||
| 4834 | * 0b101..Divide by 6 | ||
| 4835 | * 0b110..Divide by 7 | ||
| 4836 | * 0b111..Divide by 8 | ||
| 4837 | */ | ||
| 4838 | #define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK) | ||
| 4839 | #define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U) | ||
| 4840 | #define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U) | ||
| 4841 | /*! SPDIF0_CLK_PRED - Divider for spdif0 clock pred. Divider should be updated when output clock is gated. | ||
| 4842 | * 0b000..Divide by 1 | ||
| 4843 | * 0b001..Divide by 2 | ||
| 4844 | * 0b010..Divide by 3 | ||
| 4845 | * 0b011..Divide by 4 | ||
| 4846 | * 0b100..Divide by 5 | ||
| 4847 | * 0b101..Divide by 6 | ||
| 4848 | * 0b110..Divide by 7 | ||
| 4849 | * 0b111..Divide by 8 | ||
| 4850 | */ | ||
| 4851 | #define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK) | ||
| 4852 | /*! @} */ | ||
| 4853 | |||
| 4854 | /*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */ | ||
| 4855 | /*! @{ */ | ||
| 4856 | #define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U) | ||
| 4857 | #define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U) | ||
| 4858 | /*! LPI2C_CLK_SEL | ||
| 4859 | * 0b0..derive clock from pll3_60m | ||
| 4860 | * 0b1..derive clock from osc_clk | ||
| 4861 | */ | ||
| 4862 | #define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK) | ||
| 4863 | #define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U) | ||
| 4864 | #define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U) | ||
| 4865 | /*! LPI2C_CLK_PODF - Divider for lpi2c clock podf. Divider should be updated when output clock is | ||
| 4866 | * gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used | ||
| 4867 | * to achieve this. | ||
| 4868 | * 0b000000..Divide by 1 | ||
| 4869 | * 0b000001..Divide by 2 | ||
| 4870 | * 0b000010..Divide by 3 | ||
| 4871 | * 0b000011..Divide by 4 | ||
| 4872 | * 0b000100..Divide by 5 | ||
| 4873 | * 0b000101..Divide by 6 | ||
| 4874 | * 0b000110..Divide by 7 | ||
| 4875 | * 0b000111..Divide by 8 | ||
| 4876 | * 0b001000..Divide by 9 | ||
| 4877 | * 0b001001..Divide by 10 | ||
| 4878 | * 0b001010..Divide by 11 | ||
| 4879 | * 0b001011..Divide by 12 | ||
| 4880 | * 0b001100..Divide by 13 | ||
| 4881 | * 0b001101..Divide by 14 | ||
| 4882 | * 0b001110..Divide by 15 | ||
| 4883 | * 0b001111..Divide by 16 | ||
| 4884 | * 0b010000..Divide by 17 | ||
| 4885 | * 0b010001..Divide by 18 | ||
| 4886 | * 0b010010..Divide by 19 | ||
| 4887 | * 0b010011..Divide by 20 | ||
| 4888 | * 0b010100..Divide by 21 | ||
| 4889 | * 0b010101..Divide by 22 | ||
| 4890 | * 0b010110..Divide by 23 | ||
| 4891 | * 0b010111..Divide by 24 | ||
| 4892 | * 0b011000..Divide by 25 | ||
| 4893 | * 0b011001..Divide by 26 | ||
| 4894 | * 0b011010..Divide by 27 | ||
| 4895 | * 0b011011..Divide by 28 | ||
| 4896 | * 0b011100..Divide by 29 | ||
| 4897 | * 0b011101..Divide by 30 | ||
| 4898 | * 0b011110..Divide by 31 | ||
| 4899 | * 0b011111..Divide by 32 | ||
| 4900 | * 0b100000..Divide by 33 | ||
| 4901 | * 0b100001..Divide by 34 | ||
| 4902 | * 0b100010..Divide by 35 | ||
| 4903 | * 0b100011..Divide by 36 | ||
| 4904 | * 0b100100..Divide by 37 | ||
| 4905 | * 0b100101..Divide by 38 | ||
| 4906 | * 0b100110..Divide by 39 | ||
| 4907 | * 0b100111..Divide by 40 | ||
| 4908 | * 0b101000..Divide by 41 | ||
| 4909 | * 0b101001..Divide by 42 | ||
| 4910 | * 0b101010..Divide by 43 | ||
| 4911 | * 0b101011..Divide by 44 | ||
| 4912 | * 0b101100..Divide by 45 | ||
| 4913 | * 0b101101..Divide by 46 | ||
| 4914 | * 0b101110..Divide by 47 | ||
| 4915 | * 0b101111..Divide by 48 | ||
| 4916 | * 0b110000..Divide by 49 | ||
| 4917 | * 0b110001..Divide by 50 | ||
| 4918 | * 0b110010..Divide by 51 | ||
| 4919 | * 0b110011..Divide by 52 | ||
| 4920 | * 0b110100..Divide by 53 | ||
| 4921 | * 0b110101..Divide by 54 | ||
| 4922 | * 0b110110..Divide by 55 | ||
| 4923 | * 0b110111..Divide by 56 | ||
| 4924 | * 0b111000..Divide by 57 | ||
| 4925 | * 0b111001..Divide by 58 | ||
| 4926 | * 0b111010..Divide by 59 | ||
| 4927 | * 0b111011..Divide by 60 | ||
| 4928 | * 0b111100..Divide by 61 | ||
| 4929 | * 0b111101..Divide by 62 | ||
| 4930 | * 0b111110..Divide by 63 | ||
| 4931 | * 0b111111..Divide by 64 | ||
| 4932 | */ | ||
| 4933 | #define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK) | ||
| 4934 | /*! @} */ | ||
| 4935 | |||
| 4936 | /*! @name CDHIPR - CCM Divider Handshake In-Process Register */ | ||
| 4937 | /*! @{ */ | ||
| 4938 | #define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U) | ||
| 4939 | #define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U) | ||
| 4940 | /*! SEMC_PODF_BUSY | ||
| 4941 | * 0b0..divider is not busy and its value represents the actual division. | ||
| 4942 | * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous | ||
| 4943 | * value of the division factor, and after the handshake the written value of the semc_podf will be applied. | ||
| 4944 | */ | ||
| 4945 | #define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK) | ||
| 4946 | #define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U) | ||
| 4947 | #define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U) | ||
| 4948 | /*! AHB_PODF_BUSY | ||
| 4949 | * 0b0..divider is not busy and its value represents the actual division. | ||
| 4950 | * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous | ||
| 4951 | * value of the division factor, and after the handshake the written value of the ahb_podf will be applied. | ||
| 4952 | */ | ||
| 4953 | #define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK) | ||
| 4954 | #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U) | ||
| 4955 | #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U) | ||
| 4956 | /*! PERIPH2_CLK_SEL_BUSY | ||
| 4957 | * 0b0..mux is not busy and its value represents the actual division. | ||
| 4958 | * 0b1..mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the | ||
| 4959 | * previous value of select, and after the handshake periph2_clk_sel value will be applied. | ||
| 4960 | */ | ||
| 4961 | #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK) | ||
| 4962 | #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U) | ||
| 4963 | #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U) | ||
| 4964 | /*! PERIPH_CLK_SEL_BUSY | ||
| 4965 | * 0b0..mux is not busy and its value represents the actual division. | ||
| 4966 | * 0b1..mux is busy with handshake process with module. The value read in the periph_clk_sel represents the | ||
| 4967 | * previous value of select, and after the handshake periph_clk_sel value will be applied. | ||
| 4968 | */ | ||
| 4969 | #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK) | ||
| 4970 | #define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U) | ||
| 4971 | #define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U) | ||
| 4972 | /*! ARM_PODF_BUSY | ||
| 4973 | * 0b0..divider is not busy and its value represents the actual division. | ||
| 4974 | * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous | ||
| 4975 | * value of the division factor, and after the handshake the written value of the arm_podf will be applied. | ||
| 4976 | */ | ||
| 4977 | #define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK) | ||
| 4978 | /*! @} */ | ||
| 4979 | |||
| 4980 | /*! @name CLPCR - CCM Low Power Control Register */ | ||
| 4981 | /*! @{ */ | ||
| 4982 | #define CCM_CLPCR_LPM_MASK (0x3U) | ||
| 4983 | #define CCM_CLPCR_LPM_SHIFT (0U) | ||
| 4984 | /*! LPM | ||
| 4985 | * 0b00..Remain in run mode | ||
| 4986 | * 0b01..Transfer to wait mode | ||
| 4987 | * 0b10..Transfer to stop mode | ||
| 4988 | * 0b11..Reserved | ||
| 4989 | */ | ||
| 4990 | #define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK) | ||
| 4991 | #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U) | ||
| 4992 | #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U) | ||
| 4993 | /*! ARM_CLK_DIS_ON_LPM | ||
| 4994 | * 0b0..Arm clock enabled on wait mode. | ||
| 4995 | * 0b1..Arm clock disabled on wait mode. . | ||
| 4996 | */ | ||
| 4997 | #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK) | ||
| 4998 | #define CCM_CLPCR_SBYOS_MASK (0x40U) | ||
| 4999 | #define CCM_CLPCR_SBYOS_SHIFT (6U) | ||
| 5000 | /*! SBYOS | ||
| 5001 | * 0b0..On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain | ||
| 5002 | * asserted - '0' and cosc_pwrdown will remain de asserted - '0') | ||
| 5003 | * 0b1..On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be | ||
| 5004 | * deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will | ||
| 5005 | * be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will | ||
| 5006 | * continue with the exit from the STOP mode process. | ||
| 5007 | */ | ||
| 5008 | #define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK) | ||
| 5009 | #define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U) | ||
| 5010 | #define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U) | ||
| 5011 | /*! DIS_REF_OSC | ||
| 5012 | * 0b0..external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'. | ||
| 5013 | * 0b1..external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1' | ||
| 5014 | */ | ||
| 5015 | #define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK) | ||
| 5016 | #define CCM_CLPCR_VSTBY_MASK (0x100U) | ||
| 5017 | #define CCM_CLPCR_VSTBY_SHIFT (8U) | ||
| 5018 | /*! VSTBY | ||
| 5019 | * 0b0..Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0') | ||
| 5020 | * 0b1..Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1'). | ||
| 5021 | */ | ||
| 5022 | #define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK) | ||
| 5023 | #define CCM_CLPCR_STBY_COUNT_MASK (0x600U) | ||
| 5024 | #define CCM_CLPCR_STBY_COUNT_SHIFT (9U) | ||
| 5025 | /*! STBY_COUNT | ||
| 5026 | * 0b00..CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles | ||
| 5027 | * 0b01..CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles | ||
| 5028 | * 0b10..CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles | ||
| 5029 | * 0b11..CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles | ||
| 5030 | */ | ||
| 5031 | #define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK) | ||
| 5032 | #define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U) | ||
| 5033 | #define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U) | ||
| 5034 | /*! COSC_PWRDOWN | ||
| 5035 | * 0b0..On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'. | ||
| 5036 | * 0b1..On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'. | ||
| 5037 | */ | ||
| 5038 | #define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK) | ||
| 5039 | #define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U) | ||
| 5040 | #define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U) | ||
| 5041 | #define CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK) | ||
| 5042 | #define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U) | ||
| 5043 | #define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U) | ||
| 5044 | #define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK) | ||
| 5045 | #define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U) | ||
| 5046 | #define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U) | ||
| 5047 | /*! MASK_CORE0_WFI | ||
| 5048 | * 0b0..WFI of core0 is not masked | ||
| 5049 | * 0b1..WFI of core0 is masked | ||
| 5050 | */ | ||
| 5051 | #define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK) | ||
| 5052 | #define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U) | ||
| 5053 | #define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U) | ||
| 5054 | /*! MASK_SCU_IDLE | ||
| 5055 | * 0b1..SCU IDLE is masked | ||
| 5056 | * 0b0..SCU IDLE is not masked | ||
| 5057 | */ | ||
| 5058 | #define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK) | ||
| 5059 | #define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U) | ||
| 5060 | #define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U) | ||
| 5061 | /*! MASK_L2CC_IDLE | ||
| 5062 | * 0b1..L2CC IDLE is masked | ||
| 5063 | * 0b0..L2CC IDLE is not masked | ||
| 5064 | */ | ||
| 5065 | #define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK) | ||
| 5066 | /*! @} */ | ||
| 5067 | |||
| 5068 | /*! @name CISR - CCM Interrupt Status Register */ | ||
| 5069 | /*! @{ */ | ||
| 5070 | #define CCM_CISR_LRF_PLL_MASK (0x1U) | ||
| 5071 | #define CCM_CISR_LRF_PLL_SHIFT (0U) | ||
| 5072 | /*! LRF_PLL | ||
| 5073 | * 0b0..interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs | ||
| 5074 | * 0b1..interrupt generated due to lock ready of all enabled and not bypaseed PLLs | ||
| 5075 | */ | ||
| 5076 | #define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK) | ||
| 5077 | #define CCM_CISR_COSC_READY_MASK (0x40U) | ||
| 5078 | #define CCM_CISR_COSC_READY_SHIFT (6U) | ||
| 5079 | /*! COSC_READY | ||
| 5080 | * 0b0..interrupt is not generated due to on board oscillator ready | ||
| 5081 | * 0b1..interrupt generated due to on board oscillator ready | ||
| 5082 | */ | ||
| 5083 | #define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK) | ||
| 5084 | #define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U) | ||
| 5085 | #define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U) | ||
| 5086 | /*! SEMC_PODF_LOADED | ||
| 5087 | * 0b0..interrupt is not generated due to frequency change of semc_podf | ||
| 5088 | * 0b1..interrupt generated due to frequency change of semc_podf | ||
| 5089 | */ | ||
| 5090 | #define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK) | ||
| 5091 | #define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) | ||
| 5092 | #define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) | ||
| 5093 | /*! PERIPH2_CLK_SEL_LOADED | ||
| 5094 | * 0b0..interrupt is not generated due to frequency change of periph2_clk_sel | ||
| 5095 | * 0b1..interrupt generated due to frequency change of periph2_clk_sel | ||
| 5096 | */ | ||
| 5097 | #define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK) | ||
| 5098 | #define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U) | ||
| 5099 | #define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U) | ||
| 5100 | /*! AHB_PODF_LOADED | ||
| 5101 | * 0b0..interrupt is not generated due to frequency change of ahb_podf | ||
| 5102 | * 0b1..interrupt generated due to frequency change of ahb_podf | ||
| 5103 | */ | ||
| 5104 | #define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK) | ||
| 5105 | #define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) | ||
| 5106 | #define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U) | ||
| 5107 | /*! PERIPH_CLK_SEL_LOADED | ||
| 5108 | * 0b0..interrupt is not generated due to update of periph_clk_sel. | ||
| 5109 | * 0b1..interrupt generated due to update of periph_clk_sel. | ||
| 5110 | */ | ||
| 5111 | #define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK) | ||
| 5112 | #define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U) | ||
| 5113 | #define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U) | ||
| 5114 | /*! ARM_PODF_LOADED | ||
| 5115 | * 0b0..interrupt is not generated due to frequency change of arm_podf | ||
| 5116 | * 0b1..interrupt generated due to frequency change of arm_podf | ||
| 5117 | */ | ||
| 5118 | #define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK) | ||
| 5119 | /*! @} */ | ||
| 5120 | |||
| 5121 | /*! @name CIMR - CCM Interrupt Mask Register */ | ||
| 5122 | /*! @{ */ | ||
| 5123 | #define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U) | ||
| 5124 | #define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U) | ||
| 5125 | /*! MASK_LRF_PLL | ||
| 5126 | * 0b0..don't mask interrupt due to lrf of PLLs - interrupt will be created | ||
| 5127 | * 0b1..mask interrupt due to lrf of PLLs | ||
| 5128 | */ | ||
| 5129 | #define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK) | ||
| 5130 | #define CCM_CIMR_MASK_COSC_READY_MASK (0x40U) | ||
| 5131 | #define CCM_CIMR_MASK_COSC_READY_SHIFT (6U) | ||
| 5132 | /*! MASK_COSC_READY | ||
| 5133 | * 0b0..don't mask interrupt due to on board oscillator ready - interrupt will be created | ||
| 5134 | * 0b1..mask interrupt due to on board oscillator ready | ||
| 5135 | */ | ||
| 5136 | #define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK) | ||
| 5137 | #define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U) | ||
| 5138 | #define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U) | ||
| 5139 | /*! MASK_SEMC_PODF_LOADED | ||
| 5140 | * 0b0..don't mask interrupt due to frequency change of semc_podf - interrupt will be created | ||
| 5141 | * 0b1..mask interrupt due to frequency change of semc_podf | ||
| 5142 | */ | ||
| 5143 | #define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK) | ||
| 5144 | #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) | ||
| 5145 | #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) | ||
| 5146 | /*! MASK_PERIPH2_CLK_SEL_LOADED | ||
| 5147 | * 0b0..don't mask interrupt due to update of periph2_clk_sel - interrupt will be created | ||
| 5148 | * 0b1..mask interrupt due to update of periph2_clk_sel | ||
| 5149 | */ | ||
| 5150 | #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK) | ||
| 5151 | #define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U) | ||
| 5152 | #define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U) | ||
| 5153 | /*! MASK_AHB_PODF_LOADED | ||
| 5154 | * 0b0..don't mask interrupt due to frequency change of ahb_podf - interrupt will be created | ||
| 5155 | * 0b1..mask interrupt due to frequency change of ahb_podf | ||
| 5156 | */ | ||
| 5157 | #define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK) | ||
| 5158 | #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) | ||
| 5159 | #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U) | ||
| 5160 | /*! MASK_PERIPH_CLK_SEL_LOADED | ||
| 5161 | * 0b0..don't mask interrupt due to update of periph_clk_sel - interrupt will be created | ||
| 5162 | * 0b1..mask interrupt due to update of periph_clk_sel | ||
| 5163 | */ | ||
| 5164 | #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK) | ||
| 5165 | #define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U) | ||
| 5166 | #define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U) | ||
| 5167 | /*! ARM_PODF_LOADED | ||
| 5168 | * 0b0..don't mask interrupt due to frequency change of arm_podf - interrupt will be created | ||
| 5169 | * 0b1..mask interrupt due to frequency change of arm_podf | ||
| 5170 | */ | ||
| 5171 | #define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK) | ||
| 5172 | /*! @} */ | ||
| 5173 | |||
| 5174 | /*! @name CCOSR - CCM Clock Output Source Register */ | ||
| 5175 | /*! @{ */ | ||
| 5176 | #define CCM_CCOSR_CLKO1_SEL_MASK (0xFU) | ||
| 5177 | #define CCM_CCOSR_CLKO1_SEL_SHIFT (0U) | ||
| 5178 | /*! CLKO1_SEL | ||
| 5179 | * 0b0000..pll3_sw_clk (divided by 2) | ||
| 5180 | * 0b0001..PLL2 (divided by 2) | ||
| 5181 | * 0b0010..ENET PLL (divided by 2) | ||
| 5182 | * 0b0011..Reserved | ||
| 5183 | * 0b0101..semc_clk_root | ||
| 5184 | * 0b0110..Reserved | ||
| 5185 | * 0b1010..Reserved | ||
| 5186 | * 0b1011..ahb_clk_root | ||
| 5187 | * 0b1100..ipg_clk_root | ||
| 5188 | * 0b1101..perclk_root | ||
| 5189 | * 0b1110..Reserved | ||
| 5190 | * 0b1111..pll4_main_clk | ||
| 5191 | */ | ||
| 5192 | #define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK) | ||
| 5193 | #define CCM_CCOSR_CLKO1_DIV_MASK (0x70U) | ||
| 5194 | #define CCM_CCOSR_CLKO1_DIV_SHIFT (4U) | ||
| 5195 | /*! CLKO1_DIV | ||
| 5196 | * 0b000..divide by 1 | ||
| 5197 | * 0b001..divide by 2 | ||
| 5198 | * 0b010..divide by 3 | ||
| 5199 | * 0b011..divide by 4 | ||
| 5200 | * 0b100..divide by 5 | ||
| 5201 | * 0b101..divide by 6 | ||
| 5202 | * 0b110..divide by 7 | ||
| 5203 | * 0b111..divide by 8 | ||
| 5204 | */ | ||
| 5205 | #define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK) | ||
| 5206 | #define CCM_CCOSR_CLKO1_EN_MASK (0x80U) | ||
| 5207 | #define CCM_CCOSR_CLKO1_EN_SHIFT (7U) | ||
| 5208 | /*! CLKO1_EN | ||
| 5209 | * 0b0..CCM_CLKO1 disabled. | ||
| 5210 | * 0b1..CCM_CLKO1 enabled. | ||
| 5211 | */ | ||
| 5212 | #define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK) | ||
| 5213 | #define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U) | ||
| 5214 | #define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U) | ||
| 5215 | /*! CLK_OUT_SEL | ||
| 5216 | * 0b0..CCM_CLKO1 output drives CCM_CLKO1 clock | ||
| 5217 | * 0b1..CCM_CLKO1 output drives CCM_CLKO2 clock | ||
| 5218 | */ | ||
| 5219 | #define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK) | ||
| 5220 | #define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U) | ||
| 5221 | #define CCM_CCOSR_CLKO2_SEL_SHIFT (16U) | ||
| 5222 | /*! CLKO2_SEL | ||
| 5223 | * 0b00011..usdhc1_clk_root | ||
| 5224 | * 0b00101..Reserved | ||
| 5225 | * 0b00110..lpi2c_clk_root | ||
| 5226 | * 0b01110..osc_clk | ||
| 5227 | * 0b10000..lpspi_clk_root | ||
| 5228 | * 0b10001..usdhc2_clk_root | ||
| 5229 | * 0b10010..sai1_clk_root | ||
| 5230 | * 0b10011..sai2_clk_root | ||
| 5231 | * 0b10100..sai3_clk_root | ||
| 5232 | * 0b10110..trace_clk_root | ||
| 5233 | * 0b10111..can_clk_root | ||
| 5234 | * 0b11011..flexspi_clk_root | ||
| 5235 | * 0b11100..uart_clk_root | ||
| 5236 | * 0b11101..spdif0_clk_root | ||
| 5237 | * 0b11111..Reserved | ||
| 5238 | */ | ||
| 5239 | #define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK) | ||
| 5240 | #define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U) | ||
| 5241 | #define CCM_CCOSR_CLKO2_DIV_SHIFT (21U) | ||
| 5242 | /*! CLKO2_DIV | ||
| 5243 | * 0b000..divide by 1 | ||
| 5244 | * 0b001..divide by 2 | ||
| 5245 | * 0b010..divide by 3 | ||
| 5246 | * 0b011..divide by 4 | ||
| 5247 | * 0b100..divide by 5 | ||
| 5248 | * 0b101..divide by 6 | ||
| 5249 | * 0b110..divide by 7 | ||
| 5250 | * 0b111..divide by 8 | ||
| 5251 | */ | ||
| 5252 | #define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK) | ||
| 5253 | #define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U) | ||
| 5254 | #define CCM_CCOSR_CLKO2_EN_SHIFT (24U) | ||
| 5255 | /*! CLKO2_EN | ||
| 5256 | * 0b0..CCM_CLKO2 disabled. | ||
| 5257 | * 0b1..CCM_CLKO2 enabled. | ||
| 5258 | */ | ||
| 5259 | #define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK) | ||
| 5260 | /*! @} */ | ||
| 5261 | |||
| 5262 | /*! @name CGPR - CCM General Purpose Register */ | ||
| 5263 | /*! @{ */ | ||
| 5264 | #define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U) | ||
| 5265 | #define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U) | ||
| 5266 | /*! PMIC_DELAY_SCALER | ||
| 5267 | * 0b0..clock is not divided | ||
| 5268 | * 0b1..clock is divided /8 | ||
| 5269 | */ | ||
| 5270 | #define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK) | ||
| 5271 | #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U) | ||
| 5272 | #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U) | ||
| 5273 | /*! EFUSE_PROG_SUPPLY_GATE | ||
| 5274 | * 0b0..fuse programing supply voltage is gated off to the efuse module | ||
| 5275 | * 0b1..allow fuse programing. | ||
| 5276 | */ | ||
| 5277 | #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK) | ||
| 5278 | #define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U) | ||
| 5279 | #define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U) | ||
| 5280 | /*! SYS_MEM_DS_CTRL | ||
| 5281 | * 0b00..Disable memory DS mode always | ||
| 5282 | * 0b01..Enable memory (outside Arm platform) DS mode when system STOP and PLL are disabled | ||
| 5283 | * 0b1x..enable memory (outside Arm platform) DS mode when system is in STOP mode | ||
| 5284 | */ | ||
| 5285 | #define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK) | ||
| 5286 | #define CCM_CGPR_FPL_MASK (0x10000U) | ||
| 5287 | #define CCM_CGPR_FPL_SHIFT (16U) | ||
| 5288 | /*! FPL - Fast PLL enable. | ||
| 5289 | * 0b0..Engage PLL enable default way. | ||
| 5290 | * 0b1..Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode. | ||
| 5291 | */ | ||
| 5292 | #define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK) | ||
| 5293 | #define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U) | ||
| 5294 | #define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U) | ||
| 5295 | /*! INT_MEM_CLK_LPM | ||
| 5296 | * 0b0..Disable the clock to the Arm platform memories when entering Low Power Mode | ||
| 5297 | * 0b1..Keep the clocks to the Arm platform memories enabled only if an interrupt is pending when entering Low | ||
| 5298 | * Power Modes (WAIT and STOP without power gating) | ||
| 5299 | */ | ||
| 5300 | #define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK) | ||
| 5301 | /*! @} */ | ||
| 5302 | |||
| 5303 | /*! @name CCGR0 - CCM Clock Gating Register 0 */ | ||
| 5304 | /*! @{ */ | ||
| 5305 | #define CCM_CCGR0_CG0_MASK (0x3U) | ||
| 5306 | #define CCM_CCGR0_CG0_SHIFT (0U) | ||
| 5307 | #define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK) | ||
| 5308 | #define CCM_CCGR0_CG1_MASK (0xCU) | ||
| 5309 | #define CCM_CCGR0_CG1_SHIFT (2U) | ||
| 5310 | #define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK) | ||
| 5311 | #define CCM_CCGR0_CG2_MASK (0x30U) | ||
| 5312 | #define CCM_CCGR0_CG2_SHIFT (4U) | ||
| 5313 | #define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK) | ||
| 5314 | #define CCM_CCGR0_CG3_MASK (0xC0U) | ||
| 5315 | #define CCM_CCGR0_CG3_SHIFT (6U) | ||
| 5316 | #define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK) | ||
| 5317 | #define CCM_CCGR0_CG4_MASK (0x300U) | ||
| 5318 | #define CCM_CCGR0_CG4_SHIFT (8U) | ||
| 5319 | #define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK) | ||
| 5320 | #define CCM_CCGR0_CG5_MASK (0xC00U) | ||
| 5321 | #define CCM_CCGR0_CG5_SHIFT (10U) | ||
| 5322 | #define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK) | ||
| 5323 | #define CCM_CCGR0_CG6_MASK (0x3000U) | ||
| 5324 | #define CCM_CCGR0_CG6_SHIFT (12U) | ||
| 5325 | #define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK) | ||
| 5326 | #define CCM_CCGR0_CG7_MASK (0xC000U) | ||
| 5327 | #define CCM_CCGR0_CG7_SHIFT (14U) | ||
| 5328 | #define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK) | ||
| 5329 | #define CCM_CCGR0_CG8_MASK (0x30000U) | ||
| 5330 | #define CCM_CCGR0_CG8_SHIFT (16U) | ||
| 5331 | #define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK) | ||
| 5332 | #define CCM_CCGR0_CG9_MASK (0xC0000U) | ||
| 5333 | #define CCM_CCGR0_CG9_SHIFT (18U) | ||
| 5334 | #define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK) | ||
| 5335 | #define CCM_CCGR0_CG10_MASK (0x300000U) | ||
| 5336 | #define CCM_CCGR0_CG10_SHIFT (20U) | ||
| 5337 | #define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK) | ||
| 5338 | #define CCM_CCGR0_CG11_MASK (0xC00000U) | ||
| 5339 | #define CCM_CCGR0_CG11_SHIFT (22U) | ||
| 5340 | #define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK) | ||
| 5341 | #define CCM_CCGR0_CG12_MASK (0x3000000U) | ||
| 5342 | #define CCM_CCGR0_CG12_SHIFT (24U) | ||
| 5343 | #define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK) | ||
| 5344 | #define CCM_CCGR0_CG13_MASK (0xC000000U) | ||
| 5345 | #define CCM_CCGR0_CG13_SHIFT (26U) | ||
| 5346 | #define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK) | ||
| 5347 | #define CCM_CCGR0_CG14_MASK (0x30000000U) | ||
| 5348 | #define CCM_CCGR0_CG14_SHIFT (28U) | ||
| 5349 | #define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK) | ||
| 5350 | #define CCM_CCGR0_CG15_MASK (0xC0000000U) | ||
| 5351 | #define CCM_CCGR0_CG15_SHIFT (30U) | ||
| 5352 | #define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK) | ||
| 5353 | /*! @} */ | ||
| 5354 | |||
| 5355 | /*! @name CCGR1 - CCM Clock Gating Register 1 */ | ||
| 5356 | /*! @{ */ | ||
| 5357 | #define CCM_CCGR1_CG0_MASK (0x3U) | ||
| 5358 | #define CCM_CCGR1_CG0_SHIFT (0U) | ||
| 5359 | #define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK) | ||
| 5360 | #define CCM_CCGR1_CG1_MASK (0xCU) | ||
| 5361 | #define CCM_CCGR1_CG1_SHIFT (2U) | ||
| 5362 | #define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK) | ||
| 5363 | #define CCM_CCGR1_CG2_MASK (0x30U) | ||
| 5364 | #define CCM_CCGR1_CG2_SHIFT (4U) | ||
| 5365 | #define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK) | ||
| 5366 | #define CCM_CCGR1_CG3_MASK (0xC0U) | ||
| 5367 | #define CCM_CCGR1_CG3_SHIFT (6U) | ||
| 5368 | #define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK) | ||
| 5369 | #define CCM_CCGR1_CG4_MASK (0x300U) | ||
| 5370 | #define CCM_CCGR1_CG4_SHIFT (8U) | ||
| 5371 | #define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK) | ||
| 5372 | #define CCM_CCGR1_CG5_MASK (0xC00U) | ||
| 5373 | #define CCM_CCGR1_CG5_SHIFT (10U) | ||
| 5374 | #define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK) | ||
| 5375 | #define CCM_CCGR1_CG6_MASK (0x3000U) | ||
| 5376 | #define CCM_CCGR1_CG6_SHIFT (12U) | ||
| 5377 | #define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK) | ||
| 5378 | #define CCM_CCGR1_CG7_MASK (0xC000U) | ||
| 5379 | #define CCM_CCGR1_CG7_SHIFT (14U) | ||
| 5380 | #define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK) | ||
| 5381 | #define CCM_CCGR1_CG8_MASK (0x30000U) | ||
| 5382 | #define CCM_CCGR1_CG8_SHIFT (16U) | ||
| 5383 | #define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK) | ||
| 5384 | #define CCM_CCGR1_CG9_MASK (0xC0000U) | ||
| 5385 | #define CCM_CCGR1_CG9_SHIFT (18U) | ||
| 5386 | #define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK) | ||
| 5387 | #define CCM_CCGR1_CG10_MASK (0x300000U) | ||
| 5388 | #define CCM_CCGR1_CG10_SHIFT (20U) | ||
| 5389 | #define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK) | ||
| 5390 | #define CCM_CCGR1_CG11_MASK (0xC00000U) | ||
| 5391 | #define CCM_CCGR1_CG11_SHIFT (22U) | ||
| 5392 | #define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK) | ||
| 5393 | #define CCM_CCGR1_CG12_MASK (0x3000000U) | ||
| 5394 | #define CCM_CCGR1_CG12_SHIFT (24U) | ||
| 5395 | #define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK) | ||
| 5396 | #define CCM_CCGR1_CG13_MASK (0xC000000U) | ||
| 5397 | #define CCM_CCGR1_CG13_SHIFT (26U) | ||
| 5398 | #define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK) | ||
| 5399 | #define CCM_CCGR1_CG14_MASK (0x30000000U) | ||
| 5400 | #define CCM_CCGR1_CG14_SHIFT (28U) | ||
| 5401 | #define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK) | ||
| 5402 | #define CCM_CCGR1_CG15_MASK (0xC0000000U) | ||
| 5403 | #define CCM_CCGR1_CG15_SHIFT (30U) | ||
| 5404 | #define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK) | ||
| 5405 | /*! @} */ | ||
| 5406 | |||
| 5407 | /*! @name CCGR2 - CCM Clock Gating Register 2 */ | ||
| 5408 | /*! @{ */ | ||
| 5409 | #define CCM_CCGR2_CG0_MASK (0x3U) | ||
| 5410 | #define CCM_CCGR2_CG0_SHIFT (0U) | ||
| 5411 | #define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK) | ||
| 5412 | #define CCM_CCGR2_CG1_MASK (0xCU) | ||
| 5413 | #define CCM_CCGR2_CG1_SHIFT (2U) | ||
| 5414 | #define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK) | ||
| 5415 | #define CCM_CCGR2_CG2_MASK (0x30U) | ||
| 5416 | #define CCM_CCGR2_CG2_SHIFT (4U) | ||
| 5417 | #define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK) | ||
| 5418 | #define CCM_CCGR2_CG3_MASK (0xC0U) | ||
| 5419 | #define CCM_CCGR2_CG3_SHIFT (6U) | ||
| 5420 | #define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK) | ||
| 5421 | #define CCM_CCGR2_CG4_MASK (0x300U) | ||
| 5422 | #define CCM_CCGR2_CG4_SHIFT (8U) | ||
| 5423 | #define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK) | ||
| 5424 | #define CCM_CCGR2_CG5_MASK (0xC00U) | ||
| 5425 | #define CCM_CCGR2_CG5_SHIFT (10U) | ||
| 5426 | #define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK) | ||
| 5427 | #define CCM_CCGR2_CG6_MASK (0x3000U) | ||
| 5428 | #define CCM_CCGR2_CG6_SHIFT (12U) | ||
| 5429 | #define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK) | ||
| 5430 | #define CCM_CCGR2_CG7_MASK (0xC000U) | ||
| 5431 | #define CCM_CCGR2_CG7_SHIFT (14U) | ||
| 5432 | #define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK) | ||
| 5433 | #define CCM_CCGR2_CG8_MASK (0x30000U) | ||
| 5434 | #define CCM_CCGR2_CG8_SHIFT (16U) | ||
| 5435 | #define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK) | ||
| 5436 | #define CCM_CCGR2_CG9_MASK (0xC0000U) | ||
| 5437 | #define CCM_CCGR2_CG9_SHIFT (18U) | ||
| 5438 | #define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK) | ||
| 5439 | #define CCM_CCGR2_CG10_MASK (0x300000U) | ||
| 5440 | #define CCM_CCGR2_CG10_SHIFT (20U) | ||
| 5441 | #define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK) | ||
| 5442 | #define CCM_CCGR2_CG11_MASK (0xC00000U) | ||
| 5443 | #define CCM_CCGR2_CG11_SHIFT (22U) | ||
| 5444 | #define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK) | ||
| 5445 | #define CCM_CCGR2_CG12_MASK (0x3000000U) | ||
| 5446 | #define CCM_CCGR2_CG12_SHIFT (24U) | ||
| 5447 | #define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK) | ||
| 5448 | #define CCM_CCGR2_CG13_MASK (0xC000000U) | ||
| 5449 | #define CCM_CCGR2_CG13_SHIFT (26U) | ||
| 5450 | #define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK) | ||
| 5451 | #define CCM_CCGR2_CG14_MASK (0x30000000U) | ||
| 5452 | #define CCM_CCGR2_CG14_SHIFT (28U) | ||
| 5453 | #define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK) | ||
| 5454 | #define CCM_CCGR2_CG15_MASK (0xC0000000U) | ||
| 5455 | #define CCM_CCGR2_CG15_SHIFT (30U) | ||
| 5456 | #define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK) | ||
| 5457 | /*! @} */ | ||
| 5458 | |||
| 5459 | /*! @name CCGR3 - CCM Clock Gating Register 3 */ | ||
| 5460 | /*! @{ */ | ||
| 5461 | #define CCM_CCGR3_CG0_MASK (0x3U) | ||
| 5462 | #define CCM_CCGR3_CG0_SHIFT (0U) | ||
| 5463 | #define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK) | ||
| 5464 | #define CCM_CCGR3_CG1_MASK (0xCU) | ||
| 5465 | #define CCM_CCGR3_CG1_SHIFT (2U) | ||
| 5466 | #define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK) | ||
| 5467 | #define CCM_CCGR3_CG2_MASK (0x30U) | ||
| 5468 | #define CCM_CCGR3_CG2_SHIFT (4U) | ||
| 5469 | #define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK) | ||
| 5470 | #define CCM_CCGR3_CG3_MASK (0xC0U) | ||
| 5471 | #define CCM_CCGR3_CG3_SHIFT (6U) | ||
| 5472 | #define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK) | ||
| 5473 | #define CCM_CCGR3_CG4_MASK (0x300U) | ||
| 5474 | #define CCM_CCGR3_CG4_SHIFT (8U) | ||
| 5475 | #define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK) | ||
| 5476 | #define CCM_CCGR3_CG5_MASK (0xC00U) | ||
| 5477 | #define CCM_CCGR3_CG5_SHIFT (10U) | ||
| 5478 | #define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK) | ||
| 5479 | #define CCM_CCGR3_CG6_MASK (0x3000U) | ||
| 5480 | #define CCM_CCGR3_CG6_SHIFT (12U) | ||
| 5481 | #define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK) | ||
| 5482 | #define CCM_CCGR3_CG7_MASK (0xC000U) | ||
| 5483 | #define CCM_CCGR3_CG7_SHIFT (14U) | ||
| 5484 | #define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK) | ||
| 5485 | #define CCM_CCGR3_CG8_MASK (0x30000U) | ||
| 5486 | #define CCM_CCGR3_CG8_SHIFT (16U) | ||
| 5487 | #define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK) | ||
| 5488 | #define CCM_CCGR3_CG9_MASK (0xC0000U) | ||
| 5489 | #define CCM_CCGR3_CG9_SHIFT (18U) | ||
| 5490 | #define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK) | ||
| 5491 | #define CCM_CCGR3_CG10_MASK (0x300000U) | ||
| 5492 | #define CCM_CCGR3_CG10_SHIFT (20U) | ||
| 5493 | #define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK) | ||
| 5494 | #define CCM_CCGR3_CG11_MASK (0xC00000U) | ||
| 5495 | #define CCM_CCGR3_CG11_SHIFT (22U) | ||
| 5496 | #define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK) | ||
| 5497 | #define CCM_CCGR3_CG12_MASK (0x3000000U) | ||
| 5498 | #define CCM_CCGR3_CG12_SHIFT (24U) | ||
| 5499 | #define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK) | ||
| 5500 | #define CCM_CCGR3_CG13_MASK (0xC000000U) | ||
| 5501 | #define CCM_CCGR3_CG13_SHIFT (26U) | ||
| 5502 | #define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK) | ||
| 5503 | #define CCM_CCGR3_CG14_MASK (0x30000000U) | ||
| 5504 | #define CCM_CCGR3_CG14_SHIFT (28U) | ||
| 5505 | /*! CG14 - The OCRAM clock cannot be turned off when the CM cache is running on this device. | ||
| 5506 | */ | ||
| 5507 | #define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK) | ||
| 5508 | #define CCM_CCGR3_CG15_MASK (0xC0000000U) | ||
| 5509 | #define CCM_CCGR3_CG15_SHIFT (30U) | ||
| 5510 | #define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK) | ||
| 5511 | /*! @} */ | ||
| 5512 | |||
| 5513 | /*! @name CCGR4 - CCM Clock Gating Register 4 */ | ||
| 5514 | /*! @{ */ | ||
| 5515 | #define CCM_CCGR4_CG0_MASK (0x3U) | ||
| 5516 | #define CCM_CCGR4_CG0_SHIFT (0U) | ||
| 5517 | #define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK) | ||
| 5518 | #define CCM_CCGR4_CG1_MASK (0xCU) | ||
| 5519 | #define CCM_CCGR4_CG1_SHIFT (2U) | ||
| 5520 | #define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK) | ||
| 5521 | #define CCM_CCGR4_CG2_MASK (0x30U) | ||
| 5522 | #define CCM_CCGR4_CG2_SHIFT (4U) | ||
| 5523 | #define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK) | ||
| 5524 | #define CCM_CCGR4_CG3_MASK (0xC0U) | ||
| 5525 | #define CCM_CCGR4_CG3_SHIFT (6U) | ||
| 5526 | #define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK) | ||
| 5527 | #define CCM_CCGR4_CG4_MASK (0x300U) | ||
| 5528 | #define CCM_CCGR4_CG4_SHIFT (8U) | ||
| 5529 | #define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK) | ||
| 5530 | #define CCM_CCGR4_CG5_MASK (0xC00U) | ||
| 5531 | #define CCM_CCGR4_CG5_SHIFT (10U) | ||
| 5532 | #define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK) | ||
| 5533 | #define CCM_CCGR4_CG6_MASK (0x3000U) | ||
| 5534 | #define CCM_CCGR4_CG6_SHIFT (12U) | ||
| 5535 | #define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK) | ||
| 5536 | #define CCM_CCGR4_CG7_MASK (0xC000U) | ||
| 5537 | #define CCM_CCGR4_CG7_SHIFT (14U) | ||
| 5538 | #define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK) | ||
| 5539 | #define CCM_CCGR4_CG8_MASK (0x30000U) | ||
| 5540 | #define CCM_CCGR4_CG8_SHIFT (16U) | ||
| 5541 | #define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK) | ||
| 5542 | #define CCM_CCGR4_CG9_MASK (0xC0000U) | ||
| 5543 | #define CCM_CCGR4_CG9_SHIFT (18U) | ||
| 5544 | #define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK) | ||
| 5545 | #define CCM_CCGR4_CG10_MASK (0x300000U) | ||
| 5546 | #define CCM_CCGR4_CG10_SHIFT (20U) | ||
| 5547 | #define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK) | ||
| 5548 | #define CCM_CCGR4_CG11_MASK (0xC00000U) | ||
| 5549 | #define CCM_CCGR4_CG11_SHIFT (22U) | ||
| 5550 | #define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK) | ||
| 5551 | #define CCM_CCGR4_CG12_MASK (0x3000000U) | ||
| 5552 | #define CCM_CCGR4_CG12_SHIFT (24U) | ||
| 5553 | #define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK) | ||
| 5554 | #define CCM_CCGR4_CG13_MASK (0xC000000U) | ||
| 5555 | #define CCM_CCGR4_CG13_SHIFT (26U) | ||
| 5556 | #define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK) | ||
| 5557 | #define CCM_CCGR4_CG14_MASK (0x30000000U) | ||
| 5558 | #define CCM_CCGR4_CG14_SHIFT (28U) | ||
| 5559 | #define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK) | ||
| 5560 | #define CCM_CCGR4_CG15_MASK (0xC0000000U) | ||
| 5561 | #define CCM_CCGR4_CG15_SHIFT (30U) | ||
| 5562 | #define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK) | ||
| 5563 | /*! @} */ | ||
| 5564 | |||
| 5565 | /*! @name CCGR5 - CCM Clock Gating Register 5 */ | ||
| 5566 | /*! @{ */ | ||
| 5567 | #define CCM_CCGR5_CG0_MASK (0x3U) | ||
| 5568 | #define CCM_CCGR5_CG0_SHIFT (0U) | ||
| 5569 | #define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK) | ||
| 5570 | #define CCM_CCGR5_CG1_MASK (0xCU) | ||
| 5571 | #define CCM_CCGR5_CG1_SHIFT (2U) | ||
| 5572 | #define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK) | ||
| 5573 | #define CCM_CCGR5_CG2_MASK (0x30U) | ||
| 5574 | #define CCM_CCGR5_CG2_SHIFT (4U) | ||
| 5575 | #define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK) | ||
| 5576 | #define CCM_CCGR5_CG3_MASK (0xC0U) | ||
| 5577 | #define CCM_CCGR5_CG3_SHIFT (6U) | ||
| 5578 | #define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK) | ||
| 5579 | #define CCM_CCGR5_CG4_MASK (0x300U) | ||
| 5580 | #define CCM_CCGR5_CG4_SHIFT (8U) | ||
| 5581 | #define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK) | ||
| 5582 | #define CCM_CCGR5_CG5_MASK (0xC00U) | ||
| 5583 | #define CCM_CCGR5_CG5_SHIFT (10U) | ||
| 5584 | #define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK) | ||
| 5585 | #define CCM_CCGR5_CG6_MASK (0x3000U) | ||
| 5586 | #define CCM_CCGR5_CG6_SHIFT (12U) | ||
| 5587 | #define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK) | ||
| 5588 | #define CCM_CCGR5_CG7_MASK (0xC000U) | ||
| 5589 | #define CCM_CCGR5_CG7_SHIFT (14U) | ||
| 5590 | #define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK) | ||
| 5591 | #define CCM_CCGR5_CG8_MASK (0x30000U) | ||
| 5592 | #define CCM_CCGR5_CG8_SHIFT (16U) | ||
| 5593 | #define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK) | ||
| 5594 | #define CCM_CCGR5_CG9_MASK (0xC0000U) | ||
| 5595 | #define CCM_CCGR5_CG9_SHIFT (18U) | ||
| 5596 | #define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK) | ||
| 5597 | #define CCM_CCGR5_CG10_MASK (0x300000U) | ||
| 5598 | #define CCM_CCGR5_CG10_SHIFT (20U) | ||
| 5599 | #define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK) | ||
| 5600 | #define CCM_CCGR5_CG11_MASK (0xC00000U) | ||
| 5601 | #define CCM_CCGR5_CG11_SHIFT (22U) | ||
| 5602 | #define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK) | ||
| 5603 | #define CCM_CCGR5_CG12_MASK (0x3000000U) | ||
| 5604 | #define CCM_CCGR5_CG12_SHIFT (24U) | ||
| 5605 | #define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK) | ||
| 5606 | #define CCM_CCGR5_CG13_MASK (0xC000000U) | ||
| 5607 | #define CCM_CCGR5_CG13_SHIFT (26U) | ||
| 5608 | #define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK) | ||
| 5609 | #define CCM_CCGR5_CG14_MASK (0x30000000U) | ||
| 5610 | #define CCM_CCGR5_CG14_SHIFT (28U) | ||
| 5611 | #define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK) | ||
| 5612 | #define CCM_CCGR5_CG15_MASK (0xC0000000U) | ||
| 5613 | #define CCM_CCGR5_CG15_SHIFT (30U) | ||
| 5614 | #define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK) | ||
| 5615 | /*! @} */ | ||
| 5616 | |||
| 5617 | /*! @name CCGR6 - CCM Clock Gating Register 6 */ | ||
| 5618 | /*! @{ */ | ||
| 5619 | #define CCM_CCGR6_CG0_MASK (0x3U) | ||
| 5620 | #define CCM_CCGR6_CG0_SHIFT (0U) | ||
| 5621 | #define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK) | ||
| 5622 | #define CCM_CCGR6_CG1_MASK (0xCU) | ||
| 5623 | #define CCM_CCGR6_CG1_SHIFT (2U) | ||
| 5624 | #define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK) | ||
| 5625 | #define CCM_CCGR6_CG2_MASK (0x30U) | ||
| 5626 | #define CCM_CCGR6_CG2_SHIFT (4U) | ||
| 5627 | #define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK) | ||
| 5628 | #define CCM_CCGR6_CG3_MASK (0xC0U) | ||
| 5629 | #define CCM_CCGR6_CG3_SHIFT (6U) | ||
| 5630 | #define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK) | ||
| 5631 | #define CCM_CCGR6_CG4_MASK (0x300U) | ||
| 5632 | #define CCM_CCGR6_CG4_SHIFT (8U) | ||
| 5633 | #define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK) | ||
| 5634 | #define CCM_CCGR6_CG5_MASK (0xC00U) | ||
| 5635 | #define CCM_CCGR6_CG5_SHIFT (10U) | ||
| 5636 | #define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK) | ||
| 5637 | #define CCM_CCGR6_CG6_MASK (0x3000U) | ||
| 5638 | #define CCM_CCGR6_CG6_SHIFT (12U) | ||
| 5639 | #define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK) | ||
| 5640 | #define CCM_CCGR6_CG7_MASK (0xC000U) | ||
| 5641 | #define CCM_CCGR6_CG7_SHIFT (14U) | ||
| 5642 | #define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK) | ||
| 5643 | #define CCM_CCGR6_CG8_MASK (0x30000U) | ||
| 5644 | #define CCM_CCGR6_CG8_SHIFT (16U) | ||
| 5645 | #define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK) | ||
| 5646 | #define CCM_CCGR6_CG9_MASK (0xC0000U) | ||
| 5647 | #define CCM_CCGR6_CG9_SHIFT (18U) | ||
| 5648 | #define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK) | ||
| 5649 | #define CCM_CCGR6_CG10_MASK (0x300000U) | ||
| 5650 | #define CCM_CCGR6_CG10_SHIFT (20U) | ||
| 5651 | #define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK) | ||
| 5652 | #define CCM_CCGR6_CG11_MASK (0xC00000U) | ||
| 5653 | #define CCM_CCGR6_CG11_SHIFT (22U) | ||
| 5654 | #define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK) | ||
| 5655 | #define CCM_CCGR6_CG12_MASK (0x3000000U) | ||
| 5656 | #define CCM_CCGR6_CG12_SHIFT (24U) | ||
| 5657 | #define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK) | ||
| 5658 | #define CCM_CCGR6_CG13_MASK (0xC000000U) | ||
| 5659 | #define CCM_CCGR6_CG13_SHIFT (26U) | ||
| 5660 | #define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK) | ||
| 5661 | #define CCM_CCGR6_CG14_MASK (0x30000000U) | ||
| 5662 | #define CCM_CCGR6_CG14_SHIFT (28U) | ||
| 5663 | #define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK) | ||
| 5664 | #define CCM_CCGR6_CG15_MASK (0xC0000000U) | ||
| 5665 | #define CCM_CCGR6_CG15_SHIFT (30U) | ||
| 5666 | #define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK) | ||
| 5667 | /*! @} */ | ||
| 5668 | |||
| 5669 | /*! @name CMEOR - CCM Module Enable Overide Register */ | ||
| 5670 | /*! @{ */ | ||
| 5671 | #define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U) | ||
| 5672 | #define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U) | ||
| 5673 | /*! MOD_EN_OV_GPT | ||
| 5674 | * 0b0..don't override module enable signal | ||
| 5675 | * 0b1..override module enable signal | ||
| 5676 | */ | ||
| 5677 | #define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK) | ||
| 5678 | #define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U) | ||
| 5679 | #define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U) | ||
| 5680 | /*! MOD_EN_OV_PIT | ||
| 5681 | * 0b0..don't override module enable signal | ||
| 5682 | * 0b1..override module enable signal | ||
| 5683 | */ | ||
| 5684 | #define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK) | ||
| 5685 | #define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U) | ||
| 5686 | #define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U) | ||
| 5687 | /*! MOD_EN_USDHC | ||
| 5688 | * 0b0..don't override module enable signal | ||
| 5689 | * 0b1..override module enable signal | ||
| 5690 | */ | ||
| 5691 | #define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK) | ||
| 5692 | #define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U) | ||
| 5693 | #define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U) | ||
| 5694 | /*! MOD_EN_OV_TRNG | ||
| 5695 | * 0b0..don't override module enable signal | ||
| 5696 | * 0b1..override module enable signal | ||
| 5697 | */ | ||
| 5698 | #define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK) | ||
| 5699 | #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U) | ||
| 5700 | #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U) | ||
| 5701 | /*! MOD_EN_OV_CAN2_CPI | ||
| 5702 | * 0b0..don't override module enable signal | ||
| 5703 | * 0b1..override module enable signal | ||
| 5704 | */ | ||
| 5705 | #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK) | ||
| 5706 | #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U) | ||
| 5707 | #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U) | ||
| 5708 | /*! MOD_EN_OV_CAN1_CPI | ||
| 5709 | * 0b0..don't overide module enable signal | ||
| 5710 | * 0b1..overide module enable signal | ||
| 5711 | */ | ||
| 5712 | #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK) | ||
| 5713 | /*! @} */ | ||
| 5714 | |||
| 5715 | |||
| 5716 | /*! | ||
| 5717 | * @} | ||
| 5718 | */ /* end of group CCM_Register_Masks */ | ||
| 5719 | |||
| 5720 | |||
| 5721 | /* CCM - Peripheral instance base addresses */ | ||
| 5722 | /** Peripheral CCM base address */ | ||
| 5723 | #define CCM_BASE (0x400FC000u) | ||
| 5724 | /** Peripheral CCM base pointer */ | ||
| 5725 | #define CCM ((CCM_Type *)CCM_BASE) | ||
| 5726 | /** Array initializer of CCM peripheral base addresses */ | ||
| 5727 | #define CCM_BASE_ADDRS { CCM_BASE } | ||
| 5728 | /** Array initializer of CCM peripheral base pointers */ | ||
| 5729 | #define CCM_BASE_PTRS { CCM } | ||
| 5730 | /** Interrupt vectors for the CCM peripheral type */ | ||
| 5731 | #define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn } | ||
| 5732 | |||
| 5733 | /*! | ||
| 5734 | * @} | ||
| 5735 | */ /* end of group CCM_Peripheral_Access_Layer */ | ||
| 5736 | |||
| 5737 | |||
| 5738 | /* ---------------------------------------------------------------------------- | ||
| 5739 | -- CCM_ANALOG Peripheral Access Layer | ||
| 5740 | ---------------------------------------------------------------------------- */ | ||
| 5741 | |||
| 5742 | /*! | ||
| 5743 | * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer | ||
| 5744 | * @{ | ||
| 5745 | */ | ||
| 5746 | |||
| 5747 | /** CCM_ANALOG - Register Layout Typedef */ | ||
| 5748 | typedef struct { | ||
| 5749 | uint8_t RESERVED_0[16]; | ||
| 5750 | __IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */ | ||
| 5751 | __IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */ | ||
| 5752 | __IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */ | ||
| 5753 | __IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */ | ||
| 5754 | uint8_t RESERVED_1[16]; | ||
| 5755 | __IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */ | ||
| 5756 | __IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */ | ||
| 5757 | __IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */ | ||
| 5758 | __IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */ | ||
| 5759 | __IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */ | ||
| 5760 | uint8_t RESERVED_2[12]; | ||
| 5761 | __IO uint32_t PLL_SYS_NUM; /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */ | ||
| 5762 | uint8_t RESERVED_3[12]; | ||
| 5763 | __IO uint32_t PLL_SYS_DENOM; /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */ | ||
| 5764 | uint8_t RESERVED_4[12]; | ||
| 5765 | __IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */ | ||
| 5766 | __IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */ | ||
| 5767 | __IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */ | ||
| 5768 | __IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */ | ||
| 5769 | __IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */ | ||
| 5770 | uint8_t RESERVED_5[12]; | ||
| 5771 | __IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */ | ||
| 5772 | uint8_t RESERVED_6[76]; | ||
| 5773 | __IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */ | ||
| 5774 | __IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */ | ||
| 5775 | __IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */ | ||
| 5776 | __IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */ | ||
| 5777 | __IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */ | ||
| 5778 | __IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */ | ||
| 5779 | __IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */ | ||
| 5780 | __IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */ | ||
| 5781 | __IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */ | ||
| 5782 | __IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */ | ||
| 5783 | __IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */ | ||
| 5784 | __IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */ | ||
| 5785 | uint8_t RESERVED_7[64]; | ||
| 5786 | __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ | ||
| 5787 | __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ | ||
| 5788 | __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ | ||
| 5789 | __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ | ||
| 5790 | __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ | ||
| 5791 | __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ | ||
| 5792 | __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ | ||
| 5793 | __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ | ||
| 5794 | __IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */ | ||
| 5795 | __IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */ | ||
| 5796 | __IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */ | ||
| 5797 | __IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */ | ||
| 5798 | } CCM_ANALOG_Type; | ||
| 5799 | |||
| 5800 | /* ---------------------------------------------------------------------------- | ||
| 5801 | -- CCM_ANALOG Register Masks | ||
| 5802 | ---------------------------------------------------------------------------- */ | ||
| 5803 | |||
| 5804 | /*! | ||
| 5805 | * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks | ||
| 5806 | * @{ | ||
| 5807 | */ | ||
| 5808 | |||
| 5809 | /*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */ | ||
| 5810 | /*! @{ */ | ||
| 5811 | #define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U) | ||
| 5812 | #define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U) | ||
| 5813 | #define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) | ||
| 5814 | #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U) | ||
| 5815 | #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U) | ||
| 5816 | /*! EN_USB_CLKS | ||
| 5817 | * 0b0..PLL outputs for USBPHYn off. | ||
| 5818 | * 0b1..PLL outputs for USBPHYn on. | ||
| 5819 | */ | ||
| 5820 | #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK) | ||
| 5821 | #define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U) | ||
| 5822 | #define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U) | ||
| 5823 | #define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK) | ||
| 5824 | #define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U) | ||
| 5825 | #define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U) | ||
| 5826 | #define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK) | ||
| 5827 | #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U) | ||
| 5828 | #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U) | ||
| 5829 | /*! BYPASS_CLK_SRC | ||
| 5830 | * 0b00..Select the 24MHz oscillator as source. | ||
| 5831 | */ | ||
| 5832 | #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) | ||
| 5833 | #define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U) | ||
| 5834 | #define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U) | ||
| 5835 | #define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK) | ||
| 5836 | #define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U) | ||
| 5837 | #define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U) | ||
| 5838 | #define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK) | ||
| 5839 | /*! @} */ | ||
| 5840 | |||
| 5841 | /*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */ | ||
| 5842 | /*! @{ */ | ||
| 5843 | #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U) | ||
| 5844 | #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U) | ||
| 5845 | #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK) | ||
| 5846 | #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U) | ||
| 5847 | #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U) | ||
| 5848 | /*! EN_USB_CLKS | ||
| 5849 | * 0b0..PLL outputs for USBPHYn off. | ||
| 5850 | * 0b1..PLL outputs for USBPHYn on. | ||
| 5851 | */ | ||
| 5852 | #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK) | ||
| 5853 | #define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U) | ||
| 5854 | #define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U) | ||
| 5855 | #define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK) | ||
| 5856 | #define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U) | ||
| 5857 | #define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U) | ||
| 5858 | #define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK) | ||
| 5859 | #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U) | ||
| 5860 | #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U) | ||
| 5861 | /*! BYPASS_CLK_SRC | ||
| 5862 | * 0b00..Select the 24MHz oscillator as source. | ||
| 5863 | */ | ||
| 5864 | #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK) | ||
| 5865 | #define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U) | ||
| 5866 | #define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U) | ||
| 5867 | #define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK) | ||
| 5868 | #define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U) | ||
| 5869 | #define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U) | ||
| 5870 | #define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK) | ||
| 5871 | /*! @} */ | ||
| 5872 | |||
| 5873 | /*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */ | ||
| 5874 | /*! @{ */ | ||
| 5875 | #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U) | ||
| 5876 | #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U) | ||
| 5877 | #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK) | ||
| 5878 | #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U) | ||
| 5879 | #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U) | ||
| 5880 | /*! EN_USB_CLKS | ||
| 5881 | * 0b0..PLL outputs for USBPHYn off. | ||
| 5882 | * 0b1..PLL outputs for USBPHYn on. | ||
| 5883 | */ | ||
| 5884 | #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK) | ||
| 5885 | #define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U) | ||
| 5886 | #define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U) | ||
| 5887 | #define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK) | ||
| 5888 | #define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U) | ||
| 5889 | #define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U) | ||
| 5890 | #define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK) | ||
| 5891 | #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U) | ||
| 5892 | #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U) | ||
| 5893 | /*! BYPASS_CLK_SRC | ||
| 5894 | * 0b00..Select the 24MHz oscillator as source. | ||
| 5895 | */ | ||
| 5896 | #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK) | ||
| 5897 | #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U) | ||
| 5898 | #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U) | ||
| 5899 | #define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK) | ||
| 5900 | #define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U) | ||
| 5901 | #define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U) | ||
| 5902 | #define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK) | ||
| 5903 | /*! @} */ | ||
| 5904 | |||
| 5905 | /*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */ | ||
| 5906 | /*! @{ */ | ||
| 5907 | #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U) | ||
| 5908 | #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U) | ||
| 5909 | #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK) | ||
| 5910 | #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U) | ||
| 5911 | #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U) | ||
| 5912 | /*! EN_USB_CLKS | ||
| 5913 | * 0b0..PLL outputs for USBPHYn off. | ||
| 5914 | * 0b1..PLL outputs for USBPHYn on. | ||
| 5915 | */ | ||
| 5916 | #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK) | ||
| 5917 | #define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U) | ||
| 5918 | #define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U) | ||
| 5919 | #define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK) | ||
| 5920 | #define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U) | ||
| 5921 | #define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U) | ||
| 5922 | #define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK) | ||
| 5923 | #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U) | ||
| 5924 | #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U) | ||
| 5925 | /*! BYPASS_CLK_SRC | ||
| 5926 | * 0b00..Select the 24MHz oscillator as source. | ||
| 5927 | */ | ||
| 5928 | #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK) | ||
| 5929 | #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U) | ||
| 5930 | #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U) | ||
| 5931 | #define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK) | ||
| 5932 | #define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U) | ||
| 5933 | #define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U) | ||
| 5934 | #define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK) | ||
| 5935 | /*! @} */ | ||
| 5936 | |||
| 5937 | /*! @name PLL_SYS - Analog System PLL Control Register */ | ||
| 5938 | /*! @{ */ | ||
| 5939 | #define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U) | ||
| 5940 | #define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U) | ||
| 5941 | #define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) | ||
| 5942 | #define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U) | ||
| 5943 | #define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U) | ||
| 5944 | #define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK) | ||
| 5945 | #define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U) | ||
| 5946 | #define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U) | ||
| 5947 | #define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK) | ||
| 5948 | #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U) | ||
| 5949 | #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U) | ||
| 5950 | /*! BYPASS_CLK_SRC | ||
| 5951 | * 0b00..Select the 24MHz oscillator as source. | ||
| 5952 | */ | ||
| 5953 | #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) | ||
| 5954 | #define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U) | ||
| 5955 | #define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U) | ||
| 5956 | #define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK) | ||
| 5957 | #define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U) | ||
| 5958 | #define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U) | ||
| 5959 | #define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK) | ||
| 5960 | /*! @} */ | ||
| 5961 | |||
| 5962 | /*! @name PLL_SYS_SET - Analog System PLL Control Register */ | ||
| 5963 | /*! @{ */ | ||
| 5964 | #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U) | ||
| 5965 | #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U) | ||
| 5966 | #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK) | ||
| 5967 | #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U) | ||
| 5968 | #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U) | ||
| 5969 | #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK) | ||
| 5970 | #define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U) | ||
| 5971 | #define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U) | ||
| 5972 | #define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK) | ||
| 5973 | #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U) | ||
| 5974 | #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U) | ||
| 5975 | /*! BYPASS_CLK_SRC | ||
| 5976 | * 0b00..Select the 24MHz oscillator as source. | ||
| 5977 | */ | ||
| 5978 | #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK) | ||
| 5979 | #define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U) | ||
| 5980 | #define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U) | ||
| 5981 | #define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK) | ||
| 5982 | #define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U) | ||
| 5983 | #define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U) | ||
| 5984 | #define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK) | ||
| 5985 | /*! @} */ | ||
| 5986 | |||
| 5987 | /*! @name PLL_SYS_CLR - Analog System PLL Control Register */ | ||
| 5988 | /*! @{ */ | ||
| 5989 | #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U) | ||
| 5990 | #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U) | ||
| 5991 | #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK) | ||
| 5992 | #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U) | ||
| 5993 | #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U) | ||
| 5994 | #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK) | ||
| 5995 | #define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U) | ||
| 5996 | #define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U) | ||
| 5997 | #define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK) | ||
| 5998 | #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U) | ||
| 5999 | #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U) | ||
| 6000 | /*! BYPASS_CLK_SRC | ||
| 6001 | * 0b00..Select the 24MHz oscillator as source. | ||
| 6002 | */ | ||
| 6003 | #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK) | ||
| 6004 | #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U) | ||
| 6005 | #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U) | ||
| 6006 | #define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK) | ||
| 6007 | #define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U) | ||
| 6008 | #define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U) | ||
| 6009 | #define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK) | ||
| 6010 | /*! @} */ | ||
| 6011 | |||
| 6012 | /*! @name PLL_SYS_TOG - Analog System PLL Control Register */ | ||
| 6013 | /*! @{ */ | ||
| 6014 | #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U) | ||
| 6015 | #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U) | ||
| 6016 | #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK) | ||
| 6017 | #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U) | ||
| 6018 | #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U) | ||
| 6019 | #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK) | ||
| 6020 | #define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U) | ||
| 6021 | #define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U) | ||
| 6022 | #define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK) | ||
| 6023 | #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U) | ||
| 6024 | #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U) | ||
| 6025 | /*! BYPASS_CLK_SRC | ||
| 6026 | * 0b00..Select the 24MHz oscillator as source. | ||
| 6027 | */ | ||
| 6028 | #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK) | ||
| 6029 | #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U) | ||
| 6030 | #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U) | ||
| 6031 | #define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK) | ||
| 6032 | #define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U) | ||
| 6033 | #define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U) | ||
| 6034 | #define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK) | ||
| 6035 | /*! @} */ | ||
| 6036 | |||
| 6037 | /*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */ | ||
| 6038 | /*! @{ */ | ||
| 6039 | #define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU) | ||
| 6040 | #define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U) | ||
| 6041 | #define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK) | ||
| 6042 | #define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U) | ||
| 6043 | #define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U) | ||
| 6044 | /*! ENABLE - Enable bit | ||
| 6045 | * 0b0..Spread spectrum modulation disabled | ||
| 6046 | * 0b1..Soread spectrum modulation enabled | ||
| 6047 | */ | ||
| 6048 | #define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK) | ||
| 6049 | #define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U) | ||
| 6050 | #define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U) | ||
| 6051 | #define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK) | ||
| 6052 | /*! @} */ | ||
| 6053 | |||
| 6054 | /*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */ | ||
| 6055 | /*! @{ */ | ||
| 6056 | #define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU) | ||
| 6057 | #define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U) | ||
| 6058 | #define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK) | ||
| 6059 | /*! @} */ | ||
| 6060 | |||
| 6061 | /*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */ | ||
| 6062 | /*! @{ */ | ||
| 6063 | #define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU) | ||
| 6064 | #define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U) | ||
| 6065 | #define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK) | ||
| 6066 | /*! @} */ | ||
| 6067 | |||
| 6068 | /*! @name PLL_AUDIO - Analog Audio PLL control Register */ | ||
| 6069 | /*! @{ */ | ||
| 6070 | #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU) | ||
| 6071 | #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U) | ||
| 6072 | #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) | ||
| 6073 | #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U) | ||
| 6074 | #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U) | ||
| 6075 | #define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK) | ||
| 6076 | #define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U) | ||
| 6077 | #define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U) | ||
| 6078 | #define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK) | ||
| 6079 | #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U) | ||
| 6080 | #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U) | ||
| 6081 | /*! BYPASS_CLK_SRC | ||
| 6082 | * 0b00..Select the 24MHz oscillator as source. | ||
| 6083 | * 0b10..Reserved1 | ||
| 6084 | * 0b11..Reserved2 | ||
| 6085 | */ | ||
| 6086 | #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) | ||
| 6087 | #define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U) | ||
| 6088 | #define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U) | ||
| 6089 | #define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK) | ||
| 6090 | #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U) | ||
| 6091 | #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U) | ||
| 6092 | /*! POST_DIV_SELECT | ||
| 6093 | * 0b00..Divide by 4. | ||
| 6094 | * 0b01..Divide by 2. | ||
| 6095 | * 0b10..Divide by 1. | ||
| 6096 | * 0b11..Reserved | ||
| 6097 | */ | ||
| 6098 | #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) | ||
| 6099 | #define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U) | ||
| 6100 | #define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U) | ||
| 6101 | #define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) | ||
| 6102 | /*! @} */ | ||
| 6103 | |||
| 6104 | /*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */ | ||
| 6105 | /*! @{ */ | ||
| 6106 | #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU) | ||
| 6107 | #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U) | ||
| 6108 | #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) | ||
| 6109 | #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U) | ||
| 6110 | #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U) | ||
| 6111 | #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK) | ||
| 6112 | #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U) | ||
| 6113 | #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U) | ||
| 6114 | #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK) | ||
| 6115 | #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U) | ||
| 6116 | #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U) | ||
| 6117 | /*! BYPASS_CLK_SRC | ||
| 6118 | * 0b00..Select the 24MHz oscillator as source. | ||
| 6119 | * 0b10..Reserved1 | ||
| 6120 | * 0b11..Reserved2 | ||
| 6121 | */ | ||
| 6122 | #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) | ||
| 6123 | #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U) | ||
| 6124 | #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U) | ||
| 6125 | #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK) | ||
| 6126 | #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U) | ||
| 6127 | #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U) | ||
| 6128 | /*! POST_DIV_SELECT | ||
| 6129 | * 0b00..Divide by 4. | ||
| 6130 | * 0b01..Divide by 2. | ||
| 6131 | * 0b10..Divide by 1. | ||
| 6132 | * 0b11..Reserved | ||
| 6133 | */ | ||
| 6134 | #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK) | ||
| 6135 | #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U) | ||
| 6136 | #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U) | ||
| 6137 | #define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK) | ||
| 6138 | /*! @} */ | ||
| 6139 | |||
| 6140 | /*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */ | ||
| 6141 | /*! @{ */ | ||
| 6142 | #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU) | ||
| 6143 | #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U) | ||
| 6144 | #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) | ||
| 6145 | #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U) | ||
| 6146 | #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U) | ||
| 6147 | #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK) | ||
| 6148 | #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U) | ||
| 6149 | #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U) | ||
| 6150 | #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK) | ||
| 6151 | #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) | ||
| 6152 | #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U) | ||
| 6153 | /*! BYPASS_CLK_SRC | ||
| 6154 | * 0b00..Select the 24MHz oscillator as source. | ||
| 6155 | * 0b10..Reserved1 | ||
| 6156 | * 0b11..Reserved2 | ||
| 6157 | */ | ||
| 6158 | #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) | ||
| 6159 | #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U) | ||
| 6160 | #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U) | ||
| 6161 | #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK) | ||
| 6162 | #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U) | ||
| 6163 | #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U) | ||
| 6164 | /*! POST_DIV_SELECT | ||
| 6165 | * 0b00..Divide by 4. | ||
| 6166 | * 0b01..Divide by 2. | ||
| 6167 | * 0b10..Divide by 1. | ||
| 6168 | * 0b11..Reserved | ||
| 6169 | */ | ||
| 6170 | #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK) | ||
| 6171 | #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U) | ||
| 6172 | #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U) | ||
| 6173 | #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK) | ||
| 6174 | /*! @} */ | ||
| 6175 | |||
| 6176 | /*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */ | ||
| 6177 | /*! @{ */ | ||
| 6178 | #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU) | ||
| 6179 | #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U) | ||
| 6180 | #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) | ||
| 6181 | #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U) | ||
| 6182 | #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U) | ||
| 6183 | #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK) | ||
| 6184 | #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U) | ||
| 6185 | #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U) | ||
| 6186 | #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK) | ||
| 6187 | #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) | ||
| 6188 | #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U) | ||
| 6189 | /*! BYPASS_CLK_SRC | ||
| 6190 | * 0b00..Select the 24MHz oscillator as source. | ||
| 6191 | * 0b10..Reserved1 | ||
| 6192 | * 0b11..Reserved2 | ||
| 6193 | */ | ||
| 6194 | #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) | ||
| 6195 | #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U) | ||
| 6196 | #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U) | ||
| 6197 | #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK) | ||
| 6198 | #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U) | ||
| 6199 | #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U) | ||
| 6200 | /*! POST_DIV_SELECT | ||
| 6201 | * 0b00..Divide by 4. | ||
| 6202 | * 0b01..Divide by 2. | ||
| 6203 | * 0b10..Divide by 1. | ||
| 6204 | * 0b11..Reserved | ||
| 6205 | */ | ||
| 6206 | #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK) | ||
| 6207 | #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U) | ||
| 6208 | #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U) | ||
| 6209 | #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK) | ||
| 6210 | /*! @} */ | ||
| 6211 | |||
| 6212 | /*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */ | ||
| 6213 | /*! @{ */ | ||
| 6214 | #define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU) | ||
| 6215 | #define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U) | ||
| 6216 | #define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) | ||
| 6217 | /*! @} */ | ||
| 6218 | |||
| 6219 | /*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */ | ||
| 6220 | /*! @{ */ | ||
| 6221 | #define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU) | ||
| 6222 | #define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U) | ||
| 6223 | #define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) | ||
| 6224 | /*! @} */ | ||
| 6225 | |||
| 6226 | /*! @name PLL_ENET - Analog ENET PLL Control Register */ | ||
| 6227 | /*! @{ */ | ||
| 6228 | #define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U) | ||
| 6229 | #define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U) | ||
| 6230 | #define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) | ||
| 6231 | #define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U) | ||
| 6232 | #define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U) | ||
| 6233 | #define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK) | ||
| 6234 | #define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U) | ||
| 6235 | #define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U) | ||
| 6236 | #define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK) | ||
| 6237 | #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U) | ||
| 6238 | #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U) | ||
| 6239 | /*! BYPASS_CLK_SRC | ||
| 6240 | * 0b00..Select the 24MHz oscillator as source. | ||
| 6241 | * 0b10..Reserved1 | ||
| 6242 | * 0b11..Reserved2 | ||
| 6243 | */ | ||
| 6244 | #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK) | ||
| 6245 | #define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U) | ||
| 6246 | #define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U) | ||
| 6247 | #define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK) | ||
| 6248 | #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U) | ||
| 6249 | #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U) | ||
| 6250 | #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK) | ||
| 6251 | #define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK (0x400000U) | ||
| 6252 | #define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT (22U) | ||
| 6253 | #define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK) | ||
| 6254 | #define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U) | ||
| 6255 | #define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U) | ||
| 6256 | #define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK) | ||
| 6257 | /*! @} */ | ||
| 6258 | |||
| 6259 | /*! @name PLL_ENET_SET - Analog ENET PLL Control Register */ | ||
| 6260 | /*! @{ */ | ||
| 6261 | #define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U) | ||
| 6262 | #define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U) | ||
| 6263 | #define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK) | ||
| 6264 | #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U) | ||
| 6265 | #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U) | ||
| 6266 | #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK) | ||
| 6267 | #define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U) | ||
| 6268 | #define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U) | ||
| 6269 | #define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK) | ||
| 6270 | #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U) | ||
| 6271 | #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U) | ||
| 6272 | /*! BYPASS_CLK_SRC | ||
| 6273 | * 0b00..Select the 24MHz oscillator as source. | ||
| 6274 | * 0b10..Reserved1 | ||
| 6275 | * 0b11..Reserved2 | ||
| 6276 | */ | ||
| 6277 | #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK) | ||
| 6278 | #define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U) | ||
| 6279 | #define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U) | ||
| 6280 | #define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK) | ||
| 6281 | #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U) | ||
| 6282 | #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U) | ||
| 6283 | #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK) | ||
| 6284 | #define CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_MASK (0x400000U) | ||
| 6285 | #define CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_SHIFT (22U) | ||
| 6286 | #define CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_MASK) | ||
| 6287 | #define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U) | ||
| 6288 | #define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U) | ||
| 6289 | #define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK) | ||
| 6290 | /*! @} */ | ||
| 6291 | |||
| 6292 | /*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */ | ||
| 6293 | /*! @{ */ | ||
| 6294 | #define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U) | ||
| 6295 | #define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U) | ||
| 6296 | #define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK) | ||
| 6297 | #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U) | ||
| 6298 | #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U) | ||
| 6299 | #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK) | ||
| 6300 | #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U) | ||
| 6301 | #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U) | ||
| 6302 | #define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK) | ||
| 6303 | #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U) | ||
| 6304 | #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U) | ||
| 6305 | /*! BYPASS_CLK_SRC | ||
| 6306 | * 0b00..Select the 24MHz oscillator as source. | ||
| 6307 | * 0b10..Reserved1 | ||
| 6308 | * 0b11..Reserved2 | ||
| 6309 | */ | ||
| 6310 | #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK) | ||
| 6311 | #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U) | ||
| 6312 | #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U) | ||
| 6313 | #define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK) | ||
| 6314 | #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U) | ||
| 6315 | #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U) | ||
| 6316 | #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK) | ||
| 6317 | #define CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_MASK (0x400000U) | ||
| 6318 | #define CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_SHIFT (22U) | ||
| 6319 | #define CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_MASK) | ||
| 6320 | #define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U) | ||
| 6321 | #define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U) | ||
| 6322 | #define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK) | ||
| 6323 | /*! @} */ | ||
| 6324 | |||
| 6325 | /*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */ | ||
| 6326 | /*! @{ */ | ||
| 6327 | #define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U) | ||
| 6328 | #define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U) | ||
| 6329 | #define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK) | ||
| 6330 | #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U) | ||
| 6331 | #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U) | ||
| 6332 | #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK) | ||
| 6333 | #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U) | ||
| 6334 | #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U) | ||
| 6335 | #define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK) | ||
| 6336 | #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U) | ||
| 6337 | #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U) | ||
| 6338 | /*! BYPASS_CLK_SRC | ||
| 6339 | * 0b00..Select the 24MHz oscillator as source. | ||
| 6340 | * 0b10..Reserved1 | ||
| 6341 | * 0b11..Reserved2 | ||
| 6342 | */ | ||
| 6343 | #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK) | ||
| 6344 | #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U) | ||
| 6345 | #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U) | ||
| 6346 | #define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK) | ||
| 6347 | #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U) | ||
| 6348 | #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U) | ||
| 6349 | #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK) | ||
| 6350 | #define CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_MASK (0x400000U) | ||
| 6351 | #define CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_SHIFT (22U) | ||
| 6352 | #define CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_MASK) | ||
| 6353 | #define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U) | ||
| 6354 | #define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U) | ||
| 6355 | #define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK) | ||
| 6356 | /*! @} */ | ||
| 6357 | |||
| 6358 | /*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ | ||
| 6359 | /*! @{ */ | ||
| 6360 | #define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU) | ||
| 6361 | #define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U) | ||
| 6362 | #define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) | ||
| 6363 | #define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U) | ||
| 6364 | #define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U) | ||
| 6365 | #define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK) | ||
| 6366 | #define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U) | ||
| 6367 | #define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U) | ||
| 6368 | #define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK) | ||
| 6369 | #define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U) | ||
| 6370 | #define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U) | ||
| 6371 | #define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) | ||
| 6372 | #define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U) | ||
| 6373 | #define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U) | ||
| 6374 | #define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK) | ||
| 6375 | #define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U) | ||
| 6376 | #define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U) | ||
| 6377 | #define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK) | ||
| 6378 | #define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U) | ||
| 6379 | #define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U) | ||
| 6380 | #define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) | ||
| 6381 | #define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U) | ||
| 6382 | #define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U) | ||
| 6383 | #define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK) | ||
| 6384 | #define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U) | ||
| 6385 | #define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U) | ||
| 6386 | #define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK) | ||
| 6387 | #define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U) | ||
| 6388 | #define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U) | ||
| 6389 | #define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) | ||
| 6390 | #define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U) | ||
| 6391 | #define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U) | ||
| 6392 | #define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK) | ||
| 6393 | #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U) | ||
| 6394 | #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U) | ||
| 6395 | #define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK) | ||
| 6396 | /*! @} */ | ||
| 6397 | |||
| 6398 | /*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ | ||
| 6399 | /*! @{ */ | ||
| 6400 | #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU) | ||
| 6401 | #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U) | ||
| 6402 | #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK) | ||
| 6403 | #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U) | ||
| 6404 | #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U) | ||
| 6405 | #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK) | ||
| 6406 | #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U) | ||
| 6407 | #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U) | ||
| 6408 | #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK) | ||
| 6409 | #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U) | ||
| 6410 | #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U) | ||
| 6411 | #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK) | ||
| 6412 | #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U) | ||
| 6413 | #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U) | ||
| 6414 | #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK) | ||
| 6415 | #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U) | ||
| 6416 | #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U) | ||
| 6417 | #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK) | ||
| 6418 | #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U) | ||
| 6419 | #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U) | ||
| 6420 | #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK) | ||
| 6421 | #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U) | ||
| 6422 | #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U) | ||
| 6423 | #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK) | ||
| 6424 | #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U) | ||
| 6425 | #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U) | ||
| 6426 | #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK) | ||
| 6427 | #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U) | ||
| 6428 | #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U) | ||
| 6429 | #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK) | ||
| 6430 | #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U) | ||
| 6431 | #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U) | ||
| 6432 | #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK) | ||
| 6433 | #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U) | ||
| 6434 | #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U) | ||
| 6435 | #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK) | ||
| 6436 | /*! @} */ | ||
| 6437 | |||
| 6438 | /*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ | ||
| 6439 | /*! @{ */ | ||
| 6440 | #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU) | ||
| 6441 | #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U) | ||
| 6442 | #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK) | ||
| 6443 | #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U) | ||
| 6444 | #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U) | ||
| 6445 | #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK) | ||
| 6446 | #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U) | ||
| 6447 | #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U) | ||
| 6448 | #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK) | ||
| 6449 | #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U) | ||
| 6450 | #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U) | ||
| 6451 | #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK) | ||
| 6452 | #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U) | ||
| 6453 | #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U) | ||
| 6454 | #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK) | ||
| 6455 | #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U) | ||
| 6456 | #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U) | ||
| 6457 | #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK) | ||
| 6458 | #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U) | ||
| 6459 | #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U) | ||
| 6460 | #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK) | ||
| 6461 | #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U) | ||
| 6462 | #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U) | ||
| 6463 | #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK) | ||
| 6464 | #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U) | ||
| 6465 | #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U) | ||
| 6466 | #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK) | ||
| 6467 | #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U) | ||
| 6468 | #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U) | ||
| 6469 | #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK) | ||
| 6470 | #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U) | ||
| 6471 | #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U) | ||
| 6472 | #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK) | ||
| 6473 | #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U) | ||
| 6474 | #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U) | ||
| 6475 | #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK) | ||
| 6476 | /*! @} */ | ||
| 6477 | |||
| 6478 | /*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ | ||
| 6479 | /*! @{ */ | ||
| 6480 | #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU) | ||
| 6481 | #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U) | ||
| 6482 | #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK) | ||
| 6483 | #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U) | ||
| 6484 | #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U) | ||
| 6485 | #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK) | ||
| 6486 | #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U) | ||
| 6487 | #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U) | ||
| 6488 | #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK) | ||
| 6489 | #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U) | ||
| 6490 | #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U) | ||
| 6491 | #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK) | ||
| 6492 | #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U) | ||
| 6493 | #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U) | ||
| 6494 | #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK) | ||
| 6495 | #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U) | ||
| 6496 | #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U) | ||
| 6497 | #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK) | ||
| 6498 | #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U) | ||
| 6499 | #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U) | ||
| 6500 | #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK) | ||
| 6501 | #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U) | ||
| 6502 | #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U) | ||
| 6503 | #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK) | ||
| 6504 | #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U) | ||
| 6505 | #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U) | ||
| 6506 | #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK) | ||
| 6507 | #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U) | ||
| 6508 | #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U) | ||
| 6509 | #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK) | ||
| 6510 | #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U) | ||
| 6511 | #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U) | ||
| 6512 | #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK) | ||
| 6513 | #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U) | ||
| 6514 | #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U) | ||
| 6515 | #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK) | ||
| 6516 | /*! @} */ | ||
| 6517 | |||
| 6518 | /*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ | ||
| 6519 | /*! @{ */ | ||
| 6520 | #define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU) | ||
| 6521 | #define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U) | ||
| 6522 | #define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) | ||
| 6523 | #define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U) | ||
| 6524 | #define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U) | ||
| 6525 | #define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK) | ||
| 6526 | #define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U) | ||
| 6527 | #define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U) | ||
| 6528 | #define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK) | ||
| 6529 | #define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U) | ||
| 6530 | #define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U) | ||
| 6531 | #define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) | ||
| 6532 | #define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U) | ||
| 6533 | #define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U) | ||
| 6534 | #define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK) | ||
| 6535 | #define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U) | ||
| 6536 | #define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U) | ||
| 6537 | #define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK) | ||
| 6538 | #define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U) | ||
| 6539 | #define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U) | ||
| 6540 | #define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) | ||
| 6541 | #define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U) | ||
| 6542 | #define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U) | ||
| 6543 | #define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK) | ||
| 6544 | #define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U) | ||
| 6545 | #define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U) | ||
| 6546 | #define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK) | ||
| 6547 | #define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U) | ||
| 6548 | #define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U) | ||
| 6549 | #define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) | ||
| 6550 | #define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U) | ||
| 6551 | #define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U) | ||
| 6552 | #define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK) | ||
| 6553 | #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U) | ||
| 6554 | #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U) | ||
| 6555 | #define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK) | ||
| 6556 | /*! @} */ | ||
| 6557 | |||
| 6558 | /*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ | ||
| 6559 | /*! @{ */ | ||
| 6560 | #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU) | ||
| 6561 | #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U) | ||
| 6562 | #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK) | ||
| 6563 | #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U) | ||
| 6564 | #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U) | ||
| 6565 | #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK) | ||
| 6566 | #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U) | ||
| 6567 | #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U) | ||
| 6568 | #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK) | ||
| 6569 | #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U) | ||
| 6570 | #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U) | ||
| 6571 | #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK) | ||
| 6572 | #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U) | ||
| 6573 | #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U) | ||
| 6574 | #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK) | ||
| 6575 | #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U) | ||
| 6576 | #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U) | ||
| 6577 | #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK) | ||
| 6578 | #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U) | ||
| 6579 | #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U) | ||
| 6580 | #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK) | ||
| 6581 | #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U) | ||
| 6582 | #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U) | ||
| 6583 | #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK) | ||
| 6584 | #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U) | ||
| 6585 | #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U) | ||
| 6586 | #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK) | ||
| 6587 | #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U) | ||
| 6588 | #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U) | ||
| 6589 | #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK) | ||
| 6590 | #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U) | ||
| 6591 | #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U) | ||
| 6592 | #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK) | ||
| 6593 | #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U) | ||
| 6594 | #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U) | ||
| 6595 | #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK) | ||
| 6596 | /*! @} */ | ||
| 6597 | |||
| 6598 | /*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ | ||
| 6599 | /*! @{ */ | ||
| 6600 | #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU) | ||
| 6601 | #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U) | ||
| 6602 | #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK) | ||
| 6603 | #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U) | ||
| 6604 | #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U) | ||
| 6605 | #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK) | ||
| 6606 | #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U) | ||
| 6607 | #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U) | ||
| 6608 | #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK) | ||
| 6609 | #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U) | ||
| 6610 | #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U) | ||
| 6611 | #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK) | ||
| 6612 | #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U) | ||
| 6613 | #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U) | ||
| 6614 | #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK) | ||
| 6615 | #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U) | ||
| 6616 | #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U) | ||
| 6617 | #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK) | ||
| 6618 | #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U) | ||
| 6619 | #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U) | ||
| 6620 | #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK) | ||
| 6621 | #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U) | ||
| 6622 | #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U) | ||
| 6623 | #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK) | ||
| 6624 | #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U) | ||
| 6625 | #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U) | ||
| 6626 | #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK) | ||
| 6627 | #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U) | ||
| 6628 | #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U) | ||
| 6629 | #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK) | ||
| 6630 | #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U) | ||
| 6631 | #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U) | ||
| 6632 | #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK) | ||
| 6633 | #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U) | ||
| 6634 | #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U) | ||
| 6635 | #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK) | ||
| 6636 | /*! @} */ | ||
| 6637 | |||
| 6638 | /*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ | ||
| 6639 | /*! @{ */ | ||
| 6640 | #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU) | ||
| 6641 | #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U) | ||
| 6642 | #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK) | ||
| 6643 | #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U) | ||
| 6644 | #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U) | ||
| 6645 | #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK) | ||
| 6646 | #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U) | ||
| 6647 | #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U) | ||
| 6648 | #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK) | ||
| 6649 | #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U) | ||
| 6650 | #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U) | ||
| 6651 | #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK) | ||
| 6652 | #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U) | ||
| 6653 | #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U) | ||
| 6654 | #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK) | ||
| 6655 | #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U) | ||
| 6656 | #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U) | ||
| 6657 | #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK) | ||
| 6658 | #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U) | ||
| 6659 | #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U) | ||
| 6660 | #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK) | ||
| 6661 | #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U) | ||
| 6662 | #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U) | ||
| 6663 | #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK) | ||
| 6664 | #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U) | ||
| 6665 | #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U) | ||
| 6666 | #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK) | ||
| 6667 | #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U) | ||
| 6668 | #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U) | ||
| 6669 | #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK) | ||
| 6670 | #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U) | ||
| 6671 | #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U) | ||
| 6672 | #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK) | ||
| 6673 | #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U) | ||
| 6674 | #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U) | ||
| 6675 | #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK) | ||
| 6676 | /*! @} */ | ||
| 6677 | |||
| 6678 | /*! @name MISC0 - Miscellaneous Register 0 */ | ||
| 6679 | /*! @{ */ | ||
| 6680 | #define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U) | ||
| 6681 | #define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U) | ||
| 6682 | #define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK) | ||
| 6683 | #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) | ||
| 6684 | #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) | ||
| 6685 | /*! REFTOP_SELFBIASOFF | ||
| 6686 | * 0b0..Uses coarse bias currents for startup | ||
| 6687 | * 0b1..Uses bandgap-based bias currents for best performance. | ||
| 6688 | */ | ||
| 6689 | #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK) | ||
| 6690 | #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U) | ||
| 6691 | #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U) | ||
| 6692 | /*! REFTOP_VBGADJ | ||
| 6693 | * 0b000..Nominal VBG | ||
| 6694 | * 0b001..VBG+0.78% | ||
| 6695 | * 0b010..VBG+1.56% | ||
| 6696 | * 0b011..VBG+2.34% | ||
| 6697 | * 0b100..VBG-0.78% | ||
| 6698 | * 0b101..VBG-1.56% | ||
| 6699 | * 0b110..VBG-2.34% | ||
| 6700 | * 0b111..VBG-3.12% | ||
| 6701 | */ | ||
| 6702 | #define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK) | ||
| 6703 | #define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U) | ||
| 6704 | #define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U) | ||
| 6705 | #define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK) | ||
| 6706 | #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) | ||
| 6707 | #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U) | ||
| 6708 | /*! STOP_MODE_CONFIG | ||
| 6709 | * 0b00..All analog except RTC powered down on stop mode assertion. | ||
| 6710 | * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. | ||
| 6711 | * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog | ||
| 6712 | * bandgap together with the rest analog is powered down. | ||
| 6713 | * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down. | ||
| 6714 | */ | ||
| 6715 | #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK) | ||
| 6716 | #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) | ||
| 6717 | #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) | ||
| 6718 | /*! DISCON_HIGH_SNVS | ||
| 6719 | * 0b0..Turn on the switch | ||
| 6720 | * 0b1..Turn off the switch | ||
| 6721 | */ | ||
| 6722 | #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK) | ||
| 6723 | #define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U) | ||
| 6724 | #define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U) | ||
| 6725 | /*! OSC_I | ||
| 6726 | * 0b00..Nominal | ||
| 6727 | * 0b01..Decrease current by 12.5% | ||
| 6728 | * 0b10..Decrease current by 25.0% | ||
| 6729 | * 0b11..Decrease current by 37.5% | ||
| 6730 | */ | ||
| 6731 | #define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK) | ||
| 6732 | #define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U) | ||
| 6733 | #define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U) | ||
| 6734 | #define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) | ||
| 6735 | #define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U) | ||
| 6736 | #define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U) | ||
| 6737 | #define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK) | ||
| 6738 | #define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U) | ||
| 6739 | #define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U) | ||
| 6740 | /*! CLKGATE_CTRL | ||
| 6741 | * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. | ||
| 6742 | * 0b1..Prevent the logic from ever gating off the clock. | ||
| 6743 | */ | ||
| 6744 | #define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK) | ||
| 6745 | #define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) | ||
| 6746 | #define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U) | ||
| 6747 | /*! CLKGATE_DELAY | ||
| 6748 | * 0b000..0.5ms | ||
| 6749 | * 0b001..1.0ms | ||
| 6750 | * 0b010..2.0ms | ||
| 6751 | * 0b011..3.0ms | ||
| 6752 | * 0b100..4.0ms | ||
| 6753 | * 0b101..5.0ms | ||
| 6754 | * 0b110..6.0ms | ||
| 6755 | * 0b111..7.0ms | ||
| 6756 | */ | ||
| 6757 | #define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK) | ||
| 6758 | #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) | ||
| 6759 | #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) | ||
| 6760 | /*! RTC_XTAL_SOURCE | ||
| 6761 | * 0b0..Internal ring oscillator | ||
| 6762 | * 0b1..RTC_XTAL | ||
| 6763 | */ | ||
| 6764 | #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK) | ||
| 6765 | #define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U) | ||
| 6766 | #define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U) | ||
| 6767 | #define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK) | ||
| 6768 | /*! @} */ | ||
| 6769 | |||
| 6770 | /*! @name MISC0_SET - Miscellaneous Register 0 */ | ||
| 6771 | /*! @{ */ | ||
| 6772 | #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U) | ||
| 6773 | #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U) | ||
| 6774 | #define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK) | ||
| 6775 | #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) | ||
| 6776 | #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) | ||
| 6777 | /*! REFTOP_SELFBIASOFF | ||
| 6778 | * 0b0..Uses coarse bias currents for startup | ||
| 6779 | * 0b1..Uses bandgap-based bias currents for best performance. | ||
| 6780 | */ | ||
| 6781 | #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK) | ||
| 6782 | #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) | ||
| 6783 | #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) | ||
| 6784 | /*! REFTOP_VBGADJ | ||
| 6785 | * 0b000..Nominal VBG | ||
| 6786 | * 0b001..VBG+0.78% | ||
| 6787 | * 0b010..VBG+1.56% | ||
| 6788 | * 0b011..VBG+2.34% | ||
| 6789 | * 0b100..VBG-0.78% | ||
| 6790 | * 0b101..VBG-1.56% | ||
| 6791 | * 0b110..VBG-2.34% | ||
| 6792 | * 0b111..VBG-3.12% | ||
| 6793 | */ | ||
| 6794 | #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK) | ||
| 6795 | #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) | ||
| 6796 | #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) | ||
| 6797 | #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK) | ||
| 6798 | #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) | ||
| 6799 | #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) | ||
| 6800 | /*! STOP_MODE_CONFIG | ||
| 6801 | * 0b00..All analog except RTC powered down on stop mode assertion. | ||
| 6802 | * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. | ||
| 6803 | * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog | ||
| 6804 | * bandgap together with the rest analog is powered down. | ||
| 6805 | * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down. | ||
| 6806 | */ | ||
| 6807 | #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK) | ||
| 6808 | #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) | ||
| 6809 | #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) | ||
| 6810 | /*! DISCON_HIGH_SNVS | ||
| 6811 | * 0b0..Turn on the switch | ||
| 6812 | * 0b1..Turn off the switch | ||
| 6813 | */ | ||
| 6814 | #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK) | ||
| 6815 | #define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U) | ||
| 6816 | #define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U) | ||
| 6817 | /*! OSC_I | ||
| 6818 | * 0b00..Nominal | ||
| 6819 | * 0b01..Decrease current by 12.5% | ||
| 6820 | * 0b10..Decrease current by 25.0% | ||
| 6821 | * 0b11..Decrease current by 37.5% | ||
| 6822 | */ | ||
| 6823 | #define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK) | ||
| 6824 | #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U) | ||
| 6825 | #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U) | ||
| 6826 | #define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK) | ||
| 6827 | #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) | ||
| 6828 | #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) | ||
| 6829 | #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK) | ||
| 6830 | #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) | ||
| 6831 | #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) | ||
| 6832 | /*! CLKGATE_CTRL | ||
| 6833 | * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. | ||
| 6834 | * 0b1..Prevent the logic from ever gating off the clock. | ||
| 6835 | */ | ||
| 6836 | #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK) | ||
| 6837 | #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) | ||
| 6838 | #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) | ||
| 6839 | /*! CLKGATE_DELAY | ||
| 6840 | * 0b000..0.5ms | ||
| 6841 | * 0b001..1.0ms | ||
| 6842 | * 0b010..2.0ms | ||
| 6843 | * 0b011..3.0ms | ||
| 6844 | * 0b100..4.0ms | ||
| 6845 | * 0b101..5.0ms | ||
| 6846 | * 0b110..6.0ms | ||
| 6847 | * 0b111..7.0ms | ||
| 6848 | */ | ||
| 6849 | #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK) | ||
| 6850 | #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) | ||
| 6851 | #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) | ||
| 6852 | /*! RTC_XTAL_SOURCE | ||
| 6853 | * 0b0..Internal ring oscillator | ||
| 6854 | * 0b1..RTC_XTAL | ||
| 6855 | */ | ||
| 6856 | #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK) | ||
| 6857 | #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) | ||
| 6858 | #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) | ||
| 6859 | #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK) | ||
| 6860 | /*! @} */ | ||
| 6861 | |||
| 6862 | /*! @name MISC0_CLR - Miscellaneous Register 0 */ | ||
| 6863 | /*! @{ */ | ||
| 6864 | #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U) | ||
| 6865 | #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U) | ||
| 6866 | #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK) | ||
| 6867 | #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) | ||
| 6868 | #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) | ||
| 6869 | /*! REFTOP_SELFBIASOFF | ||
| 6870 | * 0b0..Uses coarse bias currents for startup | ||
| 6871 | * 0b1..Uses bandgap-based bias currents for best performance. | ||
| 6872 | */ | ||
| 6873 | #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) | ||
| 6874 | #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) | ||
| 6875 | #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) | ||
| 6876 | /*! REFTOP_VBGADJ | ||
| 6877 | * 0b000..Nominal VBG | ||
| 6878 | * 0b001..VBG+0.78% | ||
| 6879 | * 0b010..VBG+1.56% | ||
| 6880 | * 0b011..VBG+2.34% | ||
| 6881 | * 0b100..VBG-0.78% | ||
| 6882 | * 0b101..VBG-1.56% | ||
| 6883 | * 0b110..VBG-2.34% | ||
| 6884 | * 0b111..VBG-3.12% | ||
| 6885 | */ | ||
| 6886 | #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK) | ||
| 6887 | #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) | ||
| 6888 | #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) | ||
| 6889 | #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK) | ||
| 6890 | #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) | ||
| 6891 | #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) | ||
| 6892 | /*! STOP_MODE_CONFIG | ||
| 6893 | * 0b00..All analog except RTC powered down on stop mode assertion. | ||
| 6894 | * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. | ||
| 6895 | * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog | ||
| 6896 | * bandgap together with the rest analog is powered down. | ||
| 6897 | * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down. | ||
| 6898 | */ | ||
| 6899 | #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK) | ||
| 6900 | #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) | ||
| 6901 | #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) | ||
| 6902 | /*! DISCON_HIGH_SNVS | ||
| 6903 | * 0b0..Turn on the switch | ||
| 6904 | * 0b1..Turn off the switch | ||
| 6905 | */ | ||
| 6906 | #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK) | ||
| 6907 | #define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U) | ||
| 6908 | #define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U) | ||
| 6909 | /*! OSC_I | ||
| 6910 | * 0b00..Nominal | ||
| 6911 | * 0b01..Decrease current by 12.5% | ||
| 6912 | * 0b10..Decrease current by 25.0% | ||
| 6913 | * 0b11..Decrease current by 37.5% | ||
| 6914 | */ | ||
| 6915 | #define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK) | ||
| 6916 | #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) | ||
| 6917 | #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U) | ||
| 6918 | #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK) | ||
| 6919 | #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) | ||
| 6920 | #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) | ||
| 6921 | #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK) | ||
| 6922 | #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) | ||
| 6923 | #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) | ||
| 6924 | /*! CLKGATE_CTRL | ||
| 6925 | * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. | ||
| 6926 | * 0b1..Prevent the logic from ever gating off the clock. | ||
| 6927 | */ | ||
| 6928 | #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK) | ||
| 6929 | #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) | ||
| 6930 | #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) | ||
| 6931 | /*! CLKGATE_DELAY | ||
| 6932 | * 0b000..0.5ms | ||
| 6933 | * 0b001..1.0ms | ||
| 6934 | * 0b010..2.0ms | ||
| 6935 | * 0b011..3.0ms | ||
| 6936 | * 0b100..4.0ms | ||
| 6937 | * 0b101..5.0ms | ||
| 6938 | * 0b110..6.0ms | ||
| 6939 | * 0b111..7.0ms | ||
| 6940 | */ | ||
| 6941 | #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK) | ||
| 6942 | #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) | ||
| 6943 | #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) | ||
| 6944 | /*! RTC_XTAL_SOURCE | ||
| 6945 | * 0b0..Internal ring oscillator | ||
| 6946 | * 0b1..RTC_XTAL | ||
| 6947 | */ | ||
| 6948 | #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK) | ||
| 6949 | #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) | ||
| 6950 | #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) | ||
| 6951 | #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK) | ||
| 6952 | /*! @} */ | ||
| 6953 | |||
| 6954 | /*! @name MISC0_TOG - Miscellaneous Register 0 */ | ||
| 6955 | /*! @{ */ | ||
| 6956 | #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U) | ||
| 6957 | #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U) | ||
| 6958 | #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK) | ||
| 6959 | #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) | ||
| 6960 | #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) | ||
| 6961 | /*! REFTOP_SELFBIASOFF | ||
| 6962 | * 0b0..Uses coarse bias currents for startup | ||
| 6963 | * 0b1..Uses bandgap-based bias currents for best performance. | ||
| 6964 | */ | ||
| 6965 | #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) | ||
| 6966 | #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) | ||
| 6967 | #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) | ||
| 6968 | /*! REFTOP_VBGADJ | ||
| 6969 | * 0b000..Nominal VBG | ||
| 6970 | * 0b001..VBG+0.78% | ||
| 6971 | * 0b010..VBG+1.56% | ||
| 6972 | * 0b011..VBG+2.34% | ||
| 6973 | * 0b100..VBG-0.78% | ||
| 6974 | * 0b101..VBG-1.56% | ||
| 6975 | * 0b110..VBG-2.34% | ||
| 6976 | * 0b111..VBG-3.12% | ||
| 6977 | */ | ||
| 6978 | #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK) | ||
| 6979 | #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) | ||
| 6980 | #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) | ||
| 6981 | #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK) | ||
| 6982 | #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) | ||
| 6983 | #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) | ||
| 6984 | /*! STOP_MODE_CONFIG | ||
| 6985 | * 0b00..All analog except RTC powered down on stop mode assertion. | ||
| 6986 | * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. | ||
| 6987 | * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog | ||
| 6988 | * bandgap together with the rest analog is powered down. | ||
| 6989 | * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down. | ||
| 6990 | */ | ||
| 6991 | #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK) | ||
| 6992 | #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) | ||
| 6993 | #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) | ||
| 6994 | /*! DISCON_HIGH_SNVS | ||
| 6995 | * 0b0..Turn on the switch | ||
| 6996 | * 0b1..Turn off the switch | ||
| 6997 | */ | ||
| 6998 | #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK) | ||
| 6999 | #define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U) | ||
| 7000 | #define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U) | ||
| 7001 | /*! OSC_I | ||
| 7002 | * 0b00..Nominal | ||
| 7003 | * 0b01..Decrease current by 12.5% | ||
| 7004 | * 0b10..Decrease current by 25.0% | ||
| 7005 | * 0b11..Decrease current by 37.5% | ||
| 7006 | */ | ||
| 7007 | #define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK) | ||
| 7008 | #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) | ||
| 7009 | #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U) | ||
| 7010 | #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK) | ||
| 7011 | #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) | ||
| 7012 | #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) | ||
| 7013 | #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK) | ||
| 7014 | #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) | ||
| 7015 | #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) | ||
| 7016 | /*! CLKGATE_CTRL | ||
| 7017 | * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. | ||
| 7018 | * 0b1..Prevent the logic from ever gating off the clock. | ||
| 7019 | */ | ||
| 7020 | #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK) | ||
| 7021 | #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) | ||
| 7022 | #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) | ||
| 7023 | /*! CLKGATE_DELAY | ||
| 7024 | * 0b000..0.5ms | ||
| 7025 | * 0b001..1.0ms | ||
| 7026 | * 0b010..2.0ms | ||
| 7027 | * 0b011..3.0ms | ||
| 7028 | * 0b100..4.0ms | ||
| 7029 | * 0b101..5.0ms | ||
| 7030 | * 0b110..6.0ms | ||
| 7031 | * 0b111..7.0ms | ||
| 7032 | */ | ||
| 7033 | #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK) | ||
| 7034 | #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) | ||
| 7035 | #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) | ||
| 7036 | /*! RTC_XTAL_SOURCE | ||
| 7037 | * 0b0..Internal ring oscillator | ||
| 7038 | * 0b1..RTC_XTAL | ||
| 7039 | */ | ||
| 7040 | #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK) | ||
| 7041 | #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) | ||
| 7042 | #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) | ||
| 7043 | #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK) | ||
| 7044 | /*! @} */ | ||
| 7045 | |||
| 7046 | /*! @name MISC1 - Miscellaneous Register 1 */ | ||
| 7047 | /*! @{ */ | ||
| 7048 | #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) | ||
| 7049 | #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) | ||
| 7050 | #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK) | ||
| 7051 | #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U) | ||
| 7052 | #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U) | ||
| 7053 | #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK) | ||
| 7054 | #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U) | ||
| 7055 | #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U) | ||
| 7056 | #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK) | ||
| 7057 | #define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U) | ||
| 7058 | #define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U) | ||
| 7059 | #define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK) | ||
| 7060 | #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U) | ||
| 7061 | #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U) | ||
| 7062 | #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK) | ||
| 7063 | #define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U) | ||
| 7064 | #define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U) | ||
| 7065 | #define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK) | ||
| 7066 | #define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U) | ||
| 7067 | #define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U) | ||
| 7068 | #define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK) | ||
| 7069 | /*! @} */ | ||
| 7070 | |||
| 7071 | /*! @name MISC1_SET - Miscellaneous Register 1 */ | ||
| 7072 | /*! @{ */ | ||
| 7073 | #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) | ||
| 7074 | #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) | ||
| 7075 | #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) | ||
| 7076 | #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U) | ||
| 7077 | #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U) | ||
| 7078 | #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK) | ||
| 7079 | #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U) | ||
| 7080 | #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U) | ||
| 7081 | #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK) | ||
| 7082 | #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) | ||
| 7083 | #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U) | ||
| 7084 | #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK) | ||
| 7085 | #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U) | ||
| 7086 | #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U) | ||
| 7087 | #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK) | ||
| 7088 | #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U) | ||
| 7089 | #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U) | ||
| 7090 | #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK) | ||
| 7091 | #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) | ||
| 7092 | #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) | ||
| 7093 | #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK) | ||
| 7094 | /*! @} */ | ||
| 7095 | |||
| 7096 | /*! @name MISC1_CLR - Miscellaneous Register 1 */ | ||
| 7097 | /*! @{ */ | ||
| 7098 | #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) | ||
| 7099 | #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) | ||
| 7100 | #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) | ||
| 7101 | #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U) | ||
| 7102 | #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U) | ||
| 7103 | #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK) | ||
| 7104 | #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U) | ||
| 7105 | #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U) | ||
| 7106 | #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK) | ||
| 7107 | #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U) | ||
| 7108 | #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U) | ||
| 7109 | #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK) | ||
| 7110 | #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U) | ||
| 7111 | #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U) | ||
| 7112 | #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK) | ||
| 7113 | #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U) | ||
| 7114 | #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U) | ||
| 7115 | #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK) | ||
| 7116 | #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) | ||
| 7117 | #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) | ||
| 7118 | #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK) | ||
| 7119 | /*! @} */ | ||
| 7120 | |||
| 7121 | /*! @name MISC1_TOG - Miscellaneous Register 1 */ | ||
| 7122 | /*! @{ */ | ||
| 7123 | #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) | ||
| 7124 | #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) | ||
| 7125 | #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) | ||
| 7126 | #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U) | ||
| 7127 | #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U) | ||
| 7128 | #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK) | ||
| 7129 | #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U) | ||
| 7130 | #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U) | ||
| 7131 | #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK) | ||
| 7132 | #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U) | ||
| 7133 | #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U) | ||
| 7134 | #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK) | ||
| 7135 | #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U) | ||
| 7136 | #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U) | ||
| 7137 | #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK) | ||
| 7138 | #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U) | ||
| 7139 | #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U) | ||
| 7140 | #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK) | ||
| 7141 | #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) | ||
| 7142 | #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) | ||
| 7143 | #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK) | ||
| 7144 | /*! @} */ | ||
| 7145 | |||
| 7146 | /*! @name MISC2 - Miscellaneous Register 2 */ | ||
| 7147 | /*! @{ */ | ||
| 7148 | #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U) | ||
| 7149 | #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U) | ||
| 7150 | /*! REG0_BO_OFFSET | ||
| 7151 | * 0b100..Brownout offset = 0.100V | ||
| 7152 | * 0b111..Brownout offset = 0.175V | ||
| 7153 | */ | ||
| 7154 | #define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK) | ||
| 7155 | #define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U) | ||
| 7156 | #define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U) | ||
| 7157 | /*! REG0_BO_STATUS | ||
| 7158 | * 0b1..Brownout, supply is below target minus brownout offset. | ||
| 7159 | */ | ||
| 7160 | #define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK) | ||
| 7161 | #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U) | ||
| 7162 | #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U) | ||
| 7163 | #define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK) | ||
| 7164 | #define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U) | ||
| 7165 | #define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U) | ||
| 7166 | #define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK) | ||
| 7167 | #define CCM_ANALOG_MISC2_PLL3_DISABLE_MASK (0x80U) | ||
| 7168 | #define CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT (7U) | ||
| 7169 | /*! PLL3_DISABLE | ||
| 7170 | * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode | ||
| 7171 | * 0b1..PLL3 can be disabled when the SoC is not in any low power mode | ||
| 7172 | */ | ||
| 7173 | #define CCM_ANALOG_MISC2_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_PLL3_DISABLE_MASK) | ||
| 7174 | #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U) | ||
| 7175 | #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U) | ||
| 7176 | /*! REG1_BO_OFFSET | ||
| 7177 | * 0b100..Brownout offset = 0.100V | ||
| 7178 | * 0b111..Brownout offset = 0.175V | ||
| 7179 | */ | ||
| 7180 | #define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK) | ||
| 7181 | #define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U) | ||
| 7182 | #define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U) | ||
| 7183 | /*! REG1_BO_STATUS | ||
| 7184 | * 0b1..Brownout, supply is below target minus brownout offset. | ||
| 7185 | */ | ||
| 7186 | #define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK) | ||
| 7187 | #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U) | ||
| 7188 | #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U) | ||
| 7189 | #define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK) | ||
| 7190 | #define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U) | ||
| 7191 | #define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U) | ||
| 7192 | #define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK) | ||
| 7193 | #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) | ||
| 7194 | #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U) | ||
| 7195 | /*! AUDIO_DIV_LSB | ||
| 7196 | * 0b0..divide by 1 (Default) | ||
| 7197 | * 0b1..divide by 2 | ||
| 7198 | */ | ||
| 7199 | #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK) | ||
| 7200 | #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U) | ||
| 7201 | #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U) | ||
| 7202 | /*! REG2_BO_OFFSET | ||
| 7203 | * 0b100..Brownout offset = 0.100V | ||
| 7204 | * 0b111..Brownout offset = 0.175V | ||
| 7205 | */ | ||
| 7206 | #define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK) | ||
| 7207 | #define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U) | ||
| 7208 | #define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U) | ||
| 7209 | #define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK) | ||
| 7210 | #define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U) | ||
| 7211 | #define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U) | ||
| 7212 | #define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK) | ||
| 7213 | #define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U) | ||
| 7214 | #define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U) | ||
| 7215 | #define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK) | ||
| 7216 | #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) | ||
| 7217 | #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U) | ||
| 7218 | /*! AUDIO_DIV_MSB | ||
| 7219 | * 0b0..divide by 1 (Default) | ||
| 7220 | * 0b1..divide by 2 | ||
| 7221 | */ | ||
| 7222 | #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK) | ||
| 7223 | #define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U) | ||
| 7224 | #define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U) | ||
| 7225 | /*! REG0_STEP_TIME | ||
| 7226 | * 0b00..64 | ||
| 7227 | * 0b01..128 | ||
| 7228 | * 0b10..256 | ||
| 7229 | * 0b11..512 | ||
| 7230 | */ | ||
| 7231 | #define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK) | ||
| 7232 | #define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U) | ||
| 7233 | #define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U) | ||
| 7234 | /*! REG1_STEP_TIME | ||
| 7235 | * 0b00..64 | ||
| 7236 | * 0b01..128 | ||
| 7237 | * 0b10..256 | ||
| 7238 | * 0b11..512 | ||
| 7239 | */ | ||
| 7240 | #define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK) | ||
| 7241 | #define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U) | ||
| 7242 | #define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U) | ||
| 7243 | /*! REG2_STEP_TIME | ||
| 7244 | * 0b00..64 | ||
| 7245 | * 0b01..128 | ||
| 7246 | * 0b10..256 | ||
| 7247 | * 0b11..512 | ||
| 7248 | */ | ||
| 7249 | #define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK) | ||
| 7250 | /*! @} */ | ||
| 7251 | |||
| 7252 | /*! @name MISC2_SET - Miscellaneous Register 2 */ | ||
| 7253 | /*! @{ */ | ||
| 7254 | #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) | ||
| 7255 | #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) | ||
| 7256 | /*! REG0_BO_OFFSET | ||
| 7257 | * 0b100..Brownout offset = 0.100V | ||
| 7258 | * 0b111..Brownout offset = 0.175V | ||
| 7259 | */ | ||
| 7260 | #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK) | ||
| 7261 | #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) | ||
| 7262 | #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) | ||
| 7263 | /*! REG0_BO_STATUS | ||
| 7264 | * 0b1..Brownout, supply is below target minus brownout offset. | ||
| 7265 | */ | ||
| 7266 | #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK) | ||
| 7267 | #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) | ||
| 7268 | #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) | ||
| 7269 | #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK) | ||
| 7270 | #define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U) | ||
| 7271 | #define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U) | ||
| 7272 | #define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK) | ||
| 7273 | #define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK (0x80U) | ||
| 7274 | #define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT (7U) | ||
| 7275 | /*! PLL3_DISABLE | ||
| 7276 | * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode | ||
| 7277 | * 0b1..PLL3 can be disabled when the SoC is not in any low power mode | ||
| 7278 | */ | ||
| 7279 | #define CCM_ANALOG_MISC2_SET_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK) | ||
| 7280 | #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) | ||
| 7281 | #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) | ||
| 7282 | /*! REG1_BO_OFFSET | ||
| 7283 | * 0b100..Brownout offset = 0.100V | ||
| 7284 | * 0b111..Brownout offset = 0.175V | ||
| 7285 | */ | ||
| 7286 | #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK) | ||
| 7287 | #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) | ||
| 7288 | #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) | ||
| 7289 | /*! REG1_BO_STATUS | ||
| 7290 | * 0b1..Brownout, supply is below target minus brownout offset. | ||
| 7291 | */ | ||
| 7292 | #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK) | ||
| 7293 | #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) | ||
| 7294 | #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) | ||
| 7295 | #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK) | ||
| 7296 | #define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U) | ||
| 7297 | #define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U) | ||
| 7298 | #define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK) | ||
| 7299 | #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) | ||
| 7300 | #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) | ||
| 7301 | /*! AUDIO_DIV_LSB | ||
| 7302 | * 0b0..divide by 1 (Default) | ||
| 7303 | * 0b1..divide by 2 | ||
| 7304 | */ | ||
| 7305 | #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK) | ||
| 7306 | #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) | ||
| 7307 | #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) | ||
| 7308 | /*! REG2_BO_OFFSET | ||
| 7309 | * 0b100..Brownout offset = 0.100V | ||
| 7310 | * 0b111..Brownout offset = 0.175V | ||
| 7311 | */ | ||
| 7312 | #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK) | ||
| 7313 | #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) | ||
| 7314 | #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) | ||
| 7315 | #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK) | ||
| 7316 | #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U) | ||
| 7317 | #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U) | ||
| 7318 | #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK) | ||
| 7319 | #define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U) | ||
| 7320 | #define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U) | ||
| 7321 | #define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK) | ||
| 7322 | #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) | ||
| 7323 | #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) | ||
| 7324 | /*! AUDIO_DIV_MSB | ||
| 7325 | * 0b0..divide by 1 (Default) | ||
| 7326 | * 0b1..divide by 2 | ||
| 7327 | */ | ||
| 7328 | #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK) | ||
| 7329 | #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) | ||
| 7330 | #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) | ||
| 7331 | /*! REG0_STEP_TIME | ||
| 7332 | * 0b00..64 | ||
| 7333 | * 0b01..128 | ||
| 7334 | * 0b10..256 | ||
| 7335 | * 0b11..512 | ||
| 7336 | */ | ||
| 7337 | #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK) | ||
| 7338 | #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) | ||
| 7339 | #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) | ||
| 7340 | /*! REG1_STEP_TIME | ||
| 7341 | * 0b00..64 | ||
| 7342 | * 0b01..128 | ||
| 7343 | * 0b10..256 | ||
| 7344 | * 0b11..512 | ||
| 7345 | */ | ||
| 7346 | #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK) | ||
| 7347 | #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) | ||
| 7348 | #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) | ||
| 7349 | /*! REG2_STEP_TIME | ||
| 7350 | * 0b00..64 | ||
| 7351 | * 0b01..128 | ||
| 7352 | * 0b10..256 | ||
| 7353 | * 0b11..512 | ||
| 7354 | */ | ||
| 7355 | #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK) | ||
| 7356 | /*! @} */ | ||
| 7357 | |||
| 7358 | /*! @name MISC2_CLR - Miscellaneous Register 2 */ | ||
| 7359 | /*! @{ */ | ||
| 7360 | #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) | ||
| 7361 | #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) | ||
| 7362 | /*! REG0_BO_OFFSET | ||
| 7363 | * 0b100..Brownout offset = 0.100V | ||
| 7364 | * 0b111..Brownout offset = 0.175V | ||
| 7365 | */ | ||
| 7366 | #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK) | ||
| 7367 | #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) | ||
| 7368 | #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) | ||
| 7369 | /*! REG0_BO_STATUS | ||
| 7370 | * 0b1..Brownout, supply is below target minus brownout offset. | ||
| 7371 | */ | ||
| 7372 | #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK) | ||
| 7373 | #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) | ||
| 7374 | #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) | ||
| 7375 | #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK) | ||
| 7376 | #define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U) | ||
| 7377 | #define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U) | ||
| 7378 | #define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK) | ||
| 7379 | #define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK (0x80U) | ||
| 7380 | #define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT (7U) | ||
| 7381 | /*! PLL3_DISABLE | ||
| 7382 | * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode | ||
| 7383 | * 0b1..PLL3 can be disabled when the SoC is not in any low power mode | ||
| 7384 | */ | ||
| 7385 | #define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK) | ||
| 7386 | #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) | ||
| 7387 | #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) | ||
| 7388 | /*! REG1_BO_OFFSET | ||
| 7389 | * 0b100..Brownout offset = 0.100V | ||
| 7390 | * 0b111..Brownout offset = 0.175V | ||
| 7391 | */ | ||
| 7392 | #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK) | ||
| 7393 | #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) | ||
| 7394 | #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) | ||
| 7395 | /*! REG1_BO_STATUS | ||
| 7396 | * 0b1..Brownout, supply is below target minus brownout offset. | ||
| 7397 | */ | ||
| 7398 | #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK) | ||
| 7399 | #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) | ||
| 7400 | #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) | ||
| 7401 | #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK) | ||
| 7402 | #define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U) | ||
| 7403 | #define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U) | ||
| 7404 | #define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK) | ||
| 7405 | #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) | ||
| 7406 | #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) | ||
| 7407 | /*! AUDIO_DIV_LSB | ||
| 7408 | * 0b0..divide by 1 (Default) | ||
| 7409 | * 0b1..divide by 2 | ||
| 7410 | */ | ||
| 7411 | #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK) | ||
| 7412 | #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) | ||
| 7413 | #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) | ||
| 7414 | /*! REG2_BO_OFFSET | ||
| 7415 | * 0b100..Brownout offset = 0.100V | ||
| 7416 | * 0b111..Brownout offset = 0.175V | ||
| 7417 | */ | ||
| 7418 | #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK) | ||
| 7419 | #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) | ||
| 7420 | #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) | ||
| 7421 | #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK) | ||
| 7422 | #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U) | ||
| 7423 | #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U) | ||
| 7424 | #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK) | ||
| 7425 | #define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U) | ||
| 7426 | #define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U) | ||
| 7427 | #define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK) | ||
| 7428 | #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) | ||
| 7429 | #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) | ||
| 7430 | /*! AUDIO_DIV_MSB | ||
| 7431 | * 0b0..divide by 1 (Default) | ||
| 7432 | * 0b1..divide by 2 | ||
| 7433 | */ | ||
| 7434 | #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK) | ||
| 7435 | #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) | ||
| 7436 | #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) | ||
| 7437 | /*! REG0_STEP_TIME | ||
| 7438 | * 0b00..64 | ||
| 7439 | * 0b01..128 | ||
| 7440 | * 0b10..256 | ||
| 7441 | * 0b11..512 | ||
| 7442 | */ | ||
| 7443 | #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK) | ||
| 7444 | #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) | ||
| 7445 | #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) | ||
| 7446 | /*! REG1_STEP_TIME | ||
| 7447 | * 0b00..64 | ||
| 7448 | * 0b01..128 | ||
| 7449 | * 0b10..256 | ||
| 7450 | * 0b11..512 | ||
| 7451 | */ | ||
| 7452 | #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK) | ||
| 7453 | #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) | ||
| 7454 | #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) | ||
| 7455 | /*! REG2_STEP_TIME | ||
| 7456 | * 0b00..64 | ||
| 7457 | * 0b01..128 | ||
| 7458 | * 0b10..256 | ||
| 7459 | * 0b11..512 | ||
| 7460 | */ | ||
| 7461 | #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK) | ||
| 7462 | /*! @} */ | ||
| 7463 | |||
| 7464 | /*! @name MISC2_TOG - Miscellaneous Register 2 */ | ||
| 7465 | /*! @{ */ | ||
| 7466 | #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) | ||
| 7467 | #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) | ||
| 7468 | /*! REG0_BO_OFFSET | ||
| 7469 | * 0b100..Brownout offset = 0.100V | ||
| 7470 | * 0b111..Brownout offset = 0.175V | ||
| 7471 | */ | ||
| 7472 | #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK) | ||
| 7473 | #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) | ||
| 7474 | #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) | ||
| 7475 | /*! REG0_BO_STATUS | ||
| 7476 | * 0b1..Brownout, supply is below target minus brownout offset. | ||
| 7477 | */ | ||
| 7478 | #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK) | ||
| 7479 | #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) | ||
| 7480 | #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) | ||
| 7481 | #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK) | ||
| 7482 | #define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U) | ||
| 7483 | #define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U) | ||
| 7484 | #define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK) | ||
| 7485 | #define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK (0x80U) | ||
| 7486 | #define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT (7U) | ||
| 7487 | /*! PLL3_DISABLE | ||
| 7488 | * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode | ||
| 7489 | * 0b1..PLL3 can be disabled when the SoC is not in any low power mode | ||
| 7490 | */ | ||
| 7491 | #define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK) | ||
| 7492 | #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) | ||
| 7493 | #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) | ||
| 7494 | /*! REG1_BO_OFFSET | ||
| 7495 | * 0b100..Brownout offset = 0.100V | ||
| 7496 | * 0b111..Brownout offset = 0.175V | ||
| 7497 | */ | ||
| 7498 | #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK) | ||
| 7499 | #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) | ||
| 7500 | #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) | ||
| 7501 | /*! REG1_BO_STATUS | ||
| 7502 | * 0b1..Brownout, supply is below target minus brownout offset. | ||
| 7503 | */ | ||
| 7504 | #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK) | ||
| 7505 | #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) | ||
| 7506 | #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) | ||
| 7507 | #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK) | ||
| 7508 | #define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U) | ||
| 7509 | #define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U) | ||
| 7510 | #define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK) | ||
| 7511 | #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) | ||
| 7512 | #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) | ||
| 7513 | /*! AUDIO_DIV_LSB | ||
| 7514 | * 0b0..divide by 1 (Default) | ||
| 7515 | * 0b1..divide by 2 | ||
| 7516 | */ | ||
| 7517 | #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK) | ||
| 7518 | #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) | ||
| 7519 | #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) | ||
| 7520 | /*! REG2_BO_OFFSET | ||
| 7521 | * 0b100..Brownout offset = 0.100V | ||
| 7522 | * 0b111..Brownout offset = 0.175V | ||
| 7523 | */ | ||
| 7524 | #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK) | ||
| 7525 | #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) | ||
| 7526 | #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) | ||
| 7527 | #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK) | ||
| 7528 | #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U) | ||
| 7529 | #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U) | ||
| 7530 | #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK) | ||
| 7531 | #define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U) | ||
| 7532 | #define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U) | ||
| 7533 | #define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK) | ||
| 7534 | #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) | ||
| 7535 | #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) | ||
| 7536 | /*! AUDIO_DIV_MSB | ||
| 7537 | * 0b0..divide by 1 (Default) | ||
| 7538 | * 0b1..divide by 2 | ||
| 7539 | */ | ||
| 7540 | #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK) | ||
| 7541 | #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) | ||
| 7542 | #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) | ||
| 7543 | /*! REG0_STEP_TIME | ||
| 7544 | * 0b00..64 | ||
| 7545 | * 0b01..128 | ||
| 7546 | * 0b10..256 | ||
| 7547 | * 0b11..512 | ||
| 7548 | */ | ||
| 7549 | #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK) | ||
| 7550 | #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) | ||
| 7551 | #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) | ||
| 7552 | /*! REG1_STEP_TIME | ||
| 7553 | * 0b00..64 | ||
| 7554 | * 0b01..128 | ||
| 7555 | * 0b10..256 | ||
| 7556 | * 0b11..512 | ||
| 7557 | */ | ||
| 7558 | #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK) | ||
| 7559 | #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) | ||
| 7560 | #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) | ||
| 7561 | /*! REG2_STEP_TIME | ||
| 7562 | * 0b00..64 | ||
| 7563 | * 0b01..128 | ||
| 7564 | * 0b10..256 | ||
| 7565 | * 0b11..512 | ||
| 7566 | */ | ||
| 7567 | #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK) | ||
| 7568 | /*! @} */ | ||
| 7569 | |||
| 7570 | |||
| 7571 | /*! | ||
| 7572 | * @} | ||
| 7573 | */ /* end of group CCM_ANALOG_Register_Masks */ | ||
| 7574 | |||
| 7575 | |||
| 7576 | /* CCM_ANALOG - Peripheral instance base addresses */ | ||
| 7577 | /** Peripheral CCM_ANALOG base address */ | ||
| 7578 | #define CCM_ANALOG_BASE (0x400D8000u) | ||
| 7579 | /** Peripheral CCM_ANALOG base pointer */ | ||
| 7580 | #define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE) | ||
| 7581 | /** Array initializer of CCM_ANALOG peripheral base addresses */ | ||
| 7582 | #define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE } | ||
| 7583 | /** Array initializer of CCM_ANALOG peripheral base pointers */ | ||
| 7584 | #define CCM_ANALOG_BASE_PTRS { CCM_ANALOG } | ||
| 7585 | |||
| 7586 | /*! | ||
| 7587 | * @} | ||
| 7588 | */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */ | ||
| 7589 | |||
| 7590 | |||
| 7591 | /* ---------------------------------------------------------------------------- | ||
| 7592 | -- CM7_MCM Peripheral Access Layer | ||
| 7593 | ---------------------------------------------------------------------------- */ | ||
| 7594 | |||
| 7595 | /*! | ||
| 7596 | * @addtogroup CM7_MCM_Peripheral_Access_Layer CM7_MCM Peripheral Access Layer | ||
| 7597 | * @{ | ||
| 7598 | */ | ||
| 7599 | |||
| 7600 | /** CM7_MCM - Register Layout Typedef */ | ||
| 7601 | typedef struct { | ||
| 7602 | uint8_t RESERVED_0[16]; | ||
| 7603 | __IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */ | ||
| 7604 | } CM7_MCM_Type; | ||
| 7605 | |||
| 7606 | /* ---------------------------------------------------------------------------- | ||
| 7607 | -- CM7_MCM Register Masks | ||
| 7608 | ---------------------------------------------------------------------------- */ | ||
| 7609 | |||
| 7610 | /*! | ||
| 7611 | * @addtogroup CM7_MCM_Register_Masks CM7_MCM Register Masks | ||
| 7612 | * @{ | ||
| 7613 | */ | ||
| 7614 | |||
| 7615 | /*! @name ISCR - Interrupt Status and Control Register */ | ||
| 7616 | /*! @{ */ | ||
| 7617 | #define CM7_MCM_ISCR_WABS_MASK (0x20U) | ||
| 7618 | #define CM7_MCM_ISCR_WABS_SHIFT (5U) | ||
| 7619 | /*! WABS - Write Abort on Slave | ||
| 7620 | * 0b0..No abort | ||
| 7621 | * 0b1..Abort | ||
| 7622 | */ | ||
| 7623 | #define CM7_MCM_ISCR_WABS(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABS_SHIFT)) & CM7_MCM_ISCR_WABS_MASK) | ||
| 7624 | #define CM7_MCM_ISCR_WABSO_MASK (0x40U) | ||
| 7625 | #define CM7_MCM_ISCR_WABSO_SHIFT (6U) | ||
| 7626 | /*! WABSO - Write Abort on Slave Overrun | ||
| 7627 | * 0b0..No write abort overrun | ||
| 7628 | * 0b1..Write abort overrun occurred | ||
| 7629 | */ | ||
| 7630 | #define CM7_MCM_ISCR_WABSO(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABSO_SHIFT)) & CM7_MCM_ISCR_WABSO_MASK) | ||
| 7631 | #define CM7_MCM_ISCR_FIOC_MASK (0x100U) | ||
| 7632 | #define CM7_MCM_ISCR_FIOC_SHIFT (8U) | ||
| 7633 | /*! FIOC - FPU Invalid Operation interrupt Status | ||
| 7634 | * 0b0..No interrupt | ||
| 7635 | * 0b1..Interrupt occured | ||
| 7636 | */ | ||
| 7637 | #define CM7_MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOC_SHIFT)) & CM7_MCM_ISCR_FIOC_MASK) | ||
| 7638 | #define CM7_MCM_ISCR_FDZC_MASK (0x200U) | ||
| 7639 | #define CM7_MCM_ISCR_FDZC_SHIFT (9U) | ||
| 7640 | /*! FDZC - FPU Divide-by-Zero Interrupt Status | ||
| 7641 | * 0b0..No interrupt | ||
| 7642 | * 0b1..Interrupt occured | ||
| 7643 | */ | ||
| 7644 | #define CM7_MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZC_SHIFT)) & CM7_MCM_ISCR_FDZC_MASK) | ||
| 7645 | #define CM7_MCM_ISCR_FOFC_MASK (0x400U) | ||
| 7646 | #define CM7_MCM_ISCR_FOFC_SHIFT (10U) | ||
| 7647 | /*! FOFC - FPU Overflow interrupt status | ||
| 7648 | * 0b0..No interrupt | ||
| 7649 | * 0b1..Interrupt occured | ||
| 7650 | */ | ||
| 7651 | #define CM7_MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFC_SHIFT)) & CM7_MCM_ISCR_FOFC_MASK) | ||
| 7652 | #define CM7_MCM_ISCR_FUFC_MASK (0x800U) | ||
| 7653 | #define CM7_MCM_ISCR_FUFC_SHIFT (11U) | ||
| 7654 | /*! FUFC - FPU Underflow Interrupt Status | ||
| 7655 | * 0b0..No interrupt | ||
| 7656 | * 0b1..Interrupt occured | ||
| 7657 | */ | ||
| 7658 | #define CM7_MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFC_SHIFT)) & CM7_MCM_ISCR_FUFC_MASK) | ||
| 7659 | #define CM7_MCM_ISCR_FIXC_MASK (0x1000U) | ||
| 7660 | #define CM7_MCM_ISCR_FIXC_SHIFT (12U) | ||
| 7661 | /*! FIXC - FPU Inexact Interrupt Status | ||
| 7662 | * 0b0..No interrupt | ||
| 7663 | * 0b1..Interrupt occured | ||
| 7664 | */ | ||
| 7665 | #define CM7_MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXC_SHIFT)) & CM7_MCM_ISCR_FIXC_MASK) | ||
| 7666 | #define CM7_MCM_ISCR_FIDC_MASK (0x8000U) | ||
| 7667 | #define CM7_MCM_ISCR_FIDC_SHIFT (15U) | ||
| 7668 | /*! FIDC - FPU Input Denormal Interrupt Status | ||
| 7669 | * 0b0..No interrupt | ||
| 7670 | * 0b1..Interrupt occured | ||
| 7671 | */ | ||
| 7672 | #define CM7_MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDC_SHIFT)) & CM7_MCM_ISCR_FIDC_MASK) | ||
| 7673 | #define CM7_MCM_ISCR_WABE_MASK (0x200000U) | ||
| 7674 | #define CM7_MCM_ISCR_WABE_SHIFT (21U) | ||
| 7675 | /*! WABE - TCM Write Abort Interrupt enable | ||
| 7676 | * 0b0..Disable interrupt | ||
| 7677 | * 0b1..Enable interrupt | ||
| 7678 | */ | ||
| 7679 | #define CM7_MCM_ISCR_WABE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABE_SHIFT)) & CM7_MCM_ISCR_WABE_MASK) | ||
| 7680 | #define CM7_MCM_ISCR_FIOCE_MASK (0x1000000U) | ||
| 7681 | #define CM7_MCM_ISCR_FIOCE_SHIFT (24U) | ||
| 7682 | /*! FIOCE - FPU Invalid Operation Interrupt Enable | ||
| 7683 | * 0b0..Disable interrupt | ||
| 7684 | * 0b1..Enable interrupt | ||
| 7685 | */ | ||
| 7686 | #define CM7_MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOCE_SHIFT)) & CM7_MCM_ISCR_FIOCE_MASK) | ||
| 7687 | #define CM7_MCM_ISCR_FDZCE_MASK (0x2000000U) | ||
| 7688 | #define CM7_MCM_ISCR_FDZCE_SHIFT (25U) | ||
| 7689 | /*! FDZCE - FPU Divide-by-Zero Interrupt Enable | ||
| 7690 | * 0b0..Disable interrupt | ||
| 7691 | * 0b1..Enable interrupt | ||
| 7692 | */ | ||
| 7693 | #define CM7_MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZCE_SHIFT)) & CM7_MCM_ISCR_FDZCE_MASK) | ||
| 7694 | #define CM7_MCM_ISCR_FOFCE_MASK (0x4000000U) | ||
| 7695 | #define CM7_MCM_ISCR_FOFCE_SHIFT (26U) | ||
| 7696 | /*! FOFCE - FPU Overflow Interrupt Enable | ||
| 7697 | * 0b0..Disable interrupt | ||
| 7698 | * 0b1..Enable interrupt | ||
| 7699 | */ | ||
| 7700 | #define CM7_MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFCE_SHIFT)) & CM7_MCM_ISCR_FOFCE_MASK) | ||
| 7701 | #define CM7_MCM_ISCR_FUFCE_MASK (0x8000000U) | ||
| 7702 | #define CM7_MCM_ISCR_FUFCE_SHIFT (27U) | ||
| 7703 | /*! FUFCE - FPU Underflow Interrupt Enable | ||
| 7704 | * 0b0..Disable interrupt | ||
| 7705 | * 0b1..Enable interrupt | ||
| 7706 | */ | ||
| 7707 | #define CM7_MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFCE_SHIFT)) & CM7_MCM_ISCR_FUFCE_MASK) | ||
| 7708 | #define CM7_MCM_ISCR_FIXCE_MASK (0x10000000U) | ||
| 7709 | #define CM7_MCM_ISCR_FIXCE_SHIFT (28U) | ||
| 7710 | /*! FIXCE - FPU Inexact Interrupt Enable | ||
| 7711 | * 0b0..Disable interrupt | ||
| 7712 | * 0b1..Enable interrupt | ||
| 7713 | */ | ||
| 7714 | #define CM7_MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXCE_SHIFT)) & CM7_MCM_ISCR_FIXCE_MASK) | ||
| 7715 | #define CM7_MCM_ISCR_FIDCE_MASK (0x80000000U) | ||
| 7716 | #define CM7_MCM_ISCR_FIDCE_SHIFT (31U) | ||
| 7717 | /*! FIDCE - FPU Input Denormal Interrupt Enable | ||
| 7718 | * 0b0..Disable interrupt | ||
| 7719 | * 0b1..Enable interrupt | ||
| 7720 | */ | ||
| 7721 | #define CM7_MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDCE_SHIFT)) & CM7_MCM_ISCR_FIDCE_MASK) | ||
| 7722 | /*! @} */ | ||
| 7723 | |||
| 7724 | |||
| 7725 | /*! | ||
| 7726 | * @} | ||
| 7727 | */ /* end of group CM7_MCM_Register_Masks */ | ||
| 7728 | |||
| 7729 | |||
| 7730 | /* CM7_MCM - Peripheral instance base addresses */ | ||
| 7731 | /** Peripheral CM7_MCM base address */ | ||
| 7732 | #define CM7_MCM_BASE (0xE0080000u) | ||
| 7733 | /** Peripheral CM7_MCM base pointer */ | ||
| 7734 | #define CM7_MCM ((CM7_MCM_Type *)CM7_MCM_BASE) | ||
| 7735 | /** Array initializer of CM7_MCM peripheral base addresses */ | ||
| 7736 | #define CM7_MCM_BASE_ADDRS { CM7_MCM_BASE } | ||
| 7737 | /** Array initializer of CM7_MCM peripheral base pointers */ | ||
| 7738 | #define CM7_MCM_BASE_PTRS { CM7_MCM } | ||
| 7739 | |||
| 7740 | /*! | ||
| 7741 | * @} | ||
| 7742 | */ /* end of group CM7_MCM_Peripheral_Access_Layer */ | ||
| 7743 | |||
| 7744 | |||
| 7745 | /* ---------------------------------------------------------------------------- | ||
| 7746 | -- CMP Peripheral Access Layer | ||
| 7747 | ---------------------------------------------------------------------------- */ | ||
| 7748 | |||
| 7749 | /*! | ||
| 7750 | * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer | ||
| 7751 | * @{ | ||
| 7752 | */ | ||
| 7753 | |||
| 7754 | /** CMP - Register Layout Typedef */ | ||
| 7755 | typedef struct { | ||
| 7756 | __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ | ||
| 7757 | __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ | ||
| 7758 | __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ | ||
| 7759 | __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ | ||
| 7760 | __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ | ||
| 7761 | __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ | ||
| 7762 | } CMP_Type; | ||
| 7763 | |||
| 7764 | /* ---------------------------------------------------------------------------- | ||
| 7765 | -- CMP Register Masks | ||
| 7766 | ---------------------------------------------------------------------------- */ | ||
| 7767 | |||
| 7768 | /*! | ||
| 7769 | * @addtogroup CMP_Register_Masks CMP Register Masks | ||
| 7770 | * @{ | ||
| 7771 | */ | ||
| 7772 | |||
| 7773 | /*! @name CR0 - CMP Control Register 0 */ | ||
| 7774 | /*! @{ */ | ||
| 7775 | #define CMP_CR0_HYSTCTR_MASK (0x3U) | ||
| 7776 | #define CMP_CR0_HYSTCTR_SHIFT (0U) | ||
| 7777 | /*! HYSTCTR - Comparator hard block hysteresis control | ||
| 7778 | * 0b00..Level 0 | ||
| 7779 | * 0b01..Level 1 | ||
| 7780 | * 0b10..Level 2 | ||
| 7781 | * 0b11..Level 3 | ||
| 7782 | */ | ||
| 7783 | #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) | ||
| 7784 | #define CMP_CR0_FILTER_CNT_MASK (0x70U) | ||
| 7785 | #define CMP_CR0_FILTER_CNT_SHIFT (4U) | ||
| 7786 | /*! FILTER_CNT - Filter Sample Count | ||
| 7787 | * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. | ||
| 7788 | * 0b001..One sample must agree. The comparator output is simply sampled. | ||
| 7789 | * 0b010..2 consecutive samples must agree. | ||
| 7790 | * 0b011..3 consecutive samples must agree. | ||
| 7791 | * 0b100..4 consecutive samples must agree. | ||
| 7792 | * 0b101..5 consecutive samples must agree. | ||
| 7793 | * 0b110..6 consecutive samples must agree. | ||
| 7794 | * 0b111..7 consecutive samples must agree. | ||
| 7795 | */ | ||
| 7796 | #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) | ||
| 7797 | /*! @} */ | ||
| 7798 | |||
| 7799 | /*! @name CR1 - CMP Control Register 1 */ | ||
| 7800 | /*! @{ */ | ||
| 7801 | #define CMP_CR1_EN_MASK (0x1U) | ||
| 7802 | #define CMP_CR1_EN_SHIFT (0U) | ||
| 7803 | /*! EN - Comparator Module Enable | ||
| 7804 | * 0b0..Analog Comparator is disabled. | ||
| 7805 | * 0b1..Analog Comparator is enabled. | ||
| 7806 | */ | ||
| 7807 | #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) | ||
| 7808 | #define CMP_CR1_OPE_MASK (0x2U) | ||
| 7809 | #define CMP_CR1_OPE_SHIFT (1U) | ||
| 7810 | /*! OPE - Comparator Output Pin Enable | ||
| 7811 | * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. | ||
| 7812 | * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the | ||
| 7813 | * associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this | ||
| 7814 | * bit has no effect. | ||
| 7815 | */ | ||
| 7816 | #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) | ||
| 7817 | #define CMP_CR1_COS_MASK (0x4U) | ||
| 7818 | #define CMP_CR1_COS_SHIFT (2U) | ||
| 7819 | /*! COS - Comparator Output Select | ||
| 7820 | * 0b0..Set the filtered comparator output (CMPO) to equal COUT. | ||
| 7821 | * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA. | ||
| 7822 | */ | ||
| 7823 | #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) | ||
| 7824 | #define CMP_CR1_INV_MASK (0x8U) | ||
| 7825 | #define CMP_CR1_INV_SHIFT (3U) | ||
| 7826 | /*! INV - Comparator INVERT | ||
| 7827 | * 0b0..Does not invert the comparator output. | ||
| 7828 | * 0b1..Inverts the comparator output. | ||
| 7829 | */ | ||
| 7830 | #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) | ||
| 7831 | #define CMP_CR1_PMODE_MASK (0x10U) | ||
| 7832 | #define CMP_CR1_PMODE_SHIFT (4U) | ||
| 7833 | /*! PMODE - Power Mode Select | ||
| 7834 | * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. | ||
| 7835 | * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. | ||
| 7836 | */ | ||
| 7837 | #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) | ||
| 7838 | #define CMP_CR1_WE_MASK (0x40U) | ||
| 7839 | #define CMP_CR1_WE_SHIFT (6U) | ||
| 7840 | /*! WE - Windowing Enable | ||
| 7841 | * 0b0..Windowing mode is not selected. | ||
| 7842 | * 0b1..Windowing mode is selected. | ||
| 7843 | */ | ||
| 7844 | #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) | ||
| 7845 | #define CMP_CR1_SE_MASK (0x80U) | ||
| 7846 | #define CMP_CR1_SE_SHIFT (7U) | ||
| 7847 | /*! SE - Sample Enable | ||
| 7848 | * 0b0..Sampling mode is not selected. | ||
| 7849 | * 0b1..Sampling mode is selected. | ||
| 7850 | */ | ||
| 7851 | #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) | ||
| 7852 | /*! @} */ | ||
| 7853 | |||
| 7854 | /*! @name FPR - CMP Filter Period Register */ | ||
| 7855 | /*! @{ */ | ||
| 7856 | #define CMP_FPR_FILT_PER_MASK (0xFFU) | ||
| 7857 | #define CMP_FPR_FILT_PER_SHIFT (0U) | ||
| 7858 | /*! FILT_PER - Filter Sample Period | ||
| 7859 | */ | ||
| 7860 | #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) | ||
| 7861 | /*! @} */ | ||
| 7862 | |||
| 7863 | /*! @name SCR - CMP Status and Control Register */ | ||
| 7864 | /*! @{ */ | ||
| 7865 | #define CMP_SCR_COUT_MASK (0x1U) | ||
| 7866 | #define CMP_SCR_COUT_SHIFT (0U) | ||
| 7867 | /*! COUT - Analog Comparator Output | ||
| 7868 | */ | ||
| 7869 | #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) | ||
| 7870 | #define CMP_SCR_CFF_MASK (0x2U) | ||
| 7871 | #define CMP_SCR_CFF_SHIFT (1U) | ||
| 7872 | /*! CFF - Analog Comparator Flag Falling | ||
| 7873 | * 0b0..Falling-edge on COUT has not been detected. | ||
| 7874 | * 0b1..Falling-edge on COUT has occurred. | ||
| 7875 | */ | ||
| 7876 | #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) | ||
| 7877 | #define CMP_SCR_CFR_MASK (0x4U) | ||
| 7878 | #define CMP_SCR_CFR_SHIFT (2U) | ||
| 7879 | /*! CFR - Analog Comparator Flag Rising | ||
| 7880 | * 0b0..Rising-edge on COUT has not been detected. | ||
| 7881 | * 0b1..Rising-edge on COUT has occurred. | ||
| 7882 | */ | ||
| 7883 | #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) | ||
| 7884 | #define CMP_SCR_IEF_MASK (0x8U) | ||
| 7885 | #define CMP_SCR_IEF_SHIFT (3U) | ||
| 7886 | /*! IEF - Comparator Interrupt Enable Falling | ||
| 7887 | * 0b0..Interrupt is disabled. | ||
| 7888 | * 0b1..Interrupt is enabled. | ||
| 7889 | */ | ||
| 7890 | #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) | ||
| 7891 | #define CMP_SCR_IER_MASK (0x10U) | ||
| 7892 | #define CMP_SCR_IER_SHIFT (4U) | ||
| 7893 | /*! IER - Comparator Interrupt Enable Rising | ||
| 7894 | * 0b0..Interrupt is disabled. | ||
| 7895 | * 0b1..Interrupt is enabled. | ||
| 7896 | */ | ||
| 7897 | #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) | ||
| 7898 | #define CMP_SCR_DMAEN_MASK (0x40U) | ||
| 7899 | #define CMP_SCR_DMAEN_SHIFT (6U) | ||
| 7900 | /*! DMAEN - DMA Enable Control | ||
| 7901 | * 0b0..DMA is disabled. | ||
| 7902 | * 0b1..DMA is enabled. | ||
| 7903 | */ | ||
| 7904 | #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) | ||
| 7905 | /*! @} */ | ||
| 7906 | |||
| 7907 | /*! @name DACCR - DAC Control Register */ | ||
| 7908 | /*! @{ */ | ||
| 7909 | #define CMP_DACCR_VOSEL_MASK (0x3FU) | ||
| 7910 | #define CMP_DACCR_VOSEL_SHIFT (0U) | ||
| 7911 | /*! VOSEL - DAC Output Voltage Select | ||
| 7912 | */ | ||
| 7913 | #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) | ||
| 7914 | #define CMP_DACCR_VRSEL_MASK (0x40U) | ||
| 7915 | #define CMP_DACCR_VRSEL_SHIFT (6U) | ||
| 7916 | /*! VRSEL - Supply Voltage Reference Source Select | ||
| 7917 | * 0b0..Vin1 is selected as resistor ladder network supply reference. | ||
| 7918 | * 0b1..Vin2 is selected as resistor ladder network supply reference. | ||
| 7919 | */ | ||
| 7920 | #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) | ||
| 7921 | #define CMP_DACCR_DACEN_MASK (0x80U) | ||
| 7922 | #define CMP_DACCR_DACEN_SHIFT (7U) | ||
| 7923 | /*! DACEN - DAC Enable | ||
| 7924 | * 0b0..DAC is disabled. | ||
| 7925 | * 0b1..DAC is enabled. | ||
| 7926 | */ | ||
| 7927 | #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) | ||
| 7928 | /*! @} */ | ||
| 7929 | |||
| 7930 | /*! @name MUXCR - MUX Control Register */ | ||
| 7931 | /*! @{ */ | ||
| 7932 | #define CMP_MUXCR_MSEL_MASK (0x7U) | ||
| 7933 | #define CMP_MUXCR_MSEL_SHIFT (0U) | ||
| 7934 | /*! MSEL - Minus Input Mux Control | ||
| 7935 | * 0b000..IN0 | ||
| 7936 | * 0b001..IN1 | ||
| 7937 | * 0b010..IN2 | ||
| 7938 | * 0b011..IN3 | ||
| 7939 | * 0b100..IN4 | ||
| 7940 | * 0b101..IN5 | ||
| 7941 | * 0b110..IN6 | ||
| 7942 | * 0b111..IN7 | ||
| 7943 | */ | ||
| 7944 | #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) | ||
| 7945 | #define CMP_MUXCR_PSEL_MASK (0x38U) | ||
| 7946 | #define CMP_MUXCR_PSEL_SHIFT (3U) | ||
| 7947 | /*! PSEL - Plus Input Mux Control | ||
| 7948 | * 0b000..IN0 | ||
| 7949 | * 0b001..IN1 | ||
| 7950 | * 0b010..IN2 | ||
| 7951 | * 0b011..IN3 | ||
| 7952 | * 0b100..IN4 | ||
| 7953 | * 0b101..IN5 | ||
| 7954 | * 0b110..IN6 | ||
| 7955 | * 0b111..IN7 | ||
| 7956 | */ | ||
| 7957 | #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) | ||
| 7958 | /*! @} */ | ||
| 7959 | |||
| 7960 | |||
| 7961 | /*! | ||
| 7962 | * @} | ||
| 7963 | */ /* end of group CMP_Register_Masks */ | ||
| 7964 | |||
| 7965 | |||
| 7966 | /* CMP - Peripheral instance base addresses */ | ||
| 7967 | /** Peripheral CMP1 base address */ | ||
| 7968 | #define CMP1_BASE (0x40094000u) | ||
| 7969 | /** Peripheral CMP1 base pointer */ | ||
| 7970 | #define CMP1 ((CMP_Type *)CMP1_BASE) | ||
| 7971 | /** Peripheral CMP2 base address */ | ||
| 7972 | #define CMP2_BASE (0x40094008u) | ||
| 7973 | /** Peripheral CMP2 base pointer */ | ||
| 7974 | #define CMP2 ((CMP_Type *)CMP2_BASE) | ||
| 7975 | /** Peripheral CMP3 base address */ | ||
| 7976 | #define CMP3_BASE (0x40094010u) | ||
| 7977 | /** Peripheral CMP3 base pointer */ | ||
| 7978 | #define CMP3 ((CMP_Type *)CMP3_BASE) | ||
| 7979 | /** Peripheral CMP4 base address */ | ||
| 7980 | #define CMP4_BASE (0x40094018u) | ||
| 7981 | /** Peripheral CMP4 base pointer */ | ||
| 7982 | #define CMP4 ((CMP_Type *)CMP4_BASE) | ||
| 7983 | /** Array initializer of CMP peripheral base addresses */ | ||
| 7984 | #define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE } | ||
| 7985 | /** Array initializer of CMP peripheral base pointers */ | ||
| 7986 | #define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 } | ||
| 7987 | /** Interrupt vectors for the CMP peripheral type */ | ||
| 7988 | #define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn } | ||
| 7989 | |||
| 7990 | /*! | ||
| 7991 | * @} | ||
| 7992 | */ /* end of group CMP_Peripheral_Access_Layer */ | ||
| 7993 | |||
| 7994 | |||
| 7995 | /* ---------------------------------------------------------------------------- | ||
| 7996 | -- CSU Peripheral Access Layer | ||
| 7997 | ---------------------------------------------------------------------------- */ | ||
| 7998 | |||
| 7999 | /*! | ||
| 8000 | * @addtogroup CSU_Peripheral_Access_Layer CSU Peripheral Access Layer | ||
| 8001 | * @{ | ||
| 8002 | */ | ||
| 8003 | |||
| 8004 | /** CSU - Register Layout Typedef */ | ||
| 8005 | typedef struct { | ||
| 8006 | __IO uint32_t CSL[32]; /**< Config security level register, array offset: 0x0, array step: 0x4 */ | ||
| 8007 | uint8_t RESERVED_0[384]; | ||
| 8008 | __IO uint32_t HP0; /**< HP0 register, offset: 0x200 */ | ||
| 8009 | uint8_t RESERVED_1[20]; | ||
| 8010 | __IO uint32_t SA; /**< Secure access register, offset: 0x218 */ | ||
| 8011 | uint8_t RESERVED_2[316]; | ||
| 8012 | __IO uint32_t HPCONTROL0; /**< HPCONTROL0 register, offset: 0x358 */ | ||
| 8013 | } CSU_Type; | ||
| 8014 | |||
| 8015 | /* ---------------------------------------------------------------------------- | ||
| 8016 | -- CSU Register Masks | ||
| 8017 | ---------------------------------------------------------------------------- */ | ||
| 8018 | |||
| 8019 | /*! | ||
| 8020 | * @addtogroup CSU_Register_Masks CSU Register Masks | ||
| 8021 | * @{ | ||
| 8022 | */ | ||
| 8023 | |||
| 8024 | /*! @name CSL - Config security level register */ | ||
| 8025 | /*! @{ */ | ||
| 8026 | #define CSU_CSL_SUR_S2_MASK (0x1U) | ||
| 8027 | #define CSU_CSL_SUR_S2_SHIFT (0U) | ||
| 8028 | /*! SUR_S2 | ||
| 8029 | * 0b0..The secure user read access is disabled for the second slave. | ||
| 8030 | * 0b1..The secure user read access is enabled for the second slave. | ||
| 8031 | */ | ||
| 8032 | #define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK) | ||
| 8033 | #define CSU_CSL_SSR_S2_MASK (0x2U) | ||
| 8034 | #define CSU_CSL_SSR_S2_SHIFT (1U) | ||
| 8035 | /*! SSR_S2 | ||
| 8036 | * 0b0..The secure supervisor read access is disabled for the second slave. | ||
| 8037 | * 0b1..The secure supervisor read access is enabled for the second slave. | ||
| 8038 | */ | ||
| 8039 | #define CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK) | ||
| 8040 | #define CSU_CSL_NUR_S2_MASK (0x4U) | ||
| 8041 | #define CSU_CSL_NUR_S2_SHIFT (2U) | ||
| 8042 | /*! NUR_S2 | ||
| 8043 | * 0b0..The non-secure user read access is disabled for the second slave. | ||
| 8044 | * 0b1..The non-secure user read access is enabled for the second slave. | ||
| 8045 | */ | ||
| 8046 | #define CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK) | ||
| 8047 | #define CSU_CSL_NSR_S2_MASK (0x8U) | ||
| 8048 | #define CSU_CSL_NSR_S2_SHIFT (3U) | ||
| 8049 | /*! NSR_S2 | ||
| 8050 | * 0b0..The non-secure supervisor read access is disabled for the second slave. | ||
| 8051 | * 0b1..The non-secure supervisor read access is enabled for the second slave. | ||
| 8052 | */ | ||
| 8053 | #define CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK) | ||
| 8054 | #define CSU_CSL_SUW_S2_MASK (0x10U) | ||
| 8055 | #define CSU_CSL_SUW_S2_SHIFT (4U) | ||
| 8056 | /*! SUW_S2 | ||
| 8057 | * 0b0..The secure user write access is disabled for the second slave. | ||
| 8058 | * 0b1..The secure user write access is enabled for the second slave. | ||
| 8059 | */ | ||
| 8060 | #define CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK) | ||
| 8061 | #define CSU_CSL_SSW_S2_MASK (0x20U) | ||
| 8062 | #define CSU_CSL_SSW_S2_SHIFT (5U) | ||
| 8063 | /*! SSW_S2 | ||
| 8064 | * 0b0..The secure supervisor write access is disabled for the second slave. | ||
| 8065 | * 0b1..The secure supervisor write access is enabled for the second slave. | ||
| 8066 | */ | ||
| 8067 | #define CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK) | ||
| 8068 | #define CSU_CSL_NUW_S2_MASK (0x40U) | ||
| 8069 | #define CSU_CSL_NUW_S2_SHIFT (6U) | ||
| 8070 | /*! NUW_S2 | ||
| 8071 | * 0b0..The non-secure user write access is disabled for the second slave. | ||
| 8072 | * 0b1..The non-secure user write access is enabled for the second slave. | ||
| 8073 | */ | ||
| 8074 | #define CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK) | ||
| 8075 | #define CSU_CSL_NSW_S2_MASK (0x80U) | ||
| 8076 | #define CSU_CSL_NSW_S2_SHIFT (7U) | ||
| 8077 | /*! NSW_S2 | ||
| 8078 | * 0b0..The non-secure supervisor write access is disabled for the second slave. | ||
| 8079 | * 0b1..The non-secure supervisor write access is enabled for the second slave. | ||
| 8080 | */ | ||
| 8081 | #define CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK) | ||
| 8082 | #define CSU_CSL_LOCK_S2_MASK (0x100U) | ||
| 8083 | #define CSU_CSL_LOCK_S2_SHIFT (8U) | ||
| 8084 | /*! LOCK_S2 | ||
| 8085 | * 0b0..Not locked. Bits 7-0 can be written by the software. | ||
| 8086 | * 0b1..Bits 7-0 are locked and cannot be written by the software | ||
| 8087 | */ | ||
| 8088 | #define CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK) | ||
| 8089 | #define CSU_CSL_SUR_S1_MASK (0x10000U) | ||
| 8090 | #define CSU_CSL_SUR_S1_SHIFT (16U) | ||
| 8091 | /*! SUR_S1 | ||
| 8092 | * 0b0..The secure user read access is disabled for the first slave. | ||
| 8093 | * 0b1..The secure user read access is enabled for the first slave. | ||
| 8094 | */ | ||
| 8095 | #define CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK) | ||
| 8096 | #define CSU_CSL_SSR_S1_MASK (0x20000U) | ||
| 8097 | #define CSU_CSL_SSR_S1_SHIFT (17U) | ||
| 8098 | /*! SSR_S1 | ||
| 8099 | * 0b0..The secure supervisor read access is disabled for the first slave. | ||
| 8100 | * 0b1..The secure supervisor read access is enabled for the first slave. | ||
| 8101 | */ | ||
| 8102 | #define CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK) | ||
| 8103 | #define CSU_CSL_NUR_S1_MASK (0x40000U) | ||
| 8104 | #define CSU_CSL_NUR_S1_SHIFT (18U) | ||
| 8105 | /*! NUR_S1 | ||
| 8106 | * 0b0..The non-secure user read access is disabled for the first slave. | ||
| 8107 | * 0b1..The non-secure user read access is enabled for the first slave. | ||
| 8108 | */ | ||
| 8109 | #define CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK) | ||
| 8110 | #define CSU_CSL_NSR_S1_MASK (0x80000U) | ||
| 8111 | #define CSU_CSL_NSR_S1_SHIFT (19U) | ||
| 8112 | /*! NSR_S1 | ||
| 8113 | * 0b0..The non-secure supervisor read access is disabled for the first slave. | ||
| 8114 | * 0b1..The non-secure supervisor read access is enabled for the first slave. | ||
| 8115 | */ | ||
| 8116 | #define CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK) | ||
| 8117 | #define CSU_CSL_SUW_S1_MASK (0x100000U) | ||
| 8118 | #define CSU_CSL_SUW_S1_SHIFT (20U) | ||
| 8119 | /*! SUW_S1 | ||
| 8120 | * 0b0..The secure user write access is disabled for the first slave. | ||
| 8121 | * 0b1..The secure user write access is enabled for the first slave. | ||
| 8122 | */ | ||
| 8123 | #define CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK) | ||
| 8124 | #define CSU_CSL_SSW_S1_MASK (0x200000U) | ||
| 8125 | #define CSU_CSL_SSW_S1_SHIFT (21U) | ||
| 8126 | /*! SSW_S1 | ||
| 8127 | * 0b0..The secure supervisor write access is disabled for the first slave. | ||
| 8128 | * 0b1..The secure supervisor write access is enabled for the first slave. | ||
| 8129 | */ | ||
| 8130 | #define CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK) | ||
| 8131 | #define CSU_CSL_NUW_S1_MASK (0x400000U) | ||
| 8132 | #define CSU_CSL_NUW_S1_SHIFT (22U) | ||
| 8133 | /*! NUW_S1 | ||
| 8134 | * 0b0..The non-secure user write access is disabled for the first slave. | ||
| 8135 | * 0b1..The non-secure user write access is enabled for the first slave. | ||
| 8136 | */ | ||
| 8137 | #define CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK) | ||
| 8138 | #define CSU_CSL_NSW_S1_MASK (0x800000U) | ||
| 8139 | #define CSU_CSL_NSW_S1_SHIFT (23U) | ||
| 8140 | /*! NSW_S1 | ||
| 8141 | * 0b0..The non-secure supervisor write access is disabled for the first slave. | ||
| 8142 | * 0b1..The non-secure supervisor write access is enabled for the first slave | ||
| 8143 | */ | ||
| 8144 | #define CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK) | ||
| 8145 | #define CSU_CSL_LOCK_S1_MASK (0x1000000U) | ||
| 8146 | #define CSU_CSL_LOCK_S1_SHIFT (24U) | ||
| 8147 | /*! LOCK_S1 | ||
| 8148 | * 0b0..Not locked. The bits 16-23 can be written by the software. | ||
| 8149 | * 0b1..The bits 16-23 are locked and can't be written by the software. | ||
| 8150 | */ | ||
| 8151 | #define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK) | ||
| 8152 | /*! @} */ | ||
| 8153 | |||
| 8154 | /* The count of CSU_CSL */ | ||
| 8155 | #define CSU_CSL_COUNT (32U) | ||
| 8156 | |||
| 8157 | /*! @name HP0 - HP0 register */ | ||
| 8158 | /*! @{ */ | ||
| 8159 | #define CSU_HP0_HP_DMA_MASK (0x4U) | ||
| 8160 | #define CSU_HP0_HP_DMA_SHIFT (2U) | ||
| 8161 | /*! HP_DMA | ||
| 8162 | * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. | ||
| 8163 | * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. | ||
| 8164 | */ | ||
| 8165 | #define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK) | ||
| 8166 | #define CSU_HP0_L_DMA_MASK (0x8U) | ||
| 8167 | #define CSU_HP0_L_DMA_SHIFT (3U) | ||
| 8168 | /*! L_DMA | ||
| 8169 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8170 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8171 | */ | ||
| 8172 | #define CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK) | ||
| 8173 | #define CSU_HP0_HP_LCDIF_MASK (0x10U) | ||
| 8174 | #define CSU_HP0_HP_LCDIF_SHIFT (4U) | ||
| 8175 | /*! HP_LCDIF | ||
| 8176 | * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. | ||
| 8177 | * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. | ||
| 8178 | */ | ||
| 8179 | #define CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK) | ||
| 8180 | #define CSU_HP0_L_LCDIF_MASK (0x20U) | ||
| 8181 | #define CSU_HP0_L_LCDIF_SHIFT (5U) | ||
| 8182 | /*! L_LCDIF | ||
| 8183 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8184 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8185 | */ | ||
| 8186 | #define CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK) | ||
| 8187 | #define CSU_HP0_HP_CSI_MASK (0x40U) | ||
| 8188 | #define CSU_HP0_HP_CSI_SHIFT (6U) | ||
| 8189 | /*! HP_CSI | ||
| 8190 | * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. | ||
| 8191 | * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. | ||
| 8192 | */ | ||
| 8193 | #define CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK) | ||
| 8194 | #define CSU_HP0_L_CSI_MASK (0x80U) | ||
| 8195 | #define CSU_HP0_L_CSI_SHIFT (7U) | ||
| 8196 | /*! L_CSI | ||
| 8197 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8198 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8199 | */ | ||
| 8200 | #define CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK) | ||
| 8201 | #define CSU_HP0_HP_PXP_MASK (0x100U) | ||
| 8202 | #define CSU_HP0_HP_PXP_SHIFT (8U) | ||
| 8203 | /*! HP_PXP | ||
| 8204 | * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. | ||
| 8205 | * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. | ||
| 8206 | */ | ||
| 8207 | #define CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK) | ||
| 8208 | #define CSU_HP0_L_PXP_MASK (0x200U) | ||
| 8209 | #define CSU_HP0_L_PXP_SHIFT (9U) | ||
| 8210 | /*! L_PXP | ||
| 8211 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8212 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8213 | */ | ||
| 8214 | #define CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK) | ||
| 8215 | #define CSU_HP0_HP_DCP_MASK (0x400U) | ||
| 8216 | #define CSU_HP0_HP_DCP_SHIFT (10U) | ||
| 8217 | /*! HP_DCP | ||
| 8218 | * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. | ||
| 8219 | * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. | ||
| 8220 | */ | ||
| 8221 | #define CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK) | ||
| 8222 | #define CSU_HP0_L_DCP_MASK (0x800U) | ||
| 8223 | #define CSU_HP0_L_DCP_SHIFT (11U) | ||
| 8224 | /*! L_DCP | ||
| 8225 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8226 | * 0b1..Lock-the adjacent (next lower) bit cannot be written by the software. | ||
| 8227 | */ | ||
| 8228 | #define CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK) | ||
| 8229 | #define CSU_HP0_HP_ENET_MASK (0x4000U) | ||
| 8230 | #define CSU_HP0_HP_ENET_SHIFT (14U) | ||
| 8231 | /*! HP_ENET | ||
| 8232 | * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. | ||
| 8233 | * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. | ||
| 8234 | */ | ||
| 8235 | #define CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK) | ||
| 8236 | #define CSU_HP0_L_ENET_MASK (0x8000U) | ||
| 8237 | #define CSU_HP0_L_ENET_SHIFT (15U) | ||
| 8238 | /*! L_ENET | ||
| 8239 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8240 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8241 | */ | ||
| 8242 | #define CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK) | ||
| 8243 | #define CSU_HP0_HP_USDHC1_MASK (0x10000U) | ||
| 8244 | #define CSU_HP0_HP_USDHC1_SHIFT (16U) | ||
| 8245 | /*! HP_USDHC1 | ||
| 8246 | * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. | ||
| 8247 | * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. | ||
| 8248 | */ | ||
| 8249 | #define CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK) | ||
| 8250 | #define CSU_HP0_L_USDHC1_MASK (0x20000U) | ||
| 8251 | #define CSU_HP0_L_USDHC1_SHIFT (17U) | ||
| 8252 | /*! L_USDHC1 | ||
| 8253 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8254 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8255 | */ | ||
| 8256 | #define CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK) | ||
| 8257 | #define CSU_HP0_HP_USDHC2_MASK (0x40000U) | ||
| 8258 | #define CSU_HP0_HP_USDHC2_SHIFT (18U) | ||
| 8259 | /*! HP_USDHC2 | ||
| 8260 | * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. | ||
| 8261 | * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. | ||
| 8262 | */ | ||
| 8263 | #define CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK) | ||
| 8264 | #define CSU_HP0_L_USDHC2_MASK (0x80000U) | ||
| 8265 | #define CSU_HP0_L_USDHC2_SHIFT (19U) | ||
| 8266 | /*! L_USDHC2 | ||
| 8267 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8268 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8269 | */ | ||
| 8270 | #define CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK) | ||
| 8271 | #define CSU_HP0_HP_TPSMP_MASK (0x100000U) | ||
| 8272 | #define CSU_HP0_HP_TPSMP_SHIFT (20U) | ||
| 8273 | /*! HP_TPSMP | ||
| 8274 | * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. | ||
| 8275 | * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. | ||
| 8276 | */ | ||
| 8277 | #define CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK) | ||
| 8278 | #define CSU_HP0_L_TPSMP_MASK (0x200000U) | ||
| 8279 | #define CSU_HP0_L_TPSMP_SHIFT (21U) | ||
| 8280 | /*! L_TPSMP | ||
| 8281 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8282 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8283 | */ | ||
| 8284 | #define CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK) | ||
| 8285 | #define CSU_HP0_HP_USB_MASK (0x400000U) | ||
| 8286 | #define CSU_HP0_HP_USB_SHIFT (22U) | ||
| 8287 | /*! HP_USB | ||
| 8288 | * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. | ||
| 8289 | * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. | ||
| 8290 | */ | ||
| 8291 | #define CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK) | ||
| 8292 | #define CSU_HP0_L_USB_MASK (0x800000U) | ||
| 8293 | #define CSU_HP0_L_USB_SHIFT (23U) | ||
| 8294 | /*! L_USB | ||
| 8295 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8296 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8297 | */ | ||
| 8298 | #define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK) | ||
| 8299 | /*! @} */ | ||
| 8300 | |||
| 8301 | /*! @name SA - Secure access register */ | ||
| 8302 | /*! @{ */ | ||
| 8303 | #define CSU_SA_NSA_DMA_MASK (0x4U) | ||
| 8304 | #define CSU_SA_NSA_DMA_SHIFT (2U) | ||
| 8305 | /*! NSA_DMA - Non-secure access policy indicator bit | ||
| 8306 | * 0b0..Secure access for the corresponding type-1 master | ||
| 8307 | * 0b1..Non-secure access for the corresponding type-1 master | ||
| 8308 | */ | ||
| 8309 | #define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK) | ||
| 8310 | #define CSU_SA_L_DMA_MASK (0x8U) | ||
| 8311 | #define CSU_SA_L_DMA_SHIFT (3U) | ||
| 8312 | /*! L_DMA | ||
| 8313 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8314 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8315 | */ | ||
| 8316 | #define CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK) | ||
| 8317 | #define CSU_SA_NSA_LCDIF_MASK (0x10U) | ||
| 8318 | #define CSU_SA_NSA_LCDIF_SHIFT (4U) | ||
| 8319 | /*! NSA_LCDIF - Non-secure access policy indicator bit | ||
| 8320 | * 0b0..Secure access for the corresponding type-1 master | ||
| 8321 | * 0b1..Non-secure access for the corresponding type-1 master | ||
| 8322 | */ | ||
| 8323 | #define CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK) | ||
| 8324 | #define CSU_SA_L_LCDIF_MASK (0x20U) | ||
| 8325 | #define CSU_SA_L_LCDIF_SHIFT (5U) | ||
| 8326 | /*! L_LCDIF | ||
| 8327 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8328 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8329 | */ | ||
| 8330 | #define CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK) | ||
| 8331 | #define CSU_SA_NSA_CSI_MASK (0x40U) | ||
| 8332 | #define CSU_SA_NSA_CSI_SHIFT (6U) | ||
| 8333 | /*! NSA_CSI - Non-secure access policy indicator bit | ||
| 8334 | * 0b0..Secure access for the corresponding type-1 master | ||
| 8335 | * 0b1..Non-secure access for the corresponding type-1 master | ||
| 8336 | */ | ||
| 8337 | #define CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK) | ||
| 8338 | #define CSU_SA_L_CSI_MASK (0x80U) | ||
| 8339 | #define CSU_SA_L_CSI_SHIFT (7U) | ||
| 8340 | /*! L_CSI | ||
| 8341 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8342 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8343 | */ | ||
| 8344 | #define CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK) | ||
| 8345 | #define CSU_SA_NSA_PXP_MASK (0x100U) | ||
| 8346 | #define CSU_SA_NSA_PXP_SHIFT (8U) | ||
| 8347 | /*! NSA_PXP - Non-Secure Access Policy indicator bit | ||
| 8348 | * 0b0..Secure access for the corresponding type-1 master | ||
| 8349 | * 0b1..Non-secure access for the corresponding type-1 master | ||
| 8350 | */ | ||
| 8351 | #define CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK) | ||
| 8352 | #define CSU_SA_L_PXP_MASK (0x200U) | ||
| 8353 | #define CSU_SA_L_PXP_SHIFT (9U) | ||
| 8354 | /*! L_PXP | ||
| 8355 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8356 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8357 | */ | ||
| 8358 | #define CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK) | ||
| 8359 | #define CSU_SA_NSA_DCP_MASK (0x400U) | ||
| 8360 | #define CSU_SA_NSA_DCP_SHIFT (10U) | ||
| 8361 | /*! NSA_DCP - Non-secure access policy indicator bit | ||
| 8362 | * 0b0..Secure access for the corresponding type-1 master | ||
| 8363 | * 0b1..Non-secure access for the corresponding type-1 master | ||
| 8364 | */ | ||
| 8365 | #define CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK) | ||
| 8366 | #define CSU_SA_L_DCP_MASK (0x800U) | ||
| 8367 | #define CSU_SA_L_DCP_SHIFT (11U) | ||
| 8368 | /*! L_DCP | ||
| 8369 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8370 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8371 | */ | ||
| 8372 | #define CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK) | ||
| 8373 | #define CSU_SA_NSA_ENET_MASK (0x4000U) | ||
| 8374 | #define CSU_SA_NSA_ENET_SHIFT (14U) | ||
| 8375 | /*! NSA_ENET - Non-secure access policy indicator bit | ||
| 8376 | * 0b0..Secure access for the corresponding type-1 master | ||
| 8377 | * 0b1..Non-secure access for the corresponding type-1 master | ||
| 8378 | */ | ||
| 8379 | #define CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK) | ||
| 8380 | #define CSU_SA_L_ENET_MASK (0x8000U) | ||
| 8381 | #define CSU_SA_L_ENET_SHIFT (15U) | ||
| 8382 | /*! L_ENET | ||
| 8383 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8384 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8385 | */ | ||
| 8386 | #define CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK) | ||
| 8387 | #define CSU_SA_NSA_USDHC1_MASK (0x10000U) | ||
| 8388 | #define CSU_SA_NSA_USDHC1_SHIFT (16U) | ||
| 8389 | /*! NSA_USDHC1 - Non-secure access policy indicator bit | ||
| 8390 | * 0b0..Secure access for the corresponding type-1 master | ||
| 8391 | * 0b1..Non-secure access for the corresponding type-1 master | ||
| 8392 | */ | ||
| 8393 | #define CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK) | ||
| 8394 | #define CSU_SA_L_USDHC1_MASK (0x20000U) | ||
| 8395 | #define CSU_SA_L_USDHC1_SHIFT (17U) | ||
| 8396 | /*! L_USDHC1 | ||
| 8397 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8398 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8399 | */ | ||
| 8400 | #define CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK) | ||
| 8401 | #define CSU_SA_NSA_USDHC2_MASK (0x40000U) | ||
| 8402 | #define CSU_SA_NSA_USDHC2_SHIFT (18U) | ||
| 8403 | /*! NSA_USDHC2 - Non-secure access policy indicator bit | ||
| 8404 | * 0b0..Secure access for the corresponding type-1 master | ||
| 8405 | * 0b1..Non-secure access for the corresponding type-1 master | ||
| 8406 | */ | ||
| 8407 | #define CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK) | ||
| 8408 | #define CSU_SA_L_USDHC2_MASK (0x80000U) | ||
| 8409 | #define CSU_SA_L_USDHC2_SHIFT (19U) | ||
| 8410 | /*! L_USDHC2 | ||
| 8411 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8412 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8413 | */ | ||
| 8414 | #define CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK) | ||
| 8415 | #define CSU_SA_NSA_TPSMP_MASK (0x100000U) | ||
| 8416 | #define CSU_SA_NSA_TPSMP_SHIFT (20U) | ||
| 8417 | /*! NSA_TPSMP - Non-secure access policy indicator bit | ||
| 8418 | * 0b0..Secure access for the corresponding type-1 master | ||
| 8419 | * 0b1..Non-secure access for the corresponding type-1 master | ||
| 8420 | */ | ||
| 8421 | #define CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK) | ||
| 8422 | #define CSU_SA_L_TPSMP_MASK (0x200000U) | ||
| 8423 | #define CSU_SA_L_TPSMP_SHIFT (21U) | ||
| 8424 | /*! L_TPSMP | ||
| 8425 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8426 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8427 | */ | ||
| 8428 | #define CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK) | ||
| 8429 | #define CSU_SA_NSA_USB_MASK (0x400000U) | ||
| 8430 | #define CSU_SA_NSA_USB_SHIFT (22U) | ||
| 8431 | /*! NSA_USB - Non-secure access policy indicator bit | ||
| 8432 | * 0b0..Secure access for the corresponding type-1 master | ||
| 8433 | * 0b1..Non-secure access for the corresponding type-1 master | ||
| 8434 | */ | ||
| 8435 | #define CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK) | ||
| 8436 | #define CSU_SA_L_USB_MASK (0x800000U) | ||
| 8437 | #define CSU_SA_L_USB_SHIFT (23U) | ||
| 8438 | /*! L_USB | ||
| 8439 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8440 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8441 | */ | ||
| 8442 | #define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK) | ||
| 8443 | /*! @} */ | ||
| 8444 | |||
| 8445 | /*! @name HPCONTROL0 - HPCONTROL0 register */ | ||
| 8446 | /*! @{ */ | ||
| 8447 | #define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U) | ||
| 8448 | #define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U) | ||
| 8449 | /*! HPC_DMA | ||
| 8450 | * 0b0..User mode for the corresponding master | ||
| 8451 | * 0b1..Supervisor mode for the corresponding master | ||
| 8452 | */ | ||
| 8453 | #define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK) | ||
| 8454 | #define CSU_HPCONTROL0_L_DMA_MASK (0x8U) | ||
| 8455 | #define CSU_HPCONTROL0_L_DMA_SHIFT (3U) | ||
| 8456 | /*! L_DMA | ||
| 8457 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8458 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8459 | */ | ||
| 8460 | #define CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK) | ||
| 8461 | #define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U) | ||
| 8462 | #define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U) | ||
| 8463 | /*! HPC_LCDIF | ||
| 8464 | * 0b0..User mode for the corresponding master | ||
| 8465 | * 0b1..Supervisor mode for the corresponding master | ||
| 8466 | */ | ||
| 8467 | #define CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK) | ||
| 8468 | #define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U) | ||
| 8469 | #define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U) | ||
| 8470 | /*! L_LCDIF | ||
| 8471 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8472 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8473 | */ | ||
| 8474 | #define CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK) | ||
| 8475 | #define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U) | ||
| 8476 | #define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U) | ||
| 8477 | /*! HPC_CSI | ||
| 8478 | * 0b0..User mode for the corresponding master | ||
| 8479 | * 0b1..Supervisor mode for the corresponding master | ||
| 8480 | */ | ||
| 8481 | #define CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK) | ||
| 8482 | #define CSU_HPCONTROL0_L_CSI_MASK (0x80U) | ||
| 8483 | #define CSU_HPCONTROL0_L_CSI_SHIFT (7U) | ||
| 8484 | /*! L_CSI | ||
| 8485 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8486 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8487 | */ | ||
| 8488 | #define CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK) | ||
| 8489 | #define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U) | ||
| 8490 | #define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U) | ||
| 8491 | /*! HPC_PXP | ||
| 8492 | * 0b0..User mode for the corresponding master | ||
| 8493 | * 0b1..Supervisor mode for the corresponding master | ||
| 8494 | */ | ||
| 8495 | #define CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK) | ||
| 8496 | #define CSU_HPCONTROL0_L_PXP_MASK (0x200U) | ||
| 8497 | #define CSU_HPCONTROL0_L_PXP_SHIFT (9U) | ||
| 8498 | /*! L_PXP | ||
| 8499 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8500 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8501 | */ | ||
| 8502 | #define CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK) | ||
| 8503 | #define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U) | ||
| 8504 | #define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U) | ||
| 8505 | /*! HPC_DCP | ||
| 8506 | * 0b0..User mode for the corresponding master | ||
| 8507 | * 0b1..Supervisor mode for the corresponding master | ||
| 8508 | */ | ||
| 8509 | #define CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK) | ||
| 8510 | #define CSU_HPCONTROL0_L_DCP_MASK (0x800U) | ||
| 8511 | #define CSU_HPCONTROL0_L_DCP_SHIFT (11U) | ||
| 8512 | /*! L_DCP | ||
| 8513 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8514 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8515 | */ | ||
| 8516 | #define CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK) | ||
| 8517 | #define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U) | ||
| 8518 | #define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U) | ||
| 8519 | /*! HPC_ENET | ||
| 8520 | * 0b0..User mode for the corresponding master | ||
| 8521 | * 0b1..Supervisor mode for the corresponding master | ||
| 8522 | */ | ||
| 8523 | #define CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK) | ||
| 8524 | #define CSU_HPCONTROL0_L_ENET_MASK (0x8000U) | ||
| 8525 | #define CSU_HPCONTROL0_L_ENET_SHIFT (15U) | ||
| 8526 | /*! L_ENET | ||
| 8527 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8528 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8529 | */ | ||
| 8530 | #define CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK) | ||
| 8531 | #define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U) | ||
| 8532 | #define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U) | ||
| 8533 | /*! HPC_USDHC1 | ||
| 8534 | * 0b0..User mode for the corresponding master | ||
| 8535 | * 0b1..Supervisor mode for the corresponding master | ||
| 8536 | */ | ||
| 8537 | #define CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK) | ||
| 8538 | #define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U) | ||
| 8539 | #define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U) | ||
| 8540 | /*! L_USDHC1 | ||
| 8541 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8542 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8543 | */ | ||
| 8544 | #define CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK) | ||
| 8545 | #define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U) | ||
| 8546 | #define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U) | ||
| 8547 | /*! HPC_USDHC2 | ||
| 8548 | * 0b0..User mode for the corresponding master | ||
| 8549 | * 0b1..Supervisor mode for the corresponding master | ||
| 8550 | */ | ||
| 8551 | #define CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK) | ||
| 8552 | #define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U) | ||
| 8553 | #define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U) | ||
| 8554 | /*! L_USDHC2 | ||
| 8555 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8556 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8557 | */ | ||
| 8558 | #define CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK) | ||
| 8559 | #define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U) | ||
| 8560 | #define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U) | ||
| 8561 | /*! HPC_TPSMP | ||
| 8562 | * 0b0..User mode for the corresponding master | ||
| 8563 | * 0b1..Supervisor mode for the corresponding master | ||
| 8564 | */ | ||
| 8565 | #define CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK) | ||
| 8566 | #define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U) | ||
| 8567 | #define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U) | ||
| 8568 | /*! L_TPSMP | ||
| 8569 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8570 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8571 | */ | ||
| 8572 | #define CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK) | ||
| 8573 | #define CSU_HPCONTROL0_HPC_USB_MASK (0x400000U) | ||
| 8574 | #define CSU_HPCONTROL0_HPC_USB_SHIFT (22U) | ||
| 8575 | /*! HPC_USB | ||
| 8576 | * 0b0..User mode for the corresponding master | ||
| 8577 | * 0b1..Supervisor mode for the corresponding master | ||
| 8578 | */ | ||
| 8579 | #define CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK) | ||
| 8580 | #define CSU_HPCONTROL0_L_USB_MASK (0x800000U) | ||
| 8581 | #define CSU_HPCONTROL0_L_USB_SHIFT (23U) | ||
| 8582 | /*! L_USB | ||
| 8583 | * 0b0..No lock-the adjacent (next lower) bit can be written by the software. | ||
| 8584 | * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. | ||
| 8585 | */ | ||
| 8586 | #define CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK) | ||
| 8587 | /*! @} */ | ||
| 8588 | |||
| 8589 | |||
| 8590 | /*! | ||
| 8591 | * @} | ||
| 8592 | */ /* end of group CSU_Register_Masks */ | ||
| 8593 | |||
| 8594 | |||
| 8595 | /* CSU - Peripheral instance base addresses */ | ||
| 8596 | /** Peripheral CSU base address */ | ||
| 8597 | #define CSU_BASE (0x400DC000u) | ||
| 8598 | /** Peripheral CSU base pointer */ | ||
| 8599 | #define CSU ((CSU_Type *)CSU_BASE) | ||
| 8600 | /** Array initializer of CSU peripheral base addresses */ | ||
| 8601 | #define CSU_BASE_ADDRS { CSU_BASE } | ||
| 8602 | /** Array initializer of CSU peripheral base pointers */ | ||
| 8603 | #define CSU_BASE_PTRS { CSU } | ||
| 8604 | |||
| 8605 | /*! | ||
| 8606 | * @} | ||
| 8607 | */ /* end of group CSU_Peripheral_Access_Layer */ | ||
| 8608 | |||
| 8609 | |||
| 8610 | /* ---------------------------------------------------------------------------- | ||
| 8611 | -- DCDC Peripheral Access Layer | ||
| 8612 | ---------------------------------------------------------------------------- */ | ||
| 8613 | |||
| 8614 | /*! | ||
| 8615 | * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer | ||
| 8616 | * @{ | ||
| 8617 | */ | ||
| 8618 | |||
| 8619 | /** DCDC - Register Layout Typedef */ | ||
| 8620 | typedef struct { | ||
| 8621 | __IO uint32_t REG0; /**< DCDC Register 0, offset: 0x0 */ | ||
| 8622 | __IO uint32_t REG1; /**< DCDC Register 1, offset: 0x4 */ | ||
| 8623 | __IO uint32_t REG2; /**< DCDC Register 2, offset: 0x8 */ | ||
| 8624 | __IO uint32_t REG3; /**< DCDC Register 3, offset: 0xC */ | ||
| 8625 | } DCDC_Type; | ||
| 8626 | |||
| 8627 | /* ---------------------------------------------------------------------------- | ||
| 8628 | -- DCDC Register Masks | ||
| 8629 | ---------------------------------------------------------------------------- */ | ||
| 8630 | |||
| 8631 | /*! | ||
| 8632 | * @addtogroup DCDC_Register_Masks DCDC Register Masks | ||
| 8633 | * @{ | ||
| 8634 | */ | ||
| 8635 | |||
| 8636 | /*! @name REG0 - DCDC Register 0 */ | ||
| 8637 | /*! @{ */ | ||
| 8638 | #define DCDC_REG0_PWD_ZCD_MASK (0x1U) | ||
| 8639 | #define DCDC_REG0_PWD_ZCD_SHIFT (0U) | ||
| 8640 | /*! PWD_ZCD - Power Down Zero Cross Detection | ||
| 8641 | * 0b0..Zero cross detetion function powered up | ||
| 8642 | * 0b1..Zero cross detetion function powered down | ||
| 8643 | */ | ||
| 8644 | #define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK) | ||
| 8645 | #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) | ||
| 8646 | #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U) | ||
| 8647 | /*! DISABLE_AUTO_CLK_SWITCH - Disable Auto Clock Switch | ||
| 8648 | * 0b0..If DISABLE_AUTO_CLK_SWITCH is set to 0 and 24M xtal is OK, the clock source will switch from internal ring OSC to 24M xtal automatically | ||
| 8649 | * 0b1..If DISABLE_AUTO_CLK_SWITCH is set to 1, SEL_CLK will determine which clock source the DCDC uses | ||
| 8650 | */ | ||
| 8651 | #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK) | ||
| 8652 | #define DCDC_REG0_SEL_CLK_MASK (0x4U) | ||
| 8653 | #define DCDC_REG0_SEL_CLK_SHIFT (2U) | ||
| 8654 | /*! SEL_CLK - Select Clock | ||
| 8655 | * 0b0..DCDC uses internal ring oscillator | ||
| 8656 | * 0b1..DCDC uses 24M xtal | ||
| 8657 | */ | ||
| 8658 | #define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK) | ||
| 8659 | #define DCDC_REG0_PWD_OSC_INT_MASK (0x8U) | ||
| 8660 | #define DCDC_REG0_PWD_OSC_INT_SHIFT (3U) | ||
| 8661 | /*! PWD_OSC_INT - Power down internal osc | ||
| 8662 | * 0b0..Internal oscillator powered up | ||
| 8663 | * 0b1..Internal oscillator powered down | ||
| 8664 | */ | ||
| 8665 | #define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK) | ||
| 8666 | #define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U) | ||
| 8667 | #define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U) | ||
| 8668 | /*! PWD_CUR_SNS_CMP - Power down signal of the current detector. | ||
| 8669 | * 0b0..Current Detector powered up | ||
| 8670 | * 0b1..Current Detector powered down | ||
| 8671 | */ | ||
| 8672 | #define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK) | ||
| 8673 | #define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U) | ||
| 8674 | #define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U) | ||
| 8675 | /*! CUR_SNS_THRSH - Current Sense (detector) Threshold | ||
| 8676 | * 0b000..150 mA | ||
| 8677 | * 0b001..250 mA | ||
| 8678 | * 0b010..350 mA | ||
| 8679 | * 0b011..450 mA | ||
| 8680 | * 0b100..550 mA | ||
| 8681 | * 0b101..650 mA | ||
| 8682 | */ | ||
| 8683 | #define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK) | ||
| 8684 | #define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U) | ||
| 8685 | #define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U) | ||
| 8686 | /*! PWD_OVERCUR_DET - Power down overcurrent detection comparator | ||
| 8687 | * 0b0..Overcurrent detection comparator is enabled | ||
| 8688 | * 0b1..Overcurrent detection comparator is disabled | ||
| 8689 | */ | ||
| 8690 | #define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK) | ||
| 8691 | #define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U) | ||
| 8692 | #define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U) | ||
| 8693 | /*! OVERCUR_TRIG_ADJ - Overcurrent Trigger Adjust | ||
| 8694 | * 0b00..In Run Mode, 1 A. In Power Save Mode, 0.25 A | ||
| 8695 | * 0b01..In Run Mode, 2 A. In Power Save Mode, 0.25 A | ||
| 8696 | * 0b10..In Run Mode, 1 A. In Power Save Mode, 0.2 A | ||
| 8697 | * 0b11..In Run Mode, 2 A. In Power Save Mode, 0.2 A | ||
| 8698 | */ | ||
| 8699 | #define DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK) | ||
| 8700 | #define DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U) | ||
| 8701 | #define DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U) | ||
| 8702 | /*! PWD_CMP_BATT_DET - Power Down Battery Detection Comparator | ||
| 8703 | * 0b0..Low voltage detection comparator is enabled | ||
| 8704 | * 0b1..Low voltage detection comparator is disabled | ||
| 8705 | */ | ||
| 8706 | #define DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK) | ||
| 8707 | #define DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U) | ||
| 8708 | #define DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U) | ||
| 8709 | /*! EN_LP_OVERLOAD_SNS - Low Power Overload Sense Enable | ||
| 8710 | * 0b0..Overload Detection in power save mode disabled | ||
| 8711 | * 0b1..Overload Detection in power save mode enabled | ||
| 8712 | */ | ||
| 8713 | #define DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK) | ||
| 8714 | #define DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U) | ||
| 8715 | #define DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U) | ||
| 8716 | /*! PWD_HIGH_VOLT_DET - Power Down High Voltage Detection | ||
| 8717 | * 0b0..Overvoltage detection comparator is enabled | ||
| 8718 | * 0b1..Overvoltage detection comparator is disabled | ||
| 8719 | */ | ||
| 8720 | #define DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK) | ||
| 8721 | #define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U) | ||
| 8722 | #define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U) | ||
| 8723 | /*! LP_OVERLOAD_THRSH - Low Power Overload Threshold | ||
| 8724 | * 0b00..32 | ||
| 8725 | * 0b01..64 | ||
| 8726 | * 0b10..16 | ||
| 8727 | * 0b11..8 | ||
| 8728 | */ | ||
| 8729 | #define DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK) | ||
| 8730 | #define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U) | ||
| 8731 | #define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U) | ||
| 8732 | /*! LP_OVERLOAD_FREQ_SEL - Low Power Overload Frequency Select | ||
| 8733 | * 0b0..eight 32k cycle | ||
| 8734 | * 0b1..sixteen 32k cycle | ||
| 8735 | */ | ||
| 8736 | #define DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK) | ||
| 8737 | #define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U) | ||
| 8738 | #define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U) | ||
| 8739 | /*! LP_HIGH_HYS - Low Power High Hysteric Value | ||
| 8740 | * 0b0..Adjust hysteretic value in low power to 12.5mV | ||
| 8741 | * 0b1..Adjust hysteretic value in low power to 25mV | ||
| 8742 | */ | ||
| 8743 | #define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK) | ||
| 8744 | #define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U) | ||
| 8745 | #define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U) | ||
| 8746 | /*! PWD_CMP_OFFSET - Power down output range comparator | ||
| 8747 | * 0b0..Output range comparator powered up | ||
| 8748 | * 0b1..Output range comparator powered down | ||
| 8749 | */ | ||
| 8750 | #define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK) | ||
| 8751 | #define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U) | ||
| 8752 | #define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U) | ||
| 8753 | /*! XTALOK_DISABLE - Disable xtalok detection circuit | ||
| 8754 | * 0b0..Enable xtalok detection circuit | ||
| 8755 | * 0b1..Disable xtalok detection circuit and always outputs OK signal "1" | ||
| 8756 | */ | ||
| 8757 | #define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK) | ||
| 8758 | #define DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U) | ||
| 8759 | #define DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U) | ||
| 8760 | /*! CURRENT_ALERT_RESET - Reset Current Alert Signal | ||
| 8761 | * 0b0..Current Alert Signal not reset | ||
| 8762 | * 0b1..Current Alert Signal reset | ||
| 8763 | */ | ||
| 8764 | #define DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK) | ||
| 8765 | #define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U) | ||
| 8766 | #define DCDC_REG0_XTAL_24M_OK_SHIFT (29U) | ||
| 8767 | /*! XTAL_24M_OK - 24M XTAL OK | ||
| 8768 | * 0b0..DCDC uses internal ring OSC | ||
| 8769 | * 0b1..DCDC uses xtal 24M | ||
| 8770 | */ | ||
| 8771 | #define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK) | ||
| 8772 | #define DCDC_REG0_STS_DC_OK_MASK (0x80000000U) | ||
| 8773 | #define DCDC_REG0_STS_DC_OK_SHIFT (31U) | ||
| 8774 | /*! STS_DC_OK - DCDC Output OK | ||
| 8775 | * 0b0..DCDC is settling | ||
| 8776 | * 0b1..DCDC already settled | ||
| 8777 | */ | ||
| 8778 | #define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK) | ||
| 8779 | /*! @} */ | ||
| 8780 | |||
| 8781 | /*! @name REG1 - DCDC Register 1 */ | ||
| 8782 | /*! @{ */ | ||
| 8783 | #define DCDC_REG1_REG_FBK_SEL_MASK (0x180U) | ||
| 8784 | #define DCDC_REG1_REG_FBK_SEL_SHIFT (7U) | ||
| 8785 | /*! REG_FBK_SEL | ||
| 8786 | * 0b00..The regulator outputs 1.0V with 1.2V reference voltage | ||
| 8787 | * 0b01..The regulator outputs 1.1V with 1.2V reference voltage | ||
| 8788 | * 0b10..The regulator outputs 1.0V with 1.3V reference voltage | ||
| 8789 | * 0b11..The regulator outputs 1.1V with 1.3V reference voltage | ||
| 8790 | */ | ||
| 8791 | #define DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK) | ||
| 8792 | #define DCDC_REG1_REG_RLOAD_SW_MASK (0x200U) | ||
| 8793 | #define DCDC_REG1_REG_RLOAD_SW_SHIFT (9U) | ||
| 8794 | /*! REG_RLOAD_SW | ||
| 8795 | * 0b0..Load resistor disconnected | ||
| 8796 | * 0b1..Load resistor connected | ||
| 8797 | */ | ||
| 8798 | #define DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK) | ||
| 8799 | #define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U) | ||
| 8800 | #define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U) | ||
| 8801 | /*! LP_CMP_ISRC_SEL - Low Power Comparator Current Bias | ||
| 8802 | * 0b00..50 nA | ||
| 8803 | * 0b01..100 nA | ||
| 8804 | * 0b10..200 nA | ||
| 8805 | * 0b11..400 nA | ||
| 8806 | */ | ||
| 8807 | #define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK) | ||
| 8808 | #define DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U) | ||
| 8809 | #define DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U) | ||
| 8810 | /*! LOOPCTRL_HST_THRESH - Increase Threshold Detection | ||
| 8811 | * 0b0..Lower hysteresis threshold (about 2.5mV in typical, but this value can vary with PVT corners | ||
| 8812 | * 0b1..Higher hysteresis threshold (about 5mV in typical) | ||
| 8813 | */ | ||
| 8814 | #define DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK) | ||
| 8815 | #define DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U) | ||
| 8816 | #define DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U) | ||
| 8817 | /*! LOOPCTRL_EN_HYST - Enable Hysteresis | ||
| 8818 | * 0b0..Disable hysteresis in switching converter common mode analog comparators | ||
| 8819 | * 0b1..Enable hysteresis in switching converter common mode analog comparators | ||
| 8820 | */ | ||
| 8821 | #define DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK) | ||
| 8822 | #define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) | ||
| 8823 | #define DCDC_REG1_VBG_TRIM_SHIFT (24U) | ||
| 8824 | /*! VBG_TRIM - Trim Bandgap Voltage | ||
| 8825 | */ | ||
| 8826 | #define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK) | ||
| 8827 | /*! @} */ | ||
| 8828 | |||
| 8829 | /*! @name REG2 - DCDC Register 2 */ | ||
| 8830 | /*! @{ */ | ||
| 8831 | #define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U) | ||
| 8832 | #define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U) | ||
| 8833 | #define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK) | ||
| 8834 | #define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU) | ||
| 8835 | #define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U) | ||
| 8836 | #define DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK) | ||
| 8837 | #define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U) | ||
| 8838 | #define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U) | ||
| 8839 | #define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK) | ||
| 8840 | #define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U) | ||
| 8841 | #define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U) | ||
| 8842 | /*! LOOPCTRL_EN_RCSCALE - Enable RC Scale | ||
| 8843 | */ | ||
| 8844 | #define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK) | ||
| 8845 | #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U) | ||
| 8846 | #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U) | ||
| 8847 | /*! LOOPCTRL_RCSCALE_THRSH | ||
| 8848 | * 0b0..Do not increase the threshold detection for RC scale circuit. | ||
| 8849 | * 0b1..Increase the threshold detection for RC scale circuit. | ||
| 8850 | */ | ||
| 8851 | #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK) | ||
| 8852 | #define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U) | ||
| 8853 | #define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U) | ||
| 8854 | /*! LOOPCTRL_HYST_SIGN | ||
| 8855 | * 0b0..Do not invert sign of the hysteresis | ||
| 8856 | * 0b1..Invert sign of the hysteresis | ||
| 8857 | */ | ||
| 8858 | #define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK) | ||
| 8859 | #define DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK (0x8000U) | ||
| 8860 | #define DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT (15U) | ||
| 8861 | #define DCDC_REG2_BATTMONITOR_EN_BATADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT)) & DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK) | ||
| 8862 | #define DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U) | ||
| 8863 | #define DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U) | ||
| 8864 | /*! DISABLE_PULSE_SKIP - Disable Pulse Skip | ||
| 8865 | * 0b0..DCDC will be idle to save current dissipation when the duty cycle get to the low limit which is set by NEGLIMIT_IN. | ||
| 8866 | * 0b1..DCDC will keep working with the low limited duty cycle NEGLIMIT_IN. | ||
| 8867 | */ | ||
| 8868 | #define DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK) | ||
| 8869 | #define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U) | ||
| 8870 | #define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U) | ||
| 8871 | /*! DCM_SET_CTRL - DCM Set Control | ||
| 8872 | */ | ||
| 8873 | #define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK) | ||
| 8874 | /*! @} */ | ||
| 8875 | |||
| 8876 | /*! @name REG3 - DCDC Register 3 */ | ||
| 8877 | /*! @{ */ | ||
| 8878 | #define DCDC_REG3_TRG_MASK (0x1FU) | ||
| 8879 | #define DCDC_REG3_TRG_SHIFT (0U) | ||
| 8880 | /*! TRG - Target value of VDD_SOC | ||
| 8881 | */ | ||
| 8882 | #define DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK) | ||
| 8883 | #define DCDC_REG3_TARGET_LP_MASK (0x700U) | ||
| 8884 | #define DCDC_REG3_TARGET_LP_SHIFT (8U) | ||
| 8885 | /*! TARGET_LP - Low Power Target Value | ||
| 8886 | * 0b000..0.9 V | ||
| 8887 | * 0b001..0.925 V | ||
| 8888 | * 0b010..0.95 V | ||
| 8889 | * 0b011..0.975 V | ||
| 8890 | * 0b100..1.0 V | ||
| 8891 | */ | ||
| 8892 | #define DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK) | ||
| 8893 | #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) | ||
| 8894 | #define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U) | ||
| 8895 | /*! MINPWR_DC_HALFCLK | ||
| 8896 | * 0b0..DCDC clock remains at full frequency for continuous mode | ||
| 8897 | * 0b1..DCDC clock set to half frequency for continuous mode | ||
| 8898 | */ | ||
| 8899 | #define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK) | ||
| 8900 | #define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U) | ||
| 8901 | #define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U) | ||
| 8902 | #define DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK) | ||
| 8903 | #define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U) | ||
| 8904 | #define DCDC_REG3_DISABLE_STEP_SHIFT (30U) | ||
| 8905 | /*! DISABLE_STEP - Disable Step | ||
| 8906 | * 0b0..Enable stepping for the output of VDD_SOC of DCDC | ||
| 8907 | * 0b1..Disable stepping for the output of VDD_SOC of DCDC | ||
| 8908 | */ | ||
| 8909 | #define DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK) | ||
| 8910 | /*! @} */ | ||
| 8911 | |||
| 8912 | |||
| 8913 | /*! | ||
| 8914 | * @} | ||
| 8915 | */ /* end of group DCDC_Register_Masks */ | ||
| 8916 | |||
| 8917 | |||
| 8918 | /* DCDC - Peripheral instance base addresses */ | ||
| 8919 | /** Peripheral DCDC base address */ | ||
| 8920 | #define DCDC_BASE (0x40080000u) | ||
| 8921 | /** Peripheral DCDC base pointer */ | ||
| 8922 | #define DCDC ((DCDC_Type *)DCDC_BASE) | ||
| 8923 | /** Array initializer of DCDC peripheral base addresses */ | ||
| 8924 | #define DCDC_BASE_ADDRS { DCDC_BASE } | ||
| 8925 | /** Array initializer of DCDC peripheral base pointers */ | ||
| 8926 | #define DCDC_BASE_PTRS { DCDC } | ||
| 8927 | /** Interrupt vectors for the DCDC peripheral type */ | ||
| 8928 | #define DCDC_IRQS { DCDC_IRQn } | ||
| 8929 | |||
| 8930 | /*! | ||
| 8931 | * @} | ||
| 8932 | */ /* end of group DCDC_Peripheral_Access_Layer */ | ||
| 8933 | |||
| 8934 | |||
| 8935 | /* ---------------------------------------------------------------------------- | ||
| 8936 | -- DCP Peripheral Access Layer | ||
| 8937 | ---------------------------------------------------------------------------- */ | ||
| 8938 | |||
| 8939 | /*! | ||
| 8940 | * @addtogroup DCP_Peripheral_Access_Layer DCP Peripheral Access Layer | ||
| 8941 | * @{ | ||
| 8942 | */ | ||
| 8943 | |||
| 8944 | /** DCP - Register Layout Typedef */ | ||
| 8945 | typedef struct { | ||
| 8946 | __IO uint32_t CTRL; /**< DCP control register 0, offset: 0x0 */ | ||
| 8947 | __IO uint32_t CTRL_SET; /**< DCP control register 0, offset: 0x4 */ | ||
| 8948 | __IO uint32_t CTRL_CLR; /**< DCP control register 0, offset: 0x8 */ | ||
| 8949 | __IO uint32_t CTRL_TOG; /**< DCP control register 0, offset: 0xC */ | ||
| 8950 | __IO uint32_t STAT; /**< DCP status register, offset: 0x10 */ | ||
| 8951 | __IO uint32_t STAT_SET; /**< DCP status register, offset: 0x14 */ | ||
| 8952 | __IO uint32_t STAT_CLR; /**< DCP status register, offset: 0x18 */ | ||
| 8953 | __IO uint32_t STAT_TOG; /**< DCP status register, offset: 0x1C */ | ||
| 8954 | __IO uint32_t CHANNELCTRL; /**< DCP channel control register, offset: 0x20 */ | ||
| 8955 | __IO uint32_t CHANNELCTRL_SET; /**< DCP channel control register, offset: 0x24 */ | ||
| 8956 | __IO uint32_t CHANNELCTRL_CLR; /**< DCP channel control register, offset: 0x28 */ | ||
| 8957 | __IO uint32_t CHANNELCTRL_TOG; /**< DCP channel control register, offset: 0x2C */ | ||
| 8958 | __IO uint32_t CAPABILITY0; /**< DCP capability 0 register, offset: 0x30 */ | ||
| 8959 | uint8_t RESERVED_0[12]; | ||
| 8960 | __I uint32_t CAPABILITY1; /**< DCP capability 1 register, offset: 0x40 */ | ||
| 8961 | uint8_t RESERVED_1[12]; | ||
| 8962 | __IO uint32_t CONTEXT; /**< DCP context buffer pointer, offset: 0x50 */ | ||
| 8963 | uint8_t RESERVED_2[12]; | ||
| 8964 | __IO uint32_t KEY; /**< DCP key index, offset: 0x60 */ | ||
| 8965 | uint8_t RESERVED_3[12]; | ||
| 8966 | __IO uint32_t KEYDATA; /**< DCP key data, offset: 0x70 */ | ||
| 8967 | uint8_t RESERVED_4[12]; | ||
| 8968 | __I uint32_t PACKET0; /**< DCP work packet 0 status register, offset: 0x80 */ | ||
| 8969 | uint8_t RESERVED_5[12]; | ||
| 8970 | __I uint32_t PACKET1; /**< DCP work packet 1 status register, offset: 0x90 */ | ||
| 8971 | uint8_t RESERVED_6[12]; | ||
| 8972 | __I uint32_t PACKET2; /**< DCP work packet 2 status register, offset: 0xA0 */ | ||
| 8973 | uint8_t RESERVED_7[12]; | ||
| 8974 | __I uint32_t PACKET3; /**< DCP work packet 3 status register, offset: 0xB0 */ | ||
| 8975 | uint8_t RESERVED_8[12]; | ||
| 8976 | __I uint32_t PACKET4; /**< DCP work packet 4 status register, offset: 0xC0 */ | ||
| 8977 | uint8_t RESERVED_9[12]; | ||
| 8978 | __I uint32_t PACKET5; /**< DCP work packet 5 status register, offset: 0xD0 */ | ||
| 8979 | uint8_t RESERVED_10[12]; | ||
| 8980 | __I uint32_t PACKET6; /**< DCP work packet 6 status register, offset: 0xE0 */ | ||
| 8981 | uint8_t RESERVED_11[28]; | ||
| 8982 | __IO uint32_t CH0CMDPTR; /**< DCP channel 0 command pointer address register, offset: 0x100 */ | ||
| 8983 | uint8_t RESERVED_12[12]; | ||
| 8984 | __IO uint32_t CH0SEMA; /**< DCP channel 0 semaphore register, offset: 0x110 */ | ||
| 8985 | uint8_t RESERVED_13[12]; | ||
| 8986 | __IO uint32_t CH0STAT; /**< DCP channel 0 status register, offset: 0x120 */ | ||
| 8987 | __IO uint32_t CH0STAT_SET; /**< DCP channel 0 status register, offset: 0x124 */ | ||
| 8988 | __IO uint32_t CH0STAT_CLR; /**< DCP channel 0 status register, offset: 0x128 */ | ||
| 8989 | __IO uint32_t CH0STAT_TOG; /**< DCP channel 0 status register, offset: 0x12C */ | ||
| 8990 | __IO uint32_t CH0OPTS; /**< DCP channel 0 options register, offset: 0x130 */ | ||
| 8991 | __IO uint32_t CH0OPTS_SET; /**< DCP channel 0 options register, offset: 0x134 */ | ||
| 8992 | __IO uint32_t CH0OPTS_CLR; /**< DCP channel 0 options register, offset: 0x138 */ | ||
| 8993 | __IO uint32_t CH0OPTS_TOG; /**< DCP channel 0 options register, offset: 0x13C */ | ||
| 8994 | __IO uint32_t CH1CMDPTR; /**< DCP channel 1 command pointer address register, offset: 0x140 */ | ||
| 8995 | uint8_t RESERVED_14[12]; | ||
| 8996 | __IO uint32_t CH1SEMA; /**< DCP channel 1 semaphore register, offset: 0x150 */ | ||
| 8997 | uint8_t RESERVED_15[12]; | ||
| 8998 | __IO uint32_t CH1STAT; /**< DCP channel 1 status register, offset: 0x160 */ | ||
| 8999 | __IO uint32_t CH1STAT_SET; /**< DCP channel 1 status register, offset: 0x164 */ | ||
| 9000 | __IO uint32_t CH1STAT_CLR; /**< DCP channel 1 status register, offset: 0x168 */ | ||
| 9001 | __IO uint32_t CH1STAT_TOG; /**< DCP channel 1 status register, offset: 0x16C */ | ||
| 9002 | __IO uint32_t CH1OPTS; /**< DCP channel 1 options register, offset: 0x170 */ | ||
| 9003 | __IO uint32_t CH1OPTS_SET; /**< DCP channel 1 options register, offset: 0x174 */ | ||
| 9004 | __IO uint32_t CH1OPTS_CLR; /**< DCP channel 1 options register, offset: 0x178 */ | ||
| 9005 | __IO uint32_t CH1OPTS_TOG; /**< DCP channel 1 options register, offset: 0x17C */ | ||
| 9006 | __IO uint32_t CH2CMDPTR; /**< DCP channel 2 command pointer address register, offset: 0x180 */ | ||
| 9007 | uint8_t RESERVED_16[12]; | ||
| 9008 | __IO uint32_t CH2SEMA; /**< DCP channel 2 semaphore register, offset: 0x190 */ | ||
| 9009 | uint8_t RESERVED_17[12]; | ||
| 9010 | __IO uint32_t CH2STAT; /**< DCP channel 2 status register, offset: 0x1A0 */ | ||
| 9011 | __IO uint32_t CH2STAT_SET; /**< DCP channel 2 status register, offset: 0x1A4 */ | ||
| 9012 | __IO uint32_t CH2STAT_CLR; /**< DCP channel 2 status register, offset: 0x1A8 */ | ||
| 9013 | __IO uint32_t CH2STAT_TOG; /**< DCP channel 2 status register, offset: 0x1AC */ | ||
| 9014 | __IO uint32_t CH2OPTS; /**< DCP channel 2 options register, offset: 0x1B0 */ | ||
| 9015 | __IO uint32_t CH2OPTS_SET; /**< DCP channel 2 options register, offset: 0x1B4 */ | ||
| 9016 | __IO uint32_t CH2OPTS_CLR; /**< DCP channel 2 options register, offset: 0x1B8 */ | ||
| 9017 | __IO uint32_t CH2OPTS_TOG; /**< DCP channel 2 options register, offset: 0x1BC */ | ||
| 9018 | __IO uint32_t CH3CMDPTR; /**< DCP channel 3 command pointer address register, offset: 0x1C0 */ | ||
| 9019 | uint8_t RESERVED_18[12]; | ||
| 9020 | __IO uint32_t CH3SEMA; /**< DCP channel 3 semaphore register, offset: 0x1D0 */ | ||
| 9021 | uint8_t RESERVED_19[12]; | ||
| 9022 | __IO uint32_t CH3STAT; /**< DCP channel 3 status register, offset: 0x1E0 */ | ||
| 9023 | __IO uint32_t CH3STAT_SET; /**< DCP channel 3 status register, offset: 0x1E4 */ | ||
| 9024 | __IO uint32_t CH3STAT_CLR; /**< DCP channel 3 status register, offset: 0x1E8 */ | ||
| 9025 | __IO uint32_t CH3STAT_TOG; /**< DCP channel 3 status register, offset: 0x1EC */ | ||
| 9026 | __IO uint32_t CH3OPTS; /**< DCP channel 3 options register, offset: 0x1F0 */ | ||
| 9027 | __IO uint32_t CH3OPTS_SET; /**< DCP channel 3 options register, offset: 0x1F4 */ | ||
| 9028 | __IO uint32_t CH3OPTS_CLR; /**< DCP channel 3 options register, offset: 0x1F8 */ | ||
| 9029 | __IO uint32_t CH3OPTS_TOG; /**< DCP channel 3 options register, offset: 0x1FC */ | ||
| 9030 | uint8_t RESERVED_20[512]; | ||
| 9031 | __IO uint32_t DBGSELECT; /**< DCP debug select register, offset: 0x400 */ | ||
| 9032 | uint8_t RESERVED_21[12]; | ||
| 9033 | __I uint32_t DBGDATA; /**< DCP debug data register, offset: 0x410 */ | ||
| 9034 | uint8_t RESERVED_22[12]; | ||
| 9035 | __IO uint32_t PAGETABLE; /**< DCP page table register, offset: 0x420 */ | ||
| 9036 | uint8_t RESERVED_23[12]; | ||
| 9037 | __I uint32_t VERSION; /**< DCP version register, offset: 0x430 */ | ||
| 9038 | } DCP_Type; | ||
| 9039 | |||
| 9040 | /* ---------------------------------------------------------------------------- | ||
| 9041 | -- DCP Register Masks | ||
| 9042 | ---------------------------------------------------------------------------- */ | ||
| 9043 | |||
| 9044 | /*! | ||
| 9045 | * @addtogroup DCP_Register_Masks DCP Register Masks | ||
| 9046 | * @{ | ||
| 9047 | */ | ||
| 9048 | |||
| 9049 | /*! @name CTRL - DCP control register 0 */ | ||
| 9050 | /*! @{ */ | ||
| 9051 | #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) | ||
| 9052 | #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) | ||
| 9053 | /*! CHANNEL_INTERRUPT_ENABLE | ||
| 9054 | * 0b00000001..CH0 | ||
| 9055 | * 0b00000010..CH1 | ||
| 9056 | * 0b00000100..CH2 | ||
| 9057 | * 0b00001000..CH3 | ||
| 9058 | */ | ||
| 9059 | #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK) | ||
| 9060 | #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) | ||
| 9061 | #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) | ||
| 9062 | #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK) | ||
| 9063 | #define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) | ||
| 9064 | #define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) | ||
| 9065 | #define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK) | ||
| 9066 | #define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U) | ||
| 9067 | #define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U) | ||
| 9068 | #define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK) | ||
| 9069 | #define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U) | ||
| 9070 | #define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U) | ||
| 9071 | #define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK) | ||
| 9072 | #define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U) | ||
| 9073 | #define DCP_CTRL_PRESENT_SHA_SHIFT (28U) | ||
| 9074 | /*! PRESENT_SHA | ||
| 9075 | * 0b1..Present | ||
| 9076 | * 0b0..Absent | ||
| 9077 | */ | ||
| 9078 | #define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK) | ||
| 9079 | #define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U) | ||
| 9080 | #define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U) | ||
| 9081 | /*! PRESENT_CRYPTO | ||
| 9082 | * 0b1..Present | ||
| 9083 | * 0b0..Absent | ||
| 9084 | */ | ||
| 9085 | #define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK) | ||
| 9086 | #define DCP_CTRL_CLKGATE_MASK (0x40000000U) | ||
| 9087 | #define DCP_CTRL_CLKGATE_SHIFT (30U) | ||
| 9088 | #define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK) | ||
| 9089 | #define DCP_CTRL_SFTRST_MASK (0x80000000U) | ||
| 9090 | #define DCP_CTRL_SFTRST_SHIFT (31U) | ||
| 9091 | #define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK) | ||
| 9092 | /*! @} */ | ||
| 9093 | |||
| 9094 | /*! @name CTRL_SET - DCP control register 0 */ | ||
| 9095 | /*! @{ */ | ||
| 9096 | #define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) | ||
| 9097 | #define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) | ||
| 9098 | /*! CHANNEL_INTERRUPT_ENABLE | ||
| 9099 | * 0b00000001..CH0 | ||
| 9100 | * 0b00000010..CH1 | ||
| 9101 | * 0b00000100..CH2 | ||
| 9102 | * 0b00001000..CH3 | ||
| 9103 | */ | ||
| 9104 | #define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK) | ||
| 9105 | #define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) | ||
| 9106 | #define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) | ||
| 9107 | #define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK) | ||
| 9108 | #define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) | ||
| 9109 | #define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) | ||
| 9110 | #define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK) | ||
| 9111 | #define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK (0x400000U) | ||
| 9112 | #define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT (22U) | ||
| 9113 | #define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK) | ||
| 9114 | #define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK (0x800000U) | ||
| 9115 | #define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT (23U) | ||
| 9116 | #define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK) | ||
| 9117 | #define DCP_CTRL_SET_PRESENT_SHA_MASK (0x10000000U) | ||
| 9118 | #define DCP_CTRL_SET_PRESENT_SHA_SHIFT (28U) | ||
| 9119 | /*! PRESENT_SHA | ||
| 9120 | * 0b1..Present | ||
| 9121 | * 0b0..Absent | ||
| 9122 | */ | ||
| 9123 | #define DCP_CTRL_SET_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_SHA_SHIFT)) & DCP_CTRL_SET_PRESENT_SHA_MASK) | ||
| 9124 | #define DCP_CTRL_SET_PRESENT_CRYPTO_MASK (0x20000000U) | ||
| 9125 | #define DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT (29U) | ||
| 9126 | /*! PRESENT_CRYPTO | ||
| 9127 | * 0b1..Present | ||
| 9128 | * 0b0..Absent | ||
| 9129 | */ | ||
| 9130 | #define DCP_CTRL_SET_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_SET_PRESENT_CRYPTO_MASK) | ||
| 9131 | #define DCP_CTRL_SET_CLKGATE_MASK (0x40000000U) | ||
| 9132 | #define DCP_CTRL_SET_CLKGATE_SHIFT (30U) | ||
| 9133 | #define DCP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CLKGATE_SHIFT)) & DCP_CTRL_SET_CLKGATE_MASK) | ||
| 9134 | #define DCP_CTRL_SET_SFTRST_MASK (0x80000000U) | ||
| 9135 | #define DCP_CTRL_SET_SFTRST_SHIFT (31U) | ||
| 9136 | #define DCP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_SFTRST_SHIFT)) & DCP_CTRL_SET_SFTRST_MASK) | ||
| 9137 | /*! @} */ | ||
| 9138 | |||
| 9139 | /*! @name CTRL_CLR - DCP control register 0 */ | ||
| 9140 | /*! @{ */ | ||
| 9141 | #define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) | ||
| 9142 | #define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) | ||
| 9143 | /*! CHANNEL_INTERRUPT_ENABLE | ||
| 9144 | * 0b00000001..CH0 | ||
| 9145 | * 0b00000010..CH1 | ||
| 9146 | * 0b00000100..CH2 | ||
| 9147 | * 0b00001000..CH3 | ||
| 9148 | */ | ||
| 9149 | #define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK) | ||
| 9150 | #define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) | ||
| 9151 | #define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) | ||
| 9152 | #define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK) | ||
| 9153 | #define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) | ||
| 9154 | #define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) | ||
| 9155 | #define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK) | ||
| 9156 | #define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK (0x400000U) | ||
| 9157 | #define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT (22U) | ||
| 9158 | #define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK) | ||
| 9159 | #define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK (0x800000U) | ||
| 9160 | #define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT (23U) | ||
| 9161 | #define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK) | ||
| 9162 | #define DCP_CTRL_CLR_PRESENT_SHA_MASK (0x10000000U) | ||
| 9163 | #define DCP_CTRL_CLR_PRESENT_SHA_SHIFT (28U) | ||
| 9164 | /*! PRESENT_SHA | ||
| 9165 | * 0b1..Present | ||
| 9166 | * 0b0..Absent | ||
| 9167 | */ | ||
| 9168 | #define DCP_CTRL_CLR_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_SHA_SHIFT)) & DCP_CTRL_CLR_PRESENT_SHA_MASK) | ||
| 9169 | #define DCP_CTRL_CLR_PRESENT_CRYPTO_MASK (0x20000000U) | ||
| 9170 | #define DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT (29U) | ||
| 9171 | /*! PRESENT_CRYPTO | ||
| 9172 | * 0b1..Present | ||
| 9173 | * 0b0..Absent | ||
| 9174 | */ | ||
| 9175 | #define DCP_CTRL_CLR_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_CLR_PRESENT_CRYPTO_MASK) | ||
| 9176 | #define DCP_CTRL_CLR_CLKGATE_MASK (0x40000000U) | ||
| 9177 | #define DCP_CTRL_CLR_CLKGATE_SHIFT (30U) | ||
| 9178 | #define DCP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CLKGATE_SHIFT)) & DCP_CTRL_CLR_CLKGATE_MASK) | ||
| 9179 | #define DCP_CTRL_CLR_SFTRST_MASK (0x80000000U) | ||
| 9180 | #define DCP_CTRL_CLR_SFTRST_SHIFT (31U) | ||
| 9181 | #define DCP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_SFTRST_SHIFT)) & DCP_CTRL_CLR_SFTRST_MASK) | ||
| 9182 | /*! @} */ | ||
| 9183 | |||
| 9184 | /*! @name CTRL_TOG - DCP control register 0 */ | ||
| 9185 | /*! @{ */ | ||
| 9186 | #define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) | ||
| 9187 | #define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) | ||
| 9188 | /*! CHANNEL_INTERRUPT_ENABLE | ||
| 9189 | * 0b00000001..CH0 | ||
| 9190 | * 0b00000010..CH1 | ||
| 9191 | * 0b00000100..CH2 | ||
| 9192 | * 0b00001000..CH3 | ||
| 9193 | */ | ||
| 9194 | #define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK) | ||
| 9195 | #define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) | ||
| 9196 | #define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) | ||
| 9197 | #define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK) | ||
| 9198 | #define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) | ||
| 9199 | #define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) | ||
| 9200 | #define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK) | ||
| 9201 | #define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK (0x400000U) | ||
| 9202 | #define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT (22U) | ||
| 9203 | #define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK) | ||
| 9204 | #define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK (0x800000U) | ||
| 9205 | #define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT (23U) | ||
| 9206 | #define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK) | ||
| 9207 | #define DCP_CTRL_TOG_PRESENT_SHA_MASK (0x10000000U) | ||
| 9208 | #define DCP_CTRL_TOG_PRESENT_SHA_SHIFT (28U) | ||
| 9209 | /*! PRESENT_SHA | ||
| 9210 | * 0b1..Present | ||
| 9211 | * 0b0..Absent | ||
| 9212 | */ | ||
| 9213 | #define DCP_CTRL_TOG_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_SHA_SHIFT)) & DCP_CTRL_TOG_PRESENT_SHA_MASK) | ||
| 9214 | #define DCP_CTRL_TOG_PRESENT_CRYPTO_MASK (0x20000000U) | ||
| 9215 | #define DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT (29U) | ||
| 9216 | /*! PRESENT_CRYPTO | ||
| 9217 | * 0b1..Present | ||
| 9218 | * 0b0..Absent | ||
| 9219 | */ | ||
| 9220 | #define DCP_CTRL_TOG_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_TOG_PRESENT_CRYPTO_MASK) | ||
| 9221 | #define DCP_CTRL_TOG_CLKGATE_MASK (0x40000000U) | ||
| 9222 | #define DCP_CTRL_TOG_CLKGATE_SHIFT (30U) | ||
| 9223 | #define DCP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CLKGATE_SHIFT)) & DCP_CTRL_TOG_CLKGATE_MASK) | ||
| 9224 | #define DCP_CTRL_TOG_SFTRST_MASK (0x80000000U) | ||
| 9225 | #define DCP_CTRL_TOG_SFTRST_SHIFT (31U) | ||
| 9226 | #define DCP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_SFTRST_SHIFT)) & DCP_CTRL_TOG_SFTRST_MASK) | ||
| 9227 | /*! @} */ | ||
| 9228 | |||
| 9229 | /*! @name STAT - DCP status register */ | ||
| 9230 | /*! @{ */ | ||
| 9231 | #define DCP_STAT_IRQ_MASK (0xFU) | ||
| 9232 | #define DCP_STAT_IRQ_SHIFT (0U) | ||
| 9233 | #define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK) | ||
| 9234 | #define DCP_STAT_RSVD_IRQ_MASK (0x100U) | ||
| 9235 | #define DCP_STAT_RSVD_IRQ_SHIFT (8U) | ||
| 9236 | #define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK) | ||
| 9237 | #define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U) | ||
| 9238 | #define DCP_STAT_READY_CHANNELS_SHIFT (16U) | ||
| 9239 | /*! READY_CHANNELS | ||
| 9240 | * 0b00000001..CH0 | ||
| 9241 | * 0b00000010..CH1 | ||
| 9242 | * 0b00000100..CH2 | ||
| 9243 | * 0b00001000..CH3 | ||
| 9244 | */ | ||
| 9245 | #define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK) | ||
| 9246 | #define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U) | ||
| 9247 | #define DCP_STAT_CUR_CHANNEL_SHIFT (24U) | ||
| 9248 | /*! CUR_CHANNEL | ||
| 9249 | * 0b0000..None | ||
| 9250 | * 0b0001..CH0 | ||
| 9251 | * 0b0010..CH1 | ||
| 9252 | * 0b0011..CH2 | ||
| 9253 | * 0b0100..CH3 | ||
| 9254 | */ | ||
| 9255 | #define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK) | ||
| 9256 | #define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U) | ||
| 9257 | #define DCP_STAT_OTP_KEY_READY_SHIFT (28U) | ||
| 9258 | #define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK) | ||
| 9259 | /*! @} */ | ||
| 9260 | |||
| 9261 | /*! @name STAT_SET - DCP status register */ | ||
| 9262 | /*! @{ */ | ||
| 9263 | #define DCP_STAT_SET_IRQ_MASK (0xFU) | ||
| 9264 | #define DCP_STAT_SET_IRQ_SHIFT (0U) | ||
| 9265 | #define DCP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_IRQ_SHIFT)) & DCP_STAT_SET_IRQ_MASK) | ||
| 9266 | #define DCP_STAT_SET_RSVD_IRQ_MASK (0x100U) | ||
| 9267 | #define DCP_STAT_SET_RSVD_IRQ_SHIFT (8U) | ||
| 9268 | #define DCP_STAT_SET_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_RSVD_IRQ_SHIFT)) & DCP_STAT_SET_RSVD_IRQ_MASK) | ||
| 9269 | #define DCP_STAT_SET_READY_CHANNELS_MASK (0xFF0000U) | ||
| 9270 | #define DCP_STAT_SET_READY_CHANNELS_SHIFT (16U) | ||
| 9271 | /*! READY_CHANNELS | ||
| 9272 | * 0b00000001..CH0 | ||
| 9273 | * 0b00000010..CH1 | ||
| 9274 | * 0b00000100..CH2 | ||
| 9275 | * 0b00001000..CH3 | ||
| 9276 | */ | ||
| 9277 | #define DCP_STAT_SET_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_READY_CHANNELS_SHIFT)) & DCP_STAT_SET_READY_CHANNELS_MASK) | ||
| 9278 | #define DCP_STAT_SET_CUR_CHANNEL_MASK (0xF000000U) | ||
| 9279 | #define DCP_STAT_SET_CUR_CHANNEL_SHIFT (24U) | ||
| 9280 | /*! CUR_CHANNEL | ||
| 9281 | * 0b0000..None | ||
| 9282 | * 0b0001..CH0 | ||
| 9283 | * 0b0010..CH1 | ||
| 9284 | * 0b0011..CH2 | ||
| 9285 | * 0b0100..CH3 | ||
| 9286 | */ | ||
| 9287 | #define DCP_STAT_SET_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_CUR_CHANNEL_SHIFT)) & DCP_STAT_SET_CUR_CHANNEL_MASK) | ||
| 9288 | #define DCP_STAT_SET_OTP_KEY_READY_MASK (0x10000000U) | ||
| 9289 | #define DCP_STAT_SET_OTP_KEY_READY_SHIFT (28U) | ||
| 9290 | #define DCP_STAT_SET_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_OTP_KEY_READY_SHIFT)) & DCP_STAT_SET_OTP_KEY_READY_MASK) | ||
| 9291 | /*! @} */ | ||
| 9292 | |||
| 9293 | /*! @name STAT_CLR - DCP status register */ | ||
| 9294 | /*! @{ */ | ||
| 9295 | #define DCP_STAT_CLR_IRQ_MASK (0xFU) | ||
| 9296 | #define DCP_STAT_CLR_IRQ_SHIFT (0U) | ||
| 9297 | #define DCP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_IRQ_SHIFT)) & DCP_STAT_CLR_IRQ_MASK) | ||
| 9298 | #define DCP_STAT_CLR_RSVD_IRQ_MASK (0x100U) | ||
| 9299 | #define DCP_STAT_CLR_RSVD_IRQ_SHIFT (8U) | ||
| 9300 | #define DCP_STAT_CLR_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_RSVD_IRQ_SHIFT)) & DCP_STAT_CLR_RSVD_IRQ_MASK) | ||
| 9301 | #define DCP_STAT_CLR_READY_CHANNELS_MASK (0xFF0000U) | ||
| 9302 | #define DCP_STAT_CLR_READY_CHANNELS_SHIFT (16U) | ||
| 9303 | /*! READY_CHANNELS | ||
| 9304 | * 0b00000001..CH0 | ||
| 9305 | * 0b00000010..CH1 | ||
| 9306 | * 0b00000100..CH2 | ||
| 9307 | * 0b00001000..CH3 | ||
| 9308 | */ | ||
| 9309 | #define DCP_STAT_CLR_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_READY_CHANNELS_SHIFT)) & DCP_STAT_CLR_READY_CHANNELS_MASK) | ||
| 9310 | #define DCP_STAT_CLR_CUR_CHANNEL_MASK (0xF000000U) | ||
| 9311 | #define DCP_STAT_CLR_CUR_CHANNEL_SHIFT (24U) | ||
| 9312 | /*! CUR_CHANNEL | ||
| 9313 | * 0b0000..None | ||
| 9314 | * 0b0001..CH0 | ||
| 9315 | * 0b0010..CH1 | ||
| 9316 | * 0b0011..CH2 | ||
| 9317 | * 0b0100..CH3 | ||
| 9318 | */ | ||
| 9319 | #define DCP_STAT_CLR_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_CUR_CHANNEL_SHIFT)) & DCP_STAT_CLR_CUR_CHANNEL_MASK) | ||
| 9320 | #define DCP_STAT_CLR_OTP_KEY_READY_MASK (0x10000000U) | ||
| 9321 | #define DCP_STAT_CLR_OTP_KEY_READY_SHIFT (28U) | ||
| 9322 | #define DCP_STAT_CLR_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_OTP_KEY_READY_SHIFT)) & DCP_STAT_CLR_OTP_KEY_READY_MASK) | ||
| 9323 | /*! @} */ | ||
| 9324 | |||
| 9325 | /*! @name STAT_TOG - DCP status register */ | ||
| 9326 | /*! @{ */ | ||
| 9327 | #define DCP_STAT_TOG_IRQ_MASK (0xFU) | ||
| 9328 | #define DCP_STAT_TOG_IRQ_SHIFT (0U) | ||
| 9329 | #define DCP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_IRQ_SHIFT)) & DCP_STAT_TOG_IRQ_MASK) | ||
| 9330 | #define DCP_STAT_TOG_RSVD_IRQ_MASK (0x100U) | ||
| 9331 | #define DCP_STAT_TOG_RSVD_IRQ_SHIFT (8U) | ||
| 9332 | #define DCP_STAT_TOG_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_RSVD_IRQ_SHIFT)) & DCP_STAT_TOG_RSVD_IRQ_MASK) | ||
| 9333 | #define DCP_STAT_TOG_READY_CHANNELS_MASK (0xFF0000U) | ||
| 9334 | #define DCP_STAT_TOG_READY_CHANNELS_SHIFT (16U) | ||
| 9335 | /*! READY_CHANNELS | ||
| 9336 | * 0b00000001..CH0 | ||
| 9337 | * 0b00000010..CH1 | ||
| 9338 | * 0b00000100..CH2 | ||
| 9339 | * 0b00001000..CH3 | ||
| 9340 | */ | ||
| 9341 | #define DCP_STAT_TOG_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_READY_CHANNELS_SHIFT)) & DCP_STAT_TOG_READY_CHANNELS_MASK) | ||
| 9342 | #define DCP_STAT_TOG_CUR_CHANNEL_MASK (0xF000000U) | ||
| 9343 | #define DCP_STAT_TOG_CUR_CHANNEL_SHIFT (24U) | ||
| 9344 | /*! CUR_CHANNEL | ||
| 9345 | * 0b0000..None | ||
| 9346 | * 0b0001..CH0 | ||
| 9347 | * 0b0010..CH1 | ||
| 9348 | * 0b0011..CH2 | ||
| 9349 | * 0b0100..CH3 | ||
| 9350 | */ | ||
| 9351 | #define DCP_STAT_TOG_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_CUR_CHANNEL_SHIFT)) & DCP_STAT_TOG_CUR_CHANNEL_MASK) | ||
| 9352 | #define DCP_STAT_TOG_OTP_KEY_READY_MASK (0x10000000U) | ||
| 9353 | #define DCP_STAT_TOG_OTP_KEY_READY_SHIFT (28U) | ||
| 9354 | #define DCP_STAT_TOG_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_OTP_KEY_READY_SHIFT)) & DCP_STAT_TOG_OTP_KEY_READY_MASK) | ||
| 9355 | /*! @} */ | ||
| 9356 | |||
| 9357 | /*! @name CHANNELCTRL - DCP channel control register */ | ||
| 9358 | /*! @{ */ | ||
| 9359 | #define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU) | ||
| 9360 | #define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U) | ||
| 9361 | /*! ENABLE_CHANNEL | ||
| 9362 | * 0b00000001..CH0 | ||
| 9363 | * 0b00000010..CH1 | ||
| 9364 | * 0b00000100..CH2 | ||
| 9365 | * 0b00001000..CH3 | ||
| 9366 | */ | ||
| 9367 | #define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK) | ||
| 9368 | #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) | ||
| 9369 | #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U) | ||
| 9370 | /*! HIGH_PRIORITY_CHANNEL | ||
| 9371 | * 0b00000001..CH0 | ||
| 9372 | * 0b00000010..CH1 | ||
| 9373 | * 0b00000100..CH2 | ||
| 9374 | * 0b00001000..CH3 | ||
| 9375 | */ | ||
| 9376 | #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK) | ||
| 9377 | #define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U) | ||
| 9378 | #define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U) | ||
| 9379 | #define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK) | ||
| 9380 | #define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U) | ||
| 9381 | #define DCP_CHANNELCTRL_RSVD_SHIFT (17U) | ||
| 9382 | #define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK) | ||
| 9383 | /*! @} */ | ||
| 9384 | |||
| 9385 | /*! @name CHANNELCTRL_SET - DCP channel control register */ | ||
| 9386 | /*! @{ */ | ||
| 9387 | #define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK (0xFFU) | ||
| 9388 | #define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT (0U) | ||
| 9389 | /*! ENABLE_CHANNEL | ||
| 9390 | * 0b00000001..CH0 | ||
| 9391 | * 0b00000010..CH1 | ||
| 9392 | * 0b00000100..CH2 | ||
| 9393 | * 0b00001000..CH3 | ||
| 9394 | */ | ||
| 9395 | #define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK) | ||
| 9396 | #define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) | ||
| 9397 | #define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT (8U) | ||
| 9398 | /*! HIGH_PRIORITY_CHANNEL | ||
| 9399 | * 0b00000001..CH0 | ||
| 9400 | * 0b00000010..CH1 | ||
| 9401 | * 0b00000100..CH2 | ||
| 9402 | * 0b00001000..CH3 | ||
| 9403 | */ | ||
| 9404 | #define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK) | ||
| 9405 | #define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK (0x10000U) | ||
| 9406 | #define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT (16U) | ||
| 9407 | #define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK) | ||
| 9408 | #define DCP_CHANNELCTRL_SET_RSVD_MASK (0xFFFE0000U) | ||
| 9409 | #define DCP_CHANNELCTRL_SET_RSVD_SHIFT (17U) | ||
| 9410 | #define DCP_CHANNELCTRL_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_RSVD_SHIFT)) & DCP_CHANNELCTRL_SET_RSVD_MASK) | ||
| 9411 | /*! @} */ | ||
| 9412 | |||
| 9413 | /*! @name CHANNELCTRL_CLR - DCP channel control register */ | ||
| 9414 | /*! @{ */ | ||
| 9415 | #define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK (0xFFU) | ||
| 9416 | #define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT (0U) | ||
| 9417 | /*! ENABLE_CHANNEL | ||
| 9418 | * 0b00000001..CH0 | ||
| 9419 | * 0b00000010..CH1 | ||
| 9420 | * 0b00000100..CH2 | ||
| 9421 | * 0b00001000..CH3 | ||
| 9422 | */ | ||
| 9423 | #define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK) | ||
| 9424 | #define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) | ||
| 9425 | #define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT (8U) | ||
| 9426 | /*! HIGH_PRIORITY_CHANNEL | ||
| 9427 | * 0b00000001..CH0 | ||
| 9428 | * 0b00000010..CH1 | ||
| 9429 | * 0b00000100..CH2 | ||
| 9430 | * 0b00001000..CH3 | ||
| 9431 | */ | ||
| 9432 | #define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK) | ||
| 9433 | #define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK (0x10000U) | ||
| 9434 | #define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT (16U) | ||
| 9435 | #define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK) | ||
| 9436 | #define DCP_CHANNELCTRL_CLR_RSVD_MASK (0xFFFE0000U) | ||
| 9437 | #define DCP_CHANNELCTRL_CLR_RSVD_SHIFT (17U) | ||
| 9438 | #define DCP_CHANNELCTRL_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_RSVD_SHIFT)) & DCP_CHANNELCTRL_CLR_RSVD_MASK) | ||
| 9439 | /*! @} */ | ||
| 9440 | |||
| 9441 | /*! @name CHANNELCTRL_TOG - DCP channel control register */ | ||
| 9442 | /*! @{ */ | ||
| 9443 | #define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK (0xFFU) | ||
| 9444 | #define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT (0U) | ||
| 9445 | /*! ENABLE_CHANNEL | ||
| 9446 | * 0b00000001..CH0 | ||
| 9447 | * 0b00000010..CH1 | ||
| 9448 | * 0b00000100..CH2 | ||
| 9449 | * 0b00001000..CH3 | ||
| 9450 | */ | ||
| 9451 | #define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK) | ||
| 9452 | #define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) | ||
| 9453 | #define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT (8U) | ||
| 9454 | /*! HIGH_PRIORITY_CHANNEL | ||
| 9455 | * 0b00000001..CH0 | ||
| 9456 | * 0b00000010..CH1 | ||
| 9457 | * 0b00000100..CH2 | ||
| 9458 | * 0b00001000..CH3 | ||
| 9459 | */ | ||
| 9460 | #define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK) | ||
| 9461 | #define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK (0x10000U) | ||
| 9462 | #define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT (16U) | ||
| 9463 | #define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK) | ||
| 9464 | #define DCP_CHANNELCTRL_TOG_RSVD_MASK (0xFFFE0000U) | ||
| 9465 | #define DCP_CHANNELCTRL_TOG_RSVD_SHIFT (17U) | ||
| 9466 | #define DCP_CHANNELCTRL_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_RSVD_SHIFT)) & DCP_CHANNELCTRL_TOG_RSVD_MASK) | ||
| 9467 | /*! @} */ | ||
| 9468 | |||
| 9469 | /*! @name CAPABILITY0 - DCP capability 0 register */ | ||
| 9470 | /*! @{ */ | ||
| 9471 | #define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU) | ||
| 9472 | #define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U) | ||
| 9473 | #define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK) | ||
| 9474 | #define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U) | ||
| 9475 | #define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U) | ||
| 9476 | #define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK) | ||
| 9477 | #define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U) | ||
| 9478 | #define DCP_CAPABILITY0_RSVD_SHIFT (12U) | ||
| 9479 | #define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK) | ||
| 9480 | #define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U) | ||
| 9481 | #define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U) | ||
| 9482 | #define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK) | ||
| 9483 | #define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U) | ||
| 9484 | #define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U) | ||
| 9485 | #define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK) | ||
| 9486 | /*! @} */ | ||
| 9487 | |||
| 9488 | /*! @name CAPABILITY1 - DCP capability 1 register */ | ||
| 9489 | /*! @{ */ | ||
| 9490 | #define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU) | ||
| 9491 | #define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U) | ||
| 9492 | /*! CIPHER_ALGORITHMS | ||
| 9493 | * 0b0000000000000001..AES128 | ||
| 9494 | */ | ||
| 9495 | #define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK) | ||
| 9496 | #define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U) | ||
| 9497 | #define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U) | ||
| 9498 | /*! HASH_ALGORITHMS | ||
| 9499 | * 0b0000000000000001..SHA1 | ||
| 9500 | * 0b0000000000000010..CRC32 | ||
| 9501 | * 0b0000000000000100..SHA256 | ||
| 9502 | */ | ||
| 9503 | #define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK) | ||
| 9504 | /*! @} */ | ||
| 9505 | |||
| 9506 | /*! @name CONTEXT - DCP context buffer pointer */ | ||
| 9507 | /*! @{ */ | ||
| 9508 | #define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU) | ||
| 9509 | #define DCP_CONTEXT_ADDR_SHIFT (0U) | ||
| 9510 | #define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK) | ||
| 9511 | /*! @} */ | ||
| 9512 | |||
| 9513 | /*! @name | ||