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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1051/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1051/project_template/board.c
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1/*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "fsl_debug_console.h"
10#include "board.h"
11#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12#include "fsl_lpi2c.h"
13#endif /* SDK_I2C_BASED_COMPONENT_USED */
14#if defined BOARD_USE_CODEC
15#include "fsl_wm8960.h"
16#endif
17#include "fsl_iomuxc.h"
18/*******************************************************************************
19 * Variables
20 ******************************************************************************/
21#if defined BOARD_USE_CODEC
22codec_config_t boardCodecConfig = {.I2C_SendFunc = BOARD_Codec_I2C_Send,
23 .I2C_ReceiveFunc = BOARD_Codec_I2C_Receive,
24 .op.Init = WM8960_Init,
25 .op.Deinit = WM8960_Deinit,
26 .op.SetFormat = WM8960_ConfigDataFormat};
27#endif
28/*******************************************************************************
29 * Code
30 ******************************************************************************/
31
32/* Get debug console frequency. */
33uint32_t BOARD_DebugConsoleSrcFreq(void)
34{
35 uint32_t freq;
36
37 /* To make it simple, we assume default PLL and divider settings, and the only variable
38 from application is use PLL3 source or OSC source */
39 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
40 {
41 freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
42 }
43 else
44 {
45 freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
46 }
47
48 return freq;
49}
50
51/* Initialize debug console. */
52void BOARD_InitDebugConsole(void)
53{
54 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
55
56 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
57}
58
59#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
60void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
61{
62 lpi2c_master_config_t lpi2cConfig = {0};
63
64 /*
65 * lpi2cConfig.debugEnable = false;
66 * lpi2cConfig.ignoreAck = false;
67 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
68 * lpi2cConfig.baudRate_Hz = 100000U;
69 * lpi2cConfig.busIdleTimeout_ns = 0;
70 * lpi2cConfig.pinLowTimeout_ns = 0;
71 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
72 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
73 */
74 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
75 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
76}
77
78status_t BOARD_LPI2C_Send(LPI2C_Type *base,
79 uint8_t deviceAddress,
80 uint32_t subAddress,
81 uint8_t subAddressSize,
82 uint8_t *txBuff,
83 uint8_t txBuffSize)
84{
85 status_t reVal;
86
87 /* Send master blocking data to slave */
88 reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
89 if (kStatus_Success == reVal)
90 {
91 while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
92 {
93 }
94
95 reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
96 if (reVal != kStatus_Success)
97 {
98 return reVal;
99 }
100
101 reVal = LPI2C_MasterSend(base, txBuff, txBuffSize);
102 if (reVal != kStatus_Success)
103 {
104 return reVal;
105 }
106
107 reVal = LPI2C_MasterStop(base);
108 if (reVal != kStatus_Success)
109 {
110 return reVal;
111 }
112 }
113
114 return reVal;
115}
116
117status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
118 uint8_t deviceAddress,
119 uint32_t subAddress,
120 uint8_t subAddressSize,
121 uint8_t *rxBuff,
122 uint8_t rxBuffSize)
123{
124 status_t reVal;
125
126 reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
127 if (kStatus_Success == reVal)
128 {
129 while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
130 {
131 }
132
133 reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
134 if (reVal != kStatus_Success)
135 {
136 return reVal;
137 }
138
139 reVal = LPI2C_MasterRepeatedStart(base, deviceAddress, kLPI2C_Read);
140
141 if (reVal != kStatus_Success)
142 {
143 return reVal;
144 }
145
146 reVal = LPI2C_MasterReceive(base, rxBuff, rxBuffSize);
147 if (reVal != kStatus_Success)
148 {
149 return reVal;
150 }
151
152 reVal = LPI2C_MasterStop(base);
153 if (reVal != kStatus_Success)
154 {
155 return reVal;
156 }
157 }
158 return reVal;
159}
160
161status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
162 uint8_t deviceAddress,
163 uint32_t subAddress,
164 uint8_t subAddressSize,
165 uint8_t *txBuff,
166 uint8_t txBuffSize)
167{
168 return BOARD_LPI2C_Send(base, deviceAddress, subAddress, subAddressSize, txBuff, txBuffSize);
169}
170
171status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
172 uint8_t deviceAddress,
173 uint32_t subAddress,
174 uint8_t subAddressSize,
175 uint8_t *rxBuff,
176 uint8_t rxBuffSize)
177{
178 status_t reVal;
179
180 reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
181 if (kStatus_Success == reVal)
182 {
183 while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
184 {
185 }
186
187 reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
188 if (reVal != kStatus_Success)
189 {
190 return reVal;
191 }
192
193 /* SCCB does not support LPI2C repeat start, must stop then start. */
194 reVal = LPI2C_MasterStop(base);
195
196 if (reVal != kStatus_Success)
197 {
198 return reVal;
199 }
200
201 reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Read);
202
203 if (reVal != kStatus_Success)
204 {
205 return reVal;
206 }
207
208 reVal = LPI2C_MasterReceive(base, rxBuff, rxBuffSize);
209 if (reVal != kStatus_Success)
210 {
211 return reVal;
212 }
213
214 reVal = LPI2C_MasterStop(base);
215 if (reVal != kStatus_Success)
216 {
217 return reVal;
218 }
219 }
220 return reVal;
221}
222
223void BOARD_Accel_I2C_Init(void)
224{
225 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
226}
227
228status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
229{
230 uint8_t data = (uint8_t)txBuff;
231
232 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
233}
234
235status_t BOARD_Accel_I2C_Receive(
236 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
237{
238 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
239}
240
241void BOARD_Codec_I2C_Init(void)
242{
243 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
244}
245
246status_t BOARD_Codec_I2C_Send(
247 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
248{
249 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
250 txBuffSize);
251}
252
253status_t BOARD_Codec_I2C_Receive(
254 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
255{
256 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
257}
258
259void BOARD_Camera_I2C_Init(void)
260{
261 CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
262 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
263 BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
264}
265
266status_t BOARD_Camera_I2C_Send(
267 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
268{
269 return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
270 txBuffSize);
271}
272
273status_t BOARD_Camera_I2C_Receive(
274 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
275{
276 return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
277 rxBuffSize);
278}
279
280status_t BOARD_Camera_I2C_SendSCCB(
281 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
282{
283 return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
284 txBuffSize);
285}
286
287status_t BOARD_Camera_I2C_ReceiveSCCB(
288 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
289{
290 return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
291 rxBuffSize);
292}
293#endif /* SDK_I2C_BASED_COMPONENT_USED */
294
295void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength)
296{
297 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
298 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
299 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
300 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
301 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
302 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
303 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
304 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
305 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
306 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
307 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
308 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
309 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
310 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
311 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
312 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
313 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
314 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
315 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
316 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
317 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
318 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
319 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
320 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
321 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
322 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
323 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
324 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
325 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
326\
327}
328
329void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength)
330{
331 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_USDHC2_CMD,
332 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
333 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
334 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
335 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
336 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_USDHC2_CLK,
337 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
338 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
339 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
340 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0,
341 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
342 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
343 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
344 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
345 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1,
346 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
347 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
348 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
349 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
350 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2,
351 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
352 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
353 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
354 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
355 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3,
356 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
357 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
358 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
359 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
360 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4,
361 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
362 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
363 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
364 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
365 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5,
366 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
367 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
368 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
369 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
370 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6,
371 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
372 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
373 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
374 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
375 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7,
376 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
377 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
378 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
379 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
380\
381}
382
383/* MPU configuration. */
384void BOARD_ConfigMPU(void)
385{
386 /* Disable I cache and D cache */
387 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
388 {
389 SCB_DisableICache();
390 }
391 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
392 {
393 SCB_DisableDCache();
394 }
395
396 /* Disable MPU */
397 ARM_MPU_Disable();
398
399 /* MPU configure:
400 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
401 * SubRegionDisable, Size)
402 * API in core_cm7.h.
403 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
404 * disabled.
405 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
406 * Privileged mode.
407 * Use MACROS defined in core_cm7.h:
408 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
409 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
410 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
411 * 0 x 0 0 Strongly Ordered shareable
412 * 0 x 0 1 Device shareable
413 * 0 0 1 0 Normal not shareable Outer and inner write
414 * through no write allocate
415 * 0 0 1 1 Normal not shareable Outer and inner write
416 * back no write allocate
417 * 0 1 1 0 Normal shareable Outer and inner write
418 * through no write allocate
419 * 0 1 1 1 Normal shareable Outer and inner write
420 * back no write allocate
421 * 1 0 0 0 Normal not shareable outer and inner
422 * noncache
423 * 1 1 0 0 Normal shareable outer and inner
424 * noncache
425 * 1 0 1 1 Normal not shareable outer and inner write
426 * back write/read acllocate
427 * 1 1 1 1 Normal shareable outer and inner write
428 * back write/read acllocate
429 * 2 x 0 0 Device not shareable
430 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
431 * policy.
432 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
433 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
434 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
435 * core_cm7.h.
436 */
437
438 /* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
439 MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
440 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
441
442 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
443 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
444 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
445
446/* Region 2 setting */
447#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
448 /* Setting Memory with Normal type, not shareable, outer/inner write back. */
449 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
450 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
451#else
452 /* Setting Memory with Device type, not shareable, non-cacheable. */
453 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
454 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_64MB);
455#endif
456
457 /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
458 MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
459 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
460
461 /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
462 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
463 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
464
465 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
466 MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
467 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
468
469 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
470 MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
471 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
472
473/* The define sets the cacheable memory to shareable,
474 * this suggestion is referred from chapter 2.2.1 Memory regions,
475 * types and attributes in Cortex-M7 Devices, Generic User Guide */
476#if defined(SDRAM_IS_SHAREABLE)
477 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
478 MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
479 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
480#else
481 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
482 MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
483 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
484#endif
485
486 /* Region 8 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be
487 * accessed by cache can be put here */
488 /* Memory with Normal type, not shareable, non-cacheable */
489 MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
490 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
491
492 /* Enable MPU */
493 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
494
495 /* Enable I cache and D cache */
496 SCB_EnableDCache();
497 SCB_EnableICache();
498}
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 20:19:34 +0100