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Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1051')
35 files changed, 57800 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1051/MIMXRT1051.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1051/MIMXRT1051.h new file mode 100644 index 000000000..9abd97f94 --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1051/MIMXRT1051.h | |||
| @@ -0,0 +1,42788 @@ | |||
| 1 | /* | ||
| 2 | ** ################################################################### | ||
| 3 | ** Processors: MIMXRT1051CVJ5B | ||
| 4 | ** MIMXRT1051CVL5B | ||
| 5 | ** MIMXRT1051DVJ6B | ||
| 6 | ** MIMXRT1051DVL6B | ||
| 7 | ** | ||
| 8 | ** Compilers: Freescale C/C++ for Embedded ARM | ||
| 9 | ** GNU C Compiler | ||
| 10 | ** IAR ANSI C/C++ Compiler for ARM | ||
| 11 | ** Keil ARM C/C++ Compiler | ||
| 12 | ** MCUXpresso Compiler | ||
| 13 | ** | ||
| 14 | ** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2 | ||
| 15 | ** Version: rev. 1.3, 2019-04-29 | ||
| 16 | ** Build: b201019 | ||
| 17 | ** | ||
| 18 | ** Abstract: | ||
| 19 | ** CMSIS Peripheral Access Layer for MIMXRT1051 | ||
| 20 | ** | ||
| 21 | ** Copyright 1997-2016 Freescale Semiconductor, Inc. | ||
| 22 | ** Copyright 2016-2020 NXP | ||
| 23 | ** All rights reserved. | ||
| 24 | ** | ||
| 25 | ** SPDX-License-Identifier: BSD-3-Clause | ||
| 26 | ** | ||
| 27 | ** http: www.nxp.com | ||
| 28 | ** mail: [email protected] | ||
| 29 | ** | ||
| 30 | ** Revisions: | ||
| 31 | ** - rev. 0.1 (2017-01-10) | ||
| 32 | ** Initial version. | ||
| 33 | ** - rev. 1.0 (2018-09-21) | ||
| 34 | ** Update interrupt vector table and dma request source. | ||
| 35 | ** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1. | ||
| 36 | ** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS. | ||
| 37 | ** - rev. 1.1 (2018-11-16) | ||
| 38 | ** Update header files to align with IMXRT1050RM Rev.1. | ||
| 39 | ** - rev. 1.2 (2018-11-27) | ||
| 40 | ** Update header files to align with IMXRT1050RM Rev.2.1. | ||
| 41 | ** - rev. 1.3 (2019-04-29) | ||
| 42 | ** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module. | ||
| 43 | ** | ||
| 44 | ** ################################################################### | ||
| 45 | */ | ||
| 46 | |||
| 47 | /*! | ||
| 48 | * @file MIMXRT1051.h | ||
| 49 | * @version 1.3 | ||
| 50 | * @date 2019-04-29 | ||
| 51 | * @brief CMSIS Peripheral Access Layer for MIMXRT1051 | ||
| 52 | * | ||
| 53 | * CMSIS Peripheral Access Layer for MIMXRT1051 | ||
| 54 | */ | ||
| 55 | |||
| 56 | #ifndef _MIMXRT1051_H_ | ||
| 57 | #define _MIMXRT1051_H_ /**< Symbol preventing repeated inclusion */ | ||
| 58 | |||
| 59 | /** Memory map major version (memory maps with equal major version number are | ||
| 60 | * compatible) */ | ||
| 61 | #define MCU_MEM_MAP_VERSION 0x0100U | ||
| 62 | /** Memory map minor version */ | ||
| 63 | #define MCU_MEM_MAP_VERSION_MINOR 0x0003U | ||
| 64 | |||
| 65 | |||
| 66 | /* ---------------------------------------------------------------------------- | ||
| 67 | -- Interrupt vector numbers | ||
| 68 | ---------------------------------------------------------------------------- */ | ||
| 69 | |||
| 70 | /*! | ||
| 71 | * @addtogroup Interrupt_vector_numbers Interrupt vector numbers | ||
| 72 | * @{ | ||
| 73 | */ | ||
| 74 | |||
| 75 | /** Interrupt Number Definitions */ | ||
| 76 | #define NUMBER_OF_INT_VECTORS 168 /**< Number of interrupts in the Vector table */ | ||
| 77 | |||
| 78 | typedef enum IRQn { | ||
| 79 | /* Auxiliary constants */ | ||
| 80 | NotAvail_IRQn = -128, /**< Not available device specific interrupt */ | ||
| 81 | |||
| 82 | /* Core interrupts */ | ||
| 83 | NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ | ||
| 84 | HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */ | ||
| 85 | MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */ | ||
| 86 | BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */ | ||
| 87 | UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */ | ||
| 88 | SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */ | ||
| 89 | DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */ | ||
| 90 | PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */ | ||
| 91 | SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */ | ||
| 92 | |||
| 93 | /* Device specific interrupts */ | ||
| 94 | DMA0_DMA16_IRQn = 0, /**< DMA channel 0/16 transfer complete */ | ||
| 95 | DMA1_DMA17_IRQn = 1, /**< DMA channel 1/17 transfer complete */ | ||
| 96 | DMA2_DMA18_IRQn = 2, /**< DMA channel 2/18 transfer complete */ | ||
| 97 | DMA3_DMA19_IRQn = 3, /**< DMA channel 3/19 transfer complete */ | ||
| 98 | DMA4_DMA20_IRQn = 4, /**< DMA channel 4/20 transfer complete */ | ||
| 99 | DMA5_DMA21_IRQn = 5, /**< DMA channel 5/21 transfer complete */ | ||
| 100 | DMA6_DMA22_IRQn = 6, /**< DMA channel 6/22 transfer complete */ | ||
| 101 | DMA7_DMA23_IRQn = 7, /**< DMA channel 7/23 transfer complete */ | ||
| 102 | DMA8_DMA24_IRQn = 8, /**< DMA channel 8/24 transfer complete */ | ||
| 103 | DMA9_DMA25_IRQn = 9, /**< DMA channel 9/25 transfer complete */ | ||
| 104 | DMA10_DMA26_IRQn = 10, /**< DMA channel 10/26 transfer complete */ | ||
| 105 | DMA11_DMA27_IRQn = 11, /**< DMA channel 11/27 transfer complete */ | ||
| 106 | DMA12_DMA28_IRQn = 12, /**< DMA channel 12/28 transfer complete */ | ||
| 107 | DMA13_DMA29_IRQn = 13, /**< DMA channel 13/29 transfer complete */ | ||
| 108 | DMA14_DMA30_IRQn = 14, /**< DMA channel 14/30 transfer complete */ | ||
| 109 | DMA15_DMA31_IRQn = 15, /**< DMA channel 15/31 transfer complete */ | ||
| 110 | DMA_ERROR_IRQn = 16, /**< DMA error interrupt channels 0-15 / 16-31 */ | ||
| 111 | CTI0_ERROR_IRQn = 17, /**< CTI0_Error */ | ||
| 112 | CTI1_ERROR_IRQn = 18, /**< CTI1_Error */ | ||
| 113 | CORE_IRQn = 19, /**< CorePlatform exception IRQ */ | ||
| 114 | LPUART1_IRQn = 20, /**< LPUART1 TX interrupt and RX interrupt */ | ||
| 115 | LPUART2_IRQn = 21, /**< LPUART2 TX interrupt and RX interrupt */ | ||
| 116 | LPUART3_IRQn = 22, /**< LPUART3 TX interrupt and RX interrupt */ | ||
| 117 | LPUART4_IRQn = 23, /**< LPUART4 TX interrupt and RX interrupt */ | ||
| 118 | LPUART5_IRQn = 24, /**< LPUART5 TX interrupt and RX interrupt */ | ||
| 119 | LPUART6_IRQn = 25, /**< LPUART6 TX interrupt and RX interrupt */ | ||
| 120 | LPUART7_IRQn = 26, /**< LPUART7 TX interrupt and RX interrupt */ | ||
| 121 | LPUART8_IRQn = 27, /**< LPUART8 TX interrupt and RX interrupt */ | ||
| 122 | LPI2C1_IRQn = 28, /**< LPI2C1 interrupt */ | ||
| 123 | LPI2C2_IRQn = 29, /**< LPI2C2 interrupt */ | ||
| 124 | LPI2C3_IRQn = 30, /**< LPI2C3 interrupt */ | ||
| 125 | LPI2C4_IRQn = 31, /**< LPI2C4 interrupt */ | ||
| 126 | LPSPI1_IRQn = 32, /**< LPSPI1 single interrupt vector for all sources */ | ||
| 127 | LPSPI2_IRQn = 33, /**< LPSPI2 single interrupt vector for all sources */ | ||
| 128 | LPSPI3_IRQn = 34, /**< LPSPI3 single interrupt vector for all sources */ | ||
| 129 | LPSPI4_IRQn = 35, /**< LPSPI4 single interrupt vector for all sources */ | ||
| 130 | CAN1_IRQn = 36, /**< CAN1 interrupt */ | ||
| 131 | CAN2_IRQn = 37, /**< CAN2 interrupt */ | ||
| 132 | FLEXRAM_IRQn = 38, /**< FlexRAM address out of range Or access hit IRQ */ | ||
| 133 | KPP_IRQn = 39, /**< Keypad nterrupt */ | ||
| 134 | TSC_DIG_IRQn = 40, /**< TSC interrupt */ | ||
| 135 | GPR_IRQ_IRQn = 41, /**< GPR interrupt */ | ||
| 136 | Reserved58_IRQn = 42, /**< Reserved interrupt */ | ||
| 137 | Reserved59_IRQn = 43, /**< Reserved interrupt */ | ||
| 138 | Reserved60_IRQn = 44, /**< Reserved interrupt */ | ||
| 139 | WDOG2_IRQn = 45, /**< WDOG2 interrupt */ | ||
| 140 | SNVS_HP_WRAPPER_IRQn = 46, /**< SRTC Consolidated Interrupt. Non TZ */ | ||
| 141 | SNVS_HP_WRAPPER_TZ_IRQn = 47, /**< SRTC Security Interrupt. TZ */ | ||
| 142 | SNVS_LP_WRAPPER_IRQn = 48, /**< ON-OFF button press shorter than 5 secs (pulse event) */ | ||
| 143 | CSU_IRQn = 49, /**< CSU interrupt */ | ||
| 144 | DCP_IRQn = 50, /**< DCP_IRQ interrupt */ | ||
| 145 | DCP_VMI_IRQn = 51, /**< DCP_VMI_IRQ interrupt */ | ||
| 146 | Reserved68_IRQn = 52, /**< Reserved interrupt */ | ||
| 147 | TRNG_IRQn = 53, /**< TRNG interrupt */ | ||
| 148 | SJC_IRQn = 54, /**< SJC interrupt */ | ||
| 149 | BEE_IRQn = 55, /**< BEE interrupt */ | ||
| 150 | SAI1_IRQn = 56, /**< SAI1 interrupt */ | ||
| 151 | SAI2_IRQn = 57, /**< SAI1 interrupt */ | ||
| 152 | SAI3_RX_IRQn = 58, /**< SAI3 interrupt */ | ||
| 153 | SAI3_TX_IRQn = 59, /**< SAI3 interrupt */ | ||
| 154 | SPDIF_IRQn = 60, /**< SPDIF interrupt */ | ||
| 155 | PMU_EVENT_IRQn = 61, /**< Brown-out event interrupt */ | ||
| 156 | Reserved78_IRQn = 62, /**< Reserved interrupt */ | ||
| 157 | TEMP_LOW_HIGH_IRQn = 63, /**< TempSensor low/high interrupt */ | ||
| 158 | TEMP_PANIC_IRQn = 64, /**< TempSensor panic interrupt */ | ||
| 159 | USB_PHY1_IRQn = 65, /**< USBPHY (UTMI0), Interrupt */ | ||
| 160 | USB_PHY2_IRQn = 66, /**< USBPHY (UTMI0), Interrupt */ | ||
| 161 | ADC1_IRQn = 67, /**< ADC1 interrupt */ | ||
| 162 | ADC2_IRQn = 68, /**< ADC2 interrupt */ | ||
| 163 | DCDC_IRQn = 69, /**< DCDC interrupt */ | ||
| 164 | Reserved86_IRQn = 70, /**< Reserved interrupt */ | ||
| 165 | Reserved87_IRQn = 71, /**< Reserved interrupt */ | ||
| 166 | GPIO1_INT0_IRQn = 72, /**< Active HIGH Interrupt from INT0 from GPIO */ | ||
| 167 | GPIO1_INT1_IRQn = 73, /**< Active HIGH Interrupt from INT1 from GPIO */ | ||
| 168 | GPIO1_INT2_IRQn = 74, /**< Active HIGH Interrupt from INT2 from GPIO */ | ||
| 169 | GPIO1_INT3_IRQn = 75, /**< Active HIGH Interrupt from INT3 from GPIO */ | ||
| 170 | GPIO1_INT4_IRQn = 76, /**< Active HIGH Interrupt from INT4 from GPIO */ | ||
| 171 | GPIO1_INT5_IRQn = 77, /**< Active HIGH Interrupt from INT5 from GPIO */ | ||
| 172 | GPIO1_INT6_IRQn = 78, /**< Active HIGH Interrupt from INT6 from GPIO */ | ||
| 173 | GPIO1_INT7_IRQn = 79, /**< Active HIGH Interrupt from INT7 from GPIO */ | ||
| 174 | GPIO1_Combined_0_15_IRQn = 80, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */ | ||
| 175 | GPIO1_Combined_16_31_IRQn = 81, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */ | ||
| 176 | GPIO2_Combined_0_15_IRQn = 82, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */ | ||
| 177 | GPIO2_Combined_16_31_IRQn = 83, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */ | ||
| 178 | GPIO3_Combined_0_15_IRQn = 84, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */ | ||
| 179 | GPIO3_Combined_16_31_IRQn = 85, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */ | ||
| 180 | GPIO4_Combined_0_15_IRQn = 86, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */ | ||
| 181 | GPIO4_Combined_16_31_IRQn = 87, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */ | ||
| 182 | GPIO5_Combined_0_15_IRQn = 88, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */ | ||
| 183 | GPIO5_Combined_16_31_IRQn = 89, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */ | ||
| 184 | FLEXIO1_IRQn = 90, /**< FLEXIO1 interrupt */ | ||
| 185 | FLEXIO2_IRQn = 91, /**< FLEXIO2 interrupt */ | ||
| 186 | WDOG1_IRQn = 92, /**< WDOG1 interrupt */ | ||
| 187 | RTWDOG_IRQn = 93, /**< RTWDOG interrupt */ | ||
| 188 | EWM_IRQn = 94, /**< EWM interrupt */ | ||
| 189 | CCM_1_IRQn = 95, /**< CCM IRQ1 interrupt */ | ||
| 190 | CCM_2_IRQn = 96, /**< CCM IRQ2 interrupt */ | ||
| 191 | GPC_IRQn = 97, /**< GPC interrupt */ | ||
| 192 | SRC_IRQn = 98, /**< SRC interrupt */ | ||
| 193 | Reserved115_IRQn = 99, /**< Reserved interrupt */ | ||
| 194 | GPT1_IRQn = 100, /**< GPT1 interrupt */ | ||
| 195 | GPT2_IRQn = 101, /**< GPT2 interrupt */ | ||
| 196 | PWM1_0_IRQn = 102, /**< PWM1 capture 0, compare 0, or reload 0 interrupt */ | ||
| 197 | PWM1_1_IRQn = 103, /**< PWM1 capture 1, compare 1, or reload 0 interrupt */ | ||
| 198 | PWM1_2_IRQn = 104, /**< PWM1 capture 2, compare 2, or reload 0 interrupt */ | ||
| 199 | PWM1_3_IRQn = 105, /**< PWM1 capture 3, compare 3, or reload 0 interrupt */ | ||
| 200 | PWM1_FAULT_IRQn = 106, /**< PWM1 fault or reload error interrupt */ | ||
| 201 | Reserved123_IRQn = 107, /**< Reserved interrupt */ | ||
| 202 | FLEXSPI_IRQn = 108, /**< FlexSPI0 interrupt */ | ||
| 203 | SEMC_IRQn = 109, /**< Reserved interrupt */ | ||
| 204 | USDHC1_IRQn = 110, /**< USDHC1 interrupt */ | ||
| 205 | USDHC2_IRQn = 111, /**< USDHC2 interrupt */ | ||
| 206 | USB_OTG2_IRQn = 112, /**< USBO2 USB OTG2 */ | ||
| 207 | USB_OTG1_IRQn = 113, /**< USBO2 USB OTG1 */ | ||
| 208 | ENET_IRQn = 114, /**< ENET interrupt */ | ||
| 209 | ENET_1588_Timer_IRQn = 115, /**< ENET_1588_Timer interrupt */ | ||
| 210 | XBAR1_IRQ_0_1_IRQn = 116, /**< XBAR1 interrupt */ | ||
| 211 | XBAR1_IRQ_2_3_IRQn = 117, /**< XBAR1 interrupt */ | ||
| 212 | ADC_ETC_IRQ0_IRQn = 118, /**< ADCETC IRQ0 interrupt */ | ||
| 213 | ADC_ETC_IRQ1_IRQn = 119, /**< ADCETC IRQ1 interrupt */ | ||
| 214 | ADC_ETC_IRQ2_IRQn = 120, /**< ADCETC IRQ2 interrupt */ | ||
| 215 | ADC_ETC_ERROR_IRQ_IRQn = 121, /**< ADCETC Error IRQ interrupt */ | ||
| 216 | PIT_IRQn = 122, /**< PIT interrupt */ | ||
| 217 | ACMP1_IRQn = 123, /**< ACMP interrupt */ | ||
| 218 | ACMP2_IRQn = 124, /**< ACMP interrupt */ | ||
| 219 | ACMP3_IRQn = 125, /**< ACMP interrupt */ | ||
| 220 | ACMP4_IRQn = 126, /**< ACMP interrupt */ | ||
| 221 | Reserved143_IRQn = 127, /**< Reserved interrupt */ | ||
| 222 | Reserved144_IRQn = 128, /**< Reserved interrupt */ | ||
| 223 | ENC1_IRQn = 129, /**< ENC1 interrupt */ | ||
| 224 | ENC2_IRQn = 130, /**< ENC2 interrupt */ | ||
| 225 | ENC3_IRQn = 131, /**< ENC3 interrupt */ | ||
| 226 | ENC4_IRQn = 132, /**< ENC4 interrupt */ | ||
| 227 | TMR1_IRQn = 133, /**< TMR1 interrupt */ | ||
| 228 | TMR2_IRQn = 134, /**< TMR2 interrupt */ | ||
| 229 | TMR3_IRQn = 135, /**< TMR3 interrupt */ | ||
| 230 | TMR4_IRQn = 136, /**< TMR4 interrupt */ | ||
| 231 | PWM2_0_IRQn = 137, /**< PWM2 capture 0, compare 0, or reload 0 interrupt */ | ||
| 232 | PWM2_1_IRQn = 138, /**< PWM2 capture 1, compare 1, or reload 0 interrupt */ | ||
| 233 | PWM2_2_IRQn = 139, /**< PWM2 capture 2, compare 2, or reload 0 interrupt */ | ||
| 234 | PWM2_3_IRQn = 140, /**< PWM2 capture 3, compare 3, or reload 0 interrupt */ | ||
| 235 | PWM2_FAULT_IRQn = 141, /**< PWM2 fault or reload error interrupt */ | ||
| 236 | PWM3_0_IRQn = 142, /**< PWM3 capture 0, compare 0, or reload 0 interrupt */ | ||
| 237 | PWM3_1_IRQn = 143, /**< PWM3 capture 1, compare 1, or reload 0 interrupt */ | ||
| 238 | PWM3_2_IRQn = 144, /**< PWM3 capture 2, compare 2, or reload 0 interrupt */ | ||
| 239 | PWM3_3_IRQn = 145, /**< PWM3 capture 3, compare 3, or reload 0 interrupt */ | ||
| 240 | PWM3_FAULT_IRQn = 146, /**< PWM3 fault or reload error interrupt */ | ||
| 241 | PWM4_0_IRQn = 147, /**< PWM4 capture 0, compare 0, or reload 0 interrupt */ | ||
| 242 | PWM4_1_IRQn = 148, /**< PWM4 capture 1, compare 1, or reload 0 interrupt */ | ||
| 243 | PWM4_2_IRQn = 149, /**< PWM4 capture 2, compare 2, or reload 0 interrupt */ | ||
| 244 | PWM4_3_IRQn = 150, /**< PWM4 capture 3, compare 3, or reload 0 interrupt */ | ||
| 245 | PWM4_FAULT_IRQn = 151 /**< PWM4 fault or reload error interrupt */ | ||
| 246 | } IRQn_Type; | ||
| 247 | |||
| 248 | /*! | ||
| 249 | * @} | ||
| 250 | */ /* end of group Interrupt_vector_numbers */ | ||
| 251 | |||
| 252 | |||
| 253 | /* ---------------------------------------------------------------------------- | ||
| 254 | -- Cortex M7 Core Configuration | ||
| 255 | ---------------------------------------------------------------------------- */ | ||
| 256 | |||
| 257 | /*! | ||
| 258 | * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration | ||
| 259 | * @{ | ||
| 260 | */ | ||
| 261 | |||
| 262 | #define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ | ||
| 263 | #define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */ | ||
| 264 | #define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */ | ||
| 265 | #define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */ | ||
| 266 | #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ | ||
| 267 | #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ | ||
| 268 | #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ | ||
| 269 | |||
| 270 | #include "core_cm7.h" /* Core Peripheral Access Layer */ | ||
| 271 | #include "system_MIMXRT1051.h" /* Device specific configuration file */ | ||
| 272 | |||
| 273 | /*! | ||
| 274 | * @} | ||
| 275 | */ /* end of group Cortex_Core_Configuration */ | ||
| 276 | |||
| 277 | |||
| 278 | /* ---------------------------------------------------------------------------- | ||
| 279 | -- Mapping Information | ||
| 280 | ---------------------------------------------------------------------------- */ | ||
| 281 | |||
| 282 | /*! | ||
| 283 | * @addtogroup Mapping_Information Mapping Information | ||
| 284 | * @{ | ||
| 285 | */ | ||
| 286 | |||
| 287 | /** Mapping Information */ | ||
| 288 | /*! | ||
| 289 | * @addtogroup edma_request | ||
| 290 | * @{ | ||
| 291 | */ | ||
| 292 | |||
| 293 | /******************************************************************************* | ||
| 294 | * Definitions | ||
| 295 | ******************************************************************************/ | ||
| 296 | |||
| 297 | /*! | ||
| 298 | * @brief Structure for the DMA hardware request | ||
| 299 | * | ||
| 300 | * Defines the structure for the DMA hardware request collections. The user can configure the | ||
| 301 | * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index | ||
| 302 | * of the hardware request varies according to the to SoC. | ||
| 303 | */ | ||
| 304 | typedef enum _dma_request_source | ||
| 305 | { | ||
| 306 | kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */ | ||
| 307 | kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 Request0 and Request1 */ | ||
| 308 | kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */ | ||
| 309 | kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */ | ||
| 310 | kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */ | ||
| 311 | kDmaRequestMuxLPUART3Rx = 5|0x100U, /**< LPUART3 Receive */ | ||
| 312 | kDmaRequestMuxLPUART5Tx = 6|0x100U, /**< LPUART5 Transmit */ | ||
| 313 | kDmaRequestMuxLPUART5Rx = 7|0x100U, /**< LPUART5 Receive */ | ||
| 314 | kDmaRequestMuxLPUART7Tx = 8|0x100U, /**< LPUART7 Transmit */ | ||
| 315 | kDmaRequestMuxLPUART7Rx = 9|0x100U, /**< LPUART7 Receive */ | ||
| 316 | kDmaRequestMuxLPSPI1Rx = 13|0x100U, /**< LPSPI1 Receive */ | ||
| 317 | kDmaRequestMuxLPSPI1Tx = 14|0x100U, /**< LPSPI1 Transmit */ | ||
| 318 | kDmaRequestMuxLPSPI3Rx = 15|0x100U, /**< LPSPI3 Receive */ | ||
| 319 | kDmaRequestMuxLPSPI3Tx = 16|0x100U, /**< LPSPI3 Transmit */ | ||
| 320 | kDmaRequestMuxLPI2C1 = 17|0x100U, /**< LPI2C1 */ | ||
| 321 | kDmaRequestMuxLPI2C3 = 18|0x100U, /**< LPI2C3 */ | ||
| 322 | kDmaRequestMuxSai1Rx = 19|0x100U, /**< SAI1 Receive */ | ||
| 323 | kDmaRequestMuxSai1Tx = 20|0x100U, /**< SAI1 Transmit */ | ||
| 324 | kDmaRequestMuxSai2Rx = 21|0x100U, /**< SAI2 Receive */ | ||
| 325 | kDmaRequestMuxSai2Tx = 22|0x100U, /**< SAI2 Transmit */ | ||
| 326 | kDmaRequestMuxADC_ETC = 23|0x100U, /**< ADC_ETC */ | ||
| 327 | kDmaRequestMuxADC1 = 24|0x100U, /**< ADC1 */ | ||
| 328 | kDmaRequestMuxACMP1 = 25|0x100U, /**< ACMP1 */ | ||
| 329 | kDmaRequestMuxACMP3 = 26|0x100U, /**< ACMP3 */ | ||
| 330 | kDmaRequestMuxFlexSPIRx = 28|0x100U, /**< FlexSPI Receive */ | ||
| 331 | kDmaRequestMuxFlexSPITx = 29|0x100U, /**< FlexSPI Transmit */ | ||
| 332 | kDmaRequestMuxXBAR1Request0 = 30|0x100U, /**< XBAR1 Request 0 */ | ||
| 333 | kDmaRequestMuxXBAR1Request1 = 31|0x100U, /**< XBAR1 Request 1 */ | ||
| 334 | kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, /**< FlexPWM1 Capture sub-module0 */ | ||
| 335 | kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U, /**< FlexPWM1 Capture sub-module1 */ | ||
| 336 | kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, /**< FlexPWM1 Capture sub-module2 */ | ||
| 337 | kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, /**< FlexPWM1 Capture sub-module3 */ | ||
| 338 | kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U, /**< FlexPWM1 Value sub-module0 */ | ||
| 339 | kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U, /**< FlexPWM1 Value sub-module1 */ | ||
| 340 | kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U, /**< FlexPWM1 Value sub-module2 */ | ||
| 341 | kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U, /**< FlexPWM1 Value sub-module3 */ | ||
| 342 | kDmaRequestMuxFlexPWM3CaptureSub0 = 40|0x100U, /**< FlexPWM3 Capture sub-module0 */ | ||
| 343 | kDmaRequestMuxFlexPWM3CaptureSub1 = 41|0x100U, /**< FlexPWM3 Capture sub-module1 */ | ||
| 344 | kDmaRequestMuxFlexPWM3CaptureSub2 = 42|0x100U, /**< FlexPWM3 Capture sub-module2 */ | ||
| 345 | kDmaRequestMuxFlexPWM3CaptureSub3 = 43|0x100U, /**< FlexPWM3 Capture sub-module3 */ | ||
| 346 | kDmaRequestMuxFlexPWM3ValueSub0 = 44|0x100U, /**< FlexPWM3 Value sub-module0 */ | ||
| 347 | kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U, /**< FlexPWM3 Value sub-module1 */ | ||
| 348 | kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U, /**< FlexPWM3 Value sub-module2 */ | ||
| 349 | kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U, /**< FlexPWM3 Value sub-module3 */ | ||
| 350 | kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< TMR1 Capture timer 0 */ | ||
| 351 | kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< TMR1 Capture timer 1 */ | ||
| 352 | kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< TMR1 Capture timer 2 */ | ||
| 353 | kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< TMR1 Capture timer 3 */ | ||
| 354 | kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */ | ||
| 355 | kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */ | ||
| 356 | kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */ | ||
| 357 | kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */ | ||
| 358 | kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, /**< TMR3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ | ||
| 359 | kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 57|0x100U, /**< TMR3 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */ | ||
| 360 | kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 58|0x100U, /**< TMR3 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */ | ||
| 361 | kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U, /**< TMR3 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */ | ||
| 362 | kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */ | ||
| 363 | kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 Request2 and Request3 */ | ||
| 364 | kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */ | ||
| 365 | kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */ | ||
| 366 | kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */ | ||
| 367 | kDmaRequestMuxLPUART4Rx = 69|0x100U, /**< LPUART4 Receive */ | ||
| 368 | kDmaRequestMuxLPUART6Tx = 70|0x100U, /**< LPUART6 Transmit */ | ||
| 369 | kDmaRequestMuxLPUART6Rx = 71|0x100U, /**< LPUART6 Receive */ | ||
| 370 | kDmaRequestMuxLPUART8Tx = 72|0x100U, /**< LPUART8 Transmit */ | ||
| 371 | kDmaRequestMuxLPUART8Rx = 73|0x100U, /**< LPUART8 Receive */ | ||
| 372 | kDmaRequestMuxLPSPI2Rx = 77|0x100U, /**< LPSPI2 Receive */ | ||
| 373 | kDmaRequestMuxLPSPI2Tx = 78|0x100U, /**< LPSPI2 Transmit */ | ||
| 374 | kDmaRequestMuxLPSPI4Rx = 79|0x100U, /**< LPSPI4 Receive */ | ||
| 375 | kDmaRequestMuxLPSPI4Tx = 80|0x100U, /**< LPSPI4 Transmit */ | ||
| 376 | kDmaRequestMuxLPI2C2 = 81|0x100U, /**< LPI2C2 */ | ||
| 377 | kDmaRequestMuxLPI2C4 = 82|0x100U, /**< LPI2C4 */ | ||
| 378 | kDmaRequestMuxSai3Rx = 83|0x100U, /**< SAI3 Receive */ | ||
| 379 | kDmaRequestMuxSai3Tx = 84|0x100U, /**< SAI3 Transmit */ | ||
| 380 | kDmaRequestMuxSpdifRx = 85|0x100U, /**< SPDIF Receive */ | ||
| 381 | kDmaRequestMuxSpdifTx = 86|0x100U, /**< SPDIF Transmit */ | ||
| 382 | kDmaRequestMuxADC2 = 88|0x100U, /**< ADC2 */ | ||
| 383 | kDmaRequestMuxACMP2 = 89|0x100U, /**< ACMP2 */ | ||
| 384 | kDmaRequestMuxACMP4 = 90|0x100U, /**< ACMP4 */ | ||
| 385 | kDmaRequestMuxEnetTimer0 = 92|0x100U, /**< ENET Timer0 */ | ||
| 386 | kDmaRequestMuxEnetTimer1 = 93|0x100U, /**< ENET Timer1 */ | ||
| 387 | kDmaRequestMuxXBAR1Request2 = 94|0x100U, /**< XBAR1 Request 2 */ | ||
| 388 | kDmaRequestMuxXBAR1Request3 = 95|0x100U, /**< XBAR1 Request 3 */ | ||
| 389 | kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, /**< FlexPWM2 Capture sub-module0 */ | ||
| 390 | kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U, /**< FlexPWM2 Capture sub-module1 */ | ||
| 391 | kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U, /**< FlexPWM2 Capture sub-module2 */ | ||
| 392 | kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U, /**< FlexPWM2 Capture sub-module3 */ | ||
| 393 | kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U, /**< FlexPWM2 Value sub-module0 */ | ||
| 394 | kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U, /**< FlexPWM2 Value sub-module1 */ | ||
| 395 | kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U, /**< FlexPWM2 Value sub-module2 */ | ||
| 396 | kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U, /**< FlexPWM2 Value sub-module3 */ | ||
| 397 | kDmaRequestMuxFlexPWM4CaptureSub0 = 104|0x100U, /**< FlexPWM4 Capture sub-module0 */ | ||
| 398 | kDmaRequestMuxFlexPWM4CaptureSub1 = 105|0x100U, /**< FlexPWM4 Capture sub-module1 */ | ||
| 399 | kDmaRequestMuxFlexPWM4CaptureSub2 = 106|0x100U, /**< FlexPWM4 Capture sub-module2 */ | ||
| 400 | kDmaRequestMuxFlexPWM4CaptureSub3 = 107|0x100U, /**< FlexPWM4 Capture sub-module3 */ | ||
| 401 | kDmaRequestMuxFlexPWM4ValueSub0 = 108|0x100U, /**< FlexPWM4 Value sub-module0 */ | ||
| 402 | kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U, /**< FlexPWM4 Value sub-module1 */ | ||
| 403 | kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U, /**< FlexPWM4 Value sub-module2 */ | ||
| 404 | kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U, /**< FlexPWM4 Value sub-module3 */ | ||
| 405 | kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, /**< TMR2 Capture timer 0 */ | ||
| 406 | kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, /**< TMR2 Capture timer 1 */ | ||
| 407 | kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U, /**< TMR2 Capture timer 2 */ | ||
| 408 | kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, /**< TMR2 Capture timer 3 */ | ||
| 409 | kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */ | ||
| 410 | kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */ | ||
| 411 | kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */ | ||
| 412 | kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */ | ||
| 413 | kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, /**< TMR4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ | ||
| 414 | kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 121|0x100U, /**< TMR4 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */ | ||
| 415 | kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 122|0x100U, /**< TMR4 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */ | ||
| 416 | kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 123|0x100U, /**< TMR4 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */ | ||
| 417 | } dma_request_source_t; | ||
| 418 | |||
| 419 | /* @} */ | ||
| 420 | |||
| 421 | /*! | ||
| 422 | * @addtogroup iomuxc_pads | ||
| 423 | * @{ */ | ||
| 424 | |||
| 425 | /******************************************************************************* | ||
| 426 | * Definitions | ||
| 427 | *******************************************************************************/ | ||
| 428 | |||
| 429 | /*! | ||
| 430 | * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD | ||
| 431 | * | ||
| 432 | * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections. | ||
| 433 | */ | ||
| 434 | typedef enum _iomuxc_sw_mux_ctl_pad | ||
| 435 | { | ||
| 436 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 437 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 438 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 439 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 440 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 441 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 442 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 443 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 444 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 445 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 446 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 447 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 448 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 449 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 450 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 451 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 452 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 453 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 454 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 455 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 456 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 457 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 458 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 459 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 460 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 461 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 462 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 463 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 464 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 465 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 466 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 467 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 468 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 469 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 470 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 471 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 472 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 473 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 474 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 475 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 476 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 477 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 478 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 479 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 480 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 481 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 482 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 483 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 484 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 485 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 486 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 487 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 488 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 489 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 490 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 491 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 492 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 493 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 494 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 495 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 496 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 497 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 498 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 499 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 500 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 501 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 502 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 503 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 504 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 505 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 506 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 507 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 508 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 509 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 510 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 511 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 512 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 513 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 514 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 515 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 516 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 517 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 518 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 519 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 520 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 521 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 522 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 523 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 524 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 525 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 526 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 527 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 528 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 529 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 530 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 531 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 532 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 533 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 534 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 535 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 536 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 537 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 538 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 539 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 540 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 541 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 542 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 543 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 544 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 545 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 546 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 547 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 548 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 549 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 550 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 551 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 552 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 553 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 554 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 555 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 556 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 557 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 558 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 559 | kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */ | ||
| 560 | } iomuxc_sw_mux_ctl_pad_t; | ||
| 561 | |||
| 562 | /* @} */ | ||
| 563 | |||
| 564 | /*! | ||
| 565 | * @addtogroup iomuxc_pads | ||
| 566 | * @{ */ | ||
| 567 | |||
| 568 | /******************************************************************************* | ||
| 569 | * Definitions | ||
| 570 | *******************************************************************************/ | ||
| 571 | |||
| 572 | /*! | ||
| 573 | * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD | ||
| 574 | * | ||
| 575 | * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections. | ||
| 576 | */ | ||
| 577 | typedef enum _iomuxc_sw_pad_ctl_pad | ||
| 578 | { | ||
| 579 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 580 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 581 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 582 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 583 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 584 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 585 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 586 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 587 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 588 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 589 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 590 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 591 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 592 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 593 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 594 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 595 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 596 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 597 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 598 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 599 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 600 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 601 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 602 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 603 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 604 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 605 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 606 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 607 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 608 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 609 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 610 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 611 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 612 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 613 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 614 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 615 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 616 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 617 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 618 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 619 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 620 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 621 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 622 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 623 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 624 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 625 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 626 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 627 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 628 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 629 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 630 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 631 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 632 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 633 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 634 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 635 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 636 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 637 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 638 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 639 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 640 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 641 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 642 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 643 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 644 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 645 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 646 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 647 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 648 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 649 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 650 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 651 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 652 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 653 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 654 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 655 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 656 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 657 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 658 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 659 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 660 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 661 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 662 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 663 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 664 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 665 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 666 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 667 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 668 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 669 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 670 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 671 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 672 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 673 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 674 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 675 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 676 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 677 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 678 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 679 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 680 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 681 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 682 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 683 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 684 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 685 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 686 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 687 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 688 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 689 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 690 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 691 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 692 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 693 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 694 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 695 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 696 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 697 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 698 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 699 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 700 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 701 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 702 | kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */ | ||
| 703 | } iomuxc_sw_pad_ctl_pad_t; | ||
| 704 | |||
| 705 | /* @} */ | ||
| 706 | |||
| 707 | /*! | ||
| 708 | * @brief Enumeration for the IOMUXC select input | ||
| 709 | * | ||
| 710 | * Defines the enumeration for the IOMUXC select input collections. | ||
| 711 | */ | ||
| 712 | typedef enum _iomuxc_select_input | ||
| 713 | { | ||
| 714 | kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */ | ||
| 715 | kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U, /**< IOMUXC select input index */ | ||
| 716 | kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U, /**< IOMUXC select input index */ | ||
| 717 | kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U, /**< IOMUXC select input index */ | ||
| 718 | kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U, /**< IOMUXC select input index */ | ||
| 719 | kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U, /**< IOMUXC select input index */ | ||
| 720 | kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U, /**< IOMUXC select input index */ | ||
| 721 | kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U, /**< IOMUXC select input index */ | ||
| 722 | kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U, /**< IOMUXC select input index */ | ||
| 723 | kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U, /**< IOMUXC select input index */ | ||
| 724 | kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U, /**< IOMUXC select input index */ | ||
| 725 | kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U, /**< IOMUXC select input index */ | ||
| 726 | kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U, /**< IOMUXC select input index */ | ||
| 727 | kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U, /**< IOMUXC select input index */ | ||
| 728 | kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U, /**< IOMUXC select input index */ | ||
| 729 | kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U, /**< IOMUXC select input index */ | ||
| 730 | kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U, /**< IOMUXC select input index */ | ||
| 731 | kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U, /**< IOMUXC select input index */ | ||
| 732 | kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U, /**< IOMUXC select input index */ | ||
| 733 | kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U, /**< IOMUXC select input index */ | ||
| 734 | kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U, /**< IOMUXC select input index */ | ||
| 735 | kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U, /**< IOMUXC select input index */ | ||
| 736 | kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U, /**< IOMUXC select input index */ | ||
| 737 | kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U, /**< IOMUXC select input index */ | ||
| 738 | kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U, /**< IOMUXC select input index */ | ||
| 739 | kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U, /**< IOMUXC select input index */ | ||
| 740 | kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U, /**< IOMUXC select input index */ | ||
| 741 | kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U, /**< IOMUXC select input index */ | ||
| 742 | kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U, /**< IOMUXC select input index */ | ||
| 743 | kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U, /**< IOMUXC select input index */ | ||
| 744 | kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U, /**< IOMUXC select input index */ | ||
| 745 | kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U, /**< IOMUXC select input index */ | ||
| 746 | kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U, /**< IOMUXC select input index */ | ||
| 747 | kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U, /**< IOMUXC select input index */ | ||
| 748 | kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U, /**< IOMUXC select input index */ | ||
| 749 | kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U, /**< IOMUXC select input index */ | ||
| 750 | kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U, /**< IOMUXC select input index */ | ||
| 751 | kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U, /**< IOMUXC select input index */ | ||
| 752 | kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U, /**< IOMUXC select input index */ | ||
| 753 | kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U, /**< IOMUXC select input index */ | ||
| 754 | kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U, /**< IOMUXC select input index */ | ||
| 755 | kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U, /**< IOMUXC select input index */ | ||
| 756 | kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U, /**< IOMUXC select input index */ | ||
| 757 | kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U, /**< IOMUXC select input index */ | ||
| 758 | kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT = 44U, /**< IOMUXC select input index */ | ||
| 759 | kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT = 45U, /**< IOMUXC select input index */ | ||
| 760 | kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT = 46U, /**< IOMUXC select input index */ | ||
| 761 | kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT = 47U, /**< IOMUXC select input index */ | ||
| 762 | kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT = 48U, /**< IOMUXC select input index */ | ||
| 763 | kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT = 49U, /**< IOMUXC select input index */ | ||
| 764 | kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT = 50U, /**< IOMUXC select input index */ | ||
| 765 | kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT = 51U, /**< IOMUXC select input index */ | ||
| 766 | kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT = 52U, /**< IOMUXC select input index */ | ||
| 767 | kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT = 53U, /**< IOMUXC select input index */ | ||
| 768 | kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U, /**< IOMUXC select input index */ | ||
| 769 | kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U, /**< IOMUXC select input index */ | ||
| 770 | kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U, /**< IOMUXC select input index */ | ||
| 771 | kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U, /**< IOMUXC select input index */ | ||
| 772 | kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U, /**< IOMUXC select input index */ | ||
| 773 | kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U, /**< IOMUXC select input index */ | ||
| 774 | kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U, /**< IOMUXC select input index */ | ||
| 775 | kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U, /**< IOMUXC select input index */ | ||
| 776 | kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U, /**< IOMUXC select input index */ | ||
| 777 | kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U, /**< IOMUXC select input index */ | ||
| 778 | kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U, /**< IOMUXC select input index */ | ||
| 779 | kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U, /**< IOMUXC select input index */ | ||
| 780 | kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U, /**< IOMUXC select input index */ | ||
| 781 | kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U, /**< IOMUXC select input index */ | ||
| 782 | kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U, /**< IOMUXC select input index */ | ||
| 783 | kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U, /**< IOMUXC select input index */ | ||
| 784 | kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U, /**< IOMUXC select input index */ | ||
| 785 | kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U, /**< IOMUXC select input index */ | ||
| 786 | kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U, /**< IOMUXC select input index */ | ||
| 787 | kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U, /**< IOMUXC select input index */ | ||
| 788 | kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U, /**< IOMUXC select input index */ | ||
| 789 | kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U, /**< IOMUXC select input index */ | ||
| 790 | kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U, /**< IOMUXC select input index */ | ||
| 791 | kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U, /**< IOMUXC select input index */ | ||
| 792 | kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U, /**< IOMUXC select input index */ | ||
| 793 | kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U, /**< IOMUXC select input index */ | ||
| 794 | kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U, /**< IOMUXC select input index */ | ||
| 795 | kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U, /**< IOMUXC select input index */ | ||
| 796 | kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U, /**< IOMUXC select input index */ | ||
| 797 | kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U, /**< IOMUXC select input index */ | ||
| 798 | kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U, /**< IOMUXC select input index */ | ||
| 799 | kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U, /**< IOMUXC select input index */ | ||
| 800 | kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U, /**< IOMUXC select input index */ | ||
| 801 | kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U, /**< IOMUXC select input index */ | ||
| 802 | kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U, /**< IOMUXC select input index */ | ||
| 803 | kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U, /**< IOMUXC select input index */ | ||
| 804 | kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U, /**< IOMUXC select input index */ | ||
| 805 | kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U, /**< IOMUXC select input index */ | ||
| 806 | kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U, /**< IOMUXC select input index */ | ||
| 807 | kIOMUXC_NMI_SELECT_INPUT = 93U, /**< IOMUXC select input index */ | ||
| 808 | kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U, /**< IOMUXC select input index */ | ||
| 809 | kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U, /**< IOMUXC select input index */ | ||
| 810 | kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U, /**< IOMUXC select input index */ | ||
| 811 | kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U, /**< IOMUXC select input index */ | ||
| 812 | kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U, /**< IOMUXC select input index */ | ||
| 813 | kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U, /**< IOMUXC select input index */ | ||
| 814 | kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U, /**< IOMUXC select input index */ | ||
| 815 | kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U, /**< IOMUXC select input index */ | ||
| 816 | kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U, /**< IOMUXC select input index */ | ||
| 817 | kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U, /**< IOMUXC select input index */ | ||
| 818 | kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U, /**< IOMUXC select input index */ | ||
| 819 | kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U, /**< IOMUXC select input index */ | ||
| 820 | kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U, /**< IOMUXC select input index */ | ||
| 821 | kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U, /**< IOMUXC select input index */ | ||
| 822 | kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U, /**< IOMUXC select input index */ | ||
| 823 | kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U, /**< IOMUXC select input index */ | ||
| 824 | kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U, /**< IOMUXC select input index */ | ||
| 825 | kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U, /**< IOMUXC select input index */ | ||
| 826 | kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U, /**< IOMUXC select input index */ | ||
| 827 | kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U, /**< IOMUXC select input index */ | ||
| 828 | kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U, /**< IOMUXC select input index */ | ||
| 829 | kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U, /**< IOMUXC select input index */ | ||
| 830 | kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U, /**< IOMUXC select input index */ | ||
| 831 | kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U, /**< IOMUXC select input index */ | ||
| 832 | kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U, /**< IOMUXC select input index */ | ||
| 833 | kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U, /**< IOMUXC select input index */ | ||
| 834 | kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U, /**< IOMUXC select input index */ | ||
| 835 | kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U, /**< IOMUXC select input index */ | ||
| 836 | kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U, /**< IOMUXC select input index */ | ||
| 837 | kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U, /**< IOMUXC select input index */ | ||
| 838 | kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U, /**< IOMUXC select input index */ | ||
| 839 | kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U, /**< IOMUXC select input index */ | ||
| 840 | kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U, /**< IOMUXC select input index */ | ||
| 841 | kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U, /**< IOMUXC select input index */ | ||
| 842 | kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U, /**< IOMUXC select input index */ | ||
| 843 | kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U, /**< IOMUXC select input index */ | ||
| 844 | kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U, /**< IOMUXC select input index */ | ||
| 845 | kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U, /**< IOMUXC select input index */ | ||
| 846 | kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U, /**< IOMUXC select input index */ | ||
| 847 | kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U, /**< IOMUXC select input index */ | ||
| 848 | kIOMUXC_XBAR1_IN02_SELECT_INPUT = 134U, /**< IOMUXC select input index */ | ||
| 849 | kIOMUXC_XBAR1_IN03_SELECT_INPUT = 135U, /**< IOMUXC select input index */ | ||
| 850 | kIOMUXC_XBAR1_IN04_SELECT_INPUT = 136U, /**< IOMUXC select input index */ | ||
| 851 | kIOMUXC_XBAR1_IN05_SELECT_INPUT = 137U, /**< IOMUXC select input index */ | ||
| 852 | kIOMUXC_XBAR1_IN06_SELECT_INPUT = 138U, /**< IOMUXC select input index */ | ||
| 853 | kIOMUXC_XBAR1_IN07_SELECT_INPUT = 139U, /**< IOMUXC select input index */ | ||
| 854 | kIOMUXC_XBAR1_IN08_SELECT_INPUT = 140U, /**< IOMUXC select input index */ | ||
| 855 | kIOMUXC_XBAR1_IN09_SELECT_INPUT = 141U, /**< IOMUXC select input index */ | ||
| 856 | kIOMUXC_XBAR1_IN17_SELECT_INPUT = 142U, /**< IOMUXC select input index */ | ||
| 857 | kIOMUXC_XBAR1_IN18_SELECT_INPUT = 143U, /**< IOMUXC select input index */ | ||
| 858 | kIOMUXC_XBAR1_IN20_SELECT_INPUT = 144U, /**< IOMUXC select input index */ | ||
| 859 | kIOMUXC_XBAR1_IN22_SELECT_INPUT = 145U, /**< IOMUXC select input index */ | ||
| 860 | kIOMUXC_XBAR1_IN23_SELECT_INPUT = 146U, /**< IOMUXC select input index */ | ||
| 861 | kIOMUXC_XBAR1_IN24_SELECT_INPUT = 147U, /**< IOMUXC select input index */ | ||
| 862 | kIOMUXC_XBAR1_IN14_SELECT_INPUT = 148U, /**< IOMUXC select input index */ | ||
| 863 | kIOMUXC_XBAR1_IN15_SELECT_INPUT = 149U, /**< IOMUXC select input index */ | ||
| 864 | kIOMUXC_XBAR1_IN16_SELECT_INPUT = 150U, /**< IOMUXC select input index */ | ||
| 865 | kIOMUXC_XBAR1_IN25_SELECT_INPUT = 151U, /**< IOMUXC select input index */ | ||
| 866 | kIOMUXC_XBAR1_IN19_SELECT_INPUT = 152U, /**< IOMUXC select input index */ | ||
| 867 | kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U, /**< IOMUXC select input index */ | ||
| 868 | } iomuxc_select_input_t; | ||
| 869 | |||
| 870 | typedef enum _xbar_input_signal | ||
| 871 | { | ||
| 872 | kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */ | ||
| 873 | kXBARA1_InputLogicHigh = 1|0x100U, /**< LOGIC_HIGH output assigned to XBARA1_IN1 input. */ | ||
| 874 | kXBARA1_InputIomuxXbarIn02 = 2|0x100U, /**< IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */ | ||
| 875 | kXBARA1_InputIomuxXbarIn03 = 3|0x100U, /**< IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */ | ||
| 876 | kXBARA1_InputIomuxXbarInout04 = 4|0x100U, /**< IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */ | ||
| 877 | kXBARA1_InputIomuxXbarInout05 = 5|0x100U, /**< IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */ | ||
| 878 | kXBARA1_InputIomuxXbarInout06 = 6|0x100U, /**< IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */ | ||
| 879 | kXBARA1_InputIomuxXbarInout07 = 7|0x100U, /**< IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */ | ||
| 880 | kXBARA1_InputIomuxXbarInout08 = 8|0x100U, /**< IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */ | ||
| 881 | kXBARA1_InputIomuxXbarInout09 = 9|0x100U, /**< IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */ | ||
| 882 | kXBARA1_InputIomuxXbarInout10 = 10|0x100U, /**< IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */ | ||
| 883 | kXBARA1_InputIomuxXbarInout11 = 11|0x100U, /**< IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */ | ||
| 884 | kXBARA1_InputIomuxXbarInout12 = 12|0x100U, /**< IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */ | ||
| 885 | kXBARA1_InputIomuxXbarInout13 = 13|0x100U, /**< IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */ | ||
| 886 | kXBARA1_InputIomuxXbarInout14 = 14|0x100U, /**< IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */ | ||
| 887 | kXBARA1_InputIomuxXbarInout15 = 15|0x100U, /**< IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */ | ||
| 888 | kXBARA1_InputIomuxXbarInout16 = 16|0x100U, /**< IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */ | ||
| 889 | kXBARA1_InputIomuxXbarInout17 = 17|0x100U, /**< IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */ | ||
| 890 | kXBARA1_InputIomuxXbarInout18 = 18|0x100U, /**< IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */ | ||
| 891 | kXBARA1_InputIomuxXbarInout19 = 19|0x100U, /**< IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */ | ||
| 892 | kXBARA1_InputIomuxXbarIn20 = 20|0x100U, /**< IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */ | ||
| 893 | kXBARA1_InputIomuxXbarIn21 = 21|0x100U, /**< IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */ | ||
| 894 | kXBARA1_InputIomuxXbarIn22 = 22|0x100U, /**< IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */ | ||
| 895 | kXBARA1_InputIomuxXbarIn23 = 23|0x100U, /**< IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */ | ||
| 896 | kXBARA1_InputIomuxXbarIn24 = 24|0x100U, /**< IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */ | ||
| 897 | kXBARA1_InputIomuxXbarIn25 = 25|0x100U, /**< IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */ | ||
| 898 | kXBARA1_InputAcmp1Out = 26|0x100U, /**< ACMP1_OUT output assigned to XBARA1_IN26 input. */ | ||
| 899 | kXBARA1_InputAcmp2Out = 27|0x100U, /**< ACMP2_OUT output assigned to XBARA1_IN27 input. */ | ||
| 900 | kXBARA1_InputAcmp3Out = 28|0x100U, /**< ACMP3_OUT output assigned to XBARA1_IN28 input. */ | ||
| 901 | kXBARA1_InputAcmp4Out = 29|0x100U, /**< ACMP4_OUT output assigned to XBARA1_IN29 input. */ | ||
| 902 | kXBARA1_InputRESERVED30 = 30|0x100U, /**< XBARA1_IN30 input is reserved. */ | ||
| 903 | kXBARA1_InputRESERVED31 = 31|0x100U, /**< XBARA1_IN31 input is reserved. */ | ||
| 904 | kXBARA1_InputQtimer3Tmr0Output = 32|0x100U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */ | ||
| 905 | kXBARA1_InputQtimer3Tmr1Output = 33|0x100U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */ | ||
| 906 | kXBARA1_InputQtimer3Tmr2Output = 34|0x100U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */ | ||
| 907 | kXBARA1_InputQtimer3Tmr3Output = 35|0x100U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */ | ||
| 908 | kXBARA1_InputQtimer4Tmr0Output = 36|0x100U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */ | ||
| 909 | kXBARA1_InputQtimer4Tmr1Output = 37|0x100U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */ | ||
| 910 | kXBARA1_InputQtimer4Tmr2Output = 38|0x100U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */ | ||
| 911 | kXBARA1_InputQtimer4Tmr3Output = 39|0x100U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */ | ||
| 912 | kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */ | ||
| 913 | kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */ | ||
| 914 | kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */ | ||
| 915 | kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */ | ||
| 916 | kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */ | ||
| 917 | kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */ | ||
| 918 | kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */ | ||
| 919 | kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */ | ||
| 920 | kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */ | ||
| 921 | kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */ | ||
| 922 | kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */ | ||
| 923 | kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */ | ||
| 924 | kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */ | ||
| 925 | kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */ | ||
| 926 | kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */ | ||
| 927 | kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */ | ||
| 928 | kXBARA1_InputPitTrigger0 = 56|0x100U, /**< PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */ | ||
| 929 | kXBARA1_InputPitTrigger1 = 57|0x100U, /**< PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */ | ||
| 930 | kXBARA1_InputPitTrigger2 = 58|0x100U, /**< PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */ | ||
| 931 | kXBARA1_InputPitTrigger3 = 59|0x100U, /**< PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */ | ||
| 932 | kXBARA1_InputEnc1PosMatch = 60|0x100U, /**< ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */ | ||
| 933 | kXBARA1_InputEnc2PosMatch = 61|0x100U, /**< ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */ | ||
| 934 | kXBARA1_InputEnc3PosMatch = 62|0x100U, /**< ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */ | ||
| 935 | kXBARA1_InputEnc4PosMatch = 63|0x100U, /**< ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */ | ||
| 936 | kXBARA1_InputDmaDone0 = 64|0x100U, /**< DMA_DONE0 output assigned to XBARA1_IN64 input. */ | ||
| 937 | kXBARA1_InputDmaDone1 = 65|0x100U, /**< DMA_DONE1 output assigned to XBARA1_IN65 input. */ | ||
| 938 | kXBARA1_InputDmaDone2 = 66|0x100U, /**< DMA_DONE2 output assigned to XBARA1_IN66 input. */ | ||
| 939 | kXBARA1_InputDmaDone3 = 67|0x100U, /**< DMA_DONE3 output assigned to XBARA1_IN67 input. */ | ||
| 940 | kXBARA1_InputDmaDone4 = 68|0x100U, /**< DMA_DONE4 output assigned to XBARA1_IN68 input. */ | ||
| 941 | kXBARA1_InputDmaDone5 = 69|0x100U, /**< DMA_DONE5 output assigned to XBARA1_IN69 input. */ | ||
| 942 | kXBARA1_InputDmaDone6 = 70|0x100U, /**< DMA_DONE6 output assigned to XBARA1_IN70 input. */ | ||
| 943 | kXBARA1_InputDmaDone7 = 71|0x100U, /**< DMA_DONE7 output assigned to XBARA1_IN71 input. */ | ||
| 944 | kXBARA1_InputAoi1Out0 = 72|0x100U, /**< AOI1_OUT0 output assigned to XBARA1_IN72 input. */ | ||
| 945 | kXBARA1_InputAoi1Out1 = 73|0x100U, /**< AOI1_OUT1 output assigned to XBARA1_IN73 input. */ | ||
| 946 | kXBARA1_InputAoi1Out2 = 74|0x100U, /**< AOI1_OUT2 output assigned to XBARA1_IN74 input. */ | ||
| 947 | kXBARA1_InputAoi1Out3 = 75|0x100U, /**< AOI1_OUT3 output assigned to XBARA1_IN75 input. */ | ||
| 948 | kXBARA1_InputAoi2Out0 = 76|0x100U, /**< AOI2_OUT0 output assigned to XBARA1_IN76 input. */ | ||
| 949 | kXBARA1_InputAoi2Out1 = 77|0x100U, /**< AOI2_OUT1 output assigned to XBARA1_IN77 input. */ | ||
| 950 | kXBARA1_InputAoi2Out2 = 78|0x100U, /**< AOI2_OUT2 output assigned to XBARA1_IN78 input. */ | ||
| 951 | kXBARA1_InputAoi2Out3 = 79|0x100U, /**< AOI2_OUT3 output assigned to XBARA1_IN79 input. */ | ||
| 952 | kXBARA1_InputAdcEtcXbar0Coco0 = 80|0x100U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */ | ||
| 953 | kXBARA1_InputAdcEtcXbar0Coco1 = 81|0x100U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */ | ||
| 954 | kXBARA1_InputAdcEtcXbar0Coco2 = 82|0x100U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */ | ||
| 955 | kXBARA1_InputAdcEtcXbar0Coco3 = 83|0x100U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */ | ||
| 956 | kXBARA1_InputAdcEtcXbar1Coco0 = 84|0x100U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */ | ||
| 957 | kXBARA1_InputAdcEtcXbar1Coco1 = 85|0x100U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */ | ||
| 958 | kXBARA1_InputAdcEtcXbar1Coco2 = 86|0x100U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */ | ||
| 959 | kXBARA1_InputAdcEtcXbar1Coco3 = 87|0x100U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */ | ||
| 960 | kXBARB2_InputLogicLow = 0|0x200U, /**< LOGIC_LOW output assigned to XBARB2_IN0 input. */ | ||
| 961 | kXBARB2_InputLogicHigh = 1|0x200U, /**< LOGIC_HIGH output assigned to XBARB2_IN1 input. */ | ||
| 962 | kXBARB2_InputRESERVED2 = 2|0x200U, /**< XBARB2_IN2 input is reserved. */ | ||
| 963 | kXBARB2_InputRESERVED3 = 3|0x200U, /**< XBARB2_IN3 input is reserved. */ | ||
| 964 | kXBARB2_InputRESERVED4 = 4|0x200U, /**< XBARB2_IN4 input is reserved. */ | ||
| 965 | kXBARB2_InputRESERVED5 = 5|0x200U, /**< XBARB2_IN5 input is reserved. */ | ||
| 966 | kXBARB2_InputAcmp1Out = 6|0x200U, /**< ACMP1_OUT output assigned to XBARB2_IN6 input. */ | ||
| 967 | kXBARB2_InputAcmp2Out = 7|0x200U, /**< ACMP2_OUT output assigned to XBARB2_IN7 input. */ | ||
| 968 | kXBARB2_InputAcmp3Out = 8|0x200U, /**< ACMP3_OUT output assigned to XBARB2_IN8 input. */ | ||
| 969 | kXBARB2_InputAcmp4Out = 9|0x200U, /**< ACMP4_OUT output assigned to XBARB2_IN9 input. */ | ||
| 970 | kXBARB2_InputRESERVED10 = 10|0x200U, /**< XBARB2_IN10 input is reserved. */ | ||
| 971 | kXBARB2_InputRESERVED11 = 11|0x200U, /**< XBARB2_IN11 input is reserved. */ | ||
| 972 | kXBARB2_InputQtimer3Tmr0Output = 12|0x200U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */ | ||
| 973 | kXBARB2_InputQtimer3Tmr1Output = 13|0x200U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */ | ||
| 974 | kXBARB2_InputQtimer3Tmr2Output = 14|0x200U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */ | ||
| 975 | kXBARB2_InputQtimer3Tmr3Output = 15|0x200U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */ | ||
| 976 | kXBARB2_InputQtimer4Tmr0Output = 16|0x200U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */ | ||
| 977 | kXBARB2_InputQtimer4Tmr1Output = 17|0x200U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */ | ||
| 978 | kXBARB2_InputQtimer4Tmr2Output = 18|0x200U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */ | ||
| 979 | kXBARB2_InputQtimer4Tmr3Output = 19|0x200U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */ | ||
| 980 | kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */ | ||
| 981 | kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */ | ||
| 982 | kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */ | ||
| 983 | kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */ | ||
| 984 | kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */ | ||
| 985 | kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */ | ||
| 986 | kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */ | ||
| 987 | kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */ | ||
| 988 | kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */ | ||
| 989 | kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */ | ||
| 990 | kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */ | ||
| 991 | kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */ | ||
| 992 | kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */ | ||
| 993 | kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */ | ||
| 994 | kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */ | ||
| 995 | kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */ | ||
| 996 | kXBARB2_InputPitTrigger0 = 36|0x200U, /**< PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */ | ||
| 997 | kXBARB2_InputPitTrigger1 = 37|0x200U, /**< PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */ | ||
| 998 | kXBARB2_InputAdcEtcXbar0Coco0 = 38|0x200U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */ | ||
| 999 | kXBARB2_InputAdcEtcXbar0Coco1 = 39|0x200U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */ | ||
| 1000 | kXBARB2_InputAdcEtcXbar0Coco2 = 40|0x200U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */ | ||
| 1001 | kXBARB2_InputAdcEtcXbar0Coco3 = 41|0x200U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */ | ||
| 1002 | kXBARB2_InputAdcEtcXbar1Coco0 = 42|0x200U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */ | ||
| 1003 | kXBARB2_InputAdcEtcXbar1Coco1 = 43|0x200U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */ | ||
| 1004 | kXBARB2_InputAdcEtcXbar1Coco2 = 44|0x200U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */ | ||
| 1005 | kXBARB2_InputAdcEtcXbar1Coco3 = 45|0x200U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */ | ||
| 1006 | kXBARB2_InputEnc1PosMatch = 46|0x200U, /**< ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */ | ||
| 1007 | kXBARB2_InputEnc2PosMatch = 47|0x200U, /**< ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */ | ||
| 1008 | kXBARB2_InputEnc3PosMatch = 48|0x200U, /**< ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */ | ||
| 1009 | kXBARB2_InputEnc4PosMatch = 49|0x200U, /**< ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */ | ||
| 1010 | kXBARB2_InputDmaDone0 = 50|0x200U, /**< DMA_DONE0 output assigned to XBARB2_IN50 input. */ | ||
| 1011 | kXBARB2_InputDmaDone1 = 51|0x200U, /**< DMA_DONE1 output assigned to XBARB2_IN51 input. */ | ||
| 1012 | kXBARB2_InputDmaDone2 = 52|0x200U, /**< DMA_DONE2 output assigned to XBARB2_IN52 input. */ | ||
| 1013 | kXBARB2_InputDmaDone3 = 53|0x200U, /**< DMA_DONE3 output assigned to XBARB2_IN53 input. */ | ||
| 1014 | kXBARB2_InputDmaDone4 = 54|0x200U, /**< DMA_DONE4 output assigned to XBARB2_IN54 input. */ | ||
| 1015 | kXBARB2_InputDmaDone5 = 55|0x200U, /**< DMA_DONE5 output assigned to XBARB2_IN55 input. */ | ||
| 1016 | kXBARB2_InputDmaDone6 = 56|0x200U, /**< DMA_DONE6 output assigned to XBARB2_IN56 input. */ | ||
| 1017 | kXBARB2_InputDmaDone7 = 57|0x200U, /**< DMA_DONE7 output assigned to XBARB2_IN57 input. */ | ||
| 1018 | kXBARB3_InputLogicLow = 0|0x300U, /**< LOGIC_LOW output assigned to XBARB3_IN0 input. */ | ||
| 1019 | kXBARB3_InputLogicHigh = 1|0x300U, /**< LOGIC_HIGH output assigned to XBARB3_IN1 input. */ | ||
| 1020 | kXBARB3_InputRESERVED2 = 2|0x300U, /**< XBARB3_IN2 input is reserved. */ | ||
| 1021 | kXBARB3_InputRESERVED3 = 3|0x300U, /**< XBARB3_IN3 input is reserved. */ | ||
| 1022 | kXBARB3_InputRESERVED4 = 4|0x300U, /**< XBARB3_IN4 input is reserved. */ | ||
| 1023 | kXBARB3_InputRESERVED5 = 5|0x300U, /**< XBARB3_IN5 input is reserved. */ | ||
| 1024 | kXBARB3_InputAcmp1Out = 6|0x300U, /**< ACMP1_OUT output assigned to XBARB3_IN6 input. */ | ||
| 1025 | kXBARB3_InputAcmp2Out = 7|0x300U, /**< ACMP2_OUT output assigned to XBARB3_IN7 input. */ | ||
| 1026 | kXBARB3_InputAcmp3Out = 8|0x300U, /**< ACMP3_OUT output assigned to XBARB3_IN8 input. */ | ||
| 1027 | kXBARB3_InputAcmp4Out = 9|0x300U, /**< ACMP4_OUT output assigned to XBARB3_IN9 input. */ | ||
| 1028 | kXBARB3_InputRESERVED10 = 10|0x300U, /**< XBARB3_IN10 input is reserved. */ | ||
| 1029 | kXBARB3_InputRESERVED11 = 11|0x300U, /**< XBARB3_IN11 input is reserved. */ | ||
| 1030 | kXBARB3_InputQtimer3Tmr0Output = 12|0x300U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */ | ||
| 1031 | kXBARB3_InputQtimer3Tmr1Output = 13|0x300U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */ | ||
| 1032 | kXBARB3_InputQtimer3Tmr2Output = 14|0x300U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */ | ||
| 1033 | kXBARB3_InputQtimer3Tmr3Output = 15|0x300U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */ | ||
| 1034 | kXBARB3_InputQtimer4Tmr0Output = 16|0x300U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */ | ||
| 1035 | kXBARB3_InputQtimer4Tmr1Output = 17|0x300U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */ | ||
| 1036 | kXBARB3_InputQtimer4Tmr2Output = 18|0x300U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */ | ||
| 1037 | kXBARB3_InputQtimer4Tmr3Output = 19|0x300U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */ | ||
| 1038 | kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */ | ||
| 1039 | kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */ | ||
| 1040 | kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */ | ||
| 1041 | kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */ | ||
| 1042 | kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */ | ||
| 1043 | kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */ | ||
| 1044 | kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */ | ||
| 1045 | kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */ | ||
| 1046 | kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */ | ||
| 1047 | kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */ | ||
| 1048 | kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */ | ||
| 1049 | kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */ | ||
| 1050 | kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */ | ||
| 1051 | kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */ | ||
| 1052 | kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */ | ||
| 1053 | kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */ | ||
| 1054 | kXBARB3_InputPitTrigger0 = 36|0x300U, /**< PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */ | ||
| 1055 | kXBARB3_InputPitTrigger1 = 37|0x300U, /**< PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */ | ||
| 1056 | kXBARB3_InputAdcEtcXbar0Coco0 = 38|0x300U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */ | ||
| 1057 | kXBARB3_InputAdcEtcXbar0Coco1 = 39|0x300U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */ | ||
| 1058 | kXBARB3_InputAdcEtcXbar0Coco2 = 40|0x300U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */ | ||
| 1059 | kXBARB3_InputAdcEtcXbar0Coco3 = 41|0x300U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */ | ||
| 1060 | kXBARB3_InputAdcEtcXbar1Coco0 = 42|0x300U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */ | ||
| 1061 | kXBARB3_InputAdcEtcXbar1Coco1 = 43|0x300U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */ | ||
| 1062 | kXBARB3_InputAdcEtcXbar1Coco2 = 44|0x300U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */ | ||
| 1063 | kXBARB3_InputAdcEtcXbar1Coco3 = 45|0x300U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */ | ||
| 1064 | kXBARB3_InputEnc1PosMatch = 46|0x300U, /**< ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */ | ||
| 1065 | kXBARB3_InputEnc2PosMatch = 47|0x300U, /**< ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */ | ||
| 1066 | kXBARB3_InputEnc3PosMatch = 48|0x300U, /**< ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */ | ||
| 1067 | kXBARB3_InputEnc4PosMatch = 49|0x300U, /**< ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */ | ||
| 1068 | kXBARB3_InputDmaDone0 = 50|0x300U, /**< DMA_DONE0 output assigned to XBARB3_IN50 input. */ | ||
| 1069 | kXBARB3_InputDmaDone1 = 51|0x300U, /**< DMA_DONE1 output assigned to XBARB3_IN51 input. */ | ||
| 1070 | kXBARB3_InputDmaDone2 = 52|0x300U, /**< DMA_DONE2 output assigned to XBARB3_IN52 input. */ | ||
| 1071 | kXBARB3_InputDmaDone3 = 53|0x300U, /**< DMA_DONE3 output assigned to XBARB3_IN53 input. */ | ||
| 1072 | kXBARB3_InputDmaDone4 = 54|0x300U, /**< DMA_DONE4 output assigned to XBARB3_IN54 input. */ | ||
| 1073 | kXBARB3_InputDmaDone5 = 55|0x300U, /**< DMA_DONE5 output assigned to XBARB3_IN55 input. */ | ||
| 1074 | kXBARB3_InputDmaDone6 = 56|0x300U, /**< DMA_DONE6 output assigned to XBARB3_IN56 input. */ | ||
| 1075 | kXBARB3_InputDmaDone7 = 57|0x300U, /**< DMA_DONE7 output assigned to XBARB3_IN57 input. */ | ||
| 1076 | } xbar_input_signal_t; | ||
| 1077 | |||
| 1078 | typedef enum _xbar_output_signal | ||
| 1079 | { | ||
| 1080 | kXBARA1_OutputDmaChMuxReq30 = 0|0x100U, /**< XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */ | ||
| 1081 | kXBARA1_OutputDmaChMuxReq31 = 1|0x100U, /**< XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */ | ||
| 1082 | kXBARA1_OutputDmaChMuxReq94 = 2|0x100U, /**< XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */ | ||
| 1083 | kXBARA1_OutputDmaChMuxReq95 = 3|0x100U, /**< XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */ | ||
| 1084 | kXBARA1_OutputIomuxXbarInout04 = 4|0x100U, /**< XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */ | ||
| 1085 | kXBARA1_OutputIomuxXbarInout05 = 5|0x100U, /**< XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */ | ||
| 1086 | kXBARA1_OutputIomuxXbarInout06 = 6|0x100U, /**< XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */ | ||
| 1087 | kXBARA1_OutputIomuxXbarInout07 = 7|0x100U, /**< XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */ | ||
| 1088 | kXBARA1_OutputIomuxXbarInout08 = 8|0x100U, /**< XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */ | ||
| 1089 | kXBARA1_OutputIomuxXbarInout09 = 9|0x100U, /**< XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */ | ||
| 1090 | kXBARA1_OutputIomuxXbarInout10 = 10|0x100U, /**< XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */ | ||
| 1091 | kXBARA1_OutputIomuxXbarInout11 = 11|0x100U, /**< XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */ | ||
| 1092 | kXBARA1_OutputIomuxXbarInout12 = 12|0x100U, /**< XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */ | ||
| 1093 | kXBARA1_OutputIomuxXbarInout13 = 13|0x100U, /**< XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */ | ||
| 1094 | kXBARA1_OutputIomuxXbarInout14 = 14|0x100U, /**< XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */ | ||
| 1095 | kXBARA1_OutputIomuxXbarInout15 = 15|0x100U, /**< XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */ | ||
| 1096 | kXBARA1_OutputIomuxXbarInout16 = 16|0x100U, /**< XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */ | ||
| 1097 | kXBARA1_OutputIomuxXbarInout17 = 17|0x100U, /**< XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */ | ||
| 1098 | kXBARA1_OutputIomuxXbarInout18 = 18|0x100U, /**< XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */ | ||
| 1099 | kXBARA1_OutputIomuxXbarInout19 = 19|0x100U, /**< XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */ | ||
| 1100 | kXBARA1_OutputAcmp1Sample = 20|0x100U, /**< XBARA1_OUT20 output assigned to ACMP1_SAMPLE */ | ||
| 1101 | kXBARA1_OutputAcmp2Sample = 21|0x100U, /**< XBARA1_OUT21 output assigned to ACMP2_SAMPLE */ | ||
| 1102 | kXBARA1_OutputAcmp3Sample = 22|0x100U, /**< XBARA1_OUT22 output assigned to ACMP3_SAMPLE */ | ||
| 1103 | kXBARA1_OutputAcmp4Sample = 23|0x100U, /**< XBARA1_OUT23 output assigned to ACMP4_SAMPLE */ | ||
| 1104 | kXBARA1_OutputRESERVED24 = 24|0x100U, /**< XBARA1_OUT24 output is reserved. */ | ||
| 1105 | kXBARA1_OutputRESERVED25 = 25|0x100U, /**< XBARA1_OUT25 output is reserved. */ | ||
| 1106 | kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U, /**< XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */ | ||
| 1107 | kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U, /**< XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */ | ||
| 1108 | kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U, /**< XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */ | ||
| 1109 | kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U, /**< XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */ | ||
| 1110 | kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U, /**< XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */ | ||
| 1111 | kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U, /**< XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */ | ||
| 1112 | kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U, /**< XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */ | ||
| 1113 | kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U, /**< XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */ | ||
| 1114 | kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U, /**< XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */ | ||
| 1115 | kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U, /**< XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */ | ||
| 1116 | kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U, /**< XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */ | ||
| 1117 | kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U, /**< XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */ | ||
| 1118 | kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U, /**< XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */ | ||
| 1119 | kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U, /**< XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */ | ||
| 1120 | kXBARA1_OutputFlexpwm234Exta0 = 40|0x100U, /**< XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */ | ||
| 1121 | kXBARA1_OutputFlexpwm234Exta1 = 41|0x100U, /**< XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */ | ||
| 1122 | kXBARA1_OutputFlexpwm234Exta2 = 42|0x100U, /**< XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */ | ||
| 1123 | kXBARA1_OutputFlexpwm234Exta3 = 43|0x100U, /**< XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */ | ||
| 1124 | kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U, /**< XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */ | ||
| 1125 | kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U, /**< XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */ | ||
| 1126 | kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U, /**< XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */ | ||
| 1127 | kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U, /**< XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */ | ||
| 1128 | kXBARA1_OutputFlexpwm234ExtClk = 48|0x100U, /**< XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */ | ||
| 1129 | kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U, /**< XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */ | ||
| 1130 | kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U, /**< XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */ | ||
| 1131 | kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U, /**< XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */ | ||
| 1132 | kXBARA1_OutputFlexpwm3ExtSync0 = 52|0x100U, /**< XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */ | ||
| 1133 | kXBARA1_OutputFlexpwm3ExtSync1 = 53|0x100U, /**< XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */ | ||
| 1134 | kXBARA1_OutputFlexpwm3ExtSync2 = 54|0x100U, /**< XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */ | ||
| 1135 | kXBARA1_OutputFlexpwm3ExtSync3 = 55|0x100U, /**< XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */ | ||
| 1136 | kXBARA1_OutputFlexpwm3Fault0 = 56|0x100U, /**< XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */ | ||
| 1137 | kXBARA1_OutputFlexpwm3Fault1 = 57|0x100U, /**< XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */ | ||
| 1138 | kXBARA1_OutputFlexpwm3ExtForce = 58|0x100U, /**< XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */ | ||
| 1139 | kXBARA1_OutputFlexpwm4ExtSync0 = 59|0x100U, /**< XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */ | ||
| 1140 | kXBARA1_OutputFlexpwm4ExtSync1 = 60|0x100U, /**< XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */ | ||
| 1141 | kXBARA1_OutputFlexpwm4ExtSync2 = 61|0x100U, /**< XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */ | ||
| 1142 | kXBARA1_OutputFlexpwm4ExtSync3 = 62|0x100U, /**< XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */ | ||
| 1143 | kXBARA1_OutputFlexpwm4Fault0 = 63|0x100U, /**< XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */ | ||
| 1144 | kXBARA1_OutputFlexpwm4Fault1 = 64|0x100U, /**< XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */ | ||
| 1145 | kXBARA1_OutputFlexpwm4ExtForce = 65|0x100U, /**< XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */ | ||
| 1146 | kXBARA1_OutputEnc1PhaseAInput = 66|0x100U, /**< XBARA1_OUT66 output assigned to ENC1_PHASE_A_INPUT */ | ||
| 1147 | kXBARA1_OutputEnc1PhaseBInput = 67|0x100U, /**< XBARA1_OUT67 output assigned to ENC1_PHASE_B_INPUT */ | ||
| 1148 | kXBARA1_OutputEnc1Index = 68|0x100U, /**< XBARA1_OUT68 output assigned to ENC1_INDEX */ | ||
| 1149 | kXBARA1_OutputEnc1Home = 69|0x100U, /**< XBARA1_OUT69 output assigned to ENC1_HOME */ | ||
| 1150 | kXBARA1_OutputEnc1Trigger = 70|0x100U, /**< XBARA1_OUT70 output assigned to ENC1_TRIGGER */ | ||
| 1151 | kXBARA1_OutputEnc2PhaseAInput = 71|0x100U, /**< XBARA1_OUT71 output assigned to ENC2_PHASE_A_INPUT */ | ||
| 1152 | kXBARA1_OutputEnc2PhaseBInput = 72|0x100U, /**< XBARA1_OUT72 output assigned to ENC2_PHASE_B_INPUT */ | ||
| 1153 | kXBARA1_OutputEnc2Index = 73|0x100U, /**< XBARA1_OUT73 output assigned to ENC2_INDEX */ | ||
| 1154 | kXBARA1_OutputEnc2Home = 74|0x100U, /**< XBARA1_OUT74 output assigned to ENC2_HOME */ | ||
| 1155 | kXBARA1_OutputEnc2Trigger = 75|0x100U, /**< XBARA1_OUT75 output assigned to ENC2_TRIGGER */ | ||
| 1156 | kXBARA1_OutputEnc3PhaseAInput = 76|0x100U, /**< XBARA1_OUT76 output assigned to ENC3_PHASE_A_INPUT */ | ||
| 1157 | kXBARA1_OutputEnc3PhaseBInput = 77|0x100U, /**< XBARA1_OUT77 output assigned to ENC3_PHASE_B_INPUT */ | ||
| 1158 | kXBARA1_OutputEnc3Index = 78|0x100U, /**< XBARA1_OUT78 output assigned to ENC3_INDEX */ | ||
| 1159 | kXBARA1_OutputEnc3Home = 79|0x100U, /**< XBARA1_OUT79 output assigned to ENC3_HOME */ | ||
| 1160 | kXBARA1_OutputEnc3Trigger = 80|0x100U, /**< XBARA1_OUT80 output assigned to ENC3_TRIGGER */ | ||
| 1161 | kXBARA1_OutputEnc4PhaseAInput = 81|0x100U, /**< XBARA1_OUT81 output assigned to ENC4_PHASE_A_INPUT */ | ||
| 1162 | kXBARA1_OutputEnc4PhaseBInput = 82|0x100U, /**< XBARA1_OUT82 output assigned to ENC4_PHASE_B_INPUT */ | ||
| 1163 | kXBARA1_OutputEnc4Index = 83|0x100U, /**< XBARA1_OUT83 output assigned to ENC4_INDEX */ | ||
| 1164 | kXBARA1_OutputEnc4Home = 84|0x100U, /**< XBARA1_OUT84 output assigned to ENC4_HOME */ | ||
| 1165 | kXBARA1_OutputEnc4Trigger = 85|0x100U, /**< XBARA1_OUT85 output assigned to ENC4_TRIGGER */ | ||
| 1166 | kXBARA1_OutputQtimer1Tmr0Input = 86|0x100U, /**< XBARA1_OUT86 output assigned to QTIMER1_TMR0_INPUT */ | ||
| 1167 | kXBARA1_OutputQtimer1Tmr1Input = 87|0x100U, /**< XBARA1_OUT87 output assigned to QTIMER1_TMR1_INPUT */ | ||
| 1168 | kXBARA1_OutputQtimer1Tmr2Input = 88|0x100U, /**< XBARA1_OUT88 output assigned to QTIMER1_TMR2_INPUT */ | ||
| 1169 | kXBARA1_OutputQtimer1Tmr3Input = 89|0x100U, /**< XBARA1_OUT89 output assigned to QTIMER1_TMR3_INPUT */ | ||
| 1170 | kXBARA1_OutputQtimer2Tmr0Input = 90|0x100U, /**< XBARA1_OUT90 output assigned to QTIMER2_TMR0_INPUT */ | ||
| 1171 | kXBARA1_OutputQtimer2Tmr1Input = 91|0x100U, /**< XBARA1_OUT91 output assigned to QTIMER2_TMR1_INPUT */ | ||
| 1172 | kXBARA1_OutputQtimer2Tmr2Input = 92|0x100U, /**< XBARA1_OUT92 output assigned to QTIMER2_TMR2_INPUT */ | ||
| 1173 | kXBARA1_OutputQtimer2Tmr3Input = 93|0x100U, /**< XBARA1_OUT93 output assigned to QTIMER2_TMR3_INPUT */ | ||
| 1174 | kXBARA1_OutputQtimer3Tmr0Input = 94|0x100U, /**< XBARA1_OUT94 output assigned to QTIMER3_TMR0_INPUT */ | ||
| 1175 | kXBARA1_OutputQtimer3Tmr1Input = 95|0x100U, /**< XBARA1_OUT95 output assigned to QTIMER3_TMR1_INPUT */ | ||
| 1176 | kXBARA1_OutputQtimer3Tmr2Input = 96|0x100U, /**< XBARA1_OUT96 output assigned to QTIMER3_TMR2_INPUT */ | ||
| 1177 | kXBARA1_OutputQtimer3Tmr3Input = 97|0x100U, /**< XBARA1_OUT97 output assigned to QTIMER3_TMR3_INPUT */ | ||
| 1178 | kXBARA1_OutputQtimer4Tmr0Input = 98|0x100U, /**< XBARA1_OUT98 output assigned to QTIMER4_TMR0_INPUT */ | ||
| 1179 | kXBARA1_OutputQtimer4Tmr1Input = 99|0x100U, /**< XBARA1_OUT99 output assigned to QTIMER4_TMR1_INPUT */ | ||
| 1180 | kXBARA1_OutputQtimer4Tmr2Input = 100|0x100U, /**< XBARA1_OUT100 output assigned to QTIMER4_TMR2_INPUT */ | ||
| 1181 | kXBARA1_OutputQtimer4Tmr3Input = 101|0x100U, /**< XBARA1_OUT101 output assigned to QTIMER4_TMR3_INPUT */ | ||
| 1182 | kXBARA1_OutputEwmEwmIn = 102|0x100U, /**< XBARA1_OUT102 output assigned to EWM_EWM_IN */ | ||
| 1183 | kXBARA1_OutputAdcEtcXbar0Trig0 = 103|0x100U, /**< XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */ | ||
| 1184 | kXBARA1_OutputAdcEtcXbar0Trig1 = 104|0x100U, /**< XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */ | ||
| 1185 | kXBARA1_OutputAdcEtcXbar0Trig2 = 105|0x100U, /**< XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */ | ||
| 1186 | kXBARA1_OutputAdcEtcXbar0Trig3 = 106|0x100U, /**< XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */ | ||
| 1187 | kXBARA1_OutputAdcEtcXbar1Trig0 = 107|0x100U, /**< XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */ | ||
| 1188 | kXBARA1_OutputAdcEtcXbar1Trig1 = 108|0x100U, /**< XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */ | ||
| 1189 | kXBARA1_OutputAdcEtcXbar1Trig2 = 109|0x100U, /**< XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */ | ||
| 1190 | kXBARA1_OutputAdcEtcXbar1Trig3 = 110|0x100U, /**< XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */ | ||
| 1191 | kXBARA1_OutputLpi2c1TrgInput = 111|0x100U, /**< XBARA1_OUT111 output assigned to LPI2C1_TRG_INPUT */ | ||
| 1192 | kXBARA1_OutputLpi2c2TrgInput = 112|0x100U, /**< XBARA1_OUT112 output assigned to LPI2C2_TRG_INPUT */ | ||
| 1193 | kXBARA1_OutputLpi2c3TrgInput = 113|0x100U, /**< XBARA1_OUT113 output assigned to LPI2C3_TRG_INPUT */ | ||
| 1194 | kXBARA1_OutputLpi2c4TrgInput = 114|0x100U, /**< XBARA1_OUT114 output assigned to LPI2C4_TRG_INPUT */ | ||
| 1195 | kXBARA1_OutputLpspi1TrgInput = 115|0x100U, /**< XBARA1_OUT115 output assigned to LPSPI1_TRG_INPUT */ | ||
| 1196 | kXBARA1_OutputLpspi2TrgInput = 116|0x100U, /**< XBARA1_OUT116 output assigned to LPSPI2_TRG_INPUT */ | ||
| 1197 | kXBARA1_OutputLpspi3TrgInput = 117|0x100U, /**< XBARA1_OUT117 output assigned to LPSPI3_TRG_INPUT */ | ||
| 1198 | kXBARA1_OutputLpspi4TrgInput = 118|0x100U, /**< XBARA1_OUT118 output assigned to LPSPI4_TRG_INPUT */ | ||
| 1199 | kXBARA1_OutputLpuart1TrgInput = 119|0x100U, /**< XBARA1_OUT119 output assigned to LPUART1_TRG_INPUT */ | ||
| 1200 | kXBARA1_OutputLpuart2TrgInput = 120|0x100U, /**< XBARA1_OUT120 output assigned to LPUART2_TRG_INPUT */ | ||
| 1201 | kXBARA1_OutputLpuart3TrgInput = 121|0x100U, /**< XBARA1_OUT121 output assigned to LPUART3_TRG_INPUT */ | ||
| 1202 | kXBARA1_OutputLpuart4TrgInput = 122|0x100U, /**< XBARA1_OUT122 output assigned to LPUART4_TRG_INPUT */ | ||
| 1203 | kXBARA1_OutputLpuart5TrgInput = 123|0x100U, /**< XBARA1_OUT123 output assigned to LPUART5_TRG_INPUT */ | ||
| 1204 | kXBARA1_OutputLpuart6TrgInput = 124|0x100U, /**< XBARA1_OUT124 output assigned to LPUART6_TRG_INPUT */ | ||
| 1205 | kXBARA1_OutputLpuart7TrgInput = 125|0x100U, /**< XBARA1_OUT125 output assigned to LPUART7_TRG_INPUT */ | ||
| 1206 | kXBARA1_OutputLpuart8TrgInput = 126|0x100U, /**< XBARA1_OUT126 output assigned to LPUART8_TRG_INPUT */ | ||
| 1207 | kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U, /**< XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */ | ||
| 1208 | kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U, /**< XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */ | ||
| 1209 | kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U, /**< XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */ | ||
| 1210 | kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U, /**< XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */ | ||
| 1211 | kXBARB2_OutputAoi1In00 = 0|0x200U, /**< XBARB2_OUT0 output assigned to AOI1_IN00 */ | ||
| 1212 | kXBARB2_OutputAoi1In01 = 1|0x200U, /**< XBARB2_OUT1 output assigned to AOI1_IN01 */ | ||
| 1213 | kXBARB2_OutputAoi1In02 = 2|0x200U, /**< XBARB2_OUT2 output assigned to AOI1_IN02 */ | ||
| 1214 | kXBARB2_OutputAoi1In03 = 3|0x200U, /**< XBARB2_OUT3 output assigned to AOI1_IN03 */ | ||
| 1215 | kXBARB2_OutputAoi1In04 = 4|0x200U, /**< XBARB2_OUT4 output assigned to AOI1_IN04 */ | ||
| 1216 | kXBARB2_OutputAoi1In05 = 5|0x200U, /**< XBARB2_OUT5 output assigned to AOI1_IN05 */ | ||
| 1217 | kXBARB2_OutputAoi1In06 = 6|0x200U, /**< XBARB2_OUT6 output assigned to AOI1_IN06 */ | ||
| 1218 | kXBARB2_OutputAoi1In07 = 7|0x200U, /**< XBARB2_OUT7 output assigned to AOI1_IN07 */ | ||
| 1219 | kXBARB2_OutputAoi1In08 = 8|0x200U, /**< XBARB2_OUT8 output assigned to AOI1_IN08 */ | ||
| 1220 | kXBARB2_OutputAoi1In09 = 9|0x200U, /**< XBARB2_OUT9 output assigned to AOI1_IN09 */ | ||
| 1221 | kXBARB2_OutputAoi1In10 = 10|0x200U, /**< XBARB2_OUT10 output assigned to AOI1_IN10 */ | ||
| 1222 | kXBARB2_OutputAoi1In11 = 11|0x200U, /**< XBARB2_OUT11 output assigned to AOI1_IN11 */ | ||
| 1223 | kXBARB2_OutputAoi1In12 = 12|0x200U, /**< XBARB2_OUT12 output assigned to AOI1_IN12 */ | ||
| 1224 | kXBARB2_OutputAoi1In13 = 13|0x200U, /**< XBARB2_OUT13 output assigned to AOI1_IN13 */ | ||
| 1225 | kXBARB2_OutputAoi1In14 = 14|0x200U, /**< XBARB2_OUT14 output assigned to AOI1_IN14 */ | ||
| 1226 | kXBARB2_OutputAoi1In15 = 15|0x200U, /**< XBARB2_OUT15 output assigned to AOI1_IN15 */ | ||
| 1227 | kXBARB3_OutputAoi2In00 = 0|0x300U, /**< XBARB3_OUT0 output assigned to AOI2_IN00 */ | ||
| 1228 | kXBARB3_OutputAoi2In01 = 1|0x300U, /**< XBARB3_OUT1 output assigned to AOI2_IN01 */ | ||
| 1229 | kXBARB3_OutputAoi2In02 = 2|0x300U, /**< XBARB3_OUT2 output assigned to AOI2_IN02 */ | ||
| 1230 | kXBARB3_OutputAoi2In03 = 3|0x300U, /**< XBARB3_OUT3 output assigned to AOI2_IN03 */ | ||
| 1231 | kXBARB3_OutputAoi2In04 = 4|0x300U, /**< XBARB3_OUT4 output assigned to AOI2_IN04 */ | ||
| 1232 | kXBARB3_OutputAoi2In05 = 5|0x300U, /**< XBARB3_OUT5 output assigned to AOI2_IN05 */ | ||
| 1233 | kXBARB3_OutputAoi2In06 = 6|0x300U, /**< XBARB3_OUT6 output assigned to AOI2_IN06 */ | ||
| 1234 | kXBARB3_OutputAoi2In07 = 7|0x300U, /**< XBARB3_OUT7 output assigned to AOI2_IN07 */ | ||
| 1235 | kXBARB3_OutputAoi2In08 = 8|0x300U, /**< XBARB3_OUT8 output assigned to AOI2_IN08 */ | ||
| 1236 | kXBARB3_OutputAoi2In09 = 9|0x300U, /**< XBARB3_OUT9 output assigned to AOI2_IN09 */ | ||
| 1237 | kXBARB3_OutputAoi2In10 = 10|0x300U, /**< XBARB3_OUT10 output assigned to AOI2_IN10 */ | ||
| 1238 | kXBARB3_OutputAoi2In11 = 11|0x300U, /**< XBARB3_OUT11 output assigned to AOI2_IN11 */ | ||
| 1239 | kXBARB3_OutputAoi2In12 = 12|0x300U, /**< XBARB3_OUT12 output assigned to AOI2_IN12 */ | ||
| 1240 | kXBARB3_OutputAoi2In13 = 13|0x300U, /**< XBARB3_OUT13 output assigned to AOI2_IN13 */ | ||
| 1241 | kXBARB3_OutputAoi2In14 = 14|0x300U, /**< XBARB3_OUT14 output assigned to AOI2_IN14 */ | ||
| 1242 | kXBARB3_OutputAoi2In15 = 15|0x300U, /**< XBARB3_OUT15 output assigned to AOI2_IN15 */ | ||
| 1243 | } xbar_output_signal_t; | ||
| 1244 | |||
| 1245 | |||
| 1246 | /*! | ||
| 1247 | * @} | ||
| 1248 | */ /* end of group Mapping_Information */ | ||
| 1249 | |||
| 1250 | |||
| 1251 | /* ---------------------------------------------------------------------------- | ||
| 1252 | -- Device Peripheral Access Layer | ||
| 1253 | ---------------------------------------------------------------------------- */ | ||
| 1254 | |||
| 1255 | /*! | ||
| 1256 | * @addtogroup Peripheral_access_layer Device Peripheral Access Layer | ||
| 1257 | * @{ | ||
| 1258 | */ | ||
| 1259 | |||
| 1260 | |||
| 1261 | /* | ||
| 1262 | ** Start of section using anonymous unions | ||
| 1263 | */ | ||
| 1264 | |||
| 1265 | #if defined(__ARMCC_VERSION) | ||
| 1266 | #if (__ARMCC_VERSION >= 6010050) | ||
| 1267 | #pragma clang diagnostic push | ||
| 1268 | #else | ||
| 1269 | #pragma push | ||
| 1270 | #pragma anon_unions | ||
| 1271 | #endif | ||
| 1272 | #elif defined(__CWCC__) | ||
| 1273 | #pragma push | ||
| 1274 | #pragma cpp_extensions on | ||
| 1275 | #elif defined(__GNUC__) | ||
| 1276 | /* anonymous unions are enabled by default */ | ||
| 1277 | #elif defined(__IAR_SYSTEMS_ICC__) | ||
| 1278 | #pragma language=extended | ||
| 1279 | #else | ||
| 1280 | #error Not supported compiler type | ||
| 1281 | #endif | ||
| 1282 | |||
| 1283 | /* ---------------------------------------------------------------------------- | ||
| 1284 | -- ADC Peripheral Access Layer | ||
| 1285 | ---------------------------------------------------------------------------- */ | ||
| 1286 | |||
| 1287 | /*! | ||
| 1288 | * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer | ||
| 1289 | * @{ | ||
| 1290 | */ | ||
| 1291 | |||
| 1292 | /** ADC - Register Layout Typedef */ | ||
| 1293 | typedef struct { | ||
| 1294 | __IO uint32_t HC[8]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */ | ||
| 1295 | __I uint32_t HS; /**< Status register for HW triggers, offset: 0x20 */ | ||
| 1296 | __I uint32_t R[8]; /**< Data result register for HW triggers, array offset: 0x24, array step: 0x4 */ | ||
| 1297 | __IO uint32_t CFG; /**< Configuration register, offset: 0x44 */ | ||
| 1298 | __IO uint32_t GC; /**< General control register, offset: 0x48 */ | ||
| 1299 | __IO uint32_t GS; /**< General status register, offset: 0x4C */ | ||
| 1300 | __IO uint32_t CV; /**< Compare value register, offset: 0x50 */ | ||
| 1301 | __IO uint32_t OFS; /**< Offset correction value register, offset: 0x54 */ | ||
| 1302 | __IO uint32_t CAL; /**< Calibration value register, offset: 0x58 */ | ||
| 1303 | } ADC_Type; | ||
| 1304 | |||
| 1305 | /* ---------------------------------------------------------------------------- | ||
| 1306 | -- ADC Register Masks | ||
| 1307 | ---------------------------------------------------------------------------- */ | ||
| 1308 | |||
| 1309 | /*! | ||
| 1310 | * @addtogroup ADC_Register_Masks ADC Register Masks | ||
| 1311 | * @{ | ||
| 1312 | */ | ||
| 1313 | |||
| 1314 | /*! @name HC - Control register for hardware triggers */ | ||
| 1315 | /*! @{ */ | ||
| 1316 | #define ADC_HC_ADCH_MASK (0x1FU) | ||
| 1317 | #define ADC_HC_ADCH_SHIFT (0U) | ||
| 1318 | /*! ADCH - Input Channel Select | ||
| 1319 | * 0b10000..External channel selection from ADC_ETC | ||
| 1320 | * 0b11000..Reserved. | ||
| 1321 | * 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally | ||
| 1322 | * 0b11010..Reserved. | ||
| 1323 | * 0b11011..Reserved. | ||
| 1324 | * 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion. | ||
| 1325 | */ | ||
| 1326 | #define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) | ||
| 1327 | #define ADC_HC_AIEN_MASK (0x80U) | ||
| 1328 | #define ADC_HC_AIEN_SHIFT (7U) | ||
| 1329 | /*! AIEN - Conversion Complete Interrupt Enable/Disable Control | ||
| 1330 | * 0b1..Conversion complete interrupt enabled | ||
| 1331 | * 0b0..Conversion complete interrupt disabled | ||
| 1332 | */ | ||
| 1333 | #define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK) | ||
| 1334 | /*! @} */ | ||
| 1335 | |||
| 1336 | /* The count of ADC_HC */ | ||
| 1337 | #define ADC_HC_COUNT (8U) | ||
| 1338 | |||
| 1339 | /*! @name HS - Status register for HW triggers */ | ||
| 1340 | /*! @{ */ | ||
| 1341 | #define ADC_HS_COCO0_MASK (0x1U) | ||
| 1342 | #define ADC_HS_COCO0_SHIFT (0U) | ||
| 1343 | /*! COCO0 - Conversion Complete Flag | ||
| 1344 | */ | ||
| 1345 | #define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK) | ||
| 1346 | /*! @} */ | ||
| 1347 | |||
| 1348 | /*! @name R - Data result register for HW triggers */ | ||
| 1349 | /*! @{ */ | ||
| 1350 | #define ADC_R_CDATA_MASK (0xFFFU) | ||
| 1351 | #define ADC_R_CDATA_SHIFT (0U) | ||
| 1352 | /*! CDATA - Data (result of an ADC conversion) | ||
| 1353 | */ | ||
| 1354 | #define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK) | ||
| 1355 | /*! @} */ | ||
| 1356 | |||
| 1357 | /* The count of ADC_R */ | ||
| 1358 | #define ADC_R_COUNT (8U) | ||
| 1359 | |||
| 1360 | /*! @name CFG - Configuration register */ | ||
| 1361 | /*! @{ */ | ||
| 1362 | #define ADC_CFG_ADICLK_MASK (0x3U) | ||
| 1363 | #define ADC_CFG_ADICLK_SHIFT (0U) | ||
| 1364 | /*! ADICLK - Input Clock Select | ||
| 1365 | * 0b00..IPG clock | ||
| 1366 | * 0b01..IPG clock divided by 2 | ||
| 1367 | * 0b10..Reserved | ||
| 1368 | * 0b11..Asynchronous clock (ADACK) | ||
| 1369 | */ | ||
| 1370 | #define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) | ||
| 1371 | #define ADC_CFG_MODE_MASK (0xCU) | ||
| 1372 | #define ADC_CFG_MODE_SHIFT (2U) | ||
| 1373 | /*! MODE - Conversion Mode Selection | ||
| 1374 | * 0b00..8-bit conversion | ||
| 1375 | * 0b01..10-bit conversion | ||
| 1376 | * 0b10..12-bit conversion | ||
| 1377 | * 0b11..Reserved | ||
| 1378 | */ | ||
| 1379 | #define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) | ||
| 1380 | #define ADC_CFG_ADLSMP_MASK (0x10U) | ||
| 1381 | #define ADC_CFG_ADLSMP_SHIFT (4U) | ||
| 1382 | /*! ADLSMP - Long Sample Time Configuration | ||
| 1383 | * 0b0..Short sample mode. | ||
| 1384 | * 0b1..Long sample mode. | ||
| 1385 | */ | ||
| 1386 | #define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) | ||
| 1387 | #define ADC_CFG_ADIV_MASK (0x60U) | ||
| 1388 | #define ADC_CFG_ADIV_SHIFT (5U) | ||
| 1389 | /*! ADIV - Clock Divide Select | ||
| 1390 | * 0b00..Input clock | ||
| 1391 | * 0b01..Input clock / 2 | ||
| 1392 | * 0b10..Input clock / 4 | ||
| 1393 | * 0b11..Input clock / 8 | ||
| 1394 | */ | ||
| 1395 | #define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) | ||
| 1396 | #define ADC_CFG_ADLPC_MASK (0x80U) | ||
| 1397 | #define ADC_CFG_ADLPC_SHIFT (7U) | ||
| 1398 | /*! ADLPC - Low-Power Configuration | ||
| 1399 | * 0b0..ADC hard block not in low power mode. | ||
| 1400 | * 0b1..ADC hard block in low power mode. | ||
| 1401 | */ | ||
| 1402 | #define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) | ||
| 1403 | #define ADC_CFG_ADSTS_MASK (0x300U) | ||
| 1404 | #define ADC_CFG_ADSTS_SHIFT (8U) | ||
| 1405 | /*! ADSTS | ||
| 1406 | * 0b00..Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b | ||
| 1407 | * 0b01..Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b | ||
| 1408 | * 0b10..Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b | ||
| 1409 | * 0b11..Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b | ||
| 1410 | */ | ||
| 1411 | #define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) | ||
| 1412 | #define ADC_CFG_ADHSC_MASK (0x400U) | ||
| 1413 | #define ADC_CFG_ADHSC_SHIFT (10U) | ||
| 1414 | /*! ADHSC - High Speed Configuration | ||
| 1415 | * 0b0..Normal conversion selected. | ||
| 1416 | * 0b1..High speed conversion selected. | ||
| 1417 | */ | ||
| 1418 | #define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) | ||
| 1419 | #define ADC_CFG_REFSEL_MASK (0x1800U) | ||
| 1420 | #define ADC_CFG_REFSEL_SHIFT (11U) | ||
| 1421 | /*! REFSEL - Voltage Reference Selection | ||
| 1422 | * 0b00..Selects VREFH/VREFL as reference voltage. | ||
| 1423 | * 0b01..Reserved | ||
| 1424 | * 0b10..Reserved | ||
| 1425 | * 0b11..Reserved | ||
| 1426 | */ | ||
| 1427 | #define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) | ||
| 1428 | #define ADC_CFG_ADTRG_MASK (0x2000U) | ||
| 1429 | #define ADC_CFG_ADTRG_SHIFT (13U) | ||
| 1430 | /*! ADTRG - Conversion Trigger Select | ||
| 1431 | * 0b0..Software trigger selected | ||
| 1432 | * 0b1..Hardware trigger selected | ||
| 1433 | */ | ||
| 1434 | #define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) | ||
| 1435 | #define ADC_CFG_AVGS_MASK (0xC000U) | ||
| 1436 | #define ADC_CFG_AVGS_SHIFT (14U) | ||
| 1437 | /*! AVGS - Hardware Average select | ||
| 1438 | * 0b00..4 samples averaged | ||
| 1439 | * 0b01..8 samples averaged | ||
| 1440 | * 0b10..16 samples averaged | ||
| 1441 | * 0b11..32 samples averaged | ||
| 1442 | */ | ||
| 1443 | #define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) | ||
| 1444 | #define ADC_CFG_OVWREN_MASK (0x10000U) | ||
| 1445 | #define ADC_CFG_OVWREN_SHIFT (16U) | ||
| 1446 | /*! OVWREN - Data Overwrite Enable | ||
| 1447 | * 0b1..Enable the overwriting. | ||
| 1448 | * 0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data. | ||
| 1449 | */ | ||
| 1450 | #define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) | ||
| 1451 | /*! @} */ | ||
| 1452 | |||
| 1453 | /*! @name GC - General control register */ | ||
| 1454 | /*! @{ */ | ||
| 1455 | #define ADC_GC_ADACKEN_MASK (0x1U) | ||
| 1456 | #define ADC_GC_ADACKEN_SHIFT (0U) | ||
| 1457 | /*! ADACKEN - Asynchronous clock output enable | ||
| 1458 | * 0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. | ||
| 1459 | * 0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC | ||
| 1460 | */ | ||
| 1461 | #define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) | ||
| 1462 | #define ADC_GC_DMAEN_MASK (0x2U) | ||
| 1463 | #define ADC_GC_DMAEN_SHIFT (1U) | ||
| 1464 | /*! DMAEN - DMA Enable | ||
| 1465 | * 0b0..DMA disabled (default) | ||
| 1466 | * 0b1..DMA enabled | ||
| 1467 | */ | ||
| 1468 | #define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) | ||
| 1469 | #define ADC_GC_ACREN_MASK (0x4U) | ||
| 1470 | #define ADC_GC_ACREN_SHIFT (2U) | ||
| 1471 | /*! ACREN - Compare Function Range Enable | ||
| 1472 | * 0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. | ||
| 1473 | * 0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared. | ||
| 1474 | */ | ||
| 1475 | #define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) | ||
| 1476 | #define ADC_GC_ACFGT_MASK (0x8U) | ||
| 1477 | #define ADC_GC_ACFGT_SHIFT (3U) | ||
| 1478 | /*! ACFGT - Compare Function Greater Than Enable | ||
| 1479 | * 0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" | ||
| 1480 | * functionality based on the values placed in the ADC_CV register. | ||
| 1481 | * 0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" | ||
| 1482 | * functionality based on the values placed in the ADC_CV registers. | ||
| 1483 | */ | ||
| 1484 | #define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) | ||
| 1485 | #define ADC_GC_ACFE_MASK (0x10U) | ||
| 1486 | #define ADC_GC_ACFE_SHIFT (4U) | ||
| 1487 | /*! ACFE - Compare Function Enable | ||
| 1488 | * 0b0..Compare function disabled | ||
| 1489 | * 0b1..Compare function enabled | ||
| 1490 | */ | ||
| 1491 | #define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) | ||
| 1492 | #define ADC_GC_AVGE_MASK (0x20U) | ||
| 1493 | #define ADC_GC_AVGE_SHIFT (5U) | ||
| 1494 | /*! AVGE - Hardware average enable | ||
| 1495 | * 0b0..Hardware average function disabled | ||
| 1496 | * 0b1..Hardware average function enabled | ||
| 1497 | */ | ||
| 1498 | #define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) | ||
| 1499 | #define ADC_GC_ADCO_MASK (0x40U) | ||
| 1500 | #define ADC_GC_ADCO_SHIFT (6U) | ||
| 1501 | /*! ADCO - Continuous Conversion Enable | ||
| 1502 | * 0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. | ||
| 1503 | * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. | ||
| 1504 | */ | ||
| 1505 | #define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) | ||
| 1506 | #define ADC_GC_CAL_MASK (0x80U) | ||
| 1507 | #define ADC_GC_CAL_SHIFT (7U) | ||
| 1508 | /*! CAL - Calibration | ||
| 1509 | */ | ||
| 1510 | #define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) | ||
| 1511 | /*! @} */ | ||
| 1512 | |||
| 1513 | /*! @name GS - General status register */ | ||
| 1514 | /*! @{ */ | ||
| 1515 | #define ADC_GS_ADACT_MASK (0x1U) | ||
| 1516 | #define ADC_GS_ADACT_SHIFT (0U) | ||
| 1517 | /*! ADACT - Conversion Active | ||
| 1518 | * 0b0..Conversion not in progress. | ||
| 1519 | * 0b1..Conversion in progress. | ||
| 1520 | */ | ||
| 1521 | #define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) | ||
| 1522 | #define ADC_GS_CALF_MASK (0x2U) | ||
| 1523 | #define ADC_GS_CALF_SHIFT (1U) | ||
| 1524 | /*! CALF - Calibration Failed Flag | ||
| 1525 | * 0b0..Calibration completed normally. | ||
| 1526 | * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed. | ||
| 1527 | */ | ||
| 1528 | #define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) | ||
| 1529 | #define ADC_GS_AWKST_MASK (0x4U) | ||
| 1530 | #define ADC_GS_AWKST_SHIFT (2U) | ||
| 1531 | /*! AWKST - Asynchronous wakeup interrupt status | ||
| 1532 | * 0b1..Asynchronous wake up interrupt occurred in stop mode. | ||
| 1533 | * 0b0..No asynchronous interrupt. | ||
| 1534 | */ | ||
| 1535 | #define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) | ||
| 1536 | /*! @} */ | ||
| 1537 | |||
| 1538 | /*! @name CV - Compare value register */ | ||
| 1539 | /*! @{ */ | ||
| 1540 | #define ADC_CV_CV1_MASK (0xFFFU) | ||
| 1541 | #define ADC_CV_CV1_SHIFT (0U) | ||
| 1542 | /*! CV1 - Compare Value 1 | ||
| 1543 | */ | ||
| 1544 | #define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) | ||
| 1545 | #define ADC_CV_CV2_MASK (0xFFF0000U) | ||
| 1546 | #define ADC_CV_CV2_SHIFT (16U) | ||
| 1547 | /*! CV2 - Compare Value 2 | ||
| 1548 | */ | ||
| 1549 | #define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) | ||
| 1550 | /*! @} */ | ||
| 1551 | |||
| 1552 | /*! @name OFS - Offset correction value register */ | ||
| 1553 | /*! @{ */ | ||
| 1554 | #define ADC_OFS_OFS_MASK (0xFFFU) | ||
| 1555 | #define ADC_OFS_OFS_SHIFT (0U) | ||
| 1556 | /*! OFS - Offset value | ||
| 1557 | */ | ||
| 1558 | #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) | ||
| 1559 | #define ADC_OFS_SIGN_MASK (0x1000U) | ||
| 1560 | #define ADC_OFS_SIGN_SHIFT (12U) | ||
| 1561 | /*! SIGN - Sign bit | ||
| 1562 | * 0b0..The offset value is added with the raw result | ||
| 1563 | * 0b1..The offset value is subtracted from the raw converted value | ||
| 1564 | */ | ||
| 1565 | #define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) | ||
| 1566 | /*! @} */ | ||
| 1567 | |||
| 1568 | /*! @name CAL - Calibration value register */ | ||
| 1569 | /*! @{ */ | ||
| 1570 | #define ADC_CAL_CAL_CODE_MASK (0xFU) | ||
| 1571 | #define ADC_CAL_CAL_CODE_SHIFT (0U) | ||
| 1572 | /*! CAL_CODE - Calibration Result Value | ||
| 1573 | */ | ||
| 1574 | #define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) | ||
| 1575 | /*! @} */ | ||
| 1576 | |||
| 1577 | |||
| 1578 | /*! | ||
| 1579 | * @} | ||
| 1580 | */ /* end of group ADC_Register_Masks */ | ||
| 1581 | |||
| 1582 | |||
| 1583 | /* ADC - Peripheral instance base addresses */ | ||
| 1584 | /** Peripheral ADC1 base address */ | ||
| 1585 | #define ADC1_BASE (0x400C4000u) | ||
| 1586 | /** Peripheral ADC1 base pointer */ | ||
| 1587 | #define ADC1 ((ADC_Type *)ADC1_BASE) | ||
| 1588 | /** Peripheral ADC2 base address */ | ||
| 1589 | #define ADC2_BASE (0x400C8000u) | ||
| 1590 | /** Peripheral ADC2 base pointer */ | ||
| 1591 | #define ADC2 ((ADC_Type *)ADC2_BASE) | ||
| 1592 | /** Array initializer of ADC peripheral base addresses */ | ||
| 1593 | #define ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE } | ||
| 1594 | /** Array initializer of ADC peripheral base pointers */ | ||
| 1595 | #define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 } | ||
| 1596 | /** Interrupt vectors for the ADC peripheral type */ | ||
| 1597 | #define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn } | ||
| 1598 | |||
| 1599 | /*! | ||
| 1600 | * @} | ||
| 1601 | */ /* end of group ADC_Peripheral_Access_Layer */ | ||
| 1602 | |||
| 1603 | |||
| 1604 | /* ---------------------------------------------------------------------------- | ||
| 1605 | -- ADC_ETC Peripheral Access Layer | ||
| 1606 | ---------------------------------------------------------------------------- */ | ||
| 1607 | |||
| 1608 | /*! | ||
| 1609 | * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer | ||
| 1610 | * @{ | ||
| 1611 | */ | ||
| 1612 | |||
| 1613 | /** ADC_ETC - Register Layout Typedef */ | ||
| 1614 | typedef struct { | ||
| 1615 | __IO uint32_t CTRL; /**< ADC_ETC Global Control Register, offset: 0x0 */ | ||
| 1616 | __IO uint32_t DONE0_1_IRQ; /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */ | ||
| 1617 | __IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */ | ||
| 1618 | __IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */ | ||
| 1619 | struct { /* offset: 0x10, array step: 0x28 */ | ||
| 1620 | __IO uint32_t TRIGn_CTRL; /**< ETC_TRIG0 Control Register..ETC_TRIG7 Control Register, array offset: 0x10, array step: 0x28 */ | ||
| 1621 | __IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register, array offset: 0x14, array step: 0x28 */ | ||
| 1622 | __IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */ | ||
| 1623 | __IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */ | ||
| 1624 | __IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */ | ||
| 1625 | __IO uint32_t TRIGn_CHAIN_7_6; /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */ | ||
| 1626 | __I uint32_t TRIGn_RESULT_1_0; /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */ | ||
| 1627 | __I uint32_t TRIGn_RESULT_3_2; /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */ | ||
| 1628 | __I uint32_t TRIGn_RESULT_5_4; /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */ | ||
| 1629 | __I uint32_t TRIGn_RESULT_7_6; /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */ | ||
| 1630 | } TRIG[8]; | ||
| 1631 | } ADC_ETC_Type; | ||
| 1632 | |||
| 1633 | /* ---------------------------------------------------------------------------- | ||
| 1634 | -- ADC_ETC Register Masks | ||
| 1635 | ---------------------------------------------------------------------------- */ | ||
| 1636 | |||
| 1637 | /*! | ||
| 1638 | * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks | ||
| 1639 | * @{ | ||
| 1640 | */ | ||
| 1641 | |||
| 1642 | /*! @name CTRL - ADC_ETC Global Control Register */ | ||
| 1643 | /*! @{ */ | ||
| 1644 | #define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) | ||
| 1645 | #define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) | ||
| 1646 | #define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) | ||
| 1647 | #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U) | ||
| 1648 | #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U) | ||
| 1649 | #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK) | ||
| 1650 | #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U) | ||
| 1651 | #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U) | ||
| 1652 | #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK) | ||
| 1653 | #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U) | ||
| 1654 | #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U) | ||
| 1655 | #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK) | ||
| 1656 | #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U) | ||
| 1657 | #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U) | ||
| 1658 | #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK) | ||
| 1659 | #define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) | ||
| 1660 | #define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) | ||
| 1661 | #define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) | ||
| 1662 | #define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U) | ||
| 1663 | #define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U) | ||
| 1664 | #define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK) | ||
| 1665 | #define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U) | ||
| 1666 | #define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U) | ||
| 1667 | #define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK) | ||
| 1668 | #define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) | ||
| 1669 | #define ADC_ETC_CTRL_SOFTRST_SHIFT (31U) | ||
| 1670 | #define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) | ||
| 1671 | /*! @} */ | ||
| 1672 | |||
| 1673 | /*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */ | ||
| 1674 | /*! @{ */ | ||
| 1675 | #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) | ||
| 1676 | #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) | ||
| 1677 | #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) | ||
| 1678 | #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U) | ||
| 1679 | #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U) | ||
| 1680 | #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK) | ||
| 1681 | #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U) | ||
| 1682 | #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U) | ||
| 1683 | #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK) | ||
| 1684 | #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U) | ||
| 1685 | #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U) | ||
| 1686 | #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK) | ||
| 1687 | #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U) | ||
| 1688 | #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U) | ||
| 1689 | #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK) | ||
| 1690 | #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U) | ||
| 1691 | #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U) | ||
| 1692 | #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK) | ||
| 1693 | #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U) | ||
| 1694 | #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U) | ||
| 1695 | #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK) | ||
| 1696 | #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U) | ||
| 1697 | #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U) | ||
| 1698 | #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK) | ||
| 1699 | #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U) | ||
| 1700 | #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U) | ||
| 1701 | #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK) | ||
| 1702 | #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U) | ||
| 1703 | #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U) | ||
| 1704 | #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK) | ||
| 1705 | #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U) | ||
| 1706 | #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U) | ||
| 1707 | #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK) | ||
| 1708 | #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U) | ||
| 1709 | #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U) | ||
| 1710 | #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK) | ||
| 1711 | #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U) | ||
| 1712 | #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U) | ||
| 1713 | #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK) | ||
| 1714 | #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U) | ||
| 1715 | #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U) | ||
| 1716 | #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK) | ||
| 1717 | #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U) | ||
| 1718 | #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U) | ||
| 1719 | #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK) | ||
| 1720 | #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) | ||
| 1721 | #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) | ||
| 1722 | #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) | ||
| 1723 | /*! @} */ | ||
| 1724 | |||
| 1725 | /*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */ | ||
| 1726 | /*! @{ */ | ||
| 1727 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) | ||
| 1728 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) | ||
| 1729 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK) | ||
| 1730 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U) | ||
| 1731 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U) | ||
| 1732 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK) | ||
| 1733 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U) | ||
| 1734 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U) | ||
| 1735 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK) | ||
| 1736 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U) | ||
| 1737 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U) | ||
| 1738 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK) | ||
| 1739 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U) | ||
| 1740 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U) | ||
| 1741 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK) | ||
| 1742 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U) | ||
| 1743 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U) | ||
| 1744 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK) | ||
| 1745 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U) | ||
| 1746 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U) | ||
| 1747 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK) | ||
| 1748 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U) | ||
| 1749 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U) | ||
| 1750 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK) | ||
| 1751 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U) | ||
| 1752 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U) | ||
| 1753 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK) | ||
| 1754 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U) | ||
| 1755 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U) | ||
| 1756 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK) | ||
| 1757 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U) | ||
| 1758 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U) | ||
| 1759 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK) | ||
| 1760 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U) | ||
| 1761 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U) | ||
| 1762 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK) | ||
| 1763 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U) | ||
| 1764 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U) | ||
| 1765 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK) | ||
| 1766 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U) | ||
| 1767 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U) | ||
| 1768 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK) | ||
| 1769 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U) | ||
| 1770 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U) | ||
| 1771 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK) | ||
| 1772 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) | ||
| 1773 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U) | ||
| 1774 | #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK) | ||
| 1775 | /*! @} */ | ||
| 1776 | |||
| 1777 | /*! @name DMA_CTRL - ETC DMA control Register */ | ||
| 1778 | /*! @{ */ | ||
| 1779 | #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) | ||
| 1780 | #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) | ||
| 1781 | #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) | ||
| 1782 | #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U) | ||
| 1783 | #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U) | ||
| 1784 | #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK) | ||
| 1785 | #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U) | ||
| 1786 | #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U) | ||
| 1787 | #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK) | ||
| 1788 | #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U) | ||
| 1789 | #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U) | ||
| 1790 | #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK) | ||
| 1791 | #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U) | ||
| 1792 | #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U) | ||
| 1793 | #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK) | ||
| 1794 | #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U) | ||
| 1795 | #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U) | ||
| 1796 | #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK) | ||
| 1797 | #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U) | ||
| 1798 | #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U) | ||
| 1799 | #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK) | ||
| 1800 | #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U) | ||
| 1801 | #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U) | ||
| 1802 | #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK) | ||
| 1803 | #define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U) | ||
| 1804 | #define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U) | ||
| 1805 | #define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK) | ||
| 1806 | #define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U) | ||
| 1807 | #define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U) | ||
| 1808 | #define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK) | ||
| 1809 | #define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U) | ||
| 1810 | #define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U) | ||
| 1811 | #define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK) | ||
| 1812 | #define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U) | ||
| 1813 | #define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U) | ||
| 1814 | #define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK) | ||
| 1815 | #define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U) | ||
| 1816 | #define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U) | ||
| 1817 | #define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK) | ||
| 1818 | #define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U) | ||
| 1819 | #define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U) | ||
| 1820 | #define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK) | ||
| 1821 | #define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U) | ||
| 1822 | #define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U) | ||
| 1823 | #define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK) | ||
| 1824 | #define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) | ||
| 1825 | #define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) | ||
| 1826 | #define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) | ||
| 1827 | /*! @} */ | ||
| 1828 | |||
| 1829 | /*! @name TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG7 Control Register */ | ||
| 1830 | /*! @{ */ | ||
| 1831 | #define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) | ||
| 1832 | #define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) | ||
| 1833 | #define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) | ||
| 1834 | #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U) | ||
| 1835 | #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U) | ||
| 1836 | #define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK) | ||
| 1837 | #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U) | ||
| 1838 | #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U) | ||
| 1839 | #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK) | ||
| 1840 | #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U) | ||
| 1841 | #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U) | ||
| 1842 | #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK) | ||
| 1843 | #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) | ||
| 1844 | #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) | ||
| 1845 | #define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) | ||
| 1846 | /*! @} */ | ||
| 1847 | |||
| 1848 | /* The count of ADC_ETC_TRIGn_CTRL */ | ||
| 1849 | #define ADC_ETC_TRIGn_CTRL_COUNT (8U) | ||
| 1850 | |||
| 1851 | /*! @name TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register */ | ||
| 1852 | /*! @{ */ | ||
| 1853 | #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) | ||
| 1854 | #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) | ||
| 1855 | #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) | ||
| 1856 | #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) | ||
| 1857 | #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) | ||
| 1858 | #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) | ||
| 1859 | /*! @} */ | ||
| 1860 | |||
| 1861 | /* The count of ADC_ETC_TRIGn_COUNTER */ | ||
| 1862 | #define ADC_ETC_TRIGn_COUNTER_COUNT (8U) | ||
| 1863 | |||
| 1864 | /*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */ | ||
| 1865 | /*! @{ */ | ||
| 1866 | #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) | ||
| 1867 | #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) | ||
| 1868 | #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) | ||
| 1869 | #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U) | ||
| 1870 | #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U) | ||
| 1871 | #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK) | ||
| 1872 | #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U) | ||
| 1873 | #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U) | ||
| 1874 | #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK) | ||
| 1875 | #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U) | ||
| 1876 | #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U) | ||
| 1877 | #define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK) | ||
| 1878 | #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U) | ||
| 1879 | #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U) | ||
| 1880 | #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK) | ||
| 1881 | #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U) | ||
| 1882 | #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U) | ||
| 1883 | #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK) | ||
| 1884 | #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U) | ||
| 1885 | #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U) | ||
| 1886 | #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK) | ||
| 1887 | #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) | ||
| 1888 | #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) | ||
| 1889 | #define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) | ||
| 1890 | /*! @} */ | ||
| 1891 | |||
| 1892 | /* The count of ADC_ETC_TRIGn_CHAIN_1_0 */ | ||
| 1893 | #define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U) | ||
| 1894 | |||
| 1895 | /*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */ | ||
| 1896 | /*! @{ */ | ||
| 1897 | #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) | ||
| 1898 | #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) | ||
| 1899 | #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) | ||
| 1900 | #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U) | ||
| 1901 | #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U) | ||
| 1902 | #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK) | ||
| 1903 | #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U) | ||
| 1904 | #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U) | ||
| 1905 | #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK) | ||
| 1906 | #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U) | ||
| 1907 | #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U) | ||
| 1908 | #define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK) | ||
| 1909 | #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U) | ||
| 1910 | #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U) | ||
| 1911 | #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK) | ||
| 1912 | #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U) | ||
| 1913 | #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U) | ||
| 1914 | #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK) | ||
| 1915 | #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U) | ||
| 1916 | #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U) | ||
| 1917 | #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK) | ||
| 1918 | #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) | ||
| 1919 | #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) | ||
| 1920 | #define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) | ||
| 1921 | /*! @} */ | ||
| 1922 | |||
| 1923 | /* The count of ADC_ETC_TRIGn_CHAIN_3_2 */ | ||
| 1924 | #define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U) | ||
| 1925 | |||
| 1926 | /*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */ | ||
| 1927 | /*! @{ */ | ||
| 1928 | #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) | ||
| 1929 | #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) | ||
| 1930 | #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) | ||
| 1931 | #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U) | ||
| 1932 | #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U) | ||
| 1933 | #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK) | ||
| 1934 | #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U) | ||
| 1935 | #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U) | ||
| 1936 | #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK) | ||
| 1937 | #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U) | ||
| 1938 | #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U) | ||
| 1939 | #define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK) | ||
| 1940 | #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U) | ||
| 1941 | #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U) | ||
| 1942 | #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK) | ||
| 1943 | #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U) | ||
| 1944 | #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U) | ||
| 1945 | #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK) | ||
| 1946 | #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U) | ||
| 1947 | #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U) | ||
| 1948 | #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK) | ||
| 1949 | #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U) | ||
| 1950 | #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U) | ||
| 1951 | #define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK) | ||
| 1952 | /*! @} */ | ||
| 1953 | |||
| 1954 | /* The count of ADC_ETC_TRIGn_CHAIN_5_4 */ | ||
| 1955 | #define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U) | ||
| 1956 | |||
| 1957 | /*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */ | ||
| 1958 | /*! @{ */ | ||
| 1959 | #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU) | ||
| 1960 | #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U) | ||
| 1961 | #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK) | ||
| 1962 | #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U) | ||
| 1963 | #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U) | ||
| 1964 | #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK) | ||
| 1965 | #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U) | ||
| 1966 | #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U) | ||
| 1967 | #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK) | ||
| 1968 | #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U) | ||
| 1969 | #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U) | ||
| 1970 | #define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK) | ||
| 1971 | #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U) | ||
| 1972 | #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U) | ||
| 1973 | #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK) | ||
| 1974 | #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U) | ||
| 1975 | #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U) | ||
| 1976 | #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK) | ||
| 1977 | #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U) | ||
| 1978 | #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U) | ||
| 1979 | #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK) | ||
| 1980 | #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U) | ||
| 1981 | #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U) | ||
| 1982 | #define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK) | ||
| 1983 | /*! @} */ | ||
| 1984 | |||
| 1985 | /* The count of ADC_ETC_TRIGn_CHAIN_7_6 */ | ||
| 1986 | #define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U) | ||
| 1987 | |||
| 1988 | /*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */ | ||
| 1989 | /*! @{ */ | ||
| 1990 | #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU) | ||
| 1991 | #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U) | ||
| 1992 | #define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK) | ||
| 1993 | #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U) | ||
| 1994 | #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U) | ||
| 1995 | #define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK) | ||
| 1996 | /*! @} */ | ||
| 1997 | |||
| 1998 | /* The count of ADC_ETC_TRIGn_RESULT_1_0 */ | ||
| 1999 | #define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U) | ||
| 2000 | |||
| 2001 | /*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */ | ||
| 2002 | /*! @{ */ | ||
| 2003 | #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU) | ||
| 2004 | #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U) | ||
| 2005 | #define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK) | ||
| 2006 | #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U) | ||
| 2007 | #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U) | ||
| 2008 | #define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK) | ||
| 2009 | /*! @} */ | ||
| 2010 | |||
| 2011 | /* The count of ADC_ETC_TRIGn_RESULT_3_2 */ | ||
| 2012 | #define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U) | ||
| 2013 | |||
| 2014 | /*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */ | ||
| 2015 | /*! @{ */ | ||
| 2016 | #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU) | ||
| 2017 | #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U) | ||
| 2018 | #define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK) | ||
| 2019 | #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U) | ||
| 2020 | #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U) | ||
| 2021 | #define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK) | ||
| 2022 | /*! @} */ | ||
| 2023 | |||
| 2024 | /* The count of ADC_ETC_TRIGn_RESULT_5_4 */ | ||
| 2025 | #define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U) | ||
| 2026 | |||
| 2027 | /*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */ | ||
| 2028 | /*! @{ */ | ||
| 2029 | #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU) | ||
| 2030 | #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U) | ||
| 2031 | #define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK) | ||
| 2032 | #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U) | ||
| 2033 | #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U) | ||
| 2034 | #define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK) | ||
| 2035 | /*! @} */ | ||
| 2036 | |||
| 2037 | /* The count of ADC_ETC_TRIGn_RESULT_7_6 */ | ||
| 2038 | #define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U) | ||
| 2039 | |||
| 2040 | |||
| 2041 | /*! | ||
| 2042 | * @} | ||
| 2043 | */ /* end of group ADC_ETC_Register_Masks */ | ||
| 2044 | |||
| 2045 | |||
| 2046 | /* ADC_ETC - Peripheral instance base addresses */ | ||
| 2047 | /** Peripheral ADC_ETC base address */ | ||
| 2048 | #define ADC_ETC_BASE (0x403B0000u) | ||
| 2049 | /** Peripheral ADC_ETC base pointer */ | ||
| 2050 | #define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE) | ||
| 2051 | /** Array initializer of ADC_ETC peripheral base addresses */ | ||
| 2052 | #define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE } | ||
| 2053 | /** Array initializer of ADC_ETC peripheral base pointers */ | ||
| 2054 | #define ADC_ETC_BASE_PTRS { ADC_ETC } | ||
| 2055 | /** Interrupt vectors for the ADC_ETC peripheral type */ | ||
| 2056 | #define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } } | ||
| 2057 | #define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn } | ||
| 2058 | |||
| 2059 | /*! | ||
| 2060 | * @} | ||
| 2061 | */ /* end of group ADC_ETC_Peripheral_Access_Layer */ | ||
| 2062 | |||
| 2063 | |||
| 2064 | /* ---------------------------------------------------------------------------- | ||
| 2065 | -- AIPSTZ Peripheral Access Layer | ||
| 2066 | ---------------------------------------------------------------------------- */ | ||
| 2067 | |||
| 2068 | /*! | ||
| 2069 | * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer | ||
| 2070 | * @{ | ||
| 2071 | */ | ||
| 2072 | |||
| 2073 | /** AIPSTZ - Register Layout Typedef */ | ||
| 2074 | typedef struct { | ||
| 2075 | __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ | ||
| 2076 | uint8_t RESERVED_0[60]; | ||
| 2077 | __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */ | ||
| 2078 | __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */ | ||
| 2079 | __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */ | ||
| 2080 | __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */ | ||
| 2081 | __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */ | ||
| 2082 | } AIPSTZ_Type; | ||
| 2083 | |||
| 2084 | /* ---------------------------------------------------------------------------- | ||
| 2085 | -- AIPSTZ Register Masks | ||
| 2086 | ---------------------------------------------------------------------------- */ | ||
| 2087 | |||
| 2088 | /*! | ||
| 2089 | * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks | ||
| 2090 | * @{ | ||
| 2091 | */ | ||
| 2092 | |||
| 2093 | /*! @name MPR - Master Priviledge Registers */ | ||
| 2094 | /*! @{ */ | ||
| 2095 | #define AIPSTZ_MPR_MPROT5_MASK (0xF00U) | ||
| 2096 | #define AIPSTZ_MPR_MPROT5_SHIFT (8U) | ||
| 2097 | /*! MPROT5 | ||
| 2098 | * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. | ||
| 2099 | * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. | ||
| 2100 | * 0bxx0x..This master is not trusted for write accesses. | ||
| 2101 | * 0bxx1x..This master is trusted for write accesses. | ||
| 2102 | * 0bx0xx..This master is not trusted for read accesses. | ||
| 2103 | * 0bx1xx..This master is trusted for read accesses. | ||
| 2104 | * 0b1xxx..Write accesses from this master are allowed to be buffered | ||
| 2105 | */ | ||
| 2106 | #define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) | ||
| 2107 | #define AIPSTZ_MPR_MPROT3_MASK (0xF0000U) | ||
| 2108 | #define AIPSTZ_MPR_MPROT3_SHIFT (16U) | ||
| 2109 | /*! MPROT3 | ||
| 2110 | * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. | ||
| 2111 | * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. | ||
| 2112 | * 0bxx0x..This master is not trusted for write accesses. | ||
| 2113 | * 0bxx1x..This master is trusted for write accesses. | ||
| 2114 | * 0bx0xx..This master is not trusted for read accesses. | ||
| 2115 | * 0bx1xx..This master is trusted for read accesses. | ||
| 2116 | * 0b1xxx..Write accesses from this master are allowed to be buffered | ||
| 2117 | */ | ||
| 2118 | #define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) | ||
| 2119 | #define AIPSTZ_MPR_MPROT2_MASK (0xF00000U) | ||
| 2120 | #define AIPSTZ_MPR_MPROT2_SHIFT (20U) | ||
| 2121 | /*! MPROT2 | ||
| 2122 | * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. | ||
| 2123 | * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. | ||
| 2124 | * 0bxx0x..This master is not trusted for write accesses. | ||
| 2125 | * 0bxx1x..This master is trusted for write accesses. | ||
| 2126 | * 0bx0xx..This master is not trusted for read accesses. | ||
| 2127 | * 0bx1xx..This master is trusted for read accesses. | ||
| 2128 | * 0b1xxx..Write accesses from this master are allowed to be buffered | ||
| 2129 | */ | ||
| 2130 | #define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) | ||
| 2131 | #define AIPSTZ_MPR_MPROT1_MASK (0xF000000U) | ||
| 2132 | #define AIPSTZ_MPR_MPROT1_SHIFT (24U) | ||
| 2133 | /*! MPROT1 | ||
| 2134 | * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. | ||
| 2135 | * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. | ||
| 2136 | * 0bxx0x..This master is not trusted for write accesses. | ||
| 2137 | * 0bxx1x..This master is trusted for write accesses. | ||
| 2138 | * 0bx0xx..This master is not trusted for read accesses. | ||
| 2139 | * 0bx1xx..This master is trusted for read accesses. | ||
| 2140 | * 0b1xxx..Write accesses from this master are allowed to be buffered | ||
| 2141 | */ | ||
| 2142 | #define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) | ||
| 2143 | #define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) | ||
| 2144 | #define AIPSTZ_MPR_MPROT0_SHIFT (28U) | ||
| 2145 | /*! MPROT0 | ||
| 2146 | * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. | ||
| 2147 | * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. | ||
| 2148 | * 0bxx0x..This master is not trusted for write accesses. | ||
| 2149 | * 0bxx1x..This master is trusted for write accesses. | ||
| 2150 | * 0bx0xx..This master is not trusted for read accesses. | ||
| 2151 | * 0bx1xx..This master is trusted for read accesses. | ||
| 2152 | * 0b1xxx..Write accesses from this master are allowed to be buffered | ||
| 2153 | */ | ||
| 2154 | #define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) | ||
| 2155 | /*! @} */ | ||
| 2156 | |||
| 2157 | /*! @name OPACR - Off-Platform Peripheral Access Control Registers */ | ||
| 2158 | /*! @{ */ | ||
| 2159 | #define AIPSTZ_OPACR_OPAC7_MASK (0xFU) | ||
| 2160 | #define AIPSTZ_OPACR_OPAC7_SHIFT (0U) | ||
| 2161 | /*! OPAC7 | ||
| 2162 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2163 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2164 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2165 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2166 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2167 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2168 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2169 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2170 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2171 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2172 | * on the IPS bus. | ||
| 2173 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2174 | */ | ||
| 2175 | #define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) | ||
| 2176 | #define AIPSTZ_OPACR_OPAC6_MASK (0xF0U) | ||
| 2177 | #define AIPSTZ_OPACR_OPAC6_SHIFT (4U) | ||
| 2178 | /*! OPAC6 | ||
| 2179 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2180 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2181 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2182 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2183 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2184 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2185 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2186 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2187 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2188 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2189 | * on the IPS bus. | ||
| 2190 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2191 | */ | ||
| 2192 | #define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK) | ||
| 2193 | #define AIPSTZ_OPACR_OPAC5_MASK (0xF00U) | ||
| 2194 | #define AIPSTZ_OPACR_OPAC5_SHIFT (8U) | ||
| 2195 | /*! OPAC5 | ||
| 2196 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2197 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2198 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2199 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2200 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2201 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2202 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2203 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2204 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2205 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2206 | * on the IPS bus. | ||
| 2207 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2208 | */ | ||
| 2209 | #define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK) | ||
| 2210 | #define AIPSTZ_OPACR_OPAC4_MASK (0xF000U) | ||
| 2211 | #define AIPSTZ_OPACR_OPAC4_SHIFT (12U) | ||
| 2212 | /*! OPAC4 | ||
| 2213 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2214 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2215 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2216 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2217 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2218 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2219 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2220 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2221 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2222 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2223 | * on the IPS bus. | ||
| 2224 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2225 | */ | ||
| 2226 | #define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK) | ||
| 2227 | #define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U) | ||
| 2228 | #define AIPSTZ_OPACR_OPAC3_SHIFT (16U) | ||
| 2229 | /*! OPAC3 | ||
| 2230 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2231 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2232 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2233 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2234 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2235 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2236 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2237 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2238 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2239 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2240 | * on the IPS bus. | ||
| 2241 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2242 | */ | ||
| 2243 | #define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK) | ||
| 2244 | #define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U) | ||
| 2245 | #define AIPSTZ_OPACR_OPAC2_SHIFT (20U) | ||
| 2246 | /*! OPAC2 | ||
| 2247 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2248 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2249 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2250 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2251 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2252 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2253 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2254 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2255 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2256 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2257 | * on the IPS bus. | ||
| 2258 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2259 | */ | ||
| 2260 | #define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK) | ||
| 2261 | #define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U) | ||
| 2262 | #define AIPSTZ_OPACR_OPAC1_SHIFT (24U) | ||
| 2263 | /*! OPAC1 | ||
| 2264 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2265 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2266 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2267 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2268 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2269 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2270 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2271 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2272 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2273 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2274 | * on the IPS bus. | ||
| 2275 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2276 | */ | ||
| 2277 | #define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK) | ||
| 2278 | #define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) | ||
| 2279 | #define AIPSTZ_OPACR_OPAC0_SHIFT (28U) | ||
| 2280 | /*! OPAC0 | ||
| 2281 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2282 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2283 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2284 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2285 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2286 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2287 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2288 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2289 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2290 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2291 | * on the IPS bus. | ||
| 2292 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2293 | */ | ||
| 2294 | #define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) | ||
| 2295 | /*! @} */ | ||
| 2296 | |||
| 2297 | /*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */ | ||
| 2298 | /*! @{ */ | ||
| 2299 | #define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) | ||
| 2300 | #define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) | ||
| 2301 | /*! OPAC15 | ||
| 2302 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2303 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2304 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2305 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2306 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2307 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2308 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2309 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2310 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2311 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2312 | * on the IPS bus. | ||
| 2313 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2314 | */ | ||
| 2315 | #define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) | ||
| 2316 | #define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U) | ||
| 2317 | #define AIPSTZ_OPACR1_OPAC14_SHIFT (4U) | ||
| 2318 | /*! OPAC14 | ||
| 2319 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2320 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2321 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2322 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2323 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2324 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2325 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2326 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2327 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2328 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2329 | * on the IPS bus. | ||
| 2330 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2331 | */ | ||
| 2332 | #define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK) | ||
| 2333 | #define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U) | ||
| 2334 | #define AIPSTZ_OPACR1_OPAC13_SHIFT (8U) | ||
| 2335 | /*! OPAC13 | ||
| 2336 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2337 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2338 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2339 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2340 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2341 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2342 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2343 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2344 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2345 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2346 | * on the IPS bus. | ||
| 2347 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2348 | */ | ||
| 2349 | #define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK) | ||
| 2350 | #define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U) | ||
| 2351 | #define AIPSTZ_OPACR1_OPAC12_SHIFT (12U) | ||
| 2352 | /*! OPAC12 | ||
| 2353 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2354 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2355 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2356 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2357 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2358 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2359 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2360 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2361 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2362 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2363 | * on the IPS bus. | ||
| 2364 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2365 | */ | ||
| 2366 | #define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK) | ||
| 2367 | #define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U) | ||
| 2368 | #define AIPSTZ_OPACR1_OPAC11_SHIFT (16U) | ||
| 2369 | /*! OPAC11 | ||
| 2370 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2371 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2372 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2373 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2374 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2375 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2376 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2377 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2378 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2379 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2380 | * on the IPS bus. | ||
| 2381 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2382 | */ | ||
| 2383 | #define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK) | ||
| 2384 | #define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U) | ||
| 2385 | #define AIPSTZ_OPACR1_OPAC10_SHIFT (20U) | ||
| 2386 | /*! OPAC10 | ||
| 2387 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2388 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2389 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2390 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2391 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2392 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2393 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2394 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2395 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2396 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2397 | * on the IPS bus. | ||
| 2398 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2399 | */ | ||
| 2400 | #define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK) | ||
| 2401 | #define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U) | ||
| 2402 | #define AIPSTZ_OPACR1_OPAC9_SHIFT (24U) | ||
| 2403 | /*! OPAC9 | ||
| 2404 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2405 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2406 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2407 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2408 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2409 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2410 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2411 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2412 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2413 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2414 | * on the IPS bus. | ||
| 2415 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2416 | */ | ||
| 2417 | #define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK) | ||
| 2418 | #define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) | ||
| 2419 | #define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) | ||
| 2420 | /*! OPAC8 | ||
| 2421 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2422 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2423 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2424 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2425 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2426 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2427 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2428 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2429 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2430 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2431 | * on the IPS bus. | ||
| 2432 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2433 | */ | ||
| 2434 | #define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) | ||
| 2435 | /*! @} */ | ||
| 2436 | |||
| 2437 | /*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */ | ||
| 2438 | /*! @{ */ | ||
| 2439 | #define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) | ||
| 2440 | #define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) | ||
| 2441 | /*! OPAC23 | ||
| 2442 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2443 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2444 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2445 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2446 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2447 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2448 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2449 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2450 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2451 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2452 | * on the IPS bus. | ||
| 2453 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2454 | */ | ||
| 2455 | #define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) | ||
| 2456 | #define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U) | ||
| 2457 | #define AIPSTZ_OPACR2_OPAC22_SHIFT (4U) | ||
| 2458 | /*! OPAC22 | ||
| 2459 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2460 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2461 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2462 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2463 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2464 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2465 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2466 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2467 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2468 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2469 | * on the IPS bus. | ||
| 2470 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2471 | */ | ||
| 2472 | #define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK) | ||
| 2473 | #define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U) | ||
| 2474 | #define AIPSTZ_OPACR2_OPAC21_SHIFT (8U) | ||
| 2475 | /*! OPAC21 | ||
| 2476 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2477 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2478 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2479 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2480 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2481 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2482 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2483 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2484 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2485 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2486 | * on the IPS bus. | ||
| 2487 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2488 | */ | ||
| 2489 | #define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK) | ||
| 2490 | #define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U) | ||
| 2491 | #define AIPSTZ_OPACR2_OPAC20_SHIFT (12U) | ||
| 2492 | /*! OPAC20 | ||
| 2493 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2494 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2495 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2496 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2497 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2498 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2499 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2500 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2501 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2502 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2503 | * on the IPS bus. | ||
| 2504 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2505 | */ | ||
| 2506 | #define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK) | ||
| 2507 | #define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U) | ||
| 2508 | #define AIPSTZ_OPACR2_OPAC19_SHIFT (16U) | ||
| 2509 | /*! OPAC19 | ||
| 2510 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2511 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2512 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2513 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2514 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2515 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2516 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2517 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2518 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2519 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2520 | * on the IPS bus. | ||
| 2521 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2522 | */ | ||
| 2523 | #define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK) | ||
| 2524 | #define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U) | ||
| 2525 | #define AIPSTZ_OPACR2_OPAC18_SHIFT (20U) | ||
| 2526 | /*! OPAC18 | ||
| 2527 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2528 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2529 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2530 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2531 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2532 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2533 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2534 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2535 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2536 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2537 | * on the IPS bus. | ||
| 2538 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2539 | */ | ||
| 2540 | #define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK) | ||
| 2541 | #define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U) | ||
| 2542 | #define AIPSTZ_OPACR2_OPAC17_SHIFT (24U) | ||
| 2543 | /*! OPAC17 | ||
| 2544 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2545 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2546 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2547 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2548 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2549 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2550 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2551 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2552 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2553 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2554 | * on the IPS bus. | ||
| 2555 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2556 | */ | ||
| 2557 | #define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK) | ||
| 2558 | #define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) | ||
| 2559 | #define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) | ||
| 2560 | /*! OPAC16 | ||
| 2561 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2562 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2563 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2564 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2565 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2566 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2567 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2568 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2569 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2570 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2571 | * on the IPS bus. | ||
| 2572 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2573 | */ | ||
| 2574 | #define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) | ||
| 2575 | /*! @} */ | ||
| 2576 | |||
| 2577 | /*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */ | ||
| 2578 | /*! @{ */ | ||
| 2579 | #define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) | ||
| 2580 | #define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) | ||
| 2581 | /*! OPAC31 | ||
| 2582 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2583 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2584 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2585 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2586 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2587 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2588 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2589 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2590 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2591 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2592 | * on the IPS bus. | ||
| 2593 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2594 | */ | ||
| 2595 | #define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) | ||
| 2596 | #define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U) | ||
| 2597 | #define AIPSTZ_OPACR3_OPAC30_SHIFT (4U) | ||
| 2598 | /*! OPAC30 | ||
| 2599 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2600 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2601 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2602 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2603 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2604 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2605 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2606 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2607 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2608 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2609 | * on the IPS bus. | ||
| 2610 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2611 | */ | ||
| 2612 | #define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK) | ||
| 2613 | #define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U) | ||
| 2614 | #define AIPSTZ_OPACR3_OPAC29_SHIFT (8U) | ||
| 2615 | /*! OPAC29 | ||
| 2616 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2617 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2618 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2619 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2620 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2621 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2622 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2623 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2624 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2625 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2626 | * on the IPS bus. | ||
| 2627 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2628 | */ | ||
| 2629 | #define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK) | ||
| 2630 | #define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U) | ||
| 2631 | #define AIPSTZ_OPACR3_OPAC28_SHIFT (12U) | ||
| 2632 | /*! OPAC28 | ||
| 2633 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2634 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2635 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2636 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2637 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2638 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2639 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2640 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2641 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2642 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2643 | * on the IPS bus. | ||
| 2644 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2645 | */ | ||
| 2646 | #define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK) | ||
| 2647 | #define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U) | ||
| 2648 | #define AIPSTZ_OPACR3_OPAC27_SHIFT (16U) | ||
| 2649 | /*! OPAC27 | ||
| 2650 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2651 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2652 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2653 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2654 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2655 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2656 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2657 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2658 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2659 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2660 | * on the IPS bus. | ||
| 2661 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2662 | */ | ||
| 2663 | #define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK) | ||
| 2664 | #define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U) | ||
| 2665 | #define AIPSTZ_OPACR3_OPAC26_SHIFT (20U) | ||
| 2666 | /*! OPAC26 | ||
| 2667 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2668 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2669 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2670 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2671 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2672 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2673 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2674 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2675 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2676 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2677 | * on the IPS bus. | ||
| 2678 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2679 | */ | ||
| 2680 | #define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK) | ||
| 2681 | #define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U) | ||
| 2682 | #define AIPSTZ_OPACR3_OPAC25_SHIFT (24U) | ||
| 2683 | /*! OPAC25 | ||
| 2684 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2685 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2686 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2687 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2688 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2689 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2690 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2691 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2692 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2693 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2694 | * on the IPS bus. | ||
| 2695 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2696 | */ | ||
| 2697 | #define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK) | ||
| 2698 | #define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) | ||
| 2699 | #define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) | ||
| 2700 | /*! OPAC24 | ||
| 2701 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2702 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2703 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2704 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2705 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2706 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2707 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2708 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2709 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2710 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2711 | * on the IPS bus. | ||
| 2712 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2713 | */ | ||
| 2714 | #define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) | ||
| 2715 | /*! @} */ | ||
| 2716 | |||
| 2717 | /*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */ | ||
| 2718 | /*! @{ */ | ||
| 2719 | #define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) | ||
| 2720 | #define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) | ||
| 2721 | /*! OPAC33 | ||
| 2722 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2723 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2724 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2725 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2726 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2727 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2728 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2729 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2730 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2731 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2732 | * on the IPS bus. | ||
| 2733 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2734 | */ | ||
| 2735 | #define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) | ||
| 2736 | #define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) | ||
| 2737 | #define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) | ||
| 2738 | /*! OPAC32 | ||
| 2739 | * 0bxxx0..Accesses from an untrusted master are allowed. | ||
| 2740 | * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, | ||
| 2741 | * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. | ||
| 2742 | * 0bxx0x..This peripheral allows write accesses. | ||
| 2743 | * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an | ||
| 2744 | * error response and no peripheral access is initiated on the IPS bus. | ||
| 2745 | * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. | ||
| 2746 | * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must | ||
| 2747 | * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must | ||
| 2748 | * be set. If not, the access is terminated with an error response and no peripheral access is initiated | ||
| 2749 | * on the IPS bus. | ||
| 2750 | * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. | ||
| 2751 | */ | ||
| 2752 | #define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) | ||
| 2753 | /*! @} */ | ||
| 2754 | |||
| 2755 | |||
| 2756 | /*! | ||
| 2757 | * @} | ||
| 2758 | */ /* end of group AIPSTZ_Register_Masks */ | ||
| 2759 | |||
| 2760 | |||
| 2761 | /* AIPSTZ - Peripheral instance base addresses */ | ||
| 2762 | /** Peripheral AIPSTZ1 base address */ | ||
| 2763 | #define AIPSTZ1_BASE (0x4007C000u) | ||
| 2764 | /** Peripheral AIPSTZ1 base pointer */ | ||
| 2765 | #define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE) | ||
| 2766 | /** Peripheral AIPSTZ2 base address */ | ||
| 2767 | #define AIPSTZ2_BASE (0x4017C000u) | ||
| 2768 | /** Peripheral AIPSTZ2 base pointer */ | ||
| 2769 | #define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE) | ||
| 2770 | /** Peripheral AIPSTZ3 base address */ | ||
| 2771 | #define AIPSTZ3_BASE (0x4027C000u) | ||
| 2772 | /** Peripheral AIPSTZ3 base pointer */ | ||
| 2773 | #define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE) | ||
| 2774 | /** Peripheral AIPSTZ4 base address */ | ||
| 2775 | #define AIPSTZ4_BASE (0x4037C000u) | ||
| 2776 | /** Peripheral AIPSTZ4 base pointer */ | ||
| 2777 | #define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE) | ||
| 2778 | /** Array initializer of AIPSTZ peripheral base addresses */ | ||
| 2779 | #define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE } | ||
| 2780 | /** Array initializer of AIPSTZ peripheral base pointers */ | ||
| 2781 | #define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 } | ||
| 2782 | |||
| 2783 | /*! | ||
| 2784 | * @} | ||
| 2785 | */ /* end of group AIPSTZ_Peripheral_Access_Layer */ | ||
| 2786 | |||
| 2787 | |||
| 2788 | /* ---------------------------------------------------------------------------- | ||
| 2789 | -- AOI Peripheral Access Layer | ||
| 2790 | ---------------------------------------------------------------------------- */ | ||
| 2791 | |||
| 2792 | /*! | ||
| 2793 | * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer | ||
| 2794 | * @{ | ||
| 2795 | */ | ||
| 2796 | |||
| 2797 | /** AOI - Register Layout Typedef */ | ||
| 2798 | typedef struct { | ||
| 2799 | struct { /* offset: 0x0, array step: 0x4 */ | ||
| 2800 | __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */ | ||
| 2801 | __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */ | ||
| 2802 | } BFCRT[4]; | ||
| 2803 | } AOI_Type; | ||
| 2804 | |||
| 2805 | /* ---------------------------------------------------------------------------- | ||
| 2806 | -- AOI Register Masks | ||
| 2807 | ---------------------------------------------------------------------------- */ | ||
| 2808 | |||
| 2809 | /*! | ||
| 2810 | * @addtogroup AOI_Register_Masks AOI Register Masks | ||
| 2811 | * @{ | ||
| 2812 | */ | ||
| 2813 | |||
| 2814 | /*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */ | ||
| 2815 | /*! @{ */ | ||
| 2816 | #define AOI_BFCRT01_PT1_DC_MASK (0x3U) | ||
| 2817 | #define AOI_BFCRT01_PT1_DC_SHIFT (0U) | ||
| 2818 | /*! PT1_DC - Product term 1, D input configuration | ||
| 2819 | * 0b00..Force the D input in this product term to a logical zero | ||
| 2820 | * 0b01..Pass the D input in this product term | ||
| 2821 | * 0b10..Complement the D input in this product term | ||
| 2822 | * 0b11..Force the D input in this product term to a logical one | ||
| 2823 | */ | ||
| 2824 | #define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK) | ||
| 2825 | #define AOI_BFCRT01_PT1_CC_MASK (0xCU) | ||
| 2826 | #define AOI_BFCRT01_PT1_CC_SHIFT (2U) | ||
| 2827 | /*! PT1_CC - Product term 1, C input configuration | ||
| 2828 | * 0b00..Force the C input in this product term to a logical zero | ||
| 2829 | * 0b01..Pass the C input in this product term | ||
| 2830 | * 0b10..Complement the C input in this product term | ||
| 2831 | * 0b11..Force the C input in this product term to a logical one | ||
| 2832 | */ | ||
| 2833 | #define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK) | ||
| 2834 | #define AOI_BFCRT01_PT1_BC_MASK (0x30U) | ||
| 2835 | #define AOI_BFCRT01_PT1_BC_SHIFT (4U) | ||
| 2836 | /*! PT1_BC - Product term 1, B input configuration | ||
| 2837 | * 0b00..Force the B input in this product term to a logical zero | ||
| 2838 | * 0b01..Pass the B input in this product term | ||
| 2839 | * 0b10..Complement the B input in this product term | ||
| 2840 | * 0b11..Force the B input in this product term to a logical one | ||
| 2841 | */ | ||
| 2842 | #define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK) | ||
| 2843 | #define AOI_BFCRT01_PT1_AC_MASK (0xC0U) | ||
| 2844 | #define AOI_BFCRT01_PT1_AC_SHIFT (6U) | ||
| 2845 | /*! PT1_AC - Product term 1, A input configuration | ||
| 2846 | * 0b00..Force the A input in this product term to a logical zero | ||
| 2847 | * 0b01..Pass the A input in this product term | ||
| 2848 | * 0b10..Complement the A input in this product term | ||
| 2849 | * 0b11..Force the A input in this product term to a logical one | ||
| 2850 | */ | ||
| 2851 | #define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK) | ||
| 2852 | #define AOI_BFCRT01_PT0_DC_MASK (0x300U) | ||
| 2853 | #define AOI_BFCRT01_PT0_DC_SHIFT (8U) | ||
| 2854 | /*! PT0_DC - Product term 0, D input configuration | ||
| 2855 | * 0b00..Force the D input in this product term to a logical zero | ||
| 2856 | * 0b01..Pass the D input in this product term | ||
| 2857 | * 0b10..Complement the D input in this product term | ||
| 2858 | * 0b11..Force the D input in this product term to a logical one | ||
| 2859 | */ | ||
| 2860 | #define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK) | ||
| 2861 | #define AOI_BFCRT01_PT0_CC_MASK (0xC00U) | ||
| 2862 | #define AOI_BFCRT01_PT0_CC_SHIFT (10U) | ||
| 2863 | /*! PT0_CC - Product term 0, C input configuration | ||
| 2864 | * 0b00..Force the C input in this product term to a logical zero | ||
| 2865 | * 0b01..Pass the C input in this product term | ||
| 2866 | * 0b10..Complement the C input in this product term | ||
| 2867 | * 0b11..Force the C input in this product term to a logical one | ||
| 2868 | */ | ||
| 2869 | #define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK) | ||
| 2870 | #define AOI_BFCRT01_PT0_BC_MASK (0x3000U) | ||
| 2871 | #define AOI_BFCRT01_PT0_BC_SHIFT (12U) | ||
| 2872 | /*! PT0_BC - Product term 0, B input configuration | ||
| 2873 | * 0b00..Force the B input in this product term to a logical zero | ||
| 2874 | * 0b01..Pass the B input in this product term | ||
| 2875 | * 0b10..Complement the B input in this product term | ||
| 2876 | * 0b11..Force the B input in this product term to a logical one | ||
| 2877 | */ | ||
| 2878 | #define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK) | ||
| 2879 | #define AOI_BFCRT01_PT0_AC_MASK (0xC000U) | ||
| 2880 | #define AOI_BFCRT01_PT0_AC_SHIFT (14U) | ||
| 2881 | /*! PT0_AC - Product term 0, A input configuration | ||
| 2882 | * 0b00..Force the A input in this product term to a logical zero | ||
| 2883 | * 0b01..Pass the A input in this product term | ||
| 2884 | * 0b10..Complement the A input in this product term | ||
| 2885 | * 0b11..Force the A input in this product term to a logical one | ||
| 2886 | */ | ||
| 2887 | #define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK) | ||
| 2888 | /*! @} */ | ||
| 2889 | |||
| 2890 | /* The count of AOI_BFCRT01 */ | ||
| 2891 | #define AOI_BFCRT01_COUNT (4U) | ||
| 2892 | |||
| 2893 | /*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */ | ||
| 2894 | /*! @{ */ | ||
| 2895 | #define AOI_BFCRT23_PT3_DC_MASK (0x3U) | ||
| 2896 | #define AOI_BFCRT23_PT3_DC_SHIFT (0U) | ||
| 2897 | /*! PT3_DC - Product term 3, D input configuration | ||
| 2898 | * 0b00..Force the D input in this product term to a logical zero | ||
| 2899 | * 0b01..Pass the D input in this product term | ||
| 2900 | * 0b10..Complement the D input in this product term | ||
| 2901 | * 0b11..Force the D input in this product term to a logical one | ||
| 2902 | */ | ||
| 2903 | #define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK) | ||
| 2904 | #define AOI_BFCRT23_PT3_CC_MASK (0xCU) | ||
| 2905 | #define AOI_BFCRT23_PT3_CC_SHIFT (2U) | ||
| 2906 | /*! PT3_CC - Product term 3, C input configuration | ||
| 2907 | * 0b00..Force the C input in this product term to a logical zero | ||
| 2908 | * 0b01..Pass the C input in this product term | ||
| 2909 | * 0b10..Complement the C input in this product term | ||
| 2910 | * 0b11..Force the C input in this product term to a logical one | ||
| 2911 | */ | ||
| 2912 | #define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK) | ||
| 2913 | #define AOI_BFCRT23_PT3_BC_MASK (0x30U) | ||
| 2914 | #define AOI_BFCRT23_PT3_BC_SHIFT (4U) | ||
| 2915 | /*! PT3_BC - Product term 3, B input configuration | ||
| 2916 | * 0b00..Force the B input in this product term to a logical zero | ||
| 2917 | * 0b01..Pass the B input in this product term | ||
| 2918 | * 0b10..Complement the B input in this product term | ||
| 2919 | * 0b11..Force the B input in this product term to a logical one | ||
| 2920 | */ | ||
| 2921 | #define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK) | ||
| 2922 | #define AOI_BFCRT23_PT3_AC_MASK (0xC0U) | ||
| 2923 | #define AOI_BFCRT23_PT3_AC_SHIFT (6U) | ||
| 2924 | /*! PT3_AC - Product term 3, A input configuration | ||
| 2925 | * 0b00..Force the A input in this product term to a logical zero | ||
| 2926 | * 0b01..Pass the A input in this product term | ||
| 2927 | * 0b10..Complement the A input in this product term | ||
| 2928 | * 0b11..Force the A input in this product term to a logical one | ||
| 2929 | */ | ||
| 2930 | #define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK) | ||
| 2931 | #define AOI_BFCRT23_PT2_DC_MASK (0x300U) | ||
| 2932 | #define AOI_BFCRT23_PT2_DC_SHIFT (8U) | ||
| 2933 | /*! PT2_DC - Product term 2, D input configuration | ||
| 2934 | * 0b00..Force the D input in this product term to a logical zero | ||
| 2935 | * 0b01..Pass the D input in this product term | ||
| 2936 | * 0b10..Complement the D input in this product term | ||
| 2937 | * 0b11..Force the D input in this product term to a logical one | ||
| 2938 | */ | ||
| 2939 | #define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK) | ||
| 2940 | #define AOI_BFCRT23_PT2_CC_MASK (0xC00U) | ||
| 2941 | #define AOI_BFCRT23_PT2_CC_SHIFT (10U) | ||
| 2942 | /*! PT2_CC - Product term 2, C input configuration | ||
| 2943 | * 0b00..Force the C input in this product term to a logical zero | ||
| 2944 | * 0b01..Pass the C input in this product term | ||
| 2945 | * 0b10..Complement the C input in this product term | ||
| 2946 | * 0b11..Force the C input in this product term to a logical one | ||
| 2947 | */ | ||
| 2948 | #define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK) | ||
| 2949 | #define AOI_BFCRT23_PT2_BC_MASK (0x3000U) | ||
| 2950 | #define AOI_BFCRT23_PT2_BC_SHIFT (12U) | ||
| 2951 | /*! PT2_BC - Product term 2, B input configuration | ||
| 2952 | * 0b00..Force the B input in this product term to a logical zero | ||
| 2953 | * 0b01..Pass the B input in this product term | ||
| 2954 | * 0b10..Complement the B input in this product term | ||
| 2955 | * 0b11..Force the B input in this product term to a logical one | ||
| 2956 | */ | ||
| 2957 | #define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK) | ||
| 2958 | #define AOI_BFCRT23_PT2_AC_MASK (0xC000U) | ||
| 2959 | #define AOI_BFCRT23_PT2_AC_SHIFT (14U) | ||
| 2960 | /*! PT2_AC - Product term 2, A input configuration | ||
| 2961 | * 0b00..Force the A input in this product term to a logical zero | ||
| 2962 | * 0b01..Pass the A input in this product term | ||
| 2963 | * 0b10..Complement the A input in this product term | ||
| 2964 | * 0b11..Force the A input in this product term to a logical one | ||
| 2965 | */ | ||
| 2966 | #define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK) | ||
| 2967 | /*! @} */ | ||
| 2968 | |||
| 2969 | /* The count of AOI_BFCRT23 */ | ||
| 2970 | #define AOI_BFCRT23_COUNT (4U) | ||
| 2971 | |||
| 2972 | |||
| 2973 | /*! | ||
| 2974 | * @} | ||
| 2975 | */ /* end of group AOI_Register_Masks */ | ||
| 2976 | |||
| 2977 | |||
| 2978 | /* AOI - Peripheral instance base addresses */ | ||
| 2979 | /** Peripheral AOI1 base address */ | ||
| 2980 | #define AOI1_BASE (0x403B4000u) | ||
| 2981 | /** Peripheral AOI1 base pointer */ | ||
| 2982 | #define AOI1 ((AOI_Type *)AOI1_BASE) | ||
| 2983 | /** Peripheral AOI2 base address */ | ||
| 2984 | #define AOI2_BASE (0x403B8000u) | ||
| 2985 | /** Peripheral AOI2 base pointer */ | ||
| 2986 | #define AOI2 ((AOI_Type *)AOI2_BASE) | ||
| 2987 | /** Array initializer of AOI peripheral base addresses */ | ||
| 2988 | #define AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE } | ||
| 2989 | /** Array initializer of AOI peripheral base pointers */ | ||
| 2990 | #define AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 } | ||
| 2991 | |||
| 2992 | /*! | ||
| 2993 | * @} | ||
| 2994 | */ /* end of group AOI_Peripheral_Access_Layer */ | ||
| 2995 | |||
| 2996 | |||
| 2997 | /* ---------------------------------------------------------------------------- | ||
| 2998 | -- BEE Peripheral Access Layer | ||
| 2999 | ---------------------------------------------------------------------------- */ | ||
| 3000 | |||
| 3001 | /*! | ||
| 3002 | * @addtogroup BEE_Peripheral_Access_Layer BEE Peripheral Access Layer | ||
| 3003 | * @{ | ||
| 3004 | */ | ||
| 3005 | |||
| 3006 | /** BEE - Register Layout Typedef */ | ||
| 3007 | typedef struct { | ||
| 3008 | __IO uint32_t CTRL; /**< Control Register, offset: 0x0 */ | ||
| 3009 | __IO uint32_t ADDR_OFFSET0; /**< Offset region 0 Register, offset: 0x4 */ | ||
| 3010 | __IO uint32_t ADDR_OFFSET1; /**< Offset region 1 Register, offset: 0x8 */ | ||
| 3011 | __IO uint32_t AES_KEY0_W0; /**< AES Key 0 Register, offset: 0xC */ | ||
| 3012 | __IO uint32_t AES_KEY0_W1; /**< AES Key 1 Register, offset: 0x10 */ | ||
| 3013 | __IO uint32_t AES_KEY0_W2; /**< AES Key 2 Register, offset: 0x14 */ | ||
| 3014 | __IO uint32_t AES_KEY0_W3; /**< AES Key 3 Register, offset: 0x18 */ | ||
| 3015 | __IO uint32_t STATUS; /**< Status Register, offset: 0x1C */ | ||
| 3016 | __O uint32_t CTR_NONCE0_W0; /**< NONCE00 Register, offset: 0x20 */ | ||
| 3017 | __O uint32_t CTR_NONCE0_W1; /**< NONCE01 Register, offset: 0x24 */ | ||
| 3018 | __O uint32_t CTR_NONCE0_W2; /**< NONCE02 Register, offset: 0x28 */ | ||
| 3019 | __O uint32_t CTR_NONCE0_W3; /**< NONCE03 Register, offset: 0x2C */ | ||
| 3020 | __O uint32_t CTR_NONCE1_W0; /**< NONCE10 Register, offset: 0x30 */ | ||
| 3021 | __O uint32_t CTR_NONCE1_W1; /**< NONCE11 Register, offset: 0x34 */ | ||
| 3022 | __O uint32_t CTR_NONCE1_W2; /**< NONCE12 Register, offset: 0x38 */ | ||
| 3023 | __O uint32_t CTR_NONCE1_W3; /**< NONCE13 Register, offset: 0x3C */ | ||
| 3024 | __IO uint32_t REGION1_TOP; /**< Region1 Top Address Register, offset: 0x40 */ | ||
| 3025 | __IO uint32_t REGION1_BOT; /**< Region1 Bottom Address Register, offset: 0x44 */ | ||
| 3026 | } BEE_Type; | ||
| 3027 | |||
| 3028 | /* ---------------------------------------------------------------------------- | ||
| 3029 | -- BEE Register Masks | ||
| 3030 | ---------------------------------------------------------------------------- */ | ||
| 3031 | |||
| 3032 | /*! | ||
| 3033 | * @addtogroup BEE_Register_Masks BEE Register Masks | ||
| 3034 | * @{ | ||
| 3035 | */ | ||
| 3036 | |||
| 3037 | /*! @name CTRL - Control Register */ | ||
| 3038 | /*! @{ */ | ||
| 3039 | #define BEE_CTRL_BEE_ENABLE_MASK (0x1U) | ||
| 3040 | #define BEE_CTRL_BEE_ENABLE_SHIFT (0U) | ||
| 3041 | /*! BEE_ENABLE | ||
| 3042 | * 0b0..Disable BEE | ||
| 3043 | * 0b1..Enable BEE | ||
| 3044 | */ | ||
| 3045 | #define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK) | ||
| 3046 | #define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U) | ||
| 3047 | #define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U) | ||
| 3048 | #define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK) | ||
| 3049 | #define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U) | ||
| 3050 | #define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U) | ||
| 3051 | #define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK) | ||
| 3052 | #define BEE_CTRL_KEY_VALID_MASK (0x10U) | ||
| 3053 | #define BEE_CTRL_KEY_VALID_SHIFT (4U) | ||
| 3054 | #define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK) | ||
| 3055 | #define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U) | ||
| 3056 | #define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U) | ||
| 3057 | /*! KEY_REGION_SEL | ||
| 3058 | * 0b0..Load AES key for region0 | ||
| 3059 | * 0b1..Load AES key for region1 | ||
| 3060 | */ | ||
| 3061 | #define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK) | ||
| 3062 | #define BEE_CTRL_AC_PROT_EN_MASK (0x40U) | ||
| 3063 | #define BEE_CTRL_AC_PROT_EN_SHIFT (6U) | ||
| 3064 | #define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK) | ||
| 3065 | #define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U) | ||
| 3066 | #define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U) | ||
| 3067 | /*! LITTLE_ENDIAN | ||
| 3068 | * 0b0..The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8, | ||
| 3069 | * B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to | ||
| 3070 | * Byte0 to Byte15. | ||
| 3071 | * 0b1..The input and output data of AES core is not swapped. | ||
| 3072 | */ | ||
| 3073 | #define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK) | ||
| 3074 | #define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U) | ||
| 3075 | #define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U) | ||
| 3076 | #define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK) | ||
| 3077 | #define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U) | ||
| 3078 | #define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U) | ||
| 3079 | /*! CTRL_AES_MODE_R0 | ||
| 3080 | * 0b0..ECB | ||
| 3081 | * 0b1..CTR | ||
| 3082 | */ | ||
| 3083 | #define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK) | ||
| 3084 | #define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U) | ||
| 3085 | #define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U) | ||
| 3086 | #define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK) | ||
| 3087 | #define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U) | ||
| 3088 | #define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U) | ||
| 3089 | /*! CTRL_AES_MODE_R1 | ||
| 3090 | * 0b0..ECB | ||
| 3091 | * 0b1..CTR | ||
| 3092 | */ | ||
| 3093 | #define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK) | ||
| 3094 | #define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U) | ||
| 3095 | #define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U) | ||
| 3096 | #define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK) | ||
| 3097 | #define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U) | ||
| 3098 | #define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U) | ||
| 3099 | #define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK) | ||
| 3100 | #define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U) | ||
| 3101 | #define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U) | ||
| 3102 | #define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK) | ||
| 3103 | #define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U) | ||
| 3104 | #define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U) | ||
| 3105 | #define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK) | ||
| 3106 | #define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U) | ||
| 3107 | #define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U) | ||
| 3108 | #define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK) | ||
| 3109 | #define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U) | ||
| 3110 | #define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U) | ||
| 3111 | #define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK) | ||
| 3112 | #define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U) | ||
| 3113 | #define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U) | ||
| 3114 | #define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK) | ||
| 3115 | #define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U) | ||
| 3116 | #define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U) | ||
| 3117 | #define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK) | ||
| 3118 | #define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U) | ||
| 3119 | #define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U) | ||
| 3120 | #define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK) | ||
| 3121 | #define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U) | ||
| 3122 | #define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U) | ||
| 3123 | #define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK) | ||
| 3124 | #define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U) | ||
| 3125 | #define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U) | ||
| 3126 | #define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK) | ||
| 3127 | #define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U) | ||
| 3128 | #define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U) | ||
| 3129 | #define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK) | ||
| 3130 | #define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U) | ||
| 3131 | #define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U) | ||
| 3132 | #define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK) | ||
| 3133 | #define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U) | ||
| 3134 | #define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U) | ||
| 3135 | #define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK) | ||
| 3136 | /*! @} */ | ||
| 3137 | |||
| 3138 | /*! @name ADDR_OFFSET0 - Offset region 0 Register */ | ||
| 3139 | /*! @{ */ | ||
| 3140 | #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU) | ||
| 3141 | #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U) | ||
| 3142 | #define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK) | ||
| 3143 | #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U) | ||
| 3144 | #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U) | ||
| 3145 | #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK) | ||
| 3146 | /*! @} */ | ||
| 3147 | |||
| 3148 | /*! @name ADDR_OFFSET1 - Offset region 1 Register */ | ||
| 3149 | /*! @{ */ | ||
| 3150 | #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU) | ||
| 3151 | #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U) | ||
| 3152 | #define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK) | ||
| 3153 | #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U) | ||
| 3154 | #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U) | ||
| 3155 | #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK) | ||
| 3156 | /*! @} */ | ||
| 3157 | |||
| 3158 | /*! @name AES_KEY0_W0 - AES Key 0 Register */ | ||
| 3159 | /*! @{ */ | ||
| 3160 | #define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU) | ||
| 3161 | #define BEE_AES_KEY0_W0_KEY0_SHIFT (0U) | ||
| 3162 | /*! KEY0 - AES 128 key from software | ||
| 3163 | */ | ||
| 3164 | #define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK) | ||
| 3165 | /*! @} */ | ||
| 3166 | |||
| 3167 | /*! @name AES_KEY0_W1 - AES Key 1 Register */ | ||
| 3168 | /*! @{ */ | ||
| 3169 | #define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU) | ||
| 3170 | #define BEE_AES_KEY0_W1_KEY1_SHIFT (0U) | ||
| 3171 | /*! KEY1 - AES 128 key from software | ||
| 3172 | */ | ||
| 3173 | #define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK) | ||
| 3174 | /*! @} */ | ||
| 3175 | |||
| 3176 | /*! @name AES_KEY0_W2 - AES Key 2 Register */ | ||
| 3177 | /*! @{ */ | ||
| 3178 | #define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU) | ||
| 3179 | #define BEE_AES_KEY0_W2_KEY2_SHIFT (0U) | ||
| 3180 | /*! KEY2 - AES 128 key from software | ||
| 3181 | */ | ||
| 3182 | #define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK) | ||
| 3183 | /*! @} */ | ||
| 3184 | |||
| 3185 | /*! @name AES_KEY0_W3 - AES Key 3 Register */ | ||
| 3186 | /*! @{ */ | ||
| 3187 | #define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU) | ||
| 3188 | #define BEE_AES_KEY0_W3_KEY3_SHIFT (0U) | ||
| 3189 | /*! KEY3 - AES 128 key from software | ||
| 3190 | */ | ||
| 3191 | #define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK) | ||
| 3192 | /*! @} */ | ||
| 3193 | |||
| 3194 | /*! @name STATUS - Status Register */ | ||
| 3195 | /*! @{ */ | ||
| 3196 | #define BEE_STATUS_IRQ_VEC_MASK (0xFFU) | ||
| 3197 | #define BEE_STATUS_IRQ_VEC_SHIFT (0U) | ||
| 3198 | #define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK) | ||
| 3199 | #define BEE_STATUS_BEE_IDLE_MASK (0x100U) | ||
| 3200 | #define BEE_STATUS_BEE_IDLE_SHIFT (8U) | ||
| 3201 | #define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK) | ||
| 3202 | /*! @} */ | ||
| 3203 | |||
| 3204 | /*! @name CTR_NONCE0_W0 - NONCE00 Register */ | ||
| 3205 | /*! @{ */ | ||
| 3206 | #define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU) | ||
| 3207 | #define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U) | ||
| 3208 | #define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK) | ||
| 3209 | /*! @} */ | ||
| 3210 | |||
| 3211 | /*! @name CTR_NONCE0_W1 - NONCE01 Register */ | ||
| 3212 | /*! @{ */ | ||
| 3213 | #define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU) | ||
| 3214 | #define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U) | ||
| 3215 | #define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK) | ||
| 3216 | /*! @} */ | ||
| 3217 | |||
| 3218 | /*! @name CTR_NONCE0_W2 - NONCE02 Register */ | ||
| 3219 | /*! @{ */ | ||
| 3220 | #define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU) | ||
| 3221 | #define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U) | ||
| 3222 | #define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK) | ||
| 3223 | /*! @} */ | ||
| 3224 | |||
| 3225 | /*! @name CTR_NONCE0_W3 - NONCE03 Register */ | ||
| 3226 | /*! @{ */ | ||
| 3227 | #define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU) | ||
| 3228 | #define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U) | ||
| 3229 | #define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK) | ||
| 3230 | /*! @} */ | ||
| 3231 | |||
| 3232 | /*! @name CTR_NONCE1_W0 - NONCE10 Register */ | ||
| 3233 | /*! @{ */ | ||
| 3234 | #define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU) | ||
| 3235 | #define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U) | ||
| 3236 | #define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK) | ||
| 3237 | /*! @} */ | ||
| 3238 | |||
| 3239 | /*! @name CTR_NONCE1_W1 - NONCE11 Register */ | ||
| 3240 | /*! @{ */ | ||
| 3241 | #define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU) | ||
| 3242 | #define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U) | ||
| 3243 | #define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK) | ||
| 3244 | /*! @} */ | ||
| 3245 | |||
| 3246 | /*! @name CTR_NONCE1_W2 - NONCE12 Register */ | ||
| 3247 | /*! @{ */ | ||
| 3248 | #define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU) | ||
| 3249 | #define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U) | ||
| 3250 | #define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK) | ||
| 3251 | /*! @} */ | ||
| 3252 | |||
| 3253 | /*! @name CTR_NONCE1_W3 - NONCE13 Register */ | ||
| 3254 | /*! @{ */ | ||
| 3255 | #define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU) | ||
| 3256 | #define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U) | ||
| 3257 | #define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK) | ||
| 3258 | /*! @} */ | ||
| 3259 | |||
| 3260 | /*! @name REGION1_TOP - Region1 Top Address Register */ | ||
| 3261 | /*! @{ */ | ||
| 3262 | #define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU) | ||
| 3263 | #define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U) | ||
| 3264 | /*! REGION1_TOP - Address upper limit of region1 | ||
| 3265 | */ | ||
| 3266 | #define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK) | ||
| 3267 | /*! @} */ | ||
| 3268 | |||
| 3269 | /*! @name REGION1_BOT - Region1 Bottom Address Register */ | ||
| 3270 | /*! @{ */ | ||
| 3271 | #define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU) | ||
| 3272 | #define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U) | ||
| 3273 | /*! REGION1_BOT - Address lower limit of region1 | ||
| 3274 | */ | ||
| 3275 | #define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK) | ||
| 3276 | /*! @} */ | ||
| 3277 | |||
| 3278 | |||
| 3279 | /*! | ||
| 3280 | * @} | ||
| 3281 | */ /* end of group BEE_Register_Masks */ | ||
| 3282 | |||
| 3283 | |||
| 3284 | /* BEE - Peripheral instance base addresses */ | ||
| 3285 | /** Peripheral BEE base address */ | ||
| 3286 | #define BEE_BASE (0x403EC000u) | ||
| 3287 | /** Peripheral BEE base pointer */ | ||
| 3288 | #define BEE ((BEE_Type *)BEE_BASE) | ||
| 3289 | /** Array initializer of BEE peripheral base addresses */ | ||
| 3290 | #define BEE_BASE_ADDRS { BEE_BASE } | ||
| 3291 | /** Array initializer of BEE peripheral base pointers */ | ||
| 3292 | #define BEE_BASE_PTRS { BEE } | ||
| 3293 | |||
| 3294 | /*! | ||
| 3295 | * @} | ||
| 3296 | */ /* end of group BEE_Peripheral_Access_Layer */ | ||
| 3297 | |||
| 3298 | |||
| 3299 | /* ---------------------------------------------------------------------------- | ||
| 3300 | -- CAN Peripheral Access Layer | ||
| 3301 | ---------------------------------------------------------------------------- */ | ||
| 3302 | |||
| 3303 | /*! | ||
| 3304 | * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer | ||
| 3305 | * @{ | ||
| 3306 | */ | ||
| 3307 | |||
| 3308 | /** CAN - Register Layout Typedef */ | ||
| 3309 | typedef struct { | ||
| 3310 | __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ | ||
| 3311 | __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ | ||
| 3312 | __IO uint32_t TIMER; /**< Free Running Timer Register, offset: 0x8 */ | ||
| 3313 | uint8_t RESERVED_0[4]; | ||
| 3314 | __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ | ||
| 3315 | __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register, offset: 0x14 */ | ||
| 3316 | __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register, offset: 0x18 */ | ||
| 3317 | __IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */ | ||
| 3318 | __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ | ||
| 3319 | __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ | ||
| 3320 | __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ | ||
| 3321 | __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */ | ||
| 3322 | __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ | ||
| 3323 | __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ | ||
| 3324 | __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ | ||
| 3325 | uint8_t RESERVED_1[8]; | ||
| 3326 | __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ | ||
| 3327 | __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */ | ||
| 3328 | __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ | ||
| 3329 | uint8_t RESERVED_2[8]; | ||
| 3330 | __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */ | ||
| 3331 | __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */ | ||
| 3332 | uint8_t RESERVED_3[32]; | ||
| 3333 | struct { /* offset: 0x80, array step: 0x10 */ | ||
| 3334 | __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ | ||
| 3335 | __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ | ||
| 3336 | __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ | ||
| 3337 | __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ | ||
| 3338 | } MB[64]; | ||
| 3339 | uint8_t RESERVED_4[1024]; | ||
| 3340 | __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ | ||
| 3341 | uint8_t RESERVED_5[96]; | ||
| 3342 | __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */ | ||
| 3343 | } CAN_Type; | ||
| 3344 | |||
| 3345 | /* ---------------------------------------------------------------------------- | ||
| 3346 | -- CAN Register Masks | ||
| 3347 | ---------------------------------------------------------------------------- */ | ||
| 3348 | |||
| 3349 | /*! | ||
| 3350 | * @addtogroup CAN_Register_Masks CAN Register Masks | ||
| 3351 | * @{ | ||
| 3352 | */ | ||
| 3353 | |||
| 3354 | /*! @name MCR - Module Configuration Register */ | ||
| 3355 | /*! @{ */ | ||
| 3356 | #define CAN_MCR_MAXMB_MASK (0x7FU) | ||
| 3357 | #define CAN_MCR_MAXMB_SHIFT (0U) | ||
| 3358 | #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) | ||
| 3359 | #define CAN_MCR_IDAM_MASK (0x300U) | ||
| 3360 | #define CAN_MCR_IDAM_SHIFT (8U) | ||
| 3361 | /*! IDAM | ||
| 3362 | * 0b00..Format A One full ID (standard or extended) per ID filter Table element. | ||
| 3363 | * 0b01..Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element. | ||
| 3364 | * 0b10..Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element. | ||
| 3365 | * 0b11..Format D All frames rejected. | ||
| 3366 | */ | ||
| 3367 | #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) | ||
| 3368 | #define CAN_MCR_AEN_MASK (0x1000U) | ||
| 3369 | #define CAN_MCR_AEN_SHIFT (12U) | ||
| 3370 | /*! AEN | ||
| 3371 | * 0b1..Abort enabled | ||
| 3372 | * 0b0..Abort disabled | ||
| 3373 | */ | ||
| 3374 | #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) | ||
| 3375 | #define CAN_MCR_LPRIOEN_MASK (0x2000U) | ||
| 3376 | #define CAN_MCR_LPRIOEN_SHIFT (13U) | ||
| 3377 | /*! LPRIOEN | ||
| 3378 | * 0b1..Local Priority enabled | ||
| 3379 | * 0b0..Local Priority disabled | ||
| 3380 | */ | ||
| 3381 | #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) | ||
| 3382 | #define CAN_MCR_IRMQ_MASK (0x10000U) | ||
| 3383 | #define CAN_MCR_IRMQ_SHIFT (16U) | ||
| 3384 | /*! IRMQ | ||
| 3385 | * 0b1..Individual Rx masking and queue feature are enabled. | ||
| 3386 | * 0b0..Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY. | ||
| 3387 | */ | ||
| 3388 | #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) | ||
| 3389 | #define CAN_MCR_SRXDIS_MASK (0x20000U) | ||
| 3390 | #define CAN_MCR_SRXDIS_SHIFT (17U) | ||
| 3391 | /*! SRXDIS | ||
| 3392 | * 0b1..Self reception disabled | ||
| 3393 | * 0b0..Self reception enabled | ||
| 3394 | */ | ||
| 3395 | #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) | ||
| 3396 | #define CAN_MCR_WAKSRC_MASK (0x80000U) | ||
| 3397 | #define CAN_MCR_WAKSRC_SHIFT (19U) | ||
| 3398 | /*! WAKSRC | ||
| 3399 | * 0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus | ||
| 3400 | * 0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus. | ||
| 3401 | */ | ||
| 3402 | #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) | ||
| 3403 | #define CAN_MCR_LPMACK_MASK (0x100000U) | ||
| 3404 | #define CAN_MCR_LPMACK_SHIFT (20U) | ||
| 3405 | /*! LPMACK | ||
| 3406 | * 0b1..FLEXCAN is either in Disable Mode, or Stop mode | ||
| 3407 | * 0b0..FLEXCAN not in any of the low power modes | ||
| 3408 | */ | ||
| 3409 | #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) | ||
| 3410 | #define CAN_MCR_WRNEN_MASK (0x200000U) | ||
| 3411 | #define CAN_MCR_WRNEN_SHIFT (21U) | ||
| 3412 | /*! WRNEN | ||
| 3413 | * 0b1..TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96. | ||
| 3414 | * 0b0..TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters. | ||
| 3415 | */ | ||
| 3416 | #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) | ||
| 3417 | #define CAN_MCR_SLFWAK_MASK (0x400000U) | ||
| 3418 | #define CAN_MCR_SLFWAK_SHIFT (22U) | ||
| 3419 | /*! SLFWAK | ||
| 3420 | * 0b1..FLEXCAN Self Wake Up feature is enabled | ||
| 3421 | * 0b0..FLEXCAN Self Wake Up feature is disabled | ||
| 3422 | */ | ||
| 3423 | #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) | ||
| 3424 | #define CAN_MCR_SUPV_MASK (0x800000U) | ||
| 3425 | #define CAN_MCR_SUPV_SHIFT (23U) | ||
| 3426 | /*! SUPV | ||
| 3427 | * 0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access | ||
| 3428 | * behaves as though the access was done to an unimplemented register location | ||
| 3429 | * 0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses | ||
| 3430 | */ | ||
| 3431 | #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) | ||
| 3432 | #define CAN_MCR_FRZACK_MASK (0x1000000U) | ||
| 3433 | #define CAN_MCR_FRZACK_SHIFT (24U) | ||
| 3434 | /*! FRZACK | ||
| 3435 | * 0b1..FLEXCAN in Freeze Mode, prescaler stopped | ||
| 3436 | * 0b0..FLEXCAN not in Freeze Mode, prescaler running | ||
| 3437 | */ | ||
| 3438 | #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) | ||
| 3439 | #define CAN_MCR_SOFTRST_MASK (0x2000000U) | ||
| 3440 | #define CAN_MCR_SOFTRST_SHIFT (25U) | ||
| 3441 | /*! SOFTRST | ||
| 3442 | * 0b1..Reset the registers | ||
| 3443 | * 0b0..No reset request | ||
| 3444 | */ | ||
| 3445 | #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) | ||
| 3446 | #define CAN_MCR_WAKMSK_MASK (0x4000000U) | ||
| 3447 | #define CAN_MCR_WAKMSK_SHIFT (26U) | ||
| 3448 | /*! WAKMSK | ||
| 3449 | * 0b1..Wake Up Interrupt is enabled | ||
| 3450 | * 0b0..Wake Up Interrupt is disabled | ||
| 3451 | */ | ||
| 3452 | #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) | ||
| 3453 | #define CAN_MCR_NOTRDY_MASK (0x8000000U) | ||
| 3454 | #define CAN_MCR_NOTRDY_SHIFT (27U) | ||
| 3455 | /*! NOTRDY | ||
| 3456 | * 0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode | ||
| 3457 | * 0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode | ||
| 3458 | */ | ||
| 3459 | #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) | ||
| 3460 | #define CAN_MCR_HALT_MASK (0x10000000U) | ||
| 3461 | #define CAN_MCR_HALT_SHIFT (28U) | ||
| 3462 | /*! HALT | ||
| 3463 | * 0b1..Enters Freeze Mode if the FRZ bit is asserted. | ||
| 3464 | * 0b0..No Freeze Mode request. | ||
| 3465 | */ | ||
| 3466 | #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) | ||
| 3467 | #define CAN_MCR_RFEN_MASK (0x20000000U) | ||
| 3468 | #define CAN_MCR_RFEN_SHIFT (29U) | ||
| 3469 | /*! RFEN | ||
| 3470 | * 0b1..FIFO enabled | ||
| 3471 | * 0b0..FIFO not enabled | ||
| 3472 | */ | ||
| 3473 | #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) | ||
| 3474 | #define CAN_MCR_FRZ_MASK (0x40000000U) | ||
| 3475 | #define CAN_MCR_FRZ_SHIFT (30U) | ||
| 3476 | /*! FRZ | ||
| 3477 | * 0b1..Enabled to enter Freeze Mode | ||
| 3478 | * 0b0..Not enabled to enter Freeze Mode | ||
| 3479 | */ | ||
| 3480 | #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) | ||
| 3481 | #define CAN_MCR_MDIS_MASK (0x80000000U) | ||
| 3482 | #define CAN_MCR_MDIS_SHIFT (31U) | ||
| 3483 | /*! MDIS | ||
| 3484 | * 0b1..Disable the FLEXCAN module | ||
| 3485 | * 0b0..Enable the FLEXCAN module | ||
| 3486 | */ | ||
| 3487 | #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) | ||
| 3488 | /*! @} */ | ||
| 3489 | |||
| 3490 | /*! @name CTRL1 - Control 1 Register */ | ||
| 3491 | /*! @{ */ | ||
| 3492 | #define CAN_CTRL1_PROPSEG_MASK (0x7U) | ||
| 3493 | #define CAN_CTRL1_PROPSEG_SHIFT (0U) | ||
| 3494 | #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) | ||
| 3495 | #define CAN_CTRL1_LOM_MASK (0x8U) | ||
| 3496 | #define CAN_CTRL1_LOM_SHIFT (3U) | ||
| 3497 | /*! LOM | ||
| 3498 | * 0b1..FLEXCAN module operates in Listen Only Mode | ||
| 3499 | * 0b0..Listen Only Mode is deactivated | ||
| 3500 | */ | ||
| 3501 | #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) | ||
| 3502 | #define CAN_CTRL1_LBUF_MASK (0x10U) | ||
| 3503 | #define CAN_CTRL1_LBUF_SHIFT (4U) | ||
| 3504 | /*! LBUF | ||
| 3505 | * 0b1..Lowest number buffer is transmitted first | ||
| 3506 | * 0b0..Buffer with highest priority is transmitted first | ||
| 3507 | */ | ||
| 3508 | #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) | ||
| 3509 | #define CAN_CTRL1_TSYN_MASK (0x20U) | ||
| 3510 | #define CAN_CTRL1_TSYN_SHIFT (5U) | ||
| 3511 | /*! TSYN | ||
| 3512 | * 0b1..Timer Sync feature enabled | ||
| 3513 | * 0b0..Timer Sync feature disabled | ||
| 3514 | */ | ||
| 3515 | #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) | ||
| 3516 | #define CAN_CTRL1_BOFFREC_MASK (0x40U) | ||
| 3517 | #define CAN_CTRL1_BOFFREC_SHIFT (6U) | ||
| 3518 | /*! BOFFREC | ||
| 3519 | * 0b1..Automatic recovering from Bus Off state disabled | ||
| 3520 | * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B | ||
| 3521 | */ | ||
| 3522 | #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) | ||
| 3523 | #define CAN_CTRL1_SMP_MASK (0x80U) | ||
| 3524 | #define CAN_CTRL1_SMP_SHIFT (7U) | ||
| 3525 | /*! SMP | ||
| 3526 | * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 | ||
| 3527 | * preceding samples, a majority rule is used | ||
| 3528 | * 0b0..Just one sample is used to determine the bit value | ||
| 3529 | */ | ||
| 3530 | #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) | ||
| 3531 | #define CAN_CTRL1_RWRNMSK_MASK (0x400U) | ||
| 3532 | #define CAN_CTRL1_RWRNMSK_SHIFT (10U) | ||
| 3533 | /*! RWRNMSK | ||
| 3534 | * 0b1..Rx Warning Interrupt enabled | ||
| 3535 | * 0b0..Rx Warning Interrupt disabled | ||
| 3536 | */ | ||
| 3537 | #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) | ||
| 3538 | #define CAN_CTRL1_TWRNMSK_MASK (0x800U) | ||
| 3539 | #define CAN_CTRL1_TWRNMSK_SHIFT (11U) | ||
| 3540 | /*! TWRNMSK | ||
| 3541 | * 0b1..Tx Warning Interrupt enabled | ||
| 3542 | * 0b0..Tx Warning Interrupt disabled | ||
| 3543 | */ | ||
| 3544 | #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) | ||
| 3545 | #define CAN_CTRL1_LPB_MASK (0x1000U) | ||
| 3546 | #define CAN_CTRL1_LPB_SHIFT (12U) | ||
| 3547 | /*! LPB | ||
| 3548 | * 0b1..Loop Back enabled | ||
| 3549 | * 0b0..Loop Back disabled | ||
| 3550 | */ | ||
| 3551 | #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) | ||
| 3552 | #define CAN_CTRL1_ERRMSK_MASK (0x4000U) | ||
| 3553 | #define CAN_CTRL1_ERRMSK_SHIFT (14U) | ||
| 3554 | /*! ERRMSK | ||
| 3555 | * 0b1..Error interrupt enabled | ||
| 3556 | * 0b0..Error interrupt disabled | ||
| 3557 | */ | ||
| 3558 | #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) | ||
| 3559 | #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) | ||
| 3560 | #define CAN_CTRL1_BOFFMSK_SHIFT (15U) | ||
| 3561 | /*! BOFFMSK | ||
| 3562 | * 0b1..Bus Off interrupt enabled | ||
| 3563 | * 0b0..Bus Off interrupt disabled | ||
| 3564 | */ | ||
| 3565 | #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) | ||
| 3566 | #define CAN_CTRL1_PSEG2_MASK (0x70000U) | ||
| 3567 | #define CAN_CTRL1_PSEG2_SHIFT (16U) | ||
| 3568 | #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) | ||
| 3569 | #define CAN_CTRL1_PSEG1_MASK (0x380000U) | ||
| 3570 | #define CAN_CTRL1_PSEG1_SHIFT (19U) | ||
| 3571 | #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) | ||
| 3572 | #define CAN_CTRL1_RJW_MASK (0xC00000U) | ||
| 3573 | #define CAN_CTRL1_RJW_SHIFT (22U) | ||
| 3574 | #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) | ||
| 3575 | #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) | ||
| 3576 | #define CAN_CTRL1_PRESDIV_SHIFT (24U) | ||
| 3577 | #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) | ||
| 3578 | /*! @} */ | ||
| 3579 | |||
| 3580 | /*! @name TIMER - Free Running Timer Register */ | ||
| 3581 | /*! @{ */ | ||
| 3582 | #define CAN_TIMER_TIMER_MASK (0xFFFFU) | ||
| 3583 | #define CAN_TIMER_TIMER_SHIFT (0U) | ||
| 3584 | #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) | ||
| 3585 | /*! @} */ | ||
| 3586 | |||
| 3587 | /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ | ||
| 3588 | /*! @{ */ | ||
| 3589 | #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) | ||
| 3590 | #define CAN_RXMGMASK_MG_SHIFT (0U) | ||
| 3591 | /*! MG | ||
| 3592 | * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received | ||
| 3593 | * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" | ||
| 3594 | */ | ||
| 3595 | #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) | ||
| 3596 | /*! @} */ | ||
| 3597 | |||
| 3598 | /*! @name RX14MASK - Rx Buffer 14 Mask Register */ | ||
| 3599 | /*! @{ */ | ||
| 3600 | #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) | ||
| 3601 | #define CAN_RX14MASK_RX14M_SHIFT (0U) | ||
| 3602 | /*! RX14M | ||
| 3603 | * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked | ||
| 3604 | * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" | ||
| 3605 | */ | ||
| 3606 | #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) | ||
| 3607 | /*! @} */ | ||
| 3608 | |||
| 3609 | /*! @name RX15MASK - Rx Buffer 15 Mask Register */ | ||
| 3610 | /*! @{ */ | ||
| 3611 | #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) | ||
| 3612 | #define CAN_RX15MASK_RX15M_SHIFT (0U) | ||
| 3613 | /*! RX15M | ||
| 3614 | * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked | ||
| 3615 | * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" | ||
| 3616 | */ | ||
| 3617 | #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) | ||
| 3618 | /*! @} */ | ||
| 3619 | |||
| 3620 | /*! @name ECR - Error Counter Register */ | ||
| 3621 | /*! @{ */ | ||
| 3622 | #define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU) | ||
| 3623 | #define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U) | ||
| 3624 | #define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK) | ||
| 3625 | #define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U) | ||
| 3626 | #define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U) | ||
| 3627 | #define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK) | ||
| 3628 | /*! @} */ | ||
| 3629 | |||
| 3630 | /*! @name ESR1 - Error and Status 1 Register */ | ||
| 3631 | /*! @{ */ | ||
| 3632 | #define CAN_ESR1_WAKINT_MASK (0x1U) | ||
| 3633 | #define CAN_ESR1_WAKINT_SHIFT (0U) | ||
| 3634 | /*! WAKINT | ||
| 3635 | * 0b1..Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode | ||
| 3636 | * 0b0..No such occurrence | ||
| 3637 | */ | ||
| 3638 | #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) | ||
| 3639 | #define CAN_ESR1_ERRINT_MASK (0x2U) | ||
| 3640 | #define CAN_ESR1_ERRINT_SHIFT (1U) | ||
| 3641 | /*! ERRINT | ||
| 3642 | * 0b1..Indicates setting of any Error Bit in the Error and Status Register | ||
| 3643 | * 0b0..No such occurrence | ||
| 3644 | */ | ||
| 3645 | #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) | ||
| 3646 | #define CAN_ESR1_BOFFINT_MASK (0x4U) | ||
| 3647 | #define CAN_ESR1_BOFFINT_SHIFT (2U) | ||
| 3648 | /*! BOFFINT | ||
| 3649 | * 0b1..FLEXCAN module entered 'Bus Off' state | ||
| 3650 | * 0b0..No such occurrence | ||
| 3651 | */ | ||
| 3652 | #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) | ||
| 3653 | #define CAN_ESR1_RX_MASK (0x8U) | ||
| 3654 | #define CAN_ESR1_RX_SHIFT (3U) | ||
| 3655 | /*! RX | ||
| 3656 | * 0b1..FLEXCAN is transmitting a message | ||
| 3657 | * 0b0..FLEXCAN is receiving a message | ||
| 3658 | */ | ||
| 3659 | #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) | ||
| 3660 | #define CAN_ESR1_FLTCONF_MASK (0x30U) | ||
| 3661 | #define CAN_ESR1_FLTCONF_SHIFT (4U) | ||
| 3662 | /*! FLTCONF | ||
| 3663 | * 0b00..Error Active | ||
| 3664 | * 0b01..Error Passive | ||
| 3665 | * 0b1x..Bus off | ||
| 3666 | */ | ||
| 3667 | #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) | ||
| 3668 | #define CAN_ESR1_TX_MASK (0x40U) | ||
| 3669 | #define CAN_ESR1_TX_SHIFT (6U) | ||
| 3670 | /*! TX | ||
| 3671 | * 0b1..FLEXCAN is transmitting a message | ||
| 3672 | * 0b0..FLEXCAN is receiving a message | ||
| 3673 | */ | ||
| 3674 | #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) | ||
| 3675 | #define CAN_ESR1_IDLE_MASK (0x80U) | ||
| 3676 | #define CAN_ESR1_IDLE_SHIFT (7U) | ||
| 3677 | /*! IDLE | ||
| 3678 | * 0b1..CAN bus is now IDLE | ||
| 3679 | * 0b0..No such occurrence | ||
| 3680 | */ | ||
| 3681 | #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) | ||
| 3682 | #define CAN_ESR1_RXWRN_MASK (0x100U) | ||
| 3683 | #define CAN_ESR1_RXWRN_SHIFT (8U) | ||
| 3684 | /*! RXWRN | ||
| 3685 | * 0b1..Rx_Err_Counter >= 96 | ||
| 3686 | * 0b0..No such occurrence | ||
| 3687 | */ | ||
| 3688 | #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) | ||
| 3689 | #define CAN_ESR1_TXWRN_MASK (0x200U) | ||
| 3690 | #define CAN_ESR1_TXWRN_SHIFT (9U) | ||
| 3691 | /*! TXWRN | ||
| 3692 | * 0b1..TX_Err_Counter >= 96 | ||
| 3693 | * 0b0..No such occurrence | ||
| 3694 | */ | ||
| 3695 | #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) | ||
| 3696 | #define CAN_ESR1_STFERR_MASK (0x400U) | ||
| 3697 | #define CAN_ESR1_STFERR_SHIFT (10U) | ||
| 3698 | /*! STFERR | ||
| 3699 | * 0b1..A Stuffing Error occurred since last read of this register. | ||
| 3700 | * 0b0..No such occurrence. | ||
| 3701 | */ | ||
| 3702 | #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) | ||
| 3703 | #define CAN_ESR1_FRMERR_MASK (0x800U) | ||
| 3704 | #define CAN_ESR1_FRMERR_SHIFT (11U) | ||
| 3705 | /*! FRMERR | ||
| 3706 | * 0b1..A Form Error occurred since last read of this register | ||
| 3707 | * 0b0..No such occurrence | ||
| 3708 | */ | ||
| 3709 | #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) | ||
| 3710 | #define CAN_ESR1_CRCERR_MASK (0x1000U) | ||
| 3711 | #define CAN_ESR1_CRCERR_SHIFT (12U) | ||
| 3712 | /*! CRCERR | ||
| 3713 | * 0b1..A CRC error occurred since last read of this register. | ||
| 3714 | * 0b0..No such occurrence | ||
| 3715 | */ | ||
| 3716 | #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) | ||
| 3717 | #define CAN_ESR1_ACKERR_MASK (0x2000U) | ||
| 3718 | #define CAN_ESR1_ACKERR_SHIFT (13U) | ||
| 3719 | /*! ACKERR | ||
| 3720 | * 0b1..An ACK error occurred since last read of this register | ||
| 3721 | * 0b0..No such occurrence | ||
| 3722 | */ | ||
| 3723 | #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) | ||
| 3724 | #define CAN_ESR1_BIT0ERR_MASK (0x4000U) | ||
| 3725 | #define CAN_ESR1_BIT0ERR_SHIFT (14U) | ||
| 3726 | /*! BIT0ERR | ||
| 3727 | * 0b1..At least one bit sent as dominant is received as recessive | ||
| 3728 | * 0b0..No such occurrence | ||
| 3729 | */ | ||
| 3730 | #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) | ||
| 3731 | #define CAN_ESR1_BIT1ERR_MASK (0x8000U) | ||
| 3732 | #define CAN_ESR1_BIT1ERR_SHIFT (15U) | ||
| 3733 | /*! BIT1ERR | ||
| 3734 | * 0b1..At least one bit sent as recessive is received as dominant | ||
| 3735 | * 0b0..No such occurrence | ||
| 3736 | */ | ||
| 3737 | #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) | ||
| 3738 | #define CAN_ESR1_RWRNINT_MASK (0x10000U) | ||
| 3739 | #define CAN_ESR1_RWRNINT_SHIFT (16U) | ||
| 3740 | /*! RWRNINT | ||
| 3741 | * 0b1..The Rx error counter transition from < 96 to >= 96 | ||
| 3742 | * 0b0..No such occurrence | ||
| 3743 | */ | ||
| 3744 | #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) | ||
| 3745 | #define CAN_ESR1_TWRNINT_MASK (0x20000U) | ||
| 3746 | #define CAN_ESR1_TWRNINT_SHIFT (17U) | ||
| 3747 | /*! TWRNINT | ||
| 3748 | * 0b1..The Tx error counter transition from < 96 to >= 96 | ||
| 3749 | * 0b0..No such occurrence | ||
| 3750 | */ | ||
| 3751 | #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) | ||
| 3752 | #define CAN_ESR1_SYNCH_MASK (0x40000U) | ||
| 3753 | #define CAN_ESR1_SYNCH_SHIFT (18U) | ||
| 3754 | /*! SYNCH | ||
| 3755 | * 0b1..FlexCAN is synchronized to the CAN bus | ||
| 3756 | * 0b0..FlexCAN is not synchronized to the CAN bus | ||
| 3757 | */ | ||
| 3758 | #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) | ||
| 3759 | /*! @} */ | ||
| 3760 | |||
| 3761 | /*! @name IMASK2 - Interrupt Masks 2 Register */ | ||
| 3762 | /*! @{ */ | ||
| 3763 | #define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU) | ||
| 3764 | #define CAN_IMASK2_BUFHM_SHIFT (0U) | ||
| 3765 | /*! BUFHM | ||
| 3766 | * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled | ||
| 3767 | * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled | ||
| 3768 | */ | ||
| 3769 | #define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK) | ||
| 3770 | /*! @} */ | ||
| 3771 | |||
| 3772 | /*! @name IMASK1 - Interrupt Masks 1 Register */ | ||
| 3773 | /*! @{ */ | ||
| 3774 | #define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) | ||
| 3775 | #define CAN_IMASK1_BUFLM_SHIFT (0U) | ||
| 3776 | /*! BUFLM | ||
| 3777 | * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled | ||
| 3778 | * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled | ||
| 3779 | */ | ||
| 3780 | #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) | ||
| 3781 | /*! @} */ | ||
| 3782 | |||
| 3783 | /*! @name IFLAG2 - Interrupt Flags 2 Register */ | ||
| 3784 | /*! @{ */ | ||
| 3785 | #define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU) | ||
| 3786 | #define CAN_IFLAG2_BUFHI_SHIFT (0U) | ||
| 3787 | /*! BUFHI | ||
| 3788 | * 0b00000000000000000000000000000001..The corresponding buffer has successfully completed transmission or reception | ||
| 3789 | * 0b00000000000000000000000000000000..No such occurrence | ||
| 3790 | */ | ||
| 3791 | #define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK) | ||
| 3792 | /*! @} */ | ||
| 3793 | |||
| 3794 | /*! @name IFLAG1 - Interrupt Flags 1 Register */ | ||
| 3795 | /*! @{ */ | ||
| 3796 | #define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU) | ||
| 3797 | #define CAN_IFLAG1_BUF4TO0I_SHIFT (0U) | ||
| 3798 | /*! BUF4TO0I | ||
| 3799 | * 0b00001..Corresponding MB completed transmission/reception | ||
| 3800 | * 0b00000..No such occurrence | ||
| 3801 | */ | ||
| 3802 | #define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK) | ||
| 3803 | #define CAN_IFLAG1_BUF5I_MASK (0x20U) | ||
| 3804 | #define CAN_IFLAG1_BUF5I_SHIFT (5U) | ||
| 3805 | /*! BUF5I | ||
| 3806 | * 0b1..MB5 completed transmission/reception or frames available in the FIFO | ||
| 3807 | * 0b0..No such occurrence | ||
| 3808 | */ | ||
| 3809 | #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) | ||
| 3810 | #define CAN_IFLAG1_BUF6I_MASK (0x40U) | ||
| 3811 | #define CAN_IFLAG1_BUF6I_SHIFT (6U) | ||
| 3812 | /*! BUF6I | ||
| 3813 | * 0b1..MB6 completed transmission/reception or FIFO almost full | ||
| 3814 | * 0b0..No such occurrence | ||
| 3815 | */ | ||
| 3816 | #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) | ||
| 3817 | #define CAN_IFLAG1_BUF7I_MASK (0x80U) | ||
| 3818 | #define CAN_IFLAG1_BUF7I_SHIFT (7U) | ||
| 3819 | /*! BUF7I | ||
| 3820 | * 0b1..MB7 completed transmission/reception or FIFO overflow | ||
| 3821 | * 0b0..No such occurrence | ||
| 3822 | */ | ||
| 3823 | #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) | ||
| 3824 | #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) | ||
| 3825 | #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) | ||
| 3826 | /*! BUF31TO8I | ||
| 3827 | * 0b000000000000000000000001..The corresponding MB has successfully completed transmission or reception | ||
| 3828 | * 0b000000000000000000000000..No such occurrence | ||
| 3829 | */ | ||
| 3830 | #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) | ||
| 3831 | /*! @} */ | ||
| 3832 | |||
| 3833 | /*! @name CTRL2 - Control 2 Register */ | ||
| 3834 | /*! @{ */ | ||
| 3835 | #define CAN_CTRL2_EACEN_MASK (0x10000U) | ||
| 3836 | #define CAN_CTRL2_EACEN_SHIFT (16U) | ||
| 3837 | /*! EACEN | ||
| 3838 | * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within | ||
| 3839 | * the incoming frame. Mask bits do apply. | ||
| 3840 | * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. | ||
| 3841 | */ | ||
| 3842 | #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) | ||
| 3843 | #define CAN_CTRL2_RRS_MASK (0x20000U) | ||
| 3844 | #define CAN_CTRL2_RRS_SHIFT (17U) | ||
| 3845 | /*! RRS | ||
| 3846 | * 0b1..Remote Request Frame is stored | ||
| 3847 | * 0b0..Remote Response Frame is generated | ||
| 3848 | */ | ||
| 3849 | #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) | ||
| 3850 | #define CAN_CTRL2_MRP_MASK (0x40000U) | ||
| 3851 | #define CAN_CTRL2_MRP_SHIFT (18U) | ||
| 3852 | /*! MRP | ||
| 3853 | * 0b1..Matching starts from Mailboxes and continues on Rx FIFO | ||
| 3854 | * 0b0..Matching starts from Rx FIFO and continues on Mailboxes | ||
| 3855 | */ | ||
| 3856 | #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) | ||
| 3857 | #define CAN_CTRL2_TASD_MASK (0xF80000U) | ||
| 3858 | #define CAN_CTRL2_TASD_SHIFT (19U) | ||
| 3859 | #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) | ||
| 3860 | #define CAN_CTRL2_RFFN_MASK (0xF000000U) | ||
| 3861 | #define CAN_CTRL2_RFFN_SHIFT (24U) | ||
| 3862 | #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) | ||
| 3863 | #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) | ||
| 3864 | #define CAN_CTRL2_WRMFRZ_SHIFT (28U) | ||
| 3865 | /*! WRMFRZ | ||
| 3866 | * 0b1..Enable unrestricted write access to FlexCAN memory | ||
| 3867 | * 0b0..Keep the write access restricted in some regions of FlexCAN memory | ||
| 3868 | */ | ||
| 3869 | #define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) | ||
| 3870 | /*! @} */ | ||
| 3871 | |||
| 3872 | /*! @name ESR2 - Error and Status 2 Register */ | ||
| 3873 | /*! @{ */ | ||
| 3874 | #define CAN_ESR2_IMB_MASK (0x2000U) | ||
| 3875 | #define CAN_ESR2_IMB_SHIFT (13U) | ||
| 3876 | /*! IMB | ||
| 3877 | * 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. | ||
| 3878 | * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. | ||
| 3879 | */ | ||
| 3880 | #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) | ||
| 3881 | #define CAN_ESR2_VPS_MASK (0x4000U) | ||
| 3882 | #define CAN_ESR2_VPS_SHIFT (14U) | ||
| 3883 | /*! VPS | ||
| 3884 | * 0b1..Contents of IMB and LPTM are valid | ||
| 3885 | * 0b0..Contents of IMB and LPTM are invalid | ||
| 3886 | */ | ||
| 3887 | #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) | ||
| 3888 | #define CAN_ESR2_LPTM_MASK (0x7F0000U) | ||
| 3889 | #define CAN_ESR2_LPTM_SHIFT (16U) | ||
| 3890 | #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) | ||
| 3891 | /*! @} */ | ||
| 3892 | |||
| 3893 | /*! @name CRCR - CRC Register */ | ||
| 3894 | /*! @{ */ | ||
| 3895 | #define CAN_CRCR_TXCRC_MASK (0x7FFFU) | ||