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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/project_template/board.c
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1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "fsl_debug_console.h"
10#include "board.h"
11#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12#include "fsl_lpi2c.h"
13#endif /* SDK_I2C_BASED_COMPONENT_USED */
14#if defined BOARD_USE_CODEC
15#include "fsl_wm8960.h"
16#endif
17#include "fsl_iomuxc.h"
18
19/*******************************************************************************
20 * Variables
21 ******************************************************************************/
22#if defined BOARD_USE_CODEC
23codec_config_t boardCodecConfig = {.I2C_SendFunc = BOARD_Codec_I2C_Send,
24 .I2C_ReceiveFunc = BOARD_Codec_I2C_Receive,
25 .op.Init = WM8960_Init,
26 .op.Deinit = WM8960_Deinit,
27 .op.SetFormat = WM8960_ConfigDataFormat};
28#endif
29/*******************************************************************************
30 * Code
31 ******************************************************************************/
32
33/* Get debug console frequency. */
34uint32_t BOARD_DebugConsoleSrcFreq(void)
35{
36 uint32_t freq;
37
38 /* To make it simple, we assume default PLL and divider settings, and the only variable
39 from application is use PLL3 source or OSC source */
40 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
41 {
42 freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
43 }
44 else
45 {
46 freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
47 }
48
49 return freq;
50}
51
52/* Initialize debug console. */
53void BOARD_InitDebugConsole(void)
54{
55 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
56
57 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
58}
59
60#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
61void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
62{
63 lpi2c_master_config_t lpi2cConfig = {0};
64
65 /*
66 * lpi2cConfig.debugEnable = false;
67 * lpi2cConfig.ignoreAck = false;
68 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
69 * lpi2cConfig.baudRate_Hz = 100000U;
70 * lpi2cConfig.busIdleTimeout_ns = 0;
71 * lpi2cConfig.pinLowTimeout_ns = 0;
72 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
73 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
74 */
75 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
76 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
77}
78
79status_t BOARD_LPI2C_Send(LPI2C_Type *base,
80 uint8_t deviceAddress,
81 uint32_t subAddress,
82 uint8_t subAddressSize,
83 uint8_t *txBuff,
84 uint8_t txBuffSize)
85{
86 status_t reVal;
87
88 /* Send master blocking data to slave */
89 reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
90 if (kStatus_Success == reVal)
91 {
92 while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
93 {
94 }
95
96 reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
97 if (reVal != kStatus_Success)
98 {
99 return reVal;
100 }
101
102 reVal = LPI2C_MasterSend(base, txBuff, txBuffSize);
103 if (reVal != kStatus_Success)
104 {
105 return reVal;
106 }
107
108 reVal = LPI2C_MasterStop(base);
109 if (reVal != kStatus_Success)
110 {
111 return reVal;
112 }
113 }
114
115 return reVal;
116}
117
118status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
119 uint8_t deviceAddress,
120 uint32_t subAddress,
121 uint8_t subAddressSize,
122 uint8_t *rxBuff,
123 uint8_t rxBuffSize)
124{
125 status_t reVal;
126
127 reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
128 if (kStatus_Success == reVal)
129 {
130 while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
131 {
132 }
133
134 reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
135 if (reVal != kStatus_Success)
136 {
137 return reVal;
138 }
139
140 reVal = LPI2C_MasterRepeatedStart(base, deviceAddress, kLPI2C_Read);
141
142 if (reVal != kStatus_Success)
143 {
144 return reVal;
145 }
146
147 reVal = LPI2C_MasterReceive(base, rxBuff, rxBuffSize);
148 if (reVal != kStatus_Success)
149 {
150 return reVal;
151 }
152
153 reVal = LPI2C_MasterStop(base);
154 if (reVal != kStatus_Success)
155 {
156 return reVal;
157 }
158 }
159 return reVal;
160}
161
162status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
163 uint8_t deviceAddress,
164 uint32_t subAddress,
165 uint8_t subAddressSize,
166 uint8_t *txBuff,
167 uint8_t txBuffSize)
168{
169 return BOARD_LPI2C_Send(base, deviceAddress, subAddress, subAddressSize, txBuff, txBuffSize);
170}
171
172status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
173 uint8_t deviceAddress,
174 uint32_t subAddress,
175 uint8_t subAddressSize,
176 uint8_t *rxBuff,
177 uint8_t rxBuffSize)
178{
179 status_t reVal;
180
181 reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
182 if (kStatus_Success == reVal)
183 {
184 while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
185 {
186 }
187
188 reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
189 if (reVal != kStatus_Success)
190 {
191 return reVal;
192 }
193
194 /* SCCB does not support LPI2C repeat start, must stop then start. */
195 reVal = LPI2C_MasterStop(base);
196
197 if (reVal != kStatus_Success)
198 {
199 return reVal;
200 }
201
202 reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Read);
203
204 if (reVal != kStatus_Success)
205 {
206 return reVal;
207 }
208
209 reVal = LPI2C_MasterReceive(base, rxBuff, rxBuffSize);
210 if (reVal != kStatus_Success)
211 {
212 return reVal;
213 }
214
215 reVal = LPI2C_MasterStop(base);
216 if (reVal != kStatus_Success)
217 {
218 return reVal;
219 }
220 }
221 return reVal;
222}
223
224void BOARD_Accel_I2C_Init(void)
225{
226 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
227}
228
229status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
230{
231 uint8_t data = (uint8_t)txBuff;
232
233 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
234}
235
236status_t BOARD_Accel_I2C_Receive(
237 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
238{
239 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
240}
241
242void BOARD_Codec_I2C_Init(void)
243{
244 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
245}
246
247status_t BOARD_Codec_I2C_Send(
248 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
249{
250 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
251 txBuffSize);
252}
253
254status_t BOARD_Codec_I2C_Receive(
255 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
256{
257 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
258}
259
260void BOARD_Camera_I2C_Init(void)
261{
262 CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
263 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
264 BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
265}
266
267status_t BOARD_Camera_I2C_Send(
268 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
269{
270 return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
271 txBuffSize);
272}
273
274status_t BOARD_Camera_I2C_Receive(
275 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
276{
277 return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
278 rxBuffSize);
279}
280
281status_t BOARD_Camera_I2C_SendSCCB(
282 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
283{
284 return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
285 txBuffSize);
286}
287
288status_t BOARD_Camera_I2C_ReceiveSCCB(
289 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
290{
291 return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
292 rxBuffSize);
293}
294#endif /* SDK_I2C_BASED_COMPONENT_USED */
295
296/* MPU configuration. */
297void BOARD_ConfigMPU(void)
298{
299 /* Disable I cache and D cache */
300 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
301 {
302 SCB_DisableICache();
303 }
304 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
305 {
306 SCB_DisableDCache();
307 }
308
309 /* Disable MPU */
310 ARM_MPU_Disable();
311
312 /* MPU configure:
313 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
314 * SubRegionDisable, Size)
315 * API in core_cm7.h.
316 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
317 * disabled.
318 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
319 * Privileged mode.
320 * Use MACROS defined in core_cm7.h:
321 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
322 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
323 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
324 * 0 x 0 0 Strongly Ordered shareable
325 * 0 x 0 1 Device shareable
326 * 0 0 1 0 Normal not shareable Outer and inner write
327 * through no write allocate
328 * 0 0 1 1 Normal not shareable Outer and inner write
329 * back no write allocate
330 * 0 1 1 0 Normal shareable Outer and inner write
331 * through no write allocate
332 * 0 1 1 1 Normal shareable Outer and inner write
333 * back no write allocate
334 * 1 0 0 0 Normal not shareable outer and inner
335 * noncache
336 * 1 1 0 0 Normal shareable outer and inner
337 * noncache
338 * 1 0 1 1 Normal not shareable outer and inner write
339 * back write/read acllocate
340 * 1 1 1 1 Normal shareable outer and inner write
341 * back write/read acllocate
342 * 2 x 0 0 Device not shareable
343 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
344 * policy.
345 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
346 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
347 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
348 * core_cm7.h.
349 */
350
351 /* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
352 MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
353 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
354
355 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
356 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
357 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
358
359/* Region 2 setting */
360#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
361 /* Setting Memory with Normal type, not shareable, outer/inner write back. */
362 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
363 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
364#else
365 /* Setting Memory with Device type, not shareable, non-cacheable. */
366 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
367 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_8MB);
368#endif
369
370 /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
371 MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
372 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
373
374 /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
375 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
376 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
377
378 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
379 MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
380 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
381
382 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
383 MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
384 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
385
386 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
387 MPU->RBAR = ARM_MPU_RBAR(7, 0x20280000U);
388 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
389
390/* The define sets the cacheable memory to shareable,
391 * this suggestion is referred from chapter 2.2.1 Memory regions,
392 * types and attributes in Cortex-M7 Devices, Generic User Guide */
393#if defined(SDRAM_IS_SHAREABLE)
394 /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
395 MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
396 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
397#else
398 /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
399 MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
400 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
401#endif
402
403 /* Region 9 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be
404 * accessed by cache can be put here */
405 /* Memory with Normal type, not shareable, non-cacheable */
406 MPU->RBAR = ARM_MPU_RBAR(9, 0x81E00000U);
407 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
408
409 /* Enable MPU */
410 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
411
412 /* Enable I cache and D cache */
413 SCB_EnableDCache();
414 SCB_EnableICache();
415}
416
417void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength)
418{
419 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
420 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
421 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
422 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
423 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
424 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
425 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
426 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
427 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
428 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
429 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
430 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
431 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
432 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
433 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
434 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
435 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
436 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
437 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
438 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
439 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
440 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
441 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
442 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
443 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
444 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
445 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
446 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
447 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
448}
449
450void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength)
451{
452}
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