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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/MIMXRT1061.h45196
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/MIMXRT1061_features.h707
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/arm/MIMXRT106x_QSPI_4KB_SEC.FLMbin0 -> 2847664 bytes
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/drivers/driver_reset.cmake14
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/drivers/fsl_clock.c1526
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/drivers/fsl_clock.h1766
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/drivers/fsl_flexram_allocate.c157
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/drivers/fsl_flexram_allocate.h99
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/drivers/fsl_iomuxc.h1419
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/drivers/fsl_romapi.c196
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/drivers/fsl_romapi.h640
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/fsl_device_registers.h36
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/gcc/MIMXRT1061xxxxx_flexspi_nor.ld258
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/gcc/MIMXRT1061xxxxx_flexspi_nor_sdram.ld261
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/gcc/MIMXRT1061xxxxx_ram.ld225
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/gcc/MIMXRT1061xxxxx_sdram.ld228
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/gcc/MIMXRT1061xxxxx_sdram_txt.ld228
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/gcc/startup_MIMXRT1061.S1128
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/mcuxpresso/startup_mimxrt1061.c1436
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/mcuxpresso/startup_mimxrt1061.cpp1436
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/project_template/board.c452
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/project_template/board.h271
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/project_template/clock_config.c476
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/project_template/clock_config.h120
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/project_template/peripherals.c51
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/project_template/peripherals.h34
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/project_template/pin_mux.c55
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/project_template/pin_mux.h65
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/system_MIMXRT1061.c245
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/system_MIMXRT1061.h125
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/utilities/fsl_notifier.c209
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/utilities/fsl_notifier.h237
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/utilities/fsl_shell.c1085
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/utilities/fsl_shell.h292
34 files changed, 60673 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/MIMXRT1061.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/MIMXRT1061.h
new file mode 100644
index 000000000..25c586a62
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/MIMXRT1061.h
@@ -0,0 +1,45196 @@
1/*
2** ###################################################################
3** Processors: MIMXRT1061CVJ5A
4** MIMXRT1061CVL5A
5** MIMXRT1061DVJ6A
6** MIMXRT1061DVL6A
7**
8** Compilers: Freescale C/C++ for Embedded ARM
9** GNU C Compiler
10** IAR ANSI C/C++ Compiler for ARM
11** Keil ARM C/C++ Compiler
12** MCUXpresso Compiler
13**
14** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
15** Version: rev. 1.2, 2019-04-29
16** Build: b201019
17**
18** Abstract:
19** CMSIS Peripheral Access Layer for MIMXRT1061
20**
21** Copyright 1997-2016 Freescale Semiconductor, Inc.
22** Copyright 2016-2020 NXP
23** All rights reserved.
24**
25** SPDX-License-Identifier: BSD-3-Clause
26**
27** http: www.nxp.com
28** mail: [email protected]
29**
30** Revisions:
31** - rev. 0.1 (2017-01-10)
32** Initial version.
33** - rev. 1.0 (2018-11-16)
34** Update header files to align with IMXRT1060RM Rev.0.
35** - rev. 1.1 (2018-11-27)
36** Update header files to align with IMXRT1060RM Rev.1.
37** - rev. 1.2 (2019-04-29)
38** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
39**
40** ###################################################################
41*/
42
43/*!
44 * @file MIMXRT1061.h
45 * @version 1.2
46 * @date 2019-04-29
47 * @brief CMSIS Peripheral Access Layer for MIMXRT1061
48 *
49 * CMSIS Peripheral Access Layer for MIMXRT1061
50 */
51
52#ifndef _MIMXRT1061_H_
53#define _MIMXRT1061_H_ /**< Symbol preventing repeated inclusion */
54
55/** Memory map major version (memory maps with equal major version number are
56 * compatible) */
57#define MCU_MEM_MAP_VERSION 0x0100U
58/** Memory map minor version */
59#define MCU_MEM_MAP_VERSION_MINOR 0x0002U
60
61
62/* ----------------------------------------------------------------------------
63 -- Interrupt vector numbers
64 ---------------------------------------------------------------------------- */
65
66/*!
67 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
68 * @{
69 */
70
71/** Interrupt Number Definitions */
72#define NUMBER_OF_INT_VECTORS 174 /**< Number of interrupts in the Vector table */
73
74typedef enum IRQn {
75 /* Auxiliary constants */
76 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
77
78 /* Core interrupts */
79 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
80 HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */
81 MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */
82 BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */
83 UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */
84 SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */
85 DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */
86 PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */
87 SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */
88
89 /* Device specific interrupts */
90 DMA0_DMA16_IRQn = 0, /**< DMA channel 0/16 transfer complete */
91 DMA1_DMA17_IRQn = 1, /**< DMA channel 1/17 transfer complete */
92 DMA2_DMA18_IRQn = 2, /**< DMA channel 2/18 transfer complete */
93 DMA3_DMA19_IRQn = 3, /**< DMA channel 3/19 transfer complete */
94 DMA4_DMA20_IRQn = 4, /**< DMA channel 4/20 transfer complete */
95 DMA5_DMA21_IRQn = 5, /**< DMA channel 5/21 transfer complete */
96 DMA6_DMA22_IRQn = 6, /**< DMA channel 6/22 transfer complete */
97 DMA7_DMA23_IRQn = 7, /**< DMA channel 7/23 transfer complete */
98 DMA8_DMA24_IRQn = 8, /**< DMA channel 8/24 transfer complete */
99 DMA9_DMA25_IRQn = 9, /**< DMA channel 9/25 transfer complete */
100 DMA10_DMA26_IRQn = 10, /**< DMA channel 10/26 transfer complete */
101 DMA11_DMA27_IRQn = 11, /**< DMA channel 11/27 transfer complete */
102 DMA12_DMA28_IRQn = 12, /**< DMA channel 12/28 transfer complete */
103 DMA13_DMA29_IRQn = 13, /**< DMA channel 13/29 transfer complete */
104 DMA14_DMA30_IRQn = 14, /**< DMA channel 14/30 transfer complete */
105 DMA15_DMA31_IRQn = 15, /**< DMA channel 15/31 transfer complete */
106 DMA_ERROR_IRQn = 16, /**< DMA error interrupt channels 0-15 / 16-31 */
107 CTI0_ERROR_IRQn = 17, /**< CTI0_Error */
108 CTI1_ERROR_IRQn = 18, /**< CTI1_Error */
109 CORE_IRQn = 19, /**< CorePlatform exception IRQ */
110 LPUART1_IRQn = 20, /**< LPUART1 TX interrupt and RX interrupt */
111 LPUART2_IRQn = 21, /**< LPUART2 TX interrupt and RX interrupt */
112 LPUART3_IRQn = 22, /**< LPUART3 TX interrupt and RX interrupt */
113 LPUART4_IRQn = 23, /**< LPUART4 TX interrupt and RX interrupt */
114 LPUART5_IRQn = 24, /**< LPUART5 TX interrupt and RX interrupt */
115 LPUART6_IRQn = 25, /**< LPUART6 TX interrupt and RX interrupt */
116 LPUART7_IRQn = 26, /**< LPUART7 TX interrupt and RX interrupt */
117 LPUART8_IRQn = 27, /**< LPUART8 TX interrupt and RX interrupt */
118 LPI2C1_IRQn = 28, /**< LPI2C1 interrupt */
119 LPI2C2_IRQn = 29, /**< LPI2C2 interrupt */
120 LPI2C3_IRQn = 30, /**< LPI2C3 interrupt */
121 LPI2C4_IRQn = 31, /**< LPI2C4 interrupt */
122 LPSPI1_IRQn = 32, /**< LPSPI1 single interrupt vector for all sources */
123 LPSPI2_IRQn = 33, /**< LPSPI2 single interrupt vector for all sources */
124 LPSPI3_IRQn = 34, /**< LPSPI3 single interrupt vector for all sources */
125 LPSPI4_IRQn = 35, /**< LPSPI4 single interrupt vector for all sources */
126 CAN1_IRQn = 36, /**< CAN1 interrupt */
127 CAN2_IRQn = 37, /**< CAN2 interrupt */
128 FLEXRAM_IRQn = 38, /**< FlexRAM address out of range Or access hit IRQ */
129 KPP_IRQn = 39, /**< Keypad nterrupt */
130 TSC_DIG_IRQn = 40, /**< TSC interrupt */
131 GPR_IRQ_IRQn = 41, /**< GPR interrupt */
132 Reserved58_IRQn = 42, /**< Reserved interrupt */
133 Reserved59_IRQn = 43, /**< Reserved interrupt */
134 Reserved60_IRQn = 44, /**< Reserved interrupt */
135 WDOG2_IRQn = 45, /**< WDOG2 interrupt */
136 SNVS_HP_WRAPPER_IRQn = 46, /**< SRTC Consolidated Interrupt. Non TZ */
137 SNVS_HP_WRAPPER_TZ_IRQn = 47, /**< SRTC Security Interrupt. TZ */
138 SNVS_LP_WRAPPER_IRQn = 48, /**< ON-OFF button press shorter than 5 secs (pulse event) */
139 CSU_IRQn = 49, /**< CSU interrupt */
140 DCP_IRQn = 50, /**< DCP_IRQ interrupt */
141 DCP_VMI_IRQn = 51, /**< DCP_VMI_IRQ interrupt */
142 Reserved68_IRQn = 52, /**< Reserved interrupt */
143 TRNG_IRQn = 53, /**< TRNG interrupt */
144 SJC_IRQn = 54, /**< SJC interrupt */
145 BEE_IRQn = 55, /**< BEE interrupt */
146 SAI1_IRQn = 56, /**< SAI1 interrupt */
147 SAI2_IRQn = 57, /**< SAI1 interrupt */
148 SAI3_RX_IRQn = 58, /**< SAI3 interrupt */
149 SAI3_TX_IRQn = 59, /**< SAI3 interrupt */
150 SPDIF_IRQn = 60, /**< SPDIF interrupt */
151 PMU_EVENT_IRQn = 61, /**< Brown-out event interrupt */
152 Reserved78_IRQn = 62, /**< Reserved interrupt */
153 TEMP_LOW_HIGH_IRQn = 63, /**< TempSensor low/high interrupt */
154 TEMP_PANIC_IRQn = 64, /**< TempSensor panic interrupt */
155 USB_PHY1_IRQn = 65, /**< USBPHY (UTMI0), Interrupt */
156 USB_PHY2_IRQn = 66, /**< USBPHY (UTMI1), Interrupt */
157 ADC1_IRQn = 67, /**< ADC1 interrupt */
158 ADC2_IRQn = 68, /**< ADC2 interrupt */
159 DCDC_IRQn = 69, /**< DCDC interrupt */
160 Reserved86_IRQn = 70, /**< Reserved interrupt */
161 Reserved87_IRQn = 71, /**< Reserved interrupt */
162 GPIO1_INT0_IRQn = 72, /**< Active HIGH Interrupt from INT0 from GPIO */
163 GPIO1_INT1_IRQn = 73, /**< Active HIGH Interrupt from INT1 from GPIO */
164 GPIO1_INT2_IRQn = 74, /**< Active HIGH Interrupt from INT2 from GPIO */
165 GPIO1_INT3_IRQn = 75, /**< Active HIGH Interrupt from INT3 from GPIO */
166 GPIO1_INT4_IRQn = 76, /**< Active HIGH Interrupt from INT4 from GPIO */
167 GPIO1_INT5_IRQn = 77, /**< Active HIGH Interrupt from INT5 from GPIO */
168 GPIO1_INT6_IRQn = 78, /**< Active HIGH Interrupt from INT6 from GPIO */
169 GPIO1_INT7_IRQn = 79, /**< Active HIGH Interrupt from INT7 from GPIO */
170 GPIO1_Combined_0_15_IRQn = 80, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
171 GPIO1_Combined_16_31_IRQn = 81, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
172 GPIO2_Combined_0_15_IRQn = 82, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
173 GPIO2_Combined_16_31_IRQn = 83, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
174 GPIO3_Combined_0_15_IRQn = 84, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
175 GPIO3_Combined_16_31_IRQn = 85, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
176 GPIO4_Combined_0_15_IRQn = 86, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */
177 GPIO4_Combined_16_31_IRQn = 87, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */
178 GPIO5_Combined_0_15_IRQn = 88, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
179 GPIO5_Combined_16_31_IRQn = 89, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
180 FLEXIO1_IRQn = 90, /**< FLEXIO1 interrupt */
181 FLEXIO2_IRQn = 91, /**< FLEXIO2 interrupt */
182 WDOG1_IRQn = 92, /**< WDOG1 interrupt */
183 RTWDOG_IRQn = 93, /**< RTWDOG interrupt */
184 EWM_IRQn = 94, /**< EWM interrupt */
185 CCM_1_IRQn = 95, /**< CCM IRQ1 interrupt */
186 CCM_2_IRQn = 96, /**< CCM IRQ2 interrupt */
187 GPC_IRQn = 97, /**< GPC interrupt */
188 SRC_IRQn = 98, /**< SRC interrupt */
189 Reserved115_IRQn = 99, /**< Reserved interrupt */
190 GPT1_IRQn = 100, /**< GPT1 interrupt */
191 GPT2_IRQn = 101, /**< GPT2 interrupt */
192 PWM1_0_IRQn = 102, /**< PWM1 capture 0, compare 0, or reload 0 interrupt */
193 PWM1_1_IRQn = 103, /**< PWM1 capture 1, compare 1, or reload 0 interrupt */
194 PWM1_2_IRQn = 104, /**< PWM1 capture 2, compare 2, or reload 0 interrupt */
195 PWM1_3_IRQn = 105, /**< PWM1 capture 3, compare 3, or reload 0 interrupt */
196 PWM1_FAULT_IRQn = 106, /**< PWM1 fault or reload error interrupt */
197 FLEXSPI2_IRQn = 107, /**< FlexSPI2 interrupt */
198 FLEXSPI_IRQn = 108, /**< FlexSPI0 interrupt */
199 SEMC_IRQn = 109, /**< Reserved interrupt */
200 USDHC1_IRQn = 110, /**< USDHC1 interrupt */
201 USDHC2_IRQn = 111, /**< USDHC2 interrupt */
202 USB_OTG2_IRQn = 112, /**< USBO2 USB OTG2 */
203 USB_OTG1_IRQn = 113, /**< USBO2 USB OTG1 */
204 ENET_IRQn = 114, /**< ENET interrupt */
205 ENET_1588_Timer_IRQn = 115, /**< ENET_1588_Timer interrupt */
206 XBAR1_IRQ_0_1_IRQn = 116, /**< XBAR1 interrupt */
207 XBAR1_IRQ_2_3_IRQn = 117, /**< XBAR1 interrupt */
208 ADC_ETC_IRQ0_IRQn = 118, /**< ADCETC IRQ0 interrupt */
209 ADC_ETC_IRQ1_IRQn = 119, /**< ADCETC IRQ1 interrupt */
210 ADC_ETC_IRQ2_IRQn = 120, /**< ADCETC IRQ2 interrupt */
211 ADC_ETC_ERROR_IRQ_IRQn = 121, /**< ADCETC Error IRQ interrupt */
212 PIT_IRQn = 122, /**< PIT interrupt */
213 ACMP1_IRQn = 123, /**< ACMP interrupt */
214 ACMP2_IRQn = 124, /**< ACMP interrupt */
215 ACMP3_IRQn = 125, /**< ACMP interrupt */
216 ACMP4_IRQn = 126, /**< ACMP interrupt */
217 Reserved143_IRQn = 127, /**< Reserved interrupt */
218 Reserved144_IRQn = 128, /**< Reserved interrupt */
219 ENC1_IRQn = 129, /**< ENC1 interrupt */
220 ENC2_IRQn = 130, /**< ENC2 interrupt */
221 ENC3_IRQn = 131, /**< ENC3 interrupt */
222 ENC4_IRQn = 132, /**< ENC4 interrupt */
223 TMR1_IRQn = 133, /**< TMR1 interrupt */
224 TMR2_IRQn = 134, /**< TMR2 interrupt */
225 TMR3_IRQn = 135, /**< TMR3 interrupt */
226 TMR4_IRQn = 136, /**< TMR4 interrupt */
227 PWM2_0_IRQn = 137, /**< PWM2 capture 0, compare 0, or reload 0 interrupt */
228 PWM2_1_IRQn = 138, /**< PWM2 capture 1, compare 1, or reload 0 interrupt */
229 PWM2_2_IRQn = 139, /**< PWM2 capture 2, compare 2, or reload 0 interrupt */
230 PWM2_3_IRQn = 140, /**< PWM2 capture 3, compare 3, or reload 0 interrupt */
231 PWM2_FAULT_IRQn = 141, /**< PWM2 fault or reload error interrupt */
232 PWM3_0_IRQn = 142, /**< PWM3 capture 0, compare 0, or reload 0 interrupt */
233 PWM3_1_IRQn = 143, /**< PWM3 capture 1, compare 1, or reload 0 interrupt */
234 PWM3_2_IRQn = 144, /**< PWM3 capture 2, compare 2, or reload 0 interrupt */
235 PWM3_3_IRQn = 145, /**< PWM3 capture 3, compare 3, or reload 0 interrupt */
236 PWM3_FAULT_IRQn = 146, /**< PWM3 fault or reload error interrupt */
237 PWM4_0_IRQn = 147, /**< PWM4 capture 0, compare 0, or reload 0 interrupt */
238 PWM4_1_IRQn = 148, /**< PWM4 capture 1, compare 1, or reload 0 interrupt */
239 PWM4_2_IRQn = 149, /**< PWM4 capture 2, compare 2, or reload 0 interrupt */
240 PWM4_3_IRQn = 150, /**< PWM4 capture 3, compare 3, or reload 0 interrupt */
241 PWM4_FAULT_IRQn = 151, /**< PWM4 fault or reload error interrupt */
242 ENET2_IRQn = 152, /**< ENET2 interrupt */
243 ENET2_1588_Timer_IRQn = 153, /**< ENET2_1588_Timer interrupt */
244 CAN3_IRQn = 154, /**< CAN3 interrupt */
245 Reserved171_IRQn = 155, /**< Reserved interrupt */
246 FLEXIO3_IRQn = 156, /**< FLEXIO3 interrupt */
247 GPIO6_7_8_9_IRQn = 157 /**< GPIO6, GPIO7, GPIO8, GPIO9 interrupt */
248} IRQn_Type;
249
250/*!
251 * @}
252 */ /* end of group Interrupt_vector_numbers */
253
254
255/* ----------------------------------------------------------------------------
256 -- Cortex M7 Core Configuration
257 ---------------------------------------------------------------------------- */
258
259/*!
260 * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration
261 * @{
262 */
263
264#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
265#define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */
266#define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */
267#define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */
268#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
269#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
270#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
271
272#include "core_cm7.h" /* Core Peripheral Access Layer */
273#include "system_MIMXRT1061.h" /* Device specific configuration file */
274
275/*!
276 * @}
277 */ /* end of group Cortex_Core_Configuration */
278
279
280/* ----------------------------------------------------------------------------
281 -- Mapping Information
282 ---------------------------------------------------------------------------- */
283
284/*!
285 * @addtogroup Mapping_Information Mapping Information
286 * @{
287 */
288
289/** Mapping Information */
290/*!
291 * @addtogroup edma_request
292 * @{
293 */
294
295/*******************************************************************************
296 * Definitions
297 ******************************************************************************/
298
299/*!
300 * @brief Structure for the DMA hardware request
301 *
302 * Defines the structure for the DMA hardware request collections. The user can configure the
303 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
304 * of the hardware request varies according to the to SoC.
305 */
306typedef enum _dma_request_source
307{
308 kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */
309 kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 Request0 and Request1 */
310 kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */
311 kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */
312 kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */
313 kDmaRequestMuxLPUART3Rx = 5|0x100U, /**< LPUART3 Receive */
314 kDmaRequestMuxLPUART5Tx = 6|0x100U, /**< LPUART5 Transmit */
315 kDmaRequestMuxLPUART5Rx = 7|0x100U, /**< LPUART5 Receive */
316 kDmaRequestMuxLPUART7Tx = 8|0x100U, /**< LPUART7 Transmit */
317 kDmaRequestMuxLPUART7Rx = 9|0x100U, /**< LPUART7 Receive */
318 kDmaRequestMuxCAN3 = 11|0x100U, /**< CAN3 */
319 kDmaRequestMuxLPSPI1Rx = 13|0x100U, /**< LPSPI1 Receive */
320 kDmaRequestMuxLPSPI1Tx = 14|0x100U, /**< LPSPI1 Transmit */
321 kDmaRequestMuxLPSPI3Rx = 15|0x100U, /**< LPSPI3 Receive */
322 kDmaRequestMuxLPSPI3Tx = 16|0x100U, /**< LPSPI3 Transmit */
323 kDmaRequestMuxLPI2C1 = 17|0x100U, /**< LPI2C1 */
324 kDmaRequestMuxLPI2C3 = 18|0x100U, /**< LPI2C3 */
325 kDmaRequestMuxSai1Rx = 19|0x100U, /**< SAI1 Receive */
326 kDmaRequestMuxSai1Tx = 20|0x100U, /**< SAI1 Transmit */
327 kDmaRequestMuxSai2Rx = 21|0x100U, /**< SAI2 Receive */
328 kDmaRequestMuxSai2Tx = 22|0x100U, /**< SAI2 Transmit */
329 kDmaRequestMuxADC_ETC = 23|0x100U, /**< ADC_ETC */
330 kDmaRequestMuxADC1 = 24|0x100U, /**< ADC1 */
331 kDmaRequestMuxACMP1 = 25|0x100U, /**< ACMP1 */
332 kDmaRequestMuxACMP3 = 26|0x100U, /**< ACMP3 */
333 kDmaRequestMuxFlexSPIRx = 28|0x100U, /**< FlexSPI Receive */
334 kDmaRequestMuxFlexSPITx = 29|0x100U, /**< FlexSPI Transmit */
335 kDmaRequestMuxXBAR1Request0 = 30|0x100U, /**< XBAR1 Request 0 */
336 kDmaRequestMuxXBAR1Request1 = 31|0x100U, /**< XBAR1 Request 1 */
337 kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, /**< FlexPWM1 Capture sub-module0 */
338 kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U, /**< FlexPWM1 Capture sub-module1 */
339 kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, /**< FlexPWM1 Capture sub-module2 */
340 kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, /**< FlexPWM1 Capture sub-module3 */
341 kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U, /**< FlexPWM1 Value sub-module0 */
342 kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U, /**< FlexPWM1 Value sub-module1 */
343 kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U, /**< FlexPWM1 Value sub-module2 */
344 kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U, /**< FlexPWM1 Value sub-module3 */
345 kDmaRequestMuxFlexPWM3CaptureSub0 = 40|0x100U, /**< FlexPWM3 Capture sub-module0 */
346 kDmaRequestMuxFlexPWM3CaptureSub1 = 41|0x100U, /**< FlexPWM3 Capture sub-module1 */
347 kDmaRequestMuxFlexPWM3CaptureSub2 = 42|0x100U, /**< FlexPWM3 Capture sub-module2 */
348 kDmaRequestMuxFlexPWM3CaptureSub3 = 43|0x100U, /**< FlexPWM3 Capture sub-module3 */
349 kDmaRequestMuxFlexPWM3ValueSub0 = 44|0x100U, /**< FlexPWM3 Value sub-module0 */
350 kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U, /**< FlexPWM3 Value sub-module1 */
351 kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U, /**< FlexPWM3 Value sub-module2 */
352 kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U, /**< FlexPWM3 Value sub-module3 */
353 kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< TMR1 Capture timer 0 */
354 kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< TMR1 Capture timer 1 */
355 kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< TMR1 Capture timer 2 */
356 kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< TMR1 Capture timer 3 */
357 kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */
358 kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */
359 kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */
360 kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */
361 kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, /**< TMR3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */
362 kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 57|0x100U, /**< TMR3 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */
363 kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 58|0x100U, /**< TMR3 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */
364 kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U, /**< TMR3 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */
365 kDmaRequestMuxFlexSPI2Rx = 60|0x100U, /**< FlexSPI2 Receive */
366 kDmaRequestMuxFlexSPI2Tx = 61|0x100U, /**< FlexSPI2 Transmit */
367 kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */
368 kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 Request2 and Request3 */
369 kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */
370 kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */
371 kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */
372 kDmaRequestMuxLPUART4Rx = 69|0x100U, /**< LPUART4 Receive */
373 kDmaRequestMuxLPUART6Tx = 70|0x100U, /**< LPUART6 Transmit */
374 kDmaRequestMuxLPUART6Rx = 71|0x100U, /**< LPUART6 Receive */
375 kDmaRequestMuxLPUART8Tx = 72|0x100U, /**< LPUART8 Transmit */
376 kDmaRequestMuxLPUART8Rx = 73|0x100U, /**< LPUART8 Receive */
377 kDmaRequestMuxLPSPI2Rx = 77|0x100U, /**< LPSPI2 Receive */
378 kDmaRequestMuxLPSPI2Tx = 78|0x100U, /**< LPSPI2 Transmit */
379 kDmaRequestMuxLPSPI4Rx = 79|0x100U, /**< LPSPI4 Receive */
380 kDmaRequestMuxLPSPI4Tx = 80|0x100U, /**< LPSPI4 Transmit */
381 kDmaRequestMuxLPI2C2 = 81|0x100U, /**< LPI2C2 */
382 kDmaRequestMuxLPI2C4 = 82|0x100U, /**< LPI2C4 */
383 kDmaRequestMuxSai3Rx = 83|0x100U, /**< SAI3 Receive */
384 kDmaRequestMuxSai3Tx = 84|0x100U, /**< SAI3 Transmit */
385 kDmaRequestMuxSpdifRx = 85|0x100U, /**< SPDIF Receive */
386 kDmaRequestMuxSpdifTx = 86|0x100U, /**< SPDIF Transmit */
387 kDmaRequestMuxADC2 = 88|0x100U, /**< ADC2 */
388 kDmaRequestMuxACMP2 = 89|0x100U, /**< ACMP2 */
389 kDmaRequestMuxACMP4 = 90|0x100U, /**< ACMP4 */
390 kDmaRequestMuxEnetTimer0 = 92|0x100U, /**< ENET Timer0 */
391 kDmaRequestMuxEnetTimer1 = 93|0x100U, /**< ENET Timer1 */
392 kDmaRequestMuxXBAR1Request2 = 94|0x100U, /**< XBAR1 Request 2 */
393 kDmaRequestMuxXBAR1Request3 = 95|0x100U, /**< XBAR1 Request 3 */
394 kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, /**< FlexPWM2 Capture sub-module0 */
395 kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U, /**< FlexPWM2 Capture sub-module1 */
396 kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U, /**< FlexPWM2 Capture sub-module2 */
397 kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U, /**< FlexPWM2 Capture sub-module3 */
398 kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U, /**< FlexPWM2 Value sub-module0 */
399 kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U, /**< FlexPWM2 Value sub-module1 */
400 kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U, /**< FlexPWM2 Value sub-module2 */
401 kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U, /**< FlexPWM2 Value sub-module3 */
402 kDmaRequestMuxFlexPWM4CaptureSub0 = 104|0x100U, /**< FlexPWM4 Capture sub-module0 */
403 kDmaRequestMuxFlexPWM4CaptureSub1 = 105|0x100U, /**< FlexPWM4 Capture sub-module1 */
404 kDmaRequestMuxFlexPWM4CaptureSub2 = 106|0x100U, /**< FlexPWM4 Capture sub-module2 */
405 kDmaRequestMuxFlexPWM4CaptureSub3 = 107|0x100U, /**< FlexPWM4 Capture sub-module3 */
406 kDmaRequestMuxFlexPWM4ValueSub0 = 108|0x100U, /**< FlexPWM4 Value sub-module0 */
407 kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U, /**< FlexPWM4 Value sub-module1 */
408 kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U, /**< FlexPWM4 Value sub-module2 */
409 kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U, /**< FlexPWM4 Value sub-module3 */
410 kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, /**< TMR2 Capture timer 0 */
411 kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, /**< TMR2 Capture timer 1 */
412 kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U, /**< TMR2 Capture timer 2 */
413 kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, /**< TMR2 Capture timer 3 */
414 kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */
415 kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */
416 kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */
417 kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */
418 kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, /**< TMR4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */
419 kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 121|0x100U, /**< TMR4 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */
420 kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 122|0x100U, /**< TMR4 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */
421 kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 123|0x100U, /**< TMR4 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */
422 kDmaRequestMuxEnet2Timer0 = 124|0x100U, /**< ENET2 Timer0 */
423 kDmaRequestMuxEnet2Timer1 = 125|0x100U, /**< ENET2 Timer1 */
424} dma_request_source_t;
425
426/* @} */
427
428/*!
429 * @addtogroup iomuxc_pads
430 * @{ */
431
432/*******************************************************************************
433 * Definitions
434*******************************************************************************/
435
436/*!
437 * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
438 *
439 * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
440 */
441typedef enum _iomuxc_sw_mux_ctl_pad
442{
443 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
444 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
445 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
446 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
447 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
448 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
449 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
450 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
451 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
452 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
453 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
454 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
455 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
456 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
457 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
458 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
459 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */
460 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */
461 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */
462 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */
463 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */
464 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */
465 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */
466 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */
467 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */
468 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */
469 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */
470 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */
471 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */
472 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */
473 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */
474 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */
475 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */
476 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */
477 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */
478 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */
479 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */
480 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */
481 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */
482 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */
483 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */
484 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */
485 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */
486 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */
487 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */
488 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */
489 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */
490 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */
491 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */
492 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */
493 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */
494 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */
495 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */
496 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */
497 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */
498 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */
499 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */
500 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */
501 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */
502 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */
503 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */
504 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */
505 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */
506 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */
507 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */
508 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */
509 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */
510 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */
511 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */
512 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */
513 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */
514 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */
515 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */
516 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */
517 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */
518 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */
519 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */
520 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */
521 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */
522 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */
523 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */
524 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */
525 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */
526 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */
527 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */
528 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */
529 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */
530 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */
531 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */
532 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */
533 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */
534 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */
535 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */
536 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */
537 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */
538 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */
539 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */
540 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */
541 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */
542 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */
543 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */
544 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */
545 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */
546 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */
547 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */
548 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */
549 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */
550 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */
551 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */
552 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */
553 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */
554 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */
555 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */
556 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */
557 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */
558 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */
559 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */
560 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */
561 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */
562 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */
563 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */
564 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */
565 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */
566 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */
567} iomuxc_sw_mux_ctl_pad_t;
568
569/* @} */
570
571/*!
572 * @addtogroup iomuxc_pads
573 * @{ */
574
575/*******************************************************************************
576 * Definitions
577*******************************************************************************/
578
579/*!
580 * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD_1
581 *
582 * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD_1 collections.
583 */
584typedef enum _iomuxc_sw_mux_ctl_pad_1
585{
586 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
587 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
588 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
589 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
590 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
591 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
592 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
593 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
594 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
595 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
596 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
597 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
598 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
599 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
600 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_00 = 14U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
601 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_01 = 15U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
602 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_02 = 16U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
603 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_03 = 17U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
604 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_04 = 18U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
605 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_05 = 19U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
606 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_06 = 20U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
607 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_07 = 21U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
608} iomuxc_sw_mux_ctl_pad_1_t;
609
610/* @} */
611
612/*!
613 * @addtogroup iomuxc_pads
614 * @{ */
615
616/*******************************************************************************
617 * Definitions
618*******************************************************************************/
619
620/*!
621 * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
622 *
623 * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
624 */
625typedef enum _iomuxc_sw_pad_ctl_pad
626{
627 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
628 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
629 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
630 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
631 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
632 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
633 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */
634 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */
635 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */
636 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */
637 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */
638 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */
639 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */
640 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */
641 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */
642 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
643 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */
644 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */
645 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */
646 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */
647 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */
648 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */
649 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */
650 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */
651 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */
652 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */
653 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */
654 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */
655 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */
656 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */
657 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */
658 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */
659 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */
660 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */
661 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */
662 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */
663 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */
664 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */
665 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */
666 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */
667 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */
668 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */
669 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */
670 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */
671 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */
672 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */
673 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */
674 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */
675 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */
676 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */
677 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */
678 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */
679 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */
680 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */
681 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */
682 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */
683 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */
684 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */
685 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */
686 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */
687 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */
688 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */
689 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */
690 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */
691 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */
692 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */
693 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */
694 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */
695 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */
696 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */
697 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */
698 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */
699 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */
700 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */
701 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */
702 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */
703 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */
704 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */
705 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */
706 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */
707 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */
708 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */
709 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */
710 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */
711 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */
712 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */
713 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */
714 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */
715 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */
716 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */
717 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */
718 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */
719 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */
720 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */
721 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */
722 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */
723 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */
724 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */
725 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */
726 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */
727 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */
728 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */
729 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */
730 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */
731 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */
732 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */
733 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */
734 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */
735 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */
736 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */
737 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */
738 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */
739 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_PAD_CTL_PAD index */
740 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */
741 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */
742 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */
743 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */
744 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */
745 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */
746 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */
747 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */
748 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */
749 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */
750 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */
751} iomuxc_sw_pad_ctl_pad_t;
752
753/* @} */
754
755/*!
756 * @addtogroup iomuxc_pads
757 * @{ */
758
759/*******************************************************************************
760 * Definitions
761*******************************************************************************/
762
763/*!
764 * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD_1
765 *
766 * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD_1 collections.
767 */
768typedef enum _iomuxc_sw_pad_ctl_pad_1
769{
770 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
771 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
772 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
773 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
774 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
775 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
776 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
777 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
778 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
779 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
780 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
781 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
782 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
783 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
784 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_00 = 14U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
785 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_01 = 15U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
786 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_02 = 16U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
787 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_03 = 17U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
788 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_04 = 18U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
789 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_05 = 19U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
790 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_06 = 20U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
791 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_07 = 21U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
792} iomuxc_sw_pad_ctl_pad_1_t;
793
794/* @} */
795
796/*!
797 * @brief Enumeration for the IOMUXC select input
798 *
799 * Defines the enumeration for the IOMUXC select input collections.
800 */
801typedef enum _iomuxc_select_input
802{
803 kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */
804 kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U, /**< IOMUXC select input index */
805 kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U, /**< IOMUXC select input index */
806 kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U, /**< IOMUXC select input index */
807 kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U, /**< IOMUXC select input index */
808 kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U, /**< IOMUXC select input index */
809 kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U, /**< IOMUXC select input index */
810 kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U, /**< IOMUXC select input index */
811 kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U, /**< IOMUXC select input index */
812 kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U, /**< IOMUXC select input index */
813 kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U, /**< IOMUXC select input index */
814 kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U, /**< IOMUXC select input index */
815 kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U, /**< IOMUXC select input index */
816 kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U, /**< IOMUXC select input index */
817 kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U, /**< IOMUXC select input index */
818 kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U, /**< IOMUXC select input index */
819 kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U, /**< IOMUXC select input index */
820 kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U, /**< IOMUXC select input index */
821 kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U, /**< IOMUXC select input index */
822 kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U, /**< IOMUXC select input index */
823 kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U, /**< IOMUXC select input index */
824 kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U, /**< IOMUXC select input index */
825 kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U, /**< IOMUXC select input index */
826 kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U, /**< IOMUXC select input index */
827 kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U, /**< IOMUXC select input index */
828 kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U, /**< IOMUXC select input index */
829 kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U, /**< IOMUXC select input index */
830 kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U, /**< IOMUXC select input index */
831 kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U, /**< IOMUXC select input index */
832 kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U, /**< IOMUXC select input index */
833 kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U, /**< IOMUXC select input index */
834 kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U, /**< IOMUXC select input index */
835 kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U, /**< IOMUXC select input index */
836 kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U, /**< IOMUXC select input index */
837 kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U, /**< IOMUXC select input index */
838 kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U, /**< IOMUXC select input index */
839 kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U, /**< IOMUXC select input index */
840 kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U, /**< IOMUXC select input index */
841 kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U, /**< IOMUXC select input index */
842 kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U, /**< IOMUXC select input index */
843 kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U, /**< IOMUXC select input index */
844 kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U, /**< IOMUXC select input index */
845 kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U, /**< IOMUXC select input index */
846 kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U, /**< IOMUXC select input index */
847 kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT = 44U, /**< IOMUXC select input index */
848 kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT = 45U, /**< IOMUXC select input index */
849 kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT = 46U, /**< IOMUXC select input index */
850 kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT = 47U, /**< IOMUXC select input index */
851 kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT = 48U, /**< IOMUXC select input index */
852 kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT = 49U, /**< IOMUXC select input index */
853 kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT = 50U, /**< IOMUXC select input index */
854 kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT = 51U, /**< IOMUXC select input index */
855 kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT = 52U, /**< IOMUXC select input index */
856 kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT = 53U, /**< IOMUXC select input index */
857 kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U, /**< IOMUXC select input index */
858 kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U, /**< IOMUXC select input index */
859 kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U, /**< IOMUXC select input index */
860 kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U, /**< IOMUXC select input index */
861 kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U, /**< IOMUXC select input index */
862 kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U, /**< IOMUXC select input index */
863 kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U, /**< IOMUXC select input index */
864 kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U, /**< IOMUXC select input index */
865 kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U, /**< IOMUXC select input index */
866 kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U, /**< IOMUXC select input index */
867 kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U, /**< IOMUXC select input index */
868 kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U, /**< IOMUXC select input index */
869 kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U, /**< IOMUXC select input index */
870 kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U, /**< IOMUXC select input index */
871 kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U, /**< IOMUXC select input index */
872 kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U, /**< IOMUXC select input index */
873 kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U, /**< IOMUXC select input index */
874 kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U, /**< IOMUXC select input index */
875 kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U, /**< IOMUXC select input index */
876 kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U, /**< IOMUXC select input index */
877 kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U, /**< IOMUXC select input index */
878 kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U, /**< IOMUXC select input index */
879 kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U, /**< IOMUXC select input index */
880 kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U, /**< IOMUXC select input index */
881 kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U, /**< IOMUXC select input index */
882 kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U, /**< IOMUXC select input index */
883 kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U, /**< IOMUXC select input index */
884 kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U, /**< IOMUXC select input index */
885 kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U, /**< IOMUXC select input index */
886 kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U, /**< IOMUXC select input index */
887 kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U, /**< IOMUXC select input index */
888 kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U, /**< IOMUXC select input index */
889 kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U, /**< IOMUXC select input index */
890 kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U, /**< IOMUXC select input index */
891 kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U, /**< IOMUXC select input index */
892 kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U, /**< IOMUXC select input index */
893 kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U, /**< IOMUXC select input index */
894 kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U, /**< IOMUXC select input index */
895 kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U, /**< IOMUXC select input index */
896 kIOMUXC_NMI_SELECT_INPUT = 93U, /**< IOMUXC select input index */
897 kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U, /**< IOMUXC select input index */
898 kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U, /**< IOMUXC select input index */
899 kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U, /**< IOMUXC select input index */
900 kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U, /**< IOMUXC select input index */
901 kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U, /**< IOMUXC select input index */
902 kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U, /**< IOMUXC select input index */
903 kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U, /**< IOMUXC select input index */
904 kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U, /**< IOMUXC select input index */
905 kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U, /**< IOMUXC select input index */
906 kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U, /**< IOMUXC select input index */
907 kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U, /**< IOMUXC select input index */
908 kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U, /**< IOMUXC select input index */
909 kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U, /**< IOMUXC select input index */
910 kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U, /**< IOMUXC select input index */
911 kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U, /**< IOMUXC select input index */
912 kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U, /**< IOMUXC select input index */
913 kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U, /**< IOMUXC select input index */
914 kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U, /**< IOMUXC select input index */
915 kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U, /**< IOMUXC select input index */
916 kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U, /**< IOMUXC select input index */
917 kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U, /**< IOMUXC select input index */
918 kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U, /**< IOMUXC select input index */
919 kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U, /**< IOMUXC select input index */
920 kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U, /**< IOMUXC select input index */
921 kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U, /**< IOMUXC select input index */
922 kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U, /**< IOMUXC select input index */
923 kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U, /**< IOMUXC select input index */
924 kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U, /**< IOMUXC select input index */
925 kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U, /**< IOMUXC select input index */
926 kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U, /**< IOMUXC select input index */
927 kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U, /**< IOMUXC select input index */
928 kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U, /**< IOMUXC select input index */
929 kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U, /**< IOMUXC select input index */
930 kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U, /**< IOMUXC select input index */
931 kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U, /**< IOMUXC select input index */
932 kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U, /**< IOMUXC select input index */
933 kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U, /**< IOMUXC select input index */
934 kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U, /**< IOMUXC select input index */
935 kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U, /**< IOMUXC select input index */
936 kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U, /**< IOMUXC select input index */
937 kIOMUXC_XBAR1_IN02_SELECT_INPUT = 134U, /**< IOMUXC select input index */
938 kIOMUXC_XBAR1_IN03_SELECT_INPUT = 135U, /**< IOMUXC select input index */
939 kIOMUXC_XBAR1_IN04_SELECT_INPUT = 136U, /**< IOMUXC select input index */
940 kIOMUXC_XBAR1_IN05_SELECT_INPUT = 137U, /**< IOMUXC select input index */
941 kIOMUXC_XBAR1_IN06_SELECT_INPUT = 138U, /**< IOMUXC select input index */
942 kIOMUXC_XBAR1_IN07_SELECT_INPUT = 139U, /**< IOMUXC select input index */
943 kIOMUXC_XBAR1_IN08_SELECT_INPUT = 140U, /**< IOMUXC select input index */
944 kIOMUXC_XBAR1_IN09_SELECT_INPUT = 141U, /**< IOMUXC select input index */
945 kIOMUXC_XBAR1_IN17_SELECT_INPUT = 142U, /**< IOMUXC select input index */
946 kIOMUXC_XBAR1_IN18_SELECT_INPUT = 143U, /**< IOMUXC select input index */
947 kIOMUXC_XBAR1_IN20_SELECT_INPUT = 144U, /**< IOMUXC select input index */
948 kIOMUXC_XBAR1_IN22_SELECT_INPUT = 145U, /**< IOMUXC select input index */
949 kIOMUXC_XBAR1_IN23_SELECT_INPUT = 146U, /**< IOMUXC select input index */
950 kIOMUXC_XBAR1_IN24_SELECT_INPUT = 147U, /**< IOMUXC select input index */
951 kIOMUXC_XBAR1_IN14_SELECT_INPUT = 148U, /**< IOMUXC select input index */
952 kIOMUXC_XBAR1_IN15_SELECT_INPUT = 149U, /**< IOMUXC select input index */
953 kIOMUXC_XBAR1_IN16_SELECT_INPUT = 150U, /**< IOMUXC select input index */
954 kIOMUXC_XBAR1_IN25_SELECT_INPUT = 151U, /**< IOMUXC select input index */
955 kIOMUXC_XBAR1_IN19_SELECT_INPUT = 152U, /**< IOMUXC select input index */
956 kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U, /**< IOMUXC select input index */
957} iomuxc_select_input_t;
958
959/*!
960 * @brief Enumeration for the IOMUXC select input
961 *
962 * Defines the enumeration for the IOMUXC select input collections.
963 */
964typedef enum _iomuxc_select_input_1
965{
966 kIOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT = 0U, /**< IOMUXC select input index */
967 kIOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT = 1U, /**< IOMUXC select input index */
968 kIOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_0 = 2U, /**< IOMUXC select input index */
969 kIOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_1 = 3U, /**< IOMUXC select input index */
970 kIOMUXC_ENET2_IPP_IND_MAC0_RXEN_SELECT_INPUT = 4U, /**< IOMUXC select input index */
971 kIOMUXC_ENET2_IPP_IND_MAC0_RXERR_SELECT_INPUT = 5U, /**< IOMUXC select input index */
972 kIOMUXC_ENET2_IPP_IND_MAC0_TIMER_SELECT_INPUT_0 = 6U, /**< IOMUXC select input index */
973 kIOMUXC_ENET2_IPP_IND_MAC0_TXCLK_SELECT_INPUT = 7U, /**< IOMUXC select input index */
974 kIOMUXC_FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT = 8U, /**< IOMUXC select input index */
975 kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT = 9U, /**< IOMUXC select input index */
976 kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT = 10U, /**< IOMUXC select input index */
977 kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT = 11U, /**< IOMUXC select input index */
978 kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT = 12U, /**< IOMUXC select input index */
979 kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT0_SELECT_INPUT = 13U, /**< IOMUXC select input index */
980 kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT1_SELECT_INPUT = 14U, /**< IOMUXC select input index */
981 kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT2_SELECT_INPUT = 15U, /**< IOMUXC select input index */
982 kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT3_SELECT_INPUT = 16U, /**< IOMUXC select input index */
983 kIOMUXC_FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT = 17U, /**< IOMUXC select input index */
984 kIOMUXC_FLEXSPI2_IPP_IND_SCK_FB_SELECT_INPUT = 18U, /**< IOMUXC select input index */
985 kIOMUXC_GPT1_IPP_IND_CAPIN1_SELECT_INPUT = 19U, /**< IOMUXC select input index */
986 kIOMUXC_GPT1_IPP_IND_CAPIN2_SELECT_INPUT = 20U, /**< IOMUXC select input index */
987 kIOMUXC_GPT1_IPP_IND_CLKIN_SELECT_INPUT = 21U, /**< IOMUXC select input index */
988 kIOMUXC_GPT2_IPP_IND_CAPIN1_SELECT_INPUT = 22U, /**< IOMUXC select input index */
989 kIOMUXC_GPT2_IPP_IND_CAPIN2_SELECT_INPUT = 23U, /**< IOMUXC select input index */
990 kIOMUXC_GPT2_IPP_IND_CLKIN_SELECT_INPUT = 24U, /**< IOMUXC select input index */
991 kIOMUXC_SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 = 25U, /**< IOMUXC select input index */
992 kIOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 26U, /**< IOMUXC select input index */
993 kIOMUXC_SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 27U, /**< IOMUXC select input index */
994 kIOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 28U, /**< IOMUXC select input index */
995 kIOMUXC_SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 29U, /**< IOMUXC select input index */
996 kIOMUXC_SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 30U, /**< IOMUXC select input index */
997 kIOMUXC_SEMC_I_IPP_IND_DQS4_SELECT_INPUT = 31U, /**< IOMUXC select input index */
998 kIOMUXC_CANFD_IPP_IND_CANRX_SELECT_INPUT = 32U, /**< IOMUXC select input index */
999} iomuxc_select_input_1_t;
1000
1001typedef enum _xbar_input_signal
1002{
1003 kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */
1004 kXBARA1_InputLogicHigh = 1|0x100U, /**< LOGIC_HIGH output assigned to XBARA1_IN1 input. */
1005 kXBARA1_InputIomuxXbarIn02 = 2|0x100U, /**< IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */
1006 kXBARA1_InputIomuxXbarIn03 = 3|0x100U, /**< IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */
1007 kXBARA1_InputIomuxXbarInout04 = 4|0x100U, /**< IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
1008 kXBARA1_InputIomuxXbarInout05 = 5|0x100U, /**< IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
1009 kXBARA1_InputIomuxXbarInout06 = 6|0x100U, /**< IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
1010 kXBARA1_InputIomuxXbarInout07 = 7|0x100U, /**< IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
1011 kXBARA1_InputIomuxXbarInout08 = 8|0x100U, /**< IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
1012 kXBARA1_InputIomuxXbarInout09 = 9|0x100U, /**< IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
1013 kXBARA1_InputIomuxXbarInout10 = 10|0x100U, /**< IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
1014 kXBARA1_InputIomuxXbarInout11 = 11|0x100U, /**< IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
1015 kXBARA1_InputIomuxXbarInout12 = 12|0x100U, /**< IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
1016 kXBARA1_InputIomuxXbarInout13 = 13|0x100U, /**< IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
1017 kXBARA1_InputIomuxXbarInout14 = 14|0x100U, /**< IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
1018 kXBARA1_InputIomuxXbarInout15 = 15|0x100U, /**< IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
1019 kXBARA1_InputIomuxXbarInout16 = 16|0x100U, /**< IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
1020 kXBARA1_InputIomuxXbarInout17 = 17|0x100U, /**< IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
1021 kXBARA1_InputIomuxXbarInout18 = 18|0x100U, /**< IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
1022 kXBARA1_InputIomuxXbarInout19 = 19|0x100U, /**< IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
1023 kXBARA1_InputIomuxXbarIn20 = 20|0x100U, /**< IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */
1024 kXBARA1_InputIomuxXbarIn21 = 21|0x100U, /**< IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */
1025 kXBARA1_InputIomuxXbarIn22 = 22|0x100U, /**< IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */
1026 kXBARA1_InputIomuxXbarIn23 = 23|0x100U, /**< IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */
1027 kXBARA1_InputIomuxXbarIn24 = 24|0x100U, /**< IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */
1028 kXBARA1_InputIomuxXbarIn25 = 25|0x100U, /**< IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */
1029 kXBARA1_InputAcmp1Out = 26|0x100U, /**< ACMP1_OUT output assigned to XBARA1_IN26 input. */
1030 kXBARA1_InputAcmp2Out = 27|0x100U, /**< ACMP2_OUT output assigned to XBARA1_IN27 input. */
1031 kXBARA1_InputAcmp3Out = 28|0x100U, /**< ACMP3_OUT output assigned to XBARA1_IN28 input. */
1032 kXBARA1_InputAcmp4Out = 29|0x100U, /**< ACMP4_OUT output assigned to XBARA1_IN29 input. */
1033 kXBARA1_InputRESERVED30 = 30|0x100U, /**< XBARA1_IN30 input is reserved. */
1034 kXBARA1_InputRESERVED31 = 31|0x100U, /**< XBARA1_IN31 input is reserved. */
1035 kXBARA1_InputQtimer3Tmr0Output = 32|0x100U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */
1036 kXBARA1_InputQtimer3Tmr1Output = 33|0x100U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */
1037 kXBARA1_InputQtimer3Tmr2Output = 34|0x100U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */
1038 kXBARA1_InputQtimer3Tmr3Output = 35|0x100U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */
1039 kXBARA1_InputQtimer4Tmr0Output = 36|0x100U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */
1040 kXBARA1_InputQtimer4Tmr1Output = 37|0x100U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */
1041 kXBARA1_InputQtimer4Tmr2Output = 38|0x100U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */
1042 kXBARA1_InputQtimer4Tmr3Output = 39|0x100U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */
1043 kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */
1044 kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */
1045 kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */
1046 kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */
1047 kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */
1048 kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */
1049 kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */
1050 kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */
1051 kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */
1052 kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */
1053 kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */
1054 kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */
1055 kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */
1056 kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */
1057 kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */
1058 kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */
1059 kXBARA1_InputPitTrigger0 = 56|0x100U, /**< PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */
1060 kXBARA1_InputPitTrigger1 = 57|0x100U, /**< PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */
1061 kXBARA1_InputPitTrigger2 = 58|0x100U, /**< PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */
1062 kXBARA1_InputPitTrigger3 = 59|0x100U, /**< PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */
1063 kXBARA1_InputEnc1PosMatch = 60|0x100U, /**< ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */
1064 kXBARA1_InputEnc2PosMatch = 61|0x100U, /**< ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */
1065 kXBARA1_InputEnc3PosMatch = 62|0x100U, /**< ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */
1066 kXBARA1_InputEnc4PosMatch = 63|0x100U, /**< ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */
1067 kXBARA1_InputDmaDone0 = 64|0x100U, /**< DMA_DONE0 output assigned to XBARA1_IN64 input. */
1068 kXBARA1_InputDmaDone1 = 65|0x100U, /**< DMA_DONE1 output assigned to XBARA1_IN65 input. */
1069 kXBARA1_InputDmaDone2 = 66|0x100U, /**< DMA_DONE2 output assigned to XBARA1_IN66 input. */
1070 kXBARA1_InputDmaDone3 = 67|0x100U, /**< DMA_DONE3 output assigned to XBARA1_IN67 input. */
1071 kXBARA1_InputDmaDone4 = 68|0x100U, /**< DMA_DONE4 output assigned to XBARA1_IN68 input. */
1072 kXBARA1_InputDmaDone5 = 69|0x100U, /**< DMA_DONE5 output assigned to XBARA1_IN69 input. */
1073 kXBARA1_InputDmaDone6 = 70|0x100U, /**< DMA_DONE6 output assigned to XBARA1_IN70 input. */
1074 kXBARA1_InputDmaDone7 = 71|0x100U, /**< DMA_DONE7 output assigned to XBARA1_IN71 input. */
1075 kXBARA1_InputAoi1Out0 = 72|0x100U, /**< AOI1_OUT0 output assigned to XBARA1_IN72 input. */
1076 kXBARA1_InputAoi1Out1 = 73|0x100U, /**< AOI1_OUT1 output assigned to XBARA1_IN73 input. */
1077 kXBARA1_InputAoi1Out2 = 74|0x100U, /**< AOI1_OUT2 output assigned to XBARA1_IN74 input. */
1078 kXBARA1_InputAoi1Out3 = 75|0x100U, /**< AOI1_OUT3 output assigned to XBARA1_IN75 input. */
1079 kXBARA1_InputAoi2Out0 = 76|0x100U, /**< AOI2_OUT0 output assigned to XBARA1_IN76 input. */
1080 kXBARA1_InputAoi2Out1 = 77|0x100U, /**< AOI2_OUT1 output assigned to XBARA1_IN77 input. */
1081 kXBARA1_InputAoi2Out2 = 78|0x100U, /**< AOI2_OUT2 output assigned to XBARA1_IN78 input. */
1082 kXBARA1_InputAoi2Out3 = 79|0x100U, /**< AOI2_OUT3 output assigned to XBARA1_IN79 input. */
1083 kXBARA1_InputAdcEtcXbar0Coco0 = 80|0x100U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */
1084 kXBARA1_InputAdcEtcXbar0Coco1 = 81|0x100U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */
1085 kXBARA1_InputAdcEtcXbar0Coco2 = 82|0x100U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */
1086 kXBARA1_InputAdcEtcXbar0Coco3 = 83|0x100U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */
1087 kXBARA1_InputAdcEtcXbar1Coco0 = 84|0x100U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */
1088 kXBARA1_InputAdcEtcXbar1Coco1 = 85|0x100U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */
1089 kXBARA1_InputAdcEtcXbar1Coco2 = 86|0x100U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */
1090 kXBARA1_InputAdcEtcXbar1Coco3 = 87|0x100U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */
1091 kXBARB2_InputLogicLow = 0|0x200U, /**< LOGIC_LOW output assigned to XBARB2_IN0 input. */
1092 kXBARB2_InputLogicHigh = 1|0x200U, /**< LOGIC_HIGH output assigned to XBARB2_IN1 input. */
1093 kXBARB2_InputRESERVED2 = 2|0x200U, /**< XBARB2_IN2 input is reserved. */
1094 kXBARB2_InputRESERVED3 = 3|0x200U, /**< XBARB2_IN3 input is reserved. */
1095 kXBARB2_InputRESERVED4 = 4|0x200U, /**< XBARB2_IN4 input is reserved. */
1096 kXBARB2_InputRESERVED5 = 5|0x200U, /**< XBARB2_IN5 input is reserved. */
1097 kXBARB2_InputAcmp1Out = 6|0x200U, /**< ACMP1_OUT output assigned to XBARB2_IN6 input. */
1098 kXBARB2_InputAcmp2Out = 7|0x200U, /**< ACMP2_OUT output assigned to XBARB2_IN7 input. */
1099 kXBARB2_InputAcmp3Out = 8|0x200U, /**< ACMP3_OUT output assigned to XBARB2_IN8 input. */
1100 kXBARB2_InputAcmp4Out = 9|0x200U, /**< ACMP4_OUT output assigned to XBARB2_IN9 input. */
1101 kXBARB2_InputRESERVED10 = 10|0x200U, /**< XBARB2_IN10 input is reserved. */
1102 kXBARB2_InputRESERVED11 = 11|0x200U, /**< XBARB2_IN11 input is reserved. */
1103 kXBARB2_InputQtimer3Tmr0Output = 12|0x200U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */
1104 kXBARB2_InputQtimer3Tmr1Output = 13|0x200U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */
1105 kXBARB2_InputQtimer3Tmr2Output = 14|0x200U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */
1106 kXBARB2_InputQtimer3Tmr3Output = 15|0x200U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */
1107 kXBARB2_InputQtimer4Tmr0Output = 16|0x200U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */
1108 kXBARB2_InputQtimer4Tmr1Output = 17|0x200U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */
1109 kXBARB2_InputQtimer4Tmr2Output = 18|0x200U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */
1110 kXBARB2_InputQtimer4Tmr3Output = 19|0x200U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */
1111 kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */
1112 kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */
1113 kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */
1114 kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */
1115 kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */
1116 kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */
1117 kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */
1118 kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */
1119 kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */
1120 kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */
1121 kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */
1122 kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */
1123 kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */
1124 kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */
1125 kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */
1126 kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */
1127 kXBARB2_InputPitTrigger0 = 36|0x200U, /**< PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */
1128 kXBARB2_InputPitTrigger1 = 37|0x200U, /**< PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */
1129 kXBARB2_InputAdcEtcXbar0Coco0 = 38|0x200U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */
1130 kXBARB2_InputAdcEtcXbar0Coco1 = 39|0x200U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */
1131 kXBARB2_InputAdcEtcXbar0Coco2 = 40|0x200U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */
1132 kXBARB2_InputAdcEtcXbar0Coco3 = 41|0x200U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */
1133 kXBARB2_InputAdcEtcXbar1Coco0 = 42|0x200U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */
1134 kXBARB2_InputAdcEtcXbar1Coco1 = 43|0x200U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */
1135 kXBARB2_InputAdcEtcXbar1Coco2 = 44|0x200U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */
1136 kXBARB2_InputAdcEtcXbar1Coco3 = 45|0x200U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */
1137 kXBARB2_InputEnc1PosMatch = 46|0x200U, /**< ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */
1138 kXBARB2_InputEnc2PosMatch = 47|0x200U, /**< ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */
1139 kXBARB2_InputEnc3PosMatch = 48|0x200U, /**< ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */
1140 kXBARB2_InputEnc4PosMatch = 49|0x200U, /**< ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */
1141 kXBARB2_InputDmaDone0 = 50|0x200U, /**< DMA_DONE0 output assigned to XBARB2_IN50 input. */
1142 kXBARB2_InputDmaDone1 = 51|0x200U, /**< DMA_DONE1 output assigned to XBARB2_IN51 input. */
1143 kXBARB2_InputDmaDone2 = 52|0x200U, /**< DMA_DONE2 output assigned to XBARB2_IN52 input. */
1144 kXBARB2_InputDmaDone3 = 53|0x200U, /**< DMA_DONE3 output assigned to XBARB2_IN53 input. */
1145 kXBARB2_InputDmaDone4 = 54|0x200U, /**< DMA_DONE4 output assigned to XBARB2_IN54 input. */
1146 kXBARB2_InputDmaDone5 = 55|0x200U, /**< DMA_DONE5 output assigned to XBARB2_IN55 input. */
1147 kXBARB2_InputDmaDone6 = 56|0x200U, /**< DMA_DONE6 output assigned to XBARB2_IN56 input. */
1148 kXBARB2_InputDmaDone7 = 57|0x200U, /**< DMA_DONE7 output assigned to XBARB2_IN57 input. */
1149 kXBARB3_InputLogicLow = 0|0x300U, /**< LOGIC_LOW output assigned to XBARB3_IN0 input. */
1150 kXBARB3_InputLogicHigh = 1|0x300U, /**< LOGIC_HIGH output assigned to XBARB3_IN1 input. */
1151 kXBARB3_InputRESERVED2 = 2|0x300U, /**< XBARB3_IN2 input is reserved. */
1152 kXBARB3_InputRESERVED3 = 3|0x300U, /**< XBARB3_IN3 input is reserved. */
1153 kXBARB3_InputRESERVED4 = 4|0x300U, /**< XBARB3_IN4 input is reserved. */
1154 kXBARB3_InputRESERVED5 = 5|0x300U, /**< XBARB3_IN5 input is reserved. */
1155 kXBARB3_InputAcmp1Out = 6|0x300U, /**< ACMP1_OUT output assigned to XBARB3_IN6 input. */
1156 kXBARB3_InputAcmp2Out = 7|0x300U, /**< ACMP2_OUT output assigned to XBARB3_IN7 input. */
1157 kXBARB3_InputAcmp3Out = 8|0x300U, /**< ACMP3_OUT output assigned to XBARB3_IN8 input. */
1158 kXBARB3_InputAcmp4Out = 9|0x300U, /**< ACMP4_OUT output assigned to XBARB3_IN9 input. */
1159 kXBARB3_InputRESERVED10 = 10|0x300U, /**< XBARB3_IN10 input is reserved. */
1160 kXBARB3_InputRESERVED11 = 11|0x300U, /**< XBARB3_IN11 input is reserved. */
1161 kXBARB3_InputQtimer3Tmr0Output = 12|0x300U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */
1162 kXBARB3_InputQtimer3Tmr1Output = 13|0x300U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */
1163 kXBARB3_InputQtimer3Tmr2Output = 14|0x300U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */
1164 kXBARB3_InputQtimer3Tmr3Output = 15|0x300U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */
1165 kXBARB3_InputQtimer4Tmr0Output = 16|0x300U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */
1166 kXBARB3_InputQtimer4Tmr1Output = 17|0x300U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */
1167 kXBARB3_InputQtimer4Tmr2Output = 18|0x300U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */
1168 kXBARB3_InputQtimer4Tmr3Output = 19|0x300U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */
1169 kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */
1170 kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */
1171 kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */
1172 kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */
1173 kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */
1174 kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */
1175 kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */
1176 kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */
1177 kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */
1178 kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */
1179 kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */
1180 kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */
1181 kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */
1182 kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */
1183 kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */
1184 kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */
1185 kXBARB3_InputPitTrigger0 = 36|0x300U, /**< PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */
1186 kXBARB3_InputPitTrigger1 = 37|0x300U, /**< PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */
1187 kXBARB3_InputAdcEtcXbar0Coco0 = 38|0x300U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */
1188 kXBARB3_InputAdcEtcXbar0Coco1 = 39|0x300U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */
1189 kXBARB3_InputAdcEtcXbar0Coco2 = 40|0x300U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */
1190 kXBARB3_InputAdcEtcXbar0Coco3 = 41|0x300U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */
1191 kXBARB3_InputAdcEtcXbar1Coco0 = 42|0x300U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */
1192 kXBARB3_InputAdcEtcXbar1Coco1 = 43|0x300U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */
1193 kXBARB3_InputAdcEtcXbar1Coco2 = 44|0x300U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */
1194 kXBARB3_InputAdcEtcXbar1Coco3 = 45|0x300U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */
1195 kXBARB3_InputEnc1PosMatch = 46|0x300U, /**< ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */
1196 kXBARB3_InputEnc2PosMatch = 47|0x300U, /**< ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */
1197 kXBARB3_InputEnc3PosMatch = 48|0x300U, /**< ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */
1198 kXBARB3_InputEnc4PosMatch = 49|0x300U, /**< ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */
1199 kXBARB3_InputDmaDone0 = 50|0x300U, /**< DMA_DONE0 output assigned to XBARB3_IN50 input. */
1200 kXBARB3_InputDmaDone1 = 51|0x300U, /**< DMA_DONE1 output assigned to XBARB3_IN51 input. */
1201 kXBARB3_InputDmaDone2 = 52|0x300U, /**< DMA_DONE2 output assigned to XBARB3_IN52 input. */
1202 kXBARB3_InputDmaDone3 = 53|0x300U, /**< DMA_DONE3 output assigned to XBARB3_IN53 input. */
1203 kXBARB3_InputDmaDone4 = 54|0x300U, /**< DMA_DONE4 output assigned to XBARB3_IN54 input. */
1204 kXBARB3_InputDmaDone5 = 55|0x300U, /**< DMA_DONE5 output assigned to XBARB3_IN55 input. */
1205 kXBARB3_InputDmaDone6 = 56|0x300U, /**< DMA_DONE6 output assigned to XBARB3_IN56 input. */
1206 kXBARB3_InputDmaDone7 = 57|0x300U, /**< DMA_DONE7 output assigned to XBARB3_IN57 input. */
1207} xbar_input_signal_t;
1208
1209typedef enum _xbar_output_signal
1210{
1211 kXBARA1_OutputDmaChMuxReq30 = 0|0x100U, /**< XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */
1212 kXBARA1_OutputDmaChMuxReq31 = 1|0x100U, /**< XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */
1213 kXBARA1_OutputDmaChMuxReq94 = 2|0x100U, /**< XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */
1214 kXBARA1_OutputDmaChMuxReq95 = 3|0x100U, /**< XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */
1215 kXBARA1_OutputIomuxXbarInout04 = 4|0x100U, /**< XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
1216 kXBARA1_OutputIomuxXbarInout05 = 5|0x100U, /**< XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
1217 kXBARA1_OutputIomuxXbarInout06 = 6|0x100U, /**< XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
1218 kXBARA1_OutputIomuxXbarInout07 = 7|0x100U, /**< XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
1219 kXBARA1_OutputIomuxXbarInout08 = 8|0x100U, /**< XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
1220 kXBARA1_OutputIomuxXbarInout09 = 9|0x100U, /**< XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
1221 kXBARA1_OutputIomuxXbarInout10 = 10|0x100U, /**< XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
1222 kXBARA1_OutputIomuxXbarInout11 = 11|0x100U, /**< XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
1223 kXBARA1_OutputIomuxXbarInout12 = 12|0x100U, /**< XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
1224 kXBARA1_OutputIomuxXbarInout13 = 13|0x100U, /**< XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
1225 kXBARA1_OutputIomuxXbarInout14 = 14|0x100U, /**< XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
1226 kXBARA1_OutputIomuxXbarInout15 = 15|0x100U, /**< XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
1227 kXBARA1_OutputIomuxXbarInout16 = 16|0x100U, /**< XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
1228 kXBARA1_OutputIomuxXbarInout17 = 17|0x100U, /**< XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
1229 kXBARA1_OutputIomuxXbarInout18 = 18|0x100U, /**< XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
1230 kXBARA1_OutputIomuxXbarInout19 = 19|0x100U, /**< XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
1231 kXBARA1_OutputAcmp1Sample = 20|0x100U, /**< XBARA1_OUT20 output assigned to ACMP1_SAMPLE */
1232 kXBARA1_OutputAcmp2Sample = 21|0x100U, /**< XBARA1_OUT21 output assigned to ACMP2_SAMPLE */
1233 kXBARA1_OutputAcmp3Sample = 22|0x100U, /**< XBARA1_OUT22 output assigned to ACMP3_SAMPLE */
1234 kXBARA1_OutputAcmp4Sample = 23|0x100U, /**< XBARA1_OUT23 output assigned to ACMP4_SAMPLE */
1235 kXBARA1_OutputRESERVED24 = 24|0x100U, /**< XBARA1_OUT24 output is reserved. */
1236 kXBARA1_OutputRESERVED25 = 25|0x100U, /**< XBARA1_OUT25 output is reserved. */
1237 kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U, /**< XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */
1238 kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U, /**< XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */
1239 kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U, /**< XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */
1240 kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U, /**< XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */
1241 kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U, /**< XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
1242 kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U, /**< XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
1243 kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U, /**< XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
1244 kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U, /**< XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
1245 kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U, /**< XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */
1246 kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U, /**< XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */
1247 kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U, /**< XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */
1248 kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U, /**< XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */
1249 kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U, /**< XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */
1250 kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U, /**< XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
1251 kXBARA1_OutputFlexpwm234Exta0 = 40|0x100U, /**< XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */
1252 kXBARA1_OutputFlexpwm234Exta1 = 41|0x100U, /**< XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */
1253 kXBARA1_OutputFlexpwm234Exta2 = 42|0x100U, /**< XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */
1254 kXBARA1_OutputFlexpwm234Exta3 = 43|0x100U, /**< XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */
1255 kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U, /**< XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */
1256 kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U, /**< XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */
1257 kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U, /**< XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */
1258 kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U, /**< XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */
1259 kXBARA1_OutputFlexpwm234ExtClk = 48|0x100U, /**< XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */
1260 kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U, /**< XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */
1261 kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U, /**< XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */
1262 kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U, /**< XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */
1263 kXBARA1_OutputFlexpwm3ExtSync0 = 52|0x100U, /**< XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */
1264 kXBARA1_OutputFlexpwm3ExtSync1 = 53|0x100U, /**< XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */
1265 kXBARA1_OutputFlexpwm3ExtSync2 = 54|0x100U, /**< XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */
1266 kXBARA1_OutputFlexpwm3ExtSync3 = 55|0x100U, /**< XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */
1267 kXBARA1_OutputFlexpwm3Fault0 = 56|0x100U, /**< XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */
1268 kXBARA1_OutputFlexpwm3Fault1 = 57|0x100U, /**< XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */
1269 kXBARA1_OutputFlexpwm3ExtForce = 58|0x100U, /**< XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */
1270 kXBARA1_OutputFlexpwm4ExtSync0 = 59|0x100U, /**< XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */
1271 kXBARA1_OutputFlexpwm4ExtSync1 = 60|0x100U, /**< XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */
1272 kXBARA1_OutputFlexpwm4ExtSync2 = 61|0x100U, /**< XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */
1273 kXBARA1_OutputFlexpwm4ExtSync3 = 62|0x100U, /**< XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */
1274 kXBARA1_OutputFlexpwm4Fault0 = 63|0x100U, /**< XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */
1275 kXBARA1_OutputFlexpwm4Fault1 = 64|0x100U, /**< XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */
1276 kXBARA1_OutputFlexpwm4ExtForce = 65|0x100U, /**< XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */
1277 kXBARA1_OutputEnc1PhaseAInput = 66|0x100U, /**< XBARA1_OUT66 output assigned to ENC1_PHASE_A_INPUT */
1278 kXBARA1_OutputEnc1PhaseBInput = 67|0x100U, /**< XBARA1_OUT67 output assigned to ENC1_PHASE_B_INPUT */
1279 kXBARA1_OutputEnc1Index = 68|0x100U, /**< XBARA1_OUT68 output assigned to ENC1_INDEX */
1280 kXBARA1_OutputEnc1Home = 69|0x100U, /**< XBARA1_OUT69 output assigned to ENC1_HOME */
1281 kXBARA1_OutputEnc1Trigger = 70|0x100U, /**< XBARA1_OUT70 output assigned to ENC1_TRIGGER */
1282 kXBARA1_OutputEnc2PhaseAInput = 71|0x100U, /**< XBARA1_OUT71 output assigned to ENC2_PHASE_A_INPUT */
1283 kXBARA1_OutputEnc2PhaseBInput = 72|0x100U, /**< XBARA1_OUT72 output assigned to ENC2_PHASE_B_INPUT */
1284 kXBARA1_OutputEnc2Index = 73|0x100U, /**< XBARA1_OUT73 output assigned to ENC2_INDEX */
1285 kXBARA1_OutputEnc2Home = 74|0x100U, /**< XBARA1_OUT74 output assigned to ENC2_HOME */
1286 kXBARA1_OutputEnc2Trigger = 75|0x100U, /**< XBARA1_OUT75 output assigned to ENC2_TRIGGER */
1287 kXBARA1_OutputEnc3PhaseAInput = 76|0x100U, /**< XBARA1_OUT76 output assigned to ENC3_PHASE_A_INPUT */
1288 kXBARA1_OutputEnc3PhaseBInput = 77|0x100U, /**< XBARA1_OUT77 output assigned to ENC3_PHASE_B_INPUT */
1289 kXBARA1_OutputEnc3Index = 78|0x100U, /**< XBARA1_OUT78 output assigned to ENC3_INDEX */
1290 kXBARA1_OutputEnc3Home = 79|0x100U, /**< XBARA1_OUT79 output assigned to ENC3_HOME */
1291 kXBARA1_OutputEnc3Trigger = 80|0x100U, /**< XBARA1_OUT80 output assigned to ENC3_TRIGGER */
1292 kXBARA1_OutputEnc4PhaseAInput = 81|0x100U, /**< XBARA1_OUT81 output assigned to ENC4_PHASE_A_INPUT */
1293 kXBARA1_OutputEnc4PhaseBInput = 82|0x100U, /**< XBARA1_OUT82 output assigned to ENC4_PHASE_B_INPUT */
1294 kXBARA1_OutputEnc4Index = 83|0x100U, /**< XBARA1_OUT83 output assigned to ENC4_INDEX */
1295 kXBARA1_OutputEnc4Home = 84|0x100U, /**< XBARA1_OUT84 output assigned to ENC4_HOME */
1296 kXBARA1_OutputEnc4Trigger = 85|0x100U, /**< XBARA1_OUT85 output assigned to ENC4_TRIGGER */
1297 kXBARA1_OutputQtimer1Tmr0Input = 86|0x100U, /**< XBARA1_OUT86 output assigned to QTIMER1_TMR0_INPUT */
1298 kXBARA1_OutputQtimer1Tmr1Input = 87|0x100U, /**< XBARA1_OUT87 output assigned to QTIMER1_TMR1_INPUT */
1299 kXBARA1_OutputQtimer1Tmr2Input = 88|0x100U, /**< XBARA1_OUT88 output assigned to QTIMER1_TMR2_INPUT */
1300 kXBARA1_OutputQtimer1Tmr3Input = 89|0x100U, /**< XBARA1_OUT89 output assigned to QTIMER1_TMR3_INPUT */
1301 kXBARA1_OutputQtimer2Tmr0Input = 90|0x100U, /**< XBARA1_OUT90 output assigned to QTIMER2_TMR0_INPUT */
1302 kXBARA1_OutputQtimer2Tmr1Input = 91|0x100U, /**< XBARA1_OUT91 output assigned to QTIMER2_TMR1_INPUT */
1303 kXBARA1_OutputQtimer2Tmr2Input = 92|0x100U, /**< XBARA1_OUT92 output assigned to QTIMER2_TMR2_INPUT */
1304 kXBARA1_OutputQtimer2Tmr3Input = 93|0x100U, /**< XBARA1_OUT93 output assigned to QTIMER2_TMR3_INPUT */
1305 kXBARA1_OutputQtimer3Tmr0Input = 94|0x100U, /**< XBARA1_OUT94 output assigned to QTIMER3_TMR0_INPUT */
1306 kXBARA1_OutputQtimer3Tmr1Input = 95|0x100U, /**< XBARA1_OUT95 output assigned to QTIMER3_TMR1_INPUT */
1307 kXBARA1_OutputQtimer3Tmr2Input = 96|0x100U, /**< XBARA1_OUT96 output assigned to QTIMER3_TMR2_INPUT */
1308 kXBARA1_OutputQtimer3Tmr3Input = 97|0x100U, /**< XBARA1_OUT97 output assigned to QTIMER3_TMR3_INPUT */
1309 kXBARA1_OutputQtimer4Tmr0Input = 98|0x100U, /**< XBARA1_OUT98 output assigned to QTIMER4_TMR0_INPUT */
1310 kXBARA1_OutputQtimer4Tmr1Input = 99|0x100U, /**< XBARA1_OUT99 output assigned to QTIMER4_TMR1_INPUT */
1311 kXBARA1_OutputQtimer4Tmr2Input = 100|0x100U, /**< XBARA1_OUT100 output assigned to QTIMER4_TMR2_INPUT */
1312 kXBARA1_OutputQtimer4Tmr3Input = 101|0x100U, /**< XBARA1_OUT101 output assigned to QTIMER4_TMR3_INPUT */
1313 kXBARA1_OutputEwmEwmIn = 102|0x100U, /**< XBARA1_OUT102 output assigned to EWM_EWM_IN */
1314 kXBARA1_OutputAdcEtcXbar0Trig0 = 103|0x100U, /**< XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */
1315 kXBARA1_OutputAdcEtcXbar0Trig1 = 104|0x100U, /**< XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */
1316 kXBARA1_OutputAdcEtcXbar0Trig2 = 105|0x100U, /**< XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */
1317 kXBARA1_OutputAdcEtcXbar0Trig3 = 106|0x100U, /**< XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */
1318 kXBARA1_OutputAdcEtcXbar1Trig0 = 107|0x100U, /**< XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */
1319 kXBARA1_OutputAdcEtcXbar1Trig1 = 108|0x100U, /**< XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */
1320 kXBARA1_OutputAdcEtcXbar1Trig2 = 109|0x100U, /**< XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */
1321 kXBARA1_OutputAdcEtcXbar1Trig3 = 110|0x100U, /**< XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */
1322 kXBARA1_OutputLpi2c1TrgInput = 111|0x100U, /**< XBARA1_OUT111 output assigned to LPI2C1_TRG_INPUT */
1323 kXBARA1_OutputLpi2c2TrgInput = 112|0x100U, /**< XBARA1_OUT112 output assigned to LPI2C2_TRG_INPUT */
1324 kXBARA1_OutputLpi2c3TrgInput = 113|0x100U, /**< XBARA1_OUT113 output assigned to LPI2C3_TRG_INPUT */
1325 kXBARA1_OutputLpi2c4TrgInput = 114|0x100U, /**< XBARA1_OUT114 output assigned to LPI2C4_TRG_INPUT */
1326 kXBARA1_OutputLpspi1TrgInput = 115|0x100U, /**< XBARA1_OUT115 output assigned to LPSPI1_TRG_INPUT */
1327 kXBARA1_OutputLpspi2TrgInput = 116|0x100U, /**< XBARA1_OUT116 output assigned to LPSPI2_TRG_INPUT */
1328 kXBARA1_OutputLpspi3TrgInput = 117|0x100U, /**< XBARA1_OUT117 output assigned to LPSPI3_TRG_INPUT */
1329 kXBARA1_OutputLpspi4TrgInput = 118|0x100U, /**< XBARA1_OUT118 output assigned to LPSPI4_TRG_INPUT */
1330 kXBARA1_OutputLpuart1TrgInput = 119|0x100U, /**< XBARA1_OUT119 output assigned to LPUART1_TRG_INPUT */
1331 kXBARA1_OutputLpuart2TrgInput = 120|0x100U, /**< XBARA1_OUT120 output assigned to LPUART2_TRG_INPUT */
1332 kXBARA1_OutputLpuart3TrgInput = 121|0x100U, /**< XBARA1_OUT121 output assigned to LPUART3_TRG_INPUT */
1333 kXBARA1_OutputLpuart4TrgInput = 122|0x100U, /**< XBARA1_OUT122 output assigned to LPUART4_TRG_INPUT */
1334 kXBARA1_OutputLpuart5TrgInput = 123|0x100U, /**< XBARA1_OUT123 output assigned to LPUART5_TRG_INPUT */
1335 kXBARA1_OutputLpuart6TrgInput = 124|0x100U, /**< XBARA1_OUT124 output assigned to LPUART6_TRG_INPUT */
1336 kXBARA1_OutputLpuart7TrgInput = 125|0x100U, /**< XBARA1_OUT125 output assigned to LPUART7_TRG_INPUT */
1337 kXBARA1_OutputLpuart8TrgInput = 126|0x100U, /**< XBARA1_OUT126 output assigned to LPUART8_TRG_INPUT */
1338 kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U, /**< XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
1339 kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U, /**< XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
1340 kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U, /**< XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */
1341 kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U, /**< XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */
1342 kXBARB2_OutputAoi1In00 = 0|0x200U, /**< XBARB2_OUT0 output assigned to AOI1_IN00 */
1343 kXBARB2_OutputAoi1In01 = 1|0x200U, /**< XBARB2_OUT1 output assigned to AOI1_IN01 */
1344 kXBARB2_OutputAoi1In02 = 2|0x200U, /**< XBARB2_OUT2 output assigned to AOI1_IN02 */
1345 kXBARB2_OutputAoi1In03 = 3|0x200U, /**< XBARB2_OUT3 output assigned to AOI1_IN03 */
1346 kXBARB2_OutputAoi1In04 = 4|0x200U, /**< XBARB2_OUT4 output assigned to AOI1_IN04 */
1347 kXBARB2_OutputAoi1In05 = 5|0x200U, /**< XBARB2_OUT5 output assigned to AOI1_IN05 */
1348 kXBARB2_OutputAoi1In06 = 6|0x200U, /**< XBARB2_OUT6 output assigned to AOI1_IN06 */
1349 kXBARB2_OutputAoi1In07 = 7|0x200U, /**< XBARB2_OUT7 output assigned to AOI1_IN07 */
1350 kXBARB2_OutputAoi1In08 = 8|0x200U, /**< XBARB2_OUT8 output assigned to AOI1_IN08 */
1351 kXBARB2_OutputAoi1In09 = 9|0x200U, /**< XBARB2_OUT9 output assigned to AOI1_IN09 */
1352 kXBARB2_OutputAoi1In10 = 10|0x200U, /**< XBARB2_OUT10 output assigned to AOI1_IN10 */
1353 kXBARB2_OutputAoi1In11 = 11|0x200U, /**< XBARB2_OUT11 output assigned to AOI1_IN11 */
1354 kXBARB2_OutputAoi1In12 = 12|0x200U, /**< XBARB2_OUT12 output assigned to AOI1_IN12 */
1355 kXBARB2_OutputAoi1In13 = 13|0x200U, /**< XBARB2_OUT13 output assigned to AOI1_IN13 */
1356 kXBARB2_OutputAoi1In14 = 14|0x200U, /**< XBARB2_OUT14 output assigned to AOI1_IN14 */
1357 kXBARB2_OutputAoi1In15 = 15|0x200U, /**< XBARB2_OUT15 output assigned to AOI1_IN15 */
1358 kXBARB3_OutputAoi2In00 = 0|0x300U, /**< XBARB3_OUT0 output assigned to AOI2_IN00 */
1359 kXBARB3_OutputAoi2In01 = 1|0x300U, /**< XBARB3_OUT1 output assigned to AOI2_IN01 */
1360 kXBARB3_OutputAoi2In02 = 2|0x300U, /**< XBARB3_OUT2 output assigned to AOI2_IN02 */
1361 kXBARB3_OutputAoi2In03 = 3|0x300U, /**< XBARB3_OUT3 output assigned to AOI2_IN03 */
1362 kXBARB3_OutputAoi2In04 = 4|0x300U, /**< XBARB3_OUT4 output assigned to AOI2_IN04 */
1363 kXBARB3_OutputAoi2In05 = 5|0x300U, /**< XBARB3_OUT5 output assigned to AOI2_IN05 */
1364 kXBARB3_OutputAoi2In06 = 6|0x300U, /**< XBARB3_OUT6 output assigned to AOI2_IN06 */
1365 kXBARB3_OutputAoi2In07 = 7|0x300U, /**< XBARB3_OUT7 output assigned to AOI2_IN07 */
1366 kXBARB3_OutputAoi2In08 = 8|0x300U, /**< XBARB3_OUT8 output assigned to AOI2_IN08 */
1367 kXBARB3_OutputAoi2In09 = 9|0x300U, /**< XBARB3_OUT9 output assigned to AOI2_IN09 */
1368 kXBARB3_OutputAoi2In10 = 10|0x300U, /**< XBARB3_OUT10 output assigned to AOI2_IN10 */
1369 kXBARB3_OutputAoi2In11 = 11|0x300U, /**< XBARB3_OUT11 output assigned to AOI2_IN11 */
1370 kXBARB3_OutputAoi2In12 = 12|0x300U, /**< XBARB3_OUT12 output assigned to AOI2_IN12 */
1371 kXBARB3_OutputAoi2In13 = 13|0x300U, /**< XBARB3_OUT13 output assigned to AOI2_IN13 */
1372 kXBARB3_OutputAoi2In14 = 14|0x300U, /**< XBARB3_OUT14 output assigned to AOI2_IN14 */
1373 kXBARB3_OutputAoi2In15 = 15|0x300U, /**< XBARB3_OUT15 output assigned to AOI2_IN15 */
1374} xbar_output_signal_t;
1375
1376
1377/*!
1378 * @}
1379 */ /* end of group Mapping_Information */
1380
1381
1382/* ----------------------------------------------------------------------------
1383 -- Device Peripheral Access Layer
1384 ---------------------------------------------------------------------------- */
1385
1386/*!
1387 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
1388 * @{
1389 */
1390
1391
1392/*
1393** Start of section using anonymous unions
1394*/
1395
1396#if defined(__ARMCC_VERSION)
1397 #if (__ARMCC_VERSION >= 6010050)
1398 #pragma clang diagnostic push
1399 #else
1400 #pragma push
1401 #pragma anon_unions
1402 #endif
1403#elif defined(__CWCC__)
1404 #pragma push
1405 #pragma cpp_extensions on
1406#elif defined(__GNUC__)
1407 /* anonymous unions are enabled by default */
1408#elif defined(__IAR_SYSTEMS_ICC__)
1409 #pragma language=extended
1410#else
1411 #error Not supported compiler type
1412#endif
1413
1414/* ----------------------------------------------------------------------------
1415 -- ADC Peripheral Access Layer
1416 ---------------------------------------------------------------------------- */
1417
1418/*!
1419 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
1420 * @{
1421 */
1422
1423/** ADC - Register Layout Typedef */
1424typedef struct {
1425 __IO uint32_t HC[8]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */
1426 __I uint32_t HS; /**< Status register for HW triggers, offset: 0x20 */
1427 __I uint32_t R[8]; /**< Data result register for HW triggers, array offset: 0x24, array step: 0x4 */
1428 __IO uint32_t CFG; /**< Configuration register, offset: 0x44 */
1429 __IO uint32_t GC; /**< General control register, offset: 0x48 */
1430 __IO uint32_t GS; /**< General status register, offset: 0x4C */
1431 __IO uint32_t CV; /**< Compare value register, offset: 0x50 */
1432 __IO uint32_t OFS; /**< Offset correction value register, offset: 0x54 */
1433 __IO uint32_t CAL; /**< Calibration value register, offset: 0x58 */
1434} ADC_Type;
1435
1436/* ----------------------------------------------------------------------------
1437 -- ADC Register Masks
1438 ---------------------------------------------------------------------------- */
1439
1440/*!
1441 * @addtogroup ADC_Register_Masks ADC Register Masks
1442 * @{
1443 */
1444
1445/*! @name HC - Control register for hardware triggers */
1446/*! @{ */
1447#define ADC_HC_ADCH_MASK (0x1FU)
1448#define ADC_HC_ADCH_SHIFT (0U)
1449/*! ADCH - Input Channel Select
1450 * 0b10000..External channel selection from ADC_ETC
1451 * 0b11000..Reserved.
1452 * 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally
1453 * 0b11010..Reserved.
1454 * 0b11011..Reserved.
1455 * 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion.
1456 */
1457#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)
1458#define ADC_HC_AIEN_MASK (0x80U)
1459#define ADC_HC_AIEN_SHIFT (7U)
1460/*! AIEN - Conversion Complete Interrupt Enable/Disable Control
1461 * 0b1..Conversion complete interrupt enabled
1462 * 0b0..Conversion complete interrupt disabled
1463 */
1464#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)
1465/*! @} */
1466
1467/* The count of ADC_HC */
1468#define ADC_HC_COUNT (8U)
1469
1470/*! @name HS - Status register for HW triggers */
1471/*! @{ */
1472#define ADC_HS_COCO0_MASK (0x1U)
1473#define ADC_HS_COCO0_SHIFT (0U)
1474/*! COCO0 - Conversion Complete Flag
1475 */
1476#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)
1477/*! @} */
1478
1479/*! @name R - Data result register for HW triggers */
1480/*! @{ */
1481#define ADC_R_CDATA_MASK (0xFFFU)
1482#define ADC_R_CDATA_SHIFT (0U)
1483/*! CDATA - Data (result of an ADC conversion)
1484 */
1485#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)
1486/*! @} */
1487
1488/* The count of ADC_R */
1489#define ADC_R_COUNT (8U)
1490
1491/*! @name CFG - Configuration register */
1492/*! @{ */
1493#define ADC_CFG_ADICLK_MASK (0x3U)
1494#define ADC_CFG_ADICLK_SHIFT (0U)
1495/*! ADICLK - Input Clock Select
1496 * 0b00..IPG clock
1497 * 0b01..IPG clock divided by 2
1498 * 0b10..Reserved
1499 * 0b11..Asynchronous clock (ADACK)
1500 */
1501#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)
1502#define ADC_CFG_MODE_MASK (0xCU)
1503#define ADC_CFG_MODE_SHIFT (2U)
1504/*! MODE - Conversion Mode Selection
1505 * 0b00..8-bit conversion
1506 * 0b01..10-bit conversion
1507 * 0b10..12-bit conversion
1508 * 0b11..Reserved
1509 */
1510#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)
1511#define ADC_CFG_ADLSMP_MASK (0x10U)
1512#define ADC_CFG_ADLSMP_SHIFT (4U)
1513/*! ADLSMP - Long Sample Time Configuration
1514 * 0b0..Short sample mode.
1515 * 0b1..Long sample mode.
1516 */
1517#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)
1518#define ADC_CFG_ADIV_MASK (0x60U)
1519#define ADC_CFG_ADIV_SHIFT (5U)
1520/*! ADIV - Clock Divide Select
1521 * 0b00..Input clock
1522 * 0b01..Input clock / 2
1523 * 0b10..Input clock / 4
1524 * 0b11..Input clock / 8
1525 */
1526#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)
1527#define ADC_CFG_ADLPC_MASK (0x80U)
1528#define ADC_CFG_ADLPC_SHIFT (7U)
1529/*! ADLPC - Low-Power Configuration
1530 * 0b0..ADC hard block not in low power mode.
1531 * 0b1..ADC hard block in low power mode.
1532 */
1533#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)
1534#define ADC_CFG_ADSTS_MASK (0x300U)
1535#define ADC_CFG_ADSTS_SHIFT (8U)
1536/*! ADSTS
1537 * 0b00..Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b
1538 * 0b01..Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b
1539 * 0b10..Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b
1540 * 0b11..Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b
1541 */
1542#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)
1543#define ADC_CFG_ADHSC_MASK (0x400U)
1544#define ADC_CFG_ADHSC_SHIFT (10U)
1545/*! ADHSC - High Speed Configuration
1546 * 0b0..Normal conversion selected.
1547 * 0b1..High speed conversion selected.
1548 */
1549#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)
1550#define ADC_CFG_REFSEL_MASK (0x1800U)
1551#define ADC_CFG_REFSEL_SHIFT (11U)
1552/*! REFSEL - Voltage Reference Selection
1553 * 0b00..Selects VREFH/VREFL as reference voltage.
1554 * 0b01..Reserved
1555 * 0b10..Reserved
1556 * 0b11..Reserved
1557 */
1558#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
1559#define ADC_CFG_ADTRG_MASK (0x2000U)
1560#define ADC_CFG_ADTRG_SHIFT (13U)
1561/*! ADTRG - Conversion Trigger Select
1562 * 0b0..Software trigger selected
1563 * 0b1..Hardware trigger selected
1564 */
1565#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
1566#define ADC_CFG_AVGS_MASK (0xC000U)
1567#define ADC_CFG_AVGS_SHIFT (14U)
1568/*! AVGS - Hardware Average select
1569 * 0b00..4 samples averaged
1570 * 0b01..8 samples averaged
1571 * 0b10..16 samples averaged
1572 * 0b11..32 samples averaged
1573 */
1574#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)
1575#define ADC_CFG_OVWREN_MASK (0x10000U)
1576#define ADC_CFG_OVWREN_SHIFT (16U)
1577/*! OVWREN - Data Overwrite Enable
1578 * 0b1..Enable the overwriting.
1579 * 0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data.
1580 */
1581#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)
1582/*! @} */
1583
1584/*! @name GC - General control register */
1585/*! @{ */
1586#define ADC_GC_ADACKEN_MASK (0x1U)
1587#define ADC_GC_ADACKEN_SHIFT (0U)
1588/*! ADACKEN - Asynchronous clock output enable
1589 * 0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active.
1590 * 0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC
1591 */
1592#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)
1593#define ADC_GC_DMAEN_MASK (0x2U)
1594#define ADC_GC_DMAEN_SHIFT (1U)
1595/*! DMAEN - DMA Enable
1596 * 0b0..DMA disabled (default)
1597 * 0b1..DMA enabled
1598 */
1599#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)
1600#define ADC_GC_ACREN_MASK (0x4U)
1601#define ADC_GC_ACREN_SHIFT (2U)
1602/*! ACREN - Compare Function Range Enable
1603 * 0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared.
1604 * 0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared.
1605 */
1606#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
1607#define ADC_GC_ACFGT_MASK (0x8U)
1608#define ADC_GC_ACFGT_SHIFT (3U)
1609/*! ACFGT - Compare Function Greater Than Enable
1610 * 0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive"
1611 * functionality based on the values placed in the ADC_CV register.
1612 * 0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive"
1613 * functionality based on the values placed in the ADC_CV registers.
1614 */
1615#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)
1616#define ADC_GC_ACFE_MASK (0x10U)
1617#define ADC_GC_ACFE_SHIFT (4U)
1618/*! ACFE - Compare Function Enable
1619 * 0b0..Compare function disabled
1620 * 0b1..Compare function enabled
1621 */
1622#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)
1623#define ADC_GC_AVGE_MASK (0x20U)
1624#define ADC_GC_AVGE_SHIFT (5U)
1625/*! AVGE - Hardware average enable
1626 * 0b0..Hardware average function disabled
1627 * 0b1..Hardware average function enabled
1628 */
1629#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)
1630#define ADC_GC_ADCO_MASK (0x40U)
1631#define ADC_GC_ADCO_SHIFT (6U)
1632/*! ADCO - Continuous Conversion Enable
1633 * 0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
1634 * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
1635 */
1636#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)
1637#define ADC_GC_CAL_MASK (0x80U)
1638#define ADC_GC_CAL_SHIFT (7U)
1639/*! CAL - Calibration
1640 */
1641#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)
1642/*! @} */
1643
1644/*! @name GS - General status register */
1645/*! @{ */
1646#define ADC_GS_ADACT_MASK (0x1U)
1647#define ADC_GS_ADACT_SHIFT (0U)
1648/*! ADACT - Conversion Active
1649 * 0b0..Conversion not in progress.
1650 * 0b1..Conversion in progress.
1651 */
1652#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)
1653#define ADC_GS_CALF_MASK (0x2U)
1654#define ADC_GS_CALF_SHIFT (1U)
1655/*! CALF - Calibration Failed Flag
1656 * 0b0..Calibration completed normally.
1657 * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
1658 */
1659#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)
1660#define ADC_GS_AWKST_MASK (0x4U)
1661#define ADC_GS_AWKST_SHIFT (2U)
1662/*! AWKST - Asynchronous wakeup interrupt status
1663 * 0b1..Asynchronous wake up interrupt occurred in stop mode.
1664 * 0b0..No asynchronous interrupt.
1665 */
1666#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)
1667/*! @} */
1668
1669/*! @name CV - Compare value register */
1670/*! @{ */
1671#define ADC_CV_CV1_MASK (0xFFFU)
1672#define ADC_CV_CV1_SHIFT (0U)
1673/*! CV1 - Compare Value 1
1674 */
1675#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)
1676#define ADC_CV_CV2_MASK (0xFFF0000U)
1677#define ADC_CV_CV2_SHIFT (16U)
1678/*! CV2 - Compare Value 2
1679 */
1680#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)
1681/*! @} */
1682
1683/*! @name OFS - Offset correction value register */
1684/*! @{ */
1685#define ADC_OFS_OFS_MASK (0xFFFU)
1686#define ADC_OFS_OFS_SHIFT (0U)
1687/*! OFS - Offset value
1688 */
1689#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
1690#define ADC_OFS_SIGN_MASK (0x1000U)
1691#define ADC_OFS_SIGN_SHIFT (12U)
1692/*! SIGN - Sign bit
1693 * 0b0..The offset value is added with the raw result
1694 * 0b1..The offset value is subtracted from the raw converted value
1695 */
1696#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)
1697/*! @} */
1698
1699/*! @name CAL - Calibration value register */
1700/*! @{ */
1701#define ADC_CAL_CAL_CODE_MASK (0xFU)
1702#define ADC_CAL_CAL_CODE_SHIFT (0U)
1703/*! CAL_CODE - Calibration Result Value
1704 */
1705#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK)
1706/*! @} */
1707
1708
1709/*!
1710 * @}
1711 */ /* end of group ADC_Register_Masks */
1712
1713
1714/* ADC - Peripheral instance base addresses */
1715/** Peripheral ADC1 base address */
1716#define ADC1_BASE (0x400C4000u)
1717/** Peripheral ADC1 base pointer */
1718#define ADC1 ((ADC_Type *)ADC1_BASE)
1719/** Peripheral ADC2 base address */
1720#define ADC2_BASE (0x400C8000u)
1721/** Peripheral ADC2 base pointer */
1722#define ADC2 ((ADC_Type *)ADC2_BASE)
1723/** Array initializer of ADC peripheral base addresses */
1724#define ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE }
1725/** Array initializer of ADC peripheral base pointers */
1726#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 }
1727/** Interrupt vectors for the ADC peripheral type */
1728#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
1729
1730/*!
1731 * @}
1732 */ /* end of group ADC_Peripheral_Access_Layer */
1733
1734
1735/* ----------------------------------------------------------------------------
1736 -- ADC_ETC Peripheral Access Layer
1737 ---------------------------------------------------------------------------- */
1738
1739/*!
1740 * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer
1741 * @{
1742 */
1743
1744/** ADC_ETC - Register Layout Typedef */
1745typedef struct {
1746 __IO uint32_t CTRL; /**< ADC_ETC Global Control Register, offset: 0x0 */
1747 __IO uint32_t DONE0_1_IRQ; /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */
1748 __IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */
1749 __IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */
1750 struct { /* offset: 0x10, array step: 0x28 */
1751 __IO uint32_t TRIGn_CTRL; /**< ETC_TRIG0 Control Register..ETC_TRIG7 Control Register, array offset: 0x10, array step: 0x28 */
1752 __IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register, array offset: 0x14, array step: 0x28 */
1753 __IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */
1754 __IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */
1755 __IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */
1756 __IO uint32_t TRIGn_CHAIN_7_6; /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */
1757 __I uint32_t TRIGn_RESULT_1_0; /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */
1758 __I uint32_t TRIGn_RESULT_3_2; /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */
1759 __I uint32_t TRIGn_RESULT_5_4; /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */
1760 __I uint32_t TRIGn_RESULT_7_6; /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */
1761 } TRIG[8];
1762} ADC_ETC_Type;
1763
1764/* ----------------------------------------------------------------------------
1765 -- ADC_ETC Register Masks
1766 ---------------------------------------------------------------------------- */
1767
1768/*!
1769 * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks
1770 * @{
1771 */
1772
1773/*! @name CTRL - ADC_ETC Global Control Register */
1774/*! @{ */
1775#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU)
1776#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U)
1777#define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
1778#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U)
1779#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U)
1780#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK)
1781#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U)
1782#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U)
1783#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK)
1784#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U)
1785#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U)
1786#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK)
1787#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U)
1788#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U)
1789#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK)
1790#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U)
1791#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U)
1792#define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
1793#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U)
1794#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U)
1795#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
1796#define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U)
1797#define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U)
1798#define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK)
1799#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U)
1800#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U)
1801#define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
1802/*! @} */
1803
1804/*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */
1805/*! @{ */
1806#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U)
1807#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U)
1808#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
1809#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U)
1810#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U)
1811#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
1812#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U)
1813#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U)
1814#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
1815#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U)
1816#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U)
1817#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
1818#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U)
1819#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U)
1820#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
1821#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U)
1822#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U)
1823#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
1824#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U)
1825#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U)
1826#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
1827#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U)
1828#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U)
1829#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
1830#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U)
1831#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U)
1832#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
1833#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U)
1834#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U)
1835#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
1836#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U)
1837#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U)
1838#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
1839#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U)
1840#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U)
1841#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
1842#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U)
1843#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U)
1844#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
1845#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U)
1846#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U)
1847#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
1848#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U)
1849#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U)
1850#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
1851#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U)
1852#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U)
1853#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
1854/*! @} */
1855
1856/*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */
1857/*! @{ */
1858#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
1859#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
1860#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK)
1861#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
1862#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
1863#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK)
1864#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
1865#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
1866#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK)
1867#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
1868#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
1869#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK)
1870#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
1871#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
1872#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK)
1873#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
1874#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
1875#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK)
1876#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
1877#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
1878#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK)
1879#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
1880#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
1881#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK)
1882#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U)
1883#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U)
1884#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK)
1885#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U)
1886#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U)
1887#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK)
1888#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U)
1889#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U)
1890#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK)
1891#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U)
1892#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U)
1893#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK)
1894#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U)
1895#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U)
1896#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK)
1897#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U)
1898#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U)
1899#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK)
1900#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U)
1901#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U)
1902#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK)
1903#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U)
1904#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U)
1905#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK)
1906/*! @} */
1907
1908/*! @name DMA_CTRL - ETC DMA control Register */
1909/*! @{ */
1910#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U)
1911#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U)
1912#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
1913#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U)
1914#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U)
1915#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
1916#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U)
1917#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U)
1918#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
1919#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U)
1920#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U)
1921#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
1922#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U)
1923#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U)
1924#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
1925#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U)
1926#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U)
1927#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
1928#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U)
1929#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U)
1930#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
1931#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U)
1932#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U)
1933#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
1934#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U)
1935#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U)
1936#define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
1937#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U)
1938#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U)
1939#define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
1940#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U)
1941#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U)
1942#define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
1943#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U)
1944#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U)
1945#define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
1946#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U)
1947#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U)
1948#define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
1949#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U)
1950#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U)
1951#define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
1952#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U)
1953#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U)
1954#define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
1955#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U)
1956#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U)
1957#define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
1958/*! @} */
1959
1960/*! @name TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG7 Control Register */
1961/*! @{ */
1962#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U)
1963#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U)
1964#define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
1965#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U)
1966#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U)
1967#define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
1968#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U)
1969#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U)
1970#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
1971#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U)
1972#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U)
1973#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
1974#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U)
1975#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U)
1976#define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
1977/*! @} */
1978
1979/* The count of ADC_ETC_TRIGn_CTRL */
1980#define ADC_ETC_TRIGn_CTRL_COUNT (8U)
1981
1982/*! @name TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register */
1983/*! @{ */
1984#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU)
1985#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U)
1986#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
1987#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
1988#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
1989#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
1990/*! @} */
1991
1992/* The count of ADC_ETC_TRIGn_COUNTER */
1993#define ADC_ETC_TRIGn_COUNTER_COUNT (8U)
1994
1995/*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */
1996/*! @{ */
1997#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU)
1998#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U)
1999#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
2000#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U)
2001#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U)
2002#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
2003#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U)
2004#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U)
2005#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
2006#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U)
2007#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U)
2008#define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
2009#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U)
2010#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U)
2011#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
2012#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U)
2013#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U)
2014#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
2015#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U)
2016#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U)
2017#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
2018#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U)
2019#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U)
2020#define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
2021/*! @} */
2022
2023/* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
2024#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U)
2025
2026/*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */
2027/*! @{ */
2028#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU)
2029#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U)
2030#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
2031#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U)
2032#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U)
2033#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
2034#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U)
2035#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U)
2036#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
2037#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U)
2038#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U)
2039#define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
2040#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U)
2041#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U)
2042#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
2043#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U)
2044#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U)
2045#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
2046#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U)
2047#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U)
2048#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
2049#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U)
2050#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U)
2051#define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
2052/*! @} */
2053
2054/* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
2055#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U)
2056
2057/*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */
2058/*! @{ */
2059#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU)
2060#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U)
2061#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
2062#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U)
2063#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)
2064#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
2065#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)
2066#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)
2067#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
2068#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)
2069#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)
2070#define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
2071#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)
2072#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)
2073#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
2074#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)
2075#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)
2076#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
2077#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)
2078#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)
2079#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
2080#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)
2081#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)
2082#define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
2083/*! @} */
2084
2085/* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
2086#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)
2087
2088/*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */
2089/*! @{ */
2090#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)
2091#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)
2092#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
2093#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)
2094#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)
2095#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
2096#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)
2097#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)
2098#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
2099#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)
2100#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)
2101#define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
2102#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)
2103#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)
2104#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
2105#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)
2106#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)
2107#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
2108#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)
2109#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)
2110#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
2111#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)
2112#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)
2113#define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
2114/*! @} */
2115
2116/* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
2117#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)
2118
2119/*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */
2120/*! @{ */
2121#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)
2122#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)
2123#define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
2124#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)
2125#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)
2126#define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
2127/*! @} */
2128
2129/* The count of ADC_ETC_TRIGn_RESULT_1_0 */
2130#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)
2131
2132/*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */
2133/*! @{ */
2134#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)
2135#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)
2136#define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
2137#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)
2138#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)
2139#define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
2140/*! @} */
2141
2142/* The count of ADC_ETC_TRIGn_RESULT_3_2 */
2143#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)
2144
2145/*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */
2146/*! @{ */
2147#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)
2148#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)
2149#define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
2150#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)
2151#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)
2152#define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
2153/*! @} */
2154
2155/* The count of ADC_ETC_TRIGn_RESULT_5_4 */
2156#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)
2157
2158/*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */
2159/*! @{ */
2160#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)
2161#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)
2162#define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
2163#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)
2164#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)
2165#define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
2166/*! @} */
2167
2168/* The count of ADC_ETC_TRIGn_RESULT_7_6 */
2169#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)
2170
2171
2172/*!
2173 * @}
2174 */ /* end of group ADC_ETC_Register_Masks */
2175
2176
2177/* ADC_ETC - Peripheral instance base addresses */
2178/** Peripheral ADC_ETC base address */
2179#define ADC_ETC_BASE (0x403B0000u)
2180/** Peripheral ADC_ETC base pointer */
2181#define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)
2182/** Array initializer of ADC_ETC peripheral base addresses */
2183#define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }
2184/** Array initializer of ADC_ETC peripheral base pointers */
2185#define ADC_ETC_BASE_PTRS { ADC_ETC }
2186/** Interrupt vectors for the ADC_ETC peripheral type */
2187#define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } }
2188#define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }
2189
2190/*!
2191 * @}
2192 */ /* end of group ADC_ETC_Peripheral_Access_Layer */
2193
2194
2195/* ----------------------------------------------------------------------------
2196 -- AIPSTZ Peripheral Access Layer
2197 ---------------------------------------------------------------------------- */
2198
2199/*!
2200 * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
2201 * @{
2202 */
2203
2204/** AIPSTZ - Register Layout Typedef */
2205typedef struct {
2206 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */
2207 uint8_t RESERVED_0[60];
2208 __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */
2209 __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */
2210 __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */
2211 __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */
2212 __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */
2213} AIPSTZ_Type;
2214
2215/* ----------------------------------------------------------------------------
2216 -- AIPSTZ Register Masks
2217 ---------------------------------------------------------------------------- */
2218
2219/*!
2220 * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
2221 * @{
2222 */
2223
2224/*! @name MPR - Master Priviledge Registers */
2225/*! @{ */
2226#define AIPSTZ_MPR_MPROT5_MASK (0xF00U)
2227#define AIPSTZ_MPR_MPROT5_SHIFT (8U)
2228/*! MPROT5
2229 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2230 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2231 * 0bxx0x..This master is not trusted for write accesses.
2232 * 0bxx1x..This master is trusted for write accesses.
2233 * 0bx0xx..This master is not trusted for read accesses.
2234 * 0bx1xx..This master is trusted for read accesses.
2235 * 0b1xxx..Write accesses from this master are allowed to be buffered
2236 */
2237#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
2238#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
2239#define AIPSTZ_MPR_MPROT3_SHIFT (16U)
2240/*! MPROT3
2241 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2242 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2243 * 0bxx0x..This master is not trusted for write accesses.
2244 * 0bxx1x..This master is trusted for write accesses.
2245 * 0bx0xx..This master is not trusted for read accesses.
2246 * 0bx1xx..This master is trusted for read accesses.
2247 * 0b1xxx..Write accesses from this master are allowed to be buffered
2248 */
2249#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
2250#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
2251#define AIPSTZ_MPR_MPROT2_SHIFT (20U)
2252/*! MPROT2
2253 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2254 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2255 * 0bxx0x..This master is not trusted for write accesses.
2256 * 0bxx1x..This master is trusted for write accesses.
2257 * 0bx0xx..This master is not trusted for read accesses.
2258 * 0bx1xx..This master is trusted for read accesses.
2259 * 0b1xxx..Write accesses from this master are allowed to be buffered
2260 */
2261#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
2262#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
2263#define AIPSTZ_MPR_MPROT1_SHIFT (24U)
2264/*! MPROT1
2265 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2266 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2267 * 0bxx0x..This master is not trusted for write accesses.
2268 * 0bxx1x..This master is trusted for write accesses.
2269 * 0bx0xx..This master is not trusted for read accesses.
2270 * 0bx1xx..This master is trusted for read accesses.
2271 * 0b1xxx..Write accesses from this master are allowed to be buffered
2272 */
2273#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
2274#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
2275#define AIPSTZ_MPR_MPROT0_SHIFT (28U)
2276/*! MPROT0
2277 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2278 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2279 * 0bxx0x..This master is not trusted for write accesses.
2280 * 0bxx1x..This master is trusted for write accesses.
2281 * 0bx0xx..This master is not trusted for read accesses.
2282 * 0bx1xx..This master is trusted for read accesses.
2283 * 0b1xxx..Write accesses from this master are allowed to be buffered
2284 */
2285#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
2286/*! @} */
2287
2288/*! @name OPACR - Off-Platform Peripheral Access Control Registers */
2289/*! @{ */
2290#define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
2291#define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
2292/*! OPAC7
2293 * 0bxxx0..Accesses from an untrusted master are allowed.
2294 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2295 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2296 * 0bxx0x..This peripheral allows write accesses.
2297 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2298 * error response and no peripheral access is initiated on the IPS bus.
2299 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2300 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2301 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2302 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2303 * on the IPS bus.
2304 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2305 */
2306#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
2307#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
2308#define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
2309/*! OPAC6
2310 * 0bxxx0..Accesses from an untrusted master are allowed.
2311 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2312 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2313 * 0bxx0x..This peripheral allows write accesses.
2314 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2315 * error response and no peripheral access is initiated on the IPS bus.
2316 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2317 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2318 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2319 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2320 * on the IPS bus.
2321 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2322 */
2323#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
2324#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
2325#define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
2326/*! OPAC5
2327 * 0bxxx0..Accesses from an untrusted master are allowed.
2328 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2329 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2330 * 0bxx0x..This peripheral allows write accesses.
2331 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2332 * error response and no peripheral access is initiated on the IPS bus.
2333 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2334 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2335 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2336 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2337 * on the IPS bus.
2338 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2339 */
2340#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
2341#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
2342#define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
2343/*! OPAC4
2344 * 0bxxx0..Accesses from an untrusted master are allowed.
2345 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2346 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2347 * 0bxx0x..This peripheral allows write accesses.
2348 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2349 * error response and no peripheral access is initiated on the IPS bus.
2350 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2351 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2352 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2353 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2354 * on the IPS bus.
2355 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2356 */
2357#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
2358#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
2359#define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
2360/*! OPAC3
2361 * 0bxxx0..Accesses from an untrusted master are allowed.
2362 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2363 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2364 * 0bxx0x..This peripheral allows write accesses.
2365 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2366 * error response and no peripheral access is initiated on the IPS bus.
2367 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2368 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2369 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2370 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2371 * on the IPS bus.
2372 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2373 */
2374#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
2375#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
2376#define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
2377/*! OPAC2
2378 * 0bxxx0..Accesses from an untrusted master are allowed.
2379 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2380 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2381 * 0bxx0x..This peripheral allows write accesses.
2382 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2383 * error response and no peripheral access is initiated on the IPS bus.
2384 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2385 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2386 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2387 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2388 * on the IPS bus.
2389 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2390 */
2391#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
2392#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
2393#define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
2394/*! OPAC1
2395 * 0bxxx0..Accesses from an untrusted master are allowed.
2396 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2397 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2398 * 0bxx0x..This peripheral allows write accesses.
2399 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2400 * error response and no peripheral access is initiated on the IPS bus.
2401 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2402 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2403 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2404 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2405 * on the IPS bus.
2406 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2407 */
2408#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
2409#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
2410#define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
2411/*! OPAC0
2412 * 0bxxx0..Accesses from an untrusted master are allowed.
2413 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2414 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2415 * 0bxx0x..This peripheral allows write accesses.
2416 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2417 * error response and no peripheral access is initiated on the IPS bus.
2418 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2419 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2420 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2421 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2422 * on the IPS bus.
2423 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2424 */
2425#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
2426/*! @} */
2427
2428/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */
2429/*! @{ */
2430#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
2431#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
2432/*! OPAC15
2433 * 0bxxx0..Accesses from an untrusted master are allowed.
2434 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2435 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2436 * 0bxx0x..This peripheral allows write accesses.
2437 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2438 * error response and no peripheral access is initiated on the IPS bus.
2439 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2440 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2441 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2442 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2443 * on the IPS bus.
2444 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2445 */
2446#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
2447#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
2448#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
2449/*! OPAC14
2450 * 0bxxx0..Accesses from an untrusted master are allowed.
2451 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2452 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2453 * 0bxx0x..This peripheral allows write accesses.
2454 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2455 * error response and no peripheral access is initiated on the IPS bus.
2456 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2457 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2458 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2459 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2460 * on the IPS bus.
2461 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2462 */
2463#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
2464#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
2465#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
2466/*! OPAC13
2467 * 0bxxx0..Accesses from an untrusted master are allowed.
2468 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2469 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2470 * 0bxx0x..This peripheral allows write accesses.
2471 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2472 * error response and no peripheral access is initiated on the IPS bus.
2473 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2474 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2475 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2476 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2477 * on the IPS bus.
2478 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2479 */
2480#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
2481#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
2482#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
2483/*! OPAC12
2484 * 0bxxx0..Accesses from an untrusted master are allowed.
2485 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2486 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2487 * 0bxx0x..This peripheral allows write accesses.
2488 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2489 * error response and no peripheral access is initiated on the IPS bus.
2490 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2491 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2492 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2493 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2494 * on the IPS bus.
2495 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2496 */
2497#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
2498#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
2499#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
2500/*! OPAC11
2501 * 0bxxx0..Accesses from an untrusted master are allowed.
2502 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2503 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2504 * 0bxx0x..This peripheral allows write accesses.
2505 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2506 * error response and no peripheral access is initiated on the IPS bus.
2507 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2508 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2509 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2510 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2511 * on the IPS bus.
2512 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2513 */
2514#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
2515#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
2516#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
2517/*! OPAC10
2518 * 0bxxx0..Accesses from an untrusted master are allowed.
2519 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2520 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2521 * 0bxx0x..This peripheral allows write accesses.
2522 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2523 * error response and no peripheral access is initiated on the IPS bus.
2524 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2525 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2526 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2527 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2528 * on the IPS bus.
2529 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2530 */
2531#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
2532#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
2533#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
2534/*! OPAC9
2535 * 0bxxx0..Accesses from an untrusted master are allowed.
2536 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2537 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2538 * 0bxx0x..This peripheral allows write accesses.
2539 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2540 * error response and no peripheral access is initiated on the IPS bus.
2541 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2542 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2543 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2544 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2545 * on the IPS bus.
2546 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2547 */
2548#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
2549#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
2550#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
2551/*! OPAC8
2552 * 0bxxx0..Accesses from an untrusted master are allowed.
2553 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2554 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2555 * 0bxx0x..This peripheral allows write accesses.
2556 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2557 * error response and no peripheral access is initiated on the IPS bus.
2558 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2559 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2560 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2561 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2562 * on the IPS bus.
2563 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2564 */
2565#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
2566/*! @} */
2567
2568/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */
2569/*! @{ */
2570#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
2571#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
2572/*! OPAC23
2573 * 0bxxx0..Accesses from an untrusted master are allowed.
2574 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2575 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2576 * 0bxx0x..This peripheral allows write accesses.
2577 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2578 * error response and no peripheral access is initiated on the IPS bus.
2579 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2580 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2581 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2582 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2583 * on the IPS bus.
2584 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2585 */
2586#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
2587#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
2588#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
2589/*! OPAC22
2590 * 0bxxx0..Accesses from an untrusted master are allowed.
2591 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2592 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2593 * 0bxx0x..This peripheral allows write accesses.
2594 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2595 * error response and no peripheral access is initiated on the IPS bus.
2596 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2597 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2598 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2599 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2600 * on the IPS bus.
2601 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2602 */
2603#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
2604#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
2605#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
2606/*! OPAC21
2607 * 0bxxx0..Accesses from an untrusted master are allowed.
2608 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2609 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2610 * 0bxx0x..This peripheral allows write accesses.
2611 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2612 * error response and no peripheral access is initiated on the IPS bus.
2613 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2614 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2615 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2616 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2617 * on the IPS bus.
2618 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2619 */
2620#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
2621#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
2622#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
2623/*! OPAC20
2624 * 0bxxx0..Accesses from an untrusted master are allowed.
2625 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2626 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2627 * 0bxx0x..This peripheral allows write accesses.
2628 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2629 * error response and no peripheral access is initiated on the IPS bus.
2630 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2631 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2632 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2633 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2634 * on the IPS bus.
2635 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2636 */
2637#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
2638#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
2639#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
2640/*! OPAC19
2641 * 0bxxx0..Accesses from an untrusted master are allowed.
2642 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2643 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2644 * 0bxx0x..This peripheral allows write accesses.
2645 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2646 * error response and no peripheral access is initiated on the IPS bus.
2647 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2648 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2649 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2650 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2651 * on the IPS bus.
2652 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2653 */
2654#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
2655#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
2656#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
2657/*! OPAC18
2658 * 0bxxx0..Accesses from an untrusted master are allowed.
2659 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2660 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2661 * 0bxx0x..This peripheral allows write accesses.
2662 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2663 * error response and no peripheral access is initiated on the IPS bus.
2664 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2665 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2666 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2667 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2668 * on the IPS bus.
2669 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2670 */
2671#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
2672#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
2673#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
2674/*! OPAC17
2675 * 0bxxx0..Accesses from an untrusted master are allowed.
2676 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2677 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2678 * 0bxx0x..This peripheral allows write accesses.
2679 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2680 * error response and no peripheral access is initiated on the IPS bus.
2681 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2682 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2683 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2684 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2685 * on the IPS bus.
2686 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2687 */
2688#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
2689#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
2690#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
2691/*! OPAC16
2692 * 0bxxx0..Accesses from an untrusted master are allowed.
2693 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2694 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2695 * 0bxx0x..This peripheral allows write accesses.
2696 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2697 * error response and no peripheral access is initiated on the IPS bus.
2698 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2699 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2700 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2701 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2702 * on the IPS bus.
2703 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2704 */
2705#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
2706/*! @} */
2707
2708/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */
2709/*! @{ */
2710#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
2711#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
2712/*! OPAC31
2713 * 0bxxx0..Accesses from an untrusted master are allowed.
2714 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2715 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2716 * 0bxx0x..This peripheral allows write accesses.
2717 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2718 * error response and no peripheral access is initiated on the IPS bus.
2719 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2720 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2721 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2722 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2723 * on the IPS bus.
2724 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2725 */
2726#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
2727#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
2728#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
2729/*! OPAC30
2730 * 0bxxx0..Accesses from an untrusted master are allowed.
2731 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2732 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2733 * 0bxx0x..This peripheral allows write accesses.
2734 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2735 * error response and no peripheral access is initiated on the IPS bus.
2736 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2737 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2738 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2739 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2740 * on the IPS bus.
2741 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2742 */
2743#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
2744#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
2745#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
2746/*! OPAC29
2747 * 0bxxx0..Accesses from an untrusted master are allowed.
2748 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2749 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2750 * 0bxx0x..This peripheral allows write accesses.
2751 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2752 * error response and no peripheral access is initiated on the IPS bus.
2753 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2754 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2755 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2756 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2757 * on the IPS bus.
2758 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2759 */
2760#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
2761#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
2762#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
2763/*! OPAC28
2764 * 0bxxx0..Accesses from an untrusted master are allowed.
2765 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2766 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2767 * 0bxx0x..This peripheral allows write accesses.
2768 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2769 * error response and no peripheral access is initiated on the IPS bus.
2770 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2771 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2772 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2773 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2774 * on the IPS bus.
2775 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2776 */
2777#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
2778#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
2779#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
2780/*! OPAC27
2781 * 0bxxx0..Accesses from an untrusted master are allowed.
2782 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2783 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2784 * 0bxx0x..This peripheral allows write accesses.
2785 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2786 * error response and no peripheral access is initiated on the IPS bus.
2787 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2788 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2789 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2790 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2791 * on the IPS bus.
2792 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2793 */
2794#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
2795#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
2796#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
2797/*! OPAC26
2798 * 0bxxx0..Accesses from an untrusted master are allowed.
2799 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2800 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2801 * 0bxx0x..This peripheral allows write accesses.
2802 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2803 * error response and no peripheral access is initiated on the IPS bus.
2804 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2805 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2806 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2807 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2808 * on the IPS bus.
2809 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2810 */
2811#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
2812#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
2813#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
2814/*! OPAC25
2815 * 0bxxx0..Accesses from an untrusted master are allowed.
2816 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2817 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2818 * 0bxx0x..This peripheral allows write accesses.
2819 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2820 * error response and no peripheral access is initiated on the IPS bus.
2821 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2822 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2823 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2824 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2825 * on the IPS bus.
2826 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2827 */
2828#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
2829#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
2830#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
2831/*! OPAC24
2832 * 0bxxx0..Accesses from an untrusted master are allowed.
2833 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2834 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2835 * 0bxx0x..This peripheral allows write accesses.
2836 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2837 * error response and no peripheral access is initiated on the IPS bus.
2838 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2839 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2840 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2841 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2842 * on the IPS bus.
2843 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2844 */
2845#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
2846/*! @} */
2847
2848/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */
2849/*! @{ */
2850#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
2851#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
2852/*! OPAC33
2853 * 0bxxx0..Accesses from an untrusted master are allowed.
2854 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2855 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2856 * 0bxx0x..This peripheral allows write accesses.
2857 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2858 * error response and no peripheral access is initiated on the IPS bus.
2859 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2860 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2861 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2862 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2863 * on the IPS bus.
2864 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2865 */
2866#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
2867#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
2868#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
2869/*! OPAC32
2870 * 0bxxx0..Accesses from an untrusted master are allowed.
2871 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2872 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2873 * 0bxx0x..This peripheral allows write accesses.
2874 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2875 * error response and no peripheral access is initiated on the IPS bus.
2876 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2877 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2878 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2879 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2880 * on the IPS bus.
2881 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2882 */
2883#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
2884/*! @} */
2885
2886
2887/*!
2888 * @}
2889 */ /* end of group AIPSTZ_Register_Masks */
2890
2891
2892/* AIPSTZ - Peripheral instance base addresses */
2893/** Peripheral AIPSTZ1 base address */
2894#define AIPSTZ1_BASE (0x4007C000u)
2895/** Peripheral AIPSTZ1 base pointer */
2896#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)
2897/** Peripheral AIPSTZ2 base address */
2898#define AIPSTZ2_BASE (0x4017C000u)
2899/** Peripheral AIPSTZ2 base pointer */
2900#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)
2901/** Peripheral AIPSTZ3 base address */
2902#define AIPSTZ3_BASE (0x4027C000u)
2903/** Peripheral AIPSTZ3 base pointer */
2904#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)
2905/** Peripheral AIPSTZ4 base address */
2906#define AIPSTZ4_BASE (0x4037C000u)
2907/** Peripheral AIPSTZ4 base pointer */
2908#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)
2909/** Array initializer of AIPSTZ peripheral base addresses */
2910#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }
2911/** Array initializer of AIPSTZ peripheral base pointers */
2912#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }
2913
2914/*!
2915 * @}
2916 */ /* end of group AIPSTZ_Peripheral_Access_Layer */
2917
2918
2919/* ----------------------------------------------------------------------------
2920 -- AOI Peripheral Access Layer
2921 ---------------------------------------------------------------------------- */
2922
2923/*!
2924 * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer
2925 * @{
2926 */
2927
2928/** AOI - Register Layout Typedef */
2929typedef struct {
2930 struct { /* offset: 0x0, array step: 0x4 */
2931 __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */
2932 __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */
2933 } BFCRT[4];
2934} AOI_Type;
2935
2936/* ----------------------------------------------------------------------------
2937 -- AOI Register Masks
2938 ---------------------------------------------------------------------------- */
2939
2940/*!
2941 * @addtogroup AOI_Register_Masks AOI Register Masks
2942 * @{
2943 */
2944
2945/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */
2946/*! @{ */
2947#define AOI_BFCRT01_PT1_DC_MASK (0x3U)
2948#define AOI_BFCRT01_PT1_DC_SHIFT (0U)
2949/*! PT1_DC - Product term 1, D input configuration
2950 * 0b00..Force the D input in this product term to a logical zero
2951 * 0b01..Pass the D input in this product term
2952 * 0b10..Complement the D input in this product term
2953 * 0b11..Force the D input in this product term to a logical one
2954 */
2955#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
2956#define AOI_BFCRT01_PT1_CC_MASK (0xCU)
2957#define AOI_BFCRT01_PT1_CC_SHIFT (2U)
2958/*! PT1_CC - Product term 1, C input configuration
2959 * 0b00..Force the C input in this product term to a logical zero
2960 * 0b01..Pass the C input in this product term
2961 * 0b10..Complement the C input in this product term
2962 * 0b11..Force the C input in this product term to a logical one
2963 */
2964#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
2965#define AOI_BFCRT01_PT1_BC_MASK (0x30U)
2966#define AOI_BFCRT01_PT1_BC_SHIFT (4U)
2967/*! PT1_BC - Product term 1, B input configuration
2968 * 0b00..Force the B input in this product term to a logical zero
2969 * 0b01..Pass the B input in this product term
2970 * 0b10..Complement the B input in this product term
2971 * 0b11..Force the B input in this product term to a logical one
2972 */
2973#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
2974#define AOI_BFCRT01_PT1_AC_MASK (0xC0U)
2975#define AOI_BFCRT01_PT1_AC_SHIFT (6U)
2976/*! PT1_AC - Product term 1, A input configuration
2977 * 0b00..Force the A input in this product term to a logical zero
2978 * 0b01..Pass the A input in this product term
2979 * 0b10..Complement the A input in this product term
2980 * 0b11..Force the A input in this product term to a logical one
2981 */
2982#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
2983#define AOI_BFCRT01_PT0_DC_MASK (0x300U)
2984#define AOI_BFCRT01_PT0_DC_SHIFT (8U)
2985/*! PT0_DC - Product term 0, D input configuration
2986 * 0b00..Force the D input in this product term to a logical zero
2987 * 0b01..Pass the D input in this product term
2988 * 0b10..Complement the D input in this product term
2989 * 0b11..Force the D input in this product term to a logical one
2990 */
2991#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
2992#define AOI_BFCRT01_PT0_CC_MASK (0xC00U)
2993#define AOI_BFCRT01_PT0_CC_SHIFT (10U)
2994/*! PT0_CC - Product term 0, C input configuration
2995 * 0b00..Force the C input in this product term to a logical zero
2996 * 0b01..Pass the C input in this product term
2997 * 0b10..Complement the C input in this product term
2998 * 0b11..Force the C input in this product term to a logical one
2999 */
3000#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
3001#define AOI_BFCRT01_PT0_BC_MASK (0x3000U)
3002#define AOI_BFCRT01_PT0_BC_SHIFT (12U)
3003/*! PT0_BC - Product term 0, B input configuration
3004 * 0b00..Force the B input in this product term to a logical zero
3005 * 0b01..Pass the B input in this product term
3006 * 0b10..Complement the B input in this product term
3007 * 0b11..Force the B input in this product term to a logical one
3008 */
3009#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
3010#define AOI_BFCRT01_PT0_AC_MASK (0xC000U)
3011#define AOI_BFCRT01_PT0_AC_SHIFT (14U)
3012/*! PT0_AC - Product term 0, A input configuration
3013 * 0b00..Force the A input in this product term to a logical zero
3014 * 0b01..Pass the A input in this product term
3015 * 0b10..Complement the A input in this product term
3016 * 0b11..Force the A input in this product term to a logical one
3017 */
3018#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
3019/*! @} */
3020
3021/* The count of AOI_BFCRT01 */
3022#define AOI_BFCRT01_COUNT (4U)
3023
3024/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */
3025/*! @{ */
3026#define AOI_BFCRT23_PT3_DC_MASK (0x3U)
3027#define AOI_BFCRT23_PT3_DC_SHIFT (0U)
3028/*! PT3_DC - Product term 3, D input configuration
3029 * 0b00..Force the D input in this product term to a logical zero
3030 * 0b01..Pass the D input in this product term
3031 * 0b10..Complement the D input in this product term
3032 * 0b11..Force the D input in this product term to a logical one
3033 */
3034#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
3035#define AOI_BFCRT23_PT3_CC_MASK (0xCU)
3036#define AOI_BFCRT23_PT3_CC_SHIFT (2U)
3037/*! PT3_CC - Product term 3, C input configuration
3038 * 0b00..Force the C input in this product term to a logical zero
3039 * 0b01..Pass the C input in this product term
3040 * 0b10..Complement the C input in this product term
3041 * 0b11..Force the C input in this product term to a logical one
3042 */
3043#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
3044#define AOI_BFCRT23_PT3_BC_MASK (0x30U)
3045#define AOI_BFCRT23_PT3_BC_SHIFT (4U)
3046/*! PT3_BC - Product term 3, B input configuration
3047 * 0b00..Force the B input in this product term to a logical zero
3048 * 0b01..Pass the B input in this product term
3049 * 0b10..Complement the B input in this product term
3050 * 0b11..Force the B input in this product term to a logical one
3051 */
3052#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
3053#define AOI_BFCRT23_PT3_AC_MASK (0xC0U)
3054#define AOI_BFCRT23_PT3_AC_SHIFT (6U)
3055/*! PT3_AC - Product term 3, A input configuration
3056 * 0b00..Force the A input in this product term to a logical zero
3057 * 0b01..Pass the A input in this product term
3058 * 0b10..Complement the A input in this product term
3059 * 0b11..Force the A input in this product term to a logical one
3060 */
3061#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
3062#define AOI_BFCRT23_PT2_DC_MASK (0x300U)
3063#define AOI_BFCRT23_PT2_DC_SHIFT (8U)
3064/*! PT2_DC - Product term 2, D input configuration
3065 * 0b00..Force the D input in this product term to a logical zero
3066 * 0b01..Pass the D input in this product term
3067 * 0b10..Complement the D input in this product term
3068 * 0b11..Force the D input in this product term to a logical one
3069 */
3070#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
3071#define AOI_BFCRT23_PT2_CC_MASK (0xC00U)
3072#define AOI_BFCRT23_PT2_CC_SHIFT (10U)
3073/*! PT2_CC - Product term 2, C input configuration
3074 * 0b00..Force the C input in this product term to a logical zero
3075 * 0b01..Pass the C input in this product term
3076 * 0b10..Complement the C input in this product term
3077 * 0b11..Force the C input in this product term to a logical one
3078 */
3079#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
3080#define AOI_BFCRT23_PT2_BC_MASK (0x3000U)
3081#define AOI_BFCRT23_PT2_BC_SHIFT (12U)
3082/*! PT2_BC - Product term 2, B input configuration
3083 * 0b00..Force the B input in this product term to a logical zero
3084 * 0b01..Pass the B input in this product term
3085 * 0b10..Complement the B input in this product term
3086 * 0b11..Force the B input in this product term to a logical one
3087 */
3088#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
3089#define AOI_BFCRT23_PT2_AC_MASK (0xC000U)
3090#define AOI_BFCRT23_PT2_AC_SHIFT (14U)
3091/*! PT2_AC - Product term 2, A input configuration
3092 * 0b00..Force the A input in this product term to a logical zero
3093 * 0b01..Pass the A input in this product term
3094 * 0b10..Complement the A input in this product term
3095 * 0b11..Force the A input in this product term to a logical one
3096 */
3097#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
3098/*! @} */
3099
3100/* The count of AOI_BFCRT23 */
3101#define AOI_BFCRT23_COUNT (4U)
3102
3103
3104/*!
3105 * @}
3106 */ /* end of group AOI_Register_Masks */
3107
3108
3109/* AOI - Peripheral instance base addresses */
3110/** Peripheral AOI1 base address */
3111#define AOI1_BASE (0x403B4000u)
3112/** Peripheral AOI1 base pointer */
3113#define AOI1 ((AOI_Type *)AOI1_BASE)
3114/** Peripheral AOI2 base address */
3115#define AOI2_BASE (0x403B8000u)
3116/** Peripheral AOI2 base pointer */
3117#define AOI2 ((AOI_Type *)AOI2_BASE)
3118/** Array initializer of AOI peripheral base addresses */
3119#define AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE }
3120/** Array initializer of AOI peripheral base pointers */
3121#define AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 }
3122
3123/*!
3124 * @}
3125 */ /* end of group AOI_Peripheral_Access_Layer */
3126
3127
3128/* ----------------------------------------------------------------------------
3129 -- BEE Peripheral Access Layer
3130 ---------------------------------------------------------------------------- */
3131
3132/*!
3133 * @addtogroup BEE_Peripheral_Access_Layer BEE Peripheral Access Layer
3134 * @{
3135 */
3136
3137/** BEE - Register Layout Typedef */
3138typedef struct {
3139 __IO uint32_t CTRL; /**< Control Register, offset: 0x0 */
3140 __IO uint32_t ADDR_OFFSET0; /**< Offset region 0 Register, offset: 0x4 */
3141 __IO uint32_t ADDR_OFFSET1; /**< Offset region 1 Register, offset: 0x8 */
3142 __IO uint32_t AES_KEY0_W0; /**< AES Key 0 Register, offset: 0xC */
3143 __IO uint32_t AES_KEY0_W1; /**< AES Key 1 Register, offset: 0x10 */
3144 __IO uint32_t AES_KEY0_W2; /**< AES Key 2 Register, offset: 0x14 */
3145 __IO uint32_t AES_KEY0_W3; /**< AES Key 3 Register, offset: 0x18 */
3146 __IO uint32_t STATUS; /**< Status Register, offset: 0x1C */
3147 __O uint32_t CTR_NONCE0_W0; /**< NONCE00 Register, offset: 0x20 */
3148 __O uint32_t CTR_NONCE0_W1; /**< NONCE01 Register, offset: 0x24 */
3149 __O uint32_t CTR_NONCE0_W2; /**< NONCE02 Register, offset: 0x28 */
3150 __O uint32_t CTR_NONCE0_W3; /**< NONCE03 Register, offset: 0x2C */
3151 __O uint32_t CTR_NONCE1_W0; /**< NONCE10 Register, offset: 0x30 */
3152 __O uint32_t CTR_NONCE1_W1; /**< NONCE11 Register, offset: 0x34 */
3153 __O uint32_t CTR_NONCE1_W2; /**< NONCE12 Register, offset: 0x38 */
3154 __O uint32_t CTR_NONCE1_W3; /**< NONCE13 Register, offset: 0x3C */
3155 __IO uint32_t REGION1_TOP; /**< Region1 Top Address Register, offset: 0x40 */
3156 __IO uint32_t REGION1_BOT; /**< Region1 Bottom Address Register, offset: 0x44 */
3157} BEE_Type;
3158
3159/* ----------------------------------------------------------------------------
3160 -- BEE Register Masks
3161 ---------------------------------------------------------------------------- */
3162
3163/*!
3164 * @addtogroup BEE_Register_Masks BEE Register Masks
3165 * @{
3166 */
3167
3168/*! @name CTRL - Control Register */
3169/*! @{ */
3170#define BEE_CTRL_BEE_ENABLE_MASK (0x1U)
3171#define BEE_CTRL_BEE_ENABLE_SHIFT (0U)
3172/*! BEE_ENABLE
3173 * 0b0..Disable BEE
3174 * 0b1..Enable BEE
3175 */
3176#define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)
3177#define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)
3178#define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)
3179#define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)
3180#define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)
3181#define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)
3182#define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)
3183#define BEE_CTRL_KEY_VALID_MASK (0x10U)
3184#define BEE_CTRL_KEY_VALID_SHIFT (4U)
3185#define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)
3186#define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)
3187#define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)
3188/*! KEY_REGION_SEL
3189 * 0b0..Load AES key for region0
3190 * 0b1..Load AES key for region1
3191 */
3192#define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)
3193#define BEE_CTRL_AC_PROT_EN_MASK (0x40U)
3194#define BEE_CTRL_AC_PROT_EN_SHIFT (6U)
3195#define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)
3196#define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)
3197#define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)
3198/*! LITTLE_ENDIAN
3199 * 0b0..The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8,
3200 * B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to
3201 * Byte0 to Byte15.
3202 * 0b1..The input and output data of AES core is not swapped.
3203 */
3204#define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)
3205#define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)
3206#define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)
3207#define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)
3208#define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)
3209#define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)
3210/*! CTRL_AES_MODE_R0
3211 * 0b0..ECB
3212 * 0b1..CTR
3213 */
3214#define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)
3215#define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)
3216#define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)
3217#define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)
3218#define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)
3219#define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)
3220/*! CTRL_AES_MODE_R1
3221 * 0b0..ECB
3222 * 0b1..CTR
3223 */
3224#define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)
3225#define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)
3226#define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)
3227#define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)
3228#define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)
3229#define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)
3230#define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)
3231#define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)
3232#define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)
3233#define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)
3234#define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)
3235#define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)
3236#define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)
3237#define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)
3238#define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)
3239#define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)
3240#define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)
3241#define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)
3242#define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)
3243#define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)
3244#define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)
3245#define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)
3246#define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)
3247#define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)
3248#define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)
3249#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)
3250#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)
3251#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)
3252#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)
3253#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)
3254#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)
3255#define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)
3256#define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)
3257#define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)
3258#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)
3259#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)
3260#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)
3261#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)
3262#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)
3263#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)
3264#define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)
3265#define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)
3266#define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)
3267/*! @} */
3268
3269/*! @name ADDR_OFFSET0 - Offset region 0 Register */
3270/*! @{ */
3271#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)
3272#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)
3273#define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)
3274#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)
3275#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)
3276#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)
3277/*! @} */
3278
3279/*! @name ADDR_OFFSET1 - Offset region 1 Register */
3280/*! @{ */
3281#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU)
3282#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U)
3283#define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK)
3284#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U)
3285#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U)
3286#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK)
3287/*! @} */
3288
3289/*! @name AES_KEY0_W0 - AES Key 0 Register */
3290/*! @{ */
3291#define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)
3292#define BEE_AES_KEY0_W0_KEY0_SHIFT (0U)
3293/*! KEY0 - AES 128 key from software
3294 */
3295#define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)
3296/*! @} */
3297
3298/*! @name AES_KEY0_W1 - AES Key 1 Register */
3299/*! @{ */
3300#define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)
3301#define BEE_AES_KEY0_W1_KEY1_SHIFT (0U)
3302/*! KEY1 - AES 128 key from software
3303 */
3304#define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)
3305/*! @} */
3306
3307/*! @name AES_KEY0_W2 - AES Key 2 Register */
3308/*! @{ */
3309#define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)
3310#define BEE_AES_KEY0_W2_KEY2_SHIFT (0U)
3311/*! KEY2 - AES 128 key from software
3312 */
3313#define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)
3314/*! @} */
3315
3316/*! @name AES_KEY0_W3 - AES Key 3 Register */
3317/*! @{ */
3318#define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)
3319#define BEE_AES_KEY0_W3_KEY3_SHIFT (0U)
3320/*! KEY3 - AES 128 key from software
3321 */
3322#define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)
3323/*! @} */
3324
3325/*! @name STATUS - Status Register */
3326/*! @{ */
3327#define BEE_STATUS_IRQ_VEC_MASK (0xFFU)
3328#define BEE_STATUS_IRQ_VEC_SHIFT (0U)
3329#define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)
3330#define BEE_STATUS_BEE_IDLE_MASK (0x100U)
3331#define BEE_STATUS_BEE_IDLE_SHIFT (8U)
3332#define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)
3333/*! @} */
3334
3335/*! @name CTR_NONCE0_W0 - NONCE00 Register */
3336/*! @{ */
3337#define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)
3338#define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)
3339#define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)
3340/*! @} */
3341
3342/*! @name CTR_NONCE0_W1 - NONCE01 Register */
3343/*! @{ */
3344#define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)
3345#define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)
3346#define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)
3347/*! @} */
3348
3349/*! @name CTR_NONCE0_W2 - NONCE02 Register */
3350/*! @{ */
3351#define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)
3352#define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)
3353#define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)
3354/*! @} */
3355
3356/*! @name CTR_NONCE0_W3 - NONCE03 Register */
3357/*! @{ */
3358#define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)
3359#define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)
3360#define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)
3361/*! @} */
3362
3363/*! @name CTR_NONCE1_W0 - NONCE10 Register */
3364/*! @{ */
3365#define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)
3366#define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)
3367#define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)
3368/*! @} */
3369
3370/*! @name CTR_NONCE1_W1 - NONCE11 Register */
3371/*! @{ */
3372#define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)
3373#define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)
3374#define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)
3375/*! @} */
3376
3377/*! @name CTR_NONCE1_W2 - NONCE12 Register */
3378/*! @{ */
3379#define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)
3380#define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)
3381#define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)
3382/*! @} */
3383
3384/*! @name CTR_NONCE1_W3 - NONCE13 Register */
3385/*! @{ */
3386#define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)
3387#define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)
3388#define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)
3389/*! @} */
3390
3391/*! @name REGION1_TOP - Region1 Top Address Register */
3392/*! @{ */
3393#define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)
3394#define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)
3395/*! REGION1_TOP - Address upper limit of region1
3396 */
3397#define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)
3398/*! @} */
3399
3400/*! @name REGION1_BOT - Region1 Bottom Address Register */
3401/*! @{ */
3402#define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)
3403#define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)
3404/*! REGION1_BOT - Address lower limit of region1
3405 */
3406#define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK)
3407/*! @} */
3408
3409
3410/*!
3411 * @}
3412 */ /* end of group BEE_Register_Masks */
3413
3414
3415/* BEE - Peripheral instance base addresses */
3416/** Peripheral BEE base address */
3417#define BEE_BASE (0x403EC000u)
3418/** Peripheral BEE base pointer */
3419#define BEE ((BEE_Type *)BEE_BASE)
3420/** Array initializer of BEE peripheral base addresses */
3421#define BEE_BASE_ADDRS { BEE_BASE }
3422/** Array initializer of BEE peripheral base pointers */
3423#define BEE_BASE_PTRS { BEE }
3424
3425/*!
3426 * @}
3427 */ /* end of group BEE_Peripheral_Access_Layer */
3428
3429
3430/* ----------------------------------------------------------------------------
3431 -- CAN Peripheral Access Layer
3432 ---------------------------------------------------------------------------- */
3433
3434/*!
3435 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
3436 * @{
3437 */
3438
3439/** CAN - Register Layout Typedef */
3440typedef struct {
3441 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
3442 __IO uint32_t CTRL1; /**< Control 1 Register..Control 1 register, offset: 0x4 */
3443 __IO uint32_t TIMER; /**< Free Running Timer Register..Free Running Timer, offset: 0x8 */
3444 uint8_t RESERVED_0[4];
3445 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
3446 __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register..Rx 14 Mask register, offset: 0x14 */
3447 __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register..Rx 15 Mask register, offset: 0x18 */
3448 __IO uint32_t ECR; /**< Error Counter Register..Error Counter, offset: 0x1C */
3449 __IO uint32_t ESR1; /**< Error and Status 1 Register..Error and Status 1 register, offset: 0x20 */
3450 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register..Interrupt Masks 2 register, offset: 0x24 */
3451 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register..Interrupt Masks 1 register, offset: 0x28 */
3452 __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register..Interrupt Flags 2 register, offset: 0x2C */
3453 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register..Interrupt Flags 1 register, offset: 0x30 */
3454 __IO uint32_t CTRL2; /**< Control 2 Register..Control 2 register, offset: 0x34 */
3455 __I uint32_t ESR2; /**< Error and Status 2 Register..Error and Status 2 register, offset: 0x38 */
3456 uint8_t RESERVED_1[8];
3457 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
3458 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register..Legacy Rx FIFO Global Mask register, offset: 0x48 */
3459 __I uint32_t RXFIR; /**< Rx FIFO Information Register..Legacy Rx FIFO Information Register, offset: 0x4C */
3460 __IO uint32_t CBT; /**< CAN Bit Timing Register, offset: 0x50 */
3461 uint8_t RESERVED_2[4];
3462 __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */
3463 __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */
3464 uint8_t RESERVED_3[32];
3465 union { /* offset: 0x80 */
3466 struct { /* offset: 0x80, array step: 0x10 */
3467 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
3468 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
3469 __IO uint32_t WORD[2]; /**< Message Buffer 0 WORD_8B Register..Message Buffer 63 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */
3470 } MB_8B[64];
3471 struct { /* offset: 0x80, array step: 0x18 */
3472 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 41 CS Register, array offset: 0x80, array step: 0x18 */
3473 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 41 ID Register, array offset: 0x84, array step: 0x18 */
3474 __IO uint32_t WORD[4]; /**< Message Buffer 0 WORD_16B Register..Message Buffer 41 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */
3475 } MB_16B[42];
3476 struct { /* offset: 0x80, array step: 0x28 */
3477 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 23 CS Register, array offset: 0x80, array step: 0x28 */
3478 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 23 ID Register, array offset: 0x84, array step: 0x28 */
3479 __IO uint32_t WORD[8]; /**< Message Buffer 0 WORD_32B Register..Message Buffer 23 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */
3480 } MB_32B[24];
3481 struct { /* offset: 0x80, array step: 0x48 */
3482 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 13 CS Register, array offset: 0x80, array step: 0x48 */
3483 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 13 ID Register, array offset: 0x84, array step: 0x48 */
3484 __IO uint32_t WORD[16]; /**< Message Buffer 0 WORD_64B Register..Message Buffer 13 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */
3485 } MB_64B[14];
3486 struct { /* offset: 0x80, array step: 0x10 */
3487 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
3488 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
3489 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
3490 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
3491 } MB[64];
3492 };
3493 uint8_t RESERVED_4[1024];
3494 __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
3495 uint8_t RESERVED_5[96];
3496 __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */
3497 uint8_t RESERVED_6[524];
3498 __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */
3499 __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */
3500 __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN bit Timing, offset: 0xBF8 */
3501 __IO uint32_t ETDC; /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */
3502 __IO uint32_t FDCTRL; /**< CAN FD Control Register, offset: 0xC00 */
3503 __IO uint32_t FDCBT; /**< CAN FD Bit Timing Register, offset: 0xC04 */
3504 __I uint32_t FDCRC; /**< CAN FD CRC Register, offset: 0xC08 */
3505 __IO uint32_t ERFCR; /**< Enhanced Rx FIFO Control Register, offset: 0xC0C */
3506 __IO uint32_t ERFIER; /**< Enhanced Rx FIFO Interrupt Enable register, offset: 0xC10 */
3507 __IO uint32_t ERFSR; /**< Enhanced Rx FIFO Status Register, offset: 0xC14 */
3508 uint8_t RESERVED_7[24];
3509 __I uint32_t HR_TIME_STAMP[64]; /**< High Resolution Time Stamp, array offset: 0xC30, array step: 0x4 */
3510 uint8_t RESERVED_8[8912];
3511 __IO uint32_t ERFFEL[128]; /**< Enhanced Rx FIFO Filter Element, array offset: 0x3000, array step: 0x4 */
3512} CAN_Type;
3513
3514/* ----------------------------------------------------------------------------
3515 -- CAN Register Masks
3516 ---------------------------------------------------------------------------- */
3517
3518/*!
3519 * @addtogroup CAN_Register_Masks CAN Register Masks
3520 * @{
3521 */
3522
3523/*! @name MCR - Module Configuration Register */
3524/*! @{ */
3525#define CAN_MCR_MAXMB_MASK (0x7FU)
3526#define CAN_MCR_MAXMB_SHIFT (0U)
3527/*! MAXMB - Number Of The Last Message Buffer
3528 */
3529#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
3530#define CAN_MCR_IDAM_MASK (0x300U)
3531#define CAN_MCR_IDAM_SHIFT (8U)
3532/*! IDAM - ID Acceptance Mode
3533 * 0b00..Format A One full ID (standard or extended) per ID filter Table element.
3534 * 0b01..Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element.
3535 * 0b10..Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element.
3536 * 0b11..Format D All frames rejected.
3537 */
3538#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
3539#define CAN_MCR_FDEN_MASK (0x800U)
3540#define CAN_MCR_FDEN_SHIFT (11U)
3541/*! FDEN - CAN FD operation enable
3542 * 0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
3543 * 0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
3544 */
3545#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
3546#define CAN_MCR_AEN_MASK (0x1000U)
3547#define CAN_MCR_AEN_SHIFT (12U)
3548/*! AEN - Abort Enable
3549 * 0b1..Abort enabled
3550 * 0b0..Abort disabled
3551 */
3552#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
3553#define CAN_MCR_LPRIOEN_MASK (0x2000U)
3554#define CAN_MCR_LPRIOEN_SHIFT (13U)
3555/*! LPRIOEN - Local Priority Enable
3556 * 0b1..Local Priority enabled
3557 * 0b0..Local Priority disabled
3558 */
3559#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
3560#define CAN_MCR_DMA_MASK (0x8000U)
3561#define CAN_MCR_DMA_SHIFT (15U)
3562/*! DMA - DMA Enable
3563 * 0b0..DMA feature for Legacy RX FIFO or Enhanced Rx FIFO are disabled.
3564 * 0b1..DMA feature for Legacy RX FIFO or Enhanced Rx FIFO are enabled.
3565 */
3566#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
3567#define CAN_MCR_IRMQ_MASK (0x10000U)
3568#define CAN_MCR_IRMQ_SHIFT (16U)
3569/*! IRMQ - Individual Rx Masking And Queue Enable
3570 * 0b1..Individual Rx masking and queue feature are enabled.
3571 * 0b0..Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY.
3572 */
3573#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
3574#define CAN_MCR_SRXDIS_MASK (0x20000U)
3575#define CAN_MCR_SRXDIS_SHIFT (17U)
3576/*! SRXDIS - Self Reception Disable
3577 * 0b1..Self reception disabled
3578 * 0b0..Self reception enabled
3579 */
3580#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
3581#define CAN_MCR_DOZE_MASK (0x40000U)
3582#define CAN_MCR_DOZE_SHIFT (18U)
3583/*! DOZE - Doze Mode Enable
3584 * 0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested.
3585 * 0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.
3586 */
3587#define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
3588#define CAN_MCR_WAKSRC_MASK (0x80000U)
3589#define CAN_MCR_WAKSRC_SHIFT (19U)
3590/*! WAKSRC - Wake Up Source
3591 * 0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus
3592 * 0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus.
3593 */
3594#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
3595#define CAN_MCR_LPMACK_MASK (0x100000U)
3596#define CAN_MCR_LPMACK_SHIFT (20U)
3597/*! LPMACK - Low-Power Mode Acknowledge
3598 * 0b1..FLEXCAN is either in Disable Mode, or Stop mode
3599 * 0b0..FLEXCAN not in any of the low power modes
3600 */
3601#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
3602#define CAN_MCR_WRNEN_MASK (0x200000U)
3603#define CAN_MCR_WRNEN_SHIFT (21U)
3604/*! WRNEN - Warning Interrupt Enable
3605 * 0b1..TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96.
3606 * 0b0..TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters.
3607 */
3608#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
3609#define CAN_MCR_SLFWAK_MASK (0x400000U)
3610#define CAN_MCR_SLFWAK_SHIFT (22U)
3611/*! SLFWAK - Self Wake Up
3612 * 0b1..FLEXCAN Self Wake Up feature is enabled
3613 * 0b0..FLEXCAN Self Wake Up feature is disabled
3614 */
3615#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
3616#define CAN_MCR_SUPV_MASK (0x800000U)
3617#define CAN_MCR_SUPV_SHIFT (23U)
3618/*! SUPV - Supervisor Mode
3619 * 0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access
3620 * behaves as though the access was done to an unimplemented register location
3621 * 0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses
3622 */
3623#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
3624#define CAN_MCR_FRZACK_MASK (0x1000000U)
3625#define CAN_MCR_FRZACK_SHIFT (24U)
3626/*! FRZACK - Freeze Mode Acknowledge
3627 * 0b1..FLEXCAN in Freeze Mode, prescaler stopped
3628 * 0b0..FLEXCAN not in Freeze Mode, prescaler running
3629 */
3630#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
3631#define CAN_MCR_SOFTRST_MASK (0x2000000U)
3632#define CAN_MCR_SOFTRST_SHIFT (25U)
3633/*! SOFTRST - Soft Reset
3634 * 0b1..Reset the registers
3635 * 0b0..No reset request
3636 */
3637#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
3638#define CAN_MCR_WAKMSK_MASK (0x4000000U)
3639#define CAN_MCR_WAKMSK_SHIFT (26U)
3640/*! WAKMSK - Wake Up Interrupt Mask
3641 * 0b1..Wake Up Interrupt is enabled
3642 * 0b0..Wake Up Interrupt is disabled
3643 */
3644#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
3645#define CAN_MCR_NOTRDY_MASK (0x8000000U)
3646#define CAN_MCR_NOTRDY_SHIFT (27U)
3647/*! NOTRDY - FlexCAN Not Ready
3648 * 0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode
3649 * 0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode
3650 */
3651#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
3652#define CAN_MCR_HALT_MASK (0x10000000U)
3653#define CAN_MCR_HALT_SHIFT (28U)
3654/*! HALT - Halt FlexCAN
3655 * 0b1..Enters Freeze Mode if the FRZ bit is asserted.
3656 * 0b0..No Freeze Mode request.
3657 */
3658#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
3659#define CAN_MCR_RFEN_MASK (0x20000000U)
3660#define CAN_MCR_RFEN_SHIFT (29U)
3661/*! RFEN - Legacy Rx FIFO Enable
3662 * 0b1..FIFO enabled
3663 * 0b0..FIFO not enabled
3664 */
3665#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
3666#define CAN_MCR_FRZ_MASK (0x40000000U)
3667#define CAN_MCR_FRZ_SHIFT (30U)
3668/*! FRZ - Freeze Enable
3669 * 0b1..Enabled to enter Freeze Mode
3670 * 0b0..Not enabled to enter Freeze Mode
3671 */
3672#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
3673#define CAN_MCR_MDIS_MASK (0x80000000U)
3674#define CAN_MCR_MDIS_SHIFT (31U)
3675/*! MDIS - Module Disable
3676 * 0b1..Disable the FLEXCAN module
3677 * 0b0..Enable the FLEXCAN module
3678 */
3679#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
3680/*! @} */
3681
3682/*! @name CTRL1 - Control 1 Register..Control 1 register */
3683/*! @{ */
3684#define CAN_CTRL1_PROPSEG_MASK (0x7U)
3685#define CAN_CTRL1_PROPSEG_SHIFT (0U)
3686/*! PROPSEG - Propagation Segment
3687 */
3688#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
3689#define CAN_CTRL1_LOM_MASK (0x8U)
3690#define CAN_CTRL1_LOM_SHIFT (3U)
3691/*! LOM - Listen-Only Mode
3692 * 0b1..FLEXCAN module operates in Listen Only Mode
3693 * 0b0..Listen Only Mode is deactivated
3694 */
3695#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
3696#define CAN_CTRL1_LBUF_MASK (0x10U)
3697#define CAN_CTRL1_LBUF_SHIFT (4U)
3698/*! LBUF - Lowest Buffer Transmitted First
3699 * 0b1..Lowest number buffer is transmitted first
3700 * 0b0..Buffer with highest priority is transmitted first
3701 */
3702#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
3703#define CAN_CTRL1_TSYN_MASK (0x20U)
3704#define CAN_CTRL1_TSYN_SHIFT (5U)
3705/*! TSYN - Timer Sync
3706 * 0b1..Timer Sync feature enabled
3707 * 0b0..Timer Sync feature disabled
3708 */
3709#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
3710#define CAN_CTRL1_BOFFREC_MASK (0x40U)
3711#define CAN_CTRL1_BOFFREC_SHIFT (6U)
3712/*! BOFFREC - Bus Off Recovery
3713 * 0b1..Automatic recovering from Bus Off state disabled
3714 * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B
3715 */
3716#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
3717#define CAN_CTRL1_SMP_MASK (0x80U)
3718#define CAN_CTRL1_SMP_SHIFT (7U)
3719/*! SMP - CAN Bit Sampling
3720 * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2
3721 * preceding samples, a majority rule is used
3722 * 0b0..Just one sample is used to determine the bit value
3723 */
3724#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
3725#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
3726#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
3727/*! RWRNMSK - Rx Warning Interrupt Mask
3728 * 0b1..Rx Warning Interrupt enabled
3729 * 0b0..Rx Warning Interrupt disabled
3730 */
3731#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
3732#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
3733#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
3734/*! TWRNMSK - Tx Warning Interrupt Mask
3735 * 0b1..Tx Warning Interrupt enabled
3736 * 0b0..Tx Warning Interrupt disabled
3737 */
3738#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
3739#define CAN_CTRL1_LPB_MASK (0x1000U)
3740#define CAN_CTRL1_LPB_SHIFT (12U)
3741/*! LPB - Loop Back Mode
3742 * 0b1..Loop Back enabled
3743 * 0b0..Loop Back disabled
3744 */
3745#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
3746#define CAN_CTRL1_CLKSRC_MASK (0x2000U)
3747#define CAN_CTRL1_CLKSRC_SHIFT (13U)
3748/*! CLKSRC - CAN Engine Clock Source
3749 * 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
3750 * 0b1..The CAN engine clock source is the peripheral clock.
3751 */
3752#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
3753#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
3754#define CAN_CTRL1_ERRMSK_SHIFT (14U)
3755/*! ERRMSK - Error Interrupt Mask
3756 * 0b1..Error interrupt enabled
3757 * 0b0..Error interrupt disabled
3758 */
3759#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
3760#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
3761#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
3762/*! BOFFMSK - Bus Off Interrupt Mask
3763 * 0b1..Bus Off interrupt enabled
3764 * 0b0..Bus Off interrupt disabled
3765 */
3766#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
3767#define CAN_CTRL1_PSEG2_MASK (0x70000U)
3768#define CAN_CTRL1_PSEG2_SHIFT (16U)
3769/*! PSEG2 - Phase Segment 2
3770 */
3771#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
3772#define CAN_CTRL1_PSEG1_MASK (0x380000U)
3773#define CAN_CTRL1_PSEG1_SHIFT (19U)
3774/*! PSEG1 - Phase Segment 1
3775 */
3776#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
3777#define CAN_CTRL1_RJW_MASK (0xC00000U)
3778#define CAN_CTRL1_RJW_SHIFT (22U)
3779/*! RJW - Resync Jump Width
3780 */
3781#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
3782#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
3783#define CAN_CTRL1_PRESDIV_SHIFT (24U)
3784/*! PRESDIV - Prescaler Division Factor
3785 */
3786#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
3787/*! @} */
3788
3789/*! @name TIMER - Free Running Timer Register..Free Running Timer */
3790/*! @{ */
3791#define CAN_TIMER_TIMER_MASK (0xFFFFU)
3792#define CAN_TIMER_TIMER_SHIFT (0U)
3793/*! TIMER - Timer Value
3794 */
3795#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
3796/*! @} */
3797
3798/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
3799/*! @{ */
3800#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
3801#define CAN_RXMGMASK_MG_SHIFT (0U)
3802/*! MG - Rx Mailboxes Global Mask Bits
3803 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received
3804 * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
3805 */
3806#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
3807/*! @} */
3808
3809/*! @name RX14MASK - Rx Buffer 14 Mask Register..Rx 14 Mask register */
3810/*! @{ */
3811#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
3812#define CAN_RX14MASK_RX14M_SHIFT (0U)
3813/*! RX14M - Rx Buffer 14 Mask Bits
3814 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
3815 * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
3816 */
3817#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
3818/*! @} */
3819
3820/*! @name RX15MASK - Rx Buffer 15 Mask Register..Rx 15 Mask register */
3821/*! @{ */
3822#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
3823#define CAN_RX15MASK_RX15M_SHIFT (0U)
3824/*! RX15M - Rx Buffer 15 Mask Bits
3825 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
3826 * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
3827 */
3828#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
3829/*! @} */
3830
3831/*! @name ECR - Error Counter Register..Error Counter */
3832/*! @{ */
3833#define CAN_ECR_TXERRCNT_MASK (0xFFU)
3834#define CAN_ECR_TXERRCNT_SHIFT (0U)
3835/*! TXERRCNT - Transmit Error Counter
3836 */
3837#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
3838#define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU)
3839#define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U)
3840#define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)
3841#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
3842#define CAN_ECR_RXERRCNT_SHIFT (8U)
3843/*! RXERRCNT - Receive Error Counter
3844 */
3845#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
3846#define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U)
3847#define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U)
3848#define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)
3849#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U)
3850#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U)
3851/*! TXERRCNT_FAST - Transmit Error Counter for fast bits
3852 */
3853#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
3854#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U)
3855#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U)
3856/*! RXERRCNT_FAST - Receive Error Counter for fast bits
3857 */
3858#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
3859/*! @} */
3860
3861/*! @name ESR1 - Error and Status 1 Register..Error and Status 1 register */
3862/*! @{ */
3863#define CAN_ESR1_WAKINT_MASK (0x1U)
3864#define CAN_ESR1_WAKINT_SHIFT (0U)