aboutsummaryrefslogtreecommitdiff
path: root/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/project_template/clock_config.c
diff options
context:
space:
mode:
Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/project_template/clock_config.c')
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/project_template/clock_config.c476
1 files changed, 476 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/project_template/clock_config.c
new file mode 100644
index 000000000..0453127df
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1061/project_template/clock_config.c
@@ -0,0 +1,476 @@
1/*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24!!GlobalInfo
25product: Clocks v5.0
26processor: MIMXRT1061xxxxA
27package_id: MIMXRT1061DVL6A
28mcu_data: ksdk2_0
29processor_version: 0.0.0
30 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
31
32#include "clock_config.h"
33#include "fsl_iomuxc.h"
34
35/*******************************************************************************
36 * Definitions
37 ******************************************************************************/
38
39/*******************************************************************************
40 * Variables
41 ******************************************************************************/
42/* System clock frequency. */
43extern uint32_t SystemCoreClock;
44
45/*******************************************************************************
46 ************************ BOARD_InitBootClocks function ************************
47 ******************************************************************************/
48void BOARD_InitBootClocks(void)
49{
50 BOARD_BootClockRUN();
51}
52
53/*******************************************************************************
54 ********************** Configuration BOARD_BootClockRUN ***********************
55 ******************************************************************************/
56/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
57!!Configuration
58name: BOARD_BootClockRUN
59called_from_default_init: true
60outputs:
61- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
62- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
63- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
64- {id: CLK_1M.outFreq, value: 1 MHz}
65- {id: CLK_24M.outFreq, value: 24 MHz}
66- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
67- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
68- {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz}
69- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
70- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
71- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
72- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
73- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
74- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
75- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
76- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
77- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
78- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
79- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
80- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
81- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
82- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
83- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
84- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
85- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
86- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
87- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
88- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
89- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
90- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
91- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
92- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
93- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
94- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
95- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
96- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
97- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
98- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
99- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
100settings:
101- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
102- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
103- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
104- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
105- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
106- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
107- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
108- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
109- {id: CCM.SEMC_PODF.scale, value: '8'}
110- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
111- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
112- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
113- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
114- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
115- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
116- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
117- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
118- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
119- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
120- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
121- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
122- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
123- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
124- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
125- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
126- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
127- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
128- {id: CCM_ANALOG.PLL4.denom, value: '50'}
129- {id: CCM_ANALOG.PLL4.div, value: '47'}
130- {id: CCM_ANALOG.PLL5.denom, value: '1'}
131- {id: CCM_ANALOG.PLL5.div, value: '40'}
132- {id: CCM_ANALOG.PLL5.num, value: '0'}
133- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
134- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
135sources:
136- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
137- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
138 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
139
140/*******************************************************************************
141 * Variables for BOARD_BootClockRUN configuration
142 ******************************************************************************/
143const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
144 .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
145 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
146};
147const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
148 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
149 .numerator = 0, /* 30 bit numerator of fractional loop divider */
150 .denominator = 1, /* 30 bit denominator of fractional loop divider */
151 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
152};
153const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
154 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
155 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
156};
157/*******************************************************************************
158 * Code for BOARD_BootClockRUN configuration
159 ******************************************************************************/
160void BOARD_BootClockRUN(void)
161{
162 /* Init RTC OSC clock frequency. */
163 CLOCK_SetRtcXtalFreq(32768U);
164 /* Enable 1MHz clock output. */
165 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
166 /* Use free 1MHz clock output. */
167 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
168 /* Set XTAL 24MHz clock frequency. */
169 CLOCK_SetXtalFreq(24000000U);
170 /* Enable XTAL 24MHz clock source. */
171 CLOCK_InitExternalClk(0);
172 /* Enable internal RC. */
173 CLOCK_InitRcOsc24M();
174 /* Switch clock source to external OSC. */
175 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
176 /* Set Oscillator ready counter value. */
177 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
178 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
179 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
180 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
181 /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
182 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
183 /* Waiting for DCDC_STS_DC_OK bit is asserted */
184 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
185 {
186 }
187 /* Set AHB_PODF. */
188 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
189 /* Disable IPG clock gate. */
190 CLOCK_DisableClock(kCLOCK_Adc1);
191 CLOCK_DisableClock(kCLOCK_Adc2);
192 CLOCK_DisableClock(kCLOCK_Xbar1);
193 CLOCK_DisableClock(kCLOCK_Xbar2);
194 CLOCK_DisableClock(kCLOCK_Xbar3);
195 /* Set IPG_PODF. */
196 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
197 /* Set ARM_PODF. */
198 CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
199 /* Set PERIPH_CLK2_PODF. */
200 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
201 /* Disable PERCLK clock gate. */
202 CLOCK_DisableClock(kCLOCK_Gpt1);
203 CLOCK_DisableClock(kCLOCK_Gpt1S);
204 CLOCK_DisableClock(kCLOCK_Gpt2);
205 CLOCK_DisableClock(kCLOCK_Gpt2S);
206 CLOCK_DisableClock(kCLOCK_Pit);
207 /* Set PERCLK_PODF. */
208 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
209 /* Disable USDHC1 clock gate. */
210 CLOCK_DisableClock(kCLOCK_Usdhc1);
211 /* Set USDHC1_PODF. */
212 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
213 /* Set Usdhc1 clock source. */
214 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
215 /* Disable USDHC2 clock gate. */
216 CLOCK_DisableClock(kCLOCK_Usdhc2);
217 /* Set USDHC2_PODF. */
218 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
219 /* Set Usdhc2 clock source. */
220 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
221 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
222 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
223 * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
224 * well.*/
225#ifndef SKIP_SYSCLK_INIT
226 /* Disable Semc clock gate. */
227 CLOCK_DisableClock(kCLOCK_Semc);
228 /* Set SEMC_PODF. */
229 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
230 /* Set Semc alt clock source. */
231 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
232 /* Set Semc clock source. */
233 CLOCK_SetMux(kCLOCK_SemcMux, 0);
234#endif
235 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
236 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
237 * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
238 * well.*/
239#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
240 /* Disable Flexspi clock gate. */
241 CLOCK_DisableClock(kCLOCK_FlexSpi);
242 /* Set FLEXSPI_PODF. */
243 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
244 /* Set Flexspi clock source. */
245 CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
246#endif
247 /* Disable Flexspi2 clock gate. */
248 CLOCK_DisableClock(kCLOCK_FlexSpi2);
249 /* Set FLEXSPI2_PODF. */
250 CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
251 /* Set Flexspi2 clock source. */
252 CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
253 /* Disable LPSPI clock gate. */
254 CLOCK_DisableClock(kCLOCK_Lpspi1);
255 CLOCK_DisableClock(kCLOCK_Lpspi2);
256 CLOCK_DisableClock(kCLOCK_Lpspi3);
257 CLOCK_DisableClock(kCLOCK_Lpspi4);
258 /* Set LPSPI_PODF. */
259 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
260 /* Set Lpspi clock source. */
261 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
262 /* Disable TRACE clock gate. */
263 CLOCK_DisableClock(kCLOCK_Trace);
264 /* Set TRACE_PODF. */
265 CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
266 /* Set Trace clock source. */
267 CLOCK_SetMux(kCLOCK_TraceMux, 2);
268 /* Disable SAI1 clock gate. */
269 CLOCK_DisableClock(kCLOCK_Sai1);
270 /* Set SAI1_CLK_PRED. */
271 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
272 /* Set SAI1_CLK_PODF. */
273 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
274 /* Set Sai1 clock source. */
275 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
276 /* Disable SAI2 clock gate. */
277 CLOCK_DisableClock(kCLOCK_Sai2);
278 /* Set SAI2_CLK_PRED. */
279 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
280 /* Set SAI2_CLK_PODF. */
281 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
282 /* Set Sai2 clock source. */
283 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
284 /* Disable SAI3 clock gate. */
285 CLOCK_DisableClock(kCLOCK_Sai3);
286 /* Set SAI3_CLK_PRED. */
287 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
288 /* Set SAI3_CLK_PODF. */
289 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
290 /* Set Sai3 clock source. */
291 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
292 /* Disable Lpi2c clock gate. */
293 CLOCK_DisableClock(kCLOCK_Lpi2c1);
294 CLOCK_DisableClock(kCLOCK_Lpi2c2);
295 CLOCK_DisableClock(kCLOCK_Lpi2c3);
296 /* Set LPI2C_CLK_PODF. */
297 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
298 /* Set Lpi2c clock source. */
299 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
300 /* Disable CAN clock gate. */
301 CLOCK_DisableClock(kCLOCK_Can1);
302 CLOCK_DisableClock(kCLOCK_Can2);
303 CLOCK_DisableClock(kCLOCK_Can3);
304 CLOCK_DisableClock(kCLOCK_Can1S);
305 CLOCK_DisableClock(kCLOCK_Can2S);
306 CLOCK_DisableClock(kCLOCK_Can3S);
307 /* Set CAN_CLK_PODF. */
308 CLOCK_SetDiv(kCLOCK_CanDiv, 1);
309 /* Set Can clock source. */
310 CLOCK_SetMux(kCLOCK_CanMux, 2);
311 /* Disable UART clock gate. */
312 CLOCK_DisableClock(kCLOCK_Lpuart1);
313 CLOCK_DisableClock(kCLOCK_Lpuart2);
314 CLOCK_DisableClock(kCLOCK_Lpuart3);
315 CLOCK_DisableClock(kCLOCK_Lpuart4);
316 CLOCK_DisableClock(kCLOCK_Lpuart5);
317 CLOCK_DisableClock(kCLOCK_Lpuart6);
318 CLOCK_DisableClock(kCLOCK_Lpuart7);
319 CLOCK_DisableClock(kCLOCK_Lpuart8);
320 /* Set UART_CLK_PODF. */
321 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
322 /* Set Uart clock source. */
323 CLOCK_SetMux(kCLOCK_UartMux, 0);
324 /* Disable SPDIF clock gate. */
325 CLOCK_DisableClock(kCLOCK_Spdif);
326 /* Set SPDIF0_CLK_PRED. */
327 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
328 /* Set SPDIF0_CLK_PODF. */
329 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
330 /* Set Spdif clock source. */
331 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
332 /* Disable Flexio1 clock gate. */
333 CLOCK_DisableClock(kCLOCK_Flexio1);
334 /* Set FLEXIO1_CLK_PRED. */
335 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
336 /* Set FLEXIO1_CLK_PODF. */
337 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
338 /* Set Flexio1 clock source. */
339 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
340 /* Disable Flexio2 clock gate. */
341 CLOCK_DisableClock(kCLOCK_Flexio2);
342 /* Set FLEXIO2_CLK_PRED. */
343 CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
344 /* Set FLEXIO2_CLK_PODF. */
345 CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
346 /* Set Flexio2 clock source. */
347 CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
348 /* Set Pll3 sw clock source. */
349 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
350 /* Init ARM PLL. */
351 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
352 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
353 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
354 * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
355 * well.*/
356#ifndef SKIP_SYSCLK_INIT
357 /* Init System PLL. */
358 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
359 /* Init System pfd0. */
360 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
361 /* Init System pfd1. */
362 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
363 /* Init System pfd2. */
364 CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
365 /* Init System pfd3. */
366 CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
367#endif
368 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
369 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
370 * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
371 * well.*/
372#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
373 /* Init Usb1 PLL. */
374 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
375 /* Init Usb1 pfd0. */
376 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
377 /* Init Usb1 pfd1. */
378 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
379 /* Init Usb1 pfd2. */
380 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
381 /* Init Usb1 pfd3. */
382 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
383 /* Disable Usb1 PLL output for USBPHY1. */
384 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
385#endif
386 /* DeInit Audio PLL. */
387 CLOCK_DeinitAudioPll();
388 /* Bypass Audio PLL. */
389 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
390 /* Set divider for Audio PLL. */
391 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
392 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
393 /* Enable Audio PLL output. */
394 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
395 /* DeInit Video PLL. */
396 CLOCK_DeinitVideoPll();
397 /* Bypass Video PLL. */
398 CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
399 /* Set divider for Video PLL. */
400 CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
401 /* Enable Video PLL output. */
402 CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
403 /* DeInit Enet PLL. */
404 CLOCK_DeinitEnetPll();
405 /* Bypass Enet PLL. */
406 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
407 /* Set Enet output divider. */
408 CCM_ANALOG->PLL_ENET =
409 (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
410 /* Enable Enet output. */
411 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
412 /* Set Enet2 output divider. */
413 CCM_ANALOG->PLL_ENET =
414 (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
415 /* Enable Enet2 output. */
416 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
417 /* Enable Enet25M output. */
418 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
419 /* DeInit Usb2 PLL. */
420 CLOCK_DeinitUsb2Pll();
421 /* Bypass Usb2 PLL. */
422 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
423 /* Enable Usb2 PLL output. */
424 CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
425 /* Set preperiph clock source. */
426 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
427 /* Set periph clock source. */
428 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
429 /* Set periph clock2 clock source. */
430 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
431 /* Set per clock source. */
432 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
433 /* Set lvds1 clock source. */
434 CCM_ANALOG->MISC1 =
435 (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
436 /* Set clock out1 divider. */
437 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
438 /* Set clock out1 source. */
439 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
440 /* Set clock out2 divider. */
441 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
442 /* Set clock out2 source. */
443 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
444 /* Set clock out1 drives clock out1. */
445 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
446 /* Disable clock out1. */
447 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
448 /* Disable clock out2. */
449 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
450 /* Set SAI1 MCLK1 clock source. */
451 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
452 /* Set SAI1 MCLK2 clock source. */
453 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
454 /* Set SAI1 MCLK3 clock source. */
455 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
456 /* Set SAI2 MCLK3 clock source. */
457 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
458 /* Set SAI3 MCLK3 clock source. */
459 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
460 /* Set MQS configuration. */
461 IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
462 /* Set ENET1 Tx clock source. */
463 IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
464 /* Set ENET2 Tx clock source. */
465#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0)))
466 IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false);
467#else
468 IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false);
469#endif
470 /* Set GPT1 High frequency reference clock source. */
471 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
472 /* Set GPT2 High frequency reference clock source. */
473 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
474 /* Set SystemCoreClock variable. */
475 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
476}
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 20:21:21 +0100