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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/MK22F12810.h13889
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/MK22F12810_features.h1779
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/arm/MK2x_FAC.FLMbin0 -> 54808 bytes
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/arm/MK_P128.FLMbin0 -> 28800 bytes
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/drivers/driver_reset.cmake14
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/drivers/fsl_clock.c1905
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/drivers/fsl_clock.h1361
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/fsl_device_registers.h35
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/gcc/MK22FN128xxx10_flash.ld208
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/gcc/MK22FN128xxx10_ram.ld199
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/gcc/startup_MK22F12810.S699
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/mcuxpresso/startup_mk22f12810.c868
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/mcuxpresso/startup_mk22f12810.cpp868
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/project_template/board.c23
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/project_template/board.h38
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/project_template/clock_config.c169
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/project_template/clock_config.h76
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/project_template/peripherals.c27
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/project_template/peripherals.h33
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/project_template/pin_mux.c60
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/project_template/pin_mux.h52
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/system_MK22F12810.c213
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/system_MK22F12810.h143
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/template/RTE_Device.h144
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/utilities/fsl_notifier.c209
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/utilities/fsl_notifier.h237
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/utilities/fsl_shell.c1085
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/utilities/fsl_shell.h292
28 files changed, 24626 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/MK22F12810.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/MK22F12810.h
new file mode 100644
index 000000000..df24b399f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/MK22F12810.h
@@ -0,0 +1,13889 @@
1/*
2** ###################################################################
3** Processors: MK22FN128VDC10
4** MK22FN128VLH10
5** MK22FN128VLL10
6** MK22FN128VMP10
7**
8** Compilers: Keil ARM C/C++ Compiler
9** Freescale C/C++ for Embedded ARM
10** GNU C Compiler
11** IAR ANSI C/C++ Compiler for ARM
12** MCUXpresso Compiler
13**
14** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
15** Version: rev. 1.6, 2015-02-19
16** Build: b180801
17**
18** Abstract:
19** CMSIS Peripheral Access Layer for MK22F12810
20**
21** Copyright 1997-2016 Freescale Semiconductor, Inc.
22** Copyright 2016-2018 NXP
23**
24** SPDX-License-Identifier: BSD-3-Clause
25**
26** http: www.nxp.com
27** mail: [email protected]
28**
29** Revisions:
30** - rev. 1.0 (2013-11-01)
31** Initial version.
32** - rev. 1.1 (2013-12-20)
33** Update according to reference manual rev. 0.1,
34** - rev. 1.2 (2014-02-10)
35** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
36** - rev. 1.3 (2014-05-06)
37** Update according to reference manual rev. 1.0,
38** Update of system and startup files.
39** Module access macro module_BASES replaced by module_BASE_PTRS.
40** - rev. 1.4 (2014-08-28)
41** Update of system files - default clock configuration changed.
42** Update of startup files - possibility to override DefaultISR added.
43** - rev. 1.5 (2014-10-14)
44** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
45** - rev. 1.6 (2015-02-19)
46** Renamed interrupt vector LLW to LLWU.
47**
48** ###################################################################
49*/
50
51/*!
52 * @file MK22F12810.h
53 * @version 1.6
54 * @date 2015-02-19
55 * @brief CMSIS Peripheral Access Layer for MK22F12810
56 *
57 * CMSIS Peripheral Access Layer for MK22F12810
58 */
59
60#ifndef _MK22F12810_H_
61#define _MK22F12810_H_ /**< Symbol preventing repeated inclusion */
62
63/** Memory map major version (memory maps with equal major version number are
64 * compatible) */
65#define MCU_MEM_MAP_VERSION 0x0100U
66/** Memory map minor version */
67#define MCU_MEM_MAP_VERSION_MINOR 0x0006U
68
69/**
70 * @brief Macro to calculate address of an aliased word in the peripheral
71 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
72 * 0x400FFFFF).
73 * @param Reg Register to access.
74 * @param Bit Bit number to access.
75 * @return Address of the aliased word in the peripheral bitband area.
76 */
77#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
78/**
79 * @brief Macro to access a single bit of a peripheral register (bit band region
80 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
81 * be used for peripherals with 32bit access allowed.
82 * @param Reg Register to access.
83 * @param Bit Bit number to access.
84 * @return Value of the targeted bit in the bit band region.
85 */
86#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
87#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
88/**
89 * @brief Macro to access a single bit of a peripheral register (bit band region
90 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
91 * be used for peripherals with 16bit access allowed.
92 * @param Reg Register to access.
93 * @param Bit Bit number to access.
94 * @return Value of the targeted bit in the bit band region.
95 */
96#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
97/**
98 * @brief Macro to access a single bit of a peripheral register (bit band region
99 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
100 * be used for peripherals with 8bit access allowed.
101 * @param Reg Register to access.
102 * @param Bit Bit number to access.
103 * @return Value of the targeted bit in the bit band region.
104 */
105#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
106
107/* ----------------------------------------------------------------------------
108 -- Interrupt vector numbers
109 ---------------------------------------------------------------------------- */
110
111/*!
112 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
113 * @{
114 */
115
116/** Interrupt Number Definitions */
117#define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */
118
119typedef enum IRQn {
120 /* Auxiliary constants */
121 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
122
123 /* Core interrupts */
124 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
125 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
126 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
127 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
128 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
129 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
130 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
131 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
132 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
133
134 /* Device specific interrupts */
135 DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
136 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
137 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
138 DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
139 Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
140 Reserved21_IRQn = 5, /**< Reserved interrupt 21 */
141 Reserved22_IRQn = 6, /**< Reserved interrupt 22 */
142 Reserved23_IRQn = 7, /**< Reserved interrupt 23 */
143 Reserved24_IRQn = 8, /**< Reserved interrupt 24 */
144 Reserved25_IRQn = 9, /**< Reserved interrupt 25 */
145 Reserved26_IRQn = 10, /**< Reserved interrupt 26 */
146 Reserved27_IRQn = 11, /**< Reserved interrupt 27 */
147 Reserved28_IRQn = 12, /**< Reserved interrupt 28 */
148 Reserved29_IRQn = 13, /**< Reserved interrupt 29 */
149 Reserved30_IRQn = 14, /**< Reserved interrupt 30 */
150 Reserved31_IRQn = 15, /**< Reserved interrupt 31 */
151 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
152 MCM_IRQn = 17, /**< Normal Interrupt */
153 FTF_IRQn = 18, /**< FTFA Command complete interrupt */
154 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
155 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
156 LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */
157 WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */
158 Reserved39_IRQn = 23, /**< Reserved Interrupt 39 */
159 I2C0_IRQn = 24, /**< I2C0 interrupt */
160 I2C1_IRQn = 25, /**< I2C1 interrupt */
161 SPI0_IRQn = 26, /**< SPI0 Interrupt */
162 SPI1_IRQn = 27, /**< SPI1 Interrupt */
163 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
164 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
165 LPUART0_IRQn = 30, /**< LPUART0 status/error interrupt */
166 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
167 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
168 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
169 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
170 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
171 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
172 Reserved53_IRQn = 37, /**< Reserved interrupt 53 */
173 Reserved54_IRQn = 38, /**< Reserved interrupt 54 */
174 ADC0_IRQn = 39, /**< ADC0 interrupt */
175 CMP0_IRQn = 40, /**< CMP0 interrupt */
176 CMP1_IRQn = 41, /**< CMP1 interrupt */
177 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
178 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
179 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
180 Reserved61_IRQn = 45, /**< Reserved interrupt 61 */
181 RTC_IRQn = 46, /**< RTC interrupt */
182 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
183 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
184 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
185 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
186 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
187 PDB0_IRQn = 52, /**< PDB0 Interrupt */
188 USB0_IRQn = 53, /**< USB0 interrupt */
189 Reserved70_IRQn = 54, /**< Reserved interrupt 70 */
190 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
191 DAC0_IRQn = 56, /**< DAC0 interrupt */
192 MCG_IRQn = 57, /**< MCG Interrupt */
193 LPTMR0_IRQn = 58, /**< LPTimer interrupt */
194 PORTA_IRQn = 59, /**< Port A interrupt */
195 PORTB_IRQn = 60, /**< Port B interrupt */
196 PORTC_IRQn = 61, /**< Port C interrupt */
197 PORTD_IRQn = 62, /**< Port D interrupt */
198 PORTE_IRQn = 63, /**< Port E interrupt */
199 SWI_IRQn = 64, /**< Software interrupt */
200 Reserved81_IRQn = 65, /**< Reserved interrupt 81 */
201 Reserved82_IRQn = 66, /**< Reserved interrupt 82 */
202 Reserved83_IRQn = 67, /**< Reserved interrupt 83 */
203 Reserved84_IRQn = 68, /**< Reserved interrupt 84 */
204 Reserved85_IRQn = 69, /**< Reserved interrupt 85 */
205 Reserved86_IRQn = 70, /**< Reserved interrupt 86 */
206 Reserved87_IRQn = 71, /**< Reserved interrupt 87 */
207 Reserved88_IRQn = 72, /**< Reserved interrupt 88 */
208 ADC1_IRQn = 73, /**< ADC1 interrupt */
209 Reserved90_IRQn = 74, /**< Reserved Interrupt 90 */
210 Reserved91_IRQn = 75, /**< Reserved Interrupt 91 */
211 Reserved92_IRQn = 76, /**< Reserved Interrupt 92 */
212 Reserved93_IRQn = 77, /**< Reserved Interrupt 93 */
213 Reserved94_IRQn = 78, /**< Reserved Interrupt 94 */
214 Reserved95_IRQn = 79, /**< Reserved Interrupt 95 */
215 Reserved96_IRQn = 80, /**< Reserved Interrupt 96 */
216 Reserved97_IRQn = 81, /**< Reserved Interrupt 97 */
217 Reserved98_IRQn = 82, /**< Reserved Interrupt 98 */
218 Reserved99_IRQn = 83, /**< Reserved Interrupt 99 */
219 Reserved100_IRQn = 84, /**< Reserved Interrupt 100 */
220 Reserved101_IRQn = 85 /**< Reserved Interrupt 101 */
221} IRQn_Type;
222
223/*!
224 * @}
225 */ /* end of group Interrupt_vector_numbers */
226
227
228/* ----------------------------------------------------------------------------
229 -- Cortex M4 Core Configuration
230 ---------------------------------------------------------------------------- */
231
232/*!
233 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
234 * @{
235 */
236
237#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
238#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
239#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
240#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
241
242#include "core_cm4.h" /* Core Peripheral Access Layer */
243#include "system_MK22F12810.h" /* Device specific configuration file */
244
245/*!
246 * @}
247 */ /* end of group Cortex_Core_Configuration */
248
249
250/* ----------------------------------------------------------------------------
251 -- Mapping Information
252 ---------------------------------------------------------------------------- */
253
254/*!
255 * @addtogroup Mapping_Information Mapping Information
256 * @{
257 */
258
259/** Mapping Information */
260/*!
261 * @addtogroup edma_request
262 * @{
263 */
264
265/*******************************************************************************
266 * Definitions
267 ******************************************************************************/
268
269/*!
270 * @brief Structure for the DMA hardware request
271 *
272 * Defines the structure for the DMA hardware request collections. The user can configure the
273 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
274 * of the hardware request varies according to the to SoC.
275 */
276typedef enum _dma_request_source
277{
278 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
279 kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
280 kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */
281 kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */
282 kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */
283 kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */
284 kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */
285 kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */
286 kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */
287 kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */
288 kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */
289 kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */
290 kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */
291 kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */
292 kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
293 kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
294 kDmaRequestMux0SPI1 = 16|0x100U, /**< SPI1 Transmit or Receive. */
295 kDmaRequestMux0Reserved17 = 17|0x100U, /**< Reserved17 */
296 kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0. */
297 kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1. */
298 kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
299 kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
300 kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
301 kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
302 kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
303 kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
304 kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */
305 kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */
306 kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */
307 kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */
308 kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */
309 kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */
310 kDmaRequestMux0Reserved32 = 32|0x100U, /**< Reserved32 */
311 kDmaRequestMux0Reserved33 = 33|0x100U, /**< Reserved33 */
312 kDmaRequestMux0Reserved34 = 34|0x100U, /**< Reserved34 */
313 kDmaRequestMux0Reserved35 = 35|0x100U, /**< Reserved35 */
314 kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */
315 kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */
316 kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */
317 kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */
318 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
319 kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */
320 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
321 kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
322 kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */
323 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
324 kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */
325 kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */
326 kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
327 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
328 kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
329 kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
330 kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
331 kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
332 kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */
333 kDmaRequestMux0Reserved55 = 55|0x100U, /**< Reserved55 */
334 kDmaRequestMux0Reserved56 = 56|0x100U, /**< Reserved56 */
335 kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */
336 kDmaRequestMux0LPUART0Rx = 58|0x100U, /**< LPUART0 Receive. */
337 kDmaRequestMux0LPUART0Tx = 59|0x100U, /**< LPUART0 Transmit. */
338 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
339 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
340 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
341 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
342} dma_request_source_t;
343
344/* @} */
345
346
347/*!
348 * @}
349 */ /* end of group Mapping_Information */
350
351
352/* ----------------------------------------------------------------------------
353 -- Device Peripheral Access Layer
354 ---------------------------------------------------------------------------- */
355
356/*!
357 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
358 * @{
359 */
360
361
362/*
363** Start of section using anonymous unions
364*/
365
366#if defined(__ARMCC_VERSION)
367 #if (__ARMCC_VERSION >= 6010050)
368 #pragma clang diagnostic push
369 #else
370 #pragma push
371 #pragma anon_unions
372 #endif
373#elif defined(__CWCC__)
374 #pragma push
375 #pragma cpp_extensions on
376#elif defined(__GNUC__)
377 /* anonymous unions are enabled by default */
378#elif defined(__IAR_SYSTEMS_ICC__)
379 #pragma language=extended
380#else
381 #error Not supported compiler type
382#endif
383
384/* ----------------------------------------------------------------------------
385 -- ADC Peripheral Access Layer
386 ---------------------------------------------------------------------------- */
387
388/*!
389 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
390 * @{
391 */
392
393/** ADC - Register Layout Typedef */
394typedef struct {
395 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
396 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
397 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
398 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
399 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
400 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
401 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
402 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
403 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
404 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
405 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
406 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
407 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
408 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
409 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
410 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
411 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
412 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
413 uint8_t RESERVED_0[4];
414 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
415 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
416 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
417 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
418 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
419 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
420 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
421} ADC_Type;
422
423/* ----------------------------------------------------------------------------
424 -- ADC Register Masks
425 ---------------------------------------------------------------------------- */
426
427/*!
428 * @addtogroup ADC_Register_Masks ADC Register Masks
429 * @{
430 */
431
432/*! @name SC1 - ADC Status and Control Registers 1 */
433/*! @{ */
434#define ADC_SC1_ADCH_MASK (0x1FU)
435#define ADC_SC1_ADCH_SHIFT (0U)
436/*! ADCH - Input channel select
437 * 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
438 * 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
439 * 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
440 * 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
441 * 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
442 * 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
443 * 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
444 * 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
445 * 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
446 * 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
447 * 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
448 * 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
449 * 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
450 * 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
451 * 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
452 * 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
453 * 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
454 * 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
455 * 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
456 * 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
457 * 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
458 * 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
459 * 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
460 * 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
461 * 0b11000..Reserved.
462 * 0b11001..Reserved.
463 * 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
464 * 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
465 * 0b11100..Reserved.
466 * 0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
467 * 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
468 * 0b11111..Module is disabled.
469 */
470#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
471#define ADC_SC1_DIFF_MASK (0x20U)
472#define ADC_SC1_DIFF_SHIFT (5U)
473/*! DIFF - Differential Mode Enable
474 * 0b0..Single-ended conversions and input channels are selected.
475 * 0b1..Differential conversions and input channels are selected.
476 */
477#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
478#define ADC_SC1_AIEN_MASK (0x40U)
479#define ADC_SC1_AIEN_SHIFT (6U)
480/*! AIEN - Interrupt Enable
481 * 0b0..Conversion complete interrupt is disabled.
482 * 0b1..Conversion complete interrupt is enabled.
483 */
484#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
485#define ADC_SC1_COCO_MASK (0x80U)
486#define ADC_SC1_COCO_SHIFT (7U)
487/*! COCO - Conversion Complete Flag
488 * 0b0..Conversion is not completed.
489 * 0b1..Conversion is completed.
490 */
491#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
492/*! @} */
493
494/* The count of ADC_SC1 */
495#define ADC_SC1_COUNT (2U)
496
497/*! @name CFG1 - ADC Configuration Register 1 */
498/*! @{ */
499#define ADC_CFG1_ADICLK_MASK (0x3U)
500#define ADC_CFG1_ADICLK_SHIFT (0U)
501/*! ADICLK - Input Clock Select
502 * 0b00..Bus clock
503 * 0b01..Alternate clock 2 (ALTCLK2)
504 * 0b10..Alternate clock (ALTCLK)
505 * 0b11..Asynchronous clock (ADACK)
506 */
507#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
508#define ADC_CFG1_MODE_MASK (0xCU)
509#define ADC_CFG1_MODE_SHIFT (2U)
510/*! MODE - Conversion mode selection
511 * 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.
512 * 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output.
513 * 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output
514 * 0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output
515 */
516#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
517#define ADC_CFG1_ADLSMP_MASK (0x10U)
518#define ADC_CFG1_ADLSMP_SHIFT (4U)
519/*! ADLSMP - Sample Time Configuration
520 * 0b0..Short sample time.
521 * 0b1..Long sample time.
522 */
523#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
524#define ADC_CFG1_ADIV_MASK (0x60U)
525#define ADC_CFG1_ADIV_SHIFT (5U)
526/*! ADIV - Clock Divide Select
527 * 0b00..The divide ratio is 1 and the clock rate is input clock.
528 * 0b01..The divide ratio is 2 and the clock rate is (input clock)/2.
529 * 0b10..The divide ratio is 4 and the clock rate is (input clock)/4.
530 * 0b11..The divide ratio is 8 and the clock rate is (input clock)/8.
531 */
532#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
533#define ADC_CFG1_ADLPC_MASK (0x80U)
534#define ADC_CFG1_ADLPC_SHIFT (7U)
535/*! ADLPC - Low-Power Configuration
536 * 0b0..Normal power configuration.
537 * 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed.
538 */
539#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
540/*! @} */
541
542/*! @name CFG2 - ADC Configuration Register 2 */
543/*! @{ */
544#define ADC_CFG2_ADLSTS_MASK (0x3U)
545#define ADC_CFG2_ADLSTS_SHIFT (0U)
546/*! ADLSTS - Long Sample Time Select
547 * 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
548 * 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time.
549 * 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time.
550 * 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.
551 */
552#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
553#define ADC_CFG2_ADHSC_MASK (0x4U)
554#define ADC_CFG2_ADHSC_SHIFT (2U)
555/*! ADHSC - High-Speed Configuration
556 * 0b0..Normal conversion sequence selected.
557 * 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
558 */
559#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
560#define ADC_CFG2_ADACKEN_MASK (0x8U)
561#define ADC_CFG2_ADACKEN_SHIFT (3U)
562/*! ADACKEN - Asynchronous Clock Output Enable
563 * 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
564 * 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC.
565 */
566#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
567#define ADC_CFG2_MUXSEL_MASK (0x10U)
568#define ADC_CFG2_MUXSEL_SHIFT (4U)
569/*! MUXSEL - ADC Mux Select
570 * 0b0..ADxxa channels are selected.
571 * 0b1..ADxxb channels are selected.
572 */
573#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
574/*! @} */
575
576/*! @name R - ADC Data Result Register */
577/*! @{ */
578#define ADC_R_D_MASK (0xFFFFU)
579#define ADC_R_D_SHIFT (0U)
580#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
581/*! @} */
582
583/* The count of ADC_R */
584#define ADC_R_COUNT (2U)
585
586/*! @name CV1 - Compare Value Registers */
587/*! @{ */
588#define ADC_CV1_CV_MASK (0xFFFFU)
589#define ADC_CV1_CV_SHIFT (0U)
590#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
591/*! @} */
592
593/*! @name CV2 - Compare Value Registers */
594/*! @{ */
595#define ADC_CV2_CV_MASK (0xFFFFU)
596#define ADC_CV2_CV_SHIFT (0U)
597#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
598/*! @} */
599
600/*! @name SC2 - Status and Control Register 2 */
601/*! @{ */
602#define ADC_SC2_REFSEL_MASK (0x3U)
603#define ADC_SC2_REFSEL_SHIFT (0U)
604/*! REFSEL - Voltage Reference Selection
605 * 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL
606 * 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
607 * 0b10..Reserved
608 * 0b11..Reserved
609 */
610#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
611#define ADC_SC2_DMAEN_MASK (0x4U)
612#define ADC_SC2_DMAEN_SHIFT (2U)
613/*! DMAEN - DMA Enable
614 * 0b0..DMA is disabled.
615 * 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
616 */
617#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
618#define ADC_SC2_ACREN_MASK (0x8U)
619#define ADC_SC2_ACREN_SHIFT (3U)
620/*! ACREN - Compare Function Range Enable
621 * 0b0..Range function disabled. Only CV1 is compared.
622 * 0b1..Range function enabled. Both CV1 and CV2 are compared.
623 */
624#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
625#define ADC_SC2_ACFGT_MASK (0x10U)
626#define ADC_SC2_ACFGT_SHIFT (4U)
627/*! ACFGT - Compare Function Greater Than Enable
628 * 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
629 * 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
630 */
631#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
632#define ADC_SC2_ACFE_MASK (0x20U)
633#define ADC_SC2_ACFE_SHIFT (5U)
634/*! ACFE - Compare Function Enable
635 * 0b0..Compare function disabled.
636 * 0b1..Compare function enabled.
637 */
638#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
639#define ADC_SC2_ADTRG_MASK (0x40U)
640#define ADC_SC2_ADTRG_SHIFT (6U)
641/*! ADTRG - Conversion Trigger Select
642 * 0b0..Software trigger selected.
643 * 0b1..Hardware trigger selected.
644 */
645#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
646#define ADC_SC2_ADACT_MASK (0x80U)
647#define ADC_SC2_ADACT_SHIFT (7U)
648/*! ADACT - Conversion Active
649 * 0b0..Conversion not in progress.
650 * 0b1..Conversion in progress.
651 */
652#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
653/*! @} */
654
655/*! @name SC3 - Status and Control Register 3 */
656/*! @{ */
657#define ADC_SC3_AVGS_MASK (0x3U)
658#define ADC_SC3_AVGS_SHIFT (0U)
659/*! AVGS - Hardware Average Select
660 * 0b00..4 samples averaged.
661 * 0b01..8 samples averaged.
662 * 0b10..16 samples averaged.
663 * 0b11..32 samples averaged.
664 */
665#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
666#define ADC_SC3_AVGE_MASK (0x4U)
667#define ADC_SC3_AVGE_SHIFT (2U)
668/*! AVGE - Hardware Average Enable
669 * 0b0..Hardware average function disabled.
670 * 0b1..Hardware average function enabled.
671 */
672#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
673#define ADC_SC3_ADCO_MASK (0x8U)
674#define ADC_SC3_ADCO_SHIFT (3U)
675/*! ADCO - Continuous Conversion Enable
676 * 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
677 * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
678 */
679#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
680#define ADC_SC3_CALF_MASK (0x40U)
681#define ADC_SC3_CALF_SHIFT (6U)
682/*! CALF - Calibration Failed Flag
683 * 0b0..Calibration completed normally.
684 * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
685 */
686#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
687#define ADC_SC3_CAL_MASK (0x80U)
688#define ADC_SC3_CAL_SHIFT (7U)
689#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
690/*! @} */
691
692/*! @name OFS - ADC Offset Correction Register */
693/*! @{ */
694#define ADC_OFS_OFS_MASK (0xFFFFU)
695#define ADC_OFS_OFS_SHIFT (0U)
696#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
697/*! @} */
698
699/*! @name PG - ADC Plus-Side Gain Register */
700/*! @{ */
701#define ADC_PG_PG_MASK (0xFFFFU)
702#define ADC_PG_PG_SHIFT (0U)
703#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
704/*! @} */
705
706/*! @name MG - ADC Minus-Side Gain Register */
707/*! @{ */
708#define ADC_MG_MG_MASK (0xFFFFU)
709#define ADC_MG_MG_SHIFT (0U)
710#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
711/*! @} */
712
713/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
714/*! @{ */
715#define ADC_CLPD_CLPD_MASK (0x3FU)
716#define ADC_CLPD_CLPD_SHIFT (0U)
717#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
718/*! @} */
719
720/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
721/*! @{ */
722#define ADC_CLPS_CLPS_MASK (0x3FU)
723#define ADC_CLPS_CLPS_SHIFT (0U)
724#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
725/*! @} */
726
727/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
728/*! @{ */
729#define ADC_CLP4_CLP4_MASK (0x3FFU)
730#define ADC_CLP4_CLP4_SHIFT (0U)
731#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
732/*! @} */
733
734/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
735/*! @{ */
736#define ADC_CLP3_CLP3_MASK (0x1FFU)
737#define ADC_CLP3_CLP3_SHIFT (0U)
738#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
739/*! @} */
740
741/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
742/*! @{ */
743#define ADC_CLP2_CLP2_MASK (0xFFU)
744#define ADC_CLP2_CLP2_SHIFT (0U)
745#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
746/*! @} */
747
748/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
749/*! @{ */
750#define ADC_CLP1_CLP1_MASK (0x7FU)
751#define ADC_CLP1_CLP1_SHIFT (0U)
752#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
753/*! @} */
754
755/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
756/*! @{ */
757#define ADC_CLP0_CLP0_MASK (0x3FU)
758#define ADC_CLP0_CLP0_SHIFT (0U)
759#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
760/*! @} */
761
762/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
763/*! @{ */
764#define ADC_CLMD_CLMD_MASK (0x3FU)
765#define ADC_CLMD_CLMD_SHIFT (0U)
766#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
767/*! @} */
768
769/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
770/*! @{ */
771#define ADC_CLMS_CLMS_MASK (0x3FU)
772#define ADC_CLMS_CLMS_SHIFT (0U)
773#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
774/*! @} */
775
776/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
777/*! @{ */
778#define ADC_CLM4_CLM4_MASK (0x3FFU)
779#define ADC_CLM4_CLM4_SHIFT (0U)
780#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
781/*! @} */
782
783/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
784/*! @{ */
785#define ADC_CLM3_CLM3_MASK (0x1FFU)
786#define ADC_CLM3_CLM3_SHIFT (0U)
787#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
788/*! @} */
789
790/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
791/*! @{ */
792#define ADC_CLM2_CLM2_MASK (0xFFU)
793#define ADC_CLM2_CLM2_SHIFT (0U)
794#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
795/*! @} */
796
797/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
798/*! @{ */
799#define ADC_CLM1_CLM1_MASK (0x7FU)
800#define ADC_CLM1_CLM1_SHIFT (0U)
801#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
802/*! @} */
803
804/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
805/*! @{ */
806#define ADC_CLM0_CLM0_MASK (0x3FU)
807#define ADC_CLM0_CLM0_SHIFT (0U)
808#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
809/*! @} */
810
811
812/*!
813 * @}
814 */ /* end of group ADC_Register_Masks */
815
816
817/* ADC - Peripheral instance base addresses */
818/** Peripheral ADC0 base address */
819#define ADC0_BASE (0x4003B000u)
820/** Peripheral ADC0 base pointer */
821#define ADC0 ((ADC_Type *)ADC0_BASE)
822/** Peripheral ADC1 base address */
823#define ADC1_BASE (0x40027000u)
824/** Peripheral ADC1 base pointer */
825#define ADC1 ((ADC_Type *)ADC1_BASE)
826/** Array initializer of ADC peripheral base addresses */
827#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
828/** Array initializer of ADC peripheral base pointers */
829#define ADC_BASE_PTRS { ADC0, ADC1 }
830/** Interrupt vectors for the ADC peripheral type */
831#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
832
833/*!
834 * @}
835 */ /* end of group ADC_Peripheral_Access_Layer */
836
837
838/* ----------------------------------------------------------------------------
839 -- CMP Peripheral Access Layer
840 ---------------------------------------------------------------------------- */
841
842/*!
843 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
844 * @{
845 */
846
847/** CMP - Register Layout Typedef */
848typedef struct {
849 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
850 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
851 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
852 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
853 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
854 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
855} CMP_Type;
856
857/* ----------------------------------------------------------------------------
858 -- CMP Register Masks
859 ---------------------------------------------------------------------------- */
860
861/*!
862 * @addtogroup CMP_Register_Masks CMP Register Masks
863 * @{
864 */
865
866/*! @name CR0 - CMP Control Register 0 */
867/*! @{ */
868#define CMP_CR0_HYSTCTR_MASK (0x3U)
869#define CMP_CR0_HYSTCTR_SHIFT (0U)
870/*! HYSTCTR - Comparator hard block hysteresis control
871 * 0b00..Level 0
872 * 0b01..Level 1
873 * 0b10..Level 2
874 * 0b11..Level 3
875 */
876#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
877#define CMP_CR0_FILTER_CNT_MASK (0x70U)
878#define CMP_CR0_FILTER_CNT_SHIFT (4U)
879/*! FILTER_CNT - Filter Sample Count
880 * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
881 * 0b001..One sample must agree. The comparator output is simply sampled.
882 * 0b010..2 consecutive samples must agree.
883 * 0b011..3 consecutive samples must agree.
884 * 0b100..4 consecutive samples must agree.
885 * 0b101..5 consecutive samples must agree.
886 * 0b110..6 consecutive samples must agree.
887 * 0b111..7 consecutive samples must agree.
888 */
889#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
890/*! @} */
891
892/*! @name CR1 - CMP Control Register 1 */
893/*! @{ */
894#define CMP_CR1_EN_MASK (0x1U)
895#define CMP_CR1_EN_SHIFT (0U)
896/*! EN - Comparator Module Enable
897 * 0b0..Analog Comparator is disabled.
898 * 0b1..Analog Comparator is enabled.
899 */
900#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
901#define CMP_CR1_OPE_MASK (0x2U)
902#define CMP_CR1_OPE_SHIFT (1U)
903/*! OPE - Comparator Output Pin Enable
904 * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
905 * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.
906 */
907#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
908#define CMP_CR1_COS_MASK (0x4U)
909#define CMP_CR1_COS_SHIFT (2U)
910/*! COS - Comparator Output Select
911 * 0b0..Set the filtered comparator output (CMPO) to equal COUT.
912 * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
913 */
914#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
915#define CMP_CR1_INV_MASK (0x8U)
916#define CMP_CR1_INV_SHIFT (3U)
917/*! INV - Comparator INVERT
918 * 0b0..Does not invert the comparator output.
919 * 0b1..Inverts the comparator output.
920 */
921#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
922#define CMP_CR1_PMODE_MASK (0x10U)
923#define CMP_CR1_PMODE_SHIFT (4U)
924/*! PMODE - Power Mode Select
925 * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
926 * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
927 */
928#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
929#define CMP_CR1_TRIGM_MASK (0x20U)
930#define CMP_CR1_TRIGM_SHIFT (5U)
931/*! TRIGM - Trigger Mode Enable
932 * 0b0..Trigger mode is disabled.
933 * 0b1..Trigger mode is enabled.
934 */
935#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
936#define CMP_CR1_WE_MASK (0x40U)
937#define CMP_CR1_WE_SHIFT (6U)
938/*! WE - Windowing Enable
939 * 0b0..Windowing mode is not selected.
940 * 0b1..Windowing mode is selected.
941 */
942#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
943#define CMP_CR1_SE_MASK (0x80U)
944#define CMP_CR1_SE_SHIFT (7U)
945/*! SE - Sample Enable
946 * 0b0..Sampling mode is not selected.
947 * 0b1..Sampling mode is selected.
948 */
949#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
950/*! @} */
951
952/*! @name FPR - CMP Filter Period Register */
953/*! @{ */
954#define CMP_FPR_FILT_PER_MASK (0xFFU)
955#define CMP_FPR_FILT_PER_SHIFT (0U)
956#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
957/*! @} */
958
959/*! @name SCR - CMP Status and Control Register */
960/*! @{ */
961#define CMP_SCR_COUT_MASK (0x1U)
962#define CMP_SCR_COUT_SHIFT (0U)
963#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
964#define CMP_SCR_CFF_MASK (0x2U)
965#define CMP_SCR_CFF_SHIFT (1U)
966/*! CFF - Analog Comparator Flag Falling
967 * 0b0..Falling-edge on COUT has not been detected.
968 * 0b1..Falling-edge on COUT has occurred.
969 */
970#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
971#define CMP_SCR_CFR_MASK (0x4U)
972#define CMP_SCR_CFR_SHIFT (2U)
973/*! CFR - Analog Comparator Flag Rising
974 * 0b0..Rising-edge on COUT has not been detected.
975 * 0b1..Rising-edge on COUT has occurred.
976 */
977#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
978#define CMP_SCR_IEF_MASK (0x8U)
979#define CMP_SCR_IEF_SHIFT (3U)
980/*! IEF - Comparator Interrupt Enable Falling
981 * 0b0..Interrupt is disabled.
982 * 0b1..Interrupt is enabled.
983 */
984#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
985#define CMP_SCR_IER_MASK (0x10U)
986#define CMP_SCR_IER_SHIFT (4U)
987/*! IER - Comparator Interrupt Enable Rising
988 * 0b0..Interrupt is disabled.
989 * 0b1..Interrupt is enabled.
990 */
991#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
992#define CMP_SCR_DMAEN_MASK (0x40U)
993#define CMP_SCR_DMAEN_SHIFT (6U)
994/*! DMAEN - DMA Enable Control
995 * 0b0..DMA is disabled.
996 * 0b1..DMA is enabled.
997 */
998#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
999/*! @} */
1000
1001/*! @name DACCR - DAC Control Register */
1002/*! @{ */
1003#define CMP_DACCR_VOSEL_MASK (0x3FU)
1004#define CMP_DACCR_VOSEL_SHIFT (0U)
1005#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
1006#define CMP_DACCR_VRSEL_MASK (0x40U)
1007#define CMP_DACCR_VRSEL_SHIFT (6U)
1008/*! VRSEL - Supply Voltage Reference Source Select
1009 * 0b0..Vin1 is selected as resistor ladder network supply reference.
1010 * 0b1..Vin2 is selected as resistor ladder network supply reference.
1011 */
1012#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
1013#define CMP_DACCR_DACEN_MASK (0x80U)
1014#define CMP_DACCR_DACEN_SHIFT (7U)
1015/*! DACEN - DAC Enable
1016 * 0b0..DAC is disabled.
1017 * 0b1..DAC is enabled.
1018 */
1019#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
1020/*! @} */
1021
1022/*! @name MUXCR - MUX Control Register */
1023/*! @{ */
1024#define CMP_MUXCR_MSEL_MASK (0x7U)
1025#define CMP_MUXCR_MSEL_SHIFT (0U)
1026/*! MSEL - Minus Input Mux Control
1027 * 0b000..IN0
1028 * 0b001..IN1
1029 * 0b010..IN2
1030 * 0b011..IN3
1031 * 0b100..IN4
1032 * 0b101..IN5
1033 * 0b110..IN6
1034 * 0b111..IN7
1035 */
1036#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
1037#define CMP_MUXCR_PSEL_MASK (0x38U)
1038#define CMP_MUXCR_PSEL_SHIFT (3U)
1039/*! PSEL - Plus Input Mux Control
1040 * 0b000..IN0
1041 * 0b001..IN1
1042 * 0b010..IN2
1043 * 0b011..IN3
1044 * 0b100..IN4
1045 * 0b101..IN5
1046 * 0b110..IN6
1047 * 0b111..IN7
1048 */
1049#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
1050/*! @} */
1051
1052
1053/*!
1054 * @}
1055 */ /* end of group CMP_Register_Masks */
1056
1057
1058/* CMP - Peripheral instance base addresses */
1059/** Peripheral CMP0 base address */
1060#define CMP0_BASE (0x40073000u)
1061/** Peripheral CMP0 base pointer */
1062#define CMP0 ((CMP_Type *)CMP0_BASE)
1063/** Peripheral CMP1 base address */
1064#define CMP1_BASE (0x40073008u)
1065/** Peripheral CMP1 base pointer */
1066#define CMP1 ((CMP_Type *)CMP1_BASE)
1067/** Array initializer of CMP peripheral base addresses */
1068#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
1069/** Array initializer of CMP peripheral base pointers */
1070#define CMP_BASE_PTRS { CMP0, CMP1 }
1071/** Interrupt vectors for the CMP peripheral type */
1072#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
1073
1074/*!
1075 * @}
1076 */ /* end of group CMP_Peripheral_Access_Layer */
1077
1078
1079/* ----------------------------------------------------------------------------
1080 -- CRC Peripheral Access Layer
1081 ---------------------------------------------------------------------------- */
1082
1083/*!
1084 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
1085 * @{
1086 */
1087
1088/** CRC - Register Layout Typedef */
1089typedef struct {
1090 union { /* offset: 0x0 */
1091 struct { /* offset: 0x0 */
1092 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
1093 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
1094 } ACCESS16BIT;
1095 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
1096 struct { /* offset: 0x0 */
1097 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
1098 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
1099 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
1100 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
1101 } ACCESS8BIT;
1102 };
1103 union { /* offset: 0x4 */
1104 struct { /* offset: 0x4 */
1105 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
1106 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
1107 } GPOLY_ACCESS16BIT;
1108 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
1109 struct { /* offset: 0x4 */
1110 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
1111 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
1112 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
1113 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
1114 } GPOLY_ACCESS8BIT;
1115 };
1116 union { /* offset: 0x8 */
1117 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
1118 struct { /* offset: 0x8 */
1119 uint8_t RESERVED_0[3];
1120 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
1121 } CTRL_ACCESS8BIT;
1122 };
1123} CRC_Type;
1124
1125/* ----------------------------------------------------------------------------
1126 -- CRC Register Masks
1127 ---------------------------------------------------------------------------- */
1128
1129/*!
1130 * @addtogroup CRC_Register_Masks CRC Register Masks
1131 * @{
1132 */
1133
1134/*! @name DATAL - CRC_DATAL register. */
1135/*! @{ */
1136#define CRC_DATAL_DATAL_MASK (0xFFFFU)
1137#define CRC_DATAL_DATAL_SHIFT (0U)
1138#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
1139/*! @} */
1140
1141/*! @name DATAH - CRC_DATAH register. */
1142/*! @{ */
1143#define CRC_DATAH_DATAH_MASK (0xFFFFU)
1144#define CRC_DATAH_DATAH_SHIFT (0U)
1145#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
1146/*! @} */
1147
1148/*! @name DATA - CRC Data register */
1149/*! @{ */
1150#define CRC_DATA_LL_MASK (0xFFU)
1151#define CRC_DATA_LL_SHIFT (0U)
1152#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
1153#define CRC_DATA_LU_MASK (0xFF00U)
1154#define CRC_DATA_LU_SHIFT (8U)
1155#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
1156#define CRC_DATA_HL_MASK (0xFF0000U)
1157#define CRC_DATA_HL_SHIFT (16U)
1158#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
1159#define CRC_DATA_HU_MASK (0xFF000000U)
1160#define CRC_DATA_HU_SHIFT (24U)
1161#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
1162/*! @} */
1163
1164/*! @name DATALL - CRC_DATALL register. */
1165/*! @{ */
1166#define CRC_DATALL_DATALL_MASK (0xFFU)
1167#define CRC_DATALL_DATALL_SHIFT (0U)
1168#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
1169/*! @} */
1170
1171/*! @name DATALU - CRC_DATALU register. */
1172/*! @{ */
1173#define CRC_DATALU_DATALU_MASK (0xFFU)
1174#define CRC_DATALU_DATALU_SHIFT (0U)
1175#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
1176/*! @} */
1177
1178/*! @name DATAHL - CRC_DATAHL register. */
1179/*! @{ */
1180#define CRC_DATAHL_DATAHL_MASK (0xFFU)
1181#define CRC_DATAHL_DATAHL_SHIFT (0U)
1182#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
1183/*! @} */
1184
1185/*! @name DATAHU - CRC_DATAHU register. */
1186/*! @{ */
1187#define CRC_DATAHU_DATAHU_MASK (0xFFU)
1188#define CRC_DATAHU_DATAHU_SHIFT (0U)
1189#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
1190/*! @} */
1191
1192/*! @name GPOLYL - CRC_GPOLYL register. */
1193/*! @{ */
1194#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
1195#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
1196#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
1197/*! @} */
1198
1199/*! @name GPOLYH - CRC_GPOLYH register. */
1200/*! @{ */
1201#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
1202#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
1203#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
1204/*! @} */
1205
1206/*! @name GPOLY - CRC Polynomial register */
1207/*! @{ */
1208#define CRC_GPOLY_LOW_MASK (0xFFFFU)
1209#define CRC_GPOLY_LOW_SHIFT (0U)
1210#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
1211#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
1212#define CRC_GPOLY_HIGH_SHIFT (16U)
1213#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
1214/*! @} */
1215
1216/*! @name GPOLYLL - CRC_GPOLYLL register. */
1217/*! @{ */
1218#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
1219#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
1220#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
1221/*! @} */
1222
1223/*! @name GPOLYLU - CRC_GPOLYLU register. */
1224/*! @{ */
1225#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
1226#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
1227#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
1228/*! @} */
1229
1230/*! @name GPOLYHL - CRC_GPOLYHL register. */
1231/*! @{ */
1232#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
1233#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
1234#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
1235/*! @} */
1236
1237/*! @name GPOLYHU - CRC_GPOLYHU register. */
1238/*! @{ */
1239#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
1240#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
1241#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
1242/*! @} */
1243
1244/*! @name CTRL - CRC Control register */
1245/*! @{ */
1246#define CRC_CTRL_TCRC_MASK (0x1000000U)
1247#define CRC_CTRL_TCRC_SHIFT (24U)
1248/*! TCRC
1249 * 0b0..16-bit CRC protocol.
1250 * 0b1..32-bit CRC protocol.
1251 */
1252#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
1253#define CRC_CTRL_WAS_MASK (0x2000000U)
1254#define CRC_CTRL_WAS_SHIFT (25U)
1255/*! WAS - Write CRC Data Register As Seed
1256 * 0b0..Writes to the CRC data register are data values.
1257 * 0b1..Writes to the CRC data register are seed values.
1258 */
1259#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
1260#define CRC_CTRL_FXOR_MASK (0x4000000U)
1261#define CRC_CTRL_FXOR_SHIFT (26U)
1262/*! FXOR - Complement Read Of CRC Data Register
1263 * 0b0..No XOR on reading.
1264 * 0b1..Invert or complement the read value of the CRC Data register.
1265 */
1266#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
1267#define CRC_CTRL_TOTR_MASK (0x30000000U)
1268#define CRC_CTRL_TOTR_SHIFT (28U)
1269/*! TOTR - Type Of Transpose For Read
1270 * 0b00..No transposition.
1271 * 0b01..Bits in bytes are transposed; bytes are not transposed.
1272 * 0b10..Both bits in bytes and bytes are transposed.
1273 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
1274 */
1275#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
1276#define CRC_CTRL_TOT_MASK (0xC0000000U)
1277#define CRC_CTRL_TOT_SHIFT (30U)
1278/*! TOT - Type Of Transpose For Writes
1279 * 0b00..No transposition.
1280 * 0b01..Bits in bytes are transposed; bytes are not transposed.
1281 * 0b10..Both bits in bytes and bytes are transposed.
1282 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
1283 */
1284#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
1285/*! @} */
1286
1287/*! @name CTRLHU - CRC_CTRLHU register. */
1288/*! @{ */
1289#define CRC_CTRLHU_TCRC_MASK (0x1U)
1290#define CRC_CTRLHU_TCRC_SHIFT (0U)
1291/*! TCRC
1292 * 0b0..16-bit CRC protocol.
1293 * 0b1..32-bit CRC protocol.
1294 */
1295#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
1296#define CRC_CTRLHU_WAS_MASK (0x2U)
1297#define CRC_CTRLHU_WAS_SHIFT (1U)
1298/*! WAS
1299 * 0b0..Writes to CRC data register are data values.
1300 * 0b1..Writes to CRC data reguster are seed values.
1301 */
1302#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
1303#define CRC_CTRLHU_FXOR_MASK (0x4U)
1304#define CRC_CTRLHU_FXOR_SHIFT (2U)
1305/*! FXOR
1306 * 0b0..No XOR on reading.
1307 * 0b1..Invert or complement the read value of CRC data register.
1308 */
1309#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
1310#define CRC_CTRLHU_TOTR_MASK (0x30U)
1311#define CRC_CTRLHU_TOTR_SHIFT (4U)
1312/*! TOTR
1313 * 0b00..No Transposition.
1314 * 0b01..Bits in bytes are transposed, bytes are not transposed.
1315 * 0b10..Both bits in bytes and bytes are transposed.
1316 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
1317 */
1318#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
1319#define CRC_CTRLHU_TOT_MASK (0xC0U)
1320#define CRC_CTRLHU_TOT_SHIFT (6U)
1321/*! TOT
1322 * 0b00..No Transposition.
1323 * 0b01..Bits in bytes are transposed, bytes are not transposed.
1324 * 0b10..Both bits in bytes and bytes are transposed.
1325 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
1326 */
1327#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
1328/*! @} */
1329
1330
1331/*!
1332 * @}
1333 */ /* end of group CRC_Register_Masks */
1334
1335
1336/* CRC - Peripheral instance base addresses */
1337/** Peripheral CRC base address */
1338#define CRC_BASE (0x40032000u)
1339/** Peripheral CRC base pointer */
1340#define CRC0 ((CRC_Type *)CRC_BASE)
1341/** Array initializer of CRC peripheral base addresses */
1342#define CRC_BASE_ADDRS { CRC_BASE }
1343/** Array initializer of CRC peripheral base pointers */
1344#define CRC_BASE_PTRS { CRC0 }
1345
1346/*!
1347 * @}
1348 */ /* end of group CRC_Peripheral_Access_Layer */
1349
1350
1351/* ----------------------------------------------------------------------------
1352 -- DAC Peripheral Access Layer
1353 ---------------------------------------------------------------------------- */
1354
1355/*!
1356 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
1357 * @{
1358 */
1359
1360/** DAC - Register Layout Typedef */
1361typedef struct {
1362 struct { /* offset: 0x0, array step: 0x2 */
1363 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
1364 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
1365 } DAT[16];
1366 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
1367 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
1368 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
1369 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
1370} DAC_Type;
1371
1372/* ----------------------------------------------------------------------------
1373 -- DAC Register Masks
1374 ---------------------------------------------------------------------------- */
1375
1376/*!
1377 * @addtogroup DAC_Register_Masks DAC Register Masks
1378 * @{
1379 */
1380
1381/*! @name DATL - DAC Data Low Register */
1382/*! @{ */
1383#define DAC_DATL_DATA0_MASK (0xFFU)
1384#define DAC_DATL_DATA0_SHIFT (0U)
1385#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
1386/*! @} */
1387
1388/* The count of DAC_DATL */
1389#define DAC_DATL_COUNT (16U)
1390
1391/*! @name DATH - DAC Data High Register */
1392/*! @{ */
1393#define DAC_DATH_DATA1_MASK (0xFU)
1394#define DAC_DATH_DATA1_SHIFT (0U)
1395#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
1396/*! @} */
1397
1398/* The count of DAC_DATH */
1399#define DAC_DATH_COUNT (16U)
1400
1401/*! @name SR - DAC Status Register */
1402/*! @{ */
1403#define DAC_SR_DACBFRPBF_MASK (0x1U)
1404#define DAC_SR_DACBFRPBF_SHIFT (0U)
1405/*! DACBFRPBF - DAC Buffer Read Pointer Bottom Position Flag
1406 * 0b0..The DAC buffer read pointer is not equal to C2[DACBFUP].
1407 * 0b1..The DAC buffer read pointer is equal to C2[DACBFUP].
1408 */
1409#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
1410#define DAC_SR_DACBFRPTF_MASK (0x2U)
1411#define DAC_SR_DACBFRPTF_SHIFT (1U)
1412/*! DACBFRPTF - DAC Buffer Read Pointer Top Position Flag
1413 * 0b0..The DAC buffer read pointer is not zero.
1414 * 0b1..The DAC buffer read pointer is zero.
1415 */
1416#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
1417#define DAC_SR_DACBFWMF_MASK (0x4U)
1418#define DAC_SR_DACBFWMF_SHIFT (2U)
1419/*! DACBFWMF - DAC Buffer Watermark Flag
1420 * 0b0..The DAC buffer read pointer has not reached the watermark level.
1421 * 0b1..The DAC buffer read pointer has reached the watermark level.
1422 */
1423#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
1424/*! @} */
1425
1426/*! @name C0 - DAC Control Register */
1427/*! @{ */
1428#define DAC_C0_DACBBIEN_MASK (0x1U)
1429#define DAC_C0_DACBBIEN_SHIFT (0U)
1430/*! DACBBIEN - DAC Buffer Read Pointer Bottom Flag Interrupt Enable
1431 * 0b0..The DAC buffer read pointer bottom flag interrupt is disabled.
1432 * 0b1..The DAC buffer read pointer bottom flag interrupt is enabled.
1433 */
1434#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
1435#define DAC_C0_DACBTIEN_MASK (0x2U)
1436#define DAC_C0_DACBTIEN_SHIFT (1U)
1437/*! DACBTIEN - DAC Buffer Read Pointer Top Flag Interrupt Enable
1438 * 0b0..The DAC buffer read pointer top flag interrupt is disabled.
1439 * 0b1..The DAC buffer read pointer top flag interrupt is enabled.
1440 */
1441#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
1442#define DAC_C0_DACBWIEN_MASK (0x4U)
1443#define DAC_C0_DACBWIEN_SHIFT (2U)
1444/*! DACBWIEN - DAC Buffer Watermark Interrupt Enable
1445 * 0b0..The DAC buffer watermark interrupt is disabled.
1446 * 0b1..The DAC buffer watermark interrupt is enabled.
1447 */
1448#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
1449#define DAC_C0_LPEN_MASK (0x8U)
1450#define DAC_C0_LPEN_SHIFT (3U)
1451/*! LPEN - DAC Low Power Control
1452 * 0b0..High-Power mode
1453 * 0b1..Low-Power mode
1454 */
1455#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
1456#define DAC_C0_DACSWTRG_MASK (0x10U)
1457#define DAC_C0_DACSWTRG_SHIFT (4U)
1458/*! DACSWTRG - DAC Software Trigger
1459 * 0b0..The DAC soft trigger is not valid.
1460 * 0b1..The DAC soft trigger is valid.
1461 */
1462#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
1463#define DAC_C0_DACTRGSEL_MASK (0x20U)
1464#define DAC_C0_DACTRGSEL_SHIFT (5U)
1465/*! DACTRGSEL - DAC Trigger Select
1466 * 0b0..The DAC hardware trigger is selected.
1467 * 0b1..The DAC software trigger is selected.
1468 */
1469#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
1470#define DAC_C0_DACRFS_MASK (0x40U)
1471#define DAC_C0_DACRFS_SHIFT (6U)
1472/*! DACRFS - DAC Reference Select
1473 * 0b0..The DAC selects DACREF_1 as the reference voltage.
1474 * 0b1..The DAC selects DACREF_2 as the reference voltage.
1475 */
1476#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
1477#define DAC_C0_DACEN_MASK (0x80U)
1478#define DAC_C0_DACEN_SHIFT (7U)
1479/*! DACEN - DAC Enable
1480 * 0b0..The DAC system is disabled.
1481 * 0b1..The DAC system is enabled.
1482 */
1483#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
1484/*! @} */
1485
1486/*! @name C1 - DAC Control Register 1 */
1487/*! @{ */
1488#define DAC_C1_DACBFEN_MASK (0x1U)
1489#define DAC_C1_DACBFEN_SHIFT (0U)
1490/*! DACBFEN - DAC Buffer Enable
1491 * 0b0..Buffer read pointer is disabled. The converted data is always the first word of the buffer.
1492 * 0b1..Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.
1493 */
1494#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
1495#define DAC_C1_DACBFMD_MASK (0x6U)
1496#define DAC_C1_DACBFMD_SHIFT (1U)
1497/*! DACBFMD - DAC Buffer Work Mode Select
1498 * 0b00..Normal mode
1499 * 0b01..Swing mode
1500 * 0b10..One-Time Scan mode
1501 * 0b11..FIFO mode
1502 */
1503#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
1504#define DAC_C1_DACBFWM_MASK (0x18U)
1505#define DAC_C1_DACBFWM_SHIFT (3U)
1506/*! DACBFWM - DAC Buffer Watermark Select
1507 * 0b00..In normal mode, 1 word . In FIFO mode, 2 or less than 2 data remaining in FIFO will set watermark status bit.
1508 * 0b01..In normal mode, 2 words . In FIFO mode, Max/4 or less than Max/4 data remaining in FIFO will set watermark status bit.
1509 * 0b10..In normal mode, 3 words . In FIFO mode, Max/2 or less than Max/2 data remaining in FIFO will set watermark status bit.
1510 * 0b11..In normal mode, 4 words . In FIFO mode, Max-2 or less than Max-2 data remaining in FIFO will set watermark status bit.
1511 */
1512#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
1513#define DAC_C1_DMAEN_MASK (0x80U)
1514#define DAC_C1_DMAEN_SHIFT (7U)
1515/*! DMAEN - DMA Enable Select
1516 * 0b0..DMA is disabled.
1517 * 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.
1518 */
1519#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
1520/*! @} */
1521
1522/*! @name C2 - DAC Control Register 2 */
1523/*! @{ */
1524#define DAC_C2_DACBFUP_MASK (0xFU)
1525#define DAC_C2_DACBFUP_SHIFT (0U)
1526#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
1527#define DAC_C2_DACBFRP_MASK (0xF0U)
1528#define DAC_C2_DACBFRP_SHIFT (4U)
1529#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
1530/*! @} */
1531
1532
1533/*!
1534 * @}
1535 */ /* end of group DAC_Register_Masks */
1536
1537
1538/* DAC - Peripheral instance base addresses */
1539/** Peripheral DAC0 base address */
1540#define DAC0_BASE (0x4003F000u)
1541/** Peripheral DAC0 base pointer */
1542#define DAC0 ((DAC_Type *)DAC0_BASE)
1543/** Array initializer of DAC peripheral base addresses */
1544#define DAC_BASE_ADDRS { DAC0_BASE }
1545/** Array initializer of DAC peripheral base pointers */
1546#define DAC_BASE_PTRS { DAC0 }
1547/** Interrupt vectors for the DAC peripheral type */
1548#define DAC_IRQS { DAC0_IRQn }
1549
1550/*!
1551 * @}
1552 */ /* end of group DAC_Peripheral_Access_Layer */
1553
1554
1555/* ----------------------------------------------------------------------------
1556 -- DMA Peripheral Access Layer
1557 ---------------------------------------------------------------------------- */
1558
1559/*!
1560 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
1561 * @{
1562 */
1563
1564/** DMA - Register Layout Typedef */
1565typedef struct {
1566 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
1567 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
1568 uint8_t RESERVED_0[4];
1569 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
1570 uint8_t RESERVED_1[4];
1571 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
1572 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
1573 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
1574 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
1575 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
1576 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
1577 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
1578 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
1579 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
1580 uint8_t RESERVED_2[4];
1581 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
1582 uint8_t RESERVED_3[4];
1583 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
1584 uint8_t RESERVED_4[4];
1585 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
1586 uint8_t RESERVED_5[12];
1587 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
1588 uint8_t RESERVED_6[184];
1589 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
1590 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
1591 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
1592 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
1593 uint8_t RESERVED_7[3836];
1594 struct { /* offset: 0x1000, array step: 0x20 */
1595 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
1596 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
1597 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
1598 union { /* offset: 0x1008, array step: 0x20 */
1599 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
1600 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
1601 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
1602 };
1603 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
1604 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
1605 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
1606 union { /* offset: 0x1016, array step: 0x20 */
1607 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
1608 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
1609 };
1610 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
1611 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
1612 union { /* offset: 0x101E, array step: 0x20 */
1613 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
1614 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
1615 };
1616 } TCD[4];
1617} DMA_Type;
1618
1619/* ----------------------------------------------------------------------------
1620 -- DMA Register Masks
1621 ---------------------------------------------------------------------------- */
1622
1623/*!
1624 * @addtogroup DMA_Register_Masks DMA Register Masks
1625 * @{
1626 */
1627
1628/*! @name CR - Control Register */
1629/*! @{ */
1630#define DMA_CR_EDBG_MASK (0x2U)
1631#define DMA_CR_EDBG_SHIFT (1U)
1632/*! EDBG - Enable Debug
1633 * 0b0..When in debug mode, the DMA continues to operate.
1634 * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
1635 */
1636#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
1637#define DMA_CR_ERCA_MASK (0x4U)
1638#define DMA_CR_ERCA_SHIFT (2U)
1639/*! ERCA - Enable Round Robin Channel Arbitration
1640 * 0b0..Fixed priority arbitration is used for channel selection .
1641 * 0b1..Round robin arbitration is used for channel selection .
1642 */
1643#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
1644#define DMA_CR_HOE_MASK (0x10U)
1645#define DMA_CR_HOE_SHIFT (4U)
1646/*! HOE - Halt On Error
1647 * 0b0..Normal operation
1648 * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
1649 */
1650#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
1651#define DMA_CR_HALT_MASK (0x20U)
1652#define DMA_CR_HALT_SHIFT (5U)
1653/*! HALT - Halt DMA Operations
1654 * 0b0..Normal operation
1655 * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
1656 */
1657#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
1658#define DMA_CR_CLM_MASK (0x40U)
1659#define DMA_CR_CLM_SHIFT (6U)
1660/*! CLM - Continuous Link Mode
1661 * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again.
1662 * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.
1663 */
1664#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
1665#define DMA_CR_EMLM_MASK (0x80U)
1666#define DMA_CR_EMLM_SHIFT (7U)
1667/*! EMLM - Enable Minor Loop Mapping
1668 * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
1669 * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.
1670 */
1671#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
1672#define DMA_CR_ECX_MASK (0x10000U)
1673#define DMA_CR_ECX_SHIFT (16U)
1674/*! ECX - Error Cancel Transfer
1675 * 0b0..Normal operation
1676 * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.
1677 */
1678#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
1679#define DMA_CR_CX_MASK (0x20000U)
1680#define DMA_CR_CX_SHIFT (17U)
1681/*! CX - Cancel Transfer
1682 * 0b0..Normal operation
1683 * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
1684 */
1685#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
1686#define DMA_CR_ACTIVE_MASK (0x80000000U)
1687#define DMA_CR_ACTIVE_SHIFT (31U)
1688/*! ACTIVE - DMA Active Status
1689 * 0b0..eDMA is idle.
1690 * 0b1..eDMA is executing a channel.
1691 */
1692#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
1693/*! @} */
1694
1695/*! @name ES - Error Status Register */
1696/*! @{ */
1697#define DMA_ES_DBE_MASK (0x1U)
1698#define DMA_ES_DBE_SHIFT (0U)
1699/*! DBE - Destination Bus Error
1700 * 0b0..No destination bus error
1701 * 0b1..The last recorded error was a bus error on a destination write
1702 */
1703#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
1704#define DMA_ES_SBE_MASK (0x2U)
1705#define DMA_ES_SBE_SHIFT (1U)
1706/*! SBE - Source Bus Error
1707 * 0b0..No source bus error
1708 * 0b1..The last recorded error was a bus error on a source read
1709 */
1710#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
1711#define DMA_ES_SGE_MASK (0x4U)
1712#define DMA_ES_SGE_SHIFT (2U)
1713/*! SGE - Scatter/Gather Configuration Error
1714 * 0b0..No scatter/gather configuration error
1715 * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
1716 */
1717#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
1718#define DMA_ES_NCE_MASK (0x8U)
1719#define DMA_ES_NCE_SHIFT (3U)
1720/*! NCE - NBYTES/CITER Configuration Error
1721 * 0b0..No NBYTES/CITER configuration error
1722 * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
1723 */
1724#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
1725#define DMA_ES_DOE_MASK (0x10U)
1726#define DMA_ES_DOE_SHIFT (4U)
1727/*! DOE - Destination Offset Error
1728 * 0b0..No destination offset configuration error
1729 * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
1730 */
1731#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
1732#define DMA_ES_DAE_MASK (0x20U)
1733#define DMA_ES_DAE_SHIFT (5U)
1734/*! DAE - Destination Address Error
1735 * 0b0..No destination address configuration error
1736 * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
1737 */
1738#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
1739#define DMA_ES_SOE_MASK (0x40U)
1740#define DMA_ES_SOE_SHIFT (6U)
1741/*! SOE - Source Offset Error
1742 * 0b0..No source offset configuration error
1743 * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
1744 */
1745#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
1746#define DMA_ES_SAE_MASK (0x80U)
1747#define DMA_ES_SAE_SHIFT (7U)
1748/*! SAE - Source Address Error
1749 * 0b0..No source address configuration error.
1750 * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
1751 */
1752#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
1753#define DMA_ES_ERRCHN_MASK (0x300U)
1754#define DMA_ES_ERRCHN_SHIFT (8U)
1755#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
1756#define DMA_ES_CPE_MASK (0x4000U)
1757#define DMA_ES_CPE_SHIFT (14U)
1758/*! CPE - Channel Priority Error
1759 * 0b0..No channel priority error
1760 * 0b1..The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique.
1761 */
1762#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
1763#define DMA_ES_ECX_MASK (0x10000U)
1764#define DMA_ES_ECX_SHIFT (16U)
1765/*! ECX - Transfer Canceled
1766 * 0b0..No canceled transfers
1767 * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input
1768 */
1769#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
1770#define DMA_ES_VLD_MASK (0x80000000U)
1771#define DMA_ES_VLD_SHIFT (31U)
1772/*! VLD
1773 * 0b0..No ERR bits are set
1774 * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared
1775 */
1776#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
1777/*! @} */
1778
1779/*! @name ERQ - Enable Request Register */
1780/*! @{ */
1781#define DMA_ERQ_ERQ0_MASK (0x1U)
1782#define DMA_ERQ_ERQ0_SHIFT (0U)
1783/*! ERQ0 - Enable DMA Request 0
1784 * 0b0..The DMA request signal for the corresponding channel is disabled
1785 * 0b1..The DMA request signal for the corresponding channel is enabled
1786 */
1787#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
1788#define DMA_ERQ_ERQ1_MASK (0x2U)
1789#define DMA_ERQ_ERQ1_SHIFT (1U)
1790/*! ERQ1 - Enable DMA Request 1
1791 * 0b0..The DMA request signal for the corresponding channel is disabled
1792 * 0b1..The DMA request signal for the corresponding channel is enabled
1793 */
1794#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
1795#define DMA_ERQ_ERQ2_MASK (0x4U)
1796#define DMA_ERQ_ERQ2_SHIFT (2U)
1797/*! ERQ2 - Enable DMA Request 2
1798 * 0b0..The DMA request signal for the corresponding channel is disabled
1799 * 0b1..The DMA request signal for the corresponding channel is enabled
1800 */
1801#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
1802#define DMA_ERQ_ERQ3_MASK (0x8U)
1803#define DMA_ERQ_ERQ3_SHIFT (3U)
1804/*! ERQ3 - Enable DMA Request 3
1805 * 0b0..The DMA request signal for the corresponding channel is disabled
1806 * 0b1..The DMA request signal for the corresponding channel is enabled
1807 */
1808#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
1809/*! @} */
1810
1811/*! @name EEI - Enable Error Interrupt Register */
1812/*! @{ */
1813#define DMA_EEI_EEI0_MASK (0x1U)
1814#define DMA_EEI_EEI0_SHIFT (0U)
1815/*! EEI0 - Enable Error Interrupt 0
1816 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1817 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1818 */
1819#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
1820#define DMA_EEI_EEI1_MASK (0x2U)
1821#define DMA_EEI_EEI1_SHIFT (1U)
1822/*! EEI1 - Enable Error Interrupt 1
1823 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1824 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1825 */
1826#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
1827#define DMA_EEI_EEI2_MASK (0x4U)
1828#define DMA_EEI_EEI2_SHIFT (2U)
1829/*! EEI2 - Enable Error Interrupt 2
1830 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1831 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1832 */
1833#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
1834#define DMA_EEI_EEI3_MASK (0x8U)
1835#define DMA_EEI_EEI3_SHIFT (3U)
1836/*! EEI3 - Enable Error Interrupt 3
1837 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1838 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1839 */
1840#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
1841/*! @} */
1842
1843/*! @name CEEI - Clear Enable Error Interrupt Register */
1844/*! @{ */
1845#define DMA_CEEI_CEEI_MASK (0x3U)
1846#define DMA_CEEI_CEEI_SHIFT (0U)
1847#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
1848#define DMA_CEEI_CAEE_MASK (0x40U)
1849#define DMA_CEEI_CAEE_SHIFT (6U)
1850/*! CAEE - Clear All Enable Error Interrupts
1851 * 0b0..Clear only the EEI bit specified in the CEEI field
1852 * 0b1..Clear all bits in EEI
1853 */
1854#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
1855#define DMA_CEEI_NOP_MASK (0x80U)
1856#define DMA_CEEI_NOP_SHIFT (7U)
1857/*! NOP - No Op enable
1858 * 0b0..Normal operation
1859 * 0b1..No operation, ignore the other bits in this register
1860 */
1861#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
1862/*! @} */
1863
1864/*! @name SEEI - Set Enable Error Interrupt Register */
1865/*! @{ */
1866#define DMA_SEEI_SEEI_MASK (0x3U)
1867#define DMA_SEEI_SEEI_SHIFT (0U)
1868#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
1869#define DMA_SEEI_SAEE_MASK (0x40U)
1870#define DMA_SEEI_SAEE_SHIFT (6U)
1871/*! SAEE - Sets All Enable Error Interrupts
1872 * 0b0..Set only the EEI bit specified in the SEEI field.
1873 * 0b1..Sets all bits in EEI
1874 */
1875#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
1876#define DMA_SEEI_NOP_MASK (0x80U)
1877#define DMA_SEEI_NOP_SHIFT (7U)
1878/*! NOP - No Op enable
1879 * 0b0..Normal operation
1880 * 0b1..No operation, ignore the other bits in this register
1881 */
1882#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
1883/*! @} */
1884
1885/*! @name CERQ - Clear Enable Request Register */
1886/*! @{ */
1887#define DMA_CERQ_CERQ_MASK (0x3U)
1888#define DMA_CERQ_CERQ_SHIFT (0U)
1889#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
1890#define DMA_CERQ_CAER_MASK (0x40U)
1891#define DMA_CERQ_CAER_SHIFT (6U)
1892/*! CAER - Clear All Enable Requests
1893 * 0b0..Clear only the ERQ bit specified in the CERQ field
1894 * 0b1..Clear all bits in ERQ
1895 */
1896#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
1897#define DMA_CERQ_NOP_MASK (0x80U)
1898#define DMA_CERQ_NOP_SHIFT (7U)
1899/*! NOP - No Op enable
1900 * 0b0..Normal operation
1901 * 0b1..No operation, ignore the other bits in this register
1902 */
1903#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
1904/*! @} */
1905
1906/*! @name SERQ - Set Enable Request Register */
1907/*! @{ */
1908#define DMA_SERQ_SERQ_MASK (0x3U)
1909#define DMA_SERQ_SERQ_SHIFT (0U)
1910#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
1911#define DMA_SERQ_SAER_MASK (0x40U)
1912#define DMA_SERQ_SAER_SHIFT (6U)
1913/*! SAER - Set All Enable Requests
1914 * 0b0..Set only the ERQ bit specified in the SERQ field
1915 * 0b1..Set all bits in ERQ
1916 */
1917#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
1918#define DMA_SERQ_NOP_MASK (0x80U)
1919#define DMA_SERQ_NOP_SHIFT (7U)
1920/*! NOP - No Op enable
1921 * 0b0..Normal operation
1922 * 0b1..No operation, ignore the other bits in this register
1923 */
1924#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
1925/*! @} */
1926
1927/*! @name CDNE - Clear DONE Status Bit Register */
1928/*! @{ */
1929#define DMA_CDNE_CDNE_MASK (0x3U)
1930#define DMA_CDNE_CDNE_SHIFT (0U)
1931#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
1932#define DMA_CDNE_CADN_MASK (0x40U)
1933#define DMA_CDNE_CADN_SHIFT (6U)
1934/*! CADN - Clears All DONE Bits
1935 * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
1936 * 0b1..Clears all bits in TCDn_CSR[DONE]
1937 */
1938#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
1939#define DMA_CDNE_NOP_MASK (0x80U)
1940#define DMA_CDNE_NOP_SHIFT (7U)
1941/*! NOP - No Op enable
1942 * 0b0..Normal operation
1943 * 0b1..No operation, ignore the other bits in this register
1944 */
1945#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
1946/*! @} */
1947
1948/*! @name SSRT - Set START Bit Register */
1949/*! @{ */
1950#define DMA_SSRT_SSRT_MASK (0x3U)
1951#define DMA_SSRT_SSRT_SHIFT (0U)
1952#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
1953#define DMA_SSRT_SAST_MASK (0x40U)
1954#define DMA_SSRT_SAST_SHIFT (6U)
1955/*! SAST - Set All START Bits (activates all channels)
1956 * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field
1957 * 0b1..Set all bits in TCDn_CSR[START]
1958 */
1959#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
1960#define DMA_SSRT_NOP_MASK (0x80U)
1961#define DMA_SSRT_NOP_SHIFT (7U)
1962/*! NOP - No Op enable
1963 * 0b0..Normal operation
1964 * 0b1..No operation, ignore the other bits in this register
1965 */
1966#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
1967/*! @} */
1968
1969/*! @name CERR - Clear Error Register */
1970/*! @{ */
1971#define DMA_CERR_CERR_MASK (0x3U)
1972#define DMA_CERR_CERR_SHIFT (0U)
1973#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
1974#define DMA_CERR_CAEI_MASK (0x40U)
1975#define DMA_CERR_CAEI_SHIFT (6U)
1976/*! CAEI - Clear All Error Indicators
1977 * 0b0..Clear only the ERR bit specified in the CERR field
1978 * 0b1..Clear all bits in ERR
1979 */
1980#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
1981#define DMA_CERR_NOP_MASK (0x80U)
1982#define DMA_CERR_NOP_SHIFT (7U)
1983/*! NOP - No Op enable
1984 * 0b0..Normal operation
1985 * 0b1..No operation, ignore the other bits in this register
1986 */
1987#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
1988/*! @} */
1989
1990/*! @name CINT - Clear Interrupt Request Register */
1991/*! @{ */
1992#define DMA_CINT_CINT_MASK (0x3U)
1993#define DMA_CINT_CINT_SHIFT (0U)
1994#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
1995#define DMA_CINT_CAIR_MASK (0x40U)
1996#define DMA_CINT_CAIR_SHIFT (6U)
1997/*! CAIR - Clear All Interrupt Requests
1998 * 0b0..Clear only the INT bit specified in the CINT field
1999 * 0b1..Clear all bits in INT
2000 */
2001#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
2002#define DMA_CINT_NOP_MASK (0x80U)
2003#define DMA_CINT_NOP_SHIFT (7U)
2004/*! NOP - No Op enable
2005 * 0b0..Normal operation
2006 * 0b1..No operation, ignore the other bits in this register
2007 */
2008#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
2009/*! @} */
2010
2011/*! @name INT - Interrupt Request Register */
2012/*! @{ */
2013#define DMA_INT_INT0_MASK (0x1U)
2014#define DMA_INT_INT0_SHIFT (0U)
2015/*! INT0 - Interrupt Request 0
2016 * 0b0..The interrupt request for corresponding channel is cleared
2017 * 0b1..The interrupt request for corresponding channel is active
2018 */
2019#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
2020#define DMA_INT_INT1_MASK (0x2U)
2021#define DMA_INT_INT1_SHIFT (1U)
2022/*! INT1 - Interrupt Request 1
2023 * 0b0..The interrupt request for corresponding channel is cleared
2024 * 0b1..The interrupt request for corresponding channel is active
2025 */
2026#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
2027#define DMA_INT_INT2_MASK (0x4U)
2028#define DMA_INT_INT2_SHIFT (2U)
2029/*! INT2 - Interrupt Request 2
2030 * 0b0..The interrupt request for corresponding channel is cleared
2031 * 0b1..The interrupt request for corresponding channel is active
2032 */
2033#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
2034#define DMA_INT_INT3_MASK (0x8U)
2035#define DMA_INT_INT3_SHIFT (3U)
2036/*! INT3 - Interrupt Request 3
2037 * 0b0..The interrupt request for corresponding channel is cleared
2038 * 0b1..The interrupt request for corresponding channel is active
2039 */
2040#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
2041/*! @} */
2042
2043/*! @name ERR - Error Register */
2044/*! @{ */
2045#define DMA_ERR_ERR0_MASK (0x1U)
2046#define DMA_ERR_ERR0_SHIFT (0U)
2047/*! ERR0 - Error In Channel 0
2048 * 0b0..An error in the corresponding channel has not occurred
2049 * 0b1..An error in the corresponding channel has occurred
2050 */
2051#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
2052#define DMA_ERR_ERR1_MASK (0x2U)
2053#define DMA_ERR_ERR1_SHIFT (1U)
2054/*! ERR1 - Error In Channel 1
2055 * 0b0..An error in the corresponding channel has not occurred
2056 * 0b1..An error in the corresponding channel has occurred
2057 */
2058#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
2059#define DMA_ERR_ERR2_MASK (0x4U)
2060#define DMA_ERR_ERR2_SHIFT (2U)
2061/*! ERR2 - Error In Channel 2
2062 * 0b0..An error in the corresponding channel has not occurred
2063 * 0b1..An error in the corresponding channel has occurred
2064 */
2065#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
2066#define DMA_ERR_ERR3_MASK (0x8U)
2067#define DMA_ERR_ERR3_SHIFT (3U)
2068/*! ERR3 - Error In Channel 3
2069 * 0b0..An error in the corresponding channel has not occurred
2070 * 0b1..An error in the corresponding channel has occurred
2071 */
2072#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
2073/*! @} */
2074
2075/*! @name HRS - Hardware Request Status Register */
2076/*! @{ */
2077#define DMA_HRS_HRS0_MASK (0x1U)
2078#define DMA_HRS_HRS0_SHIFT (0U)
2079/*! HRS0 - Hardware Request Status Channel 0
2080 * 0b0..A hardware service request for channel 0 is not present
2081 * 0b1..A hardware service request for channel 0 is present
2082 */
2083#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
2084#define DMA_HRS_HRS1_MASK (0x2U)
2085#define DMA_HRS_HRS1_SHIFT (1U)
2086/*! HRS1 - Hardware Request Status Channel 1
2087 * 0b0..A hardware service request for channel 1 is not present
2088 * 0b1..A hardware service request for channel 1 is present
2089 */
2090#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
2091#define DMA_HRS_HRS2_MASK (0x4U)
2092#define DMA_HRS_HRS2_SHIFT (2U)
2093/*! HRS2 - Hardware Request Status Channel 2
2094 * 0b0..A hardware service request for channel 2 is not present
2095 * 0b1..A hardware service request for channel 2 is present
2096 */
2097#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
2098#define DMA_HRS_HRS3_MASK (0x8U)
2099#define DMA_HRS_HRS3_SHIFT (3U)
2100/*! HRS3 - Hardware Request Status Channel 3
2101 * 0b0..A hardware service request for channel 3 is not present
2102 * 0b1..A hardware service request for channel 3 is present
2103 */
2104#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
2105/*! @} */
2106
2107/*! @name EARS - Enable Asynchronous Request in Stop Register */
2108/*! @{ */
2109#define DMA_EARS_EDREQ_0_MASK (0x1U)
2110#define DMA_EARS_EDREQ_0_SHIFT (0U)
2111/*! EDREQ_0 - Enable asynchronous DMA request in stop for channel 0.
2112 * 0b0..Disable asynchronous DMA request for channel 0.
2113 * 0b1..Enable asynchronous DMA request for channel 0.
2114 */
2115#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
2116#define DMA_EARS_EDREQ_1_MASK (0x2U)
2117#define DMA_EARS_EDREQ_1_SHIFT (1U)
2118/*! EDREQ_1 - Enable asynchronous DMA request in stop for channel 1.
2119 * 0b0..Disable asynchronous DMA request for channel 1
2120 * 0b1..Enable asynchronous DMA request for channel 1.
2121 */
2122#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
2123#define DMA_EARS_EDREQ_2_MASK (0x4U)
2124#define DMA_EARS_EDREQ_2_SHIFT (2U)
2125/*! EDREQ_2 - Enable asynchronous DMA request in stop for channel 2.
2126 * 0b0..Disable asynchronous DMA request for channel 2.
2127 * 0b1..Enable asynchronous DMA request for channel 2.
2128 */
2129#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
2130#define DMA_EARS_EDREQ_3_MASK (0x8U)
2131#define DMA_EARS_EDREQ_3_SHIFT (3U)
2132/*! EDREQ_3 - Enable asynchronous DMA request in stop for channel 3.
2133 * 0b0..Disable asynchronous DMA request for channel 3.
2134 * 0b1..Enable asynchronous DMA request for channel 3.
2135 */
2136#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
2137/*! @} */
2138
2139/*! @name DCHPRI3 - Channel n Priority Register */
2140/*! @{ */
2141#define DMA_DCHPRI3_CHPRI_MASK (0x3U)
2142#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
2143#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
2144#define DMA_DCHPRI3_DPA_MASK (0x40U)
2145#define DMA_DCHPRI3_DPA_SHIFT (6U)
2146/*! DPA - Disable Preempt Ability
2147 * 0b0..Channel n can suspend a lower priority channel
2148 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2149 */
2150#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
2151#define DMA_DCHPRI3_ECP_MASK (0x80U)
2152#define DMA_DCHPRI3_ECP_SHIFT (7U)
2153/*! ECP - Enable Channel Preemption
2154 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2155 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2156 */
2157#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
2158/*! @} */
2159
2160/*! @name DCHPRI2 - Channel n Priority Register */
2161/*! @{ */
2162#define DMA_DCHPRI2_CHPRI_MASK (0x3U)
2163#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
2164#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
2165#define DMA_DCHPRI2_DPA_MASK (0x40U)
2166#define DMA_DCHPRI2_DPA_SHIFT (6U)
2167/*! DPA - Disable Preempt Ability
2168 * 0b0..Channel n can suspend a lower priority channel
2169 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2170 */
2171#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
2172#define DMA_DCHPRI2_ECP_MASK (0x80U)
2173#define DMA_DCHPRI2_ECP_SHIFT (7U)
2174/*! ECP - Enable Channel Preemption
2175 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2176 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2177 */
2178#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
2179/*! @} */
2180
2181/*! @name DCHPRI1 - Channel n Priority Register */
2182/*! @{ */
2183#define DMA_DCHPRI1_CHPRI_MASK (0x3U)
2184#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
2185#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
2186#define DMA_DCHPRI1_DPA_MASK (0x40U)
2187#define DMA_DCHPRI1_DPA_SHIFT (6U)
2188/*! DPA - Disable Preempt Ability
2189 * 0b0..Channel n can suspend a lower priority channel
2190 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2191 */
2192#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
2193#define DMA_DCHPRI1_ECP_MASK (0x80U)
2194#define DMA_DCHPRI1_ECP_SHIFT (7U)
2195/*! ECP - Enable Channel Preemption
2196 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2197 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2198 */
2199#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
2200/*! @} */
2201
2202/*! @name DCHPRI0 - Channel n Priority Register */
2203/*! @{ */
2204#define DMA_DCHPRI0_CHPRI_MASK (0x3U)
2205#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
2206#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
2207#define DMA_DCHPRI0_DPA_MASK (0x40U)
2208#define DMA_DCHPRI0_DPA_SHIFT (6U)
2209/*! DPA - Disable Preempt Ability
2210 * 0b0..Channel n can suspend a lower priority channel
2211 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2212 */
2213#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
2214#define DMA_DCHPRI0_ECP_MASK (0x80U)
2215#define DMA_DCHPRI0_ECP_SHIFT (7U)
2216/*! ECP - Enable Channel Preemption
2217 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2218 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2219 */
2220#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
2221/*! @} */
2222
2223/*! @name SADDR - TCD Source Address */
2224/*! @{ */
2225#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
2226#define DMA_SADDR_SADDR_SHIFT (0U)
2227#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
2228/*! @} */
2229
2230/* The count of DMA_SADDR */
2231#define DMA_SADDR_COUNT (4U)
2232
2233/*! @name SOFF - TCD Signed Source Address Offset */
2234/*! @{ */
2235#define DMA_SOFF_SOFF_MASK (0xFFFFU)
2236#define DMA_SOFF_SOFF_SHIFT (0U)
2237#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
2238/*! @} */
2239
2240/* The count of DMA_SOFF */
2241#define DMA_SOFF_COUNT (4U)
2242
2243/*! @name ATTR - TCD Transfer Attributes */
2244/*! @{ */
2245#define DMA_ATTR_DSIZE_MASK (0x7U)
2246#define DMA_ATTR_DSIZE_SHIFT (0U)
2247#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
2248#define DMA_ATTR_DMOD_MASK (0xF8U)
2249#define DMA_ATTR_DMOD_SHIFT (3U)
2250#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
2251#define DMA_ATTR_SSIZE_MASK (0x700U)
2252#define DMA_ATTR_SSIZE_SHIFT (8U)
2253/*! SSIZE - Source data transfer size
2254 * 0b000..8-bit
2255 * 0b001..16-bit
2256 * 0b010..32-bit
2257 * 0b011..Reserved
2258 * 0b100..16-byte
2259 * 0b101..32-byte
2260 * 0b110..Reserved
2261 * 0b111..Reserved
2262 */
2263#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
2264#define DMA_ATTR_SMOD_MASK (0xF800U)
2265#define DMA_ATTR_SMOD_SHIFT (11U)
2266/*! SMOD - Source Address Modulo.
2267 * 0b00000..Source address modulo feature is disabled
2268 */
2269#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
2270/*! @} */
2271
2272/* The count of DMA_ATTR */
2273#define DMA_ATTR_COUNT (4U)
2274
2275/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */
2276/*! @{ */
2277#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
2278#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
2279#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
2280/*! @} */
2281
2282/* The count of DMA_NBYTES_MLNO */
2283#define DMA_NBYTES_MLNO_COUNT (4U)
2284
2285/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
2286/*! @{ */
2287#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
2288#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
2289#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
2290#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
2291#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
2292/*! DMLOE - Destination Minor Loop Offset enable
2293 * 0b0..The minor loop offset is not applied to the DADDR
2294 * 0b1..The minor loop offset is applied to the DADDR
2295 */
2296#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
2297#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
2298#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
2299/*! SMLOE - Source Minor Loop Offset Enable
2300 * 0b0..The minor loop offset is not applied to the SADDR
2301 * 0b1..The minor loop offset is applied to the SADDR
2302 */
2303#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
2304/*! @} */
2305
2306/* The count of DMA_NBYTES_MLOFFNO */
2307#define DMA_NBYTES_MLOFFNO_COUNT (4U)
2308
2309/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
2310/*! @{ */
2311#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
2312#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
2313#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
2314#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
2315#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
2316#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
2317#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
2318#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
2319/*! DMLOE - Destination Minor Loop Offset enable
2320 * 0b0..The minor loop offset is not applied to the DADDR
2321 * 0b1..The minor loop offset is applied to the DADDR
2322 */
2323#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
2324#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
2325#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
2326/*! SMLOE - Source Minor Loop Offset Enable
2327 * 0b0..The minor loop offset is not applied to the SADDR
2328 * 0b1..The minor loop offset is applied to the SADDR
2329 */
2330#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
2331/*! @} */
2332
2333/* The count of DMA_NBYTES_MLOFFYES */
2334#define DMA_NBYTES_MLOFFYES_COUNT (4U)
2335
2336/*! @name SLAST - TCD Last Source Address Adjustment */
2337/*! @{ */
2338#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
2339#define DMA_SLAST_SLAST_SHIFT (0U)
2340#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
2341/*! @} */
2342
2343/* The count of DMA_SLAST */
2344#define DMA_SLAST_COUNT (4U)
2345
2346/*! @name DADDR - TCD Destination Address */
2347/*! @{ */
2348#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
2349#define DMA_DADDR_DADDR_SHIFT (0U)
2350#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
2351/*! @} */
2352
2353/* The count of DMA_DADDR */
2354#define DMA_DADDR_COUNT (4U)
2355
2356/*! @name DOFF - TCD Signed Destination Address Offset */
2357/*! @{ */
2358#define DMA_DOFF_DOFF_MASK (0xFFFFU)
2359#define DMA_DOFF_DOFF_SHIFT (0U)
2360#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
2361/*! @} */
2362
2363/* The count of DMA_DOFF */
2364#define DMA_DOFF_COUNT (4U)
2365
2366/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
2367/*! @{ */
2368#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
2369#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
2370#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
2371#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
2372#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
2373/*! ELINK - Enable channel-to-channel linking on minor-loop complete
2374 * 0b0..The channel-to-channel linking is disabled
2375 * 0b1..The channel-to-channel linking is enabled
2376 */
2377#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
2378/*! @} */
2379
2380/* The count of DMA_CITER_ELINKNO */
2381#define DMA_CITER_ELINKNO_COUNT (4U)
2382
2383/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
2384/*! @{ */
2385#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
2386#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
2387#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
2388#define DMA_CITER_ELINKYES_LINKCH_MASK (0x600U)
2389#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
2390#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
2391#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
2392#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
2393/*! ELINK - Enable channel-to-channel linking on minor-loop complete
2394 * 0b0..The channel-to-channel linking is disabled
2395 * 0b1..The channel-to-channel linking is enabled
2396 */
2397#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
2398/*! @} */
2399
2400/* The count of DMA_CITER_ELINKYES */
2401#define DMA_CITER_ELINKYES_COUNT (4U)
2402
2403/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
2404/*! @{ */
2405#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
2406#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
2407#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
2408/*! @} */
2409
2410/* The count of DMA_DLAST_SGA */
2411#define DMA_DLAST_SGA_COUNT (4U)
2412
2413/*! @name CSR - TCD Control and Status */
2414/*! @{ */
2415#define DMA_CSR_START_MASK (0x1U)
2416#define DMA_CSR_START_SHIFT (0U)
2417/*! START - Channel Start
2418 * 0b0..The channel is not explicitly started
2419 * 0b1..The channel is explicitly started via a software initiated service request
2420 */
2421#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
2422#define DMA_CSR_INTMAJOR_MASK (0x2U)
2423#define DMA_CSR_INTMAJOR_SHIFT (1U)
2424/*! INTMAJOR - Enable an interrupt when major iteration count completes
2425 * 0b0..The end-of-major loop interrupt is disabled
2426 * 0b1..The end-of-major loop interrupt is enabled
2427 */
2428#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
2429#define DMA_CSR_INTHALF_MASK (0x4U)
2430#define DMA_CSR_INTHALF_SHIFT (2U)
2431/*! INTHALF - Enable an interrupt when major counter is half complete.
2432 * 0b0..The half-point interrupt is disabled
2433 * 0b1..The half-point interrupt is enabled
2434 */
2435#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
2436#define DMA_CSR_DREQ_MASK (0x8U)
2437#define DMA_CSR_DREQ_SHIFT (3U)
2438/*! DREQ - Disable Request
2439 * 0b0..The channel's ERQ bit is not affected
2440 * 0b1..The channel's ERQ bit is cleared when the major loop is complete
2441 */
2442#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
2443#define DMA_CSR_ESG_MASK (0x10U)
2444#define DMA_CSR_ESG_SHIFT (4U)
2445/*! ESG - Enable Scatter/Gather Processing
2446 * 0b0..The current channel's TCD is normal format.
2447 * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
2448 */
2449#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
2450#define DMA_CSR_MAJORELINK_MASK (0x20U)
2451#define DMA_CSR_MAJORELINK_SHIFT (5U)
2452/*! MAJORELINK - Enable channel-to-channel linking on major loop complete
2453 * 0b0..The channel-to-channel linking is disabled
2454 * 0b1..The channel-to-channel linking is enabled
2455 */
2456#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
2457#define DMA_CSR_ACTIVE_MASK (0x40U)
2458#define DMA_CSR_ACTIVE_SHIFT (6U)
2459#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
2460#define DMA_CSR_DONE_MASK (0x80U)
2461#define DMA_CSR_DONE_SHIFT (7U)
2462#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
2463#define DMA_CSR_MAJORLINKCH_MASK (0x300U)
2464#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
2465#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
2466#define DMA_CSR_BWC_MASK (0xC000U)
2467#define DMA_CSR_BWC_SHIFT (14U)
2468/*! BWC - Bandwidth Control
2469 * 0b00..No eDMA engine stalls
2470 * 0b01..Reserved
2471 * 0b10..eDMA engine stalls for 4 cycles after each r/w
2472 * 0b11..eDMA engine stalls for 8 cycles after each r/w
2473 */
2474#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
2475/*! @} */
2476
2477/* The count of DMA_CSR */
2478#define DMA_CSR_COUNT (4U)
2479
2480/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
2481/*! @{ */
2482#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
2483#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
2484#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
2485#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
2486#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
2487/*! ELINK - Enables channel-to-channel linking on minor loop complete
2488 * 0b0..The channel-to-channel linking is disabled
2489 * 0b1..The channel-to-channel linking is enabled
2490 */
2491#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
2492/*! @} */
2493
2494/* The count of DMA_BITER_ELINKNO */
2495#define DMA_BITER_ELINKNO_COUNT (4U)
2496
2497/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
2498/*! @{ */
2499#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
2500#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
2501#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
2502#define DMA_BITER_ELINKYES_LINKCH_MASK (0x600U)
2503#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
2504#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
2505#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
2506#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
2507/*! ELINK - Enables channel-to-channel linking on minor loop complete
2508 * 0b0..The channel-to-channel linking is disabled
2509 * 0b1..The channel-to-channel linking is enabled
2510 */
2511#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
2512/*! @} */
2513
2514/* The count of DMA_BITER_ELINKYES */
2515#define DMA_BITER_ELINKYES_COUNT (4U)
2516
2517
2518/*!
2519 * @}
2520 */ /* end of group DMA_Register_Masks */
2521
2522
2523/* DMA - Peripheral instance base addresses */
2524/** Peripheral DMA base address */
2525#define DMA_BASE (0x40008000u)
2526/** Peripheral DMA base pointer */
2527#define DMA0 ((DMA_Type *)DMA_BASE)
2528/** Array initializer of DMA peripheral base addresses */
2529#define DMA_BASE_ADDRS { DMA_BASE }
2530/** Array initializer of DMA peripheral base pointers */
2531#define DMA_BASE_PTRS { DMA0 }
2532/** Interrupt vectors for the DMA peripheral type */
2533#define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
2534#define DMA_ERROR_IRQS { DMA_Error_IRQn }
2535
2536/*!
2537 * @}
2538 */ /* end of group DMA_Peripheral_Access_Layer */
2539
2540
2541/* ----------------------------------------------------------------------------
2542 -- DMAMUX Peripheral Access Layer
2543 ---------------------------------------------------------------------------- */
2544
2545/*!
2546 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
2547 * @{
2548 */
2549
2550/** DMAMUX - Register Layout Typedef */
2551typedef struct {
2552 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
2553} DMAMUX_Type;
2554
2555/* ----------------------------------------------------------------------------
2556 -- DMAMUX Register Masks
2557 ---------------------------------------------------------------------------- */
2558
2559/*!
2560 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
2561 * @{
2562 */
2563
2564/*! @name CHCFG - Channel Configuration register */
2565/*! @{ */
2566#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
2567#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
2568/*! SOURCE - DMA Channel Source (Slot)
2569 * 0b000000..Disable_Signal
2570 * 0b000010..UART0_Rx_Signal
2571 * 0b000011..UART0_Tx_Signal
2572 * 0b000100..UART1_Rx_Signal
2573 * 0b000101..UART1_Tx_Signal
2574 * 0b000110..UART2_Rx_Signal
2575 * 0b000111..UART2_Tx_Signal
2576 * 0b001100..I2S0_Rx_Signal
2577 * 0b001101..I2S0_Tx_Signal
2578 * 0b001110..SPI0_Rx_Signal
2579 * 0b001111..SPI0_Tx_Signal
2580 * 0b010000..SPI1_Signal
2581 * 0b010010..I2C0_Signal
2582 * 0b010011..I2C1_Signal
2583 * 0b010100..FTM0_Channel0_Signal
2584 * 0b010101..FTM0_Channel1_Signal
2585 * 0b010110..FTM0_Channel2_Signal
2586 * 0b010111..FTM0_Channel3_Signal
2587 * 0b011000..FTM0_Channel4_Signal
2588 * 0b011001..FTM0_Channel5_Signal
2589 * 0b011010..FTM0_Channel6_Signal
2590 * 0b011011..FTM0_Channel7_Signal
2591 * 0b011100..FTM1_Channel0_Signal
2592 * 0b011101..FTM1_Channel1_Signal
2593 * 0b011110..FTM2_Channel0_Signal
2594 * 0b011111..FTM2_Channel1_Signal
2595 * 0b101000..ADC0_Signal
2596 * 0b101001..ADC1_Signal
2597 * 0b101010..CMP0_Signal
2598 * 0b101011..CMP1_Signal
2599 * 0b101101..DAC0_Signal
2600 * 0b110000..PDB_Signal
2601 * 0b110001..PortA_Signal
2602 * 0b110010..PortB_Signal
2603 * 0b110011..PortC_Signal
2604 * 0b110100..PortD_Signal
2605 * 0b110101..PortE_Signal
2606 * 0b111010..LPUART0_Rx_Signal
2607 * 0b111011..LPUART0_Tx_Signal
2608 * 0b111100..AlwaysOn60_Signal
2609 * 0b111101..AlwaysOn61_Signal
2610 * 0b111110..AlwaysOn62_Signal
2611 * 0b111111..AlwaysOn63_Signal
2612 */
2613#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
2614#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
2615#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
2616/*! TRIG - DMA Channel Trigger Enable
2617 * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
2618 * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
2619 */
2620#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
2621#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
2622#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
2623/*! ENBL - DMA Channel Enable
2624 * 0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
2625 * 0b1..DMA channel is enabled
2626 */
2627#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
2628/*! @} */
2629
2630/* The count of DMAMUX_CHCFG */
2631#define DMAMUX_CHCFG_COUNT (4U)
2632
2633
2634/*!
2635 * @}
2636 */ /* end of group DMAMUX_Register_Masks */
2637
2638
2639/* DMAMUX - Peripheral instance base addresses */
2640/** Peripheral DMAMUX base address */
2641#define DMAMUX_BASE (0x40021000u)
2642/** Peripheral DMAMUX base pointer */
2643#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
2644/** Array initializer of DMAMUX peripheral base addresses */
2645#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
2646/** Array initializer of DMAMUX peripheral base pointers */
2647#define DMAMUX_BASE_PTRS { DMAMUX }
2648
2649/*!
2650 * @}
2651 */ /* end of group DMAMUX_Peripheral_Access_Layer */
2652
2653
2654/* ----------------------------------------------------------------------------
2655 -- EWM Peripheral Access Layer
2656 ---------------------------------------------------------------------------- */
2657
2658/*!
2659 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
2660 * @{
2661 */
2662
2663/** EWM - Register Layout Typedef */
2664typedef struct {
2665 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
2666 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
2667 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
2668 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
2669 uint8_t RESERVED_0[1];
2670 __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
2671} EWM_Type;
2672
2673/* ----------------------------------------------------------------------------
2674 -- EWM Register Masks
2675 ---------------------------------------------------------------------------- */
2676
2677/*!
2678 * @addtogroup EWM_Register_Masks EWM Register Masks
2679 * @{
2680 */
2681
2682/*! @name CTRL - Control Register */
2683/*! @{ */
2684#define EWM_CTRL_EWMEN_MASK (0x1U)
2685#define EWM_CTRL_EWMEN_SHIFT (0U)
2686#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
2687#define EWM_CTRL_ASSIN_MASK (0x2U)
2688#define EWM_CTRL_ASSIN_SHIFT (1U)
2689#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
2690#define EWM_CTRL_INEN_MASK (0x4U)
2691#define EWM_CTRL_INEN_SHIFT (2U)
2692#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
2693#define EWM_CTRL_INTEN_MASK (0x8U)
2694#define EWM_CTRL_INTEN_SHIFT (3U)
2695#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
2696/*! @} */
2697
2698/*! @name SERV - Service Register */
2699/*! @{ */
2700#define EWM_SERV_SERVICE_MASK (0xFFU)
2701#define EWM_SERV_SERVICE_SHIFT (0U)
2702#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
2703/*! @} */
2704
2705/*! @name CMPL - Compare Low Register */
2706/*! @{ */
2707#define EWM_CMPL_COMPAREL_MASK (0xFFU)
2708#define EWM_CMPL_COMPAREL_SHIFT (0U)
2709#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
2710/*! @} */
2711
2712/*! @name CMPH - Compare High Register */
2713/*! @{ */
2714#define EWM_CMPH_COMPAREH_MASK (0xFFU)
2715#define EWM_CMPH_COMPAREH_SHIFT (0U)
2716#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
2717/*! @} */
2718
2719/*! @name CLKPRESCALER - Clock Prescaler Register */
2720/*! @{ */
2721#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
2722#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
2723#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
2724/*! @} */
2725
2726
2727/*!
2728 * @}
2729 */ /* end of group EWM_Register_Masks */
2730
2731
2732/* EWM - Peripheral instance base addresses */
2733/** Peripheral EWM base address */
2734#define EWM_BASE (0x40061000u)
2735/** Peripheral EWM base pointer */
2736#define EWM ((EWM_Type *)EWM_BASE)
2737/** Array initializer of EWM peripheral base addresses */
2738#define EWM_BASE_ADDRS { EWM_BASE }
2739/** Array initializer of EWM peripheral base pointers */
2740#define EWM_BASE_PTRS { EWM }
2741/** Interrupt vectors for the EWM peripheral type */
2742#define EWM_IRQS { WDOG_EWM_IRQn }
2743
2744/*!
2745 * @}
2746 */ /* end of group EWM_Peripheral_Access_Layer */
2747
2748
2749/* ----------------------------------------------------------------------------
2750 -- FMC Peripheral Access Layer
2751 ---------------------------------------------------------------------------- */
2752
2753/*!
2754 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
2755 * @{
2756 */
2757
2758/** FMC - Register Layout Typedef */
2759typedef struct {
2760 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
2761 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
2762 __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
2763 uint8_t RESERVED_0[244];
2764 __IO uint32_t TAGVDW0S[8]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
2765 __IO uint32_t TAGVDW1S[8]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
2766 __IO uint32_t TAGVDW2S[8]; /**< Cache Tag Storage, array offset: 0x140, array step: 0x4 */
2767 __IO uint32_t TAGVDW3S[8]; /**< Cache Tag Storage, array offset: 0x160, array step: 0x4 */
2768 uint8_t RESERVED_1[128];
2769 struct { /* offset: 0x200, array step: index*0x40, index2*0x8 */
2770 __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */
2771 __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */
2772 } SET[4][8];
2773} FMC_Type;
2774
2775/* ----------------------------------------------------------------------------
2776 -- FMC Register Masks
2777 ---------------------------------------------------------------------------- */
2778
2779/*!
2780 * @addtogroup FMC_Register_Masks FMC Register Masks
2781 * @{
2782 */
2783
2784/*! @name PFAPR - Flash Access Protection Register */
2785/*! @{ */
2786#define FMC_PFAPR_M0AP_MASK (0x3U)
2787#define FMC_PFAPR_M0AP_SHIFT (0U)
2788/*! M0AP - Master 0 Access Protection
2789 * 0b00..No access may be performed by this master
2790 * 0b01..Only read accesses may be performed by this master
2791 * 0b10..Only write accesses may be performed by this master
2792 * 0b11..Both read and write accesses may be performed by this master
2793 */
2794#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
2795#define FMC_PFAPR_M1AP_MASK (0xCU)
2796#define FMC_PFAPR_M1AP_SHIFT (2U)
2797/*! M1AP - Master 1 Access Protection
2798 * 0b00..No access may be performed by this master
2799 * 0b01..Only read accesses may be performed by this master
2800 * 0b10..Only write accesses may be performed by this master
2801 * 0b11..Both read and write accesses may be performed by this master
2802 */
2803#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
2804#define FMC_PFAPR_M2AP_MASK (0x30U)
2805#define FMC_PFAPR_M2AP_SHIFT (4U)
2806/*! M2AP - Master 2 Access Protection
2807 * 0b00..No access may be performed by this master
2808 * 0b01..Only read accesses may be performed by this master
2809 * 0b10..Only write accesses may be performed by this master
2810 * 0b11..Both read and write accesses may be performed by this master
2811 */
2812#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
2813#define FMC_PFAPR_M3AP_MASK (0xC0U)
2814#define FMC_PFAPR_M3AP_SHIFT (6U)
2815/*! M3AP - Master 3 Access Protection
2816 * 0b00..No access may be performed by this master
2817 * 0b01..Only read accesses may be performed by this master
2818 * 0b10..Only write accesses may be performed by this master
2819 * 0b11..Both read and write accesses may be performed by this master
2820 */
2821#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
2822#define FMC_PFAPR_M4AP_MASK (0x300U)
2823#define FMC_PFAPR_M4AP_SHIFT (8U)
2824/*! M4AP - Master 4 Access Protection
2825 * 0b00..No access may be performed by this master
2826 * 0b01..Only read accesses may be performed by this master
2827 * 0b10..Only write accesses may be performed by this master
2828 * 0b11..Both read and write accesses may be performed by this master
2829 */
2830#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
2831#define FMC_PFAPR_M5AP_MASK (0xC00U)
2832#define FMC_PFAPR_M5AP_SHIFT (10U)
2833/*! M5AP - Master 5 Access Protection
2834 * 0b00..No access may be performed by this master
2835 * 0b01..Only read accesses may be performed by this master
2836 * 0b10..Only write accesses may be performed by this master
2837 * 0b11..Both read and write accesses may be performed by this master
2838 */
2839#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
2840#define FMC_PFAPR_M6AP_MASK (0x3000U)
2841#define FMC_PFAPR_M6AP_SHIFT (12U)
2842/*! M6AP - Master 6 Access Protection
2843 * 0b00..No access may be performed by this master
2844 * 0b01..Only read accesses may be performed by this master
2845 * 0b10..Only write accesses may be performed by this master
2846 * 0b11..Both read and write accesses may be performed by this master
2847 */
2848#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
2849#define FMC_PFAPR_M7AP_MASK (0xC000U)
2850#define FMC_PFAPR_M7AP_SHIFT (14U)
2851/*! M7AP - Master 7 Access Protection
2852 * 0b00..No access may be performed by this master.
2853 * 0b01..Only read accesses may be performed by this master.
2854 * 0b10..Only write accesses may be performed by this master.
2855 * 0b11..Both read and write accesses may be performed by this master.
2856 */
2857#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
2858#define FMC_PFAPR_M0PFD_MASK (0x10000U)
2859#define FMC_PFAPR_M0PFD_SHIFT (16U)
2860/*! M0PFD - Master 0 Prefetch Disable
2861 * 0b0..Prefetching for this master is enabled.
2862 * 0b1..Prefetching for this master is disabled.
2863 */
2864#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
2865#define FMC_PFAPR_M1PFD_MASK (0x20000U)
2866#define FMC_PFAPR_M1PFD_SHIFT (17U)
2867/*! M1PFD - Master 1 Prefetch Disable
2868 * 0b0..Prefetching for this master is enabled.
2869 * 0b1..Prefetching for this master is disabled.
2870 */
2871#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
2872#define FMC_PFAPR_M2PFD_MASK (0x40000U)
2873#define FMC_PFAPR_M2PFD_SHIFT (18U)
2874/*! M2PFD - Master 2 Prefetch Disable
2875 * 0b0..Prefetching for this master is enabled.
2876 * 0b1..Prefetching for this master is disabled.
2877 */
2878#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
2879#define FMC_PFAPR_M3PFD_MASK (0x80000U)
2880#define FMC_PFAPR_M3PFD_SHIFT (19U)
2881/*! M3PFD - Master 3 Prefetch Disable
2882 * 0b0..Prefetching for this master is enabled.
2883 * 0b1..Prefetching for this master is disabled.
2884 */
2885#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
2886#define FMC_PFAPR_M4PFD_MASK (0x100000U)
2887#define FMC_PFAPR_M4PFD_SHIFT (20U)
2888/*! M4PFD - Master 4 Prefetch Disable
2889 * 0b0..Prefetching for this master is enabled.
2890 * 0b1..Prefetching for this master is disabled.
2891 */
2892#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
2893#define FMC_PFAPR_M5PFD_MASK (0x200000U)
2894#define FMC_PFAPR_M5PFD_SHIFT (21U)
2895/*! M5PFD - Master 5 Prefetch Disable
2896 * 0b0..Prefetching for this master is enabled.
2897 * 0b1..Prefetching for this master is disabled.
2898 */
2899#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
2900#define FMC_PFAPR_M6PFD_MASK (0x400000U)
2901#define FMC_PFAPR_M6PFD_SHIFT (22U)
2902/*! M6PFD - Master 6 Prefetch Disable
2903 * 0b0..Prefetching for this master is enabled.
2904 * 0b1..Prefetching for this master is disabled.
2905 */
2906#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
2907#define FMC_PFAPR_M7PFD_MASK (0x800000U)
2908#define FMC_PFAPR_M7PFD_SHIFT (23U)
2909/*! M7PFD - Master 7 Prefetch Disable
2910 * 0b0..Prefetching for this master is enabled.
2911 * 0b1..Prefetching for this master is disabled.
2912 */
2913#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
2914/*! @} */
2915
2916/*! @name PFB0CR - Flash Bank 0 Control Register */
2917/*! @{ */
2918#define FMC_PFB0CR_B0SEBE_MASK (0x1U)
2919#define FMC_PFB0CR_B0SEBE_SHIFT (0U)
2920/*! B0SEBE - Bank 0 Single Entry Buffer Enable
2921 * 0b0..Single entry buffer is disabled.
2922 * 0b1..Single entry buffer is enabled.
2923 */
2924#define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
2925#define FMC_PFB0CR_B0IPE_MASK (0x2U)
2926#define FMC_PFB0CR_B0IPE_SHIFT (1U)
2927/*! B0IPE - Bank 0 Instruction Prefetch Enable
2928 * 0b0..Do not prefetch in response to instruction fetches.
2929 * 0b1..Enable prefetches in response to instruction fetches.
2930 */
2931#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
2932#define FMC_PFB0CR_B0DPE_MASK (0x4U)
2933#define FMC_PFB0CR_B0DPE_SHIFT (2U)
2934/*! B0DPE - Bank 0 Data Prefetch Enable
2935 * 0b0..Do not prefetch in response to data references.
2936 * 0b1..Enable prefetches in response to data references.
2937 */
2938#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
2939#define FMC_PFB0CR_B0ICE_MASK (0x8U)
2940#define FMC_PFB0CR_B0ICE_SHIFT (3U)
2941/*! B0ICE - Bank 0 Instruction Cache Enable
2942 * 0b0..Do not cache instruction fetches.
2943 * 0b1..Cache instruction fetches.
2944 */
2945#define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
2946#define FMC_PFB0CR_B0DCE_MASK (0x10U)
2947#define FMC_PFB0CR_B0DCE_SHIFT (4U)
2948/*! B0DCE - Bank 0 Data Cache Enable
2949 * 0b0..Do not cache data references.
2950 * 0b1..Cache data references.
2951 */
2952#define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
2953#define FMC_PFB0CR_CRC_MASK (0xE0U)
2954#define FMC_PFB0CR_CRC_SHIFT (5U)
2955/*! CRC - Cache Replacement Control
2956 * 0b000..LRU replacement algorithm per set across all four ways
2957 * 0b001..Reserved
2958 * 0b010..Independent LRU with ways [0-1] for ifetches, [2-3] for data
2959 * 0b011..Independent LRU with ways [0-2] for ifetches, [3] for data
2960 * 0b1xx..Reserved
2961 */
2962#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
2963#define FMC_PFB0CR_B0MW_MASK (0x60000U)
2964#define FMC_PFB0CR_B0MW_SHIFT (17U)
2965/*! B0MW - Bank 0 Memory Width
2966 * 0b00..32 bits
2967 * 0b01..64 bits
2968 * 0b10..Reserved
2969 * 0b11..Reserved
2970 */
2971#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
2972#define FMC_PFB0CR_S_B_INV_MASK (0x80000U)
2973#define FMC_PFB0CR_S_B_INV_SHIFT (19U)
2974/*! S_B_INV - Invalidate Prefetch Speculation Buffer
2975 * 0b0..Speculation buffer and single entry buffer are not affected.
2976 * 0b1..Invalidate (clear) speculation buffer and single entry buffer.
2977 */
2978#define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
2979#define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U)
2980#define FMC_PFB0CR_CINV_WAY_SHIFT (20U)
2981/*! CINV_WAY - Cache Invalidate Way x
2982 * 0b0000..No cache way invalidation for the corresponding cache
2983 * 0b0001..Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected
2984 */
2985#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
2986#define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U)
2987#define FMC_PFB0CR_CLCK_WAY_SHIFT (24U)
2988/*! CLCK_WAY - Cache Lock Way x
2989 * 0b0000..Cache way is unlocked and may be displaced
2990 * 0b0001..Cache way is locked and its contents are not displaced
2991 */
2992#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
2993#define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U)
2994#define FMC_PFB0CR_B0RWSC_SHIFT (28U)
2995#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
2996/*! @} */
2997
2998/*! @name PFB1CR - Flash Bank 1 Control Register */
2999/*! @{ */
3000#define FMC_PFB1CR_B1SEBE_MASK (0x1U)
3001#define FMC_PFB1CR_B1SEBE_SHIFT (0U)
3002/*! B1SEBE - Bank 1 Single Entry Buffer Enable
3003 * 0b0..Single entry buffer is disabled.
3004 * 0b1..Single entry buffer is enabled.
3005 */
3006#define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK)
3007#define FMC_PFB1CR_B1IPE_MASK (0x2U)
3008#define FMC_PFB1CR_B1IPE_SHIFT (1U)
3009/*! B1IPE - Bank 1 Instruction Prefetch Enable
3010 * 0b0..Do not prefetch in response to instruction fetches.
3011 * 0b1..Enable prefetches in response to instruction fetches.
3012 */
3013#define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK)
3014#define FMC_PFB1CR_B1DPE_MASK (0x4U)
3015#define FMC_PFB1CR_B1DPE_SHIFT (2U)
3016/*! B1DPE - Bank 1 Data Prefetch Enable
3017 * 0b0..Do not prefetch in response to data references.
3018 * 0b1..Enable prefetches in response to data references.
3019 */
3020#define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK)
3021#define FMC_PFB1CR_B1ICE_MASK (0x8U)
3022#define FMC_PFB1CR_B1ICE_SHIFT (3U)
3023/*! B1ICE - Bank 1 Instruction Cache Enable
3024 * 0b0..Do not cache instruction fetches.
3025 * 0b1..Cache instruction fetches.
3026 */
3027#define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK)
3028#define FMC_PFB1CR_B1DCE_MASK (0x10U)
3029#define FMC_PFB1CR_B1DCE_SHIFT (4U)
3030/*! B1DCE - Bank 1 Data Cache Enable
3031 * 0b0..Do not cache data references.
3032 * 0b1..Cache data references.
3033 */
3034#define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK)
3035#define FMC_PFB1CR_B1MW_MASK (0x60000U)
3036#define FMC_PFB1CR_B1MW_SHIFT (17U)
3037/*! B1MW - Bank 1 Memory Width
3038 * 0b00..32 bits
3039 * 0b01..64 bits
3040 * 0b10..Reserved
3041 * 0b11..Reserved
3042 */
3043#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)
3044#define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U)
3045#define FMC_PFB1CR_B1RWSC_SHIFT (28U)
3046#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK)
3047/*! @} */
3048
3049/*! @name TAGVDW0S - Cache Tag Storage */
3050/*! @{ */
3051#define FMC_TAGVDW0S_valid_MASK (0x1U)
3052#define FMC_TAGVDW0S_valid_SHIFT (0U)
3053#define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
3054#define FMC_TAGVDW0S_tag_MASK (0x7FFE0U)
3055#define FMC_TAGVDW0S_tag_SHIFT (5U)
3056#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
3057/*! @} */
3058
3059/* The count of FMC_TAGVDW0S */
3060#define FMC_TAGVDW0S_COUNT (8U)
3061
3062/*! @name TAGVDW1S - Cache Tag Storage */
3063/*! @{ */
3064#define FMC_TAGVDW1S_valid_MASK (0x1U)
3065#define FMC_TAGVDW1S_valid_SHIFT (0U)
3066#define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
3067#define FMC_TAGVDW1S_tag_MASK (0x7FFE0U)
3068#define FMC_TAGVDW1S_tag_SHIFT (5U)
3069#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
3070/*! @} */
3071
3072/* The count of FMC_TAGVDW1S */
3073#define FMC_TAGVDW1S_COUNT (8U)
3074
3075/*! @name TAGVDW2S - Cache Tag Storage */
3076/*! @{ */
3077#define FMC_TAGVDW2S_valid_MASK (0x1U)
3078#define FMC_TAGVDW2S_valid_SHIFT (0U)
3079#define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
3080#define FMC_TAGVDW2S_tag_MASK (0x7FFE0U)
3081#define FMC_TAGVDW2S_tag_SHIFT (5U)
3082#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
3083/*! @} */
3084
3085/* The count of FMC_TAGVDW2S */
3086#define FMC_TAGVDW2S_COUNT (8U)
3087
3088/*! @name TAGVDW3S - Cache Tag Storage */
3089/*! @{ */
3090#define FMC_TAGVDW3S_valid_MASK (0x1U)
3091#define FMC_TAGVDW3S_valid_SHIFT (0U)
3092#define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
3093#define FMC_TAGVDW3S_tag_MASK (0x7FFE0U)
3094#define FMC_TAGVDW3S_tag_SHIFT (5U)
3095#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
3096/*! @} */
3097
3098/* The count of FMC_TAGVDW3S */
3099#define FMC_TAGVDW3S_COUNT (8U)
3100
3101/*! @name DATA_U - Cache Data Storage (upper word) */
3102/*! @{ */
3103#define FMC_DATA_U_data_MASK (0xFFFFFFFFU)
3104#define FMC_DATA_U_data_SHIFT (0U)
3105#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK)
3106/*! @} */
3107
3108/* The count of FMC_DATA_U */
3109#define FMC_DATA_U_COUNT (4U)
3110
3111/* The count of FMC_DATA_U */
3112#define FMC_DATA_U_COUNT2 (8U)
3113
3114/*! @name DATA_L - Cache Data Storage (lower word) */
3115/*! @{ */
3116#define FMC_DATA_L_data_MASK (0xFFFFFFFFU)
3117#define FMC_DATA_L_data_SHIFT (0U)
3118#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK)
3119/*! @} */
3120
3121/* The count of FMC_DATA_L */
3122#define FMC_DATA_L_COUNT (4U)
3123
3124/* The count of FMC_DATA_L */
3125#define FMC_DATA_L_COUNT2 (8U)
3126
3127
3128/*!
3129 * @}
3130 */ /* end of group FMC_Register_Masks */
3131
3132
3133/* FMC - Peripheral instance base addresses */
3134/** Peripheral FMC base address */
3135#define FMC_BASE (0x4001F000u)
3136/** Peripheral FMC base pointer */
3137#define FMC ((FMC_Type *)FMC_BASE)
3138/** Array initializer of FMC peripheral base addresses */
3139#define FMC_BASE_ADDRS { FMC_BASE }
3140/** Array initializer of FMC peripheral base pointers */
3141#define FMC_BASE_PTRS { FMC }
3142
3143/*!
3144 * @}
3145 */ /* end of group FMC_Peripheral_Access_Layer */
3146
3147
3148/* ----------------------------------------------------------------------------
3149 -- FTFA Peripheral Access Layer
3150 ---------------------------------------------------------------------------- */
3151
3152/*!
3153 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
3154 * @{
3155 */
3156
3157/** FTFA - Register Layout Typedef */
3158typedef struct {
3159 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
3160 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
3161 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
3162 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
3163 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
3164 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
3165 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
3166 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
3167 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
3168 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
3169 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
3170 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
3171 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
3172 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
3173 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
3174 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
3175 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
3176 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
3177 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
3178 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
3179 uint8_t RESERVED_0[4];
3180 __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
3181 __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
3182 __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
3183 __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
3184 __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
3185 __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
3186 __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
3187 __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
3188 __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
3189 __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
3190 __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
3191 __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
3192 __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
3193 __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
3194 __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
3195 __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
3196 __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
3197 uint8_t RESERVED_1[2];
3198 __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
3199} FTFA_Type;
3200
3201/* ----------------------------------------------------------------------------
3202 -- FTFA Register Masks
3203 ---------------------------------------------------------------------------- */
3204
3205/*!
3206 * @addtogroup FTFA_Register_Masks FTFA Register Masks
3207 * @{
3208 */
3209
3210/*! @name FSTAT - Flash Status Register */
3211/*! @{ */
3212#define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
3213#define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
3214#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
3215#define FTFA_FSTAT_FPVIOL_MASK (0x10U)
3216#define FTFA_FSTAT_FPVIOL_SHIFT (4U)
3217/*! FPVIOL - Flash Protection Violation Flag
3218 * 0b0..No protection violation detected
3219 * 0b1..Protection violation detected
3220 */
3221#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
3222#define FTFA_FSTAT_ACCERR_MASK (0x20U)
3223#define FTFA_FSTAT_ACCERR_SHIFT (5U)
3224/*! ACCERR - Flash Access Error Flag
3225 * 0b0..No access error detected
3226 * 0b1..Access error detected
3227 */
3228#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
3229#define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
3230#define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
3231/*! RDCOLERR - Flash Read Collision Error Flag
3232 * 0b0..No collision error detected
3233 * 0b1..Collision error detected
3234 */
3235#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
3236#define FTFA_FSTAT_CCIF_MASK (0x80U)
3237#define FTFA_FSTAT_CCIF_SHIFT (7U)
3238/*! CCIF - Command Complete Interrupt Flag
3239 * 0b0..Flash command in progress
3240 * 0b1..Flash command has completed
3241 */
3242#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
3243/*! @} */
3244
3245/*! @name FCNFG - Flash Configuration Register */
3246/*! @{ */
3247#define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
3248#define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
3249/*! ERSSUSP - Erase Suspend
3250 * 0b0..No suspend requested
3251 * 0b1..Suspend the current Erase Flash Sector command execution.
3252 */
3253#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
3254#define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
3255#define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
3256/*! ERSAREQ - Erase All Request
3257 * 0b0..No request or request complete
3258 * 0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state.
3259 */
3260#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
3261#define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
3262#define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
3263/*! RDCOLLIE - Read Collision Error Interrupt Enable
3264 * 0b0..Read collision error interrupt disabled
3265 * 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]).
3266 */
3267#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
3268#define FTFA_FCNFG_CCIE_MASK (0x80U)
3269#define FTFA_FCNFG_CCIE_SHIFT (7U)
3270/*! CCIE - Command Complete Interrupt Enable
3271 * 0b0..Command complete interrupt disabled
3272 * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
3273 */
3274#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
3275/*! @} */
3276
3277/*! @name FSEC - Flash Security Register */
3278/*! @{ */
3279#define FTFA_FSEC_SEC_MASK (0x3U)
3280#define FTFA_FSEC_SEC_SHIFT (0U)
3281/*! SEC - Flash Security
3282 * 0b00..MCU security status is secure.
3283 * 0b01..MCU security status is secure.
3284 * 0b10..MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
3285 * 0b11..MCU security status is secure.
3286 */
3287#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
3288#define FTFA_FSEC_FSLACC_MASK (0xCU)
3289#define FTFA_FSEC_FSLACC_SHIFT (2U)
3290/*! FSLACC - Freescale Failure Analysis Access Code
3291 * 0b00..Freescale factory access granted
3292 * 0b01..Freescale factory access denied
3293 * 0b10..Freescale factory access denied
3294 * 0b11..Freescale factory access granted
3295 */
3296#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
3297#define FTFA_FSEC_MEEN_MASK (0x30U)
3298#define FTFA_FSEC_MEEN_SHIFT (4U)
3299/*! MEEN - Mass Erase Enable Bits
3300 * 0b00..Mass erase is enabled
3301 * 0b01..Mass erase is enabled
3302 * 0b10..Mass erase is disabled
3303 * 0b11..Mass erase is enabled
3304 */
3305#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
3306#define FTFA_FSEC_KEYEN_MASK (0xC0U)
3307#define FTFA_FSEC_KEYEN_SHIFT (6U)
3308/*! KEYEN - Backdoor Key Security Enable
3309 * 0b00..Backdoor key access disabled
3310 * 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
3311 * 0b10..Backdoor key access enabled
3312 * 0b11..Backdoor key access disabled
3313 */
3314#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
3315/*! @} */
3316
3317/*! @name FOPT - Flash Option Register */
3318/*! @{ */
3319#define FTFA_FOPT_OPT_MASK (0xFFU)
3320#define FTFA_FOPT_OPT_SHIFT (0U)
3321#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
3322/*! @} */
3323
3324/*! @name FCCOB3 - Flash Common Command Object Registers */
3325/*! @{ */
3326#define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
3327#define FTFA_FCCOB3_CCOBn_SHIFT (0U)
3328#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
3329/*! @} */
3330
3331/*! @name FCCOB2 - Flash Common Command Object Registers */
3332/*! @{ */
3333#define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
3334#define FTFA_FCCOB2_CCOBn_SHIFT (0U)
3335#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
3336/*! @} */
3337
3338/*! @name FCCOB1 - Flash Common Command Object Registers */
3339/*! @{ */
3340#define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
3341#define FTFA_FCCOB1_CCOBn_SHIFT (0U)
3342#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
3343/*! @} */
3344
3345/*! @name FCCOB0 - Flash Common Command Object Registers */
3346/*! @{ */
3347#define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
3348#define FTFA_FCCOB0_CCOBn_SHIFT (0U)
3349#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
3350/*! @} */
3351
3352/*! @name FCCOB7 - Flash Common Command Object Registers */
3353/*! @{ */
3354#define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
3355#define FTFA_FCCOB7_CCOBn_SHIFT (0U)
3356#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
3357/*! @} */
3358
3359/*! @name FCCOB6 - Flash Common Command Object Registers */
3360/*! @{ */
3361#define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
3362#define FTFA_FCCOB6_CCOBn_SHIFT (0U)
3363#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
3364/*! @} */
3365
3366/*! @name FCCOB5 - Flash Common Command Object Registers */
3367/*! @{ */
3368#define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
3369#define FTFA_FCCOB5_CCOBn_SHIFT (0U)
3370#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
3371/*! @} */
3372
3373/*! @name FCCOB4 - Flash Common Command Object Registers */
3374/*! @{ */
3375#define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
3376#define FTFA_FCCOB4_CCOBn_SHIFT (0U)
3377#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
3378/*! @} */
3379
3380/*! @name FCCOBB - Flash Common Command Object Registers */
3381/*! @{ */
3382#define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
3383#define FTFA_FCCOBB_CCOBn_SHIFT (0U)
3384#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
3385/*! @} */
3386
3387/*! @name FCCOBA - Flash Common Command Object Registers */
3388/*! @{ */
3389#define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
3390#define FTFA_FCCOBA_CCOBn_SHIFT (0U)
3391#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
3392/*! @} */
3393
3394/*! @name FCCOB9 - Flash Common Command Object Registers */
3395/*! @{ */
3396#define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
3397#define FTFA_FCCOB9_CCOBn_SHIFT (0U)
3398#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
3399/*! @} */
3400
3401/*! @name FCCOB8 - Flash Common Command Object Registers */
3402/*! @{ */
3403#define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
3404#define FTFA_FCCOB8_CCOBn_SHIFT (0U)
3405#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
3406/*! @} */
3407
3408/*! @name FPROT3 - Program Flash Protection Registers */
3409/*! @{ */
3410#define FTFA_FPROT3_PROT_MASK (0xFFU)
3411#define FTFA_FPROT3_PROT_SHIFT (0U)
3412/*! PROT - Program Flash Region Protect
3413 * 0b00000000..Program flash region is protected.
3414 * 0b00000001..Program flash region is not protected
3415 */
3416#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
3417/*! @} */
3418
3419/*! @name FPROT2 - Program Flash Protection Registers */
3420/*! @{ */
3421#define FTFA_FPROT2_PROT_MASK (0xFFU)
3422#define FTFA_FPROT2_PROT_SHIFT (0U)
3423/*! PROT - Program Flash Region Protect
3424 * 0b00000000..Program flash region is protected.
3425 * 0b00000001..Program flash region is not protected
3426 */
3427#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
3428/*! @} */
3429
3430/*! @name FPROT1 - Program Flash Protection Registers */
3431/*! @{ */
3432#define FTFA_FPROT1_PROT_MASK (0xFFU)
3433#define FTFA_FPROT1_PROT_SHIFT (0U)
3434/*! PROT - Program Flash Region Protect
3435 * 0b00000000..Program flash region is protected.
3436 * 0b00000001..Program flash region is not protected
3437 */
3438#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
3439/*! @} */
3440
3441/*! @name FPROT0 - Program Flash Protection Registers */
3442/*! @{ */
3443#define FTFA_FPROT0_PROT_MASK (0xFFU)
3444#define FTFA_FPROT0_PROT_SHIFT (0U)
3445/*! PROT - Program Flash Region Protect
3446 * 0b00000000..Program flash region is protected.
3447 * 0b00000001..Program flash region is not protected
3448 */
3449#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
3450/*! @} */
3451
3452/*! @name XACCH3 - Execute-only Access Registers */
3453/*! @{ */
3454#define FTFA_XACCH3_XA_MASK (0xFFU)
3455#define FTFA_XACCH3_XA_SHIFT (0U)
3456/*! XA - Execute-only access control
3457 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
3458 * 0b00000001..Associated segment is accessible as data or in execute mode
3459 */
3460#define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH3_XA_SHIFT)) & FTFA_XACCH3_XA_MASK)
3461/*! @} */
3462
3463/*! @name XACCH2 - Execute-only Access Registers */
3464/*! @{ */
3465#define FTFA_XACCH2_XA_MASK (0xFFU)
3466#define FTFA_XACCH2_XA_SHIFT (0U)
3467/*! XA - Execute-only access control
3468 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
3469 * 0b00000001..Associated segment is accessible as data or in execute mode
3470 */
3471#define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH2_XA_SHIFT)) & FTFA_XACCH2_XA_MASK)
3472/*! @} */
3473
3474/*! @name XACCH1 - Execute-only Access Registers */
3475/*! @{ */
3476#define FTFA_XACCH1_XA_MASK (0xFFU)
3477#define FTFA_XACCH1_XA_SHIFT (0U)
3478/*! XA - Execute-only access control
3479 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
3480 * 0b00000001..Associated segment is accessible as data or in execute mode
3481 */
3482#define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH1_XA_SHIFT)) & FTFA_XACCH1_XA_MASK)
3483/*! @} */
3484
3485/*! @name XACCH0 - Execute-only Access Registers */
3486/*! @{ */
3487#define FTFA_XACCH0_XA_MASK (0xFFU)
3488#define FTFA_XACCH0_XA_SHIFT (0U)
3489/*! XA - Execute-only access control
3490 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
3491 * 0b00000001..Associated segment is accessible as data or in execute mode
3492 */
3493#define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH0_XA_SHIFT)) & FTFA_XACCH0_XA_MASK)
3494/*! @} */
3495
3496/*! @name XACCL3 - Execute-only Access Registers */
3497/*! @{ */
3498#define FTFA_XACCL3_XA_MASK (0xFFU)
3499#define FTFA_XACCL3_XA_SHIFT (0U)
3500/*! XA - Execute-only access control
3501 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
3502 * 0b00000001..Associated segment is accessible as data or in execute mode
3503 */
3504#define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL3_XA_SHIFT)) & FTFA_XACCL3_XA_MASK)
3505/*! @} */
3506
3507/*! @name XACCL2 - Execute-only Access Registers */
3508/*! @{ */
3509#define FTFA_XACCL2_XA_MASK (0xFFU)
3510#define FTFA_XACCL2_XA_SHIFT (0U)
3511/*! XA - Execute-only access control
3512 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
3513 * 0b00000001..Associated segment is accessible as data or in execute mode
3514 */
3515#define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL2_XA_SHIFT)) & FTFA_XACCL2_XA_MASK)
3516/*! @} */
3517
3518/*! @name XACCL1 - Execute-only Access Registers */
3519/*! @{ */
3520#define FTFA_XACCL1_XA_MASK (0xFFU)
3521#define FTFA_XACCL1_XA_SHIFT (0U)
3522/*! XA - Execute-only access control
3523 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
3524 * 0b00000001..Associated segment is accessible as data or in execute mode
3525 */
3526#define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL1_XA_SHIFT)) & FTFA_XACCL1_XA_MASK)
3527/*! @} */
3528
3529/*! @name XACCL0 - Execute-only Access Registers */
3530/*! @{ */
3531#define FTFA_XACCL0_XA_MASK (0xFFU)
3532#define FTFA_XACCL0_XA_SHIFT (0U)
3533/*! XA - Execute-only access control
3534 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
3535 * 0b00000001..Associated segment is accessible as data or in execute mode
3536 */
3537#define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL0_XA_SHIFT)) & FTFA_XACCL0_XA_MASK)
3538/*! @} */
3539
3540/*! @name SACCH3 - Supervisor-only Access Registers */
3541/*! @{ */
3542#define FTFA_SACCH3_SA_MASK (0xFFU)
3543#define FTFA_SACCH3_SA_SHIFT (0U)
3544/*! SA - Supervisor-only access control
3545 * 0b00000000..Associated segment is accessible in supervisor mode only
3546 * 0b00000001..Associated segment is accessible in user or supervisor mode
3547 */
3548#define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH3_SA_SHIFT)) & FTFA_SACCH3_SA_MASK)
3549/*! @} */
3550
3551/*! @name SACCH2 - Supervisor-only Access Registers */
3552/*! @{ */
3553#define FTFA_SACCH2_SA_MASK (0xFFU)
3554#define FTFA_SACCH2_SA_SHIFT (0U)
3555/*! SA - Supervisor-only access control
3556 * 0b00000000..Associated segment is accessible in supervisor mode only
3557 * 0b00000001..Associated segment is accessible in user or supervisor mode
3558 */
3559#define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH2_SA_SHIFT)) & FTFA_SACCH2_SA_MASK)
3560/*! @} */
3561
3562/*! @name SACCH1 - Supervisor-only Access Registers */
3563/*! @{ */
3564#define FTFA_SACCH1_SA_MASK (0xFFU)
3565#define FTFA_SACCH1_SA_SHIFT (0U)
3566/*! SA - Supervisor-only access control
3567 * 0b00000000..Associated segment is accessible in supervisor mode only
3568 * 0b00000001..Associated segment is accessible in user or supervisor mode
3569 */
3570#define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH1_SA_SHIFT)) & FTFA_SACCH1_SA_MASK)
3571/*! @} */
3572
3573/*! @name SACCH0 - Supervisor-only Access Registers */
3574/*! @{ */
3575#define FTFA_SACCH0_SA_MASK (0xFFU)
3576#define FTFA_SACCH0_SA_SHIFT (0U)
3577/*! SA - Supervisor-only access control
3578 * 0b00000000..Associated segment is accessible in supervisor mode only
3579 * 0b00000001..Associated segment is accessible in user or supervisor mode
3580 */
3581#define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH0_SA_SHIFT)) & FTFA_SACCH0_SA_MASK)
3582/*! @} */
3583
3584/*! @name SACCL3 - Supervisor-only Access Registers */
3585/*! @{ */
3586#define FTFA_SACCL3_SA_MASK (0xFFU)
3587#define FTFA_SACCL3_SA_SHIFT (0U)
3588/*! SA - Supervisor-only access control
3589 * 0b00000000..Associated segment is accessible in supervisor mode only
3590 * 0b00000001..Associated segment is accessible in user or supervisor mode
3591 */
3592#define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL3_SA_SHIFT)) & FTFA_SACCL3_SA_MASK)
3593/*! @} */
3594
3595/*! @name SACCL2 - Supervisor-only Access Registers */
3596/*! @{ */
3597#define FTFA_SACCL2_SA_MASK (0xFFU)
3598#define FTFA_SACCL2_SA_SHIFT (0U)
3599/*! SA - Supervisor-only access control
3600 * 0b00000000..Associated segment is accessible in supervisor mode only
3601 * 0b00000001..Associated segment is accessible in user or supervisor mode
3602 */
3603#define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL2_SA_SHIFT)) & FTFA_SACCL2_SA_MASK)
3604/*! @} */
3605
3606/*! @name SACCL1 - Supervisor-only Access Registers */
3607/*! @{ */
3608#define FTFA_SACCL1_SA_MASK (0xFFU)
3609#define FTFA_SACCL1_SA_SHIFT (0U)
3610/*! SA - Supervisor-only access control
3611 * 0b00000000..Associated segment is accessible in supervisor mode only
3612 * 0b00000001..Associated segment is accessible in user or supervisor mode
3613 */
3614#define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL1_SA_SHIFT)) & FTFA_SACCL1_SA_MASK)
3615/*! @} */
3616
3617/*! @name SACCL0 - Supervisor-only Access Registers */
3618/*! @{ */
3619#define FTFA_SACCL0_SA_MASK (0xFFU)
3620#define FTFA_SACCL0_SA_SHIFT (0U)
3621/*! SA - Supervisor-only access control
3622 * 0b00000000..Associated segment is accessible in supervisor mode only
3623 * 0b00000001..Associated segment is accessible in user or supervisor mode
3624 */
3625#define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL0_SA_SHIFT)) & FTFA_SACCL0_SA_MASK)
3626/*! @} */
3627
3628/*! @name FACSS - Flash Access Segment Size Register */
3629/*! @{ */
3630#define FTFA_FACSS_SGSIZE_MASK (0xFFU)
3631#define FTFA_FACSS_SGSIZE_SHIFT (0U)
3632#define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSS_SGSIZE_SHIFT)) & FTFA_FACSS_SGSIZE_MASK)
3633/*! @} */
3634
3635/*! @name FACSN - Flash Access Segment Number Register */
3636/*! @{ */
3637#define FTFA_FACSN_NUMSG_MASK (0xFFU)
3638#define FTFA_FACSN_NUMSG_SHIFT (0U)
3639/*! NUMSG - Number of Segments Indicator
3640 * 0b00100000..Program flash memory is divided into 32 segments (64 Kbytes, 128 Kbytes)
3641 * 0b00101000..Program flash memory is divided into 40 segments (160 Kbytes)
3642 * 0b01000000..Program flash memory is divided into 64 segments (256 Kbytes, 512 Kbytes)
3643 */
3644#define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSN_NUMSG_SHIFT)) & FTFA_FACSN_NUMSG_MASK)
3645/*! @} */
3646
3647
3648/*!
3649 * @}
3650 */ /* end of group FTFA_Register_Masks */
3651
3652
3653/* FTFA - Peripheral instance base addresses */
3654/** Peripheral FTFA base address */
3655#define FTFA_BASE (0x40020000u)
3656/** Peripheral FTFA base pointer */
3657#define FTFA ((FTFA_Type *)FTFA_BASE)
3658/** Array initializer of FTFA peripheral base addresses */
3659#define FTFA_BASE_ADDRS { FTFA_BASE }
3660/** Array initializer of FTFA peripheral base pointers */
3661#define FTFA_BASE_PTRS { FTFA }
3662/** Interrupt vectors for the FTFA peripheral type */
3663#define FTFA_COMMAND_COMPLETE_IRQS { FTF_IRQn }
3664#define FTFA_READ_COLLISION_IRQS { Read_Collision_IRQn }
3665
3666/*!
3667 * @}
3668 */ /* end of group FTFA_Peripheral_Access_Layer */
3669
3670
3671/* ----------------------------------------------------------------------------
3672 -- FTM Peripheral Access Layer
3673 ---------------------------------------------------------------------------- */
3674
3675/*!
3676 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
3677 * @{
3678 */
3679
3680/** FTM - Register Layout Typedef */
3681typedef struct {
3682 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
3683 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
3684 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
3685 struct { /* offset: 0xC, array step: 0x8 */
3686 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
3687 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
3688 } CONTROLS[8];
3689 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
3690 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
3691 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
3692 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
3693 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
3694 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
3695 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
3696 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
3697 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
3698 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
3699 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
3700 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
3701 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
3702 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
3703 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
3704 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
3705 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
3706 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
3707 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
3708 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
3709} FTM_Type;
3710
3711/* ----------------------------------------------------------------------------
3712 -- FTM Register Masks
3713 ---------------------------------------------------------------------------- */
3714
3715/*!
3716 * @addtogroup FTM_Register_Masks FTM Register Masks
3717 * @{
3718 */
3719
3720/*! @name SC - Status And Control */
3721/*! @{ */
3722#define FTM_SC_PS_MASK (0x7U)
3723#define FTM_SC_PS_SHIFT (0U)
3724/*! PS - Prescale Factor Selection
3725 * 0b000..Divide by 1
3726 * 0b001..Divide by 2
3727 * 0b010..Divide by 4
3728 * 0b011..Divide by 8
3729 * 0b100..Divide by 16
3730 * 0b101..Divide by 32
3731 * 0b110..Divide by 64
3732 * 0b111..Divide by 128
3733 */
3734#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
3735#define FTM_SC_CLKS_MASK (0x18U)
3736#define FTM_SC_CLKS_SHIFT (3U)
3737/*! CLKS - Clock Source Selection
3738 * 0b00..No clock selected. This in effect disables the FTM counter.
3739 * 0b01..System clock
3740 * 0b10..Fixed frequency clock
3741 * 0b11..External clock
3742 */
3743#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
3744#define FTM_SC_CPWMS_MASK (0x20U)
3745#define FTM_SC_CPWMS_SHIFT (5U)
3746/*! CPWMS - Center-Aligned PWM Select
3747 * 0b0..FTM counter operates in Up Counting mode.
3748 * 0b1..FTM counter operates in Up-Down Counting mode.
3749 */
3750#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
3751#define FTM_SC_TOIE_MASK (0x40U)
3752#define FTM_SC_TOIE_SHIFT (6U)
3753/*! TOIE - Timer Overflow Interrupt Enable
3754 * 0b0..Disable TOF interrupts. Use software polling.
3755 * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
3756 */
3757#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
3758#define FTM_SC_TOF_MASK (0x80U)
3759#define FTM_SC_TOF_SHIFT (7U)
3760/*! TOF - Timer Overflow Flag
3761 * 0b0..FTM counter has not overflowed.
3762 * 0b1..FTM counter has overflowed.
3763 */
3764#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
3765/*! @} */
3766
3767/*! @name CNT - Counter */
3768/*! @{ */
3769#define FTM_CNT_COUNT_MASK (0xFFFFU)
3770#define FTM_CNT_COUNT_SHIFT (0U)
3771#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
3772/*! @} */
3773
3774/*! @name MOD - Modulo */
3775/*! @{ */
3776#define FTM_MOD_MOD_MASK (0xFFFFU)
3777#define FTM_MOD_MOD_SHIFT (0U)
3778#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
3779/*! @} */
3780
3781/*! @name CnSC - Channel (n) Status And Control */
3782/*! @{ */
3783#define FTM_CnSC_DMA_MASK (0x1U)
3784#define FTM_CnSC_DMA_SHIFT (0U)
3785/*! DMA - DMA Enable
3786 * 0b0..Disable DMA transfers.
3787 * 0b1..Enable DMA transfers.
3788 */
3789#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
3790#define FTM_CnSC_ICRST_MASK (0x2U)
3791#define FTM_CnSC_ICRST_SHIFT (1U)
3792/*! ICRST - FTM counter reset by the selected input capture event.
3793 * 0b0..FTM counter is not reset when the selected channel (n) input event is detected.
3794 * 0b1..FTM counter is reset when the selected channel (n) input event is detected.
3795 */
3796#define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK)
3797#define FTM_CnSC_ELSA_MASK (0x4U)
3798#define FTM_CnSC_ELSA_SHIFT (2U)
3799#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
3800#define FTM_CnSC_ELSB_MASK (0x8U)
3801#define FTM_CnSC_ELSB_SHIFT (3U)
3802#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
3803#define FTM_CnSC_MSA_MASK (0x10U)
3804#define FTM_CnSC_MSA_SHIFT (4U)
3805#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
3806#define FTM_CnSC_MSB_MASK (0x20U)
3807#define FTM_CnSC_MSB_SHIFT (5U)
3808#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
3809#define FTM_CnSC_CHIE_MASK (0x40U)
3810#define FTM_CnSC_CHIE_SHIFT (6U)
3811/*! CHIE - Channel Interrupt Enable
3812 * 0b0..Disable channel interrupts. Use software polling.
3813 * 0b1..Enable channel interrupts.
3814 */
3815#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
3816#define FTM_CnSC_CHF_MASK (0x80U)
3817#define FTM_CnSC_CHF_SHIFT (7U)
3818/*! CHF - Channel Flag
3819 * 0b0..No channel event has occurred.
3820 * 0b1..A channel event has occurred.
3821 */
3822#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
3823/*! @} */
3824
3825/* The count of FTM_CnSC */
3826#define FTM_CnSC_COUNT (8U)
3827
3828/*! @name CnV - Channel (n) Value */
3829/*! @{ */
3830#define FTM_CnV_VAL_MASK (0xFFFFU)
3831#define FTM_CnV_VAL_SHIFT (0U)
3832#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
3833/*! @} */
3834
3835/* The count of FTM_CnV */
3836#define FTM_CnV_COUNT (8U)
3837
3838/*! @name CNTIN - Counter Initial Value */
3839/*! @{ */
3840#define FTM_CNTIN_INIT_MASK (0xFFFFU)
3841#define FTM_CNTIN_INIT_SHIFT (0U)
3842#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
3843/*! @} */
3844
3845/*! @name STATUS - Capture And Compare Status */
3846/*! @{ */
3847#define FTM_STATUS_CH0F_MASK (0x1U)
3848#define FTM_STATUS_CH0F_SHIFT (0U)
3849/*! CH0F - Channel 0 Flag
3850 * 0b0..No channel event has occurred.
3851 * 0b1..A channel event has occurred.
3852 */
3853#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
3854#define FTM_STATUS_CH1F_MASK (0x2U)
3855#define FTM_STATUS_CH1F_SHIFT (1U)
3856/*! CH1F - Channel 1 Flag
3857 * 0b0..No channel event has occurred.
3858 * 0b1..A channel event has occurred.
3859 */
3860#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
3861#define FTM_STATUS_CH2F_MASK (0x4U)
3862#define FTM_STATUS_CH2F_SHIFT (2U)
3863/*! CH2F - Channel 2 Flag
3864 * 0b0..No channel event has occurred.
3865 * 0b1..A channel event has occurred.
3866 */
3867#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
3868#define FTM_STATUS_CH3F_MASK (0x8U)
3869#define FTM_STATUS_CH3F_SHIFT (3U)
3870/*! CH3F - Channel 3 Flag
3871 * 0b0..No channel event has occurred.
3872 * 0b1..A channel event has occurred.
3873 */
3874#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
3875#define FTM_STATUS_CH4F_MASK (0x10U)
3876#define FTM_STATUS_CH4F_SHIFT (4U)
3877/*! CH4F - Channel 4 Flag
3878 * 0b0..No channel event has occurred.
3879 * 0b1..A channel event has occurred.
3880 */
3881#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
3882#define FTM_STATUS_CH5F_MASK (0x20U)
3883#define FTM_STATUS_CH5F_SHIFT (5U)
3884/*! CH5F - Channel 5 Flag
3885 * 0b0..No channel event has occurred.
3886 * 0b1..A channel event has occurred.
3887 */
3888#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
3889#define FTM_STATUS_CH6F_MASK (0x40U)
3890#define FTM_STATUS_CH6F_SHIFT (6U)
3891/*! CH6F - Channel 6 Flag
3892 * 0b0..No channel event has occurred.
3893 * 0b1..A channel event has occurred.
3894 */
3895#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
3896#define FTM_STATUS_CH7F_MASK (0x80U)
3897#define FTM_STATUS_CH7F_SHIFT (7U)
3898/*! CH7F - Channel 7 Flag
3899 * 0b0..No channel event has occurred.
3900 * 0b1..A channel event has occurred.
3901 */
3902#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
3903/*! @} */
3904
3905/*! @name MODE - Features Mode Selection */
3906/*! @{ */
3907#define FTM_MODE_FTMEN_MASK (0x1U)
3908#define FTM_MODE_FTMEN_SHIFT (0U)
3909/*! FTMEN - FTM Enable
3910 * 0b0..TPM compatibility. Free running counter and synchronization compatible with TPM.
3911 * 0b1..Free running counter and synchronization are different from TPM behavior.
3912 */
3913#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
3914#define FTM_MODE_INIT_MASK (0x2U)
3915#define FTM_MODE_INIT_SHIFT (1U)
3916#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
3917#define FTM_MODE_WPDIS_MASK (0x4U)
3918#define FTM_MODE_WPDIS_SHIFT (2U)
3919/*! WPDIS - Write Protection Disable
3920 * 0b0..Write protection is enabled.
3921 * 0b1..Write protection is disabled.
3922 */
3923#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
3924#define FTM_MODE_PWMSYNC_MASK (0x8U)
3925#define FTM_MODE_PWMSYNC_SHIFT (3U)
3926/*! PWMSYNC - PWM Synchronization Mode
3927 * 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
3928 * 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
3929 */
3930#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
3931#define FTM_MODE_CAPTEST_MASK (0x10U)
3932#define FTM_MODE_CAPTEST_SHIFT (4U)
3933/*! CAPTEST - Capture Test Mode Enable
3934 * 0b0..Capture test mode is disabled.
3935 * 0b1..Capture test mode is enabled.
3936 */
3937#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
3938#define FTM_MODE_FAULTM_MASK (0x60U)
3939#define FTM_MODE_FAULTM_SHIFT (5U)
3940/*! FAULTM - Fault Control Mode
3941 * 0b00..Fault control is disabled for all channels.
3942 * 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
3943 * 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
3944 * 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
3945 */
3946#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
3947#define FTM_MODE_FAULTIE_MASK (0x80U)
3948#define FTM_MODE_FAULTIE_SHIFT (7U)
3949/*! FAULTIE - Fault Interrupt Enable
3950 * 0b0..Fault control interrupt is disabled.
3951 * 0b1..Fault control interrupt is enabled.
3952 */
3953#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
3954/*! @} */
3955
3956/*! @name SYNC - Synchronization */
3957/*! @{ */
3958#define FTM_SYNC_CNTMIN_MASK (0x1U)
3959#define FTM_SYNC_CNTMIN_SHIFT (0U)
3960/*! CNTMIN - Minimum Loading Point Enable
3961 * 0b0..The minimum loading point is disabled.
3962 * 0b1..The minimum loading point is enabled.
3963 */
3964#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
3965#define FTM_SYNC_CNTMAX_MASK (0x2U)
3966#define FTM_SYNC_CNTMAX_SHIFT (1U)
3967/*! CNTMAX - Maximum Loading Point Enable
3968 * 0b0..The maximum loading point is disabled.
3969 * 0b1..The maximum loading point is enabled.
3970 */
3971#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
3972#define FTM_SYNC_REINIT_MASK (0x4U)
3973#define FTM_SYNC_REINIT_SHIFT (2U)
3974/*! REINIT - FTM Counter Reinitialization By Synchronization (FTM counter synchronization)
3975 * 0b0..FTM counter continues to count normally.
3976 * 0b1..FTM counter is updated with its initial value when the selected trigger is detected.
3977 */
3978#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
3979#define FTM_SYNC_SYNCHOM_MASK (0x8U)
3980#define FTM_SYNC_SYNCHOM_SHIFT (3U)
3981/*! SYNCHOM - Output Mask Synchronization
3982 * 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
3983 * 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
3984 */
3985#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
3986#define FTM_SYNC_TRIG0_MASK (0x10U)
3987#define FTM_SYNC_TRIG0_SHIFT (4U)
3988/*! TRIG0 - PWM Synchronization Hardware Trigger 0
3989 * 0b0..Trigger is disabled.
3990 * 0b1..Trigger is enabled.
3991 */
3992#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
3993#define FTM_SYNC_TRIG1_MASK (0x20U)
3994#define FTM_SYNC_TRIG1_SHIFT (5U)
3995/*! TRIG1 - PWM Synchronization Hardware Trigger 1
3996 * 0b0..Trigger is disabled.
3997 * 0b1..Trigger is enabled.
3998 */
3999#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
4000#define FTM_SYNC_TRIG2_MASK (0x40U)
4001#define FTM_SYNC_TRIG2_SHIFT (6U)
4002/*! TRIG2 - PWM Synchronization Hardware Trigger 2
4003 * 0b0..Trigger is disabled.
4004 * 0b1..Trigger is enabled.
4005 */
4006#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
4007#define FTM_SYNC_SWSYNC_MASK (0x80U)
4008#define FTM_SYNC_SWSYNC_SHIFT (7U)
4009/*! SWSYNC - PWM Synchronization Software Trigger
4010 * 0b0..Software trigger is not selected.
4011 * 0b1..Software trigger is selected.
4012 */
4013#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
4014/*! @} */
4015
4016/*! @name OUTINIT - Initial State For Channels Output */
4017/*! @{ */
4018#define FTM_OUTINIT_CH0OI_MASK (0x1U)
4019#define FTM_OUTINIT_CH0OI_SHIFT (0U)
4020/*! CH0OI - Channel 0 Output Initialization Value
4021 * 0b0..The initialization value is 0.
4022 * 0b1..The initialization value is 1.
4023 */
4024#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
4025#define FTM_OUTINIT_CH1OI_MASK (0x2U)
4026#define FTM_OUTINIT_CH1OI_SHIFT (1U)
4027/*! CH1OI - Channel 1 Output Initialization Value
4028 * 0b0..The initialization value is 0.
4029 * 0b1..The initialization value is 1.
4030 */
4031#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
4032#define FTM_OUTINIT_CH2OI_MASK (0x4U)
4033#define FTM_OUTINIT_CH2OI_SHIFT (2U)
4034/*! CH2OI - Channel 2 Output Initialization Value
4035 * 0b0..The initialization value is 0.
4036 * 0b1..The initialization value is 1.
4037 */
4038#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
4039#define FTM_OUTINIT_CH3OI_MASK (0x8U)
4040#define FTM_OUTINIT_CH3OI_SHIFT (3U)
4041/*! CH3OI - Channel 3 Output Initialization Value
4042 * 0b0..The initialization value is 0.
4043 * 0b1..The initialization value is 1.
4044 */
4045#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
4046#define FTM_OUTINIT_CH4OI_MASK (0x10U)
4047#define FTM_OUTINIT_CH4OI_SHIFT (4U)
4048/*! CH4OI - Channel 4 Output Initialization Value
4049 * 0b0..The initialization value is 0.
4050 * 0b1..The initialization value is 1.
4051 */
4052#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
4053#define FTM_OUTINIT_CH5OI_MASK (0x20U)
4054#define FTM_OUTINIT_CH5OI_SHIFT (5U)
4055/*! CH5OI - Channel 5 Output Initialization Value
4056 * 0b0..The initialization value is 0.
4057 * 0b1..The initialization value is 1.
4058 */
4059#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
4060#define FTM_OUTINIT_CH6OI_MASK (0x40U)
4061#define FTM_OUTINIT_CH6OI_SHIFT (6U)
4062/*! CH6OI - Channel 6 Output Initialization Value
4063 * 0b0..The initialization value is 0.
4064 * 0b1..The initialization value is 1.
4065 */
4066#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
4067#define FTM_OUTINIT_CH7OI_MASK (0x80U)
4068#define FTM_OUTINIT_CH7OI_SHIFT (7U)
4069/*! CH7OI - Channel 7 Output Initialization Value
4070 * 0b0..The initialization value is 0.
4071 * 0b1..The initialization value is 1.
4072 */
4073#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
4074/*! @} */
4075
4076/*! @name OUTMASK - Output Mask */
4077/*! @{ */
4078#define FTM_OUTMASK_CH0OM_MASK (0x1U)
4079#define FTM_OUTMASK_CH0OM_SHIFT (0U)
4080/*! CH0OM - Channel 0 Output Mask
4081 * 0b0..Channel output is not masked. It continues to operate normally.
4082 * 0b1..Channel output is masked. It is forced to its inactive state.
4083 */
4084#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
4085#define FTM_OUTMASK_CH1OM_MASK (0x2U)
4086#define FTM_OUTMASK_CH1OM_SHIFT (1U)
4087/*! CH1OM - Channel 1 Output Mask
4088 * 0b0..Channel output is not masked. It continues to operate normally.
4089 * 0b1..Channel output is masked. It is forced to its inactive state.
4090 */
4091#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
4092#define FTM_OUTMASK_CH2OM_MASK (0x4U)
4093#define FTM_OUTMASK_CH2OM_SHIFT (2U)
4094/*! CH2OM - Channel 2 Output Mask
4095 * 0b0..Channel output is not masked. It continues to operate normally.
4096 * 0b1..Channel output is masked. It is forced to its inactive state.
4097 */
4098#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
4099#define FTM_OUTMASK_CH3OM_MASK (0x8U)
4100#define FTM_OUTMASK_CH3OM_SHIFT (3U)
4101/*! CH3OM - Channel 3 Output Mask
4102 * 0b0..Channel output is not masked. It continues to operate normally.
4103 * 0b1..Channel output is masked. It is forced to its inactive state.
4104 */
4105#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
4106#define FTM_OUTMASK_CH4OM_MASK (0x10U)
4107#define FTM_OUTMASK_CH4OM_SHIFT (4U)
4108/*! CH4OM - Channel 4 Output Mask
4109 * 0b0..Channel output is not masked. It continues to operate normally.
4110 * 0b1..Channel output is masked. It is forced to its inactive state.
4111 */
4112#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
4113#define FTM_OUTMASK_CH5OM_MASK (0x20U)
4114#define FTM_OUTMASK_CH5OM_SHIFT (5U)
4115/*! CH5OM - Channel 5 Output Mask
4116 * 0b0..Channel output is not masked. It continues to operate normally.
4117 * 0b1..Channel output is masked. It is forced to its inactive state.
4118 */
4119#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
4120#define FTM_OUTMASK_CH6OM_MASK (0x40U)
4121#define FTM_OUTMASK_CH6OM_SHIFT (6U)
4122/*! CH6OM - Channel 6 Output Mask
4123 * 0b0..Channel output is not masked. It continues to operate normally.
4124 * 0b1..Channel output is masked. It is forced to its inactive state.
4125 */
4126#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
4127#define FTM_OUTMASK_CH7OM_MASK (0x80U)
4128#define FTM_OUTMASK_CH7OM_SHIFT (7U)
4129/*! CH7OM - Channel 7 Output Mask
4130 * 0b0..Channel output is not masked. It continues to operate normally.
4131 * 0b1..Channel output is masked. It is forced to its inactive state.
4132 */
4133#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
4134/*! @} */
4135
4136/*! @name COMBINE - Function For Linked Channels */
4137/*! @{ */
4138#define FTM_COMBINE_COMBINE0_MASK (0x1U)
4139#define FTM_COMBINE_COMBINE0_SHIFT (0U)
4140/*! COMBINE0 - Combine Channels For n = 0
4141 * 0b0..Channels (n) and (n+1) are independent.
4142 * 0b1..Channels (n) and (n+1) are combined.
4143 */
4144#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
4145#define FTM_COMBINE_COMP0_MASK (0x2U)
4146#define FTM_COMBINE_COMP0_SHIFT (1U)
4147/*! COMP0 - Complement Of Channel (n) For n = 0
4148 * 0b0..The channel (n+1) output is the same as the channel (n) output.
4149 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
4150 */
4151#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
4152#define FTM_COMBINE_DECAPEN0_MASK (0x4U)
4153#define FTM_COMBINE_DECAPEN0_SHIFT (2U)
4154/*! DECAPEN0 - Dual Edge Capture Mode Enable For n = 0
4155 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
4156 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
4157 */
4158#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
4159#define FTM_COMBINE_DECAP0_MASK (0x8U)
4160#define FTM_COMBINE_DECAP0_SHIFT (3U)
4161/*! DECAP0 - Dual Edge Capture Mode Captures For n = 0
4162 * 0b0..The dual edge captures are inactive.
4163 * 0b1..The dual edge captures are active.
4164 */
4165#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
4166#define FTM_COMBINE_DTEN0_MASK (0x10U)
4167#define FTM_COMBINE_DTEN0_SHIFT (4U)
4168/*! DTEN0 - Deadtime Enable For n = 0
4169 * 0b0..The deadtime insertion in this pair of channels is disabled.
4170 * 0b1..The deadtime insertion in this pair of channels is enabled.
4171 */
4172#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
4173#define FTM_COMBINE_SYNCEN0_MASK (0x20U)
4174#define FTM_COMBINE_SYNCEN0_SHIFT (5U)
4175/*! SYNCEN0 - Synchronization Enable For n = 0
4176 * 0b0..The PWM synchronization in this pair of channels is disabled.
4177 * 0b1..The PWM synchronization in this pair of channels is enabled.
4178 */
4179#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
4180#define FTM_COMBINE_FAULTEN0_MASK (0x40U)
4181#define FTM_COMBINE_FAULTEN0_SHIFT (6U)
4182/*! FAULTEN0 - Fault Control Enable For n = 0
4183 * 0b0..The fault control in this pair of channels is disabled.
4184 * 0b1..The fault control in this pair of channels is enabled.
4185 */
4186#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
4187#define FTM_COMBINE_COMBINE1_MASK (0x100U)
4188#define FTM_COMBINE_COMBINE1_SHIFT (8U)
4189/*! COMBINE1 - Combine Channels For n = 2
4190 * 0b0..Channels (n) and (n+1) are independent.
4191 * 0b1..Channels (n) and (n+1) are combined.
4192 */
4193#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
4194#define FTM_COMBINE_COMP1_MASK (0x200U)
4195#define FTM_COMBINE_COMP1_SHIFT (9U)
4196/*! COMP1 - Complement Of Channel (n) For n = 2
4197 * 0b0..The channel (n+1) output is the same as the channel (n) output.
4198 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
4199 */
4200#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
4201#define FTM_COMBINE_DECAPEN1_MASK (0x400U)
4202#define FTM_COMBINE_DECAPEN1_SHIFT (10U)
4203/*! DECAPEN1 - Dual Edge Capture Mode Enable For n = 2
4204 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
4205 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
4206 */
4207#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
4208#define FTM_COMBINE_DECAP1_MASK (0x800U)
4209#define FTM_COMBINE_DECAP1_SHIFT (11U)
4210/*! DECAP1 - Dual Edge Capture Mode Captures For n = 2
4211 * 0b0..The dual edge captures are inactive.
4212 * 0b1..The dual edge captures are active.
4213 */
4214#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
4215#define FTM_COMBINE_DTEN1_MASK (0x1000U)
4216#define FTM_COMBINE_DTEN1_SHIFT (12U)
4217/*! DTEN1 - Deadtime Enable For n = 2
4218 * 0b0..The deadtime insertion in this pair of channels is disabled.
4219 * 0b1..The deadtime insertion in this pair of channels is enabled.
4220 */
4221#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
4222#define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
4223#define FTM_COMBINE_SYNCEN1_SHIFT (13U)
4224/*! SYNCEN1 - Synchronization Enable For n = 2
4225 * 0b0..The PWM synchronization in this pair of channels is disabled.
4226 * 0b1..The PWM synchronization in this pair of channels is enabled.
4227 */
4228#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
4229#define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
4230#define FTM_COMBINE_FAULTEN1_SHIFT (14U)
4231/*! FAULTEN1 - Fault Control Enable For n = 2
4232 * 0b0..The fault control in this pair of channels is disabled.
4233 * 0b1..The fault control in this pair of channels is enabled.
4234 */
4235#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
4236#define FTM_COMBINE_COMBINE2_MASK (0x10000U)
4237#define FTM_COMBINE_COMBINE2_SHIFT (16U)
4238/*! COMBINE2 - Combine Channels For n = 4
4239 * 0b0..Channels (n) and (n+1) are independent.
4240 * 0b1..Channels (n) and (n+1) are combined.
4241 */
4242#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
4243#define FTM_COMBINE_COMP2_MASK (0x20000U)
4244#define FTM_COMBINE_COMP2_SHIFT (17U)
4245/*! COMP2 - Complement Of Channel (n) For n = 4
4246 * 0b0..The channel (n+1) output is the same as the channel (n) output.
4247 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
4248 */
4249#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
4250#define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
4251#define FTM_COMBINE_DECAPEN2_SHIFT (18U)
4252/*! DECAPEN2 - Dual Edge Capture Mode Enable For n = 4
4253 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
4254 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
4255 */
4256#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
4257#define FTM_COMBINE_DECAP2_MASK (0x80000U)
4258#define FTM_COMBINE_DECAP2_SHIFT (19U)
4259/*! DECAP2 - Dual Edge Capture Mode Captures For n = 4
4260 * 0b0..The dual edge captures are inactive.
4261 * 0b1..The dual edge captures are active.
4262 */
4263#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
4264#define FTM_COMBINE_DTEN2_MASK (0x100000U)
4265#define FTM_COMBINE_DTEN2_SHIFT (20U)
4266/*! DTEN2 - Deadtime Enable For n = 4
4267 * 0b0..The deadtime insertion in this pair of channels is disabled.
4268 * 0b1..The deadtime insertion in this pair of channels is enabled.
4269 */
4270#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
4271#define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
4272#define FTM_COMBINE_SYNCEN2_SHIFT (21U)
4273/*! SYNCEN2 - Synchronization Enable For n = 4
4274 * 0b0..The PWM synchronization in this pair of channels is disabled.
4275 * 0b1..The PWM synchronization in this pair of channels is enabled.
4276 */
4277#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
4278#define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
4279#define FTM_COMBINE_FAULTEN2_SHIFT (22U)
4280/*! FAULTEN2 - Fault Control Enable For n = 4
4281 * 0b0..The fault control in this pair of channels is disabled.
4282 * 0b1..The fault control in this pair of channels is enabled.
4283 */
4284#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
4285#define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
4286#define FTM_COMBINE_COMBINE3_SHIFT (24U)
4287/*! COMBINE3 - Combine Channels For n = 6
4288 * 0b0..Channels (n) and (n+1) are independent.
4289 * 0b1..Channels (n) and (n+1) are combined.
4290 */
4291#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
4292#define FTM_COMBINE_COMP3_MASK (0x2000000U)
4293#define FTM_COMBINE_COMP3_SHIFT (25U)
4294/*! COMP3 - Complement Of Channel (n) for n = 6
4295 * 0b0..The channel (n+1) output is the same as the channel (n) output.
4296 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
4297 */
4298#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
4299#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
4300#define FTM_COMBINE_DECAPEN3_SHIFT (26U)
4301/*! DECAPEN3 - Dual Edge Capture Mode Enable For n = 6
4302 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
4303 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
4304 */
4305#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
4306#define FTM_COMBINE_DECAP3_MASK (0x8000000U)
4307#define FTM_COMBINE_DECAP3_SHIFT (27U)
4308/*! DECAP3 - Dual Edge Capture Mode Captures For n = 6
4309 * 0b0..The dual edge captures are inactive.
4310 * 0b1..The dual edge captures are active.
4311 */
4312#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
4313#define FTM_COMBINE_DTEN3_MASK (0x10000000U)
4314#define FTM_COMBINE_DTEN3_SHIFT (28U)
4315/*! DTEN3 - Deadtime Enable For n = 6
4316 * 0b0..The deadtime insertion in this pair of channels is disabled.
4317 * 0b1..The deadtime insertion in this pair of channels is enabled.
4318 */
4319#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
4320#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
4321#define FTM_COMBINE_SYNCEN3_SHIFT (29U)
4322/*! SYNCEN3 - Synchronization Enable For n = 6
4323 * 0b0..The PWM synchronization in this pair of channels is disabled.
4324 * 0b1..The PWM synchronization in this pair of channels is enabled.
4325 */
4326#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
4327#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
4328#define FTM_COMBINE_FAULTEN3_SHIFT (30U)
4329/*! FAULTEN3 - Fault Control Enable For n = 6
4330 * 0b0..The fault control in this pair of channels is disabled.
4331 * 0b1..The fault control in this pair of channels is enabled.
4332 */
4333#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
4334/*! @} */
4335
4336/*! @name DEADTIME - Deadtime Insertion Control */
4337/*! @{ */
4338#define FTM_DEADTIME_DTVAL_MASK (0x3FU)
4339#define FTM_DEADTIME_DTVAL_SHIFT (0U)
4340#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
4341#define FTM_DEADTIME_DTPS_MASK (0xC0U)
4342#define FTM_DEADTIME_DTPS_SHIFT (6U)
4343/*! DTPS - Deadtime Prescaler Value
4344 * 0b0x..Divide the system clock by 1.
4345 * 0b10..Divide the system clock by 4.
4346 * 0b11..Divide the system clock by 16.
4347 */
4348#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
4349/*! @} */
4350
4351/*! @name EXTTRIG - FTM External Trigger */
4352/*! @{ */
4353#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
4354#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
4355/*! CH2TRIG - Channel 2 Trigger Enable
4356 * 0b0..The generation of the channel trigger is disabled.
4357 * 0b1..The generation of the channel trigger is enabled.
4358 */
4359#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
4360#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
4361#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
4362/*! CH3TRIG - Channel 3 Trigger Enable
4363 * 0b0..The generation of the channel trigger is disabled.
4364 * 0b1..The generation of the channel trigger is enabled.
4365 */
4366#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
4367#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
4368#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
4369/*! CH4TRIG - Channel 4 Trigger Enable
4370 * 0b0..The generation of the channel trigger is disabled.
4371 * 0b1..The generation of the channel trigger is enabled.
4372 */
4373#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
4374#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
4375#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
4376/*! CH5TRIG - Channel 5 Trigger Enable
4377 * 0b0..The generation of the channel trigger is disabled.
4378 * 0b1..The generation of the channel trigger is enabled.
4379 */
4380#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
4381#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
4382#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
4383/*! CH0TRIG - Channel 0 Trigger Enable
4384 * 0b0..The generation of the channel trigger is disabled.
4385 * 0b1..The generation of the channel trigger is enabled.
4386 */
4387#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
4388#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
4389#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
4390/*! CH1TRIG - Channel 1 Trigger Enable
4391 * 0b0..The generation of the channel trigger is disabled.
4392 * 0b1..The generation of the channel trigger is enabled.
4393 */
4394#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
4395#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
4396#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
4397/*! INITTRIGEN - Initialization Trigger Enable
4398 * 0b0..The generation of initialization trigger is disabled.
4399 * 0b1..The generation of initialization trigger is enabled.
4400 */
4401#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
4402#define FTM_EXTTRIG_TRIGF_MASK (0x80U)
4403#define FTM_EXTTRIG_TRIGF_SHIFT (7U)
4404/*! TRIGF - Channel Trigger Flag
4405 * 0b0..No channel trigger was generated.
4406 * 0b1..A channel trigger was generated.
4407 */
4408#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
4409/*! @} */
4410
4411/*! @name POL - Channels Polarity */
4412/*! @{ */
4413#define FTM_POL_POL0_MASK (0x1U)
4414#define FTM_POL_POL0_SHIFT (0U)
4415/*! POL0 - Channel 0 Polarity
4416 * 0b0..The channel polarity is active high.
4417 * 0b1..The channel polarity is active low.
4418 */
4419#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
4420#define FTM_POL_POL1_MASK (0x2U)
4421#define FTM_POL_POL1_SHIFT (1U)
4422/*! POL1 - Channel 1 Polarity
4423 * 0b0..The channel polarity is active high.
4424 * 0b1..The channel polarity is active low.
4425 */
4426#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
4427#define FTM_POL_POL2_MASK (0x4U)
4428#define FTM_POL_POL2_SHIFT (2U)
4429/*! POL2 - Channel 2 Polarity
4430 * 0b0..The channel polarity is active high.
4431 * 0b1..The channel polarity is active low.
4432 */
4433#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
4434#define FTM_POL_POL3_MASK (0x8U)
4435#define FTM_POL_POL3_SHIFT (3U)
4436/*! POL3 - Channel 3 Polarity
4437 * 0b0..The channel polarity is active high.
4438 * 0b1..The channel polarity is active low.
4439 */
4440#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
4441#define FTM_POL_POL4_MASK (0x10U)
4442#define FTM_POL_POL4_SHIFT (4U)
4443/*! POL4 - Channel 4 Polarity
4444 * 0b0..The channel polarity is active high.
4445 * 0b1..The channel polarity is active low.
4446 */
4447#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
4448#define FTM_POL_POL5_MASK (0x20U)
4449#define FTM_POL_POL5_SHIFT (5U)
4450/*! POL5 - Channel 5 Polarity
4451 * 0b0..The channel polarity is active high.
4452 * 0b1..The channel polarity is active low.
4453 */
4454#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
4455#define FTM_POL_POL6_MASK (0x40U)
4456#define FTM_POL_POL6_SHIFT (6U)
4457/*! POL6 - Channel 6 Polarity
4458 * 0b0..The channel polarity is active high.
4459 * 0b1..The channel polarity is active low.
4460 */
4461#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
4462#define FTM_POL_POL7_MASK (0x80U)
4463#define FTM_POL_POL7_SHIFT (7U)
4464/*! POL7 - Channel 7 Polarity
4465 * 0b0..The channel polarity is active high.
4466 * 0b1..The channel polarity is active low.
4467 */
4468#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
4469/*! @} */
4470
4471/*! @name FMS - Fault Mode Status */
4472/*! @{ */
4473#define FTM_FMS_FAULTF0_MASK (0x1U)
4474#define FTM_FMS_FAULTF0_SHIFT (0U)
4475/*! FAULTF0 - Fault Detection Flag 0
4476 * 0b0..No fault condition was detected at the fault input.
4477 * 0b1..A fault condition was detected at the fault input.
4478 */
4479#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
4480#define FTM_FMS_FAULTF1_MASK (0x2U)
4481#define FTM_FMS_FAULTF1_SHIFT (1U)
4482/*! FAULTF1 - Fault Detection Flag 1
4483 * 0b0..No fault condition was detected at the fault input.
4484 * 0b1..A fault condition was detected at the fault input.
4485 */
4486#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
4487#define FTM_FMS_FAULTF2_MASK (0x4U)
4488#define FTM_FMS_FAULTF2_SHIFT (2U)
4489/*! FAULTF2 - Fault Detection Flag 2
4490 * 0b0..No fault condition was detected at the fault input.
4491 * 0b1..A fault condition was detected at the fault input.
4492 */
4493#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
4494#define FTM_FMS_FAULTF3_MASK (0x8U)
4495#define FTM_FMS_FAULTF3_SHIFT (3U)
4496/*! FAULTF3 - Fault Detection Flag 3
4497 * 0b0..No fault condition was detected at the fault input.
4498 * 0b1..A fault condition was detected at the fault input.
4499 */
4500#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
4501#define FTM_FMS_FAULTIN_MASK (0x20U)
4502#define FTM_FMS_FAULTIN_SHIFT (5U)
4503/*! FAULTIN - Fault Inputs
4504 * 0b0..The logic OR of the enabled fault inputs is 0.
4505 * 0b1..The logic OR of the enabled fault inputs is 1.
4506 */
4507#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
4508#define FTM_FMS_WPEN_MASK (0x40U)
4509#define FTM_FMS_WPEN_SHIFT (6U)
4510/*! WPEN - Write Protection Enable
4511 * 0b0..Write protection is disabled. Write protected bits can be written.
4512 * 0b1..Write protection is enabled. Write protected bits cannot be written.
4513 */
4514#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
4515#define FTM_FMS_FAULTF_MASK (0x80U)
4516#define FTM_FMS_FAULTF_SHIFT (7U)
4517/*! FAULTF - Fault Detection Flag
4518 * 0b0..No fault condition was detected.
4519 * 0b1..A fault condition was detected.
4520 */
4521#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
4522/*! @} */
4523
4524/*! @name FILTER - Input Capture Filter Control */
4525/*! @{ */
4526#define FTM_FILTER_CH0FVAL_MASK (0xFU)
4527#define FTM_FILTER_CH0FVAL_SHIFT (0U)
4528#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
4529#define FTM_FILTER_CH1FVAL_MASK (0xF0U)
4530#define FTM_FILTER_CH1FVAL_SHIFT (4U)
4531#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
4532#define FTM_FILTER_CH2FVAL_MASK (0xF00U)
4533#define FTM_FILTER_CH2FVAL_SHIFT (8U)
4534#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
4535#define FTM_FILTER_CH3FVAL_MASK (0xF000U)
4536#define FTM_FILTER_CH3FVAL_SHIFT (12U)
4537#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
4538/*! @} */
4539
4540/*! @name FLTCTRL - Fault Control */
4541/*! @{ */
4542#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
4543#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
4544/*! FAULT0EN - Fault Input 0 Enable
4545 * 0b0..Fault input is disabled.
4546 * 0b1..Fault input is enabled.
4547 */
4548#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
4549#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
4550#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
4551/*! FAULT1EN - Fault Input 1 Enable
4552 * 0b0..Fault input is disabled.
4553 * 0b1..Fault input is enabled.
4554 */
4555#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
4556#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
4557#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
4558/*! FAULT2EN - Fault Input 2 Enable
4559 * 0b0..Fault input is disabled.
4560 * 0b1..Fault input is enabled.
4561 */
4562#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
4563#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
4564#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
4565/*! FAULT3EN - Fault Input 3 Enable
4566 * 0b0..Fault input is disabled.
4567 * 0b1..Fault input is enabled.
4568 */
4569#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
4570#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
4571#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
4572/*! FFLTR0EN - Fault Input 0 Filter Enable
4573 * 0b0..Fault input filter is disabled.
4574 * 0b1..Fault input filter is enabled.
4575 */
4576#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
4577#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
4578#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
4579/*! FFLTR1EN - Fault Input 1 Filter Enable
4580 * 0b0..Fault input filter is disabled.
4581 * 0b1..Fault input filter is enabled.
4582 */
4583#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
4584#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
4585#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
4586/*! FFLTR2EN - Fault Input 2 Filter Enable
4587 * 0b0..Fault input filter is disabled.
4588 * 0b1..Fault input filter is enabled.
4589 */
4590#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
4591#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
4592#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
4593/*! FFLTR3EN - Fault Input 3 Filter Enable
4594 * 0b0..Fault input filter is disabled.
4595 * 0b1..Fault input filter is enabled.
4596 */
4597#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
4598#define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
4599#define FTM_FLTCTRL_FFVAL_SHIFT (8U)
4600#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
4601/*! @} */
4602
4603/*! @name QDCTRL - Quadrature Decoder Control And Status */
4604/*! @{ */
4605#define FTM_QDCTRL_QUADEN_MASK (0x1U)
4606#define FTM_QDCTRL_QUADEN_SHIFT (0U)
4607/*! QUADEN - Quadrature Decoder Mode Enable
4608 * 0b0..Quadrature Decoder mode is disabled.
4609 * 0b1..Quadrature Decoder mode is enabled.
4610 */
4611#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
4612#define FTM_QDCTRL_TOFDIR_MASK (0x2U)
4613#define FTM_QDCTRL_TOFDIR_SHIFT (1U)
4614/*! TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode
4615 * 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).
4616 * 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).
4617 */
4618#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
4619#define FTM_QDCTRL_QUADIR_MASK (0x4U)
4620#define FTM_QDCTRL_QUADIR_SHIFT (2U)
4621/*! QUADIR - FTM Counter Direction In Quadrature Decoder Mode
4622 * 0b0..Counting direction is decreasing (FTM counter decrement).
4623 * 0b1..Counting direction is increasing (FTM counter increment).
4624 */
4625#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
4626#define FTM_QDCTRL_QUADMODE_MASK (0x8U)
4627#define FTM_QDCTRL_QUADMODE_SHIFT (3U)
4628/*! QUADMODE - Quadrature Decoder Mode
4629 * 0b0..Phase A and phase B encoding mode.
4630 * 0b1..Count and direction encoding mode.
4631 */
4632#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
4633#define FTM_QDCTRL_PHBPOL_MASK (0x10U)
4634#define FTM_QDCTRL_PHBPOL_SHIFT (4U)
4635/*! PHBPOL - Phase B Input Polarity
4636 * 0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.
4637 * 0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.
4638 */
4639#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
4640#define FTM_QDCTRL_PHAPOL_MASK (0x20U)
4641#define FTM_QDCTRL_PHAPOL_SHIFT (5U)
4642/*! PHAPOL - Phase A Input Polarity
4643 * 0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.
4644 * 0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.
4645 */
4646#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
4647#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
4648#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
4649/*! PHBFLTREN - Phase B Input Filter Enable
4650 * 0b0..Phase B input filter is disabled.
4651 * 0b1..Phase B input filter is enabled.
4652 */
4653#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
4654#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
4655#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
4656/*! PHAFLTREN - Phase A Input Filter Enable
4657 * 0b0..Phase A input filter is disabled.
4658 * 0b1..Phase A input filter is enabled.
4659 */
4660#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
4661/*! @} */
4662
4663/*! @name CONF - Configuration */
4664/*! @{ */
4665#define FTM_CONF_NUMTOF_MASK (0x1FU)
4666#define FTM_CONF_NUMTOF_SHIFT (0U)
4667#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
4668#define FTM_CONF_BDMMODE_MASK (0xC0U)
4669#define FTM_CONF_BDMMODE_SHIFT (6U)
4670#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
4671#define FTM_CONF_GTBEEN_MASK (0x200U)
4672#define FTM_CONF_GTBEEN_SHIFT (9U)
4673/*! GTBEEN - Global Time Base Enable
4674 * 0b0..Use of an external global time base is disabled.
4675 * 0b1..Use of an external global time base is enabled.
4676 */
4677#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
4678#define FTM_CONF_GTBEOUT_MASK (0x400U)
4679#define FTM_CONF_GTBEOUT_SHIFT (10U)
4680/*! GTBEOUT - Global Time Base Output
4681 * 0b0..A global time base signal generation is disabled.
4682 * 0b1..A global time base signal generation is enabled.
4683 */
4684#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
4685/*! @} */
4686
4687/*! @name FLTPOL - FTM Fault Input Polarity */
4688/*! @{ */
4689#define FTM_FLTPOL_FLT0POL_MASK (0x1U)
4690#define FTM_FLTPOL_FLT0POL_SHIFT (0U)
4691/*! FLT0POL - Fault Input 0 Polarity
4692 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
4693 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
4694 */
4695#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
4696#define FTM_FLTPOL_FLT1POL_MASK (0x2U)
4697#define FTM_FLTPOL_FLT1POL_SHIFT (1U)
4698/*! FLT1POL - Fault Input 1 Polarity
4699 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
4700 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
4701 */
4702#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
4703#define FTM_FLTPOL_FLT2POL_MASK (0x4U)
4704#define FTM_FLTPOL_FLT2POL_SHIFT (2U)
4705/*! FLT2POL - Fault Input 2 Polarity
4706 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
4707 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
4708 */
4709#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
4710#define FTM_FLTPOL_FLT3POL_MASK (0x8U)
4711#define FTM_FLTPOL_FLT3POL_SHIFT (3U)
4712/*! FLT3POL - Fault Input 3 Polarity
4713 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
4714 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
4715 */
4716#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
4717/*! @} */
4718
4719/*! @name SYNCONF - Synchronization Configuration */
4720/*! @{ */
4721#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
4722#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
4723/*! HWTRIGMODE - Hardware Trigger Mode
4724 * 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
4725 * 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
4726 */
4727#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
4728#define FTM_SYNCONF_CNTINC_MASK (0x4U)
4729#define FTM_SYNCONF_CNTINC_SHIFT (2U)
4730/*! CNTINC - CNTIN Register Synchronization
4731 * 0b0..CNTIN register is updated with its buffer value at all rising edges of system clock.
4732 * 0b1..CNTIN register is updated with its buffer value by the PWM synchronization.
4733 */
4734#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
4735#define FTM_SYNCONF_INVC_MASK (0x10U)
4736#define FTM_SYNCONF_INVC_SHIFT (4U)
4737/*! INVC - INVCTRL Register Synchronization
4738 * 0b0..INVCTRL register is updated with its buffer value at all rising edges of system clock.
4739 * 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization.
4740 */
4741#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
4742#define FTM_SYNCONF_SWOC_MASK (0x20U)
4743#define FTM_SYNCONF_SWOC_SHIFT (5U)
4744/*! SWOC - SWOCTRL Register Synchronization
4745 * 0b0..SWOCTRL register is updated with its buffer value at all rising edges of system clock.
4746 * 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization.
4747 */
4748#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
4749#define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
4750#define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
4751/*! SYNCMODE - Synchronization Mode
4752 * 0b0..Legacy PWM synchronization is selected.
4753 * 0b1..Enhanced PWM synchronization is selected.
4754 */
4755#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
4756#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
4757#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
4758/*! SWRSTCNT
4759 * 0b0..The software trigger does not activate the FTM counter synchronization.
4760 * 0b1..The software trigger activates the FTM counter synchronization.
4761 */
4762#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
4763#define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
4764#define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
4765/*! SWWRBUF
4766 * 0b0..The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
4767 * 0b1..The software trigger activates MOD, CNTIN, and CV registers synchronization.
4768 */
4769#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
4770#define FTM_SYNCONF_SWOM_MASK (0x400U)
4771#define FTM_SYNCONF_SWOM_SHIFT (10U)
4772/*! SWOM
4773 * 0b0..The software trigger does not activate the OUTMASK register synchronization.
4774 * 0b1..The software trigger activates the OUTMASK register synchronization.
4775 */
4776#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
4777#define FTM_SYNCONF_SWINVC_MASK (0x800U)
4778#define FTM_SYNCONF_SWINVC_SHIFT (11U)
4779/*! SWINVC
4780 * 0b0..The software trigger does not activate the INVCTRL register synchronization.
4781 * 0b1..The software trigger activates the INVCTRL register synchronization.
4782 */
4783#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
4784#define FTM_SYNCONF_SWSOC_MASK (0x1000U)
4785#define FTM_SYNCONF_SWSOC_SHIFT (12U)
4786/*! SWSOC
4787 * 0b0..The software trigger does not activate the SWOCTRL register synchronization.
4788 * 0b1..The software trigger activates the SWOCTRL register synchronization.
4789 */
4790#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
4791#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
4792#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
4793/*! HWRSTCNT
4794 * 0b0..A hardware trigger does not activate the FTM counter synchronization.
4795 * 0b1..A hardware trigger activates the FTM counter synchronization.
4796 */
4797#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
4798#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
4799#define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
4800/*! HWWRBUF
4801 * 0b0..A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
4802 * 0b1..A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
4803 */
4804#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
4805#define FTM_SYNCONF_HWOM_MASK (0x40000U)
4806#define FTM_SYNCONF_HWOM_SHIFT (18U)
4807/*! HWOM
4808 * 0b0..A hardware trigger does not activate the OUTMASK register synchronization.
4809 * 0b1..A hardware trigger activates the OUTMASK register synchronization.
4810 */
4811#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
4812#define FTM_SYNCONF_HWINVC_MASK (0x80000U)
4813#define FTM_SYNCONF_HWINVC_SHIFT (19U)
4814/*! HWINVC
4815 * 0b0..A hardware trigger does not activate the INVCTRL register synchronization.
4816 * 0b1..A hardware trigger activates the INVCTRL register synchronization.
4817 */
4818#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
4819#define FTM_SYNCONF_HWSOC_MASK (0x100000U)
4820#define FTM_SYNCONF_HWSOC_SHIFT (20U)
4821/*! HWSOC
4822 * 0b0..A hardware trigger does not activate the SWOCTRL register synchronization.
4823 * 0b1..A hardware trigger activates the SWOCTRL register synchronization.
4824 */
4825#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
4826/*! @} */
4827
4828/*! @name INVCTRL - FTM Inverting Control */
4829/*! @{ */
4830#define FTM_INVCTRL_INV0EN_MASK (0x1U)
4831#define FTM_INVCTRL_INV0EN_SHIFT (0U)
4832/*! INV0EN - Pair Channels 0 Inverting Enable
4833 * 0b0..Inverting is disabled.
4834 * 0b1..Inverting is enabled.
4835 */
4836#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
4837#define FTM_INVCTRL_INV1EN_MASK (0x2U)
4838#define FTM_INVCTRL_INV1EN_SHIFT (1U)
4839/*! INV1EN - Pair Channels 1 Inverting Enable
4840 * 0b0..Inverting is disabled.
4841 * 0b1..Inverting is enabled.
4842 */
4843#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
4844#define FTM_INVCTRL_INV2EN_MASK (0x4U)
4845#define FTM_INVCTRL_INV2EN_SHIFT (2U)
4846/*! INV2EN - Pair Channels 2 Inverting Enable
4847 * 0b0..Inverting is disabled.
4848 * 0b1..Inverting is enabled.
4849 */
4850#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
4851#define FTM_INVCTRL_INV3EN_MASK (0x8U)
4852#define FTM_INVCTRL_INV3EN_SHIFT (3U)
4853/*! INV3EN - Pair Channels 3 Inverting Enable
4854 * 0b0..Inverting is disabled.
4855 * 0b1..Inverting is enabled.
4856 */
4857#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
4858/*! @} */
4859
4860/*! @name SWOCTRL - FTM Software Output Control */
4861/*! @{ */
4862#define FTM_SWOCTRL_CH0OC_MASK (0x1U)
4863#define FTM_SWOCTRL_CH0OC_SHIFT (0U)
4864/*! CH0OC - Channel 0 Software Output Control Enable
4865 * 0b0..The channel output is not affected by software output control.
4866 * 0b1..The channel output is affected by software output control.
4867 */
4868#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
4869#define FTM_SWOCTRL_CH1OC_MASK (0x2U)
4870#define FTM_SWOCTRL_CH1OC_SHIFT (1U)
4871/*! CH1OC - Channel 1 Software Output Control Enable
4872 * 0b0..The channel output is not affected by software output control.
4873 * 0b1..The channel output is affected by software output control.
4874 */
4875#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
4876#define FTM_SWOCTRL_CH2OC_MASK (0x4U)
4877#define FTM_SWOCTRL_CH2OC_SHIFT (2U)
4878/*! CH2OC - Channel 2 Software Output Control Enable
4879 * 0b0..The channel output is not affected by software output control.
4880 * 0b1..The channel output is affected by software output control.
4881 */
4882#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
4883#define FTM_SWOCTRL_CH3OC_MASK (0x8U)
4884#define FTM_SWOCTRL_CH3OC_SHIFT (3U)
4885/*! CH3OC - Channel 3 Software Output Control Enable
4886 * 0b0..The channel output is not affected by software output control.
4887 * 0b1..The channel output is affected by software output control.
4888 */
4889#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
4890#define FTM_SWOCTRL_CH4OC_MASK (0x10U)
4891#define FTM_SWOCTRL_CH4OC_SHIFT (4U)
4892/*! CH4OC - Channel 4 Software Output Control Enable
4893 * 0b0..The channel output is not affected by software output control.
4894 * 0b1..The channel output is affected by software output control.
4895 */
4896#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
4897#define FTM_SWOCTRL_CH5OC_MASK (0x20U)
4898#define FTM_SWOCTRL_CH5OC_SHIFT (5U)
4899/*! CH5OC - Channel 5 Software Output Control Enable
4900 * 0b0..The channel output is not affected by software output control.
4901 * 0b1..The channel output is affected by software output control.
4902 */
4903#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
4904#define FTM_SWOCTRL_CH6OC_MASK (0x40U)
4905#define FTM_SWOCTRL_CH6OC_SHIFT (6U)
4906/*! CH6OC - Channel 6 Software Output Control Enable
4907 * 0b0..The channel output is not affected by software output control.
4908 * 0b1..The channel output is affected by software output control.
4909 */
4910#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
4911#define FTM_SWOCTRL_CH7OC_MASK (0x80U)
4912#define FTM_SWOCTRL_CH7OC_SHIFT (7U)
4913/*! CH7OC - Channel 7 Software Output Control Enable
4914 * 0b0..The channel output is not affected by software output control.
4915 * 0b1..The channel output is affected by software output control.
4916 */
4917#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
4918#define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
4919#define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
4920/*! CH0OCV - Channel 0 Software Output Control Value
4921 * 0b0..The software output control forces 0 to the channel output.
4922 * 0b1..The software output control forces 1 to the channel output.
4923 */
4924#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
4925#define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
4926#define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
4927/*! CH1OCV - Channel 1 Software Output Control Value
4928 * 0b0..The software output control forces 0 to the channel output.
4929 * 0b1..The software output control forces 1 to the channel output.
4930 */
4931#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
4932#define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
4933#define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
4934/*! CH2OCV - Channel 2 Software Output Control Value
4935 * 0b0..The software output control forces 0 to the channel output.
4936 * 0b1..The software output control forces 1 to the channel output.
4937 */
4938#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
4939#define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
4940#define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
4941/*! CH3OCV - Channel 3 Software Output Control Value
4942 * 0b0..The software output control forces 0 to the channel output.
4943 * 0b1..The software output control forces 1 to the channel output.
4944 */
4945#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
4946#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
4947#define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
4948/*! CH4OCV - Channel 4 Software Output Control Value
4949 * 0b0..The software output control forces 0 to the channel output.
4950 * 0b1..The software output control forces 1 to the channel output.
4951 */
4952#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
4953#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
4954#define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
4955/*! CH5OCV - Channel 5 Software Output Control Value
4956 * 0b0..The software output control forces 0 to the channel output.
4957 * 0b1..The software output control forces 1 to the channel output.
4958 */
4959#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
4960#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
4961#define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
4962/*! CH6OCV - Channel 6 Software Output Control Value
4963 * 0b0..The software output control forces 0 to the channel output.
4964 * 0b1..The software output control forces 1 to the channel output.
4965 */
4966#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
4967#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
4968#define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
4969/*! CH7OCV - Channel 7 Software Output Control Value
4970 * 0b0..The software output control forces 0 to the channel output.
4971 * 0b1..The software output control forces 1 to the channel output.
4972 */
4973#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
4974/*! @} */
4975
4976/*! @name PWMLOAD - FTM PWM Load */
4977/*! @{ */
4978#define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
4979#define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
4980/*! CH0SEL - Channel 0 Select
4981 * 0b0..Do not include the channel in the matching process.
4982 * 0b1..Include the channel in the matching process.
4983 */
4984#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
4985#define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
4986#define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
4987/*! CH1SEL - Channel 1 Select
4988 * 0b0..Do not include the channel in the matching process.
4989 * 0b1..Include the channel in the matching process.
4990 */
4991#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
4992#define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
4993#define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
4994/*! CH2SEL - Channel 2 Select
4995 * 0b0..Do not include the channel in the matching process.
4996 * 0b1..Include the channel in the matching process.
4997 */
4998#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
4999#define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
5000#define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
5001/*! CH3SEL - Channel 3 Select
5002 * 0b0..Do not include the channel in the matching process.
5003 * 0b1..Include the channel in the matching process.
5004 */
5005#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
5006#define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
5007#define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
5008/*! CH4SEL - Channel 4 Select
5009 * 0b0..Do not include the channel in the matching process.
5010 * 0b1..Include the channel in the matching process.
5011 */
5012#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
5013#define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
5014#define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
5015/*! CH5SEL - Channel 5 Select
5016 * 0b0..Do not include the channel in the matching process.
5017 * 0b1..Include the channel in the matching process.
5018 */
5019#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
5020#define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
5021#define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
5022/*! CH6SEL - Channel 6 Select
5023 * 0b0..Do not include the channel in the matching process.
5024 * 0b1..Include the channel in the matching process.
5025 */
5026#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
5027#define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
5028#define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
5029/*! CH7SEL - Channel 7 Select
5030 * 0b0..Do not include the channel in the matching process.
5031 * 0b1..Include the channel in the matching process.
5032 */
5033#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
5034#define FTM_PWMLOAD_LDOK_MASK (0x200U)
5035#define FTM_PWMLOAD_LDOK_SHIFT (9U)
5036/*! LDOK - Load Enable
5037 * 0b0..Loading updated values is disabled.
5038 * 0b1..Loading updated values is enabled.
5039 */
5040#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
5041/*! @} */
5042
5043
5044/*!
5045 * @}
5046 */ /* end of group FTM_Register_Masks */
5047
5048
5049/* FTM - Peripheral instance base addresses */
5050/** Peripheral FTM0 base address */
5051#define FTM0_BASE (0x40038000u)
5052/** Peripheral FTM0 base pointer */
5053#define FTM0 ((FTM_Type *)FTM0_BASE)
5054/** Peripheral FTM1 base address */
5055#define FTM1_BASE (0x40039000u)
5056/** Peripheral FTM1 base pointer */
5057#define FTM1 ((FTM_Type *)FTM1_BASE)
5058/** Peripheral FTM2 base address */
5059#define FTM2_BASE (0x4003A000u)
5060/** Peripheral FTM2 base pointer */
5061#define FTM2 ((FTM_Type *)FTM2_BASE)
5062/** Array initializer of FTM peripheral base addresses */
5063#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE }
5064/** Array initializer of FTM peripheral base pointers */
5065#define FTM_BASE_PTRS { FTM0, FTM1, FTM2 }
5066/** Interrupt vectors for the FTM peripheral type */
5067#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn }
5068
5069/*!
5070 * @}
5071 */ /* end of group FTM_Peripheral_Access_Layer */
5072
5073
5074/* ----------------------------------------------------------------------------
5075 -- GPIO Peripheral Access Layer
5076 ---------------------------------------------------------------------------- */
5077
5078/*!
5079 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
5080 * @{
5081 */
5082
5083/** GPIO - Register Layout Typedef */
5084typedef struct {
5085 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
5086 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
5087 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
5088 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
5089 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
5090 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
5091} GPIO_Type;
5092
5093/* ----------------------------------------------------------------------------
5094 -- GPIO Register Masks
5095 ---------------------------------------------------------------------------- */
5096
5097/*!
5098 * @addtogroup GPIO_Register_Masks GPIO Register Masks
5099 * @{
5100 */
5101
5102/*! @name PDOR - Port Data Output Register */
5103/*! @{ */
5104#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
5105#define GPIO_PDOR_PDO_SHIFT (0U)
5106/*! PDO - Port Data Output
5107 * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
5108 * 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
5109 */
5110#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
5111/*! @} */
5112
5113/*! @name PSOR - Port Set Output Register */
5114/*! @{ */
5115#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
5116#define GPIO_PSOR_PTSO_SHIFT (0U)
5117/*! PTSO - Port Set Output
5118 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
5119 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1.
5120 */
5121#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
5122/*! @} */
5123
5124/*! @name PCOR - Port Clear Output Register */
5125/*! @{ */
5126#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
5127#define GPIO_PCOR_PTCO_SHIFT (0U)
5128/*! PTCO - Port Clear Output
5129 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
5130 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0.
5131 */
5132#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
5133/*! @} */
5134
5135/*! @name PTOR - Port Toggle Output Register */
5136/*! @{ */
5137#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
5138#define GPIO_PTOR_PTTO_SHIFT (0U)
5139/*! PTTO - Port Toggle Output
5140 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
5141 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state.
5142 */
5143#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
5144/*! @} */
5145
5146/*! @name PDIR - Port Data Input Register */
5147/*! @{ */
5148#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
5149#define GPIO_PDIR_PDI_SHIFT (0U)
5150/*! PDI - Port Data Input
5151 * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function.
5152 * 0b00000000000000000000000000000001..Pin logic level is logic 1.
5153 */
5154#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
5155/*! @} */
5156
5157/*! @name PDDR - Port Data Direction Register */
5158/*! @{ */
5159#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
5160#define GPIO_PDDR_PDD_SHIFT (0U)
5161/*! PDD - Port Data Direction
5162 * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function.
5163 * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function.
5164 */
5165#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
5166/*! @} */
5167
5168
5169/*!
5170 * @}
5171 */ /* end of group GPIO_Register_Masks */
5172
5173
5174/* GPIO - Peripheral instance base addresses */
5175/** Peripheral GPIOA base address */
5176#define GPIOA_BASE (0x400FF000u)
5177/** Peripheral GPIOA base pointer */
5178#define GPIOA ((GPIO_Type *)GPIOA_BASE)
5179/** Peripheral GPIOB base address */
5180#define GPIOB_BASE (0x400FF040u)
5181/** Peripheral GPIOB base pointer */
5182#define GPIOB ((GPIO_Type *)GPIOB_BASE)
5183/** Peripheral GPIOC base address */
5184#define GPIOC_BASE (0x400FF080u)
5185/** Peripheral GPIOC base pointer */
5186#define GPIOC ((GPIO_Type *)GPIOC_BASE)
5187/** Peripheral GPIOD base address */
5188#define GPIOD_BASE (0x400FF0C0u)
5189/** Peripheral GPIOD base pointer */
5190#define GPIOD ((GPIO_Type *)GPIOD_BASE)
5191/** Peripheral GPIOE base address */
5192#define GPIOE_BASE (0x400FF100u)
5193/** Peripheral GPIOE base pointer */
5194#define GPIOE ((GPIO_Type *)GPIOE_BASE)
5195/** Array initializer of GPIO peripheral base addresses */
5196#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
5197/** Array initializer of GPIO peripheral base pointers */
5198#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
5199
5200/*!
5201 * @}
5202 */ /* end of group GPIO_Peripheral_Access_Layer */
5203
5204
5205/* ----------------------------------------------------------------------------
5206 -- I2C Peripheral Access Layer
5207 ---------------------------------------------------------------------------- */
5208
5209/*!
5210 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
5211 * @{
5212 */
5213
5214/** I2C - Register Layout Typedef */
5215typedef struct {
5216 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
5217 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
5218 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
5219 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
5220 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
5221 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
5222 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
5223 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
5224 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
5225 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
5226 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
5227 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
5228} I2C_Type;
5229
5230/* ----------------------------------------------------------------------------
5231 -- I2C Register Masks
5232 ---------------------------------------------------------------------------- */
5233
5234/*!
5235 * @addtogroup I2C_Register_Masks I2C Register Masks
5236 * @{
5237 */
5238
5239/*! @name A1 - I2C Address Register 1 */
5240/*! @{ */
5241#define I2C_A1_AD_MASK (0xFEU)
5242#define I2C_A1_AD_SHIFT (1U)
5243#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
5244/*! @} */
5245
5246/*! @name F - I2C Frequency Divider register */
5247/*! @{ */
5248#define I2C_F_ICR_MASK (0x3FU)
5249#define I2C_F_ICR_SHIFT (0U)
5250#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
5251#define I2C_F_MULT_MASK (0xC0U)
5252#define I2C_F_MULT_SHIFT (6U)
5253/*! MULT - Multiplier Factor
5254 * 0b00..mul = 1
5255 * 0b01..mul = 2
5256 * 0b10..mul = 4
5257 * 0b11..Reserved
5258 */
5259#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
5260/*! @} */
5261
5262/*! @name C1 - I2C Control Register 1 */
5263/*! @{ */
5264#define I2C_C1_DMAEN_MASK (0x1U)
5265#define I2C_C1_DMAEN_SHIFT (0U)
5266/*! DMAEN - DMA Enable
5267 * 0b0..All DMA signalling disabled.
5268 * 0b1..DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.
5269 */
5270#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
5271#define I2C_C1_WUEN_MASK (0x2U)
5272#define I2C_C1_WUEN_SHIFT (1U)
5273/*! WUEN - Wakeup Enable
5274 * 0b0..Normal operation. No interrupt generated when address matching in low power mode.
5275 * 0b1..Enables the wakeup function in low power mode.
5276 */
5277#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
5278#define I2C_C1_RSTA_MASK (0x4U)
5279#define I2C_C1_RSTA_SHIFT (2U)
5280#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
5281#define I2C_C1_TXAK_MASK (0x8U)
5282#define I2C_C1_TXAK_SHIFT (3U)
5283/*! TXAK - Transmit Acknowledge Enable
5284 * 0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
5285 * 0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
5286 */
5287#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
5288#define I2C_C1_TX_MASK (0x10U)
5289#define I2C_C1_TX_SHIFT (4U)
5290/*! TX - Transmit Mode Select
5291 * 0b0..Receive
5292 * 0b1..Transmit
5293 */
5294#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
5295#define I2C_C1_MST_MASK (0x20U)
5296#define I2C_C1_MST_SHIFT (5U)
5297/*! MST - Master Mode Select
5298 * 0b0..Slave mode
5299 * 0b1..Master mode
5300 */
5301#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
5302#define I2C_C1_IICIE_MASK (0x40U)
5303#define I2C_C1_IICIE_SHIFT (6U)
5304/*! IICIE - I2C Interrupt Enable
5305 * 0b0..Disabled
5306 * 0b1..Enabled
5307 */
5308#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
5309#define I2C_C1_IICEN_MASK (0x80U)
5310#define I2C_C1_IICEN_SHIFT (7U)
5311/*! IICEN - I2C Enable
5312 * 0b0..Disabled
5313 * 0b1..Enabled
5314 */
5315#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
5316/*! @} */
5317
5318/*! @name S - I2C Status register */
5319/*! @{ */
5320#define I2C_S_RXAK_MASK (0x1U)
5321#define I2C_S_RXAK_SHIFT (0U)
5322/*! RXAK - Receive Acknowledge
5323 * 0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus
5324 * 0b1..No acknowledge signal detected
5325 */
5326#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
5327#define I2C_S_IICIF_MASK (0x2U)
5328#define I2C_S_IICIF_SHIFT (1U)
5329/*! IICIF - Interrupt Flag
5330 * 0b0..No interrupt pending
5331 * 0b1..Interrupt pending
5332 */
5333#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
5334#define I2C_S_SRW_MASK (0x4U)
5335#define I2C_S_SRW_SHIFT (2U)
5336/*! SRW - Slave Read/Write
5337 * 0b0..Slave receive, master writing to slave
5338 * 0b1..Slave transmit, master reading from slave
5339 */
5340#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
5341#define I2C_S_RAM_MASK (0x8U)
5342#define I2C_S_RAM_SHIFT (3U)
5343/*! RAM - Range Address Match
5344 * 0b0..Not addressed
5345 * 0b1..Addressed as a slave
5346 */
5347#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
5348#define I2C_S_ARBL_MASK (0x10U)
5349#define I2C_S_ARBL_SHIFT (4U)
5350/*! ARBL - Arbitration Lost
5351 * 0b0..Standard bus operation.
5352 * 0b1..Loss of arbitration.
5353 */
5354#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
5355#define I2C_S_BUSY_MASK (0x20U)
5356#define I2C_S_BUSY_SHIFT (5U)
5357/*! BUSY - Bus Busy
5358 * 0b0..Bus is idle
5359 * 0b1..Bus is busy
5360 */
5361#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
5362#define I2C_S_IAAS_MASK (0x40U)
5363#define I2C_S_IAAS_SHIFT (6U)
5364/*! IAAS - Addressed As A Slave
5365 * 0b0..Not addressed
5366 * 0b1..Addressed as a slave
5367 */
5368#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
5369#define I2C_S_TCF_MASK (0x80U)
5370#define I2C_S_TCF_SHIFT (7U)
5371/*! TCF - Transfer Complete Flag
5372 * 0b0..Transfer in progress
5373 * 0b1..Transfer complete
5374 */
5375#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
5376/*! @} */
5377
5378/*! @name D - I2C Data I/O register */
5379/*! @{ */
5380#define I2C_D_DATA_MASK (0xFFU)
5381#define I2C_D_DATA_SHIFT (0U)
5382#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
5383/*! @} */
5384
5385/*! @name C2 - I2C Control Register 2 */
5386/*! @{ */
5387#define I2C_C2_AD_MASK (0x7U)
5388#define I2C_C2_AD_SHIFT (0U)
5389#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
5390#define I2C_C2_RMEN_MASK (0x8U)
5391#define I2C_C2_RMEN_SHIFT (3U)
5392/*! RMEN - Range Address Matching Enable
5393 * 0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.
5394 * 0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
5395 */
5396#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
5397#define I2C_C2_SBRC_MASK (0x10U)
5398#define I2C_C2_SBRC_SHIFT (4U)
5399/*! SBRC - Slave Baud Rate Control
5400 * 0b0..The slave baud rate follows the master baud rate and clock stretching may occur
5401 * 0b1..Slave baud rate is independent of the master baud rate
5402 */
5403#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
5404#define I2C_C2_HDRS_MASK (0x20U)
5405#define I2C_C2_HDRS_SHIFT (5U)
5406/*! HDRS - High Drive Select
5407 * 0b0..Normal drive mode
5408 * 0b1..High drive mode
5409 */
5410#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
5411#define I2C_C2_ADEXT_MASK (0x40U)
5412#define I2C_C2_ADEXT_SHIFT (6U)
5413/*! ADEXT - Address Extension
5414 * 0b0..7-bit address scheme
5415 * 0b1..10-bit address scheme
5416 */
5417#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
5418#define I2C_C2_GCAEN_MASK (0x80U)
5419#define I2C_C2_GCAEN_SHIFT (7U)
5420/*! GCAEN - General Call Address Enable
5421 * 0b0..Disabled
5422 * 0b1..Enabled
5423 */
5424#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
5425/*! @} */
5426
5427/*! @name FLT - I2C Programmable Input Glitch Filter register */
5428/*! @{ */
5429#define I2C_FLT_FLT_MASK (0xFU)
5430#define I2C_FLT_FLT_SHIFT (0U)
5431/*! FLT - I2C Programmable Filter Factor
5432 * 0b0000..No filter/bypass
5433 */
5434#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
5435#define I2C_FLT_STARTF_MASK (0x10U)
5436#define I2C_FLT_STARTF_SHIFT (4U)
5437/*! STARTF - I2C Bus Start Detect Flag
5438 * 0b0..No start happens on I2C bus
5439 * 0b1..Start detected on I2C bus
5440 */
5441#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
5442#define I2C_FLT_SSIE_MASK (0x20U)
5443#define I2C_FLT_SSIE_SHIFT (5U)
5444/*! SSIE - I2C Bus Stop or Start Interrupt Enable
5445 * 0b0..Stop or start detection interrupt is disabled
5446 * 0b1..Stop or start detection interrupt is enabled
5447 */
5448#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
5449#define I2C_FLT_STOPF_MASK (0x40U)
5450#define I2C_FLT_STOPF_SHIFT (6U)
5451/*! STOPF - I2C Bus Stop Detect Flag
5452 * 0b0..No stop happens on I2C bus
5453 * 0b1..Stop detected on I2C bus
5454 */
5455#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
5456#define I2C_FLT_SHEN_MASK (0x80U)
5457#define I2C_FLT_SHEN_SHIFT (7U)
5458/*! SHEN - Stop Hold Enable
5459 * 0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
5460 * 0b1..Stop holdoff is enabled.
5461 */
5462#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
5463/*! @} */
5464
5465/*! @name RA - I2C Range Address register */
5466/*! @{ */
5467#define I2C_RA_RAD_MASK (0xFEU)
5468#define I2C_RA_RAD_SHIFT (1U)
5469#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
5470/*! @} */
5471
5472/*! @name SMB - I2C SMBus Control and Status register */
5473/*! @{ */
5474#define I2C_SMB_SHTF2IE_MASK (0x1U)
5475#define I2C_SMB_SHTF2IE_SHIFT (0U)
5476/*! SHTF2IE - SHTF2 Interrupt Enable
5477 * 0b0..SHTF2 interrupt is disabled
5478 * 0b1..SHTF2 interrupt is enabled
5479 */
5480#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
5481#define I2C_SMB_SHTF2_MASK (0x2U)
5482#define I2C_SMB_SHTF2_SHIFT (1U)
5483/*! SHTF2 - SCL High Timeout Flag 2
5484 * 0b0..No SCL high and SDA low timeout occurs
5485 * 0b1..SCL high and SDA low timeout occurs
5486 */
5487#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
5488#define I2C_SMB_SHTF1_MASK (0x4U)
5489#define I2C_SMB_SHTF1_SHIFT (2U)
5490/*! SHTF1 - SCL High Timeout Flag 1
5491 * 0b0..No SCL high and SDA high timeout occurs
5492 * 0b1..SCL high and SDA high timeout occurs
5493 */
5494#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
5495#define I2C_SMB_SLTF_MASK (0x8U)
5496#define I2C_SMB_SLTF_SHIFT (3U)
5497/*! SLTF - SCL Low Timeout Flag
5498 * 0b0..No low timeout occurs
5499 * 0b1..Low timeout occurs
5500 */
5501#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
5502#define I2C_SMB_TCKSEL_MASK (0x10U)
5503#define I2C_SMB_TCKSEL_SHIFT (4U)
5504/*! TCKSEL - Timeout Counter Clock Select
5505 * 0b0..Timeout counter counts at the frequency of the I2C module clock / 64
5506 * 0b1..Timeout counter counts at the frequency of the I2C module clock
5507 */
5508#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
5509#define I2C_SMB_SIICAEN_MASK (0x20U)
5510#define I2C_SMB_SIICAEN_SHIFT (5U)
5511/*! SIICAEN - Second I2C Address Enable
5512 * 0b0..I2C address register 2 matching is disabled
5513 * 0b1..I2C address register 2 matching is enabled
5514 */
5515#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
5516#define I2C_SMB_ALERTEN_MASK (0x40U)
5517#define I2C_SMB_ALERTEN_SHIFT (6U)
5518/*! ALERTEN - SMBus Alert Response Address Enable
5519 * 0b0..SMBus alert response address matching is disabled
5520 * 0b1..SMBus alert response address matching is enabled
5521 */
5522#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
5523#define I2C_SMB_FACK_MASK (0x80U)
5524#define I2C_SMB_FACK_SHIFT (7U)
5525/*! FACK - Fast NACK/ACK Enable
5526 * 0b0..An ACK or NACK is sent on the following receiving data byte
5527 * 0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
5528 */
5529#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
5530/*! @} */
5531
5532/*! @name A2 - I2C Address Register 2 */
5533/*! @{ */
5534#define I2C_A2_SAD_MASK (0xFEU)
5535#define I2C_A2_SAD_SHIFT (1U)
5536#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
5537/*! @} */
5538
5539/*! @name SLTH - I2C SCL Low Timeout Register High */
5540/*! @{ */
5541#define I2C_SLTH_SSLT_MASK (0xFFU)
5542#define I2C_SLTH_SSLT_SHIFT (0U)
5543#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
5544/*! @} */
5545
5546/*! @name SLTL - I2C SCL Low Timeout Register Low */
5547/*! @{ */
5548#define I2C_SLTL_SSLT_MASK (0xFFU)
5549#define I2C_SLTL_SSLT_SHIFT (0U)
5550#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
5551/*! @} */
5552
5553
5554/*!
5555 * @}
5556 */ /* end of group I2C_Register_Masks */
5557
5558
5559/* I2C - Peripheral instance base addresses */
5560/** Peripheral I2C0 base address */
5561#define I2C0_BASE (0x40066000u)
5562/** Peripheral I2C0 base pointer */
5563#define I2C0 ((I2C_Type *)I2C0_BASE)
5564/** Peripheral I2C1 base address */
5565#define I2C1_BASE (0x40067000u)
5566/** Peripheral I2C1 base pointer */
5567#define I2C1 ((I2C_Type *)I2C1_BASE)
5568/** Array initializer of I2C peripheral base addresses */
5569#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
5570/** Array initializer of I2C peripheral base pointers */
5571#define I2C_BASE_PTRS { I2C0, I2C1 }
5572/** Interrupt vectors for the I2C peripheral type */
5573#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
5574
5575/*!
5576 * @}
5577 */ /* end of group I2C_Peripheral_Access_Layer */
5578
5579
5580/* ----------------------------------------------------------------------------
5581 -- I2S Peripheral Access Layer
5582 ---------------------------------------------------------------------------- */
5583
5584/*!
5585 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
5586 * @{
5587 */
5588
5589/** I2S - Register Layout Typedef */
5590typedef struct {
5591 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
5592 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
5593 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
5594 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
5595 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
5596 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
5597 uint8_t RESERVED_0[8];
5598 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
5599 uint8_t RESERVED_1[28];
5600 __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
5601 uint8_t RESERVED_2[28];
5602 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
5603 uint8_t RESERVED_3[28];
5604 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
5605 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
5606 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
5607 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
5608 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
5609 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
5610 uint8_t RESERVED_4[8];
5611 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
5612 uint8_t RESERVED_5[28];
5613 __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
5614 uint8_t RESERVED_6[28];
5615 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
5616 uint8_t RESERVED_7[28];
5617 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
5618 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
5619} I2S_Type;
5620
5621/* ----------------------------------------------------------------------------
5622 -- I2S Register Masks
5623 ---------------------------------------------------------------------------- */
5624
5625/*!
5626 * @addtogroup I2S_Register_Masks I2S Register Masks
5627 * @{
5628 */
5629
5630/*! @name TCSR - SAI Transmit Control Register */
5631/*! @{ */
5632#define I2S_TCSR_FRDE_MASK (0x1U)
5633#define I2S_TCSR_FRDE_SHIFT (0U)
5634/*! FRDE - FIFO Request DMA Enable
5635 * 0b0..Disables the DMA request.
5636 * 0b1..Enables the DMA request.
5637 */
5638#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
5639#define I2S_TCSR_FWDE_MASK (0x2U)
5640#define I2S_TCSR_FWDE_SHIFT (1U)
5641/*! FWDE - FIFO Warning DMA Enable
5642 * 0b0..Disables the DMA request.
5643 * 0b1..Enables the DMA request.
5644 */
5645#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
5646#define I2S_TCSR_FRIE_MASK (0x100U)
5647#define I2S_TCSR_FRIE_SHIFT (8U)
5648/*! FRIE - FIFO Request Interrupt Enable
5649 * 0b0..Disables the interrupt.
5650 * 0b1..Enables the interrupt.
5651 */
5652#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
5653#define I2S_TCSR_FWIE_MASK (0x200U)
5654#define I2S_TCSR_FWIE_SHIFT (9U)
5655/*! FWIE - FIFO Warning Interrupt Enable
5656 * 0b0..Disables the interrupt.
5657 * 0b1..Enables the interrupt.
5658 */
5659#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
5660#define I2S_TCSR_FEIE_MASK (0x400U)
5661#define I2S_TCSR_FEIE_SHIFT (10U)
5662/*! FEIE - FIFO Error Interrupt Enable
5663 * 0b0..Disables the interrupt.
5664 * 0b1..Enables the interrupt.
5665 */
5666#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
5667#define I2S_TCSR_SEIE_MASK (0x800U)
5668#define I2S_TCSR_SEIE_SHIFT (11U)
5669/*! SEIE - Sync Error Interrupt Enable
5670 * 0b0..Disables interrupt.
5671 * 0b1..Enables interrupt.
5672 */
5673#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
5674#define I2S_TCSR_WSIE_MASK (0x1000U)
5675#define I2S_TCSR_WSIE_SHIFT (12U)
5676/*! WSIE - Word Start Interrupt Enable
5677 * 0b0..Disables interrupt.
5678 * 0b1..Enables interrupt.
5679 */
5680#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
5681#define I2S_TCSR_FRF_MASK (0x10000U)
5682#define I2S_TCSR_FRF_SHIFT (16U)
5683/*! FRF - FIFO Request Flag
5684 * 0b0..Transmit FIFO watermark has not been reached.
5685 * 0b1..Transmit FIFO watermark has been reached.
5686 */
5687#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
5688#define I2S_TCSR_FWF_MASK (0x20000U)
5689#define I2S_TCSR_FWF_SHIFT (17U)
5690/*! FWF - FIFO Warning Flag
5691 * 0b0..No enabled transmit FIFO is empty.
5692 * 0b1..Enabled transmit FIFO is empty.
5693 */
5694#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
5695#define I2S_TCSR_FEF_MASK (0x40000U)
5696#define I2S_TCSR_FEF_SHIFT (18U)
5697/*! FEF - FIFO Error Flag
5698 * 0b0..Transmit underrun not detected.
5699 * 0b1..Transmit underrun detected.
5700 */
5701#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
5702#define I2S_TCSR_SEF_MASK (0x80000U)
5703#define I2S_TCSR_SEF_SHIFT (19U)
5704/*! SEF - Sync Error Flag
5705 * 0b0..Sync error not detected.
5706 * 0b1..Frame sync error detected.
5707 */
5708#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
5709#define I2S_TCSR_WSF_MASK (0x100000U)
5710#define I2S_TCSR_WSF_SHIFT (20U)
5711/*! WSF - Word Start Flag
5712 * 0b0..Start of word not detected.
5713 * 0b1..Start of word detected.
5714 */
5715#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
5716#define I2S_TCSR_SR_MASK (0x1000000U)
5717#define I2S_TCSR_SR_SHIFT (24U)
5718/*! SR - Software Reset
5719 * 0b0..No effect.
5720 * 0b1..Software reset.
5721 */
5722#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
5723#define I2S_TCSR_FR_MASK (0x2000000U)
5724#define I2S_TCSR_FR_SHIFT (25U)
5725/*! FR - FIFO Reset
5726 * 0b0..No effect.
5727 * 0b1..FIFO reset.
5728 */
5729#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
5730#define I2S_TCSR_BCE_MASK (0x10000000U)
5731#define I2S_TCSR_BCE_SHIFT (28U)
5732/*! BCE - Bit Clock Enable
5733 * 0b0..Transmit bit clock is disabled.
5734 * 0b1..Transmit bit clock is enabled.
5735 */
5736#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
5737#define I2S_TCSR_DBGE_MASK (0x20000000U)
5738#define I2S_TCSR_DBGE_SHIFT (29U)
5739/*! DBGE - Debug Enable
5740 * 0b0..Transmitter is disabled in Debug mode, after completing the current frame.
5741 * 0b1..Transmitter is enabled in Debug mode.
5742 */
5743#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
5744#define I2S_TCSR_STOPE_MASK (0x40000000U)
5745#define I2S_TCSR_STOPE_SHIFT (30U)
5746/*! STOPE - Stop Enable
5747 * 0b0..Transmitter disabled in Stop mode.
5748 * 0b1..Transmitter enabled in Stop mode.
5749 */
5750#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
5751#define I2S_TCSR_TE_MASK (0x80000000U)
5752#define I2S_TCSR_TE_SHIFT (31U)
5753/*! TE - Transmitter Enable
5754 * 0b0..Transmitter is disabled.
5755 * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
5756 */
5757#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
5758/*! @} */
5759
5760/*! @name TCR1 - SAI Transmit Configuration 1 Register */
5761/*! @{ */
5762#define I2S_TCR1_TFW_MASK (0x7U)
5763#define I2S_TCR1_TFW_SHIFT (0U)
5764#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
5765/*! @} */
5766
5767/*! @name TCR2 - SAI Transmit Configuration 2 Register */
5768/*! @{ */
5769#define I2S_TCR2_DIV_MASK (0xFFU)
5770#define I2S_TCR2_DIV_SHIFT (0U)
5771#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
5772#define I2S_TCR2_BCD_MASK (0x1000000U)
5773#define I2S_TCR2_BCD_SHIFT (24U)
5774/*! BCD - Bit Clock Direction
5775 * 0b0..Bit clock is generated externally in Slave mode.
5776 * 0b1..Bit clock is generated internally in Master mode.
5777 */
5778#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
5779#define I2S_TCR2_BCP_MASK (0x2000000U)
5780#define I2S_TCR2_BCP_SHIFT (25U)
5781/*! BCP - Bit Clock Polarity
5782 * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
5783 * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
5784 */
5785#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
5786#define I2S_TCR2_MSEL_MASK (0xC000000U)
5787#define I2S_TCR2_MSEL_SHIFT (26U)
5788/*! MSEL - MCLK Select
5789 * 0b00..Bus Clock selected.
5790 * 0b01..Master Clock (MCLK) 1 option selected.
5791 * 0b10..Master Clock (MCLK) 2 option selected.
5792 * 0b11..Master Clock (MCLK) 3 option selected.
5793 */
5794#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
5795#define I2S_TCR2_BCI_MASK (0x10000000U)
5796#define I2S_TCR2_BCI_SHIFT (28U)
5797/*! BCI - Bit Clock Input
5798 * 0b0..No effect.
5799 * 0b1..Internal logic is clocked as if bit clock was externally generated.
5800 */
5801#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
5802#define I2S_TCR2_BCS_MASK (0x20000000U)
5803#define I2S_TCR2_BCS_SHIFT (29U)
5804/*! BCS - Bit Clock Swap
5805 * 0b0..Use the normal bit clock source.
5806 * 0b1..Swap the bit clock source.
5807 */
5808#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
5809#define I2S_TCR2_SYNC_MASK (0xC0000000U)
5810#define I2S_TCR2_SYNC_SHIFT (30U)
5811/*! SYNC - Synchronous Mode
5812 * 0b00..Asynchronous mode.
5813 * 0b01..Synchronous with receiver.
5814 * 0b10..Synchronous with another SAI transmitter.
5815 * 0b11..Synchronous with another SAI receiver.
5816 */
5817#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
5818/*! @} */
5819
5820/*! @name TCR3 - SAI Transmit Configuration 3 Register */
5821/*! @{ */
5822#define I2S_TCR3_WDFL_MASK (0xFU)
5823#define I2S_TCR3_WDFL_SHIFT (0U)
5824#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
5825#define I2S_TCR3_TCE_MASK (0x10000U)
5826#define I2S_TCR3_TCE_SHIFT (16U)
5827/*! TCE - Transmit Channel Enable
5828 * 0b0..Transmit data channel N is disabled.
5829 * 0b1..Transmit data channel N is enabled.
5830 */
5831#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
5832/*! @} */
5833
5834/*! @name TCR4 - SAI Transmit Configuration 4 Register */
5835/*! @{ */
5836#define I2S_TCR4_FSD_MASK (0x1U)
5837#define I2S_TCR4_FSD_SHIFT (0U)
5838/*! FSD - Frame Sync Direction
5839 * 0b0..Frame sync is generated externally in Slave mode.
5840 * 0b1..Frame sync is generated internally in Master mode.
5841 */
5842#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
5843#define I2S_TCR4_FSP_MASK (0x2U)
5844#define I2S_TCR4_FSP_SHIFT (1U)
5845/*! FSP - Frame Sync Polarity
5846 * 0b0..Frame sync is active high.
5847 * 0b1..Frame sync is active low.
5848 */
5849#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
5850#define I2S_TCR4_ONDEM_MASK (0x4U)
5851#define I2S_TCR4_ONDEM_SHIFT (2U)
5852/*! ONDEM - On Demand Mode
5853 * 0b0..Internal frame sync is generated continuously.
5854 * 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
5855 */
5856#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
5857#define I2S_TCR4_FSE_MASK (0x8U)
5858#define I2S_TCR4_FSE_SHIFT (3U)
5859/*! FSE - Frame Sync Early
5860 * 0b0..Frame sync asserts with the first bit of the frame.
5861 * 0b1..Frame sync asserts one bit before the first bit of the frame.
5862 */
5863#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
5864#define I2S_TCR4_MF_MASK (0x10U)
5865#define I2S_TCR4_MF_SHIFT (4U)
5866/*! MF - MSB First
5867 * 0b0..LSB is transmitted first.
5868 * 0b1..MSB is transmitted first.
5869 */
5870#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
5871#define I2S_TCR4_SYWD_MASK (0x1F00U)
5872#define I2S_TCR4_SYWD_SHIFT (8U)
5873#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
5874#define I2S_TCR4_FRSZ_MASK (0xF0000U)
5875#define I2S_TCR4_FRSZ_SHIFT (16U)
5876#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
5877#define I2S_TCR4_FPACK_MASK (0x3000000U)
5878#define I2S_TCR4_FPACK_SHIFT (24U)
5879/*! FPACK - FIFO Packing Mode
5880 * 0b00..FIFO packing is disabled
5881 * 0b01..Reserved
5882 * 0b10..8-bit FIFO packing is enabled
5883 * 0b11..16-bit FIFO packing is enabled
5884 */
5885#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
5886#define I2S_TCR4_FCONT_MASK (0x10000000U)
5887#define I2S_TCR4_FCONT_SHIFT (28U)
5888/*! FCONT - FIFO Continue on Error
5889 * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
5890 * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
5891 */
5892#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
5893/*! @} */
5894
5895/*! @name TCR5 - SAI Transmit Configuration 5 Register */
5896/*! @{ */
5897#define I2S_TCR5_FBT_MASK (0x1F00U)
5898#define I2S_TCR5_FBT_SHIFT (8U)
5899#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
5900#define I2S_TCR5_W0W_MASK (0x1F0000U)
5901#define I2S_TCR5_W0W_SHIFT (16U)
5902#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
5903#define I2S_TCR5_WNW_MASK (0x1F000000U)
5904#define I2S_TCR5_WNW_SHIFT (24U)
5905#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
5906/*! @} */
5907
5908/*! @name TDR - SAI Transmit Data Register */
5909/*! @{ */
5910#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
5911#define I2S_TDR_TDR_SHIFT (0U)
5912#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
5913/*! @} */
5914
5915/* The count of I2S_TDR */
5916#define I2S_TDR_COUNT (1U)
5917
5918/*! @name TFR - SAI Transmit FIFO Register */
5919/*! @{ */
5920#define I2S_TFR_RFP_MASK (0xFU)
5921#define I2S_TFR_RFP_SHIFT (0U)
5922#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
5923#define I2S_TFR_WFP_MASK (0xF0000U)
5924#define I2S_TFR_WFP_SHIFT (16U)
5925#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
5926/*! @} */
5927
5928/* The count of I2S_TFR */
5929#define I2S_TFR_COUNT (1U)
5930
5931/*! @name TMR - SAI Transmit Mask Register */
5932/*! @{ */
5933#define I2S_TMR_TWM_MASK (0xFFFFU)
5934#define I2S_TMR_TWM_SHIFT (0U)
5935/*! TWM - Transmit Word Mask
5936 * 0b0000000000000000..Word N is enabled.
5937 * 0b0000000000000001..Word N is masked. The transmit data pins are tri-stated when masked.
5938 */
5939#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
5940/*! @} */
5941
5942/*! @name RCSR - SAI Receive Control Register */
5943/*! @{ */
5944#define I2S_RCSR_FRDE_MASK (0x1U)
5945#define I2S_RCSR_FRDE_SHIFT (0U)
5946/*! FRDE - FIFO Request DMA Enable
5947 * 0b0..Disables the DMA request.
5948 * 0b1..Enables the DMA request.
5949 */
5950#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
5951#define I2S_RCSR_FWDE_MASK (0x2U)
5952#define I2S_RCSR_FWDE_SHIFT (1U)
5953/*! FWDE - FIFO Warning DMA Enable
5954 * 0b0..Disables the DMA request.
5955 * 0b1..Enables the DMA request.
5956 */
5957#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
5958#define I2S_RCSR_FRIE_MASK (0x100U)
5959#define I2S_RCSR_FRIE_SHIFT (8U)
5960/*! FRIE - FIFO Request Interrupt Enable
5961 * 0b0..Disables the interrupt.
5962 * 0b1..Enables the interrupt.
5963 */
5964#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
5965#define I2S_RCSR_FWIE_MASK (0x200U)
5966#define I2S_RCSR_FWIE_SHIFT (9U)
5967/*! FWIE - FIFO Warning Interrupt Enable
5968 * 0b0..Disables the interrupt.
5969 * 0b1..Enables the interrupt.
5970 */
5971#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
5972#define I2S_RCSR_FEIE_MASK (0x400U)
5973#define I2S_RCSR_FEIE_SHIFT (10U)
5974/*! FEIE - FIFO Error Interrupt Enable
5975 * 0b0..Disables the interrupt.
5976 * 0b1..Enables the interrupt.
5977 */
5978#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
5979#define I2S_RCSR_SEIE_MASK (0x800U)
5980#define I2S_RCSR_SEIE_SHIFT (11U)
5981/*! SEIE - Sync Error Interrupt Enable
5982 * 0b0..Disables interrupt.
5983 * 0b1..Enables interrupt.
5984 */
5985#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
5986#define I2S_RCSR_WSIE_MASK (0x1000U)
5987#define I2S_RCSR_WSIE_SHIFT (12U)
5988/*! WSIE - Word Start Interrupt Enable
5989 * 0b0..Disables interrupt.
5990 * 0b1..Enables interrupt.
5991 */
5992#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
5993#define I2S_RCSR_FRF_MASK (0x10000U)
5994#define I2S_RCSR_FRF_SHIFT (16U)
5995/*! FRF - FIFO Request Flag
5996 * 0b0..Receive FIFO watermark not reached.
5997 * 0b1..Receive FIFO watermark has been reached.
5998 */
5999#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
6000#define I2S_RCSR_FWF_MASK (0x20000U)
6001#define I2S_RCSR_FWF_SHIFT (17U)
6002/*! FWF - FIFO Warning Flag
6003 * 0b0..No enabled receive FIFO is full.
6004 * 0b1..Enabled receive FIFO is full.
6005 */
6006#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
6007#define I2S_RCSR_FEF_MASK (0x40000U)
6008#define I2S_RCSR_FEF_SHIFT (18U)
6009/*! FEF - FIFO Error Flag
6010 * 0b0..Receive overflow not detected.
6011 * 0b1..Receive overflow detected.
6012 */
6013#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
6014#define I2S_RCSR_SEF_MASK (0x80000U)
6015#define I2S_RCSR_SEF_SHIFT (19U)
6016/*! SEF - Sync Error Flag
6017 * 0b0..Sync error not detected.
6018 * 0b1..Frame sync error detected.
6019 */
6020#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
6021#define I2S_RCSR_WSF_MASK (0x100000U)
6022#define I2S_RCSR_WSF_SHIFT (20U)
6023/*! WSF - Word Start Flag
6024 * 0b0..Start of word not detected.
6025 * 0b1..Start of word detected.
6026 */
6027#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
6028#define I2S_RCSR_SR_MASK (0x1000000U)
6029#define I2S_RCSR_SR_SHIFT (24U)
6030/*! SR - Software Reset
6031 * 0b0..No effect.
6032 * 0b1..Software reset.
6033 */
6034#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
6035#define I2S_RCSR_FR_MASK (0x2000000U)
6036#define I2S_RCSR_FR_SHIFT (25U)
6037/*! FR - FIFO Reset
6038 * 0b0..No effect.
6039 * 0b1..FIFO reset.
6040 */
6041#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
6042#define I2S_RCSR_BCE_MASK (0x10000000U)
6043#define I2S_RCSR_BCE_SHIFT (28U)
6044/*! BCE - Bit Clock Enable
6045 * 0b0..Receive bit clock is disabled.
6046 * 0b1..Receive bit clock is enabled.
6047 */
6048#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
6049#define I2S_RCSR_DBGE_MASK (0x20000000U)
6050#define I2S_RCSR_DBGE_SHIFT (29U)
6051/*! DBGE - Debug Enable
6052 * 0b0..Receiver is disabled in Debug mode, after completing the current frame.
6053 * 0b1..Receiver is enabled in Debug mode.
6054 */
6055#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
6056#define I2S_RCSR_STOPE_MASK (0x40000000U)
6057#define I2S_RCSR_STOPE_SHIFT (30U)
6058/*! STOPE - Stop Enable
6059 * 0b0..Receiver disabled in Stop mode.
6060 * 0b1..Receiver enabled in Stop mode.
6061 */
6062#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
6063#define I2S_RCSR_RE_MASK (0x80000000U)
6064#define I2S_RCSR_RE_SHIFT (31U)
6065/*! RE - Receiver Enable
6066 * 0b0..Receiver is disabled.
6067 * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
6068 */
6069#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
6070/*! @} */
6071
6072/*! @name RCR1 - SAI Receive Configuration 1 Register */
6073/*! @{ */
6074#define I2S_RCR1_RFW_MASK (0x7U)
6075#define I2S_RCR1_RFW_SHIFT (0U)
6076#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
6077/*! @} */
6078
6079/*! @name RCR2 - SAI Receive Configuration 2 Register */
6080/*! @{ */
6081#define I2S_RCR2_DIV_MASK (0xFFU)
6082#define I2S_RCR2_DIV_SHIFT (0U)
6083#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
6084#define I2S_RCR2_BCD_MASK (0x1000000U)
6085#define I2S_RCR2_BCD_SHIFT (24U)
6086/*! BCD - Bit Clock Direction
6087 * 0b0..Bit clock is generated externally in Slave mode.
6088 * 0b1..Bit clock is generated internally in Master mode.
6089 */
6090#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
6091#define I2S_RCR2_BCP_MASK (0x2000000U)
6092#define I2S_RCR2_BCP_SHIFT (25U)
6093/*! BCP - Bit Clock Polarity
6094 * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
6095 * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
6096 */
6097#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
6098#define I2S_RCR2_MSEL_MASK (0xC000000U)
6099#define I2S_RCR2_MSEL_SHIFT (26U)
6100/*! MSEL - MCLK Select
6101 * 0b00..Bus Clock selected.
6102 * 0b01..Master Clock (MCLK) 1 option selected.
6103 * 0b10..Master Clock (MCLK) 2 option selected.
6104 * 0b11..Master Clock (MCLK) 3 option selected.
6105 */
6106#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
6107#define I2S_RCR2_BCI_MASK (0x10000000U)
6108#define I2S_RCR2_BCI_SHIFT (28U)
6109/*! BCI - Bit Clock Input
6110 * 0b0..No effect.
6111 * 0b1..Internal logic is clocked as if bit clock was externally generated.
6112 */
6113#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
6114#define I2S_RCR2_BCS_MASK (0x20000000U)
6115#define I2S_RCR2_BCS_SHIFT (29U)
6116/*! BCS - Bit Clock Swap
6117 * 0b0..Use the normal bit clock source.
6118 * 0b1..Swap the bit clock source.
6119 */
6120#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
6121#define I2S_RCR2_SYNC_MASK (0xC0000000U)
6122#define I2S_RCR2_SYNC_SHIFT (30U)
6123/*! SYNC - Synchronous Mode
6124 * 0b00..Asynchronous mode.
6125 * 0b01..Synchronous with transmitter.
6126 * 0b10..Synchronous with another SAI receiver.
6127 * 0b11..Synchronous with another SAI transmitter.
6128 */
6129#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
6130/*! @} */
6131
6132/*! @name RCR3 - SAI Receive Configuration 3 Register */
6133/*! @{ */
6134#define I2S_RCR3_WDFL_MASK (0xFU)
6135#define I2S_RCR3_WDFL_SHIFT (0U)
6136#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
6137#define I2S_RCR3_RCE_MASK (0x10000U)
6138#define I2S_RCR3_RCE_SHIFT (16U)
6139/*! RCE - Receive Channel Enable
6140 * 0b0..Receive data channel N is disabled.
6141 * 0b1..Receive data channel N is enabled.
6142 */
6143#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
6144/*! @} */
6145
6146/*! @name RCR4 - SAI Receive Configuration 4 Register */
6147/*! @{ */
6148#define I2S_RCR4_FSD_MASK (0x1U)
6149#define I2S_RCR4_FSD_SHIFT (0U)
6150/*! FSD - Frame Sync Direction
6151 * 0b0..Frame Sync is generated externally in Slave mode.
6152 * 0b1..Frame Sync is generated internally in Master mode.
6153 */
6154#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
6155#define I2S_RCR4_FSP_MASK (0x2U)
6156#define I2S_RCR4_FSP_SHIFT (1U)
6157/*! FSP - Frame Sync Polarity
6158 * 0b0..Frame sync is active high.
6159 * 0b1..Frame sync is active low.
6160 */
6161#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
6162#define I2S_RCR4_ONDEM_MASK (0x4U)
6163#define I2S_RCR4_ONDEM_SHIFT (2U)
6164/*! ONDEM - On Demand Mode
6165 * 0b0..Internal frame sync is generated continuously.
6166 * 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
6167 */
6168#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
6169#define I2S_RCR4_FSE_MASK (0x8U)
6170#define I2S_RCR4_FSE_SHIFT (3U)
6171/*! FSE - Frame Sync Early
6172 * 0b0..Frame sync asserts with the first bit of the frame.
6173 * 0b1..Frame sync asserts one bit before the first bit of the frame.
6174 */
6175#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
6176#define I2S_RCR4_MF_MASK (0x10U)
6177#define I2S_RCR4_MF_SHIFT (4U)
6178/*! MF - MSB First
6179 * 0b0..LSB is received first.
6180 * 0b1..MSB is received first.
6181 */
6182#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
6183#define I2S_RCR4_SYWD_MASK (0x1F00U)
6184#define I2S_RCR4_SYWD_SHIFT (8U)
6185#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
6186#define I2S_RCR4_FRSZ_MASK (0xF0000U)
6187#define I2S_RCR4_FRSZ_SHIFT (16U)
6188#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
6189#define I2S_RCR4_FPACK_MASK (0x3000000U)
6190#define I2S_RCR4_FPACK_SHIFT (24U)
6191/*! FPACK - FIFO Packing Mode
6192 * 0b00..FIFO packing is disabled
6193 * 0b01..Reserved.
6194 * 0b10..8-bit FIFO packing is enabled
6195 * 0b11..16-bit FIFO packing is enabled
6196 */
6197#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
6198#define I2S_RCR4_FCONT_MASK (0x10000000U)
6199#define I2S_RCR4_FCONT_SHIFT (28U)
6200/*! FCONT - FIFO Continue on Error
6201 * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
6202 * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
6203 */
6204#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
6205/*! @} */
6206
6207/*! @name RCR5 - SAI Receive Configuration 5 Register */
6208/*! @{ */
6209#define I2S_RCR5_FBT_MASK (0x1F00U)
6210#define I2S_RCR5_FBT_SHIFT (8U)
6211#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
6212#define I2S_RCR5_W0W_MASK (0x1F0000U)
6213#define I2S_RCR5_W0W_SHIFT (16U)
6214#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
6215#define I2S_RCR5_WNW_MASK (0x1F000000U)
6216#define I2S_RCR5_WNW_SHIFT (24U)
6217#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
6218/*! @} */
6219
6220/*! @name RDR - SAI Receive Data Register */
6221/*! @{ */
6222#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
6223#define I2S_RDR_RDR_SHIFT (0U)
6224#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
6225/*! @} */
6226
6227/* The count of I2S_RDR */
6228#define I2S_RDR_COUNT (1U)
6229
6230/*! @name RFR - SAI Receive FIFO Register */
6231/*! @{ */
6232#define I2S_RFR_RFP_MASK (0xFU)
6233#define I2S_RFR_RFP_SHIFT (0U)
6234#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
6235#define I2S_RFR_WFP_MASK (0xF0000U)
6236#define I2S_RFR_WFP_SHIFT (16U)
6237#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
6238/*! @} */
6239
6240/* The count of I2S_RFR */
6241#define I2S_RFR_COUNT (1U)
6242
6243/*! @name RMR - SAI Receive Mask Register */
6244/*! @{ */
6245#define I2S_RMR_RWM_MASK (0xFFFFU)
6246#define I2S_RMR_RWM_SHIFT (0U)
6247/*! RWM - Receive Word Mask
6248 * 0b0000000000000000..Word N is enabled.
6249 * 0b0000000000000001..Word N is masked.
6250 */
6251#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
6252/*! @} */
6253
6254/*! @name MCR - SAI MCLK Control Register */
6255/*! @{ */
6256#define I2S_MCR_MICS_MASK (0x3000000U)
6257#define I2S_MCR_MICS_SHIFT (24U)
6258/*! MICS - MCLK Input Clock Select
6259 * 0b00..MCLK divider input clock 0 selected.
6260 * 0b01..MCLK divider input clock 1 selected.
6261 * 0b10..MCLK divider input clock 2 selected.
6262 * 0b11..MCLK divider input clock 3 selected.
6263 */
6264#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
6265#define I2S_MCR_MOE_MASK (0x40000000U)
6266#define I2S_MCR_MOE_SHIFT (30U)
6267/*! MOE - MCLK Output Enable
6268 * 0b0..MCLK signal pin is configured as an input that bypasses the MCLK divider.
6269 * 0b1..MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled.
6270 */
6271#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
6272#define I2S_MCR_DUF_MASK (0x80000000U)
6273#define I2S_MCR_DUF_SHIFT (31U)
6274/*! DUF - Divider Update Flag
6275 * 0b0..MCLK divider ratio is not being updated currently.
6276 * 0b1..MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set.
6277 */
6278#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
6279/*! @} */
6280
6281/*! @name MDR - SAI MCLK Divide Register */
6282/*! @{ */
6283#define I2S_MDR_DIVIDE_MASK (0xFFFU)
6284#define I2S_MDR_DIVIDE_SHIFT (0U)
6285#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
6286#define I2S_MDR_FRACT_MASK (0xFF000U)
6287#define I2S_MDR_FRACT_SHIFT (12U)
6288#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
6289/*! @} */
6290
6291
6292/*!
6293 * @}
6294 */ /* end of group I2S_Register_Masks */
6295
6296
6297/* I2S - Peripheral instance base addresses */
6298/** Peripheral I2S0 base address */
6299#define I2S0_BASE (0x4002F000u)
6300/** Peripheral I2S0 base pointer */
6301#define I2S0 ((I2S_Type *)I2S0_BASE)
6302/** Array initializer of I2S peripheral base addresses */
6303#define I2S_BASE_ADDRS { I2S0_BASE }
6304/** Array initializer of I2S peripheral base pointers */
6305#define I2S_BASE_PTRS { I2S0 }
6306/** Interrupt vectors for the I2S peripheral type */
6307#define I2S_RX_IRQS { I2S0_Rx_IRQn }
6308#define I2S_TX_IRQS { I2S0_Tx_IRQn }
6309
6310/*!
6311 * @}
6312 */ /* end of group I2S_Peripheral_Access_Layer */
6313
6314
6315/* ----------------------------------------------------------------------------
6316 -- LLWU Peripheral Access Layer
6317 ---------------------------------------------------------------------------- */
6318
6319/*!
6320 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
6321 * @{
6322 */
6323
6324/** LLWU - Register Layout Typedef */
6325typedef struct {
6326 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
6327 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
6328 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
6329 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
6330 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
6331 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
6332 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
6333 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
6334 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
6335 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
6336} LLWU_Type;
6337
6338/* ----------------------------------------------------------------------------
6339 -- LLWU Register Masks
6340 ---------------------------------------------------------------------------- */
6341
6342/*!
6343 * @addtogroup LLWU_Register_Masks LLWU Register Masks
6344 * @{
6345 */
6346
6347/*! @name PE1 - LLWU Pin Enable 1 register */
6348/*! @{ */
6349#define LLWU_PE1_WUPE0_MASK (0x3U)
6350#define LLWU_PE1_WUPE0_SHIFT (0U)
6351/*! WUPE0 - Wakeup Pin Enable For LLWU_P0
6352 * 0b00..External input pin disabled as wakeup input
6353 * 0b01..External input pin enabled with rising edge detection
6354 * 0b10..External input pin enabled with falling edge detection
6355 * 0b11..External input pin enabled with any change detection
6356 */
6357#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
6358#define LLWU_PE1_WUPE1_MASK (0xCU)
6359#define LLWU_PE1_WUPE1_SHIFT (2U)
6360/*! WUPE1 - Wakeup Pin Enable For LLWU_P1
6361 * 0b00..External input pin disabled as wakeup input
6362 * 0b01..External input pin enabled with rising edge detection
6363 * 0b10..External input pin enabled with falling edge detection
6364 * 0b11..External input pin enabled with any change detection
6365 */
6366#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
6367#define LLWU_PE1_WUPE2_MASK (0x30U)
6368#define LLWU_PE1_WUPE2_SHIFT (4U)
6369/*! WUPE2 - Wakeup Pin Enable For LLWU_P2
6370 * 0b00..External input pin disabled as wakeup input
6371 * 0b01..External input pin enabled with rising edge detection
6372 * 0b10..External input pin enabled with falling edge detection
6373 * 0b11..External input pin enabled with any change detection
6374 */
6375#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
6376#define LLWU_PE1_WUPE3_MASK (0xC0U)
6377#define LLWU_PE1_WUPE3_SHIFT (6U)
6378/*! WUPE3 - Wakeup Pin Enable For LLWU_P3
6379 * 0b00..External input pin disabled as wakeup input
6380 * 0b01..External input pin enabled with rising edge detection
6381 * 0b10..External input pin enabled with falling edge detection
6382 * 0b11..External input pin enabled with any change detection
6383 */
6384#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
6385/*! @} */
6386
6387/*! @name PE2 - LLWU Pin Enable 2 register */
6388/*! @{ */
6389#define LLWU_PE2_WUPE4_MASK (0x3U)
6390#define LLWU_PE2_WUPE4_SHIFT (0U)
6391/*! WUPE4 - Wakeup Pin Enable For LLWU_P4
6392 * 0b00..External input pin disabled as wakeup input
6393 * 0b01..External input pin enabled with rising edge detection
6394 * 0b10..External input pin enabled with falling edge detection
6395 * 0b11..External input pin enabled with any change detection
6396 */
6397#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
6398#define LLWU_PE2_WUPE5_MASK (0xCU)
6399#define LLWU_PE2_WUPE5_SHIFT (2U)
6400/*! WUPE5 - Wakeup Pin Enable For LLWU_P5
6401 * 0b00..External input pin disabled as wakeup input
6402 * 0b01..External input pin enabled with rising edge detection
6403 * 0b10..External input pin enabled with falling edge detection
6404 * 0b11..External input pin enabled with any change detection
6405 */
6406#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
6407#define LLWU_PE2_WUPE6_MASK (0x30U)
6408#define LLWU_PE2_WUPE6_SHIFT (4U)
6409/*! WUPE6 - Wakeup Pin Enable For LLWU_P6
6410 * 0b00..External input pin disabled as wakeup input
6411 * 0b01..External input pin enabled with rising edge detection
6412 * 0b10..External input pin enabled with falling edge detection
6413 * 0b11..External input pin enabled with any change detection
6414 */
6415#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
6416#define LLWU_PE2_WUPE7_MASK (0xC0U)
6417#define LLWU_PE2_WUPE7_SHIFT (6U)
6418/*! WUPE7 - Wakeup Pin Enable For LLWU_P7
6419 * 0b00..External input pin disabled as wakeup input
6420 * 0b01..External input pin enabled with rising edge detection
6421 * 0b10..External input pin enabled with falling edge detection
6422 * 0b11..External input pin enabled with any change detection
6423 */
6424#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
6425/*! @} */
6426
6427/*! @name PE3 - LLWU Pin Enable 3 register */
6428/*! @{ */
6429#define LLWU_PE3_WUPE8_MASK (0x3U)
6430#define LLWU_PE3_WUPE8_SHIFT (0U)
6431/*! WUPE8 - Wakeup Pin Enable For LLWU_P8
6432 * 0b00..External input pin disabled as wakeup input
6433 * 0b01..External input pin enabled with rising edge detection
6434 * 0b10..External input pin enabled with falling edge detection
6435 * 0b11..External input pin enabled with any change detection
6436 */
6437#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
6438#define LLWU_PE3_WUPE9_MASK (0xCU)
6439#define LLWU_PE3_WUPE9_SHIFT (2U)
6440/*! WUPE9 - Wakeup Pin Enable For LLWU_P9
6441 * 0b00..External input pin disabled as wakeup input
6442 * 0b01..External input pin enabled with rising edge detection
6443 * 0b10..External input pin enabled with falling edge detection
6444 * 0b11..External input pin enabled with any change detection
6445 */
6446#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
6447#define LLWU_PE3_WUPE10_MASK (0x30U)
6448#define LLWU_PE3_WUPE10_SHIFT (4U)
6449/*! WUPE10 - Wakeup Pin Enable For LLWU_P10
6450 * 0b00..External input pin disabled as wakeup input
6451 * 0b01..External input pin enabled with rising edge detection
6452 * 0b10..External input pin enabled with falling edge detection
6453 * 0b11..External input pin enabled with any change detection
6454 */
6455#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
6456#define LLWU_PE3_WUPE11_MASK (0xC0U)
6457#define LLWU_PE3_WUPE11_SHIFT (6U)
6458/*! WUPE11 - Wakeup Pin Enable For LLWU_P11
6459 * 0b00..External input pin disabled as wakeup input
6460 * 0b01..External input pin enabled with rising edge detection
6461 * 0b10..External input pin enabled with falling edge detection
6462 * 0b11..External input pin enabled with any change detection
6463 */
6464#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
6465/*! @} */
6466
6467/*! @name PE4 - LLWU Pin Enable 4 register */
6468/*! @{ */
6469#define LLWU_PE4_WUPE12_MASK (0x3U)
6470#define LLWU_PE4_WUPE12_SHIFT (0U)
6471/*! WUPE12 - Wakeup Pin Enable For LLWU_P12
6472 * 0b00..External input pin disabled as wakeup input
6473 * 0b01..External input pin enabled with rising edge detection
6474 * 0b10..External input pin enabled with falling edge detection
6475 * 0b11..External input pin enabled with any change detection
6476 */
6477#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
6478#define LLWU_PE4_WUPE13_MASK (0xCU)
6479#define LLWU_PE4_WUPE13_SHIFT (2U)
6480/*! WUPE13 - Wakeup Pin Enable For LLWU_P13
6481 * 0b00..External input pin disabled as wakeup input
6482 * 0b01..External input pin enabled with rising edge detection
6483 * 0b10..External input pin enabled with falling edge detection
6484 * 0b11..External input pin enabled with any change detection
6485 */
6486#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
6487#define LLWU_PE4_WUPE14_MASK (0x30U)
6488#define LLWU_PE4_WUPE14_SHIFT (4U)
6489/*! WUPE14 - Wakeup Pin Enable For LLWU_P14
6490 * 0b00..External input pin disabled as wakeup input
6491 * 0b01..External input pin enabled with rising edge detection
6492 * 0b10..External input pin enabled with falling edge detection
6493 * 0b11..External input pin enabled with any change detection
6494 */
6495#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
6496#define LLWU_PE4_WUPE15_MASK (0xC0U)
6497#define LLWU_PE4_WUPE15_SHIFT (6U)
6498/*! WUPE15 - Wakeup Pin Enable For LLWU_P15
6499 * 0b00..External input pin disabled as wakeup input
6500 * 0b01..External input pin enabled with rising edge detection
6501 * 0b10..External input pin enabled with falling edge detection
6502 * 0b11..External input pin enabled with any change detection
6503 */
6504#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
6505/*! @} */
6506
6507/*! @name ME - LLWU Module Enable register */
6508/*! @{ */
6509#define LLWU_ME_WUME0_MASK (0x1U)
6510#define LLWU_ME_WUME0_SHIFT (0U)
6511/*! WUME0 - Wakeup Module Enable For Module 0
6512 * 0b0..Internal module flag not used as wakeup source
6513 * 0b1..Internal module flag used as wakeup source
6514 */
6515#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
6516#define LLWU_ME_WUME1_MASK (0x2U)
6517#define LLWU_ME_WUME1_SHIFT (1U)
6518/*! WUME1 - Wakeup Module Enable for Module 1
6519 * 0b0..Internal module flag not used as wakeup source
6520 * 0b1..Internal module flag used as wakeup source
6521 */
6522#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
6523#define LLWU_ME_WUME2_MASK (0x4U)
6524#define LLWU_ME_WUME2_SHIFT (2U)
6525/*! WUME2 - Wakeup Module Enable For Module 2
6526 * 0b0..Internal module flag not used as wakeup source
6527 * 0b1..Internal module flag used as wakeup source
6528 */
6529#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
6530#define LLWU_ME_WUME3_MASK (0x8U)
6531#define LLWU_ME_WUME3_SHIFT (3U)
6532/*! WUME3 - Wakeup Module Enable For Module 3
6533 * 0b0..Internal module flag not used as wakeup source
6534 * 0b1..Internal module flag used as wakeup source
6535 */
6536#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
6537#define LLWU_ME_WUME4_MASK (0x10U)
6538#define LLWU_ME_WUME4_SHIFT (4U)
6539/*! WUME4 - Wakeup Module Enable For Module 4
6540 * 0b0..Internal module flag not used as wakeup source
6541 * 0b1..Internal module flag used as wakeup source
6542 */
6543#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
6544#define LLWU_ME_WUME5_MASK (0x20U)
6545#define LLWU_ME_WUME5_SHIFT (5U)
6546/*! WUME5 - Wakeup Module Enable For Module 5
6547 * 0b0..Internal module flag not used as wakeup source
6548 * 0b1..Internal module flag used as wakeup source
6549 */
6550#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
6551#define LLWU_ME_WUME6_MASK (0x40U)
6552#define LLWU_ME_WUME6_SHIFT (6U)
6553/*! WUME6 - Wakeup Module Enable For Module 6
6554 * 0b0..Internal module flag not used as wakeup source
6555 * 0b1..Internal module flag used as wakeup source
6556 */
6557#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
6558#define LLWU_ME_WUME7_MASK (0x80U)
6559#define LLWU_ME_WUME7_SHIFT (7U)
6560/*! WUME7 - Wakeup Module Enable For Module 7
6561 * 0b0..Internal module flag not used as wakeup source
6562 * 0b1..Internal module flag used as wakeup source
6563 */
6564#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
6565/*! @} */
6566
6567/*! @name F1 - LLWU Flag 1 register */
6568/*! @{ */
6569#define LLWU_F1_WUF0_MASK (0x1U)
6570#define LLWU_F1_WUF0_SHIFT (0U)
6571/*! WUF0 - Wakeup Flag For LLWU_P0
6572 * 0b0..LLWU_P0 input was not a wakeup source
6573 * 0b1..LLWU_P0 input was a wakeup source
6574 */
6575#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
6576#define LLWU_F1_WUF1_MASK (0x2U)
6577#define LLWU_F1_WUF1_SHIFT (1U)
6578/*! WUF1 - Wakeup Flag For LLWU_P1
6579 * 0b0..LLWU_P1 input was not a wakeup source
6580 * 0b1..LLWU_P1 input was a wakeup source
6581 */
6582#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
6583#define LLWU_F1_WUF2_MASK (0x4U)
6584#define LLWU_F1_WUF2_SHIFT (2U)
6585/*! WUF2 - Wakeup Flag For LLWU_P2
6586 * 0b0..LLWU_P2 input was not a wakeup source
6587 * 0b1..LLWU_P2 input was a wakeup source
6588 */
6589#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
6590#define LLWU_F1_WUF3_MASK (0x8U)
6591#define LLWU_F1_WUF3_SHIFT (3U)
6592/*! WUF3 - Wakeup Flag For LLWU_P3
6593 * 0b0..LLWU_P3 input was not a wake-up source
6594 * 0b1..LLWU_P3 input was a wake-up source
6595 */
6596#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
6597#define LLWU_F1_WUF4_MASK (0x10U)
6598#define LLWU_F1_WUF4_SHIFT (4U)
6599/*! WUF4 - Wakeup Flag For LLWU_P4
6600 * 0b0..LLWU_P4 input was not a wakeup source
6601 * 0b1..LLWU_P4 input was a wakeup source
6602 */
6603#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
6604#define LLWU_F1_WUF5_MASK (0x20U)
6605#define LLWU_F1_WUF5_SHIFT (5U)
6606/*! WUF5 - Wakeup Flag For LLWU_P5
6607 * 0b0..LLWU_P5 input was not a wakeup source
6608 * 0b1..LLWU_P5 input was a wakeup source
6609 */
6610#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
6611#define LLWU_F1_WUF6_MASK (0x40U)
6612#define LLWU_F1_WUF6_SHIFT (6U)
6613/*! WUF6 - Wakeup Flag For LLWU_P6
6614 * 0b0..LLWU_P6 input was not a wakeup source
6615 * 0b1..LLWU_P6 input was a wakeup source
6616 */
6617#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
6618#define LLWU_F1_WUF7_MASK (0x80U)
6619#define LLWU_F1_WUF7_SHIFT (7U)
6620/*! WUF7 - Wakeup Flag For LLWU_P7
6621 * 0b0..LLWU_P7 input was not a wakeup source
6622 * 0b1..LLWU_P7 input was a wakeup source
6623 */
6624#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
6625/*! @} */
6626
6627/*! @name F2 - LLWU Flag 2 register */
6628/*! @{ */
6629#define LLWU_F2_WUF8_MASK (0x1U)
6630#define LLWU_F2_WUF8_SHIFT (0U)
6631/*! WUF8 - Wakeup Flag For LLWU_P8
6632 * 0b0..LLWU_P8 input was not a wakeup source
6633 * 0b1..LLWU_P8 input was a wakeup source
6634 */
6635#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
6636#define LLWU_F2_WUF9_MASK (0x2U)
6637#define LLWU_F2_WUF9_SHIFT (1U)
6638/*! WUF9 - Wakeup Flag For LLWU_P9
6639 * 0b0..LLWU_P9 input was not a wakeup source
6640 * 0b1..LLWU_P9 input was a wakeup source
6641 */
6642#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
6643#define LLWU_F2_WUF10_MASK (0x4U)
6644#define LLWU_F2_WUF10_SHIFT (2U)
6645/*! WUF10 - Wakeup Flag For LLWU_P10
6646 * 0b0..LLWU_P10 input was not a wakeup source
6647 * 0b1..LLWU_P10 input was a wakeup source
6648 */
6649#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
6650#define LLWU_F2_WUF11_MASK (0x8U)
6651#define LLWU_F2_WUF11_SHIFT (3U)
6652/*! WUF11 - Wakeup Flag For LLWU_P11
6653 * 0b0..LLWU_P11 input was not a wakeup source
6654 * 0b1..LLWU_P11 input was a wakeup source
6655 */
6656#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
6657#define LLWU_F2_WUF12_MASK (0x10U)
6658#define LLWU_F2_WUF12_SHIFT (4U)
6659/*! WUF12 - Wakeup Flag For LLWU_P12
6660 * 0b0..LLWU_P12 input was not a wakeup source
6661 * 0b1..LLWU_P12 input was a wakeup source
6662 */
6663#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
6664#define LLWU_F2_WUF13_MASK (0x20U)
6665#define LLWU_F2_WUF13_SHIFT (5U)
6666/*! WUF13 - Wakeup Flag For LLWU_P13
6667 * 0b0..LLWU_P13 input was not a wakeup source
6668 * 0b1..LLWU_P13 input was a wakeup source
6669 */
6670#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
6671#define LLWU_F2_WUF14_MASK (0x40U)
6672#define LLWU_F2_WUF14_SHIFT (6U)
6673/*! WUF14 - Wakeup Flag For LLWU_P14
6674 * 0b0..LLWU_P14 input was not a wakeup source
6675 * 0b1..LLWU_P14 input was a wakeup source
6676 */
6677#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
6678#define LLWU_F2_WUF15_MASK (0x80U)
6679#define LLWU_F2_WUF15_SHIFT (7U)
6680/*! WUF15 - Wakeup Flag For LLWU_P15
6681 * 0b0..LLWU_P15 input was not a wakeup source
6682 * 0b1..LLWU_P15 input was a wakeup source
6683 */
6684#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
6685/*! @} */
6686
6687/*! @name F3 - LLWU Flag 3 register */
6688/*! @{ */
6689#define LLWU_F3_MWUF0_MASK (0x1U)
6690#define LLWU_F3_MWUF0_SHIFT (0U)
6691/*! MWUF0 - Wakeup flag For module 0
6692 * 0b0..Module 0 input was not a wakeup source
6693 * 0b1..Module 0 input was a wakeup source
6694 */
6695#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
6696#define LLWU_F3_MWUF1_MASK (0x2U)
6697#define LLWU_F3_MWUF1_SHIFT (1U)
6698/*! MWUF1 - Wakeup flag For module 1
6699 * 0b0..Module 1 input was not a wakeup source
6700 * 0b1..Module 1 input was a wakeup source
6701 */
6702#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
6703#define LLWU_F3_MWUF2_MASK (0x4U)
6704#define LLWU_F3_MWUF2_SHIFT (2U)
6705/*! MWUF2 - Wakeup flag For module 2
6706 * 0b0..Module 2 input was not a wakeup source
6707 * 0b1..Module 2 input was a wakeup source
6708 */
6709#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
6710#define LLWU_F3_MWUF3_MASK (0x8U)
6711#define LLWU_F3_MWUF3_SHIFT (3U)
6712/*! MWUF3 - Wakeup flag For module 3
6713 * 0b0..Module 3 input was not a wakeup source
6714 * 0b1..Module 3 input was a wakeup source
6715 */
6716#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
6717#define LLWU_F3_MWUF4_MASK (0x10U)
6718#define LLWU_F3_MWUF4_SHIFT (4U)
6719/*! MWUF4 - Wakeup flag For module 4
6720 * 0b0..Module 4 input was not a wakeup source
6721 * 0b1..Module 4 input was a wakeup source
6722 */
6723#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
6724#define LLWU_F3_MWUF5_MASK (0x20U)
6725#define LLWU_F3_MWUF5_SHIFT (5U)
6726/*! MWUF5 - Wakeup flag For module 5
6727 * 0b0..Module 5 input was not a wakeup source
6728 * 0b1..Module 5 input was a wakeup source
6729 */
6730#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
6731#define LLWU_F3_MWUF6_MASK (0x40U)
6732#define LLWU_F3_MWUF6_SHIFT (6U)
6733/*! MWUF6 - Wakeup flag For module 6
6734 * 0b0..Module 6 input was not a wakeup source
6735 * 0b1..Module 6 input was a wakeup source
6736 */
6737#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
6738#define LLWU_F3_MWUF7_MASK (0x80U)
6739#define LLWU_F3_MWUF7_SHIFT (7U)
6740/*! MWUF7 - Wakeup flag For module 7
6741 * 0b0..Module 7 input was not a wakeup source
6742 * 0b1..Module 7 input was a wakeup source
6743 */
6744#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
6745/*! @} */
6746
6747/*! @name FILT1 - LLWU Pin Filter 1 register */
6748/*! @{ */
6749#define LLWU_FILT1_FILTSEL_MASK (0xFU)
6750#define LLWU_FILT1_FILTSEL_SHIFT (0U)
6751/*! FILTSEL - Filter Pin Select
6752 * 0b0000..Select LLWU_P0 for filter
6753 * 0b1111..Select LLWU_P15 for filter
6754 */
6755#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
6756#define LLWU_FILT1_FILTE_MASK (0x60U)
6757#define LLWU_FILT1_FILTE_SHIFT (5U)
6758/*! FILTE - Digital Filter On External Pin
6759 * 0b00..Filter disabled
6760 * 0b01..Filter posedge detect enabled
6761 * 0b10..Filter negedge detect enabled
6762 * 0b11..Filter any edge detect enabled
6763 */
6764#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
6765#define LLWU_FILT1_FILTF_MASK (0x80U)
6766#define LLWU_FILT1_FILTF_SHIFT (7U)
6767/*! FILTF - Filter Detect Flag
6768 * 0b0..Pin Filter 1 was not a wakeup source
6769 * 0b1..Pin Filter 1 was a wakeup source
6770 */
6771#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
6772/*! @} */
6773
6774/*! @name FILT2 - LLWU Pin Filter 2 register */
6775/*! @{ */
6776#define LLWU_FILT2_FILTSEL_MASK (0xFU)
6777#define LLWU_FILT2_FILTSEL_SHIFT (0U)
6778/*! FILTSEL - Filter Pin Select
6779 * 0b0000..Select LLWU_P0 for filter
6780 * 0b1111..Select LLWU_P15 for filter
6781 */
6782#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
6783#define LLWU_FILT2_FILTE_MASK (0x60U)
6784#define LLWU_FILT2_FILTE_SHIFT (5U)
6785/*! FILTE - Digital Filter On External Pin
6786 * 0b00..Filter disabled
6787 * 0b01..Filter posedge detect enabled
6788 * 0b10..Filter negedge detect enabled
6789 * 0b11..Filter any edge detect enabled
6790 */
6791#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
6792#define LLWU_FILT2_FILTF_MASK (0x80U)
6793#define LLWU_FILT2_FILTF_SHIFT (7U)
6794/*! FILTF - Filter Detect Flag
6795 * 0b0..Pin Filter 2 was not a wakeup source
6796 * 0b1..Pin Filter 2 was a wakeup source
6797 */
6798#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
6799/*! @} */
6800
6801
6802/*!
6803 * @}
6804 */ /* end of group LLWU_Register_Masks */
6805
6806
6807/* LLWU - Peripheral instance base addresses */
6808/** Peripheral LLWU base address */
6809#define LLWU_BASE (0x4007C000u)
6810/** Peripheral LLWU base pointer */
6811#define LLWU ((LLWU_Type *)LLWU_BASE)
6812/** Array initializer of LLWU peripheral base addresses */
6813#define LLWU_BASE_ADDRS { LLWU_BASE }
6814/** Array initializer of LLWU peripheral base pointers */
6815#define LLWU_BASE_PTRS { LLWU }
6816/** Interrupt vectors for the LLWU peripheral type */
6817#define LLWU_IRQS { LLWU_IRQn }
6818
6819/*!
6820 * @}
6821 */ /* end of group LLWU_Peripheral_Access_Layer */
6822
6823
6824/* ----------------------------------------------------------------------------
6825 -- LPTMR Peripheral Access Layer
6826 ---------------------------------------------------------------------------- */
6827
6828/*!
6829 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
6830 * @{
6831 */
6832
6833/** LPTMR - Register Layout Typedef */
6834typedef struct {
6835 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
6836 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
6837 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
6838 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
6839} LPTMR_Type;
6840
6841/* ----------------------------------------------------------------------------
6842 -- LPTMR Register Masks
6843 ---------------------------------------------------------------------------- */
6844
6845/*!
6846 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
6847 * @{
6848 */
6849
6850/*! @name CSR - Low Power Timer Control Status Register */
6851/*! @{ */
6852#define LPTMR_CSR_TEN_MASK (0x1U)
6853#define LPTMR_CSR_TEN_SHIFT (0U)
6854/*! TEN - Timer Enable
6855 * 0b0..LPTMR is disabled and internal logic is reset.
6856 * 0b1..LPTMR is enabled.
6857 */
6858#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
6859#define LPTMR_CSR_TMS_MASK (0x2U)
6860#define LPTMR_CSR_TMS_SHIFT (1U)
6861/*! TMS - Timer Mode Select
6862 * 0b0..Time Counter mode.
6863 * 0b1..Pulse Counter mode.
6864 */
6865#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
6866#define LPTMR_CSR_TFC_MASK (0x4U)
6867#define LPTMR_CSR_TFC_SHIFT (2U)
6868/*! TFC - Timer Free-Running Counter
6869 * 0b0..CNR is reset whenever TCF is set.
6870 * 0b1..CNR is reset on overflow.
6871 */
6872#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
6873#define LPTMR_CSR_TPP_MASK (0x8U)
6874#define LPTMR_CSR_TPP_SHIFT (3U)
6875/*! TPP - Timer Pin Polarity
6876 * 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
6877 * 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
6878 */
6879#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
6880#define LPTMR_CSR_TPS_MASK (0x30U)
6881#define LPTMR_CSR_TPS_SHIFT (4U)
6882/*! TPS - Timer Pin Select
6883 * 0b00..Pulse counter input 0 is selected.
6884 * 0b01..Pulse counter input 1 is selected.
6885 * 0b10..Pulse counter input 2 is selected.
6886 * 0b11..Pulse counter input 3 is selected.
6887 */
6888#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
6889#define LPTMR_CSR_TIE_MASK (0x40U)
6890#define LPTMR_CSR_TIE_SHIFT (6U)
6891/*! TIE - Timer Interrupt Enable
6892 * 0b0..Timer interrupt disabled.
6893 * 0b1..Timer interrupt enabled.
6894 */
6895#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
6896#define LPTMR_CSR_TCF_MASK (0x80U)
6897#define LPTMR_CSR_TCF_SHIFT (7U)
6898/*! TCF - Timer Compare Flag
6899 * 0b0..The value of CNR is not equal to CMR and increments.
6900 * 0b1..The value of CNR is equal to CMR and increments.
6901 */
6902#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
6903/*! @} */
6904
6905/*! @name PSR - Low Power Timer Prescale Register */
6906/*! @{ */
6907#define LPTMR_PSR_PCS_MASK (0x3U)
6908#define LPTMR_PSR_PCS_SHIFT (0U)
6909/*! PCS - Prescaler Clock Select
6910 * 0b00..Prescaler/glitch filter clock 0 selected.
6911 * 0b01..Prescaler/glitch filter clock 1 selected.
6912 * 0b10..Prescaler/glitch filter clock 2 selected.
6913 * 0b11..Prescaler/glitch filter clock 3 selected.
6914 */
6915#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
6916#define LPTMR_PSR_PBYP_MASK (0x4U)
6917#define LPTMR_PSR_PBYP_SHIFT (2U)
6918/*! PBYP - Prescaler Bypass
6919 * 0b0..Prescaler/glitch filter is enabled.
6920 * 0b1..Prescaler/glitch filter is bypassed.
6921 */
6922#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
6923#define LPTMR_PSR_PRESCALE_MASK (0x78U)
6924#define LPTMR_PSR_PRESCALE_SHIFT (3U)
6925/*! PRESCALE - Prescale Value
6926 * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
6927 * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.
6928 * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.
6929 * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.
6930 * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.
6931 * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.
6932 * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.
6933 * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.
6934 * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.
6935 * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
6936 * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.
6937 * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.
6938 * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.
6939 * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.
6940 * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.
6941 * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.
6942 */
6943#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
6944/*! @} */
6945
6946/*! @name CMR - Low Power Timer Compare Register */
6947/*! @{ */
6948#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
6949#define LPTMR_CMR_COMPARE_SHIFT (0U)
6950#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
6951/*! @} */
6952
6953/*! @name CNR - Low Power Timer Counter Register */
6954/*! @{ */
6955#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
6956#define LPTMR_CNR_COUNTER_SHIFT (0U)
6957#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
6958/*! @} */
6959
6960
6961/*!
6962 * @}
6963 */ /* end of group LPTMR_Register_Masks */
6964
6965
6966/* LPTMR - Peripheral instance base addresses */
6967/** Peripheral LPTMR0 base address */
6968#define LPTMR0_BASE (0x40040000u)
6969/** Peripheral LPTMR0 base pointer */
6970#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
6971/** Array initializer of LPTMR peripheral base addresses */
6972#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
6973/** Array initializer of LPTMR peripheral base pointers */
6974#define LPTMR_BASE_PTRS { LPTMR0 }
6975/** Interrupt vectors for the LPTMR peripheral type */
6976#define LPTMR_IRQS { LPTMR0_IRQn }
6977
6978/*!
6979 * @}
6980 */ /* end of group LPTMR_Peripheral_Access_Layer */
6981
6982
6983/* ----------------------------------------------------------------------------
6984 -- LPUART Peripheral Access Layer
6985 ---------------------------------------------------------------------------- */
6986
6987/*!
6988 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
6989 * @{
6990 */
6991
6992/** LPUART - Register Layout Typedef */
6993typedef struct {
6994 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
6995 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
6996 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
6997 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
6998 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
6999 __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */
7000} LPUART_Type;
7001
7002/* ----------------------------------------------------------------------------
7003 -- LPUART Register Masks
7004 ---------------------------------------------------------------------------- */
7005
7006/*!
7007 * @addtogroup LPUART_Register_Masks LPUART Register Masks
7008 * @{
7009 */
7010
7011/*! @name BAUD - LPUART Baud Rate Register */
7012/*! @{ */
7013#define LPUART_BAUD_SBR_MASK (0x1FFFU)
7014#define LPUART_BAUD_SBR_SHIFT (0U)
7015#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
7016#define LPUART_BAUD_SBNS_MASK (0x2000U)
7017#define LPUART_BAUD_SBNS_SHIFT (13U)
7018/*! SBNS - Stop Bit Number Select
7019 * 0b0..One stop bit.
7020 * 0b1..Two stop bits.
7021 */
7022#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
7023#define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
7024#define LPUART_BAUD_RXEDGIE_SHIFT (14U)
7025/*! RXEDGIE - RX Input Active Edge Interrupt Enable
7026 * 0b0..Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).
7027 * 0b1..Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.
7028 */
7029#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
7030#define LPUART_BAUD_LBKDIE_MASK (0x8000U)
7031#define LPUART_BAUD_LBKDIE_SHIFT (15U)
7032/*! LBKDIE - LIN Break Detect Interrupt Enable
7033 * 0b0..Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).
7034 * 0b1..Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.
7035 */
7036#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
7037#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
7038#define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
7039/*! RESYNCDIS - Resynchronization Disable
7040 * 0b0..Resynchronization during received data word is supported
7041 * 0b1..Resynchronization during received data word is disabled
7042 */
7043#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
7044#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
7045#define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
7046/*! BOTHEDGE - Both Edge Sampling
7047 * 0b0..Receiver samples input data using the rising edge of the baud rate clock.
7048 * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
7049 */
7050#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
7051#define LPUART_BAUD_MATCFG_MASK (0xC0000U)
7052#define LPUART_BAUD_MATCFG_SHIFT (18U)
7053/*! MATCFG - Match Configuration
7054 * 0b00..Address Match Wakeup
7055 * 0b01..Idle Match Wakeup
7056 * 0b10..Match On and Match Off
7057 * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
7058 */
7059#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
7060#define LPUART_BAUD_RDMAE_MASK (0x200000U)
7061#define LPUART_BAUD_RDMAE_SHIFT (21U)
7062/*! RDMAE - Receiver Full DMA Enable
7063 * 0b0..DMA request disabled.
7064 * 0b1..DMA request enabled.
7065 */
7066#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
7067#define LPUART_BAUD_TDMAE_MASK (0x800000U)
7068#define LPUART_BAUD_TDMAE_SHIFT (23U)
7069/*! TDMAE - Transmitter DMA Enable
7070 * 0b0..DMA request disabled.
7071 * 0b1..DMA request enabled.
7072 */
7073#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
7074#define LPUART_BAUD_OSR_MASK (0x1F000000U)
7075#define LPUART_BAUD_OSR_SHIFT (24U)
7076#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
7077#define LPUART_BAUD_M10_MASK (0x20000000U)
7078#define LPUART_BAUD_M10_SHIFT (29U)
7079/*! M10 - 10-bit Mode select
7080 * 0b0..Receiver and transmitter use 8-bit or 9-bit data characters.
7081 * 0b1..Receiver and transmitter use 10-bit data characters.
7082 */
7083#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
7084#define LPUART_BAUD_MAEN2_MASK (0x40000000U)
7085#define LPUART_BAUD_MAEN2_SHIFT (30U)
7086/*! MAEN2 - Match Address Mode Enable 2
7087 * 0b0..Normal operation.
7088 * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
7089 */
7090#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
7091#define LPUART_BAUD_MAEN1_MASK (0x80000000U)
7092#define LPUART_BAUD_MAEN1_SHIFT (31U)
7093/*! MAEN1 - Match Address Mode Enable 1
7094 * 0b0..Normal operation.
7095 * 0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
7096 */
7097#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
7098/*! @} */
7099
7100/*! @name STAT - LPUART Status Register */
7101/*! @{ */
7102#define LPUART_STAT_MA2F_MASK (0x4000U)
7103#define LPUART_STAT_MA2F_SHIFT (14U)
7104/*! MA2F - Match 2 Flag
7105 * 0b0..Received data is not equal to MA2
7106 * 0b1..Received data is equal to MA2
7107 */
7108#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
7109#define LPUART_STAT_MA1F_MASK (0x8000U)
7110#define LPUART_STAT_MA1F_SHIFT (15U)
7111/*! MA1F - Match 1 Flag
7112 * 0b0..Received data is not equal to MA1
7113 * 0b1..Received data is equal to MA1
7114 */
7115#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
7116#define LPUART_STAT_PF_MASK (0x10000U)
7117#define LPUART_STAT_PF_SHIFT (16U)
7118/*! PF - Parity Error Flag
7119 * 0b0..No parity error.
7120 * 0b1..Parity error.
7121 */
7122#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
7123#define LPUART_STAT_FE_MASK (0x20000U)
7124#define LPUART_STAT_FE_SHIFT (17U)
7125/*! FE - Framing Error Flag
7126 * 0b0..No framing error detected. This does not guarantee the framing is correct.
7127 * 0b1..Framing error.
7128 */
7129#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
7130#define LPUART_STAT_NF_MASK (0x40000U)
7131#define LPUART_STAT_NF_SHIFT (18U)
7132/*! NF - Noise Flag
7133 * 0b0..No noise detected.
7134 * 0b1..Noise detected in the received character in LPUART_DATA.
7135 */
7136#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
7137#define LPUART_STAT_OR_MASK (0x80000U)
7138#define LPUART_STAT_OR_SHIFT (19U)
7139/*! OR - Receiver Overrun Flag
7140 * 0b0..No overrun.
7141 * 0b1..Receive overrun (new LPUART data lost).
7142 */
7143#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
7144#define LPUART_STAT_IDLE_MASK (0x100000U)
7145#define LPUART_STAT_IDLE_SHIFT (20U)
7146/*! IDLE - Idle Line Flag
7147 * 0b0..No idle line detected.
7148 * 0b1..Idle line was detected.
7149 */
7150#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
7151#define LPUART_STAT_RDRF_MASK (0x200000U)
7152#define LPUART_STAT_RDRF_SHIFT (21U)
7153/*! RDRF - Receive Data Register Full Flag
7154 * 0b0..Receive data buffer empty.
7155 * 0b1..Receive data buffer full.
7156 */
7157#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
7158#define LPUART_STAT_TC_MASK (0x400000U)
7159#define LPUART_STAT_TC_SHIFT (22U)
7160/*! TC - Transmission Complete Flag
7161 * 0b0..Transmitter active (sending data, a preamble, or a break).
7162 * 0b1..Transmitter idle (transmission activity complete).
7163 */
7164#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
7165#define LPUART_STAT_TDRE_MASK (0x800000U)
7166#define LPUART_STAT_TDRE_SHIFT (23U)
7167/*! TDRE - Transmit Data Register Empty Flag
7168 * 0b0..Transmit data buffer full.
7169 * 0b1..Transmit data buffer empty.
7170 */
7171#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
7172#define LPUART_STAT_RAF_MASK (0x1000000U)
7173#define LPUART_STAT_RAF_SHIFT (24U)
7174/*! RAF - Receiver Active Flag
7175 * 0b0..LPUART receiver idle waiting for a start bit.
7176 * 0b1..LPUART receiver active (LPUART_RX input not idle).
7177 */
7178#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
7179#define LPUART_STAT_LBKDE_MASK (0x2000000U)
7180#define LPUART_STAT_LBKDE_SHIFT (25U)
7181/*! LBKDE - LIN Break Detection Enable
7182 * 0b0..Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
7183 * 0b1..Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
7184 */
7185#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
7186#define LPUART_STAT_BRK13_MASK (0x4000000U)
7187#define LPUART_STAT_BRK13_SHIFT (26U)
7188/*! BRK13 - Break Character Generation Length
7189 * 0b0..Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
7190 * 0b1..Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
7191 */
7192#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
7193#define LPUART_STAT_RWUID_MASK (0x8000000U)
7194#define LPUART_STAT_RWUID_SHIFT (27U)
7195/*! RWUID - Receive Wake Up Idle Detect
7196 * 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match.
7197 * 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match.
7198 */
7199#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
7200#define LPUART_STAT_RXINV_MASK (0x10000000U)
7201#define LPUART_STAT_RXINV_SHIFT (28U)
7202/*! RXINV - Receive Data Inversion
7203 * 0b0..Receive data not inverted.
7204 * 0b1..Receive data inverted.
7205 */
7206#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
7207#define LPUART_STAT_MSBF_MASK (0x20000000U)
7208#define LPUART_STAT_MSBF_SHIFT (29U)
7209/*! MSBF - MSB First
7210 * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
7211 * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
7212 */
7213#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
7214#define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
7215#define LPUART_STAT_RXEDGIF_SHIFT (30U)
7216/*! RXEDGIF - LPUART_RX Pin Active Edge Interrupt Flag
7217 * 0b0..No active edge on the receive pin has occurred.
7218 * 0b1..An active edge on the receive pin has occurred.
7219 */
7220#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
7221#define LPUART_STAT_LBKDIF_MASK (0x80000000U)
7222#define LPUART_STAT_LBKDIF_SHIFT (31U)
7223/*! LBKDIF - LIN Break Detect Interrupt Flag
7224 * 0b0..No LIN break character has been detected.
7225 * 0b1..LIN break character has been detected.
7226 */
7227#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
7228/*! @} */
7229
7230/*! @name CTRL - LPUART Control Register */
7231/*! @{ */
7232#define LPUART_CTRL_PT_MASK (0x1U)
7233#define LPUART_CTRL_PT_SHIFT (0U)
7234/*! PT - Parity Type
7235 * 0b0..Even parity.
7236 * 0b1..Odd parity.
7237 */
7238#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
7239#define LPUART_CTRL_PE_MASK (0x2U)
7240#define LPUART_CTRL_PE_SHIFT (1U)
7241/*! PE - Parity Enable
7242 * 0b0..No hardware parity generation or checking.
7243 * 0b1..Parity enabled.
7244 */
7245#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
7246#define LPUART_CTRL_ILT_MASK (0x4U)
7247#define LPUART_CTRL_ILT_SHIFT (2U)
7248/*! ILT - Idle Line Type Select
7249 * 0b0..Idle character bit count starts after start bit.
7250 * 0b1..Idle character bit count starts after stop bit.
7251 */
7252#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
7253#define LPUART_CTRL_WAKE_MASK (0x8U)
7254#define LPUART_CTRL_WAKE_SHIFT (3U)
7255/*! WAKE - Receiver Wakeup Method Select
7256 * 0b0..Configures RWU for idle-line wakeup.
7257 * 0b1..Configures RWU with address-mark wakeup.
7258 */
7259#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
7260#define LPUART_CTRL_M_MASK (0x10U)
7261#define LPUART_CTRL_M_SHIFT (4U)
7262/*! M - 9-Bit or 8-Bit Mode Select
7263 * 0b0..Receiver and transmitter use 8-bit data characters.
7264 * 0b1..Receiver and transmitter use 9-bit data characters.
7265 */
7266#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
7267#define LPUART_CTRL_RSRC_MASK (0x20U)
7268#define LPUART_CTRL_RSRC_SHIFT (5U)
7269/*! RSRC - Receiver Source Select
7270 * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin.
7271 * 0b1..Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input.
7272 */
7273#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
7274#define LPUART_CTRL_DOZEEN_MASK (0x40U)
7275#define LPUART_CTRL_DOZEEN_SHIFT (6U)
7276/*! DOZEEN - Doze Enable
7277 * 0b0..LPUART is enabled in Doze mode.
7278 * 0b1..LPUART is disabled in Doze mode.
7279 */
7280#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
7281#define LPUART_CTRL_LOOPS_MASK (0x80U)
7282#define LPUART_CTRL_LOOPS_SHIFT (7U)
7283/*! LOOPS - Loop Mode Select
7284 * 0b0..Normal operation - LPUART_RX and LPUART_TX use separate pins.
7285 * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
7286 */
7287#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
7288#define LPUART_CTRL_IDLECFG_MASK (0x700U)
7289#define LPUART_CTRL_IDLECFG_SHIFT (8U)
7290/*! IDLECFG - Idle Configuration
7291 * 0b000..1 idle character
7292 * 0b001..2 idle characters
7293 * 0b010..4 idle characters
7294 * 0b011..8 idle characters
7295 * 0b100..16 idle characters
7296 * 0b101..32 idle characters
7297 * 0b110..64 idle characters
7298 * 0b111..128 idle characters
7299 */
7300#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
7301#define LPUART_CTRL_MA2IE_MASK (0x4000U)
7302#define LPUART_CTRL_MA2IE_SHIFT (14U)
7303/*! MA2IE - Match 2 Interrupt Enable
7304 * 0b0..MA2F interrupt disabled
7305 * 0b1..MA2F interrupt enabled
7306 */
7307#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
7308#define LPUART_CTRL_MA1IE_MASK (0x8000U)
7309#define LPUART_CTRL_MA1IE_SHIFT (15U)
7310/*! MA1IE - Match 1 Interrupt Enable
7311 * 0b0..MA1F interrupt disabled
7312 * 0b1..MA1F interrupt enabled
7313 */
7314#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
7315#define LPUART_CTRL_SBK_MASK (0x10000U)
7316#define LPUART_CTRL_SBK_SHIFT (16U)
7317/*! SBK - Send Break
7318 * 0b0..Normal transmitter operation.
7319 * 0b1..Queue break character(s) to be sent.
7320 */
7321#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
7322#define LPUART_CTRL_RWU_MASK (0x20000U)
7323#define LPUART_CTRL_RWU_SHIFT (17U)
7324/*! RWU - Receiver Wakeup Control
7325 * 0b0..Normal receiver operation.
7326 * 0b1..LPUART receiver in standby waiting for wakeup condition.
7327 */
7328#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
7329#define LPUART_CTRL_RE_MASK (0x40000U)
7330#define LPUART_CTRL_RE_SHIFT (18U)
7331/*! RE - Receiver Enable
7332 * 0b0..Receiver disabled.
7333 * 0b1..Receiver enabled.
7334 */
7335#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
7336#define LPUART_CTRL_TE_MASK (0x80000U)
7337#define LPUART_CTRL_TE_SHIFT (19U)
7338/*! TE - Transmitter Enable
7339 * 0b0..Transmitter disabled.
7340 * 0b1..Transmitter enabled.
7341 */
7342#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
7343#define LPUART_CTRL_ILIE_MASK (0x100000U)
7344#define LPUART_CTRL_ILIE_SHIFT (20U)
7345/*! ILIE - Idle Line Interrupt Enable
7346 * 0b0..Hardware interrupts from IDLE disabled; use polling.
7347 * 0b1..Hardware interrupt requested when IDLE flag is 1.
7348 */
7349#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
7350#define LPUART_CTRL_RIE_MASK (0x200000U)
7351#define LPUART_CTRL_RIE_SHIFT (21U)
7352/*! RIE - Receiver Interrupt Enable
7353 * 0b0..Hardware interrupts from RDRF disabled; use polling.
7354 * 0b1..Hardware interrupt requested when RDRF flag is 1.
7355 */
7356#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
7357#define LPUART_CTRL_TCIE_MASK (0x400000U)
7358#define LPUART_CTRL_TCIE_SHIFT (22U)
7359/*! TCIE - Transmission Complete Interrupt Enable for
7360 * 0b0..Hardware interrupts from TC disabled; use polling.
7361 * 0b1..Hardware interrupt requested when TC flag is 1.
7362 */
7363#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
7364#define LPUART_CTRL_TIE_MASK (0x800000U)
7365#define LPUART_CTRL_TIE_SHIFT (23U)
7366/*! TIE - Transmit Interrupt Enable
7367 * 0b0..Hardware interrupts from TDRE disabled; use polling.
7368 * 0b1..Hardware interrupt requested when TDRE flag is 1.
7369 */
7370#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
7371#define LPUART_CTRL_PEIE_MASK (0x1000000U)
7372#define LPUART_CTRL_PEIE_SHIFT (24U)
7373/*! PEIE - Parity Error Interrupt Enable
7374 * 0b0..PF interrupts disabled; use polling).
7375 * 0b1..Hardware interrupt requested when PF is set.
7376 */
7377#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
7378#define LPUART_CTRL_FEIE_MASK (0x2000000U)
7379#define LPUART_CTRL_FEIE_SHIFT (25U)
7380/*! FEIE - Framing Error Interrupt Enable
7381 * 0b0..FE interrupts disabled; use polling.
7382 * 0b1..Hardware interrupt requested when FE is set.
7383 */
7384#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
7385#define LPUART_CTRL_NEIE_MASK (0x4000000U)
7386#define LPUART_CTRL_NEIE_SHIFT (26U)
7387/*! NEIE - Noise Error Interrupt Enable
7388 * 0b0..NF interrupts disabled; use polling.
7389 * 0b1..Hardware interrupt requested when NF is set.
7390 */
7391#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
7392#define LPUART_CTRL_ORIE_MASK (0x8000000U)
7393#define LPUART_CTRL_ORIE_SHIFT (27U)
7394/*! ORIE - Overrun Interrupt Enable
7395 * 0b0..OR interrupts disabled; use polling.
7396 * 0b1..Hardware interrupt requested when OR is set.
7397 */
7398#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
7399#define LPUART_CTRL_TXINV_MASK (0x10000000U)
7400#define LPUART_CTRL_TXINV_SHIFT (28U)
7401/*! TXINV - Transmit Data Inversion
7402 * 0b0..Transmit data not inverted.
7403 * 0b1..Transmit data inverted.
7404 */
7405#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
7406#define LPUART_CTRL_TXDIR_MASK (0x20000000U)
7407#define LPUART_CTRL_TXDIR_SHIFT (29U)
7408/*! TXDIR - LPUART_TX Pin Direction in Single-Wire Mode
7409 * 0b0..LPUART_TX pin is an input in single-wire mode.
7410 * 0b1..LPUART_TX pin is an output in single-wire mode.
7411 */
7412#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
7413#define LPUART_CTRL_R9T8_MASK (0x40000000U)
7414#define LPUART_CTRL_R9T8_SHIFT (30U)
7415#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
7416#define LPUART_CTRL_R8T9_MASK (0x80000000U)
7417#define LPUART_CTRL_R8T9_SHIFT (31U)
7418#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
7419/*! @} */
7420
7421/*! @name DATA - LPUART Data Register */
7422/*! @{ */
7423#define LPUART_DATA_R0T0_MASK (0x1U)
7424#define LPUART_DATA_R0T0_SHIFT (0U)
7425#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
7426#define LPUART_DATA_R1T1_MASK (0x2U)
7427#define LPUART_DATA_R1T1_SHIFT (1U)
7428#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
7429#define LPUART_DATA_R2T2_MASK (0x4U)
7430#define LPUART_DATA_R2T2_SHIFT (2U)
7431#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
7432#define LPUART_DATA_R3T3_MASK (0x8U)
7433#define LPUART_DATA_R3T3_SHIFT (3U)
7434#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
7435#define LPUART_DATA_R4T4_MASK (0x10U)
7436#define LPUART_DATA_R4T4_SHIFT (4U)
7437#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
7438#define LPUART_DATA_R5T5_MASK (0x20U)
7439#define LPUART_DATA_R5T5_SHIFT (5U)
7440#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
7441#define LPUART_DATA_R6T6_MASK (0x40U)
7442#define LPUART_DATA_R6T6_SHIFT (6U)
7443#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
7444#define LPUART_DATA_R7T7_MASK (0x80U)
7445#define LPUART_DATA_R7T7_SHIFT (7U)
7446#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
7447#define LPUART_DATA_R8T8_MASK (0x100U)
7448#define LPUART_DATA_R8T8_SHIFT (8U)
7449#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
7450#define LPUART_DATA_R9T9_MASK (0x200U)
7451#define LPUART_DATA_R9T9_SHIFT (9U)
7452#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
7453#define LPUART_DATA_IDLINE_MASK (0x800U)
7454#define LPUART_DATA_IDLINE_SHIFT (11U)
7455/*! IDLINE - Idle Line
7456 * 0b0..Receiver was not idle before receiving this character.
7457 * 0b1..Receiver was idle before receiving this character.
7458 */
7459#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
7460#define LPUART_DATA_RXEMPT_MASK (0x1000U)
7461#define LPUART_DATA_RXEMPT_SHIFT (12U)
7462/*! RXEMPT - Receive Buffer Empty
7463 * 0b0..Receive buffer contains valid data.
7464 * 0b1..Receive buffer is empty, data returned on read is not valid.
7465 */
7466#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
7467#define LPUART_DATA_FRETSC_MASK (0x2000U)
7468#define LPUART_DATA_FRETSC_SHIFT (13U)
7469/*! FRETSC - Frame Error / Transmit Special Character
7470 * 0b0..The dataword was received without a frame error on read, transmit a normal character on write.
7471 * 0b1..The dataword was received with a frame error, transmit an idle or break character on transmit.
7472 */
7473#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
7474#define LPUART_DATA_PARITYE_MASK (0x4000U)
7475#define LPUART_DATA_PARITYE_SHIFT (14U)
7476/*! PARITYE
7477 * 0b0..The dataword was received without a parity error.
7478 * 0b1..The dataword was received with a parity error.
7479 */
7480#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
7481#define LPUART_DATA_NOISY_MASK (0x8000U)
7482#define LPUART_DATA_NOISY_SHIFT (15U)
7483/*! NOISY
7484 * 0b0..The dataword was received without noise.
7485 * 0b1..The data was received with noise.
7486 */
7487#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
7488/*! @} */
7489
7490/*! @name MATCH - LPUART Match Address Register */
7491/*! @{ */
7492#define LPUART_MATCH_MA1_MASK (0x3FFU)
7493#define LPUART_MATCH_MA1_SHIFT (0U)
7494#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
7495#define LPUART_MATCH_MA2_MASK (0x3FF0000U)
7496#define LPUART_MATCH_MA2_SHIFT (16U)
7497#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
7498/*! @} */
7499
7500/*! @name MODIR - LPUART Modem IrDA Register */
7501/*! @{ */
7502#define LPUART_MODIR_TXCTSE_MASK (0x1U)
7503#define LPUART_MODIR_TXCTSE_SHIFT (0U)
7504/*! TXCTSE - Transmitter clear-to-send enable
7505 * 0b0..CTS has no effect on the transmitter.
7506 * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
7507 */
7508#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
7509#define LPUART_MODIR_TXRTSE_MASK (0x2U)
7510#define LPUART_MODIR_TXRTSE_SHIFT (1U)
7511/*! TXRTSE - Transmitter request-to-send enable
7512 * 0b0..The transmitter has no effect on RTS.
7513 * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.
7514 */
7515#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
7516#define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
7517#define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
7518/*! TXRTSPOL - Transmitter request-to-send polarity
7519 * 0b0..Transmitter RTS is active low.
7520 * 0b1..Transmitter RTS is active high.
7521 */
7522#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
7523#define LPUART_MODIR_RXRTSE_MASK (0x8U)
7524#define LPUART_MODIR_RXRTSE_SHIFT (3U)
7525/*! RXRTSE - Receiver request-to-send enable
7526 * 0b0..The receiver has no effect on RTS.
7527 * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full.
7528 */
7529#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
7530#define LPUART_MODIR_TXCTSC_MASK (0x10U)
7531#define LPUART_MODIR_TXCTSC_SHIFT (4U)
7532/*! TXCTSC - Transmit CTS Configuration
7533 * 0b0..CTS input is sampled at the start of each character.
7534 * 0b1..CTS input is sampled when the transmitter is idle.
7535 */
7536#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
7537#define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
7538#define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
7539/*! TXCTSSRC - Transmit CTS Source
7540 * 0b0..CTS input is the LPUART_CTS pin.
7541 * 0b1..CTS input is the inverted Receiver Match result.
7542 */
7543#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
7544#define LPUART_MODIR_TNP_MASK (0x30000U)
7545#define LPUART_MODIR_TNP_SHIFT (16U)
7546/*! TNP - Transmitter narrow pulse
7547 * 0b00..1/OSR.
7548 * 0b01..2/OSR.
7549 * 0b10..3/OSR.
7550 * 0b11..4/OSR.
7551 */
7552#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
7553#define LPUART_MODIR_IREN_MASK (0x40000U)
7554#define LPUART_MODIR_IREN_SHIFT (18U)
7555/*! IREN - Infrared enable
7556 * 0b0..IR disabled.
7557 * 0b1..IR enabled.
7558 */
7559#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
7560/*! @} */
7561
7562
7563/*!
7564 * @}
7565 */ /* end of group LPUART_Register_Masks */
7566
7567
7568/* LPUART - Peripheral instance base addresses */
7569/** Peripheral LPUART0 base address */
7570#define LPUART0_BASE (0x4002A000u)
7571/** Peripheral LPUART0 base pointer */
7572#define LPUART0 ((LPUART_Type *)LPUART0_BASE)
7573/** Array initializer of LPUART peripheral base addresses */
7574#define LPUART_BASE_ADDRS { LPUART0_BASE }
7575/** Array initializer of LPUART peripheral base pointers */
7576#define LPUART_BASE_PTRS { LPUART0 }
7577/** Interrupt vectors for the LPUART peripheral type */
7578#define LPUART_RX_TX_IRQS { LPUART0_IRQn }
7579#define LPUART_ERR_IRQS { LPUART0_IRQn }
7580
7581/*!
7582 * @}
7583 */ /* end of group LPUART_Peripheral_Access_Layer */
7584
7585
7586/* ----------------------------------------------------------------------------
7587 -- MCG Peripheral Access Layer
7588 ---------------------------------------------------------------------------- */
7589
7590/*!
7591 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
7592 * @{
7593 */
7594
7595/** MCG - Register Layout Typedef */
7596typedef struct {
7597 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
7598 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
7599 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
7600 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
7601 uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
7602 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
7603 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
7604 uint8_t RESERVED_0[1];
7605 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
7606 uint8_t RESERVED_1[1];
7607 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
7608 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
7609 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
7610 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
7611} MCG_Type;
7612
7613/* ----------------------------------------------------------------------------
7614 -- MCG Register Masks
7615 ---------------------------------------------------------------------------- */
7616
7617/*!
7618 * @addtogroup MCG_Register_Masks MCG Register Masks
7619 * @{
7620 */
7621
7622/*! @name C1 - MCG Control 1 Register */
7623/*! @{ */
7624#define MCG_C1_IREFSTEN_MASK (0x1U)
7625#define MCG_C1_IREFSTEN_SHIFT (0U)
7626/*! IREFSTEN - Internal Reference Stop Enable
7627 * 0b0..Internal reference clock is disabled in Stop mode.
7628 * 0b1..Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
7629 */
7630#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
7631#define MCG_C1_IRCLKEN_MASK (0x2U)
7632#define MCG_C1_IRCLKEN_SHIFT (1U)
7633/*! IRCLKEN - Internal Reference Clock Enable
7634 * 0b0..MCGIRCLK inactive.
7635 * 0b1..MCGIRCLK active.
7636 */
7637#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
7638#define MCG_C1_IREFS_MASK (0x4U)
7639#define MCG_C1_IREFS_SHIFT (2U)
7640/*! IREFS - Internal Reference Select
7641 * 0b0..External reference clock is selected.
7642 * 0b1..The slow internal reference clock is selected.
7643 */
7644#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
7645#define MCG_C1_FRDIV_MASK (0x38U)
7646#define MCG_C1_FRDIV_SHIFT (3U)
7647/*! FRDIV - FLL External Reference Divider
7648 * 0b000..If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32.
7649 * 0b001..If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64.
7650 * 0b010..If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128.
7651 * 0b011..If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
7652 * 0b100..If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512.
7653 * 0b101..If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024.
7654 * 0b110..If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 .
7655 * 0b111..If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .
7656 */
7657#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
7658#define MCG_C1_CLKS_MASK (0xC0U)
7659#define MCG_C1_CLKS_SHIFT (6U)
7660/*! CLKS - Clock Source Select
7661 * 0b00..Encoding 0 - Output of FLL is selected.
7662 * 0b01..Encoding 1 - Internal reference clock is selected.
7663 * 0b10..Encoding 2 - External reference clock is selected.
7664 * 0b11..Encoding 3 - Reserved.
7665 */
7666#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
7667/*! @} */
7668
7669/*! @name C2 - MCG Control 2 Register */
7670/*! @{ */
7671#define MCG_C2_IRCS_MASK (0x1U)
7672#define MCG_C2_IRCS_SHIFT (0U)
7673/*! IRCS - Internal Reference Clock Select
7674 * 0b0..Slow internal reference clock selected.
7675 * 0b1..Fast internal reference clock selected.
7676 */
7677#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
7678#define MCG_C2_LP_MASK (0x2U)
7679#define MCG_C2_LP_SHIFT (1U)
7680/*! LP - Low Power Select
7681 * 0b0..FLL is not disabled in bypass modes.
7682 * 0b1..FLL is disabled in bypass modes (lower power)
7683 */
7684#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
7685#define MCG_C2_EREFS_MASK (0x4U)
7686#define MCG_C2_EREFS_SHIFT (2U)
7687/*! EREFS - External Reference Select
7688 * 0b0..External reference clock requested.
7689 * 0b1..Oscillator requested.
7690 */
7691#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
7692#define MCG_C2_HGO_MASK (0x8U)
7693#define MCG_C2_HGO_SHIFT (3U)
7694/*! HGO - High Gain Oscillator Select
7695 * 0b0..Configure crystal oscillator for low-power operation.
7696 * 0b1..Configure crystal oscillator for high-gain operation.
7697 */
7698#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
7699#define MCG_C2_RANGE_MASK (0x30U)
7700#define MCG_C2_RANGE_SHIFT (4U)
7701/*! RANGE - Frequency Range Select
7702 * 0b00..Encoding 0 - Low frequency range selected for the crystal oscillator .
7703 * 0b01..Encoding 1 - High frequency range selected for the crystal oscillator .
7704 * 0b1x..Encoding 2 - Very high frequency range selected for the crystal oscillator .
7705 */
7706#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
7707#define MCG_C2_FCFTRIM_MASK (0x40U)
7708#define MCG_C2_FCFTRIM_SHIFT (6U)
7709#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
7710#define MCG_C2_LOCRE0_MASK (0x80U)
7711#define MCG_C2_LOCRE0_SHIFT (7U)
7712/*! LOCRE0 - Loss of Clock Reset Enable
7713 * 0b0..Interrupt request is generated on a loss of OSC0 external reference clock.
7714 * 0b1..Generate a reset request on a loss of OSC0 external reference clock.
7715 */
7716#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
7717/*! @} */
7718
7719/*! @name C3 - MCG Control 3 Register */
7720/*! @{ */
7721#define MCG_C3_SCTRIM_MASK (0xFFU)
7722#define MCG_C3_SCTRIM_SHIFT (0U)
7723#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
7724/*! @} */
7725
7726/*! @name C4 - MCG Control 4 Register */
7727/*! @{ */
7728#define MCG_C4_SCFTRIM_MASK (0x1U)
7729#define MCG_C4_SCFTRIM_SHIFT (0U)
7730#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
7731#define MCG_C4_FCTRIM_MASK (0x1EU)
7732#define MCG_C4_FCTRIM_SHIFT (1U)
7733#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
7734#define MCG_C4_DRST_DRS_MASK (0x60U)
7735#define MCG_C4_DRST_DRS_SHIFT (5U)
7736/*! DRST_DRS - DCO Range Select
7737 * 0b00..Encoding 0 - Low range (reset default).
7738 * 0b01..Encoding 1 - Mid range.
7739 * 0b10..Encoding 2 - Mid-high range.
7740 * 0b11..Encoding 3 - High range.
7741 */
7742#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
7743#define MCG_C4_DMX32_MASK (0x80U)
7744#define MCG_C4_DMX32_SHIFT (7U)
7745/*! DMX32 - DCO Maximum Frequency with 32.768 kHz Reference
7746 * 0b0..DCO has a default range of 25%.
7747 * 0b1..DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
7748 */
7749#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
7750/*! @} */
7751
7752/*! @name C6 - MCG Control 6 Register */
7753/*! @{ */
7754#define MCG_C6_CME_MASK (0x20U)
7755#define MCG_C6_CME_SHIFT (5U)
7756/*! CME - Clock Monitor Enable
7757 * 0b0..External clock monitor is disabled.
7758 * 0b1..Generate a reset request on loss of external clock.
7759 */
7760#define MCG_C6_CME(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME_SHIFT)) & MCG_C6_CME_MASK)
7761/*! @} */
7762
7763/*! @name S - MCG Status Register */
7764/*! @{ */
7765#define MCG_S_IRCST_MASK (0x1U)
7766#define MCG_S_IRCST_SHIFT (0U)
7767/*! IRCST - Internal Reference Clock Status
7768 * 0b0..Source of internal reference clock is the slow clock (32 kHz IRC).
7769 * 0b1..Source of internal reference clock is the fast clock (4 MHz IRC).
7770 */
7771#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
7772#define MCG_S_OSCINIT0_MASK (0x2U)
7773#define MCG_S_OSCINIT0_SHIFT (1U)
7774#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
7775#define MCG_S_CLKST_MASK (0xCU)
7776#define MCG_S_CLKST_SHIFT (2U)
7777/*! CLKST - Clock Mode Status
7778 * 0b00..Encoding 0 - Output of the FLL is selected (reset default).
7779 * 0b01..Encoding 1 - Internal reference clock is selected.
7780 * 0b10..Encoding 2 - External reference clock is selected.
7781 * 0b11..Reserved.
7782 */
7783#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
7784#define MCG_S_IREFST_MASK (0x10U)
7785#define MCG_S_IREFST_SHIFT (4U)
7786/*! IREFST - Internal Reference Status
7787 * 0b0..Source of FLL reference clock is the external reference clock.
7788 * 0b1..Source of FLL reference clock is the internal reference clock.
7789 */
7790#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
7791/*! @} */
7792
7793/*! @name SC - MCG Status and Control Register */
7794/*! @{ */
7795#define MCG_SC_LOCS0_MASK (0x1U)
7796#define MCG_SC_LOCS0_SHIFT (0U)
7797/*! LOCS0 - OSC0 Loss of Clock Status
7798 * 0b0..Loss of OSC0 has not occurred.
7799 * 0b1..Loss of OSC0 has occurred.
7800 */
7801#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
7802#define MCG_SC_FCRDIV_MASK (0xEU)
7803#define MCG_SC_FCRDIV_SHIFT (1U)
7804/*! FCRDIV - Fast Clock Internal Reference Divider
7805 * 0b000..Divide Factor is 1
7806 * 0b001..Divide Factor is 2.
7807 * 0b010..Divide Factor is 4.
7808 * 0b011..Divide Factor is 8.
7809 * 0b100..Divide Factor is 16
7810 * 0b101..Divide Factor is 32
7811 * 0b110..Divide Factor is 64
7812 * 0b111..Divide Factor is 128.
7813 */
7814#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
7815#define MCG_SC_FLTPRSRV_MASK (0x10U)
7816#define MCG_SC_FLTPRSRV_SHIFT (4U)
7817/*! FLTPRSRV - FLL Filter Preserve Enable
7818 * 0b0..FLL filter and FLL frequency will reset on changes to currect clock mode.
7819 * 0b1..Fll filter and FLL frequency retain their previous values during new clock mode change.
7820 */
7821#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
7822#define MCG_SC_ATMF_MASK (0x20U)
7823#define MCG_SC_ATMF_SHIFT (5U)
7824/*! ATMF - Automatic Trim Machine Fail Flag
7825 * 0b0..Automatic Trim Machine completed normally.
7826 * 0b1..Automatic Trim Machine failed.
7827 */
7828#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
7829#define MCG_SC_ATMS_MASK (0x40U)
7830#define MCG_SC_ATMS_SHIFT (6U)
7831/*! ATMS - Automatic Trim Machine Select
7832 * 0b0..32 kHz Internal Reference Clock selected.
7833 * 0b1..4 MHz Internal Reference Clock selected.
7834 */
7835#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
7836#define MCG_SC_ATME_MASK (0x80U)
7837#define MCG_SC_ATME_SHIFT (7U)
7838/*! ATME - Automatic Trim Machine Enable
7839 * 0b0..Auto Trim Machine disabled.
7840 * 0b1..Auto Trim Machine enabled.
7841 */
7842#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
7843/*! @} */
7844
7845/*! @name ATCVH - MCG Auto Trim Compare Value High Register */
7846/*! @{ */
7847#define MCG_ATCVH_ATCVH_MASK (0xFFU)
7848#define MCG_ATCVH_ATCVH_SHIFT (0U)
7849#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
7850/*! @} */
7851
7852/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
7853/*! @{ */
7854#define MCG_ATCVL_ATCVL_MASK (0xFFU)
7855#define MCG_ATCVL_ATCVL_SHIFT (0U)
7856#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
7857/*! @} */
7858
7859/*! @name C7 - MCG Control 7 Register */
7860/*! @{ */
7861#define MCG_C7_OSCSEL_MASK (0x3U)
7862#define MCG_C7_OSCSEL_SHIFT (0U)
7863/*! OSCSEL - MCG OSC Clock Select
7864 * 0b00..Selects Oscillator (OSCCLK0).
7865 * 0b01..Selects 32 kHz RTC Oscillator.
7866 * 0b10..Selects Oscillator (OSCCLK1).
7867 * 0b11..RESERVED
7868 */
7869#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
7870/*! @} */
7871
7872/*! @name C8 - MCG Control 8 Register */
7873/*! @{ */
7874#define MCG_C8_LOCS1_MASK (0x1U)
7875#define MCG_C8_LOCS1_SHIFT (0U)
7876/*! LOCS1 - RTC Loss of Clock Status
7877 * 0b0..Loss of RTC has not occur.
7878 * 0b1..Loss of RTC has occur
7879 */
7880#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
7881#define MCG_C8_CME1_MASK (0x20U)
7882#define MCG_C8_CME1_SHIFT (5U)
7883/*! CME1 - Clock Monitor Enable1
7884 * 0b0..External clock monitor is disabled for RTC clock.
7885 * 0b1..External clock monitor is enabled for RTC clock.
7886 */
7887#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
7888#define MCG_C8_LOCRE1_MASK (0x80U)
7889#define MCG_C8_LOCRE1_SHIFT (7U)
7890/*! LOCRE1 - Loss of Clock Reset Enable
7891 * 0b0..Interrupt request is generated on a loss of RTC external reference clock.
7892 * 0b1..Generate a reset request on a loss of RTC external reference clock
7893 */
7894#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
7895/*! @} */
7896
7897
7898/*!
7899 * @}
7900 */ /* end of group MCG_Register_Masks */
7901
7902
7903/* MCG - Peripheral instance base addresses */
7904/** Peripheral MCG base address */
7905#define MCG_BASE (0x40064000u)
7906/** Peripheral MCG base pointer */
7907#define MCG ((MCG_Type *)MCG_BASE)
7908/** Array initializer of MCG peripheral base addresses */
7909#define MCG_BASE_ADDRS { MCG_BASE }
7910/** Array initializer of MCG peripheral base pointers */
7911#define MCG_BASE_PTRS { MCG }
7912
7913/*!
7914 * @}
7915 */ /* end of group MCG_Peripheral_Access_Layer */
7916
7917
7918/* ----------------------------------------------------------------------------
7919 -- MCM Peripheral Access Layer
7920 ---------------------------------------------------------------------------- */
7921
7922/*!
7923 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
7924 * @{
7925 */
7926
7927/** MCM - Register Layout Typedef */
7928typedef struct {
7929 uint8_t RESERVED_0[8];
7930 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
7931 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
7932 __IO uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */
7933 __IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */
7934 uint8_t RESERVED_1[44];
7935 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
7936} MCM_Type;
7937
7938/* ----------------------------------------------------------------------------
7939 -- MCM Register Masks
7940 ---------------------------------------------------------------------------- */
7941
7942/*!
7943 * @addtogroup MCM_Register_Masks MCM Register Masks
7944 * @{
7945 */
7946
7947/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
7948/*! @{ */
7949#define MCM_PLASC_ASC_MASK (0xFFU)
7950#define MCM_PLASC_ASC_SHIFT (0U)
7951/*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
7952 * 0b00000000..A bus slave connection to AXBS input port n is absent
7953 * 0b00000001..A bus slave connection to AXBS input port n is present
7954 */
7955#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
7956/*! @} */
7957
7958/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
7959/*! @{ */
7960#define MCM_PLAMC_AMC_MASK (0xFFU)
7961#define MCM_PLAMC_AMC_SHIFT (0U)
7962/*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
7963 * 0b00000000..A bus master connection to AXBS input port n is absent
7964 * 0b00000001..A bus master connection to AXBS input port n is present
7965 */
7966#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
7967/*! @} */
7968
7969/*! @name PLACR - Crossbar Switch (AXBS) Control Register */
7970/*! @{ */
7971#define MCM_PLACR_ARB_MASK (0x200U)
7972#define MCM_PLACR_ARB_SHIFT (9U)
7973/*! ARB - Arbitration select
7974 * 0b0..Fixed-priority arbitration for the crossbar masters
7975 * 0b1..Round-robin arbitration for the crossbar masters
7976 */
7977#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
7978/*! @} */
7979
7980/*! @name ISCR - Interrupt Status and Control Register */
7981/*! @{ */
7982#define MCM_ISCR_FIOC_MASK (0x100U)
7983#define MCM_ISCR_FIOC_SHIFT (8U)
7984/*! FIOC - FPU invalid operation interrupt status
7985 * 0b0..No interrupt
7986 * 0b1..Interrupt occurred
7987 */
7988#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
7989#define MCM_ISCR_FDZC_MASK (0x200U)
7990#define MCM_ISCR_FDZC_SHIFT (9U)
7991/*! FDZC - FPU divide-by-zero interrupt status
7992 * 0b0..No interrupt
7993 * 0b1..Interrupt occurred
7994 */
7995#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
7996#define MCM_ISCR_FOFC_MASK (0x400U)
7997#define MCM_ISCR_FOFC_SHIFT (10U)
7998/*! FOFC - FPU overflow interrupt status
7999 * 0b0..No interrupt
8000 * 0b1..Interrupt occurred
8001 */
8002#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
8003#define MCM_ISCR_FUFC_MASK (0x800U)
8004#define MCM_ISCR_FUFC_SHIFT (11U)
8005/*! FUFC - FPU underflow interrupt status
8006 * 0b0..No interrupt
8007 * 0b1..Interrupt occurred
8008 */
8009#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
8010#define MCM_ISCR_FIXC_MASK (0x1000U)
8011#define MCM_ISCR_FIXC_SHIFT (12U)
8012/*! FIXC - FPU inexact interrupt status
8013 * 0b0..No interrupt
8014 * 0b1..Interrupt occurred
8015 */
8016#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
8017#define MCM_ISCR_FIDC_MASK (0x8000U)
8018#define MCM_ISCR_FIDC_SHIFT (15U)
8019/*! FIDC - FPU input denormal interrupt status
8020 * 0b0..No interrupt
8021 * 0b1..Interrupt occurred
8022 */
8023#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
8024#define MCM_ISCR_FIOCE_MASK (0x1000000U)
8025#define MCM_ISCR_FIOCE_SHIFT (24U)
8026/*! FIOCE - FPU invalid operation interrupt enable
8027 * 0b0..Disable interrupt
8028 * 0b1..Enable interrupt
8029 */
8030#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
8031#define MCM_ISCR_FDZCE_MASK (0x2000000U)
8032#define MCM_ISCR_FDZCE_SHIFT (25U)
8033/*! FDZCE - FPU divide-by-zero interrupt enable
8034 * 0b0..Disable interrupt
8035 * 0b1..Enable interrupt
8036 */
8037#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
8038#define MCM_ISCR_FOFCE_MASK (0x4000000U)
8039#define MCM_ISCR_FOFCE_SHIFT (26U)
8040/*! FOFCE - FPU overflow interrupt enable
8041 * 0b0..Disable interrupt
8042 * 0b1..Enable interrupt
8043 */
8044#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
8045#define MCM_ISCR_FUFCE_MASK (0x8000000U)
8046#define MCM_ISCR_FUFCE_SHIFT (27U)
8047/*! FUFCE - FPU underflow interrupt enable
8048 * 0b0..Disable interrupt
8049 * 0b1..Enable interrupt
8050 */
8051#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
8052#define MCM_ISCR_FIXCE_MASK (0x10000000U)
8053#define MCM_ISCR_FIXCE_SHIFT (28U)
8054/*! FIXCE - FPU inexact interrupt enable
8055 * 0b0..Disable interrupt
8056 * 0b1..Enable interrupt
8057 */
8058#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
8059#define MCM_ISCR_FIDCE_MASK (0x80000000U)
8060#define MCM_ISCR_FIDCE_SHIFT (31U)
8061/*! FIDCE - FPU input denormal interrupt enable
8062 * 0b0..Disable interrupt
8063 * 0b1..Enable interrupt
8064 */
8065#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
8066/*! @} */
8067
8068/*! @name CPO - Compute Operation Control Register */
8069/*! @{ */
8070#define MCM_CPO_CPOREQ_MASK (0x1U)
8071#define MCM_CPO_CPOREQ_SHIFT (0U)
8072/*! CPOREQ - Compute Operation request
8073 * 0b0..Request is cleared.
8074 * 0b1..Request Compute Operation.
8075 */
8076#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
8077#define MCM_CPO_CPOACK_MASK (0x2U)
8078#define MCM_CPO_CPOACK_SHIFT (1U)
8079/*! CPOACK - Compute Operation acknowledge
8080 * 0b0..Compute operation entry has not completed or compute operation exit has completed.
8081 * 0b1..Compute operation entry has completed or compute operation exit has not completed.
8082 */
8083#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
8084#define MCM_CPO_CPOWOI_MASK (0x4U)
8085#define MCM_CPO_CPOWOI_SHIFT (2U)
8086/*! CPOWOI - Compute Operation wakeup on interrupt
8087 * 0b0..No effect.
8088 * 0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
8089 */
8090#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
8091/*! @} */
8092
8093
8094/*!
8095 * @}
8096 */ /* end of group MCM_Register_Masks */
8097
8098
8099/* MCM - Peripheral instance base addresses */
8100/** Peripheral MCM base address */
8101#define MCM_BASE (0xE0080000u)
8102/** Peripheral MCM base pointer */
8103#define MCM ((MCM_Type *)MCM_BASE)
8104/** Array initializer of MCM peripheral base addresses */
8105#define MCM_BASE_ADDRS { MCM_BASE }
8106/** Array initializer of MCM peripheral base pointers */
8107#define MCM_BASE_PTRS { MCM }
8108/** Interrupt vectors for the MCM peripheral type */
8109#define MCM_IRQS { MCM_IRQn }
8110
8111/*!
8112 * @}
8113 */ /* end of group MCM_Peripheral_Access_Layer */
8114
8115
8116/* ----------------------------------------------------------------------------
8117 -- NV Peripheral Access Layer
8118 ---------------------------------------------------------------------------- */
8119
8120/*!
8121 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
8122 * @{
8123 */
8124
8125/** NV - Register Layout Typedef */
8126typedef struct {
8127 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
8128 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
8129 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
8130 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
8131 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
8132 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
8133 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
8134 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
8135 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
8136 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
8137 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
8138 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
8139 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
8140 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
8141} NV_Type;
8142
8143/* ----------------------------------------------------------------------------
8144 -- NV Register Masks
8145 ---------------------------------------------------------------------------- */
8146
8147/*!
8148 * @addtogroup NV_Register_Masks NV Register Masks
8149 * @{
8150 */
8151
8152/*! @name BACKKEY3 - Backdoor Comparison Key 3. */
8153/*! @{ */
8154#define NV_BACKKEY3_KEY_MASK (0xFFU)
8155#define NV_BACKKEY3_KEY_SHIFT (0U)
8156#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
8157/*! @} */
8158
8159/*! @name BACKKEY2 - Backdoor Comparison Key 2. */
8160/*! @{ */
8161#define NV_BACKKEY2_KEY_MASK (0xFFU)
8162#define NV_BACKKEY2_KEY_SHIFT (0U)
8163#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
8164/*! @} */
8165
8166/*! @name BACKKEY1 - Backdoor Comparison Key 1. */
8167/*! @{ */
8168#define NV_BACKKEY1_KEY_MASK (0xFFU)
8169#define NV_BACKKEY1_KEY_SHIFT (0U)
8170#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
8171/*! @} */
8172
8173/*! @name BACKKEY0 - Backdoor Comparison Key 0. */
8174/*! @{ */
8175#define NV_BACKKEY0_KEY_MASK (0xFFU)
8176#define NV_BACKKEY0_KEY_SHIFT (0U)
8177#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
8178/*! @} */
8179
8180/*! @name BACKKEY7 - Backdoor Comparison Key 7. */
8181/*! @{ */
8182#define NV_BACKKEY7_KEY_MASK (0xFFU)
8183#define NV_BACKKEY7_KEY_SHIFT (0U)
8184#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
8185/*! @} */
8186
8187/*! @name BACKKEY6 - Backdoor Comparison Key 6. */
8188/*! @{ */
8189#define NV_BACKKEY6_KEY_MASK (0xFFU)
8190#define NV_BACKKEY6_KEY_SHIFT (0U)
8191#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
8192/*! @} */
8193
8194/*! @name BACKKEY5 - Backdoor Comparison Key 5. */
8195/*! @{ */
8196#define NV_BACKKEY5_KEY_MASK (0xFFU)
8197#define NV_BACKKEY5_KEY_SHIFT (0U)
8198#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
8199/*! @} */
8200
8201/*! @name BACKKEY4 - Backdoor Comparison Key 4. */
8202/*! @{ */
8203#define NV_BACKKEY4_KEY_MASK (0xFFU)
8204#define NV_BACKKEY4_KEY_SHIFT (0U)
8205#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
8206/*! @} */
8207
8208/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
8209/*! @{ */
8210#define NV_FPROT3_PROT_MASK (0xFFU)
8211#define NV_FPROT3_PROT_SHIFT (0U)
8212#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
8213/*! @} */
8214
8215/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
8216/*! @{ */
8217#define NV_FPROT2_PROT_MASK (0xFFU)
8218#define NV_FPROT2_PROT_SHIFT (0U)
8219#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
8220/*! @} */
8221
8222/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
8223/*! @{ */
8224#define NV_FPROT1_PROT_MASK (0xFFU)
8225#define NV_FPROT1_PROT_SHIFT (0U)
8226#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
8227/*! @} */
8228
8229/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
8230/*! @{ */
8231#define NV_FPROT0_PROT_MASK (0xFFU)
8232#define NV_FPROT0_PROT_SHIFT (0U)
8233#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
8234/*! @} */
8235
8236/*! @name FSEC - Non-volatile Flash Security Register */
8237/*! @{ */
8238#define NV_FSEC_SEC_MASK (0x3U)
8239#define NV_FSEC_SEC_SHIFT (0U)
8240/*! SEC - Flash Security
8241 * 0b10..MCU security status is unsecure
8242 * 0b11..MCU security status is secure
8243 */
8244#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
8245#define NV_FSEC_FSLACC_MASK (0xCU)
8246#define NV_FSEC_FSLACC_SHIFT (2U)
8247/*! FSLACC - Freescale Failure Analysis Access Code
8248 * 0b10..Freescale factory access denied
8249 * 0b11..Freescale factory access granted
8250 */
8251#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
8252#define NV_FSEC_MEEN_MASK (0x30U)
8253#define NV_FSEC_MEEN_SHIFT (4U)
8254/*! MEEN
8255 * 0b10..Mass erase is disabled
8256 * 0b11..Mass erase is enabled
8257 */
8258#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
8259#define NV_FSEC_KEYEN_MASK (0xC0U)
8260#define NV_FSEC_KEYEN_SHIFT (6U)
8261/*! KEYEN - Backdoor Key Security Enable
8262 * 0b10..Backdoor key access enabled
8263 * 0b11..Backdoor key access disabled
8264 */
8265#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
8266/*! @} */
8267
8268/*! @name FOPT - Non-volatile Flash Option Register */
8269/*! @{ */
8270#define NV_FOPT_LPBOOT_MASK (0x1U)
8271#define NV_FOPT_LPBOOT_SHIFT (0U)
8272/*! LPBOOT
8273 * 0b0..Low-power boot
8274 * 0b1..Normal boot
8275 */
8276#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
8277#define NV_FOPT_EZPORT_DIS_MASK (0x2U)
8278#define NV_FOPT_EZPORT_DIS_SHIFT (1U)
8279/*! EZPORT_DIS
8280 * 0b0..EzPort operation is disabled
8281 * 0b1..EzPort operation is enabled
8282 */
8283#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
8284#define NV_FOPT_NMI_DIS_MASK (0x4U)
8285#define NV_FOPT_NMI_DIS_SHIFT (2U)
8286/*! NMI_DIS
8287 * 0b0..NMI interrupts are always blocked
8288 * 0b1..NMI_b pin/interrupts reset default to enabled
8289 */
8290#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
8291#define NV_FOPT_FAST_INIT_MASK (0x20U)
8292#define NV_FOPT_FAST_INIT_SHIFT (5U)
8293/*! FAST_INIT
8294 * 0b0..Slower initialization
8295 * 0b1..Fast Initialization
8296 */
8297#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
8298/*! @} */
8299
8300
8301/*!
8302 * @}
8303 */ /* end of group NV_Register_Masks */
8304
8305
8306/* NV - Peripheral instance base addresses */
8307/** Peripheral FTFA_FlashConfig base address */
8308#define FTFA_FlashConfig_BASE (0x400u)
8309/** Peripheral FTFA_FlashConfig base pointer */
8310#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
8311/** Array initializer of NV peripheral base addresses */
8312#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
8313/** Array initializer of NV peripheral base pointers */
8314#define NV_BASE_PTRS { FTFA_FlashConfig }
8315
8316/*!
8317 * @}
8318 */ /* end of group NV_Peripheral_Access_Layer */
8319
8320
8321/* ----------------------------------------------------------------------------
8322 -- OSC Peripheral Access Layer
8323 ---------------------------------------------------------------------------- */
8324
8325/*!
8326 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
8327 * @{
8328 */
8329
8330/** OSC - Register Layout Typedef */
8331typedef struct {
8332 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
8333 uint8_t RESERVED_0[1];
8334 __IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */
8335} OSC_Type;
8336
8337/* ----------------------------------------------------------------------------
8338 -- OSC Register Masks
8339 ---------------------------------------------------------------------------- */
8340
8341/*!
8342 * @addtogroup OSC_Register_Masks OSC Register Masks
8343 * @{
8344 */
8345
8346/*! @name CR - OSC Control Register */
8347/*! @{ */
8348#define OSC_CR_SC16P_MASK (0x1U)
8349#define OSC_CR_SC16P_SHIFT (0U)
8350/*! SC16P - Oscillator 16 pF Capacitor Load Configure
8351 * 0b0..Disable the selection.
8352 * 0b1..Add 16 pF capacitor to the oscillator load.
8353 */
8354#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
8355#define OSC_CR_SC8P_MASK (0x2U)
8356#define OSC_CR_SC8P_SHIFT (1U)
8357/*! SC8P - Oscillator 8 pF Capacitor Load Configure
8358 * 0b0..Disable the selection.
8359 * 0b1..Add 8 pF capacitor to the oscillator load.
8360 */
8361#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
8362#define OSC_CR_SC4P_MASK (0x4U)
8363#define OSC_CR_SC4P_SHIFT (2U)
8364/*! SC4P - Oscillator 4 pF Capacitor Load Configure
8365 * 0b0..Disable the selection.
8366 * 0b1..Add 4 pF capacitor to the oscillator load.
8367 */
8368#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
8369#define OSC_CR_SC2P_MASK (0x8U)
8370#define OSC_CR_SC2P_SHIFT (3U)
8371/*! SC2P - Oscillator 2 pF Capacitor Load Configure
8372 * 0b0..Disable the selection.
8373 * 0b1..Add 2 pF capacitor to the oscillator load.
8374 */
8375#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
8376#define OSC_CR_EREFSTEN_MASK (0x20U)
8377#define OSC_CR_EREFSTEN_SHIFT (5U)
8378/*! EREFSTEN - External Reference Stop Enable
8379 * 0b0..External reference clock is disabled in Stop mode.
8380 * 0b1..External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.
8381 */
8382#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
8383#define OSC_CR_ERCLKEN_MASK (0x80U)
8384#define OSC_CR_ERCLKEN_SHIFT (7U)
8385/*! ERCLKEN - External Reference Enable
8386 * 0b0..External reference clock is inactive.
8387 * 0b1..External reference clock is enabled.
8388 */
8389#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
8390/*! @} */
8391
8392/*! @name DIV - OSC_DIV */
8393/*! @{ */
8394#define OSC_DIV_ERPS_MASK (0xC0U)
8395#define OSC_DIV_ERPS_SHIFT (6U)
8396/*! ERPS
8397 * 0b00..The divisor ratio is 1.
8398 * 0b01..The divisor ratio is 2.
8399 * 0b10..The divisor ratio is 4.
8400 * 0b11..The divisor ratio is 8.
8401 */
8402#define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x)) << OSC_DIV_ERPS_SHIFT)) & OSC_DIV_ERPS_MASK)
8403/*! @} */
8404
8405
8406/*!
8407 * @}
8408 */ /* end of group OSC_Register_Masks */
8409
8410
8411/* OSC - Peripheral instance base addresses */
8412/** Peripheral OSC base address */
8413#define OSC_BASE (0x40065000u)
8414/** Peripheral OSC base pointer */
8415#define OSC ((OSC_Type *)OSC_BASE)
8416/** Array initializer of OSC peripheral base addresses */
8417#define OSC_BASE_ADDRS { OSC_BASE }
8418/** Array initializer of OSC peripheral base pointers */
8419#define OSC_BASE_PTRS { OSC }
8420
8421/*!
8422 * @}
8423 */ /* end of group OSC_Peripheral_Access_Layer */
8424
8425
8426/* ----------------------------------------------------------------------------
8427 -- PDB Peripheral Access Layer
8428 ---------------------------------------------------------------------------- */
8429
8430/*!
8431 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
8432 * @{
8433 */
8434
8435/** PDB - Register Layout Typedef */
8436typedef struct {
8437 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
8438 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
8439 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
8440 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
8441 struct { /* offset: 0x10, array step: 0x28 */
8442 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
8443 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
8444 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
8445 uint8_t RESERVED_0[24];
8446 } CH[2];
8447 uint8_t RESERVED_0[240];
8448 struct { /* offset: 0x150, array step: 0x8 */
8449 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
8450 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
8451 } DAC[1];
8452 uint8_t RESERVED_1[56];
8453 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
8454 __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
8455} PDB_Type;
8456
8457/* ----------------------------------------------------------------------------
8458 -- PDB Register Masks
8459 ---------------------------------------------------------------------------- */
8460
8461/*!
8462 * @addtogroup PDB_Register_Masks PDB Register Masks
8463 * @{
8464 */
8465
8466/*! @name SC - Status and Control register */
8467/*! @{ */
8468#define PDB_SC_LDOK_MASK (0x1U)
8469#define PDB_SC_LDOK_SHIFT (0U)
8470#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
8471#define PDB_SC_CONT_MASK (0x2U)
8472#define PDB_SC_CONT_SHIFT (1U)
8473/*! CONT - Continuous Mode Enable
8474 * 0b0..PDB operation in One-Shot mode
8475 * 0b1..PDB operation in Continuous mode
8476 */
8477#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
8478#define PDB_SC_MULT_MASK (0xCU)
8479#define PDB_SC_MULT_SHIFT (2U)
8480/*! MULT - Multiplication Factor Select for Prescaler
8481 * 0b00..Multiplication factor is 1.
8482 * 0b01..Multiplication factor is 10.
8483 * 0b10..Multiplication factor is 20.
8484 * 0b11..Multiplication factor is 40.
8485 */
8486#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
8487#define PDB_SC_PDBIE_MASK (0x20U)
8488#define PDB_SC_PDBIE_SHIFT (5U)
8489/*! PDBIE - PDB Interrupt Enable
8490 * 0b0..PDB interrupt disabled.
8491 * 0b1..PDB interrupt enabled.
8492 */
8493#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
8494#define PDB_SC_PDBIF_MASK (0x40U)
8495#define PDB_SC_PDBIF_SHIFT (6U)
8496#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
8497#define PDB_SC_PDBEN_MASK (0x80U)
8498#define PDB_SC_PDBEN_SHIFT (7U)
8499/*! PDBEN - PDB Enable
8500 * 0b0..PDB disabled. Counter is off.
8501 * 0b1..PDB enabled.
8502 */
8503#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
8504#define PDB_SC_TRGSEL_MASK (0xF00U)
8505#define PDB_SC_TRGSEL_SHIFT (8U)
8506/*! TRGSEL - Trigger Input Source Select
8507 * 0b0000..Trigger-In 0 is selected.
8508 * 0b0001..Trigger-In 1 is selected.
8509 * 0b0010..Trigger-In 2 is selected.
8510 * 0b0011..Trigger-In 3 is selected.
8511 * 0b0100..Trigger-In 4 is selected.
8512 * 0b0101..Trigger-In 5 is selected.
8513 * 0b0110..Trigger-In 6 is selected.
8514 * 0b0111..Trigger-In 7 is selected.
8515 * 0b1000..Trigger-In 8 is selected.
8516 * 0b1001..Trigger-In 9 is selected.
8517 * 0b1010..Trigger-In 10 is selected.
8518 * 0b1011..Trigger-In 11 is selected.
8519 * 0b1100..Trigger-In 12 is selected.
8520 * 0b1101..Trigger-In 13 is selected.
8521 * 0b1110..Trigger-In 14 is selected.
8522 * 0b1111..Software trigger is selected.
8523 */
8524#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
8525#define PDB_SC_PRESCALER_MASK (0x7000U)
8526#define PDB_SC_PRESCALER_SHIFT (12U)
8527/*! PRESCALER - Prescaler Divider Select
8528 * 0b000..Counting uses the peripheral clock divided by multiplication factor selected by MULT.
8529 * 0b001..Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT.
8530 * 0b010..Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT.
8531 * 0b011..Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT.
8532 * 0b100..Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT.
8533 * 0b101..Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT.
8534 * 0b110..Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT.
8535 * 0b111..Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT.
8536 */
8537#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
8538#define PDB_SC_DMAEN_MASK (0x8000U)
8539#define PDB_SC_DMAEN_SHIFT (15U)
8540/*! DMAEN - DMA Enable
8541 * 0b0..DMA disabled.
8542 * 0b1..DMA enabled.
8543 */
8544#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
8545#define PDB_SC_SWTRIG_MASK (0x10000U)
8546#define PDB_SC_SWTRIG_SHIFT (16U)
8547#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
8548#define PDB_SC_PDBEIE_MASK (0x20000U)
8549#define PDB_SC_PDBEIE_SHIFT (17U)
8550/*! PDBEIE - PDB Sequence Error Interrupt Enable
8551 * 0b0..PDB sequence error interrupt disabled.
8552 * 0b1..PDB sequence error interrupt enabled.
8553 */
8554#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
8555#define PDB_SC_LDMOD_MASK (0xC0000U)
8556#define PDB_SC_LDMOD_SHIFT (18U)
8557/*! LDMOD - Load Mode Select
8558 * 0b00..The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK.
8559 * 0b01..The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK.
8560 * 0b10..The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK.
8561 * 0b11..The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK.
8562 */
8563#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
8564/*! @} */
8565
8566/*! @name MOD - Modulus register */
8567/*! @{ */
8568#define PDB_MOD_MOD_MASK (0xFFFFU)
8569#define PDB_MOD_MOD_SHIFT (0U)
8570#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
8571/*! @} */
8572
8573/*! @name CNT - Counter register */
8574/*! @{ */
8575#define PDB_CNT_CNT_MASK (0xFFFFU)
8576#define PDB_CNT_CNT_SHIFT (0U)
8577#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
8578/*! @} */
8579
8580/*! @name IDLY - Interrupt Delay register */
8581/*! @{ */
8582#define PDB_IDLY_IDLY_MASK (0xFFFFU)
8583#define PDB_IDLY_IDLY_SHIFT (0U)
8584#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
8585/*! @} */
8586
8587/*! @name C1 - Channel n Control register 1 */
8588/*! @{ */
8589#define PDB_C1_EN_MASK (0xFFU)
8590#define PDB_C1_EN_SHIFT (0U)
8591/*! EN - PDB Channel Pre-Trigger Enable
8592 * 0b00000000..PDB channel's corresponding pre-trigger disabled.
8593 * 0b00000001..PDB channel's corresponding pre-trigger enabled.
8594 */
8595#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
8596#define PDB_C1_TOS_MASK (0xFF00U)
8597#define PDB_C1_TOS_SHIFT (8U)
8598/*! TOS - PDB Channel Pre-Trigger Output Select
8599 * 0b00000000..PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
8600 * 0b00000001..PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
8601 */
8602#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
8603#define PDB_C1_BB_MASK (0xFF0000U)
8604#define PDB_C1_BB_SHIFT (16U)
8605/*! BB - PDB Channel Pre-Trigger Back-to-Back Operation Enable
8606 * 0b00000000..PDB channel's corresponding pre-trigger back-to-back operation disabled.
8607 * 0b00000001..PDB channel's corresponding pre-trigger back-to-back operation enabled.
8608 */
8609#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
8610/*! @} */
8611
8612/* The count of PDB_C1 */
8613#define PDB_C1_COUNT (2U)
8614
8615/*! @name S - Channel n Status register */
8616/*! @{ */
8617#define PDB_S_ERR_MASK (0xFFU)
8618#define PDB_S_ERR_SHIFT (0U)
8619/*! ERR - PDB Channel Sequence Error Flags
8620 * 0b00000000..Sequence error not detected on PDB channel's corresponding pre-trigger.
8621 * 0b00000001..Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.
8622 */
8623#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
8624#define PDB_S_CF_MASK (0xFF0000U)
8625#define PDB_S_CF_SHIFT (16U)
8626#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
8627/*! @} */
8628
8629/* The count of PDB_S */
8630#define PDB_S_COUNT (2U)
8631
8632/*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
8633/*! @{ */
8634#define PDB_DLY_DLY_MASK (0xFFFFU)
8635#define PDB_DLY_DLY_SHIFT (0U)
8636#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
8637/*! @} */
8638
8639/* The count of PDB_DLY */
8640#define PDB_DLY_COUNT (2U)
8641
8642/* The count of PDB_DLY */
8643#define PDB_DLY_COUNT2 (2U)
8644
8645/*! @name INTC - DAC Interval Trigger n Control register */
8646/*! @{ */
8647#define PDB_INTC_TOE_MASK (0x1U)
8648#define PDB_INTC_TOE_SHIFT (0U)
8649/*! TOE - DAC Interval Trigger Enable
8650 * 0b0..DAC interval trigger disabled.
8651 * 0b1..DAC interval trigger enabled.
8652 */
8653#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
8654#define PDB_INTC_EXT_MASK (0x2U)
8655#define PDB_INTC_EXT_SHIFT (1U)
8656/*! EXT - DAC External Trigger Input Enable
8657 * 0b0..DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
8658 * 0b1..DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger.
8659 */
8660#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
8661/*! @} */
8662
8663/* The count of PDB_INTC */
8664#define PDB_INTC_COUNT (1U)
8665
8666/*! @name INT - DAC Interval n register */
8667/*! @{ */
8668#define PDB_INT_INT_MASK (0xFFFFU)
8669#define PDB_INT_INT_SHIFT (0U)
8670#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
8671/*! @} */
8672
8673/* The count of PDB_INT */
8674#define PDB_INT_COUNT (1U)
8675
8676/*! @name POEN - Pulse-Out n Enable register */
8677/*! @{ */
8678#define PDB_POEN_POEN_MASK (0xFFU)
8679#define PDB_POEN_POEN_SHIFT (0U)
8680/*! POEN - PDB Pulse-Out Enable
8681 * 0b00000000..PDB Pulse-Out disabled
8682 * 0b00000001..PDB Pulse-Out enabled
8683 */
8684#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
8685/*! @} */
8686
8687/*! @name PODLY - Pulse-Out n Delay register */
8688/*! @{ */
8689#define PDB_PODLY_DLY2_MASK (0xFFFFU)
8690#define PDB_PODLY_DLY2_SHIFT (0U)
8691#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
8692#define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
8693#define PDB_PODLY_DLY1_SHIFT (16U)
8694#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
8695/*! @} */
8696
8697/* The count of PDB_PODLY */
8698#define PDB_PODLY_COUNT (2U)
8699
8700
8701/*!
8702 * @}
8703 */ /* end of group PDB_Register_Masks */
8704
8705
8706/* PDB - Peripheral instance base addresses */
8707/** Peripheral PDB0 base address */
8708#define PDB0_BASE (0x40036000u)
8709/** Peripheral PDB0 base pointer */
8710#define PDB0 ((PDB_Type *)PDB0_BASE)
8711/** Array initializer of PDB peripheral base addresses */
8712#define PDB_BASE_ADDRS { PDB0_BASE }
8713/** Array initializer of PDB peripheral base pointers */
8714#define PDB_BASE_PTRS { PDB0 }
8715/** Interrupt vectors for the PDB peripheral type */
8716#define PDB_IRQS { PDB0_IRQn }
8717
8718/*!
8719 * @}
8720 */ /* end of group PDB_Peripheral_Access_Layer */
8721
8722
8723/* ----------------------------------------------------------------------------
8724 -- PIT Peripheral Access Layer
8725 ---------------------------------------------------------------------------- */
8726
8727/*!
8728 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
8729 * @{
8730 */
8731
8732/** PIT - Register Layout Typedef */
8733typedef struct {
8734 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
8735 uint8_t RESERVED_0[252];
8736 struct { /* offset: 0x100, array step: 0x10 */
8737 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
8738 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
8739 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
8740 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
8741 } CHANNEL[4];
8742} PIT_Type;
8743
8744/* ----------------------------------------------------------------------------
8745 -- PIT Register Masks
8746 ---------------------------------------------------------------------------- */
8747
8748/*!
8749 * @addtogroup PIT_Register_Masks PIT Register Masks
8750 * @{
8751 */
8752
8753/*! @name MCR - PIT Module Control Register */
8754/*! @{ */
8755#define PIT_MCR_FRZ_MASK (0x1U)
8756#define PIT_MCR_FRZ_SHIFT (0U)
8757/*! FRZ - Freeze
8758 * 0b0..Timers continue to run in Debug mode.
8759 * 0b1..Timers are stopped in Debug mode.
8760 */
8761#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
8762#define PIT_MCR_MDIS_MASK (0x2U)
8763#define PIT_MCR_MDIS_SHIFT (1U)
8764/*! MDIS - Module Disable - (PIT section)
8765 * 0b0..Clock for standard PIT timers is enabled.
8766 * 0b1..Clock for standard PIT timers is disabled.
8767 */
8768#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
8769/*! @} */
8770
8771/*! @name LDVAL - Timer Load Value Register */
8772/*! @{ */
8773#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
8774#define PIT_LDVAL_TSV_SHIFT (0U)
8775#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
8776/*! @} */
8777
8778/* The count of PIT_LDVAL */
8779#define PIT_LDVAL_COUNT (4U)
8780
8781/*! @name CVAL - Current Timer Value Register */
8782/*! @{ */
8783#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
8784#define PIT_CVAL_TVL_SHIFT (0U)
8785#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
8786/*! @} */
8787
8788/* The count of PIT_CVAL */
8789#define PIT_CVAL_COUNT (4U)
8790
8791/*! @name TCTRL - Timer Control Register */
8792/*! @{ */
8793#define PIT_TCTRL_TEN_MASK (0x1U)
8794#define PIT_TCTRL_TEN_SHIFT (0U)
8795/*! TEN - Timer Enable
8796 * 0b0..Timer n is disabled.
8797 * 0b1..Timer n is enabled.
8798 */
8799#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
8800#define PIT_TCTRL_TIE_MASK (0x2U)
8801#define PIT_TCTRL_TIE_SHIFT (1U)
8802/*! TIE - Timer Interrupt Enable
8803 * 0b0..Interrupt requests from Timer n are disabled.
8804 * 0b1..Interrupt will be requested whenever TIF is set.
8805 */
8806#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
8807#define PIT_TCTRL_CHN_MASK (0x4U)
8808#define PIT_TCTRL_CHN_SHIFT (2U)
8809/*! CHN - Chain Mode
8810 * 0b0..Timer is not chained.
8811 * 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
8812 */
8813#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
8814/*! @} */
8815
8816/* The count of PIT_TCTRL */
8817#define PIT_TCTRL_COUNT (4U)
8818
8819/*! @name TFLG - Timer Flag Register */
8820/*! @{ */
8821#define PIT_TFLG_TIF_MASK (0x1U)
8822#define PIT_TFLG_TIF_SHIFT (0U)
8823/*! TIF - Timer Interrupt Flag
8824 * 0b0..Timeout has not yet occurred.
8825 * 0b1..Timeout has occurred.
8826 */
8827#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
8828/*! @} */
8829
8830/* The count of PIT_TFLG */
8831#define PIT_TFLG_COUNT (4U)
8832
8833
8834/*!
8835 * @}
8836 */ /* end of group PIT_Register_Masks */
8837
8838
8839/* PIT - Peripheral instance base addresses */
8840/** Peripheral PIT base address */
8841#define PIT_BASE (0x40037000u)
8842/** Peripheral PIT base pointer */
8843#define PIT ((PIT_Type *)PIT_BASE)
8844/** Array initializer of PIT peripheral base addresses */
8845#define PIT_BASE_ADDRS { PIT_BASE }
8846/** Array initializer of PIT peripheral base pointers */
8847#define PIT_BASE_PTRS { PIT }
8848/** Interrupt vectors for the PIT peripheral type */
8849#define PIT_IRQS { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
8850
8851/*!
8852 * @}
8853 */ /* end of group PIT_Peripheral_Access_Layer */
8854
8855
8856/* ----------------------------------------------------------------------------
8857 -- PMC Peripheral Access Layer
8858 ---------------------------------------------------------------------------- */
8859
8860/*!
8861 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
8862 * @{
8863 */
8864
8865/** PMC - Register Layout Typedef */
8866typedef struct {
8867 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
8868 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
8869 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
8870} PMC_Type;
8871
8872/* ----------------------------------------------------------------------------
8873 -- PMC Register Masks
8874 ---------------------------------------------------------------------------- */
8875
8876/*!
8877 * @addtogroup PMC_Register_Masks PMC Register Masks
8878 * @{
8879 */
8880
8881/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
8882/*! @{ */
8883#define PMC_LVDSC1_LVDV_MASK (0x3U)
8884#define PMC_LVDSC1_LVDV_SHIFT (0U)
8885/*! LVDV - Low-Voltage Detect Voltage Select
8886 * 0b00..Low trip point selected (V LVD = V LVDL )
8887 * 0b01..High trip point selected (V LVD = V LVDH )
8888 * 0b10..Reserved
8889 * 0b11..Reserved
8890 */
8891#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
8892#define PMC_LVDSC1_LVDRE_MASK (0x10U)
8893#define PMC_LVDSC1_LVDRE_SHIFT (4U)
8894/*! LVDRE - Low-Voltage Detect Reset Enable
8895 * 0b0..LVDF does not generate hardware resets
8896 * 0b1..Force an MCU reset when LVDF = 1
8897 */
8898#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
8899#define PMC_LVDSC1_LVDIE_MASK (0x20U)
8900#define PMC_LVDSC1_LVDIE_SHIFT (5U)
8901/*! LVDIE - Low-Voltage Detect Interrupt Enable
8902 * 0b0..Hardware interrupt disabled (use polling)
8903 * 0b1..Request a hardware interrupt when LVDF = 1
8904 */
8905#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
8906#define PMC_LVDSC1_LVDACK_MASK (0x40U)
8907#define PMC_LVDSC1_LVDACK_SHIFT (6U)
8908#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
8909#define PMC_LVDSC1_LVDF_MASK (0x80U)
8910#define PMC_LVDSC1_LVDF_SHIFT (7U)
8911/*! LVDF - Low-Voltage Detect Flag
8912 * 0b0..Low-voltage event not detected
8913 * 0b1..Low-voltage event detected
8914 */
8915#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
8916/*! @} */
8917
8918/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
8919/*! @{ */
8920#define PMC_LVDSC2_LVWV_MASK (0x3U)
8921#define PMC_LVDSC2_LVWV_SHIFT (0U)
8922/*! LVWV - Low-Voltage Warning Voltage Select
8923 * 0b00..Low trip point selected (VLVW = VLVW1)
8924 * 0b01..Mid 1 trip point selected (VLVW = VLVW2)
8925 * 0b10..Mid 2 trip point selected (VLVW = VLVW3)
8926 * 0b11..High trip point selected (VLVW = VLVW4)
8927 */
8928#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
8929#define PMC_LVDSC2_LVWIE_MASK (0x20U)
8930#define PMC_LVDSC2_LVWIE_SHIFT (5U)
8931/*! LVWIE - Low-Voltage Warning Interrupt Enable
8932 * 0b0..Hardware interrupt disabled (use polling)
8933 * 0b1..Request a hardware interrupt when LVWF = 1
8934 */
8935#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
8936#define PMC_LVDSC2_LVWACK_MASK (0x40U)
8937#define PMC_LVDSC2_LVWACK_SHIFT (6U)
8938#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
8939#define PMC_LVDSC2_LVWF_MASK (0x80U)
8940#define PMC_LVDSC2_LVWF_SHIFT (7U)
8941/*! LVWF - Low-Voltage Warning Flag
8942 * 0b0..Low-voltage warning event not detected
8943 * 0b1..Low-voltage warning event detected
8944 */
8945#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
8946/*! @} */
8947
8948/*! @name REGSC - Regulator Status And Control register */
8949/*! @{ */
8950#define PMC_REGSC_BGBE_MASK (0x1U)
8951#define PMC_REGSC_BGBE_SHIFT (0U)
8952/*! BGBE - Bandgap Buffer Enable
8953 * 0b0..Bandgap buffer not enabled
8954 * 0b1..Bandgap buffer enabled
8955 */
8956#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
8957#define PMC_REGSC_REGONS_MASK (0x4U)
8958#define PMC_REGSC_REGONS_SHIFT (2U)
8959/*! REGONS - Regulator In Run Regulation Status
8960 * 0b0..Regulator is in stop regulation or in transition to/from it
8961 * 0b1..Regulator is in run regulation
8962 */
8963#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
8964#define PMC_REGSC_ACKISO_MASK (0x8U)
8965#define PMC_REGSC_ACKISO_SHIFT (3U)
8966/*! ACKISO - Acknowledge Isolation
8967 * 0b0..Peripherals and I/O pads are in normal run state.
8968 * 0b1..Certain peripherals and I/O pads are in an isolated and latched state.
8969 */
8970#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
8971#define PMC_REGSC_BGEN_MASK (0x10U)
8972#define PMC_REGSC_BGEN_SHIFT (4U)
8973/*! BGEN - Bandgap Enable In VLPx Operation
8974 * 0b0..Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
8975 * 0b1..Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
8976 */
8977#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
8978/*! @} */
8979
8980
8981/*!
8982 * @}
8983 */ /* end of group PMC_Register_Masks */
8984
8985
8986/* PMC - Peripheral instance base addresses */
8987/** Peripheral PMC base address */
8988#define PMC_BASE (0x4007D000u)
8989/** Peripheral PMC base pointer */
8990#define PMC ((PMC_Type *)PMC_BASE)
8991/** Array initializer of PMC peripheral base addresses */
8992#define PMC_BASE_ADDRS { PMC_BASE }
8993/** Array initializer of PMC peripheral base pointers */
8994#define PMC_BASE_PTRS { PMC }
8995/** Interrupt vectors for the PMC peripheral type */
8996#define PMC_IRQS { LVD_LVW_IRQn }
8997
8998/*!
8999 * @}
9000 */ /* end of group PMC_Peripheral_Access_Layer */
9001
9002
9003/* ----------------------------------------------------------------------------
9004 -- PORT Peripheral Access Layer
9005 ---------------------------------------------------------------------------- */
9006
9007/*!
9008 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
9009 * @{
9010 */
9011
9012/** PORT - Register Layout Typedef */
9013typedef struct {
9014 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
9015 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
9016 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
9017 uint8_t RESERVED_0[24];
9018 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
9019 uint8_t RESERVED_1[28];
9020 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
9021 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
9022 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
9023} PORT_Type;
9024
9025/* ----------------------------------------------------------------------------
9026 -- PORT Register Masks
9027 ---------------------------------------------------------------------------- */
9028
9029/*!
9030 * @addtogroup PORT_Register_Masks PORT Register Masks
9031 * @{
9032 */
9033
9034/*! @name PCR - Pin Control Register n */
9035/*! @{ */
9036#define PORT_PCR_PS_MASK (0x1U)
9037#define PORT_PCR_PS_SHIFT (0U)
9038/*! PS - Pull Select
9039 * 0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
9040 * 0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
9041 */
9042#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
9043#define PORT_PCR_PE_MASK (0x2U)
9044#define PORT_PCR_PE_SHIFT (1U)
9045/*! PE - Pull Enable
9046 * 0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin.
9047 * 0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
9048 */
9049#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
9050#define PORT_PCR_SRE_MASK (0x4U)
9051#define PORT_PCR_SRE_SHIFT (2U)
9052/*! SRE - Slew Rate Enable
9053 * 0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
9054 * 0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
9055 */
9056#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
9057#define PORT_PCR_PFE_MASK (0x10U)
9058#define PORT_PCR_PFE_SHIFT (4U)
9059/*! PFE - Passive Filter Enable
9060 * 0b0..Passive input filter is disabled on the corresponding pin.
9061 * 0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
9062 */
9063#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
9064#define PORT_PCR_ODE_MASK (0x20U)
9065#define PORT_PCR_ODE_SHIFT (5U)
9066/*! ODE - Open Drain Enable
9067 * 0b0..Open drain output is disabled on the corresponding pin.
9068 * 0b1..Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
9069 */
9070#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
9071#define PORT_PCR_DSE_MASK (0x40U)
9072#define PORT_PCR_DSE_SHIFT (6U)
9073/*! DSE - Drive Strength Enable
9074 * 0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
9075 * 0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
9076 */
9077#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
9078#define PORT_PCR_MUX_MASK (0x700U)
9079#define PORT_PCR_MUX_SHIFT (8U)
9080/*! MUX - Pin Mux Control
9081 * 0b000..Pin disabled (analog).
9082 * 0b001..Alternative 1 (GPIO).
9083 * 0b010..Alternative 2 (chip-specific).
9084 * 0b011..Alternative 3 (chip-specific).
9085 * 0b100..Alternative 4 (chip-specific).
9086 * 0b101..Alternative 5 (chip-specific).
9087 * 0b110..Alternative 6 (chip-specific).
9088 * 0b111..Alternative 7 (chip-specific).
9089 */
9090#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
9091#define PORT_PCR_LK_MASK (0x8000U)
9092#define PORT_PCR_LK_SHIFT (15U)
9093/*! LK - Lock Register
9094 * 0b0..Pin Control Register fields [15:0] are not locked.
9095 * 0b1..Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
9096 */
9097#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
9098#define PORT_PCR_IRQC_MASK (0xF0000U)
9099#define PORT_PCR_IRQC_SHIFT (16U)
9100/*! IRQC - Interrupt Configuration
9101 * 0b0000..Interrupt/DMA request disabled.
9102 * 0b0001..DMA request on rising edge.
9103 * 0b0010..DMA request on falling edge.
9104 * 0b0011..DMA request on either edge.
9105 * 0b1000..Interrupt when logic 0.
9106 * 0b1001..Interrupt on rising-edge.
9107 * 0b1010..Interrupt on falling-edge.
9108 * 0b1011..Interrupt on either edge.
9109 * 0b1100..Interrupt when logic 1.
9110 */
9111#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
9112#define PORT_PCR_ISF_MASK (0x1000000U)
9113#define PORT_PCR_ISF_SHIFT (24U)
9114/*! ISF - Interrupt Status Flag
9115 * 0b0..Configured interrupt is not detected.
9116 * 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
9117 */
9118#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
9119/*! @} */
9120
9121/* The count of PORT_PCR */
9122#define PORT_PCR_COUNT (32U)
9123
9124/*! @name GPCLR - Global Pin Control Low Register */
9125/*! @{ */
9126#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
9127#define PORT_GPCLR_GPWD_SHIFT (0U)
9128#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
9129#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
9130#define PORT_GPCLR_GPWE_SHIFT (16U)
9131/*! GPWE - Global Pin Write Enable
9132 * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD.
9133 * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.
9134 */
9135#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
9136/*! @} */
9137
9138/*! @name GPCHR - Global Pin Control High Register */
9139/*! @{ */
9140#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
9141#define PORT_GPCHR_GPWD_SHIFT (0U)
9142#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
9143#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
9144#define PORT_GPCHR_GPWE_SHIFT (16U)
9145/*! GPWE - Global Pin Write Enable
9146 * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD.
9147 * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.
9148 */
9149#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
9150/*! @} */
9151
9152/*! @name ISFR - Interrupt Status Flag Register */
9153/*! @{ */
9154#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
9155#define PORT_ISFR_ISF_SHIFT (0U)
9156/*! ISF - Interrupt Status Flag
9157 * 0b00000000000000000000000000000000..Configured interrupt is not detected.
9158 * 0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
9159 */
9160#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
9161/*! @} */
9162
9163/*! @name DFER - Digital Filter Enable Register */
9164/*! @{ */
9165#define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
9166#define PORT_DFER_DFE_SHIFT (0U)
9167/*! DFE - Digital Filter Enable
9168 * 0b00000000000000000000000000000000..Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
9169 * 0b00000000000000000000000000000001..Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
9170 */
9171#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
9172/*! @} */
9173
9174/*! @name DFCR - Digital Filter Clock Register */
9175/*! @{ */
9176#define PORT_DFCR_CS_MASK (0x1U)
9177#define PORT_DFCR_CS_SHIFT (0U)
9178/*! CS - Clock Source
9179 * 0b0..Digital filters are clocked by the bus clock.
9180 * 0b1..Digital filters are clocked by the 1 kHz LPO clock.
9181 */
9182#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
9183/*! @} */
9184
9185/*! @name DFWR - Digital Filter Width Register */
9186/*! @{ */
9187#define PORT_DFWR_FILT_MASK (0x1FU)
9188#define PORT_DFWR_FILT_SHIFT (0U)
9189#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
9190/*! @} */
9191
9192
9193/*!
9194 * @}
9195 */ /* end of group PORT_Register_Masks */
9196
9197
9198/* PORT - Peripheral instance base addresses */
9199/** Peripheral PORTA base address */
9200#define PORTA_BASE (0x40049000u)
9201/** Peripheral PORTA base pointer */
9202#define PORTA ((PORT_Type *)PORTA_BASE)
9203/** Peripheral PORTB base address */
9204#define PORTB_BASE (0x4004A000u)
9205/** Peripheral PORTB base pointer */
9206#define PORTB ((PORT_Type *)PORTB_BASE)
9207/** Peripheral PORTC base address */
9208#define PORTC_BASE (0x4004B000u)
9209/** Peripheral PORTC base pointer */
9210#define PORTC ((PORT_Type *)PORTC_BASE)
9211/** Peripheral PORTD base address */
9212#define PORTD_BASE (0x4004C000u)
9213/** Peripheral PORTD base pointer */
9214#define PORTD ((PORT_Type *)PORTD_BASE)
9215/** Peripheral PORTE base address */
9216#define PORTE_BASE (0x4004D000u)
9217/** Peripheral PORTE base pointer */
9218#define PORTE ((PORT_Type *)PORTE_BASE)
9219/** Array initializer of PORT peripheral base addresses */
9220#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
9221/** Array initializer of PORT peripheral base pointers */
9222#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
9223/** Interrupt vectors for the PORT peripheral type */
9224#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
9225
9226/*!
9227 * @}
9228 */ /* end of group PORT_Peripheral_Access_Layer */
9229
9230
9231/* ----------------------------------------------------------------------------
9232 -- RCM Peripheral Access Layer
9233 ---------------------------------------------------------------------------- */
9234
9235/*!
9236 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
9237 * @{
9238 */
9239
9240/** RCM - Register Layout Typedef */
9241typedef struct {
9242 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
9243 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
9244 uint8_t RESERVED_0[2];
9245 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
9246 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
9247 uint8_t RESERVED_1[1];
9248 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
9249 __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
9250 __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
9251} RCM_Type;
9252
9253/* ----------------------------------------------------------------------------
9254 -- RCM Register Masks
9255 ---------------------------------------------------------------------------- */
9256
9257/*!
9258 * @addtogroup RCM_Register_Masks RCM Register Masks
9259 * @{
9260 */
9261
9262/*! @name SRS0 - System Reset Status Register 0 */
9263/*! @{ */
9264#define RCM_SRS0_WAKEUP_MASK (0x1U)
9265#define RCM_SRS0_WAKEUP_SHIFT (0U)
9266/*! WAKEUP - Low Leakage Wakeup Reset
9267 * 0b0..Reset not caused by LLWU module wakeup source
9268 * 0b1..Reset caused by LLWU module wakeup source
9269 */
9270#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
9271#define RCM_SRS0_LVD_MASK (0x2U)
9272#define RCM_SRS0_LVD_SHIFT (1U)
9273/*! LVD - Low-Voltage Detect Reset
9274 * 0b0..Reset not caused by LVD trip or POR
9275 * 0b1..Reset caused by LVD trip or POR
9276 */
9277#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
9278#define RCM_SRS0_LOC_MASK (0x4U)
9279#define RCM_SRS0_LOC_SHIFT (2U)
9280/*! LOC - Loss-of-Clock Reset
9281 * 0b0..Reset not caused by a loss of external clock.
9282 * 0b1..Reset caused by a loss of external clock.
9283 */
9284#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
9285#define RCM_SRS0_WDOG_MASK (0x20U)
9286#define RCM_SRS0_WDOG_SHIFT (5U)
9287/*! WDOG - Watchdog
9288 * 0b0..Reset not caused by watchdog timeout
9289 * 0b1..Reset caused by watchdog timeout
9290 */
9291#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
9292#define RCM_SRS0_PIN_MASK (0x40U)
9293#define RCM_SRS0_PIN_SHIFT (6U)
9294/*! PIN - External Reset Pin
9295 * 0b0..Reset not caused by external reset pin
9296 * 0b1..Reset caused by external reset pin
9297 */
9298#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
9299#define RCM_SRS0_POR_MASK (0x80U)
9300#define RCM_SRS0_POR_SHIFT (7U)
9301/*! POR - Power-On Reset
9302 * 0b0..Reset not caused by POR
9303 * 0b1..Reset caused by POR
9304 */
9305#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
9306/*! @} */
9307
9308/*! @name SRS1 - System Reset Status Register 1 */
9309/*! @{ */
9310#define RCM_SRS1_JTAG_MASK (0x1U)
9311#define RCM_SRS1_JTAG_SHIFT (0U)
9312/*! JTAG - JTAG Generated Reset
9313 * 0b0..Reset not caused by JTAG
9314 * 0b1..Reset caused by JTAG
9315 */
9316#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
9317#define RCM_SRS1_LOCKUP_MASK (0x2U)
9318#define RCM_SRS1_LOCKUP_SHIFT (1U)
9319/*! LOCKUP - Core Lockup
9320 * 0b0..Reset not caused by core LOCKUP event
9321 * 0b1..Reset caused by core LOCKUP event
9322 */
9323#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
9324#define RCM_SRS1_SW_MASK (0x4U)
9325#define RCM_SRS1_SW_SHIFT (2U)
9326/*! SW - Software
9327 * 0b0..Reset not caused by software setting of SYSRESETREQ bit
9328 * 0b1..Reset caused by software setting of SYSRESETREQ bit
9329 */
9330#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
9331#define RCM_SRS1_MDM_AP_MASK (0x8U)
9332#define RCM_SRS1_MDM_AP_SHIFT (3U)
9333/*! MDM_AP - MDM-AP System Reset Request
9334 * 0b0..Reset not caused by host debugger system setting of the System Reset Request bit
9335 * 0b1..Reset caused by host debugger system setting of the System Reset Request bit
9336 */
9337#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
9338#define RCM_SRS1_EZPT_MASK (0x10U)
9339#define RCM_SRS1_EZPT_SHIFT (4U)
9340/*! EZPT - EzPort Reset
9341 * 0b0..Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode
9342 * 0b1..Reset caused by EzPort receiving the RESET command while the device is in EzPort mode
9343 */
9344#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
9345#define RCM_SRS1_SACKERR_MASK (0x20U)
9346#define RCM_SRS1_SACKERR_SHIFT (5U)
9347/*! SACKERR - Stop Mode Acknowledge Error Reset
9348 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
9349 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
9350 */
9351#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
9352/*! @} */
9353
9354/*! @name RPFC - Reset Pin Filter Control register */
9355/*! @{ */
9356#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
9357#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
9358/*! RSTFLTSRW - Reset Pin Filter Select in Run and Wait Modes
9359 * 0b00..All filtering disabled
9360 * 0b01..Bus clock filter enabled for normal operation
9361 * 0b10..LPO clock filter enabled for normal operation
9362 * 0b11..Reserved
9363 */
9364#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
9365#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
9366#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
9367/*! RSTFLTSS - Reset Pin Filter Select in Stop Mode
9368 * 0b0..All filtering disabled
9369 * 0b1..LPO clock filter enabled
9370 */
9371#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
9372/*! @} */
9373
9374/*! @name RPFW - Reset Pin Filter Width register */
9375/*! @{ */
9376#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
9377#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
9378/*! RSTFLTSEL - Reset Pin Filter Bus Clock Select
9379 * 0b00000..Bus clock filter count is 1
9380 * 0b00001..Bus clock filter count is 2
9381 * 0b00010..Bus clock filter count is 3
9382 * 0b00011..Bus clock filter count is 4
9383 * 0b00100..Bus clock filter count is 5
9384 * 0b00101..Bus clock filter count is 6
9385 * 0b00110..Bus clock filter count is 7
9386 * 0b00111..Bus clock filter count is 8
9387 * 0b01000..Bus clock filter count is 9
9388 * 0b01001..Bus clock filter count is 10
9389 * 0b01010..Bus clock filter count is 11
9390 * 0b01011..Bus clock filter count is 12
9391 * 0b01100..Bus clock filter count is 13
9392 * 0b01101..Bus clock filter count is 14
9393 * 0b01110..Bus clock filter count is 15
9394 * 0b01111..Bus clock filter count is 16
9395 * 0b10000..Bus clock filter count is 17
9396 * 0b10001..Bus clock filter count is 18
9397 * 0b10010..Bus clock filter count is 19
9398 * 0b10011..Bus clock filter count is 20
9399 * 0b10100..Bus clock filter count is 21
9400 * 0b10101..Bus clock filter count is 22
9401 * 0b10110..Bus clock filter count is 23
9402 * 0b10111..Bus clock filter count is 24
9403 * 0b11000..Bus clock filter count is 25
9404 * 0b11001..Bus clock filter count is 26
9405 * 0b11010..Bus clock filter count is 27
9406 * 0b11011..Bus clock filter count is 28
9407 * 0b11100..Bus clock filter count is 29
9408 * 0b11101..Bus clock filter count is 30
9409 * 0b11110..Bus clock filter count is 31
9410 * 0b11111..Bus clock filter count is 32
9411 */
9412#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
9413/*! @} */
9414
9415/*! @name MR - Mode Register */
9416/*! @{ */
9417#define RCM_MR_EZP_MS_MASK (0x2U)
9418#define RCM_MR_EZP_MS_SHIFT (1U)
9419/*! EZP_MS - EZP_MS_B pin state
9420 * 0b0..Pin deasserted (logic 1)
9421 * 0b1..Pin asserted (logic 0)
9422 */
9423#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
9424/*! @} */
9425
9426/*! @name SSRS0 - Sticky System Reset Status Register 0 */
9427/*! @{ */
9428#define RCM_SSRS0_SWAKEUP_MASK (0x1U)
9429#define RCM_SSRS0_SWAKEUP_SHIFT (0U)
9430/*! SWAKEUP - Sticky Low Leakage Wakeup Reset
9431 * 0b0..Reset not caused by LLWU module wakeup source
9432 * 0b1..Reset caused by LLWU module wakeup source
9433 */
9434#define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
9435#define RCM_SSRS0_SLVD_MASK (0x2U)
9436#define RCM_SSRS0_SLVD_SHIFT (1U)
9437/*! SLVD - Sticky Low-Voltage Detect Reset
9438 * 0b0..Reset not caused by LVD trip or POR
9439 * 0b1..Reset caused by LVD trip or POR
9440 */
9441#define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
9442#define RCM_SSRS0_SLOC_MASK (0x4U)
9443#define RCM_SSRS0_SLOC_SHIFT (2U)
9444/*! SLOC - Sticky Loss-of-Clock Reset
9445 * 0b0..Reset not caused by a loss of external clock.
9446 * 0b1..Reset caused by a loss of external clock.
9447 */
9448#define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK)
9449#define RCM_SSRS0_SWDOG_MASK (0x20U)
9450#define RCM_SSRS0_SWDOG_SHIFT (5U)
9451/*! SWDOG - Sticky Watchdog
9452 * 0b0..Reset not caused by watchdog timeout
9453 * 0b1..Reset caused by watchdog timeout
9454 */
9455#define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
9456#define RCM_SSRS0_SPIN_MASK (0x40U)
9457#define RCM_SSRS0_SPIN_SHIFT (6U)
9458/*! SPIN - Sticky External Reset Pin
9459 * 0b0..Reset not caused by external reset pin
9460 * 0b1..Reset caused by external reset pin
9461 */
9462#define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
9463#define RCM_SSRS0_SPOR_MASK (0x80U)
9464#define RCM_SSRS0_SPOR_SHIFT (7U)
9465/*! SPOR - Sticky Power-On Reset
9466 * 0b0..Reset not caused by POR
9467 * 0b1..Reset caused by POR
9468 */
9469#define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
9470/*! @} */
9471
9472/*! @name SSRS1 - Sticky System Reset Status Register 1 */
9473/*! @{ */
9474#define RCM_SSRS1_SJTAG_MASK (0x1U)
9475#define RCM_SSRS1_SJTAG_SHIFT (0U)
9476/*! SJTAG - Sticky JTAG Generated Reset
9477 * 0b0..Reset not caused by JTAG
9478 * 0b1..Reset caused by JTAG
9479 */
9480#define RCM_SSRS1_SJTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK)
9481#define RCM_SSRS1_SLOCKUP_MASK (0x2U)
9482#define RCM_SSRS1_SLOCKUP_SHIFT (1U)
9483/*! SLOCKUP - Sticky Core Lockup
9484 * 0b0..Reset not caused by core LOCKUP event
9485 * 0b1..Reset caused by core LOCKUP event
9486 */
9487#define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
9488#define RCM_SSRS1_SSW_MASK (0x4U)
9489#define RCM_SSRS1_SSW_SHIFT (2U)
9490/*! SSW - Sticky Software
9491 * 0b0..Reset not caused by software setting of SYSRESETREQ bit
9492 * 0b1..Reset caused by software setting of SYSRESETREQ bit
9493 */
9494#define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
9495#define RCM_SSRS1_SMDM_AP_MASK (0x8U)
9496#define RCM_SSRS1_SMDM_AP_SHIFT (3U)
9497/*! SMDM_AP - Sticky MDM-AP System Reset Request
9498 * 0b0..Reset not caused by host debugger system setting of the System Reset Request bit
9499 * 0b1..Reset caused by host debugger system setting of the System Reset Request bit
9500 */
9501#define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
9502#define RCM_SSRS1_SEZPT_MASK (0x10U)
9503#define RCM_SSRS1_SEZPT_SHIFT (4U)
9504/*! SEZPT - Sticky EzPort Reset
9505 * 0b0..Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode
9506 * 0b1..Reset caused by EzPort receiving the RESET command while the device is in EzPort mode
9507 */
9508#define RCM_SSRS1_SEZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SEZPT_SHIFT)) & RCM_SSRS1_SEZPT_MASK)
9509#define RCM_SSRS1_SSACKERR_MASK (0x20U)
9510#define RCM_SSRS1_SSACKERR_SHIFT (5U)
9511/*! SSACKERR - Sticky Stop Mode Acknowledge Error Reset
9512 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
9513 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
9514 */
9515#define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
9516/*! @} */
9517
9518
9519/*!
9520 * @}
9521 */ /* end of group RCM_Register_Masks */
9522
9523
9524/* RCM - Peripheral instance base addresses */
9525/** Peripheral RCM base address */
9526#define RCM_BASE (0x4007F000u)
9527/** Peripheral RCM base pointer */
9528#define RCM ((RCM_Type *)RCM_BASE)
9529/** Array initializer of RCM peripheral base addresses */
9530#define RCM_BASE_ADDRS { RCM_BASE }
9531/** Array initializer of RCM peripheral base pointers */
9532#define RCM_BASE_PTRS { RCM }
9533
9534/*!
9535 * @}
9536 */ /* end of group RCM_Peripheral_Access_Layer */
9537
9538
9539/* ----------------------------------------------------------------------------
9540 -- RFSYS Peripheral Access Layer
9541 ---------------------------------------------------------------------------- */
9542
9543/*!
9544 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
9545 * @{
9546 */
9547
9548/** RFSYS - Register Layout Typedef */
9549typedef struct {
9550 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
9551} RFSYS_Type;
9552
9553/* ----------------------------------------------------------------------------
9554 -- RFSYS Register Masks
9555 ---------------------------------------------------------------------------- */
9556
9557/*!
9558 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
9559 * @{
9560 */
9561
9562/*! @name REG - Register file register */
9563/*! @{ */
9564#define RFSYS_REG_LL_MASK (0xFFU)
9565#define RFSYS_REG_LL_SHIFT (0U)
9566#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
9567#define RFSYS_REG_LH_MASK (0xFF00U)
9568#define RFSYS_REG_LH_SHIFT (8U)
9569#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
9570#define RFSYS_REG_HL_MASK (0xFF0000U)
9571#define RFSYS_REG_HL_SHIFT (16U)
9572#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
9573#define RFSYS_REG_HH_MASK (0xFF000000U)
9574#define RFSYS_REG_HH_SHIFT (24U)
9575#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
9576/*! @} */
9577
9578/* The count of RFSYS_REG */
9579#define RFSYS_REG_COUNT (8U)
9580
9581
9582/*!
9583 * @}
9584 */ /* end of group RFSYS_Register_Masks */
9585
9586
9587/* RFSYS - Peripheral instance base addresses */
9588/** Peripheral RFSYS base address */
9589#define RFSYS_BASE (0x40041000u)
9590/** Peripheral RFSYS base pointer */
9591#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
9592/** Array initializer of RFSYS peripheral base addresses */
9593#define RFSYS_BASE_ADDRS { RFSYS_BASE }
9594/** Array initializer of RFSYS peripheral base pointers */
9595#define RFSYS_BASE_PTRS { RFSYS }
9596
9597/*!
9598 * @}
9599 */ /* end of group RFSYS_Peripheral_Access_Layer */
9600
9601
9602/* ----------------------------------------------------------------------------
9603 -- RFVBAT Peripheral Access Layer
9604 ---------------------------------------------------------------------------- */
9605
9606/*!
9607 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
9608 * @{
9609 */
9610
9611/** RFVBAT - Register Layout Typedef */
9612typedef struct {
9613 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
9614} RFVBAT_Type;
9615
9616/* ----------------------------------------------------------------------------
9617 -- RFVBAT Register Masks
9618 ---------------------------------------------------------------------------- */
9619
9620/*!
9621 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
9622 * @{
9623 */
9624
9625/*! @name REG - VBAT register file register */
9626/*! @{ */
9627#define RFVBAT_REG_LL_MASK (0xFFU)
9628#define RFVBAT_REG_LL_SHIFT (0U)
9629#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
9630#define RFVBAT_REG_LH_MASK (0xFF00U)
9631#define RFVBAT_REG_LH_SHIFT (8U)
9632#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
9633#define RFVBAT_REG_HL_MASK (0xFF0000U)
9634#define RFVBAT_REG_HL_SHIFT (16U)
9635#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
9636#define RFVBAT_REG_HH_MASK (0xFF000000U)
9637#define RFVBAT_REG_HH_SHIFT (24U)
9638#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
9639/*! @} */
9640
9641/* The count of RFVBAT_REG */
9642#define RFVBAT_REG_COUNT (8U)
9643
9644
9645/*!
9646 * @}
9647 */ /* end of group RFVBAT_Register_Masks */
9648
9649
9650/* RFVBAT - Peripheral instance base addresses */
9651/** Peripheral RFVBAT base address */
9652#define RFVBAT_BASE (0x4003E000u)
9653/** Peripheral RFVBAT base pointer */
9654#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
9655/** Array initializer of RFVBAT peripheral base addresses */
9656#define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
9657/** Array initializer of RFVBAT peripheral base pointers */
9658#define RFVBAT_BASE_PTRS { RFVBAT }
9659
9660/*!
9661 * @}
9662 */ /* end of group RFVBAT_Peripheral_Access_Layer */
9663
9664
9665/* ----------------------------------------------------------------------------
9666 -- RTC Peripheral Access Layer
9667 ---------------------------------------------------------------------------- */
9668
9669/*!
9670 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
9671 * @{
9672 */
9673
9674/** RTC - Register Layout Typedef */
9675typedef struct {
9676 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
9677 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
9678 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
9679 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
9680 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
9681 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
9682 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
9683 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
9684 uint8_t RESERVED_0[2016];
9685 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
9686 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
9687} RTC_Type;
9688
9689/* ----------------------------------------------------------------------------
9690 -- RTC Register Masks
9691 ---------------------------------------------------------------------------- */
9692
9693/*!
9694 * @addtogroup RTC_Register_Masks RTC Register Masks
9695 * @{
9696 */
9697
9698/*! @name TSR - RTC Time Seconds Register */
9699/*! @{ */
9700#define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
9701#define RTC_TSR_TSR_SHIFT (0U)
9702#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
9703/*! @} */
9704
9705/*! @name TPR - RTC Time Prescaler Register */
9706/*! @{ */
9707#define RTC_TPR_TPR_MASK (0xFFFFU)
9708#define RTC_TPR_TPR_SHIFT (0U)
9709#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
9710/*! @} */
9711
9712/*! @name TAR - RTC Time Alarm Register */
9713/*! @{ */
9714#define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
9715#define RTC_TAR_TAR_SHIFT (0U)
9716#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
9717/*! @} */
9718
9719/*! @name TCR - RTC Time Compensation Register */
9720/*! @{ */
9721#define RTC_TCR_TCR_MASK (0xFFU)
9722#define RTC_TCR_TCR_SHIFT (0U)
9723/*! TCR - Time Compensation Register
9724 * 0b10000000..Time Prescaler Register overflows every 32896 clock cycles.
9725 * 0b11111111..Time Prescaler Register overflows every 32769 clock cycles.
9726 * 0b00000000..Time Prescaler Register overflows every 32768 clock cycles.
9727 * 0b00000001..Time Prescaler Register overflows every 32767 clock cycles.
9728 * 0b01111111..Time Prescaler Register overflows every 32641 clock cycles.
9729 */
9730#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
9731#define RTC_TCR_CIR_MASK (0xFF00U)
9732#define RTC_TCR_CIR_SHIFT (8U)
9733#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
9734#define RTC_TCR_TCV_MASK (0xFF0000U)
9735#define RTC_TCR_TCV_SHIFT (16U)
9736#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
9737#define RTC_TCR_CIC_MASK (0xFF000000U)
9738#define RTC_TCR_CIC_SHIFT (24U)
9739#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
9740/*! @} */
9741
9742/*! @name CR - RTC Control Register */
9743/*! @{ */
9744#define RTC_CR_SWR_MASK (0x1U)
9745#define RTC_CR_SWR_SHIFT (0U)
9746/*! SWR - Software Reset
9747 * 0b0..No effect.
9748 * 0b1..Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software explicitly clearing it.
9749 */
9750#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
9751#define RTC_CR_WPE_MASK (0x2U)
9752#define RTC_CR_WPE_SHIFT (1U)
9753/*! WPE - Wakeup Pin Enable
9754 * 0b0..Wakeup pin is disabled.
9755 * 0b1..Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.
9756 */
9757#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
9758#define RTC_CR_SUP_MASK (0x4U)
9759#define RTC_CR_SUP_SHIFT (2U)
9760/*! SUP - Supervisor Access
9761 * 0b0..Non-supervisor mode write accesses are not supported and generate a bus error.
9762 * 0b1..Non-supervisor mode write accesses are supported.
9763 */
9764#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
9765#define RTC_CR_UM_MASK (0x8U)
9766#define RTC_CR_UM_SHIFT (3U)
9767/*! UM - Update Mode
9768 * 0b0..Registers cannot be written when locked.
9769 * 0b1..Registers can be written when locked under limited conditions.
9770 */
9771#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
9772#define RTC_CR_WPS_MASK (0x10U)
9773#define RTC_CR_WPS_SHIFT (4U)
9774/*! WPS - Wakeup Pin Select
9775 * 0b0..Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on.
9776 * 0b1..Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals.
9777 */
9778#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
9779#define RTC_CR_OSCE_MASK (0x100U)
9780#define RTC_CR_OSCE_SHIFT (8U)
9781/*! OSCE - Oscillator Enable
9782 * 0b0..32.768 kHz oscillator is disabled.
9783 * 0b1..32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.
9784 */
9785#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
9786#define RTC_CR_CLKO_MASK (0x200U)
9787#define RTC_CR_CLKO_SHIFT (9U)
9788/*! CLKO - Clock Output
9789 * 0b0..The 32 kHz clock is output to other peripherals.
9790 * 0b1..The 32 kHz clock is not output to other peripherals.
9791 */
9792#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
9793#define RTC_CR_SC16P_MASK (0x400U)
9794#define RTC_CR_SC16P_SHIFT (10U)
9795/*! SC16P - Oscillator 16pF Load Configure
9796 * 0b0..Disable the load.
9797 * 0b1..Enable the additional load.
9798 */
9799#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
9800#define RTC_CR_SC8P_MASK (0x800U)
9801#define RTC_CR_SC8P_SHIFT (11U)
9802/*! SC8P - Oscillator 8pF Load Configure
9803 * 0b0..Disable the load.
9804 * 0b1..Enable the additional load.
9805 */
9806#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
9807#define RTC_CR_SC4P_MASK (0x1000U)
9808#define RTC_CR_SC4P_SHIFT (12U)
9809/*! SC4P - Oscillator 4pF Load Configure
9810 * 0b0..Disable the load.
9811 * 0b1..Enable the additional load.
9812 */
9813#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
9814#define RTC_CR_SC2P_MASK (0x2000U)
9815#define RTC_CR_SC2P_SHIFT (13U)
9816/*! SC2P - Oscillator 2pF Load Configure
9817 * 0b0..Disable the load.
9818 * 0b1..Enable the additional load.
9819 */
9820#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
9821/*! @} */
9822
9823/*! @name SR - RTC Status Register */
9824/*! @{ */
9825#define RTC_SR_TIF_MASK (0x1U)
9826#define RTC_SR_TIF_SHIFT (0U)
9827/*! TIF - Time Invalid Flag
9828 * 0b0..Time is valid.
9829 * 0b1..Time is invalid and time counter is read as zero.
9830 */
9831#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
9832#define RTC_SR_TOF_MASK (0x2U)
9833#define RTC_SR_TOF_SHIFT (1U)
9834/*! TOF - Time Overflow Flag
9835 * 0b0..Time overflow has not occurred.
9836 * 0b1..Time overflow has occurred and time counter is read as zero.
9837 */
9838#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
9839#define RTC_SR_TAF_MASK (0x4U)
9840#define RTC_SR_TAF_SHIFT (2U)
9841/*! TAF - Time Alarm Flag
9842 * 0b0..Time alarm has not occurred.
9843 * 0b1..Time alarm has occurred.
9844 */
9845#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
9846#define RTC_SR_TCE_MASK (0x10U)
9847#define RTC_SR_TCE_SHIFT (4U)
9848/*! TCE - Time Counter Enable
9849 * 0b0..Time counter is disabled.
9850 * 0b1..Time counter is enabled.
9851 */
9852#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
9853/*! @} */
9854
9855/*! @name LR - RTC Lock Register */
9856/*! @{ */
9857#define RTC_LR_TCL_MASK (0x8U)
9858#define RTC_LR_TCL_SHIFT (3U)
9859/*! TCL - Time Compensation Lock
9860 * 0b0..Time Compensation Register is locked and writes are ignored.
9861 * 0b1..Time Compensation Register is not locked and writes complete as normal.
9862 */
9863#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
9864#define RTC_LR_CRL_MASK (0x10U)
9865#define RTC_LR_CRL_SHIFT (4U)
9866/*! CRL - Control Register Lock
9867 * 0b0..Control Register is locked and writes are ignored.
9868 * 0b1..Control Register is not locked and writes complete as normal.
9869 */
9870#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
9871#define RTC_LR_SRL_MASK (0x20U)
9872#define RTC_LR_SRL_SHIFT (5U)
9873/*! SRL - Status Register Lock
9874 * 0b0..Status Register is locked and writes are ignored.
9875 * 0b1..Status Register is not locked and writes complete as normal.
9876 */
9877#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
9878#define RTC_LR_LRL_MASK (0x40U)
9879#define RTC_LR_LRL_SHIFT (6U)
9880/*! LRL - Lock Register Lock
9881 * 0b0..Lock Register is locked and writes are ignored.
9882 * 0b1..Lock Register is not locked and writes complete as normal.
9883 */
9884#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
9885/*! @} */
9886
9887/*! @name IER - RTC Interrupt Enable Register */
9888/*! @{ */
9889#define RTC_IER_TIIE_MASK (0x1U)
9890#define RTC_IER_TIIE_SHIFT (0U)
9891/*! TIIE - Time Invalid Interrupt Enable
9892 * 0b0..Time invalid flag does not generate an interrupt.
9893 * 0b1..Time invalid flag does generate an interrupt.
9894 */
9895#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
9896#define RTC_IER_TOIE_MASK (0x2U)
9897#define RTC_IER_TOIE_SHIFT (1U)
9898/*! TOIE - Time Overflow Interrupt Enable
9899 * 0b0..Time overflow flag does not generate an interrupt.
9900 * 0b1..Time overflow flag does generate an interrupt.
9901 */
9902#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
9903#define RTC_IER_TAIE_MASK (0x4U)
9904#define RTC_IER_TAIE_SHIFT (2U)
9905/*! TAIE - Time Alarm Interrupt Enable
9906 * 0b0..Time alarm flag does not generate an interrupt.
9907 * 0b1..Time alarm flag does generate an interrupt.
9908 */
9909#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
9910#define RTC_IER_TSIE_MASK (0x10U)
9911#define RTC_IER_TSIE_SHIFT (4U)
9912/*! TSIE - Time Seconds Interrupt Enable
9913 * 0b0..Seconds interrupt is disabled.
9914 * 0b1..Seconds interrupt is enabled.
9915 */
9916#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
9917#define RTC_IER_WPON_MASK (0x80U)
9918#define RTC_IER_WPON_SHIFT (7U)
9919/*! WPON - Wakeup Pin On
9920 * 0b0..No effect.
9921 * 0b1..If the wakeup pin is enabled, then the wakeup pin will assert.
9922 */
9923#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
9924/*! @} */
9925
9926/*! @name WAR - RTC Write Access Register */
9927/*! @{ */
9928#define RTC_WAR_TSRW_MASK (0x1U)
9929#define RTC_WAR_TSRW_SHIFT (0U)
9930/*! TSRW - Time Seconds Register Write
9931 * 0b0..Writes to the Time Seconds Register are ignored.
9932 * 0b1..Writes to the Time Seconds Register complete as normal.
9933 */
9934#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
9935#define RTC_WAR_TPRW_MASK (0x2U)
9936#define RTC_WAR_TPRW_SHIFT (1U)
9937/*! TPRW - Time Prescaler Register Write
9938 * 0b0..Writes to the Time Prescaler Register are ignored.
9939 * 0b1..Writes to the Time Prescaler Register complete as normal.
9940 */
9941#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
9942#define RTC_WAR_TARW_MASK (0x4U)
9943#define RTC_WAR_TARW_SHIFT (2U)
9944/*! TARW - Time Alarm Register Write
9945 * 0b0..Writes to the Time Alarm Register are ignored.
9946 * 0b1..Writes to the Time Alarm Register complete as normal.
9947 */
9948#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
9949#define RTC_WAR_TCRW_MASK (0x8U)
9950#define RTC_WAR_TCRW_SHIFT (3U)
9951/*! TCRW - Time Compensation Register Write
9952 * 0b0..Writes to the Time Compensation Register are ignored.
9953 * 0b1..Writes to the Time Compensation Register complete as normal.
9954 */
9955#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
9956#define RTC_WAR_CRW_MASK (0x10U)
9957#define RTC_WAR_CRW_SHIFT (4U)
9958/*! CRW - Control Register Write
9959 * 0b0..Writes to the Control Register are ignored.
9960 * 0b1..Writes to the Control Register complete as normal.
9961 */
9962#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
9963#define RTC_WAR_SRW_MASK (0x20U)
9964#define RTC_WAR_SRW_SHIFT (5U)
9965/*! SRW - Status Register Write
9966 * 0b0..Writes to the Status Register are ignored.
9967 * 0b1..Writes to the Status Register complete as normal.
9968 */
9969#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
9970#define RTC_WAR_LRW_MASK (0x40U)
9971#define RTC_WAR_LRW_SHIFT (6U)
9972/*! LRW - Lock Register Write
9973 * 0b0..Writes to the Lock Register are ignored.
9974 * 0b1..Writes to the Lock Register complete as normal.
9975 */
9976#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
9977#define RTC_WAR_IERW_MASK (0x80U)
9978#define RTC_WAR_IERW_SHIFT (7U)
9979/*! IERW - Interrupt Enable Register Write
9980 * 0b0..Writes to the Interupt Enable Register are ignored.
9981 * 0b1..Writes to the Interrupt Enable Register complete as normal.
9982 */
9983#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
9984/*! @} */
9985
9986/*! @name RAR - RTC Read Access Register */
9987/*! @{ */
9988#define RTC_RAR_TSRR_MASK (0x1U)
9989#define RTC_RAR_TSRR_SHIFT (0U)
9990/*! TSRR - Time Seconds Register Read
9991 * 0b0..Reads to the Time Seconds Register are ignored.
9992 * 0b1..Reads to the Time Seconds Register complete as normal.
9993 */
9994#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
9995#define RTC_RAR_TPRR_MASK (0x2U)
9996#define RTC_RAR_TPRR_SHIFT (1U)
9997/*! TPRR - Time Prescaler Register Read
9998 * 0b0..Reads to the Time Pprescaler Register are ignored.
9999 * 0b1..Reads to the Time Prescaler Register complete as normal.
10000 */
10001#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
10002#define RTC_RAR_TARR_MASK (0x4U)
10003#define RTC_RAR_TARR_SHIFT (2U)
10004/*! TARR - Time Alarm Register Read
10005 * 0b0..Reads to the Time Alarm Register are ignored.
10006 * 0b1..Reads to the Time Alarm Register complete as normal.
10007 */
10008#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
10009#define RTC_RAR_TCRR_MASK (0x8U)
10010#define RTC_RAR_TCRR_SHIFT (3U)
10011/*! TCRR - Time Compensation Register Read
10012 * 0b0..Reads to the Time Compensation Register are ignored.
10013 * 0b1..Reads to the Time Compensation Register complete as normal.
10014 */
10015#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
10016#define RTC_RAR_CRR_MASK (0x10U)
10017#define RTC_RAR_CRR_SHIFT (4U)
10018/*! CRR - Control Register Read
10019 * 0b0..Reads to the Control Register are ignored.
10020 * 0b1..Reads to the Control Register complete as normal.
10021 */
10022#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
10023#define RTC_RAR_SRR_MASK (0x20U)
10024#define RTC_RAR_SRR_SHIFT (5U)
10025/*! SRR - Status Register Read
10026 * 0b0..Reads to the Status Register are ignored.
10027 * 0b1..Reads to the Status Register complete as normal.
10028 */
10029#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
10030#define RTC_RAR_LRR_MASK (0x40U)
10031#define RTC_RAR_LRR_SHIFT (6U)
10032/*! LRR - Lock Register Read
10033 * 0b0..Reads to the Lock Register are ignored.
10034 * 0b1..Reads to the Lock Register complete as normal.
10035 */
10036#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
10037#define RTC_RAR_IERR_MASK (0x80U)
10038#define RTC_RAR_IERR_SHIFT (7U)
10039/*! IERR - Interrupt Enable Register Read
10040 * 0b0..Reads to the Interrupt Enable Register are ignored.
10041 * 0b1..Reads to the Interrupt Enable Register complete as normal.
10042 */
10043#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
10044/*! @} */
10045
10046
10047/*!
10048 * @}
10049 */ /* end of group RTC_Register_Masks */
10050
10051
10052/* RTC - Peripheral instance base addresses */
10053/** Peripheral RTC base address */
10054#define RTC_BASE (0x4003D000u)
10055/** Peripheral RTC base pointer */
10056#define RTC ((RTC_Type *)RTC_BASE)
10057/** Array initializer of RTC peripheral base addresses */
10058#define RTC_BASE_ADDRS { RTC_BASE }
10059/** Array initializer of RTC peripheral base pointers */
10060#define RTC_BASE_PTRS { RTC }
10061/** Interrupt vectors for the RTC peripheral type */
10062#define RTC_IRQS { RTC_IRQn }
10063#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
10064
10065/*!
10066 * @}
10067 */ /* end of group RTC_Peripheral_Access_Layer */
10068
10069
10070/* ----------------------------------------------------------------------------
10071 -- SIM Peripheral Access Layer
10072 ---------------------------------------------------------------------------- */
10073
10074/*!
10075 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
10076 * @{
10077 */
10078
10079/** SIM - Register Layout Typedef */
10080typedef struct {
10081 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
10082 uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
10083 uint8_t RESERVED_0[4092];
10084 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
10085 uint8_t RESERVED_1[4];
10086 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
10087 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
10088 uint8_t RESERVED_2[4];
10089 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
10090 __IO uint32_t SOPT8; /**< System Options Register 8, offset: 0x101C */
10091 uint8_t RESERVED_3[4];
10092 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
10093 uint8_t RESERVED_4[12];
10094 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
10095 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
10096 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
10097 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
10098 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
10099 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
10100 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
10101 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
10102 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
10103 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
10104 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
10105 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
10106} SIM_Type;
10107
10108/* ----------------------------------------------------------------------------
10109 -- SIM Register Masks
10110 ---------------------------------------------------------------------------- */
10111
10112/*!
10113 * @addtogroup SIM_Register_Masks SIM Register Masks
10114 * @{
10115 */
10116
10117/*! @name SOPT1 - System Options Register 1 */
10118/*! @{ */
10119#define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
10120#define SIM_SOPT1_RAMSIZE_SHIFT (12U)
10121/*! RAMSIZE - RAM size
10122 * 0b0001..8 KB
10123 * 0b0011..16 KB
10124 * 0b0100..24 KB
10125 * 0b0101..32 KB
10126 * 0b0110..48 KB
10127 * 0b0111..64 KB
10128 * 0b1000..96 KB
10129 * 0b1001..128 KB
10130 * 0b1011..256 KB
10131 */
10132#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
10133#define SIM_SOPT1_OSC32KOUT_MASK (0x30000U)
10134#define SIM_SOPT1_OSC32KOUT_SHIFT (16U)
10135/*! OSC32KOUT - 32K Oscillator Clock Output
10136 * 0b00..ERCLK32K is not output.
10137 * 0b01..ERCLK32K is output on PTE0.
10138 * 0b10..ERCLK32K is output on PTE26.
10139 * 0b11..Reserved.
10140 */
10141#define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KOUT_SHIFT)) & SIM_SOPT1_OSC32KOUT_MASK)
10142#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
10143#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
10144/*! OSC32KSEL - 32K oscillator clock select
10145 * 0b00..System oscillator (OSC32KCLK)
10146 * 0b01..Reserved
10147 * 0b10..RTC 32.768kHz oscillator
10148 * 0b11..LPO 1 kHz
10149 */
10150#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
10151/*! @} */
10152
10153/*! @name SOPT2 - System Options Register 2 */
10154/*! @{ */
10155#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
10156#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
10157/*! RTCCLKOUTSEL - RTC clock out select
10158 * 0b0..RTC 1 Hz clock is output on the RTC_CLKOUT pin.
10159 * 0b1..RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
10160 */
10161#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
10162#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
10163#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
10164/*! CLKOUTSEL - CLKOUT select
10165 * 0b000..Reserved
10166 * 0b001..Reserved
10167 * 0b010..Flash clock
10168 * 0b011..LPO clock (1 kHz)
10169 * 0b100..MCGIRCLK
10170 * 0b101..RTC 32.768kHz clock
10171 * 0b110..OSCERCLK0
10172 * 0b111..IRC 48 MHz clock
10173 */
10174#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
10175#define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
10176#define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
10177/*! TRACECLKSEL - Debug trace clock select
10178 * 0b0..MCGOUTCLK
10179 * 0b1..Core/system clock
10180 */
10181#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
10182#define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U)
10183#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
10184/*! PLLFLLSEL - PLL/FLL clock select
10185 * 0b00..MCGFLLCLK clock
10186 * 0b01..Reserved
10187 * 0b10..Reserved
10188 * 0b11..IRC48 MHz clock
10189 */
10190#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
10191#define SIM_SOPT2_USBSRC_MASK (0x40000U)
10192#define SIM_SOPT2_USBSRC_SHIFT (18U)
10193/*! USBSRC - USB clock source select
10194 * 0b0..External bypass clock (USB_CLKIN).
10195 * 0b1..MCGFLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, USBDIV].
10196 */
10197#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
10198#define SIM_SOPT2_LPUARTSRC_MASK (0xC000000U)
10199#define SIM_SOPT2_LPUARTSRC_SHIFT (26U)
10200/*! LPUARTSRC - LPUART clock source select
10201 * 0b00..Clock disabled
10202 * 0b01..MCGFLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL].
10203 * 0b10..OSCERCLK clock
10204 * 0b11..MCGIRCLK clock
10205 */
10206#define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)
10207/*! @} */
10208
10209/*! @name SOPT4 - System Options Register 4 */
10210/*! @{ */
10211#define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
10212#define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
10213/*! FTM0FLT0 - FTM0 Fault 0 Select
10214 * 0b0..FTM0_FLT0 pin
10215 * 0b1..CMP0 out
10216 */
10217#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
10218#define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
10219#define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
10220/*! FTM0FLT1 - FTM0 Fault 1 Select
10221 * 0b0..FTM0_FLT1 pin
10222 * 0b1..CMP1 out
10223 */
10224#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
10225#define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
10226#define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
10227/*! FTM1FLT0 - FTM1 Fault 0 Select
10228 * 0b0..FTM1_FLT0 pin
10229 * 0b1..CMP0 out
10230 */
10231#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
10232#define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
10233#define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
10234/*! FTM2FLT0 - FTM2 Fault 0 Select
10235 * 0b0..FTM2_FLT0 pin
10236 * 0b1..CMP0 out
10237 */
10238#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
10239#define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
10240#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
10241/*! FTM1CH0SRC - FTM1 channel 0 input capture source select
10242 * 0b00..FTM1_CH0 signal
10243 * 0b01..CMP0 output
10244 * 0b10..CMP1 output
10245 * 0b11..USB start of frame pulse
10246 */
10247#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
10248#define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
10249#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
10250/*! FTM2CH0SRC - FTM2 channel 0 input capture source select
10251 * 0b00..FTM2_CH0 signal
10252 * 0b01..CMP0 output
10253 * 0b10..CMP1 output
10254 * 0b11..Reserved
10255 */
10256#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
10257#define SIM_SOPT4_FTM2CH1SRC_MASK (0x400000U)
10258#define SIM_SOPT4_FTM2CH1SRC_SHIFT (22U)
10259/*! FTM2CH1SRC - FTM2 channel 1 input capture source select
10260 * 0b0..FTM2_CH1 signal
10261 * 0b1..Exclusive OR of FTM2_CH1, FTM2_CH0 and FTM1_CH1.
10262 */
10263#define SIM_SOPT4_FTM2CH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)
10264#define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
10265#define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
10266/*! FTM0CLKSEL - FlexTimer 0 External Clock Pin Select
10267 * 0b0..FTM_CLK0 pin
10268 * 0b1..FTM_CLK1 pin
10269 */
10270#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
10271#define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
10272#define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
10273/*! FTM1CLKSEL - FTM1 External Clock Pin Select
10274 * 0b0..FTM_CLK0 pin
10275 * 0b1..FTM_CLK1 pin
10276 */
10277#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
10278#define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
10279#define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
10280/*! FTM2CLKSEL - FlexTimer 2 External Clock Pin Select
10281 * 0b0..FTM2 external clock driven by FTM_CLK0 pin.
10282 * 0b1..FTM2 external clock driven by FTM_CLK1 pin.
10283 */
10284#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
10285#define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
10286#define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
10287/*! FTM0TRG0SRC - FlexTimer 0 Hardware Trigger 0 Source Select
10288 * 0b0..HSCMP0 output drives FTM0 hardware trigger 0
10289 * 0b1..FTM1 channel match drives FTM0 hardware trigger 0
10290 */
10291#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
10292#define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
10293#define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
10294/*! FTM0TRG1SRC - FlexTimer 0 Hardware Trigger 1 Source Select
10295 * 0b0..PDB output trigger 1 drives FTM0 hardware trigger 1
10296 * 0b1..FTM2 channel match drives FTM0 hardware trigger 1
10297 */
10298#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
10299/*! @} */
10300
10301/*! @name SOPT5 - System Options Register 5 */
10302/*! @{ */
10303#define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
10304#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
10305/*! UART0TXSRC - UART 0 transmit data source select
10306 * 0b00..UART0_TX pin
10307 * 0b01..UART0_TX pin modulated with FTM1 channel 0 output
10308 * 0b10..UART0_TX pin modulated with FTM2 channel 0 output
10309 * 0b11..Reserved
10310 */
10311#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
10312#define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
10313#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
10314/*! UART0RXSRC - UART 0 receive data source select
10315 * 0b00..UART0_RX pin
10316 * 0b01..CMP0
10317 * 0b10..CMP1
10318 * 0b11..Reserved
10319 */
10320#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
10321#define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
10322#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
10323/*! UART1TXSRC - UART 1 transmit data source select
10324 * 0b00..UART1_TX pin
10325 * 0b01..UART1_TX pin modulated with FTM1 channel 0 output
10326 * 0b10..UART1_TX pin modulated with FTM2 channel 0 output
10327 * 0b11..Reserved
10328 */
10329#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
10330#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
10331#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
10332/*! UART1RXSRC - UART 1 receive data source select
10333 * 0b00..UART1_RX pin
10334 * 0b01..CMP0
10335 * 0b10..CMP1
10336 * 0b11..Reserved
10337 */
10338#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
10339#define SIM_SOPT5_LPUART0RXSRC_MASK (0xC0000U)
10340#define SIM_SOPT5_LPUART0RXSRC_SHIFT (18U)
10341/*! LPUART0RXSRC - LPUART0 receive data source select
10342 * 0b00..LPUART0_RX pin
10343 * 0b01..CMP0 output
10344 * 0b10..CMP1 output
10345 * 0b11..Reserved
10346 */
10347#define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
10348/*! @} */
10349
10350/*! @name SOPT7 - System Options Register 7 */
10351/*! @{ */
10352#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
10353#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
10354/*! ADC0TRGSEL - ADC0 trigger select
10355 * 0b0000..PDB external trigger pin input (PDB0_EXTRG)
10356 * 0b0001..High speed comparator 0 output
10357 * 0b0010..High speed comparator 1 output
10358 * 0b0011..Reserved
10359 * 0b0100..PIT trigger 0
10360 * 0b0101..PIT trigger 1
10361 * 0b0110..PIT trigger 2
10362 * 0b0111..PIT trigger 3
10363 * 0b1000..FTM0 trigger
10364 * 0b1001..FTM1 trigger
10365 * 0b1010..FTM2 trigger
10366 * 0b1011..Reserved
10367 * 0b1100..RTC alarm
10368 * 0b1101..RTC seconds
10369 * 0b1110..Low-power timer (LPTMR) trigger
10370 * 0b1111..Reserved
10371 */
10372#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
10373#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
10374#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
10375/*! ADC0PRETRGSEL - ADC0 pretrigger select
10376 * 0b0..Pre-trigger A
10377 * 0b1..Pre-trigger B
10378 */
10379#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
10380#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
10381#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
10382/*! ADC0ALTTRGEN - ADC0 alternate trigger enable
10383 * 0b0..PDB trigger selected for ADC0.
10384 * 0b1..Alternate trigger selected for ADC0.
10385 */
10386#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
10387#define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U)
10388#define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U)
10389/*! ADC1TRGSEL - ADC1 trigger select
10390 * 0b0000..PDB external trigger pin input (PDB0_EXTRG)
10391 * 0b0001..High speed comparator 0 output
10392 * 0b0010..High speed comparator 1 output
10393 * 0b0011..Reserved
10394 * 0b0100..PIT trigger 0
10395 * 0b0101..PIT trigger 1
10396 * 0b0110..PIT trigger 2
10397 * 0b0111..PIT trigger 3
10398 * 0b1000..FTM0 trigger
10399 * 0b1001..FTM1 trigger
10400 * 0b1010..FTM2 trigger
10401 * 0b1011..Reserved
10402 * 0b1100..RTC alarm
10403 * 0b1101..RTC seconds
10404 * 0b1110..Low-power timer (LPTMR) trigger
10405 * 0b1111..Reserved
10406 */
10407#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
10408#define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U)
10409#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U)
10410/*! ADC1PRETRGSEL - ADC1 pre-trigger select
10411 * 0b0..Pre-trigger A selected for ADC1.
10412 * 0b1..Pre-trigger B selected for ADC1.
10413 */
10414#define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
10415#define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U)
10416#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U)
10417/*! ADC1ALTTRGEN - ADC1 alternate trigger enable
10418 * 0b0..PDB trigger selected for ADC1
10419 * 0b1..Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
10420 */
10421#define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
10422/*! @} */
10423
10424/*! @name SOPT8 - System Options Register 8 */
10425/*! @{ */
10426#define SIM_SOPT8_FTM0SYNCBIT_MASK (0x1U)
10427#define SIM_SOPT8_FTM0SYNCBIT_SHIFT (0U)
10428/*! FTM0SYNCBIT - FTM0 Hardware Trigger 0 Software Synchronization
10429 * 0b0..No effect
10430 * 0b1..Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert.
10431 */
10432#define SIM_SOPT8_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
10433#define SIM_SOPT8_FTM1SYNCBIT_MASK (0x2U)
10434#define SIM_SOPT8_FTM1SYNCBIT_SHIFT (1U)
10435/*! FTM1SYNCBIT - FTM1 Hardware Trigger 0 Software Synchronization
10436 * 0b0..No effect.
10437 * 0b1..Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert.
10438 */
10439#define SIM_SOPT8_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
10440#define SIM_SOPT8_FTM2SYNCBIT_MASK (0x4U)
10441#define SIM_SOPT8_FTM2SYNCBIT_SHIFT (2U)
10442/*! FTM2SYNCBIT - FTM2 Hardware Trigger 0 Software Synchronization
10443 * 0b0..No effect.
10444 * 0b1..Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert.
10445 */
10446#define SIM_SOPT8_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
10447#define SIM_SOPT8_FTM0OCH0SRC_MASK (0x10000U)
10448#define SIM_SOPT8_FTM0OCH0SRC_SHIFT (16U)
10449/*! FTM0OCH0SRC - FTM0 channel 0 output source
10450 * 0b0..FTM0_CH0 pin is output of FTM0 channel 0 output
10451 * 0b1..FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 channel 1 output
10452 */
10453#define SIM_SOPT8_FTM0OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
10454#define SIM_SOPT8_FTM0OCH1SRC_MASK (0x20000U)
10455#define SIM_SOPT8_FTM0OCH1SRC_SHIFT (17U)
10456/*! FTM0OCH1SRC - FTM0 channel 1 output source
10457 * 0b0..FTM0_CH1 pin is output of FTM0 channel 1 output
10458 * 0b1..FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 channel 1 output
10459 */
10460#define SIM_SOPT8_FTM0OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
10461#define SIM_SOPT8_FTM0OCH2SRC_MASK (0x40000U)
10462#define SIM_SOPT8_FTM0OCH2SRC_SHIFT (18U)
10463/*! FTM0OCH2SRC - FTM0 channel 2 output source
10464 * 0b0..FTM0_CH2 pin is output of FTM0 channel 2 output
10465 * 0b1..FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 channel 1 output
10466 */
10467#define SIM_SOPT8_FTM0OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
10468#define SIM_SOPT8_FTM0OCH3SRC_MASK (0x80000U)
10469#define SIM_SOPT8_FTM0OCH3SRC_SHIFT (19U)
10470/*! FTM0OCH3SRC - FTM0 channel 3 output source
10471 * 0b0..FTM0_CH3 pin is output of FTM0 channel 3 output
10472 * 0b1..FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 channel 1 output
10473 */
10474#define SIM_SOPT8_FTM0OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
10475#define SIM_SOPT8_FTM0OCH4SRC_MASK (0x100000U)
10476#define SIM_SOPT8_FTM0OCH4SRC_SHIFT (20U)
10477/*! FTM0OCH4SRC - FTM0 channel 4 output source
10478 * 0b0..FTM0_CH4 pin is output of FTM0 channel 4 output
10479 * 0b1..FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output
10480 */
10481#define SIM_SOPT8_FTM0OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
10482#define SIM_SOPT8_FTM0OCH5SRC_MASK (0x200000U)
10483#define SIM_SOPT8_FTM0OCH5SRC_SHIFT (21U)
10484/*! FTM0OCH5SRC - FTM0 channel 5 output source
10485 * 0b0..FTM0_CH5 pin is output of FTM0 channel 5 output
10486 * 0b1..FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output
10487 */
10488#define SIM_SOPT8_FTM0OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
10489#define SIM_SOPT8_FTM0OCH6SRC_MASK (0x400000U)
10490#define SIM_SOPT8_FTM0OCH6SRC_SHIFT (22U)
10491/*! FTM0OCH6SRC - FTM0 channel 6 output source
10492 * 0b0..FTM0_CH6 pin is output of FTM0 channel 6 output
10493 * 0b1..FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1 channel 1 output
10494 */
10495#define SIM_SOPT8_FTM0OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
10496#define SIM_SOPT8_FTM0OCH7SRC_MASK (0x800000U)
10497#define SIM_SOPT8_FTM0OCH7SRC_SHIFT (23U)
10498/*! FTM0OCH7SRC - FTM0 channel 7 output source
10499 * 0b0..FTM0_CH7 pin is output of FTM0 channel 7 output
10500 * 0b1..FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by FTM1 channel 1 output
10501 */
10502#define SIM_SOPT8_FTM0OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
10503/*! @} */
10504
10505/*! @name SDID - System Device Identification Register */
10506/*! @{ */
10507#define SIM_SDID_PINID_MASK (0xFU)
10508#define SIM_SDID_PINID_SHIFT (0U)
10509/*! PINID - Pincount identification
10510 * 0b0000..Reserved
10511 * 0b0001..Reserved
10512 * 0b0010..32-pin
10513 * 0b0011..Reserved
10514 * 0b0100..48-pin
10515 * 0b0101..64-pin
10516 * 0b0110..80-pin
10517 * 0b0111..81-pin or 121-pin
10518 * 0b1000..100-pin
10519 * 0b1001..121-pin
10520 * 0b1010..144-pin
10521 * 0b1011..Custom pinout (WLCSP)
10522 * 0b1100..169-pin
10523 * 0b1101..Reserved
10524 * 0b1110..256-pin
10525 * 0b1111..Reserved
10526 */
10527#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
10528#define SIM_SDID_FAMID_MASK (0x70U)
10529#define SIM_SDID_FAMID_SHIFT (4U)
10530/*! FAMID - Kinetis family identification
10531 * 0b000..K1x Family (without tamper)
10532 * 0b001..K2x Family (without tamper)
10533 * 0b010..K3x Family or K1x/K6x Family (with tamper)
10534 * 0b011..K4x Family or K2x Family (with tamper)
10535 * 0b100..K6x Family (without tamper)
10536 * 0b101..K7x Family
10537 * 0b110..Reserved
10538 * 0b111..Reserved
10539 */
10540#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
10541#define SIM_SDID_DIEID_MASK (0xF80U)
10542#define SIM_SDID_DIEID_SHIFT (7U)
10543#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
10544#define SIM_SDID_REVID_MASK (0xF000U)
10545#define SIM_SDID_REVID_SHIFT (12U)
10546#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
10547#define SIM_SDID_SERIESID_MASK (0xF00000U)
10548#define SIM_SDID_SERIESID_SHIFT (20U)
10549/*! SERIESID - Kinetis Series ID
10550 * 0b0000..Kinetis K series
10551 * 0b0001..Kinetis L series
10552 * 0b0101..Kinetis W series
10553 * 0b0110..Kinetis V series
10554 */
10555#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
10556#define SIM_SDID_SUBFAMID_MASK (0xF000000U)
10557#define SIM_SDID_SUBFAMID_SHIFT (24U)
10558/*! SUBFAMID - Kinetis Sub-Family ID
10559 * 0b0000..Kx0 Subfamily
10560 * 0b0001..Kx1 Subfamily (tamper detect)
10561 * 0b0010..Kx2 Subfamily
10562 * 0b0011..Kx3 Subfamily (tamper detect)
10563 * 0b0100..Kx4 Subfamily
10564 * 0b0101..Kx5 Subfamily (tamper detect)
10565 * 0b0110..Kx6 Subfamily
10566 */
10567#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
10568#define SIM_SDID_FAMILYID_MASK (0xF0000000U)
10569#define SIM_SDID_FAMILYID_SHIFT (28U)
10570/*! FAMILYID - Kinetis Family ID
10571 * 0b0000..K0x Family
10572 * 0b0001..K1x Family
10573 * 0b0010..K2x Family
10574 * 0b0011..K3x Family
10575 * 0b0100..K4x Family
10576 * 0b0110..K6x Family
10577 * 0b0111..K7x Family
10578 */
10579#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
10580/*! @} */
10581
10582/*! @name SCGC4 - System Clock Gating Control Register 4 */
10583/*! @{ */
10584#define SIM_SCGC4_EWM_MASK (0x2U)
10585#define SIM_SCGC4_EWM_SHIFT (1U)
10586/*! EWM - EWM Clock Gate Control
10587 * 0b0..Clock disabled
10588 * 0b1..Clock enabled
10589 */
10590#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
10591#define SIM_SCGC4_I2C0_MASK (0x40U)
10592#define SIM_SCGC4_I2C0_SHIFT (6U)
10593/*! I2C0 - I2C0 Clock Gate Control
10594 * 0b0..Clock disabled
10595 * 0b1..Clock enabled
10596 */
10597#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
10598#define SIM_SCGC4_I2C1_MASK (0x80U)
10599#define SIM_SCGC4_I2C1_SHIFT (7U)
10600/*! I2C1 - I2C1 Clock Gate Control
10601 * 0b0..Clock disabled
10602 * 0b1..Clock enabled
10603 */
10604#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
10605#define SIM_SCGC4_UART0_MASK (0x400U)
10606#define SIM_SCGC4_UART0_SHIFT (10U)
10607/*! UART0 - UART0 Clock Gate Control
10608 * 0b0..Clock disabled
10609 * 0b1..Clock enabled
10610 */
10611#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
10612#define SIM_SCGC4_UART1_MASK (0x800U)
10613#define SIM_SCGC4_UART1_SHIFT (11U)
10614/*! UART1 - UART1 Clock Gate Control
10615 * 0b0..Clock disabled
10616 * 0b1..Clock enabled
10617 */
10618#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
10619#define SIM_SCGC4_UART2_MASK (0x1000U)
10620#define SIM_SCGC4_UART2_SHIFT (12U)
10621/*! UART2 - UART2 Clock Gate Control
10622 * 0b0..Clock disabled
10623 * 0b1..Clock enabled
10624 */
10625#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
10626#define SIM_SCGC4_USBOTG_MASK (0x40000U)
10627#define SIM_SCGC4_USBOTG_SHIFT (18U)
10628/*! USBOTG - USB Clock Gate Control
10629 * 0b0..Clock disabled
10630 * 0b1..Clock enabled
10631 */
10632#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
10633#define SIM_SCGC4_CMP_MASK (0x80000U)
10634#define SIM_SCGC4_CMP_SHIFT (19U)
10635/*! CMP - Comparator Clock Gate Control
10636 * 0b0..Clock disabled
10637 * 0b1..Clock enabled
10638 */
10639#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
10640#define SIM_SCGC4_VREF_MASK (0x100000U)
10641#define SIM_SCGC4_VREF_SHIFT (20U)
10642/*! VREF - VREF Clock Gate Control
10643 * 0b0..Clock disabled
10644 * 0b1..Clock enabled
10645 */
10646#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
10647/*! @} */
10648
10649/*! @name SCGC5 - System Clock Gating Control Register 5 */
10650/*! @{ */
10651#define SIM_SCGC5_LPTMR_MASK (0x1U)
10652#define SIM_SCGC5_LPTMR_SHIFT (0U)
10653/*! LPTMR - Low Power Timer Access Control
10654 * 0b0..Access disabled
10655 * 0b1..Access enabled
10656 */
10657#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
10658#define SIM_SCGC5_PORTA_MASK (0x200U)
10659#define SIM_SCGC5_PORTA_SHIFT (9U)
10660/*! PORTA - Port A Clock Gate Control
10661 * 0b0..Clock disabled
10662 * 0b1..Clock enabled
10663 */
10664#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
10665#define SIM_SCGC5_PORTB_MASK (0x400U)
10666#define SIM_SCGC5_PORTB_SHIFT (10U)
10667/*! PORTB - Port B Clock Gate Control
10668 * 0b0..Clock disabled
10669 * 0b1..Clock enabled
10670 */
10671#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
10672#define SIM_SCGC5_PORTC_MASK (0x800U)
10673#define SIM_SCGC5_PORTC_SHIFT (11U)
10674/*! PORTC - Port C Clock Gate Control
10675 * 0b0..Clock disabled
10676 * 0b1..Clock enabled
10677 */
10678#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
10679#define SIM_SCGC5_PORTD_MASK (0x1000U)
10680#define SIM_SCGC5_PORTD_SHIFT (12U)
10681/*! PORTD - Port D Clock Gate Control
10682 * 0b0..Clock disabled
10683 * 0b1..Clock enabled
10684 */
10685#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
10686#define SIM_SCGC5_PORTE_MASK (0x2000U)
10687#define SIM_SCGC5_PORTE_SHIFT (13U)
10688/*! PORTE - Port E Clock Gate Control
10689 * 0b0..Clock disabled
10690 * 0b1..Clock enabled
10691 */
10692#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
10693/*! @} */
10694
10695/*! @name SCGC6 - System Clock Gating Control Register 6 */
10696/*! @{ */
10697#define SIM_SCGC6_FTF_MASK (0x1U)
10698#define SIM_SCGC6_FTF_SHIFT (0U)
10699/*! FTF - Flash Memory Clock Gate Control
10700 * 0b0..Clock disabled
10701 * 0b1..Clock enabled
10702 */
10703#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
10704#define SIM_SCGC6_DMAMUX_MASK (0x2U)
10705#define SIM_SCGC6_DMAMUX_SHIFT (1U)
10706/*! DMAMUX - DMA Mux Clock Gate Control
10707 * 0b0..Clock disabled
10708 * 0b1..Clock enabled
10709 */
10710#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
10711#define SIM_SCGC6_ADC1_MASK (0x80U)
10712#define SIM_SCGC6_ADC1_SHIFT (7U)
10713/*! ADC1 - ADC1 Clock Gate Control
10714 * 0b0..Clock disabled
10715 * 0b1..Clock enabled
10716 */
10717#define SIM_SCGC6_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC1_SHIFT)) & SIM_SCGC6_ADC1_MASK)
10718#define SIM_SCGC6_LPUART0_MASK (0x400U)
10719#define SIM_SCGC6_LPUART0_SHIFT (10U)
10720/*! LPUART0 - LPUART0 Clock Gate Control
10721 * 0b0..Clock disabled
10722 * 0b1..Clock enabled
10723 */
10724#define SIM_SCGC6_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_LPUART0_SHIFT)) & SIM_SCGC6_LPUART0_MASK)
10725#define SIM_SCGC6_SPI0_MASK (0x1000U)
10726#define SIM_SCGC6_SPI0_SHIFT (12U)
10727/*! SPI0 - SPI0 Clock Gate Control
10728 * 0b0..Clock disabled
10729 * 0b1..Clock enabled
10730 */
10731#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
10732#define SIM_SCGC6_SPI1_MASK (0x2000U)
10733#define SIM_SCGC6_SPI1_SHIFT (13U)
10734/*! SPI1 - SPI1 Clock Gate Control
10735 * 0b0..Clock disabled
10736 * 0b1..Clock enabled
10737 */
10738#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
10739#define SIM_SCGC6_I2S_MASK (0x8000U)
10740#define SIM_SCGC6_I2S_SHIFT (15U)
10741/*! I2S - I2S Clock Gate Control
10742 * 0b0..Clock disabled
10743 * 0b1..Clock enabled
10744 */
10745#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
10746#define SIM_SCGC6_CRC_MASK (0x40000U)
10747#define SIM_SCGC6_CRC_SHIFT (18U)
10748/*! CRC - CRC Clock Gate Control
10749 * 0b0..Clock disabled
10750 * 0b1..Clock enabled
10751 */
10752#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
10753#define SIM_SCGC6_PDB_MASK (0x400000U)
10754#define SIM_SCGC6_PDB_SHIFT (22U)
10755/*! PDB - PDB Clock Gate Control
10756 * 0b0..Clock disabled
10757 * 0b1..Clock enabled
10758 */
10759#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
10760#define SIM_SCGC6_PIT_MASK (0x800000U)
10761#define SIM_SCGC6_PIT_SHIFT (23U)
10762/*! PIT - PIT Clock Gate Control
10763 * 0b0..Clock disabled
10764 * 0b1..Clock enabled
10765 */
10766#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
10767#define SIM_SCGC6_FTM0_MASK (0x1000000U)
10768#define SIM_SCGC6_FTM0_SHIFT (24U)
10769/*! FTM0 - FTM0 Clock Gate Control
10770 * 0b0..Clock disabled
10771 * 0b1..Clock enabled
10772 */
10773#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
10774#define SIM_SCGC6_FTM1_MASK (0x2000000U)
10775#define SIM_SCGC6_FTM1_SHIFT (25U)
10776/*! FTM1 - FTM1 Clock Gate Control
10777 * 0b0..Clock disabled
10778 * 0b1..Clock enabled
10779 */
10780#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
10781#define SIM_SCGC6_FTM2_MASK (0x4000000U)
10782#define SIM_SCGC6_FTM2_SHIFT (26U)
10783/*! FTM2 - FTM2 Clock Gate Control
10784 * 0b0..Clock disabled
10785 * 0b1..Clock enabled
10786 */
10787#define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
10788#define SIM_SCGC6_ADC0_MASK (0x8000000U)
10789#define SIM_SCGC6_ADC0_SHIFT (27U)
10790/*! ADC0 - ADC0 Clock Gate Control
10791 * 0b0..Clock disabled
10792 * 0b1..Clock enabled
10793 */
10794#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
10795#define SIM_SCGC6_RTC_MASK (0x20000000U)
10796#define SIM_SCGC6_RTC_SHIFT (29U)
10797/*! RTC - RTC Access Control
10798 * 0b0..Access and interrupts disabled
10799 * 0b1..Access and interrupts enabled
10800 */
10801#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
10802#define SIM_SCGC6_DAC0_MASK (0x80000000U)
10803#define SIM_SCGC6_DAC0_SHIFT (31U)
10804/*! DAC0 - DAC0 Clock Gate Control
10805 * 0b0..Clock disabled
10806 * 0b1..Clock enabled
10807 */
10808#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
10809/*! @} */
10810
10811/*! @name SCGC7 - System Clock Gating Control Register 7 */
10812/*! @{ */
10813#define SIM_SCGC7_DMA_MASK (0x2U)
10814#define SIM_SCGC7_DMA_SHIFT (1U)
10815/*! DMA - DMA Clock Gate Control
10816 * 0b0..Clock disabled
10817 * 0b1..Clock enabled
10818 */
10819#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
10820/*! @} */
10821
10822/*! @name CLKDIV1 - System Clock Divider Register 1 */
10823/*! @{ */
10824#define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
10825#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
10826/*! OUTDIV4 - Clock 4 output divider value
10827 * 0b0000..Divide-by-1.
10828 * 0b0001..Divide-by-2.
10829 * 0b0010..Divide-by-3.
10830 * 0b0011..Divide-by-4.
10831 * 0b0100..Divide-by-5.
10832 * 0b0101..Divide-by-6.
10833 * 0b0110..Divide-by-7.
10834 * 0b0111..Divide-by-8.
10835 * 0b1000..Divide-by-9.
10836 * 0b1001..Divide-by-10.
10837 * 0b1010..Divide-by-11.
10838 * 0b1011..Divide-by-12.
10839 * 0b1100..Divide-by-13.
10840 * 0b1101..Divide-by-14.
10841 * 0b1110..Divide-by-15.
10842 * 0b1111..Divide-by-16.
10843 */
10844#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
10845#define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
10846#define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
10847/*! OUTDIV2 - Clock 2 output divider value
10848 * 0b0000..Divide-by-1.
10849 * 0b0001..Divide-by-2.
10850 * 0b0010..Divide-by-3.
10851 * 0b0011..Divide-by-4.
10852 * 0b0100..Divide-by-5.
10853 * 0b0101..Divide-by-6.
10854 * 0b0110..Divide-by-7.
10855 * 0b0111..Divide-by-8.
10856 * 0b1000..Divide-by-9.
10857 * 0b1001..Divide-by-10.
10858 * 0b1010..Divide-by-11.
10859 * 0b1011..Divide-by-12.
10860 * 0b1100..Divide-by-13.
10861 * 0b1101..Divide-by-14.
10862 * 0b1110..Divide-by-15.
10863 * 0b1111..Divide-by-16.
10864 */
10865#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
10866#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
10867#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
10868/*! OUTDIV1 - Clock 1 output divider value
10869 * 0b0000..Divide-by-1.
10870 * 0b0001..Divide-by-2.
10871 * 0b0010..Divide-by-3.
10872 * 0b0011..Divide-by-4.
10873 * 0b0100..Divide-by-5.
10874 * 0b0101..Divide-by-6.
10875 * 0b0110..Divide-by-7.
10876 * 0b0111..Divide-by-8.
10877 * 0b1000..Divide-by-9.
10878 * 0b1001..Divide-by-10.
10879 * 0b1010..Divide-by-11.
10880 * 0b1011..Divide-by-12.
10881 * 0b1100..Divide-by-13.
10882 * 0b1101..Divide-by-14.
10883 * 0b1110..Divide-by-15.
10884 * 0b1111..Divide-by-16.
10885 */
10886#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
10887/*! @} */
10888
10889/*! @name CLKDIV2 - System Clock Divider Register 2 */
10890/*! @{ */
10891#define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
10892#define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
10893#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
10894#define SIM_CLKDIV2_USBDIV_MASK (0xEU)
10895#define SIM_CLKDIV2_USBDIV_SHIFT (1U)
10896#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
10897/*! @} */
10898
10899/*! @name FCFG1 - Flash Configuration Register 1 */
10900/*! @{ */
10901#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
10902#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
10903/*! FLASHDIS - Flash Disable
10904 * 0b0..Flash is enabled
10905 * 0b1..Flash is disabled
10906 */
10907#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
10908#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
10909#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
10910/*! FLASHDOZE - Flash Doze
10911 * 0b0..Flash remains enabled during Wait mode
10912 * 0b1..Flash is disabled for the duration of Wait mode
10913 */
10914#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
10915#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
10916#define SIM_FCFG1_PFSIZE_SHIFT (24U)
10917/*! PFSIZE - Program flash size
10918 * 0b0011..32 KB of program flash memory
10919 * 0b0101..64 KB of program flash memory
10920 * 0b0111..128 KB of program flash memory
10921 * 0b1001..256 KB of program flash memory
10922 * 0b1011..512 KB of program flash memory
10923 * 0b1101..1024 KB of program flash memory
10924 * 0b1111..128 KB of program flash memory
10925 */
10926#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
10927/*! @} */
10928
10929/*! @name FCFG2 - Flash Configuration Register 2 */
10930/*! @{ */
10931#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
10932#define SIM_FCFG2_MAXADDR1_SHIFT (16U)
10933#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
10934#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
10935#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
10936#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
10937/*! @} */
10938
10939/*! @name UIDH - Unique Identification Register High */
10940/*! @{ */
10941#define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
10942#define SIM_UIDH_UID_SHIFT (0U)
10943#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
10944/*! @} */
10945
10946/*! @name UIDMH - Unique Identification Register Mid-High */
10947/*! @{ */
10948#define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
10949#define SIM_UIDMH_UID_SHIFT (0U)
10950#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
10951/*! @} */
10952
10953/*! @name UIDML - Unique Identification Register Mid Low */
10954/*! @{ */
10955#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
10956#define SIM_UIDML_UID_SHIFT (0U)
10957#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
10958/*! @} */
10959
10960/*! @name UIDL - Unique Identification Register Low */
10961/*! @{ */
10962#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
10963#define SIM_UIDL_UID_SHIFT (0U)
10964#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
10965/*! @} */
10966
10967
10968/*!
10969 * @}
10970 */ /* end of group SIM_Register_Masks */
10971
10972
10973/* SIM - Peripheral instance base addresses */
10974/** Peripheral SIM base address */
10975#define SIM_BASE (0x40047000u)
10976/** Peripheral SIM base pointer */
10977#define SIM ((SIM_Type *)SIM_BASE)
10978/** Array initializer of SIM peripheral base addresses */
10979#define SIM_BASE_ADDRS { SIM_BASE }
10980/** Array initializer of SIM peripheral base pointers */
10981#define SIM_BASE_PTRS { SIM }
10982
10983/*!
10984 * @}
10985 */ /* end of group SIM_Peripheral_Access_Layer */
10986
10987
10988/* ----------------------------------------------------------------------------
10989 -- SMC Peripheral Access Layer
10990 ---------------------------------------------------------------------------- */
10991
10992/*!
10993 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
10994 * @{
10995 */
10996
10997/** SMC - Register Layout Typedef */
10998typedef struct {
10999 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
11000 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
11001 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
11002 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
11003} SMC_Type;
11004
11005/* ----------------------------------------------------------------------------
11006 -- SMC Register Masks
11007 ---------------------------------------------------------------------------- */
11008
11009/*!
11010 * @addtogroup SMC_Register_Masks SMC Register Masks
11011 * @{
11012 */
11013
11014/*! @name PMPROT - Power Mode Protection register */
11015/*! @{ */
11016#define SMC_PMPROT_AVLLS_MASK (0x2U)
11017#define SMC_PMPROT_AVLLS_SHIFT (1U)
11018/*! AVLLS - Allow Very-Low-Leakage Stop Mode
11019 * 0b0..Any VLLSx mode is not allowed
11020 * 0b1..Any VLLSx mode is allowed
11021 */
11022#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
11023#define SMC_PMPROT_ALLS_MASK (0x8U)
11024#define SMC_PMPROT_ALLS_SHIFT (3U)
11025/*! ALLS - Allow Low-Leakage Stop Mode
11026 * 0b0..Any LLSx mode is not allowed
11027 * 0b1..Any LLSx mode is allowed
11028 */
11029#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
11030#define SMC_PMPROT_AVLP_MASK (0x20U)
11031#define SMC_PMPROT_AVLP_SHIFT (5U)
11032/*! AVLP - Allow Very-Low-Power Modes
11033 * 0b0..VLPR, VLPW, and VLPS are not allowed.
11034 * 0b1..VLPR, VLPW, and VLPS are allowed.
11035 */
11036#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
11037#define SMC_PMPROT_AHSRUN_MASK (0x80U)
11038#define SMC_PMPROT_AHSRUN_SHIFT (7U)
11039/*! AHSRUN - Allow High Speed Run mode
11040 * 0b0..HSRUN is not allowed
11041 * 0b1..HSRUN is allowed
11042 */
11043#define SMC_PMPROT_AHSRUN(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
11044/*! @} */
11045
11046/*! @name PMCTRL - Power Mode Control register */
11047/*! @{ */
11048#define SMC_PMCTRL_STOPM_MASK (0x7U)
11049#define SMC_PMCTRL_STOPM_SHIFT (0U)
11050/*! STOPM - Stop Mode Control
11051 * 0b000..Normal Stop (STOP)
11052 * 0b001..Reserved
11053 * 0b010..Very-Low-Power Stop (VLPS)
11054 * 0b011..Low-Leakage Stop (LLSx)
11055 * 0b100..Very-Low-Leakage Stop (VLLSx)
11056 * 0b101..Reserved
11057 * 0b110..Reseved
11058 * 0b111..Reserved
11059 */
11060#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
11061#define SMC_PMCTRL_STOPA_MASK (0x8U)
11062#define SMC_PMCTRL_STOPA_SHIFT (3U)
11063/*! STOPA - Stop Aborted
11064 * 0b0..The previous stop mode entry was successsful.
11065 * 0b1..The previous stop mode entry was aborted.
11066 */
11067#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
11068#define SMC_PMCTRL_RUNM_MASK (0x60U)
11069#define SMC_PMCTRL_RUNM_SHIFT (5U)
11070/*! RUNM - Run Mode Control
11071 * 0b00..Normal Run mode (RUN)
11072 * 0b01..Reserved
11073 * 0b10..Very-Low-Power Run mode (VLPR)
11074 * 0b11..High Speed Run mode (HSRUN)
11075 */
11076#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
11077/*! @} */
11078
11079/*! @name STOPCTRL - Stop Control Register */
11080/*! @{ */
11081#define SMC_STOPCTRL_LLSM_MASK (0x7U)
11082#define SMC_STOPCTRL_LLSM_SHIFT (0U)
11083/*! LLSM - LLS or VLLS Mode Control
11084 * 0b000..VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx
11085 * 0b001..VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx
11086 * 0b010..VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
11087 * 0b011..VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx
11088 * 0b100..Reserved
11089 * 0b101..Reserved
11090 * 0b110..Reserved
11091 * 0b111..Reserved
11092 */
11093#define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
11094#define SMC_STOPCTRL_PORPO_MASK (0x20U)
11095#define SMC_STOPCTRL_PORPO_SHIFT (5U)
11096/*! PORPO - POR Power Option
11097 * 0b0..POR detect circuit is enabled in VLLS0
11098 * 0b1..POR detect circuit is disabled in VLLS0
11099 */
11100#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
11101#define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
11102#define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
11103/*! PSTOPO - Partial Stop Option
11104 * 0b00..STOP - Normal Stop mode
11105 * 0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled
11106 * 0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
11107 * 0b11..Reserved
11108 */
11109#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
11110/*! @} */
11111
11112/*! @name PMSTAT - Power Mode Status register */
11113/*! @{ */
11114#define SMC_PMSTAT_PMSTAT_MASK (0xFFU)
11115#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
11116#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
11117/*! @} */
11118
11119
11120/*!
11121 * @}
11122 */ /* end of group SMC_Register_Masks */
11123
11124
11125/* SMC - Peripheral instance base addresses */
11126/** Peripheral SMC base address */
11127#define SMC_BASE (0x4007E000u)
11128/** Peripheral SMC base pointer */
11129#define SMC ((SMC_Type *)SMC_BASE)
11130/** Array initializer of SMC peripheral base addresses */
11131#define SMC_BASE_ADDRS { SMC_BASE }
11132/** Array initializer of SMC peripheral base pointers */
11133#define SMC_BASE_PTRS { SMC }
11134
11135/*!
11136 * @}
11137 */ /* end of group SMC_Peripheral_Access_Layer */
11138
11139
11140/* ----------------------------------------------------------------------------
11141 -- SPI Peripheral Access Layer
11142 ---------------------------------------------------------------------------- */
11143
11144/*!
11145 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
11146 * @{
11147 */
11148
11149/** SPI - Register Layout Typedef */
11150typedef struct {
11151 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
11152 uint8_t RESERVED_0[4];
11153 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
11154 union { /* offset: 0xC */
11155 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
11156 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */