aboutsummaryrefslogtreecommitdiff
path: root/lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/drivers/fsl_clock.h
diff options
context:
space:
mode:
Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/drivers/fsl_clock.h')
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/drivers/fsl_clock.h1361
1 files changed, 1361 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/drivers/fsl_clock.h
new file mode 100644
index 000000000..9a91865f0
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MK22F12810/drivers/fsl_clock.h
@@ -0,0 +1,1361 @@
1/*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2020, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_CLOCK_H_
10#define _FSL_CLOCK_H_
11
12#include "fsl_common.h"
13
14/*! @addtogroup clock */
15/*! @{ */
16
17/*! @file */
18
19/*******************************************************************************
20 * Configurations
21 ******************************************************************************/
22
23/*! @brief Configures whether to check a parameter in a function.
24 *
25 * Some MCG settings must be changed with conditions, for example:
26 * 1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when
27 * MCGIRCLK is used as a system clock source.
28 * 2. MCG_C7[OSCSEL] should not be changed when the external reference clock is used
29 * as a system clock source. For example, in FBE/BLPE/PBE modes.
30 * 3. The users should only switch between the supported clock modes.
31 *
32 * MCG functions check the parameter and MCG status before setting, if not allowed
33 * to change, the functions return error. The parameter checking increases code size,
34 * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to
35 * disable parameter checking.
36 */
37#ifndef MCG_CONFIG_CHECK_PARAM
38#define MCG_CONFIG_CHECK_PARAM 0U
39#endif
40
41/*! @brief Configure whether driver controls clock
42 *
43 * When set to 0, peripheral drivers will enable clock in initialize function
44 * and disable clock in de-initialize function. When set to 1, peripheral
45 * driver will not control the clock, application could control the clock out of
46 * the driver.
47 *
48 * @note All drivers share this feature switcher. If it is set to 1, application
49 * should handle clock enable and disable for all drivers.
50 */
51#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
52#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
53#endif
54
55/*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58
59/*! @name Driver version */
60/*@{*/
61/*! @brief CLOCK driver version 2.5.1. */
62#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
63/*@}*/
64
65/*! @brief External XTAL0 (OSC0) clock frequency.
66 *
67 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
68 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
69 * if XTAL0 is 8 MHz:
70 * @code
71 * Set up the OSC0
72 * CLOCK_InitOsc0(...);
73 * Set the XTAL0 value to the clock driver.
74 * CLOCK_SetXtal0Freq(80000000);
75 * @endcode
76 *
77 * This is important for the multicore platforms where only one core needs to set up the
78 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
79 * to get a valid clock frequency.
80 */
81extern volatile uint32_t g_xtal0Freq;
82
83/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
84 *
85 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
86 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
87 *
88 * This is important for the multicore platforms where only one core needs to set up
89 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
90 * to get a valid clock frequency.
91 */
92extern volatile uint32_t g_xtal32Freq;
93
94/*! @brief IRC48M clock frequency in Hz. */
95#define MCG_INTERNAL_IRC_48M 48000000U
96
97#if (defined(OSC) && !(defined(OSC0)))
98#define OSC0 OSC
99#endif
100
101/* Definition for delay API in clock driver, users can redefine it to the real application. */
102#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
103#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (120000000UL)
104#endif
105
106/*! @brief Clock ip name array for DMAMUX. */
107#define DMAMUX_CLOCKS \
108 { \
109 kCLOCK_Dmamux0 \
110 }
111
112/*! @brief Clock ip name array for RTC. */
113#define RTC_CLOCKS \
114 { \
115 kCLOCK_Rtc0 \
116 }
117
118/*! @brief Clock ip name array for SAI. */
119#define SAI_CLOCKS \
120 { \
121 kCLOCK_Sai0 \
122 }
123
124/*! @brief Clock ip name array for PORT. */
125#define PORT_CLOCKS \
126 { \
127 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
128 }
129
130/*! @brief Clock ip name array for EWM. */
131#define EWM_CLOCKS \
132 { \
133 kCLOCK_Ewm0 \
134 }
135
136/*! @brief Clock ip name array for PIT. */
137#define PIT_CLOCKS \
138 { \
139 kCLOCK_Pit0 \
140 }
141
142/*! @brief Clock ip name array for DSPI. */
143#define DSPI_CLOCKS \
144 { \
145 kCLOCK_Spi0, kCLOCK_Spi1 \
146 }
147
148/*! @brief Clock ip name array for LPTMR. */
149#define LPTMR_CLOCKS \
150 { \
151 kCLOCK_Lptmr0 \
152 }
153
154/*! @brief Clock ip name array for FTM. */
155#define FTM_CLOCKS \
156 { \
157 kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2 \
158 }
159
160/*! @brief Clock ip name array for EDMA. */
161#define EDMA_CLOCKS \
162 { \
163 kCLOCK_Dma0 \
164 }
165
166/*! @brief Clock ip name array for LPUART. */
167#define LPUART_CLOCKS \
168 { \
169 kCLOCK_Lpuart0 \
170 }
171
172/*! @brief Clock ip name array for DAC. */
173#define DAC_CLOCKS \
174 { \
175 kCLOCK_Dac0 \
176 }
177
178/*! @brief Clock ip name array for ADC16. */
179#define ADC16_CLOCKS \
180 { \
181 kCLOCK_Adc0, kCLOCK_Adc1 \
182 }
183
184/*! @brief Clock ip name array for VREF. */
185#define VREF_CLOCKS \
186 { \
187 kCLOCK_Vref0 \
188 }
189
190/*! @brief Clock ip name array for UART. */
191#define UART_CLOCKS \
192 { \
193 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2 \
194 }
195
196/*! @brief Clock ip name array for CRC. */
197#define CRC_CLOCKS \
198 { \
199 kCLOCK_Crc0 \
200 }
201
202/*! @brief Clock ip name array for I2C. */
203#define I2C_CLOCKS \
204 { \
205 kCLOCK_I2c0, kCLOCK_I2c1 \
206 }
207
208/*! @brief Clock ip name array for FTF. */
209#define FTF_CLOCKS \
210 { \
211 kCLOCK_Ftf0 \
212 }
213
214/*! @brief Clock ip name array for PDB. */
215#define PDB_CLOCKS \
216 { \
217 kCLOCK_Pdb0 \
218 }
219
220/*! @brief Clock ip name array for CMP. */
221#define CMP_CLOCKS \
222 { \
223 kCLOCK_Cmp0, kCLOCK_Cmp1 \
224 }
225
226/*!
227 * @brief LPO clock frequency.
228 */
229#define LPO_CLK_FREQ 1000U
230
231/*! @brief Peripherals clock source definition. */
232#define SYS_CLK kCLOCK_CoreSysClk
233#define BUS_CLK kCLOCK_BusClk
234#define FAST_CLK kCLOCK_FastPeriphClk
235
236#define I2C0_CLK_SRC BUS_CLK
237#define I2C1_CLK_SRC BUS_CLK
238#define DSPI0_CLK_SRC BUS_CLK
239#define DSPI1_CLK_SRC BUS_CLK
240#define UART0_CLK_SRC SYS_CLK
241#define UART1_CLK_SRC SYS_CLK
242#define UART2_CLK_SRC BUS_CLK
243
244/*! @brief Clock name used to get clock frequency. */
245typedef enum _clock_name
246{
247
248 /* ----------------------------- System layer clock -------------------------------*/
249 kCLOCK_CoreSysClk, /*!< Core/system clock */
250 kCLOCK_PlatClk, /*!< Platform clock */
251 kCLOCK_BusClk, /*!< Bus clock */
252 kCLOCK_FlexBusClk, /*!< FlexBus clock */
253 kCLOCK_FlashClk, /*!< Flash clock */
254 kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */
255 kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */
256
257 /* ---------------------------------- OSC clock -----------------------------------*/
258 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
259 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
260 kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */
261 kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */
262
263 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
264 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
265 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
266 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
267 kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */
268 kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */
269 kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */
270 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
271 kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */
272
273 /* --------------------------------- Other clock ----------------------------------*/
274 kCLOCK_LpoClk, /*!< LPO clock */
275
276} clock_name_t;
277
278/*! @brief USB clock source definition. */
279typedef enum _clock_usb_src
280{
281 kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */
282 kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M. */
283 kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */
284} clock_usb_src_t;
285/*------------------------------------------------------------------------------
286
287 clock_gate_t definition:
288
289 31 16 0
290 -----------------------------------------------------------------
291 | SIM_SCGC register offset | control bit offset in SCGC |
292 -----------------------------------------------------------------
293
294 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
295 SIM_SCGC3 offset in SIM is 0x1030, then kCLOCK_GateSdhc0 is defined as
296
297 kCLOCK_GateSdhc0 = (0x1030 << 16) | 17;
298
299------------------------------------------------------------------------------*/
300
301#define CLK_GATE_REG_OFFSET_SHIFT 16U
302#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
303#define CLK_GATE_BIT_SHIFT_SHIFT 0U
304#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
305
306#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
307 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
308 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
309
310#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
311#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
312
313/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
314typedef enum _clock_ip_name
315{
316 kCLOCK_IpInvalid = 0U,
317
318 kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
319 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
320 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
321 kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U),
322 kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U),
323 kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U),
324 kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U),
325 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
326 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
327 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
328
329 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
330 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
331 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
332 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
333 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
334 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
335
336 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
337 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
338 kCLOCK_Adc1 = CLK_GATE_DEFINE(0x103CU, 7U),
339 kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x103CU, 10U),
340 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
341 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
342 kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U),
343 kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
344 kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
345 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
346 kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U),
347 kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U),
348 kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U),
349 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
350 kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
351 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x103CU, 31U),
352
353 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
354} clock_ip_name_t;
355
356/*!@brief SIM configuration structure for clock setting. */
357typedef struct _sim_clock_config
358{
359 uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
360 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
361 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
362} sim_clock_config_t;
363
364/*! @brief OSC work mode. */
365typedef enum _osc_mode
366{
367 kOSC_ModeExt = 0U, /*!< Use an external clock. */
368#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
369 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
370#else
371 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
372#endif
373 kOSC_ModeOscHighGain = 0U
374#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
375 | MCG_C2_EREFS_MASK
376#else
377 | MCG_C2_EREFS0_MASK
378#endif
379#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
380 | MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
381#else
382 | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
383#endif
384} osc_mode_t;
385
386/*! @brief Oscillator capacitor load setting.*/
387enum _osc_cap_load
388{
389 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
390 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
391 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
392 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
393};
394
395/*! @brief OSCERCLK enable mode. */
396enum _oscer_enable_mode
397{
398 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
399 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
400};
401
402/*! @brief OSC configuration for OSCERCLK. */
403typedef struct _oscer_config
404{
405 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */
406
407 uint8_t erclkDiv; /*!< Divider for OSCERCLK.*/
408} oscer_config_t;
409
410/*!
411 * @brief OSC Initialization Configuration Structure
412 *
413 * Defines the configuration data structure to initialize the OSC.
414 * When porting to a new board, set the following members
415 * according to the board setting:
416 * 1. freq: The external frequency.
417 * 2. workMode: The OSC module mode.
418 */
419typedef struct _osc_config
420{
421 uint32_t freq; /*!< External clock frequency. */
422 uint8_t capLoad; /*!< Capacitor load setting. */
423 osc_mode_t workMode; /*!< OSC work mode setting. */
424 oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
425} osc_config_t;
426
427/*! @brief MCG FLL reference clock source select. */
428typedef enum _mcg_fll_src
429{
430 kMCG_FllSrcExternal, /*!< External reference clock is selected */
431 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
432} mcg_fll_src_t;
433
434/*! @brief MCG internal reference clock select */
435typedef enum _mcg_irc_mode
436{
437 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
438 kMCG_IrcFast /*!< Fast internal reference clock selected */
439} mcg_irc_mode_t;
440
441/*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
442typedef enum _mcg_dmx32
443{
444 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
445 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
446} mcg_dmx32_t;
447
448/*! @brief MCG DCO range select */
449typedef enum _mcg_drs
450{
451 kMCG_DrsLow, /*!< Low frequency range */
452 kMCG_DrsMid, /*!< Mid frequency range */
453 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
454 kMCG_DrsHigh /*!< High frequency range */
455} mcg_drs_t;
456
457/*! @brief MCG PLL reference clock select */
458typedef enum _mcg_pll_ref_src
459{
460 kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
461 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
462} mcg_pll_ref_src_t;
463
464/*! @brief MCGOUT clock source. */
465typedef enum _mcg_clkout_src
466{
467 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
468 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
469 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
470} mcg_clkout_src_t;
471
472/*! @brief MCG Automatic Trim Machine Select */
473typedef enum _mcg_atm_select
474{
475 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
476 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
477} mcg_atm_select_t;
478
479/*! @brief MCG OSC Clock Select */
480typedef enum _mcg_oscsel
481{
482 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
483 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
484 kMCG_OscselIrc /*!< Selects 48 MHz IRC Oscillator */
485} mcg_oscsel_t;
486
487/*! @brief MCG PLLCS select */
488typedef enum _mcg_pll_clk_select
489{
490 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
491 kMCG_PllClkSelPll1 /* PLL1 output clock is selected */
492} mcg_pll_clk_select_t;
493
494/*! @brief MCG clock monitor mode. */
495typedef enum _mcg_monitor_mode
496{
497 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
498 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
499 kMCG_MonitorReset /*!< System reset when clock lost. */
500} mcg_monitor_mode_t;
501
502/*! @brief MCG status. Enumeration _mcg_status */
503enum
504{
505 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0U), /*!< Can't switch to target mode. */
506 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1U), /*!< Current mode invalid for the specific
507 function. */
508 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2U), /*!< Invalid bus clock for ATM. */
509 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3U), /*!< Invalid desired frequency for ATM. */
510 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4U), /*!< IRC is used when using ATM. */
511 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5U), /*!< Hardware fail occurs during ATM. */
512 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6U) /*!< Can't change the clock source because
513 it is in use. */
514};
515
516/*! @brief MCG status flags. Enumeration _mcg_status_flags_t */
517enum
518{
519 kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */
520 kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */
521 kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */
522};
523
524/*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. Enumeration _mcg_irclk_enable_mode */
525enum
526{
527 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
528 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
529};
530
531/*! @brief MCG mode definitions */
532typedef enum _mcg_mode
533{
534 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
535 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
536 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
537 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
538 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
539 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
540 kMCG_ModeError /*!< Unknown mode */
541} mcg_mode_t;
542
543/*! @brief MCG mode change configuration structure
544 *
545 * When porting to a new board, set the following members
546 * according to the board setting:
547 * 1. frdiv: If the FLL uses the external reference clock, set this
548 * value to ensure that the external reference clock divided by frdiv is
549 * in the 31.25 kHz to 39.0625 kHz range.
550 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
551 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
552 * FSL_FEATURE_MCG_PLL_REF_MAX range.
553 */
554typedef struct _mcg_config
555{
556 mcg_mode_t mcgMode; /*!< MCG mode. */
557
558 /* ----------------------- MCGIRCCLK settings ------------------------ */
559 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
560 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
561 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
562
563 /* ------------------------ MCG FLL settings ------------------------- */
564 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
565 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
566 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
567 mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */
568
569 /* ------------------------ MCG PLL settings ------------------------- */
570} mcg_config_t;
571
572/*******************************************************************************
573 * API
574 ******************************************************************************/
575
576#if defined(__cplusplus)
577extern "C" {
578#endif /* __cplusplus */
579
580/*!
581 * @brief Enable the clock for specific IP.
582 *
583 * @param name Which clock to enable, see \ref clock_ip_name_t.
584 */
585static inline void CLOCK_EnableClock(clock_ip_name_t name)
586{
587 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
588 (*(volatile uint32_t *)regAddr) |= (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
589}
590
591/*!
592 * @brief Disable the clock for specific IP.
593 *
594 * @param name Which clock to disable, see \ref clock_ip_name_t.
595 */
596static inline void CLOCK_DisableClock(clock_ip_name_t name)
597{
598 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
599 (*(volatile uint32_t *)regAddr) &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
600}
601
602/*!
603 * @brief Set LPUART clock source.
604 *
605 * @param src The value to set LPUART clock source.
606 */
607static inline void CLOCK_SetLpuartClock(uint32_t src)
608{
609 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUARTSRC_MASK) | SIM_SOPT2_LPUARTSRC(src));
610}
611
612/*!
613 * @brief Set ERCLK32K source.
614 *
615 * @param src The value to set ERCLK32K clock source.
616 */
617static inline void CLOCK_SetEr32kClock(uint32_t src)
618{
619 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
620}
621
622/*!
623 * @brief Set debug trace clock source.
624 *
625 * @param src The value to set debug trace clock source.
626 */
627static inline void CLOCK_SetTraceClock(uint32_t src)
628{
629 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src));
630}
631
632/*!
633 * @brief Set PLLFLLSEL clock source.
634 *
635 * @param src The value to set PLLFLLSEL clock source.
636 */
637static inline void CLOCK_SetPllFllSelClock(uint32_t src)
638{
639 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src));
640}
641
642/*!
643 * @brief Set CLKOUT source.
644 *
645 * @param src The value to set CLKOUT source.
646 */
647static inline void CLOCK_SetClkOutClock(uint32_t src)
648{
649 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
650}
651
652/*!
653 * @brief Set RTC_CLKOUT source.
654 *
655 * @param src The value to set RTC_CLKOUT source.
656 */
657static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
658{
659 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src));
660}
661
662/*! @brief Enable USB FS clock.
663 *
664 * @param src USB FS clock source.
665 * @param freq The frequency specified by src.
666 * @retval true The clock is set successfully.
667 * @retval false The clock source is invalid to get proper USB FS clock.
668 */
669bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
670
671/*! @brief Disable USB FS clock.
672 *
673 * Disable USB FS clock.
674 */
675static inline void CLOCK_DisableUsbfs0Clock(void)
676{
677 CLOCK_DisableClock(kCLOCK_Usbfs0);
678}
679
680/*!
681 * @brief System clock divider
682 *
683 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV4].
684 *
685 * @param outdiv1 Clock 1 output divider value.
686 *
687 * @param outdiv2 Clock 2 output divider value.
688 *
689 * @param outdiv4 Clock 4 output divider value.
690 */
691static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv4)
692{
693 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV4(outdiv4);
694}
695
696/*!
697 * @brief Gets the clock frequency for a specific clock name.
698 *
699 * This function checks the current clock configurations and then calculates
700 * the clock frequency for a specific clock name defined in clock_name_t.
701 * The MCG must be properly configured before using this function.
702 *
703 * @param clockName Clock names defined in clock_name_t
704 * @return Clock frequency value in Hertz
705 */
706uint32_t CLOCK_GetFreq(clock_name_t clockName);
707
708/*!
709 * @brief Get the core clock or system clock frequency.
710 *
711 * @return Clock frequency in Hz.
712 */
713uint32_t CLOCK_GetCoreSysClkFreq(void);
714
715/*!
716 * @brief Get the platform clock frequency.
717 *
718 * @return Clock frequency in Hz.
719 */
720uint32_t CLOCK_GetPlatClkFreq(void);
721
722/*!
723 * @brief Get the bus clock frequency.
724 *
725 * @return Clock frequency in Hz.
726 */
727uint32_t CLOCK_GetBusClkFreq(void);
728
729/*!
730 * @brief Get the flash clock frequency.
731 *
732 * @return Clock frequency in Hz.
733 */
734uint32_t CLOCK_GetFlashClkFreq(void);
735
736/*!
737 * @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
738 *
739 * @return Clock frequency in Hz.
740 */
741uint32_t CLOCK_GetPllFllSelClkFreq(void);
742
743/*!
744 * @brief Get the external reference 32K clock frequency (ERCLK32K).
745 *
746 * @return Clock frequency in Hz.
747 */
748uint32_t CLOCK_GetEr32kClkFreq(void);
749
750/*!
751 * @brief Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV).
752 *
753 * @return Clock frequency in Hz.
754 */
755uint32_t CLOCK_GetOsc0ErClkUndivFreq(void);
756
757/*!
758 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
759 *
760 * @return Clock frequency in Hz.
761 */
762uint32_t CLOCK_GetOsc0ErClkFreq(void);
763
764/*!
765 * @brief Get the OSC0 external reference divided clock frequency.
766 *
767 * @return Clock frequency in Hz.
768 */
769uint32_t CLOCK_GetOsc0ErClkDivFreq(void);
770
771/*!
772 * @brief Set the clock configure in SIM module.
773 *
774 * This function sets system layer clock settings in SIM module.
775 *
776 * @param config Pointer to the configure structure.
777 */
778void CLOCK_SetSimConfig(sim_clock_config_t const *config);
779
780/*!
781 * @brief Set the system clock dividers in SIM to safe value.
782 *
783 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
784 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
785 * changes then the system level clocks may be out of range. This function could
786 * be used before MCG mode change, to make sure system level clocks are in allowed
787 * range.
788 *
789 * @param config Pointer to the configure structure.
790 */
791static inline void CLOCK_SetSimSafeDivs(void)
792{
793 SIM->CLKDIV1 = 0x11070000U;
794}
795
796/*! @name MCG frequency functions. */
797/*@{*/
798
799/*!
800 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
801 *
802 * This function gets the MCG output clock frequency in Hz based on the current MCG
803 * register value.
804 *
805 * @return The frequency of MCGOUTCLK.
806 */
807uint32_t CLOCK_GetOutClkFreq(void);
808
809/*!
810 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
811 *
812 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
813 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
814 * disabled in low power state in other modes.
815 *
816 * @return The frequency of MCGFLLCLK.
817 */
818uint32_t CLOCK_GetFllFreq(void);
819
820/*!
821 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
822 *
823 * This function gets the MCG internal reference clock frequency in Hz based
824 * on the current MCG register value.
825 *
826 * @return The frequency of MCGIRCLK.
827 */
828uint32_t CLOCK_GetInternalRefClkFreq(void);
829
830/*!
831 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
832 *
833 * This function gets the MCG fixed frequency clock frequency in Hz based
834 * on the current MCG register value.
835 *
836 * @return The frequency of MCGFFCLK.
837 */
838uint32_t CLOCK_GetFixedFreqClkFreq(void);
839
840/*@}*/
841
842/*! @name MCG clock configuration. */
843/*@{*/
844
845/*!
846 * @brief Enables or disables the MCG low power.
847 *
848 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
849 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
850 * PBI modes, enabling low power sets the MCG to BLPI mode.
851 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
852 *
853 * @param enable True to enable MCG low power, false to disable MCG low power.
854 */
855static inline void CLOCK_SetLowPowerEnable(bool enable)
856{
857 if (enable)
858 {
859 MCG->C2 |= MCG_C2_LP_MASK;
860 }
861 else
862 {
863 MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
864 }
865}
866
867/*!
868 * @brief Configures the Internal Reference clock (MCGIRCLK).
869 *
870 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
871 * source. If the fast IRC is used, this function sets the fast IRC divider.
872 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
873 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
874 * using the function in these modes it is not allowed.
875 *
876 * @param enableMode MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
877 * @param ircs MCGIRCLK clock source, choose fast or slow.
878 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
879 * @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source,
880 * the configuration should not be changed. Otherwise, a glitch occurs.
881 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
882 */
883status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
884
885/*!
886 * @brief Selects the MCG external reference clock.
887 *
888 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
889 * and waits for the clock source to be stable. Because the external reference
890 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
891 *
892 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
893 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
894 * the configuration should not be changed. Otherwise, a glitch occurs.
895 * @retval kStatus_Success External reference clock set successfully.
896 */
897status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
898
899/*!
900 * @brief Set the FLL external reference clock divider value.
901 *
902 * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
903 *
904 * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
905 */
906static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
907{
908 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
909}
910
911/*@}*/
912
913/*! @name MCG clock lock monitor functions. */
914/*@{*/
915
916/*!
917 * @brief Sets the OSC0 clock monitor mode.
918 *
919 * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
920 *
921 * @param mode Monitor mode to set.
922 */
923void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
924
925/*!
926 * @brief Sets the RTC OSC clock monitor mode.
927 *
928 * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
929 *
930 * @param mode Monitor mode to set.
931 */
932void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
933
934/*!
935 * @brief Gets the MCG status flags.
936 *
937 * This function gets the MCG clock status flags. All status flags are
938 * returned as a logical OR of the enumeration refer to _mcg_status_flags_t. To
939 * check a specific flag, compare the return value with the flag.
940 *
941 * Example:
942 * @code
943 * To check the clock lost lock status of OSC0 and PLL0.
944 * uint32_t mcgFlags;
945 *
946 * mcgFlags = CLOCK_GetStatusFlags();
947 *
948 * if (mcgFlags & kMCG_Osc0LostFlag)
949 * {
950 * OSC0 clock lock lost. Do something.
951 * }
952 * if (mcgFlags & kMCG_Pll0LostFlag)
953 * {
954 * PLL0 clock lock lost. Do something.
955 * }
956 * @endcode
957 *
958 * @return Logical OR value of the enumeration _mcg_status_flags_t.
959 */
960uint32_t CLOCK_GetStatusFlags(void);
961
962/*!
963 * @brief Clears the MCG status flags.
964 *
965 * This function clears the MCG clock lock lost status. The parameter is a logical
966 * OR value of the flags to clear. See the enumeration _mcg_status_flags_t.
967 *
968 * Example:
969 * @code
970 * To clear the clock lost lock status flags of OSC0 and PLL0.
971 *
972 * CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
973 * @endcode
974 *
975 * @param mask The status flags to clear. This is a logical OR of members of the
976 * enumeration _mcg_status_flags_t.
977 */
978void CLOCK_ClearStatusFlags(uint32_t mask);
979
980/*@}*/
981
982/*!
983 * @name OSC configuration
984 * @{
985 */
986
987/*!
988 * @brief Configures the OSC external reference clock (OSCERCLK).
989 *
990 * This function configures the OSC external reference clock (OSCERCLK).
991 * This is an example to enable the OSCERCLK in normal and stop modes and also set
992 * the output divider to 1:
993 *
994 @code
995 oscer_config_t config =
996 {
997 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
998 .erclkDiv = 1U,
999 };
1000
1001 OSC_SetExtRefClkConfig(OSC, &config);
1002 @endcode
1003 *
1004 * @param base OSC peripheral address.
1005 * @param config Pointer to the configuration structure.
1006 */
1007static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
1008{
1009 uint8_t reg = base->CR;
1010
1011 reg &= (uint8_t)(~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK));
1012 reg |= config->enableMode;
1013
1014 base->CR = reg;
1015
1016 base->DIV = OSC_DIV_ERPS(config->erclkDiv);
1017}
1018
1019/*!
1020 * @brief Sets the capacitor load configuration for the oscillator.
1021 *
1022 * This function sets the specified capacitors configuration for the oscillator.
1023 * This should be done in the early system level initialization function call
1024 * based on the system configuration.
1025 *
1026 * @param base OSC peripheral address.
1027 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
1028 *
1029 * Example:
1030 @code
1031 To enable only 2 pF and 8 pF capacitor load, please use like this.
1032 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
1033 @endcode
1034 */
1035static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
1036{
1037 uint8_t reg = base->CR;
1038
1039 reg &= (uint8_t)(~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK));
1040 reg |= capLoad;
1041
1042 base->CR = reg;
1043}
1044
1045/*!
1046 * @brief Initializes the OSC0.
1047 *
1048 * This function initializes the OSC0 according to the board configuration.
1049 *
1050 * @param config Pointer to the OSC0 configuration structure.
1051 */
1052void CLOCK_InitOsc0(osc_config_t const *config);
1053
1054/*!
1055 * @brief Deinitializes the OSC0.
1056 *
1057 * This function deinitializes the OSC0.
1058 */
1059void CLOCK_DeinitOsc0(void);
1060
1061/* @} */
1062
1063/*!
1064 * @name External clock frequency
1065 * @{
1066 */
1067
1068/*!
1069 * @brief Sets the XTAL0 frequency based on board settings.
1070 *
1071 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
1072 */
1073static inline void CLOCK_SetXtal0Freq(uint32_t freq)
1074{
1075 g_xtal0Freq = freq;
1076}
1077
1078/*!
1079 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
1080 *
1081 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
1082 */
1083static inline void CLOCK_SetXtal32Freq(uint32_t freq)
1084{
1085 g_xtal32Freq = freq;
1086}
1087/* @} */
1088
1089/*!
1090 * @name IRCs frequency
1091 * @{
1092 */
1093
1094/*!
1095 * @brief Set the Slow IRC frequency based on the trimmed value
1096 *
1097 * @param freq The Slow IRC frequency input clock frequency in Hz.
1098 */
1099void CLOCK_SetSlowIrcFreq(uint32_t freq);
1100
1101/*!
1102 * @brief Set the Fast IRC frequency based on the trimmed value
1103 *
1104 * @param freq The Fast IRC frequency input clock frequency in Hz.
1105 */
1106void CLOCK_SetFastIrcFreq(uint32_t freq);
1107/* @} */
1108
1109/*!
1110 * @name MCG auto-trim machine.
1111 * @{
1112 */
1113
1114/*!
1115 * @brief Auto trims the internal reference clock.
1116 *
1117 * This function trims the internal reference clock by using the external clock. If
1118 * successful, it returns the kStatus_Success and the frequency after
1119 * trimming is received in the parameter @p actualFreq. If an error occurs,
1120 * the error code is returned.
1121 *
1122 * @param extFreq External clock frequency, which should be a bus clock.
1123 * @param desireFreq Frequency to trim to.
1124 * @param actualFreq Actual frequency after trimming.
1125 * @param atms Trim fast or slow internal reference clock.
1126 * @retval kStatus_Success ATM success.
1127 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
1128 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
1129 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
1130 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
1131 */
1132status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
1133/* @} */
1134
1135/*! @name MCG mode functions. */
1136/*@{*/
1137
1138/*!
1139 * @brief Gets the current MCG mode.
1140 *
1141 * This function checks the MCG registers and determines the current MCG mode.
1142 *
1143 * @return Current MCG mode or error code; See @ref mcg_mode_t.
1144 */
1145mcg_mode_t CLOCK_GetMode(void);
1146
1147/*!
1148 * @brief Sets the MCG to FEI mode.
1149 *
1150 * This function sets the MCG to FEI mode. If setting to FEI mode fails
1151 * from the current mode, this function returns an error.
1152 *
1153 * @param dmx32 DMX32 in FEI mode.
1154 * @param drs The DCO range selection.
1155 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
1156 * NULL does not cause a delay.
1157 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1158 * @retval kStatus_Success Switched to the target mode successfully.
1159 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1160 * to a frequency above 32768 Hz.
1161 */
1162status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1163
1164/*!
1165 * @brief Sets the MCG to FEE mode.
1166 *
1167 * This function sets the MCG to FEE mode. If setting to FEE mode fails
1168 * from the current mode, this function returns an error.
1169 *
1170 * @param frdiv FLL reference clock divider setting, FRDIV.
1171 * @param dmx32 DMX32 in FEE mode.
1172 * @param drs The DCO range selection.
1173 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
1174 * NULL does not cause a delay.
1175 *
1176 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1177 * @retval kStatus_Success Switched to the target mode successfully.
1178 */
1179status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1180
1181/*!
1182 * @brief Sets the MCG to FBI mode.
1183 *
1184 * This function sets the MCG to FBI mode. If setting to FBI mode fails
1185 * from the current mode, this function returns an error.
1186 *
1187 * @param dmx32 DMX32 in FBI mode.
1188 * @param drs The DCO range selection.
1189 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1190 * is not used in FBI mode, this parameter can be NULL. Passing
1191 * NULL does not cause a delay.
1192 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1193 * @retval kStatus_Success Switched to the target mode successfully.
1194 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1195 * to frequency above 32768 Hz.
1196 */
1197status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1198
1199/*!
1200 * @brief Sets the MCG to FBE mode.
1201 *
1202 * This function sets the MCG to FBE mode. If setting to FBE mode fails
1203 * from the current mode, this function returns an error.
1204 *
1205 * @param frdiv FLL reference clock divider setting, FRDIV.
1206 * @param dmx32 DMX32 in FBE mode.
1207 * @param drs The DCO range selection.
1208 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1209 * is not used in FBE mode, this parameter can be NULL. Passing NULL
1210 * does not cause a delay.
1211 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1212 * @retval kStatus_Success Switched to the target mode successfully.
1213 */
1214status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1215
1216/*!
1217 * @brief Sets the MCG to BLPI mode.
1218 *
1219 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
1220 * from the current mode, this function returns an error.
1221 *
1222 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1223 * @retval kStatus_Success Switched to the target mode successfully.
1224 */
1225status_t CLOCK_SetBlpiMode(void);
1226
1227/*!
1228 * @brief Sets the MCG to BLPE mode.
1229 *
1230 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
1231 * from the current mode, this function returns an error.
1232 *
1233 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1234 * @retval kStatus_Success Switched to the target mode successfully.
1235 */
1236status_t CLOCK_SetBlpeMode(void);
1237
1238/*!
1239 * @brief Switches the MCG to FBE mode from the external mode.
1240 *
1241 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
1242 * The external clock is used as the system clock source and PLL is disabled. However,
1243 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
1244 * during the mode switch. For example, to switch from PEE mode to FEI mode:
1245 *
1246 * @code
1247 * CLOCK_ExternalModeToFbeModeQuick();
1248 * CLOCK_SetFeiMode(...);
1249 * @endcode
1250 *
1251 * @retval kStatus_Success Switched successfully.
1252 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
1253 */
1254status_t CLOCK_ExternalModeToFbeModeQuick(void);
1255
1256/*!
1257 * @brief Switches the MCG to FBI mode from internal modes.
1258 *
1259 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
1260 * The MCGIRCLK is used as the system clock source and PLL is disabled. However,
1261 * FLL settings are not configured. This is a lite function with a small code size, which is useful
1262 * during the mode switch. For example, to switch from PEI mode to FEE mode:
1263 *
1264 * @code
1265 * CLOCK_InternalModeToFbiModeQuick();
1266 * CLOCK_SetFeeMode(...);
1267 * @endcode
1268 *
1269 * @retval kStatus_Success Switched successfully.
1270 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
1271 */
1272status_t CLOCK_InternalModeToFbiModeQuick(void);
1273
1274/*!
1275 * @brief Sets the MCG to FEI mode during system boot up.
1276 *
1277 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
1278 * set up MCG during system boot up.
1279 *
1280 * @param dmx32 DMX32 in FEI mode.
1281 * @param drs The DCO range selection.
1282 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1283 *
1284 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1285 * @retval kStatus_Success Switched to the target mode successfully.
1286 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1287 * to frequency above 32768 Hz.
1288 */
1289status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1290
1291/*!
1292 * @brief Sets the MCG to FEE mode during system bootup.
1293 *
1294 * This function sets MCG to FEE mode from the reset mode. It can also be used to
1295 * set up the MCG during system boot up.
1296 *
1297 * @param oscsel OSC clock select, OSCSEL.
1298 * @param frdiv FLL reference clock divider setting, FRDIV.
1299 * @param dmx32 DMX32 in FEE mode.
1300 * @param drs The DCO range selection.
1301 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1302 *
1303 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1304 * @retval kStatus_Success Switched to the target mode successfully.
1305 */
1306status_t CLOCK_BootToFeeMode(
1307 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1308
1309/*!
1310 * @brief Sets the MCG to BLPI mode during system boot up.
1311 *
1312 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
1313 * set up the MCG during system boot up.
1314 *
1315 * @param fcrdiv Fast IRC divider, FCRDIV.
1316 * @param ircs The internal reference clock to select, IRCS.
1317 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
1318 *
1319 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
1320 * @retval kStatus_Success Switched to the target mode successfully.
1321 */
1322status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
1323
1324/*!
1325 * @brief Sets the MCG to BLPE mode during system boot up.
1326 *
1327 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
1328 * set up the MCG during system boot up.
1329 *
1330 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1331 *
1332 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1333 * @retval kStatus_Success Switched to the target mode successfully.
1334 */
1335status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
1336
1337/*!
1338 * @brief Sets the MCG to a target mode.
1339 *
1340 * This function sets MCG to a target mode defined by the configuration
1341 * structure. If switching to the target mode fails, this function
1342 * chooses the correct path.
1343 *
1344 * @param config Pointer to the target MCG mode configuration structure.
1345 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code _mcg_status.
1346 *
1347 * @note If the external clock is used in the target mode, ensure that it is
1348 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
1349 * function.
1350 */
1351status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
1352
1353/*@}*/
1354
1355#if defined(__cplusplus)
1356}
1357#endif /* __cplusplus */
1358
1359/*! @} */
1360
1361#endif /* _FSL_CLOCK_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 18:28:07 +0100