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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/MK28FA15.h29390
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/MK28FA15_features.h1597
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/all_lib_device_MK28FA15.cmake126
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/arm/MK_P2M0.FLMbin0 -> 26580 bytes
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/device_CMSIS.cmake15
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/device_startup.cmake15
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/device_system.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/drivers/driver_clock.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/drivers/driver_reset.cmake14
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/drivers/fsl_clock.c2630
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/drivers/fsl_clock.h1754
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/fsl_device_registers.h34
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/gcc/MK28FN2M0Axxx15_flash.ld232
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/gcc/MK28FN2M0Axxx15_ram.ld215
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/gcc/startup_MK28FA15.S908
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/mcuxpresso/startup_mk28fa15.c1057
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/mcuxpresso/startup_mk28fa15.cpp1057
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/project_template/board.c39
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/project_template/board.h205
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/project_template/clock_config.c181
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/project_template/clock_config.h76
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/project_template/peripherals.c51
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/project_template/peripherals.h34
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/project_template/pin_mux.c60
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/project_template/pin_mux.h52
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/system_MK28FA15.c213
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/system_MK28FA15.h133
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/template/RTE_Device.h203
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/utilities/fsl_notifier.c209
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/utilities/fsl_notifier.h237
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/utilities/fsl_shell.c1085
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/utilities/fsl_shell.h292
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/utilities/utility_notifier.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/utilities/utility_shell.cmake18
34 files changed, 42180 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/MK28FA15.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/MK28FA15.h
new file mode 100644
index 000000000..103ee3d48
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/MK28FA15.h
@@ -0,0 +1,29390 @@
1/*
2** ###################################################################
3** Processors: MK28FN2M0ACAU15R
4** MK28FN2M0AVMI15
5**
6** Compilers: Keil ARM C/C++ Compiler
7** Freescale C/C++ for Embedded ARM
8** GNU C Compiler
9** IAR ANSI C/C++ Compiler for ARM
10** MCUXpresso Compiler
11**
12** Reference manual: K28P210M150SF5RM, Rev. 4, Aug 2017
13** Version: rev. 1.3, 2018-01-09
14** Build: b180801
15**
16** Abstract:
17** CMSIS Peripheral Access Layer for MK28FA15
18**
19** Copyright 1997-2016 Freescale Semiconductor, Inc.
20** Copyright 2016-2018 NXP
21**
22** SPDX-License-Identifier: BSD-3-Clause
23**
24** http: www.nxp.com
25** mail: [email protected]
26**
27** Revisions:
28** - rev. 1.0 (2016-05-10)
29** Initial version
30** - rev. 1.1 (2016-10-20)
31** Update based on Rev1 RM.
32** - rev. 1.2 (2017-04-06)
33** Remove TSI.
34** Add ISD2FA, ISD3FA, ISD2FB and ISD3FB bits in QuadSPI0_MCR.
35** - rev. 1.3 (2018-01-09)
36** Add K28FA support.
37**
38** ###################################################################
39*/
40
41/*!
42 * @file MK28FA15.h
43 * @version 1.3
44 * @date 2018-01-09
45 * @brief CMSIS Peripheral Access Layer for MK28FA15
46 *
47 * CMSIS Peripheral Access Layer for MK28FA15
48 */
49
50#ifndef _MK28FA15_H_
51#define _MK28FA15_H_ /**< Symbol preventing repeated inclusion */
52
53/** Memory map major version (memory maps with equal major version number are
54 * compatible) */
55#define MCU_MEM_MAP_VERSION 0x0100U
56/** Memory map minor version */
57#define MCU_MEM_MAP_VERSION_MINOR 0x0003U
58
59/**
60 * @brief Macro to calculate address of an aliased word in the peripheral
61 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
62 * 0x400FFFFF).
63 * @param Reg Register to access.
64 * @param Bit Bit number to access.
65 * @return Address of the aliased word in the peripheral bitband area.
66 */
67#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
68/**
69 * @brief Macro to access a single bit of a peripheral register (bit band region
70 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
71 * be used for peripherals with 32bit access allowed.
72 * @param Reg Register to access.
73 * @param Bit Bit number to access.
74 * @return Value of the targeted bit in the bit band region.
75 */
76#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
77#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
78/**
79 * @brief Macro to access a single bit of a peripheral register (bit band region
80 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
81 * be used for peripherals with 16bit access allowed.
82 * @param Reg Register to access.
83 * @param Bit Bit number to access.
84 * @return Value of the targeted bit in the bit band region.
85 */
86#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
87/**
88 * @brief Macro to access a single bit of a peripheral register (bit band region
89 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
90 * be used for peripherals with 8bit access allowed.
91 * @param Reg Register to access.
92 * @param Bit Bit number to access.
93 * @return Value of the targeted bit in the bit band region.
94 */
95#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
96
97/* ----------------------------------------------------------------------------
98 -- Interrupt vector numbers
99 ---------------------------------------------------------------------------- */
100
101/*!
102 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
103 * @{
104 */
105
106/** Interrupt Number Definitions */
107#define NUMBER_OF_INT_VECTORS 123 /**< Number of interrupts in the Vector table */
108
109typedef enum IRQn {
110 /* Auxiliary constants */
111 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
112
113 /* Core interrupts */
114 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
115 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
116 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
117 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
118 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
119 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
120 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
121 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
122 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
123
124 /* Device specific interrupts */
125 DMA0_DMA16_IRQn = 0, /**< DMA channel 0,16 transfer complete */
126 DMA1_DMA17_IRQn = 1, /**< DMA channel 1,17 transfer complete */
127 DMA2_DMA18_IRQn = 2, /**< DMA channel 2,18 transfer complete */
128 DMA3_DMA19_IRQn = 3, /**< DMA channel 3,19 transfer complete */
129 DMA4_DMA20_IRQn = 4, /**< DMA channel 4,20 transfer complete */
130 DMA5_DMA21_IRQn = 5, /**< DMA channel 5,21 transfer complete */
131 DMA6_DMA22_IRQn = 6, /**< DMA channel 6,22 transfer complete */
132 DMA7_DMA23_IRQn = 7, /**< DMA channel 7,23 transfer complete */
133 DMA8_DMA24_IRQn = 8, /**< DMA channel 8,24 transfer complete */
134 DMA9_DMA25_IRQn = 9, /**< DMA channel 9,25 transfer complete */
135 DMA10_DMA26_IRQn = 10, /**< DMA channel 10,26 transfer complete */
136 DMA11_DMA27_IRQn = 11, /**< DMA channel 11,27 transfer complete */
137 DMA12_DMA28_IRQn = 12, /**< DMA channel 12,28 transfer complete */
138 DMA13_DMA29_IRQn = 13, /**< DMA channel 13,29 transfer complete */
139 DMA14_DMA30_IRQn = 14, /**< DMA channel 14,30 transfer complete */
140 DMA15_DMA31_IRQn = 15, /**< DMA channel 15,31 transfer complete */
141 DMA_Error_IRQn = 16, /**< DMA channel 0 - 31 error */
142 MCM_IRQn = 17, /**< MCM normal interrupt */
143 FTFE_IRQn = 18, /**< FTFE command complete */
144 Read_Collision_IRQn = 19, /**< FTFE read collision */
145 LVD_LVW_IRQn = 20, /**< PMC controller low-voltage detect, low-voltage warning */
146 LLWU_IRQn = 21, /**< Low leakage wakeup unit */
147 WDOG_EWM_IRQn = 22, /**< Single interrupt vector for WDOG and EWM */
148 TRNG0_IRQn = 23, /**< True randon number generator */
149 I2C0_IRQn = 24, /**< Inter-integrated circuit 0 */
150 I2C1_IRQn = 25, /**< Inter-integrated circuit 1 */
151 SPI0_IRQn = 26, /**< Serial peripheral Interface 0 */
152 SPI1_IRQn = 27, /**< Serial peripheral Interface 1 */
153 I2S0_Tx_IRQn = 28, /**< Integrated interchip sound 0 transmit interrupt */
154 I2S0_Rx_IRQn = 29, /**< Integrated interchip sound 0 receive interrupt */
155 LPUART0_IRQn = 30, /**< LPUART0 receive/transmit/error interrupt */
156 LPUART1_IRQn = 31, /**< LPUART1 receive/transmit/error interrupt */
157 LPUART2_IRQn = 32, /**< LPUART2 receive/transmit/error interrupt */
158 LPUART3_IRQn = 33, /**< LPUART3 receive/transmit/error interrupt */
159 LPUART4_IRQn = 34, /**< LPUART4 receive/transmit/error interrupt */
160 Reserved51_IRQn = 35, /**< Reserved interrupt */
161 Reserved52_IRQn = 36, /**< Reserved interrupt */
162 Reserved53_IRQn = 37, /**< Reserved interrupt */
163 Reserved54_IRQn = 38, /**< Reserved interrupt */
164 ADC0_IRQn = 39, /**< Analog-to-digital converter 0 */
165 CMP0_IRQn = 40, /**< Comparator 0 */
166 CMP1_IRQn = 41, /**< Comparator 1 */
167 FTM0_IRQn = 42, /**< FlexTimer module 0 fault, overflow and channels interrupt */
168 FTM1_IRQn = 43, /**< FlexTimer module 1 fault, overflow and channels interrupt */
169 FTM2_IRQn = 44, /**< FlexTimer module 2 fault, overflow and channels interrupt */
170 CMT_IRQn = 45, /**< Carrier modulator transmitter */
171 RTC_IRQn = 46, /**< Real time clock */
172 RTC_Seconds_IRQn = 47, /**< Real time clock seconds */
173 PIT0CH0_IRQn = 48, /**< Periodic interrupt timer 0 channel 0 */
174 PIT0CH1_IRQn = 49, /**< Periodic interrupt timer 0 channel 1 */
175 PIT0CH2_IRQn = 50, /**< Periodic interrupt timer 0 channel 2 */
176 PIT0CH3_IRQn = 51, /**< Periodic interrupt timer 0 channel 3 */
177 PDB0_IRQn = 52, /**< Programmable delay block */
178 USB0_IRQn = 53, /**< USB OTG interrupt */
179 USBDCD_IRQn = 54, /**< USB charger detect */
180 Reserved71_IRQn = 55, /**< Reserved interrupt */
181 DAC0_IRQn = 56, /**< Digital-to-analog converter 0 */
182 MCG_IRQn = 57, /**< Multipurpose clock generator */
183 LPTMR0_LPTMR1_IRQn = 58, /**< Single interrupt vector for Low Power Timer 0 and 1 */
184 PORTA_IRQn = 59, /**< Port A pin detect interrupt */
185 PORTB_IRQn = 60, /**< Port B pin detect interrupt */
186 PORTC_IRQn = 61, /**< Port C pin detect interrupt */
187 PORTD_IRQn = 62, /**< Port D pin detect interrupt */
188 PORTE_IRQn = 63, /**< Port E pin detect interrupt */
189 SWI_IRQn = 64, /**< Software interrupt */
190 SPI2_IRQn = 65, /**< Serial peripheral Interface 2 */
191 SPI3_IRQn = 66, /**< Serial peripheral Interface 3 */
192 Reserved83_IRQn = 67, /**< Reserved interrupt */
193 I2S1_Tx_IRQn = 68, /**< Integrated interchip sound 1 transmit interrupt */
194 I2S1_Rx_IRQn = 69, /**< Integrated interchip sound 1 receive interrupt */
195 FLEXIO0_IRQn = 70, /**< FLEXIO0 */
196 FTM3_IRQn = 71, /**< FlexTimer module 3 fault, overflow and channels interrupt */
197 Reserved88_IRQn = 72, /**< Reserved interrupt */
198 Reserved89_IRQn = 73, /**< Reserved interrupt */
199 I2C2_IRQn = 74, /**< Inter-integrated circuit 2 */
200 Reserved91_IRQn = 75, /**< Reserved interrupt */
201 Reserved92_IRQn = 76, /**< Reserved interrupt */
202 Reserved93_IRQn = 77, /**< Reserved interrupt */
203 Reserved94_IRQn = 78, /**< Reserved interrupt */
204 Reserved95_IRQn = 79, /**< Reserved interrupt */
205 Reserved96_IRQn = 80, /**< Reserved interrupt */
206 SDHC_IRQn = 81, /**< Secured digital host controller */
207 Reserved98_IRQn = 82, /**< Reserved interrupt */
208 Reserved99_IRQn = 83, /**< Reserved interrupt */
209 Reserved100_IRQn = 84, /**< Reserved interrupt */
210 Reserved101_IRQn = 85, /**< Reserved interrupt */
211 Reserved102_IRQn = 86, /**< Reserved interrupt */
212 Reserved103_IRQn = 87, /**< Reserved interrupt */
213 TPM1_IRQn = 88, /**< TPM1 single interrupt vector for all sources */
214 TPM2_IRQn = 89, /**< TPM2 single interrupt vector for all sources */
215 USBHSDCD_IRQn = 90, /**< HS USB charger detect */
216 I2C3_IRQn = 91, /**< Inter-integrated circuit 3 */
217 Reserved108_IRQn = 92, /**< Reserved interrupt */
218 USBHS_IRQn = 93, /**< USB HS interrupt */
219 Reserved110_IRQn = 94, /**< Reserved interrupt */
220 Reserved111_IRQn = 95, /**< Reserved interrupt */
221 Reserved112_IRQn = 96, /**< Reserved interrupt */
222 Reserved113_IRQn = 97, /**< Reserved interrupt */
223 Reserved114_IRQn = 98, /**< Reserved interrupt */
224 Reserved115_IRQn = 99, /**< Reserved interrupt */
225 QuadSPI0_IRQn = 100, /**< qspi */
226 Reserved117_IRQn = 101, /**< Reserved interrupt */
227 Reserved118_IRQn = 102, /**< Reserved interrupt */
228 Reserved119_IRQn = 103, /**< Reserved interrupt */
229 Reserved120_IRQn = 104, /**< Reserved interrupt */
230 Reserved121_IRQn = 105, /**< Reserved interrupt */
231 Reserved122_IRQn = 106 /**< Reserved interrupt */
232} IRQn_Type;
233
234/*!
235 * @}
236 */ /* end of group Interrupt_vector_numbers */
237
238
239/* ----------------------------------------------------------------------------
240 -- Cortex M4 Core Configuration
241 ---------------------------------------------------------------------------- */
242
243/*!
244 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
245 * @{
246 */
247
248#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
249#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
250#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
251#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
252
253#include "core_cm4.h" /* Core Peripheral Access Layer */
254#include "system_MK28FA15.h" /* Device specific configuration file */
255
256/*!
257 * @}
258 */ /* end of group Cortex_Core_Configuration */
259
260
261/* ----------------------------------------------------------------------------
262 -- Mapping Information
263 ---------------------------------------------------------------------------- */
264
265/*!
266 * @addtogroup Mapping_Information Mapping Information
267 * @{
268 */
269
270/** Mapping Information */
271/*!
272 * @addtogroup edma_request
273 * @{
274 */
275
276/*******************************************************************************
277 * Definitions
278 ******************************************************************************/
279
280/*!
281 * @brief Structure for the DMA hardware request
282 *
283 * Defines the structure for the DMA hardware request collections. The user can configure the
284 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
285 * of the hardware request varies according to the to SoC.
286 */
287typedef enum _dma_request_source
288{
289 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
290 kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
291 kDmaRequestMux0LPUART0Rx = 2|0x100U, /**< LPUART0 Receive. */
292 kDmaRequestMux0LPUART0Tx = 3|0x100U, /**< LPUART0 Transmit. */
293 kDmaRequestMux0LPUART1Rx = 4|0x100U, /**< LPUART1 Receive. */
294 kDmaRequestMux0LPUART1Tx = 5|0x100U, /**< LPUART1 Transmit. */
295 kDmaRequestMux0LPUART2Rx = 6|0x100U, /**< LPUART2 Receive. */
296 kDmaRequestMux0LPUART2Tx = 7|0x100U, /**< LPUART2 Transmit. */
297 kDmaRequestMux0LPUART3Rx = 8|0x100U, /**< LPUART3 Receive. */
298 kDmaRequestMux0LPUART3Tx = 9|0x100U, /**< LPUART3 Transmit. */
299 kDmaRequestMux0LPUART4Rx = 10|0x100U, /**< LPUART4 Receive. */
300 kDmaRequestMux0LPUART4Tx = 11|0x100U, /**< LPUART4 Transmit. */
301 kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */
302 kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */
303 kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
304 kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
305 kDmaRequestMux0SPI1Rx = 16|0x100U, /**< SPI1 Receive. */
306 kDmaRequestMux0SPI1Tx = 17|0x100U, /**< SPI1 Transmit. */
307 kDmaRequestMux0I2C0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */
308 kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0 and I2C3. */
309 kDmaRequestMux0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */
310 kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
311 kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */
312 kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
313 kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
314 kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
315 kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
316 kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
317 kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
318 kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
319 kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */
320 kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */
321 kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */
322 kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */
323 kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */
324 kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */
325 kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */
326 kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */
327 kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */
328 kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */
329 kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */
330 kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */
331 kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V. */
332 kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V. */
333 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
334 kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */
335 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
336 kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
337 kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */
338 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
339 kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */
340 kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */
341 kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
342 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
343 kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
344 kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
345 kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
346 kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
347 kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */
348 kDmaRequestMux0Reserved55 = 55|0x100U, /**< Reserved55 */
349 kDmaRequestMux0Reserved56 = 56|0x100U, /**< Reserved56 */
350 kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */
351 kDmaRequestMux0SPI2Rx = 58|0x100U, /**< SPI2 Receive. */
352 kDmaRequestMux0SPI2Tx = 59|0x100U, /**< SPI2 Transmit. */
353 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
354 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
355 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
356 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
357 kDmaRequestMux0Group1Disable = 0|0x200U, /**< DMAMUX TriggerDisabled. */
358 kDmaRequestMux0Group1FlexIO0Channel0 = 1|0x200U, /**< FLEXIO0. */
359 kDmaRequestMux0Group1FlexIO0Channel1 = 2|0x200U, /**< FLEXIO0. */
360 kDmaRequestMux0Group1FlexIO0Channel2 = 3|0x200U, /**< FLEXIO0. */
361 kDmaRequestMux0Group1FlexIO0Channel3 = 4|0x200U, /**< FLEXIO0. */
362 kDmaRequestMux0Group1FlexIO0Channel4 = 5|0x200U, /**< FLEXIO0. */
363 kDmaRequestMux0Group1FlexIO0Channel5 = 6|0x200U, /**< FLEXIO0. */
364 kDmaRequestMux0Group1FlexIO0Channel6 = 7|0x200U, /**< FLEXIO0. */
365 kDmaRequestMux0Group1FlexIO0Channel7 = 8|0x200U, /**< FLEXIO0. */
366 kDmaRequestMux0Group1Reserved9 = 9|0x200U, /**< Reserved9 */
367 kDmaRequestMux0Group1Reserved10 = 10|0x200U, /**< Reserved10 */
368 kDmaRequestMux0Group1Reserved11 = 11|0x200U, /**< Reserved11 */
369 kDmaRequestMux0Group1I2S1Tx = 12|0x200U, /**< I2S1 Transmit. */
370 kDmaRequestMux0Group1I2S1Rx = 13|0x200U, /**< I2S1 Receive. */
371 kDmaRequestMux0Group1Reserved14 = 14|0x200U, /**< Reserved14 */
372 kDmaRequestMux0Group1Reserved15 = 15|0x200U, /**< Reserved15 */
373 kDmaRequestMux0Group1Reserved16 = 16|0x200U, /**< Reserved16 */
374 kDmaRequestMux0Group1Reserved17 = 17|0x200U, /**< Reserved17 */
375 kDmaRequestMux0Group1Reserved18 = 18|0x200U, /**< Reserved18 */
376 kDmaRequestMux0Group1Reserved19 = 19|0x200U, /**< Reserved19 */
377 kDmaRequestMux0Group1Reserved20 = 20|0x200U, /**< Reserved20 */
378 kDmaRequestMux0Group1Reserved21 = 21|0x200U, /**< Reserved21 */
379 kDmaRequestMux0Group1Reserved22 = 22|0x200U, /**< Reserved22 */
380 kDmaRequestMux0Group1Reserved23 = 23|0x200U, /**< Reserved23 */
381 kDmaRequestMux0Group1QSPI0Rx = 24|0x200U, /**< QuadSPI0 Receive. */
382 kDmaRequestMux0Group1QSPI0Tx = 25|0x200U, /**< QuadSPI0 Transmit. */
383 kDmaRequestMux0Group1Reserved26 = 26|0x200U, /**< Reserved26 */
384 kDmaRequestMux0Group1Reserved27 = 27|0x200U, /**< Reserved27 */
385 kDmaRequestMux0Group1SPI0Rx = 28|0x200U, /**< SPI0 Receive. */
386 kDmaRequestMux0Group1SPI0Tx = 29|0x200U, /**< SPI0 Transmit. */
387 kDmaRequestMux0Group1SPI1Rx = 30|0x200U, /**< SPI1 Receive. */
388 kDmaRequestMux0Group1SPI1Tx = 31|0x200U, /**< SPI1 Transmit. */
389 kDmaRequestMux0Group1Reserved32 = 32|0x200U, /**< Reserved32 */
390 kDmaRequestMux0Group1Reserved33 = 33|0x200U, /**< Reserved33 */
391 kDmaRequestMux0Group1Reserved34 = 34|0x200U, /**< Reserved34 */
392 kDmaRequestMux0Group1Reserved35 = 35|0x200U, /**< Reserved35 */
393 kDmaRequestMux0Group1Reserved36 = 36|0x200U, /**< Reserved36 */
394 kDmaRequestMux0Group1Reserved37 = 37|0x200U, /**< Reserved37 */
395 kDmaRequestMux0Group1Reserved38 = 38|0x200U, /**< Reserved38 */
396 kDmaRequestMux0Group1Reserved39 = 39|0x200U, /**< Reserved39 */
397 kDmaRequestMux0Group1Reserved40 = 40|0x200U, /**< Reserved40 */
398 kDmaRequestMux0Group1Reserved41 = 41|0x200U, /**< Reserved41 */
399 kDmaRequestMux0Group1TPM1Channel0 = 42|0x200U, /**< TPM1 C0V. */
400 kDmaRequestMux0Group1TPM1Channel1 = 43|0x200U, /**< TPM1 C1V. */
401 kDmaRequestMux0Group1TPM2Channel0 = 44|0x200U, /**< TPM2 C0V. */
402 kDmaRequestMux0Group1TPM2Channel1 = 45|0x200U, /**< TPM2 C1V. */
403 kDmaRequestMux0Group1Reserved46 = 46|0x200U, /**< Reserved46 */
404 kDmaRequestMux0Group1Reserved47 = 47|0x200U, /**< Reserved47 */
405 kDmaRequestMux0Group1Reserved48 = 48|0x200U, /**< Reserved48 */
406 kDmaRequestMux0Group1Reserved49 = 49|0x200U, /**< Reserved49 */
407 kDmaRequestMux0Group1Reserved50 = 50|0x200U, /**< Reserved50 */
408 kDmaRequestMux0Group1Reserved51 = 51|0x200U, /**< Reserved51 */
409 kDmaRequestMux0Group1Reserved52 = 52|0x200U, /**< Reserved52 */
410 kDmaRequestMux0Group1Reserved53 = 53|0x200U, /**< Reserved53 */
411 kDmaRequestMux0Group1Reserved54 = 54|0x200U, /**< Reserved54 */
412 kDmaRequestMux0Group1TPM1Overflow = 55|0x200U, /**< TPM1. */
413 kDmaRequestMux0Group1TPM2Overflow = 56|0x200U, /**< TPM2. */
414 kDmaRequestMux0Group1Reserved57 = 57|0x200U, /**< Reserved57 */
415 kDmaRequestMux0Group1SPI3Rx = 58|0x200U, /**< SPI3 Receive. */
416 kDmaRequestMux0Group1SPI3Tx = 59|0x200U, /**< SPI3 Transmit. */
417 kDmaRequestMux0Group1AlwaysOn60 = 60|0x200U, /**< DMAMUX Always Enabled slot. */
418 kDmaRequestMux0Group1AlwaysOn61 = 61|0x200U, /**< DMAMUX Always Enabled slot. */
419 kDmaRequestMux0Group1AlwaysOn62 = 62|0x200U, /**< DMAMUX Always Enabled slot. */
420 kDmaRequestMux0Group1AlwaysOn63 = 63|0x200U, /**< DMAMUX Always Enabled slot. */
421} dma_request_source_t;
422
423/* @} */
424
425
426/*!
427 * @}
428 */ /* end of group Mapping_Information */
429
430
431/* ----------------------------------------------------------------------------
432 -- Device Peripheral Access Layer
433 ---------------------------------------------------------------------------- */
434
435/*!
436 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
437 * @{
438 */
439
440
441/*
442** Start of section using anonymous unions
443*/
444
445#if defined(__ARMCC_VERSION)
446 #if (__ARMCC_VERSION >= 6010050)
447 #pragma clang diagnostic push
448 #else
449 #pragma push
450 #pragma anon_unions
451 #endif
452#elif defined(__CWCC__)
453 #pragma push
454 #pragma cpp_extensions on
455#elif defined(__GNUC__)
456 /* anonymous unions are enabled by default */
457#elif defined(__IAR_SYSTEMS_ICC__)
458 #pragma language=extended
459#else
460 #error Not supported compiler type
461#endif
462
463/* ----------------------------------------------------------------------------
464 -- ADC Peripheral Access Layer
465 ---------------------------------------------------------------------------- */
466
467/*!
468 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
469 * @{
470 */
471
472/** ADC - Register Layout Typedef */
473typedef struct {
474 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
475 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
476 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
477 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
478 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
479 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
480 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
481 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
482 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
483 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
484 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
485 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
486 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
487 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
488 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
489 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
490 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
491 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
492 uint8_t RESERVED_0[4];
493 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
494 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
495 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
496 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
497 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
498 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
499 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
500} ADC_Type;
501
502/* ----------------------------------------------------------------------------
503 -- ADC Register Masks
504 ---------------------------------------------------------------------------- */
505
506/*!
507 * @addtogroup ADC_Register_Masks ADC Register Masks
508 * @{
509 */
510
511/*! @name SC1 - ADC Status and Control Registers 1 */
512/*! @{ */
513#define ADC_SC1_ADCH_MASK (0x1FU)
514#define ADC_SC1_ADCH_SHIFT (0U)
515/*! ADCH - Input channel select
516 * 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
517 * 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
518 * 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
519 * 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
520 * 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
521 * 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
522 * 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
523 * 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
524 * 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
525 * 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
526 * 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
527 * 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
528 * 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
529 * 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
530 * 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
531 * 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
532 * 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
533 * 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
534 * 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
535 * 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
536 * 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
537 * 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
538 * 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
539 * 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
540 * 0b11000..Reserved.
541 * 0b11001..Reserved.
542 * 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
543 * 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
544 * 0b11100..Reserved.
545 * 0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
546 * 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
547 * 0b11111..Module is disabled.
548 */
549#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
550#define ADC_SC1_DIFF_MASK (0x20U)
551#define ADC_SC1_DIFF_SHIFT (5U)
552/*! DIFF - Differential Mode Enable
553 * 0b0..Single-ended conversions and input channels are selected.
554 * 0b1..Differential conversions and input channels are selected.
555 */
556#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
557#define ADC_SC1_AIEN_MASK (0x40U)
558#define ADC_SC1_AIEN_SHIFT (6U)
559/*! AIEN - Interrupt Enable
560 * 0b0..Conversion complete interrupt is disabled.
561 * 0b1..Conversion complete interrupt is enabled.
562 */
563#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
564#define ADC_SC1_COCO_MASK (0x80U)
565#define ADC_SC1_COCO_SHIFT (7U)
566/*! COCO - Conversion Complete Flag
567 * 0b0..Conversion is not completed.
568 * 0b1..Conversion is completed.
569 */
570#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
571/*! @} */
572
573/* The count of ADC_SC1 */
574#define ADC_SC1_COUNT (2U)
575
576/*! @name CFG1 - ADC Configuration Register 1 */
577/*! @{ */
578#define ADC_CFG1_ADICLK_MASK (0x3U)
579#define ADC_CFG1_ADICLK_SHIFT (0U)
580/*! ADICLK - Input Clock Select
581 * 0b00..Bus clock
582 * 0b01..Alternate clock 2 (ALTCLK2)
583 * 0b10..Alternate clock (ALTCLK)
584 * 0b11..Asynchronous clock (ADACK)
585 */
586#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
587#define ADC_CFG1_MODE_MASK (0xCU)
588#define ADC_CFG1_MODE_SHIFT (2U)
589/*! MODE - Conversion mode selection
590 * 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.
591 * 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output.
592 * 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output
593 * 0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output
594 */
595#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
596#define ADC_CFG1_ADLSMP_MASK (0x10U)
597#define ADC_CFG1_ADLSMP_SHIFT (4U)
598/*! ADLSMP - Sample Time Configuration
599 * 0b0..Short sample time.
600 * 0b1..Long sample time.
601 */
602#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
603#define ADC_CFG1_ADIV_MASK (0x60U)
604#define ADC_CFG1_ADIV_SHIFT (5U)
605/*! ADIV - Clock Divide Select
606 * 0b00..The divide ratio is 1 and the clock rate is input clock.
607 * 0b01..The divide ratio is 2 and the clock rate is (input clock)/2.
608 * 0b10..The divide ratio is 4 and the clock rate is (input clock)/4.
609 * 0b11..The divide ratio is 8 and the clock rate is (input clock)/8.
610 */
611#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
612#define ADC_CFG1_ADLPC_MASK (0x80U)
613#define ADC_CFG1_ADLPC_SHIFT (7U)
614/*! ADLPC - Low-Power Configuration
615 * 0b0..Normal power configuration.
616 * 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed.
617 */
618#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
619/*! @} */
620
621/*! @name CFG2 - ADC Configuration Register 2 */
622/*! @{ */
623#define ADC_CFG2_ADLSTS_MASK (0x3U)
624#define ADC_CFG2_ADLSTS_SHIFT (0U)
625/*! ADLSTS - Long Sample Time Select
626 * 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
627 * 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time.
628 * 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time.
629 * 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.
630 */
631#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
632#define ADC_CFG2_ADHSC_MASK (0x4U)
633#define ADC_CFG2_ADHSC_SHIFT (2U)
634/*! ADHSC - High-Speed Configuration
635 * 0b0..Normal conversion sequence selected.
636 * 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
637 */
638#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
639#define ADC_CFG2_ADACKEN_MASK (0x8U)
640#define ADC_CFG2_ADACKEN_SHIFT (3U)
641/*! ADACKEN - Asynchronous Clock Output Enable
642 * 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
643 * 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC.
644 */
645#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
646#define ADC_CFG2_MUXSEL_MASK (0x10U)
647#define ADC_CFG2_MUXSEL_SHIFT (4U)
648/*! MUXSEL - ADC Mux Select
649 * 0b0..ADxxa channels are selected.
650 * 0b1..ADxxb channels are selected.
651 */
652#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
653/*! @} */
654
655/*! @name R - ADC Data Result Register */
656/*! @{ */
657#define ADC_R_D_MASK (0xFFFFU)
658#define ADC_R_D_SHIFT (0U)
659#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
660/*! @} */
661
662/* The count of ADC_R */
663#define ADC_R_COUNT (2U)
664
665/*! @name CV1 - Compare Value Registers */
666/*! @{ */
667#define ADC_CV1_CV_MASK (0xFFFFU)
668#define ADC_CV1_CV_SHIFT (0U)
669#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
670/*! @} */
671
672/*! @name CV2 - Compare Value Registers */
673/*! @{ */
674#define ADC_CV2_CV_MASK (0xFFFFU)
675#define ADC_CV2_CV_SHIFT (0U)
676#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
677/*! @} */
678
679/*! @name SC2 - Status and Control Register 2 */
680/*! @{ */
681#define ADC_SC2_REFSEL_MASK (0x3U)
682#define ADC_SC2_REFSEL_SHIFT (0U)
683/*! REFSEL - Voltage Reference Selection
684 * 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL
685 * 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
686 * 0b10..Reserved
687 * 0b11..Reserved
688 */
689#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
690#define ADC_SC2_DMAEN_MASK (0x4U)
691#define ADC_SC2_DMAEN_SHIFT (2U)
692/*! DMAEN - DMA Enable
693 * 0b0..DMA is disabled.
694 * 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
695 */
696#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
697#define ADC_SC2_ACREN_MASK (0x8U)
698#define ADC_SC2_ACREN_SHIFT (3U)
699/*! ACREN - Compare Function Range Enable
700 * 0b0..Range function disabled. Only CV1 is compared.
701 * 0b1..Range function enabled. Both CV1 and CV2 are compared.
702 */
703#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
704#define ADC_SC2_ACFGT_MASK (0x10U)
705#define ADC_SC2_ACFGT_SHIFT (4U)
706/*! ACFGT - Compare Function Greater Than Enable
707 * 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
708 * 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
709 */
710#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
711#define ADC_SC2_ACFE_MASK (0x20U)
712#define ADC_SC2_ACFE_SHIFT (5U)
713/*! ACFE - Compare Function Enable
714 * 0b0..Compare function disabled.
715 * 0b1..Compare function enabled.
716 */
717#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
718#define ADC_SC2_ADTRG_MASK (0x40U)
719#define ADC_SC2_ADTRG_SHIFT (6U)
720/*! ADTRG - Conversion Trigger Select
721 * 0b0..Software trigger selected.
722 * 0b1..Hardware trigger selected.
723 */
724#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
725#define ADC_SC2_ADACT_MASK (0x80U)
726#define ADC_SC2_ADACT_SHIFT (7U)
727/*! ADACT - Conversion Active
728 * 0b0..Conversion not in progress.
729 * 0b1..Conversion in progress.
730 */
731#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
732/*! @} */
733
734/*! @name SC3 - Status and Control Register 3 */
735/*! @{ */
736#define ADC_SC3_AVGS_MASK (0x3U)
737#define ADC_SC3_AVGS_SHIFT (0U)
738/*! AVGS - Hardware Average Select
739 * 0b00..4 samples averaged.
740 * 0b01..8 samples averaged.
741 * 0b10..16 samples averaged.
742 * 0b11..32 samples averaged.
743 */
744#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
745#define ADC_SC3_AVGE_MASK (0x4U)
746#define ADC_SC3_AVGE_SHIFT (2U)
747/*! AVGE - Hardware Average Enable
748 * 0b0..Hardware average function disabled.
749 * 0b1..Hardware average function enabled.
750 */
751#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
752#define ADC_SC3_ADCO_MASK (0x8U)
753#define ADC_SC3_ADCO_SHIFT (3U)
754/*! ADCO - Continuous Conversion Enable
755 * 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
756 * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
757 */
758#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
759#define ADC_SC3_CALF_MASK (0x40U)
760#define ADC_SC3_CALF_SHIFT (6U)
761/*! CALF - Calibration Failed Flag
762 * 0b0..Calibration completed normally.
763 * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
764 */
765#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
766#define ADC_SC3_CAL_MASK (0x80U)
767#define ADC_SC3_CAL_SHIFT (7U)
768#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
769/*! @} */
770
771/*! @name OFS - ADC Offset Correction Register */
772/*! @{ */
773#define ADC_OFS_OFS_MASK (0xFFFFU)
774#define ADC_OFS_OFS_SHIFT (0U)
775#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
776/*! @} */
777
778/*! @name PG - ADC Plus-Side Gain Register */
779/*! @{ */
780#define ADC_PG_PG_MASK (0xFFFFU)
781#define ADC_PG_PG_SHIFT (0U)
782#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
783/*! @} */
784
785/*! @name MG - ADC Minus-Side Gain Register */
786/*! @{ */
787#define ADC_MG_MG_MASK (0xFFFFU)
788#define ADC_MG_MG_SHIFT (0U)
789#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
790/*! @} */
791
792/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
793/*! @{ */
794#define ADC_CLPD_CLPD_MASK (0x3FU)
795#define ADC_CLPD_CLPD_SHIFT (0U)
796#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
797/*! @} */
798
799/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
800/*! @{ */
801#define ADC_CLPS_CLPS_MASK (0x3FU)
802#define ADC_CLPS_CLPS_SHIFT (0U)
803#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
804/*! @} */
805
806/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
807/*! @{ */
808#define ADC_CLP4_CLP4_MASK (0x3FFU)
809#define ADC_CLP4_CLP4_SHIFT (0U)
810#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
811/*! @} */
812
813/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
814/*! @{ */
815#define ADC_CLP3_CLP3_MASK (0x1FFU)
816#define ADC_CLP3_CLP3_SHIFT (0U)
817#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
818/*! @} */
819
820/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
821/*! @{ */
822#define ADC_CLP2_CLP2_MASK (0xFFU)
823#define ADC_CLP2_CLP2_SHIFT (0U)
824#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
825/*! @} */
826
827/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
828/*! @{ */
829#define ADC_CLP1_CLP1_MASK (0x7FU)
830#define ADC_CLP1_CLP1_SHIFT (0U)
831#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
832/*! @} */
833
834/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
835/*! @{ */
836#define ADC_CLP0_CLP0_MASK (0x3FU)
837#define ADC_CLP0_CLP0_SHIFT (0U)
838#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
839/*! @} */
840
841/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
842/*! @{ */
843#define ADC_CLMD_CLMD_MASK (0x3FU)
844#define ADC_CLMD_CLMD_SHIFT (0U)
845#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
846/*! @} */
847
848/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
849/*! @{ */
850#define ADC_CLMS_CLMS_MASK (0x3FU)
851#define ADC_CLMS_CLMS_SHIFT (0U)
852#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
853/*! @} */
854
855/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
856/*! @{ */
857#define ADC_CLM4_CLM4_MASK (0x3FFU)
858#define ADC_CLM4_CLM4_SHIFT (0U)
859#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
860/*! @} */
861
862/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
863/*! @{ */
864#define ADC_CLM3_CLM3_MASK (0x1FFU)
865#define ADC_CLM3_CLM3_SHIFT (0U)
866#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
867/*! @} */
868
869/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
870/*! @{ */
871#define ADC_CLM2_CLM2_MASK (0xFFU)
872#define ADC_CLM2_CLM2_SHIFT (0U)
873#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
874/*! @} */
875
876/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
877/*! @{ */
878#define ADC_CLM1_CLM1_MASK (0x7FU)
879#define ADC_CLM1_CLM1_SHIFT (0U)
880#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
881/*! @} */
882
883/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
884/*! @{ */
885#define ADC_CLM0_CLM0_MASK (0x3FU)
886#define ADC_CLM0_CLM0_SHIFT (0U)
887#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
888/*! @} */
889
890
891/*!
892 * @}
893 */ /* end of group ADC_Register_Masks */
894
895
896/* ADC - Peripheral instance base addresses */
897/** Peripheral ADC0 base address */
898#define ADC0_BASE (0x4003B000u)
899/** Peripheral ADC0 base pointer */
900#define ADC0 ((ADC_Type *)ADC0_BASE)
901/** Array initializer of ADC peripheral base addresses */
902#define ADC_BASE_ADDRS { ADC0_BASE }
903/** Array initializer of ADC peripheral base pointers */
904#define ADC_BASE_PTRS { ADC0 }
905/** Interrupt vectors for the ADC peripheral type */
906#define ADC_IRQS { ADC0_IRQn }
907
908/*!
909 * @}
910 */ /* end of group ADC_Peripheral_Access_Layer */
911
912
913/* ----------------------------------------------------------------------------
914 -- AIPS Peripheral Access Layer
915 ---------------------------------------------------------------------------- */
916
917/*!
918 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
919 * @{
920 */
921
922/** AIPS - Register Layout Typedef */
923typedef struct {
924 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
925 uint8_t RESERVED_0[28];
926 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
927 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
928 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
929 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
930 uint8_t RESERVED_1[16];
931 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
932 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
933 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
934 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
935 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
936 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
937 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
938 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
939 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
940 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
941 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
942 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
943} AIPS_Type;
944
945/* ----------------------------------------------------------------------------
946 -- AIPS Register Masks
947 ---------------------------------------------------------------------------- */
948
949/*!
950 * @addtogroup AIPS_Register_Masks AIPS Register Masks
951 * @{
952 */
953
954/*! @name MPRA - Master Privilege Register A */
955/*! @{ */
956#define AIPS_MPRA_MPL4_MASK (0x1000U)
957#define AIPS_MPRA_MPL4_SHIFT (12U)
958/*! MPL4 - Master 4 Privilege Level
959 * 0b0..Accesses from this master are forced to user-mode.
960 * 0b1..Accesses from this master are not forced to user-mode.
961 */
962#define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
963#define AIPS_MPRA_MTW4_MASK (0x2000U)
964#define AIPS_MPRA_MTW4_SHIFT (13U)
965/*! MTW4 - Master 4 Trusted For Writes
966 * 0b0..This master is not trusted for write accesses.
967 * 0b1..This master is trusted for write accesses.
968 */
969#define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
970#define AIPS_MPRA_MTR4_MASK (0x4000U)
971#define AIPS_MPRA_MTR4_SHIFT (14U)
972/*! MTR4 - Master 4 Trusted For Read
973 * 0b0..This master is not trusted for read accesses.
974 * 0b1..This master is trusted for read accesses.
975 */
976#define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
977#define AIPS_MPRA_MPL3_MASK (0x10000U)
978#define AIPS_MPRA_MPL3_SHIFT (16U)
979/*! MPL3 - Master 3 Privilege Level
980 * 0b0..Accesses from this master are forced to user-mode.
981 * 0b1..Accesses from this master are not forced to user-mode.
982 */
983#define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
984#define AIPS_MPRA_MTW3_MASK (0x20000U)
985#define AIPS_MPRA_MTW3_SHIFT (17U)
986/*! MTW3 - Master 3 Trusted For Writes
987 * 0b0..This master is not trusted for write accesses.
988 * 0b1..This master is trusted for write accesses.
989 */
990#define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
991#define AIPS_MPRA_MTR3_MASK (0x40000U)
992#define AIPS_MPRA_MTR3_SHIFT (18U)
993/*! MTR3 - Master 3 Trusted For Read
994 * 0b0..This master is not trusted for read accesses.
995 * 0b1..This master is trusted for read accesses.
996 */
997#define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
998#define AIPS_MPRA_MPL2_MASK (0x100000U)
999#define AIPS_MPRA_MPL2_SHIFT (20U)
1000/*! MPL2 - Master 2 Privilege Level
1001 * 0b0..Accesses from this master are forced to user-mode.
1002 * 0b1..Accesses from this master are not forced to user-mode.
1003 */
1004#define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
1005#define AIPS_MPRA_MTW2_MASK (0x200000U)
1006#define AIPS_MPRA_MTW2_SHIFT (21U)
1007/*! MTW2 - Master 2 Trusted For Writes
1008 * 0b0..This master is not trusted for write accesses.
1009 * 0b1..This master is trusted for write accesses.
1010 */
1011#define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
1012#define AIPS_MPRA_MTR2_MASK (0x400000U)
1013#define AIPS_MPRA_MTR2_SHIFT (22U)
1014/*! MTR2 - Master 2 Trusted For Read
1015 * 0b0..This master is not trusted for read accesses.
1016 * 0b1..This master is trusted for read accesses.
1017 */
1018#define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
1019#define AIPS_MPRA_MPL1_MASK (0x1000000U)
1020#define AIPS_MPRA_MPL1_SHIFT (24U)
1021/*! MPL1 - Master 1 Privilege Level
1022 * 0b0..Accesses from this master are forced to user-mode.
1023 * 0b1..Accesses from this master are not forced to user-mode.
1024 */
1025#define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
1026#define AIPS_MPRA_MTW1_MASK (0x2000000U)
1027#define AIPS_MPRA_MTW1_SHIFT (25U)
1028/*! MTW1 - Master 1 Trusted for Writes
1029 * 0b0..This master is not trusted for write accesses.
1030 * 0b1..This master is trusted for write accesses.
1031 */
1032#define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
1033#define AIPS_MPRA_MTR1_MASK (0x4000000U)
1034#define AIPS_MPRA_MTR1_SHIFT (26U)
1035/*! MTR1 - Master 1 Trusted for Read
1036 * 0b0..This master is not trusted for read accesses.
1037 * 0b1..This master is trusted for read accesses.
1038 */
1039#define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
1040#define AIPS_MPRA_MPL0_MASK (0x10000000U)
1041#define AIPS_MPRA_MPL0_SHIFT (28U)
1042/*! MPL0 - Master 0 Privilege Level
1043 * 0b0..Accesses from this master are forced to user-mode.
1044 * 0b1..Accesses from this master are not forced to user-mode.
1045 */
1046#define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
1047#define AIPS_MPRA_MTW0_MASK (0x20000000U)
1048#define AIPS_MPRA_MTW0_SHIFT (29U)
1049/*! MTW0 - Master 0 Trusted For Writes
1050 * 0b0..This master is not trusted for write accesses.
1051 * 0b1..This master is trusted for write accesses.
1052 */
1053#define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
1054#define AIPS_MPRA_MTR0_MASK (0x40000000U)
1055#define AIPS_MPRA_MTR0_SHIFT (30U)
1056/*! MTR0 - Master 0 Trusted For Read
1057 * 0b0..This master is not trusted for read accesses.
1058 * 0b1..This master is trusted for read accesses.
1059 */
1060#define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
1061/*! @} */
1062
1063/*! @name PACRA - Peripheral Access Control Register */
1064/*! @{ */
1065#define AIPS_PACRA_TP7_MASK (0x1U)
1066#define AIPS_PACRA_TP7_SHIFT (0U)
1067/*! TP7 - Trusted Protect
1068 * 0b0..Accesses from an untrusted master are allowed.
1069 * 0b1..Accesses from an untrusted master are not allowed.
1070 */
1071#define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
1072#define AIPS_PACRA_WP7_MASK (0x2U)
1073#define AIPS_PACRA_WP7_SHIFT (1U)
1074/*! WP7 - Write Protect
1075 * 0b0..This peripheral allows write accesses.
1076 * 0b1..This peripheral is write protected.
1077 */
1078#define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
1079#define AIPS_PACRA_SP7_MASK (0x4U)
1080#define AIPS_PACRA_SP7_SHIFT (2U)
1081/*! SP7 - Supervisor Protect
1082 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1083 * 0b1..This peripheral requires supervisor privilege level for accesses.
1084 */
1085#define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
1086#define AIPS_PACRA_TP6_MASK (0x10U)
1087#define AIPS_PACRA_TP6_SHIFT (4U)
1088/*! TP6 - Trusted Protect
1089 * 0b0..Accesses from an untrusted master are allowed.
1090 * 0b1..Accesses from an untrusted master are not allowed.
1091 */
1092#define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
1093#define AIPS_PACRA_WP6_MASK (0x20U)
1094#define AIPS_PACRA_WP6_SHIFT (5U)
1095/*! WP6 - Write Protect
1096 * 0b0..This peripheral allows write accesses.
1097 * 0b1..This peripheral is write protected.
1098 */
1099#define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
1100#define AIPS_PACRA_SP6_MASK (0x40U)
1101#define AIPS_PACRA_SP6_SHIFT (6U)
1102/*! SP6 - Supervisor Protect
1103 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1104 * 0b1..This peripheral requires supervisor privilege level for accesses.
1105 */
1106#define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
1107#define AIPS_PACRA_TP5_MASK (0x100U)
1108#define AIPS_PACRA_TP5_SHIFT (8U)
1109/*! TP5 - Trusted Protect
1110 * 0b0..Accesses from an untrusted master are allowed.
1111 * 0b1..Accesses from an untrusted master are not allowed.
1112 */
1113#define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
1114#define AIPS_PACRA_WP5_MASK (0x200U)
1115#define AIPS_PACRA_WP5_SHIFT (9U)
1116/*! WP5 - Write Protect
1117 * 0b0..This peripheral allows write accesses.
1118 * 0b1..This peripheral is write protected.
1119 */
1120#define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
1121#define AIPS_PACRA_SP5_MASK (0x400U)
1122#define AIPS_PACRA_SP5_SHIFT (10U)
1123/*! SP5 - Supervisor Protect
1124 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1125 * 0b1..This peripheral requires supervisor privilege level for accesses.
1126 */
1127#define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
1128#define AIPS_PACRA_TP4_MASK (0x1000U)
1129#define AIPS_PACRA_TP4_SHIFT (12U)
1130/*! TP4 - Trusted Protect
1131 * 0b0..Accesses from an untrusted master are allowed.
1132 * 0b1..Accesses from an untrusted master are not allowed.
1133 */
1134#define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
1135#define AIPS_PACRA_WP4_MASK (0x2000U)
1136#define AIPS_PACRA_WP4_SHIFT (13U)
1137/*! WP4 - Write Protect
1138 * 0b0..This peripheral allows write accesses.
1139 * 0b1..This peripheral is write protected.
1140 */
1141#define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
1142#define AIPS_PACRA_SP4_MASK (0x4000U)
1143#define AIPS_PACRA_SP4_SHIFT (14U)
1144/*! SP4 - Supervisor Protect
1145 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1146 * 0b1..This peripheral requires supervisor privilege level for accesses.
1147 */
1148#define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
1149#define AIPS_PACRA_TP3_MASK (0x10000U)
1150#define AIPS_PACRA_TP3_SHIFT (16U)
1151/*! TP3 - Trusted Protect
1152 * 0b0..Accesses from an untrusted master are allowed.
1153 * 0b1..Accesses from an untrusted master are not allowed.
1154 */
1155#define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
1156#define AIPS_PACRA_WP3_MASK (0x20000U)
1157#define AIPS_PACRA_WP3_SHIFT (17U)
1158/*! WP3 - Write Protect
1159 * 0b0..This peripheral allows write accesses.
1160 * 0b1..This peripheral is write protected.
1161 */
1162#define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
1163#define AIPS_PACRA_SP3_MASK (0x40000U)
1164#define AIPS_PACRA_SP3_SHIFT (18U)
1165/*! SP3 - Supervisor Protect
1166 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1167 * 0b1..This peripheral requires supervisor privilege level for accesses.
1168 */
1169#define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
1170#define AIPS_PACRA_TP2_MASK (0x100000U)
1171#define AIPS_PACRA_TP2_SHIFT (20U)
1172/*! TP2 - Trusted Protect
1173 * 0b0..Accesses from an untrusted master are allowed.
1174 * 0b1..Accesses from an untrusted master are not allowed.
1175 */
1176#define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
1177#define AIPS_PACRA_WP2_MASK (0x200000U)
1178#define AIPS_PACRA_WP2_SHIFT (21U)
1179/*! WP2 - Write Protect
1180 * 0b0..This peripheral allows write accesses.
1181 * 0b1..This peripheral is write protected.
1182 */
1183#define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
1184#define AIPS_PACRA_SP2_MASK (0x400000U)
1185#define AIPS_PACRA_SP2_SHIFT (22U)
1186/*! SP2 - Supervisor Protect
1187 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1188 * 0b1..This peripheral requires supervisor privilege level for accesses.
1189 */
1190#define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
1191#define AIPS_PACRA_TP1_MASK (0x1000000U)
1192#define AIPS_PACRA_TP1_SHIFT (24U)
1193/*! TP1 - Trusted Protect
1194 * 0b0..Accesses from an untrusted master are allowed.
1195 * 0b1..Accesses from an untrusted master are not allowed.
1196 */
1197#define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
1198#define AIPS_PACRA_WP1_MASK (0x2000000U)
1199#define AIPS_PACRA_WP1_SHIFT (25U)
1200/*! WP1 - Write Protect
1201 * 0b0..This peripheral allows write accesses.
1202 * 0b1..This peripheral is write protected.
1203 */
1204#define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
1205#define AIPS_PACRA_SP1_MASK (0x4000000U)
1206#define AIPS_PACRA_SP1_SHIFT (26U)
1207/*! SP1 - Supervisor Protect
1208 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1209 * 0b1..This peripheral requires supervisor privilege level for accesses.
1210 */
1211#define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
1212#define AIPS_PACRA_TP0_MASK (0x10000000U)
1213#define AIPS_PACRA_TP0_SHIFT (28U)
1214/*! TP0 - Trusted Protect
1215 * 0b0..Accesses from an untrusted master are allowed.
1216 * 0b1..Accesses from an untrusted master are not allowed.
1217 */
1218#define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
1219#define AIPS_PACRA_WP0_MASK (0x20000000U)
1220#define AIPS_PACRA_WP0_SHIFT (29U)
1221/*! WP0 - Write Protect
1222 * 0b0..This peripheral allows write accesses.
1223 * 0b1..This peripheral is write protected.
1224 */
1225#define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
1226#define AIPS_PACRA_SP0_MASK (0x40000000U)
1227#define AIPS_PACRA_SP0_SHIFT (30U)
1228/*! SP0 - Supervisor Protect
1229 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1230 * 0b1..This peripheral requires supervisor privilege level for accesses.
1231 */
1232#define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
1233/*! @} */
1234
1235/*! @name PACRB - Peripheral Access Control Register */
1236/*! @{ */
1237#define AIPS_PACRB_TP7_MASK (0x1U)
1238#define AIPS_PACRB_TP7_SHIFT (0U)
1239/*! TP7 - Trusted Protect
1240 * 0b0..Accesses from an untrusted master are allowed.
1241 * 0b1..Accesses from an untrusted master are not allowed.
1242 */
1243#define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
1244#define AIPS_PACRB_WP7_MASK (0x2U)
1245#define AIPS_PACRB_WP7_SHIFT (1U)
1246/*! WP7 - Write Protect
1247 * 0b0..This peripheral allows write accesses.
1248 * 0b1..This peripheral is write protected.
1249 */
1250#define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
1251#define AIPS_PACRB_SP7_MASK (0x4U)
1252#define AIPS_PACRB_SP7_SHIFT (2U)
1253/*! SP7 - Supervisor Protect
1254 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1255 * 0b1..This peripheral requires supervisor privilege level for accesses.
1256 */
1257#define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
1258#define AIPS_PACRB_TP6_MASK (0x10U)
1259#define AIPS_PACRB_TP6_SHIFT (4U)
1260/*! TP6 - Trusted Protect
1261 * 0b0..Accesses from an untrusted master are allowed.
1262 * 0b1..Accesses from an untrusted master are not allowed.
1263 */
1264#define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
1265#define AIPS_PACRB_WP6_MASK (0x20U)
1266#define AIPS_PACRB_WP6_SHIFT (5U)
1267/*! WP6 - Write Protect
1268 * 0b0..This peripheral allows write accesses.
1269 * 0b1..This peripheral is write protected.
1270 */
1271#define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
1272#define AIPS_PACRB_SP6_MASK (0x40U)
1273#define AIPS_PACRB_SP6_SHIFT (6U)
1274/*! SP6 - Supervisor Protect
1275 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1276 * 0b1..This peripheral requires supervisor privilege level for accesses.
1277 */
1278#define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
1279#define AIPS_PACRB_TP5_MASK (0x100U)
1280#define AIPS_PACRB_TP5_SHIFT (8U)
1281/*! TP5 - Trusted Protect
1282 * 0b0..Accesses from an untrusted master are allowed.
1283 * 0b1..Accesses from an untrusted master are not allowed.
1284 */
1285#define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
1286#define AIPS_PACRB_WP5_MASK (0x200U)
1287#define AIPS_PACRB_WP5_SHIFT (9U)
1288/*! WP5 - Write Protect
1289 * 0b0..This peripheral allows write accesses.
1290 * 0b1..This peripheral is write protected.
1291 */
1292#define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
1293#define AIPS_PACRB_SP5_MASK (0x400U)
1294#define AIPS_PACRB_SP5_SHIFT (10U)
1295/*! SP5 - Supervisor Protect
1296 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1297 * 0b1..This peripheral requires supervisor privilege level for accesses.
1298 */
1299#define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
1300#define AIPS_PACRB_TP4_MASK (0x1000U)
1301#define AIPS_PACRB_TP4_SHIFT (12U)
1302/*! TP4 - Trusted Protect
1303 * 0b0..Accesses from an untrusted master are allowed.
1304 * 0b1..Accesses from an untrusted master are not allowed.
1305 */
1306#define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
1307#define AIPS_PACRB_WP4_MASK (0x2000U)
1308#define AIPS_PACRB_WP4_SHIFT (13U)
1309/*! WP4 - Write Protect
1310 * 0b0..This peripheral allows write accesses.
1311 * 0b1..This peripheral is write protected.
1312 */
1313#define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
1314#define AIPS_PACRB_SP4_MASK (0x4000U)
1315#define AIPS_PACRB_SP4_SHIFT (14U)
1316/*! SP4 - Supervisor Protect
1317 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1318 * 0b1..This peripheral requires supervisor privilege level for accesses.
1319 */
1320#define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
1321#define AIPS_PACRB_TP3_MASK (0x10000U)
1322#define AIPS_PACRB_TP3_SHIFT (16U)
1323/*! TP3 - Trusted Protect
1324 * 0b0..Accesses from an untrusted master are allowed.
1325 * 0b1..Accesses from an untrusted master are not allowed.
1326 */
1327#define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
1328#define AIPS_PACRB_WP3_MASK (0x20000U)
1329#define AIPS_PACRB_WP3_SHIFT (17U)
1330/*! WP3 - Write Protect
1331 * 0b0..This peripheral allows write accesses.
1332 * 0b1..This peripheral is write protected.
1333 */
1334#define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
1335#define AIPS_PACRB_SP3_MASK (0x40000U)
1336#define AIPS_PACRB_SP3_SHIFT (18U)
1337/*! SP3 - Supervisor Protect
1338 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1339 * 0b1..This peripheral requires supervisor privilege level for accesses.
1340 */
1341#define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
1342#define AIPS_PACRB_TP2_MASK (0x100000U)
1343#define AIPS_PACRB_TP2_SHIFT (20U)
1344/*! TP2 - Trusted Protect
1345 * 0b0..Accesses from an untrusted master are allowed.
1346 * 0b1..Accesses from an untrusted master are not allowed.
1347 */
1348#define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
1349#define AIPS_PACRB_WP2_MASK (0x200000U)
1350#define AIPS_PACRB_WP2_SHIFT (21U)
1351/*! WP2 - Write Protect
1352 * 0b0..This peripheral allows write accesses.
1353 * 0b1..This peripheral is write protected.
1354 */
1355#define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
1356#define AIPS_PACRB_SP2_MASK (0x400000U)
1357#define AIPS_PACRB_SP2_SHIFT (22U)
1358/*! SP2 - Supervisor Protect
1359 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1360 * 0b1..This peripheral requires supervisor privilege level for accesses.
1361 */
1362#define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
1363#define AIPS_PACRB_TP1_MASK (0x1000000U)
1364#define AIPS_PACRB_TP1_SHIFT (24U)
1365/*! TP1 - Trusted Protect
1366 * 0b0..Accesses from an untrusted master are allowed.
1367 * 0b1..Accesses from an untrusted master are not allowed.
1368 */
1369#define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
1370#define AIPS_PACRB_WP1_MASK (0x2000000U)
1371#define AIPS_PACRB_WP1_SHIFT (25U)
1372/*! WP1 - Write Protect
1373 * 0b0..This peripheral allows write accesses.
1374 * 0b1..This peripheral is write protected.
1375 */
1376#define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
1377#define AIPS_PACRB_SP1_MASK (0x4000000U)
1378#define AIPS_PACRB_SP1_SHIFT (26U)
1379/*! SP1 - Supervisor Protect
1380 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1381 * 0b1..This peripheral requires supervisor privilege level for accesses.
1382 */
1383#define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
1384#define AIPS_PACRB_TP0_MASK (0x10000000U)
1385#define AIPS_PACRB_TP0_SHIFT (28U)
1386/*! TP0 - Trusted Protect
1387 * 0b0..Accesses from an untrusted master are allowed.
1388 * 0b1..Accesses from an untrusted master are not allowed.
1389 */
1390#define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
1391#define AIPS_PACRB_WP0_MASK (0x20000000U)
1392#define AIPS_PACRB_WP0_SHIFT (29U)
1393/*! WP0 - Write Protect
1394 * 0b0..This peripheral allows write accesses.
1395 * 0b1..This peripheral is write protected.
1396 */
1397#define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
1398#define AIPS_PACRB_SP0_MASK (0x40000000U)
1399#define AIPS_PACRB_SP0_SHIFT (30U)
1400/*! SP0 - Supervisor Protect
1401 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1402 * 0b1..This peripheral requires supervisor privilege level for accesses.
1403 */
1404#define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
1405/*! @} */
1406
1407/*! @name PACRC - Peripheral Access Control Register */
1408/*! @{ */
1409#define AIPS_PACRC_TP7_MASK (0x1U)
1410#define AIPS_PACRC_TP7_SHIFT (0U)
1411/*! TP7 - Trusted Protect
1412 * 0b0..Accesses from an untrusted master are allowed.
1413 * 0b1..Accesses from an untrusted master are not allowed.
1414 */
1415#define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
1416#define AIPS_PACRC_WP7_MASK (0x2U)
1417#define AIPS_PACRC_WP7_SHIFT (1U)
1418/*! WP7 - Write Protect
1419 * 0b0..This peripheral allows write accesses.
1420 * 0b1..This peripheral is write protected.
1421 */
1422#define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
1423#define AIPS_PACRC_SP7_MASK (0x4U)
1424#define AIPS_PACRC_SP7_SHIFT (2U)
1425/*! SP7 - Supervisor Protect
1426 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1427 * 0b1..This peripheral requires supervisor privilege level for accesses.
1428 */
1429#define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
1430#define AIPS_PACRC_TP6_MASK (0x10U)
1431#define AIPS_PACRC_TP6_SHIFT (4U)
1432/*! TP6 - Trusted Protect
1433 * 0b0..Accesses from an untrusted master are allowed.
1434 * 0b1..Accesses from an untrusted master are not allowed.
1435 */
1436#define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
1437#define AIPS_PACRC_WP6_MASK (0x20U)
1438#define AIPS_PACRC_WP6_SHIFT (5U)
1439/*! WP6 - Write Protect
1440 * 0b0..This peripheral allows write accesses.
1441 * 0b1..This peripheral is write protected.
1442 */
1443#define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
1444#define AIPS_PACRC_SP6_MASK (0x40U)
1445#define AIPS_PACRC_SP6_SHIFT (6U)
1446/*! SP6 - Supervisor Protect
1447 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1448 * 0b1..This peripheral requires supervisor privilege level for accesses.
1449 */
1450#define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
1451#define AIPS_PACRC_TP5_MASK (0x100U)
1452#define AIPS_PACRC_TP5_SHIFT (8U)
1453/*! TP5 - Trusted Protect
1454 * 0b0..Accesses from an untrusted master are allowed.
1455 * 0b1..Accesses from an untrusted master are not allowed.
1456 */
1457#define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
1458#define AIPS_PACRC_WP5_MASK (0x200U)
1459#define AIPS_PACRC_WP5_SHIFT (9U)
1460/*! WP5 - Write Protect
1461 * 0b0..This peripheral allows write accesses.
1462 * 0b1..This peripheral is write protected.
1463 */
1464#define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
1465#define AIPS_PACRC_SP5_MASK (0x400U)
1466#define AIPS_PACRC_SP5_SHIFT (10U)
1467/*! SP5 - Supervisor Protect
1468 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1469 * 0b1..This peripheral requires supervisor privilege level for accesses.
1470 */
1471#define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
1472#define AIPS_PACRC_TP4_MASK (0x1000U)
1473#define AIPS_PACRC_TP4_SHIFT (12U)
1474/*! TP4 - Trusted Protect
1475 * 0b0..Accesses from an untrusted master are allowed.
1476 * 0b1..Accesses from an untrusted master are not allowed.
1477 */
1478#define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
1479#define AIPS_PACRC_WP4_MASK (0x2000U)
1480#define AIPS_PACRC_WP4_SHIFT (13U)
1481/*! WP4 - Write Protect
1482 * 0b0..This peripheral allows write accesses.
1483 * 0b1..This peripheral is write protected.
1484 */
1485#define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
1486#define AIPS_PACRC_SP4_MASK (0x4000U)
1487#define AIPS_PACRC_SP4_SHIFT (14U)
1488/*! SP4 - Supervisor Protect
1489 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1490 * 0b1..This peripheral requires supervisor privilege level for accesses.
1491 */
1492#define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
1493#define AIPS_PACRC_TP3_MASK (0x10000U)
1494#define AIPS_PACRC_TP3_SHIFT (16U)
1495/*! TP3 - Trusted Protect
1496 * 0b0..Accesses from an untrusted master are allowed.
1497 * 0b1..Accesses from an untrusted master are not allowed.
1498 */
1499#define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
1500#define AIPS_PACRC_WP3_MASK (0x20000U)
1501#define AIPS_PACRC_WP3_SHIFT (17U)
1502/*! WP3 - Write Protect
1503 * 0b0..This peripheral allows write accesses.
1504 * 0b1..This peripheral is write protected.
1505 */
1506#define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
1507#define AIPS_PACRC_SP3_MASK (0x40000U)
1508#define AIPS_PACRC_SP3_SHIFT (18U)
1509/*! SP3 - Supervisor Protect
1510 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1511 * 0b1..This peripheral requires supervisor privilege level for accesses.
1512 */
1513#define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
1514#define AIPS_PACRC_TP2_MASK (0x100000U)
1515#define AIPS_PACRC_TP2_SHIFT (20U)
1516/*! TP2 - Trusted Protect
1517 * 0b0..Accesses from an untrusted master are allowed.
1518 * 0b1..Accesses from an untrusted master are not allowed.
1519 */
1520#define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
1521#define AIPS_PACRC_WP2_MASK (0x200000U)
1522#define AIPS_PACRC_WP2_SHIFT (21U)
1523/*! WP2 - Write Protect
1524 * 0b0..This peripheral allows write accesses.
1525 * 0b1..This peripheral is write protected.
1526 */
1527#define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
1528#define AIPS_PACRC_SP2_MASK (0x400000U)
1529#define AIPS_PACRC_SP2_SHIFT (22U)
1530/*! SP2 - Supervisor Protect
1531 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1532 * 0b1..This peripheral requires supervisor privilege level for accesses.
1533 */
1534#define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
1535#define AIPS_PACRC_TP1_MASK (0x1000000U)
1536#define AIPS_PACRC_TP1_SHIFT (24U)
1537/*! TP1 - Trusted Protect
1538 * 0b0..Accesses from an untrusted master are allowed.
1539 * 0b1..Accesses from an untrusted master are not allowed.
1540 */
1541#define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
1542#define AIPS_PACRC_WP1_MASK (0x2000000U)
1543#define AIPS_PACRC_WP1_SHIFT (25U)
1544/*! WP1 - Write Protect
1545 * 0b0..This peripheral allows write accesses.
1546 * 0b1..This peripheral is write protected.
1547 */
1548#define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
1549#define AIPS_PACRC_SP1_MASK (0x4000000U)
1550#define AIPS_PACRC_SP1_SHIFT (26U)
1551/*! SP1 - Supervisor Protect
1552 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1553 * 0b1..This peripheral requires supervisor privilege level for accesses.
1554 */
1555#define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
1556#define AIPS_PACRC_TP0_MASK (0x10000000U)
1557#define AIPS_PACRC_TP0_SHIFT (28U)
1558/*! TP0 - Trusted Protect
1559 * 0b0..Accesses from an untrusted master are allowed.
1560 * 0b1..Accesses from an untrusted master are not allowed.
1561 */
1562#define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
1563#define AIPS_PACRC_WP0_MASK (0x20000000U)
1564#define AIPS_PACRC_WP0_SHIFT (29U)
1565/*! WP0 - Write Protect
1566 * 0b0..This peripheral allows write accesses.
1567 * 0b1..This peripheral is write protected.
1568 */
1569#define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
1570#define AIPS_PACRC_SP0_MASK (0x40000000U)
1571#define AIPS_PACRC_SP0_SHIFT (30U)
1572/*! SP0 - Supervisor Protect
1573 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1574 * 0b1..This peripheral requires supervisor privilege level for accesses.
1575 */
1576#define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
1577/*! @} */
1578
1579/*! @name PACRD - Peripheral Access Control Register */
1580/*! @{ */
1581#define AIPS_PACRD_TP7_MASK (0x1U)
1582#define AIPS_PACRD_TP7_SHIFT (0U)
1583/*! TP7 - Trusted Protect
1584 * 0b0..Accesses from an untrusted master are allowed.
1585 * 0b1..Accesses from an untrusted master are not allowed.
1586 */
1587#define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
1588#define AIPS_PACRD_WP7_MASK (0x2U)
1589#define AIPS_PACRD_WP7_SHIFT (1U)
1590/*! WP7 - Write Protect
1591 * 0b0..This peripheral allows write accesses.
1592 * 0b1..This peripheral is write protected.
1593 */
1594#define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
1595#define AIPS_PACRD_SP7_MASK (0x4U)
1596#define AIPS_PACRD_SP7_SHIFT (2U)
1597/*! SP7 - Supervisor Protect
1598 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1599 * 0b1..This peripheral requires supervisor privilege level for accesses.
1600 */
1601#define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
1602#define AIPS_PACRD_TP6_MASK (0x10U)
1603#define AIPS_PACRD_TP6_SHIFT (4U)
1604/*! TP6 - Trusted Protect
1605 * 0b0..Accesses from an untrusted master are allowed.
1606 * 0b1..Accesses from an untrusted master are not allowed.
1607 */
1608#define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
1609#define AIPS_PACRD_WP6_MASK (0x20U)
1610#define AIPS_PACRD_WP6_SHIFT (5U)
1611/*! WP6 - Write Protect
1612 * 0b0..This peripheral allows write accesses.
1613 * 0b1..This peripheral is write protected.
1614 */
1615#define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
1616#define AIPS_PACRD_SP6_MASK (0x40U)
1617#define AIPS_PACRD_SP6_SHIFT (6U)
1618/*! SP6 - Supervisor Protect
1619 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1620 * 0b1..This peripheral requires supervisor privilege level for accesses.
1621 */
1622#define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
1623#define AIPS_PACRD_TP5_MASK (0x100U)
1624#define AIPS_PACRD_TP5_SHIFT (8U)
1625/*! TP5 - Trusted Protect
1626 * 0b0..Accesses from an untrusted master are allowed.
1627 * 0b1..Accesses from an untrusted master are not allowed.
1628 */
1629#define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
1630#define AIPS_PACRD_WP5_MASK (0x200U)
1631#define AIPS_PACRD_WP5_SHIFT (9U)
1632/*! WP5 - Write Protect
1633 * 0b0..This peripheral allows write accesses.
1634 * 0b1..This peripheral is write protected.
1635 */
1636#define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
1637#define AIPS_PACRD_SP5_MASK (0x400U)
1638#define AIPS_PACRD_SP5_SHIFT (10U)
1639/*! SP5 - Supervisor Protect
1640 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1641 * 0b1..This peripheral requires supervisor privilege level for accesses.
1642 */
1643#define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
1644#define AIPS_PACRD_TP4_MASK (0x1000U)
1645#define AIPS_PACRD_TP4_SHIFT (12U)
1646/*! TP4 - Trusted Protect
1647 * 0b0..Accesses from an untrusted master are allowed.
1648 * 0b1..Accesses from an untrusted master are not allowed.
1649 */
1650#define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
1651#define AIPS_PACRD_WP4_MASK (0x2000U)
1652#define AIPS_PACRD_WP4_SHIFT (13U)
1653/*! WP4 - Write Protect
1654 * 0b0..This peripheral allows write accesses.
1655 * 0b1..This peripheral is write protected.
1656 */
1657#define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
1658#define AIPS_PACRD_SP4_MASK (0x4000U)
1659#define AIPS_PACRD_SP4_SHIFT (14U)
1660/*! SP4 - Supervisor Protect
1661 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1662 * 0b1..This peripheral requires supervisor privilege level for accesses.
1663 */
1664#define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
1665#define AIPS_PACRD_TP3_MASK (0x10000U)
1666#define AIPS_PACRD_TP3_SHIFT (16U)
1667/*! TP3 - Trusted Protect
1668 * 0b0..Accesses from an untrusted master are allowed.
1669 * 0b1..Accesses from an untrusted master are not allowed.
1670 */
1671#define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
1672#define AIPS_PACRD_WP3_MASK (0x20000U)
1673#define AIPS_PACRD_WP3_SHIFT (17U)
1674/*! WP3 - Write Protect
1675 * 0b0..This peripheral allows write accesses.
1676 * 0b1..This peripheral is write protected.
1677 */
1678#define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
1679#define AIPS_PACRD_SP3_MASK (0x40000U)
1680#define AIPS_PACRD_SP3_SHIFT (18U)
1681/*! SP3 - Supervisor Protect
1682 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1683 * 0b1..This peripheral requires supervisor privilege level for accesses.
1684 */
1685#define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
1686#define AIPS_PACRD_TP2_MASK (0x100000U)
1687#define AIPS_PACRD_TP2_SHIFT (20U)
1688/*! TP2 - Trusted Protect
1689 * 0b0..Accesses from an untrusted master are allowed.
1690 * 0b1..Accesses from an untrusted master are not allowed.
1691 */
1692#define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
1693#define AIPS_PACRD_WP2_MASK (0x200000U)
1694#define AIPS_PACRD_WP2_SHIFT (21U)
1695/*! WP2 - Write Protect
1696 * 0b0..This peripheral allows write accesses.
1697 * 0b1..This peripheral is write protected.
1698 */
1699#define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
1700#define AIPS_PACRD_SP2_MASK (0x400000U)
1701#define AIPS_PACRD_SP2_SHIFT (22U)
1702/*! SP2 - Supervisor Protect
1703 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1704 * 0b1..This peripheral requires supervisor privilege level for accesses.
1705 */
1706#define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
1707#define AIPS_PACRD_TP1_MASK (0x1000000U)
1708#define AIPS_PACRD_TP1_SHIFT (24U)
1709/*! TP1 - Trusted Protect
1710 * 0b0..Accesses from an untrusted master are allowed.
1711 * 0b1..Accesses from an untrusted master are not allowed.
1712 */
1713#define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
1714#define AIPS_PACRD_WP1_MASK (0x2000000U)
1715#define AIPS_PACRD_WP1_SHIFT (25U)
1716/*! WP1 - Write Protect
1717 * 0b0..This peripheral allows write accesses.
1718 * 0b1..This peripheral is write protected.
1719 */
1720#define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
1721#define AIPS_PACRD_SP1_MASK (0x4000000U)
1722#define AIPS_PACRD_SP1_SHIFT (26U)
1723/*! SP1 - Supervisor Protect
1724 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1725 * 0b1..This peripheral requires supervisor privilege level for accesses.
1726 */
1727#define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
1728#define AIPS_PACRD_TP0_MASK (0x10000000U)
1729#define AIPS_PACRD_TP0_SHIFT (28U)
1730/*! TP0 - Trusted Protect
1731 * 0b0..Accesses from an untrusted master are allowed.
1732 * 0b1..Accesses from an untrusted master are not allowed.
1733 */
1734#define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
1735#define AIPS_PACRD_WP0_MASK (0x20000000U)
1736#define AIPS_PACRD_WP0_SHIFT (29U)
1737/*! WP0 - Write Protect
1738 * 0b0..This peripheral allows write accesses.
1739 * 0b1..This peripheral is write protected.
1740 */
1741#define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
1742#define AIPS_PACRD_SP0_MASK (0x40000000U)
1743#define AIPS_PACRD_SP0_SHIFT (30U)
1744/*! SP0 - Supervisor Protect
1745 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1746 * 0b1..This peripheral requires supervisor privilege level for accesses.
1747 */
1748#define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
1749/*! @} */
1750
1751/*! @name PACRE - Peripheral Access Control Register */
1752/*! @{ */
1753#define AIPS_PACRE_TP7_MASK (0x1U)
1754#define AIPS_PACRE_TP7_SHIFT (0U)
1755/*! TP7 - Trusted Protect
1756 * 0b0..Accesses from an untrusted master are allowed.
1757 * 0b1..Accesses from an untrusted master are not allowed.
1758 */
1759#define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
1760#define AIPS_PACRE_WP7_MASK (0x2U)
1761#define AIPS_PACRE_WP7_SHIFT (1U)
1762/*! WP7 - Write Protect
1763 * 0b0..This peripheral allows write accesses.
1764 * 0b1..This peripheral is write protected.
1765 */
1766#define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
1767#define AIPS_PACRE_SP7_MASK (0x4U)
1768#define AIPS_PACRE_SP7_SHIFT (2U)
1769/*! SP7 - Supervisor Protect
1770 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1771 * 0b1..This peripheral requires supervisor privilege level for accesses.
1772 */
1773#define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
1774#define AIPS_PACRE_TP6_MASK (0x10U)
1775#define AIPS_PACRE_TP6_SHIFT (4U)
1776/*! TP6 - Trusted Protect
1777 * 0b0..Accesses from an untrusted master are allowed.
1778 * 0b1..Accesses from an untrusted master are not allowed.
1779 */
1780#define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
1781#define AIPS_PACRE_WP6_MASK (0x20U)
1782#define AIPS_PACRE_WP6_SHIFT (5U)
1783/*! WP6 - Write Protect
1784 * 0b0..This peripheral allows write accesses.
1785 * 0b1..This peripheral is write protected.
1786 */
1787#define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
1788#define AIPS_PACRE_SP6_MASK (0x40U)
1789#define AIPS_PACRE_SP6_SHIFT (6U)
1790/*! SP6 - Supervisor Protect
1791 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1792 * 0b1..This peripheral requires supervisor privilege level for accesses.
1793 */
1794#define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
1795#define AIPS_PACRE_TP5_MASK (0x100U)
1796#define AIPS_PACRE_TP5_SHIFT (8U)
1797/*! TP5 - Trusted Protect
1798 * 0b0..Accesses from an untrusted master are allowed.
1799 * 0b1..Accesses from an untrusted master are not allowed.
1800 */
1801#define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
1802#define AIPS_PACRE_WP5_MASK (0x200U)
1803#define AIPS_PACRE_WP5_SHIFT (9U)
1804/*! WP5 - Write Protect
1805 * 0b0..This peripheral allows write accesses.
1806 * 0b1..This peripheral is write protected.
1807 */
1808#define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
1809#define AIPS_PACRE_SP5_MASK (0x400U)
1810#define AIPS_PACRE_SP5_SHIFT (10U)
1811/*! SP5 - Supervisor Protect
1812 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1813 * 0b1..This peripheral requires supervisor privilege level for accesses.
1814 */
1815#define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
1816#define AIPS_PACRE_TP4_MASK (0x1000U)
1817#define AIPS_PACRE_TP4_SHIFT (12U)
1818/*! TP4 - Trusted Protect
1819 * 0b0..Accesses from an untrusted master are allowed.
1820 * 0b1..Accesses from an untrusted master are not allowed.
1821 */
1822#define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
1823#define AIPS_PACRE_WP4_MASK (0x2000U)
1824#define AIPS_PACRE_WP4_SHIFT (13U)
1825/*! WP4 - Write Protect
1826 * 0b0..This peripheral allows write accesses.
1827 * 0b1..This peripheral is write protected.
1828 */
1829#define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
1830#define AIPS_PACRE_SP4_MASK (0x4000U)
1831#define AIPS_PACRE_SP4_SHIFT (14U)
1832/*! SP4 - Supervisor Protect
1833 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1834 * 0b1..This peripheral requires supervisor privilege level for accesses.
1835 */
1836#define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
1837#define AIPS_PACRE_TP3_MASK (0x10000U)
1838#define AIPS_PACRE_TP3_SHIFT (16U)
1839/*! TP3 - Trusted Protect
1840 * 0b0..Accesses from an untrusted master are allowed.
1841 * 0b1..Accesses from an untrusted master are not allowed.
1842 */
1843#define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
1844#define AIPS_PACRE_WP3_MASK (0x20000U)
1845#define AIPS_PACRE_WP3_SHIFT (17U)
1846/*! WP3 - Write Protect
1847 * 0b0..This peripheral allows write accesses.
1848 * 0b1..This peripheral is write protected.
1849 */
1850#define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
1851#define AIPS_PACRE_SP3_MASK (0x40000U)
1852#define AIPS_PACRE_SP3_SHIFT (18U)
1853/*! SP3 - Supervisor Protect
1854 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1855 * 0b1..This peripheral requires supervisor privilege level for accesses.
1856 */
1857#define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
1858#define AIPS_PACRE_TP2_MASK (0x100000U)
1859#define AIPS_PACRE_TP2_SHIFT (20U)
1860/*! TP2 - Trusted Protect
1861 * 0b0..Accesses from an untrusted master are allowed.
1862 * 0b1..Accesses from an untrusted master are not allowed.
1863 */
1864#define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
1865#define AIPS_PACRE_WP2_MASK (0x200000U)
1866#define AIPS_PACRE_WP2_SHIFT (21U)
1867/*! WP2 - Write Protect
1868 * 0b0..This peripheral allows write accesses.
1869 * 0b1..This peripheral is write protected.
1870 */
1871#define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
1872#define AIPS_PACRE_SP2_MASK (0x400000U)
1873#define AIPS_PACRE_SP2_SHIFT (22U)
1874/*! SP2 - Supervisor Protect
1875 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1876 * 0b1..This peripheral requires supervisor privilege level for accesses.
1877 */
1878#define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
1879#define AIPS_PACRE_TP1_MASK (0x1000000U)
1880#define AIPS_PACRE_TP1_SHIFT (24U)
1881/*! TP1 - Trusted Protect
1882 * 0b0..Accesses from an untrusted master are allowed.
1883 * 0b1..Accesses from an untrusted master are not allowed.
1884 */
1885#define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
1886#define AIPS_PACRE_WP1_MASK (0x2000000U)
1887#define AIPS_PACRE_WP1_SHIFT (25U)
1888/*! WP1 - Write Protect
1889 * 0b0..This peripheral allows write accesses.
1890 * 0b1..This peripheral is write protected.
1891 */
1892#define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
1893#define AIPS_PACRE_SP1_MASK (0x4000000U)
1894#define AIPS_PACRE_SP1_SHIFT (26U)
1895/*! SP1 - Supervisor Protect
1896 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1897 * 0b1..This peripheral requires supervisor privilege level for accesses.
1898 */
1899#define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
1900#define AIPS_PACRE_TP0_MASK (0x10000000U)
1901#define AIPS_PACRE_TP0_SHIFT (28U)
1902/*! TP0 - Trusted Protect
1903 * 0b0..Accesses from an untrusted master are allowed.
1904 * 0b1..Accesses from an untrusted master are not allowed.
1905 */
1906#define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
1907#define AIPS_PACRE_WP0_MASK (0x20000000U)
1908#define AIPS_PACRE_WP0_SHIFT (29U)
1909/*! WP0 - Write Protect
1910 * 0b0..This peripheral allows write accesses.
1911 * 0b1..This peripheral is write protected.
1912 */
1913#define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
1914#define AIPS_PACRE_SP0_MASK (0x40000000U)
1915#define AIPS_PACRE_SP0_SHIFT (30U)
1916/*! SP0 - Supervisor Protect
1917 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1918 * 0b1..This peripheral requires supervisor privilege level for accesses.
1919 */
1920#define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
1921/*! @} */
1922
1923/*! @name PACRF - Peripheral Access Control Register */
1924/*! @{ */
1925#define AIPS_PACRF_TP7_MASK (0x1U)
1926#define AIPS_PACRF_TP7_SHIFT (0U)
1927/*! TP7 - Trusted Protect
1928 * 0b0..Accesses from an untrusted master are allowed.
1929 * 0b1..Accesses from an untrusted master are not allowed.
1930 */
1931#define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
1932#define AIPS_PACRF_WP7_MASK (0x2U)
1933#define AIPS_PACRF_WP7_SHIFT (1U)
1934/*! WP7 - Write Protect
1935 * 0b0..This peripheral allows write accesses.
1936 * 0b1..This peripheral is write protected.
1937 */
1938#define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
1939#define AIPS_PACRF_SP7_MASK (0x4U)
1940#define AIPS_PACRF_SP7_SHIFT (2U)
1941/*! SP7 - Supervisor Protect
1942 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1943 * 0b1..This peripheral requires supervisor privilege level for accesses.
1944 */
1945#define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
1946#define AIPS_PACRF_TP6_MASK (0x10U)
1947#define AIPS_PACRF_TP6_SHIFT (4U)
1948/*! TP6 - Trusted Protect
1949 * 0b0..Accesses from an untrusted master are allowed.
1950 * 0b1..Accesses from an untrusted master are not allowed.
1951 */
1952#define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
1953#define AIPS_PACRF_WP6_MASK (0x20U)
1954#define AIPS_PACRF_WP6_SHIFT (5U)
1955/*! WP6 - Write Protect
1956 * 0b0..This peripheral allows write accesses.
1957 * 0b1..This peripheral is write protected.
1958 */
1959#define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
1960#define AIPS_PACRF_SP6_MASK (0x40U)
1961#define AIPS_PACRF_SP6_SHIFT (6U)
1962/*! SP6 - Supervisor Protect
1963 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1964 * 0b1..This peripheral requires supervisor privilege level for accesses.
1965 */
1966#define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
1967#define AIPS_PACRF_TP5_MASK (0x100U)
1968#define AIPS_PACRF_TP5_SHIFT (8U)
1969/*! TP5 - Trusted Protect
1970 * 0b0..Accesses from an untrusted master are allowed.
1971 * 0b1..Accesses from an untrusted master are not allowed.
1972 */
1973#define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
1974#define AIPS_PACRF_WP5_MASK (0x200U)
1975#define AIPS_PACRF_WP5_SHIFT (9U)
1976/*! WP5 - Write Protect
1977 * 0b0..This peripheral allows write accesses.
1978 * 0b1..This peripheral is write protected.
1979 */
1980#define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
1981#define AIPS_PACRF_SP5_MASK (0x400U)
1982#define AIPS_PACRF_SP5_SHIFT (10U)
1983/*! SP5 - Supervisor Protect
1984 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1985 * 0b1..This peripheral requires supervisor privilege level for accesses.
1986 */
1987#define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
1988#define AIPS_PACRF_TP4_MASK (0x1000U)
1989#define AIPS_PACRF_TP4_SHIFT (12U)
1990/*! TP4 - Trusted Protect
1991 * 0b0..Accesses from an untrusted master are allowed.
1992 * 0b1..Accesses from an untrusted master are not allowed.
1993 */
1994#define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
1995#define AIPS_PACRF_WP4_MASK (0x2000U)
1996#define AIPS_PACRF_WP4_SHIFT (13U)
1997/*! WP4 - Write Protect
1998 * 0b0..This peripheral allows write accesses.
1999 * 0b1..This peripheral is write protected.
2000 */
2001#define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
2002#define AIPS_PACRF_SP4_MASK (0x4000U)
2003#define AIPS_PACRF_SP4_SHIFT (14U)
2004/*! SP4 - Supervisor Protect
2005 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2006 * 0b1..This peripheral requires supervisor privilege level for accesses.
2007 */
2008#define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
2009#define AIPS_PACRF_TP3_MASK (0x10000U)
2010#define AIPS_PACRF_TP3_SHIFT (16U)
2011/*! TP3 - Trusted Protect
2012 * 0b0..Accesses from an untrusted master are allowed.
2013 * 0b1..Accesses from an untrusted master are not allowed.
2014 */
2015#define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
2016#define AIPS_PACRF_WP3_MASK (0x20000U)
2017#define AIPS_PACRF_WP3_SHIFT (17U)
2018/*! WP3 - Write Protect
2019 * 0b0..This peripheral allows write accesses.
2020 * 0b1..This peripheral is write protected.
2021 */
2022#define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
2023#define AIPS_PACRF_SP3_MASK (0x40000U)
2024#define AIPS_PACRF_SP3_SHIFT (18U)
2025/*! SP3 - Supervisor Protect
2026 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2027 * 0b1..This peripheral requires supervisor privilege level for accesses.
2028 */
2029#define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
2030#define AIPS_PACRF_TP2_MASK (0x100000U)
2031#define AIPS_PACRF_TP2_SHIFT (20U)
2032/*! TP2 - Trusted Protect
2033 * 0b0..Accesses from an untrusted master are allowed.
2034 * 0b1..Accesses from an untrusted master are not allowed.
2035 */
2036#define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
2037#define AIPS_PACRF_WP2_MASK (0x200000U)
2038#define AIPS_PACRF_WP2_SHIFT (21U)
2039/*! WP2 - Write Protect
2040 * 0b0..This peripheral allows write accesses.
2041 * 0b1..This peripheral is write protected.
2042 */
2043#define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
2044#define AIPS_PACRF_SP2_MASK (0x400000U)
2045#define AIPS_PACRF_SP2_SHIFT (22U)
2046/*! SP2 - Supervisor Protect
2047 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2048 * 0b1..This peripheral requires supervisor privilege level for accesses.
2049 */
2050#define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
2051#define AIPS_PACRF_TP1_MASK (0x1000000U)
2052#define AIPS_PACRF_TP1_SHIFT (24U)
2053/*! TP1 - Trusted Protect
2054 * 0b0..Accesses from an untrusted master are allowed.
2055 * 0b1..Accesses from an untrusted master are not allowed.
2056 */
2057#define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
2058#define AIPS_PACRF_WP1_MASK (0x2000000U)
2059#define AIPS_PACRF_WP1_SHIFT (25U)
2060/*! WP1 - Write Protect
2061 * 0b0..This peripheral allows write accesses.
2062 * 0b1..This peripheral is write protected.
2063 */
2064#define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
2065#define AIPS_PACRF_SP1_MASK (0x4000000U)
2066#define AIPS_PACRF_SP1_SHIFT (26U)
2067/*! SP1 - Supervisor Protect
2068 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2069 * 0b1..This peripheral requires supervisor privilege level for accesses.
2070 */
2071#define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
2072#define AIPS_PACRF_TP0_MASK (0x10000000U)
2073#define AIPS_PACRF_TP0_SHIFT (28U)
2074/*! TP0 - Trusted Protect
2075 * 0b0..Accesses from an untrusted master are allowed.
2076 * 0b1..Accesses from an untrusted master are not allowed.
2077 */
2078#define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
2079#define AIPS_PACRF_WP0_MASK (0x20000000U)
2080#define AIPS_PACRF_WP0_SHIFT (29U)
2081/*! WP0 - Write Protect
2082 * 0b0..This peripheral allows write accesses.
2083 * 0b1..This peripheral is write protected.
2084 */
2085#define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
2086#define AIPS_PACRF_SP0_MASK (0x40000000U)
2087#define AIPS_PACRF_SP0_SHIFT (30U)
2088/*! SP0 - Supervisor Protect
2089 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2090 * 0b1..This peripheral requires supervisor privilege level for accesses.
2091 */
2092#define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
2093/*! @} */
2094
2095/*! @name PACRG - Peripheral Access Control Register */
2096/*! @{ */
2097#define AIPS_PACRG_TP7_MASK (0x1U)
2098#define AIPS_PACRG_TP7_SHIFT (0U)
2099/*! TP7 - Trusted Protect
2100 * 0b0..Accesses from an untrusted master are allowed.
2101 * 0b1..Accesses from an untrusted master are not allowed.
2102 */
2103#define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
2104#define AIPS_PACRG_WP7_MASK (0x2U)
2105#define AIPS_PACRG_WP7_SHIFT (1U)
2106/*! WP7 - Write Protect
2107 * 0b0..This peripheral allows write accesses.
2108 * 0b1..This peripheral is write protected.
2109 */
2110#define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
2111#define AIPS_PACRG_SP7_MASK (0x4U)
2112#define AIPS_PACRG_SP7_SHIFT (2U)
2113/*! SP7 - Supervisor Protect
2114 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2115 * 0b1..This peripheral requires supervisor privilege level for accesses.
2116 */
2117#define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
2118#define AIPS_PACRG_TP6_MASK (0x10U)
2119#define AIPS_PACRG_TP6_SHIFT (4U)
2120/*! TP6 - Trusted Protect
2121 * 0b0..Accesses from an untrusted master are allowed.
2122 * 0b1..Accesses from an untrusted master are not allowed.
2123 */
2124#define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
2125#define AIPS_PACRG_WP6_MASK (0x20U)
2126#define AIPS_PACRG_WP6_SHIFT (5U)
2127/*! WP6 - Write Protect
2128 * 0b0..This peripheral allows write accesses.
2129 * 0b1..This peripheral is write protected.
2130 */
2131#define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
2132#define AIPS_PACRG_SP6_MASK (0x40U)
2133#define AIPS_PACRG_SP6_SHIFT (6U)
2134/*! SP6 - Supervisor Protect
2135 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2136 * 0b1..This peripheral requires supervisor privilege level for accesses.
2137 */
2138#define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
2139#define AIPS_PACRG_TP5_MASK (0x100U)
2140#define AIPS_PACRG_TP5_SHIFT (8U)
2141/*! TP5 - Trusted Protect
2142 * 0b0..Accesses from an untrusted master are allowed.
2143 * 0b1..Accesses from an untrusted master are not allowed.
2144 */
2145#define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
2146#define AIPS_PACRG_WP5_MASK (0x200U)
2147#define AIPS_PACRG_WP5_SHIFT (9U)
2148/*! WP5 - Write Protect
2149 * 0b0..This peripheral allows write accesses.
2150 * 0b1..This peripheral is write protected.
2151 */
2152#define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
2153#define AIPS_PACRG_SP5_MASK (0x400U)
2154#define AIPS_PACRG_SP5_SHIFT (10U)
2155/*! SP5 - Supervisor Protect
2156 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2157 * 0b1..This peripheral requires supervisor privilege level for accesses.
2158 */
2159#define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
2160#define AIPS_PACRG_TP4_MASK (0x1000U)
2161#define AIPS_PACRG_TP4_SHIFT (12U)
2162/*! TP4 - Trusted Protect
2163 * 0b0..Accesses from an untrusted master are allowed.
2164 * 0b1..Accesses from an untrusted master are not allowed.
2165 */
2166#define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
2167#define AIPS_PACRG_WP4_MASK (0x2000U)
2168#define AIPS_PACRG_WP4_SHIFT (13U)
2169/*! WP4 - Write Protect
2170 * 0b0..This peripheral allows write accesses.
2171 * 0b1..This peripheral is write protected.
2172 */
2173#define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
2174#define AIPS_PACRG_SP4_MASK (0x4000U)
2175#define AIPS_PACRG_SP4_SHIFT (14U)
2176/*! SP4 - Supervisor Protect
2177 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2178 * 0b1..This peripheral requires supervisor privilege level for accesses.
2179 */
2180#define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
2181#define AIPS_PACRG_TP3_MASK (0x10000U)
2182#define AIPS_PACRG_TP3_SHIFT (16U)
2183/*! TP3 - Trusted Protect
2184 * 0b0..Accesses from an untrusted master are allowed.
2185 * 0b1..Accesses from an untrusted master are not allowed.
2186 */
2187#define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
2188#define AIPS_PACRG_WP3_MASK (0x20000U)
2189#define AIPS_PACRG_WP3_SHIFT (17U)
2190/*! WP3 - Write Protect
2191 * 0b0..This peripheral allows write accesses.
2192 * 0b1..This peripheral is write protected.
2193 */
2194#define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
2195#define AIPS_PACRG_SP3_MASK (0x40000U)
2196#define AIPS_PACRG_SP3_SHIFT (18U)
2197/*! SP3 - Supervisor Protect
2198 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2199 * 0b1..This peripheral requires supervisor privilege level for accesses.
2200 */
2201#define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
2202#define AIPS_PACRG_TP2_MASK (0x100000U)
2203#define AIPS_PACRG_TP2_SHIFT (20U)
2204/*! TP2 - Trusted Protect
2205 * 0b0..Accesses from an untrusted master are allowed.
2206 * 0b1..Accesses from an untrusted master are not allowed.
2207 */
2208#define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
2209#define AIPS_PACRG_WP2_MASK (0x200000U)
2210#define AIPS_PACRG_WP2_SHIFT (21U)
2211/*! WP2 - Write Protect
2212 * 0b0..This peripheral allows write accesses.
2213 * 0b1..This peripheral is write protected.
2214 */
2215#define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
2216#define AIPS_PACRG_SP2_MASK (0x400000U)
2217#define AIPS_PACRG_SP2_SHIFT (22U)
2218/*! SP2 - Supervisor Protect
2219 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2220 * 0b1..This peripheral requires supervisor privilege level for accesses.
2221 */
2222#define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
2223#define AIPS_PACRG_TP1_MASK (0x1000000U)
2224#define AIPS_PACRG_TP1_SHIFT (24U)
2225/*! TP1 - Trusted Protect
2226 * 0b0..Accesses from an untrusted master are allowed.
2227 * 0b1..Accesses from an untrusted master are not allowed.
2228 */
2229#define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
2230#define AIPS_PACRG_WP1_MASK (0x2000000U)
2231#define AIPS_PACRG_WP1_SHIFT (25U)
2232/*! WP1 - Write Protect
2233 * 0b0..This peripheral allows write accesses.
2234 * 0b1..This peripheral is write protected.
2235 */
2236#define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
2237#define AIPS_PACRG_SP1_MASK (0x4000000U)
2238#define AIPS_PACRG_SP1_SHIFT (26U)
2239/*! SP1 - Supervisor Protect
2240 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2241 * 0b1..This peripheral requires supervisor privilege level for accesses.
2242 */
2243#define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
2244#define AIPS_PACRG_TP0_MASK (0x10000000U)
2245#define AIPS_PACRG_TP0_SHIFT (28U)
2246/*! TP0 - Trusted Protect
2247 * 0b0..Accesses from an untrusted master are allowed.
2248 * 0b1..Accesses from an untrusted master are not allowed.
2249 */
2250#define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
2251#define AIPS_PACRG_WP0_MASK (0x20000000U)
2252#define AIPS_PACRG_WP0_SHIFT (29U)
2253/*! WP0 - Write Protect
2254 * 0b0..This peripheral allows write accesses.
2255 * 0b1..This peripheral is write protected.
2256 */
2257#define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
2258#define AIPS_PACRG_SP0_MASK (0x40000000U)
2259#define AIPS_PACRG_SP0_SHIFT (30U)
2260/*! SP0 - Supervisor Protect
2261 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2262 * 0b1..This peripheral requires supervisor privilege level for accesses.
2263 */
2264#define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
2265/*! @} */
2266
2267/*! @name PACRH - Peripheral Access Control Register */
2268/*! @{ */
2269#define AIPS_PACRH_TP7_MASK (0x1U)
2270#define AIPS_PACRH_TP7_SHIFT (0U)
2271/*! TP7 - Trusted Protect
2272 * 0b0..Accesses from an untrusted master are allowed.
2273 * 0b1..Accesses from an untrusted master are not allowed.
2274 */
2275#define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
2276#define AIPS_PACRH_WP7_MASK (0x2U)
2277#define AIPS_PACRH_WP7_SHIFT (1U)
2278/*! WP7 - Write Protect
2279 * 0b0..This peripheral allows write accesses.
2280 * 0b1..This peripheral is write protected.
2281 */
2282#define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
2283#define AIPS_PACRH_SP7_MASK (0x4U)
2284#define AIPS_PACRH_SP7_SHIFT (2U)
2285/*! SP7 - Supervisor Protect
2286 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2287 * 0b1..This peripheral requires supervisor privilege level for accesses.
2288 */
2289#define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
2290#define AIPS_PACRH_TP6_MASK (0x10U)
2291#define AIPS_PACRH_TP6_SHIFT (4U)
2292/*! TP6 - Trusted Protect
2293 * 0b0..Accesses from an untrusted master are allowed.
2294 * 0b1..Accesses from an untrusted master are not allowed.
2295 */
2296#define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
2297#define AIPS_PACRH_WP6_MASK (0x20U)
2298#define AIPS_PACRH_WP6_SHIFT (5U)
2299/*! WP6 - Write Protect
2300 * 0b0..This peripheral allows write accesses.
2301 * 0b1..This peripheral is write protected.
2302 */
2303#define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
2304#define AIPS_PACRH_SP6_MASK (0x40U)
2305#define AIPS_PACRH_SP6_SHIFT (6U)
2306/*! SP6 - Supervisor Protect
2307 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2308 * 0b1..This peripheral requires supervisor privilege level for accesses.
2309 */
2310#define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
2311#define AIPS_PACRH_TP5_MASK (0x100U)
2312#define AIPS_PACRH_TP5_SHIFT (8U)
2313/*! TP5 - Trusted Protect
2314 * 0b0..Accesses from an untrusted master are allowed.
2315 * 0b1..Accesses from an untrusted master are not allowed.
2316 */
2317#define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
2318#define AIPS_PACRH_WP5_MASK (0x200U)
2319#define AIPS_PACRH_WP5_SHIFT (9U)
2320/*! WP5 - Write Protect
2321 * 0b0..This peripheral allows write accesses.
2322 * 0b1..This peripheral is write protected.
2323 */
2324#define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
2325#define AIPS_PACRH_SP5_MASK (0x400U)
2326#define AIPS_PACRH_SP5_SHIFT (10U)
2327/*! SP5 - Supervisor Protect
2328 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2329 * 0b1..This peripheral requires supervisor privilege level for accesses.
2330 */
2331#define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
2332#define AIPS_PACRH_TP4_MASK (0x1000U)
2333#define AIPS_PACRH_TP4_SHIFT (12U)
2334/*! TP4 - Trusted Protect
2335 * 0b0..Accesses from an untrusted master are allowed.
2336 * 0b1..Accesses from an untrusted master are not allowed.
2337 */
2338#define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
2339#define AIPS_PACRH_WP4_MASK (0x2000U)
2340#define AIPS_PACRH_WP4_SHIFT (13U)
2341/*! WP4 - Write Protect
2342 * 0b0..This peripheral allows write accesses.
2343 * 0b1..This peripheral is write protected.
2344 */
2345#define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
2346#define AIPS_PACRH_SP4_MASK (0x4000U)
2347#define AIPS_PACRH_SP4_SHIFT (14U)
2348/*! SP4 - Supervisor Protect
2349 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2350 * 0b1..This peripheral requires supervisor privilege level for accesses.
2351 */
2352#define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
2353#define AIPS_PACRH_TP3_MASK (0x10000U)
2354#define AIPS_PACRH_TP3_SHIFT (16U)
2355/*! TP3 - Trusted Protect
2356 * 0b0..Accesses from an untrusted master are allowed.
2357 * 0b1..Accesses from an untrusted master are not allowed.
2358 */
2359#define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
2360#define AIPS_PACRH_WP3_MASK (0x20000U)
2361#define AIPS_PACRH_WP3_SHIFT (17U)
2362/*! WP3 - Write Protect
2363 * 0b0..This peripheral allows write accesses.
2364 * 0b1..This peripheral is write protected.
2365 */
2366#define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
2367#define AIPS_PACRH_SP3_MASK (0x40000U)
2368#define AIPS_PACRH_SP3_SHIFT (18U)
2369/*! SP3 - Supervisor Protect
2370 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2371 * 0b1..This peripheral requires supervisor privilege level for accesses.
2372 */
2373#define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
2374#define AIPS_PACRH_TP2_MASK (0x100000U)
2375#define AIPS_PACRH_TP2_SHIFT (20U)
2376/*! TP2 - Trusted Protect
2377 * 0b0..Accesses from an untrusted master are allowed.
2378 * 0b1..Accesses from an untrusted master are not allowed.
2379 */
2380#define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
2381#define AIPS_PACRH_WP2_MASK (0x200000U)
2382#define AIPS_PACRH_WP2_SHIFT (21U)
2383/*! WP2 - Write Protect
2384 * 0b0..This peripheral allows write accesses.
2385 * 0b1..This peripheral is write protected.
2386 */
2387#define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
2388#define AIPS_PACRH_SP2_MASK (0x400000U)
2389#define AIPS_PACRH_SP2_SHIFT (22U)
2390/*! SP2 - Supervisor Protect
2391 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2392 * 0b1..This peripheral requires supervisor privilege level for accesses.
2393 */
2394#define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
2395#define AIPS_PACRH_TP1_MASK (0x1000000U)
2396#define AIPS_PACRH_TP1_SHIFT (24U)
2397/*! TP1 - Trusted Protect
2398 * 0b0..Accesses from an untrusted master are allowed.
2399 * 0b1..Accesses from an untrusted master are not allowed.
2400 */
2401#define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
2402#define AIPS_PACRH_WP1_MASK (0x2000000U)
2403#define AIPS_PACRH_WP1_SHIFT (25U)
2404/*! WP1 - Write Protect
2405 * 0b0..This peripheral allows write accesses.
2406 * 0b1..This peripheral is write protected.
2407 */
2408#define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
2409#define AIPS_PACRH_SP1_MASK (0x4000000U)
2410#define AIPS_PACRH_SP1_SHIFT (26U)
2411/*! SP1 - Supervisor Protect
2412 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2413 * 0b1..This peripheral requires supervisor privilege level for accesses.
2414 */
2415#define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
2416#define AIPS_PACRH_TP0_MASK (0x10000000U)
2417#define AIPS_PACRH_TP0_SHIFT (28U)
2418/*! TP0 - Trusted Protect
2419 * 0b0..Accesses from an untrusted master are allowed.
2420 * 0b1..Accesses from an untrusted master are not allowed.
2421 */
2422#define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
2423#define AIPS_PACRH_WP0_MASK (0x20000000U)
2424#define AIPS_PACRH_WP0_SHIFT (29U)
2425/*! WP0 - Write Protect
2426 * 0b0..This peripheral allows write accesses.
2427 * 0b1..This peripheral is write protected.
2428 */
2429#define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
2430#define AIPS_PACRH_SP0_MASK (0x40000000U)
2431#define AIPS_PACRH_SP0_SHIFT (30U)
2432/*! SP0 - Supervisor Protect
2433 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2434 * 0b1..This peripheral requires supervisor privilege level for accesses.
2435 */
2436#define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
2437/*! @} */
2438
2439/*! @name PACRI - Peripheral Access Control Register */
2440/*! @{ */
2441#define AIPS_PACRI_TP7_MASK (0x1U)
2442#define AIPS_PACRI_TP7_SHIFT (0U)
2443/*! TP7 - Trusted Protect
2444 * 0b0..Accesses from an untrusted master are allowed.
2445 * 0b1..Accesses from an untrusted master are not allowed.
2446 */
2447#define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
2448#define AIPS_PACRI_WP7_MASK (0x2U)
2449#define AIPS_PACRI_WP7_SHIFT (1U)
2450/*! WP7 - Write Protect
2451 * 0b0..This peripheral allows write accesses.
2452 * 0b1..This peripheral is write protected.
2453 */
2454#define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
2455#define AIPS_PACRI_SP7_MASK (0x4U)
2456#define AIPS_PACRI_SP7_SHIFT (2U)
2457/*! SP7 - Supervisor Protect
2458 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2459 * 0b1..This peripheral requires supervisor privilege level for accesses.
2460 */
2461#define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
2462#define AIPS_PACRI_TP6_MASK (0x10U)
2463#define AIPS_PACRI_TP6_SHIFT (4U)
2464/*! TP6 - Trusted Protect
2465 * 0b0..Accesses from an untrusted master are allowed.
2466 * 0b1..Accesses from an untrusted master are not allowed.
2467 */
2468#define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
2469#define AIPS_PACRI_WP6_MASK (0x20U)
2470#define AIPS_PACRI_WP6_SHIFT (5U)
2471/*! WP6 - Write Protect
2472 * 0b0..This peripheral allows write accesses.
2473 * 0b1..This peripheral is write protected.
2474 */
2475#define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
2476#define AIPS_PACRI_SP6_MASK (0x40U)
2477#define AIPS_PACRI_SP6_SHIFT (6U)
2478/*! SP6 - Supervisor Protect
2479 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2480 * 0b1..This peripheral requires supervisor privilege level for accesses.
2481 */
2482#define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
2483#define AIPS_PACRI_TP5_MASK (0x100U)
2484#define AIPS_PACRI_TP5_SHIFT (8U)
2485/*! TP5 - Trusted Protect
2486 * 0b0..Accesses from an untrusted master are allowed.
2487 * 0b1..Accesses from an untrusted master are not allowed.
2488 */
2489#define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
2490#define AIPS_PACRI_WP5_MASK (0x200U)
2491#define AIPS_PACRI_WP5_SHIFT (9U)
2492/*! WP5 - Write Protect
2493 * 0b0..This peripheral allows write accesses.
2494 * 0b1..This peripheral is write protected.
2495 */
2496#define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
2497#define AIPS_PACRI_SP5_MASK (0x400U)
2498#define AIPS_PACRI_SP5_SHIFT (10U)
2499/*! SP5 - Supervisor Protect
2500 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2501 * 0b1..This peripheral requires supervisor privilege level for accesses.
2502 */
2503#define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
2504#define AIPS_PACRI_TP4_MASK (0x1000U)
2505#define AIPS_PACRI_TP4_SHIFT (12U)
2506/*! TP4 - Trusted Protect
2507 * 0b0..Accesses from an untrusted master are allowed.
2508 * 0b1..Accesses from an untrusted master are not allowed.
2509 */
2510#define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
2511#define AIPS_PACRI_WP4_MASK (0x2000U)
2512#define AIPS_PACRI_WP4_SHIFT (13U)
2513/*! WP4 - Write Protect
2514 * 0b0..This peripheral allows write accesses.
2515 * 0b1..This peripheral is write protected.
2516 */
2517#define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
2518#define AIPS_PACRI_SP4_MASK (0x4000U)
2519#define AIPS_PACRI_SP4_SHIFT (14U)
2520/*! SP4 - Supervisor Protect
2521 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2522 * 0b1..This peripheral requires supervisor privilege level for accesses.
2523 */
2524#define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
2525#define AIPS_PACRI_TP3_MASK (0x10000U)
2526#define AIPS_PACRI_TP3_SHIFT (16U)
2527/*! TP3 - Trusted Protect
2528 * 0b0..Accesses from an untrusted master are allowed.
2529 * 0b1..Accesses from an untrusted master are not allowed.
2530 */
2531#define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
2532#define AIPS_PACRI_WP3_MASK (0x20000U)
2533#define AIPS_PACRI_WP3_SHIFT (17U)
2534/*! WP3 - Write Protect
2535 * 0b0..This peripheral allows write accesses.
2536 * 0b1..This peripheral is write protected.
2537 */
2538#define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
2539#define AIPS_PACRI_SP3_MASK (0x40000U)
2540#define AIPS_PACRI_SP3_SHIFT (18U)
2541/*! SP3 - Supervisor Protect
2542 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2543 * 0b1..This peripheral requires supervisor privilege level for accesses.
2544 */
2545#define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
2546#define AIPS_PACRI_TP2_MASK (0x100000U)
2547#define AIPS_PACRI_TP2_SHIFT (20U)
2548/*! TP2 - Trusted Protect
2549 * 0b0..Accesses from an untrusted master are allowed.
2550 * 0b1..Accesses from an untrusted master are not allowed.
2551 */
2552#define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
2553#define AIPS_PACRI_WP2_MASK (0x200000U)
2554#define AIPS_PACRI_WP2_SHIFT (21U)
2555/*! WP2 - Write Protect
2556 * 0b0..This peripheral allows write accesses.
2557 * 0b1..This peripheral is write protected.
2558 */
2559#define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
2560#define AIPS_PACRI_SP2_MASK (0x400000U)
2561#define AIPS_PACRI_SP2_SHIFT (22U)
2562/*! SP2 - Supervisor Protect
2563 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2564 * 0b1..This peripheral requires supervisor privilege level for accesses.
2565 */
2566#define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
2567#define AIPS_PACRI_TP1_MASK (0x1000000U)
2568#define AIPS_PACRI_TP1_SHIFT (24U)
2569/*! TP1 - Trusted Protect
2570 * 0b0..Accesses from an untrusted master are allowed.
2571 * 0b1..Accesses from an untrusted master are not allowed.
2572 */
2573#define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
2574#define AIPS_PACRI_WP1_MASK (0x2000000U)
2575#define AIPS_PACRI_WP1_SHIFT (25U)
2576/*! WP1 - Write Protect
2577 * 0b0..This peripheral allows write accesses.
2578 * 0b1..This peripheral is write protected.
2579 */
2580#define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
2581#define AIPS_PACRI_SP1_MASK (0x4000000U)
2582#define AIPS_PACRI_SP1_SHIFT (26U)
2583/*! SP1 - Supervisor Protect
2584 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2585 * 0b1..This peripheral requires supervisor privilege level for accesses.
2586 */
2587#define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
2588#define AIPS_PACRI_TP0_MASK (0x10000000U)
2589#define AIPS_PACRI_TP0_SHIFT (28U)
2590/*! TP0 - Trusted Protect
2591 * 0b0..Accesses from an untrusted master are allowed.
2592 * 0b1..Accesses from an untrusted master are not allowed.
2593 */
2594#define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
2595#define AIPS_PACRI_WP0_MASK (0x20000000U)
2596#define AIPS_PACRI_WP0_SHIFT (29U)
2597/*! WP0 - Write Protect
2598 * 0b0..This peripheral allows write accesses.
2599 * 0b1..This peripheral is write protected.
2600 */
2601#define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
2602#define AIPS_PACRI_SP0_MASK (0x40000000U)
2603#define AIPS_PACRI_SP0_SHIFT (30U)
2604/*! SP0 - Supervisor Protect
2605 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2606 * 0b1..This peripheral requires supervisor privilege level for accesses.
2607 */
2608#define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
2609/*! @} */
2610
2611/*! @name PACRJ - Peripheral Access Control Register */
2612/*! @{ */
2613#define AIPS_PACRJ_TP7_MASK (0x1U)
2614#define AIPS_PACRJ_TP7_SHIFT (0U)
2615/*! TP7 - Trusted Protect
2616 * 0b0..Accesses from an untrusted master are allowed.
2617 * 0b1..Accesses from an untrusted master are not allowed.
2618 */
2619#define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
2620#define AIPS_PACRJ_WP7_MASK (0x2U)
2621#define AIPS_PACRJ_WP7_SHIFT (1U)
2622/*! WP7 - Write Protect
2623 * 0b0..This peripheral allows write accesses.
2624 * 0b1..This peripheral is write protected.
2625 */
2626#define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
2627#define AIPS_PACRJ_SP7_MASK (0x4U)
2628#define AIPS_PACRJ_SP7_SHIFT (2U)
2629/*! SP7 - Supervisor Protect
2630 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2631 * 0b1..This peripheral requires supervisor privilege level for accesses.
2632 */
2633#define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
2634#define AIPS_PACRJ_TP6_MASK (0x10U)
2635#define AIPS_PACRJ_TP6_SHIFT (4U)
2636/*! TP6 - Trusted Protect
2637 * 0b0..Accesses from an untrusted master are allowed.
2638 * 0b1..Accesses from an untrusted master are not allowed.
2639 */
2640#define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
2641#define AIPS_PACRJ_WP6_MASK (0x20U)
2642#define AIPS_PACRJ_WP6_SHIFT (5U)
2643/*! WP6 - Write Protect
2644 * 0b0..This peripheral allows write accesses.
2645 * 0b1..This peripheral is write protected.
2646 */
2647#define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
2648#define AIPS_PACRJ_SP6_MASK (0x40U)
2649#define AIPS_PACRJ_SP6_SHIFT (6U)
2650/*! SP6 - Supervisor Protect
2651 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2652 * 0b1..This peripheral requires supervisor privilege level for accesses.
2653 */
2654#define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
2655#define AIPS_PACRJ_TP5_MASK (0x100U)
2656#define AIPS_PACRJ_TP5_SHIFT (8U)
2657/*! TP5 - Trusted Protect
2658 * 0b0..Accesses from an untrusted master are allowed.
2659 * 0b1..Accesses from an untrusted master are not allowed.
2660 */
2661#define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
2662#define AIPS_PACRJ_WP5_MASK (0x200U)
2663#define AIPS_PACRJ_WP5_SHIFT (9U)
2664/*! WP5 - Write Protect
2665 * 0b0..This peripheral allows write accesses.
2666 * 0b1..This peripheral is write protected.
2667 */
2668#define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
2669#define AIPS_PACRJ_SP5_MASK (0x400U)
2670#define AIPS_PACRJ_SP5_SHIFT (10U)
2671/*! SP5 - Supervisor Protect
2672 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2673 * 0b1..This peripheral requires supervisor privilege level for accesses.
2674 */
2675#define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
2676#define AIPS_PACRJ_TP4_MASK (0x1000U)
2677#define AIPS_PACRJ_TP4_SHIFT (12U)
2678/*! TP4 - Trusted Protect
2679 * 0b0..Accesses from an untrusted master are allowed.
2680 * 0b1..Accesses from an untrusted master are not allowed.
2681 */
2682#define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
2683#define AIPS_PACRJ_WP4_MASK (0x2000U)
2684#define AIPS_PACRJ_WP4_SHIFT (13U)
2685/*! WP4 - Write Protect
2686 * 0b0..This peripheral allows write accesses.
2687 * 0b1..This peripheral is write protected.
2688 */
2689#define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
2690#define AIPS_PACRJ_SP4_MASK (0x4000U)
2691#define AIPS_PACRJ_SP4_SHIFT (14U)
2692/*! SP4 - Supervisor Protect
2693 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2694 * 0b1..This peripheral requires supervisor privilege level for accesses.
2695 */
2696#define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
2697#define AIPS_PACRJ_TP3_MASK (0x10000U)
2698#define AIPS_PACRJ_TP3_SHIFT (16U)
2699/*! TP3 - Trusted Protect
2700 * 0b0..Accesses from an untrusted master are allowed.
2701 * 0b1..Accesses from an untrusted master are not allowed.
2702 */
2703#define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
2704#define AIPS_PACRJ_WP3_MASK (0x20000U)
2705#define AIPS_PACRJ_WP3_SHIFT (17U)
2706/*! WP3 - Write Protect
2707 * 0b0..This peripheral allows write accesses.
2708 * 0b1..This peripheral is write protected.
2709 */
2710#define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
2711#define AIPS_PACRJ_SP3_MASK (0x40000U)
2712#define AIPS_PACRJ_SP3_SHIFT (18U)
2713/*! SP3 - Supervisor Protect
2714 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2715 * 0b1..This peripheral requires supervisor privilege level for accesses.
2716 */
2717#define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
2718#define AIPS_PACRJ_TP2_MASK (0x100000U)
2719#define AIPS_PACRJ_TP2_SHIFT (20U)
2720/*! TP2 - Trusted Protect
2721 * 0b0..Accesses from an untrusted master are allowed.
2722 * 0b1..Accesses from an untrusted master are not allowed.
2723 */
2724#define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
2725#define AIPS_PACRJ_WP2_MASK (0x200000U)
2726#define AIPS_PACRJ_WP2_SHIFT (21U)
2727/*! WP2 - Write Protect
2728 * 0b0..This peripheral allows write accesses.
2729 * 0b1..This peripheral is write protected.
2730 */
2731#define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
2732#define AIPS_PACRJ_SP2_MASK (0x400000U)
2733#define AIPS_PACRJ_SP2_SHIFT (22U)
2734/*! SP2 - Supervisor Protect
2735 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2736 * 0b1..This peripheral requires supervisor privilege level for accesses.
2737 */
2738#define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
2739#define AIPS_PACRJ_TP1_MASK (0x1000000U)
2740#define AIPS_PACRJ_TP1_SHIFT (24U)
2741/*! TP1 - Trusted Protect
2742 * 0b0..Accesses from an untrusted master are allowed.
2743 * 0b1..Accesses from an untrusted master are not allowed.
2744 */
2745#define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
2746#define AIPS_PACRJ_WP1_MASK (0x2000000U)
2747#define AIPS_PACRJ_WP1_SHIFT (25U)
2748/*! WP1 - Write Protect
2749 * 0b0..This peripheral allows write accesses.
2750 * 0b1..This peripheral is write protected.
2751 */
2752#define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
2753#define AIPS_PACRJ_SP1_MASK (0x4000000U)
2754#define AIPS_PACRJ_SP1_SHIFT (26U)
2755/*! SP1 - Supervisor Protect
2756 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2757 * 0b1..This peripheral requires supervisor privilege level for accesses.
2758 */
2759#define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
2760#define AIPS_PACRJ_TP0_MASK (0x10000000U)
2761#define AIPS_PACRJ_TP0_SHIFT (28U)
2762/*! TP0 - Trusted Protect
2763 * 0b0..Accesses from an untrusted master are allowed.
2764 * 0b1..Accesses from an untrusted master are not allowed.
2765 */
2766#define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
2767#define AIPS_PACRJ_WP0_MASK (0x20000000U)
2768#define AIPS_PACRJ_WP0_SHIFT (29U)
2769/*! WP0 - Write Protect
2770 * 0b0..This peripheral allows write accesses.
2771 * 0b1..This peripheral is write protected.
2772 */
2773#define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
2774#define AIPS_PACRJ_SP0_MASK (0x40000000U)
2775#define AIPS_PACRJ_SP0_SHIFT (30U)
2776/*! SP0 - Supervisor Protect
2777 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2778 * 0b1..This peripheral requires supervisor privilege level for accesses.
2779 */
2780#define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
2781/*! @} */
2782
2783/*! @name PACRK - Peripheral Access Control Register */
2784/*! @{ */
2785#define AIPS_PACRK_TP7_MASK (0x1U)
2786#define AIPS_PACRK_TP7_SHIFT (0U)
2787/*! TP7 - Trusted Protect
2788 * 0b0..Accesses from an untrusted master are allowed.
2789 * 0b1..Accesses from an untrusted master are not allowed.
2790 */
2791#define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
2792#define AIPS_PACRK_WP7_MASK (0x2U)
2793#define AIPS_PACRK_WP7_SHIFT (1U)
2794/*! WP7 - Write Protect
2795 * 0b0..This peripheral allows write accesses.
2796 * 0b1..This peripheral is write protected.
2797 */
2798#define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
2799#define AIPS_PACRK_SP7_MASK (0x4U)
2800#define AIPS_PACRK_SP7_SHIFT (2U)
2801/*! SP7 - Supervisor Protect
2802 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2803 * 0b1..This peripheral requires supervisor privilege level for accesses.
2804 */
2805#define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
2806#define AIPS_PACRK_TP6_MASK (0x10U)
2807#define AIPS_PACRK_TP6_SHIFT (4U)
2808/*! TP6 - Trusted Protect
2809 * 0b0..Accesses from an untrusted master are allowed.
2810 * 0b1..Accesses from an untrusted master are not allowed.
2811 */
2812#define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
2813#define AIPS_PACRK_WP6_MASK (0x20U)
2814#define AIPS_PACRK_WP6_SHIFT (5U)
2815/*! WP6 - Write Protect
2816 * 0b0..This peripheral allows write accesses.
2817 * 0b1..This peripheral is write protected.
2818 */
2819#define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
2820#define AIPS_PACRK_SP6_MASK (0x40U)
2821#define AIPS_PACRK_SP6_SHIFT (6U)
2822/*! SP6 - Supervisor Protect
2823 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2824 * 0b1..This peripheral requires supervisor privilege level for accesses.
2825 */
2826#define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
2827#define AIPS_PACRK_TP5_MASK (0x100U)
2828#define AIPS_PACRK_TP5_SHIFT (8U)
2829/*! TP5 - Trusted Protect
2830 * 0b0..Accesses from an untrusted master are allowed.
2831 * 0b1..Accesses from an untrusted master are not allowed.
2832 */
2833#define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
2834#define AIPS_PACRK_WP5_MASK (0x200U)
2835#define AIPS_PACRK_WP5_SHIFT (9U)
2836/*! WP5 - Write Protect
2837 * 0b0..This peripheral allows write accesses.
2838 * 0b1..This peripheral is write protected.
2839 */
2840#define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
2841#define AIPS_PACRK_SP5_MASK (0x400U)
2842#define AIPS_PACRK_SP5_SHIFT (10U)
2843/*! SP5 - Supervisor Protect
2844 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2845 * 0b1..This peripheral requires supervisor privilege level for accesses.
2846 */
2847#define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
2848#define AIPS_PACRK_TP4_MASK (0x1000U)
2849#define AIPS_PACRK_TP4_SHIFT (12U)
2850/*! TP4 - Trusted Protect
2851 * 0b0..Accesses from an untrusted master are allowed.
2852 * 0b1..Accesses from an untrusted master are not allowed.
2853 */
2854#define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
2855#define AIPS_PACRK_WP4_MASK (0x2000U)
2856#define AIPS_PACRK_WP4_SHIFT (13U)
2857/*! WP4 - Write Protect
2858 * 0b0..This peripheral allows write accesses.
2859 * 0b1..This peripheral is write protected.
2860 */
2861#define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
2862#define AIPS_PACRK_SP4_MASK (0x4000U)
2863#define AIPS_PACRK_SP4_SHIFT (14U)
2864/*! SP4 - Supervisor Protect
2865 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2866 * 0b1..This peripheral requires supervisor privilege level for accesses.
2867 */
2868#define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
2869#define AIPS_PACRK_TP3_MASK (0x10000U)
2870#define AIPS_PACRK_TP3_SHIFT (16U)
2871/*! TP3 - Trusted Protect
2872 * 0b0..Accesses from an untrusted master are allowed.
2873 * 0b1..Accesses from an untrusted master are not allowed.
2874 */
2875#define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
2876#define AIPS_PACRK_WP3_MASK (0x20000U)
2877#define AIPS_PACRK_WP3_SHIFT (17U)
2878/*! WP3 - Write Protect
2879 * 0b0..This peripheral allows write accesses.
2880 * 0b1..This peripheral is write protected.
2881 */
2882#define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
2883#define AIPS_PACRK_SP3_MASK (0x40000U)
2884#define AIPS_PACRK_SP3_SHIFT (18U)
2885/*! SP3 - Supervisor Protect
2886 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2887 * 0b1..This peripheral requires supervisor privilege level for accesses.
2888 */
2889#define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
2890#define AIPS_PACRK_TP2_MASK (0x100000U)
2891#define AIPS_PACRK_TP2_SHIFT (20U)
2892/*! TP2 - Trusted Protect
2893 * 0b0..Accesses from an untrusted master are allowed.
2894 * 0b1..Accesses from an untrusted master are not allowed.
2895 */
2896#define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
2897#define AIPS_PACRK_WP2_MASK (0x200000U)
2898#define AIPS_PACRK_WP2_SHIFT (21U)
2899/*! WP2 - Write Protect
2900 * 0b0..This peripheral allows write accesses.
2901 * 0b1..This peripheral is write protected.
2902 */
2903#define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
2904#define AIPS_PACRK_SP2_MASK (0x400000U)
2905#define AIPS_PACRK_SP2_SHIFT (22U)
2906/*! SP2 - Supervisor Protect
2907 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2908 * 0b1..This peripheral requires supervisor privilege level for accesses.
2909 */
2910#define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
2911#define AIPS_PACRK_TP1_MASK (0x1000000U)
2912#define AIPS_PACRK_TP1_SHIFT (24U)
2913/*! TP1 - Trusted Protect
2914 * 0b0..Accesses from an untrusted master are allowed.
2915 * 0b1..Accesses from an untrusted master are not allowed.
2916 */
2917#define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
2918#define AIPS_PACRK_WP1_MASK (0x2000000U)
2919#define AIPS_PACRK_WP1_SHIFT (25U)
2920/*! WP1 - Write Protect
2921 * 0b0..This peripheral allows write accesses.
2922 * 0b1..This peripheral is write protected.
2923 */
2924#define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
2925#define AIPS_PACRK_SP1_MASK (0x4000000U)
2926#define AIPS_PACRK_SP1_SHIFT (26U)
2927/*! SP1 - Supervisor Protect
2928 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2929 * 0b1..This peripheral requires supervisor privilege level for accesses.
2930 */
2931#define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
2932#define AIPS_PACRK_TP0_MASK (0x10000000U)
2933#define AIPS_PACRK_TP0_SHIFT (28U)
2934/*! TP0 - Trusted Protect
2935 * 0b0..Accesses from an untrusted master are allowed.
2936 * 0b1..Accesses from an untrusted master are not allowed.
2937 */
2938#define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
2939#define AIPS_PACRK_WP0_MASK (0x20000000U)
2940#define AIPS_PACRK_WP0_SHIFT (29U)
2941/*! WP0 - Write Protect
2942 * 0b0..This peripheral allows write accesses.
2943 * 0b1..This peripheral is write protected.
2944 */
2945#define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
2946#define AIPS_PACRK_SP0_MASK (0x40000000U)
2947#define AIPS_PACRK_SP0_SHIFT (30U)
2948/*! SP0 - Supervisor Protect
2949 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2950 * 0b1..This peripheral requires supervisor privilege level for accesses.
2951 */
2952#define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
2953/*! @} */
2954
2955/*! @name PACRL - Peripheral Access Control Register */
2956/*! @{ */
2957#define AIPS_PACRL_TP7_MASK (0x1U)
2958#define AIPS_PACRL_TP7_SHIFT (0U)
2959/*! TP7 - Trusted Protect
2960 * 0b0..Accesses from an untrusted master are allowed.
2961 * 0b1..Accesses from an untrusted master are not allowed.
2962 */
2963#define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
2964#define AIPS_PACRL_WP7_MASK (0x2U)
2965#define AIPS_PACRL_WP7_SHIFT (1U)
2966/*! WP7 - Write Protect
2967 * 0b0..This peripheral allows write accesses.
2968 * 0b1..This peripheral is write protected.
2969 */
2970#define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
2971#define AIPS_PACRL_SP7_MASK (0x4U)
2972#define AIPS_PACRL_SP7_SHIFT (2U)
2973/*! SP7 - Supervisor Protect
2974 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2975 * 0b1..This peripheral requires supervisor privilege level for accesses.
2976 */
2977#define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
2978#define AIPS_PACRL_TP6_MASK (0x10U)
2979#define AIPS_PACRL_TP6_SHIFT (4U)
2980/*! TP6 - Trusted Protect
2981 * 0b0..Accesses from an untrusted master are allowed.
2982 * 0b1..Accesses from an untrusted master are not allowed.
2983 */
2984#define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
2985#define AIPS_PACRL_WP6_MASK (0x20U)
2986#define AIPS_PACRL_WP6_SHIFT (5U)
2987/*! WP6 - Write Protect
2988 * 0b0..This peripheral allows write accesses.
2989 * 0b1..This peripheral is write protected.
2990 */
2991#define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
2992#define AIPS_PACRL_SP6_MASK (0x40U)
2993#define AIPS_PACRL_SP6_SHIFT (6U)
2994/*! SP6 - Supervisor Protect
2995 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2996 * 0b1..This peripheral requires supervisor privilege level for accesses.
2997 */
2998#define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
2999#define AIPS_PACRL_TP5_MASK (0x100U)
3000#define AIPS_PACRL_TP5_SHIFT (8U)
3001/*! TP5 - Trusted Protect
3002 * 0b0..Accesses from an untrusted master are allowed.
3003 * 0b1..Accesses from an untrusted master are not allowed.
3004 */
3005#define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
3006#define AIPS_PACRL_WP5_MASK (0x200U)
3007#define AIPS_PACRL_WP5_SHIFT (9U)
3008/*! WP5 - Write Protect
3009 * 0b0..This peripheral allows write accesses.
3010 * 0b1..This peripheral is write protected.
3011 */
3012#define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
3013#define AIPS_PACRL_SP5_MASK (0x400U)
3014#define AIPS_PACRL_SP5_SHIFT (10U)
3015/*! SP5 - Supervisor Protect
3016 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3017 * 0b1..This peripheral requires supervisor privilege level for accesses.
3018 */
3019#define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
3020#define AIPS_PACRL_TP4_MASK (0x1000U)
3021#define AIPS_PACRL_TP4_SHIFT (12U)
3022/*! TP4 - Trusted Protect
3023 * 0b0..Accesses from an untrusted master are allowed.
3024 * 0b1..Accesses from an untrusted master are not allowed.
3025 */
3026#define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
3027#define AIPS_PACRL_WP4_MASK (0x2000U)
3028#define AIPS_PACRL_WP4_SHIFT (13U)
3029/*! WP4 - Write Protect
3030 * 0b0..This peripheral allows write accesses.
3031 * 0b1..This peripheral is write protected.
3032 */
3033#define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
3034#define AIPS_PACRL_SP4_MASK (0x4000U)
3035#define AIPS_PACRL_SP4_SHIFT (14U)
3036/*! SP4 - Supervisor Protect
3037 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3038 * 0b1..This peripheral requires supervisor privilege level for accesses.
3039 */
3040#define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
3041#define AIPS_PACRL_TP3_MASK (0x10000U)
3042#define AIPS_PACRL_TP3_SHIFT (16U)
3043/*! TP3 - Trusted Protect
3044 * 0b0..Accesses from an untrusted master are allowed.
3045 * 0b1..Accesses from an untrusted master are not allowed.
3046 */
3047#define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
3048#define AIPS_PACRL_WP3_MASK (0x20000U)
3049#define AIPS_PACRL_WP3_SHIFT (17U)
3050/*! WP3 - Write Protect
3051 * 0b0..This peripheral allows write accesses.
3052 * 0b1..This peripheral is write protected.
3053 */
3054#define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
3055#define AIPS_PACRL_SP3_MASK (0x40000U)
3056#define AIPS_PACRL_SP3_SHIFT (18U)
3057/*! SP3 - Supervisor Protect
3058 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3059 * 0b1..This peripheral requires supervisor privilege level for accesses.
3060 */
3061#define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
3062#define AIPS_PACRL_TP2_MASK (0x100000U)
3063#define AIPS_PACRL_TP2_SHIFT (20U)
3064/*! TP2 - Trusted Protect
3065 * 0b0..Accesses from an untrusted master are allowed.
3066 * 0b1..Accesses from an untrusted master are not allowed.
3067 */
3068#define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
3069#define AIPS_PACRL_WP2_MASK (0x200000U)
3070#define AIPS_PACRL_WP2_SHIFT (21U)
3071/*! WP2 - Write Protect
3072 * 0b0..This peripheral allows write accesses.
3073 * 0b1..This peripheral is write protected.
3074 */
3075#define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
3076#define AIPS_PACRL_SP2_MASK (0x400000U)
3077#define AIPS_PACRL_SP2_SHIFT (22U)
3078/*! SP2 - Supervisor Protect
3079 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3080 * 0b1..This peripheral requires supervisor privilege level for accesses.
3081 */
3082#define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
3083#define AIPS_PACRL_TP1_MASK (0x1000000U)
3084#define AIPS_PACRL_TP1_SHIFT (24U)
3085/*! TP1 - Trusted Protect
3086 * 0b0..Accesses from an untrusted master are allowed.
3087 * 0b1..Accesses from an untrusted master are not allowed.
3088 */
3089#define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
3090#define AIPS_PACRL_WP1_MASK (0x2000000U)
3091#define AIPS_PACRL_WP1_SHIFT (25U)
3092/*! WP1 - Write Protect
3093 * 0b0..This peripheral allows write accesses.
3094 * 0b1..This peripheral is write protected.
3095 */
3096#define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
3097#define AIPS_PACRL_SP1_MASK (0x4000000U)
3098#define AIPS_PACRL_SP1_SHIFT (26U)
3099/*! SP1 - Supervisor Protect
3100 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3101 * 0b1..This peripheral requires supervisor privilege level for accesses.
3102 */
3103#define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
3104#define AIPS_PACRL_TP0_MASK (0x10000000U)
3105#define AIPS_PACRL_TP0_SHIFT (28U)
3106/*! TP0 - Trusted Protect
3107 * 0b0..Accesses from an untrusted master are allowed.
3108 * 0b1..Accesses from an untrusted master are not allowed.
3109 */
3110#define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
3111#define AIPS_PACRL_WP0_MASK (0x20000000U)
3112#define AIPS_PACRL_WP0_SHIFT (29U)
3113/*! WP0 - Write Protect
3114 * 0b0..This peripheral allows write accesses.
3115 * 0b1..This peripheral is write protected.
3116 */
3117#define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
3118#define AIPS_PACRL_SP0_MASK (0x40000000U)
3119#define AIPS_PACRL_SP0_SHIFT (30U)
3120/*! SP0 - Supervisor Protect
3121 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3122 * 0b1..This peripheral requires supervisor privilege level for accesses.
3123 */
3124#define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
3125/*! @} */
3126
3127/*! @name PACRM - Peripheral Access Control Register */
3128/*! @{ */
3129#define AIPS_PACRM_TP7_MASK (0x1U)
3130#define AIPS_PACRM_TP7_SHIFT (0U)
3131/*! TP7 - Trusted Protect
3132 * 0b0..Accesses from an untrusted master are allowed.
3133 * 0b1..Accesses from an untrusted master are not allowed.
3134 */
3135#define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
3136#define AIPS_PACRM_WP7_MASK (0x2U)
3137#define AIPS_PACRM_WP7_SHIFT (1U)
3138/*! WP7 - Write Protect
3139 * 0b0..This peripheral allows write accesses.
3140 * 0b1..This peripheral is write protected.
3141 */
3142#define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
3143#define AIPS_PACRM_SP7_MASK (0x4U)
3144#define AIPS_PACRM_SP7_SHIFT (2U)
3145/*! SP7 - Supervisor Protect
3146 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3147 * 0b1..This peripheral requires supervisor privilege level for accesses.
3148 */
3149#define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
3150#define AIPS_PACRM_TP6_MASK (0x10U)
3151#define AIPS_PACRM_TP6_SHIFT (4U)
3152/*! TP6 - Trusted Protect
3153 * 0b0..Accesses from an untrusted master are allowed.
3154 * 0b1..Accesses from an untrusted master are not allowed.
3155 */
3156#define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
3157#define AIPS_PACRM_WP6_MASK (0x20U)
3158#define AIPS_PACRM_WP6_SHIFT (5U)
3159/*! WP6 - Write Protect
3160 * 0b0..This peripheral allows write accesses.
3161 * 0b1..This peripheral is write protected.
3162 */
3163#define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
3164#define AIPS_PACRM_SP6_MASK (0x40U)
3165#define AIPS_PACRM_SP6_SHIFT (6U)
3166/*! SP6 - Supervisor Protect
3167 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3168 * 0b1..This peripheral requires supervisor privilege level for accesses.
3169 */
3170#define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
3171#define AIPS_PACRM_TP5_MASK (0x100U)
3172#define AIPS_PACRM_TP5_SHIFT (8U)
3173/*! TP5 - Trusted Protect
3174 * 0b0..Accesses from an untrusted master are allowed.
3175 * 0b1..Accesses from an untrusted master are not allowed.
3176 */
3177#define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
3178#define AIPS_PACRM_WP5_MASK (0x200U)
3179#define AIPS_PACRM_WP5_SHIFT (9U)
3180/*! WP5 - Write Protect
3181 * 0b0..This peripheral allows write accesses.
3182 * 0b1..This peripheral is write protected.
3183 */
3184#define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
3185#define AIPS_PACRM_SP5_MASK (0x400U)
3186#define AIPS_PACRM_SP5_SHIFT (10U)
3187/*! SP5 - Supervisor Protect
3188 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3189 * 0b1..This peripheral requires supervisor privilege level for accesses.
3190 */
3191#define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
3192#define AIPS_PACRM_TP4_MASK (0x1000U)
3193#define AIPS_PACRM_TP4_SHIFT (12U)
3194/*! TP4 - Trusted Protect
3195 * 0b0..Accesses from an untrusted master are allowed.
3196 * 0b1..Accesses from an untrusted master are not allowed.
3197 */
3198#define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
3199#define AIPS_PACRM_WP4_MASK (0x2000U)
3200#define AIPS_PACRM_WP4_SHIFT (13U)
3201/*! WP4 - Write Protect
3202 * 0b0..This peripheral allows write accesses.
3203 * 0b1..This peripheral is write protected.
3204 */
3205#define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
3206#define AIPS_PACRM_SP4_MASK (0x4000U)
3207#define AIPS_PACRM_SP4_SHIFT (14U)
3208/*! SP4 - Supervisor Protect
3209 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3210 * 0b1..This peripheral requires supervisor privilege level for accesses.
3211 */
3212#define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
3213#define AIPS_PACRM_TP3_MASK (0x10000U)
3214#define AIPS_PACRM_TP3_SHIFT (16U)
3215/*! TP3 - Trusted Protect
3216 * 0b0..Accesses from an untrusted master are allowed.
3217 * 0b1..Accesses from an untrusted master are not allowed.
3218 */
3219#define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
3220#define AIPS_PACRM_WP3_MASK (0x20000U)
3221#define AIPS_PACRM_WP3_SHIFT (17U)
3222/*! WP3 - Write Protect
3223 * 0b0..This peripheral allows write accesses.
3224 * 0b1..This peripheral is write protected.
3225 */
3226#define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
3227#define AIPS_PACRM_SP3_MASK (0x40000U)
3228#define AIPS_PACRM_SP3_SHIFT (18U)
3229/*! SP3 - Supervisor Protect
3230 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3231 * 0b1..This peripheral requires supervisor privilege level for accesses.
3232 */
3233#define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
3234#define AIPS_PACRM_TP2_MASK (0x100000U)
3235#define AIPS_PACRM_TP2_SHIFT (20U)
3236/*! TP2 - Trusted Protect
3237 * 0b0..Accesses from an untrusted master are allowed.
3238 * 0b1..Accesses from an untrusted master are not allowed.
3239 */
3240#define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
3241#define AIPS_PACRM_WP2_MASK (0x200000U)
3242#define AIPS_PACRM_WP2_SHIFT (21U)
3243/*! WP2 - Write Protect
3244 * 0b0..This peripheral allows write accesses.
3245 * 0b1..This peripheral is write protected.
3246 */
3247#define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
3248#define AIPS_PACRM_SP2_MASK (0x400000U)
3249#define AIPS_PACRM_SP2_SHIFT (22U)
3250/*! SP2 - Supervisor Protect
3251 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3252 * 0b1..This peripheral requires supervisor privilege level for accesses.
3253 */
3254#define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
3255#define AIPS_PACRM_TP1_MASK (0x1000000U)
3256#define AIPS_PACRM_TP1_SHIFT (24U)
3257/*! TP1 - Trusted Protect
3258 * 0b0..Accesses from an untrusted master are allowed.
3259 * 0b1..Accesses from an untrusted master are not allowed.
3260 */
3261#define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
3262#define AIPS_PACRM_WP1_MASK (0x2000000U)
3263#define AIPS_PACRM_WP1_SHIFT (25U)
3264/*! WP1 - Write Protect
3265 * 0b0..This peripheral allows write accesses.
3266 * 0b1..This peripheral is write protected.
3267 */
3268#define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
3269#define AIPS_PACRM_SP1_MASK (0x4000000U)
3270#define AIPS_PACRM_SP1_SHIFT (26U)
3271/*! SP1 - Supervisor Protect
3272 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3273 * 0b1..This peripheral requires supervisor privilege level for accesses.
3274 */
3275#define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
3276#define AIPS_PACRM_TP0_MASK (0x10000000U)
3277#define AIPS_PACRM_TP0_SHIFT (28U)
3278/*! TP0 - Trusted Protect
3279 * 0b0..Accesses from an untrusted master are allowed.
3280 * 0b1..Accesses from an untrusted master are not allowed.
3281 */
3282#define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
3283#define AIPS_PACRM_WP0_MASK (0x20000000U)
3284#define AIPS_PACRM_WP0_SHIFT (29U)
3285/*! WP0 - Write Protect
3286 * 0b0..This peripheral allows write accesses.
3287 * 0b1..This peripheral is write protected.
3288 */
3289#define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
3290#define AIPS_PACRM_SP0_MASK (0x40000000U)
3291#define AIPS_PACRM_SP0_SHIFT (30U)
3292/*! SP0 - Supervisor Protect
3293 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3294 * 0b1..This peripheral requires supervisor privilege level for accesses.
3295 */
3296#define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
3297/*! @} */
3298
3299/*! @name PACRN - Peripheral Access Control Register */
3300/*! @{ */
3301#define AIPS_PACRN_TP7_MASK (0x1U)
3302#define AIPS_PACRN_TP7_SHIFT (0U)
3303/*! TP7 - Trusted Protect
3304 * 0b0..Accesses from an untrusted master are allowed.
3305 * 0b1..Accesses from an untrusted master are not allowed.
3306 */
3307#define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
3308#define AIPS_PACRN_WP7_MASK (0x2U)
3309#define AIPS_PACRN_WP7_SHIFT (1U)
3310/*! WP7 - Write Protect
3311 * 0b0..This peripheral allows write accesses.
3312 * 0b1..This peripheral is write protected.
3313 */
3314#define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
3315#define AIPS_PACRN_SP7_MASK (0x4U)
3316#define AIPS_PACRN_SP7_SHIFT (2U)
3317/*! SP7 - Supervisor Protect
3318 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3319 * 0b1..This peripheral requires supervisor privilege level for accesses.
3320 */
3321#define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
3322#define AIPS_PACRN_TP6_MASK (0x10U)
3323#define AIPS_PACRN_TP6_SHIFT (4U)
3324/*! TP6 - Trusted Protect
3325 * 0b0..Accesses from an untrusted master are allowed.
3326 * 0b1..Accesses from an untrusted master are not allowed.
3327 */
3328#define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
3329#define AIPS_PACRN_WP6_MASK (0x20U)
3330#define AIPS_PACRN_WP6_SHIFT (5U)
3331/*! WP6 - Write Protect
3332 * 0b0..This peripheral allows write accesses.
3333 * 0b1..This peripheral is write protected.
3334 */
3335#define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
3336#define AIPS_PACRN_SP6_MASK (0x40U)
3337#define AIPS_PACRN_SP6_SHIFT (6U)
3338/*! SP6 - Supervisor Protect
3339 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3340 * 0b1..This peripheral requires supervisor privilege level for accesses.
3341 */
3342#define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
3343#define AIPS_PACRN_TP5_MASK (0x100U)
3344#define AIPS_PACRN_TP5_SHIFT (8U)
3345/*! TP5 - Trusted Protect
3346 * 0b0..Accesses from an untrusted master are allowed.
3347 * 0b1..Accesses from an untrusted master are not allowed.
3348 */
3349#define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
3350#define AIPS_PACRN_WP5_MASK (0x200U)
3351#define AIPS_PACRN_WP5_SHIFT (9U)
3352/*! WP5 - Write Protect
3353 * 0b0..This peripheral allows write accesses.
3354 * 0b1..This peripheral is write protected.
3355 */
3356#define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
3357#define AIPS_PACRN_SP5_MASK (0x400U)
3358#define AIPS_PACRN_SP5_SHIFT (10U)
3359/*! SP5 - Supervisor Protect
3360 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3361 * 0b1..This peripheral requires supervisor privilege level for accesses.
3362 */
3363#define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
3364#define AIPS_PACRN_TP4_MASK (0x1000U)
3365#define AIPS_PACRN_TP4_SHIFT (12U)
3366/*! TP4 - Trusted Protect
3367 * 0b0..Accesses from an untrusted master are allowed.
3368 * 0b1..Accesses from an untrusted master are not allowed.
3369 */
3370#define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
3371#define AIPS_PACRN_WP4_MASK (0x2000U)
3372#define AIPS_PACRN_WP4_SHIFT (13U)
3373/*! WP4 - Write Protect
3374 * 0b0..This peripheral allows write accesses.
3375 * 0b1..This peripheral is write protected.
3376 */
3377#define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
3378#define AIPS_PACRN_SP4_MASK (0x4000U)
3379#define AIPS_PACRN_SP4_SHIFT (14U)
3380/*! SP4 - Supervisor Protect
3381 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3382 * 0b1..This peripheral requires supervisor privilege level for accesses.
3383 */
3384#define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
3385#define AIPS_PACRN_TP3_MASK (0x10000U)
3386#define AIPS_PACRN_TP3_SHIFT (16U)
3387/*! TP3 - Trusted Protect
3388 * 0b0..Accesses from an untrusted master are allowed.
3389 * 0b1..Accesses from an untrusted master are not allowed.
3390 */
3391#define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
3392#define AIPS_PACRN_WP3_MASK (0x20000U)
3393#define AIPS_PACRN_WP3_SHIFT (17U)
3394/*! WP3 - Write Protect
3395 * 0b0..This peripheral allows write accesses.
3396 * 0b1..This peripheral is write protected.
3397 */
3398#define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
3399#define AIPS_PACRN_SP3_MASK (0x40000U)
3400#define AIPS_PACRN_SP3_SHIFT (18U)
3401/*! SP3 - Supervisor Protect
3402 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3403 * 0b1..This peripheral requires supervisor privilege level for accesses.
3404 */
3405#define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
3406#define AIPS_PACRN_TP2_MASK (0x100000U)
3407#define AIPS_PACRN_TP2_SHIFT (20U)
3408/*! TP2 - Trusted Protect
3409 * 0b0..Accesses from an untrusted master are allowed.
3410 * 0b1..Accesses from an untrusted master are not allowed.
3411 */
3412#define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
3413#define AIPS_PACRN_WP2_MASK (0x200000U)
3414#define AIPS_PACRN_WP2_SHIFT (21U)
3415/*! WP2 - Write Protect
3416 * 0b0..This peripheral allows write accesses.
3417 * 0b1..This peripheral is write protected.
3418 */
3419#define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
3420#define AIPS_PACRN_SP2_MASK (0x400000U)
3421#define AIPS_PACRN_SP2_SHIFT (22U)
3422/*! SP2 - Supervisor Protect
3423 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3424 * 0b1..This peripheral requires supervisor privilege level for accesses.
3425 */
3426#define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
3427#define AIPS_PACRN_TP1_MASK (0x1000000U)
3428#define AIPS_PACRN_TP1_SHIFT (24U)
3429/*! TP1 - Trusted Protect
3430 * 0b0..Accesses from an untrusted master are allowed.
3431 * 0b1..Accesses from an untrusted master are not allowed.
3432 */
3433#define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
3434#define AIPS_PACRN_WP1_MASK (0x2000000U)
3435#define AIPS_PACRN_WP1_SHIFT (25U)
3436/*! WP1 - Write Protect
3437 * 0b0..This peripheral allows write accesses.
3438 * 0b1..This peripheral is write protected.
3439 */
3440#define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
3441#define AIPS_PACRN_SP1_MASK (0x4000000U)
3442#define AIPS_PACRN_SP1_SHIFT (26U)
3443/*! SP1 - Supervisor Protect
3444 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3445 * 0b1..This peripheral requires supervisor privilege level for accesses.
3446 */
3447#define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
3448#define AIPS_PACRN_TP0_MASK (0x10000000U)
3449#define AIPS_PACRN_TP0_SHIFT (28U)
3450/*! TP0 - Trusted Protect
3451 * 0b0..Accesses from an untrusted master are allowed.
3452 * 0b1..Accesses from an untrusted master are not allowed.
3453 */
3454#define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
3455#define AIPS_PACRN_WP0_MASK (0x20000000U)
3456#define AIPS_PACRN_WP0_SHIFT (29U)
3457/*! WP0 - Write Protect
3458 * 0b0..This peripheral allows write accesses.
3459 * 0b1..This peripheral is write protected.
3460 */
3461#define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
3462#define AIPS_PACRN_SP0_MASK (0x40000000U)
3463#define AIPS_PACRN_SP0_SHIFT (30U)
3464/*! SP0 - Supervisor Protect
3465 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3466 * 0b1..This peripheral requires supervisor privilege level for accesses.
3467 */
3468#define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
3469/*! @} */
3470
3471/*! @name PACRO - Peripheral Access Control Register */
3472/*! @{ */
3473#define AIPS_PACRO_TP7_MASK (0x1U)
3474#define AIPS_PACRO_TP7_SHIFT (0U)
3475/*! TP7 - Trusted Protect
3476 * 0b0..Accesses from an untrusted master are allowed.
3477 * 0b1..Accesses from an untrusted master are not allowed.
3478 */
3479#define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
3480#define AIPS_PACRO_WP7_MASK (0x2U)
3481#define AIPS_PACRO_WP7_SHIFT (1U)
3482/*! WP7 - Write Protect
3483 * 0b0..This peripheral allows write accesses.
3484 * 0b1..This peripheral is write protected.
3485 */
3486#define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
3487#define AIPS_PACRO_SP7_MASK (0x4U)
3488#define AIPS_PACRO_SP7_SHIFT (2U)
3489/*! SP7 - Supervisor Protect
3490 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3491 * 0b1..This peripheral requires supervisor privilege level for accesses.
3492 */
3493#define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
3494#define AIPS_PACRO_TP6_MASK (0x10U)
3495#define AIPS_PACRO_TP6_SHIFT (4U)
3496/*! TP6 - Trusted Protect
3497 * 0b0..Accesses from an untrusted master are allowed.
3498 * 0b1..Accesses from an untrusted master are not allowed.
3499 */
3500#define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
3501#define AIPS_PACRO_WP6_MASK (0x20U)
3502#define AIPS_PACRO_WP6_SHIFT (5U)
3503/*! WP6 - Write Protect
3504 * 0b0..This peripheral allows write accesses.
3505 * 0b1..This peripheral is write protected.
3506 */
3507#define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
3508#define AIPS_PACRO_SP6_MASK (0x40U)
3509#define AIPS_PACRO_SP6_SHIFT (6U)
3510/*! SP6 - Supervisor Protect
3511 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3512 * 0b1..This peripheral requires supervisor privilege level for accesses.
3513 */
3514#define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
3515#define AIPS_PACRO_TP5_MASK (0x100U)
3516#define AIPS_PACRO_TP5_SHIFT (8U)
3517/*! TP5 - Trusted Protect
3518 * 0b0..Accesses from an untrusted master are allowed.
3519 * 0b1..Accesses from an untrusted master are not allowed.
3520 */
3521#define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
3522#define AIPS_PACRO_WP5_MASK (0x200U)
3523#define AIPS_PACRO_WP5_SHIFT (9U)
3524/*! WP5 - Write Protect
3525 * 0b0..This peripheral allows write accesses.
3526 * 0b1..This peripheral is write protected.
3527 */
3528#define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
3529#define AIPS_PACRO_SP5_MASK (0x400U)
3530#define AIPS_PACRO_SP5_SHIFT (10U)
3531/*! SP5 - Supervisor Protect
3532 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3533 * 0b1..This peripheral requires supervisor privilege level for accesses.
3534 */
3535#define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
3536#define AIPS_PACRO_TP4_MASK (0x1000U)
3537#define AIPS_PACRO_TP4_SHIFT (12U)
3538/*! TP4 - Trusted Protect
3539 * 0b0..Accesses from an untrusted master are allowed.
3540 * 0b1..Accesses from an untrusted master are not allowed.
3541 */
3542#define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
3543#define AIPS_PACRO_WP4_MASK (0x2000U)
3544#define AIPS_PACRO_WP4_SHIFT (13U)
3545/*! WP4 - Write Protect
3546 * 0b0..This peripheral allows write accesses.
3547 * 0b1..This peripheral is write protected.
3548 */
3549#define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
3550#define AIPS_PACRO_SP4_MASK (0x4000U)
3551#define AIPS_PACRO_SP4_SHIFT (14U)
3552/*! SP4 - Supervisor Protect
3553 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3554 * 0b1..This peripheral requires supervisor privilege level for accesses.
3555 */
3556#define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
3557#define AIPS_PACRO_TP3_MASK (0x10000U)
3558#define AIPS_PACRO_TP3_SHIFT (16U)
3559/*! TP3 - Trusted Protect
3560 * 0b0..Accesses from an untrusted master are allowed.
3561 * 0b1..Accesses from an untrusted master are not allowed.
3562 */
3563#define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
3564#define AIPS_PACRO_WP3_MASK (0x20000U)
3565#define AIPS_PACRO_WP3_SHIFT (17U)
3566/*! WP3 - Write Protect
3567 * 0b0..This peripheral allows write accesses.
3568 * 0b1..This peripheral is write protected.
3569 */
3570#define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
3571#define AIPS_PACRO_SP3_MASK (0x40000U)
3572#define AIPS_PACRO_SP3_SHIFT (18U)
3573/*! SP3 - Supervisor Protect
3574 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3575 * 0b1..This peripheral requires supervisor privilege level for accesses.
3576 */
3577#define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
3578#define AIPS_PACRO_TP2_MASK (0x100000U)
3579#define AIPS_PACRO_TP2_SHIFT (20U)
3580/*! TP2 - Trusted Protect
3581 * 0b0..Accesses from an untrusted master are allowed.
3582 * 0b1..Accesses from an untrusted master are not allowed.
3583 */
3584#define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
3585#define AIPS_PACRO_WP2_MASK (0x200000U)
3586#define AIPS_PACRO_WP2_SHIFT (21U)
3587/*! WP2 - Write Protect
3588 * 0b0..This peripheral allows write accesses.
3589 * 0b1..This peripheral is write protected.
3590 */
3591#define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
3592#define AIPS_PACRO_SP2_MASK (0x400000U)
3593#define AIPS_PACRO_SP2_SHIFT (22U)
3594/*! SP2 - Supervisor Protect
3595 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3596 * 0b1..This peripheral requires supervisor privilege level for accesses.
3597 */
3598#define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
3599#define AIPS_PACRO_TP1_MASK (0x1000000U)
3600#define AIPS_PACRO_TP1_SHIFT (24U)
3601/*! TP1 - Trusted Protect
3602 * 0b0..Accesses from an untrusted master are allowed.
3603 * 0b1..Accesses from an untrusted master are not allowed.
3604 */
3605#define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
3606#define AIPS_PACRO_WP1_MASK (0x2000000U)
3607#define AIPS_PACRO_WP1_SHIFT (25U)
3608/*! WP1 - Write Protect
3609 * 0b0..This peripheral allows write accesses.
3610 * 0b1..This peripheral is write protected.
3611 */
3612#define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
3613#define AIPS_PACRO_SP1_MASK (0x4000000U)
3614#define AIPS_PACRO_SP1_SHIFT (26U)
3615/*! SP1 - Supervisor Protect
3616 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3617 * 0b1..This peripheral requires supervisor privilege level for accesses.
3618 */
3619#define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
3620#define AIPS_PACRO_TP0_MASK (0x10000000U)
3621#define AIPS_PACRO_TP0_SHIFT (28U)
3622/*! TP0 - Trusted Protect
3623 * 0b0..Accesses from an untrusted master are allowed.
3624 * 0b1..Accesses from an untrusted master are not allowed.
3625 */
3626#define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
3627#define AIPS_PACRO_WP0_MASK (0x20000000U)
3628#define AIPS_PACRO_WP0_SHIFT (29U)
3629/*! WP0 - Write Protect
3630 * 0b0..This peripheral allows write accesses.
3631 * 0b1..This peripheral is write protected.
3632 */
3633#define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
3634#define AIPS_PACRO_SP0_MASK (0x40000000U)
3635#define AIPS_PACRO_SP0_SHIFT (30U)
3636/*! SP0 - Supervisor Protect
3637 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3638 * 0b1..This peripheral requires supervisor privilege level for accesses.
3639 */
3640#define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
3641/*! @} */
3642
3643/*! @name PACRP - Peripheral Access Control Register */
3644/*! @{ */
3645#define AIPS_PACRP_TP7_MASK (0x1U)
3646#define AIPS_PACRP_TP7_SHIFT (0U)
3647/*! TP7 - Trusted Protect
3648 * 0b0..Accesses from an untrusted master are allowed.
3649 * 0b1..Accesses from an untrusted master are not allowed.
3650 */
3651#define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
3652#define AIPS_PACRP_WP7_MASK (0x2U)
3653#define AIPS_PACRP_WP7_SHIFT (1U)
3654/*! WP7 - Write Protect
3655 * 0b0..This peripheral allows write accesses.
3656 * 0b1..This peripheral is write protected.
3657 */
3658#define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
3659#define AIPS_PACRP_SP7_MASK (0x4U)
3660#define AIPS_PACRP_SP7_SHIFT (2U)
3661/*! SP7 - Supervisor Protect
3662 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3663 * 0b1..This peripheral requires supervisor privilege level for accesses.
3664 */
3665#define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
3666#define AIPS_PACRP_TP6_MASK (0x10U)
3667#define AIPS_PACRP_TP6_SHIFT (4U)
3668/*! TP6 - Trusted Protect
3669 * 0b0..Accesses from an untrusted master are allowed.
3670 * 0b1..Accesses from an untrusted master are not allowed.
3671 */
3672#define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
3673#define AIPS_PACRP_WP6_MASK (0x20U)
3674#define AIPS_PACRP_WP6_SHIFT (5U)
3675/*! WP6 - Write Protect
3676 * 0b0..This peripheral allows write accesses.
3677 * 0b1..This peripheral is write protected.
3678 */
3679#define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
3680#define AIPS_PACRP_SP6_MASK (0x40U)
3681#define AIPS_PACRP_SP6_SHIFT (6U)
3682/*! SP6 - Supervisor Protect
3683 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3684 * 0b1..This peripheral requires supervisor privilege level for accesses.
3685 */
3686#define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
3687#define AIPS_PACRP_TP5_MASK (0x100U)
3688#define AIPS_PACRP_TP5_SHIFT (8U)
3689/*! TP5 - Trusted Protect
3690 * 0b0..Accesses from an untrusted master are allowed.
3691 * 0b1..Accesses from an untrusted master are not allowed.
3692 */
3693#define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
3694#define AIPS_PACRP_WP5_MASK (0x200U)
3695#define AIPS_PACRP_WP5_SHIFT (9U)
3696/*! WP5 - Write Protect
3697 * 0b0..This peripheral allows write accesses.
3698 * 0b1..This peripheral is write protected.
3699 */
3700#define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
3701#define AIPS_PACRP_SP5_MASK (0x400U)
3702#define AIPS_PACRP_SP5_SHIFT (10U)
3703/*! SP5 - Supervisor Protect
3704 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3705 * 0b1..This peripheral requires supervisor privilege level for accesses.
3706 */
3707#define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
3708#define AIPS_PACRP_TP4_MASK (0x1000U)
3709#define AIPS_PACRP_TP4_SHIFT (12U)
3710/*! TP4 - Trusted Protect
3711 * 0b0..Accesses from an untrusted master are allowed.
3712 * 0b1..Accesses from an untrusted master are not allowed.
3713 */
3714#define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
3715#define AIPS_PACRP_WP4_MASK (0x2000U)
3716#define AIPS_PACRP_WP4_SHIFT (13U)
3717/*! WP4 - Write Protect
3718 * 0b0..This peripheral allows write accesses.
3719 * 0b1..This peripheral is write protected.
3720 */
3721#define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
3722#define AIPS_PACRP_SP4_MASK (0x4000U)
3723#define AIPS_PACRP_SP4_SHIFT (14U)
3724/*! SP4 - Supervisor Protect
3725 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3726 * 0b1..This peripheral requires supervisor privilege level for accesses.
3727 */
3728#define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
3729#define AIPS_PACRP_TP3_MASK (0x10000U)
3730#define AIPS_PACRP_TP3_SHIFT (16U)
3731/*! TP3 - Trusted Protect
3732 * 0b0..Accesses from an untrusted master are allowed.
3733 * 0b1..Accesses from an untrusted master are not allowed.
3734 */
3735#define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
3736#define AIPS_PACRP_WP3_MASK (0x20000U)
3737#define AIPS_PACRP_WP3_SHIFT (17U)
3738/*! WP3 - Write Protect
3739 * 0b0..This peripheral allows write accesses.
3740 * 0b1..This peripheral is write protected.
3741 */
3742#define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
3743#define AIPS_PACRP_SP3_MASK (0x40000U)
3744#define AIPS_PACRP_SP3_SHIFT (18U)
3745/*! SP3 - Supervisor Protect
3746 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3747 * 0b1..This peripheral requires supervisor privilege level for accesses.
3748 */
3749#define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
3750#define AIPS_PACRP_TP2_MASK (0x100000U)
3751#define AIPS_PACRP_TP2_SHIFT (20U)
3752/*! TP2 - Trusted Protect
3753 * 0b0..Accesses from an untrusted master are allowed.
3754 * 0b1..Accesses from an untrusted master are not allowed.
3755 */
3756#define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
3757#define AIPS_PACRP_WP2_MASK (0x200000U)
3758#define AIPS_PACRP_WP2_SHIFT (21U)
3759/*! WP2 - Write Protect
3760 * 0b0..This peripheral allows write accesses.
3761 * 0b1..This peripheral is write protected.
3762 */
3763#define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
3764#define AIPS_PACRP_SP2_MASK (0x400000U)
3765#define AIPS_PACRP_SP2_SHIFT (22U)
3766/*! SP2 - Supervisor Protect
3767 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3768 * 0b1..This peripheral requires supervisor privilege level for accesses.
3769 */
3770#define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
3771#define AIPS_PACRP_TP1_MASK (0x1000000U)
3772#define AIPS_PACRP_TP1_SHIFT (24U)
3773/*! TP1 - Trusted Protect
3774 * 0b0..Accesses from an untrusted master are allowed.
3775 * 0b1..Accesses from an untrusted master are not allowed.
3776 */
3777#define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
3778#define AIPS_PACRP_WP1_MASK (0x2000000U)
3779#define AIPS_PACRP_WP1_SHIFT (25U)
3780/*! WP1 - Write Protect
3781 * 0b0..This peripheral allows write accesses.
3782 * 0b1..This peripheral is write protected.
3783 */
3784#define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
3785#define AIPS_PACRP_SP1_MASK (0x4000000U)
3786#define AIPS_PACRP_SP1_SHIFT (26U)
3787/*! SP1 - Supervisor Protect
3788 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3789 * 0b1..This peripheral requires supervisor privilege level for accesses.
3790 */
3791#define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
3792#define AIPS_PACRP_TP0_MASK (0x10000000U)
3793#define AIPS_PACRP_TP0_SHIFT (28U)
3794/*! TP0 - Trusted Protect
3795 * 0b0..Accesses from an untrusted master are allowed.
3796 * 0b1..Accesses from an untrusted master are not allowed.
3797 */
3798#define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
3799#define AIPS_PACRP_WP0_MASK (0x20000000U)
3800#define AIPS_PACRP_WP0_SHIFT (29U)
3801/*! WP0 - Write Protect
3802 * 0b0..This peripheral allows write accesses.
3803 * 0b1..This peripheral is write protected.
3804 */
3805#define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
3806#define AIPS_PACRP_SP0_MASK (0x40000000U)
3807#define AIPS_PACRP_SP0_SHIFT (30U)
3808/*! SP0 - Supervisor Protect
3809 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3810 * 0b1..This peripheral requires supervisor privilege level for accesses.
3811 */
3812#define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
3813/*! @} */
3814
3815
3816/*!
3817 * @}
3818 */ /* end of group AIPS_Register_Masks */
3819
3820
3821/* AIPS - Peripheral instance base addresses */
3822/** Peripheral AIPS0 base address */
3823#define AIPS0_BASE (0x40000000u)
3824/** Peripheral AIPS0 base pointer */
3825#define AIPS0 ((AIPS_Type *)AIPS0_BASE)
3826/** Peripheral AIPS1 base address */
3827#define AIPS1_BASE (0x40080000u)
3828/** Peripheral AIPS1 base pointer */
3829#define AIPS1 ((AIPS_Type *)AIPS1_BASE)
3830/** Array initializer of AIPS peripheral base addresses */
3831#define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
3832/** Array initializer of AIPS peripheral base pointers */
3833#define AIPS_BASE_PTRS { AIPS0, AIPS1 }
3834
3835/*!
3836 * @}
3837 */ /* end of group AIPS_Peripheral_Access_Layer */
3838
3839
3840/* ----------------------------------------------------------------------------
3841 -- AXBS Peripheral Access Layer
3842 ---------------------------------------------------------------------------- */
3843
3844/*!
3845 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
3846 * @{
3847 */
3848
3849/** AXBS - Register Layout Typedef */
3850typedef struct {
3851 struct { /* offset: 0x0, array step: 0x100 */
3852 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
3853 uint8_t RESERVED_0[12];
3854 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
3855 uint8_t RESERVED_1[236];
3856 } SLAVE[8];
3857 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
3858 uint8_t RESERVED_0[252];
3859 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
3860 uint8_t RESERVED_1[252];
3861 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
3862 uint8_t RESERVED_2[252];
3863 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
3864 uint8_t RESERVED_3[252];
3865 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
3866 uint8_t RESERVED_4[252];
3867 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
3868 uint8_t RESERVED_5[252];
3869 __IO uint32_t MGPCR6; /**< Master General Purpose Control Register, offset: 0xE00 */
3870 uint8_t RESERVED_6[252];
3871 __IO uint32_t MGPCR7; /**< Master General Purpose Control Register, offset: 0xF00 */
3872} AXBS_Type;
3873
3874/* ----------------------------------------------------------------------------
3875 -- AXBS Register Masks
3876 ---------------------------------------------------------------------------- */
3877
3878/*!
3879 * @addtogroup AXBS_Register_Masks AXBS Register Masks
3880 * @{
3881 */
3882
3883/*! @name PRS - Priority Registers Slave */
3884/*! @{ */
3885#define AXBS_PRS_M0_MASK (0x7U)
3886#define AXBS_PRS_M0_SHIFT (0U)
3887/*! M0 - Master 0 Priority. Sets the arbitration priority for this port on the associated slave port.
3888 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3889 * 0b001..This master has level 2 priority when accessing the slave port.
3890 * 0b010..This master has level 3 priority when accessing the slave port.
3891 * 0b011..This master has level 4 priority when accessing the slave port.
3892 * 0b100..This master has level 5 priority when accessing the slave port.
3893 * 0b101..This master has level 6 priority when accessing the slave port.
3894 * 0b110..This master has level 7 priority when accessing the slave port.
3895 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3896 */
3897#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
3898#define AXBS_PRS_M1_MASK (0x70U)
3899#define AXBS_PRS_M1_SHIFT (4U)
3900/*! M1 - Master 1 Priority. Sets the arbitration priority for this port on the associated slave port.
3901 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3902 * 0b001..This master has level 2 priority when accessing the slave port.
3903 * 0b010..This master has level 3 priority when accessing the slave port.
3904 * 0b011..This master has level 4 priority when accessing the slave port.
3905 * 0b100..This master has level 5 priority when accessing the slave port.
3906 * 0b101..This master has level 6 priority when accessing the slave port.
3907 * 0b110..This master has level 7 priority when accessing the slave port.
3908 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3909 */
3910#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
3911#define AXBS_PRS_M2_MASK (0x700U)
3912#define AXBS_PRS_M2_SHIFT (8U)
3913/*! M2 - Master 2 Priority. Sets the arbitration priority for this port on the associated slave port.
3914 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3915 * 0b001..This master has level 2 priority when accessing the slave port.
3916 * 0b010..This master has level 3 priority when accessing the slave port.
3917 * 0b011..This master has level 4 priority when accessing the slave port.
3918 * 0b100..This master has level 5 priority when accessing the slave port.
3919 * 0b101..This master has level 6 priority when accessing the slave port.
3920 * 0b110..This master has level 7 priority when accessing the slave port.
3921 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3922 */
3923#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
3924#define AXBS_PRS_M3_MASK (0x7000U)
3925#define AXBS_PRS_M3_SHIFT (12U)
3926/*! M3 - Master 3 Priority. Sets the arbitration priority for this port on the associated slave port.
3927 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3928 * 0b001..This master has level 2 priority when accessing the slave port.
3929 * 0b010..This master has level 3 priority when accessing the slave port.
3930 * 0b011..This master has level 4 priority when accessing the slave port.
3931 * 0b100..This master has level 5 priority when accessing the slave port.
3932 * 0b101..This master has level 6 priority when accessing the slave port.
3933 * 0b110..This master has level 7 priority when accessing the slave port.
3934 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3935 */
3936#define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
3937#define AXBS_PRS_M4_MASK (0x70000U)
3938#define AXBS_PRS_M4_SHIFT (16U)
3939/*! M4 - Master 4 Priority. Sets the arbitration priority for this port on the associated slave port.
3940 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3941 * 0b001..This master has level 2 priority when accessing the slave port.
3942 * 0b010..This master has level 3 priority when accessing the slave port.
3943 * 0b011..This master has level 4 priority when accessing the slave port.
3944 * 0b100..This master has level 5 priority when accessing the slave port.
3945 * 0b101..This master has level 6 priority when accessing the slave port.
3946 * 0b110..This master has level 7 priority when accessing the slave port.
3947 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3948 */
3949#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
3950#define AXBS_PRS_M5_MASK (0x700000U)
3951#define AXBS_PRS_M5_SHIFT (20U)
3952/*! M5 - Master 5 Priority. Sets the arbitration priority for this port on the associated slave port.
3953 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3954 * 0b001..This master has level 2 priority when accessing the slave port.
3955 * 0b010..This master has level 3 priority when accessing the slave port.
3956 * 0b011..This master has level 4 priority when accessing the slave port.
3957 * 0b100..This master has level 5 priority when accessing the slave port.
3958 * 0b101..This master has level 6 priority when accessing the slave port.
3959 * 0b110..This master has level 7 priority when accessing the slave port.
3960 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3961 */
3962#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
3963/*! @} */
3964
3965/* The count of AXBS_PRS */
3966#define AXBS_PRS_COUNT (8U)
3967
3968/*! @name CRS - Control Register */
3969/*! @{ */
3970#define AXBS_CRS_PARK_MASK (0x7U)
3971#define AXBS_CRS_PARK_SHIFT (0U)
3972/*! PARK - Park
3973 * 0b000..Park on master port M0
3974 * 0b001..Park on master port M1
3975 * 0b010..Park on master port M2
3976 * 0b011..Park on master port M3
3977 * 0b100..Park on master port M4
3978 * 0b101..Park on master port M5
3979 * 0b110..Park on master port M6
3980 * 0b111..Park on master port M7
3981 */
3982#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
3983#define AXBS_CRS_PCTL_MASK (0x30U)
3984#define AXBS_CRS_PCTL_SHIFT (4U)
3985/*! PCTL - Parking Control
3986 * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field
3987 * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port
3988 * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state
3989 * 0b11..Reserved
3990 */
3991#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
3992#define AXBS_CRS_ARB_MASK (0x300U)
3993#define AXBS_CRS_ARB_SHIFT (8U)
3994/*! ARB - Arbitration Mode
3995 * 0b00..Fixed priority
3996 * 0b01..Round-robin, or rotating, priority
3997 * 0b10..Reserved
3998 * 0b11..Reserved
3999 */
4000#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
4001#define AXBS_CRS_HLP_MASK (0x40000000U)
4002#define AXBS_CRS_HLP_SHIFT (30U)
4003/*! HLP - Halt Low Priority
4004 * 0b0..The low power mode request has the highest priority for arbitration on this slave port
4005 * 0b1..The low power mode request has the lowest initial priority for arbitration on this slave port
4006 */
4007#define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
4008#define AXBS_CRS_RO_MASK (0x80000000U)
4009#define AXBS_CRS_RO_SHIFT (31U)
4010/*! RO - Read Only
4011 * 0b0..The slave port's registers are writeable
4012 * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response.
4013 */
4014#define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
4015/*! @} */
4016
4017/* The count of AXBS_CRS */
4018#define AXBS_CRS_COUNT (8U)
4019
4020/*! @name MGPCR0 - Master General Purpose Control Register */
4021/*! @{ */
4022#define AXBS_MGPCR0_AULB_MASK (0x7U)
4023#define AXBS_MGPCR0_AULB_SHIFT (0U)
4024/*! AULB - Arbitrates On Undefined Length Bursts
4025 * 0b000..No arbitration is allowed during an undefined length burst
4026 * 0b001..Arbitration is allowed at any time during an undefined length burst
4027 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4028 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4029 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4030 * 0b101..Reserved
4031 * 0b110..Reserved
4032 * 0b111..Reserved
4033 */
4034#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
4035/*! @} */
4036
4037/*! @name MGPCR1 - Master General Purpose Control Register */
4038/*! @{ */
4039#define AXBS_MGPCR1_AULB_MASK (0x7U)
4040#define AXBS_MGPCR1_AULB_SHIFT (0U)
4041/*! AULB - Arbitrates On Undefined Length Bursts
4042 * 0b000..No arbitration is allowed during an undefined length burst
4043 * 0b001..Arbitration is allowed at any time during an undefined length burst
4044 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4045 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4046 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4047 * 0b101..Reserved
4048 * 0b110..Reserved
4049 * 0b111..Reserved
4050 */
4051#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
4052/*! @} */
4053
4054/*! @name MGPCR2 - Master General Purpose Control Register */
4055/*! @{ */
4056#define AXBS_MGPCR2_AULB_MASK (0x7U)
4057#define AXBS_MGPCR2_AULB_SHIFT (0U)
4058/*! AULB - Arbitrates On Undefined Length Bursts
4059 * 0b000..No arbitration is allowed during an undefined length burst
4060 * 0b001..Arbitration is allowed at any time during an undefined length burst
4061 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4062 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4063 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4064 * 0b101..Reserved
4065 * 0b110..Reserved
4066 * 0b111..Reserved
4067 */
4068#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
4069/*! @} */
4070
4071/*! @name MGPCR3 - Master General Purpose Control Register */
4072/*! @{ */
4073#define AXBS_MGPCR3_AULB_MASK (0x7U)
4074#define AXBS_MGPCR3_AULB_SHIFT (0U)
4075/*! AULB - Arbitrates On Undefined Length Bursts
4076 * 0b000..No arbitration is allowed during an undefined length burst
4077 * 0b001..Arbitration is allowed at any time during an undefined length burst
4078 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4079 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4080 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4081 * 0b101..Reserved
4082 * 0b110..Reserved
4083 * 0b111..Reserved
4084 */
4085#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
4086/*! @} */
4087
4088/*! @name MGPCR4 - Master General Purpose Control Register */
4089/*! @{ */
4090#define AXBS_MGPCR4_AULB_MASK (0x7U)
4091#define AXBS_MGPCR4_AULB_SHIFT (0U)
4092/*! AULB - Arbitrates On Undefined Length Bursts
4093 * 0b000..No arbitration is allowed during an undefined length burst
4094 * 0b001..Arbitration is allowed at any time during an undefined length burst
4095 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4096 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4097 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4098 * 0b101..Reserved
4099 * 0b110..Reserved
4100 * 0b111..Reserved
4101 */
4102#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
4103/*! @} */
4104
4105/*! @name MGPCR5 - Master General Purpose Control Register */
4106/*! @{ */
4107#define AXBS_MGPCR5_AULB_MASK (0x7U)
4108#define AXBS_MGPCR5_AULB_SHIFT (0U)
4109/*! AULB - Arbitrates On Undefined Length Bursts
4110 * 0b000..No arbitration is allowed during an undefined length burst
4111 * 0b001..Arbitration is allowed at any time during an undefined length burst
4112 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4113 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4114 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4115 * 0b101..Reserved
4116 * 0b110..Reserved
4117 * 0b111..Reserved
4118 */
4119#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
4120/*! @} */
4121
4122/*! @name MGPCR6 - Master General Purpose Control Register */
4123/*! @{ */
4124#define AXBS_MGPCR6_AULB_MASK (0x7U)
4125#define AXBS_MGPCR6_AULB_SHIFT (0U)
4126/*! AULB - Arbitrates On Undefined Length Bursts
4127 * 0b000..No arbitration is allowed during an undefined length burst
4128 * 0b001..Arbitration is allowed at any time during an undefined length burst
4129 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4130 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4131 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4132 * 0b101..Reserved
4133 * 0b110..Reserved
4134 * 0b111..Reserved
4135 */
4136#define AXBS_MGPCR6_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR6_AULB_SHIFT)) & AXBS_MGPCR6_AULB_MASK)
4137/*! @} */
4138
4139/*! @name MGPCR7 - Master General Purpose Control Register */
4140/*! @{ */
4141#define AXBS_MGPCR7_AULB_MASK (0x7U)
4142#define AXBS_MGPCR7_AULB_SHIFT (0U)
4143/*! AULB - Arbitrates On Undefined Length Bursts
4144 * 0b000..No arbitration is allowed during an undefined length burst
4145 * 0b001..Arbitration is allowed at any time during an undefined length burst
4146 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4147 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4148 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4149 * 0b101..Reserved
4150 * 0b110..Reserved
4151 * 0b111..Reserved
4152 */
4153#define AXBS_MGPCR7_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR7_AULB_SHIFT)) & AXBS_MGPCR7_AULB_MASK)
4154/*! @} */
4155
4156
4157/*!
4158 * @}
4159 */ /* end of group AXBS_Register_Masks */
4160
4161
4162/* AXBS - Peripheral instance base addresses */
4163/** Peripheral AXBS base address */
4164#define AXBS_BASE (0x40004000u)
4165/** Peripheral AXBS base pointer */
4166#define AXBS ((AXBS_Type *)AXBS_BASE)
4167/** Array initializer of AXBS peripheral base addresses */
4168#define AXBS_BASE_ADDRS { AXBS_BASE }
4169/** Array initializer of AXBS peripheral base pointers */
4170#define AXBS_BASE_PTRS { AXBS }
4171
4172/*!
4173 * @}
4174 */ /* end of group AXBS_Peripheral_Access_Layer */
4175
4176
4177/* ----------------------------------------------------------------------------
4178 -- CAU Peripheral Access Layer
4179 ---------------------------------------------------------------------------- */
4180
4181/*!
4182 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
4183 * @{
4184 */
4185
4186/** CAU - Register Layout Typedef */
4187typedef struct {
4188 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
4189 uint8_t RESERVED_0[2048];
4190 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
4191 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
4192 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
4193 uint8_t RESERVED_1[20];
4194 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
4195 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
4196 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
4197 uint8_t RESERVED_2[20];
4198 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
4199 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
4200 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
4201 uint8_t RESERVED_3[20];
4202 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
4203 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
4204 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
4205 uint8_t RESERVED_4[84];
4206 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
4207 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
4208 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
4209 uint8_t RESERVED_5[20];
4210 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
4211 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
4212 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
4213 uint8_t RESERVED_6[276];
4214 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
4215 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
4216 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
4217 uint8_t RESERVED_7[20];
4218 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
4219 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
4220 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
4221} CAU_Type;
4222
4223/* ----------------------------------------------------------------------------
4224 -- CAU Register Masks
4225 ---------------------------------------------------------------------------- */
4226
4227/*!
4228 * @addtogroup CAU_Register_Masks CAU Register Masks
4229 * @{
4230 */
4231
4232/*! @name DIRECT - Direct access register 0..Direct access register 15 */
4233/*! @{ */
4234#define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
4235#define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
4236#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
4237#define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
4238#define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
4239#define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
4240#define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
4241#define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
4242#define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
4243#define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
4244#define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
4245#define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
4246#define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
4247#define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
4248#define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
4249#define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
4250#define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
4251#define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
4252#define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
4253#define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
4254#define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
4255#define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
4256#define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
4257#define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
4258#define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
4259#define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
4260#define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
4261#define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
4262#define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
4263#define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
4264#define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
4265#define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
4266#define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
4267#define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
4268#define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
4269#define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
4270#define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
4271#define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
4272#define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
4273#define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
4274#define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
4275#define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
4276#define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
4277#define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
4278#define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
4279#define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
4280#define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
4281#define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
4282/*! @} */
4283
4284/* The count of CAU_DIRECT */
4285#define CAU_DIRECT_COUNT (16U)
4286
4287/*! @name LDR_CASR - Status register - Load Register command */
4288/*! @{ */
4289#define CAU_LDR_CASR_IC_MASK (0x1U)
4290#define CAU_LDR_CASR_IC_SHIFT (0U)
4291/*! IC
4292 * 0b0..No illegal commands issued
4293 * 0b1..Illegal command issued
4294 */
4295#define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
4296#define CAU_LDR_CASR_DPE_MASK (0x2U)
4297#define CAU_LDR_CASR_DPE_SHIFT (1U)
4298/*! DPE
4299 * 0b0..No error detected
4300 * 0b1..DES key parity error detected
4301 */
4302#define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
4303#define CAU_LDR_CASR_VER_MASK (0xF0000000U)
4304#define CAU_LDR_CASR_VER_SHIFT (28U)
4305/*! VER - CAU version
4306 * 0b0001..Initial CAU version
4307 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
4308 */
4309#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
4310/*! @} */
4311
4312/*! @name LDR_CAA - Accumulator register - Load Register command */
4313/*! @{ */
4314#define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
4315#define CAU_LDR_CAA_ACC_SHIFT (0U)
4316#define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
4317/*! @} */
4318
4319/*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */
4320/*! @{ */
4321#define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
4322#define CAU_LDR_CA_CA0_SHIFT (0U)
4323#define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
4324#define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
4325#define CAU_LDR_CA_CA1_SHIFT (0U)
4326#define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
4327#define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
4328#define CAU_LDR_CA_CA2_SHIFT (0U)
4329#define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
4330#define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
4331#define CAU_LDR_CA_CA3_SHIFT (0U)
4332#define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
4333#define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
4334#define CAU_LDR_CA_CA4_SHIFT (0U)
4335#define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
4336#define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
4337#define CAU_LDR_CA_CA5_SHIFT (0U)
4338#define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
4339#define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
4340#define CAU_LDR_CA_CA6_SHIFT (0U)
4341#define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
4342#define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
4343#define CAU_LDR_CA_CA7_SHIFT (0U)
4344#define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
4345#define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
4346#define CAU_LDR_CA_CA8_SHIFT (0U)
4347#define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
4348/*! @} */
4349
4350/* The count of CAU_LDR_CA */
4351#define CAU_LDR_CA_COUNT (9U)
4352
4353/*! @name STR_CASR - Status register - Store Register command */
4354/*! @{ */
4355#define CAU_STR_CASR_IC_MASK (0x1U)
4356#define CAU_STR_CASR_IC_SHIFT (0U)
4357/*! IC
4358 * 0b0..No illegal commands issued
4359 * 0b1..Illegal command issued
4360 */
4361#define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
4362#define CAU_STR_CASR_DPE_MASK (0x2U)
4363#define CAU_STR_CASR_DPE_SHIFT (1U)
4364/*! DPE
4365 * 0b0..No error detected
4366 * 0b1..DES key parity error detected
4367 */
4368#define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
4369#define CAU_STR_CASR_VER_MASK (0xF0000000U)
4370#define CAU_STR_CASR_VER_SHIFT (28U)
4371/*! VER - CAU version
4372 * 0b0001..Initial CAU version
4373 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
4374 */
4375#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
4376/*! @} */
4377
4378/*! @name STR_CAA - Accumulator register - Store Register command */
4379/*! @{ */
4380#define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
4381#define CAU_STR_CAA_ACC_SHIFT (0U)
4382#define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
4383/*! @} */
4384
4385/*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */
4386/*! @{ */
4387#define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
4388#define CAU_STR_CA_CA0_SHIFT (0U)
4389#define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
4390#define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
4391#define CAU_STR_CA_CA1_SHIFT (0U)
4392#define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
4393#define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
4394#define CAU_STR_CA_CA2_SHIFT (0U)
4395#define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
4396#define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
4397#define CAU_STR_CA_CA3_SHIFT (0U)
4398#define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
4399#define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
4400#define CAU_STR_CA_CA4_SHIFT (0U)
4401#define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
4402#define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
4403#define CAU_STR_CA_CA5_SHIFT (0U)
4404#define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
4405#define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
4406#define CAU_STR_CA_CA6_SHIFT (0U)
4407#define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
4408#define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
4409#define CAU_STR_CA_CA7_SHIFT (0U)
4410#define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
4411#define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
4412#define CAU_STR_CA_CA8_SHIFT (0U)
4413#define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
4414/*! @} */
4415
4416/* The count of CAU_STR_CA */
4417#define CAU_STR_CA_COUNT (9U)
4418
4419/*! @name ADR_CASR - Status register - Add Register command */
4420/*! @{ */
4421#define CAU_ADR_CASR_IC_MASK (0x1U)
4422#define CAU_ADR_CASR_IC_SHIFT (0U)
4423/*! IC
4424 * 0b0..No illegal commands issued
4425 * 0b1..Illegal command issued
4426 */
4427#define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
4428#define CAU_ADR_CASR_DPE_MASK (0x2U)
4429#define CAU_ADR_CASR_DPE_SHIFT (1U)
4430/*! DPE
4431 * 0b0..No error detected
4432 * 0b1..DES key parity error detected
4433 */
4434#define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
4435#define CAU_ADR_CASR_VER_MASK (0xF0000000U)
4436#define CAU_ADR_CASR_VER_SHIFT (28U)
4437/*! VER - CAU version
4438 * 0b0001..Initial CAU version
4439 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
4440 */
4441#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
4442/*! @} */
4443
4444/*! @name ADR_CAA - Accumulator register - Add to register command */
4445/*! @{ */
4446#define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
4447#define CAU_ADR_CAA_ACC_SHIFT (0U)
4448#define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
4449/*! @} */
4450
4451/*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */
4452/*! @{ */
4453#define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
4454#define CAU_ADR_CA_CA0_SHIFT (0U)
4455#define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
4456#define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
4457#define CAU_ADR_CA_CA1_SHIFT (0U)
4458#define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
4459#define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
4460#define CAU_ADR_CA_CA2_SHIFT (0U)
4461#define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
4462#define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
4463#define CAU_ADR_CA_CA3_SHIFT (0U)
4464#define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
4465#define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
4466#define CAU_ADR_CA_CA4_SHIFT (0U)
4467#define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
4468#define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
4469#define CAU_ADR_CA_CA5_SHIFT (0U)
4470#define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
4471#define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
4472#define CAU_ADR_CA_CA6_SHIFT (0U)
4473#define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
4474#define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
4475#define CAU_ADR_CA_CA7_SHIFT (0U)
4476#define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
4477#define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
4478#define CAU_ADR_CA_CA8_SHIFT (0U)
4479#define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
4480/*! @} */
4481
4482/* The count of CAU_ADR_CA */
4483#define CAU_ADR_CA_COUNT (9U)
4484
4485/*! @name RADR_CASR - Status register - Reverse and Add to Register command */
4486/*! @{ */
4487#define CAU_RADR_CASR_IC_MASK (0x1U)
4488#define CAU_RADR_CASR_IC_SHIFT (0U)
4489/*! IC
4490 * 0b0..No illegal commands issued
4491 * 0b1..Illegal command issued
4492 */
4493#define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
4494#define CAU_RADR_CASR_DPE_MASK (0x2U)
4495#define CAU_RADR_CASR_DPE_SHIFT (1U)
4496/*! DPE
4497 * 0b0..No error detected
4498 * 0b1..DES key parity error detected
4499 */
4500#define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
4501#define CAU_RADR_CASR_VER_MASK (0xF0000000U)
4502#define CAU_RADR_CASR_VER_SHIFT (28U)
4503/*! VER - CAU version
4504 * 0b0001..Initial CAU version
4505 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
4506 */
4507#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
4508/*! @} */
4509
4510/*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
4511/*! @{ */
4512#define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
4513#define CAU_RADR_CAA_ACC_SHIFT (0U)
4514#define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
4515/*! @} */
4516
4517/*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */
4518/*! @{ */
4519#define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
4520#define CAU_RADR_CA_CA0_SHIFT (0U)
4521#define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
4522#define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
4523#define CAU_RADR_CA_CA1_SHIFT (0U)
4524#define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
4525#define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
4526#define CAU_RADR_CA_CA2_SHIFT (0U)
4527#define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
4528#define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
4529#define CAU_RADR_CA_CA3_SHIFT (0U)
4530#define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
4531#define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
4532#define CAU_RADR_CA_CA4_SHIFT (0U)
4533#define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
4534#define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
4535#define CAU_RADR_CA_CA5_SHIFT (0U)
4536#define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
4537#define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
4538#define CAU_RADR_CA_CA6_SHIFT (0U)
4539#define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
4540#define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
4541#define CAU_RADR_CA_CA7_SHIFT (0U)
4542#define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
4543#define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
4544#define CAU_RADR_CA_CA8_SHIFT (0U)
4545#define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
4546/*! @} */
4547
4548/* The count of CAU_RADR_CA */
4549#define CAU_RADR_CA_COUNT (9U)
4550
4551/*! @name XOR_CASR - Status register - Exclusive Or command */
4552/*! @{ */
4553#define CAU_XOR_CASR_IC_MASK (0x1U)
4554#define CAU_XOR_CASR_IC_SHIFT (0U)
4555/*! IC
4556 * 0b0..No illegal commands issued
4557 * 0b1..Illegal command issued
4558 */
4559#define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
4560#define CAU_XOR_CASR_DPE_MASK (0x2U)
4561#define CAU_XOR_CASR_DPE_SHIFT (1U)
4562/*! DPE
4563 * 0b0..No error detected
4564 * 0b1..DES key parity error detected
4565 */
4566#define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
4567#define CAU_XOR_CASR_VER_MASK (0xF0000000U)
4568#define CAU_XOR_CASR_VER_SHIFT (28U)
4569/*! VER - CAU version
4570 * 0b0001..Initial CAU version
4571 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
4572 */
4573#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
4574/*! @} */
4575
4576/*! @name XOR_CAA - Accumulator register - Exclusive Or command */
4577/*! @{ */
4578#define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
4579#define CAU_XOR_CAA_ACC_SHIFT (0U)
4580#define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
4581/*! @} */
4582
4583/*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */
4584/*! @{ */
4585#define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
4586#define CAU_XOR_CA_CA0_SHIFT (0U)
4587#define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
4588#define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
4589#define CAU_XOR_CA_CA1_SHIFT (0U)
4590#define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
4591#define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
4592#define CAU_XOR_CA_CA2_SHIFT (0U)
4593#define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
4594#define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
4595#define CAU_XOR_CA_CA3_SHIFT (0U)
4596#define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
4597#define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
4598#define CAU_XOR_CA_CA4_SHIFT (0U)
4599#define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
4600#define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
4601#define CAU_XOR_CA_CA5_SHIFT (0U)
4602#define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
4603#define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
4604#define CAU_XOR_CA_CA6_SHIFT (0U)
4605#define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
4606#define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
4607#define CAU_XOR_CA_CA7_SHIFT (0U)
4608#define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
4609#define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
4610#define CAU_XOR_CA_CA8_SHIFT (0U)
4611#define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
4612/*! @} */
4613
4614/* The count of CAU_XOR_CA */
4615#define CAU_XOR_CA_COUNT (9U)
4616
4617/*! @name ROTL_CASR - Status register - Rotate Left command */
4618/*! @{ */
4619#define CAU_ROTL_CASR_IC_MASK (0x1U)
4620#define CAU_ROTL_CASR_IC_SHIFT (0U)
4621/*! IC
4622 * 0b0..No illegal commands issued
4623 * 0b1..Illegal command issued
4624 */
4625#define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
4626#define CAU_ROTL_CASR_DPE_MASK (0x2U)
4627#define CAU_ROTL_CASR_DPE_SHIFT (1U)
4628/*! DPE
4629 * 0b0..No error detected
4630 * 0b1..DES key parity error detected
4631 */
4632#define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
4633#define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
4634#define CAU_ROTL_CASR_VER_SHIFT (28U)
4635/*! VER - CAU version
4636 * 0b0001..Initial CAU version
4637 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
4638 */
4639#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
4640/*! @} */
4641
4642/*! @name ROTL_CAA - Accumulator register - Rotate Left command */
4643/*! @{ */
4644#define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
4645#define CAU_ROTL_CAA_ACC_SHIFT (0U)
4646#define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
4647/*! @} */
4648
4649/*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */
4650/*! @{ */
4651#define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
4652#define CAU_ROTL_CA_CA0_SHIFT (0U)
4653#define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
4654#define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
4655#define CAU_ROTL_CA_CA1_SHIFT (0U)
4656#define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
4657#define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
4658#define CAU_ROTL_CA_CA2_SHIFT (0U)
4659#define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
4660#define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
4661#define CAU_ROTL_CA_CA3_SHIFT (0U)
4662#define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
4663#define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
4664#define CAU_ROTL_CA_CA4_SHIFT (0U)
4665#define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
4666#define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
4667#define CAU_ROTL_CA_CA5_SHIFT (0U)
4668#define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
4669#define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
4670#define CAU_ROTL_CA_CA6_SHIFT (0U)
4671#define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
4672#define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
4673#define CAU_ROTL_CA_CA7_SHIFT (0U)
4674#define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
4675#define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
4676#define CAU_ROTL_CA_CA8_SHIFT (0U)
4677#define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
4678/*! @} */
4679
4680/* The count of CAU_ROTL_CA */
4681#define CAU_ROTL_CA_COUNT (9U)
4682
4683/*! @name AESC_CASR - Status register - AES Column Operation command */
4684/*! @{ */
4685#define CAU_AESC_CASR_IC_MASK (0x1U)
4686#define CAU_AESC_CASR_IC_SHIFT (0U)
4687/*! IC
4688 * 0b0..No illegal commands issued
4689 * 0b1..Illegal command issued
4690 */
4691#define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
4692#define CAU_AESC_CASR_DPE_MASK (0x2U)
4693#define CAU_AESC_CASR_DPE_SHIFT (1U)
4694/*! DPE
4695 * 0b0..No error detected
4696 * 0b1..DES key parity error detected
4697 */
4698#define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
4699#define CAU_AESC_CASR_VER_MASK (0xF0000000U)
4700#define CAU_AESC_CASR_VER_SHIFT (28U)
4701/*! VER - CAU version
4702 * 0b0001..Initial CAU version
4703 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
4704 */
4705#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
4706/*! @} */
4707
4708/*! @name AESC_CAA - Accumulator register - AES Column Operation command */
4709/*! @{ */
4710#define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
4711#define CAU_AESC_CAA_ACC_SHIFT (0U)
4712#define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
4713/*! @} */
4714
4715/*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */
4716/*! @{ */
4717#define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
4718#define CAU_AESC_CA_CA0_SHIFT (0U)
4719#define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
4720#define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
4721#define CAU_AESC_CA_CA1_SHIFT (0U)
4722#define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
4723#define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
4724#define CAU_AESC_CA_CA2_SHIFT (0U)
4725#define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
4726#define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
4727#define CAU_AESC_CA_CA3_SHIFT (0U)
4728#define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
4729#define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
4730#define CAU_AESC_CA_CA4_SHIFT (0U)
4731#define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
4732#define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
4733#define CAU_AESC_CA_CA5_SHIFT (0U)
4734#define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
4735#define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
4736#define CAU_AESC_CA_CA6_SHIFT (0U)
4737#define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
4738#define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
4739#define CAU_AESC_CA_CA7_SHIFT (0U)
4740#define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
4741#define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
4742#define CAU_AESC_CA_CA8_SHIFT (0U)
4743#define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
4744/*! @} */
4745
4746/* The count of CAU_AESC_CA */
4747#define CAU_AESC_CA_COUNT (9U)
4748
4749/*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
4750/*! @{ */
4751#define CAU_AESIC_CASR_IC_MASK (0x1U)
4752#define CAU_AESIC_CASR_IC_SHIFT (0U)
4753/*! IC
4754 * 0b0..No illegal commands issued
4755 * 0b1..Illegal command issued
4756 */
4757#define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
4758#define CAU_AESIC_CASR_DPE_MASK (0x2U)
4759#define CAU_AESIC_CASR_DPE_SHIFT (1U)
4760/*! DPE
4761 * 0b0..No error detected
4762 * 0b1..DES key parity error detected
4763 */
4764#define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
4765#define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
4766#define CAU_AESIC_CASR_VER_SHIFT (28U)
4767/*! VER - CAU version
4768 * 0b0001..Initial CAU version
4769 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
4770 */
4771#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
4772/*! @} */
4773
4774/*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */
4775/*! @{ */
4776#define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
4777#define CAU_AESIC_CAA_ACC_SHIFT (0U)
4778#define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
4779/*! @} */
4780
4781/*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */
4782/*! @{ */
4783#define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
4784#define CAU_AESIC_CA_CA0_SHIFT (0U)
4785#define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
4786#define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
4787#define CAU_AESIC_CA_CA1_SHIFT (0U)
4788#define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
4789#define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
4790#define CAU_AESIC_CA_CA2_SHIFT (0U)
4791#define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
4792#define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
4793#define CAU_AESIC_CA_CA3_SHIFT (0U)
4794#define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
4795#define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
4796#define CAU_AESIC_CA_CA4_SHIFT (0U)
4797#define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
4798#define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
4799#define CAU_AESIC_CA_CA5_SHIFT (0U)
4800#define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
4801#define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
4802#define CAU_AESIC_CA_CA6_SHIFT (0U)
4803#define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
4804#define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
4805#define CAU_AESIC_CA_CA7_SHIFT (0U)
4806#define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
4807#define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
4808#define CAU_AESIC_CA_CA8_SHIFT (0U)
4809#define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
4810/*! @} */
4811
4812/* The count of CAU_AESIC_CA */
4813#define CAU_AESIC_CA_COUNT (9U)
4814
4815
4816/*!
4817 * @}
4818 */ /* end of group CAU_Register_Masks */
4819
4820
4821/* CAU - Peripheral instance base addresses */
4822/** Peripheral CAU base address */
4823#define CAU_BASE (0xE0081000u)
4824/** Peripheral CAU base pointer */
4825#define CAU ((CAU_Type *)CAU_BASE)
4826/** Array initializer of CAU peripheral base addresses */
4827#define CAU_BASE_ADDRS { CAU_BASE }
4828/** Array initializer of CAU peripheral base pointers */
4829#define CAU_BASE_PTRS { CAU }
4830
4831/*!
4832 * @}
4833 */ /* end of group CAU_Peripheral_Access_Layer */
4834
4835
4836/* ----------------------------------------------------------------------------
4837 -- CMP Peripheral Access Layer
4838 ---------------------------------------------------------------------------- */
4839
4840/*!
4841 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
4842 * @{
4843 */
4844
4845/** CMP - Register Layout Typedef */
4846typedef struct {
4847 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
4848 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
4849 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
4850 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
4851 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
4852 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
4853} CMP_Type;
4854
4855/* ----------------------------------------------------------------------------
4856 -- CMP Register Masks
4857 ---------------------------------------------------------------------------- */
4858
4859/*!
4860 * @addtogroup CMP_Register_Masks CMP Register Masks
4861 * @{
4862 */
4863
4864/*! @name CR0 - CMP Control Register 0 */
4865/*! @{ */
4866#define CMP_CR0_HYSTCTR_MASK (0x3U)
4867#define CMP_CR0_HYSTCTR_SHIFT (0U)
4868/*! HYSTCTR - Comparator hard block hysteresis control
4869 * 0b00..Level 0
4870 * 0b01..Level 1
4871 * 0b10..Level 2
4872 * 0b11..Level 3
4873 */
4874#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
4875#define CMP_CR0_FILTER_CNT_MASK (0x70U)
4876#define CMP_CR0_FILTER_CNT_SHIFT (4U)
4877/*! FILTER_CNT - Filter Sample Count
4878 * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
4879 * 0b001..One sample must agree. The comparator output is simply sampled.
4880 * 0b010..2 consecutive samples must agree.
4881 * 0b011..3 consecutive samples must agree.
4882 * 0b100..4 consecutive samples must agree.
4883 * 0b101..5 consecutive samples must agree.
4884 * 0b110..6 consecutive samples must agree.
4885 * 0b111..7 consecutive samples must agree.
4886 */
4887#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
4888/*! @} */
4889
4890/*! @name CR1 - CMP Control Register 1 */
4891/*! @{ */
4892#define CMP_CR1_EN_MASK (0x1U)
4893#define CMP_CR1_EN_SHIFT (0U)
4894/*! EN - Comparator Module Enable
4895 * 0b0..Analog Comparator is disabled.
4896 * 0b1..Analog Comparator is enabled.
4897 */
4898#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
4899#define CMP_CR1_OPE_MASK (0x2U)
4900#define CMP_CR1_OPE_SHIFT (1U)
4901/*! OPE - Comparator Output Pin Enable
4902 * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
4903 * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.
4904 */
4905#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
4906#define CMP_CR1_COS_MASK (0x4U)
4907#define CMP_CR1_COS_SHIFT (2U)
4908/*! COS - Comparator Output Select
4909 * 0b0..Set the filtered comparator output (CMPO) to equal COUT.
4910 * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
4911 */
4912#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
4913#define CMP_CR1_INV_MASK (0x8U)
4914#define CMP_CR1_INV_SHIFT (3U)
4915/*! INV - Comparator INVERT
4916 * 0b0..Does not invert the comparator output.
4917 * 0b1..Inverts the comparator output.
4918 */
4919#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
4920#define CMP_CR1_PMODE_MASK (0x10U)
4921#define CMP_CR1_PMODE_SHIFT (4U)
4922/*! PMODE - Power Mode Select
4923 * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
4924 * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
4925 */
4926#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
4927#define CMP_CR1_TRIGM_MASK (0x20U)
4928#define CMP_CR1_TRIGM_SHIFT (5U)
4929/*! TRIGM - Trigger Mode Enable
4930 * 0b0..Trigger mode is disabled.
4931 * 0b1..Trigger mode is enabled.
4932 */
4933#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
4934#define CMP_CR1_WE_MASK (0x40U)
4935#define CMP_CR1_WE_SHIFT (6U)
4936/*! WE - Windowing Enable
4937 * 0b0..Windowing mode is not selected.
4938 * 0b1..Windowing mode is selected.
4939 */
4940#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
4941#define CMP_CR1_SE_MASK (0x80U)
4942#define CMP_CR1_SE_SHIFT (7U)
4943/*! SE - Sample Enable
4944 * 0b0..Sampling mode is not selected.
4945 * 0b1..Sampling mode is selected.
4946 */
4947#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
4948/*! @} */
4949
4950/*! @name FPR - CMP Filter Period Register */
4951/*! @{ */
4952#define CMP_FPR_FILT_PER_MASK (0xFFU)
4953#define CMP_FPR_FILT_PER_SHIFT (0U)
4954#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
4955/*! @} */
4956
4957/*! @name SCR - CMP Status and Control Register */
4958/*! @{ */
4959#define CMP_SCR_COUT_MASK (0x1U)
4960#define CMP_SCR_COUT_SHIFT (0U)
4961#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
4962#define CMP_SCR_CFF_MASK (0x2U)
4963#define CMP_SCR_CFF_SHIFT (1U)
4964/*! CFF - Analog Comparator Flag Falling
4965 * 0b0..Falling-edge on COUT has not been detected.
4966 * 0b1..Falling-edge on COUT has occurred.
4967 */
4968#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
4969#define CMP_SCR_CFR_MASK (0x4U)
4970#define CMP_SCR_CFR_SHIFT (2U)
4971/*! CFR - Analog Comparator Flag Rising
4972 * 0b0..Rising-edge on COUT has not been detected.
4973 * 0b1..Rising-edge on COUT has occurred.
4974 */
4975#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
4976#define CMP_SCR_IEF_MASK (0x8U)
4977#define CMP_SCR_IEF_SHIFT (3U)
4978/*! IEF - Comparator Interrupt Enable Falling
4979 * 0b0..Interrupt is disabled.
4980 * 0b1..Interrupt is enabled.
4981 */
4982#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
4983#define CMP_SCR_IER_MASK (0x10U)
4984#define CMP_SCR_IER_SHIFT (4U)
4985/*! IER - Comparator Interrupt Enable Rising
4986 * 0b0..Interrupt is disabled.
4987 * 0b1..Interrupt is enabled.
4988 */
4989#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
4990#define CMP_SCR_DMAEN_MASK (0x40U)
4991#define CMP_SCR_DMAEN_SHIFT (6U)
4992/*! DMAEN - DMA Enable Control
4993 * 0b0..DMA is disabled.
4994 * 0b1..DMA is enabled.
4995 */
4996#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
4997/*! @} */
4998
4999/*! @name DACCR - DAC Control Register */
5000/*! @{ */
5001#define CMP_DACCR_VOSEL_MASK (0x3FU)
5002#define CMP_DACCR_VOSEL_SHIFT (0U)
5003#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
5004#define CMP_DACCR_VRSEL_MASK (0x40U)
5005#define CMP_DACCR_VRSEL_SHIFT (6U)
5006/*! VRSEL - Supply Voltage Reference Source Select
5007 * 0b0..Vin1 is selected as resistor ladder network supply reference.
5008 * 0b1..Vin2 is selected as resistor ladder network supply reference.
5009 */
5010#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
5011#define CMP_DACCR_DACEN_MASK (0x80U)
5012#define CMP_DACCR_DACEN_SHIFT (7U)
5013/*! DACEN - DAC Enable
5014 * 0b0..DAC is disabled.
5015 * 0b1..DAC is enabled.
5016 */
5017#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
5018/*! @} */
5019
5020/*! @name MUXCR - MUX Control Register */
5021/*! @{ */
5022#define CMP_MUXCR_MSEL_MASK (0x7U)
5023#define CMP_MUXCR_MSEL_SHIFT (0U)
5024/*! MSEL - Minus Input Mux Control
5025 * 0b000..IN0
5026 * 0b001..IN1
5027 * 0b010..IN2
5028 * 0b011..IN3
5029 * 0b100..IN4
5030 * 0b101..IN5
5031 * 0b110..IN6
5032 * 0b111..IN7
5033 */
5034#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
5035#define CMP_MUXCR_PSEL_MASK (0x38U)
5036#define CMP_MUXCR_PSEL_SHIFT (3U)
5037/*! PSEL - Plus Input Mux Control
5038 * 0b000..IN0
5039 * 0b001..IN1
5040 * 0b010..IN2
5041 * 0b011..IN3
5042 * 0b100..IN4
5043 * 0b101..IN5
5044 * 0b110..IN6
5045 * 0b111..IN7
5046 */
5047#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
5048/*! @} */
5049
5050
5051/*!
5052 * @}
5053 */ /* end of group CMP_Register_Masks */
5054
5055
5056/* CMP - Peripheral instance base addresses */
5057/** Peripheral CMP0 base address */
5058#define CMP0_BASE (0x40073000u)
5059/** Peripheral CMP0 base pointer */
5060#define CMP0 ((CMP_Type *)CMP0_BASE)
5061/** Peripheral CMP1 base address */
5062#define CMP1_BASE (0x40073008u)
5063/** Peripheral CMP1 base pointer */
5064#define CMP1 ((CMP_Type *)CMP1_BASE)
5065/** Array initializer of CMP peripheral base addresses */
5066#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
5067/** Array initializer of CMP peripheral base pointers */
5068#define CMP_BASE_PTRS { CMP0, CMP1 }
5069/** Interrupt vectors for the CMP peripheral type */
5070#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
5071
5072/*!
5073 * @}
5074 */ /* end of group CMP_Peripheral_Access_Layer */
5075
5076
5077/* ----------------------------------------------------------------------------
5078 -- CMT Peripheral Access Layer
5079 ---------------------------------------------------------------------------- */
5080
5081/*!
5082 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
5083 * @{
5084 */
5085
5086/** CMT - Register Layout Typedef */
5087typedef struct {
5088 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
5089 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
5090 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
5091 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
5092 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
5093 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
5094 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
5095 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
5096 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
5097 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
5098 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
5099 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
5100} CMT_Type;
5101
5102/* ----------------------------------------------------------------------------
5103 -- CMT Register Masks
5104 ---------------------------------------------------------------------------- */
5105
5106/*!
5107 * @addtogroup CMT_Register_Masks CMT Register Masks
5108 * @{
5109 */
5110
5111/*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
5112/*! @{ */
5113#define CMT_CGH1_PH_MASK (0xFFU)
5114#define CMT_CGH1_PH_SHIFT (0U)
5115#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
5116/*! @} */
5117
5118/*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
5119/*! @{ */
5120#define CMT_CGL1_PL_MASK (0xFFU)
5121#define CMT_CGL1_PL_SHIFT (0U)
5122#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
5123/*! @} */
5124
5125/*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
5126/*! @{ */
5127#define CMT_CGH2_SH_MASK (0xFFU)
5128#define CMT_CGH2_SH_SHIFT (0U)
5129#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
5130/*! @} */
5131
5132/*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
5133/*! @{ */
5134#define CMT_CGL2_SL_MASK (0xFFU)
5135#define CMT_CGL2_SL_SHIFT (0U)
5136#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
5137/*! @} */
5138
5139/*! @name OC - CMT Output Control Register */
5140/*! @{ */
5141#define CMT_OC_IROPEN_MASK (0x20U)
5142#define CMT_OC_IROPEN_SHIFT (5U)
5143/*! IROPEN - IRO Pin Enable
5144 * 0b0..The IRO signal is disabled.
5145 * 0b1..The IRO signal is enabled as output.
5146 */
5147#define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
5148#define CMT_OC_CMTPOL_MASK (0x40U)
5149#define CMT_OC_CMTPOL_SHIFT (6U)
5150/*! CMTPOL - CMT Output Polarity
5151 * 0b0..The IRO signal is active-low.
5152 * 0b1..The IRO signal is active-high.
5153 */
5154#define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
5155#define CMT_OC_IROL_MASK (0x80U)
5156#define CMT_OC_IROL_SHIFT (7U)
5157#define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
5158/*! @} */
5159
5160/*! @name MSC - CMT Modulator Status and Control Register */
5161/*! @{ */
5162#define CMT_MSC_MCGEN_MASK (0x1U)
5163#define CMT_MSC_MCGEN_SHIFT (0U)
5164/*! MCGEN - Modulator and Carrier Generator Enable
5165 * 0b0..Modulator and carrier generator disabled
5166 * 0b1..Modulator and carrier generator enabled
5167 */
5168#define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
5169#define CMT_MSC_EOCIE_MASK (0x2U)
5170#define CMT_MSC_EOCIE_SHIFT (1U)
5171/*! EOCIE - End of Cycle Interrupt Enable
5172 * 0b0..CPU interrupt is disabled.
5173 * 0b1..CPU interrupt is enabled.
5174 */
5175#define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
5176#define CMT_MSC_FSK_MASK (0x4U)
5177#define CMT_MSC_FSK_SHIFT (2U)
5178/*! FSK - FSK Mode Select
5179 * 0b0..The CMT operates in Time or Baseband mode.
5180 * 0b1..The CMT operates in FSK mode.
5181 */
5182#define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
5183#define CMT_MSC_BASE_MASK (0x8U)
5184#define CMT_MSC_BASE_SHIFT (3U)
5185/*! BASE - Baseband Enable
5186 * 0b0..Baseband mode is disabled.
5187 * 0b1..Baseband mode is enabled.
5188 */
5189#define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
5190#define CMT_MSC_EXSPC_MASK (0x10U)
5191#define CMT_MSC_EXSPC_SHIFT (4U)
5192/*! EXSPC - Extended Space Enable
5193 * 0b0..Extended space is disabled.
5194 * 0b1..Extended space is enabled.
5195 */
5196#define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
5197#define CMT_MSC_CMTDIV_MASK (0x60U)
5198#define CMT_MSC_CMTDIV_SHIFT (5U)
5199/*! CMTDIV - CMT Clock Divide Prescaler
5200 * 0b00..IF * 1
5201 * 0b01..IF * 2
5202 * 0b10..IF * 4
5203 * 0b11..IF * 8
5204 */
5205#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
5206#define CMT_MSC_EOCF_MASK (0x80U)
5207#define CMT_MSC_EOCF_SHIFT (7U)
5208/*! EOCF - End Of Cycle Status Flag
5209 * 0b0..End of modulation cycle has not occured since the flag last cleared.
5210 * 0b1..End of modulator cycle has occurred.
5211 */
5212#define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
5213/*! @} */
5214
5215/*! @name CMD1 - CMT Modulator Data Register Mark High */
5216/*! @{ */
5217#define CMT_CMD1_MB_MASK (0xFFU)
5218#define CMT_CMD1_MB_SHIFT (0U)
5219#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
5220/*! @} */
5221
5222/*! @name CMD2 - CMT Modulator Data Register Mark Low */
5223/*! @{ */
5224#define CMT_CMD2_MB_MASK (0xFFU)
5225#define CMT_CMD2_MB_SHIFT (0U)
5226#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
5227/*! @} */
5228
5229/*! @name CMD3 - CMT Modulator Data Register Space High */
5230/*! @{ */
5231#define CMT_CMD3_SB_MASK (0xFFU)
5232#define CMT_CMD3_SB_SHIFT (0U)
5233#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
5234/*! @} */
5235
5236/*! @name CMD4 - CMT Modulator Data Register Space Low */
5237/*! @{ */
5238#define CMT_CMD4_SB_MASK (0xFFU)
5239#define CMT_CMD4_SB_SHIFT (0U)
5240#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
5241/*! @} */
5242
5243/*! @name PPS - CMT Primary Prescaler Register */
5244/*! @{ */
5245#define CMT_PPS_PPSDIV_MASK (0xFU)
5246#define CMT_PPS_PPSDIV_SHIFT (0U)
5247/*! PPSDIV - Primary Prescaler Divider
5248 * 0b0000..Bus clock * 1
5249 * 0b0001..Bus clock * 2
5250 * 0b0010..Bus clock * 3
5251 * 0b0011..Bus clock * 4
5252 * 0b0100..Bus clock * 5
5253 * 0b0101..Bus clock * 6
5254 * 0b0110..Bus clock * 7
5255 * 0b0111..Bus clock * 8
5256 * 0b1000..Bus clock * 9
5257 * 0b1001..Bus clock * 10
5258 * 0b1010..Bus clock * 11
5259 * 0b1011..Bus clock * 12
5260 * 0b1100..Bus clock * 13
5261 * 0b1101..Bus clock * 14
5262 * 0b1110..Bus clock * 15
5263 * 0b1111..Bus clock * 16
5264 */
5265#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
5266/*! @} */
5267
5268/*! @name DMA - CMT Direct Memory Access Register */
5269/*! @{ */
5270#define CMT_DMA_DMA_MASK (0x1U)
5271#define CMT_DMA_DMA_SHIFT (0U)
5272/*! DMA - DMA Enable
5273 * 0b0..DMA transfer request and done are disabled.
5274 * 0b1..DMA transfer request and done are enabled.
5275 */
5276#define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
5277/*! @} */
5278
5279
5280/*!
5281 * @}
5282 */ /* end of group CMT_Register_Masks */
5283
5284
5285/* CMT - Peripheral instance base addresses */
5286/** Peripheral CMT base address */
5287#define CMT_BASE (0x40062000u)
5288/** Peripheral CMT base pointer */
5289#define CMT ((CMT_Type *)CMT_BASE)
5290/** Array initializer of CMT peripheral base addresses */
5291#define CMT_BASE_ADDRS { CMT_BASE }
5292/** Array initializer of CMT peripheral base pointers */
5293#define CMT_BASE_PTRS { CMT }
5294/** Interrupt vectors for the CMT peripheral type */
5295#define CMT_IRQS { CMT_IRQn }
5296
5297/*!
5298 * @}
5299 */ /* end of group CMT_Peripheral_Access_Layer */
5300
5301
5302/* ----------------------------------------------------------------------------
5303 -- CRC Peripheral Access Layer
5304 ---------------------------------------------------------------------------- */
5305
5306/*!
5307 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
5308 * @{
5309 */
5310
5311/** CRC - Register Layout Typedef */
5312typedef struct {
5313 union { /* offset: 0x0 */
5314 struct { /* offset: 0x0 */
5315 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
5316 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
5317 } ACCESS16BIT;
5318 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
5319 struct { /* offset: 0x0 */
5320 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
5321 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
5322 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
5323 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
5324 } ACCESS8BIT;
5325 };
5326 union { /* offset: 0x4 */
5327 struct { /* offset: 0x4 */
5328 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
5329 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
5330 } GPOLY_ACCESS16BIT;
5331 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
5332 struct { /* offset: 0x4 */
5333 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
5334 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
5335 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
5336 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
5337 } GPOLY_ACCESS8BIT;
5338 };
5339 union { /* offset: 0x8 */
5340 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
5341 struct { /* offset: 0x8 */
5342 uint8_t RESERVED_0[3];
5343 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
5344 } CTRL_ACCESS8BIT;
5345 };
5346} CRC_Type;
5347
5348/* ----------------------------------------------------------------------------
5349 -- CRC Register Masks
5350 ---------------------------------------------------------------------------- */
5351
5352/*!
5353 * @addtogroup CRC_Register_Masks CRC Register Masks
5354 * @{
5355 */
5356
5357/*! @name DATAL - CRC_DATAL register. */
5358/*! @{ */
5359#define CRC_DATAL_DATAL_MASK (0xFFFFU)
5360#define CRC_DATAL_DATAL_SHIFT (0U)
5361#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
5362/*! @} */
5363
5364/*! @name DATAH - CRC_DATAH register. */
5365/*! @{ */
5366#define CRC_DATAH_DATAH_MASK (0xFFFFU)
5367#define CRC_DATAH_DATAH_SHIFT (0U)
5368#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
5369/*! @} */
5370
5371/*! @name DATA - CRC Data register */
5372/*! @{ */
5373#define CRC_DATA_LL_MASK (0xFFU)
5374#define CRC_DATA_LL_SHIFT (0U)
5375#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
5376#define CRC_DATA_LU_MASK (0xFF00U)
5377#define CRC_DATA_LU_SHIFT (8U)
5378#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
5379#define CRC_DATA_HL_MASK (0xFF0000U)
5380#define CRC_DATA_HL_SHIFT (16U)
5381#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
5382#define CRC_DATA_HU_MASK (0xFF000000U)
5383#define CRC_DATA_HU_SHIFT (24U)
5384#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
5385/*! @} */
5386
5387/*! @name DATALL - CRC_DATALL register. */
5388/*! @{ */
5389#define CRC_DATALL_DATALL_MASK (0xFFU)
5390#define CRC_DATALL_DATALL_SHIFT (0U)
5391#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
5392/*! @} */
5393
5394/*! @name DATALU - CRC_DATALU register. */
5395/*! @{ */
5396#define CRC_DATALU_DATALU_MASK (0xFFU)
5397#define CRC_DATALU_DATALU_SHIFT (0U)
5398#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
5399/*! @} */
5400
5401/*! @name DATAHL - CRC_DATAHL register. */
5402/*! @{ */
5403#define CRC_DATAHL_DATAHL_MASK (0xFFU)
5404#define CRC_DATAHL_DATAHL_SHIFT (0U)
5405#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
5406/*! @} */
5407
5408/*! @name DATAHU - CRC_DATAHU register. */
5409/*! @{ */
5410#define CRC_DATAHU_DATAHU_MASK (0xFFU)
5411#define CRC_DATAHU_DATAHU_SHIFT (0U)
5412#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
5413/*! @} */
5414
5415/*! @name GPOLYL - CRC_GPOLYL register. */
5416/*! @{ */
5417#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
5418#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
5419#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
5420/*! @} */
5421
5422/*! @name GPOLYH - CRC_GPOLYH register. */
5423/*! @{ */
5424#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
5425#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
5426#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
5427/*! @} */
5428
5429/*! @name GPOLY - CRC Polynomial register */
5430/*! @{ */
5431#define CRC_GPOLY_LOW_MASK (0xFFFFU)
5432#define CRC_GPOLY_LOW_SHIFT (0U)
5433#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
5434#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
5435#define CRC_GPOLY_HIGH_SHIFT (16U)
5436#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
5437/*! @} */
5438
5439/*! @name GPOLYLL - CRC_GPOLYLL register. */
5440/*! @{ */
5441#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
5442#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
5443#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
5444/*! @} */
5445
5446/*! @name GPOLYLU - CRC_GPOLYLU register. */
5447/*! @{ */
5448#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
5449#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
5450#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
5451/*! @} */
5452
5453/*! @name GPOLYHL - CRC_GPOLYHL register. */
5454/*! @{ */
5455#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
5456#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
5457#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
5458/*! @} */
5459
5460/*! @name GPOLYHU - CRC_GPOLYHU register. */
5461/*! @{ */
5462#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
5463#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
5464#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
5465/*! @} */
5466
5467/*! @name CTRL - CRC Control register */
5468/*! @{ */
5469#define CRC_CTRL_TCRC_MASK (0x1000000U)
5470#define CRC_CTRL_TCRC_SHIFT (24U)
5471/*! TCRC
5472 * 0b0..16-bit CRC protocol.
5473 * 0b1..32-bit CRC protocol.
5474 */
5475#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
5476#define CRC_CTRL_WAS_MASK (0x2000000U)
5477#define CRC_CTRL_WAS_SHIFT (25U)
5478/*! WAS - Write CRC Data Register As Seed
5479 * 0b0..Writes to the CRC data register are data values.
5480 * 0b1..Writes to the CRC data register are seed values.
5481 */
5482#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
5483#define CRC_CTRL_FXOR_MASK (0x4000000U)
5484#define CRC_CTRL_FXOR_SHIFT (26U)
5485/*! FXOR - Complement Read Of CRC Data Register
5486 * 0b0..No XOR on reading.
5487 * 0b1..Invert or complement the read value of the CRC Data register.
5488 */
5489#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
5490#define CRC_CTRL_TOTR_MASK (0x30000000U)
5491#define CRC_CTRL_TOTR_SHIFT (28U)
5492/*! TOTR - Type Of Transpose For Read
5493 * 0b00..No transposition.
5494 * 0b01..Bits in bytes are transposed; bytes are not transposed.
5495 * 0b10..Both bits in bytes and bytes are transposed.
5496 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
5497 */
5498#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
5499#define CRC_CTRL_TOT_MASK (0xC0000000U)
5500#define CRC_CTRL_TOT_SHIFT (30U)
5501/*! TOT - Type Of Transpose For Writes
5502 * 0b00..No transposition.
5503 * 0b01..Bits in bytes are transposed; bytes are not transposed.
5504 * 0b10..Both bits in bytes and bytes are transposed.
5505 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
5506 */
5507#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
5508/*! @} */
5509
5510/*! @name CTRLHU - CRC_CTRLHU register. */
5511/*! @{ */
5512#define CRC_CTRLHU_TCRC_MASK (0x1U)
5513#define CRC_CTRLHU_TCRC_SHIFT (0U)
5514/*! TCRC
5515 * 0b0..16-bit CRC protocol.
5516 * 0b1..32-bit CRC protocol.
5517 */
5518#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
5519#define CRC_CTRLHU_WAS_MASK (0x2U)
5520#define CRC_CTRLHU_WAS_SHIFT (1U)
5521/*! WAS
5522 * 0b0..Writes to CRC data register are data values.
5523 * 0b1..Writes to CRC data reguster are seed values.
5524 */
5525#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
5526#define CRC_CTRLHU_FXOR_MASK (0x4U)
5527#define CRC_CTRLHU_FXOR_SHIFT (2U)
5528/*! FXOR
5529 * 0b0..No XOR on reading.
5530 * 0b1..Invert or complement the read value of CRC data register.
5531 */
5532#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
5533#define CRC_CTRLHU_TOTR_MASK (0x30U)
5534#define CRC_CTRLHU_TOTR_SHIFT (4U)
5535/*! TOTR
5536 * 0b00..No Transposition.
5537 * 0b01..Bits in bytes are transposed, bytes are not transposed.
5538 * 0b10..Both bits in bytes and bytes are transposed.
5539 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
5540 */
5541#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
5542#define CRC_CTRLHU_TOT_MASK (0xC0U)
5543#define CRC_CTRLHU_TOT_SHIFT (6U)
5544/*! TOT
5545 * 0b00..No Transposition.
5546 * 0b01..Bits in bytes are transposed, bytes are not transposed.
5547 * 0b10..Both bits in bytes and bytes are transposed.
5548 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
5549 */
5550#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
5551/*! @} */
5552
5553
5554/*!
5555 * @}
5556 */ /* end of group CRC_Register_Masks */
5557
5558
5559/* CRC - Peripheral instance base addresses */
5560/** Peripheral CRC base address */
5561#define CRC_BASE (0x40032000u)
5562/** Peripheral CRC base pointer */
5563#define CRC0 ((CRC_Type *)CRC_BASE)
5564/** Array initializer of CRC peripheral base addresses */
5565#define CRC_BASE_ADDRS { CRC_BASE }
5566/** Array initializer of CRC peripheral base pointers */
5567#define CRC_BASE_PTRS { CRC0 }
5568
5569/*!
5570 * @}
5571 */ /* end of group CRC_Peripheral_Access_Layer */
5572
5573
5574/* ----------------------------------------------------------------------------
5575 -- DAC Peripheral Access Layer
5576 ---------------------------------------------------------------------------- */
5577
5578/*!
5579 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
5580 * @{
5581 */
5582
5583/** DAC - Register Layout Typedef */
5584typedef struct {
5585 struct { /* offset: 0x0, array step: 0x2 */
5586 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
5587 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
5588 } DAT[16];
5589 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
5590 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
5591 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
5592 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
5593} DAC_Type;
5594
5595/* ----------------------------------------------------------------------------
5596 -- DAC Register Masks
5597 ---------------------------------------------------------------------------- */
5598
5599/*!
5600 * @addtogroup DAC_Register_Masks DAC Register Masks
5601 * @{
5602 */
5603
5604/*! @name DATL - DAC Data Low Register */
5605/*! @{ */
5606#define DAC_DATL_DATA0_MASK (0xFFU)
5607#define DAC_DATL_DATA0_SHIFT (0U)
5608#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
5609/*! @} */
5610
5611/* The count of DAC_DATL */
5612#define DAC_DATL_COUNT (16U)
5613
5614/*! @name DATH - DAC Data High Register */
5615/*! @{ */
5616#define DAC_DATH_DATA1_MASK (0xFU)
5617#define DAC_DATH_DATA1_SHIFT (0U)
5618#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
5619/*! @} */
5620
5621/* The count of DAC_DATH */
5622#define DAC_DATH_COUNT (16U)
5623
5624/*! @name SR - DAC Status Register */
5625/*! @{ */
5626#define DAC_SR_DACBFRPBF_MASK (0x1U)
5627#define DAC_SR_DACBFRPBF_SHIFT (0U)
5628/*! DACBFRPBF - DAC Buffer Read Pointer Bottom Position Flag
5629 * 0b0..The DAC buffer read pointer is not equal to C2[DACBFUP].
5630 * 0b1..The DAC buffer read pointer is equal to C2[DACBFUP].
5631 */
5632#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
5633#define DAC_SR_DACBFRPTF_MASK (0x2U)
5634#define DAC_SR_DACBFRPTF_SHIFT (1U)
5635/*! DACBFRPTF - DAC Buffer Read Pointer Top Position Flag
5636 * 0b0..The DAC buffer read pointer is not zero.
5637 * 0b1..The DAC buffer read pointer is zero.
5638 */
5639#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
5640#define DAC_SR_DACBFWMF_MASK (0x4U)
5641#define DAC_SR_DACBFWMF_SHIFT (2U)
5642/*! DACBFWMF - DAC Buffer Watermark Flag
5643 * 0b0..The DAC buffer read pointer has not reached the watermark level.
5644 * 0b1..The DAC buffer read pointer has reached the watermark level.
5645 */
5646#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
5647/*! @} */
5648
5649/*! @name C0 - DAC Control Register */
5650/*! @{ */
5651#define DAC_C0_DACBBIEN_MASK (0x1U)
5652#define DAC_C0_DACBBIEN_SHIFT (0U)
5653/*! DACBBIEN - DAC Buffer Read Pointer Bottom Flag Interrupt Enable
5654 * 0b0..The DAC buffer read pointer bottom flag interrupt is disabled.
5655 * 0b1..The DAC buffer read pointer bottom flag interrupt is enabled.
5656 */
5657#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
5658#define DAC_C0_DACBTIEN_MASK (0x2U)
5659#define DAC_C0_DACBTIEN_SHIFT (1U)
5660/*! DACBTIEN - DAC Buffer Read Pointer Top Flag Interrupt Enable
5661 * 0b0..The DAC buffer read pointer top flag interrupt is disabled.
5662 * 0b1..The DAC buffer read pointer top flag interrupt is enabled.
5663 */
5664#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
5665#define DAC_C0_DACBWIEN_MASK (0x4U)
5666#define DAC_C0_DACBWIEN_SHIFT (2U)
5667/*! DACBWIEN - DAC Buffer Watermark Interrupt Enable
5668 * 0b0..The DAC buffer watermark interrupt is disabled.
5669 * 0b1..The DAC buffer watermark interrupt is enabled.
5670 */
5671#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
5672#define DAC_C0_LPEN_MASK (0x8U)
5673#define DAC_C0_LPEN_SHIFT (3U)
5674/*! LPEN - DAC Low Power Control
5675 * 0b0..High-Power mode
5676 * 0b1..Low-Power mode
5677 */
5678#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
5679#define DAC_C0_DACSWTRG_MASK (0x10U)
5680#define DAC_C0_DACSWTRG_SHIFT (4U)
5681/*! DACSWTRG - DAC Software Trigger
5682 * 0b0..The DAC soft trigger is not valid.
5683 * 0b1..The DAC soft trigger is valid.
5684 */
5685#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
5686#define DAC_C0_DACTRGSEL_MASK (0x20U)
5687#define DAC_C0_DACTRGSEL_SHIFT (5U)
5688/*! DACTRGSEL - DAC Trigger Select
5689 * 0b0..The DAC hardware trigger is selected.
5690 * 0b1..The DAC software trigger is selected.
5691 */
5692#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
5693#define DAC_C0_DACRFS_MASK (0x40U)
5694#define DAC_C0_DACRFS_SHIFT (6U)
5695/*! DACRFS - DAC Reference Select
5696 * 0b0..The DAC selects DACREF_1 as the reference voltage.
5697 * 0b1..The DAC selects DACREF_2 as the reference voltage.
5698 */
5699#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
5700#define DAC_C0_DACEN_MASK (0x80U)
5701#define DAC_C0_DACEN_SHIFT (7U)
5702/*! DACEN - DAC Enable
5703 * 0b0..The DAC system is disabled.
5704 * 0b1..The DAC system is enabled.
5705 */
5706#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
5707/*! @} */
5708
5709/*! @name C1 - DAC Control Register 1 */
5710/*! @{ */
5711#define DAC_C1_DACBFEN_MASK (0x1U)
5712#define DAC_C1_DACBFEN_SHIFT (0U)
5713/*! DACBFEN - DAC Buffer Enable
5714 * 0b0..Buffer read pointer is disabled. The converted data is always the first word of the buffer.
5715 * 0b1..Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.
5716 */
5717#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
5718#define DAC_C1_DACBFMD_MASK (0x6U)
5719#define DAC_C1_DACBFMD_SHIFT (1U)
5720/*! DACBFMD - DAC Buffer Work Mode Select
5721 * 0b00..Normal mode
5722 * 0b01..Swing mode
5723 * 0b10..One-Time Scan mode
5724 * 0b11..FIFO mode
5725 */
5726#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
5727#define DAC_C1_DACBFWM_MASK (0x18U)
5728#define DAC_C1_DACBFWM_SHIFT (3U)
5729/*! DACBFWM - DAC Buffer Watermark Select
5730 * 0b00..In normal mode, 1 word . In FIFO mode, 2 or less than 2 data remaining in FIFO will set watermark status bit.
5731 * 0b01..In normal mode, 2 words . In FIFO mode, Max/4 or less than Max/4 data remaining in FIFO will set watermark status bit.
5732 * 0b10..In normal mode, 3 words . In FIFO mode, Max/2 or less than Max/2 data remaining in FIFO will set watermark status bit.
5733 * 0b11..In normal mode, 4 words . In FIFO mode, Max-2 or less than Max-2 data remaining in FIFO will set watermark status bit.
5734 */
5735#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
5736#define DAC_C1_DMAEN_MASK (0x80U)
5737#define DAC_C1_DMAEN_SHIFT (7U)
5738/*! DMAEN - DMA Enable Select
5739 * 0b0..DMA is disabled.
5740 * 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.
5741 */
5742#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
5743/*! @} */
5744
5745/*! @name C2 - DAC Control Register 2 */
5746/*! @{ */
5747#define DAC_C2_DACBFUP_MASK (0xFU)
5748#define DAC_C2_DACBFUP_SHIFT (0U)
5749#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
5750#define DAC_C2_DACBFRP_MASK (0xF0U)
5751#define DAC_C2_DACBFRP_SHIFT (4U)
5752#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
5753/*! @} */
5754
5755
5756/*!
5757 * @}
5758 */ /* end of group DAC_Register_Masks */
5759
5760
5761/* DAC - Peripheral instance base addresses */
5762/** Peripheral DAC0 base address */
5763#define DAC0_BASE (0x400CC000u)
5764/** Peripheral DAC0 base pointer */
5765#define DAC0 ((DAC_Type *)DAC0_BASE)
5766/** Array initializer of DAC peripheral base addresses */
5767#define DAC_BASE_ADDRS { DAC0_BASE }
5768/** Array initializer of DAC peripheral base pointers */
5769#define DAC_BASE_PTRS { DAC0 }
5770/** Interrupt vectors for the DAC peripheral type */
5771#define DAC_IRQS { DAC0_IRQn }
5772
5773/*!
5774 * @}
5775 */ /* end of group DAC_Peripheral_Access_Layer */
5776
5777
5778/* ----------------------------------------------------------------------------
5779 -- DMA Peripheral Access Layer
5780 ---------------------------------------------------------------------------- */
5781
5782/*!
5783 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
5784 * @{
5785 */
5786
5787/** DMA - Register Layout Typedef */
5788typedef struct {
5789 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
5790 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
5791 uint8_t RESERVED_0[4];
5792 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
5793 uint8_t RESERVED_1[4];
5794 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
5795 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
5796 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
5797 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
5798 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
5799 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
5800 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
5801 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
5802 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
5803 uint8_t RESERVED_2[4];
5804 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
5805 uint8_t RESERVED_3[4];
5806 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
5807 uint8_t RESERVED_4[4];
5808 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
5809 uint8_t RESERVED_5[12];
5810 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
5811 uint8_t RESERVED_6[184];
5812 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
5813 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
5814 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
5815 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
5816 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
5817 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
5818 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
5819 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
5820 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
5821 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
5822 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
5823 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
5824 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
5825 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
5826 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
5827 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
5828 __IO uint8_t DCHPRI19; /**< Channel n Priority Register, offset: 0x110 */
5829 __IO uint8_t DCHPRI18; /**< Channel n Priority Register, offset: 0x111 */
5830 __IO uint8_t DCHPRI17; /**< Channel n Priority Register, offset: 0x112 */
5831 __IO uint8_t DCHPRI16; /**< Channel n Priority Register, offset: 0x113 */
5832 __IO uint8_t DCHPRI23; /**< Channel n Priority Register, offset: 0x114 */
5833 __IO uint8_t DCHPRI22; /**< Channel n Priority Register, offset: 0x115 */
5834 __IO uint8_t DCHPRI21; /**< Channel n Priority Register, offset: 0x116 */
5835 __IO uint8_t DCHPRI20; /**< Channel n Priority Register, offset: 0x117 */
5836 __IO uint8_t DCHPRI27; /**< Channel n Priority Register, offset: 0x118 */
5837 __IO uint8_t DCHPRI26; /**< Channel n Priority Register, offset: 0x119 */
5838 __IO uint8_t DCHPRI25; /**< Channel n Priority Register, offset: 0x11A */
5839 __IO uint8_t DCHPRI24; /**< Channel n Priority Register, offset: 0x11B */
5840 __IO uint8_t DCHPRI31; /**< Channel n Priority Register, offset: 0x11C */
5841 __IO uint8_t DCHPRI30; /**< Channel n Priority Register, offset: 0x11D */
5842 __IO uint8_t DCHPRI29; /**< Channel n Priority Register, offset: 0x11E */
5843 __IO uint8_t DCHPRI28; /**< Channel n Priority Register, offset: 0x11F */
5844 uint8_t RESERVED_7[3808];
5845 struct { /* offset: 0x1000, array step: 0x20 */
5846 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
5847 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
5848 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
5849 union { /* offset: 0x1008, array step: 0x20 */
5850 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
5851 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
5852 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
5853 };
5854 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
5855 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
5856 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
5857 union { /* offset: 0x1016, array step: 0x20 */
5858 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
5859 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
5860 };
5861 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
5862 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
5863 union { /* offset: 0x101E, array step: 0x20 */
5864 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
5865 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
5866 };
5867 } TCD[32];
5868} DMA_Type;
5869
5870/* ----------------------------------------------------------------------------
5871 -- DMA Register Masks
5872 ---------------------------------------------------------------------------- */
5873
5874/*!
5875 * @addtogroup DMA_Register_Masks DMA Register Masks
5876 * @{
5877 */
5878
5879/*! @name CR - Control Register */
5880/*! @{ */
5881#define DMA_CR_EDBG_MASK (0x2U)
5882#define DMA_CR_EDBG_SHIFT (1U)
5883/*! EDBG - Enable Debug
5884 * 0b0..When in debug mode, the DMA continues to operate.
5885 * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
5886 */
5887#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
5888#define DMA_CR_ERCA_MASK (0x4U)
5889#define DMA_CR_ERCA_SHIFT (2U)
5890/*! ERCA - Enable Round Robin Channel Arbitration
5891 * 0b0..Fixed priority arbitration is used for channel selection within each group.
5892 * 0b1..Round robin arbitration is used for channel selection within each group.
5893 */
5894#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
5895#define DMA_CR_ERGA_MASK (0x8U)
5896#define DMA_CR_ERGA_SHIFT (3U)
5897/*! ERGA - Enable Round Robin Group Arbitration
5898 * 0b0..Fixed priority arbitration is used for selection among the groups.
5899 * 0b1..Round robin arbitration is used for selection among the groups.
5900 */
5901#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
5902#define DMA_CR_HOE_MASK (0x10U)
5903#define DMA_CR_HOE_SHIFT (4U)
5904/*! HOE - Halt On Error
5905 * 0b0..Normal operation
5906 * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
5907 */
5908#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
5909#define DMA_CR_HALT_MASK (0x20U)
5910#define DMA_CR_HALT_SHIFT (5U)
5911/*! HALT - Halt DMA Operations
5912 * 0b0..Normal operation
5913 * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
5914 */
5915#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
5916#define DMA_CR_CLM_MASK (0x40U)
5917#define DMA_CR_CLM_SHIFT (6U)
5918/*! CLM - Continuous Link Mode
5919 * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again.
5920 * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.
5921 */
5922#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
5923#define DMA_CR_EMLM_MASK (0x80U)
5924#define DMA_CR_EMLM_SHIFT (7U)
5925/*! EMLM - Enable Minor Loop Mapping
5926 * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
5927 * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.
5928 */
5929#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
5930#define DMA_CR_GRP0PRI_MASK (0x100U)
5931#define DMA_CR_GRP0PRI_SHIFT (8U)
5932#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
5933#define DMA_CR_GRP1PRI_MASK (0x400U)
5934#define DMA_CR_GRP1PRI_SHIFT (10U)
5935#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
5936#define DMA_CR_ECX_MASK (0x10000U)
5937#define DMA_CR_ECX_SHIFT (16U)
5938/*! ECX - Error Cancel Transfer
5939 * 0b0..Normal operation
5940 * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.
5941 */
5942#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
5943#define DMA_CR_CX_MASK (0x20000U)
5944#define DMA_CR_CX_SHIFT (17U)
5945/*! CX - Cancel Transfer
5946 * 0b0..Normal operation
5947 * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
5948 */
5949#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
5950/*! @} */
5951
5952/*! @name ES - Error Status Register */
5953/*! @{ */
5954#define DMA_ES_DBE_MASK (0x1U)
5955#define DMA_ES_DBE_SHIFT (0U)
5956/*! DBE - Destination Bus Error
5957 * 0b0..No destination bus error
5958 * 0b1..The last recorded error was a bus error on a destination write
5959 */
5960#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
5961#define DMA_ES_SBE_MASK (0x2U)
5962#define DMA_ES_SBE_SHIFT (1U)
5963/*! SBE - Source Bus Error
5964 * 0b0..No source bus error
5965 * 0b1..The last recorded error was a bus error on a source read
5966 */
5967#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
5968#define DMA_ES_SGE_MASK (0x4U)
5969#define DMA_ES_SGE_SHIFT (2U)
5970/*! SGE - Scatter/Gather Configuration Error
5971 * 0b0..No scatter/gather configuration error
5972 * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
5973 */
5974#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
5975#define DMA_ES_NCE_MASK (0x8U)
5976#define DMA_ES_NCE_SHIFT (3U)
5977/*! NCE - NBYTES/CITER Configuration Error
5978 * 0b0..No NBYTES/CITER configuration error
5979 * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
5980 */
5981#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
5982#define DMA_ES_DOE_MASK (0x10U)
5983#define DMA_ES_DOE_SHIFT (4U)
5984/*! DOE - Destination Offset Error
5985 * 0b0..No destination offset configuration error
5986 * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
5987 */
5988#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
5989#define DMA_ES_DAE_MASK (0x20U)
5990#define DMA_ES_DAE_SHIFT (5U)
5991/*! DAE - Destination Address Error
5992 * 0b0..No destination address configuration error
5993 * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
5994 */
5995#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
5996#define DMA_ES_SOE_MASK (0x40U)
5997#define DMA_ES_SOE_SHIFT (6U)
5998/*! SOE - Source Offset Error
5999 * 0b0..No source offset configuration error
6000 * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
6001 */
6002#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
6003#define DMA_ES_SAE_MASK (0x80U)
6004#define DMA_ES_SAE_SHIFT (7U)
6005/*! SAE - Source Address Error
6006 * 0b0..No source address configuration error.
6007 * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
6008 */
6009#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
6010#define DMA_ES_ERRCHN_MASK (0x1F00U)
6011#define DMA_ES_ERRCHN_SHIFT (8U)
6012#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
6013#define DMA_ES_CPE_MASK (0x4000U)
6014#define DMA_ES_CPE_SHIFT (14U)
6015/*! CPE - Channel Priority Error
6016 * 0b0..No channel priority error
6017 * 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique.
6018 */
6019#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
6020#define DMA_ES_GPE_MASK (0x8000U)
6021#define DMA_ES_GPE_SHIFT (15U)
6022/*! GPE - Group Priority Error
6023 * 0b0..No group priority error
6024 * 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique.
6025 */
6026#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
6027#define DMA_ES_ECX_MASK (0x10000U)
6028#define DMA_ES_ECX_SHIFT (16U)
6029/*! ECX - Transfer Canceled
6030 * 0b0..No canceled transfers
6031 * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input
6032 */
6033#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
6034#define DMA_ES_VLD_MASK (0x80000000U)
6035#define DMA_ES_VLD_SHIFT (31U)
6036/*! VLD
6037 * 0b0..No ERR bits are set.
6038 * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.
6039 */
6040#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
6041/*! @} */
6042
6043/*! @name ERQ - Enable Request Register */
6044/*! @{ */
6045#define DMA_ERQ_ERQ0_MASK (0x1U)
6046#define DMA_ERQ_ERQ0_SHIFT (0U)
6047/*! ERQ0 - Enable DMA Request 0
6048 * 0b0..The DMA request signal for the corresponding channel is disabled
6049 * 0b1..The DMA request signal for the corresponding channel is enabled
6050 */
6051#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
6052#define DMA_ERQ_ERQ1_MASK (0x2U)
6053#define DMA_ERQ_ERQ1_SHIFT (1U)
6054/*! ERQ1 - Enable DMA Request 1
6055 * 0b0..The DMA request signal for the corresponding channel is disabled
6056 * 0b1..The DMA request signal for the corresponding channel is enabled
6057 */
6058#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
6059#define DMA_ERQ_ERQ2_MASK (0x4U)
6060#define DMA_ERQ_ERQ2_SHIFT (2U)
6061/*! ERQ2 - Enable DMA Request 2
6062 * 0b0..The DMA request signal for the corresponding channel is disabled
6063 * 0b1..The DMA request signal for the corresponding channel is enabled
6064 */
6065#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
6066#define DMA_ERQ_ERQ3_MASK (0x8U)
6067#define DMA_ERQ_ERQ3_SHIFT (3U)
6068/*! ERQ3 - Enable DMA Request 3
6069 * 0b0..The DMA request signal for the corresponding channel is disabled
6070 * 0b1..The DMA request signal for the corresponding channel is enabled
6071 */
6072#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
6073#define DMA_ERQ_ERQ4_MASK (0x10U)
6074#define DMA_ERQ_ERQ4_SHIFT (4U)
6075/*! ERQ4 - Enable DMA Request 4
6076 * 0b0..The DMA request signal for the corresponding channel is disabled
6077 * 0b1..The DMA request signal for the corresponding channel is enabled
6078 */
6079#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
6080#define DMA_ERQ_ERQ5_MASK (0x20U)
6081#define DMA_ERQ_ERQ5_SHIFT (5U)
6082/*! ERQ5 - Enable DMA Request 5
6083 * 0b0..The DMA request signal for the corresponding channel is disabled
6084 * 0b1..The DMA request signal for the corresponding channel is enabled
6085 */
6086#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
6087#define DMA_ERQ_ERQ6_MASK (0x40U)
6088#define DMA_ERQ_ERQ6_SHIFT (6U)
6089/*! ERQ6 - Enable DMA Request 6
6090 * 0b0..The DMA request signal for the corresponding channel is disabled
6091 * 0b1..The DMA request signal for the corresponding channel is enabled
6092 */
6093#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
6094#define DMA_ERQ_ERQ7_MASK (0x80U)
6095#define DMA_ERQ_ERQ7_SHIFT (7U)
6096/*! ERQ7 - Enable DMA Request 7
6097 * 0b0..The DMA request signal for the corresponding channel is disabled
6098 * 0b1..The DMA request signal for the corresponding channel is enabled
6099 */
6100#define DMA_ERQ_ERQ7(x) (((uint32_t)(