1 files changed, 181 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/project_template/clock_config.c
new file mode 100644
index 000000000..833423d81
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/project_template/clock_config.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright 2018 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
+ *    and flash clock are in allowed range during clock mode switch.
+ *
+ * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
+ *
+ * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
+ *    internal reference clock(MCGIRCLK). Follow the steps to setup:
+ *
+ *    1). Call CLOCK_BootToXxxMode to set MCG to target mode.
+ *
+ *    2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
+ *        correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
+ *        explicitly to setup MCGIRCLK.
+ *
+ *    3). Don't need to configure FLL explicitly, because if target mode is FLL
+ *        mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
+ *        if the target mode is not FLL mode, the FLL is disabled.
+ *
+ *    4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
+ *        setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
+ *        be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
+ *
+ * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
+ */
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v5.0
+processor: MK28FN2M0Axxx15
+mcu_data: ksdk2_0
+processor_version: 0.0.5
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+#include "clock_config.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define MCG_IRCLK_DISABLE                                 0U  /*!< MCGIRCLK disabled */
+#define MCG_PLL_DISABLE                                   0U  /*!< MCGPLLCLK disabled */
+#define OSC_CAP0P                                         0U  /*!< Oscillator 0pF capacitor load */
+#define OSC_ER_CLK_DISABLE                                0U  /*!< Disable external reference clock */
+#define SIM_OSC32KSEL_OSC32KCLK_CLK                       0U  /*!< OSC32KSEL select: OSC32KCLK clock */
+#define SIM_PLLFLLSEL_MCGFLLCLK_CLK                       0U  /*!< PLLFLL select: MCGFLLCLK clock */
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_FllStableDelay
+ * Description   : This function is used to delay for FLL stable.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_FllStableDelay(void)
+{
+    uint32_t i = 30000U;
+    while (i--)
+    {
+        __NOP();
+    }
+}
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: Bus_clock.outFreq, value: 20.97152 MHz}
+- {id: Core_clock.outFreq, value: 20.97152 MHz}
+- {id: Flash_clock.outFreq, value: 10.48576 MHz}
+- {id: FlexBus_clock.outFreq, value: 20.97152 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGFFCLK.outFreq, value: 32.768 kHz}
+- {id: MCGFLLCLK.outFreq, value: 20.97152 MHz}
+- {id: PLLFLLCLK.outFreq, value: 20.97152 MHz}
+- {id: System_clock.outFreq, value: 20.97152 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockRUN =
+    {
+        .mcgMode = kMCG_ModeFEI,                  /* FEI - FLL Engaged Internal */
+        .irclkEnableMode = MCG_IRCLK_DISABLE,     /* MCGIRCLK disabled */
+        .ircs = kMCG_IrcSlow,                     /* Slow internal reference clock selected */
+        .fcrdiv = 0x1U,                           /* Fast IRC divider: divided by 2 */
+        .frdiv = 0x0U,                            /* FLL reference clock divider: divided by 1 */
+        .drs = kMCG_DrsLow,                       /* Low frequency range */
+        .dmx32 = kMCG_Dmx32Default,               /* DCO has a default range of 25% */
+        .oscsel = kMCG_OscselOsc,                 /* Selects System Oscillator (OSCCLK) */
+        .pll0Config =
+            {
+                .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
+                .prdiv = 0x0U,                    /* PLL Reference divider: divided by 1 */
+                .vdiv = 0x0U,                     /* VCO divider: multiplied by 16 */
+            },
+        .pllcs = kMCG_PllClkSelPll0,              /* PLL0 output clock is selected */
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockRUN =
+    {
+        .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
+        .pllFllDiv = 0,                           /* PLLFLLSEL clock divider divisor: divided by 1 */
+        .pllFllFrac = 0,                          /* PLLFLLSEL clock divider fraction: multiplied by 1 */
+        .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK,  /* OSC32KSEL select: OSC32KCLK clock */
+        .clkdiv1 = 0x10000U,                      /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /2 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockRUN =
+    {
+        .freq = 0U,                               /* Oscillator frequency: 0Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeExt,                 /* Use external clock */
+        .oscerConfig =
+            {
+                .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+                .erclkDiv = 0,                    /* Divider for OSCERCLK: divided by 1 */
+            }
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Configure the Internal Reference clock (MCGIRCLK). */
+    CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
+                                  mcgConfig_BOARD_BootClockRUN.ircs, 
+                                  mcgConfig_BOARD_BootClockRUN.fcrdiv);
+    /* Set MCG to FEI mode. */
+#if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
+    CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.dmx32,
+                        mcgConfig_BOARD_BootClockRUN.drs,
+                        CLOCK_CONFIG_FllStableDelay);
+#else
+    CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.drs,
+                        CLOCK_CONFIG_FllStableDelay);
+#endif
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}

diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/project_template/clock_config.c new file mode 100644 index 000000000..833423d81 --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MK28FA15/project_template/clock_config.c
@@ -0,0 +1,181 @@
	1	/*
	2	* Copyright 2018 NXP.
	3	* All rights reserved.
	4	*
	5	* SPDX-License-Identifier: BSD-3-Clause
	6	*/
	7
	8	/***********************************************************************************************************************
	9	* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
	10	* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
	11	**********************************************************************************************************************/
	12	/*
	13	* How to setup clock using clock driver functions:
	14	*
	15	* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
	16	* and flash clock are in allowed range during clock mode switch.
	17	*
	18	* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
	19	*
	20	* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
	21	* internal reference clock(MCGIRCLK). Follow the steps to setup:
	22	*
	23	* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
	24	*
	25	* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
	26	* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
	27	* explicitly to setup MCGIRCLK.
	28	*
	29	* 3). Don't need to configure FLL explicitly, because if target mode is FLL
	30	* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
	31	* if the target mode is not FLL mode, the FLL is disabled.
	32	*
	33	* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
	34	* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
	35	* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
	36	*
	37	* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
	38	*/
	39
	40	/* clang-format off */
	41	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	42	!!GlobalInfo
	43	product: Clocks v5.0
	44	processor: MK28FN2M0Axxx15
	45	mcu_data: ksdk2_0
	46	processor_version: 0.0.5
	47	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	48	/* clang-format on */
	49
	50	#include "clock_config.h"
	51
	52	/*******************************************************************************
	53	* Definitions
	54	******************************************************************************/
	55	#define MCG_IRCLK_DISABLE 0U /!< MCGIRCLK disabled /
	56	#define MCG_PLL_DISABLE 0U /!< MCGPLLCLK disabled /
	57	#define OSC_CAP0P 0U /!< Oscillator 0pF capacitor load /
	58	#define OSC_ER_CLK_DISABLE 0U /!< Disable external reference clock /
	59	#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /!< OSC32KSEL select: OSC32KCLK clock /
	60	#define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /!< PLLFLL select: MCGFLLCLK clock /
	61
	62	/*******************************************************************************
	63	* Variables
	64	******************************************************************************/
	65	/* System clock frequency. */
	66	extern uint32_t SystemCoreClock;
	67
	68	/*******************************************************************************
	69	* Code
	70	******************************************************************************/
	71	/FUNCTION*********************************************************************
	72	*
	73	* Function Name : CLOCK_CONFIG_FllStableDelay
	74	* Description : This function is used to delay for FLL stable.
	75	*
	76	END*************************************************************************/
	77	static void CLOCK_CONFIG_FllStableDelay(void)
	78	{
	79	uint32_t i = 30000U;
	80	while (i--)
	81	{
	82	__NOP();
	83	}
	84	}
	85
	86	/*******************************************************************************
	87	********************** BOARD_InitBootClocks function **********************
	88	******************************************************************************/
	89	void BOARD_InitBootClocks(void)
	90	{
	91	BOARD_BootClockRUN();
	92	}
	93
	94	/*******************************************************************************
	95	******************** Configuration BOARD_BootClockRUN *********************
	96	******************************************************************************/
	97	/* clang-format off */
	98	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	99	!!Configuration
	100	name: BOARD_BootClockRUN
	101	called_from_default_init: true
	102	outputs:
	103	- {id: Bus_clock.outFreq, value: 20.97152 MHz}
	104	- {id: Core_clock.outFreq, value: 20.97152 MHz}
	105	- {id: Flash_clock.outFreq, value: 10.48576 MHz}
	106	- {id: FlexBus_clock.outFreq, value: 20.97152 MHz}
	107	- {id: LPO_clock.outFreq, value: 1 kHz}
	108	- {id: MCGFFCLK.outFreq, value: 32.768 kHz}
	109	- {id: MCGFLLCLK.outFreq, value: 20.97152 MHz}
	110	- {id: PLLFLLCLK.outFreq, value: 20.97152 MHz}
	111	- {id: System_clock.outFreq, value: 20.97152 MHz}
	112	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	113	/* clang-format on */
	114
	115	/*******************************************************************************
	116	* Variables for BOARD_BootClockRUN configuration
	117	******************************************************************************/
	118	const mcg_config_t mcgConfig_BOARD_BootClockRUN =
	119	{
	120	.mcgMode = kMCG_ModeFEI, /* FEI - FLL Engaged Internal */
	121	.irclkEnableMode = MCG_IRCLK_DISABLE, /* MCGIRCLK disabled */
	122	.ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
	123	.fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */
	124	.frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
	125	.drs = kMCG_DrsLow, /* Low frequency range */
	126	.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
	127	.oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
	128	.pll0Config =
	129	{
	130	.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
	131	.prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
	132	.vdiv = 0x0U, /* VCO divider: multiplied by 16 */
	133	},
	134	.pllcs = kMCG_PllClkSelPll0, /* PLL0 output clock is selected */
	135	};
	136	const sim_clock_config_t simConfig_BOARD_BootClockRUN =
	137	{
	138	.pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
	139	.pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */
	140	.pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
	141	.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
	142	.clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /2 */
	143	};
	144	const osc_config_t oscConfig_BOARD_BootClockRUN =
	145	{
	146	.freq = 0U, /* Oscillator frequency: 0Hz */
	147	.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
	148	.workMode = kOSC_ModeExt, /* Use external clock */
	149	.oscerConfig =
	150	{
	151	.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
	152	.erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
	153	}
	154	};
	155
	156	/*******************************************************************************
	157	* Code for BOARD_BootClockRUN configuration
	158	******************************************************************************/
	159	void BOARD_BootClockRUN(void)
	160	{
	161	/* Set the system clock dividers in SIM to safe value. */
	162	CLOCK_SetSimSafeDivs();
	163	/* Configure the Internal Reference clock (MCGIRCLK). */
	164	CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
	165	mcgConfig_BOARD_BootClockRUN.ircs,
	166	mcgConfig_BOARD_BootClockRUN.fcrdiv);
	167	/* Set MCG to FEI mode. */
	168	#if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
	169	CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.dmx32,
	170	mcgConfig_BOARD_BootClockRUN.drs,
	171	CLOCK_CONFIG_FllStableDelay);
	172	#else
	173	CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.drs,
	174	CLOCK_CONFIG_FllStableDelay);
	175	#endif
	176	/* Set the clock configuration in SIM module. */
	177	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
	178	/* Set SystemCoreClock variable. */
	179	SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
	180	}
	181