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1/*
2** ###################################################################
3** Processors: MK64FN1M0CAJ12
4** MK64FN1M0VDC12
5** MK64FN1M0VLL12
6** MK64FN1M0VLQ12
7** MK64FN1M0VMD12
8** MK64FX512VDC12
9** MK64FX512VLL12
10** MK64FX512VLQ12
11** MK64FX512VMD12
12**
13** Compilers: Freescale C/C++ for Embedded ARM
14** GNU C Compiler
15** IAR ANSI C/C++ Compiler for ARM
16** Keil ARM C/C++ Compiler
17** MCUXpresso Compiler
18**
19** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
20** Version: rev. 2.9, 2016-03-21
21** Build: b181105
22**
23** Abstract:
24** Provides a system configuration function and a global variable that
25** contains the system frequency. It configures the device and initializes
26** the oscillator (PLL) that is part of the microcontroller device.
27**
28** Copyright 2016 Freescale Semiconductor, Inc.
29** Copyright 2016-2018 NXP
30** All rights reserved.
31**
32** SPDX-License-Identifier: BSD-3-Clause
33**
34** http: www.nxp.com
35** mail: [email protected]
36**
37** Revisions:
38** - rev. 1.0 (2013-08-12)
39** Initial version.
40** - rev. 2.0 (2013-10-29)
41** Register accessor macros added to the memory map.
42** Symbols for Processor Expert memory map compatibility added to the memory map.
43** Startup file for gcc has been updated according to CMSIS 3.2.
44** System initialization updated.
45** MCG - registers updated.
46** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
47** - rev. 2.1 (2013-10-30)
48** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
49** - rev. 2.2 (2013-12-09)
50** DMA - EARS register removed.
51** AIPS0, AIPS1 - MPRA register updated.
52** - rev. 2.3 (2014-01-24)
53** Update according to reference manual rev. 2
54** ENET, MCG, MCM, SIM, USB - registers updated
55** - rev. 2.4 (2014-02-10)
56** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
57** Update of SystemInit() and SystemCoreClockUpdate() functions.
58** - rev. 2.5 (2014-02-10)
59** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
60** Update of SystemInit() and SystemCoreClockUpdate() functions.
61** Module access macro module_BASES replaced by module_BASE_PTRS.
62** - rev. 2.6 (2014-08-28)
63** Update of system files - default clock configuration changed.
64** Update of startup files - possibility to override DefaultISR added.
65** - rev. 2.7 (2014-10-14)
66** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
67** - rev. 2.8 (2015-02-19)
68** Renamed interrupt vector LLW to LLWU.
69** - rev. 2.9 (2016-03-21)
70** Added MK64FN1M0CAJ12 part.
71** GPIO - renamed port instances: PTx -> GPIOx.
72**
73** ###################################################################
74*/
75
76/*!
77 * @file MK64F12
78 * @version 2.9
79 * @date 2016-03-21
80 * @brief Device specific configuration file for MK64F12 (implementation file)
81 *
82 * Provides a system configuration function and a global variable that contains
83 * the system frequency. It configures the device and initializes the oscillator
84 * (PLL) that is part of the microcontroller device.
85 */
86
87#include <stdint.h>
88#include "fsl_device_registers.h"
89
90
91
92/* ----------------------------------------------------------------------------
93 -- Core clock
94 ---------------------------------------------------------------------------- */
95
96uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
97
98/* ----------------------------------------------------------------------------
99 -- SystemInit()
100 ---------------------------------------------------------------------------- */
101
102void SystemInit (void) {
103#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
104 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
105#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
106#if (DISABLE_WDOG)
107 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
108 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
109 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
110 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
111 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
112 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
113 WDOG_STCTRLH_WAITEN_MASK |
114 WDOG_STCTRLH_STOPEN_MASK |
115 WDOG_STCTRLH_ALLOWUPDATE_MASK |
116 WDOG_STCTRLH_CLKSRC_MASK |
117 0x0100U;
118#endif /* (DISABLE_WDOG) */
119
120 SystemInitHook();
121}
122
123/* ----------------------------------------------------------------------------
124 -- SystemCoreClockUpdate()
125 ---------------------------------------------------------------------------- */
126
127void SystemCoreClockUpdate (void) {
128 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
129 uint16_t Divider;
130 uint8_t tmpC7 = 0;
131
132 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
133 /* Output of FLL or PLL is selected */
134 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
135 /* FLL is selected */
136 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
137 /* External reference clock is selected */
138 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
139 case 0x00U:
140 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
141 break;
142 case 0x01U:
143 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
144 break;
145 case 0x02U:
146 default:
147 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
148 break;
149 }
150 tmpC7 = MCG->C7;
151 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
152 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
153 case 0x38U:
154 Divider = 1536U;
155 break;
156 case 0x30U:
157 Divider = 1280U;
158 break;
159 default:
160 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
161 break;
162 }
163 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
164 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
165 }
166 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
167 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
168 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
169 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
170 /* Select correct multiplier to calculate the MCG output clock */
171 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
172 case 0x00U:
173 MCGOUTClock *= 640U;
174 break;
175 case 0x20U:
176 MCGOUTClock *= 1280U;
177 break;
178 case 0x40U:
179 MCGOUTClock *= 1920U;
180 break;
181 case 0x60U:
182 MCGOUTClock *= 2560U;
183 break;
184 case 0x80U:
185 MCGOUTClock *= 732U;
186 break;
187 case 0xA0U:
188 MCGOUTClock *= 1464U;
189 break;
190 case 0xC0U:
191 MCGOUTClock *= 2197U;
192 break;
193 case 0xE0U:
194 MCGOUTClock *= 2929U;
195 break;
196 default:
197 MCGOUTClock *= 640U;
198 break;
199 }
200 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
201 /* PLL is selected */
202 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
203 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
204 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
205 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
206 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
207 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
208 /* Internal reference clock is selected */
209 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
210 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
211 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
212 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
213 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
214 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
215 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
216 /* External reference clock is selected */
217 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
218 case 0x00U:
219 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
220 break;
221 case 0x01U:
222 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
223 break;
224 case 0x02U:
225 default:
226 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
227 break;
228 }
229 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
230 /* Reserved value */
231 return;
232 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
233 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
234}
235
236/* ----------------------------------------------------------------------------
237 -- SystemInitHook()
238 ---------------------------------------------------------------------------- */
239
240__attribute__ ((weak)) void SystemInitHook (void) {
241 /* Void implementation of the weak function. */
242}
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