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Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/MK64F12')
38 files changed, 35293 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MK64F12/MK64F12.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MK64F12/MK64F12.h new file mode 100644 index 000000000..0756881fc --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MK64F12/MK64F12.h | |||
| @@ -0,0 +1,22404 @@ | |||
| 1 | /* | ||
| 2 | ** ################################################################### | ||
| 3 | ** Processors: MK64FN1M0CAJ12 | ||
| 4 | ** MK64FN1M0VDC12 | ||
| 5 | ** MK64FN1M0VLL12 | ||
| 6 | ** MK64FN1M0VLQ12 | ||
| 7 | ** MK64FN1M0VMD12 | ||
| 8 | ** MK64FX512VDC12 | ||
| 9 | ** MK64FX512VLL12 | ||
| 10 | ** MK64FX512VLQ12 | ||
| 11 | ** MK64FX512VMD12 | ||
| 12 | ** | ||
| 13 | ** Compilers: Keil ARM C/C++ Compiler | ||
| 14 | ** Freescale C/C++ for Embedded ARM | ||
| 15 | ** GNU C Compiler | ||
| 16 | ** IAR ANSI C/C++ Compiler for ARM | ||
| 17 | ** MCUXpresso Compiler | ||
| 18 | ** | ||
| 19 | ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 | ||
| 20 | ** Version: rev. 2.9, 2016-03-21 | ||
| 21 | ** Build: b180801 | ||
| 22 | ** | ||
| 23 | ** Abstract: | ||
| 24 | ** CMSIS Peripheral Access Layer for MK64F12 | ||
| 25 | ** | ||
| 26 | ** Copyright 1997-2016 Freescale Semiconductor, Inc. | ||
| 27 | ** Copyright 2016-2018 NXP | ||
| 28 | ** | ||
| 29 | ** SPDX-License-Identifier: BSD-3-Clause | ||
| 30 | ** | ||
| 31 | ** http: www.nxp.com | ||
| 32 | ** mail: [email protected] | ||
| 33 | ** | ||
| 34 | ** Revisions: | ||
| 35 | ** - rev. 1.0 (2013-08-12) | ||
| 36 | ** Initial version. | ||
| 37 | ** - rev. 2.0 (2013-10-29) | ||
| 38 | ** Register accessor macros added to the memory map. | ||
| 39 | ** Symbols for Processor Expert memory map compatibility added to the memory map. | ||
| 40 | ** Startup file for gcc has been updated according to CMSIS 3.2. | ||
| 41 | ** System initialization updated. | ||
| 42 | ** MCG - registers updated. | ||
| 43 | ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. | ||
| 44 | ** - rev. 2.1 (2013-10-30) | ||
| 45 | ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. | ||
| 46 | ** - rev. 2.2 (2013-12-09) | ||
| 47 | ** DMA - EARS register removed. | ||
| 48 | ** AIPS0, AIPS1 - MPRA register updated. | ||
| 49 | ** - rev. 2.3 (2014-01-24) | ||
| 50 | ** Update according to reference manual rev. 2 | ||
| 51 | ** ENET, MCG, MCM, SIM, USB - registers updated | ||
| 52 | ** - rev. 2.4 (2014-02-10) | ||
| 53 | ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h | ||
| 54 | ** Update of SystemInit() and SystemCoreClockUpdate() functions. | ||
| 55 | ** - rev. 2.5 (2014-02-10) | ||
| 56 | ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h | ||
| 57 | ** Update of SystemInit() and SystemCoreClockUpdate() functions. | ||
| 58 | ** Module access macro module_BASES replaced by module_BASE_PTRS. | ||
| 59 | ** - rev. 2.6 (2014-08-28) | ||
| 60 | ** Update of system files - default clock configuration changed. | ||
| 61 | ** Update of startup files - possibility to override DefaultISR added. | ||
| 62 | ** - rev. 2.7 (2014-10-14) | ||
| 63 | ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. | ||
| 64 | ** - rev. 2.8 (2015-02-19) | ||
| 65 | ** Renamed interrupt vector LLW to LLWU. | ||
| 66 | ** - rev. 2.9 (2016-03-21) | ||
| 67 | ** Added MK64FN1M0CAJ12 part. | ||
| 68 | ** GPIO - renamed port instances: PTx -> GPIOx. | ||
| 69 | ** | ||
| 70 | ** ################################################################### | ||
| 71 | */ | ||
| 72 | |||
| 73 | /*! | ||
| 74 | * @file MK64F12.h | ||
| 75 | * @version 2.9 | ||
| 76 | * @date 2016-03-21 | ||
| 77 | * @brief CMSIS Peripheral Access Layer for MK64F12 | ||
| 78 | * | ||
| 79 | * CMSIS Peripheral Access Layer for MK64F12 | ||
| 80 | */ | ||
| 81 | |||
| 82 | #ifndef _MK64F12_H_ | ||
| 83 | #define _MK64F12_H_ /**< Symbol preventing repeated inclusion */ | ||
| 84 | |||
| 85 | /** Memory map major version (memory maps with equal major version number are | ||
| 86 | * compatible) */ | ||
| 87 | #define MCU_MEM_MAP_VERSION 0x0200U | ||
| 88 | /** Memory map minor version */ | ||
| 89 | #define MCU_MEM_MAP_VERSION_MINOR 0x0009U | ||
| 90 | |||
| 91 | /** | ||
| 92 | * @brief Macro to calculate address of an aliased word in the peripheral | ||
| 93 | * bitband area for a peripheral register and bit (bit band region 0x40000000 to | ||
| 94 | * 0x400FFFFF). | ||
| 95 | * @param Reg Register to access. | ||
| 96 | * @param Bit Bit number to access. | ||
| 97 | * @return Address of the aliased word in the peripheral bitband area. | ||
| 98 | */ | ||
| 99 | #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) | ||
| 100 | /** | ||
| 101 | * @brief Macro to access a single bit of a peripheral register (bit band region | ||
| 102 | * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can | ||
| 103 | * be used for peripherals with 32bit access allowed. | ||
| 104 | * @param Reg Register to access. | ||
| 105 | * @param Bit Bit number to access. | ||
| 106 | * @return Value of the targeted bit in the bit band region. | ||
| 107 | */ | ||
| 108 | #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) | ||
| 109 | #define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit))) | ||
| 110 | /** | ||
| 111 | * @brief Macro to access a single bit of a peripheral register (bit band region | ||
| 112 | * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can | ||
| 113 | * be used for peripherals with 16bit access allowed. | ||
| 114 | * @param Reg Register to access. | ||
| 115 | * @param Bit Bit number to access. | ||
| 116 | * @return Value of the targeted bit in the bit band region. | ||
| 117 | */ | ||
| 118 | #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) | ||
| 119 | /** | ||
| 120 | * @brief Macro to access a single bit of a peripheral register (bit band region | ||
| 121 | * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can | ||
| 122 | * be used for peripherals with 8bit access allowed. | ||
| 123 | * @param Reg Register to access. | ||
| 124 | * @param Bit Bit number to access. | ||
| 125 | * @return Value of the targeted bit in the bit band region. | ||
| 126 | */ | ||
| 127 | #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) | ||
| 128 | |||
| 129 | /* ---------------------------------------------------------------------------- | ||
| 130 | -- Interrupt vector numbers | ||
| 131 | ---------------------------------------------------------------------------- */ | ||
| 132 | |||
| 133 | /*! | ||
| 134 | * @addtogroup Interrupt_vector_numbers Interrupt vector numbers | ||
| 135 | * @{ | ||
| 136 | */ | ||
| 137 | |||
| 138 | /** Interrupt Number Definitions */ | ||
| 139 | #define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */ | ||
| 140 | |||
| 141 | typedef enum IRQn { | ||
| 142 | /* Auxiliary constants */ | ||
| 143 | NotAvail_IRQn = -128, /**< Not available device specific interrupt */ | ||
| 144 | |||
| 145 | /* Core interrupts */ | ||
| 146 | NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ | ||
| 147 | HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ | ||
| 148 | MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ | ||
| 149 | BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ | ||
| 150 | UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ | ||
| 151 | SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ | ||
| 152 | DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ | ||
| 153 | PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ | ||
| 154 | SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ | ||
| 155 | |||
| 156 | /* Device specific interrupts */ | ||
| 157 | DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */ | ||
| 158 | DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ | ||
| 159 | DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ | ||
| 160 | DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */ | ||
| 161 | DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */ | ||
| 162 | DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */ | ||
| 163 | DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */ | ||
| 164 | DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */ | ||
| 165 | DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */ | ||
| 166 | DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */ | ||
| 167 | DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */ | ||
| 168 | DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */ | ||
| 169 | DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */ | ||
| 170 | DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */ | ||
| 171 | DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */ | ||
| 172 | DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */ | ||
| 173 | DMA_Error_IRQn = 16, /**< DMA Error Interrupt */ | ||
| 174 | MCM_IRQn = 17, /**< Normal Interrupt */ | ||
| 175 | FTFE_IRQn = 18, /**< FTFE Command complete interrupt */ | ||
| 176 | Read_Collision_IRQn = 19, /**< Read Collision Interrupt */ | ||
| 177 | LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ | ||
| 178 | LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */ | ||
| 179 | WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */ | ||
| 180 | RNG_IRQn = 23, /**< RNG Interrupt */ | ||
| 181 | I2C0_IRQn = 24, /**< I2C0 interrupt */ | ||
| 182 | I2C1_IRQn = 25, /**< I2C1 interrupt */ | ||
| 183 | SPI0_IRQn = 26, /**< SPI0 Interrupt */ | ||
| 184 | SPI1_IRQn = 27, /**< SPI1 Interrupt */ | ||
| 185 | I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */ | ||
| 186 | I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */ | ||
| 187 | UART0_LON_IRQn = 30, /**< UART0 LON interrupt */ | ||
| 188 | UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */ | ||
| 189 | UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */ | ||
| 190 | UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */ | ||
| 191 | UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */ | ||
| 192 | UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */ | ||
| 193 | UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */ | ||
| 194 | UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */ | ||
| 195 | UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */ | ||
| 196 | ADC0_IRQn = 39, /**< ADC0 interrupt */ | ||
| 197 | CMP0_IRQn = 40, /**< CMP0 interrupt */ | ||
| 198 | CMP1_IRQn = 41, /**< CMP1 interrupt */ | ||
| 199 | FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */ | ||
| 200 | FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */ | ||
| 201 | FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */ | ||
| 202 | CMT_IRQn = 45, /**< CMT interrupt */ | ||
| 203 | RTC_IRQn = 46, /**< RTC interrupt */ | ||
| 204 | RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */ | ||
| 205 | PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */ | ||
| 206 | PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */ | ||
| 207 | PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */ | ||
| 208 | PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */ | ||
| 209 | PDB0_IRQn = 52, /**< PDB0 Interrupt */ | ||
| 210 | USB0_IRQn = 53, /**< USB0 interrupt */ | ||
| 211 | USBDCD_IRQn = 54, /**< USBDCD Interrupt */ | ||
| 212 | Reserved71_IRQn = 55, /**< Reserved interrupt 71 */ | ||
| 213 | DAC0_IRQn = 56, /**< DAC0 interrupt */ | ||
| 214 | MCG_IRQn = 57, /**< MCG Interrupt */ | ||
| 215 | LPTMR0_IRQn = 58, /**< LPTimer interrupt */ | ||
| 216 | PORTA_IRQn = 59, /**< Port A interrupt */ | ||
| 217 | PORTB_IRQn = 60, /**< Port B interrupt */ | ||
| 218 | PORTC_IRQn = 61, /**< Port C interrupt */ | ||
| 219 | PORTD_IRQn = 62, /**< Port D interrupt */ | ||
| 220 | PORTE_IRQn = 63, /**< Port E interrupt */ | ||
| 221 | SWI_IRQn = 64, /**< Software interrupt */ | ||
| 222 | SPI2_IRQn = 65, /**< SPI2 Interrupt */ | ||
| 223 | UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */ | ||
| 224 | UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */ | ||
| 225 | UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */ | ||
| 226 | UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */ | ||
| 227 | CMP2_IRQn = 70, /**< CMP2 interrupt */ | ||
| 228 | FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */ | ||
| 229 | DAC1_IRQn = 72, /**< DAC1 interrupt */ | ||
| 230 | ADC1_IRQn = 73, /**< ADC1 interrupt */ | ||
| 231 | I2C2_IRQn = 74, /**< I2C2 interrupt */ | ||
| 232 | CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */ | ||
| 233 | CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */ | ||
| 234 | CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */ | ||
| 235 | CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */ | ||
| 236 | CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */ | ||
| 237 | CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */ | ||
| 238 | SDHC_IRQn = 81, /**< SDHC interrupt */ | ||
| 239 | ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */ | ||
| 240 | ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */ | ||
| 241 | ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */ | ||
| 242 | ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */ | ||
| 243 | } IRQn_Type; | ||
| 244 | |||
| 245 | /*! | ||
| 246 | * @} | ||
| 247 | */ /* end of group Interrupt_vector_numbers */ | ||
| 248 | |||
| 249 | |||
| 250 | /* ---------------------------------------------------------------------------- | ||
| 251 | -- Cortex M4 Core Configuration | ||
| 252 | ---------------------------------------------------------------------------- */ | ||
| 253 | |||
| 254 | /*! | ||
| 255 | * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration | ||
| 256 | * @{ | ||
| 257 | */ | ||
| 258 | |||
| 259 | #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ | ||
| 260 | #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ | ||
| 261 | #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ | ||
| 262 | #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ | ||
| 263 | |||
| 264 | #include "core_cm4.h" /* Core Peripheral Access Layer */ | ||
| 265 | #include "system_MK64F12.h" /* Device specific configuration file */ | ||
| 266 | |||
| 267 | /*! | ||
| 268 | * @} | ||
| 269 | */ /* end of group Cortex_Core_Configuration */ | ||
| 270 | |||
| 271 | |||
| 272 | /* ---------------------------------------------------------------------------- | ||
| 273 | -- Mapping Information | ||
| 274 | ---------------------------------------------------------------------------- */ | ||
| 275 | |||
| 276 | /*! | ||
| 277 | * @addtogroup Mapping_Information Mapping Information | ||
| 278 | * @{ | ||
| 279 | */ | ||
| 280 | |||
| 281 | /** Mapping Information */ | ||
| 282 | /*! | ||
| 283 | * @addtogroup edma_request | ||
| 284 | * @{ | ||
| 285 | */ | ||
| 286 | |||
| 287 | /******************************************************************************* | ||
| 288 | * Definitions | ||
| 289 | ******************************************************************************/ | ||
| 290 | |||
| 291 | /*! | ||
| 292 | * @brief Structure for the DMA hardware request | ||
| 293 | * | ||
| 294 | * Defines the structure for the DMA hardware request collections. The user can configure the | ||
| 295 | * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index | ||
| 296 | * of the hardware request varies according to the to SoC. | ||
| 297 | */ | ||
| 298 | typedef enum _dma_request_source | ||
| 299 | { | ||
| 300 | kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ | ||
| 301 | kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ | ||
| 302 | kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */ | ||
| 303 | kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */ | ||
| 304 | kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */ | ||
| 305 | kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */ | ||
| 306 | kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */ | ||
| 307 | kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */ | ||
| 308 | kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 Receive. */ | ||
| 309 | kDmaRequestMux0UART3Tx = 9|0x100U, /**< UART3 Transmit. */ | ||
| 310 | kDmaRequestMux0UART4 = 10|0x100U, /**< UART4 Transmit or Receive. */ | ||
| 311 | kDmaRequestMux0UART5 = 11|0x100U, /**< UART5 Transmit or Receive. */ | ||
| 312 | kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */ | ||
| 313 | kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */ | ||
| 314 | kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */ | ||
| 315 | kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */ | ||
| 316 | kDmaRequestMux0SPI1 = 16|0x100U, /**< SPI1 Transmit or Receive. */ | ||
| 317 | kDmaRequestMux0SPI2 = 17|0x100U, /**< SPI2 Transmit or Receive. */ | ||
| 318 | kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0. */ | ||
| 319 | kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */ | ||
| 320 | kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */ | ||
| 321 | kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */ | ||
| 322 | kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */ | ||
| 323 | kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */ | ||
| 324 | kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */ | ||
| 325 | kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */ | ||
| 326 | kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */ | ||
| 327 | kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */ | ||
| 328 | kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */ | ||
| 329 | kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */ | ||
| 330 | kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */ | ||
| 331 | kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */ | ||
| 332 | kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */ | ||
| 333 | kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */ | ||
| 334 | kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */ | ||
| 335 | kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */ | ||
| 336 | kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */ | ||
| 337 | kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */ | ||
| 338 | kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */ | ||
| 339 | kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */ | ||
| 340 | kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V. */ | ||
| 341 | kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V. */ | ||
| 342 | kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ | ||
| 343 | kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */ | ||
| 344 | kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ | ||
| 345 | kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */ | ||
| 346 | kDmaRequestMux0CMP2 = 44|0x100U, /**< CMP2. */ | ||
| 347 | kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */ | ||
| 348 | kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1. */ | ||
| 349 | kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */ | ||
| 350 | kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */ | ||
| 351 | kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ | ||
| 352 | kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */ | ||
| 353 | kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */ | ||
| 354 | kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */ | ||
| 355 | kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */ | ||
| 356 | kDmaRequestMux0IEEE1588Timer0 = 54|0x100U, /**< ENET IEEE 1588 timer 0. */ | ||
| 357 | kDmaRequestMux0IEEE1588Timer1 = 55|0x100U, /**< ENET IEEE 1588 timer 1. */ | ||
| 358 | kDmaRequestMux0IEEE1588Timer2 = 56|0x100U, /**< ENET IEEE 1588 timer 2. */ | ||
| 359 | kDmaRequestMux0IEEE1588Timer3 = 57|0x100U, /**< ENET IEEE 1588 timer 3. */ | ||
| 360 | kDmaRequestMux0AlwaysOn58 = 58|0x100U, /**< DMAMUX Always Enabled slot. */ | ||
| 361 | kDmaRequestMux0AlwaysOn59 = 59|0x100U, /**< DMAMUX Always Enabled slot. */ | ||
| 362 | kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ | ||
| 363 | kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ | ||
| 364 | kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ | ||
| 365 | kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ | ||
| 366 | } dma_request_source_t; | ||
| 367 | |||
| 368 | /* @} */ | ||
| 369 | |||
| 370 | |||
| 371 | /*! | ||
| 372 | * @} | ||
| 373 | */ /* end of group Mapping_Information */ | ||
| 374 | |||
| 375 | |||
| 376 | /* ---------------------------------------------------------------------------- | ||
| 377 | -- Device Peripheral Access Layer | ||
| 378 | ---------------------------------------------------------------------------- */ | ||
| 379 | |||
| 380 | /*! | ||
| 381 | * @addtogroup Peripheral_access_layer Device Peripheral Access Layer | ||
| 382 | * @{ | ||
| 383 | */ | ||
| 384 | |||
| 385 | |||
| 386 | /* | ||
| 387 | ** Start of section using anonymous unions | ||
| 388 | */ | ||
| 389 | |||
| 390 | #if defined(__ARMCC_VERSION) | ||
| 391 | #if (__ARMCC_VERSION >= 6010050) | ||
| 392 | #pragma clang diagnostic push | ||
| 393 | #else | ||
| 394 | #pragma push | ||
| 395 | #pragma anon_unions | ||
| 396 | #endif | ||
| 397 | #elif defined(__CWCC__) | ||
| 398 | #pragma push | ||
| 399 | #pragma cpp_extensions on | ||
| 400 | #elif defined(__GNUC__) | ||
| 401 | /* anonymous unions are enabled by default */ | ||
| 402 | #elif defined(__IAR_SYSTEMS_ICC__) | ||
| 403 | #pragma language=extended | ||
| 404 | #else | ||
| 405 | #error Not supported compiler type | ||
| 406 | #endif | ||
| 407 | |||
| 408 | /* ---------------------------------------------------------------------------- | ||
| 409 | -- ADC Peripheral Access Layer | ||
| 410 | ---------------------------------------------------------------------------- */ | ||
| 411 | |||
| 412 | /*! | ||
| 413 | * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer | ||
| 414 | * @{ | ||
| 415 | */ | ||
| 416 | |||
| 417 | /** ADC - Register Layout Typedef */ | ||
| 418 | typedef struct { | ||
| 419 | __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ | ||
| 420 | __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ | ||
| 421 | __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ | ||
| 422 | __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ | ||
| 423 | __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ | ||
| 424 | __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ | ||
| 425 | __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ | ||
| 426 | __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ | ||
| 427 | __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ | ||
| 428 | __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ | ||
| 429 | __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ | ||
| 430 | __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ | ||
| 431 | __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ | ||
| 432 | __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ | ||
| 433 | __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ | ||
| 434 | __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ | ||
| 435 | __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ | ||
| 436 | __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ | ||
| 437 | uint8_t RESERVED_0[4]; | ||
| 438 | __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ | ||
| 439 | __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ | ||
| 440 | __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ | ||
| 441 | __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ | ||
| 442 | __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ | ||
| 443 | __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ | ||
| 444 | __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ | ||
| 445 | } ADC_Type; | ||
| 446 | |||
| 447 | /* ---------------------------------------------------------------------------- | ||
| 448 | -- ADC Register Masks | ||
| 449 | ---------------------------------------------------------------------------- */ | ||
| 450 | |||
| 451 | /*! | ||
| 452 | * @addtogroup ADC_Register_Masks ADC Register Masks | ||
| 453 | * @{ | ||
| 454 | */ | ||
| 455 | |||
| 456 | /*! @name SC1 - ADC Status and Control Registers 1 */ | ||
| 457 | /*! @{ */ | ||
| 458 | #define ADC_SC1_ADCH_MASK (0x1FU) | ||
| 459 | #define ADC_SC1_ADCH_SHIFT (0U) | ||
| 460 | /*! ADCH - Input channel select | ||
| 461 | * 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. | ||
| 462 | * 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. | ||
| 463 | * 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. | ||
| 464 | * 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. | ||
| 465 | * 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. | ||
| 466 | * 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. | ||
| 467 | * 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. | ||
| 468 | * 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. | ||
| 469 | * 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. | ||
| 470 | * 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. | ||
| 471 | * 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. | ||
| 472 | * 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. | ||
| 473 | * 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. | ||
| 474 | * 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. | ||
| 475 | * 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. | ||
| 476 | * 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. | ||
| 477 | * 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. | ||
| 478 | * 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. | ||
| 479 | * 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. | ||
| 480 | * 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. | ||
| 481 | * 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. | ||
| 482 | * 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. | ||
| 483 | * 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. | ||
| 484 | * 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. | ||
| 485 | * 0b11000..Reserved. | ||
| 486 | * 0b11001..Reserved. | ||
| 487 | * 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. | ||
| 488 | * 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. | ||
| 489 | * 0b11100..Reserved. | ||
| 490 | * 0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. | ||
| 491 | * 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. | ||
| 492 | * 0b11111..Module is disabled. | ||
| 493 | */ | ||
| 494 | #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) | ||
| 495 | #define ADC_SC1_DIFF_MASK (0x20U) | ||
| 496 | #define ADC_SC1_DIFF_SHIFT (5U) | ||
| 497 | /*! DIFF - Differential Mode Enable | ||
| 498 | * 0b0..Single-ended conversions and input channels are selected. | ||
| 499 | * 0b1..Differential conversions and input channels are selected. | ||
| 500 | */ | ||
| 501 | #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK) | ||
| 502 | #define ADC_SC1_AIEN_MASK (0x40U) | ||
| 503 | #define ADC_SC1_AIEN_SHIFT (6U) | ||
| 504 | /*! AIEN - Interrupt Enable | ||
| 505 | * 0b0..Conversion complete interrupt is disabled. | ||
| 506 | * 0b1..Conversion complete interrupt is enabled. | ||
| 507 | */ | ||
| 508 | #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) | ||
| 509 | #define ADC_SC1_COCO_MASK (0x80U) | ||
| 510 | #define ADC_SC1_COCO_SHIFT (7U) | ||
| 511 | /*! COCO - Conversion Complete Flag | ||
| 512 | * 0b0..Conversion is not completed. | ||
| 513 | * 0b1..Conversion is completed. | ||
| 514 | */ | ||
| 515 | #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) | ||
| 516 | /*! @} */ | ||
| 517 | |||
| 518 | /* The count of ADC_SC1 */ | ||
| 519 | #define ADC_SC1_COUNT (2U) | ||
| 520 | |||
| 521 | /*! @name CFG1 - ADC Configuration Register 1 */ | ||
| 522 | /*! @{ */ | ||
| 523 | #define ADC_CFG1_ADICLK_MASK (0x3U) | ||
| 524 | #define ADC_CFG1_ADICLK_SHIFT (0U) | ||
| 525 | /*! ADICLK - Input Clock Select | ||
| 526 | * 0b00..Bus clock | ||
| 527 | * 0b01..Alternate clock 2 (ALTCLK2) | ||
| 528 | * 0b10..Alternate clock (ALTCLK) | ||
| 529 | * 0b11..Asynchronous clock (ADACK) | ||
| 530 | */ | ||
| 531 | #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) | ||
| 532 | #define ADC_CFG1_MODE_MASK (0xCU) | ||
| 533 | #define ADC_CFG1_MODE_SHIFT (2U) | ||
| 534 | /*! MODE - Conversion mode selection | ||
| 535 | * 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. | ||
| 536 | * 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output. | ||
| 537 | * 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output | ||
| 538 | * 0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output | ||
| 539 | */ | ||
| 540 | #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) | ||
| 541 | #define ADC_CFG1_ADLSMP_MASK (0x10U) | ||
| 542 | #define ADC_CFG1_ADLSMP_SHIFT (4U) | ||
| 543 | /*! ADLSMP - Sample Time Configuration | ||
| 544 | * 0b0..Short sample time. | ||
| 545 | * 0b1..Long sample time. | ||
| 546 | */ | ||
| 547 | #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) | ||
| 548 | #define ADC_CFG1_ADIV_MASK (0x60U) | ||
| 549 | #define ADC_CFG1_ADIV_SHIFT (5U) | ||
| 550 | /*! ADIV - Clock Divide Select | ||
| 551 | * 0b00..The divide ratio is 1 and the clock rate is input clock. | ||
| 552 | * 0b01..The divide ratio is 2 and the clock rate is (input clock)/2. | ||
| 553 | * 0b10..The divide ratio is 4 and the clock rate is (input clock)/4. | ||
| 554 | * 0b11..The divide ratio is 8 and the clock rate is (input clock)/8. | ||
| 555 | */ | ||
| 556 | #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) | ||
| 557 | #define ADC_CFG1_ADLPC_MASK (0x80U) | ||
| 558 | #define ADC_CFG1_ADLPC_SHIFT (7U) | ||
| 559 | /*! ADLPC - Low-Power Configuration | ||
| 560 | * 0b0..Normal power configuration. | ||
| 561 | * 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed. | ||
| 562 | */ | ||
| 563 | #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) | ||
| 564 | /*! @} */ | ||
| 565 | |||
| 566 | /*! @name CFG2 - ADC Configuration Register 2 */ | ||
| 567 | /*! @{ */ | ||
| 568 | #define ADC_CFG2_ADLSTS_MASK (0x3U) | ||
| 569 | #define ADC_CFG2_ADLSTS_SHIFT (0U) | ||
| 570 | /*! ADLSTS - Long Sample Time Select | ||
| 571 | * 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. | ||
| 572 | * 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time. | ||
| 573 | * 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time. | ||
| 574 | * 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time. | ||
| 575 | */ | ||
| 576 | #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) | ||
| 577 | #define ADC_CFG2_ADHSC_MASK (0x4U) | ||
| 578 | #define ADC_CFG2_ADHSC_SHIFT (2U) | ||
| 579 | /*! ADHSC - High-Speed Configuration | ||
| 580 | * 0b0..Normal conversion sequence selected. | ||
| 581 | * 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. | ||
| 582 | */ | ||
| 583 | #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) | ||
| 584 | #define ADC_CFG2_ADACKEN_MASK (0x8U) | ||
| 585 | #define ADC_CFG2_ADACKEN_SHIFT (3U) | ||
| 586 | /*! ADACKEN - Asynchronous Clock Output Enable | ||
| 587 | * 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. | ||
| 588 | * 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC. | ||
| 589 | */ | ||
| 590 | #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) | ||
| 591 | #define ADC_CFG2_MUXSEL_MASK (0x10U) | ||
| 592 | #define ADC_CFG2_MUXSEL_SHIFT (4U) | ||
| 593 | /*! MUXSEL - ADC Mux Select | ||
| 594 | * 0b0..ADxxa channels are selected. | ||
| 595 | * 0b1..ADxxb channels are selected. | ||
| 596 | */ | ||
| 597 | #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK) | ||
| 598 | /*! @} */ | ||
| 599 | |||
| 600 | /*! @name R - ADC Data Result Register */ | ||
| 601 | /*! @{ */ | ||
| 602 | #define ADC_R_D_MASK (0xFFFFU) | ||
| 603 | #define ADC_R_D_SHIFT (0U) | ||
| 604 | #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) | ||
| 605 | /*! @} */ | ||
| 606 | |||
| 607 | /* The count of ADC_R */ | ||
| 608 | #define ADC_R_COUNT (2U) | ||
| 609 | |||
| 610 | /*! @name CV1 - Compare Value Registers */ | ||
| 611 | /*! @{ */ | ||
| 612 | #define ADC_CV1_CV_MASK (0xFFFFU) | ||
| 613 | #define ADC_CV1_CV_SHIFT (0U) | ||
| 614 | #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) | ||
| 615 | /*! @} */ | ||
| 616 | |||
| 617 | /*! @name CV2 - Compare Value Registers */ | ||
| 618 | /*! @{ */ | ||
| 619 | #define ADC_CV2_CV_MASK (0xFFFFU) | ||
| 620 | #define ADC_CV2_CV_SHIFT (0U) | ||
| 621 | #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) | ||
| 622 | /*! @} */ | ||
| 623 | |||
| 624 | /*! @name SC2 - Status and Control Register 2 */ | ||
| 625 | /*! @{ */ | ||
| 626 | #define ADC_SC2_REFSEL_MASK (0x3U) | ||
| 627 | #define ADC_SC2_REFSEL_SHIFT (0U) | ||
| 628 | /*! REFSEL - Voltage Reference Selection | ||
| 629 | * 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL | ||
| 630 | * 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU | ||
| 631 | * 0b10..Reserved | ||
| 632 | * 0b11..Reserved | ||
| 633 | */ | ||
| 634 | #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) | ||
| 635 | #define ADC_SC2_DMAEN_MASK (0x4U) | ||
| 636 | #define ADC_SC2_DMAEN_SHIFT (2U) | ||
| 637 | /*! DMAEN - DMA Enable | ||
| 638 | * 0b0..DMA is disabled. | ||
| 639 | * 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted. | ||
| 640 | */ | ||
| 641 | #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) | ||
| 642 | #define ADC_SC2_ACREN_MASK (0x8U) | ||
| 643 | #define ADC_SC2_ACREN_SHIFT (3U) | ||
| 644 | /*! ACREN - Compare Function Range Enable | ||
| 645 | * 0b0..Range function disabled. Only CV1 is compared. | ||
| 646 | * 0b1..Range function enabled. Both CV1 and CV2 are compared. | ||
| 647 | */ | ||
| 648 | #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) | ||
| 649 | #define ADC_SC2_ACFGT_MASK (0x10U) | ||
| 650 | #define ADC_SC2_ACFGT_SHIFT (4U) | ||
| 651 | /*! ACFGT - Compare Function Greater Than Enable | ||
| 652 | * 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. | ||
| 653 | * 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2. | ||
| 654 | */ | ||
| 655 | #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) | ||
| 656 | #define ADC_SC2_ACFE_MASK (0x20U) | ||
| 657 | #define ADC_SC2_ACFE_SHIFT (5U) | ||
| 658 | /*! ACFE - Compare Function Enable | ||
| 659 | * 0b0..Compare function disabled. | ||
| 660 | * 0b1..Compare function enabled. | ||
| 661 | */ | ||
| 662 | #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) | ||
| 663 | #define ADC_SC2_ADTRG_MASK (0x40U) | ||
| 664 | #define ADC_SC2_ADTRG_SHIFT (6U) | ||
| 665 | /*! ADTRG - Conversion Trigger Select | ||
| 666 | * 0b0..Software trigger selected. | ||
| 667 | * 0b1..Hardware trigger selected. | ||
| 668 | */ | ||
| 669 | #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) | ||
| 670 | #define ADC_SC2_ADACT_MASK (0x80U) | ||
| 671 | #define ADC_SC2_ADACT_SHIFT (7U) | ||
| 672 | /*! ADACT - Conversion Active | ||
| 673 | * 0b0..Conversion not in progress. | ||
| 674 | * 0b1..Conversion in progress. | ||
| 675 | */ | ||
| 676 | #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) | ||
| 677 | /*! @} */ | ||
| 678 | |||
| 679 | /*! @name SC3 - Status and Control Register 3 */ | ||
| 680 | /*! @{ */ | ||
| 681 | #define ADC_SC3_AVGS_MASK (0x3U) | ||
| 682 | #define ADC_SC3_AVGS_SHIFT (0U) | ||
| 683 | /*! AVGS - Hardware Average Select | ||
| 684 | * 0b00..4 samples averaged. | ||
| 685 | * 0b01..8 samples averaged. | ||
| 686 | * 0b10..16 samples averaged. | ||
| 687 | * 0b11..32 samples averaged. | ||
| 688 | */ | ||
| 689 | #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) | ||
| 690 | #define ADC_SC3_AVGE_MASK (0x4U) | ||
| 691 | #define ADC_SC3_AVGE_SHIFT (2U) | ||
| 692 | /*! AVGE - Hardware Average Enable | ||
| 693 | * 0b0..Hardware average function disabled. | ||
| 694 | * 0b1..Hardware average function enabled. | ||
| 695 | */ | ||
| 696 | #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) | ||
| 697 | #define ADC_SC3_ADCO_MASK (0x8U) | ||
| 698 | #define ADC_SC3_ADCO_SHIFT (3U) | ||
| 699 | /*! ADCO - Continuous Conversion Enable | ||
| 700 | * 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. | ||
| 701 | * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. | ||
| 702 | */ | ||
| 703 | #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) | ||
| 704 | #define ADC_SC3_CALF_MASK (0x40U) | ||
| 705 | #define ADC_SC3_CALF_SHIFT (6U) | ||
| 706 | /*! CALF - Calibration Failed Flag | ||
| 707 | * 0b0..Calibration completed normally. | ||
| 708 | * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed. | ||
| 709 | */ | ||
| 710 | #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) | ||
| 711 | #define ADC_SC3_CAL_MASK (0x80U) | ||
| 712 | #define ADC_SC3_CAL_SHIFT (7U) | ||
| 713 | #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) | ||
| 714 | /*! @} */ | ||
| 715 | |||
| 716 | /*! @name OFS - ADC Offset Correction Register */ | ||
| 717 | /*! @{ */ | ||
| 718 | #define ADC_OFS_OFS_MASK (0xFFFFU) | ||
| 719 | #define ADC_OFS_OFS_SHIFT (0U) | ||
| 720 | #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) | ||
| 721 | /*! @} */ | ||
| 722 | |||
| 723 | /*! @name PG - ADC Plus-Side Gain Register */ | ||
| 724 | /*! @{ */ | ||
| 725 | #define ADC_PG_PG_MASK (0xFFFFU) | ||
| 726 | #define ADC_PG_PG_SHIFT (0U) | ||
| 727 | #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) | ||
| 728 | /*! @} */ | ||
| 729 | |||
| 730 | /*! @name MG - ADC Minus-Side Gain Register */ | ||
| 731 | /*! @{ */ | ||
| 732 | #define ADC_MG_MG_MASK (0xFFFFU) | ||
| 733 | #define ADC_MG_MG_SHIFT (0U) | ||
| 734 | #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK) | ||
| 735 | /*! @} */ | ||
| 736 | |||
| 737 | /*! @name CLPD - ADC Plus-Side General Calibration Value Register */ | ||
| 738 | /*! @{ */ | ||
| 739 | #define ADC_CLPD_CLPD_MASK (0x3FU) | ||
| 740 | #define ADC_CLPD_CLPD_SHIFT (0U) | ||
| 741 | #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) | ||
| 742 | /*! @} */ | ||
| 743 | |||
| 744 | /*! @name CLPS - ADC Plus-Side General Calibration Value Register */ | ||
| 745 | /*! @{ */ | ||
| 746 | #define ADC_CLPS_CLPS_MASK (0x3FU) | ||
| 747 | #define ADC_CLPS_CLPS_SHIFT (0U) | ||
| 748 | #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) | ||
| 749 | /*! @} */ | ||
| 750 | |||
| 751 | /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ | ||
| 752 | /*! @{ */ | ||
| 753 | #define ADC_CLP4_CLP4_MASK (0x3FFU) | ||
| 754 | #define ADC_CLP4_CLP4_SHIFT (0U) | ||
| 755 | #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) | ||
| 756 | /*! @} */ | ||
| 757 | |||
| 758 | /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ | ||
| 759 | /*! @{ */ | ||
| 760 | #define ADC_CLP3_CLP3_MASK (0x1FFU) | ||
| 761 | #define ADC_CLP3_CLP3_SHIFT (0U) | ||
| 762 | #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) | ||
| 763 | /*! @} */ | ||
| 764 | |||
| 765 | /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ | ||
| 766 | /*! @{ */ | ||
| 767 | #define ADC_CLP2_CLP2_MASK (0xFFU) | ||
| 768 | #define ADC_CLP2_CLP2_SHIFT (0U) | ||
| 769 | #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) | ||
| 770 | /*! @} */ | ||
| 771 | |||
| 772 | /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ | ||
| 773 | /*! @{ */ | ||
| 774 | #define ADC_CLP1_CLP1_MASK (0x7FU) | ||
| 775 | #define ADC_CLP1_CLP1_SHIFT (0U) | ||
| 776 | #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) | ||
| 777 | /*! @} */ | ||
| 778 | |||
| 779 | /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ | ||
| 780 | /*! @{ */ | ||
| 781 | #define ADC_CLP0_CLP0_MASK (0x3FU) | ||
| 782 | #define ADC_CLP0_CLP0_SHIFT (0U) | ||
| 783 | #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) | ||
| 784 | /*! @} */ | ||
| 785 | |||
| 786 | /*! @name CLMD - ADC Minus-Side General Calibration Value Register */ | ||
| 787 | /*! @{ */ | ||
| 788 | #define ADC_CLMD_CLMD_MASK (0x3FU) | ||
| 789 | #define ADC_CLMD_CLMD_SHIFT (0U) | ||
| 790 | #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK) | ||
| 791 | /*! @} */ | ||
| 792 | |||
| 793 | /*! @name CLMS - ADC Minus-Side General Calibration Value Register */ | ||
| 794 | /*! @{ */ | ||
| 795 | #define ADC_CLMS_CLMS_MASK (0x3FU) | ||
| 796 | #define ADC_CLMS_CLMS_SHIFT (0U) | ||
| 797 | #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK) | ||
| 798 | /*! @} */ | ||
| 799 | |||
| 800 | /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */ | ||
| 801 | /*! @{ */ | ||
| 802 | #define ADC_CLM4_CLM4_MASK (0x3FFU) | ||
| 803 | #define ADC_CLM4_CLM4_SHIFT (0U) | ||
| 804 | #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK) | ||
| 805 | /*! @} */ | ||
| 806 | |||
| 807 | /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */ | ||
| 808 | /*! @{ */ | ||
| 809 | #define ADC_CLM3_CLM3_MASK (0x1FFU) | ||
| 810 | #define ADC_CLM3_CLM3_SHIFT (0U) | ||
| 811 | #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK) | ||
| 812 | /*! @} */ | ||
| 813 | |||
| 814 | /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */ | ||
| 815 | /*! @{ */ | ||
| 816 | #define ADC_CLM2_CLM2_MASK (0xFFU) | ||
| 817 | #define ADC_CLM2_CLM2_SHIFT (0U) | ||
| 818 | #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK) | ||
| 819 | /*! @} */ | ||
| 820 | |||
| 821 | /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */ | ||
| 822 | /*! @{ */ | ||
| 823 | #define ADC_CLM1_CLM1_MASK (0x7FU) | ||
| 824 | #define ADC_CLM1_CLM1_SHIFT (0U) | ||
| 825 | #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK) | ||
| 826 | /*! @} */ | ||
| 827 | |||
| 828 | /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */ | ||
| 829 | /*! @{ */ | ||
| 830 | #define ADC_CLM0_CLM0_MASK (0x3FU) | ||
| 831 | #define ADC_CLM0_CLM0_SHIFT (0U) | ||
| 832 | #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK) | ||
| 833 | /*! @} */ | ||
| 834 | |||
| 835 | |||
| 836 | /*! | ||
| 837 | * @} | ||
| 838 | */ /* end of group ADC_Register_Masks */ | ||
| 839 | |||
| 840 | |||
| 841 | /* ADC - Peripheral instance base addresses */ | ||
| 842 | /** Peripheral ADC0 base address */ | ||
| 843 | #define ADC0_BASE (0x4003B000u) | ||
| 844 | /** Peripheral ADC0 base pointer */ | ||
| 845 | #define ADC0 ((ADC_Type *)ADC0_BASE) | ||
| 846 | /** Peripheral ADC1 base address */ | ||
| 847 | #define ADC1_BASE (0x400BB000u) | ||
| 848 | /** Peripheral ADC1 base pointer */ | ||
| 849 | #define ADC1 ((ADC_Type *)ADC1_BASE) | ||
| 850 | /** Array initializer of ADC peripheral base addresses */ | ||
| 851 | #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } | ||
| 852 | /** Array initializer of ADC peripheral base pointers */ | ||
| 853 | #define ADC_BASE_PTRS { ADC0, ADC1 } | ||
| 854 | /** Interrupt vectors for the ADC peripheral type */ | ||
| 855 | #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } | ||
| 856 | |||
| 857 | /*! | ||
| 858 | * @} | ||
| 859 | */ /* end of group ADC_Peripheral_Access_Layer */ | ||
| 860 | |||
| 861 | |||
| 862 | /* ---------------------------------------------------------------------------- | ||
| 863 | -- AIPS Peripheral Access Layer | ||
| 864 | ---------------------------------------------------------------------------- */ | ||
| 865 | |||
| 866 | /*! | ||
| 867 | * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer | ||
| 868 | * @{ | ||
| 869 | */ | ||
| 870 | |||
| 871 | /** AIPS - Register Layout Typedef */ | ||
| 872 | typedef struct { | ||
| 873 | __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */ | ||
| 874 | uint8_t RESERVED_0[28]; | ||
| 875 | __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */ | ||
| 876 | __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */ | ||
| 877 | __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */ | ||
| 878 | __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */ | ||
| 879 | uint8_t RESERVED_1[16]; | ||
| 880 | __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */ | ||
| 881 | __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */ | ||
| 882 | __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */ | ||
| 883 | __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */ | ||
| 884 | __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */ | ||
| 885 | __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */ | ||
| 886 | __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */ | ||
| 887 | __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */ | ||
| 888 | __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */ | ||
| 889 | __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */ | ||
| 890 | __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */ | ||
| 891 | __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */ | ||
| 892 | uint8_t RESERVED_2[16]; | ||
| 893 | __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */ | ||
| 894 | } AIPS_Type; | ||
| 895 | |||
| 896 | /* ---------------------------------------------------------------------------- | ||
| 897 | -- AIPS Register Masks | ||
| 898 | ---------------------------------------------------------------------------- */ | ||
| 899 | |||
| 900 | /*! | ||
| 901 | * @addtogroup AIPS_Register_Masks AIPS Register Masks | ||
| 902 | * @{ | ||
| 903 | */ | ||
| 904 | |||
| 905 | /*! @name MPRA - Master Privilege Register A */ | ||
| 906 | /*! @{ */ | ||
| 907 | #define AIPS_MPRA_MPL5_MASK (0x100U) | ||
| 908 | #define AIPS_MPRA_MPL5_SHIFT (8U) | ||
| 909 | /*! MPL5 - Master 5 Privilege Level | ||
| 910 | * 0b0..Accesses from this master are forced to user-mode. | ||
| 911 | * 0b1..Accesses from this master are not forced to user-mode. | ||
| 912 | */ | ||
| 913 | #define AIPS_MPRA_MPL5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK) | ||
| 914 | #define AIPS_MPRA_MTW5_MASK (0x200U) | ||
| 915 | #define AIPS_MPRA_MTW5_SHIFT (9U) | ||
| 916 | /*! MTW5 - Master 5 Trusted For Writes | ||
| 917 | * 0b0..This master is not trusted for write accesses. | ||
| 918 | * 0b1..This master is trusted for write accesses. | ||
| 919 | */ | ||
| 920 | #define AIPS_MPRA_MTW5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK) | ||
| 921 | #define AIPS_MPRA_MTR5_MASK (0x400U) | ||
| 922 | #define AIPS_MPRA_MTR5_SHIFT (10U) | ||
| 923 | /*! MTR5 - Master 5 Trusted For Read | ||
| 924 | * 0b0..This master is not trusted for read accesses. | ||
| 925 | * 0b1..This master is trusted for read accesses. | ||
| 926 | */ | ||
| 927 | #define AIPS_MPRA_MTR5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK) | ||
| 928 | #define AIPS_MPRA_MPL4_MASK (0x1000U) | ||
| 929 | #define AIPS_MPRA_MPL4_SHIFT (12U) | ||
| 930 | /*! MPL4 - Master 4 Privilege Level | ||
| 931 | * 0b0..Accesses from this master are forced to user-mode. | ||
| 932 | * 0b1..Accesses from this master are not forced to user-mode. | ||
| 933 | */ | ||
| 934 | #define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK) | ||
| 935 | #define AIPS_MPRA_MTW4_MASK (0x2000U) | ||
| 936 | #define AIPS_MPRA_MTW4_SHIFT (13U) | ||
| 937 | /*! MTW4 - Master 4 Trusted For Writes | ||
| 938 | * 0b0..This master is not trusted for write accesses. | ||
| 939 | * 0b1..This master is trusted for write accesses. | ||
| 940 | */ | ||
| 941 | #define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK) | ||
| 942 | #define AIPS_MPRA_MTR4_MASK (0x4000U) | ||
| 943 | #define AIPS_MPRA_MTR4_SHIFT (14U) | ||
| 944 | /*! MTR4 - Master 4 Trusted For Read | ||
| 945 | * 0b0..This master is not trusted for read accesses. | ||
| 946 | * 0b1..This master is trusted for read accesses. | ||
| 947 | */ | ||
| 948 | #define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK) | ||
| 949 | #define AIPS_MPRA_MPL3_MASK (0x10000U) | ||
| 950 | #define AIPS_MPRA_MPL3_SHIFT (16U) | ||
| 951 | /*! MPL3 - Master 3 Privilege Level | ||
| 952 | * 0b0..Accesses from this master are forced to user-mode. | ||
| 953 | * 0b1..Accesses from this master are not forced to user-mode. | ||
| 954 | */ | ||
| 955 | #define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK) | ||
| 956 | #define AIPS_MPRA_MTW3_MASK (0x20000U) | ||
| 957 | #define AIPS_MPRA_MTW3_SHIFT (17U) | ||
| 958 | /*! MTW3 - Master 3 Trusted For Writes | ||
| 959 | * 0b0..This master is not trusted for write accesses. | ||
| 960 | * 0b1..This master is trusted for write accesses. | ||
| 961 | */ | ||
| 962 | #define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK) | ||
| 963 | #define AIPS_MPRA_MTR3_MASK (0x40000U) | ||
| 964 | #define AIPS_MPRA_MTR3_SHIFT (18U) | ||
| 965 | /*! MTR3 - Master 3 Trusted For Read | ||
| 966 | * 0b0..This master is not trusted for read accesses. | ||
| 967 | * 0b1..This master is trusted for read accesses. | ||
| 968 | */ | ||
| 969 | #define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK) | ||
| 970 | #define AIPS_MPRA_MPL2_MASK (0x100000U) | ||
| 971 | #define AIPS_MPRA_MPL2_SHIFT (20U) | ||
| 972 | /*! MPL2 - Master 2 Privilege Level | ||
| 973 | * 0b0..Accesses from this master are forced to user-mode. | ||
| 974 | * 0b1..Accesses from this master are not forced to user-mode. | ||
| 975 | */ | ||
| 976 | #define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK) | ||
| 977 | #define AIPS_MPRA_MTW2_MASK (0x200000U) | ||
| 978 | #define AIPS_MPRA_MTW2_SHIFT (21U) | ||
| 979 | /*! MTW2 - Master 2 Trusted For Writes | ||
| 980 | * 0b0..This master is not trusted for write accesses. | ||
| 981 | * 0b1..This master is trusted for write accesses. | ||
| 982 | */ | ||
| 983 | #define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK) | ||
| 984 | #define AIPS_MPRA_MTR2_MASK (0x400000U) | ||
| 985 | #define AIPS_MPRA_MTR2_SHIFT (22U) | ||
| 986 | /*! MTR2 - Master 2 Trusted For Read | ||
| 987 | * 0b0..This master is not trusted for read accesses. | ||
| 988 | * 0b1..This master is trusted for read accesses. | ||
| 989 | */ | ||
| 990 | #define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK) | ||
| 991 | #define AIPS_MPRA_MPL1_MASK (0x1000000U) | ||
| 992 | #define AIPS_MPRA_MPL1_SHIFT (24U) | ||
| 993 | /*! MPL1 - Master 1 Privilege Level | ||
| 994 | * 0b0..Accesses from this master are forced to user-mode. | ||
| 995 | * 0b1..Accesses from this master are not forced to user-mode. | ||
| 996 | */ | ||
| 997 | #define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK) | ||
| 998 | #define AIPS_MPRA_MTW1_MASK (0x2000000U) | ||
| 999 | #define AIPS_MPRA_MTW1_SHIFT (25U) | ||
| 1000 | /*! MTW1 - Master 1 Trusted for Writes | ||
| 1001 | * 0b0..This master is not trusted for write accesses. | ||
| 1002 | * 0b1..This master is trusted for write accesses. | ||
| 1003 | */ | ||
| 1004 | #define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK) | ||
| 1005 | #define AIPS_MPRA_MTR1_MASK (0x4000000U) | ||
| 1006 | #define AIPS_MPRA_MTR1_SHIFT (26U) | ||
| 1007 | /*! MTR1 - Master 1 Trusted for Read | ||
| 1008 | * 0b0..This master is not trusted for read accesses. | ||
| 1009 | * 0b1..This master is trusted for read accesses. | ||
| 1010 | */ | ||
| 1011 | #define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK) | ||
| 1012 | #define AIPS_MPRA_MPL0_MASK (0x10000000U) | ||
| 1013 | #define AIPS_MPRA_MPL0_SHIFT (28U) | ||
| 1014 | /*! MPL0 - Master 0 Privilege Level | ||
| 1015 | * 0b0..Accesses from this master are forced to user-mode. | ||
| 1016 | * 0b1..Accesses from this master are not forced to user-mode. | ||
| 1017 | */ | ||
| 1018 | #define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK) | ||
| 1019 | #define AIPS_MPRA_MTW0_MASK (0x20000000U) | ||
| 1020 | #define AIPS_MPRA_MTW0_SHIFT (29U) | ||
| 1021 | /*! MTW0 - Master 0 Trusted For Writes | ||
| 1022 | * 0b0..This master is not trusted for write accesses. | ||
| 1023 | * 0b1..This master is trusted for write accesses. | ||
| 1024 | */ | ||
| 1025 | #define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK) | ||
| 1026 | #define AIPS_MPRA_MTR0_MASK (0x40000000U) | ||
| 1027 | #define AIPS_MPRA_MTR0_SHIFT (30U) | ||
| 1028 | /*! MTR0 - Master 0 Trusted For Read | ||
| 1029 | * 0b0..This master is not trusted for read accesses. | ||
| 1030 | * 0b1..This master is trusted for read accesses. | ||
| 1031 | */ | ||
| 1032 | #define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK) | ||
| 1033 | /*! @} */ | ||
| 1034 | |||
| 1035 | /*! @name PACRA - Peripheral Access Control Register */ | ||
| 1036 | /*! @{ */ | ||
| 1037 | #define AIPS_PACRA_TP7_MASK (0x1U) | ||
| 1038 | #define AIPS_PACRA_TP7_SHIFT (0U) | ||
| 1039 | /*! TP7 - Trusted Protect | ||
| 1040 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1041 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1042 | */ | ||
| 1043 | #define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK) | ||
| 1044 | #define AIPS_PACRA_WP7_MASK (0x2U) | ||
| 1045 | #define AIPS_PACRA_WP7_SHIFT (1U) | ||
| 1046 | /*! WP7 - Write Protect | ||
| 1047 | * 0b0..This peripheral allows write accesses. | ||
| 1048 | * 0b1..This peripheral is write protected. | ||
| 1049 | */ | ||
| 1050 | #define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK) | ||
| 1051 | #define AIPS_PACRA_SP7_MASK (0x4U) | ||
| 1052 | #define AIPS_PACRA_SP7_SHIFT (2U) | ||
| 1053 | /*! SP7 - Supervisor Protect | ||
| 1054 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1055 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1056 | */ | ||
| 1057 | #define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK) | ||
| 1058 | #define AIPS_PACRA_TP6_MASK (0x10U) | ||
| 1059 | #define AIPS_PACRA_TP6_SHIFT (4U) | ||
| 1060 | /*! TP6 - Trusted Protect | ||
| 1061 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1062 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1063 | */ | ||
| 1064 | #define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK) | ||
| 1065 | #define AIPS_PACRA_WP6_MASK (0x20U) | ||
| 1066 | #define AIPS_PACRA_WP6_SHIFT (5U) | ||
| 1067 | /*! WP6 - Write Protect | ||
| 1068 | * 0b0..This peripheral allows write accesses. | ||
| 1069 | * 0b1..This peripheral is write protected. | ||
| 1070 | */ | ||
| 1071 | #define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK) | ||
| 1072 | #define AIPS_PACRA_SP6_MASK (0x40U) | ||
| 1073 | #define AIPS_PACRA_SP6_SHIFT (6U) | ||
| 1074 | /*! SP6 - Supervisor Protect | ||
| 1075 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1076 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1077 | */ | ||
| 1078 | #define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK) | ||
| 1079 | #define AIPS_PACRA_TP5_MASK (0x100U) | ||
| 1080 | #define AIPS_PACRA_TP5_SHIFT (8U) | ||
| 1081 | /*! TP5 - Trusted Protect | ||
| 1082 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1083 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1084 | */ | ||
| 1085 | #define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK) | ||
| 1086 | #define AIPS_PACRA_WP5_MASK (0x200U) | ||
| 1087 | #define AIPS_PACRA_WP5_SHIFT (9U) | ||
| 1088 | /*! WP5 - Write Protect | ||
| 1089 | * 0b0..This peripheral allows write accesses. | ||
| 1090 | * 0b1..This peripheral is write protected. | ||
| 1091 | */ | ||
| 1092 | #define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK) | ||
| 1093 | #define AIPS_PACRA_SP5_MASK (0x400U) | ||
| 1094 | #define AIPS_PACRA_SP5_SHIFT (10U) | ||
| 1095 | /*! SP5 - Supervisor Protect | ||
| 1096 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1097 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1098 | */ | ||
| 1099 | #define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK) | ||
| 1100 | #define AIPS_PACRA_TP4_MASK (0x1000U) | ||
| 1101 | #define AIPS_PACRA_TP4_SHIFT (12U) | ||
| 1102 | /*! TP4 - Trusted Protect | ||
| 1103 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1104 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1105 | */ | ||
| 1106 | #define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK) | ||
| 1107 | #define AIPS_PACRA_WP4_MASK (0x2000U) | ||
| 1108 | #define AIPS_PACRA_WP4_SHIFT (13U) | ||
| 1109 | /*! WP4 - Write Protect | ||
| 1110 | * 0b0..This peripheral allows write accesses. | ||
| 1111 | * 0b1..This peripheral is write protected. | ||
| 1112 | */ | ||
| 1113 | #define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK) | ||
| 1114 | #define AIPS_PACRA_SP4_MASK (0x4000U) | ||
| 1115 | #define AIPS_PACRA_SP4_SHIFT (14U) | ||
| 1116 | /*! SP4 - Supervisor Protect | ||
| 1117 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1118 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1119 | */ | ||
| 1120 | #define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK) | ||
| 1121 | #define AIPS_PACRA_TP3_MASK (0x10000U) | ||
| 1122 | #define AIPS_PACRA_TP3_SHIFT (16U) | ||
| 1123 | /*! TP3 - Trusted Protect | ||
| 1124 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1125 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1126 | */ | ||
| 1127 | #define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK) | ||
| 1128 | #define AIPS_PACRA_WP3_MASK (0x20000U) | ||
| 1129 | #define AIPS_PACRA_WP3_SHIFT (17U) | ||
| 1130 | /*! WP3 - Write Protect | ||
| 1131 | * 0b0..This peripheral allows write accesses. | ||
| 1132 | * 0b1..This peripheral is write protected. | ||
| 1133 | */ | ||
| 1134 | #define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK) | ||
| 1135 | #define AIPS_PACRA_SP3_MASK (0x40000U) | ||
| 1136 | #define AIPS_PACRA_SP3_SHIFT (18U) | ||
| 1137 | /*! SP3 - Supervisor Protect | ||
| 1138 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1139 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1140 | */ | ||
| 1141 | #define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK) | ||
| 1142 | #define AIPS_PACRA_TP2_MASK (0x100000U) | ||
| 1143 | #define AIPS_PACRA_TP2_SHIFT (20U) | ||
| 1144 | /*! TP2 - Trusted Protect | ||
| 1145 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1146 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1147 | */ | ||
| 1148 | #define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK) | ||
| 1149 | #define AIPS_PACRA_WP2_MASK (0x200000U) | ||
| 1150 | #define AIPS_PACRA_WP2_SHIFT (21U) | ||
| 1151 | /*! WP2 - Write Protect | ||
| 1152 | * 0b0..This peripheral allows write accesses. | ||
| 1153 | * 0b1..This peripheral is write protected. | ||
| 1154 | */ | ||
| 1155 | #define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK) | ||
| 1156 | #define AIPS_PACRA_SP2_MASK (0x400000U) | ||
| 1157 | #define AIPS_PACRA_SP2_SHIFT (22U) | ||
| 1158 | /*! SP2 - Supervisor Protect | ||
| 1159 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1160 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1161 | */ | ||
| 1162 | #define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK) | ||
| 1163 | #define AIPS_PACRA_TP1_MASK (0x1000000U) | ||
| 1164 | #define AIPS_PACRA_TP1_SHIFT (24U) | ||
| 1165 | /*! TP1 - Trusted Protect | ||
| 1166 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1167 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1168 | */ | ||
| 1169 | #define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK) | ||
| 1170 | #define AIPS_PACRA_WP1_MASK (0x2000000U) | ||
| 1171 | #define AIPS_PACRA_WP1_SHIFT (25U) | ||
| 1172 | /*! WP1 - Write Protect | ||
| 1173 | * 0b0..This peripheral allows write accesses. | ||
| 1174 | * 0b1..This peripheral is write protected. | ||
| 1175 | */ | ||
| 1176 | #define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK) | ||
| 1177 | #define AIPS_PACRA_SP1_MASK (0x4000000U) | ||
| 1178 | #define AIPS_PACRA_SP1_SHIFT (26U) | ||
| 1179 | /*! SP1 - Supervisor Protect | ||
| 1180 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1181 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1182 | */ | ||
| 1183 | #define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK) | ||
| 1184 | #define AIPS_PACRA_TP0_MASK (0x10000000U) | ||
| 1185 | #define AIPS_PACRA_TP0_SHIFT (28U) | ||
| 1186 | /*! TP0 - Trusted Protect | ||
| 1187 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1188 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1189 | */ | ||
| 1190 | #define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK) | ||
| 1191 | #define AIPS_PACRA_WP0_MASK (0x20000000U) | ||
| 1192 | #define AIPS_PACRA_WP0_SHIFT (29U) | ||
| 1193 | /*! WP0 - Write Protect | ||
| 1194 | * 0b0..This peripheral allows write accesses. | ||
| 1195 | * 0b1..This peripheral is write protected. | ||
| 1196 | */ | ||
| 1197 | #define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK) | ||
| 1198 | #define AIPS_PACRA_SP0_MASK (0x40000000U) | ||
| 1199 | #define AIPS_PACRA_SP0_SHIFT (30U) | ||
| 1200 | /*! SP0 - Supervisor Protect | ||
| 1201 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1202 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1203 | */ | ||
| 1204 | #define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK) | ||
| 1205 | /*! @} */ | ||
| 1206 | |||
| 1207 | /*! @name PACRB - Peripheral Access Control Register */ | ||
| 1208 | /*! @{ */ | ||
| 1209 | #define AIPS_PACRB_TP7_MASK (0x1U) | ||
| 1210 | #define AIPS_PACRB_TP7_SHIFT (0U) | ||
| 1211 | /*! TP7 - Trusted Protect | ||
| 1212 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1213 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1214 | */ | ||
| 1215 | #define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK) | ||
| 1216 | #define AIPS_PACRB_WP7_MASK (0x2U) | ||
| 1217 | #define AIPS_PACRB_WP7_SHIFT (1U) | ||
| 1218 | /*! WP7 - Write Protect | ||
| 1219 | * 0b0..This peripheral allows write accesses. | ||
| 1220 | * 0b1..This peripheral is write protected. | ||
| 1221 | */ | ||
| 1222 | #define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK) | ||
| 1223 | #define AIPS_PACRB_SP7_MASK (0x4U) | ||
| 1224 | #define AIPS_PACRB_SP7_SHIFT (2U) | ||
| 1225 | /*! SP7 - Supervisor Protect | ||
| 1226 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1227 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1228 | */ | ||
| 1229 | #define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK) | ||
| 1230 | #define AIPS_PACRB_TP6_MASK (0x10U) | ||
| 1231 | #define AIPS_PACRB_TP6_SHIFT (4U) | ||
| 1232 | /*! TP6 - Trusted Protect | ||
| 1233 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1234 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1235 | */ | ||
| 1236 | #define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK) | ||
| 1237 | #define AIPS_PACRB_WP6_MASK (0x20U) | ||
| 1238 | #define AIPS_PACRB_WP6_SHIFT (5U) | ||
| 1239 | /*! WP6 - Write Protect | ||
| 1240 | * 0b0..This peripheral allows write accesses. | ||
| 1241 | * 0b1..This peripheral is write protected. | ||
| 1242 | */ | ||
| 1243 | #define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK) | ||
| 1244 | #define AIPS_PACRB_SP6_MASK (0x40U) | ||
| 1245 | #define AIPS_PACRB_SP6_SHIFT (6U) | ||
| 1246 | /*! SP6 - Supervisor Protect | ||
| 1247 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1248 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1249 | */ | ||
| 1250 | #define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK) | ||
| 1251 | #define AIPS_PACRB_TP5_MASK (0x100U) | ||
| 1252 | #define AIPS_PACRB_TP5_SHIFT (8U) | ||
| 1253 | /*! TP5 - Trusted Protect | ||
| 1254 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1255 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1256 | */ | ||
| 1257 | #define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK) | ||
| 1258 | #define AIPS_PACRB_WP5_MASK (0x200U) | ||
| 1259 | #define AIPS_PACRB_WP5_SHIFT (9U) | ||
| 1260 | /*! WP5 - Write Protect | ||
| 1261 | * 0b0..This peripheral allows write accesses. | ||
| 1262 | * 0b1..This peripheral is write protected. | ||
| 1263 | */ | ||
| 1264 | #define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK) | ||
| 1265 | #define AIPS_PACRB_SP5_MASK (0x400U) | ||
| 1266 | #define AIPS_PACRB_SP5_SHIFT (10U) | ||
| 1267 | /*! SP5 - Supervisor Protect | ||
| 1268 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1269 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1270 | */ | ||
| 1271 | #define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK) | ||
| 1272 | #define AIPS_PACRB_TP4_MASK (0x1000U) | ||
| 1273 | #define AIPS_PACRB_TP4_SHIFT (12U) | ||
| 1274 | /*! TP4 - Trusted Protect | ||
| 1275 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1276 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1277 | */ | ||
| 1278 | #define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK) | ||
| 1279 | #define AIPS_PACRB_WP4_MASK (0x2000U) | ||
| 1280 | #define AIPS_PACRB_WP4_SHIFT (13U) | ||
| 1281 | /*! WP4 - Write Protect | ||
| 1282 | * 0b0..This peripheral allows write accesses. | ||
| 1283 | * 0b1..This peripheral is write protected. | ||
| 1284 | */ | ||
| 1285 | #define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK) | ||
| 1286 | #define AIPS_PACRB_SP4_MASK (0x4000U) | ||
| 1287 | #define AIPS_PACRB_SP4_SHIFT (14U) | ||
| 1288 | /*! SP4 - Supervisor Protect | ||
| 1289 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1290 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1291 | */ | ||
| 1292 | #define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK) | ||
| 1293 | #define AIPS_PACRB_TP3_MASK (0x10000U) | ||
| 1294 | #define AIPS_PACRB_TP3_SHIFT (16U) | ||
| 1295 | /*! TP3 - Trusted Protect | ||
| 1296 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1297 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1298 | */ | ||
| 1299 | #define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK) | ||
| 1300 | #define AIPS_PACRB_WP3_MASK (0x20000U) | ||
| 1301 | #define AIPS_PACRB_WP3_SHIFT (17U) | ||
| 1302 | /*! WP3 - Write Protect | ||
| 1303 | * 0b0..This peripheral allows write accesses. | ||
| 1304 | * 0b1..This peripheral is write protected. | ||
| 1305 | */ | ||
| 1306 | #define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK) | ||
| 1307 | #define AIPS_PACRB_SP3_MASK (0x40000U) | ||
| 1308 | #define AIPS_PACRB_SP3_SHIFT (18U) | ||
| 1309 | /*! SP3 - Supervisor Protect | ||
| 1310 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1311 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1312 | */ | ||
| 1313 | #define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK) | ||
| 1314 | #define AIPS_PACRB_TP2_MASK (0x100000U) | ||
| 1315 | #define AIPS_PACRB_TP2_SHIFT (20U) | ||
| 1316 | /*! TP2 - Trusted Protect | ||
| 1317 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1318 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1319 | */ | ||
| 1320 | #define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK) | ||
| 1321 | #define AIPS_PACRB_WP2_MASK (0x200000U) | ||
| 1322 | #define AIPS_PACRB_WP2_SHIFT (21U) | ||
| 1323 | /*! WP2 - Write Protect | ||
| 1324 | * 0b0..This peripheral allows write accesses. | ||
| 1325 | * 0b1..This peripheral is write protected. | ||
| 1326 | */ | ||
| 1327 | #define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK) | ||
| 1328 | #define AIPS_PACRB_SP2_MASK (0x400000U) | ||
| 1329 | #define AIPS_PACRB_SP2_SHIFT (22U) | ||
| 1330 | /*! SP2 - Supervisor Protect | ||
| 1331 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1332 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1333 | */ | ||
| 1334 | #define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK) | ||
| 1335 | #define AIPS_PACRB_TP1_MASK (0x1000000U) | ||
| 1336 | #define AIPS_PACRB_TP1_SHIFT (24U) | ||
| 1337 | /*! TP1 - Trusted Protect | ||
| 1338 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1339 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1340 | */ | ||
| 1341 | #define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK) | ||
| 1342 | #define AIPS_PACRB_WP1_MASK (0x2000000U) | ||
| 1343 | #define AIPS_PACRB_WP1_SHIFT (25U) | ||
| 1344 | /*! WP1 - Write Protect | ||
| 1345 | * 0b0..This peripheral allows write accesses. | ||
| 1346 | * 0b1..This peripheral is write protected. | ||
| 1347 | */ | ||
| 1348 | #define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK) | ||
| 1349 | #define AIPS_PACRB_SP1_MASK (0x4000000U) | ||
| 1350 | #define AIPS_PACRB_SP1_SHIFT (26U) | ||
| 1351 | /*! SP1 - Supervisor Protect | ||
| 1352 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1353 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1354 | */ | ||
| 1355 | #define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK) | ||
| 1356 | #define AIPS_PACRB_TP0_MASK (0x10000000U) | ||
| 1357 | #define AIPS_PACRB_TP0_SHIFT (28U) | ||
| 1358 | /*! TP0 - Trusted Protect | ||
| 1359 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1360 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1361 | */ | ||
| 1362 | #define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK) | ||
| 1363 | #define AIPS_PACRB_WP0_MASK (0x20000000U) | ||
| 1364 | #define AIPS_PACRB_WP0_SHIFT (29U) | ||
| 1365 | /*! WP0 - Write Protect | ||
| 1366 | * 0b0..This peripheral allows write accesses. | ||
| 1367 | * 0b1..This peripheral is write protected. | ||
| 1368 | */ | ||
| 1369 | #define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK) | ||
| 1370 | #define AIPS_PACRB_SP0_MASK (0x40000000U) | ||
| 1371 | #define AIPS_PACRB_SP0_SHIFT (30U) | ||
| 1372 | /*! SP0 - Supervisor Protect | ||
| 1373 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1374 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1375 | */ | ||
| 1376 | #define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK) | ||
| 1377 | /*! @} */ | ||
| 1378 | |||
| 1379 | /*! @name PACRC - Peripheral Access Control Register */ | ||
| 1380 | /*! @{ */ | ||
| 1381 | #define AIPS_PACRC_TP7_MASK (0x1U) | ||
| 1382 | #define AIPS_PACRC_TP7_SHIFT (0U) | ||
| 1383 | /*! TP7 - Trusted Protect | ||
| 1384 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1385 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1386 | */ | ||
| 1387 | #define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK) | ||
| 1388 | #define AIPS_PACRC_WP7_MASK (0x2U) | ||
| 1389 | #define AIPS_PACRC_WP7_SHIFT (1U) | ||
| 1390 | /*! WP7 - Write Protect | ||
| 1391 | * 0b0..This peripheral allows write accesses. | ||
| 1392 | * 0b1..This peripheral is write protected. | ||
| 1393 | */ | ||
| 1394 | #define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK) | ||
| 1395 | #define AIPS_PACRC_SP7_MASK (0x4U) | ||
| 1396 | #define AIPS_PACRC_SP7_SHIFT (2U) | ||
| 1397 | /*! SP7 - Supervisor Protect | ||
| 1398 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1399 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1400 | */ | ||
| 1401 | #define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK) | ||
| 1402 | #define AIPS_PACRC_TP6_MASK (0x10U) | ||
| 1403 | #define AIPS_PACRC_TP6_SHIFT (4U) | ||
| 1404 | /*! TP6 - Trusted Protect | ||
| 1405 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1406 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1407 | */ | ||
| 1408 | #define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK) | ||
| 1409 | #define AIPS_PACRC_WP6_MASK (0x20U) | ||
| 1410 | #define AIPS_PACRC_WP6_SHIFT (5U) | ||
| 1411 | /*! WP6 - Write Protect | ||
| 1412 | * 0b0..This peripheral allows write accesses. | ||
| 1413 | * 0b1..This peripheral is write protected. | ||
| 1414 | */ | ||
| 1415 | #define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK) | ||
| 1416 | #define AIPS_PACRC_SP6_MASK (0x40U) | ||
| 1417 | #define AIPS_PACRC_SP6_SHIFT (6U) | ||
| 1418 | /*! SP6 - Supervisor Protect | ||
| 1419 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1420 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1421 | */ | ||
| 1422 | #define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK) | ||
| 1423 | #define AIPS_PACRC_TP5_MASK (0x100U) | ||
| 1424 | #define AIPS_PACRC_TP5_SHIFT (8U) | ||
| 1425 | /*! TP5 - Trusted Protect | ||
| 1426 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1427 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1428 | */ | ||
| 1429 | #define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK) | ||
| 1430 | #define AIPS_PACRC_WP5_MASK (0x200U) | ||
| 1431 | #define AIPS_PACRC_WP5_SHIFT (9U) | ||
| 1432 | /*! WP5 - Write Protect | ||
| 1433 | * 0b0..This peripheral allows write accesses. | ||
| 1434 | * 0b1..This peripheral is write protected. | ||
| 1435 | */ | ||
| 1436 | #define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK) | ||
| 1437 | #define AIPS_PACRC_SP5_MASK (0x400U) | ||
| 1438 | #define AIPS_PACRC_SP5_SHIFT (10U) | ||
| 1439 | /*! SP5 - Supervisor Protect | ||
| 1440 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1441 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1442 | */ | ||
| 1443 | #define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK) | ||
| 1444 | #define AIPS_PACRC_TP4_MASK (0x1000U) | ||
| 1445 | #define AIPS_PACRC_TP4_SHIFT (12U) | ||
| 1446 | /*! TP4 - Trusted Protect | ||
| 1447 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1448 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1449 | */ | ||
| 1450 | #define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK) | ||
| 1451 | #define AIPS_PACRC_WP4_MASK (0x2000U) | ||
| 1452 | #define AIPS_PACRC_WP4_SHIFT (13U) | ||
| 1453 | /*! WP4 - Write Protect | ||
| 1454 | * 0b0..This peripheral allows write accesses. | ||
| 1455 | * 0b1..This peripheral is write protected. | ||
| 1456 | */ | ||
| 1457 | #define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK) | ||
| 1458 | #define AIPS_PACRC_SP4_MASK (0x4000U) | ||
| 1459 | #define AIPS_PACRC_SP4_SHIFT (14U) | ||
| 1460 | /*! SP4 - Supervisor Protect | ||
| 1461 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1462 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1463 | */ | ||
| 1464 | #define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK) | ||
| 1465 | #define AIPS_PACRC_TP3_MASK (0x10000U) | ||
| 1466 | #define AIPS_PACRC_TP3_SHIFT (16U) | ||
| 1467 | /*! TP3 - Trusted Protect | ||
| 1468 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1469 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1470 | */ | ||
| 1471 | #define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK) | ||
| 1472 | #define AIPS_PACRC_WP3_MASK (0x20000U) | ||
| 1473 | #define AIPS_PACRC_WP3_SHIFT (17U) | ||
| 1474 | /*! WP3 - Write Protect | ||
| 1475 | * 0b0..This peripheral allows write accesses. | ||
| 1476 | * 0b1..This peripheral is write protected. | ||
| 1477 | */ | ||
| 1478 | #define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK) | ||
| 1479 | #define AIPS_PACRC_SP3_MASK (0x40000U) | ||
| 1480 | #define AIPS_PACRC_SP3_SHIFT (18U) | ||
| 1481 | /*! SP3 - Supervisor Protect | ||
| 1482 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1483 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1484 | */ | ||
| 1485 | #define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK) | ||
| 1486 | #define AIPS_PACRC_TP2_MASK (0x100000U) | ||
| 1487 | #define AIPS_PACRC_TP2_SHIFT (20U) | ||
| 1488 | /*! TP2 - Trusted Protect | ||
| 1489 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1490 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1491 | */ | ||
| 1492 | #define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK) | ||
| 1493 | #define AIPS_PACRC_WP2_MASK (0x200000U) | ||
| 1494 | #define AIPS_PACRC_WP2_SHIFT (21U) | ||
| 1495 | /*! WP2 - Write Protect | ||
| 1496 | * 0b0..This peripheral allows write accesses. | ||
| 1497 | * 0b1..This peripheral is write protected. | ||
| 1498 | */ | ||
| 1499 | #define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK) | ||
| 1500 | #define AIPS_PACRC_SP2_MASK (0x400000U) | ||
| 1501 | #define AIPS_PACRC_SP2_SHIFT (22U) | ||
| 1502 | /*! SP2 - Supervisor Protect | ||
| 1503 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1504 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1505 | */ | ||
| 1506 | #define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK) | ||
| 1507 | #define AIPS_PACRC_TP1_MASK (0x1000000U) | ||
| 1508 | #define AIPS_PACRC_TP1_SHIFT (24U) | ||
| 1509 | /*! TP1 - Trusted Protect | ||
| 1510 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1511 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1512 | */ | ||
| 1513 | #define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK) | ||
| 1514 | #define AIPS_PACRC_WP1_MASK (0x2000000U) | ||
| 1515 | #define AIPS_PACRC_WP1_SHIFT (25U) | ||
| 1516 | /*! WP1 - Write Protect | ||
| 1517 | * 0b0..This peripheral allows write accesses. | ||
| 1518 | * 0b1..This peripheral is write protected. | ||
| 1519 | */ | ||
| 1520 | #define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK) | ||
| 1521 | #define AIPS_PACRC_SP1_MASK (0x4000000U) | ||
| 1522 | #define AIPS_PACRC_SP1_SHIFT (26U) | ||
| 1523 | /*! SP1 - Supervisor Protect | ||
| 1524 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1525 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1526 | */ | ||
| 1527 | #define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK) | ||
| 1528 | #define AIPS_PACRC_TP0_MASK (0x10000000U) | ||
| 1529 | #define AIPS_PACRC_TP0_SHIFT (28U) | ||
| 1530 | /*! TP0 - Trusted Protect | ||
| 1531 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1532 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1533 | */ | ||
| 1534 | #define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK) | ||
| 1535 | #define AIPS_PACRC_WP0_MASK (0x20000000U) | ||
| 1536 | #define AIPS_PACRC_WP0_SHIFT (29U) | ||
| 1537 | /*! WP0 - Write Protect | ||
| 1538 | * 0b0..This peripheral allows write accesses. | ||
| 1539 | * 0b1..This peripheral is write protected. | ||
| 1540 | */ | ||
| 1541 | #define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK) | ||
| 1542 | #define AIPS_PACRC_SP0_MASK (0x40000000U) | ||
| 1543 | #define AIPS_PACRC_SP0_SHIFT (30U) | ||
| 1544 | /*! SP0 - Supervisor Protect | ||
| 1545 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1546 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1547 | */ | ||
| 1548 | #define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK) | ||
| 1549 | /*! @} */ | ||
| 1550 | |||
| 1551 | /*! @name PACRD - Peripheral Access Control Register */ | ||
| 1552 | /*! @{ */ | ||
| 1553 | #define AIPS_PACRD_TP7_MASK (0x1U) | ||
| 1554 | #define AIPS_PACRD_TP7_SHIFT (0U) | ||
| 1555 | /*! TP7 - Trusted Protect | ||
| 1556 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1557 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1558 | */ | ||
| 1559 | #define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK) | ||
| 1560 | #define AIPS_PACRD_WP7_MASK (0x2U) | ||
| 1561 | #define AIPS_PACRD_WP7_SHIFT (1U) | ||
| 1562 | /*! WP7 - Write Protect | ||
| 1563 | * 0b0..This peripheral allows write accesses. | ||
| 1564 | * 0b1..This peripheral is write protected. | ||
| 1565 | */ | ||
| 1566 | #define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK) | ||
| 1567 | #define AIPS_PACRD_SP7_MASK (0x4U) | ||
| 1568 | #define AIPS_PACRD_SP7_SHIFT (2U) | ||
| 1569 | /*! SP7 - Supervisor Protect | ||
| 1570 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1571 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1572 | */ | ||
| 1573 | #define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK) | ||
| 1574 | #define AIPS_PACRD_TP6_MASK (0x10U) | ||
| 1575 | #define AIPS_PACRD_TP6_SHIFT (4U) | ||
| 1576 | /*! TP6 - Trusted Protect | ||
| 1577 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1578 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1579 | */ | ||
| 1580 | #define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK) | ||
| 1581 | #define AIPS_PACRD_WP6_MASK (0x20U) | ||
| 1582 | #define AIPS_PACRD_WP6_SHIFT (5U) | ||
| 1583 | /*! WP6 - Write Protect | ||
| 1584 | * 0b0..This peripheral allows write accesses. | ||
| 1585 | * 0b1..This peripheral is write protected. | ||
| 1586 | */ | ||
| 1587 | #define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK) | ||
| 1588 | #define AIPS_PACRD_SP6_MASK (0x40U) | ||
| 1589 | #define AIPS_PACRD_SP6_SHIFT (6U) | ||
| 1590 | /*! SP6 - Supervisor Protect | ||
| 1591 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1592 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1593 | */ | ||
| 1594 | #define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK) | ||
| 1595 | #define AIPS_PACRD_TP5_MASK (0x100U) | ||
| 1596 | #define AIPS_PACRD_TP5_SHIFT (8U) | ||
| 1597 | /*! TP5 - Trusted Protect | ||
| 1598 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1599 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1600 | */ | ||
| 1601 | #define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK) | ||
| 1602 | #define AIPS_PACRD_WP5_MASK (0x200U) | ||
| 1603 | #define AIPS_PACRD_WP5_SHIFT (9U) | ||
| 1604 | /*! WP5 - Write Protect | ||
| 1605 | * 0b0..This peripheral allows write accesses. | ||
| 1606 | * 0b1..This peripheral is write protected. | ||
| 1607 | */ | ||
| 1608 | #define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK) | ||
| 1609 | #define AIPS_PACRD_SP5_MASK (0x400U) | ||
| 1610 | #define AIPS_PACRD_SP5_SHIFT (10U) | ||
| 1611 | /*! SP5 - Supervisor Protect | ||
| 1612 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1613 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1614 | */ | ||
| 1615 | #define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK) | ||
| 1616 | #define AIPS_PACRD_TP4_MASK (0x1000U) | ||
| 1617 | #define AIPS_PACRD_TP4_SHIFT (12U) | ||
| 1618 | /*! TP4 - Trusted Protect | ||
| 1619 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1620 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1621 | */ | ||
| 1622 | #define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK) | ||
| 1623 | #define AIPS_PACRD_WP4_MASK (0x2000U) | ||
| 1624 | #define AIPS_PACRD_WP4_SHIFT (13U) | ||
| 1625 | /*! WP4 - Write Protect | ||
| 1626 | * 0b0..This peripheral allows write accesses. | ||
| 1627 | * 0b1..This peripheral is write protected. | ||
| 1628 | */ | ||
| 1629 | #define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK) | ||
| 1630 | #define AIPS_PACRD_SP4_MASK (0x4000U) | ||
| 1631 | #define AIPS_PACRD_SP4_SHIFT (14U) | ||
| 1632 | /*! SP4 - Supervisor Protect | ||
| 1633 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1634 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1635 | */ | ||
| 1636 | #define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK) | ||
| 1637 | #define AIPS_PACRD_TP3_MASK (0x10000U) | ||
| 1638 | #define AIPS_PACRD_TP3_SHIFT (16U) | ||
| 1639 | /*! TP3 - Trusted Protect | ||
| 1640 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1641 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1642 | */ | ||
| 1643 | #define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK) | ||
| 1644 | #define AIPS_PACRD_WP3_MASK (0x20000U) | ||
| 1645 | #define AIPS_PACRD_WP3_SHIFT (17U) | ||
| 1646 | /*! WP3 - Write Protect | ||
| 1647 | * 0b0..This peripheral allows write accesses. | ||
| 1648 | * 0b1..This peripheral is write protected. | ||
| 1649 | */ | ||
| 1650 | #define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK) | ||
| 1651 | #define AIPS_PACRD_SP3_MASK (0x40000U) | ||
| 1652 | #define AIPS_PACRD_SP3_SHIFT (18U) | ||
| 1653 | /*! SP3 - Supervisor Protect | ||
| 1654 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1655 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1656 | */ | ||
| 1657 | #define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK) | ||
| 1658 | #define AIPS_PACRD_TP2_MASK (0x100000U) | ||
| 1659 | #define AIPS_PACRD_TP2_SHIFT (20U) | ||
| 1660 | /*! TP2 - Trusted Protect | ||
| 1661 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1662 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1663 | */ | ||
| 1664 | #define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK) | ||
| 1665 | #define AIPS_PACRD_WP2_MASK (0x200000U) | ||
| 1666 | #define AIPS_PACRD_WP2_SHIFT (21U) | ||
| 1667 | /*! WP2 - Write Protect | ||
| 1668 | * 0b0..This peripheral allows write accesses. | ||
| 1669 | * 0b1..This peripheral is write protected. | ||
| 1670 | */ | ||
| 1671 | #define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK) | ||
| 1672 | #define AIPS_PACRD_SP2_MASK (0x400000U) | ||
| 1673 | #define AIPS_PACRD_SP2_SHIFT (22U) | ||
| 1674 | /*! SP2 - Supervisor Protect | ||
| 1675 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1676 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1677 | */ | ||
| 1678 | #define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK) | ||
| 1679 | #define AIPS_PACRD_TP1_MASK (0x1000000U) | ||
| 1680 | #define AIPS_PACRD_TP1_SHIFT (24U) | ||
| 1681 | /*! TP1 - Trusted Protect | ||
| 1682 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1683 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1684 | */ | ||
| 1685 | #define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK) | ||
| 1686 | #define AIPS_PACRD_WP1_MASK (0x2000000U) | ||
| 1687 | #define AIPS_PACRD_WP1_SHIFT (25U) | ||
| 1688 | /*! WP1 - Write Protect | ||
| 1689 | * 0b0..This peripheral allows write accesses. | ||
| 1690 | * 0b1..This peripheral is write protected. | ||
| 1691 | */ | ||
| 1692 | #define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK) | ||
| 1693 | #define AIPS_PACRD_SP1_MASK (0x4000000U) | ||
| 1694 | #define AIPS_PACRD_SP1_SHIFT (26U) | ||
| 1695 | /*! SP1 - Supervisor Protect | ||
| 1696 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1697 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1698 | */ | ||
| 1699 | #define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK) | ||
| 1700 | #define AIPS_PACRD_TP0_MASK (0x10000000U) | ||
| 1701 | #define AIPS_PACRD_TP0_SHIFT (28U) | ||
| 1702 | /*! TP0 - Trusted Protect | ||
| 1703 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1704 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1705 | */ | ||
| 1706 | #define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK) | ||
| 1707 | #define AIPS_PACRD_WP0_MASK (0x20000000U) | ||
| 1708 | #define AIPS_PACRD_WP0_SHIFT (29U) | ||
| 1709 | /*! WP0 - Write Protect | ||
| 1710 | * 0b0..This peripheral allows write accesses. | ||
| 1711 | * 0b1..This peripheral is write protected. | ||
| 1712 | */ | ||
| 1713 | #define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK) | ||
| 1714 | #define AIPS_PACRD_SP0_MASK (0x40000000U) | ||
| 1715 | #define AIPS_PACRD_SP0_SHIFT (30U) | ||
| 1716 | /*! SP0 - Supervisor Protect | ||
| 1717 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1718 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1719 | */ | ||
| 1720 | #define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK) | ||
| 1721 | /*! @} */ | ||
| 1722 | |||
| 1723 | /*! @name PACRE - Peripheral Access Control Register */ | ||
| 1724 | /*! @{ */ | ||
| 1725 | #define AIPS_PACRE_TP7_MASK (0x1U) | ||
| 1726 | #define AIPS_PACRE_TP7_SHIFT (0U) | ||
| 1727 | /*! TP7 - Trusted Protect | ||
| 1728 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1729 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1730 | */ | ||
| 1731 | #define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK) | ||
| 1732 | #define AIPS_PACRE_WP7_MASK (0x2U) | ||
| 1733 | #define AIPS_PACRE_WP7_SHIFT (1U) | ||
| 1734 | /*! WP7 - Write Protect | ||
| 1735 | * 0b0..This peripheral allows write accesses. | ||
| 1736 | * 0b1..This peripheral is write protected. | ||
| 1737 | */ | ||
| 1738 | #define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK) | ||
| 1739 | #define AIPS_PACRE_SP7_MASK (0x4U) | ||
| 1740 | #define AIPS_PACRE_SP7_SHIFT (2U) | ||
| 1741 | /*! SP7 - Supervisor Protect | ||
| 1742 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1743 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1744 | */ | ||
| 1745 | #define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK) | ||
| 1746 | #define AIPS_PACRE_TP6_MASK (0x10U) | ||
| 1747 | #define AIPS_PACRE_TP6_SHIFT (4U) | ||
| 1748 | /*! TP6 - Trusted Protect | ||
| 1749 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1750 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1751 | */ | ||
| 1752 | #define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK) | ||
| 1753 | #define AIPS_PACRE_WP6_MASK (0x20U) | ||
| 1754 | #define AIPS_PACRE_WP6_SHIFT (5U) | ||
| 1755 | /*! WP6 - Write Protect | ||
| 1756 | * 0b0..This peripheral allows write accesses. | ||
| 1757 | * 0b1..This peripheral is write protected. | ||
| 1758 | */ | ||
| 1759 | #define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK) | ||
| 1760 | #define AIPS_PACRE_SP6_MASK (0x40U) | ||
| 1761 | #define AIPS_PACRE_SP6_SHIFT (6U) | ||
| 1762 | /*! SP6 - Supervisor Protect | ||
| 1763 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1764 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1765 | */ | ||
| 1766 | #define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK) | ||
| 1767 | #define AIPS_PACRE_TP5_MASK (0x100U) | ||
| 1768 | #define AIPS_PACRE_TP5_SHIFT (8U) | ||
| 1769 | /*! TP5 - Trusted Protect | ||
| 1770 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1771 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1772 | */ | ||
| 1773 | #define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK) | ||
| 1774 | #define AIPS_PACRE_WP5_MASK (0x200U) | ||
| 1775 | #define AIPS_PACRE_WP5_SHIFT (9U) | ||
| 1776 | /*! WP5 - Write Protect | ||
| 1777 | * 0b0..This peripheral allows write accesses. | ||
| 1778 | * 0b1..This peripheral is write protected. | ||
| 1779 | */ | ||
| 1780 | #define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK) | ||
| 1781 | #define AIPS_PACRE_SP5_MASK (0x400U) | ||
| 1782 | #define AIPS_PACRE_SP5_SHIFT (10U) | ||
| 1783 | /*! SP5 - Supervisor Protect | ||
| 1784 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1785 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1786 | */ | ||
| 1787 | #define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK) | ||
| 1788 | #define AIPS_PACRE_TP4_MASK (0x1000U) | ||
| 1789 | #define AIPS_PACRE_TP4_SHIFT (12U) | ||
| 1790 | /*! TP4 - Trusted Protect | ||
| 1791 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1792 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1793 | */ | ||
| 1794 | #define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK) | ||
| 1795 | #define AIPS_PACRE_WP4_MASK (0x2000U) | ||
| 1796 | #define AIPS_PACRE_WP4_SHIFT (13U) | ||
| 1797 | /*! WP4 - Write Protect | ||
| 1798 | * 0b0..This peripheral allows write accesses. | ||
| 1799 | * 0b1..This peripheral is write protected. | ||
| 1800 | */ | ||
| 1801 | #define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK) | ||
| 1802 | #define AIPS_PACRE_SP4_MASK (0x4000U) | ||
| 1803 | #define AIPS_PACRE_SP4_SHIFT (14U) | ||
| 1804 | /*! SP4 - Supervisor Protect | ||
| 1805 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1806 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1807 | */ | ||
| 1808 | #define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK) | ||
| 1809 | #define AIPS_PACRE_TP3_MASK (0x10000U) | ||
| 1810 | #define AIPS_PACRE_TP3_SHIFT (16U) | ||
| 1811 | /*! TP3 - Trusted Protect | ||
| 1812 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1813 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1814 | */ | ||
| 1815 | #define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK) | ||
| 1816 | #define AIPS_PACRE_WP3_MASK (0x20000U) | ||
| 1817 | #define AIPS_PACRE_WP3_SHIFT (17U) | ||
| 1818 | /*! WP3 - Write Protect | ||
| 1819 | * 0b0..This peripheral allows write accesses. | ||
| 1820 | * 0b1..This peripheral is write protected. | ||
| 1821 | */ | ||
| 1822 | #define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK) | ||
| 1823 | #define AIPS_PACRE_SP3_MASK (0x40000U) | ||
| 1824 | #define AIPS_PACRE_SP3_SHIFT (18U) | ||
| 1825 | /*! SP3 - Supervisor Protect | ||
| 1826 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1827 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1828 | */ | ||
| 1829 | #define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK) | ||
| 1830 | #define AIPS_PACRE_TP2_MASK (0x100000U) | ||
| 1831 | #define AIPS_PACRE_TP2_SHIFT (20U) | ||
| 1832 | /*! TP2 - Trusted Protect | ||
| 1833 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1834 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1835 | */ | ||
| 1836 | #define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK) | ||
| 1837 | #define AIPS_PACRE_WP2_MASK (0x200000U) | ||
| 1838 | #define AIPS_PACRE_WP2_SHIFT (21U) | ||
| 1839 | /*! WP2 - Write Protect | ||
| 1840 | * 0b0..This peripheral allows write accesses. | ||
| 1841 | * 0b1..This peripheral is write protected. | ||
| 1842 | */ | ||
| 1843 | #define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK) | ||
| 1844 | #define AIPS_PACRE_SP2_MASK (0x400000U) | ||
| 1845 | #define AIPS_PACRE_SP2_SHIFT (22U) | ||
| 1846 | /*! SP2 - Supervisor Protect | ||
| 1847 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1848 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1849 | */ | ||
| 1850 | #define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK) | ||
| 1851 | #define AIPS_PACRE_TP1_MASK (0x1000000U) | ||
| 1852 | #define AIPS_PACRE_TP1_SHIFT (24U) | ||
| 1853 | /*! TP1 - Trusted Protect | ||
| 1854 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1855 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1856 | */ | ||
| 1857 | #define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK) | ||
| 1858 | #define AIPS_PACRE_WP1_MASK (0x2000000U) | ||
| 1859 | #define AIPS_PACRE_WP1_SHIFT (25U) | ||
| 1860 | /*! WP1 - Write Protect | ||
| 1861 | * 0b0..This peripheral allows write accesses. | ||
| 1862 | * 0b1..This peripheral is write protected. | ||
| 1863 | */ | ||
| 1864 | #define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK) | ||
| 1865 | #define AIPS_PACRE_SP1_MASK (0x4000000U) | ||
| 1866 | #define AIPS_PACRE_SP1_SHIFT (26U) | ||
| 1867 | /*! SP1 - Supervisor Protect | ||
| 1868 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1869 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1870 | */ | ||
| 1871 | #define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK) | ||
| 1872 | #define AIPS_PACRE_TP0_MASK (0x10000000U) | ||
| 1873 | #define AIPS_PACRE_TP0_SHIFT (28U) | ||
| 1874 | /*! TP0 - Trusted Protect | ||
| 1875 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1876 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1877 | */ | ||
| 1878 | #define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK) | ||
| 1879 | #define AIPS_PACRE_WP0_MASK (0x20000000U) | ||
| 1880 | #define AIPS_PACRE_WP0_SHIFT (29U) | ||
| 1881 | /*! WP0 - Write Protect | ||
| 1882 | * 0b0..This peripheral allows write accesses. | ||
| 1883 | * 0b1..This peripheral is write protected. | ||
| 1884 | */ | ||
| 1885 | #define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK) | ||
| 1886 | #define AIPS_PACRE_SP0_MASK (0x40000000U) | ||
| 1887 | #define AIPS_PACRE_SP0_SHIFT (30U) | ||
| 1888 | /*! SP0 - Supervisor Protect | ||
| 1889 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1890 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1891 | */ | ||
| 1892 | #define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK) | ||
| 1893 | /*! @} */ | ||
| 1894 | |||
| 1895 | /*! @name PACRF - Peripheral Access Control Register */ | ||
| 1896 | /*! @{ */ | ||
| 1897 | #define AIPS_PACRF_TP7_MASK (0x1U) | ||
| 1898 | #define AIPS_PACRF_TP7_SHIFT (0U) | ||
| 1899 | /*! TP7 - Trusted Protect | ||
| 1900 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1901 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1902 | */ | ||
| 1903 | #define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK) | ||
| 1904 | #define AIPS_PACRF_WP7_MASK (0x2U) | ||
| 1905 | #define AIPS_PACRF_WP7_SHIFT (1U) | ||
| 1906 | /*! WP7 - Write Protect | ||
| 1907 | * 0b0..This peripheral allows write accesses. | ||
| 1908 | * 0b1..This peripheral is write protected. | ||
| 1909 | */ | ||
| 1910 | #define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK) | ||
| 1911 | #define AIPS_PACRF_SP7_MASK (0x4U) | ||
| 1912 | #define AIPS_PACRF_SP7_SHIFT (2U) | ||
| 1913 | /*! SP7 - Supervisor Protect | ||
| 1914 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1915 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1916 | */ | ||
| 1917 | #define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK) | ||
| 1918 | #define AIPS_PACRF_TP6_MASK (0x10U) | ||
| 1919 | #define AIPS_PACRF_TP6_SHIFT (4U) | ||
| 1920 | /*! TP6 - Trusted Protect | ||
| 1921 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1922 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1923 | */ | ||
| 1924 | #define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK) | ||
| 1925 | #define AIPS_PACRF_WP6_MASK (0x20U) | ||
| 1926 | #define AIPS_PACRF_WP6_SHIFT (5U) | ||
| 1927 | /*! WP6 - Write Protect | ||
| 1928 | * 0b0..This peripheral allows write accesses. | ||
| 1929 | * 0b1..This peripheral is write protected. | ||
| 1930 | */ | ||
| 1931 | #define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK) | ||
| 1932 | #define AIPS_PACRF_SP6_MASK (0x40U) | ||
| 1933 | #define AIPS_PACRF_SP6_SHIFT (6U) | ||
| 1934 | /*! SP6 - Supervisor Protect | ||
| 1935 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1936 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1937 | */ | ||
| 1938 | #define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK) | ||
| 1939 | #define AIPS_PACRF_TP5_MASK (0x100U) | ||
| 1940 | #define AIPS_PACRF_TP5_SHIFT (8U) | ||
| 1941 | /*! TP5 - Trusted Protect | ||
| 1942 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1943 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1944 | */ | ||
| 1945 | #define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK) | ||
| 1946 | #define AIPS_PACRF_WP5_MASK (0x200U) | ||
| 1947 | #define AIPS_PACRF_WP5_SHIFT (9U) | ||
| 1948 | /*! WP5 - Write Protect | ||
| 1949 | * 0b0..This peripheral allows write accesses. | ||
| 1950 | * 0b1..This peripheral is write protected. | ||
| 1951 | */ | ||
| 1952 | #define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK) | ||
| 1953 | #define AIPS_PACRF_SP5_MASK (0x400U) | ||
| 1954 | #define AIPS_PACRF_SP5_SHIFT (10U) | ||
| 1955 | /*! SP5 - Supervisor Protect | ||
| 1956 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1957 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1958 | */ | ||
| 1959 | #define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK) | ||
| 1960 | #define AIPS_PACRF_TP4_MASK (0x1000U) | ||
| 1961 | #define AIPS_PACRF_TP4_SHIFT (12U) | ||
| 1962 | /*! TP4 - Trusted Protect | ||
| 1963 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1964 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1965 | */ | ||
| 1966 | #define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK) | ||
| 1967 | #define AIPS_PACRF_WP4_MASK (0x2000U) | ||
| 1968 | #define AIPS_PACRF_WP4_SHIFT (13U) | ||
| 1969 | /*! WP4 - Write Protect | ||
| 1970 | * 0b0..This peripheral allows write accesses. | ||
| 1971 | * 0b1..This peripheral is write protected. | ||
| 1972 | */ | ||
| 1973 | #define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK) | ||
| 1974 | #define AIPS_PACRF_SP4_MASK (0x4000U) | ||
| 1975 | #define AIPS_PACRF_SP4_SHIFT (14U) | ||
| 1976 | /*! SP4 - Supervisor Protect | ||
| 1977 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1978 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 1979 | */ | ||
| 1980 | #define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK) | ||
| 1981 | #define AIPS_PACRF_TP3_MASK (0x10000U) | ||
| 1982 | #define AIPS_PACRF_TP3_SHIFT (16U) | ||
| 1983 | /*! TP3 - Trusted Protect | ||
| 1984 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 1985 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 1986 | */ | ||
| 1987 | #define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK) | ||
| 1988 | #define AIPS_PACRF_WP3_MASK (0x20000U) | ||
| 1989 | #define AIPS_PACRF_WP3_SHIFT (17U) | ||
| 1990 | /*! WP3 - Write Protect | ||
| 1991 | * 0b0..This peripheral allows write accesses. | ||
| 1992 | * 0b1..This peripheral is write protected. | ||
| 1993 | */ | ||
| 1994 | #define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK) | ||
| 1995 | #define AIPS_PACRF_SP3_MASK (0x40000U) | ||
| 1996 | #define AIPS_PACRF_SP3_SHIFT (18U) | ||
| 1997 | /*! SP3 - Supervisor Protect | ||
| 1998 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 1999 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2000 | */ | ||
| 2001 | #define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK) | ||
| 2002 | #define AIPS_PACRF_TP2_MASK (0x100000U) | ||
| 2003 | #define AIPS_PACRF_TP2_SHIFT (20U) | ||
| 2004 | /*! TP2 - Trusted Protect | ||
| 2005 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2006 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2007 | */ | ||
| 2008 | #define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK) | ||
| 2009 | #define AIPS_PACRF_WP2_MASK (0x200000U) | ||
| 2010 | #define AIPS_PACRF_WP2_SHIFT (21U) | ||
| 2011 | /*! WP2 - Write Protect | ||
| 2012 | * 0b0..This peripheral allows write accesses. | ||
| 2013 | * 0b1..This peripheral is write protected. | ||
| 2014 | */ | ||
| 2015 | #define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK) | ||
| 2016 | #define AIPS_PACRF_SP2_MASK (0x400000U) | ||
| 2017 | #define AIPS_PACRF_SP2_SHIFT (22U) | ||
| 2018 | /*! SP2 - Supervisor Protect | ||
| 2019 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2020 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2021 | */ | ||
| 2022 | #define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK) | ||
| 2023 | #define AIPS_PACRF_TP1_MASK (0x1000000U) | ||
| 2024 | #define AIPS_PACRF_TP1_SHIFT (24U) | ||
| 2025 | /*! TP1 - Trusted Protect | ||
| 2026 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2027 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2028 | */ | ||
| 2029 | #define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK) | ||
| 2030 | #define AIPS_PACRF_WP1_MASK (0x2000000U) | ||
| 2031 | #define AIPS_PACRF_WP1_SHIFT (25U) | ||
| 2032 | /*! WP1 - Write Protect | ||
| 2033 | * 0b0..This peripheral allows write accesses. | ||
| 2034 | * 0b1..This peripheral is write protected. | ||
| 2035 | */ | ||
| 2036 | #define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK) | ||
| 2037 | #define AIPS_PACRF_SP1_MASK (0x4000000U) | ||
| 2038 | #define AIPS_PACRF_SP1_SHIFT (26U) | ||
| 2039 | /*! SP1 - Supervisor Protect | ||
| 2040 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2041 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2042 | */ | ||
| 2043 | #define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK) | ||
| 2044 | #define AIPS_PACRF_TP0_MASK (0x10000000U) | ||
| 2045 | #define AIPS_PACRF_TP0_SHIFT (28U) | ||
| 2046 | /*! TP0 - Trusted Protect | ||
| 2047 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2048 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2049 | */ | ||
| 2050 | #define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK) | ||
| 2051 | #define AIPS_PACRF_WP0_MASK (0x20000000U) | ||
| 2052 | #define AIPS_PACRF_WP0_SHIFT (29U) | ||
| 2053 | /*! WP0 - Write Protect | ||
| 2054 | * 0b0..This peripheral allows write accesses. | ||
| 2055 | * 0b1..This peripheral is write protected. | ||
| 2056 | */ | ||
| 2057 | #define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK) | ||
| 2058 | #define AIPS_PACRF_SP0_MASK (0x40000000U) | ||
| 2059 | #define AIPS_PACRF_SP0_SHIFT (30U) | ||
| 2060 | /*! SP0 - Supervisor Protect | ||
| 2061 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2062 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2063 | */ | ||
| 2064 | #define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK) | ||
| 2065 | /*! @} */ | ||
| 2066 | |||
| 2067 | /*! @name PACRG - Peripheral Access Control Register */ | ||
| 2068 | /*! @{ */ | ||
| 2069 | #define AIPS_PACRG_TP7_MASK (0x1U) | ||
| 2070 | #define AIPS_PACRG_TP7_SHIFT (0U) | ||
| 2071 | /*! TP7 - Trusted Protect | ||
| 2072 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2073 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2074 | */ | ||
| 2075 | #define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK) | ||
| 2076 | #define AIPS_PACRG_WP7_MASK (0x2U) | ||
| 2077 | #define AIPS_PACRG_WP7_SHIFT (1U) | ||
| 2078 | /*! WP7 - Write Protect | ||
| 2079 | * 0b0..This peripheral allows write accesses. | ||
| 2080 | * 0b1..This peripheral is write protected. | ||
| 2081 | */ | ||
| 2082 | #define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK) | ||
| 2083 | #define AIPS_PACRG_SP7_MASK (0x4U) | ||
| 2084 | #define AIPS_PACRG_SP7_SHIFT (2U) | ||
| 2085 | /*! SP7 - Supervisor Protect | ||
| 2086 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2087 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2088 | */ | ||
| 2089 | #define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK) | ||
| 2090 | #define AIPS_PACRG_TP6_MASK (0x10U) | ||
| 2091 | #define AIPS_PACRG_TP6_SHIFT (4U) | ||
| 2092 | /*! TP6 - Trusted Protect | ||
| 2093 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2094 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2095 | */ | ||
| 2096 | #define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK) | ||
| 2097 | #define AIPS_PACRG_WP6_MASK (0x20U) | ||
| 2098 | #define AIPS_PACRG_WP6_SHIFT (5U) | ||
| 2099 | /*! WP6 - Write Protect | ||
| 2100 | * 0b0..This peripheral allows write accesses. | ||
| 2101 | * 0b1..This peripheral is write protected. | ||
| 2102 | */ | ||
| 2103 | #define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK) | ||
| 2104 | #define AIPS_PACRG_SP6_MASK (0x40U) | ||
| 2105 | #define AIPS_PACRG_SP6_SHIFT (6U) | ||
| 2106 | /*! SP6 - Supervisor Protect | ||
| 2107 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2108 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2109 | */ | ||
| 2110 | #define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK) | ||
| 2111 | #define AIPS_PACRG_TP5_MASK (0x100U) | ||
| 2112 | #define AIPS_PACRG_TP5_SHIFT (8U) | ||
| 2113 | /*! TP5 - Trusted Protect | ||
| 2114 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2115 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2116 | */ | ||
| 2117 | #define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK) | ||
| 2118 | #define AIPS_PACRG_WP5_MASK (0x200U) | ||
| 2119 | #define AIPS_PACRG_WP5_SHIFT (9U) | ||
| 2120 | /*! WP5 - Write Protect | ||
| 2121 | * 0b0..This peripheral allows write accesses. | ||
| 2122 | * 0b1..This peripheral is write protected. | ||
| 2123 | */ | ||
| 2124 | #define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK) | ||
| 2125 | #define AIPS_PACRG_SP5_MASK (0x400U) | ||
| 2126 | #define AIPS_PACRG_SP5_SHIFT (10U) | ||
| 2127 | /*! SP5 - Supervisor Protect | ||
| 2128 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2129 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2130 | */ | ||
| 2131 | #define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK) | ||
| 2132 | #define AIPS_PACRG_TP4_MASK (0x1000U) | ||
| 2133 | #define AIPS_PACRG_TP4_SHIFT (12U) | ||
| 2134 | /*! TP4 - Trusted Protect | ||
| 2135 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2136 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2137 | */ | ||
| 2138 | #define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK) | ||
| 2139 | #define AIPS_PACRG_WP4_MASK (0x2000U) | ||
| 2140 | #define AIPS_PACRG_WP4_SHIFT (13U) | ||
| 2141 | /*! WP4 - Write Protect | ||
| 2142 | * 0b0..This peripheral allows write accesses. | ||
| 2143 | * 0b1..This peripheral is write protected. | ||
| 2144 | */ | ||
| 2145 | #define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK) | ||
| 2146 | #define AIPS_PACRG_SP4_MASK (0x4000U) | ||
| 2147 | #define AIPS_PACRG_SP4_SHIFT (14U) | ||
| 2148 | /*! SP4 - Supervisor Protect | ||
| 2149 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2150 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2151 | */ | ||
| 2152 | #define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK) | ||
| 2153 | #define AIPS_PACRG_TP3_MASK (0x10000U) | ||
| 2154 | #define AIPS_PACRG_TP3_SHIFT (16U) | ||
| 2155 | /*! TP3 - Trusted Protect | ||
| 2156 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2157 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2158 | */ | ||
| 2159 | #define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK) | ||
| 2160 | #define AIPS_PACRG_WP3_MASK (0x20000U) | ||
| 2161 | #define AIPS_PACRG_WP3_SHIFT (17U) | ||
| 2162 | /*! WP3 - Write Protect | ||
| 2163 | * 0b0..This peripheral allows write accesses. | ||
| 2164 | * 0b1..This peripheral is write protected. | ||
| 2165 | */ | ||
| 2166 | #define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK) | ||
| 2167 | #define AIPS_PACRG_SP3_MASK (0x40000U) | ||
| 2168 | #define AIPS_PACRG_SP3_SHIFT (18U) | ||
| 2169 | /*! SP3 - Supervisor Protect | ||
| 2170 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2171 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2172 | */ | ||
| 2173 | #define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK) | ||
| 2174 | #define AIPS_PACRG_TP2_MASK (0x100000U) | ||
| 2175 | #define AIPS_PACRG_TP2_SHIFT (20U) | ||
| 2176 | /*! TP2 - Trusted Protect | ||
| 2177 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2178 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2179 | */ | ||
| 2180 | #define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK) | ||
| 2181 | #define AIPS_PACRG_WP2_MASK (0x200000U) | ||
| 2182 | #define AIPS_PACRG_WP2_SHIFT (21U) | ||
| 2183 | /*! WP2 - Write Protect | ||
| 2184 | * 0b0..This peripheral allows write accesses. | ||
| 2185 | * 0b1..This peripheral is write protected. | ||
| 2186 | */ | ||
| 2187 | #define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK) | ||
| 2188 | #define AIPS_PACRG_SP2_MASK (0x400000U) | ||
| 2189 | #define AIPS_PACRG_SP2_SHIFT (22U) | ||
| 2190 | /*! SP2 - Supervisor Protect | ||
| 2191 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2192 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2193 | */ | ||
| 2194 | #define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK) | ||
| 2195 | #define AIPS_PACRG_TP1_MASK (0x1000000U) | ||
| 2196 | #define AIPS_PACRG_TP1_SHIFT (24U) | ||
| 2197 | /*! TP1 - Trusted Protect | ||
| 2198 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2199 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2200 | */ | ||
| 2201 | #define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK) | ||
| 2202 | #define AIPS_PACRG_WP1_MASK (0x2000000U) | ||
| 2203 | #define AIPS_PACRG_WP1_SHIFT (25U) | ||
| 2204 | /*! WP1 - Write Protect | ||
| 2205 | * 0b0..This peripheral allows write accesses. | ||
| 2206 | * 0b1..This peripheral is write protected. | ||
| 2207 | */ | ||
| 2208 | #define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK) | ||
| 2209 | #define AIPS_PACRG_SP1_MASK (0x4000000U) | ||
| 2210 | #define AIPS_PACRG_SP1_SHIFT (26U) | ||
| 2211 | /*! SP1 - Supervisor Protect | ||
| 2212 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2213 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2214 | */ | ||
| 2215 | #define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK) | ||
| 2216 | #define AIPS_PACRG_TP0_MASK (0x10000000U) | ||
| 2217 | #define AIPS_PACRG_TP0_SHIFT (28U) | ||
| 2218 | /*! TP0 - Trusted Protect | ||
| 2219 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2220 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2221 | */ | ||
| 2222 | #define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK) | ||
| 2223 | #define AIPS_PACRG_WP0_MASK (0x20000000U) | ||
| 2224 | #define AIPS_PACRG_WP0_SHIFT (29U) | ||
| 2225 | /*! WP0 - Write Protect | ||
| 2226 | * 0b0..This peripheral allows write accesses. | ||
| 2227 | * 0b1..This peripheral is write protected. | ||
| 2228 | */ | ||
| 2229 | #define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK) | ||
| 2230 | #define AIPS_PACRG_SP0_MASK (0x40000000U) | ||
| 2231 | #define AIPS_PACRG_SP0_SHIFT (30U) | ||
| 2232 | /*! SP0 - Supervisor Protect | ||
| 2233 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2234 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2235 | */ | ||
| 2236 | #define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK) | ||
| 2237 | /*! @} */ | ||
| 2238 | |||
| 2239 | /*! @name PACRH - Peripheral Access Control Register */ | ||
| 2240 | /*! @{ */ | ||
| 2241 | #define AIPS_PACRH_TP7_MASK (0x1U) | ||
| 2242 | #define AIPS_PACRH_TP7_SHIFT (0U) | ||
| 2243 | /*! TP7 - Trusted Protect | ||
| 2244 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2245 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2246 | */ | ||
| 2247 | #define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK) | ||
| 2248 | #define AIPS_PACRH_WP7_MASK (0x2U) | ||
| 2249 | #define AIPS_PACRH_WP7_SHIFT (1U) | ||
| 2250 | /*! WP7 - Write Protect | ||
| 2251 | * 0b0..This peripheral allows write accesses. | ||
| 2252 | * 0b1..This peripheral is write protected. | ||
| 2253 | */ | ||
| 2254 | #define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK) | ||
| 2255 | #define AIPS_PACRH_SP7_MASK (0x4U) | ||
| 2256 | #define AIPS_PACRH_SP7_SHIFT (2U) | ||
| 2257 | /*! SP7 - Supervisor Protect | ||
| 2258 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2259 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2260 | */ | ||
| 2261 | #define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK) | ||
| 2262 | #define AIPS_PACRH_TP6_MASK (0x10U) | ||
| 2263 | #define AIPS_PACRH_TP6_SHIFT (4U) | ||
| 2264 | /*! TP6 - Trusted Protect | ||
| 2265 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2266 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2267 | */ | ||
| 2268 | #define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK) | ||
| 2269 | #define AIPS_PACRH_WP6_MASK (0x20U) | ||
| 2270 | #define AIPS_PACRH_WP6_SHIFT (5U) | ||
| 2271 | /*! WP6 - Write Protect | ||
| 2272 | * 0b0..This peripheral allows write accesses. | ||
| 2273 | * 0b1..This peripheral is write protected. | ||
| 2274 | */ | ||
| 2275 | #define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK) | ||
| 2276 | #define AIPS_PACRH_SP6_MASK (0x40U) | ||
| 2277 | #define AIPS_PACRH_SP6_SHIFT (6U) | ||
| 2278 | /*! SP6 - Supervisor Protect | ||
| 2279 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2280 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2281 | */ | ||
| 2282 | #define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK) | ||
| 2283 | #define AIPS_PACRH_TP5_MASK (0x100U) | ||
| 2284 | #define AIPS_PACRH_TP5_SHIFT (8U) | ||
| 2285 | /*! TP5 - Trusted Protect | ||
| 2286 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2287 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2288 | */ | ||
| 2289 | #define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK) | ||
| 2290 | #define AIPS_PACRH_WP5_MASK (0x200U) | ||
| 2291 | #define AIPS_PACRH_WP5_SHIFT (9U) | ||
| 2292 | /*! WP5 - Write Protect | ||
| 2293 | * 0b0..This peripheral allows write accesses. | ||
| 2294 | * 0b1..This peripheral is write protected. | ||
| 2295 | */ | ||
| 2296 | #define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK) | ||
| 2297 | #define AIPS_PACRH_SP5_MASK (0x400U) | ||
| 2298 | #define AIPS_PACRH_SP5_SHIFT (10U) | ||
| 2299 | /*! SP5 - Supervisor Protect | ||
| 2300 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2301 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2302 | */ | ||
| 2303 | #define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK) | ||
| 2304 | #define AIPS_PACRH_TP4_MASK (0x1000U) | ||
| 2305 | #define AIPS_PACRH_TP4_SHIFT (12U) | ||
| 2306 | /*! TP4 - Trusted Protect | ||
| 2307 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2308 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2309 | */ | ||
| 2310 | #define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK) | ||
| 2311 | #define AIPS_PACRH_WP4_MASK (0x2000U) | ||
| 2312 | #define AIPS_PACRH_WP4_SHIFT (13U) | ||
| 2313 | /*! WP4 - Write Protect | ||
| 2314 | * 0b0..This peripheral allows write accesses. | ||
| 2315 | * 0b1..This peripheral is write protected. | ||
| 2316 | */ | ||
| 2317 | #define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK) | ||
| 2318 | #define AIPS_PACRH_SP4_MASK (0x4000U) | ||
| 2319 | #define AIPS_PACRH_SP4_SHIFT (14U) | ||
| 2320 | /*! SP4 - Supervisor Protect | ||
| 2321 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2322 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2323 | */ | ||
| 2324 | #define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK) | ||
| 2325 | #define AIPS_PACRH_TP3_MASK (0x10000U) | ||
| 2326 | #define AIPS_PACRH_TP3_SHIFT (16U) | ||
| 2327 | /*! TP3 - Trusted Protect | ||
| 2328 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2329 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2330 | */ | ||
| 2331 | #define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK) | ||
| 2332 | #define AIPS_PACRH_WP3_MASK (0x20000U) | ||
| 2333 | #define AIPS_PACRH_WP3_SHIFT (17U) | ||
| 2334 | /*! WP3 - Write Protect | ||
| 2335 | * 0b0..This peripheral allows write accesses. | ||
| 2336 | * 0b1..This peripheral is write protected. | ||
| 2337 | */ | ||
| 2338 | #define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK) | ||
| 2339 | #define AIPS_PACRH_SP3_MASK (0x40000U) | ||
| 2340 | #define AIPS_PACRH_SP3_SHIFT (18U) | ||
| 2341 | /*! SP3 - Supervisor Protect | ||
| 2342 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2343 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2344 | */ | ||
| 2345 | #define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK) | ||
| 2346 | #define AIPS_PACRH_TP2_MASK (0x100000U) | ||
| 2347 | #define AIPS_PACRH_TP2_SHIFT (20U) | ||
| 2348 | /*! TP2 - Trusted Protect | ||
| 2349 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2350 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2351 | */ | ||
| 2352 | #define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK) | ||
| 2353 | #define AIPS_PACRH_WP2_MASK (0x200000U) | ||
| 2354 | #define AIPS_PACRH_WP2_SHIFT (21U) | ||
| 2355 | /*! WP2 - Write Protect | ||
| 2356 | * 0b0..This peripheral allows write accesses. | ||
| 2357 | * 0b1..This peripheral is write protected. | ||
| 2358 | */ | ||
| 2359 | #define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK) | ||
| 2360 | #define AIPS_PACRH_SP2_MASK (0x400000U) | ||
| 2361 | #define AIPS_PACRH_SP2_SHIFT (22U) | ||
| 2362 | /*! SP2 - Supervisor Protect | ||
| 2363 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2364 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2365 | */ | ||
| 2366 | #define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK) | ||
| 2367 | #define AIPS_PACRH_TP1_MASK (0x1000000U) | ||
| 2368 | #define AIPS_PACRH_TP1_SHIFT (24U) | ||
| 2369 | /*! TP1 - Trusted Protect | ||
| 2370 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2371 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2372 | */ | ||
| 2373 | #define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK) | ||
| 2374 | #define AIPS_PACRH_WP1_MASK (0x2000000U) | ||
| 2375 | #define AIPS_PACRH_WP1_SHIFT (25U) | ||
| 2376 | /*! WP1 - Write Protect | ||
| 2377 | * 0b0..This peripheral allows write accesses. | ||
| 2378 | * 0b1..This peripheral is write protected. | ||
| 2379 | */ | ||
| 2380 | #define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK) | ||
| 2381 | #define AIPS_PACRH_SP1_MASK (0x4000000U) | ||
| 2382 | #define AIPS_PACRH_SP1_SHIFT (26U) | ||
| 2383 | /*! SP1 - Supervisor Protect | ||
| 2384 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2385 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2386 | */ | ||
| 2387 | #define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK) | ||
| 2388 | #define AIPS_PACRH_TP0_MASK (0x10000000U) | ||
| 2389 | #define AIPS_PACRH_TP0_SHIFT (28U) | ||
| 2390 | /*! TP0 - Trusted Protect | ||
| 2391 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2392 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2393 | */ | ||
| 2394 | #define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK) | ||
| 2395 | #define AIPS_PACRH_WP0_MASK (0x20000000U) | ||
| 2396 | #define AIPS_PACRH_WP0_SHIFT (29U) | ||
| 2397 | /*! WP0 - Write Protect | ||
| 2398 | * 0b0..This peripheral allows write accesses. | ||
| 2399 | * 0b1..This peripheral is write protected. | ||
| 2400 | */ | ||
| 2401 | #define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK) | ||
| 2402 | #define AIPS_PACRH_SP0_MASK (0x40000000U) | ||
| 2403 | #define AIPS_PACRH_SP0_SHIFT (30U) | ||
| 2404 | /*! SP0 - Supervisor Protect | ||
| 2405 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2406 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2407 | */ | ||
| 2408 | #define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK) | ||
| 2409 | /*! @} */ | ||
| 2410 | |||
| 2411 | /*! @name PACRI - Peripheral Access Control Register */ | ||
| 2412 | /*! @{ */ | ||
| 2413 | #define AIPS_PACRI_TP7_MASK (0x1U) | ||
| 2414 | #define AIPS_PACRI_TP7_SHIFT (0U) | ||
| 2415 | /*! TP7 - Trusted Protect | ||
| 2416 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2417 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2418 | */ | ||
| 2419 | #define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK) | ||
| 2420 | #define AIPS_PACRI_WP7_MASK (0x2U) | ||
| 2421 | #define AIPS_PACRI_WP7_SHIFT (1U) | ||
| 2422 | /*! WP7 - Write Protect | ||
| 2423 | * 0b0..This peripheral allows write accesses. | ||
| 2424 | * 0b1..This peripheral is write protected. | ||
| 2425 | */ | ||
| 2426 | #define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK) | ||
| 2427 | #define AIPS_PACRI_SP7_MASK (0x4U) | ||
| 2428 | #define AIPS_PACRI_SP7_SHIFT (2U) | ||
| 2429 | /*! SP7 - Supervisor Protect | ||
| 2430 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2431 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2432 | */ | ||
| 2433 | #define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK) | ||
| 2434 | #define AIPS_PACRI_TP6_MASK (0x10U) | ||
| 2435 | #define AIPS_PACRI_TP6_SHIFT (4U) | ||
| 2436 | /*! TP6 - Trusted Protect | ||
| 2437 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2438 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2439 | */ | ||
| 2440 | #define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK) | ||
| 2441 | #define AIPS_PACRI_WP6_MASK (0x20U) | ||
| 2442 | #define AIPS_PACRI_WP6_SHIFT (5U) | ||
| 2443 | /*! WP6 - Write Protect | ||
| 2444 | * 0b0..This peripheral allows write accesses. | ||
| 2445 | * 0b1..This peripheral is write protected. | ||
| 2446 | */ | ||
| 2447 | #define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK) | ||
| 2448 | #define AIPS_PACRI_SP6_MASK (0x40U) | ||
| 2449 | #define AIPS_PACRI_SP6_SHIFT (6U) | ||
| 2450 | /*! SP6 - Supervisor Protect | ||
| 2451 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2452 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2453 | */ | ||
| 2454 | #define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK) | ||
| 2455 | #define AIPS_PACRI_TP5_MASK (0x100U) | ||
| 2456 | #define AIPS_PACRI_TP5_SHIFT (8U) | ||
| 2457 | /*! TP5 - Trusted Protect | ||
| 2458 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2459 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2460 | */ | ||
| 2461 | #define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK) | ||
| 2462 | #define AIPS_PACRI_WP5_MASK (0x200U) | ||
| 2463 | #define AIPS_PACRI_WP5_SHIFT (9U) | ||
| 2464 | /*! WP5 - Write Protect | ||
| 2465 | * 0b0..This peripheral allows write accesses. | ||
| 2466 | * 0b1..This peripheral is write protected. | ||
| 2467 | */ | ||
| 2468 | #define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK) | ||
| 2469 | #define AIPS_PACRI_SP5_MASK (0x400U) | ||
| 2470 | #define AIPS_PACRI_SP5_SHIFT (10U) | ||
| 2471 | /*! SP5 - Supervisor Protect | ||
| 2472 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2473 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2474 | */ | ||
| 2475 | #define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK) | ||
| 2476 | #define AIPS_PACRI_TP4_MASK (0x1000U) | ||
| 2477 | #define AIPS_PACRI_TP4_SHIFT (12U) | ||
| 2478 | /*! TP4 - Trusted Protect | ||
| 2479 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2480 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2481 | */ | ||
| 2482 | #define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK) | ||
| 2483 | #define AIPS_PACRI_WP4_MASK (0x2000U) | ||
| 2484 | #define AIPS_PACRI_WP4_SHIFT (13U) | ||
| 2485 | /*! WP4 - Write Protect | ||
| 2486 | * 0b0..This peripheral allows write accesses. | ||
| 2487 | * 0b1..This peripheral is write protected. | ||
| 2488 | */ | ||
| 2489 | #define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK) | ||
| 2490 | #define AIPS_PACRI_SP4_MASK (0x4000U) | ||
| 2491 | #define AIPS_PACRI_SP4_SHIFT (14U) | ||
| 2492 | /*! SP4 - Supervisor Protect | ||
| 2493 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2494 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2495 | */ | ||
| 2496 | #define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK) | ||
| 2497 | #define AIPS_PACRI_TP3_MASK (0x10000U) | ||
| 2498 | #define AIPS_PACRI_TP3_SHIFT (16U) | ||
| 2499 | /*! TP3 - Trusted Protect | ||
| 2500 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2501 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2502 | */ | ||
| 2503 | #define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK) | ||
| 2504 | #define AIPS_PACRI_WP3_MASK (0x20000U) | ||
| 2505 | #define AIPS_PACRI_WP3_SHIFT (17U) | ||
| 2506 | /*! WP3 - Write Protect | ||
| 2507 | * 0b0..This peripheral allows write accesses. | ||
| 2508 | * 0b1..This peripheral is write protected. | ||
| 2509 | */ | ||
| 2510 | #define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK) | ||
| 2511 | #define AIPS_PACRI_SP3_MASK (0x40000U) | ||
| 2512 | #define AIPS_PACRI_SP3_SHIFT (18U) | ||
| 2513 | /*! SP3 - Supervisor Protect | ||
| 2514 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2515 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2516 | */ | ||
| 2517 | #define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK) | ||
| 2518 | #define AIPS_PACRI_TP2_MASK (0x100000U) | ||
| 2519 | #define AIPS_PACRI_TP2_SHIFT (20U) | ||
| 2520 | /*! TP2 - Trusted Protect | ||
| 2521 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2522 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2523 | */ | ||
| 2524 | #define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK) | ||
| 2525 | #define AIPS_PACRI_WP2_MASK (0x200000U) | ||
| 2526 | #define AIPS_PACRI_WP2_SHIFT (21U) | ||
| 2527 | /*! WP2 - Write Protect | ||
| 2528 | * 0b0..This peripheral allows write accesses. | ||
| 2529 | * 0b1..This peripheral is write protected. | ||
| 2530 | */ | ||
| 2531 | #define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK) | ||
| 2532 | #define AIPS_PACRI_SP2_MASK (0x400000U) | ||
| 2533 | #define AIPS_PACRI_SP2_SHIFT (22U) | ||
| 2534 | /*! SP2 - Supervisor Protect | ||
| 2535 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2536 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2537 | */ | ||
| 2538 | #define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK) | ||
| 2539 | #define AIPS_PACRI_TP1_MASK (0x1000000U) | ||
| 2540 | #define AIPS_PACRI_TP1_SHIFT (24U) | ||
| 2541 | /*! TP1 - Trusted Protect | ||
| 2542 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2543 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2544 | */ | ||
| 2545 | #define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK) | ||
| 2546 | #define AIPS_PACRI_WP1_MASK (0x2000000U) | ||
| 2547 | #define AIPS_PACRI_WP1_SHIFT (25U) | ||
| 2548 | /*! WP1 - Write Protect | ||
| 2549 | * 0b0..This peripheral allows write accesses. | ||
| 2550 | * 0b1..This peripheral is write protected. | ||
| 2551 | */ | ||
| 2552 | #define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK) | ||
| 2553 | #define AIPS_PACRI_SP1_MASK (0x4000000U) | ||
| 2554 | #define AIPS_PACRI_SP1_SHIFT (26U) | ||
| 2555 | /*! SP1 - Supervisor Protect | ||
| 2556 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2557 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2558 | */ | ||
| 2559 | #define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK) | ||
| 2560 | #define AIPS_PACRI_TP0_MASK (0x10000000U) | ||
| 2561 | #define AIPS_PACRI_TP0_SHIFT (28U) | ||
| 2562 | /*! TP0 - Trusted Protect | ||
| 2563 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2564 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2565 | */ | ||
| 2566 | #define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK) | ||
| 2567 | #define AIPS_PACRI_WP0_MASK (0x20000000U) | ||
| 2568 | #define AIPS_PACRI_WP0_SHIFT (29U) | ||
| 2569 | /*! WP0 - Write Protect | ||
| 2570 | * 0b0..This peripheral allows write accesses. | ||
| 2571 | * 0b1..This peripheral is write protected. | ||
| 2572 | */ | ||
| 2573 | #define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK) | ||
| 2574 | #define AIPS_PACRI_SP0_MASK (0x40000000U) | ||
| 2575 | #define AIPS_PACRI_SP0_SHIFT (30U) | ||
| 2576 | /*! SP0 - Supervisor Protect | ||
| 2577 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2578 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2579 | */ | ||
| 2580 | #define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK) | ||
| 2581 | /*! @} */ | ||
| 2582 | |||
| 2583 | /*! @name PACRJ - Peripheral Access Control Register */ | ||
| 2584 | /*! @{ */ | ||
| 2585 | #define AIPS_PACRJ_TP7_MASK (0x1U) | ||
| 2586 | #define AIPS_PACRJ_TP7_SHIFT (0U) | ||
| 2587 | /*! TP7 - Trusted Protect | ||
| 2588 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2589 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2590 | */ | ||
| 2591 | #define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK) | ||
| 2592 | #define AIPS_PACRJ_WP7_MASK (0x2U) | ||
| 2593 | #define AIPS_PACRJ_WP7_SHIFT (1U) | ||
| 2594 | /*! WP7 - Write Protect | ||
| 2595 | * 0b0..This peripheral allows write accesses. | ||
| 2596 | * 0b1..This peripheral is write protected. | ||
| 2597 | */ | ||
| 2598 | #define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK) | ||
| 2599 | #define AIPS_PACRJ_SP7_MASK (0x4U) | ||
| 2600 | #define AIPS_PACRJ_SP7_SHIFT (2U) | ||
| 2601 | /*! SP7 - Supervisor Protect | ||
| 2602 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2603 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2604 | */ | ||
| 2605 | #define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK) | ||
| 2606 | #define AIPS_PACRJ_TP6_MASK (0x10U) | ||
| 2607 | #define AIPS_PACRJ_TP6_SHIFT (4U) | ||
| 2608 | /*! TP6 - Trusted Protect | ||
| 2609 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2610 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2611 | */ | ||
| 2612 | #define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK) | ||
| 2613 | #define AIPS_PACRJ_WP6_MASK (0x20U) | ||
| 2614 | #define AIPS_PACRJ_WP6_SHIFT (5U) | ||
| 2615 | /*! WP6 - Write Protect | ||
| 2616 | * 0b0..This peripheral allows write accesses. | ||
| 2617 | * 0b1..This peripheral is write protected. | ||
| 2618 | */ | ||
| 2619 | #define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK) | ||
| 2620 | #define AIPS_PACRJ_SP6_MASK (0x40U) | ||
| 2621 | #define AIPS_PACRJ_SP6_SHIFT (6U) | ||
| 2622 | /*! SP6 - Supervisor Protect | ||
| 2623 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2624 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2625 | */ | ||
| 2626 | #define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK) | ||
| 2627 | #define AIPS_PACRJ_TP5_MASK (0x100U) | ||
| 2628 | #define AIPS_PACRJ_TP5_SHIFT (8U) | ||
| 2629 | /*! TP5 - Trusted Protect | ||
| 2630 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2631 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2632 | */ | ||
| 2633 | #define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK) | ||
| 2634 | #define AIPS_PACRJ_WP5_MASK (0x200U) | ||
| 2635 | #define AIPS_PACRJ_WP5_SHIFT (9U) | ||
| 2636 | /*! WP5 - Write Protect | ||
| 2637 | * 0b0..This peripheral allows write accesses. | ||
| 2638 | * 0b1..This peripheral is write protected. | ||
| 2639 | */ | ||
| 2640 | #define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK) | ||
| 2641 | #define AIPS_PACRJ_SP5_MASK (0x400U) | ||
| 2642 | #define AIPS_PACRJ_SP5_SHIFT (10U) | ||
| 2643 | /*! SP5 - Supervisor Protect | ||
| 2644 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2645 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2646 | */ | ||
| 2647 | #define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK) | ||
| 2648 | #define AIPS_PACRJ_TP4_MASK (0x1000U) | ||
| 2649 | #define AIPS_PACRJ_TP4_SHIFT (12U) | ||
| 2650 | /*! TP4 - Trusted Protect | ||
| 2651 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2652 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2653 | */ | ||
| 2654 | #define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK) | ||
| 2655 | #define AIPS_PACRJ_WP4_MASK (0x2000U) | ||
| 2656 | #define AIPS_PACRJ_WP4_SHIFT (13U) | ||
| 2657 | /*! WP4 - Write Protect | ||
| 2658 | * 0b0..This peripheral allows write accesses. | ||
| 2659 | * 0b1..This peripheral is write protected. | ||
| 2660 | */ | ||
| 2661 | #define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK) | ||
| 2662 | #define AIPS_PACRJ_SP4_MASK (0x4000U) | ||
| 2663 | #define AIPS_PACRJ_SP4_SHIFT (14U) | ||
| 2664 | /*! SP4 - Supervisor Protect | ||
| 2665 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2666 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2667 | */ | ||
| 2668 | #define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK) | ||
| 2669 | #define AIPS_PACRJ_TP3_MASK (0x10000U) | ||
| 2670 | #define AIPS_PACRJ_TP3_SHIFT (16U) | ||
| 2671 | /*! TP3 - Trusted Protect | ||
| 2672 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2673 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2674 | */ | ||
| 2675 | #define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK) | ||
| 2676 | #define AIPS_PACRJ_WP3_MASK (0x20000U) | ||
| 2677 | #define AIPS_PACRJ_WP3_SHIFT (17U) | ||
| 2678 | /*! WP3 - Write Protect | ||
| 2679 | * 0b0..This peripheral allows write accesses. | ||
| 2680 | * 0b1..This peripheral is write protected. | ||
| 2681 | */ | ||
| 2682 | #define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK) | ||
| 2683 | #define AIPS_PACRJ_SP3_MASK (0x40000U) | ||
| 2684 | #define AIPS_PACRJ_SP3_SHIFT (18U) | ||
| 2685 | /*! SP3 - Supervisor Protect | ||
| 2686 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2687 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2688 | */ | ||
| 2689 | #define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK) | ||
| 2690 | #define AIPS_PACRJ_TP2_MASK (0x100000U) | ||
| 2691 | #define AIPS_PACRJ_TP2_SHIFT (20U) | ||
| 2692 | /*! TP2 - Trusted Protect | ||
| 2693 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2694 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2695 | */ | ||
| 2696 | #define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK) | ||
| 2697 | #define AIPS_PACRJ_WP2_MASK (0x200000U) | ||
| 2698 | #define AIPS_PACRJ_WP2_SHIFT (21U) | ||
| 2699 | /*! WP2 - Write Protect | ||
| 2700 | * 0b0..This peripheral allows write accesses. | ||
| 2701 | * 0b1..This peripheral is write protected. | ||
| 2702 | */ | ||
| 2703 | #define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK) | ||
| 2704 | #define AIPS_PACRJ_SP2_MASK (0x400000U) | ||
| 2705 | #define AIPS_PACRJ_SP2_SHIFT (22U) | ||
| 2706 | /*! SP2 - Supervisor Protect | ||
| 2707 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2708 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2709 | */ | ||
| 2710 | #define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK) | ||
| 2711 | #define AIPS_PACRJ_TP1_MASK (0x1000000U) | ||
| 2712 | #define AIPS_PACRJ_TP1_SHIFT (24U) | ||
| 2713 | /*! TP1 - Trusted Protect | ||
| 2714 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2715 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2716 | */ | ||
| 2717 | #define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK) | ||
| 2718 | #define AIPS_PACRJ_WP1_MASK (0x2000000U) | ||
| 2719 | #define AIPS_PACRJ_WP1_SHIFT (25U) | ||
| 2720 | /*! WP1 - Write Protect | ||
| 2721 | * 0b0..This peripheral allows write accesses. | ||
| 2722 | * 0b1..This peripheral is write protected. | ||
| 2723 | */ | ||
| 2724 | #define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK) | ||
| 2725 | #define AIPS_PACRJ_SP1_MASK (0x4000000U) | ||
| 2726 | #define AIPS_PACRJ_SP1_SHIFT (26U) | ||
| 2727 | /*! SP1 - Supervisor Protect | ||
| 2728 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2729 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2730 | */ | ||
| 2731 | #define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK) | ||
| 2732 | #define AIPS_PACRJ_TP0_MASK (0x10000000U) | ||
| 2733 | #define AIPS_PACRJ_TP0_SHIFT (28U) | ||
| 2734 | /*! TP0 - Trusted Protect | ||
| 2735 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2736 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2737 | */ | ||
| 2738 | #define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK) | ||
| 2739 | #define AIPS_PACRJ_WP0_MASK (0x20000000U) | ||
| 2740 | #define AIPS_PACRJ_WP0_SHIFT (29U) | ||
| 2741 | /*! WP0 - Write Protect | ||
| 2742 | * 0b0..This peripheral allows write accesses. | ||
| 2743 | * 0b1..This peripheral is write protected. | ||
| 2744 | */ | ||
| 2745 | #define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK) | ||
| 2746 | #define AIPS_PACRJ_SP0_MASK (0x40000000U) | ||
| 2747 | #define AIPS_PACRJ_SP0_SHIFT (30U) | ||
| 2748 | /*! SP0 - Supervisor Protect | ||
| 2749 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2750 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2751 | */ | ||
| 2752 | #define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK) | ||
| 2753 | /*! @} */ | ||
| 2754 | |||
| 2755 | /*! @name PACRK - Peripheral Access Control Register */ | ||
| 2756 | /*! @{ */ | ||
| 2757 | #define AIPS_PACRK_TP7_MASK (0x1U) | ||
| 2758 | #define AIPS_PACRK_TP7_SHIFT (0U) | ||
| 2759 | /*! TP7 - Trusted Protect | ||
| 2760 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2761 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2762 | */ | ||
| 2763 | #define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK) | ||
| 2764 | #define AIPS_PACRK_WP7_MASK (0x2U) | ||
| 2765 | #define AIPS_PACRK_WP7_SHIFT (1U) | ||
| 2766 | /*! WP7 - Write Protect | ||
| 2767 | * 0b0..This peripheral allows write accesses. | ||
| 2768 | * 0b1..This peripheral is write protected. | ||
| 2769 | */ | ||
| 2770 | #define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK) | ||
| 2771 | #define AIPS_PACRK_SP7_MASK (0x4U) | ||
| 2772 | #define AIPS_PACRK_SP7_SHIFT (2U) | ||
| 2773 | /*! SP7 - Supervisor Protect | ||
| 2774 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2775 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2776 | */ | ||
| 2777 | #define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK) | ||
| 2778 | #define AIPS_PACRK_TP6_MASK (0x10U) | ||
| 2779 | #define AIPS_PACRK_TP6_SHIFT (4U) | ||
| 2780 | /*! TP6 - Trusted Protect | ||
| 2781 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2782 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2783 | */ | ||
| 2784 | #define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK) | ||
| 2785 | #define AIPS_PACRK_WP6_MASK (0x20U) | ||
| 2786 | #define AIPS_PACRK_WP6_SHIFT (5U) | ||
| 2787 | /*! WP6 - Write Protect | ||
| 2788 | * 0b0..This peripheral allows write accesses. | ||
| 2789 | * 0b1..This peripheral is write protected. | ||
| 2790 | */ | ||
| 2791 | #define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK) | ||
| 2792 | #define AIPS_PACRK_SP6_MASK (0x40U) | ||
| 2793 | #define AIPS_PACRK_SP6_SHIFT (6U) | ||
| 2794 | /*! SP6 - Supervisor Protect | ||
| 2795 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2796 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2797 | */ | ||
| 2798 | #define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK) | ||
| 2799 | #define AIPS_PACRK_TP5_MASK (0x100U) | ||
| 2800 | #define AIPS_PACRK_TP5_SHIFT (8U) | ||
| 2801 | /*! TP5 - Trusted Protect | ||
| 2802 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2803 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2804 | */ | ||
| 2805 | #define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK) | ||
| 2806 | #define AIPS_PACRK_WP5_MASK (0x200U) | ||
| 2807 | #define AIPS_PACRK_WP5_SHIFT (9U) | ||
| 2808 | /*! WP5 - Write Protect | ||
| 2809 | * 0b0..This peripheral allows write accesses. | ||
| 2810 | * 0b1..This peripheral is write protected. | ||
| 2811 | */ | ||
| 2812 | #define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK) | ||
| 2813 | #define AIPS_PACRK_SP5_MASK (0x400U) | ||
| 2814 | #define AIPS_PACRK_SP5_SHIFT (10U) | ||
| 2815 | /*! SP5 - Supervisor Protect | ||
| 2816 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2817 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2818 | */ | ||
| 2819 | #define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK) | ||
| 2820 | #define AIPS_PACRK_TP4_MASK (0x1000U) | ||
| 2821 | #define AIPS_PACRK_TP4_SHIFT (12U) | ||
| 2822 | /*! TP4 - Trusted Protect | ||
| 2823 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2824 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2825 | */ | ||
| 2826 | #define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK) | ||
| 2827 | #define AIPS_PACRK_WP4_MASK (0x2000U) | ||
| 2828 | #define AIPS_PACRK_WP4_SHIFT (13U) | ||
| 2829 | /*! WP4 - Write Protect | ||
| 2830 | * 0b0..This peripheral allows write accesses. | ||
| 2831 | * 0b1..This peripheral is write protected. | ||
| 2832 | */ | ||
| 2833 | #define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK) | ||
| 2834 | #define AIPS_PACRK_SP4_MASK (0x4000U) | ||
| 2835 | #define AIPS_PACRK_SP4_SHIFT (14U) | ||
| 2836 | /*! SP4 - Supervisor Protect | ||
| 2837 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2838 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2839 | */ | ||
| 2840 | #define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK) | ||
| 2841 | #define AIPS_PACRK_TP3_MASK (0x10000U) | ||
| 2842 | #define AIPS_PACRK_TP3_SHIFT (16U) | ||
| 2843 | /*! TP3 - Trusted Protect | ||
| 2844 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2845 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2846 | */ | ||
| 2847 | #define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK) | ||
| 2848 | #define AIPS_PACRK_WP3_MASK (0x20000U) | ||
| 2849 | #define AIPS_PACRK_WP3_SHIFT (17U) | ||
| 2850 | /*! WP3 - Write Protect | ||
| 2851 | * 0b0..This peripheral allows write accesses. | ||
| 2852 | * 0b1..This peripheral is write protected. | ||
| 2853 | */ | ||
| 2854 | #define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK) | ||
| 2855 | #define AIPS_PACRK_SP3_MASK (0x40000U) | ||
| 2856 | #define AIPS_PACRK_SP3_SHIFT (18U) | ||
| 2857 | /*! SP3 - Supervisor Protect | ||
| 2858 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2859 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2860 | */ | ||
| 2861 | #define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK) | ||
| 2862 | #define AIPS_PACRK_TP2_MASK (0x100000U) | ||
| 2863 | #define AIPS_PACRK_TP2_SHIFT (20U) | ||
| 2864 | /*! TP2 - Trusted Protect | ||
| 2865 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2866 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2867 | */ | ||
| 2868 | #define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK) | ||
| 2869 | #define AIPS_PACRK_WP2_MASK (0x200000U) | ||
| 2870 | #define AIPS_PACRK_WP2_SHIFT (21U) | ||
| 2871 | /*! WP2 - Write Protect | ||
| 2872 | * 0b0..This peripheral allows write accesses. | ||
| 2873 | * 0b1..This peripheral is write protected. | ||
| 2874 | */ | ||
| 2875 | #define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK) | ||
| 2876 | #define AIPS_PACRK_SP2_MASK (0x400000U) | ||
| 2877 | #define AIPS_PACRK_SP2_SHIFT (22U) | ||
| 2878 | /*! SP2 - Supervisor Protect | ||
| 2879 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2880 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2881 | */ | ||
| 2882 | #define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK) | ||
| 2883 | #define AIPS_PACRK_TP1_MASK (0x1000000U) | ||
| 2884 | #define AIPS_PACRK_TP1_SHIFT (24U) | ||
| 2885 | /*! TP1 - Trusted Protect | ||
| 2886 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2887 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2888 | */ | ||
| 2889 | #define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK) | ||
| 2890 | #define AIPS_PACRK_WP1_MASK (0x2000000U) | ||
| 2891 | #define AIPS_PACRK_WP1_SHIFT (25U) | ||
| 2892 | /*! WP1 - Write Protect | ||
| 2893 | * 0b0..This peripheral allows write accesses. | ||
| 2894 | * 0b1..This peripheral is write protected. | ||
| 2895 | */ | ||
| 2896 | #define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK) | ||
| 2897 | #define AIPS_PACRK_SP1_MASK (0x4000000U) | ||
| 2898 | #define AIPS_PACRK_SP1_SHIFT (26U) | ||
| 2899 | /*! SP1 - Supervisor Protect | ||
| 2900 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2901 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2902 | */ | ||
| 2903 | #define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK) | ||
| 2904 | #define AIPS_PACRK_TP0_MASK (0x10000000U) | ||
| 2905 | #define AIPS_PACRK_TP0_SHIFT (28U) | ||
| 2906 | /*! TP0 - Trusted Protect | ||
| 2907 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2908 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2909 | */ | ||
| 2910 | #define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK) | ||
| 2911 | #define AIPS_PACRK_WP0_MASK (0x20000000U) | ||
| 2912 | #define AIPS_PACRK_WP0_SHIFT (29U) | ||
| 2913 | /*! WP0 - Write Protect | ||
| 2914 | * 0b0..This peripheral allows write accesses. | ||
| 2915 | * 0b1..This peripheral is write protected. | ||
| 2916 | */ | ||
| 2917 | #define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK) | ||
| 2918 | #define AIPS_PACRK_SP0_MASK (0x40000000U) | ||
| 2919 | #define AIPS_PACRK_SP0_SHIFT (30U) | ||
| 2920 | /*! SP0 - Supervisor Protect | ||
| 2921 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2922 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2923 | */ | ||
| 2924 | #define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK) | ||
| 2925 | /*! @} */ | ||
| 2926 | |||
| 2927 | /*! @name PACRL - Peripheral Access Control Register */ | ||
| 2928 | /*! @{ */ | ||
| 2929 | #define AIPS_PACRL_TP7_MASK (0x1U) | ||
| 2930 | #define AIPS_PACRL_TP7_SHIFT (0U) | ||
| 2931 | /*! TP7 - Trusted Protect | ||
| 2932 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2933 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2934 | */ | ||
| 2935 | #define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK) | ||
| 2936 | #define AIPS_PACRL_WP7_MASK (0x2U) | ||
| 2937 | #define AIPS_PACRL_WP7_SHIFT (1U) | ||
| 2938 | /*! WP7 - Write Protect | ||
| 2939 | * 0b0..This peripheral allows write accesses. | ||
| 2940 | * 0b1..This peripheral is write protected. | ||
| 2941 | */ | ||
| 2942 | #define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK) | ||
| 2943 | #define AIPS_PACRL_SP7_MASK (0x4U) | ||
| 2944 | #define AIPS_PACRL_SP7_SHIFT (2U) | ||
| 2945 | /*! SP7 - Supervisor Protect | ||
| 2946 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2947 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2948 | */ | ||
| 2949 | #define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK) | ||
| 2950 | #define AIPS_PACRL_TP6_MASK (0x10U) | ||
| 2951 | #define AIPS_PACRL_TP6_SHIFT (4U) | ||
| 2952 | /*! TP6 - Trusted Protect | ||
| 2953 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2954 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2955 | */ | ||
| 2956 | #define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK) | ||
| 2957 | #define AIPS_PACRL_WP6_MASK (0x20U) | ||
| 2958 | #define AIPS_PACRL_WP6_SHIFT (5U) | ||
| 2959 | /*! WP6 - Write Protect | ||
| 2960 | * 0b0..This peripheral allows write accesses. | ||
| 2961 | * 0b1..This peripheral is write protected. | ||
| 2962 | */ | ||
| 2963 | #define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK) | ||
| 2964 | #define AIPS_PACRL_SP6_MASK (0x40U) | ||
| 2965 | #define AIPS_PACRL_SP6_SHIFT (6U) | ||
| 2966 | /*! SP6 - Supervisor Protect | ||
| 2967 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2968 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2969 | */ | ||
| 2970 | #define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK) | ||
| 2971 | #define AIPS_PACRL_TP5_MASK (0x100U) | ||
| 2972 | #define AIPS_PACRL_TP5_SHIFT (8U) | ||
| 2973 | /*! TP5 - Trusted Protect | ||
| 2974 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2975 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2976 | */ | ||
| 2977 | #define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK) | ||
| 2978 | #define AIPS_PACRL_WP5_MASK (0x200U) | ||
| 2979 | #define AIPS_PACRL_WP5_SHIFT (9U) | ||
| 2980 | /*! WP5 - Write Protect | ||
| 2981 | * 0b0..This peripheral allows write accesses. | ||
| 2982 | * 0b1..This peripheral is write protected. | ||
| 2983 | */ | ||
| 2984 | #define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK) | ||
| 2985 | #define AIPS_PACRL_SP5_MASK (0x400U) | ||
| 2986 | #define AIPS_PACRL_SP5_SHIFT (10U) | ||
| 2987 | /*! SP5 - Supervisor Protect | ||
| 2988 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 2989 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 2990 | */ | ||
| 2991 | #define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK) | ||
| 2992 | #define AIPS_PACRL_TP4_MASK (0x1000U) | ||
| 2993 | #define AIPS_PACRL_TP4_SHIFT (12U) | ||
| 2994 | /*! TP4 - Trusted Protect | ||
| 2995 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 2996 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 2997 | */ | ||
| 2998 | #define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK) | ||
| 2999 | #define AIPS_PACRL_WP4_MASK (0x2000U) | ||
| 3000 | #define AIPS_PACRL_WP4_SHIFT (13U) | ||
| 3001 | /*! WP4 - Write Protect | ||
| 3002 | * 0b0..This peripheral allows write accesses. | ||
| 3003 | * 0b1..This peripheral is write protected. | ||
| 3004 | */ | ||
| 3005 | #define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK) | ||
| 3006 | #define AIPS_PACRL_SP4_MASK (0x4000U) | ||
| 3007 | #define AIPS_PACRL_SP4_SHIFT (14U) | ||
| 3008 | /*! SP4 - Supervisor Protect | ||
| 3009 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3010 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3011 | */ | ||
| 3012 | #define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK) | ||
| 3013 | #define AIPS_PACRL_TP3_MASK (0x10000U) | ||
| 3014 | #define AIPS_PACRL_TP3_SHIFT (16U) | ||
| 3015 | /*! TP3 - Trusted Protect | ||
| 3016 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3017 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3018 | */ | ||
| 3019 | #define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK) | ||
| 3020 | #define AIPS_PACRL_WP3_MASK (0x20000U) | ||
| 3021 | #define AIPS_PACRL_WP3_SHIFT (17U) | ||
| 3022 | /*! WP3 - Write Protect | ||
| 3023 | * 0b0..This peripheral allows write accesses. | ||
| 3024 | * 0b1..This peripheral is write protected. | ||
| 3025 | */ | ||
| 3026 | #define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK) | ||
| 3027 | #define AIPS_PACRL_SP3_MASK (0x40000U) | ||
| 3028 | #define AIPS_PACRL_SP3_SHIFT (18U) | ||
| 3029 | /*! SP3 - Supervisor Protect | ||
| 3030 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3031 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3032 | */ | ||
| 3033 | #define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK) | ||
| 3034 | #define AIPS_PACRL_TP2_MASK (0x100000U) | ||
| 3035 | #define AIPS_PACRL_TP2_SHIFT (20U) | ||
| 3036 | /*! TP2 - Trusted Protect | ||
| 3037 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3038 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3039 | */ | ||
| 3040 | #define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK) | ||
| 3041 | #define AIPS_PACRL_WP2_MASK (0x200000U) | ||
| 3042 | #define AIPS_PACRL_WP2_SHIFT (21U) | ||
| 3043 | /*! WP2 - Write Protect | ||
| 3044 | * 0b0..This peripheral allows write accesses. | ||
| 3045 | * 0b1..This peripheral is write protected. | ||
| 3046 | */ | ||
| 3047 | #define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK) | ||
| 3048 | #define AIPS_PACRL_SP2_MASK (0x400000U) | ||
| 3049 | #define AIPS_PACRL_SP2_SHIFT (22U) | ||
| 3050 | /*! SP2 - Supervisor Protect | ||
| 3051 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3052 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3053 | */ | ||
| 3054 | #define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK) | ||
| 3055 | #define AIPS_PACRL_TP1_MASK (0x1000000U) | ||
| 3056 | #define AIPS_PACRL_TP1_SHIFT (24U) | ||
| 3057 | /*! TP1 - Trusted Protect | ||
| 3058 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3059 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3060 | */ | ||
| 3061 | #define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK) | ||
| 3062 | #define AIPS_PACRL_WP1_MASK (0x2000000U) | ||
| 3063 | #define AIPS_PACRL_WP1_SHIFT (25U) | ||
| 3064 | /*! WP1 - Write Protect | ||
| 3065 | * 0b0..This peripheral allows write accesses. | ||
| 3066 | * 0b1..This peripheral is write protected. | ||
| 3067 | */ | ||
| 3068 | #define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK) | ||
| 3069 | #define AIPS_PACRL_SP1_MASK (0x4000000U) | ||
| 3070 | #define AIPS_PACRL_SP1_SHIFT (26U) | ||
| 3071 | /*! SP1 - Supervisor Protect | ||
| 3072 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3073 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3074 | */ | ||
| 3075 | #define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK) | ||
| 3076 | #define AIPS_PACRL_TP0_MASK (0x10000000U) | ||
| 3077 | #define AIPS_PACRL_TP0_SHIFT (28U) | ||
| 3078 | /*! TP0 - Trusted Protect | ||
| 3079 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3080 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3081 | */ | ||
| 3082 | #define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK) | ||
| 3083 | #define AIPS_PACRL_WP0_MASK (0x20000000U) | ||
| 3084 | #define AIPS_PACRL_WP0_SHIFT (29U) | ||
| 3085 | /*! WP0 - Write Protect | ||
| 3086 | * 0b0..This peripheral allows write accesses. | ||
| 3087 | * 0b1..This peripheral is write protected. | ||
| 3088 | */ | ||
| 3089 | #define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK) | ||
| 3090 | #define AIPS_PACRL_SP0_MASK (0x40000000U) | ||
| 3091 | #define AIPS_PACRL_SP0_SHIFT (30U) | ||
| 3092 | /*! SP0 - Supervisor Protect | ||
| 3093 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3094 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3095 | */ | ||
| 3096 | #define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK) | ||
| 3097 | /*! @} */ | ||
| 3098 | |||
| 3099 | /*! @name PACRM - Peripheral Access Control Register */ | ||
| 3100 | /*! @{ */ | ||
| 3101 | #define AIPS_PACRM_TP7_MASK (0x1U) | ||
| 3102 | #define AIPS_PACRM_TP7_SHIFT (0U) | ||
| 3103 | /*! TP7 - Trusted Protect | ||
| 3104 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3105 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3106 | */ | ||
| 3107 | #define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK) | ||
| 3108 | #define AIPS_PACRM_WP7_MASK (0x2U) | ||
| 3109 | #define AIPS_PACRM_WP7_SHIFT (1U) | ||
| 3110 | /*! WP7 - Write Protect | ||
| 3111 | * 0b0..This peripheral allows write accesses. | ||
| 3112 | * 0b1..This peripheral is write protected. | ||
| 3113 | */ | ||
| 3114 | #define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK) | ||
| 3115 | #define AIPS_PACRM_SP7_MASK (0x4U) | ||
| 3116 | #define AIPS_PACRM_SP7_SHIFT (2U) | ||
| 3117 | /*! SP7 - Supervisor Protect | ||
| 3118 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3119 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3120 | */ | ||
| 3121 | #define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK) | ||
| 3122 | #define AIPS_PACRM_TP6_MASK (0x10U) | ||
| 3123 | #define AIPS_PACRM_TP6_SHIFT (4U) | ||
| 3124 | /*! TP6 - Trusted Protect | ||
| 3125 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3126 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3127 | */ | ||
| 3128 | #define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK) | ||
| 3129 | #define AIPS_PACRM_WP6_MASK (0x20U) | ||
| 3130 | #define AIPS_PACRM_WP6_SHIFT (5U) | ||
| 3131 | /*! WP6 - Write Protect | ||
| 3132 | * 0b0..This peripheral allows write accesses. | ||
| 3133 | * 0b1..This peripheral is write protected. | ||
| 3134 | */ | ||
| 3135 | #define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK) | ||
| 3136 | #define AIPS_PACRM_SP6_MASK (0x40U) | ||
| 3137 | #define AIPS_PACRM_SP6_SHIFT (6U) | ||
| 3138 | /*! SP6 - Supervisor Protect | ||
| 3139 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3140 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3141 | */ | ||
| 3142 | #define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK) | ||
| 3143 | #define AIPS_PACRM_TP5_MASK (0x100U) | ||
| 3144 | #define AIPS_PACRM_TP5_SHIFT (8U) | ||
| 3145 | /*! TP5 - Trusted Protect | ||
| 3146 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3147 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3148 | */ | ||
| 3149 | #define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK) | ||
| 3150 | #define AIPS_PACRM_WP5_MASK (0x200U) | ||
| 3151 | #define AIPS_PACRM_WP5_SHIFT (9U) | ||
| 3152 | /*! WP5 - Write Protect | ||
| 3153 | * 0b0..This peripheral allows write accesses. | ||
| 3154 | * 0b1..This peripheral is write protected. | ||
| 3155 | */ | ||
| 3156 | #define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK) | ||
| 3157 | #define AIPS_PACRM_SP5_MASK (0x400U) | ||
| 3158 | #define AIPS_PACRM_SP5_SHIFT (10U) | ||
| 3159 | /*! SP5 - Supervisor Protect | ||
| 3160 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3161 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3162 | */ | ||
| 3163 | #define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK) | ||
| 3164 | #define AIPS_PACRM_TP4_MASK (0x1000U) | ||
| 3165 | #define AIPS_PACRM_TP4_SHIFT (12U) | ||
| 3166 | /*! TP4 - Trusted Protect | ||
| 3167 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3168 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3169 | */ | ||
| 3170 | #define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK) | ||
| 3171 | #define AIPS_PACRM_WP4_MASK (0x2000U) | ||
| 3172 | #define AIPS_PACRM_WP4_SHIFT (13U) | ||
| 3173 | /*! WP4 - Write Protect | ||
| 3174 | * 0b0..This peripheral allows write accesses. | ||
| 3175 | * 0b1..This peripheral is write protected. | ||
| 3176 | */ | ||
| 3177 | #define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK) | ||
| 3178 | #define AIPS_PACRM_SP4_MASK (0x4000U) | ||
| 3179 | #define AIPS_PACRM_SP4_SHIFT (14U) | ||
| 3180 | /*! SP4 - Supervisor Protect | ||
| 3181 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3182 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3183 | */ | ||
| 3184 | #define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK) | ||
| 3185 | #define AIPS_PACRM_TP3_MASK (0x10000U) | ||
| 3186 | #define AIPS_PACRM_TP3_SHIFT (16U) | ||
| 3187 | /*! TP3 - Trusted Protect | ||
| 3188 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3189 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3190 | */ | ||
| 3191 | #define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK) | ||
| 3192 | #define AIPS_PACRM_WP3_MASK (0x20000U) | ||
| 3193 | #define AIPS_PACRM_WP3_SHIFT (17U) | ||
| 3194 | /*! WP3 - Write Protect | ||
| 3195 | * 0b0..This peripheral allows write accesses. | ||
| 3196 | * 0b1..This peripheral is write protected. | ||
| 3197 | */ | ||
| 3198 | #define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK) | ||
| 3199 | #define AIPS_PACRM_SP3_MASK (0x40000U) | ||
| 3200 | #define AIPS_PACRM_SP3_SHIFT (18U) | ||
| 3201 | /*! SP3 - Supervisor Protect | ||
| 3202 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3203 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3204 | */ | ||
| 3205 | #define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK) | ||
| 3206 | #define AIPS_PACRM_TP2_MASK (0x100000U) | ||
| 3207 | #define AIPS_PACRM_TP2_SHIFT (20U) | ||
| 3208 | /*! TP2 - Trusted Protect | ||
| 3209 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3210 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3211 | */ | ||
| 3212 | #define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK) | ||
| 3213 | #define AIPS_PACRM_WP2_MASK (0x200000U) | ||
| 3214 | #define AIPS_PACRM_WP2_SHIFT (21U) | ||
| 3215 | /*! WP2 - Write Protect | ||
| 3216 | * 0b0..This peripheral allows write accesses. | ||
| 3217 | * 0b1..This peripheral is write protected. | ||
| 3218 | */ | ||
| 3219 | #define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK) | ||
| 3220 | #define AIPS_PACRM_SP2_MASK (0x400000U) | ||
| 3221 | #define AIPS_PACRM_SP2_SHIFT (22U) | ||
| 3222 | /*! SP2 - Supervisor Protect | ||
| 3223 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3224 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3225 | */ | ||
| 3226 | #define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK) | ||
| 3227 | #define AIPS_PACRM_TP1_MASK (0x1000000U) | ||
| 3228 | #define AIPS_PACRM_TP1_SHIFT (24U) | ||
| 3229 | /*! TP1 - Trusted Protect | ||
| 3230 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3231 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3232 | */ | ||
| 3233 | #define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK) | ||
| 3234 | #define AIPS_PACRM_WP1_MASK (0x2000000U) | ||
| 3235 | #define AIPS_PACRM_WP1_SHIFT (25U) | ||
| 3236 | /*! WP1 - Write Protect | ||
| 3237 | * 0b0..This peripheral allows write accesses. | ||
| 3238 | * 0b1..This peripheral is write protected. | ||
| 3239 | */ | ||
| 3240 | #define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK) | ||
| 3241 | #define AIPS_PACRM_SP1_MASK (0x4000000U) | ||
| 3242 | #define AIPS_PACRM_SP1_SHIFT (26U) | ||
| 3243 | /*! SP1 - Supervisor Protect | ||
| 3244 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3245 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3246 | */ | ||
| 3247 | #define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK) | ||
| 3248 | #define AIPS_PACRM_TP0_MASK (0x10000000U) | ||
| 3249 | #define AIPS_PACRM_TP0_SHIFT (28U) | ||
| 3250 | /*! TP0 - Trusted Protect | ||
| 3251 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3252 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3253 | */ | ||
| 3254 | #define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK) | ||
| 3255 | #define AIPS_PACRM_WP0_MASK (0x20000000U) | ||
| 3256 | #define AIPS_PACRM_WP0_SHIFT (29U) | ||
| 3257 | /*! WP0 - Write Protect | ||
| 3258 | * 0b0..This peripheral allows write accesses. | ||
| 3259 | * 0b1..This peripheral is write protected. | ||
| 3260 | */ | ||
| 3261 | #define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK) | ||
| 3262 | #define AIPS_PACRM_SP0_MASK (0x40000000U) | ||
| 3263 | #define AIPS_PACRM_SP0_SHIFT (30U) | ||
| 3264 | /*! SP0 - Supervisor Protect | ||
| 3265 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3266 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3267 | */ | ||
| 3268 | #define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK) | ||
| 3269 | /*! @} */ | ||
| 3270 | |||
| 3271 | /*! @name PACRN - Peripheral Access Control Register */ | ||
| 3272 | /*! @{ */ | ||
| 3273 | #define AIPS_PACRN_TP7_MASK (0x1U) | ||
| 3274 | #define AIPS_PACRN_TP7_SHIFT (0U) | ||
| 3275 | /*! TP7 - Trusted Protect | ||
| 3276 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3277 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3278 | */ | ||
| 3279 | #define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK) | ||
| 3280 | #define AIPS_PACRN_WP7_MASK (0x2U) | ||
| 3281 | #define AIPS_PACRN_WP7_SHIFT (1U) | ||
| 3282 | /*! WP7 - Write Protect | ||
| 3283 | * 0b0..This peripheral allows write accesses. | ||
| 3284 | * 0b1..This peripheral is write protected. | ||
| 3285 | */ | ||
| 3286 | #define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK) | ||
| 3287 | #define AIPS_PACRN_SP7_MASK (0x4U) | ||
| 3288 | #define AIPS_PACRN_SP7_SHIFT (2U) | ||
| 3289 | /*! SP7 - Supervisor Protect | ||
| 3290 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3291 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3292 | */ | ||
| 3293 | #define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK) | ||
| 3294 | #define AIPS_PACRN_TP6_MASK (0x10U) | ||
| 3295 | #define AIPS_PACRN_TP6_SHIFT (4U) | ||
| 3296 | /*! TP6 - Trusted Protect | ||
| 3297 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3298 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3299 | */ | ||
| 3300 | #define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK) | ||
| 3301 | #define AIPS_PACRN_WP6_MASK (0x20U) | ||
| 3302 | #define AIPS_PACRN_WP6_SHIFT (5U) | ||
| 3303 | /*! WP6 - Write Protect | ||
| 3304 | * 0b0..This peripheral allows write accesses. | ||
| 3305 | * 0b1..This peripheral is write protected. | ||
| 3306 | */ | ||
| 3307 | #define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK) | ||
| 3308 | #define AIPS_PACRN_SP6_MASK (0x40U) | ||
| 3309 | #define AIPS_PACRN_SP6_SHIFT (6U) | ||
| 3310 | /*! SP6 - Supervisor Protect | ||
| 3311 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3312 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3313 | */ | ||
| 3314 | #define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK) | ||
| 3315 | #define AIPS_PACRN_TP5_MASK (0x100U) | ||
| 3316 | #define AIPS_PACRN_TP5_SHIFT (8U) | ||
| 3317 | /*! TP5 - Trusted Protect | ||
| 3318 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3319 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3320 | */ | ||
| 3321 | #define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK) | ||
| 3322 | #define AIPS_PACRN_WP5_MASK (0x200U) | ||
| 3323 | #define AIPS_PACRN_WP5_SHIFT (9U) | ||
| 3324 | /*! WP5 - Write Protect | ||
| 3325 | * 0b0..This peripheral allows write accesses. | ||
| 3326 | * 0b1..This peripheral is write protected. | ||
| 3327 | */ | ||
| 3328 | #define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK) | ||
| 3329 | #define AIPS_PACRN_SP5_MASK (0x400U) | ||
| 3330 | #define AIPS_PACRN_SP5_SHIFT (10U) | ||
| 3331 | /*! SP5 - Supervisor Protect | ||
| 3332 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3333 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3334 | */ | ||
| 3335 | #define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK) | ||
| 3336 | #define AIPS_PACRN_TP4_MASK (0x1000U) | ||
| 3337 | #define AIPS_PACRN_TP4_SHIFT (12U) | ||
| 3338 | /*! TP4 - Trusted Protect | ||
| 3339 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3340 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3341 | */ | ||
| 3342 | #define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK) | ||
| 3343 | #define AIPS_PACRN_WP4_MASK (0x2000U) | ||
| 3344 | #define AIPS_PACRN_WP4_SHIFT (13U) | ||
| 3345 | /*! WP4 - Write Protect | ||
| 3346 | * 0b0..This peripheral allows write accesses. | ||
| 3347 | * 0b1..This peripheral is write protected. | ||
| 3348 | */ | ||
| 3349 | #define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK) | ||
| 3350 | #define AIPS_PACRN_SP4_MASK (0x4000U) | ||
| 3351 | #define AIPS_PACRN_SP4_SHIFT (14U) | ||
| 3352 | /*! SP4 - Supervisor Protect | ||
| 3353 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3354 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3355 | */ | ||
| 3356 | #define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK) | ||
| 3357 | #define AIPS_PACRN_TP3_MASK (0x10000U) | ||
| 3358 | #define AIPS_PACRN_TP3_SHIFT (16U) | ||
| 3359 | /*! TP3 - Trusted Protect | ||
| 3360 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3361 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3362 | */ | ||
| 3363 | #define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK) | ||
| 3364 | #define AIPS_PACRN_WP3_MASK (0x20000U) | ||
| 3365 | #define AIPS_PACRN_WP3_SHIFT (17U) | ||
| 3366 | /*! WP3 - Write Protect | ||
| 3367 | * 0b0..This peripheral allows write accesses. | ||
| 3368 | * 0b1..This peripheral is write protected. | ||
| 3369 | */ | ||
| 3370 | #define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK) | ||
| 3371 | #define AIPS_PACRN_SP3_MASK (0x40000U) | ||
| 3372 | #define AIPS_PACRN_SP3_SHIFT (18U) | ||
| 3373 | /*! SP3 - Supervisor Protect | ||
| 3374 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3375 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3376 | */ | ||
| 3377 | #define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK) | ||
| 3378 | #define AIPS_PACRN_TP2_MASK (0x100000U) | ||
| 3379 | #define AIPS_PACRN_TP2_SHIFT (20U) | ||
| 3380 | /*! TP2 - Trusted Protect | ||
| 3381 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3382 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3383 | */ | ||
| 3384 | #define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK) | ||
| 3385 | #define AIPS_PACRN_WP2_MASK (0x200000U) | ||
| 3386 | #define AIPS_PACRN_WP2_SHIFT (21U) | ||
| 3387 | /*! WP2 - Write Protect | ||
| 3388 | * 0b0..This peripheral allows write accesses. | ||
| 3389 | * 0b1..This peripheral is write protected. | ||
| 3390 | */ | ||
| 3391 | #define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK) | ||
| 3392 | #define AIPS_PACRN_SP2_MASK (0x400000U) | ||
| 3393 | #define AIPS_PACRN_SP2_SHIFT (22U) | ||
| 3394 | /*! SP2 - Supervisor Protect | ||
| 3395 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3396 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3397 | */ | ||
| 3398 | #define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK) | ||
| 3399 | #define AIPS_PACRN_TP1_MASK (0x1000000U) | ||
| 3400 | #define AIPS_PACRN_TP1_SHIFT (24U) | ||
| 3401 | /*! TP1 - Trusted Protect | ||
| 3402 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3403 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3404 | */ | ||
| 3405 | #define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK) | ||
| 3406 | #define AIPS_PACRN_WP1_MASK (0x2000000U) | ||
| 3407 | #define AIPS_PACRN_WP1_SHIFT (25U) | ||
| 3408 | /*! WP1 - Write Protect | ||
| 3409 | * 0b0..This peripheral allows write accesses. | ||
| 3410 | * 0b1..This peripheral is write protected. | ||
| 3411 | */ | ||
| 3412 | #define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK) | ||
| 3413 | #define AIPS_PACRN_SP1_MASK (0x4000000U) | ||
| 3414 | #define AIPS_PACRN_SP1_SHIFT (26U) | ||
| 3415 | /*! SP1 - Supervisor Protect | ||
| 3416 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3417 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3418 | */ | ||
| 3419 | #define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK) | ||
| 3420 | #define AIPS_PACRN_TP0_MASK (0x10000000U) | ||
| 3421 | #define AIPS_PACRN_TP0_SHIFT (28U) | ||
| 3422 | /*! TP0 - Trusted Protect | ||
| 3423 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3424 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3425 | */ | ||
| 3426 | #define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK) | ||
| 3427 | #define AIPS_PACRN_WP0_MASK (0x20000000U) | ||
| 3428 | #define AIPS_PACRN_WP0_SHIFT (29U) | ||
| 3429 | /*! WP0 - Write Protect | ||
| 3430 | * 0b0..This peripheral allows write accesses. | ||
| 3431 | * 0b1..This peripheral is write protected. | ||
| 3432 | */ | ||
| 3433 | #define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK) | ||
| 3434 | #define AIPS_PACRN_SP0_MASK (0x40000000U) | ||
| 3435 | #define AIPS_PACRN_SP0_SHIFT (30U) | ||
| 3436 | /*! SP0 - Supervisor Protect | ||
| 3437 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3438 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3439 | */ | ||
| 3440 | #define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK) | ||
| 3441 | /*! @} */ | ||
| 3442 | |||
| 3443 | /*! @name PACRO - Peripheral Access Control Register */ | ||
| 3444 | /*! @{ */ | ||
| 3445 | #define AIPS_PACRO_TP7_MASK (0x1U) | ||
| 3446 | #define AIPS_PACRO_TP7_SHIFT (0U) | ||
| 3447 | /*! TP7 - Trusted Protect | ||
| 3448 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3449 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3450 | */ | ||
| 3451 | #define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK) | ||
| 3452 | #define AIPS_PACRO_WP7_MASK (0x2U) | ||
| 3453 | #define AIPS_PACRO_WP7_SHIFT (1U) | ||
| 3454 | /*! WP7 - Write Protect | ||
| 3455 | * 0b0..This peripheral allows write accesses. | ||
| 3456 | * 0b1..This peripheral is write protected. | ||
| 3457 | */ | ||
| 3458 | #define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK) | ||
| 3459 | #define AIPS_PACRO_SP7_MASK (0x4U) | ||
| 3460 | #define AIPS_PACRO_SP7_SHIFT (2U) | ||
| 3461 | /*! SP7 - Supervisor Protect | ||
| 3462 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3463 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3464 | */ | ||
| 3465 | #define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK) | ||
| 3466 | #define AIPS_PACRO_TP6_MASK (0x10U) | ||
| 3467 | #define AIPS_PACRO_TP6_SHIFT (4U) | ||
| 3468 | /*! TP6 - Trusted Protect | ||
| 3469 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3470 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3471 | */ | ||
| 3472 | #define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK) | ||
| 3473 | #define AIPS_PACRO_WP6_MASK (0x20U) | ||
| 3474 | #define AIPS_PACRO_WP6_SHIFT (5U) | ||
| 3475 | /*! WP6 - Write Protect | ||
| 3476 | * 0b0..This peripheral allows write accesses. | ||
| 3477 | * 0b1..This peripheral is write protected. | ||
| 3478 | */ | ||
| 3479 | #define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK) | ||
| 3480 | #define AIPS_PACRO_SP6_MASK (0x40U) | ||
| 3481 | #define AIPS_PACRO_SP6_SHIFT (6U) | ||
| 3482 | /*! SP6 - Supervisor Protect | ||
| 3483 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3484 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3485 | */ | ||
| 3486 | #define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK) | ||
| 3487 | #define AIPS_PACRO_TP5_MASK (0x100U) | ||
| 3488 | #define AIPS_PACRO_TP5_SHIFT (8U) | ||
| 3489 | /*! TP5 - Trusted Protect | ||
| 3490 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3491 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3492 | */ | ||
| 3493 | #define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK) | ||
| 3494 | #define AIPS_PACRO_WP5_MASK (0x200U) | ||
| 3495 | #define AIPS_PACRO_WP5_SHIFT (9U) | ||
| 3496 | /*! WP5 - Write Protect | ||
| 3497 | * 0b0..This peripheral allows write accesses. | ||
| 3498 | * 0b1..This peripheral is write protected. | ||
| 3499 | */ | ||
| 3500 | #define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK) | ||
| 3501 | #define AIPS_PACRO_SP5_MASK (0x400U) | ||
| 3502 | #define AIPS_PACRO_SP5_SHIFT (10U) | ||
| 3503 | /*! SP5 - Supervisor Protect | ||
| 3504 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3505 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3506 | */ | ||
| 3507 | #define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK) | ||
| 3508 | #define AIPS_PACRO_TP4_MASK (0x1000U) | ||
| 3509 | #define AIPS_PACRO_TP4_SHIFT (12U) | ||
| 3510 | /*! TP4 - Trusted Protect | ||
| 3511 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3512 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3513 | */ | ||
| 3514 | #define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK) | ||
| 3515 | #define AIPS_PACRO_WP4_MASK (0x2000U) | ||
| 3516 | #define AIPS_PACRO_WP4_SHIFT (13U) | ||
| 3517 | /*! WP4 - Write Protect | ||
| 3518 | * 0b0..This peripheral allows write accesses. | ||
| 3519 | * 0b1..This peripheral is write protected. | ||
| 3520 | */ | ||
| 3521 | #define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK) | ||
| 3522 | #define AIPS_PACRO_SP4_MASK (0x4000U) | ||
| 3523 | #define AIPS_PACRO_SP4_SHIFT (14U) | ||
| 3524 | /*! SP4 - Supervisor Protect | ||
| 3525 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3526 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3527 | */ | ||
| 3528 | #define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK) | ||
| 3529 | #define AIPS_PACRO_TP3_MASK (0x10000U) | ||
| 3530 | #define AIPS_PACRO_TP3_SHIFT (16U) | ||
| 3531 | /*! TP3 - Trusted Protect | ||
| 3532 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3533 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3534 | */ | ||
| 3535 | #define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK) | ||
| 3536 | #define AIPS_PACRO_WP3_MASK (0x20000U) | ||
| 3537 | #define AIPS_PACRO_WP3_SHIFT (17U) | ||
| 3538 | /*! WP3 - Write Protect | ||
| 3539 | * 0b0..This peripheral allows write accesses. | ||
| 3540 | * 0b1..This peripheral is write protected. | ||
| 3541 | */ | ||
| 3542 | #define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK) | ||
| 3543 | #define AIPS_PACRO_SP3_MASK (0x40000U) | ||
| 3544 | #define AIPS_PACRO_SP3_SHIFT (18U) | ||
| 3545 | /*! SP3 - Supervisor Protect | ||
| 3546 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3547 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3548 | */ | ||
| 3549 | #define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK) | ||
| 3550 | #define AIPS_PACRO_TP2_MASK (0x100000U) | ||
| 3551 | #define AIPS_PACRO_TP2_SHIFT (20U) | ||
| 3552 | /*! TP2 - Trusted Protect | ||
| 3553 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3554 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3555 | */ | ||
| 3556 | #define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK) | ||
| 3557 | #define AIPS_PACRO_WP2_MASK (0x200000U) | ||
| 3558 | #define AIPS_PACRO_WP2_SHIFT (21U) | ||
| 3559 | /*! WP2 - Write Protect | ||
| 3560 | * 0b0..This peripheral allows write accesses. | ||
| 3561 | * 0b1..This peripheral is write protected. | ||
| 3562 | */ | ||
| 3563 | #define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK) | ||
| 3564 | #define AIPS_PACRO_SP2_MASK (0x400000U) | ||
| 3565 | #define AIPS_PACRO_SP2_SHIFT (22U) | ||
| 3566 | /*! SP2 - Supervisor Protect | ||
| 3567 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3568 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3569 | */ | ||
| 3570 | #define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK) | ||
| 3571 | #define AIPS_PACRO_TP1_MASK (0x1000000U) | ||
| 3572 | #define AIPS_PACRO_TP1_SHIFT (24U) | ||
| 3573 | /*! TP1 - Trusted Protect | ||
| 3574 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3575 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3576 | */ | ||
| 3577 | #define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK) | ||
| 3578 | #define AIPS_PACRO_WP1_MASK (0x2000000U) | ||
| 3579 | #define AIPS_PACRO_WP1_SHIFT (25U) | ||
| 3580 | /*! WP1 - Write Protect | ||
| 3581 | * 0b0..This peripheral allows write accesses. | ||
| 3582 | * 0b1..This peripheral is write protected. | ||
| 3583 | */ | ||
| 3584 | #define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK) | ||
| 3585 | #define AIPS_PACRO_SP1_MASK (0x4000000U) | ||
| 3586 | #define AIPS_PACRO_SP1_SHIFT (26U) | ||
| 3587 | /*! SP1 - Supervisor Protect | ||
| 3588 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3589 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3590 | */ | ||
| 3591 | #define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK) | ||
| 3592 | #define AIPS_PACRO_TP0_MASK (0x10000000U) | ||
| 3593 | #define AIPS_PACRO_TP0_SHIFT (28U) | ||
| 3594 | /*! TP0 - Trusted Protect | ||
| 3595 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3596 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3597 | */ | ||
| 3598 | #define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK) | ||
| 3599 | #define AIPS_PACRO_WP0_MASK (0x20000000U) | ||
| 3600 | #define AIPS_PACRO_WP0_SHIFT (29U) | ||
| 3601 | /*! WP0 - Write Protect | ||
| 3602 | * 0b0..This peripheral allows write accesses. | ||
| 3603 | * 0b1..This peripheral is write protected. | ||
| 3604 | */ | ||
| 3605 | #define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK) | ||
| 3606 | #define AIPS_PACRO_SP0_MASK (0x40000000U) | ||
| 3607 | #define AIPS_PACRO_SP0_SHIFT (30U) | ||
| 3608 | /*! SP0 - Supervisor Protect | ||
| 3609 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3610 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3611 | */ | ||
| 3612 | #define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK) | ||
| 3613 | /*! @} */ | ||
| 3614 | |||
| 3615 | /*! @name PACRP - Peripheral Access Control Register */ | ||
| 3616 | /*! @{ */ | ||
| 3617 | #define AIPS_PACRP_TP7_MASK (0x1U) | ||
| 3618 | #define AIPS_PACRP_TP7_SHIFT (0U) | ||
| 3619 | /*! TP7 - Trusted Protect | ||
| 3620 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3621 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3622 | */ | ||
| 3623 | #define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK) | ||
| 3624 | #define AIPS_PACRP_WP7_MASK (0x2U) | ||
| 3625 | #define AIPS_PACRP_WP7_SHIFT (1U) | ||
| 3626 | /*! WP7 - Write Protect | ||
| 3627 | * 0b0..This peripheral allows write accesses. | ||
| 3628 | * 0b1..This peripheral is write protected. | ||
| 3629 | */ | ||
| 3630 | #define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK) | ||
| 3631 | #define AIPS_PACRP_SP7_MASK (0x4U) | ||
| 3632 | #define AIPS_PACRP_SP7_SHIFT (2U) | ||
| 3633 | /*! SP7 - Supervisor Protect | ||
| 3634 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3635 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3636 | */ | ||
| 3637 | #define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK) | ||
| 3638 | #define AIPS_PACRP_TP6_MASK (0x10U) | ||
| 3639 | #define AIPS_PACRP_TP6_SHIFT (4U) | ||
| 3640 | /*! TP6 - Trusted Protect | ||
| 3641 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3642 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3643 | */ | ||
| 3644 | #define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK) | ||
| 3645 | #define AIPS_PACRP_WP6_MASK (0x20U) | ||
| 3646 | #define AIPS_PACRP_WP6_SHIFT (5U) | ||
| 3647 | /*! WP6 - Write Protect | ||
| 3648 | * 0b0..This peripheral allows write accesses. | ||
| 3649 | * 0b1..This peripheral is write protected. | ||
| 3650 | */ | ||
| 3651 | #define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK) | ||
| 3652 | #define AIPS_PACRP_SP6_MASK (0x40U) | ||
| 3653 | #define AIPS_PACRP_SP6_SHIFT (6U) | ||
| 3654 | /*! SP6 - Supervisor Protect | ||
| 3655 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3656 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3657 | */ | ||
| 3658 | #define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK) | ||
| 3659 | #define AIPS_PACRP_TP5_MASK (0x100U) | ||
| 3660 | #define AIPS_PACRP_TP5_SHIFT (8U) | ||
| 3661 | /*! TP5 - Trusted Protect | ||
| 3662 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3663 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3664 | */ | ||
| 3665 | #define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK) | ||
| 3666 | #define AIPS_PACRP_WP5_MASK (0x200U) | ||
| 3667 | #define AIPS_PACRP_WP5_SHIFT (9U) | ||
| 3668 | /*! WP5 - Write Protect | ||
| 3669 | * 0b0..This peripheral allows write accesses. | ||
| 3670 | * 0b1..This peripheral is write protected. | ||
| 3671 | */ | ||
| 3672 | #define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK) | ||
| 3673 | #define AIPS_PACRP_SP5_MASK (0x400U) | ||
| 3674 | #define AIPS_PACRP_SP5_SHIFT (10U) | ||
| 3675 | /*! SP5 - Supervisor Protect | ||
| 3676 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3677 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3678 | */ | ||
| 3679 | #define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK) | ||
| 3680 | #define AIPS_PACRP_TP4_MASK (0x1000U) | ||
| 3681 | #define AIPS_PACRP_TP4_SHIFT (12U) | ||
| 3682 | /*! TP4 - Trusted Protect | ||
| 3683 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3684 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3685 | */ | ||
| 3686 | #define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK) | ||
| 3687 | #define AIPS_PACRP_WP4_MASK (0x2000U) | ||
| 3688 | #define AIPS_PACRP_WP4_SHIFT (13U) | ||
| 3689 | /*! WP4 - Write Protect | ||
| 3690 | * 0b0..This peripheral allows write accesses. | ||
| 3691 | * 0b1..This peripheral is write protected. | ||
| 3692 | */ | ||
| 3693 | #define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK) | ||
| 3694 | #define AIPS_PACRP_SP4_MASK (0x4000U) | ||
| 3695 | #define AIPS_PACRP_SP4_SHIFT (14U) | ||
| 3696 | /*! SP4 - Supervisor Protect | ||
| 3697 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3698 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3699 | */ | ||
| 3700 | #define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK) | ||
| 3701 | #define AIPS_PACRP_TP3_MASK (0x10000U) | ||
| 3702 | #define AIPS_PACRP_TP3_SHIFT (16U) | ||
| 3703 | /*! TP3 - Trusted Protect | ||
| 3704 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3705 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3706 | */ | ||
| 3707 | #define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK) | ||
| 3708 | #define AIPS_PACRP_WP3_MASK (0x20000U) | ||
| 3709 | #define AIPS_PACRP_WP3_SHIFT (17U) | ||
| 3710 | /*! WP3 - Write Protect | ||
| 3711 | * 0b0..This peripheral allows write accesses. | ||
| 3712 | * 0b1..This peripheral is write protected. | ||
| 3713 | */ | ||
| 3714 | #define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK) | ||
| 3715 | #define AIPS_PACRP_SP3_MASK (0x40000U) | ||
| 3716 | #define AIPS_PACRP_SP3_SHIFT (18U) | ||
| 3717 | /*! SP3 - Supervisor Protect | ||
| 3718 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3719 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3720 | */ | ||
| 3721 | #define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK) | ||
| 3722 | #define AIPS_PACRP_TP2_MASK (0x100000U) | ||
| 3723 | #define AIPS_PACRP_TP2_SHIFT (20U) | ||
| 3724 | /*! TP2 - Trusted Protect | ||
| 3725 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3726 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3727 | */ | ||
| 3728 | #define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK) | ||
| 3729 | #define AIPS_PACRP_WP2_MASK (0x200000U) | ||
| 3730 | #define AIPS_PACRP_WP2_SHIFT (21U) | ||
| 3731 | /*! WP2 - Write Protect | ||
| 3732 | * 0b0..This peripheral allows write accesses. | ||
| 3733 | * 0b1..This peripheral is write protected. | ||
| 3734 | */ | ||
| 3735 | #define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK) | ||
| 3736 | #define AIPS_PACRP_SP2_MASK (0x400000U) | ||
| 3737 | #define AIPS_PACRP_SP2_SHIFT (22U) | ||
| 3738 | /*! SP2 - Supervisor Protect | ||
| 3739 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3740 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3741 | */ | ||
| 3742 | #define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK) | ||
| 3743 | #define AIPS_PACRP_TP1_MASK (0x1000000U) | ||
| 3744 | #define AIPS_PACRP_TP1_SHIFT (24U) | ||
| 3745 | /*! TP1 - Trusted Protect | ||
| 3746 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3747 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3748 | */ | ||
| 3749 | #define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK) | ||
| 3750 | #define AIPS_PACRP_WP1_MASK (0x2000000U) | ||
| 3751 | #define AIPS_PACRP_WP1_SHIFT (25U) | ||
| 3752 | /*! WP1 - Write Protect | ||
| 3753 | * 0b0..This peripheral allows write accesses. | ||
| 3754 | * 0b1..This peripheral is write protected. | ||
| 3755 | */ | ||
| 3756 | #define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK) | ||
| 3757 | #define AIPS_PACRP_SP1_MASK (0x4000000U) | ||
| 3758 | #define AIPS_PACRP_SP1_SHIFT (26U) | ||
| 3759 | /*! SP1 - Supervisor Protect | ||
| 3760 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3761 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3762 | */ | ||
| 3763 | #define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK) | ||
| 3764 | #define AIPS_PACRP_TP0_MASK (0x10000000U) | ||
| 3765 | #define AIPS_PACRP_TP0_SHIFT (28U) | ||
| 3766 | /*! TP0 - Trusted Protect | ||
| 3767 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3768 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3769 | */ | ||
| 3770 | #define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK) | ||
| 3771 | #define AIPS_PACRP_WP0_MASK (0x20000000U) | ||
| 3772 | #define AIPS_PACRP_WP0_SHIFT (29U) | ||
| 3773 | /*! WP0 - Write Protect | ||
| 3774 | * 0b0..This peripheral allows write accesses. | ||
| 3775 | * 0b1..This peripheral is write protected. | ||
| 3776 | */ | ||
| 3777 | #define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK) | ||
| 3778 | #define AIPS_PACRP_SP0_MASK (0x40000000U) | ||
| 3779 | #define AIPS_PACRP_SP0_SHIFT (30U) | ||
| 3780 | /*! SP0 - Supervisor Protect | ||
| 3781 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3782 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3783 | */ | ||
| 3784 | #define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK) | ||
| 3785 | /*! @} */ | ||
| 3786 | |||
| 3787 | /*! @name PACRU - Peripheral Access Control Register */ | ||
| 3788 | /*! @{ */ | ||
| 3789 | #define AIPS_PACRU_TP1_MASK (0x1000000U) | ||
| 3790 | #define AIPS_PACRU_TP1_SHIFT (24U) | ||
| 3791 | /*! TP1 - Trusted Protect | ||
| 3792 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3793 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3794 | */ | ||
| 3795 | #define AIPS_PACRU_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP1_SHIFT)) & AIPS_PACRU_TP1_MASK) | ||
| 3796 | #define AIPS_PACRU_WP1_MASK (0x2000000U) | ||
| 3797 | #define AIPS_PACRU_WP1_SHIFT (25U) | ||
| 3798 | /*! WP1 - Write Protect | ||
| 3799 | * 0b0..This peripheral allows write accesses. | ||
| 3800 | * 0b1..This peripheral is write protected. | ||
| 3801 | */ | ||
| 3802 | #define AIPS_PACRU_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP1_SHIFT)) & AIPS_PACRU_WP1_MASK) | ||
| 3803 | #define AIPS_PACRU_SP1_MASK (0x4000000U) | ||
| 3804 | #define AIPS_PACRU_SP1_SHIFT (26U) | ||
| 3805 | /*! SP1 - Supervisor Protect | ||
| 3806 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3807 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3808 | */ | ||
| 3809 | #define AIPS_PACRU_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP1_SHIFT)) & AIPS_PACRU_SP1_MASK) | ||
| 3810 | #define AIPS_PACRU_TP0_MASK (0x10000000U) | ||
| 3811 | #define AIPS_PACRU_TP0_SHIFT (28U) | ||
| 3812 | /*! TP0 - Trusted Protect | ||
| 3813 | * 0b0..Accesses from an untrusted master are allowed. | ||
| 3814 | * 0b1..Accesses from an untrusted master are not allowed. | ||
| 3815 | */ | ||
| 3816 | #define AIPS_PACRU_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP0_SHIFT)) & AIPS_PACRU_TP0_MASK) | ||
| 3817 | #define AIPS_PACRU_WP0_MASK (0x20000000U) | ||
| 3818 | #define AIPS_PACRU_WP0_SHIFT (29U) | ||
| 3819 | /*! WP0 - Write Protect | ||
| 3820 | * 0b0..This peripheral allows write accesses. | ||
| 3821 | * 0b1..This peripheral is write protected. | ||
| 3822 | */ | ||
| 3823 | #define AIPS_PACRU_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP0_SHIFT)) & AIPS_PACRU_WP0_MASK) | ||
| 3824 | #define AIPS_PACRU_SP0_MASK (0x40000000U) | ||
| 3825 | #define AIPS_PACRU_SP0_SHIFT (30U) | ||
| 3826 | /*! SP0 - Supervisor Protect | ||
| 3827 | * 0b0..This peripheral does not require supervisor privilege level for accesses. | ||
| 3828 | * 0b1..This peripheral requires supervisor privilege level for accesses. | ||
| 3829 | */ | ||
| 3830 | #define AIPS_PACRU_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP0_SHIFT)) & AIPS_PACRU_SP0_MASK) | ||
| 3831 | /*! @} */ | ||
| 3832 | |||
| 3833 | |||
| 3834 | /*! | ||
| 3835 | * @} | ||
| 3836 | */ /* end of group AIPS_Register_Masks */ | ||
| 3837 | |||
| 3838 | |||
| 3839 | /* AIPS - Peripheral instance base addresses */ | ||
| 3840 | /** Peripheral AIPS0 base address */ | ||
| 3841 | #define AIPS0_BASE (0x40000000u) | ||
| 3842 | /** Peripheral AIPS0 base pointer */ | ||
| 3843 | #define AIPS0 ((AIPS_Type *)AIPS0_BASE) | ||
| 3844 | /** Peripheral AIPS1 base address */ | ||
| 3845 | #define AIPS1_BASE (0x40080000u) | ||
| 3846 | /** Peripheral AIPS1 base pointer */ | ||
| 3847 | #define AIPS1 ((AIPS_Type *)AIPS1_BASE) | ||
| 3848 | /** Array initializer of AIPS peripheral base addresses */ | ||
| 3849 | #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE } | ||
| 3850 | /** Array initializer of AIPS peripheral base pointers */ | ||
| 3851 | #define AIPS_BASE_PTRS { AIPS0, AIPS1 } | ||
| 3852 | |||
| 3853 | /*! | ||
| 3854 | * @} | ||
| 3855 | */ /* end of group AIPS_Peripheral_Access_Layer */ | ||
| 3856 | |||
| 3857 | |||
| 3858 | /* ---------------------------------------------------------------------------- | ||
| 3859 | -- AXBS Peripheral Access Layer | ||
| 3860 | ---------------------------------------------------------------------------- */ | ||
| 3861 | |||
| 3862 | /*! | ||
| 3863 | * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer | ||
| 3864 | * @{ | ||
| 3865 | */ | ||
| 3866 | |||
| 3867 | /** AXBS - Register Layout Typedef */ | ||
| 3868 | typedef struct { | ||
| 3869 | struct { /* offset: 0x0, array step: 0x100 */ | ||
| 3870 | __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */ | ||
| 3871 | uint8_t RESERVED_0[12]; | ||
| 3872 | __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */ | ||
| 3873 | uint8_t RESERVED_1[236]; | ||
| 3874 | } SLAVE[5]; | ||
| 3875 | uint8_t RESERVED_0[768]; | ||
| 3876 | __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ | ||
| 3877 | uint8_t RESERVED_1[252]; | ||
| 3878 | __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ | ||
| 3879 | uint8_t RESERVED_2[252]; | ||
| 3880 | __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ | ||
| 3881 | uint8_t RESERVED_3[252]; | ||
| 3882 | __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */ | ||
| 3883 | uint8_t RESERVED_4[252]; | ||
| 3884 | __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ | ||
| 3885 | uint8_t RESERVED_5[252]; | ||
| 3886 | __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ | ||
| 3887 | } AXBS_Type; | ||
| 3888 | |||
| 3889 | /* ---------------------------------------------------------------------------- | ||
| 3890 | -- AXBS Register Masks | ||
| 3891 | ---------------------------------------------------------------------------- */ | ||
| 3892 | |||
| 3893 | /*! | ||
| 3894 | * @addtogroup AXBS_Register_Masks AXBS Register Masks | ||
| 3895 | * @{ | ||
| 3896 | */ | ||
| 3897 | |||
| 3898 | /*! @name PRS - Priority Registers Slave */ | ||
| 3899 | /*! @{ */ | ||
| 3900 | #define AXBS_PRS_M0_MASK (0x7U) | ||
| 3901 | #define AXBS_PRS_M0_SHIFT (0U) | ||
| 3902 | /*! M0 - Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. | ||
| 3903 | * 0b000..This master has level 1, or highest, priority when accessing the slave port. | ||
| 3904 | * 0b001..This master has level 2 priority when accessing the slave port. | ||
| 3905 | * 0b010..This master has level 3 priority when accessing the slave port. | ||
| 3906 | * 0b011..This master has level 4 priority when accessing the slave port. | ||
| 3907 | * 0b100..This master has level 5 priority when accessing the slave port. | ||
| 3908 | * 0b101..This master has level 6 priority when accessing the slave port. | ||
| 3909 | * 0b110..This master has level 7 priority when accessing the slave port. | ||
| 3910 | * 0b111..This master has level 8, or lowest, priority when accessing the slave port. | ||
| 3911 | */ | ||
| 3912 | #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK) | ||
| 3913 | #define AXBS_PRS_M1_MASK (0x70U) | ||
| 3914 | #define AXBS_PRS_M1_SHIFT (4U) | ||
| 3915 | /*! M1 - Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. | ||
| 3916 | * 0b000..This master has level 1, or highest, priority when accessing the slave port. | ||
| 3917 | * 0b001..This master has level 2 priority when accessing the slave port. | ||
| 3918 | * 0b010..This master has level 3 priority when accessing the slave port. | ||
| 3919 | * 0b011..This master has level 4 priority when accessing the slave port. | ||
| 3920 | * 0b100..This master has level 5 priority when accessing the slave port. | ||
| 3921 | * 0b101..This master has level 6 priority when accessing the slave port. | ||
| 3922 | * 0b110..This master has level 7 priority when accessing the slave port. | ||
| 3923 | * 0b111..This master has level 8, or lowest, priority when accessing the slave port. | ||
| 3924 | */ | ||
| 3925 | #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK) | ||
| 3926 | #define AXBS_PRS_M2_MASK (0x700U) | ||
| 3927 | #define AXBS_PRS_M2_SHIFT (8U) | ||
| 3928 | /*! M2 - Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. | ||
| 3929 | * 0b000..This master has level 1, or highest, priority when accessing the slave port. | ||
| 3930 | * 0b001..This master has level 2 priority when accessing the slave port. | ||
| 3931 | * 0b010..This master has level 3 priority when accessing the slave port. | ||
| 3932 | * 0b011..This master has level 4 priority when accessing the slave port. | ||
| 3933 | * 0b100..This master has level 5 priority when accessing the slave port. | ||
| 3934 | * 0b101..This master has level 6 priority when accessing the slave port. | ||
| 3935 | * 0b110..This master has level 7 priority when accessing the slave port. | ||
| 3936 | * 0b111..This master has level 8, or lowest, priority when accessing the slave port. | ||
| 3937 | */ | ||
| 3938 | #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK) | ||
| 3939 | #define AXBS_PRS_M3_MASK (0x7000U) | ||
| 3940 | #define AXBS_PRS_M3_SHIFT (12U) | ||
| 3941 | /*! M3 - Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. | ||
| 3942 | * 0b000..This master has level 1, or highest, priority when accessing the slave port. | ||
| 3943 | * 0b001..This master has level 2 priority when accessing the slave port. | ||
| 3944 | * 0b010..This master has level 3 priority when accessing the slave port. | ||
| 3945 | * 0b011..This master has level 4 priority when accessing the slave port. | ||
| 3946 | * 0b100..This master has level 5 priority when accessing the slave port. | ||
| 3947 | * 0b101..This master has level 6 priority when accessing the slave port. | ||
| 3948 | * 0b110..This master has level 7 priority when accessing the slave port. | ||
| 3949 | * 0b111..This master has level 8, or lowest, priority when accessing the slave port. | ||
| 3950 | */ | ||
| 3951 | #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK) | ||
| 3952 | #define AXBS_PRS_M4_MASK (0x70000U) | ||
| 3953 | #define AXBS_PRS_M4_SHIFT (16U) | ||
| 3954 | /*! M4 - Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. | ||
| 3955 | * 0b000..This master has level 1, or highest, priority when accessing the slave port. | ||
| 3956 | * 0b001..This master has level 2 priority when accessing the slave port. | ||
| 3957 | * 0b010..This master has level 3 priority when accessing the slave port. | ||
| 3958 | * 0b011..This master has level 4 priority when accessing the slave port. | ||
| 3959 | * 0b100..This master has level 5 priority when accessing the slave port. | ||
| 3960 | * 0b101..This master has level 6 priority when accessing the slave port. | ||
| 3961 | * 0b110..This master has level 7 priority when accessing the slave port. | ||
| 3962 | * 0b111..This master has level 8, or lowest, priority when accessing the slave port. | ||
| 3963 | */ | ||
| 3964 | #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK) | ||
| 3965 | #define AXBS_PRS_M5_MASK (0x700000U) | ||
| 3966 | #define AXBS_PRS_M5_SHIFT (20U) | ||
| 3967 | /*! M5 - Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. | ||
| 3968 | * 0b000..This master has level 1, or highest, priority when accessing the slave port. | ||
| 3969 | * 0b001..This master has level 2 priority when accessing the slave port. | ||
| 3970 | * 0b010..This master has level 3 priority when accessing the slave port. | ||
| 3971 | * 0b011..This master has level 4 priority when accessing the slave port. | ||
| 3972 | * 0b100..This master has level 5 priority when accessing the slave port. | ||
| 3973 | * 0b101..This master has level 6 priority when accessing the slave port. | ||
| 3974 | * 0b110..This master has level 7 priority when accessing the slave port. | ||
| 3975 | * 0b111..This master has level 8, or lowest, priority when accessing the slave port. | ||
| 3976 | */ | ||
| 3977 | #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK) | ||
| 3978 | /*! @} */ | ||
| 3979 | |||
| 3980 | /* The count of AXBS_PRS */ | ||
| 3981 | #define AXBS_PRS_COUNT (5U) | ||
| 3982 | |||
| 3983 | /*! @name CRS - Control Register */ | ||
| 3984 | /*! @{ */ | ||
| 3985 | #define AXBS_CRS_PARK_MASK (0x7U) | ||
| 3986 | #define AXBS_CRS_PARK_SHIFT (0U) | ||
| 3987 | /*! PARK - Park | ||
| 3988 | * 0b000..Park on master port M0 | ||
| 3989 | * 0b001..Park on master port M1 | ||
| 3990 | * 0b010..Park on master port M2 | ||
| 3991 | * 0b011..Park on master port M3 | ||
| 3992 | * 0b100..Park on master port M4 | ||
| 3993 | * 0b101..Park on master port M5 | ||
| 3994 | * 0b110..Park on master port M6 | ||
| 3995 | * 0b111..Park on master port M7 | ||
| 3996 | */ | ||
| 3997 | #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK) | ||
| 3998 | #define AXBS_CRS_PCTL_MASK (0x30U) | ||
| 3999 | #define AXBS_CRS_PCTL_SHIFT (4U) | ||
| 4000 | /*! PCTL - Parking Control | ||
| 4001 | * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field | ||
| 4002 | * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port | ||
| 4003 | * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state | ||
| 4004 | * 0b11..Reserved | ||
| 4005 | */ | ||
| 4006 | #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK) | ||
| 4007 | #define AXBS_CRS_ARB_MASK (0x300U) | ||
| 4008 | #define AXBS_CRS_ARB_SHIFT (8U) | ||
| 4009 | /*! ARB - Arbitration Mode | ||
| 4010 | * 0b00..Fixed priority | ||
| 4011 | * 0b01..Round-robin, or rotating, priority | ||
| 4012 | * 0b10..Reserved | ||
| 4013 | * 0b11..Reserved | ||
| 4014 | */ | ||
| 4015 | #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK) | ||
| 4016 | #define AXBS_CRS_HLP_MASK (0x40000000U) | ||
| 4017 | #define AXBS_CRS_HLP_SHIFT (30U) | ||
| 4018 | /*! HLP - Halt Low Priority | ||
| 4019 | * 0b0..The low power mode request has the highest priority for arbitration on this slave port | ||
| 4020 | * 0b1..The low power mode request has the lowest initial priority for arbitration on this slave port | ||
| 4021 | */ | ||
| 4022 | #define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK) | ||
| 4023 | #define AXBS_CRS_RO_MASK (0x80000000U) | ||
| 4024 | #define AXBS_CRS_RO_SHIFT (31U) | ||
| 4025 | /*! RO - Read Only | ||
| 4026 | * 0b0..The slave port's registers are writeable | ||
| 4027 | * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. | ||
| 4028 | */ | ||
| 4029 | #define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK) | ||
| 4030 | /*! @} */ | ||
| 4031 | |||
| 4032 | /* The count of AXBS_CRS */ | ||
| 4033 | #define AXBS_CRS_COUNT (5U) | ||
| 4034 | |||
| 4035 | /*! @name MGPCR0 - Master General Purpose Control Register */ | ||
| 4036 | /*! @{ */ | ||
| 4037 | #define AXBS_MGPCR0_AULB_MASK (0x7U) | ||
| 4038 | #define AXBS_MGPCR0_AULB_SHIFT (0U) | ||
| 4039 | /*! AULB - Arbitrates On Undefined Length Bursts | ||
| 4040 | * 0b000..No arbitration is allowed during an undefined length burst | ||
| 4041 | * 0b001..Arbitration is allowed at any time during an undefined length burst | ||
| 4042 | * 0b010..Arbitration is allowed after four beats of an undefined length burst | ||
| 4043 | * 0b011..Arbitration is allowed after eight beats of an undefined length burst | ||
| 4044 | * 0b100..Arbitration is allowed after 16 beats of an undefined length burst | ||
| 4045 | * 0b101..Reserved | ||
| 4046 | * 0b110..Reserved | ||
| 4047 | * 0b111..Reserved | ||
| 4048 | */ | ||
| 4049 | #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK) | ||
| 4050 | /*! @} */ | ||
| 4051 | |||
| 4052 | /*! @name MGPCR1 - Master General Purpose Control Register */ | ||
| 4053 | /*! @{ */ | ||
| 4054 | #define AXBS_MGPCR1_AULB_MASK (0x7U) | ||
| 4055 | #define AXBS_MGPCR1_AULB_SHIFT (0U) | ||
| 4056 | /*! AULB - Arbitrates On Undefined Length Bursts | ||
| 4057 | * 0b000..No arbitration is allowed during an undefined length burst | ||
| 4058 | * 0b001..Arbitration is allowed at any time during an undefined length burst | ||
| 4059 | * 0b010..Arbitration is allowed after four beats of an undefined length burst | ||
| 4060 | * 0b011..Arbitration is allowed after eight beats of an undefined length burst | ||
| 4061 | * 0b100..Arbitration is allowed after 16 beats of an undefined length burst | ||
| 4062 | * 0b101..Reserved | ||
| 4063 | * 0b110..Reserved | ||
| 4064 | * 0b111..Reserved | ||
| 4065 | */ | ||
| 4066 | #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK) | ||
| 4067 | /*! @} */ | ||
| 4068 | |||
| 4069 | /*! @name MGPCR2 - Master General Purpose Control Register */ | ||
| 4070 | /*! @{ */ | ||
| 4071 | #define AXBS_MGPCR2_AULB_MASK (0x7U) | ||
| 4072 | #define AXBS_MGPCR2_AULB_SHIFT (0U) | ||
| 4073 | /*! AULB - Arbitrates On Undefined Length Bursts | ||
| 4074 | * 0b000..No arbitration is allowed during an undefined length burst | ||
| 4075 | * 0b001..Arbitration is allowed at any time during an undefined length burst | ||
| 4076 | * 0b010..Arbitration is allowed after four beats of an undefined length burst | ||
| 4077 | * 0b011..Arbitration is allowed after eight beats of an undefined length burst | ||
| 4078 | * 0b100..Arbitration is allowed after 16 beats of an undefined length burst | ||
| 4079 | * 0b101..Reserved | ||
| 4080 | * 0b110..Reserved | ||
| 4081 | * 0b111..Reserved | ||
| 4082 | */ | ||
| 4083 | #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK) | ||
| 4084 | /*! @} */ | ||
| 4085 | |||
| 4086 | /*! @name MGPCR3 - Master General Purpose Control Register */ | ||
| 4087 | /*! @{ */ | ||
| 4088 | #define AXBS_MGPCR3_AULB_MASK (0x7U) | ||
| 4089 | #define AXBS_MGPCR3_AULB_SHIFT (0U) | ||
| 4090 | /*! AULB - Arbitrates On Undefined Length Bursts | ||
| 4091 | * 0b000..No arbitration is allowed during an undefined length burst | ||
| 4092 | * 0b001..Arbitration is allowed at any time during an undefined length burst | ||
| 4093 | * 0b010..Arbitration is allowed after four beats of an undefined length burst | ||
| 4094 | * 0b011..Arbitration is allowed after eight beats of an undefined length burst | ||
| 4095 | * 0b100..Arbitration is allowed after 16 beats of an undefined length burst | ||
| 4096 | * 0b101..Reserved | ||
| 4097 | * 0b110..Reserved | ||
| 4098 | * 0b111..Reserved | ||
| 4099 | */ | ||
| 4100 | #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK) | ||
| 4101 | /*! @} */ | ||
| 4102 | |||
| 4103 | /*! @name MGPCR4 - Master General Purpose Control Register */ | ||
| 4104 | /*! @{ */ | ||
| 4105 | #define AXBS_MGPCR4_AULB_MASK (0x7U) | ||
| 4106 | #define AXBS_MGPCR4_AULB_SHIFT (0U) | ||
| 4107 | /*! AULB - Arbitrates On Undefined Length Bursts | ||
| 4108 | * 0b000..No arbitration is allowed during an undefined length burst | ||
| 4109 | * 0b001..Arbitration is allowed at any time during an undefined length burst | ||
| 4110 | * 0b010..Arbitration is allowed after four beats of an undefined length burst | ||
| 4111 | * 0b011..Arbitration is allowed after eight beats of an undefined length burst | ||
| 4112 | * 0b100..Arbitration is allowed after 16 beats of an undefined length burst | ||
| 4113 | * 0b101..Reserved | ||
| 4114 | * 0b110..Reserved | ||
| 4115 | * 0b111..Reserved | ||
| 4116 | */ | ||
| 4117 | #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK) | ||
| 4118 | /*! @} */ | ||
| 4119 | |||
| 4120 | /*! @name MGPCR5 - Master General Purpose Control Register */ | ||
| 4121 | /*! @{ */ | ||
| 4122 | #define AXBS_MGPCR5_AULB_MASK (0x7U) | ||
| 4123 | #define AXBS_MGPCR5_AULB_SHIFT (0U) | ||
| 4124 | /*! AULB - Arbitrates On Undefined Length Bursts | ||
| 4125 | * 0b000..No arbitration is allowed during an undefined length burst | ||
| 4126 | * 0b001..Arbitration is allowed at any time during an undefined length burst | ||
| 4127 | * 0b010..Arbitration is allowed after four beats of an undefined length burst | ||
| 4128 | * 0b011..Arbitration is allowed after eight beats of an undefined length burst | ||
| 4129 | * 0b100..Arbitration is allowed after 16 beats of an undefined length burst | ||
| 4130 | * 0b101..Reserved | ||
| 4131 | * 0b110..Reserved | ||
| 4132 | * 0b111..Reserved | ||
| 4133 | */ | ||
| 4134 | #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK) | ||
| 4135 | /*! @} */ | ||
| 4136 | |||
| 4137 | |||
| 4138 | /*! | ||
| 4139 | * @} | ||
| 4140 | */ /* end of group AXBS_Register_Masks */ | ||
| 4141 | |||
| 4142 | |||
| 4143 | /* AXBS - Peripheral instance base addresses */ | ||
| 4144 | /** Peripheral AXBS base address */ | ||
| 4145 | #define AXBS_BASE (0x40004000u) | ||
| 4146 | /** Peripheral AXBS base pointer */ | ||
| 4147 | #define AXBS ((AXBS_Type *)AXBS_BASE) | ||
| 4148 | /** Array initializer of AXBS peripheral base addresses */ | ||
| 4149 | #define AXBS_BASE_ADDRS { AXBS_BASE } | ||
| 4150 | /** Array initializer of AXBS peripheral base pointers */ | ||
| 4151 | #define AXBS_BASE_PTRS { AXBS } | ||
| 4152 | |||
| 4153 | /*! | ||
| 4154 | * @} | ||
| 4155 | */ /* end of group AXBS_Peripheral_Access_Layer */ | ||
| 4156 | |||
| 4157 | |||
| 4158 | /* ---------------------------------------------------------------------------- | ||
| 4159 | -- CAN Peripheral Access Layer | ||
| 4160 | ---------------------------------------------------------------------------- */ | ||
| 4161 | |||
| 4162 | /*! | ||
| 4163 | * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer | ||
| 4164 | * @{ | ||
| 4165 | */ | ||
| 4166 | |||
| 4167 | /** CAN - Register Layout Typedef */ | ||
| 4168 | typedef struct { | ||
| 4169 | __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ | ||
| 4170 | __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */ | ||
| 4171 | __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */ | ||
| 4172 | uint8_t RESERVED_0[4]; | ||
| 4173 | __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ | ||
| 4174 | __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */ | ||
| 4175 | __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */ | ||
| 4176 | __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ | ||
| 4177 | __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */ | ||
| 4178 | uint8_t RESERVED_1[4]; | ||
| 4179 | __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */ | ||
| 4180 | uint8_t RESERVED_2[4]; | ||
| 4181 | __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */ | ||
| 4182 | __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */ | ||
| 4183 | __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */ | ||
| 4184 | uint8_t RESERVED_3[8]; | ||
| 4185 | __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ | ||
| 4186 | __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */ | ||
| 4187 | __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ | ||
| 4188 | uint8_t RESERVED_4[48]; | ||
| 4189 | struct { /* offset: 0x80, array step: 0x10 */ | ||
| 4190 | __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */ | ||
| 4191 | __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */ | ||
| 4192 | __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */ | ||
| 4193 | __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */ | ||
| 4194 | } MB[16]; | ||
| 4195 | uint8_t RESERVED_5[1792]; | ||
| 4196 | __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ | ||
| 4197 | } CAN_Type; | ||
| 4198 | |||
| 4199 | /* ---------------------------------------------------------------------------- | ||
| 4200 | -- CAN Register Masks | ||
| 4201 | ---------------------------------------------------------------------------- */ | ||
| 4202 | |||
| 4203 | /*! | ||
| 4204 | * @addtogroup CAN_Register_Masks CAN Register Masks | ||
| 4205 | * @{ | ||
| 4206 | */ | ||
| 4207 | |||
| 4208 | /*! @name MCR - Module Configuration Register */ | ||
| 4209 | /*! @{ */ | ||
| 4210 | #define CAN_MCR_MAXMB_MASK (0x7FU) | ||
| 4211 | #define CAN_MCR_MAXMB_SHIFT (0U) | ||
| 4212 | #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) | ||
| 4213 | #define CAN_MCR_IDAM_MASK (0x300U) | ||
| 4214 | #define CAN_MCR_IDAM_SHIFT (8U) | ||
| 4215 | /*! IDAM - ID Acceptance Mode | ||
| 4216 | * 0b00..Format A: One full ID (standard and extended) per ID Filter Table element. | ||
| 4217 | * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. | ||
| 4218 | * 0b10..Format C: Four partial 8-bit Standard IDs per ID Filter Table element. | ||
| 4219 | * 0b11..Format D: All frames rejected. | ||
| 4220 | */ | ||
| 4221 | #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) | ||
| 4222 | #define CAN_MCR_AEN_MASK (0x1000U) | ||
| 4223 | #define CAN_MCR_AEN_SHIFT (12U) | ||
| 4224 | /*! AEN - Abort Enable | ||
| 4225 | * 0b0..Abort disabled. | ||
| 4226 | * 0b1..Abort enabled. | ||
| 4227 | */ | ||
| 4228 | #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) | ||
| 4229 | #define CAN_MCR_LPRIOEN_MASK (0x2000U) | ||
| 4230 | #define CAN_MCR_LPRIOEN_SHIFT (13U) | ||
| 4231 | /*! LPRIOEN - Local Priority Enable | ||
| 4232 | * 0b0..Local Priority disabled. | ||
| 4233 | * 0b1..Local Priority enabled. | ||
| 4234 | */ | ||
| 4235 | #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) | ||
| 4236 | #define CAN_MCR_IRMQ_MASK (0x10000U) | ||
| 4237 | #define CAN_MCR_IRMQ_SHIFT (16U) | ||
| 4238 | /*! IRMQ - Individual Rx Masking And Queue Enable | ||
| 4239 | * 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. | ||
| 4240 | * 0b1..Individual Rx masking and queue feature are enabled. | ||
| 4241 | */ | ||
| 4242 | #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) | ||
| 4243 | #define CAN_MCR_SRXDIS_MASK (0x20000U) | ||
| 4244 | #define CAN_MCR_SRXDIS_SHIFT (17U) | ||
| 4245 | /*! SRXDIS - Self Reception Disable | ||
| 4246 | * 0b0..Self reception enabled. | ||
| 4247 | * 0b1..Self reception disabled. | ||
| 4248 | */ | ||
| 4249 | #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) | ||
| 4250 | #define CAN_MCR_WAKSRC_MASK (0x80000U) | ||
| 4251 | #define CAN_MCR_WAKSRC_SHIFT (19U) | ||
| 4252 | /*! WAKSRC - Wake Up Source | ||
| 4253 | * 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. | ||
| 4254 | * 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. | ||
| 4255 | */ | ||
| 4256 | #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) | ||
| 4257 | #define CAN_MCR_LPMACK_MASK (0x100000U) | ||
| 4258 | #define CAN_MCR_LPMACK_SHIFT (20U) | ||
| 4259 | /*! LPMACK - Low-Power Mode Acknowledge | ||
| 4260 | * 0b0..FlexCAN is not in a low-power mode. | ||
| 4261 | * 0b1..FlexCAN is in a low-power mode. | ||
| 4262 | */ | ||
| 4263 | #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) | ||
| 4264 | #define CAN_MCR_WRNEN_MASK (0x200000U) | ||
| 4265 | #define CAN_MCR_WRNEN_SHIFT (21U) | ||
| 4266 | /*! WRNEN - Warning Interrupt Enable | ||
| 4267 | * 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. | ||
| 4268 | * 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. | ||
| 4269 | */ | ||
| 4270 | #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) | ||
| 4271 | #define CAN_MCR_SLFWAK_MASK (0x400000U) | ||
| 4272 | #define CAN_MCR_SLFWAK_SHIFT (22U) | ||
| 4273 | /*! SLFWAK - Self Wake Up | ||
| 4274 | * 0b0..FlexCAN Self Wake Up feature is disabled. | ||
| 4275 | * 0b1..FlexCAN Self Wake Up feature is enabled. | ||
| 4276 | */ | ||
| 4277 | #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) | ||
| 4278 | #define CAN_MCR_SUPV_MASK (0x800000U) | ||
| 4279 | #define CAN_MCR_SUPV_SHIFT (23U) | ||
| 4280 | /*! SUPV - Supervisor Mode | ||
| 4281 | * 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses . | ||
| 4282 | * 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location . | ||
| 4283 | */ | ||
| 4284 | #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) | ||
| 4285 | #define CAN_MCR_FRZACK_MASK (0x1000000U) | ||
| 4286 | #define CAN_MCR_FRZACK_SHIFT (24U) | ||
| 4287 | /*! FRZACK - Freeze Mode Acknowledge | ||
| 4288 | * 0b0..FlexCAN not in Freeze mode, prescaler running. | ||
| 4289 | * 0b1..FlexCAN in Freeze mode, prescaler stopped. | ||
| 4290 | */ | ||
| 4291 | #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) | ||
| 4292 | #define CAN_MCR_SOFTRST_MASK (0x2000000U) | ||
| 4293 | #define CAN_MCR_SOFTRST_SHIFT (25U) | ||
| 4294 | /*! SOFTRST - Soft Reset | ||
| 4295 | * 0b0..No reset request. | ||
| 4296 | * 0b1..Resets the registers affected by soft reset. | ||
| 4297 | */ | ||
| 4298 | #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) | ||
| 4299 | #define CAN_MCR_WAKMSK_MASK (0x4000000U) | ||
| 4300 | #define CAN_MCR_WAKMSK_SHIFT (26U) | ||
| 4301 | /*! WAKMSK - Wake Up Interrupt Mask | ||
| 4302 | * 0b0..Wake Up Interrupt is disabled. | ||
| 4303 | * 0b1..Wake Up Interrupt is enabled. | ||
| 4304 | */ | ||
| 4305 | #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) | ||
| 4306 | #define CAN_MCR_NOTRDY_MASK (0x8000000U) | ||
| 4307 | #define CAN_MCR_NOTRDY_SHIFT (27U) | ||
| 4308 | /*! NOTRDY - FlexCAN Not Ready | ||
| 4309 | * 0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. | ||
| 4310 | * 0b1..FlexCAN module is either in Disable mode , Stop mode or Freeze mode. | ||
| 4311 | */ | ||
| 4312 | #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) | ||
| 4313 | #define CAN_MCR_HALT_MASK (0x10000000U) | ||
| 4314 | #define CAN_MCR_HALT_SHIFT (28U) | ||
| 4315 | /*! HALT - Halt FlexCAN | ||
| 4316 | * 0b0..No Freeze mode request. | ||
| 4317 | * 0b1..Enters Freeze mode if the FRZ bit is asserted. | ||
| 4318 | */ | ||
| 4319 | #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) | ||
| 4320 | #define CAN_MCR_RFEN_MASK (0x20000000U) | ||
| 4321 | #define CAN_MCR_RFEN_SHIFT (29U) | ||
| 4322 | /*! RFEN - Rx FIFO Enable | ||
| 4323 | * 0b0..Rx FIFO not enabled. | ||
| 4324 | * 0b1..Rx FIFO enabled. | ||
| 4325 | */ | ||
| 4326 | #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) | ||
| 4327 | #define CAN_MCR_FRZ_MASK (0x40000000U) | ||
| 4328 | #define CAN_MCR_FRZ_SHIFT (30U) | ||
| 4329 | /*! FRZ - Freeze Enable | ||
| 4330 | * 0b0..Not enabled to enter Freeze mode. | ||
| 4331 | * 0b1..Enabled to enter Freeze mode. | ||
| 4332 | */ | ||
| 4333 | #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) | ||
| 4334 | #define CAN_MCR_MDIS_MASK (0x80000000U) | ||
| 4335 | #define CAN_MCR_MDIS_SHIFT (31U) | ||
| 4336 | /*! MDIS - Module Disable | ||
| 4337 | * 0b0..Enable the FlexCAN module. | ||
| 4338 | * 0b1..Disable the FlexCAN module. | ||
| 4339 | */ | ||
| 4340 | #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) | ||
| 4341 | /*! @} */ | ||
| 4342 | |||
| 4343 | /*! @name CTRL1 - Control 1 register */ | ||
| 4344 | /*! @{ */ | ||
| 4345 | #define CAN_CTRL1_PROPSEG_MASK (0x7U) | ||
| 4346 | #define CAN_CTRL1_PROPSEG_SHIFT (0U) | ||
| 4347 | #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) | ||
| 4348 | #define CAN_CTRL1_LOM_MASK (0x8U) | ||
| 4349 | #define CAN_CTRL1_LOM_SHIFT (3U) | ||
| 4350 | /*! LOM - Listen-Only Mode | ||
| 4351 | * 0b0..Listen-Only mode is deactivated. | ||
| 4352 | * 0b1..FlexCAN module operates in Listen-Only mode. | ||
| 4353 | */ | ||
| 4354 | #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) | ||
| 4355 | #define CAN_CTRL1_LBUF_MASK (0x10U) | ||
| 4356 | #define CAN_CTRL1_LBUF_SHIFT (4U) | ||
| 4357 | /*! LBUF - Lowest Buffer Transmitted First | ||
| 4358 | * 0b0..Buffer with highest priority is transmitted first. | ||
| 4359 | * 0b1..Lowest number buffer is transmitted first. | ||
| 4360 | */ | ||
| 4361 | #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) | ||
| 4362 | #define CAN_CTRL1_TSYN_MASK (0x20U) | ||
| 4363 | #define CAN_CTRL1_TSYN_SHIFT (5U) | ||
| 4364 | /*! TSYN - Timer Sync | ||
| 4365 | * 0b0..Timer Sync feature disabled | ||
| 4366 | * 0b1..Timer Sync feature enabled | ||
| 4367 | */ | ||
| 4368 | #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) | ||
| 4369 | #define CAN_CTRL1_BOFFREC_MASK (0x40U) | ||
| 4370 | #define CAN_CTRL1_BOFFREC_SHIFT (6U) | ||
| 4371 | /*! BOFFREC - Bus Off Recovery | ||
| 4372 | * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B. | ||
| 4373 | * 0b1..Automatic recovering from Bus Off state disabled. | ||
| 4374 | */ | ||
| 4375 | #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) | ||
| 4376 | #define CAN_CTRL1_SMP_MASK (0x80U) | ||
| 4377 | #define CAN_CTRL1_SMP_SHIFT (7U) | ||
| 4378 | /*! SMP - CAN Bit Sampling | ||
| 4379 | * 0b0..Just one sample is used to determine the bit value. | ||
| 4380 | * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used. | ||
| 4381 | */ | ||
| 4382 | #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) | ||
| 4383 | #define CAN_CTRL1_RWRNMSK_MASK (0x400U) | ||
| 4384 | #define CAN_CTRL1_RWRNMSK_SHIFT (10U) | ||
| 4385 | /*! RWRNMSK - Rx Warning Interrupt Mask | ||
| 4386 | * 0b0..Rx Warning Interrupt disabled. | ||
| 4387 | * 0b1..Rx Warning Interrupt enabled. | ||
| 4388 | */ | ||
| 4389 | #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) | ||
| 4390 | #define CAN_CTRL1_TWRNMSK_MASK (0x800U) | ||
| 4391 | #define CAN_CTRL1_TWRNMSK_SHIFT (11U) | ||
| 4392 | /*! TWRNMSK - Tx Warning Interrupt Mask | ||
| 4393 | * 0b0..Tx Warning Interrupt disabled. | ||
| 4394 | * 0b1..Tx Warning Interrupt enabled. | ||
| 4395 | */ | ||
| 4396 | #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) | ||
| 4397 | #define CAN_CTRL1_LPB_MASK (0x1000U) | ||
| 4398 | #define CAN_CTRL1_LPB_SHIFT (12U) | ||
| 4399 | /*! LPB - Loop Back Mode | ||
| 4400 | * 0b0..Loop Back disabled. | ||
| 4401 | * 0b1..Loop Back enabled. | ||
| 4402 | */ | ||
| 4403 | #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) | ||
| 4404 | #define CAN_CTRL1_CLKSRC_MASK (0x2000U) | ||
| 4405 | #define CAN_CTRL1_CLKSRC_SHIFT (13U) | ||
| 4406 | /*! CLKSRC - CAN Engine Clock Source | ||
| 4407 | * 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. | ||
| 4408 | * 0b1..The CAN engine clock source is the peripheral clock. | ||
| 4409 | */ | ||
| 4410 | #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK) | ||
| 4411 | #define CAN_CTRL1_ERRMSK_MASK (0x4000U) | ||
| 4412 | #define CAN_CTRL1_ERRMSK_SHIFT (14U) | ||
| 4413 | /*! ERRMSK - Error Mask | ||
| 4414 | * 0b0..Error interrupt disabled. | ||
| 4415 | * 0b1..Error interrupt enabled. | ||
| 4416 | */ | ||
| 4417 | #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) | ||
| 4418 | #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) | ||
| 4419 | #define CAN_CTRL1_BOFFMSK_SHIFT (15U) | ||
| 4420 | /*! BOFFMSK - Bus Off Mask | ||
| 4421 | * 0b0..Bus Off interrupt disabled. | ||
| 4422 | * 0b1..Bus Off interrupt enabled. | ||
| 4423 | */ | ||
| 4424 | #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) | ||
| 4425 | #define CAN_CTRL1_PSEG2_MASK (0x70000U) | ||
| 4426 | #define CAN_CTRL1_PSEG2_SHIFT (16U) | ||
| 4427 | #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) | ||
| 4428 | #define CAN_CTRL1_PSEG1_MASK (0x380000U) | ||
| 4429 | #define CAN_CTRL1_PSEG1_SHIFT (19U) | ||
| 4430 | #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) | ||
| 4431 | #define CAN_CTRL1_RJW_MASK (0xC00000U) | ||
| 4432 | #define CAN_CTRL1_RJW_SHIFT (22U) | ||
| 4433 | #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) | ||
| 4434 | #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) | ||
| 4435 | #define CAN_CTRL1_PRESDIV_SHIFT (24U) | ||
| 4436 | #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) | ||
| 4437 | /*! @} */ | ||
| 4438 | |||
| 4439 | /*! @name TIMER - Free Running Timer */ | ||
| 4440 | /*! @{ */ | ||
| 4441 | #define CAN_TIMER_TIMER_MASK (0xFFFFU) | ||
| 4442 | #define CAN_TIMER_TIMER_SHIFT (0U) | ||
| 4443 | #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) | ||
| 4444 | /*! @} */ | ||
| 4445 | |||
| 4446 | /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ | ||
| 4447 | /*! @{ */ | ||
| 4448 | #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) | ||
| 4449 | #define CAN_RXMGMASK_MG_SHIFT (0U) | ||
| 4450 | /*! MG - Rx Mailboxes Global Mask Bits | ||
| 4451 | * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." | ||
| 4452 | * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked. | ||
| 4453 | */ | ||
| 4454 | #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) | ||
| 4455 | /*! @} */ | ||
| 4456 | |||
| 4457 | /*! @name RX14MASK - Rx 14 Mask register */ | ||
| 4458 | /*! @{ */ | ||
| 4459 | #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) | ||
| 4460 | #define CAN_RX14MASK_RX14M_SHIFT (0U) | ||
| 4461 | /*! RX14M - Rx Buffer 14 Mask Bits | ||
| 4462 | * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." | ||
| 4463 | * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked. | ||
| 4464 | */ | ||
| 4465 | #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) | ||
| 4466 | /*! @} */ | ||
| 4467 | |||
| 4468 | /*! @name RX15MASK - Rx 15 Mask register */ | ||
| 4469 | /*! @{ */ | ||
| 4470 | #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) | ||
| 4471 | #define CAN_RX15MASK_RX15M_SHIFT (0U) | ||
| 4472 | /*! RX15M - Rx Buffer 15 Mask Bits | ||
| 4473 | * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." | ||
| 4474 | * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked. | ||
| 4475 | */ | ||
| 4476 | #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) | ||
| 4477 | /*! @} */ | ||
| 4478 | |||
| 4479 | /*! @name ECR - Error Counter */ | ||
| 4480 | /*! @{ */ | ||
| 4481 | #define CAN_ECR_TXERRCNT_MASK (0xFFU) | ||
| 4482 | #define CAN_ECR_TXERRCNT_SHIFT (0U) | ||
| 4483 | #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) | ||
| 4484 | #define CAN_ECR_RXERRCNT_MASK (0xFF00U) | ||
| 4485 | #define CAN_ECR_RXERRCNT_SHIFT (8U) | ||
| 4486 | #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) | ||
| 4487 | /*! @} */ | ||
| 4488 | |||
| 4489 | /*! @name ESR1 - Error and Status 1 register */ | ||
| 4490 | /*! @{ */ | ||
| 4491 | #define CAN_ESR1_WAKINT_MASK (0x1U) | ||
| 4492 | #define CAN_ESR1_WAKINT_SHIFT (0U) | ||
| 4493 | /*! WAKINT - Wake-Up Interrupt | ||
| 4494 | * 0b0..No such occurrence. | ||
| 4495 | * 0b1..Indicates a recessive to dominant transition was received on the CAN bus. | ||
| 4496 | */ | ||
| 4497 | #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) | ||
| 4498 | #define CAN_ESR1_ERRINT_MASK (0x2U) | ||
| 4499 | #define CAN_ESR1_ERRINT_SHIFT (1U) | ||
| 4500 | /*! ERRINT - Error Interrupt | ||
| 4501 | * 0b0..No such occurrence. | ||
| 4502 | * 0b1..Indicates setting of any Error Bit in the Error and Status Register. | ||
| 4503 | */ | ||
| 4504 | #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) | ||
| 4505 | #define CAN_ESR1_BOFFINT_MASK (0x4U) | ||
| 4506 | #define CAN_ESR1_BOFFINT_SHIFT (2U) | ||
| 4507 | /*! BOFFINT - Bus Off Interrupt | ||
| 4508 | * 0b0..No such occurrence. | ||
| 4509 | * 0b1..FlexCAN module entered Bus Off state. | ||
| 4510 | */ | ||
| 4511 | #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) | ||
| 4512 | #define CAN_ESR1_RX_MASK (0x8U) | ||
| 4513 | #define CAN_ESR1_RX_SHIFT (3U) | ||
| 4514 | /*! RX - FlexCAN In Reception | ||
| 4515 | * 0b0..FlexCAN is not receiving a message. | ||
| 4516 | * 0b1..FlexCAN is receiving a message. | ||
| 4517 | */ | ||
| 4518 | #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) | ||
| 4519 | #define CAN_ESR1_FLTCONF_MASK (0x30U) | ||
| 4520 | #define CAN_ESR1_FLTCONF_SHIFT (4U) | ||
| 4521 | /*! FLTCONF - Fault Confinement State | ||
| 4522 | * 0b00..Error Active | ||
| 4523 | * 0b01..Error Passive | ||
| 4524 | * 0b1x..Bus Off | ||
| 4525 | */ | ||
| 4526 | #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) | ||
| 4527 | #define CAN_ESR1_TX_MASK (0x40U) | ||
| 4528 | #define CAN_ESR1_TX_SHIFT (6U) | ||
| 4529 | /*! TX - FlexCAN In Transmission | ||
| 4530 | * 0b0..FlexCAN is not transmitting a message. | ||
| 4531 | * 0b1..FlexCAN is transmitting a message. | ||
| 4532 | */ | ||
| 4533 | #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) | ||
| 4534 | #define CAN_ESR1_IDLE_MASK (0x80U) | ||
| 4535 | #define CAN_ESR1_IDLE_SHIFT (7U) | ||
| 4536 | /*! IDLE | ||
| 4537 | * 0b0..No such occurrence. | ||
| 4538 | * 0b1..CAN bus is now IDLE. | ||
| 4539 | */ | ||
| 4540 | #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) | ||
| 4541 | #define CAN_ESR1_RXWRN_MASK (0x100U) | ||
| 4542 | #define CAN_ESR1_RXWRN_SHIFT (8U) | ||
| 4543 | /*! RXWRN - Rx Error Warning | ||
| 4544 | * 0b0..No such occurrence. | ||
| 4545 | * 0b1..RXERRCNT is greater than or equal to 96. | ||
| 4546 | */ | ||
| 4547 | #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) | ||
| 4548 | #define CAN_ESR1_TXWRN_MASK (0x200U) | ||
| 4549 | #define CAN_ESR1_TXWRN_SHIFT (9U) | ||
| 4550 | /*! TXWRN - TX Error Warning | ||
| 4551 | * 0b0..No such occurrence. | ||
| 4552 | * 0b1..TXERRCNT is greater than or equal to 96. | ||
| 4553 | */ | ||
| 4554 | #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) | ||
| 4555 | #define CAN_ESR1_STFERR_MASK (0x400U) | ||
| 4556 | #define CAN_ESR1_STFERR_SHIFT (10U) | ||
| 4557 | /*! STFERR - Stuffing Error | ||
| 4558 | * 0b0..No such occurrence. | ||
| 4559 | * 0b1..A Stuffing Error occurred since last read of this register. | ||
| 4560 | */ | ||
| 4561 | #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) | ||
| 4562 | #define CAN_ESR1_FRMERR_MASK (0x800U) | ||
| 4563 | #define CAN_ESR1_FRMERR_SHIFT (11U) | ||
| 4564 | /*! FRMERR - Form Error | ||
| 4565 | * 0b0..No such occurrence. | ||
| 4566 | * 0b1..A Form Error occurred since last read of this register. | ||
| 4567 | */ | ||
| 4568 | #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) | ||
| 4569 | #define CAN_ESR1_CRCERR_MASK (0x1000U) | ||
| 4570 | #define CAN_ESR1_CRCERR_SHIFT (12U) | ||
| 4571 | /*! CRCERR - Cyclic Redundancy Check Error | ||
| 4572 | * 0b0..No such occurrence. | ||
| 4573 | * 0b1..A CRC error occurred since last read of this register. | ||
| 4574 | */ | ||
| 4575 | #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) | ||
| 4576 | #define CAN_ESR1_ACKERR_MASK (0x2000U) | ||
| 4577 | #define CAN_ESR1_ACKERR_SHIFT (13U) | ||
| 4578 | /*! ACKERR - Acknowledge Error | ||
| 4579 | * 0b0..No such occurrence. | ||
| 4580 | * 0b1..An ACK error occurred since last read of this register. | ||
| 4581 | */ | ||
| 4582 | #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) | ||
| 4583 | #define CAN_ESR1_BIT0ERR_MASK (0x4000U) | ||
| 4584 | #define CAN_ESR1_BIT0ERR_SHIFT (14U) | ||
| 4585 | /*! BIT0ERR - Bit0 Error | ||
| 4586 | * 0b0..No such occurrence. | ||
| 4587 | * 0b1..At least one bit sent as dominant is received as recessive. | ||
| 4588 | */ | ||
| 4589 | #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) | ||
| 4590 | #define CAN_ESR1_BIT1ERR_MASK (0x8000U) | ||
| 4591 | #define CAN_ESR1_BIT1ERR_SHIFT (15U) | ||
| 4592 | /*! BIT1ERR - Bit1 Error | ||
| 4593 | * 0b0..No such occurrence. | ||
| 4594 | * 0b1..At least one bit sent as recessive is received as dominant. | ||
| 4595 | */ | ||
| 4596 | #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) | ||
| 4597 | #define CAN_ESR1_RWRNINT_MASK (0x10000U) | ||
| 4598 | #define CAN_ESR1_RWRNINT_SHIFT (16U) | ||
| 4599 | /*! RWRNINT - Rx Warning Interrupt Flag | ||
| 4600 | * 0b0..No such occurrence. | ||
| 4601 | * 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96. | ||
| 4602 | */ | ||
| 4603 | #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) | ||
| 4604 | #define CAN_ESR1_TWRNINT_MASK (0x20000U) | ||
| 4605 | #define CAN_ESR1_TWRNINT_SHIFT (17U) | ||
| 4606 | /*! TWRNINT - Tx Warning Interrupt Flag | ||
| 4607 | * 0b0..No such occurrence. | ||
| 4608 | * 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96. | ||
| 4609 | */ | ||
| 4610 | #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) | ||
| 4611 | #define CAN_ESR1_SYNCH_MASK (0x40000U) | ||
| 4612 | #define CAN_ESR1_SYNCH_SHIFT (18U) | ||
| 4613 | /*! SYNCH - CAN Synchronization Status | ||
| 4614 | * 0b0..FlexCAN is not synchronized to the CAN bus. | ||
| 4615 | * 0b1..FlexCAN is synchronized to the CAN bus. | ||
| 4616 | */ | ||
| 4617 | #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) | ||
| 4618 | /*! @} */ | ||
| 4619 | |||
| 4620 | /*! @name IMASK1 - Interrupt Masks 1 register */ | ||
| 4621 | /*! @{ */ | ||
| 4622 | #define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) | ||
| 4623 | #define CAN_IMASK1_BUFLM_SHIFT (0U) | ||
| 4624 | /*! BUFLM - Buffer MB i Mask | ||
| 4625 | * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled. | ||
| 4626 | * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled. | ||
| 4627 | */ | ||
| 4628 | #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) | ||
| 4629 | /*! @} */ | ||
| 4630 | |||
| 4631 | /*! @name IFLAG1 - Interrupt Flags 1 register */ | ||
| 4632 | /*! @{ */ | ||
| 4633 | #define CAN_IFLAG1_BUF0I_MASK (0x1U) | ||
| 4634 | #define CAN_IFLAG1_BUF0I_SHIFT (0U) | ||
| 4635 | /*! BUF0I - Buffer MB0 Interrupt Or "reserved" | ||
| 4636 | * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. | ||
| 4637 | * 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. | ||
| 4638 | */ | ||
| 4639 | #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) | ||
| 4640 | #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) | ||
| 4641 | #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) | ||
| 4642 | /*! BUF4TO1I - Buffer MB i Interrupt Or "reserved" | ||
| 4643 | * 0b0000..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. | ||
| 4644 | * 0b0001..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. | ||
| 4645 | */ | ||
| 4646 | #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) | ||
| 4647 | #define CAN_IFLAG1_BUF5I_MASK (0x20U) | ||
| 4648 | #define CAN_IFLAG1_BUF5I_SHIFT (5U) | ||
| 4649 | /*! BUF5I - Buffer MB5 Interrupt Or "Frames available in Rx FIFO" | ||
| 4650 | * 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 | ||
| 4651 | * 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1 | ||
| 4652 | */ | ||
| 4653 | #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) | ||
| 4654 | #define CAN_IFLAG1_BUF6I_MASK (0x40U) | ||
| 4655 | #define CAN_IFLAG1_BUF6I_SHIFT (6U) | ||
| 4656 | /*! BUF6I - Buffer MB6 Interrupt Or "Rx FIFO Warning" | ||
| 4657 | * 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 | ||
| 4658 | * 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1 | ||
| 4659 | */ | ||
| 4660 | #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) | ||
| 4661 | #define CAN_IFLAG1_BUF7I_MASK (0x80U) | ||
| 4662 | #define CAN_IFLAG1_BUF7I_SHIFT (7U) | ||
| 4663 | /*! BUF7I - Buffer MB7 Interrupt Or "Rx FIFO Overflow" | ||
| 4664 | * 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 | ||
| 4665 | * 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1 | ||
| 4666 | */ | ||
| 4667 | #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) | ||
| 4668 | #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) | ||
| 4669 | #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) | ||
| 4670 | /*! BUF31TO8I - Buffer MBi Interrupt | ||
| 4671 | * 0b000000000000000000000000..The corresponding buffer has no occurrence of successfully completed transmission or reception. | ||
| 4672 | * 0b000000000000000000000001..The corresponding buffer has successfully completed transmission or reception. | ||
| 4673 | */ | ||
| 4674 | #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) | ||
| 4675 | /*! @} */ | ||
| 4676 | |||
| 4677 | /*! @name CTRL2 - Control 2 register */ | ||
| 4678 | /*! @{ */ | ||
| 4679 | #define CAN_CTRL2_EACEN_MASK (0x10000U) | ||
| 4680 | #define CAN_CTRL2_EACEN_SHIFT (16U) | ||
| 4681 | /*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes | ||
| 4682 | * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. | ||
| 4683 | * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. | ||
| 4684 | */ | ||
| 4685 | #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) | ||
| 4686 | #define CAN_CTRL2_RRS_MASK (0x20000U) | ||
| 4687 | #define CAN_CTRL2_RRS_SHIFT (17U) | ||
| 4688 | /*! RRS - Remote Request Storing | ||
| 4689 | * 0b0..Remote Response Frame is generated. | ||
| 4690 | * 0b1..Remote Request Frame is stored. | ||
| 4691 | */ | ||
| 4692 | #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) | ||
| 4693 | #define CAN_CTRL2_MRP_MASK (0x40000U) | ||
| 4694 | #define CAN_CTRL2_MRP_SHIFT (18U) | ||
| 4695 | /*! MRP - Mailboxes Reception Priority | ||
| 4696 | * 0b0..Matching starts from Rx FIFO and continues on Mailboxes. | ||
| 4697 | * 0b1..Matching starts from Mailboxes and continues on Rx FIFO. | ||
| 4698 | */ | ||
| 4699 | #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) | ||
| 4700 | #define CAN_CTRL2_TASD_MASK (0xF80000U) | ||
| 4701 | #define CAN_CTRL2_TASD_SHIFT (19U) | ||
| 4702 | #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) | ||
| 4703 | #define CAN_CTRL2_RFFN_MASK (0xF000000U) | ||
| 4704 | #define CAN_CTRL2_RFFN_SHIFT (24U) | ||
| 4705 | #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) | ||
| 4706 | #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) | ||
| 4707 | #define CAN_CTRL2_WRMFRZ_SHIFT (28U) | ||
| 4708 | /*! WRMFRZ - Write-Access To Memory In Freeze Mode | ||
| 4709 | * 0b0..Maintain the write access restrictions. | ||
| 4710 | * 0b1..Enable unrestricted write access to FlexCAN memory. | ||
| 4711 | */ | ||
| 4712 | #define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) | ||
| 4713 | /*! @} */ | ||
| 4714 | |||
| 4715 | /*! @name ESR2 - Error and Status 2 register */ | ||
| 4716 | /*! @{ */ | ||
| 4717 | #define CAN_ESR2_IMB_MASK (0x2000U) | ||
| 4718 | #define CAN_ESR2_IMB_SHIFT (13U) | ||
| 4719 | /*! IMB - Inactive Mailbox | ||
| 4720 | * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. | ||
| 4721 | * 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. | ||
| 4722 | */ | ||
| 4723 | #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) | ||
| 4724 | #define CAN_ESR2_VPS_MASK (0x4000U) | ||
| 4725 | #define CAN_ESR2_VPS_SHIFT (14U) | ||
| 4726 | /*! VPS - Valid Priority Status | ||
| 4727 | * 0b0..Contents of IMB and LPTM are invalid. | ||
| 4728 | * 0b1..Contents of IMB and LPTM are valid. | ||
| 4729 | */ | ||
| 4730 | #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) | ||
| 4731 | #define CAN_ESR2_LPTM_MASK (0x7F0000U) | ||
| 4732 | #define CAN_ESR2_LPTM_SHIFT (16U) | ||
| 4733 | #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) | ||
| 4734 | /*! @} */ | ||
| 4735 | |||
| 4736 | /*! @name CRCR - CRC Register */ | ||
| 4737 | /*! @{ */ | ||
| 4738 | #define CAN_CRCR_TXCRC_MASK (0x7FFFU) | ||
| 4739 | #define CAN_CRCR_TXCRC_SHIFT (0U) | ||
| 4740 | #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) | ||
| 4741 | #define CAN_CRCR_MBCRC_MASK (0x7F0000U) | ||
| 4742 | #define CAN_CRCR_MBCRC_SHIFT (16U) | ||
| 4743 | #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) | ||
| 4744 | /*! @} */ | ||
| 4745 | |||
| 4746 | /*! @name RXFGMASK - Rx FIFO Global Mask register */ | ||
| 4747 | /*! @{ */ | ||
| 4748 | #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) | ||
| 4749 | #define CAN_RXFGMASK_FGM_SHIFT (0U) | ||
| 4750 | /*! FGM - Rx FIFO Global Mask Bits | ||
| 4751 | * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." | ||
| 4752 | * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked. | ||
| 4753 | */ | ||
| 4754 | #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) | ||
| 4755 | /*! @} */ | ||
| 4756 | |||
| 4757 | /*! @name RXFIR - Rx FIFO Information Register */ | ||
| 4758 | /*! @{ */ | ||
| 4759 | #define CAN_RXFIR_IDHIT_MASK (0x1FFU) | ||
| 4760 | #define CAN_RXFIR_IDHIT_SHIFT (0U) | ||
| 4761 | #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) | ||
| 4762 | /*! @} */ | ||
| 4763 | |||
| 4764 | /*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */ | ||
| 4765 | /*! @{ */ | ||
| 4766 | #define CAN_CS_TIME_STAMP_MASK (0xFFFFU) | ||
| 4767 | #define CAN_CS_TIME_STAMP_SHIFT (0U) | ||
| 4768 | #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) | ||
| 4769 | #define CAN_CS_DLC_MASK (0xF0000U) | ||
| 4770 | #define CAN_CS_DLC_SHIFT (16U) | ||
| 4771 | #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) | ||
| 4772 | #define CAN_CS_RTR_MASK (0x100000U) | ||
| 4773 | #define CAN_CS_RTR_SHIFT (20U) | ||
| 4774 | #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) | ||
| 4775 | #define CAN_CS_IDE_MASK (0x200000U) | ||
| 4776 | #define CAN_CS_IDE_SHIFT (21U) | ||
| 4777 | #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) | ||
| 4778 | #define CAN_CS_SRR_MASK (0x400000U) | ||
| 4779 | #define CAN_CS_SRR_SHIFT (22U) | ||
| 4780 | #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) | ||
| 4781 | #define CAN_CS_CODE_MASK (0xF000000U) | ||
| 4782 | #define CAN_CS_CODE_SHIFT (24U) | ||
| 4783 | #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) | ||
| 4784 | /*! @} */ | ||
| 4785 | |||
| 4786 | /* The count of CAN_CS */ | ||
| 4787 | #define CAN_CS_COUNT (16U) | ||
| 4788 | |||
| 4789 | /*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */ | ||
| 4790 | /*! @{ */ | ||
| 4791 | #define CAN_ID_EXT_MASK (0x3FFFFU) | ||
| 4792 | #define CAN_ID_EXT_SHIFT (0U) | ||
| 4793 | #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) | ||
| 4794 | #define CAN_ID_STD_MASK (0x1FFC0000U) | ||
| 4795 | #define CAN_ID_STD_SHIFT (18U) | ||
| 4796 | #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) | ||
| 4797 | #define CAN_ID_PRIO_MASK (0xE0000000U) | ||
| 4798 | #define CAN_ID_PRIO_SHIFT (29U) | ||
| 4799 | #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) | ||
| 4800 | /*! @} */ | ||
| 4801 | |||
| 4802 | /* The count of CAN_ID */ | ||
| 4803 | #define CAN_ID_COUNT (16U) | ||
| 4804 | |||
| 4805 | /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */ | ||
| 4806 | /*! @{ */ | ||
| 4807 | #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) | ||
| 4808 | #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) | ||
| 4809 | #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) | ||
| 4810 | #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) | ||
| 4811 | #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) | ||
| 4812 | #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) | ||
| 4813 | #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) | ||
| 4814 | #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) | ||
| 4815 | #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) | ||
| 4816 | #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) | ||
| 4817 | #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) | ||
| 4818 | #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) | ||
| 4819 | /*! @} */ | ||
| 4820 | |||
| 4821 | /* The count of CAN_WORD0 */ | ||
| 4822 | #define CAN_WORD0_COUNT (16U) | ||
| 4823 | |||
| 4824 | /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */ | ||
| 4825 | /*! @{ */ | ||
| 4826 | #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) | ||
| 4827 | #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) | ||
| 4828 | #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) | ||
| 4829 | #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) | ||
| 4830 | #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) | ||
| 4831 | #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) | ||
| 4832 | #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) | ||
| 4833 | #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) | ||
| 4834 | #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) | ||
| 4835 | #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) | ||
| 4836 | #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) | ||
| 4837 | #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) | ||
| 4838 | /*! @} */ | ||
| 4839 | |||
| 4840 | /* The count of CAN_WORD1 */ | ||
| 4841 | #define CAN_WORD1_COUNT (16U) | ||
| 4842 | |||
| 4843 | /*! @name RXIMR - Rx Individual Mask Registers */ | ||
| 4844 | /*! @{ */ | ||
| 4845 | #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) | ||
| 4846 | #define CAN_RXIMR_MI_SHIFT (0U) | ||
| 4847 | /*! MI - Individual Mask Bits | ||
| 4848 | * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." | ||
| 4849 | * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked. | ||
| 4850 | */ | ||
| 4851 | #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) | ||
| 4852 | /*! @} */ | ||
| 4853 | |||
| 4854 | /* The count of CAN_RXIMR */ | ||
| 4855 | #define CAN_RXIMR_COUNT (16U) | ||
| 4856 | |||
| 4857 | |||
| 4858 | /*! | ||
| 4859 | * @} | ||
| 4860 | */ /* end of group CAN_Register_Masks */ | ||
| 4861 | |||
| 4862 | |||
| 4863 | /* CAN - Peripheral instance base addresses */ | ||
| 4864 | /** Peripheral CAN0 base address */ | ||
| 4865 | #define CAN0_BASE (0x40024000u) | ||
| 4866 | /** Peripheral CAN0 base pointer */ | ||
| 4867 | #define CAN0 ((CAN_Type *)CAN0_BASE) | ||
| 4868 | /** Array initializer of CAN peripheral base addresses */ | ||
| 4869 | #define CAN_BASE_ADDRS { CAN0_BASE } | ||
| 4870 | /** Array initializer of CAN peripheral base pointers */ | ||
| 4871 | #define CAN_BASE_PTRS { CAN0 } | ||
| 4872 | /** Interrupt vectors for the CAN peripheral type */ | ||
| 4873 | #define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn } | ||
| 4874 | #define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn } | ||
| 4875 | #define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn } | ||
| 4876 | #define CAN_Error_IRQS { CAN0_Error_IRQn } | ||
| 4877 | #define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn } | ||
| 4878 | #define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn } | ||
| 4879 | |||
| 4880 | /*! | ||
| 4881 | * @} | ||
| 4882 | */ /* end of group CAN_Peripheral_Access_Layer */ | ||
| 4883 | |||
| 4884 | |||
| 4885 | /* ---------------------------------------------------------------------------- | ||
| 4886 | -- CAU Peripheral Access Layer | ||
| 4887 | ---------------------------------------------------------------------------- */ | ||
| 4888 | |||
| 4889 | /*! | ||
| 4890 | * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer | ||
| 4891 | * @{ | ||
| 4892 | */ | ||
| 4893 | |||
| 4894 | /** CAU - Register Layout Typedef */ | ||
| 4895 | typedef struct { | ||
| 4896 | __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */ | ||
| 4897 | uint8_t RESERVED_0[2048]; | ||
| 4898 | __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */ | ||
| 4899 | __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */ | ||
| 4900 | __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */ | ||
| 4901 | uint8_t RESERVED_1[20]; | ||
| 4902 | __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */ | ||
| 4903 | __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */ | ||
| 4904 | __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */ | ||
| 4905 | uint8_t RESERVED_2[20]; | ||
| 4906 | __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */ | ||
| 4907 | __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */ | ||
| 4908 | __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */ | ||
| 4909 | uint8_t RESERVED_3[20]; | ||
| 4910 | __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */ | ||
| 4911 | __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */ | ||
| 4912 | __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */ | ||
| 4913 | uint8_t RESERVED_4[84]; | ||
| 4914 | __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */ | ||
| 4915 | __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */ | ||
| 4916 | __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */ | ||
| 4917 | uint8_t RESERVED_5[20]; | ||
| 4918 | __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */ | ||
| 4919 | __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */ | ||
| 4920 | __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */ | ||
| 4921 | uint8_t RESERVED_6[276]; | ||
| 4922 | __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */ | ||
| 4923 | __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */ | ||
| 4924 | __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */ | ||
| 4925 | uint8_t RESERVED_7[20]; | ||
| 4926 | __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */ | ||
| 4927 | __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */ | ||
| 4928 | __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */ | ||
| 4929 | } CAU_Type; | ||
| 4930 | |||
| 4931 | /* ---------------------------------------------------------------------------- | ||
| 4932 | -- CAU Register Masks | ||
| 4933 | ---------------------------------------------------------------------------- */ | ||
| 4934 | |||
| 4935 | /*! | ||
| 4936 | * @addtogroup CAU_Register_Masks CAU Register Masks | ||
| 4937 | * @{ | ||
| 4938 | */ | ||
| 4939 | |||
| 4940 | /*! @name DIRECT - Direct access register 0..Direct access register 15 */ | ||
| 4941 | /*! @{ */ | ||
| 4942 | #define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU) | ||
| 4943 | #define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U) | ||
| 4944 | #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK) | ||
| 4945 | #define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU) | ||
| 4946 | #define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U) | ||
| 4947 | #define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK) | ||
| 4948 | #define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU) | ||
| 4949 | #define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U) | ||
| 4950 | #define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK) | ||
| 4951 | #define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU) | ||
| 4952 | #define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U) | ||
| 4953 | #define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK) | ||
| 4954 | #define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU) | ||
| 4955 | #define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U) | ||
| 4956 | #define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK) | ||
| 4957 | #define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU) | ||
| 4958 | #define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U) | ||
| 4959 | #define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK) | ||
| 4960 | #define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU) | ||
| 4961 | #define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U) | ||
| 4962 | #define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK) | ||
| 4963 | #define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU) | ||
| 4964 | #define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U) | ||
| 4965 | #define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK) | ||
| 4966 | #define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU) | ||
| 4967 | #define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U) | ||
| 4968 | #define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK) | ||
| 4969 | #define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU) | ||
| 4970 | #define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U) | ||
| 4971 | #define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK) | ||
| 4972 | #define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU) | ||
| 4973 | #define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U) | ||
| 4974 | #define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK) | ||
| 4975 | #define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU) | ||
| 4976 | #define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U) | ||
| 4977 | #define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK) | ||
| 4978 | #define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU) | ||
| 4979 | #define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U) | ||
| 4980 | #define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK) | ||
| 4981 | #define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU) | ||
| 4982 | #define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U) | ||
| 4983 | #define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK) | ||
| 4984 | #define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU) | ||
| 4985 | #define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U) | ||
| 4986 | #define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK) | ||
| 4987 | #define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU) | ||
| 4988 | #define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U) | ||
| 4989 | #define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK) | ||
| 4990 | /*! @} */ | ||
| 4991 | |||
| 4992 | /* The count of CAU_DIRECT */ | ||
| 4993 | #define CAU_DIRECT_COUNT (16U) | ||
| 4994 | |||
| 4995 | /*! @name LDR_CASR - Status register - Load Register command */ | ||
| 4996 | /*! @{ */ | ||
| 4997 | #define CAU_LDR_CASR_IC_MASK (0x1U) | ||
| 4998 | #define CAU_LDR_CASR_IC_SHIFT (0U) | ||
| 4999 | /*! IC | ||
| 5000 | * 0b0..No illegal commands issued | ||
| 5001 | * 0b1..Illegal command issued | ||
| 5002 | */ | ||
| 5003 | #define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK) | ||
| 5004 | #define CAU_LDR_CASR_DPE_MASK (0x2U) | ||
| 5005 | #define CAU_LDR_CASR_DPE_SHIFT (1U) | ||
| 5006 | /*! DPE | ||
| 5007 | * 0b0..No error detected | ||
| 5008 | * 0b1..DES key parity error detected | ||
| 5009 | */ | ||
| 5010 | #define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK) | ||
| 5011 | #define CAU_LDR_CASR_VER_MASK (0xF0000000U) | ||
| 5012 | #define CAU_LDR_CASR_VER_SHIFT (28U) | ||
| 5013 | /*! VER - CAU version | ||
| 5014 | * 0b0001..Initial CAU version | ||
| 5015 | * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device) | ||
| 5016 | */ | ||
| 5017 | #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK) | ||
| 5018 | /*! @} */ | ||
| 5019 | |||
| 5020 | /*! @name LDR_CAA - Accumulator register - Load Register command */ | ||
| 5021 | /*! @{ */ | ||
| 5022 | #define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU) | ||
| 5023 | #define CAU_LDR_CAA_ACC_SHIFT (0U) | ||
| 5024 | #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK) | ||
| 5025 | /*! @} */ | ||
| 5026 | |||
| 5027 | /*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */ | ||
| 5028 | /*! @{ */ | ||
| 5029 | #define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU) | ||
| 5030 | #define CAU_LDR_CA_CA0_SHIFT (0U) | ||
| 5031 | #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK) | ||
| 5032 | #define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU) | ||
| 5033 | #define CAU_LDR_CA_CA1_SHIFT (0U) | ||
| 5034 | #define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK) | ||
| 5035 | #define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU) | ||
| 5036 | #define CAU_LDR_CA_CA2_SHIFT (0U) | ||
| 5037 | #define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK) | ||
| 5038 | #define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU) | ||
| 5039 | #define CAU_LDR_CA_CA3_SHIFT (0U) | ||
| 5040 | #define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK) | ||
| 5041 | #define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU) | ||
| 5042 | #define CAU_LDR_CA_CA4_SHIFT (0U) | ||
| 5043 | #define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK) | ||
| 5044 | #define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU) | ||
| 5045 | #define CAU_LDR_CA_CA5_SHIFT (0U) | ||
| 5046 | #define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK) | ||
| 5047 | #define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU) | ||
| 5048 | #define CAU_LDR_CA_CA6_SHIFT (0U) | ||
| 5049 | #define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK) | ||
| 5050 | #define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU) | ||
| 5051 | #define CAU_LDR_CA_CA7_SHIFT (0U) | ||
| 5052 | #define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK) | ||
| 5053 | #define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU) | ||
| 5054 | #define CAU_LDR_CA_CA8_SHIFT (0U) | ||
| 5055 | #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK) | ||
| 5056 | /*! @} */ | ||
| 5057 | |||
| 5058 | /* The count of CAU_LDR_CA */ | ||
| 5059 | #define CAU_LDR_CA_COUNT (9U) | ||
| 5060 | |||
| 5061 | /*! @name STR_CASR - Status register - Store Register command */ | ||
| 5062 | /*! @{ */ | ||
| 5063 | #define CAU_STR_CASR_IC_MASK (0x1U) | ||
| 5064 | #define CAU_STR_CASR_IC_SHIFT (0U) | ||
| 5065 | /*! IC | ||
| 5066 | * 0b0..No illegal commands issued | ||
| 5067 | * 0b1..Illegal command issued | ||
| 5068 | */ | ||
| 5069 | #define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK) | ||
| 5070 | #define CAU_STR_CASR_DPE_MASK (0x2U) | ||
| 5071 | #define CAU_STR_CASR_DPE_SHIFT (1U) | ||
| 5072 | /*! DPE | ||
| 5073 | * 0b0..No error detected | ||
| 5074 | * 0b1..DES key parity error detected | ||
| 5075 | */ | ||
| 5076 | #define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK) | ||
| 5077 | #define CAU_STR_CASR_VER_MASK (0xF0000000U) | ||
| 5078 | #define CAU_STR_CASR_VER_SHIFT (28U) | ||
| 5079 | /*! VER - CAU version | ||
| 5080 | * 0b0001..Initial CAU version | ||
| 5081 | * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device) | ||
| 5082 | */ | ||
| 5083 | #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK) | ||
| 5084 | /*! @} */ | ||
| 5085 | |||
| 5086 | /*! @name STR_CAA - Accumulator register - Store Register command */ | ||
| 5087 | /*! @{ */ | ||
| 5088 | #define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU) | ||
| 5089 | #define CAU_STR_CAA_ACC_SHIFT (0U) | ||
| 5090 | #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK) | ||
| 5091 | /*! @} */ | ||
| 5092 | |||
| 5093 | /*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */ | ||
| 5094 | /*! @{ */ | ||
| 5095 | #define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU) | ||
| 5096 | #define CAU_STR_CA_CA0_SHIFT (0U) | ||
| 5097 | #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK) | ||
| 5098 | #define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU) | ||
| 5099 | #define CAU_STR_CA_CA1_SHIFT (0U) | ||
| 5100 | #define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK) | ||
| 5101 | #define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU) | ||
| 5102 | #define CAU_STR_CA_CA2_SHIFT (0U) | ||
| 5103 | #define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK) | ||
| 5104 | #define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU) | ||
| 5105 | #define CAU_STR_CA_CA3_SHIFT (0U) | ||
| 5106 | #define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK) | ||
| 5107 | #define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU) | ||
| 5108 | #define CAU_STR_CA_CA4_SHIFT (0U) | ||
| 5109 | #define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK) | ||
| 5110 | #define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU) | ||
| 5111 | #define CAU_STR_CA_CA5_SHIFT (0U) | ||
| 5112 | #define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK) | ||
| 5113 | #define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU) | ||
| 5114 | #define CAU_STR_CA_CA6_SHIFT (0U) | ||
| 5115 | #define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK) | ||
| 5116 | #define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU) | ||
| 5117 | #define CAU_STR_CA_CA7_SHIFT (0U) | ||
| 5118 | #define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK) | ||
| 5119 | #define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU) | ||
| 5120 | #define CAU_STR_CA_CA8_SHIFT (0U) | ||
| 5121 | #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK) | ||
| 5122 | /*! @} */ | ||
| 5123 | |||
| 5124 | /* The count of CAU_STR_CA */ | ||
| 5125 | #define CAU_STR_CA_COUNT (9U) | ||
| 5126 | |||
| 5127 | /*! @name ADR_CASR - Status register - Add Register command */ | ||
| 5128 | /*! @{ */ | ||
| 5129 | #define CAU_ADR_CASR_IC_MASK (0x1U) | ||
| 5130 | #define CAU_ADR_CASR_IC_SHIFT (0U) | ||
| 5131 | /*! IC | ||
| 5132 | * 0b0..No illegal commands issued | ||
| 5133 | * 0b1..Illegal command issued | ||
| 5134 | */ | ||
| 5135 | #define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK) | ||
| 5136 | #define CAU_ADR_CASR_DPE_MASK (0x2U) | ||
| 5137 | #define CAU_ADR_CASR_DPE_SHIFT (1U) | ||
| 5138 | /*! DPE | ||
| 5139 | * 0b0..No error detected | ||
| 5140 | * 0b1..DES key parity error detected | ||
| 5141 | */ | ||
| 5142 | #define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK) | ||
| 5143 | #define CAU_ADR_CASR_VER_MASK (0xF0000000U) | ||
| 5144 | #define CAU_ADR_CASR_VER_SHIFT (28U) | ||
| 5145 | /*! VER - CAU version | ||
| 5146 | * 0b0001..Initial CAU version | ||
| 5147 | * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device) | ||
| 5148 | */ | ||
| 5149 | #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK) | ||
| 5150 | /*! @} */ | ||
| 5151 | |||
| 5152 | /*! @name ADR_CAA - Accumulator register - Add to register command */ | ||
| 5153 | /*! @{ */ | ||
| 5154 | #define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU) | ||
| 5155 | #define CAU_ADR_CAA_ACC_SHIFT (0U) | ||
| 5156 | #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK) | ||
| 5157 | /*! @} */ | ||
| 5158 | |||
| 5159 | /*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */ | ||
| 5160 | /*! @{ */ | ||
| 5161 | #define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU) | ||
| 5162 | #define CAU_ADR_CA_CA0_SHIFT (0U) | ||
| 5163 | #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK) | ||
| 5164 | #define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU) | ||
| 5165 | #define CAU_ADR_CA_CA1_SHIFT (0U) | ||
| 5166 | #define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK) | ||
| 5167 | #define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU) | ||
| 5168 | #define CAU_ADR_CA_CA2_SHIFT (0U) | ||
| 5169 | #define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK) | ||
| 5170 | #define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU) | ||
| 5171 | #define CAU_ADR_CA_CA3_SHIFT (0U) | ||
| 5172 | #define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK) | ||
| 5173 | #define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU) | ||
| 5174 | #define CAU_ADR_CA_CA4_SHIFT (0U) | ||
| 5175 | #define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK) | ||
| 5176 | #define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU) | ||
| 5177 | #define CAU_ADR_CA_CA5_SHIFT (0U) | ||
| 5178 | #define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK) | ||
| 5179 | #define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU) | ||
| 5180 | #define CAU_ADR_CA_CA6_SHIFT (0U) | ||
| 5181 | #define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK) | ||
| 5182 | #define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU) | ||
| 5183 | #define CAU_ADR_CA_CA7_SHIFT (0U) | ||
| 5184 | #define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK) | ||
| 5185 | #define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU) | ||
| 5186 | #define CAU_ADR_CA_CA8_SHIFT (0U) | ||
| 5187 | #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK) | ||
| 5188 | /*! @} */ | ||
| 5189 | |||
| 5190 | /* The count of CAU_ADR_CA */ | ||
| 5191 | #define CAU_ADR_CA_COUNT (9U) | ||
| 5192 | |||
| 5193 | /*! @name RADR_CASR - Status register - Reverse and Add to Register command */ | ||
| 5194 | /*! @{ */ | ||
| 5195 | #define CAU_RADR_CASR_IC_MASK (0x1U) | ||
| 5196 | #define CAU_RADR_CASR_IC_SHIFT (0U) | ||
| 5197 | /*! IC | ||
| 5198 | * 0b0..No illegal commands issued | ||
| 5199 | * 0b1..Illegal command issued | ||
| 5200 | */ | ||
| 5201 | #define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK) | ||
| 5202 | #define CAU_RADR_CASR_DPE_MASK (0x2U) | ||
| 5203 | #define CAU_RADR_CASR_DPE_SHIFT (1U) | ||
| 5204 | /*! DPE | ||
| 5205 | * 0b0..No error detected | ||
| 5206 | * 0b1..DES key parity error detected | ||
| 5207 | */ | ||
| 5208 | #define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK) | ||
| 5209 | #define CAU_RADR_CASR_VER_MASK (0xF0000000U) | ||
| 5210 | #define CAU_RADR_CASR_VER_SHIFT (28U) | ||
| 5211 | /*! VER - CAU version | ||
| 5212 | * 0b0001..Initial CAU version | ||
| 5213 | * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device) | ||
| 5214 | */ | ||
| 5215 | #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK) | ||
| 5216 | /*! @} */ | ||
| 5217 | |||
| 5218 | /*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */ | ||
| 5219 | /*! @{ */ | ||
| 5220 | #define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU) | ||
| 5221 | #define CAU_RADR_CAA_ACC_SHIFT (0U) | ||
| 5222 | #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK) | ||
| 5223 | /*! @} */ | ||
| 5224 | |||
| 5225 | /*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */ | ||
| 5226 | /*! @{ */ | ||
| 5227 | #define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU) | ||
| 5228 | #define CAU_RADR_CA_CA0_SHIFT (0U) | ||
| 5229 | #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK) | ||
| 5230 | #define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU) | ||
| 5231 | #define CAU_RADR_CA_CA1_SHIFT (0U) | ||
| 5232 | #define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK) | ||
| 5233 | #define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU) | ||
| 5234 | #define CAU_RADR_CA_CA2_SHIFT (0U) | ||
| 5235 | #define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK) | ||
| 5236 | #define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU) | ||
| 5237 | #define CAU_RADR_CA_CA3_SHIFT (0U) | ||
| 5238 | #define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK) | ||
| 5239 | #define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU) | ||
| 5240 | #define CAU_RADR_CA_CA4_SHIFT (0U) | ||
| 5241 | #define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK) | ||
| 5242 | #define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU) | ||
| 5243 | #define CAU_RADR_CA_CA5_SHIFT (0U) | ||
| 5244 | #define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK) | ||
| 5245 | #define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU) | ||
| 5246 | #define CAU_RADR_CA_CA6_SHIFT (0U) | ||
| 5247 | #define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK) | ||
| 5248 | #define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU) | ||
| 5249 | #define CAU_RADR_CA_CA7_SHIFT (0U) | ||
| 5250 | #define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK) | ||
| 5251 | #define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU) | ||
| 5252 | #define CAU_RADR_CA_CA8_SHIFT (0U) | ||
| 5253 | #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK) | ||
| 5254 | /*! @} */ | ||
| 5255 | |||
| 5256 | /* The count of CAU_RADR_CA */ | ||
| 5257 | #define CAU_RADR_CA_COUNT (9U) | ||
| 5258 | |||
| 5259 | /*! @name XOR_CASR - Status register - Exclusive Or command */ | ||
| 5260 | /*! @{ */ | ||
| 5261 | #define CAU_XOR_CASR_IC_MASK (0x1U) | ||
| 5262 | #define CAU_XOR_CASR_IC_SHIFT (0U) | ||
| 5263 | /*! IC | ||
| 5264 | * 0b0..No illegal commands issued | ||
| 5265 | * 0b1..Illegal command issued | ||
| 5266 | */ | ||
| 5267 | #define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK) | ||
| 5268 | #define CAU_XOR_CASR_DPE_MASK (0x2U) | ||
| 5269 | #define CAU_XOR_CASR_DPE_SHIFT (1U) | ||
| 5270 | /*! DPE | ||
| 5271 | * 0b0..No error detected | ||
| 5272 | * 0b1..DES key parity error detected | ||
| 5273 | */ | ||
| 5274 | #define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK) | ||
| 5275 | #define CAU_XOR_CASR_VER_MASK (0xF0000000U) | ||
| 5276 | #define CAU_XOR_CASR_VER_SHIFT (28U) | ||
| 5277 | /*! VER - CAU version | ||
| 5278 | * 0b0001..Initial CAU version | ||
| 5279 | * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device) | ||
| 5280 | */ | ||
| 5281 | #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK) | ||
| 5282 | /*! @} */ | ||
| 5283 | |||
| 5284 | /*! @name XOR_CAA - Accumulator register - Exclusive Or command */ | ||
| 5285 | /*! @{ */ | ||
| 5286 | #define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU) | ||
| 5287 | #define CAU_XOR_CAA_ACC_SHIFT (0U) | ||
| 5288 | #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK) | ||
| 5289 | /*! @} */ | ||
| 5290 | |||
| 5291 | /*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */ | ||
| 5292 | /*! @{ */ | ||
| 5293 | #define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU) | ||
| 5294 | #define CAU_XOR_CA_CA0_SHIFT (0U) | ||
| 5295 | #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK) | ||
| 5296 | #define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU) | ||
| 5297 | #define CAU_XOR_CA_CA1_SHIFT (0U) | ||
| 5298 | #define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK) | ||
| 5299 | #define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU) | ||
| 5300 | #define CAU_XOR_CA_CA2_SHIFT (0U) | ||
| 5301 | #define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK) | ||
| 5302 | #define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU) | ||
| 5303 | #define CAU_XOR_CA_CA3_SHIFT (0U) | ||
| 5304 | #define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK) | ||
| 5305 | #define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU) | ||
| 5306 | #define CAU_XOR_CA_CA4_SHIFT (0U) | ||
| 5307 | #define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK) | ||
| 5308 | #define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU) | ||
| 5309 | #define CAU_XOR_CA_CA5_SHIFT (0U) | ||
| 5310 | #define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK) | ||
| 5311 | #define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU) | ||
| 5312 | #define CAU_XOR_CA_CA6_SHIFT (0U) | ||
| 5313 | #define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK) | ||
| 5314 | #define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU) | ||
| 5315 | #define CAU_XOR_CA_CA7_SHIFT (0U) | ||
| 5316 | #define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK) | ||
| 5317 | #define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU) | ||
| 5318 | #define CAU_XOR_CA_CA8_SHIFT (0U) | ||
| 5319 | #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK) | ||
| 5320 | /*! @} */ | ||
| 5321 | |||
| 5322 | /* The count of CAU_XOR_CA */ | ||
| 5323 | #define CAU_XOR_CA_COUNT (9U) | ||
| 5324 | |||
| 5325 | /*! @name ROTL_CASR - Status register - Rotate Left command */ | ||
| 5326 | /*! @{ */ | ||
| 5327 | #define CAU_ROTL_CASR_IC_MASK (0x1U) | ||
| 5328 | #define CAU_ROTL_CASR_IC_SHIFT (0U) | ||
| 5329 | /*! IC | ||
| 5330 | * 0b0..No illegal commands issued | ||
| 5331 | * 0b1..Illegal command issued | ||
| 5332 | */ | ||
| 5333 | #define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK) | ||
| 5334 | #define CAU_ROTL_CASR_DPE_MASK (0x2U) | ||
| 5335 | #define CAU_ROTL_CASR_DPE_SHIFT (1U) | ||
| 5336 | /*! DPE | ||
| 5337 | * 0b0..No error detected | ||
| 5338 | * 0b1..DES key parity error detected | ||
| 5339 | */ | ||
| 5340 | #define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK) | ||
| 5341 | #define CAU_ROTL_CASR_VER_MASK (0xF0000000U) | ||
| 5342 | #define CAU_ROTL_CASR_VER_SHIFT (28U) | ||
| 5343 | /*! VER - CAU version | ||
| 5344 | * 0b0001..Initial CAU version | ||
| 5345 | * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device) | ||
| 5346 | */ | ||
| 5347 | #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK) | ||
| 5348 | /*! @} */ | ||
| 5349 | |||
| 5350 | /*! @name ROTL_CAA - Accumulator register - Rotate Left command */ | ||
| 5351 | /*! @{ */ | ||
| 5352 | #define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU) | ||
| 5353 | #define CAU_ROTL_CAA_ACC_SHIFT (0U) | ||
| 5354 | #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK) | ||
| 5355 | /*! @} */ | ||
| 5356 | |||
| 5357 | /*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */ | ||
| 5358 | /*! @{ */ | ||
| 5359 | #define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU) | ||
| 5360 | #define CAU_ROTL_CA_CA0_SHIFT (0U) | ||
| 5361 | #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK) | ||
| 5362 | #define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU) | ||
| 5363 | #define CAU_ROTL_CA_CA1_SHIFT (0U) | ||
| 5364 | #define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK) | ||
| 5365 | #define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU) | ||
| 5366 | #define CAU_ROTL_CA_CA2_SHIFT (0U) | ||
| 5367 | #define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK) | ||
| 5368 | #define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU) | ||
| 5369 | #define CAU_ROTL_CA_CA3_SHIFT (0U) | ||
| 5370 | #define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK) | ||
| 5371 | #define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU) | ||
| 5372 | #define CAU_ROTL_CA_CA4_SHIFT (0U) | ||
| 5373 | #define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK) | ||
| 5374 | #define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU) | ||
| 5375 | #define CAU_ROTL_CA_CA5_SHIFT (0U) | ||
| 5376 | #define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK) | ||
| 5377 | #define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU) | ||
| 5378 | #define CAU_ROTL_CA_CA6_SHIFT (0U) | ||
| 5379 | #define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK) | ||
| 5380 | #define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU) | ||
| 5381 | #define CAU_ROTL_CA_CA7_SHIFT (0U) | ||
| 5382 | #define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK) | ||
| 5383 | #define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU) | ||
| 5384 | #define CAU_ROTL_CA_CA8_SHIFT (0U) | ||
| 5385 | #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK) | ||
| 5386 | /*! @} */ | ||
| 5387 | |||
| 5388 | /* The count of CAU_ROTL_CA */ | ||
| 5389 | #define CAU_ROTL_CA_COUNT (9U) | ||
| 5390 | |||
| 5391 | /*! @name AESC_CASR - Status register - AES Column Operation command */ | ||
| 5392 | /*! @{ */ | ||
| 5393 | #define CAU_AESC_CASR_IC_MASK (0x1U) | ||
| 5394 | #define CAU_AESC_CASR_IC_SHIFT (0U) | ||
| 5395 | /*! IC | ||
| 5396 | * 0b0..No illegal commands issued | ||
| 5397 | * 0b1..Illegal command issued | ||
| 5398 | */ | ||
| 5399 | #define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK) | ||
| 5400 | #define CAU_AESC_CASR_DPE_MASK (0x2U) | ||
| 5401 | #define CAU_AESC_CASR_DPE_SHIFT (1U) | ||
| 5402 | /*! DPE | ||
| 5403 | * 0b0..No error detected | ||
| 5404 | * 0b1..DES key parity error detected | ||
| 5405 | */ | ||
| 5406 | #define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK) | ||
| 5407 | #define CAU_AESC_CASR_VER_MASK (0xF0000000U) | ||
| 5408 | #define CAU_AESC_CASR_VER_SHIFT (28U) | ||
| 5409 | /*! VER - CAU version | ||
| 5410 | * 0b0001..Initial CAU version | ||
| 5411 | * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device) | ||
| 5412 | */ | ||
| 5413 | #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK) | ||
| 5414 | /*! @} */ | ||
| 5415 | |||
| 5416 | /*! @name AESC_CAA - Accumulator register - AES Column Operation command */ | ||
| 5417 | /*! @{ */ | ||
| 5418 | #define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU) | ||
| 5419 | #define CAU_AESC_CAA_ACC_SHIFT (0U) | ||
| 5420 | #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK) | ||
| 5421 | /*! @} */ | ||
| 5422 | |||
| 5423 | /*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */ | ||
| 5424 | /*! @{ */ | ||
| 5425 | #define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU) | ||
| 5426 | #define CAU_AESC_CA_CA0_SHIFT (0U) | ||
| 5427 | #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK) | ||
| 5428 | #define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU) | ||
| 5429 | #define CAU_AESC_CA_CA1_SHIFT (0U) | ||
| 5430 | #define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK) | ||
| 5431 | #define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU) | ||
| 5432 | #define CAU_AESC_CA_CA2_SHIFT (0U) | ||
| 5433 | #define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK) | ||
| 5434 | #define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU) | ||
| 5435 | #define CAU_AESC_CA_CA3_SHIFT (0U) | ||
| 5436 | #define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK) | ||
| 5437 | #define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU) | ||
| 5438 | #define CAU_AESC_CA_CA4_SHIFT (0U) | ||
| 5439 | #define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK) | ||
| 5440 | #define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU) | ||
| 5441 | #define CAU_AESC_CA_CA5_SHIFT (0U) | ||
| 5442 | #define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK) | ||
| 5443 | #define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU) | ||
| 5444 | #define CAU_AESC_CA_CA6_SHIFT (0U) | ||
| 5445 | #define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK) | ||
| 5446 | #define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU) | ||
| 5447 | #define CAU_AESC_CA_CA7_SHIFT (0U) | ||
| 5448 | #define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK) | ||
| 5449 | #define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU) | ||
| 5450 | #define CAU_AESC_CA_CA8_SHIFT (0U) | ||
| 5451 | #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK) | ||
| 5452 | /*! @} */ | ||
| 5453 | |||
| 5454 | /* The count of CAU_AESC_CA */ | ||
| 5455 | #define CAU_AESC_CA_COUNT (9U) | ||
| 5456 | |||
| 5457 | /*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */ | ||
| 5458 | /*! @{ */ | ||
| 5459 | #define CAU_AESIC_CASR_IC_MASK (0x1U) | ||
| 5460 | #define CAU_AESIC_CASR_IC_SHIFT (0U) | ||
| 5461 | /*! IC | ||
| 5462 | * 0b0..No illegal commands issued | ||
| 5463 | * 0b1..Illegal command issued | ||
| 5464 | */ | ||
| 5465 | #define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK) | ||
| 5466 | #define CAU_AESIC_CASR_DPE_MASK (0x2U) | ||
| 5467 | #define CAU_AESIC_CASR_DPE_SHIFT (1U) | ||
| 5468 | /*! DPE | ||
| 5469 | * 0b0..No error detected | ||
| 5470 | * 0b1..DES key parity error detected | ||
| 5471 | */ | ||
| 5472 | #define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK) | ||
| 5473 | #define CAU_AESIC_CASR_VER_MASK (0xF0000000U) | ||
| 5474 | #define CAU_AESIC_CASR_VER_SHIFT (28U) | ||
| 5475 | /*! VER - CAU version | ||
| 5476 | * 0b0001..Initial CAU version | ||
| 5477 | * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device) | ||
| 5478 | */ | ||
| 5479 | #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK) | ||
| 5480 | /*! @} */ | ||
| 5481 | |||
| 5482 | /*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */ | ||
| 5483 | /*! @{ */ | ||
| 5484 | #define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU) | ||
| 5485 | #define CAU_AESIC_CAA_ACC_SHIFT (0U) | ||
| 5486 | #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK) | ||
| 5487 | /*! @} */ | ||
| 5488 | |||
| 5489 | /*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */ | ||
| 5490 | /*! @{ */ | ||
| 5491 | #define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU) | ||
| 5492 | #define CAU_AESIC_CA_CA0_SHIFT (0U) | ||
| 5493 | #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK) | ||
| 5494 | #define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU) | ||
| 5495 | #define CAU_AESIC_CA_CA1_SHIFT (0U) | ||
| 5496 | #define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK) | ||
| 5497 | #define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU) | ||
| 5498 | #define CAU_AESIC_CA_CA2_SHIFT (0U) | ||
| 5499 | #define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK) | ||
| 5500 | #define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU) | ||
| 5501 | #define CAU_AESIC_CA_CA3_SHIFT (0U) | ||
| 5502 | #define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK) | ||
| 5503 | #define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU) | ||
| 5504 | #define CAU_AESIC_CA_CA4_SHIFT (0U) | ||
| 5505 | #define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK) | ||
| 5506 | #define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU) | ||
| 5507 | #define CAU_AESIC_CA_CA5_SHIFT (0U) | ||
| 5508 | #define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK) | ||
| 5509 | #define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU) | ||
| 5510 | #define CAU_AESIC_CA_CA6_SHIFT (0U) | ||
| 5511 | #define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK) | ||
| 5512 | #define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU) | ||
| 5513 | #define CAU_AESIC_CA_CA7_SHIFT (0U) | ||
| 5514 | #define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK) | ||
| 5515 | #define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU) | ||
| 5516 | #define CAU_AESIC_CA_CA8_SHIFT (0U) | ||
| 5517 | #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK) | ||
| 5518 | /*! @} */ | ||
| 5519 | |||
| 5520 | /* The count of CAU_AESIC_CA */ | ||
| 5521 | #define CAU_AESIC_CA_COUNT (9U) | ||
| 5522 | |||
| 5523 | |||
| 5524 | /*! | ||
| 5525 | * @} | ||
| 5526 | */ /* end of group CAU_Register_Masks */ | ||
| 5527 | |||
| 5528 | |||
| 5529 | /* CAU - Peripheral instance base addresses */ | ||
| 5530 | /** Peripheral CAU base address */ | ||
| 5531 | #define CAU_BASE (0xE0081000u) | ||
| 5532 | /** Peripheral CAU base pointer */ | ||
| 5533 | #define CAU ((CAU_Type *)CAU_BASE) | ||
| 5534 | /** Array initializer of CAU peripheral base addresses */ | ||
| 5535 | #define CAU_BASE_ADDRS { CAU_BASE } | ||
| 5536 | /** Array initializer of CAU peripheral base pointers */ | ||
| 5537 | #define CAU_BASE_PTRS { CAU } | ||
| 5538 | |||
| 5539 | /*! | ||
| 5540 | * @} | ||
| 5541 | */ /* end of group CAU_Peripheral_Access_Layer */ | ||
| 5542 | |||
| 5543 | |||
| 5544 | /* ---------------------------------------------------------------------------- | ||
| 5545 | -- CMP Peripheral Access Layer | ||
| 5546 | ---------------------------------------------------------------------------- */ | ||
| 5547 | |||
| 5548 | /*! | ||
| 5549 | * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer | ||
| 5550 | * @{ | ||
| 5551 | */ | ||
| 5552 | |||
| 5553 | /** CMP - Register Layout Typedef */ | ||
| 5554 | typedef struct { | ||
| 5555 | __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ | ||
| 5556 | __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ | ||
| 5557 | __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ | ||
| 5558 | __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ | ||
| 5559 | __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ | ||
| 5560 | __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ | ||
| 5561 | } CMP_Type; | ||
| 5562 | |||
| 5563 | /* ---------------------------------------------------------------------------- | ||
| 5564 | -- CMP Register Masks | ||
| 5565 | ---------------------------------------------------------------------------- */ | ||
| 5566 | |||
| 5567 | /*! | ||
| 5568 | * @addtogroup CMP_Register_Masks CMP Register Masks | ||
| 5569 | * @{ | ||
| 5570 | */ | ||
| 5571 | |||
| 5572 | /*! @name CR0 - CMP Control Register 0 */ | ||
| 5573 | /*! @{ */ | ||
| 5574 | #define CMP_CR0_HYSTCTR_MASK (0x3U) | ||
| 5575 | #define CMP_CR0_HYSTCTR_SHIFT (0U) | ||
| 5576 | /*! HYSTCTR - Comparator hard block hysteresis control | ||
| 5577 | * 0b00..Level 0 | ||
| 5578 | * 0b01..Level 1 | ||
| 5579 | * 0b10..Level 2 | ||
| 5580 | * 0b11..Level 3 | ||
| 5581 | */ | ||
| 5582 | #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) | ||
| 5583 | #define CMP_CR0_FILTER_CNT_MASK (0x70U) | ||
| 5584 | #define CMP_CR0_FILTER_CNT_SHIFT (4U) | ||
| 5585 | /*! FILTER_CNT - Filter Sample Count | ||
| 5586 | * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. | ||
| 5587 | * 0b001..One sample must agree. The comparator output is simply sampled. | ||
| 5588 | * 0b010..2 consecutive samples must agree. | ||
| 5589 | * 0b011..3 consecutive samples must agree. | ||
| 5590 | * 0b100..4 consecutive samples must agree. | ||
| 5591 | * 0b101..5 consecutive samples must agree. | ||
| 5592 | * 0b110..6 consecutive samples must agree. | ||
| 5593 | * 0b111..7 consecutive samples must agree. | ||
| 5594 | */ | ||
| 5595 | #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) | ||
| 5596 | /*! @} */ | ||
| 5597 | |||
| 5598 | /*! @name CR1 - CMP Control Register 1 */ | ||
| 5599 | /*! @{ */ | ||
| 5600 | #define CMP_CR1_EN_MASK (0x1U) | ||
| 5601 | #define CMP_CR1_EN_SHIFT (0U) | ||
| 5602 | /*! EN - Comparator Module Enable | ||
| 5603 | * 0b0..Analog Comparator is disabled. | ||
| 5604 | * 0b1..Analog Comparator is enabled. | ||
| 5605 | */ | ||
| 5606 | #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) | ||
| 5607 | #define CMP_CR1_OPE_MASK (0x2U) | ||
| 5608 | #define CMP_CR1_OPE_SHIFT (1U) | ||
| 5609 | /*! OPE - Comparator Output Pin Enable | ||
| 5610 | * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. | ||
| 5611 | * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. | ||
| 5612 | */ | ||
| 5613 | #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) | ||
| 5614 | #define CMP_CR1_COS_MASK (0x4U) | ||
| 5615 | #define CMP_CR1_COS_SHIFT (2U) | ||
| 5616 | /*! COS - Comparator Output Select | ||
| 5617 | * 0b0..Set the filtered comparator output (CMPO) to equal COUT. | ||
| 5618 | * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA. | ||
| 5619 | */ | ||
| 5620 | #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) | ||
| 5621 | #define CMP_CR1_INV_MASK (0x8U) | ||
| 5622 | #define CMP_CR1_INV_SHIFT (3U) | ||
| 5623 | /*! INV - Comparator INVERT | ||
| 5624 | * 0b0..Does not invert the comparator output. | ||
| 5625 | * 0b1..Inverts the comparator output. | ||
| 5626 | */ | ||
| 5627 | #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) | ||
| 5628 | #define CMP_CR1_PMODE_MASK (0x10U) | ||
| 5629 | #define CMP_CR1_PMODE_SHIFT (4U) | ||
| 5630 | /*! PMODE - Power Mode Select | ||
| 5631 | * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. | ||
| 5632 | * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. | ||
| 5633 | */ | ||
| 5634 | #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) | ||
| 5635 | #define CMP_CR1_WE_MASK (0x40U) | ||
| 5636 | #define CMP_CR1_WE_SHIFT (6U) | ||
| 5637 | /*! WE - Windowing Enable | ||
| 5638 | * 0b0..Windowing mode is not selected. | ||
| 5639 | * 0b1..Windowing mode is selected. | ||
| 5640 | */ | ||
| 5641 | #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) | ||
| 5642 | #define CMP_CR1_SE_MASK (0x80U) | ||
| 5643 | #define CMP_CR1_SE_SHIFT (7U) | ||
| 5644 | /*! SE - Sample Enable | ||
| 5645 | * 0b0..Sampling mode is not selected. | ||
| 5646 | * 0b1..Sampling mode is selected. | ||
| 5647 | */ | ||
| 5648 | #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) | ||
| 5649 | /*! @} */ | ||
| 5650 | |||
| 5651 | /*! @name FPR - CMP Filter Period Register */ | ||
| 5652 | /*! @{ */ | ||
| 5653 | #define CMP_FPR_FILT_PER_MASK (0xFFU) | ||
| 5654 | #define CMP_FPR_FILT_PER_SHIFT (0U) | ||
| 5655 | #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) | ||
| 5656 | /*! @} */ | ||
| 5657 | |||
| 5658 | /*! @name SCR - CMP Status and Control Register */ | ||
| 5659 | /*! @{ */ | ||
| 5660 | #define CMP_SCR_COUT_MASK (0x1U) | ||
| 5661 | #define CMP_SCR_COUT_SHIFT (0U) | ||
| 5662 | #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) | ||
| 5663 | #define CMP_SCR_CFF_MASK (0x2U) | ||
| 5664 | #define CMP_SCR_CFF_SHIFT (1U) | ||
| 5665 | /*! CFF - Analog Comparator Flag Falling | ||
| 5666 | * 0b0..Falling-edge on COUT has not been detected. | ||
| 5667 | * 0b1..Falling-edge on COUT has occurred. | ||
| 5668 | */ | ||
| 5669 | #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) | ||
| 5670 | #define CMP_SCR_CFR_MASK (0x4U) | ||
| 5671 | #define CMP_SCR_CFR_SHIFT (2U) | ||
| 5672 | /*! CFR - Analog Comparator Flag Rising | ||
| 5673 | * 0b0..Rising-edge on COUT has not been detected. | ||
| 5674 | * 0b1..Rising-edge on COUT has occurred. | ||
| 5675 | */ | ||
| 5676 | #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) | ||
| 5677 | #define CMP_SCR_IEF_MASK (0x8U) | ||
| 5678 | #define CMP_SCR_IEF_SHIFT (3U) | ||
| 5679 | /*! IEF - Comparator Interrupt Enable Falling | ||
| 5680 | * 0b0..Interrupt is disabled. | ||
| 5681 | * 0b1..Interrupt is enabled. | ||
| 5682 | */ | ||
| 5683 | #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) | ||
| 5684 | #define CMP_SCR_IER_MASK (0x10U) | ||
| 5685 | #define CMP_SCR_IER_SHIFT (4U) | ||
| 5686 | /*! IER - Comparator Interrupt Enable Rising | ||
| 5687 | * 0b0..Interrupt is disabled. | ||
| 5688 | * 0b1..Interrupt is enabled. | ||
| 5689 | */ | ||
| 5690 | #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) | ||
| 5691 | #define CMP_SCR_DMAEN_MASK (0x40U) | ||
| 5692 | #define CMP_SCR_DMAEN_SHIFT (6U) | ||
| 5693 | /*! DMAEN - DMA Enable Control | ||
| 5694 | * 0b0..DMA is disabled. | ||
| 5695 | * 0b1..DMA is enabled. | ||
| 5696 | */ | ||
| 5697 | #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) | ||
| 5698 | /*! @} */ | ||
| 5699 | |||
| 5700 | /*! @name DACCR - DAC Control Register */ | ||
| 5701 | /*! @{ */ | ||
| 5702 | #define CMP_DACCR_VOSEL_MASK (0x3FU) | ||
| 5703 | #define CMP_DACCR_VOSEL_SHIFT (0U) | ||
| 5704 | #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) | ||
| 5705 | #define CMP_DACCR_VRSEL_MASK (0x40U) | ||
| 5706 | #define CMP_DACCR_VRSEL_SHIFT (6U) | ||
| 5707 | /*! VRSEL - Supply Voltage Reference Source Select | ||
| 5708 | * 0b0..V is selected as resistor ladder network supply reference V. in1 in | ||
| 5709 | * 0b1..V is selected as resistor ladder network supply reference V. in2 in | ||
| 5710 | */ | ||
| 5711 | #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) | ||
| 5712 | #define CMP_DACCR_DACEN_MASK (0x80U) | ||
| 5713 | #define CMP_DACCR_DACEN_SHIFT (7U) | ||
| 5714 | /*! DACEN - DAC Enable | ||
| 5715 | * 0b0..DAC is disabled. | ||
| 5716 | * 0b1..DAC is enabled. | ||
| 5717 | */ | ||
| 5718 | #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) | ||
| 5719 | /*! @} */ | ||
| 5720 | |||
| 5721 | /*! @name MUXCR - MUX Control Register */ | ||
| 5722 | /*! @{ */ | ||
| 5723 | #define CMP_MUXCR_MSEL_MASK (0x7U) | ||
| 5724 | #define CMP_MUXCR_MSEL_SHIFT (0U) | ||
| 5725 | /*! MSEL - Minus Input Mux Control | ||
| 5726 | * 0b000..IN0 | ||
| 5727 | * 0b001..IN1 | ||
| 5728 | * 0b010..IN2 | ||
| 5729 | * 0b011..IN3 | ||
| 5730 | * 0b100..IN4 | ||
| 5731 | * 0b101..IN5 | ||
| 5732 | * 0b110..IN6 | ||
| 5733 | * 0b111..IN7 | ||
| 5734 | */ | ||
| 5735 | #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) | ||
| 5736 | #define CMP_MUXCR_PSEL_MASK (0x38U) | ||
| 5737 | #define CMP_MUXCR_PSEL_SHIFT (3U) | ||
| 5738 | /*! PSEL - Plus Input Mux Control | ||
| 5739 | * 0b000..IN0 | ||
| 5740 | * 0b001..IN1 | ||
| 5741 | * 0b010..IN2 | ||
| 5742 | * 0b011..IN3 | ||
| 5743 | * 0b100..IN4 | ||
| 5744 | * 0b101..IN5 | ||
| 5745 | * 0b110..IN6 | ||
| 5746 | * 0b111..IN7 | ||
| 5747 | */ | ||
| 5748 | #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) | ||
| 5749 | #define CMP_MUXCR_PSTM_MASK (0x80U) | ||
| 5750 | #define CMP_MUXCR_PSTM_SHIFT (7U) | ||
| 5751 | /*! PSTM - Pass Through Mode Enable | ||
| 5752 | * 0b0..Pass Through Mode is disabled. | ||
| 5753 | * 0b1..Pass Through Mode is enabled. | ||
| 5754 | */ | ||
| 5755 | #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK) | ||
| 5756 | /*! @} */ | ||
| 5757 | |||
| 5758 | |||
| 5759 | /*! | ||
| 5760 | * @} | ||
| 5761 | */ /* end of group CMP_Register_Masks */ | ||
| 5762 | |||
| 5763 | |||
| 5764 | /* CMP - Peripheral instance base addresses */ | ||
| 5765 | /** Peripheral CMP0 base address */ | ||
| 5766 | #define CMP0_BASE (0x40073000u) | ||
| 5767 | /** Peripheral CMP0 base pointer */ | ||
| 5768 | #define CMP0 ((CMP_Type *)CMP0_BASE) | ||
| 5769 | /** Peripheral CMP1 base address */ | ||
| 5770 | #define CMP1_BASE (0x40073008u) | ||
| 5771 | /** Peripheral CMP1 base pointer */ | ||
| 5772 | #define CMP1 ((CMP_Type *)CMP1_BASE) | ||
| 5773 | /** Peripheral CMP2 base address */ | ||
| 5774 | #define CMP2_BASE (0x40073010u) | ||
| 5775 | /** Peripheral CMP2 base pointer */ | ||
| 5776 | #define CMP2 ((CMP_Type *)CMP2_BASE) | ||
| 5777 | /** Array initializer of CMP peripheral base addresses */ | ||
| 5778 | #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } | ||
| 5779 | /** Array initializer of CMP peripheral base pointers */ | ||
| 5780 | #define CMP_BASE_PTRS { CMP0, CMP1, CMP2 } | ||
| 5781 | /** Interrupt vectors for the CMP peripheral type */ | ||
| 5782 | #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn } | ||
| 5783 | |||
| 5784 | /*! | ||
| 5785 | * @} | ||
| 5786 | */ /* end of group CMP_Peripheral_Access_Layer */ | ||
| 5787 | |||
| 5788 | |||
| 5789 | /* ---------------------------------------------------------------------------- | ||
| 5790 | -- CMT Peripheral Access Layer | ||
| 5791 | ---------------------------------------------------------------------------- */ | ||
| 5792 | |||
| 5793 | /*! | ||
| 5794 | * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer | ||
| 5795 | * @{ | ||
| 5796 | */ | ||
| 5797 | |||
| 5798 | /** CMT - Register Layout Typedef */ | ||
| 5799 | typedef struct { | ||
| 5800 | __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */ | ||
| 5801 | __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */ | ||
| 5802 | __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */ | ||
| 5803 | __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */ | ||
| 5804 | __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */ | ||
| 5805 | __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */ | ||
| 5806 | __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */ | ||
| 5807 | __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */ | ||
| 5808 | __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */ | ||
| 5809 | __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */ | ||
| 5810 | __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */ | ||
| 5811 | __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */ | ||
| 5812 | } CMT_Type; | ||
| 5813 | |||
| 5814 | /* ---------------------------------------------------------------------------- | ||
| 5815 | -- CMT Register Masks | ||
| 5816 | ---------------------------------------------------------------------------- */ | ||
| 5817 | |||
| 5818 | /*! | ||
| 5819 | * @addtogroup CMT_Register_Masks CMT Register Masks | ||
| 5820 | * @{ | ||
| 5821 | */ | ||
| 5822 | |||
| 5823 | /*! @name CGH1 - CMT Carrier Generator High Data Register 1 */ | ||
| 5824 | /*! @{ */ | ||
| 5825 | #define CMT_CGH1_PH_MASK (0xFFU) | ||
| 5826 | #define CMT_CGH1_PH_SHIFT (0U) | ||
| 5827 | #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK) | ||
| 5828 | /*! @} */ | ||
| 5829 | |||
| 5830 | /*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */ | ||
| 5831 | /*! @{ */ | ||
| 5832 | #define CMT_CGL1_PL_MASK (0xFFU) | ||
| 5833 | #define CMT_CGL1_PL_SHIFT (0U) | ||
| 5834 | #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK) | ||
| 5835 | /*! @} */ | ||
| 5836 | |||
| 5837 | /*! @name CGH2 - CMT Carrier Generator High Data Register 2 */ | ||
| 5838 | /*! @{ */ | ||
| 5839 | #define CMT_CGH2_SH_MASK (0xFFU) | ||
| 5840 | #define CMT_CGH2_SH_SHIFT (0U) | ||
| 5841 | #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK) | ||
| 5842 | /*! @} */ | ||
| 5843 | |||
| 5844 | /*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */ | ||
| 5845 | /*! @{ */ | ||
| 5846 | #define CMT_CGL2_SL_MASK (0xFFU) | ||
| 5847 | #define CMT_CGL2_SL_SHIFT (0U) | ||
| 5848 | #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK) | ||
| 5849 | /*! @} */ | ||
| 5850 | |||
| 5851 | /*! @name OC - CMT Output Control Register */ | ||
| 5852 | /*! @{ */ | ||
| 5853 | #define CMT_OC_IROPEN_MASK (0x20U) | ||
| 5854 | #define CMT_OC_IROPEN_SHIFT (5U) | ||
| 5855 | /*! IROPEN - IRO Pin Enable | ||
| 5856 | * 0b0..The IRO signal is disabled. | ||
| 5857 | * 0b1..The IRO signal is enabled as output. | ||
| 5858 | */ | ||
| 5859 | #define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK) | ||
| 5860 | #define CMT_OC_CMTPOL_MASK (0x40U) | ||
| 5861 | #define CMT_OC_CMTPOL_SHIFT (6U) | ||
| 5862 | /*! CMTPOL - CMT Output Polarity | ||
| 5863 | * 0b0..The IRO signal is active-low. | ||
| 5864 | * 0b1..The IRO signal is active-high. | ||
| 5865 | */ | ||
| 5866 | #define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK) | ||
| 5867 | #define CMT_OC_IROL_MASK (0x80U) | ||
| 5868 | #define CMT_OC_IROL_SHIFT (7U) | ||
| 5869 | #define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK) | ||
| 5870 | /*! @} */ | ||
| 5871 | |||
| 5872 | /*! @name MSC - CMT Modulator Status and Control Register */ | ||
| 5873 | /*! @{ */ | ||
| 5874 | #define CMT_MSC_MCGEN_MASK (0x1U) | ||
| 5875 | #define CMT_MSC_MCGEN_SHIFT (0U) | ||
| 5876 | /*! MCGEN - Modulator and Carrier Generator Enable | ||
| 5877 | * 0b0..Modulator and carrier generator disabled | ||
| 5878 | * 0b1..Modulator and carrier generator enabled | ||
| 5879 | */ | ||
| 5880 | #define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK) | ||
| 5881 | #define CMT_MSC_EOCIE_MASK (0x2U) | ||
| 5882 | #define CMT_MSC_EOCIE_SHIFT (1U) | ||
| 5883 | /*! EOCIE - End of Cycle Interrupt Enable | ||
| 5884 | * 0b0..CPU interrupt is disabled. | ||
| 5885 | * 0b1..CPU interrupt is enabled. | ||
| 5886 | */ | ||
| 5887 | #define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK) | ||
| 5888 | #define CMT_MSC_FSK_MASK (0x4U) | ||
| 5889 | #define CMT_MSC_FSK_SHIFT (2U) | ||
| 5890 | /*! FSK - FSK Mode Select | ||
| 5891 | * 0b0..The CMT operates in Time or Baseband mode. | ||
| 5892 | * 0b1..The CMT operates in FSK mode. | ||
| 5893 | */ | ||
| 5894 | #define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK) | ||
| 5895 | #define CMT_MSC_BASE_MASK (0x8U) | ||
| 5896 | #define CMT_MSC_BASE_SHIFT (3U) | ||
| 5897 | /*! BASE - Baseband Enable | ||
| 5898 | * 0b0..Baseband mode is disabled. | ||
| 5899 | * 0b1..Baseband mode is enabled. | ||
| 5900 | */ | ||
| 5901 | #define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK) | ||
| 5902 | #define CMT_MSC_EXSPC_MASK (0x10U) | ||
| 5903 | #define CMT_MSC_EXSPC_SHIFT (4U) | ||
| 5904 | /*! EXSPC - Extended Space Enable | ||
| 5905 | * 0b0..Extended space is disabled. | ||
| 5906 | * 0b1..Extended space is enabled. | ||
| 5907 | */ | ||
| 5908 | #define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK) | ||
| 5909 | #define CMT_MSC_CMTDIV_MASK (0x60U) | ||
| 5910 | #define CMT_MSC_CMTDIV_SHIFT (5U) | ||
| 5911 | /*! CMTDIV - CMT Clock Divide Prescaler | ||
| 5912 | * 0b00..IF * 1 | ||
| 5913 | * 0b01..IF * 2 | ||
| 5914 | * 0b10..IF * 4 | ||
| 5915 | * 0b11..IF * 8 | ||
| 5916 | */ | ||
| 5917 | #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK) | ||
| 5918 | #define CMT_MSC_EOCF_MASK (0x80U) | ||
| 5919 | #define CMT_MSC_EOCF_SHIFT (7U) | ||
| 5920 | /*! EOCF - End Of Cycle Status Flag | ||
| 5921 | * 0b0..End of modulation cycle has not occured since the flag last cleared. | ||
| 5922 | * 0b1..End of modulator cycle has occurred. | ||
| 5923 | */ | ||
| 5924 | #define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK) | ||
| 5925 | /*! @} */ | ||
| 5926 | |||
| 5927 | /*! @name CMD1 - CMT Modulator Data Register Mark High */ | ||
| 5928 | /*! @{ */ | ||
| 5929 | #define CMT_CMD1_MB_MASK (0xFFU) | ||
| 5930 | #define CMT_CMD1_MB_SHIFT (0U) | ||
| 5931 | #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK) | ||
| 5932 | /*! @} */ | ||
| 5933 | |||
| 5934 | /*! @name CMD2 - CMT Modulator Data Register Mark Low */ | ||
| 5935 | /*! @{ */ | ||
| 5936 | #define CMT_CMD2_MB_MASK (0xFFU) | ||
| 5937 | #define CMT_CMD2_MB_SHIFT (0U) | ||
| 5938 | #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK) | ||
| 5939 | /*! @} */ | ||
| 5940 | |||
| 5941 | /*! @name CMD3 - CMT Modulator Data Register Space High */ | ||
| 5942 | /*! @{ */ | ||
| 5943 | #define CMT_CMD3_SB_MASK (0xFFU) | ||
| 5944 | #define CMT_CMD3_SB_SHIFT (0U) | ||
| 5945 | #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK) | ||
| 5946 | /*! @} */ | ||
| 5947 | |||
| 5948 | /*! @name CMD4 - CMT Modulator Data Register Space Low */ | ||
| 5949 | /*! @{ */ | ||
| 5950 | #define CMT_CMD4_SB_MASK (0xFFU) | ||
| 5951 | #define CMT_CMD4_SB_SHIFT (0U) | ||
| 5952 | #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK) | ||
| 5953 | /*! @} */ | ||
| 5954 | |||
| 5955 | /*! @name PPS - CMT Primary Prescaler Register */ | ||
| 5956 | /*! @{ */ | ||
| 5957 | #define CMT_PPS_PPSDIV_MASK (0xFU) | ||
| 5958 | #define CMT_PPS_PPSDIV_SHIFT (0U) | ||
| 5959 | /*! PPSDIV - Primary Prescaler Divider | ||
| 5960 | * 0b0000..Bus clock * 1 | ||
| 5961 | * 0b0001..Bus clock * 2 | ||
| 5962 | * 0b0010..Bus clock * 3 | ||
| 5963 | * 0b0011..Bus clock * 4 | ||
| 5964 | * 0b0100..Bus clock * 5 | ||
| 5965 | * 0b0101..Bus clock * 6 | ||
| 5966 | * 0b0110..Bus clock * 7 | ||
| 5967 | * 0b0111..Bus clock * 8 | ||
| 5968 | * 0b1000..Bus clock * 9 | ||
| 5969 | * 0b1001..Bus clock * 10 | ||
| 5970 | * 0b1010..Bus clock * 11 | ||
| 5971 | * 0b1011..Bus clock * 12 | ||
| 5972 | * 0b1100..Bus clock * 13 | ||
| 5973 | * 0b1101..Bus clock * 14 | ||
| 5974 | * 0b1110..Bus clock * 15 | ||
| 5975 | * 0b1111..Bus clock * 16 | ||
| 5976 | */ | ||
| 5977 | #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK) | ||
| 5978 | /*! @} */ | ||
| 5979 | |||
| 5980 | /*! @name DMA - CMT Direct Memory Access Register */ | ||
| 5981 | /*! @{ */ | ||
| 5982 | #define CMT_DMA_DMA_MASK (0x1U) | ||
| 5983 | #define CMT_DMA_DMA_SHIFT (0U) | ||
| 5984 | /*! DMA - DMA Enable | ||
| 5985 | * 0b0..DMA transfer request and done are disabled. | ||
| 5986 | * 0b1..DMA transfer request and done are enabled. | ||
| 5987 | */ | ||
| 5988 | #define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK) | ||
| 5989 | /*! @} */ | ||
| 5990 | |||
| 5991 | |||
| 5992 | /*! | ||
| 5993 | * @} | ||
| 5994 | */ /* end of group CMT_Register_Masks */ | ||
| 5995 | |||
| 5996 | |||
| 5997 | /* CMT - Peripheral instance base addresses */ | ||
| 5998 | /** Peripheral CMT base address */ | ||
| 5999 | #define CMT_BASE (0x40062000u) | ||
| 6000 | /** Peripheral CMT base pointer */ | ||
| 6001 | #define CMT ((CMT_Type *)CMT_BASE) | ||
| 6002 | /** Array initializer of CMT peripheral base addresses */ | ||
| 6003 | #define CMT_BASE_ADDRS { CMT_BASE } | ||
| 6004 | /** Array initializer of CMT peripheral base pointers */ | ||
| 6005 | #define CMT_BASE_PTRS { CMT } | ||
| 6006 | /** Interrupt vectors for the CMT peripheral type */ | ||
| 6007 | #define CMT_IRQS { CMT_IRQn } | ||
| 6008 | |||
| 6009 | /*! | ||
| 6010 | * @} | ||
| 6011 | */ /* end of group CMT_Peripheral_Access_Layer */ | ||
| 6012 | |||
| 6013 | |||
| 6014 | /* ---------------------------------------------------------------------------- | ||
| 6015 | -- CRC Peripheral Access Layer | ||
| 6016 | ---------------------------------------------------------------------------- */ | ||
| 6017 | |||
| 6018 | /*! | ||
| 6019 | * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer | ||
| 6020 | * @{ | ||
| 6021 | */ | ||
| 6022 | |||
| 6023 | /** CRC - Register Layout Typedef */ | ||
| 6024 | typedef struct { | ||
| 6025 | union { /* offset: 0x0 */ | ||
| 6026 | struct { /* offset: 0x0 */ | ||
| 6027 | __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */ | ||
| 6028 | __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */ | ||
| 6029 | } ACCESS16BIT; | ||
| 6030 | __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ | ||
| 6031 | struct { /* offset: 0x0 */ | ||
| 6032 | __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */ | ||
| 6033 | __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */ | ||
| 6034 | __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */ | ||
| 6035 | __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */ | ||
| 6036 | } ACCESS8BIT; | ||
| 6037 | }; | ||
| 6038 | union { /* offset: 0x4 */ | ||
| 6039 | struct { /* offset: 0x4 */ | ||
| 6040 | __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ | ||
| 6041 | __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ | ||
| 6042 | } GPOLY_ACCESS16BIT; | ||
| 6043 | __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ | ||
| 6044 | struct { /* offset: 0x4 */ | ||
| 6045 | __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ | ||
| 6046 | __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ | ||
| 6047 | __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ | ||
| 6048 | __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ | ||
| 6049 | } GPOLY_ACCESS8BIT; | ||
| 6050 | }; | ||
| 6051 | union { /* offset: 0x8 */ | ||
| 6052 | __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ | ||
| 6053 | struct { /* offset: 0x8 */ | ||
| 6054 | uint8_t RESERVED_0[3]; | ||
| 6055 | __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ | ||
| 6056 | } CTRL_ACCESS8BIT; | ||
| 6057 | }; | ||
| 6058 | } CRC_Type; | ||
| 6059 | |||
| 6060 | /* ---------------------------------------------------------------------------- | ||
| 6061 | -- CRC Register Masks | ||
| 6062 | ---------------------------------------------------------------------------- */ | ||
| 6063 | |||
| 6064 | /*! | ||
| 6065 | * @addtogroup CRC_Register_Masks CRC Register Masks | ||
| 6066 | * @{ | ||
| 6067 | */ | ||
| 6068 | |||
| 6069 | /*! @name DATAL - CRC_DATAL register. */ | ||
| 6070 | /*! @{ */ | ||
| 6071 | #define CRC_DATAL_DATAL_MASK (0xFFFFU) | ||
| 6072 | #define CRC_DATAL_DATAL_SHIFT (0U) | ||
| 6073 | #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) | ||
| 6074 | /*! @} */ | ||
| 6075 | |||
| 6076 | /*! @name DATAH - CRC_DATAH register. */ | ||
| 6077 | /*! @{ */ | ||
| 6078 | #define CRC_DATAH_DATAH_MASK (0xFFFFU) | ||
| 6079 | #define CRC_DATAH_DATAH_SHIFT (0U) | ||
| 6080 | #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) | ||
| 6081 | /*! @} */ | ||
| 6082 | |||
| 6083 | /*! @name DATA - CRC Data register */ | ||
| 6084 | /*! @{ */ | ||
| 6085 | #define CRC_DATA_LL_MASK (0xFFU) | ||
| 6086 | #define CRC_DATA_LL_SHIFT (0U) | ||
| 6087 | #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) | ||
| 6088 | #define CRC_DATA_LU_MASK (0xFF00U) | ||
| 6089 | #define CRC_DATA_LU_SHIFT (8U) | ||
| 6090 | #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) | ||
| 6091 | #define CRC_DATA_HL_MASK (0xFF0000U) | ||
| 6092 | #define CRC_DATA_HL_SHIFT (16U) | ||
| 6093 | #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) | ||
| 6094 | #define CRC_DATA_HU_MASK (0xFF000000U) | ||
| 6095 | #define CRC_DATA_HU_SHIFT (24U) | ||
| 6096 | #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) | ||
| 6097 | /*! @} */ | ||
| 6098 | |||
| 6099 | /*! @name DATALL - CRC_DATALL register. */ | ||
| 6100 | /*! @{ */ | ||
| 6101 | #define CRC_DATALL_DATALL_MASK (0xFFU) | ||
| 6102 | #define CRC_DATALL_DATALL_SHIFT (0U) | ||
| 6103 | #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) | ||
| 6104 | /*! @} */ | ||
| 6105 | |||
| 6106 | /*! @name DATALU - CRC_DATALU register. */ | ||
| 6107 | /*! @{ */ | ||
| 6108 | #define CRC_DATALU_DATALU_MASK (0xFFU) | ||
| 6109 | #define CRC_DATALU_DATALU_SHIFT (0U) | ||
| 6110 | #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) | ||
| 6111 | /*! @} */ | ||
| 6112 | |||
| 6113 | /*! @name DATAHL - CRC_DATAHL register. */ | ||
| 6114 | /*! @{ */ | ||
| 6115 | #define CRC_DATAHL_DATAHL_MASK (0xFFU) | ||
| 6116 | #define CRC_DATAHL_DATAHL_SHIFT (0U) | ||
| 6117 | #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) | ||
| 6118 | /*! @} */ | ||
| 6119 | |||
| 6120 | /*! @name DATAHU - CRC_DATAHU register. */ | ||
| 6121 | /*! @{ */ | ||
| 6122 | #define CRC_DATAHU_DATAHU_MASK (0xFFU) | ||
| 6123 | #define CRC_DATAHU_DATAHU_SHIFT (0U) | ||
| 6124 | #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) | ||
| 6125 | /*! @} */ | ||
| 6126 | |||
| 6127 | /*! @name GPOLYL - CRC_GPOLYL register. */ | ||
| 6128 | /*! @{ */ | ||
| 6129 | #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) | ||
| 6130 | #define CRC_GPOLYL_GPOLYL_SHIFT (0U) | ||
| 6131 | #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) | ||
| 6132 | /*! @} */ | ||
| 6133 | |||
| 6134 | /*! @name GPOLYH - CRC_GPOLYH register. */ | ||
| 6135 | /*! @{ */ | ||
| 6136 | #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) | ||
| 6137 | #define CRC_GPOLYH_GPOLYH_SHIFT (0U) | ||
| 6138 | #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) | ||
| 6139 | /*! @} */ | ||
| 6140 | |||
| 6141 | /*! @name GPOLY - CRC Polynomial register */ | ||
| 6142 | /*! @{ */ | ||
| 6143 | #define CRC_GPOLY_LOW_MASK (0xFFFFU) | ||
| 6144 | #define CRC_GPOLY_LOW_SHIFT (0U) | ||
| 6145 | #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) | ||
| 6146 | #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) | ||
| 6147 | #define CRC_GPOLY_HIGH_SHIFT (16U) | ||
| 6148 | #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) | ||
| 6149 | /*! @} */ | ||
| 6150 | |||
| 6151 | /*! @name GPOLYLL - CRC_GPOLYLL register. */ | ||
| 6152 | /*! @{ */ | ||
| 6153 | #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) | ||
| 6154 | #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) | ||
| 6155 | #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) | ||
| 6156 | /*! @} */ | ||
| 6157 | |||
| 6158 | /*! @name GPOLYLU - CRC_GPOLYLU register. */ | ||
| 6159 | /*! @{ */ | ||
| 6160 | #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) | ||
| 6161 | #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) | ||
| 6162 | #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) | ||
| 6163 | /*! @} */ | ||
| 6164 | |||
| 6165 | /*! @name GPOLYHL - CRC_GPOLYHL register. */ | ||
| 6166 | /*! @{ */ | ||
| 6167 | #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) | ||
| 6168 | #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) | ||
| 6169 | #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) | ||
| 6170 | /*! @} */ | ||
| 6171 | |||
| 6172 | /*! @name GPOLYHU - CRC_GPOLYHU register. */ | ||
| 6173 | /*! @{ */ | ||
| 6174 | #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) | ||
| 6175 | #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) | ||
| 6176 | #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) | ||
| 6177 | /*! @} */ | ||
| 6178 | |||
| 6179 | /*! @name CTRL - CRC Control register */ | ||
| 6180 | /*! @{ */ | ||
| 6181 | #define CRC_CTRL_TCRC_MASK (0x1000000U) | ||
| 6182 | #define CRC_CTRL_TCRC_SHIFT (24U) | ||
| 6183 | /*! TCRC | ||
| 6184 | * 0b0..16-bit CRC protocol. | ||
| 6185 | * 0b1..32-bit CRC protocol. | ||
| 6186 | */ | ||
| 6187 | #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) | ||
| 6188 | #define CRC_CTRL_WAS_MASK (0x2000000U) | ||
| 6189 | #define CRC_CTRL_WAS_SHIFT (25U) | ||
| 6190 | /*! WAS - Write CRC Data Register As Seed | ||
| 6191 | * 0b0..Writes to the CRC data register are data values. | ||
| 6192 | * 0b1..Writes to the CRC data register are seed values. | ||
| 6193 | */ | ||
| 6194 | #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) | ||
| 6195 | #define CRC_CTRL_FXOR_MASK (0x4000000U) | ||
| 6196 | #define CRC_CTRL_FXOR_SHIFT (26U) | ||
| 6197 | /*! FXOR - Complement Read Of CRC Data Register | ||
| 6198 | * 0b0..No XOR on reading. | ||
| 6199 | * 0b1..Invert or complement the read value of the CRC Data register. | ||
| 6200 | */ | ||
| 6201 | #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) | ||
| 6202 | #define CRC_CTRL_TOTR_MASK (0x30000000U) | ||
| 6203 | #define CRC_CTRL_TOTR_SHIFT (28U) | ||
| 6204 | /*! TOTR - Type Of Transpose For Read | ||
| 6205 | * 0b00..No transposition. | ||
| 6206 | * 0b01..Bits in bytes are transposed; bytes are not transposed. | ||
| 6207 | * 0b10..Both bits in bytes and bytes are transposed. | ||
| 6208 | * 0b11..Only bytes are transposed; no bits in a byte are transposed. | ||
| 6209 | */ | ||
| 6210 | #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) | ||
| 6211 | #define CRC_CTRL_TOT_MASK (0xC0000000U) | ||
| 6212 | #define CRC_CTRL_TOT_SHIFT (30U) | ||
| 6213 | /*! TOT - Type Of Transpose For Writes | ||
| 6214 | * 0b00..No transposition. | ||
| 6215 | * 0b01..Bits in bytes are transposed; bytes are not transposed. | ||
| 6216 | * 0b10..Both bits in bytes and bytes are transposed. | ||
| 6217 | * 0b11..Only bytes are transposed; no bits in a byte are transposed. | ||
| 6218 | */ | ||
| 6219 | #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) | ||
| 6220 | /*! @} */ | ||
| 6221 | |||
| 6222 | /*! @name CTRLHU - CRC_CTRLHU register. */ | ||
| 6223 | /*! @{ */ | ||
| 6224 | #define CRC_CTRLHU_TCRC_MASK (0x1U) | ||
| 6225 | #define CRC_CTRLHU_TCRC_SHIFT (0U) | ||
| 6226 | /*! TCRC | ||
| 6227 | * 0b0..16-bit CRC protocol. | ||
| 6228 | * 0b1..32-bit CRC protocol. | ||
| 6229 | */ | ||
| 6230 | #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) | ||
| 6231 | #define CRC_CTRLHU_WAS_MASK (0x2U) | ||
| 6232 | #define CRC_CTRLHU_WAS_SHIFT (1U) | ||
| 6233 | /*! WAS | ||
| 6234 | * 0b0..Writes to CRC data register are data values. | ||
| 6235 | * 0b1..Writes to CRC data reguster are seed values. | ||
| 6236 | */ | ||
| 6237 | #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) | ||
| 6238 | #define CRC_CTRLHU_FXOR_MASK (0x4U) | ||
| 6239 | #define CRC_CTRLHU_FXOR_SHIFT (2U) | ||
| 6240 | /*! FXOR | ||
| 6241 | * 0b0..No XOR on reading. | ||
| 6242 | * 0b1..Invert or complement the read value of CRC data register. | ||
| 6243 | */ | ||
| 6244 | #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) | ||
| 6245 | #define CRC_CTRLHU_TOTR_MASK (0x30U) | ||
| 6246 | #define CRC_CTRLHU_TOTR_SHIFT (4U) | ||
| 6247 | /*! TOTR | ||
| 6248 | * 0b00..No Transposition. | ||
| 6249 | * 0b01..Bits in bytes are transposed, bytes are not transposed. | ||
| 6250 | * 0b10..Both bits in bytes and bytes are transposed. | ||
| 6251 | * 0b11..Only bytes are transposed; no bits in a byte are transposed. | ||
| 6252 | */ | ||
| 6253 | #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) | ||
| 6254 | #define CRC_CTRLHU_TOT_MASK (0xC0U) | ||
| 6255 | #define CRC_CTRLHU_TOT_SHIFT (6U) | ||
| 6256 | /*! TOT | ||
| 6257 | * 0b00..No Transposition. | ||
| 6258 | * 0b01..Bits in bytes are transposed, bytes are not transposed. | ||
| 6259 | * 0b10..Both bits in bytes and bytes are transposed. | ||
| 6260 | * 0b11..Only bytes are transposed; no bits in a byte are transposed. | ||
| 6261 | */ | ||
| 6262 | #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) | ||
| 6263 | /*! @} */ | ||
| 6264 | |||
| 6265 | |||
| 6266 | /*! | ||
| 6267 | * @} | ||
| 6268 | */ /* end of group CRC_Register_Masks */ | ||
| 6269 | |||
| 6270 | |||
| 6271 | /* CRC - Peripheral instance base addresses */ | ||
| 6272 | /** Peripheral CRC base address */ | ||
| 6273 | #define CRC_BASE (0x40032000u) | ||
| 6274 | /** Peripheral CRC base pointer */ | ||
| 6275 | #define CRC0 ((CRC_Type *)CRC_BASE) | ||
| 6276 | /** Array initializer of CRC peripheral base addresses */ | ||
| 6277 | #define CRC_BASE_ADDRS { CRC_BASE } | ||
| 6278 | /** Array initializer of CRC peripheral base pointers */ | ||
| 6279 | #define CRC_BASE_PTRS { CRC0 } | ||
| 6280 | |||
| 6281 | /*! | ||
| 6282 | * @} | ||
| 6283 | */ /* end of group CRC_Peripheral_Access_Layer */ | ||
| 6284 | |||
| 6285 | |||
| 6286 | /* ---------------------------------------------------------------------------- | ||
| 6287 | -- DAC Peripheral Access Layer | ||
| 6288 | ---------------------------------------------------------------------------- */ | ||
| 6289 | |||
| 6290 | /*! | ||
| 6291 | * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer | ||
| 6292 | * @{ | ||
| 6293 | */ | ||
| 6294 | |||
| 6295 | /** DAC - Register Layout Typedef */ | ||
| 6296 | typedef struct { | ||
| 6297 | struct { /* offset: 0x0, array step: 0x2 */ | ||
| 6298 | __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ | ||
| 6299 | __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ | ||
| 6300 | } DAT[16]; | ||
| 6301 | __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ | ||
| 6302 | __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ | ||
| 6303 | __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ | ||
| 6304 | __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ | ||
| 6305 | } DAC_Type; | ||
| 6306 | |||
| 6307 | /* ---------------------------------------------------------------------------- | ||
| 6308 | -- DAC Register Masks | ||
| 6309 | ---------------------------------------------------------------------------- */ | ||
| 6310 | |||
| 6311 | /*! | ||
| 6312 | * @addtogroup DAC_Register_Masks DAC Register Masks | ||
| 6313 | * @{ | ||
| 6314 | */ | ||
| 6315 | |||
| 6316 | /*! @name DATL - DAC Data Low Register */ | ||
| 6317 | /*! @{ */ | ||
| 6318 | #define DAC_DATL_DATA0_MASK (0xFFU) | ||
| 6319 | #define DAC_DATL_DATA0_SHIFT (0U) | ||
| 6320 | #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK) | ||
| 6321 | /*! @} */ | ||
| 6322 | |||
| 6323 | /* The count of DAC_DATL */ | ||
| 6324 | #define DAC_DATL_COUNT (16U) | ||
| 6325 | |||
| 6326 | /*! @name DATH - DAC Data High Register */ | ||
| 6327 | /*! @{ */ | ||
| 6328 | #define DAC_DATH_DATA1_MASK (0xFU) | ||
| 6329 | #define DAC_DATH_DATA1_SHIFT (0U) | ||
| 6330 | #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK) | ||
| 6331 | /*! @} */ | ||
| 6332 | |||
| 6333 | /* The count of DAC_DATH */ | ||
| 6334 | #define DAC_DATH_COUNT (16U) | ||
| 6335 | |||
| 6336 | /*! @name SR - DAC Status Register */ | ||
| 6337 | /*! @{ */ | ||
| 6338 | #define DAC_SR_DACBFRPBF_MASK (0x1U) | ||
| 6339 | #define DAC_SR_DACBFRPBF_SHIFT (0U) | ||
| 6340 | /*! DACBFRPBF - DAC Buffer Read Pointer Bottom Position Flag | ||
| 6341 | * 0b0..The DAC buffer read pointer is not equal to C2[DACBFUP]. | ||
| 6342 | * 0b1..The DAC buffer read pointer is equal to C2[DACBFUP]. | ||
| 6343 | */ | ||
| 6344 | #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK) | ||
| 6345 | #define DAC_SR_DACBFRPTF_MASK (0x2U) | ||
| 6346 | #define DAC_SR_DACBFRPTF_SHIFT (1U) | ||
| 6347 | /*! DACBFRPTF - DAC Buffer Read Pointer Top Position Flag | ||
| 6348 | * 0b0..The DAC buffer read pointer is not zero. | ||
| 6349 | * 0b1..The DAC buffer read pointer is zero. | ||
| 6350 | */ | ||
| 6351 | #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK) | ||
| 6352 | #define DAC_SR_DACBFWMF_MASK (0x4U) | ||
| 6353 | #define DAC_SR_DACBFWMF_SHIFT (2U) | ||
| 6354 | /*! DACBFWMF - DAC Buffer Watermark Flag | ||
| 6355 | * 0b0..The DAC buffer read pointer has not reached the watermark level. | ||
| 6356 | * 0b1..The DAC buffer read pointer has reached the watermark level. | ||
| 6357 | */ | ||
| 6358 | #define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK) | ||
| 6359 | /*! @} */ | ||
| 6360 | |||
| 6361 | /*! @name C0 - DAC Control Register */ | ||
| 6362 | /*! @{ */ | ||
| 6363 | #define DAC_C0_DACBBIEN_MASK (0x1U) | ||
| 6364 | #define DAC_C0_DACBBIEN_SHIFT (0U) | ||
| 6365 | /*! DACBBIEN - DAC Buffer Read Pointer Bottom Flag Interrupt Enable | ||
| 6366 | * 0b0..The DAC buffer read pointer bottom flag interrupt is disabled. | ||
| 6367 | * 0b1..The DAC buffer read pointer bottom flag interrupt is enabled. | ||
| 6368 | */ | ||
| 6369 | #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK) | ||
| 6370 | #define DAC_C0_DACBTIEN_MASK (0x2U) | ||
| 6371 | #define DAC_C0_DACBTIEN_SHIFT (1U) | ||
| 6372 | /*! DACBTIEN - DAC Buffer Read Pointer Top Flag Interrupt Enable | ||
| 6373 | * 0b0..The DAC buffer read pointer top flag interrupt is disabled. | ||
| 6374 | * 0b1..The DAC buffer read pointer top flag interrupt is enabled. | ||
| 6375 | */ | ||
| 6376 | #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK) | ||
| 6377 | #define DAC_C0_DACBWIEN_MASK (0x4U) | ||
| 6378 | #define DAC_C0_DACBWIEN_SHIFT (2U) | ||
| 6379 | /*! DACBWIEN - DAC Buffer Watermark Interrupt Enable | ||
| 6380 | * 0b0..The DAC buffer watermark interrupt is disabled. | ||
| 6381 | * 0b1..The DAC buffer watermark interrupt is enabled. | ||
| 6382 | */ | ||
| 6383 | #define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK) | ||
| 6384 | #define DAC_C0_LPEN_MASK (0x8U) | ||
| 6385 | #define DAC_C0_LPEN_SHIFT (3U) | ||
| 6386 | /*! LPEN - DAC Low Power Control | ||
| 6387 | * 0b0..High-Power mode | ||
| 6388 | * 0b1..Low-Power mode | ||
| 6389 | */ | ||
| 6390 | #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK) | ||
| 6391 | #define DAC_C0_DACSWTRG_MASK (0x10U) | ||
| 6392 | #define DAC_C0_DACSWTRG_SHIFT (4U) | ||
| 6393 | /*! DACSWTRG - DAC Software Trigger | ||
| 6394 | * 0b0..The DAC soft trigger is not valid. | ||
| 6395 | * 0b1..The DAC soft trigger is valid. | ||
| 6396 | */ | ||
| 6397 | #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK) | ||
| 6398 | #define DAC_C0_DACTRGSEL_MASK (0x20U) | ||
| 6399 | #define DAC_C0_DACTRGSEL_SHIFT (5U) | ||
| 6400 | /*! DACTRGSEL - DAC Trigger Select | ||
| 6401 | * 0b0..The DAC hardware trigger is selected. | ||
| 6402 | * 0b1..The DAC software trigger is selected. | ||
| 6403 | */ | ||
| 6404 | #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK) | ||
| 6405 | #define DAC_C0_DACRFS_MASK (0x40U) | ||
| 6406 | #define DAC_C0_DACRFS_SHIFT (6U) | ||
| 6407 | /*! DACRFS - DAC Reference Select | ||
| 6408 | * 0b0..The DAC selects DACREF_1 as the reference voltage. | ||
| 6409 | * 0b1..The DAC selects DACREF_2 as the reference voltage. | ||
| 6410 | */ | ||
| 6411 | #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK) | ||
| 6412 | #define DAC_C0_DACEN_MASK (0x80U) | ||
| 6413 | #define DAC_C0_DACEN_SHIFT (7U) | ||
| 6414 | /*! DACEN - DAC Enable | ||
| 6415 | * 0b0..The DAC system is disabled. | ||
| 6416 | * 0b1..The DAC system is enabled. | ||
| 6417 | */ | ||
| 6418 | #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK) | ||
| 6419 | /*! @} */ | ||
| 6420 | |||
| 6421 | /*! @name C1 - DAC Control Register 1 */ | ||
| 6422 | /*! @{ */ | ||
| 6423 | #define DAC_C1_DACBFEN_MASK (0x1U) | ||
| 6424 | #define DAC_C1_DACBFEN_SHIFT (0U) | ||
| 6425 | /*! DACBFEN - DAC Buffer Enable | ||
| 6426 | * 0b0..Buffer read pointer is disabled. The converted data is always the first word of the buffer. | ||
| 6427 | * 0b1..Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. | ||
| 6428 | */ | ||
| 6429 | #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK) | ||
| 6430 | #define DAC_C1_DACBFMD_MASK (0x6U) | ||
| 6431 | #define DAC_C1_DACBFMD_SHIFT (1U) | ||
| 6432 | /*! DACBFMD - DAC Buffer Work Mode Select | ||
| 6433 | * 0b00..Normal mode | ||
| 6434 | * 0b01..Swing mode | ||
| 6435 | * 0b10..One-Time Scan mode | ||
| 6436 | * 0b11..Reserved | ||
| 6437 | */ | ||
| 6438 | #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK) | ||
| 6439 | #define DAC_C1_DACBFWM_MASK (0x18U) | ||
| 6440 | #define DAC_C1_DACBFWM_SHIFT (3U) | ||
| 6441 | /*! DACBFWM - DAC Buffer Watermark Select | ||
| 6442 | * 0b00..1 word | ||
| 6443 | * 0b01..2 words | ||
| 6444 | * 0b10..3 words | ||
| 6445 | * 0b11..4 words | ||
| 6446 | */ | ||
| 6447 | #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK) | ||
| 6448 | #define DAC_C1_DMAEN_MASK (0x80U) | ||
| 6449 | #define DAC_C1_DMAEN_SHIFT (7U) | ||
| 6450 | /*! DMAEN - DMA Enable Select | ||
| 6451 | * 0b0..DMA is disabled. | ||
| 6452 | * 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time. | ||
| 6453 | */ | ||
| 6454 | #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK) | ||
| 6455 | /*! @} */ | ||
| 6456 | |||
| 6457 | /*! @name C2 - DAC Control Register 2 */ | ||
| 6458 | /*! @{ */ | ||
| 6459 | #define DAC_C2_DACBFUP_MASK (0xFU) | ||
| 6460 | #define DAC_C2_DACBFUP_SHIFT (0U) | ||
| 6461 | #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK) | ||
| 6462 | #define DAC_C2_DACBFRP_MASK (0xF0U) | ||
| 6463 | #define DAC_C2_DACBFRP_SHIFT (4U) | ||
| 6464 | #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK) | ||
| 6465 | /*! @} */ | ||
| 6466 | |||
| 6467 | |||
| 6468 | /*! | ||
| 6469 | * @} | ||
| 6470 | */ /* end of group DAC_Register_Masks */ | ||
| 6471 | |||
| 6472 | |||
| 6473 | /* DAC - Peripheral instance base addresses */ | ||
| 6474 | /** Peripheral DAC0 base address */ | ||
| 6475 | #define DAC0_BASE (0x400CC000u) | ||
| 6476 | /** Peripheral DAC0 base pointer */ | ||
| 6477 | #define DAC0 ((DAC_Type *)DAC0_BASE) | ||
| 6478 | /** Peripheral DAC1 base address */ | ||
| 6479 | #define DAC1_BASE (0x400CD000u) | ||
| 6480 | /** Peripheral DAC1 base pointer */ | ||
| 6481 | #define DAC1 ((DAC_Type *)DAC1_BASE) | ||
| 6482 | /** Array initializer of DAC peripheral base addresses */ | ||
| 6483 | #define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } | ||
| 6484 | /** Array initializer of DAC peripheral base pointers */ | ||
| 6485 | #define DAC_BASE_PTRS { DAC0, DAC1 } | ||
| 6486 | /** Interrupt vectors for the DAC peripheral type */ | ||
| 6487 | #define DAC_IRQS { DAC0_IRQn, DAC1_IRQn } | ||
| 6488 | |||
| 6489 | /*! | ||
| 6490 | * @} | ||
| 6491 | */ /* end of group DAC_Peripheral_Access_Layer */ | ||
| 6492 | |||
| 6493 | |||
| 6494 | /* ---------------------------------------------------------------------------- | ||
| 6495 | -- DMA Peripheral Access Layer | ||
| 6496 | ---------------------------------------------------------------------------- */ | ||
| 6497 | |||
| 6498 | /*! | ||
| 6499 | * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer | ||
| 6500 | * @{ | ||
| 6501 | */ | ||
| 6502 | |||
| 6503 | /** DMA - Register Layout Typedef */ | ||
| 6504 | typedef struct { | ||
| 6505 | __IO uint32_t CR; /**< Control Register, offset: 0x0 */ | ||
| 6506 | __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ | ||
| 6507 | uint8_t RESERVED_0[4]; | ||
| 6508 | __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ | ||
| 6509 | uint8_t RESERVED_1[4]; | ||
| 6510 | __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ | ||
| 6511 | __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ | ||
| 6512 | __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ | ||
| 6513 | __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ | ||
| 6514 | __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ | ||
| 6515 | __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ | ||
| 6516 | __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ | ||
| 6517 | __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ | ||
| 6518 | __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ | ||
| 6519 | uint8_t RESERVED_2[4]; | ||
| 6520 | __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ | ||
| 6521 | uint8_t RESERVED_3[4]; | ||
| 6522 | __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ | ||
| 6523 | uint8_t RESERVED_4[4]; | ||
| 6524 | __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ | ||
| 6525 | uint8_t RESERVED_5[200]; | ||
| 6526 | __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ | ||
| 6527 | __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ | ||
| 6528 | __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ | ||
| 6529 | __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ | ||
| 6530 | __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ | ||
| 6531 | __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ | ||
| 6532 | __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ | ||
| 6533 | __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ | ||
| 6534 | __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */ | ||
| 6535 | __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */ | ||
| 6536 | __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */ | ||
| 6537 | __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */ | ||
| 6538 | __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */ | ||
| 6539 | __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */ | ||
| 6540 | __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */ | ||
| 6541 | __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */ | ||
| 6542 | uint8_t RESERVED_6[3824]; | ||
| 6543 | struct { /* offset: 0x1000, array step: 0x20 */ | ||
| 6544 | __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ | ||
| 6545 | __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ | ||
| 6546 | __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ | ||
| 6547 | union { /* offset: 0x1008, array step: 0x20 */ | ||
| 6548 | __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */ | ||
| 6549 | __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ | ||
| 6550 | __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */ | ||
| 6551 | }; | ||
| 6552 | __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ | ||
| 6553 | __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ | ||
| 6554 | __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ | ||
| 6555 | union { /* offset: 0x1016, array step: 0x20 */ | ||
| 6556 | __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ | ||
| 6557 | __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ | ||
| 6558 | }; | ||
| 6559 | __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ | ||
| 6560 | __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ | ||
| 6561 | union { /* offset: 0x101E, array step: 0x20 */ | ||
| 6562 | __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ | ||
| 6563 | __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ | ||
| 6564 | }; | ||
| 6565 | } TCD[16]; | ||
| 6566 | } DMA_Type; | ||
| 6567 | |||
| 6568 | /* ---------------------------------------------------------------------------- | ||
| 6569 | -- DMA Register Masks | ||
| 6570 | ---------------------------------------------------------------------------- */ | ||
| 6571 | |||
| 6572 | /*! | ||
| 6573 | * @addtogroup DMA_Register_Masks DMA Register Masks | ||
| 6574 | * @{ | ||
| 6575 | */ | ||
| 6576 | |||
| 6577 | /*! @name CR - Control Register */ | ||
| 6578 | /*! @{ */ | ||
| 6579 | #define DMA_CR_EDBG_MASK (0x2U) | ||
| 6580 | #define DMA_CR_EDBG_SHIFT (1U) | ||
| 6581 | /*! EDBG - Enable Debug | ||
| 6582 | * 0b0..When in debug mode, the DMA continues to operate. | ||
| 6583 | * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. | ||
| 6584 | */ | ||
| 6585 | #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) | ||
| 6586 | #define DMA_CR_ERCA_MASK (0x4U) | ||
| 6587 | #define DMA_CR_ERCA_SHIFT (2U) | ||
| 6588 | /*! ERCA - Enable Round Robin Channel Arbitration | ||
| 6589 | * 0b0..Fixed priority arbitration is used for channel selection . | ||
| 6590 | * 0b1..Round robin arbitration is used for channel selection . | ||
| 6591 | */ | ||
| 6592 | #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) | ||
| 6593 | #define DMA_CR_HOE_MASK (0x10U) | ||
| 6594 | #define DMA_CR_HOE_SHIFT (4U) | ||
| 6595 | /*! HOE - Halt On Error | ||
| 6596 | * 0b0..Normal operation | ||
| 6597 | * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. | ||
| 6598 | */ | ||
| 6599 | #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) | ||
| 6600 | #define DMA_CR_HALT_MASK (0x20U) | ||
| 6601 | #define DMA_CR_HALT_SHIFT (5U) | ||
| 6602 | /*! HALT - Halt DMA Operations | ||
| 6603 | * 0b0..Normal operation | ||
| 6604 | * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. | ||
| 6605 | */ | ||
| 6606 | #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) | ||
| 6607 | #define DMA_CR_CLM_MASK (0x40U) | ||
| 6608 | #define DMA_CR_CLM_SHIFT (6U) | ||
| 6609 | /*! CLM - Continuous Link Mode | ||
| 6610 | * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. | ||
| 6611 | * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. | ||
| 6612 | */ | ||
| 6613 | #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) | ||
| 6614 | #define DMA_CR_EMLM_MASK (0x80U) | ||
| 6615 | #define DMA_CR_EMLM_SHIFT (7U) | ||
| 6616 | /*! EMLM - Enable Minor Loop Mapping | ||
| 6617 | * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. | ||
| 6618 | * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. | ||
| 6619 | */ | ||
| 6620 | #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) | ||
| 6621 | #define DMA_CR_ECX_MASK (0x10000U) | ||
| 6622 | #define DMA_CR_ECX_SHIFT (16U) | ||
| 6623 | /*! ECX - Error Cancel Transfer | ||
| 6624 | * 0b0..Normal operation | ||
| 6625 | * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. | ||
| 6626 | */ | ||
| 6627 | #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) | ||
| 6628 | #define DMA_CR_CX_MASK (0x20000U) | ||
| 6629 | #define DMA_CR_CX_SHIFT (17U) | ||
| 6630 | /*! CX - Cancel Transfer | ||
| 6631 | * 0b0..Normal operation | ||
| 6632 | * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. | ||
| 6633 | */ | ||
| 6634 | #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) | ||
| 6635 | /*! @} */ | ||
| 6636 | |||
| 6637 | /*! @name ES - Error Status Register */ | ||
| 6638 | /*! @{ */ | ||
| 6639 | #define DMA_ES_DBE_MASK (0x1U) | ||
| 6640 | #define DMA_ES_DBE_SHIFT (0U) | ||
| 6641 | /*! DBE - Destination Bus Error | ||
| 6642 | * 0b0..No destination bus error | ||
| 6643 | * 0b1..The last recorded error was a bus error on a destination write | ||
| 6644 | */ | ||
| 6645 | #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) | ||
| 6646 | #define DMA_ES_SBE_MASK (0x2U) | ||
| 6647 | #define DMA_ES_SBE_SHIFT (1U) | ||
| 6648 | /*! SBE - Source Bus Error | ||
| 6649 | * 0b0..No source bus error | ||
| 6650 | * 0b1..The last recorded error was a bus error on a source read | ||
| 6651 | */ | ||
| 6652 | #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) | ||
| 6653 | #define DMA_ES_SGE_MASK (0x4U) | ||
| 6654 | #define DMA_ES_SGE_SHIFT (2U) | ||
| 6655 | /*! SGE - Scatter/Gather Configuration Error | ||
| 6656 | * 0b0..No scatter/gather configuration error | ||
| 6657 | * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. | ||
| 6658 | */ | ||
| 6659 | #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) | ||
| 6660 | #define DMA_ES_NCE_MASK (0x8U) | ||
| 6661 | #define DMA_ES_NCE_SHIFT (3U) | ||
| 6662 | /*! NCE - NBYTES/CITER Configuration Error | ||
| 6663 | * 0b0..No NBYTES/CITER configuration error | ||
| 6664 | * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] | ||
| 6665 | */ | ||
| 6666 | #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) | ||
| 6667 | #define DMA_ES_DOE_MASK (0x10U) | ||
| 6668 | #define DMA_ES_DOE_SHIFT (4U) | ||
| 6669 | /*! DOE - Destination Offset Error | ||
| 6670 | * 0b0..No destination offset configuration error | ||
| 6671 | * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. | ||
| 6672 | */ | ||
| 6673 | #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) | ||
| 6674 | #define DMA_ES_DAE_MASK (0x20U) | ||
| 6675 | #define DMA_ES_DAE_SHIFT (5U) | ||
| 6676 | /*! DAE - Destination Address Error | ||
| 6677 | * 0b0..No destination address configuration error | ||
| 6678 | * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. | ||
| 6679 | */ | ||
| 6680 | #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) | ||
| 6681 | #define DMA_ES_SOE_MASK (0x40U) | ||
| 6682 | #define DMA_ES_SOE_SHIFT (6U) | ||
| 6683 | /*! SOE - Source Offset Error | ||
| 6684 | * 0b0..No source offset configuration error | ||
| 6685 | * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. | ||
| 6686 | */ | ||
| 6687 | #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) | ||
| 6688 | #define DMA_ES_SAE_MASK (0x80U) | ||
| 6689 | #define DMA_ES_SAE_SHIFT (7U) | ||
| 6690 | /*! SAE - Source Address Error | ||
| 6691 | * 0b0..No source address configuration error. | ||
| 6692 | * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. | ||
| 6693 | */ | ||
| 6694 | #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) | ||
| 6695 | #define DMA_ES_ERRCHN_MASK (0xF00U) | ||
| 6696 | #define DMA_ES_ERRCHN_SHIFT (8U) | ||
| 6697 | #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) | ||
| 6698 | #define DMA_ES_CPE_MASK (0x4000U) | ||
| 6699 | #define DMA_ES_CPE_SHIFT (14U) | ||
| 6700 | /*! CPE - Channel Priority Error | ||
| 6701 | * 0b0..No channel priority error | ||
| 6702 | * 0b1..The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique. | ||
| 6703 | */ | ||
| 6704 | #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) | ||
| 6705 | #define DMA_ES_ECX_MASK (0x10000U) | ||
| 6706 | #define DMA_ES_ECX_SHIFT (16U) | ||
| 6707 | /*! ECX - Transfer Canceled | ||
| 6708 | * 0b0..No canceled transfers | ||
| 6709 | * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input | ||
| 6710 | */ | ||
| 6711 | #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) | ||
| 6712 | #define DMA_ES_VLD_MASK (0x80000000U) | ||
| 6713 | #define DMA_ES_VLD_SHIFT (31U) | ||
| 6714 | /*! VLD | ||
| 6715 | * 0b0..No ERR bits are set | ||
| 6716 | * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared | ||
| 6717 | */ | ||
| 6718 | #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) | ||
| 6719 | /*! @} */ | ||
| 6720 | |||
| 6721 | /*! @name ERQ - Enable Request Register */ | ||
| 6722 | /*! @{ */ | ||
| 6723 | #define DMA_ERQ_ERQ0_MASK (0x1U) | ||
| 6724 | #define DMA_ERQ_ERQ0_SHIFT (0U) | ||
| 6725 | /*! ERQ0 - Enable DMA Request 0 | ||
| 6726 | * 0b0..The DMA request signal for the corresponding channel is disabled | ||
| 6727 | * 0b1..The DMA request signal for the corresponding channel is enabled | ||
| 6728 | */ | ||
| 6729 | #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) | ||
| 6730 | #define DMA_ERQ_ERQ1_MASK (0x2U) | ||
| 6731 | #define DMA_ERQ_ERQ1_SHIFT (1U) | ||
| 6732 | /*! ERQ1 - Enable DMA Request 1 | ||
| 6733 | * 0b0..The DMA request signal for the corresponding channel is disabled | ||
| 6734 | * 0b1..The DMA request signal for the corresponding channel is enabled | ||
| 6735 | */ | ||
| 6736 | #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) | ||
| 6737 | #define DMA_ERQ_ERQ2_MASK (0x4U) | ||
| 6738 | #define DMA_ERQ_ERQ2_SHIFT (2U) | ||
| 6739 | /*! ERQ2 - Enable DMA Request 2 | ||
| 6740 | * 0b0..The DMA request signal for the corresponding channel is disabled | ||
| 6741 | * 0b1..The DMA request signal for the corresponding channel is enabled | ||
| 6742 | */ | ||
| 6743 | #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) | ||
| 6744 | #define DMA_ERQ_ERQ3_MASK (0x8U) | ||
| 6745 | #define DMA_ERQ_ERQ3_SHIFT (3U) | ||
| 6746 | /*! ERQ3 - Enable DMA Request 3 | ||
| 6747 | * 0b0..The DMA request signal for the corresponding channel is disabled | ||
| 6748 | * 0b1..The DMA request signal for the corresponding channel is enabled | ||
| 6749 | */ | ||
| 6750 | #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) | ||
| 6751 | #define DMA_ERQ_ERQ4_MASK (0x10U) | ||
| 6752 | #define DMA_ERQ_ERQ4_SHIFT (4U) | ||
| 6753 | /*! ERQ4 - Enable DMA Request 4 | ||
| 6754 | * 0b0..The DMA request signal for the corresponding channel is disabled | ||
| 6755 | * 0b1..The DMA request signal for the corresponding channel is enabled | ||
| 6756 | */ | ||
| 6757 | #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) | ||
| 6758 | #define DMA_ERQ_ERQ5_MASK (0x20U) | ||
| 6759 | #define DMA_ERQ_ERQ5_SHIFT (5U) | ||
| 6760 | /*! ERQ5 - Enable DMA Request 5 | ||
| 6761 | * 0b0..The DMA request signal for the corresponding channel is disabled | ||
| 6762 | * 0b1..The DMA request signal for the corresponding channel is enabled | ||
| 6763 | */ | ||
| 6764 | #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) | ||
| 6765 | #define DMA_ERQ_ERQ6_MASK (0x40U) | ||
| 6766 | #define DMA_ERQ_ERQ6_SHIFT (6U) | ||
| 6767 | /*! ERQ6 - Enable DMA Request 6 | ||
| 6768 | * 0b0..The DMA request signal for the corresponding channel is disabled | ||
| 6769 | * 0b1..The DMA request signal for the corresponding channel is enabled | ||
| 6770 | */ | ||
| 6771 | #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) | ||
| 6772 | #define DMA_ERQ_ERQ7_MASK (0x80U) | ||
| 6773 | #define DMA_ERQ_ERQ7_SHIFT (7U) | ||
| 6774 | /*! ERQ7 - Enable DMA Request 7 | ||
| 6775 | * 0b0..The DMA request signal for the corresponding channel is disabled | ||
| 6776 | * 0b1..The DMA request signal for the corresponding channel is enabled | ||
| 6777 | */ | ||
| 6778 | #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) | ||
| 6779 | #define DMA_ERQ_ERQ8_MASK (0x100U) | ||
| 6780 | #define DMA_ERQ_ERQ8_SHIFT (8U) | ||
| 6781 | /*! ERQ8 - Enable DMA Request 8 | ||
| 6782 | * 0b0..The DMA request signal for the corresponding channel is disabled | ||
| 6783 | * 0b1..The DMA request signal for the corresponding channel is enabled | ||
| 6784 | */ | ||
| 6785 | #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) | ||
| 6786 | #define DMA_ERQ_ERQ9_MASK (0x200U) | ||
| 6787 | #define DMA_ERQ_ERQ9_SHIFT (9U) | ||
| 6788 | /*! ERQ9 - Enable DMA Request 9 | ||
| 6789 | * 0b0..The DMA request signal for the corresponding channel is disabled | ||
| 6790 | * 0b1..The DMA request signal for the corresponding channel is enabled | ||
| 6791 | */ | ||
| 6792 | #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) | ||
| 6793 | #define DMA_ERQ_ERQ10_MASK (0x400U) | ||
| 6794 | #define DMA_ERQ_ERQ10_SHIFT (10U) | ||
| 6795 | /*! ERQ10 - Enable DMA Request 10 | ||
| 6796 | * 0b0..The DMA request signal for the corresponding channel is disabled | ||
| 6797 | * 0b1..The DMA request signal for the corresponding channel is enabled | ||
| 6798 | */ | ||
| 6799 | #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) | ||
| 6800 | #define DMA_ERQ_ERQ11_MASK (0x800U) | ||
| 6801 | #define DMA_ERQ_ERQ11_SHIFT (11U) | ||
| 6802 | /*! ERQ11 - Enable DMA Request 11 | ||
| 6803 | * 0b0..The DMA request signal for the corresponding channel is disabled | ||
| 6804 | * 0b1..The DMA request signal for the corresponding channel is enabled | ||
| 6805 | */ | ||
| 6806 | #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) | ||
| 6807 | #define DMA_ERQ_ERQ12_MASK (0x1000U) | ||
| 6808 | #define DMA_ERQ_ERQ12_SHIFT (12U) | ||
| 6809 | /*! ERQ12 - Enable DMA Request 12 | ||
| 6810 | * 0b0..The DMA request signal for the corresponding channel is disabled | ||
| 6811 | * 0b1..The DMA request signal for the corresponding channel is enabled | ||
| 6812 | */ | ||
| 6813 | #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) | ||
| 6814 | #define DMA_ERQ_ERQ13_MASK (0x2000U) | ||
| 6815 | #define DMA_ERQ_ERQ13_SHIFT (13U) | ||
| 6816 | /*! ERQ13 - Enable DMA Request 13 | ||
| 6817 | * 0b0..The DMA request signal for the corresponding channel is disabled | ||
| 6818 | * 0b1..The DMA request signal for the corresponding channel is enabled | ||
| 6819 | */ | ||
| 6820 | #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) | ||
| 6821 | #define DMA_ERQ_ERQ14_MASK (0x4000U) | ||
| 6822 | #define DMA_ERQ_ERQ14_SHIFT (14U) | ||
| 6823 | /*! ERQ14 - Enable DMA Request 14 | ||
| 6824 | * 0b0..The DMA request signal for the corresponding channel is disabled | ||
| 6825 | * 0b1..The DMA request signal for the corresponding channel is enabled | ||
| 6826 | */ | ||
| 6827 | #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) | ||
| 6828 | #define DMA_ERQ_ERQ15_MASK (0x8000U) | ||
| 6829 | #define DMA_ERQ_ERQ15_SHIFT (15U) | ||
| 6830 | /*! ERQ15 - Enable DMA Request 15 | ||
| 6831 | * 0b0..The DMA request signal for the corresponding channel is disabled | ||
| 6832 | * 0b1..The DMA request signal for the corresponding channel is enabled | ||
| 6833 | */ | ||
| 6834 | #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) | ||
| 6835 | /*! @} */ | ||
| 6836 | |||
| 6837 | /*! @name EEI - Enable Error Interrupt Register */ | ||
| 6838 | /*! @{ */ | ||
| 6839 | #define DMA_EEI_EEI0_MASK (0x1U) | ||
| 6840 | #define DMA_EEI_EEI0_SHIFT (0U) | ||
| 6841 | /*! EEI0 - Enable Error Interrupt 0 | ||
| 6842 | * 0b0..The error signal for corresponding channel does not generate an error interrupt | ||
| 6843 | * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request | ||
| 6844 | */ | ||
| 6845 | #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) | ||
| 6846 | #define DMA_EEI_EEI1_MASK (0x2U) | ||
| 6847 | #define DMA_EEI_EEI1_SHIFT (1U) | ||
| 6848 | /*! EEI1 - Enable Error Interrupt 1 | ||
| 6849 | * 0b0..The error signal for corresponding channel does not generate an error interrupt | ||
| 6850 | * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request | ||
| 6851 | */ | ||
| 6852 | #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) | ||
| 6853 | #define DMA_EEI_EEI2_MASK (0x4U) | ||
| 6854 | #define DMA_EEI_EEI2_SHIFT (2U) | ||
| 6855 | /*! EEI2 - Enable Error Interrupt 2 | ||
| 6856 | * 0b0..The error signal for corresponding channel does not generate an error interrupt | ||
| 6857 | * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request | ||
| 6858 | */ | ||
| 6859 | #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) | ||
| 6860 | #define DMA_EEI_EEI3_MASK (0x8U) | ||
| 6861 | #define DMA_EEI_EEI3_SHIFT (3U) | ||
| 6862 | /*! EEI3 - Enable Error Interrupt 3 | ||
| 6863 | * 0b0..The error signal for corresponding channel does not generate an error interrupt | ||
| 6864 | * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request | ||
| 6865 | */ | ||
| 6866 | #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) | ||
| 6867 | #define DMA_EEI_EEI4_MASK (0x10U) | ||
| 6868 | #define DMA_EEI_EEI4_SHIFT (4U) | ||
| 6869 | /*! EEI4 - Enable Error Interrupt 4 | ||
| 6870 | * 0b0..The error signal for corresponding channel does not generate an error interrupt | ||
| 6871 | * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request | ||
| 6872 | */ | ||
| 6873 | #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) | ||
| 6874 | #define DMA_EEI_EEI5_MASK (0x20U) | ||
| 6875 | #define DMA_EEI_EEI5_SHIFT (5U) | ||
| 6876 | /*! EEI5 - Enable Error Interrupt 5 | ||
| 6877 | * 0b0..The error signal for corresponding channel does not generate an error interrupt | ||
| 6878 | * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request | ||
| 6879 | */ | ||
| 6880 | #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) | ||
| 6881 | #define DMA_EEI_EEI6_MASK (0x40U) | ||
| 6882 | #define DMA_EEI_EEI6_SHIFT (6U) | ||
| 6883 | /*! EEI6 - Enable Error Interrupt 6 | ||
| 6884 | * 0b0..The error signal for corresponding channel does not generate an error interrupt | ||
| 6885 | * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request | ||
| 6886 | */ | ||
| 6887 | #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) | ||
| 6888 | #define DMA_EEI_EEI7_MASK (0x80U) | ||
| 6889 | #define DMA_EEI_EEI7_SHIFT (7U) | ||
| 6890 | /*! EEI7 - Enable Error Interrupt 7 | ||
| 6891 | * 0b0..The error signal for corresponding channel does not generate an error interrupt | ||
| 6892 | * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request | ||
| 6893 | */ | ||
| 6894 | #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) | ||
| 6895 | #define DMA_EEI_EEI8_MASK (0x100U) | ||
| 6896 | #define DMA_EEI_EEI8_SHIFT (8U) | ||
| 6897 | /*! EEI8 - Enable Error Interrupt 8 | ||
| 6898 | * 0b0..The error signal for corresponding channel does not generate an error interrupt | ||
| 6899 | * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request | ||
| 6900 | */ | ||
| 6901 | #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) | ||
| 6902 | #define DMA_EEI_EEI9_MASK (0x200U) | ||
| 6903 | #define DMA_EEI_EEI9_SHIFT (9U) | ||
| 6904 | /*! EEI9 - Enable Error Interrupt 9 | ||
| 6905 | * 0b0..The error signal for corresponding channel does not generate an error interrupt | ||
| 6906 | * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request | ||
| 6907 | */ | ||
| 6908 | #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) | ||
| 6909 | #define DMA_EEI_EEI10_MASK (0x400U) | ||
| 6910 | #define DMA_EEI_EEI10_SHIFT (10U) | ||
| 6911 | /*! EEI10 - Enable Error Interrupt 10 | ||
| 6912 | * 0b0..The error signal for corresponding channel does not generate an error interrupt | ||
| 6913 | * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request | ||
| 6914 | */ | ||
| 6915 | #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) | ||
| 6916 | #define DMA_EEI_EEI11_MASK (0x800U) | ||
| 6917 | #define DMA_EEI_EEI11_SHIFT (11U) | ||
| 6918 | /*! EEI11 - Enable Error Interrupt 11 | ||
| 6919 | * 0b0..The error signal for corresponding channel does not generate an error interrupt | ||
| 6920 | * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request | ||
| 6921 | */ | ||
| 6922 | #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) | ||
| 6923 | #define DMA_EEI_EEI12_MASK (0x1000U) | ||
| 6924 | #define DMA_EEI_EEI12_SHIFT (12U) | ||
| 6925 | /*! EEI12 - Enable Error Interrupt 12 | ||
| 6926 | * 0b0..The error signal for corresponding channel does not generate an error interrupt | ||
| 6927 | * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request | ||
| 6928 | */ | ||
| 6929 | #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) | ||
| 6930 | #define DMA_EEI_EEI13_MASK (0x2000U) | ||
| 6931 | #define DMA_EEI_EEI13_SHIFT (13U) | ||
| 6932 | /*! EEI13 - Enable Error Interrupt 13 | ||
| 6933 | * 0b0..The error signal for corresponding channel does not generate an error interrupt | ||
| 6934 | * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request | ||
| 6935 | */ | ||
| 6936 | #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) | ||
| 6937 | #define DMA_EEI_EEI14_MASK (0x4000U) | ||
| 6938 | #define DMA_EEI_EEI14_SHIFT (14U) | ||
| 6939 | /*! EEI14 - Enable Error Interrupt 14 | ||
| 6940 | * 0b0..The error signal for corresponding channel does not generate an error interrupt | ||
| 6941 | * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request | ||
| 6942 | */ | ||
| 6943 | #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) | ||
| 6944 | #define DMA_EEI_EEI15_MASK (0x8000U) | ||
| 6945 | #define DMA_EEI_EEI15_SHIFT (15U) | ||
| 6946 | /*! EEI15 - Enable Error Interrupt 15 | ||
| 6947 | * 0b0..The error signal for corresponding channel does not generate an error interrupt | ||
| 6948 | * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request | ||
| 6949 | */ | ||
| 6950 | #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) | ||
| 6951 | /*! @} */ | ||
| 6952 | |||
| 6953 | /*! @name CEEI - Clear Enable Error Interrupt Register */ | ||
| 6954 | /*! @{ */ | ||
| 6955 | #define DMA_CEEI_CEEI_MASK (0xFU) | ||
| 6956 | #define DMA_CEEI_CEEI_SHIFT (0U) | ||
| 6957 | #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) | ||
| 6958 | #define DMA_CEEI_CAEE_MASK (0x40U) | ||
| 6959 | #define DMA_CEEI_CAEE_SHIFT (6U) | ||
| 6960 | /*! CAEE - Clear All Enable Error Interrupts | ||
| 6961 | * 0b0..Clear only the EEI bit specified in the CEEI field | ||
| 6962 | * 0b1..Clear all bits in EEI | ||
| 6963 | */ | ||
| 6964 | #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) | ||
| 6965 | #define DMA_CEEI_NOP_MASK (0x80U) | ||
| 6966 | #define DMA_CEEI_NOP_SHIFT (7U) | ||
| 6967 | /*! NOP - No Op enable | ||
| 6968 | * 0b0..Normal operation | ||
| 6969 | * 0b1..No operation, ignore the other bits in this register | ||
| 6970 | */ | ||
| 6971 | #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) | ||
| 6972 | /*! @} */ | ||
| 6973 | |||
| 6974 | /*! @name SEEI - Set Enable Error Interrupt Register */ | ||
| 6975 | /*! @{ */ | ||
| 6976 | #define DMA_SEEI_SEEI_MASK (0xFU) | ||
| 6977 | #define DMA_SEEI_SEEI_SHIFT (0U) | ||
| 6978 | #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) | ||
| 6979 | #define DMA_SEEI_SAEE_MASK (0x40U) | ||
| 6980 | #define DMA_SEEI_SAEE_SHIFT (6U) | ||
| 6981 | /*! SAEE - Sets All Enable Error Interrupts | ||
| 6982 | * 0b0..Set only the EEI bit specified in the SEEI field. | ||
| 6983 | * 0b1..Sets all bits in EEI | ||
| 6984 | */ | ||
| 6985 | #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) | ||
| 6986 | #define DMA_SEEI_NOP_MASK (0x80U) | ||
| 6987 | #define DMA_SEEI_NOP_SHIFT (7U) | ||
| 6988 | /*! NOP - No Op enable | ||
| 6989 | * 0b0..Normal operation | ||
| 6990 | * 0b1..No operation, ignore the other bits in this register | ||
| 6991 | */ | ||
| 6992 | #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) | ||
| 6993 | /*! @} */ | ||
| 6994 | |||
| 6995 | /*! @name CERQ - Clear Enable Request Register */ | ||
| 6996 | /*! @{ */ | ||
| 6997 | #define DMA_CERQ_CERQ_MASK (0xFU) | ||
| 6998 | #define DMA_CERQ_CERQ_SHIFT (0U) | ||
| 6999 | #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) | ||
| 7000 | #define DMA_CERQ_CAER_MASK (0x40U) | ||
| 7001 | #define DMA_CERQ_CAER_SHIFT (6U) | ||
| 7002 | /*! CAER - Clear All Enable Requests | ||
| 7003 | * 0b0..Clear only the ERQ bit specified in the CERQ field | ||
| 7004 | * 0b1..Clear all bits in ERQ | ||
| 7005 | */ | ||
| 7006 | #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) | ||
| 7007 | #define DMA_CERQ_NOP_MASK (0x80U) | ||
| 7008 | #define DMA_CERQ_NOP_SHIFT (7U) | ||
| 7009 | /*! NOP - No Op enable | ||
| 7010 | * 0b0..Normal operation | ||
| 7011 | * 0b1..No operation, ignore the other bits in this register | ||
| 7012 | */ | ||
| 7013 | #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) | ||
| 7014 | /*! @} */ | ||
| 7015 | |||
| 7016 | /*! @name SERQ - Set Enable Request Register */ | ||
| 7017 | /*! @{ */ | ||
| 7018 | #define DMA_SERQ_SERQ_MASK (0xFU) | ||
| 7019 | #define DMA_SERQ_SERQ_SHIFT (0U) | ||
| 7020 | #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) | ||
| 7021 | #define DMA_SERQ_SAER_MASK (0x40U) | ||
| 7022 | #define DMA_SERQ_SAER_SHIFT (6U) | ||
| 7023 | /*! SAER - Set All Enable Requests | ||
| 7024 | * 0b0..Set only the ERQ bit specified in the SERQ field | ||
| 7025 | * 0b1..Set all bits in ERQ | ||
| 7026 | */ | ||
| 7027 | #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) | ||
| 7028 | #define DMA_SERQ_NOP_MASK (0x80U) | ||
| 7029 | #define DMA_SERQ_NOP_SHIFT (7U) | ||
| 7030 | /*! NOP - No Op enable | ||
| 7031 | * 0b0..Normal operation | ||
| 7032 | * 0b1..No operation, ignore the other bits in this register | ||
| 7033 | */ | ||
| 7034 | #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) | ||
| 7035 | /*! @} */ | ||
| 7036 | |||
| 7037 | /*! @name CDNE - Clear DONE Status Bit Register */ | ||
| 7038 | /*! @{ */ | ||
| 7039 | #define DMA_CDNE_CDNE_MASK (0xFU) | ||
| 7040 | #define DMA_CDNE_CDNE_SHIFT (0U) | ||
| 7041 | #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) | ||
| 7042 | #define DMA_CDNE_CADN_MASK (0x40U) | ||
| 7043 | #define DMA_CDNE_CADN_SHIFT (6U) | ||
| 7044 | /*! CADN - Clears All DONE Bits | ||
| 7045 | * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field | ||
| 7046 | * 0b1..Clears all bits in TCDn_CSR[DONE] | ||
| 7047 | */ | ||
| 7048 | #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) | ||
| 7049 | #define DMA_CDNE_NOP_MASK (0x80U) | ||
| 7050 | #define DMA_CDNE_NOP_SHIFT (7U) | ||
| 7051 | /*! NOP - No Op enable | ||
| 7052 | * 0b0..Normal operation | ||
| 7053 | * 0b1..No operation, ignore the other bits in this register | ||
| 7054 | */ | ||
| 7055 | #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) | ||
| 7056 | /*! @} */ | ||
| 7057 | |||
| 7058 | /*! @name SSRT - Set START Bit Register */ | ||
| 7059 | /*! @{ */ | ||
| 7060 | #define DMA_SSRT_SSRT_MASK (0xFU) | ||
| 7061 | #define DMA_SSRT_SSRT_SHIFT (0U) | ||
| 7062 | #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) | ||
| 7063 | #define DMA_SSRT_SAST_MASK (0x40U) | ||
| 7064 | #define DMA_SSRT_SAST_SHIFT (6U) | ||
| 7065 | /*! SAST - Set All START Bits (activates all channels) | ||
| 7066 | * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field | ||
| 7067 | * 0b1..Set all bits in TCDn_CSR[START] | ||
| 7068 | */ | ||
| 7069 | #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) | ||
| 7070 | #define DMA_SSRT_NOP_MASK (0x80U) | ||
| 7071 | #define DMA_SSRT_NOP_SHIFT (7U) | ||
| 7072 | /*! NOP - No Op enable | ||
| 7073 | * 0b0..Normal operation | ||
| 7074 | * 0b1..No operation, ignore the other bits in this register | ||
| 7075 | */ | ||
| 7076 | #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) | ||
| 7077 | /*! @} */ | ||
| 7078 | |||
| 7079 | /*! @name CERR - Clear Error Register */ | ||
| 7080 | /*! @{ */ | ||
| 7081 | #define DMA_CERR_CERR_MASK (0xFU) | ||
| 7082 | #define DMA_CERR_CERR_SHIFT (0U) | ||
| 7083 | #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) | ||
| 7084 | #define DMA_CERR_CAEI_MASK (0x40U) | ||
| 7085 | #define DMA_CERR_CAEI_SHIFT (6U) | ||
| 7086 | /*! CAEI - Clear All Error Indicators | ||
| 7087 | * 0b0..Clear only the ERR bit specified in the CERR field | ||
| 7088 | * 0b1..Clear all bits in ERR | ||
| 7089 | */ | ||
| 7090 | #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) | ||
| 7091 | #define DMA_CERR_NOP_MASK (0x80U) | ||
| 7092 | #define DMA_CERR_NOP_SHIFT (7U) | ||
| 7093 | /*! NOP - No Op enable | ||
| 7094 | * 0b0..Normal operation | ||
| 7095 | * 0b1..No operation, ignore the other bits in this register | ||
| 7096 | */ | ||
| 7097 | #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) | ||
| 7098 | /*! @} */ | ||
| 7099 | |||
| 7100 | /*! @name CINT - Clear Interrupt Request Register */ | ||
| 7101 | /*! @{ */ | ||
| 7102 | #define DMA_CINT_CINT_MASK (0xFU) | ||
| 7103 | #define DMA_CINT_CINT_SHIFT (0U) | ||
| 7104 | #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) | ||
| 7105 | #define DMA_CINT_CAIR_MASK (0x40U) | ||
| 7106 | #define DMA_CINT_CAIR_SHIFT (6U) | ||
| 7107 | /*! CAIR - Clear All Interrupt Requests | ||
| 7108 | * 0b0..Clear only the INT bit specified in the CINT field | ||
| 7109 | * 0b1..Clear all bits in INT | ||
| 7110 | */ | ||
| 7111 | #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) | ||
| 7112 | #define DMA_CINT_NOP_MASK (0x80U) | ||
| 7113 | #define DMA_CINT_NOP_SHIFT (7U) | ||
| 7114 | /*! NOP - No Op enable | ||
| 7115 | * 0b0..Normal operation | ||
| 7116 | * 0b1..No operation, ignore the other bits in this register | ||
| 7117 | */ | ||
| 7118 | #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) | ||
| 7119 | /*! @} */ | ||
| 7120 | |||
| 7121 | /*! @name INT - Interrupt Request Register */ | ||
| 7122 | /*! @{ */ | ||
| 7123 | #define DMA_INT_INT0_MASK (0x1U) | ||
| 7124 | #define DMA_INT_INT0_SHIFT (0U) | ||
| 7125 | /*! INT0 - Interrupt Request 0 | ||
| 7126 | * 0b0..The interrupt request for corresponding channel is cleared | ||
| 7127 | * 0b1..The interrupt request for corresponding channel is active | ||
| 7128 | */ | ||
| 7129 | #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) | ||
| 7130 | #define DMA_INT_INT1_MASK (0x2U) | ||
| 7131 | #define DMA_INT_INT1_SHIFT (1U) | ||
| 7132 | /*! INT1 - Interrupt Request 1 | ||
| 7133 | * 0b0..The interrupt request for corresponding channel is cleared | ||
| 7134 | * 0b1..The interrupt request for corresponding channel is active | ||
| 7135 | */ | ||
| 7136 | #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) | ||
| 7137 | #define DMA_INT_INT2_MASK (0x4U) | ||
| 7138 | #define DMA_INT_INT2_SHIFT (2U) | ||
| 7139 | /*! INT2 - Interrupt Request 2 | ||
| 7140 | * 0b0..The interrupt request for corresponding channel is cleared | ||
| 7141 | * 0b1..The interrupt request for corresponding channel is active | ||
| 7142 | */ | ||
| 7143 | #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) | ||
| 7144 | #define DMA_INT_INT3_MASK (0x8U) | ||
| 7145 | #define DMA_INT_INT3_SHIFT (3U) | ||
| 7146 | /*! INT3 - Interrupt Request 3 | ||
| 7147 | * 0b0..The interrupt request for corresponding channel is cleared | ||
| 7148 | * 0b1..The interrupt request for corresponding channel is active | ||
| 7149 | */ | ||
| 7150 | #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) | ||
| 7151 | #define DMA_INT_INT4_MASK (0x10U) | ||
| 7152 | #define DMA_INT_INT4_SHIFT (4U) | ||
| 7153 | /*! INT4 - Interrupt Request 4 | ||
| 7154 | * 0b0..The interrupt request for corresponding channel is cleared | ||
| 7155 | * 0b1..The interrupt request for corresponding channel is active | ||
| 7156 | */ | ||
| 7157 | #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) | ||
| 7158 | #define DMA_INT_INT5_MASK (0x20U) | ||
| 7159 | #define DMA_INT_INT5_SHIFT (5U) | ||
| 7160 | /*! INT5 - Interrupt Request 5 | ||
| 7161 | * 0b0..The interrupt request for corresponding channel is cleared | ||
| 7162 | * 0b1..The interrupt request for corresponding channel is active | ||
| 7163 | */ | ||
| 7164 | #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) | ||
| 7165 | #define DMA_INT_INT6_MASK (0x40U) | ||
| 7166 | #define DMA_INT_INT6_SHIFT (6U) | ||
| 7167 | /*! INT6 - Interrupt Request 6 | ||
| 7168 | * 0b0..The interrupt request for corresponding channel is cleared | ||
| 7169 | * 0b1..The interrupt request for corresponding channel is active | ||
| 7170 | */ | ||
| 7171 | #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) | ||
| 7172 | #define DMA_INT_INT7_MASK (0x80U) | ||
| 7173 | #define DMA_INT_INT7_SHIFT (7U) | ||
| 7174 | /*! INT7 - Interrupt Request 7 | ||
| 7175 | * 0b0..The interrupt request for corresponding channel is cleared | ||
| 7176 | * 0b1..The interrupt request for corresponding channel is active | ||
| 7177 | */ | ||
| 7178 | #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) | ||
| 7179 | #define DMA_INT_INT8_MASK (0x100U) | ||
| 7180 | #define DMA_INT_INT8_SHIFT (8U) | ||
| 7181 | /*! INT8 - Interrupt Request 8 | ||
| 7182 | * 0b0..The interrupt request for corresponding channel is cleared | ||
| 7183 | * 0b1..The interrupt request for corresponding channel is active | ||
| 7184 | */ | ||
| 7185 | #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) | ||
| 7186 | #define DMA_INT_INT9_MASK (0x200U) | ||
| 7187 | #define DMA_INT_INT9_SHIFT (9U) | ||
| 7188 | /*! INT9 - Interrupt Request 9 | ||
| 7189 | * 0b0..The interrupt request for corresponding channel is cleared | ||
| 7190 | * 0b1..The interrupt request for corresponding channel is active | ||
| 7191 | */ | ||
| 7192 | #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) | ||
| 7193 | #define DMA_INT_INT10_MASK (0x400U) | ||
| 7194 | #define DMA_INT_INT10_SHIFT (10U) | ||
| 7195 | /*! INT10 - Interrupt Request 10 | ||
| 7196 | * 0b0..The interrupt request for corresponding channel is cleared | ||
| 7197 | * 0b1..The interrupt request for corresponding channel is active | ||
| 7198 | */ | ||
| 7199 | #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) | ||
| 7200 | #define DMA_INT_INT11_MASK (0x800U) | ||
| 7201 | #define DMA_INT_INT11_SHIFT (11U) | ||
| 7202 | /*! INT11 - Interrupt Request 11 | ||
| 7203 | * 0b0..The interrupt request for corresponding channel is cleared | ||
| 7204 | * 0b1..The interrupt request for corresponding channel is active | ||
| 7205 | */ | ||
| 7206 | #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) | ||
| 7207 | #define DMA_INT_INT12_MASK (0x1000U) | ||
| 7208 | #define DMA_INT_INT12_SHIFT (12U) | ||
| 7209 | /*! INT12 - Interrupt Request 12 | ||
| 7210 | * 0b0..The interrupt request for corresponding channel is cleared | ||
| 7211 | * 0b1..The interrupt request for corresponding channel is active | ||
| 7212 | */ | ||
| 7213 | #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) | ||
| 7214 | #define DMA_INT_INT13_MASK (0x2000U) | ||
| 7215 | #define DMA_INT_INT13_SHIFT (13U) | ||
| 7216 | /*! INT13 - Interrupt Request 13 | ||
| 7217 | * 0b0..The interrupt request for corresponding channel is cleared | ||
| 7218 | * 0b1..The interrupt request for corresponding channel is active | ||
| 7219 | */ | ||
| 7220 | #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) | ||
| 7221 | #define DMA_INT_INT14_MASK (0x4000U) | ||
| 7222 | #define DMA_INT_INT14_SHIFT (14U) | ||
| 7223 | /*! INT14 - Interrupt Request 14 | ||
| 7224 | * 0b0..The interrupt request for corresponding channel is cleared | ||
| 7225 | * 0b1..The interrupt request for corresponding channel is active | ||
| 7226 | */ | ||
| 7227 | #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) | ||
| 7228 | #define DMA_INT_INT15_MASK (0x8000U) | ||
| 7229 | #define DMA_INT_INT15_SHIFT (15U) | ||
| 7230 | /*! INT15 - Interrupt Request 15 | ||
| 7231 | * 0b0..The interrupt request for corresponding channel is cleared | ||
| 7232 | * 0b1..The interrupt request for corresponding channel is active | ||
| 7233 | */ | ||
| 7234 | #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) | ||
| 7235 | /*! @} */ | ||
| 7236 | |||
| 7237 | /*! @name ERR - Error Register */ | ||
| 7238 | /*! @{ */ | ||
| 7239 | #define DMA_ERR_ERR0_MASK (0x1U) | ||
| 7240 | #define DMA_ERR_ERR0_SHIFT (0U) | ||
| 7241 | /*! ERR0 - Error In Channel 0 | ||
| 7242 | * 0b0..An error in the corresponding channel has not occurred | ||
| 7243 | * 0b1..An error in the corresponding channel has occurred | ||
| 7244 | */ | ||
| 7245 | #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) | ||
| 7246 | #define DMA_ERR_ERR1_MASK (0x2U) | ||
| 7247 | #define DMA_ERR_ERR1_SHIFT (1U) | ||
| 7248 | /*! ERR1 - Error In Channel 1 | ||
| 7249 | * 0b0..An error in the corresponding channel has not occurred | ||
| 7250 | * 0b1..An error in the corresponding channel has occurred | ||
| 7251 | */ | ||
| 7252 | #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) | ||
| 7253 | #define DMA_ERR_ERR2_MASK (0x4U) | ||
| 7254 | #define DMA_ERR_ERR2_SHIFT (2U) | ||
| 7255 | /*! ERR2 - Error In Channel 2 | ||
| 7256 | * 0b0..An error in the corresponding channel has not occurred | ||
| 7257 | * 0b1..An error in the corresponding channel has occurred | ||
| 7258 | */ | ||
| 7259 | #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) | ||
| 7260 | #define DMA_ERR_ERR3_MASK (0x8U) | ||
| 7261 | #define DMA_ERR_ERR3_SHIFT (3U) | ||
| 7262 | /*! ERR3 - Error In Channel 3 | ||
| 7263 | * 0b0..An error in the corresponding channel has not occurred | ||
| 7264 | * 0b1..An error in the corresponding channel has occurred | ||
| 7265 | */ | ||
| 7266 | #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) | ||
| 7267 | #define DMA_ERR_ERR4_MASK (0x10U) | ||
| 7268 | #define DMA_ERR_ERR4_SHIFT (4U) | ||
| 7269 | /*! ERR4 - Error In Channel 4 | ||
| 7270 | * 0b0..An error in the corresponding channel has not occurred | ||
| 7271 | * 0b1..An error in the corresponding channel has occurred | ||
| 7272 | */ | ||
| 7273 | #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) | ||
| 7274 | #define DMA_ERR_ERR5_MASK (0x20U) | ||
| 7275 | #define DMA_ERR_ERR5_SHIFT (5U) | ||
| 7276 | /*! ERR5 - Error In Channel 5 | ||
| 7277 | * 0b0..An error in the corresponding channel has not occurred | ||
| 7278 | * 0b1..An error in the corresponding channel has occurred | ||
| 7279 | */ | ||
| 7280 | #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) | ||
| 7281 | #define DMA_ERR_ERR6_MASK (0x40U) | ||
| 7282 | #define DMA_ERR_ERR6_SHIFT (6U) | ||
| 7283 | /*! ERR6 - Error In Channel 6 | ||
| 7284 | * 0b0..An error in the corresponding channel has not occurred | ||
| 7285 | * 0b1..An error in the corresponding channel has occurred | ||
| 7286 | */ | ||
| 7287 | #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) | ||
| 7288 | #define DMA_ERR_ERR7_MASK (0x80U) | ||
| 7289 | #define DMA_ERR_ERR7_SHIFT (7U) | ||
| 7290 | /*! ERR7 - Error In Channel 7 | ||
| 7291 | * 0b0..An error in the corresponding channel has not occurred | ||
| 7292 | * 0b1..An error in the corresponding channel has occurred | ||
| 7293 | */ | ||
| 7294 | #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) | ||
| 7295 | #define DMA_ERR_ERR8_MASK (0x100U) | ||
| 7296 | #define DMA_ERR_ERR8_SHIFT (8U) | ||
| 7297 | /*! ERR8 - Error In Channel 8 | ||
| 7298 | * 0b0..An error in the corresponding channel has not occurred | ||
| 7299 | * 0b1..An error in the corresponding channel has occurred | ||
| 7300 | */ | ||
| 7301 | #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) | ||
| 7302 | #define DMA_ERR_ERR9_MASK (0x200U) | ||
| 7303 | #define DMA_ERR_ERR9_SHIFT (9U) | ||
| 7304 | /*! ERR9 - Error In Channel 9 | ||
| 7305 | * 0b0..An error in the corresponding channel has not occurred | ||
| 7306 | * 0b1..An error in the corresponding channel has occurred | ||
| 7307 | */ | ||
| 7308 | #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) | ||
| 7309 | #define DMA_ERR_ERR10_MASK (0x400U) | ||
| 7310 | #define DMA_ERR_ERR10_SHIFT (10U) | ||
| 7311 | /*! ERR10 - Error In Channel 10 | ||
| 7312 | * 0b0..An error in the corresponding channel has not occurred | ||
| 7313 | * 0b1..An error in the corresponding channel has occurred | ||
| 7314 | */ | ||
| 7315 | #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) | ||
| 7316 | #define DMA_ERR_ERR11_MASK (0x800U) | ||
| 7317 | #define DMA_ERR_ERR11_SHIFT (11U) | ||
| 7318 | /*! ERR11 - Error In Channel 11 | ||
| 7319 | * 0b0..An error in the corresponding channel has not occurred | ||
| 7320 | * 0b1..An error in the corresponding channel has occurred | ||
| 7321 | */ | ||
| 7322 | #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) | ||
| 7323 | #define DMA_ERR_ERR12_MASK (0x1000U) | ||
| 7324 | #define DMA_ERR_ERR12_SHIFT (12U) | ||
| 7325 | /*! ERR12 - Error In Channel 12 | ||
| 7326 | * 0b0..An error in the corresponding channel has not occurred | ||
| 7327 | * 0b1..An error in the corresponding channel has occurred | ||
| 7328 | */ | ||
| 7329 | #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) | ||
| 7330 | #define DMA_ERR_ERR13_MASK (0x2000U) | ||
| 7331 | #define DMA_ERR_ERR13_SHIFT (13U) | ||
| 7332 | /*! ERR13 - Error In Channel 13 | ||
| 7333 | * 0b0..An error in the corresponding channel has not occurred | ||
| 7334 | * 0b1..An error in the corresponding channel has occurred | ||
| 7335 | */ | ||
| 7336 | #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) | ||
| 7337 | #define DMA_ERR_ERR14_MASK (0x4000U) | ||
| 7338 | #define DMA_ERR_ERR14_SHIFT (14U) | ||
| 7339 | /*! ERR14 - Error In Channel 14 | ||
| 7340 | * 0b0..An error in the corresponding channel has not occurred | ||
| 7341 | * 0b1..An error in the corresponding channel has occurred | ||
| 7342 | */ | ||
| 7343 | #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) | ||
| 7344 | #define DMA_ERR_ERR15_MASK (0x8000U) | ||
| 7345 | #define DMA_ERR_ERR15_SHIFT (15U) | ||
| 7346 | /*! ERR15 - Error In Channel 15 | ||
| 7347 | * 0b0..An error in the corresponding channel has not occurred | ||
| 7348 | * 0b1..An error in the corresponding channel has occurred | ||
| 7349 | */ | ||
| 7350 | #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) | ||
| 7351 | /*! @} */ | ||
| 7352 | |||
| 7353 | /*! @name HRS - Hardware Request Status Register */ | ||
| 7354 | /*! @{ */ | ||
| 7355 | #define DMA_HRS_HRS0_MASK (0x1U) | ||
| 7356 | #define DMA_HRS_HRS0_SHIFT (0U) | ||
| 7357 | /*! HRS0 - Hardware Request Status Channel 0 | ||
| 7358 | * 0b0..A hardware service request for channel 0 is not present | ||
| 7359 | * 0b1..A hardware service request for channel 0 is present | ||
| 7360 | */ | ||
| 7361 | #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) | ||
| 7362 | #define DMA_HRS_HRS1_MASK (0x2U) | ||
| 7363 | #define DMA_HRS_HRS1_SHIFT (1U) | ||
| 7364 | /*! HRS1 - Hardware Request Status Channel 1 | ||
| 7365 | * 0b0..A hardware service request for channel 1 is not present | ||
| 7366 | * 0b1..A hardware service request for channel 1 is present | ||
| 7367 | */ | ||
| 7368 | #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) | ||
| 7369 | #define DMA_HRS_HRS2_MASK (0x4U) | ||
| 7370 | #define DMA_HRS_HRS2_SHIFT (2U) | ||
| 7371 | /*! HRS2 - Hardware Request Status Channel 2 | ||
| 7372 | * 0b0..A hardware service request for channel 2 is not present | ||
| 7373 | * 0b1..A hardware service request for channel 2 is present | ||
| 7374 | */ | ||
| 7375 | #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) | ||
| 7376 | #define DMA_HRS_HRS3_MASK (0x8U) | ||
| 7377 | #define DMA_HRS_HRS3_SHIFT (3U) | ||
| 7378 | /*! HRS3 - Hardware Request Status Channel 3 | ||
| 7379 | * 0b0..A hardware service request for channel 3 is not present | ||
| 7380 | * 0b1..A hardware service request for channel 3 is present | ||
| 7381 | */ | ||
| 7382 | #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) | ||
| 7383 | #define DMA_HRS_HRS4_MASK (0x10U) | ||
| 7384 | #define DMA_HRS_HRS4_SHIFT (4U) | ||
| 7385 | /*! HRS4 - Hardware Request Status Channel 4 | ||
| 7386 | * 0b0..A hardware service request for channel 4 is not present | ||
| 7387 | * 0b1..A hardware service request for channel 4 is present | ||
| 7388 | */ | ||
| 7389 | #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) | ||
| 7390 | #define DMA_HRS_HRS5_MASK (0x20U) | ||
| 7391 | #define DMA_HRS_HRS5_SHIFT (5U) | ||
| 7392 | /*! HRS5 - Hardware Request Status Channel 5 | ||
| 7393 | * 0b0..A hardware service request for channel 5 is not present | ||
| 7394 | * 0b1..A hardware service request for channel 5 is present | ||
| 7395 | */ | ||
| 7396 | #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) | ||
| 7397 | #define DMA_HRS_HRS6_MASK (0x40U) | ||
| 7398 | #define DMA_HRS_HRS6_SHIFT (6U) | ||
| 7399 | /*! HRS6 - Hardware Request Status Channel 6 | ||
| 7400 | * 0b0..A hardware service request for channel 6 is not present | ||
| 7401 | * 0b1..A hardware service request for channel 6 is present | ||
| 7402 | */ | ||
| 7403 | #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) | ||
| 7404 | #define DMA_HRS_HRS7_MASK (0x80U) | ||
| 7405 | #define DMA_HRS_HRS7_SHIFT (7U) | ||
| 7406 | /*! HRS7 - Hardware Request Status Channel 7 | ||
| 7407 | * 0b0..A hardware service request for channel 7 is not present | ||
| 7408 | * 0b1..A hardware service request for channel 7 is present | ||
| 7409 | */ | ||
| 7410 | #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) | ||
| 7411 | #define DMA_HRS_HRS8_MASK (0x100U) | ||
| 7412 | #define DMA_HRS_HRS8_SHIFT (8U) | ||
| 7413 | /*! HRS8 - Hardware Request Status Channel 8 | ||
| 7414 | * 0b0..A hardware service request for channel 8 is not present | ||
| 7415 | * 0b1..A hardware service request for channel 8 is present | ||
| 7416 | */ | ||
| 7417 | #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) | ||
| 7418 | #define DMA_HRS_HRS9_MASK (0x200U) | ||
| 7419 | #define DMA_HRS_HRS9_SHIFT (9U) | ||
| 7420 | /*! HRS9 - Hardware Request Status Channel 9 | ||
| 7421 | * 0b0..A hardware service request for channel 9 is not present | ||
| 7422 | * 0b1..A hardware service request for channel 9 is present | ||
| 7423 | */ | ||
| 7424 | #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) | ||
| 7425 | #define DMA_HRS_HRS10_MASK (0x400U) | ||
| 7426 | #define DMA_HRS_HRS10_SHIFT (10U) | ||
| 7427 | /*! HRS10 - Hardware Request Status Channel 10 | ||
| 7428 | * 0b0..A hardware service request for channel 10 is not present | ||
| 7429 | * 0b1..A hardware service request for channel 10 is present | ||
| 7430 | */ | ||
| 7431 | #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) | ||
| 7432 | #define DMA_HRS_HRS11_MASK (0x800U) | ||
| 7433 | #define DMA_HRS_HRS11_SHIFT (11U) | ||
| 7434 | /*! HRS11 - Hardware Request Status Channel 11 | ||
| 7435 | * 0b0..A hardware service request for channel 11 is not present | ||
| 7436 | * 0b1..A hardware service request for channel 11 is present | ||
| 7437 | */ | ||
| 7438 | #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) | ||
| 7439 | #define DMA_HRS_HRS12_MASK (0x1000U) | ||
| 7440 | #define DMA_HRS_HRS12_SHIFT (12U) | ||
| 7441 | /*! HRS12 - Hardware Request Status Channel 12 | ||
| 7442 | * 0b0..A hardware service request for channel 12 is not present | ||
| 7443 | * 0b1..A hardware service request for channel 12 is present | ||
| 7444 | */ | ||
| 7445 | #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) | ||
| 7446 | #define DMA_HRS_HRS13_MASK (0x2000U) | ||
| 7447 | #define DMA_HRS_HRS13_SHIFT (13U) | ||
| 7448 | /*! HRS13 - Hardware Request Status Channel 13 | ||
| 7449 | * 0b0..A hardware service request for channel 13 is not present | ||
| 7450 | * 0b1..A hardware service request for channel 13 is present | ||
| 7451 | */ | ||
| 7452 | #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) | ||
| 7453 | #define DMA_HRS_HRS14_MASK (0x4000U) | ||
| 7454 | #define DMA_HRS_HRS14_SHIFT (14U) | ||
| 7455 | /*! HRS14 - Hardware Request Status Channel 14 | ||
| 7456 | * 0b0..A hardware service request for channel 14 is not present | ||
| 7457 | * 0b1..A hardware service request for channel 14 is present | ||
| 7458 | */ | ||
| 7459 | #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) | ||
| 7460 | #define DMA_HRS_HRS15_MASK (0x8000U) | ||
| 7461 | #define DMA_HRS_HRS15_SHIFT (15U) | ||
| 7462 | /*! HRS15 - Hardware Request Status Channel 15 | ||
| 7463 | * 0b0..A hardware service request for channel 15 is not present | ||
| 7464 | * 0b1..A hardware service request for channel 15 is present | ||
| 7465 | */ | ||
| 7466 | #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) | ||
| 7467 | /*! @} */ | ||
| 7468 | |||
| 7469 | /*! @name DCHPRI3 - Channel n Priority Register */ | ||
| 7470 | /*! @{ */ | ||
| 7471 | #define DMA_DCHPRI3_CHPRI_MASK (0xFU) | ||
| 7472 | #define DMA_DCHPRI3_CHPRI_SHIFT (0U) | ||
| 7473 | #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) | ||
| 7474 | #define DMA_DCHPRI3_DPA_MASK (0x40U) | ||
| 7475 | #define DMA_DCHPRI3_DPA_SHIFT (6U) | ||
| 7476 | /*! DPA - Disable Preempt Ability | ||
| 7477 | * 0b0..Channel n can suspend a lower priority channel | ||
| 7478 | * 0b1..Channel n cannot suspend any channel, regardless of channel priority | ||
| 7479 | */ | ||
| 7480 | #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) | ||
| 7481 | #define DMA_DCHPRI3_ECP_MASK (0x80U) | ||
| 7482 | #define DMA_DCHPRI3_ECP_SHIFT (7U) | ||
| 7483 | /*! ECP - Enable Channel Preemption | ||
| 7484 | * 0b0..Channel n cannot be suspended by a higher priority channel's service request | ||
| 7485 | * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel | ||
| 7486 | */ | ||
| 7487 | #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) | ||
| 7488 | /*! @} */ | ||
| 7489 | |||
| 7490 | /*! @name DCHPRI2 - Channel n Priority Register */ | ||
| 7491 | /*! @{ */ | ||
| 7492 | #define DMA_DCHPRI2_CHPRI_MASK (0xFU) | ||
| 7493 | #define DMA_DCHPRI2_CHPRI_SHIFT (0U) | ||
| 7494 | #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) | ||
| 7495 | #define DMA_DCHPRI2_DPA_MASK (0x40U) | ||
| 7496 | #define DMA_DCHPRI2_DPA_SHIFT (6U) | ||
| 7497 | /*! DPA - Disable Preempt Ability | ||
| 7498 | * 0b0..Channel n can suspend a lower priority channel | ||
| 7499 | * 0b1..Channel n cannot suspend any channel, regardless of channel priority | ||
| 7500 | */ | ||
| 7501 | #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) | ||
| 7502 | #define DMA_DCHPRI2_ECP_MASK (0x80U) | ||
| 7503 | #define DMA_DCHPRI2_ECP_SHIFT (7U) | ||
| 7504 | /*! ECP - Enable Channel Preemption | ||
| 7505 | * 0b0..Channel n cannot be suspended by a higher priority channel's service request | ||
| 7506 | * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel | ||
| 7507 | */ | ||
| 7508 | #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) | ||
| 7509 | /*! @} */ | ||
| 7510 | |||
| 7511 | /*! @name DCHPRI1 - Channel n Priority Register */ | ||
| 7512 | /*! @{ */ | ||
| 7513 | #define DMA_DCHPRI1_CHPRI_MASK (0xFU) | ||
| 7514 | #define DMA_DCHPRI1_CHPRI_SHIFT (0U) | ||
| 7515 | #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) | ||
| 7516 | #define DMA_DCHPRI1_DPA_MASK (0x40U) | ||
| 7517 | #define DMA_DCHPRI1_DPA_SHIFT (6U) | ||
| 7518 | /*! DPA - Disable Preempt Ability | ||
| 7519 | * 0b0..Channel n can suspend a lower priority channel | ||
| 7520 | * 0b1..Channel n cannot suspend any channel, regardless of channel priority | ||
| 7521 | */ | ||
| 7522 | #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) | ||
| 7523 | #define DMA_DCHPRI1_ECP_MASK (0x80U) | ||
| 7524 | #define DMA_DCHPRI1_ECP_SHIFT (7U) | ||
| 7525 | /*! ECP - Enable Channel Preemption | ||
| 7526 | * 0b0..Channel n cannot be suspended by a higher priority channel's service request | ||
| 7527 | * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel | ||
| 7528 | */ | ||
| 7529 | #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) | ||
| 7530 | /*! @} */ | ||
| 7531 | |||
| 7532 | /*! @name DCHPRI0 - Channel n Priority Register */ | ||
| 7533 | /*! @{ */ | ||
| 7534 | #define DMA_DCHPRI0_CHPRI_MASK (0xFU) | ||
| 7535 | #define DMA_DCHPRI0_CHPRI_SHIFT (0U) | ||
| 7536 | #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) | ||
| 7537 | #define DMA_DCHPRI0_DPA_MASK (0x40U) | ||
| 7538 | #define DMA_DCHPRI0_DPA_SHIFT (6U) | ||
| 7539 | /*! DPA - Disable Preempt Ability | ||
| 7540 | * 0b0..Channel n can suspend a lower priority channel | ||
| 7541 | * 0b1..Channel n cannot suspend any channel, regardless of channel priority | ||
| 7542 | */ | ||
| 7543 | #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) | ||
| 7544 | #define DMA_DCHPRI0_ECP_MASK (0x80U) | ||
| 7545 | #define DMA_DCHPRI0_ECP_SHIFT (7U) | ||
| 7546 | /*! ECP - Enable Channel Preemption | ||
| 7547 | * 0b0..Channel n cannot be suspended by a higher priority channel's service request | ||
| 7548 | * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel | ||
| 7549 | */ | ||
| 7550 | #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) | ||
| 7551 | /*! @} */ | ||
| 7552 | |||
| 7553 | /*! @name DCHPRI7 - Channel n Priority Register */ | ||
| 7554 | /*! @{ */ | ||
| 7555 | #define DMA_DCHPRI7_CHPRI_MASK (0xFU) | ||
| 7556 | #define DMA_DCHPRI7_CHPRI_SHIFT (0U) | ||
| 7557 | #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) | ||
| 7558 | #define DMA_DCHPRI7_DPA_MASK (0x40U) | ||
| 7559 | #define DMA_DCHPRI7_DPA_SHIFT (6U) | ||
| 7560 | /*! DPA - Disable Preempt Ability | ||
| 7561 | * 0b0..Channel n can suspend a lower priority channel | ||
| 7562 | * 0b1..Channel n cannot suspend any channel, regardless of channel priority | ||
| 7563 | */ | ||
| 7564 | #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) | ||
| 7565 | #define DMA_DCHPRI7_ECP_MASK (0x80U) | ||
| 7566 | #define DMA_DCHPRI7_ECP_SHIFT (7U) | ||
| 7567 | /*! ECP - Enable Channel Preemption | ||
| 7568 | * 0b0..Channel n cannot be suspended by a higher priority channel's service request | ||
| 7569 | * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel | ||
| 7570 | */ | ||
| 7571 | #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) | ||
| 7572 | /*! @} */ | ||
| 7573 | |||
| 7574 | /*! @name DCHPRI6 - Channel n Priority Register */ | ||
| 7575 | /*! @{ */ | ||
| 7576 | #define DMA_DCHPRI6_CHPRI_MASK (0xFU) | ||
| 7577 | #define DMA_DCHPRI6_CHPRI_SHIFT (0U) | ||
| 7578 | #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) | ||
| 7579 | #define DMA_DCHPRI6_DPA_MASK (0x40U) | ||
| 7580 | #define DMA_DCHPRI6_DPA_SHIFT (6U) | ||
| 7581 | /*! DPA - Disable Preempt Ability | ||
| 7582 | * 0b0..Channel n can suspend a lower priority channel | ||
| 7583 | * 0b1..Channel n cannot suspend any channel, regardless of channel priority | ||
| 7584 | */ | ||
| 7585 | #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) | ||
| 7586 | #define DMA_DCHPRI6_ECP_MASK (0x80U) | ||
| 7587 | #define DMA_DCHPRI6_ECP_SHIFT (7U) | ||
| 7588 | /*! ECP - Enable Channel Preemption | ||
| 7589 | * 0b0..Channel n cannot be suspended by a higher priority channel's service request | ||
| 7590 | * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel | ||
| 7591 | */ | ||
| 7592 | #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) | ||
| 7593 | /*! @} */ | ||
| 7594 | |||
| 7595 | /*! @name DCHPRI5 - Channel n Priority Register */ | ||
| 7596 | /*! @{ */ | ||
| 7597 | #define DMA_DCHPRI5_CHPRI_MASK (0xFU) | ||
| 7598 | #define DMA_DCHPRI5_CHPRI_SHIFT (0U) | ||
| 7599 | #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) | ||
| 7600 | #define DMA_DCHPRI5_DPA_MASK (0x40U) | ||
| 7601 | #define DMA_DCHPRI5_DPA_SHIFT (6U) | ||
| 7602 | /*! DPA - Disable Preempt Ability | ||
| 7603 | * 0b0..Channel n can suspend a lower priority channel | ||
| 7604 | * 0b1..Channel n cannot suspend any channel, regardless of channel priority | ||
| 7605 | */ | ||
| 7606 | #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) | ||
| 7607 | #define DMA_DCHPRI5_ECP_MASK (0x80U) | ||
| 7608 | #define DMA_DCHPRI5_ECP_SHIFT (7U) | ||
| 7609 | /*! ECP - Enable Channel Preemption | ||
| 7610 | * 0b0..Channel n cannot be suspended by a higher priority channel's service request | ||
| 7611 | * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel | ||
| 7612 | */ | ||
| 7613 | #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) | ||
| 7614 | /*! @} */ | ||
| 7615 | |||
| 7616 | /*! @name DCHPRI4 - Channel n Priority Register */ | ||
| 7617 | /*! @{ */ | ||
| 7618 | #define DMA_DCHPRI4_CHPRI_MASK (0xFU) | ||
| 7619 | #define DMA_DCHPRI4_CHPRI_SHIFT (0U) | ||
| 7620 | #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) | ||
| 7621 | #define DMA_DCHPRI4_DPA_MASK (0x40U) | ||
| 7622 | #define DMA_DCHPRI4_DPA_SHIFT (6U) | ||
| 7623 | /*! DPA - Disable Preempt Ability | ||
| 7624 | * 0b0..Channel n can suspend a lower priority channel | ||
| 7625 | * 0b1..Channel n cannot suspend any channel, regardless of channel priority | ||
| 7626 | */ | ||
| 7627 | #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) | ||
| 7628 | #define DMA_DCHPRI4_ECP_MASK (0x80U) | ||
| 7629 | #define DMA_DCHPRI4_ECP_SHIFT (7U) | ||
| 7630 | /*! ECP - Enable Channel Preemption | ||
| 7631 | * 0b0..Channel n cannot be suspended by a higher priority channel's service request | ||
| 7632 | * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel | ||
| 7633 | */ | ||
| 7634 | #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) | ||
| 7635 | /*! @} */ | ||
| 7636 | |||
| 7637 | /*! @name DCHPRI11 - Channel n Priority Register */ | ||
| 7638 | /*! @{ */ | ||
| 7639 | #define DMA_DCHPRI11_CHPRI_MASK (0xFU) | ||
| 7640 | #define DMA_DCHPRI11_CHPRI_SHIFT (0U) | ||
| 7641 | #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) | ||
| 7642 | #define DMA_DCHPRI11_DPA_MASK (0x40U) | ||
| 7643 | #define DMA_DCHPRI11_DPA_SHIFT (6U) | ||
| 7644 | /*! DPA - Disable Preempt Ability | ||
| 7645 | * 0b0..Channel n can suspend a lower priority channel | ||
| 7646 | * 0b1..Channel n cannot suspend any channel, regardless of channel priority | ||
| 7647 | */ | ||
| 7648 | #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) | ||
| 7649 | #define DMA_DCHPRI11_ECP_MASK (0x80U) | ||
| 7650 | #define DMA_DCHPRI11_ECP_SHIFT (7U) | ||
| 7651 | /*! ECP - Enable Channel Preemption | ||
| 7652 | * 0b0..Channel n cannot be suspended by a higher priority channel's service request | ||
| 7653 | * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel | ||
| 7654 | */ | ||
| 7655 | #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) | ||
| 7656 | /*! @} */ | ||
| 7657 | |||
| 7658 | /*! @name DCHPRI10 - Channel n Priority Register */ | ||
| 7659 | /*! @{ */ | ||
| 7660 | #define DMA_DCHPRI10_CHPRI_MASK (0xFU) | ||
| 7661 | #define DMA_DCHPRI10_CHPRI_SHIFT (0U) | ||
| 7662 | #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) | ||
| 7663 | #define DMA_DCHPRI10_DPA_MASK (0x40U) | ||
| 7664 | #define DMA_DCHPRI10_DPA_SHIFT (6U) | ||
| 7665 | /*! DPA - Disable Preempt Ability | ||
| 7666 | * 0b0..Channel n can suspend a lower priority channel | ||
| 7667 | * 0b1..Channel n cannot suspend any channel, regardless of channel priority | ||
| 7668 | */ | ||
| 7669 | #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) | ||
| 7670 | #define DMA_DCHPRI10_ECP_MASK (0x80U) | ||
| 7671 | #define DMA_DCHPRI10_ECP_SHIFT (7U) | ||
| 7672 | /*! ECP - Enable Channel Preemption | ||
| 7673 | * 0b0..Channel n cannot be suspended by a higher priority channel's service request | ||
| 7674 | * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel | ||
| 7675 | */ | ||
| 7676 | #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) | ||
| 7677 | /*! @} */ | ||
| 7678 | |||
| 7679 | /*! @name DCHPRI9 - Channel n Priority Register */ | ||
| 7680 | /*! @{ */ | ||
| 7681 | #define DMA_DCHPRI9_CHPRI_MASK (0xFU) | ||
| 7682 | #define DMA_DCHPRI9_CHPRI_SHIFT (0U) | ||
| 7683 | #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) | ||
| 7684 | #define DMA_DCHPRI9_DPA_MASK (0x40U) | ||
| 7685 | #define DMA_DCHPRI9_DPA_SHIFT (6U) | ||
| 7686 | /*! DPA - Disable Preempt Ability | ||
| 7687 | * 0b0..Channel n can suspend a lower priority channel | ||
| 7688 | * 0b1..Channel n cannot suspend any channel, regardless of channel priority | ||
| 7689 | */ | ||
| 7690 | #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) | ||
| 7691 | #define DMA_DCHPRI9_ECP_MASK (0x80U) | ||
| 7692 | #define DMA_DCHPRI9_ECP_SHIFT (7U) | ||
| 7693 | /*! ECP - Enable Channel Preemption | ||
| 7694 | * 0b0..Channel n cannot be suspended by a higher priority channel's service request | ||
| 7695 | * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel | ||
| 7696 | */ | ||
| 7697 | #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) | ||
| 7698 | /*! @} */ | ||
| 7699 | |||
| 7700 | /*! @name DCHPRI8 - Channel n Priority Register */ | ||
| 7701 | /*! @{ */ | ||
| 7702 | #define DMA_DCHPRI8_CHPRI_MASK (0xFU) | ||
| 7703 | #define DMA_DCHPRI8_CHPRI_SHIFT (0U) | ||
| 7704 | #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) | ||
| 7705 | #define DMA_DCHPRI8_DPA_MASK (0x40U) | ||
| 7706 | #define DMA_DCHPRI8_DPA_SHIFT (6U) | ||
| 7707 | /*! DPA - Disable Preempt Ability | ||
| 7708 | * 0b0..Channel n can suspend a lower priority channel | ||
| 7709 | * 0b1..Channel n cannot suspend any channel, regardless of channel priority | ||
| 7710 | */ | ||
| 7711 | #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) | ||
| 7712 | #define DMA_DCHPRI8_ECP_MASK (0x80U) | ||
| 7713 | #define DMA_DCHPRI8_ECP_SHIFT (7U) | ||
| 7714 | /*! ECP - Enable Channel Preemption | ||
| 7715 | * 0b0..Channel n cannot be suspended by a higher priority channel's service request | ||
| 7716 | * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel | ||
| 7717 | */ | ||
| 7718 | #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) | ||
| 7719 | /*! @} */ | ||
| 7720 | |||
| 7721 | /*! @name DCHPRI15 - Channel n Priority Register */ | ||
| 7722 | /*! @{ */ | ||
| 7723 | #define DMA_DCHPRI15_CHPRI_MASK (0xFU) | ||
| 7724 | #define DMA_DCHPRI15_CHPRI_SHIFT (0U) | ||
| 7725 | #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) | ||
| 7726 | #define DMA_DCHPRI15_DPA_MASK (0x40U) | ||
| 7727 | #define DMA_DCHPRI15_DPA_SHIFT (6U) | ||
| 7728 | /*! DPA - Disable Preempt Ability | ||
| 7729 | * 0b0..Channel n can suspend a lower priority channel | ||
| 7730 | * 0b1..Channel n cannot suspend any channel, regardless of channel priority | ||
| 7731 | */ | ||
| 7732 | #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) | ||
| 7733 | #define DMA_DCHPRI15_ECP_MASK (0x80U) | ||
| 7734 | #define DMA_DCHPRI15_ECP_SHIFT (7U) | ||
| 7735 | /*! ECP - Enable Channel Preemption | ||
| 7736 | * 0b0..Channel n cannot be suspended by a higher priority channel's service request | ||
| 7737 | * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel | ||
| 7738 | */ | ||
| 7739 | #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) | ||
| 7740 | /*! @} */ | ||
| 7741 | |||
| 7742 | /*! @name DCHPRI14 - Channel n Priority Register */ | ||
| 7743 | /*! @{ */ | ||
| 7744 | #define DMA_DCHPRI14_CHPRI_MASK (0xFU) | ||
| 7745 | #define DMA_DCHPRI14_CHPRI_SHIFT (0U) | ||
| 7746 | #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) | ||
| 7747 | #define DMA_DCHPRI14_DPA_MASK (0x40U) | ||
| 7748 | #define DMA_DCHPRI14_DPA_SHIFT (6U) | ||
| 7749 | /*! DPA - Disable Preempt Ability | ||
| 7750 | * 0b0..Channel n can suspend a lower priority channel | ||
| 7751 | * 0b1..Channel n cannot suspend any channel, regardless of channel priority | ||
| 7752 | */ | ||
| 7753 | #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) | ||
| 7754 | #define DMA_DCHPRI14_ECP_MASK (0x80U) | ||
| 7755 | #define DMA_DCHPRI14_ECP_SHIFT (7U) | ||
| 7756 | /*! ECP - Enable Channel Preemption | ||
| 7757 | * 0b0..Channel n cannot be suspended by a higher priority channel's service request | ||
| 7758 | * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel | ||
| 7759 | */ | ||
| 7760 | #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) | ||
| 7761 | /*! @} */ | ||
| 7762 | |||
| 7763 | /*! @name DCHPRI13 - Channel n Priority Register */ | ||
| 7764 | /*! @{ */ | ||
| 7765 | #define DMA_DCHPRI13_CHPRI_MASK (0xFU) | ||
| 7766 | #define DMA_DCHPRI13_CHPRI_SHIFT (0U) | ||
| 7767 | #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) | ||
| 7768 | #define DMA_DCHPRI13_DPA_MASK (0x40U) | ||
| 7769 | #define DMA_DCHPRI13_DPA_SHIFT (6U) | ||
| 7770 | /*! DPA - Disable Preempt Ability | ||
| 7771 | * 0b0..Channel n can suspend a lower priority channel | ||
| 7772 | * 0b1..Channel n cannot suspend any channel, regardless of channel priority | ||
| 7773 | */ | ||
| 7774 | #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) | ||
| 7775 | #define DMA_DCHPRI13_ECP_MASK (0x80U) | ||
| 7776 | #define DMA_DCHPRI13_ECP_SHIFT (7U) | ||
| 7777 | /*! ECP - Enable Channel Preemption | ||
| 7778 | * 0b0..Channel n cannot be suspended by a higher priority channel's service request | ||
| 7779 | * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel | ||
| 7780 | */ | ||
| 7781 | #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) | ||
| 7782 | /*! @} */ | ||
| 7783 | |||
| 7784 | /*! @name DCHPRI12 - Channel n Priority Register */ | ||
| 7785 | /*! @{ */ | ||
| 7786 | #define DMA_DCHPRI12_CHPRI_MASK (0xFU) | ||
| 7787 | #define DMA_DCHPRI12_CHPRI_SHIFT (0U) | ||
| 7788 | #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) | ||
| 7789 | #define DMA_DCHPRI12_DPA_MASK (0x40U) | ||
| 7790 | #define DMA_DCHPRI12_DPA_SHIFT (6U) | ||
| 7791 | /*! DPA - Disable Preempt Ability | ||
| 7792 | * 0b0..Channel n can suspend a lower priority channel | ||
| 7793 | * 0b1..Channel n cannot suspend any channel, regardless of channel priority | ||
| 7794 | */ | ||
| 7795 | #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) | ||
| 7796 | #define DMA_DCHPRI12_ECP_MASK (0x80U) | ||
| 7797 | #define DMA_DCHPRI12_ECP_SHIFT (7U) | ||
| 7798 | /*! ECP - Enable Channel Preemption | ||
| 7799 | * 0b0..Channel n cannot be suspended by a higher priority channel's service request | ||
| 7800 | * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel | ||
| 7801 | */ | ||
| 7802 | #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) | ||
| 7803 | /*! @} */ | ||
| 7804 | |||
| 7805 | /*! @name SADDR - TCD Source Address */ | ||
| 7806 | /*! @{ */ | ||
| 7807 | #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) | ||
| 7808 | #define DMA_SADDR_SADDR_SHIFT (0U) | ||
| 7809 | #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) | ||
| 7810 | /*! @} */ | ||
| 7811 | |||
| 7812 | /* The count of DMA_SADDR */ | ||
| 7813 | #define DMA_SADDR_COUNT (16U) | ||
| 7814 | |||
| 7815 | /*! @name SOFF - TCD Signed Source Address Offset */ | ||
| 7816 | /*! @{ */ | ||
| 7817 | #define DMA_SOFF_SOFF_MASK (0xFFFFU) | ||
| 7818 | #define DMA_SOFF_SOFF_SHIFT (0U) | ||
| 7819 | #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) | ||
| 7820 | /*! @} */ | ||
| 7821 | |||
| 7822 | /* The count of DMA_SOFF */ | ||
| 7823 | #define DMA_SOFF_COUNT (16U) | ||
| 7824 | |||
| 7825 | /*! @name ATTR - TCD Transfer Attributes */ | ||
| 7826 | /*! @{ */ | ||
| 7827 | #define DMA_ATTR_DSIZE_MASK (0x7U) | ||
| 7828 | #define DMA_ATTR_DSIZE_SHIFT (0U) | ||
| 7829 | #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) | ||
| 7830 | #define DMA_ATTR_DMOD_MASK (0xF8U) | ||
| 7831 | #define DMA_ATTR_DMOD_SHIFT (3U) | ||
| 7832 | #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) | ||
| 7833 | #define DMA_ATTR_SSIZE_MASK (0x700U) | ||
| 7834 | #define DMA_ATTR_SSIZE_SHIFT (8U) | ||
| 7835 | /*! SSIZE - Source data transfer size | ||
| 7836 | * 0b000..8-bit | ||
| 7837 | * 0b001..16-bit | ||
| 7838 | * 0b010..32-bit | ||
| 7839 | * 0b011..Reserved | ||
| 7840 | * 0b100..16-byte | ||
| 7841 | * 0b101..32-byte | ||
| 7842 | * 0b110..Reserved | ||
| 7843 | * 0b111..Reserved | ||
| 7844 | */ | ||
| 7845 | #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) | ||
| 7846 | #define DMA_ATTR_SMOD_MASK (0xF800U) | ||
| 7847 | #define DMA_ATTR_SMOD_SHIFT (11U) | ||
| 7848 | /*! SMOD - Source Address Modulo. | ||
| 7849 | * 0b00000..Source address modulo feature is disabled | ||
| 7850 | */ | ||
| 7851 | #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) | ||
| 7852 | /*! @} */ | ||
| 7853 | |||
| 7854 | /* The count of DMA_ATTR */ | ||
| 7855 | #define DMA_ATTR_COUNT (16U) | ||
| 7856 | |||
| 7857 | /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */ | ||
| 7858 | /*! @{ */ | ||
| 7859 | #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) | ||
| 7860 | #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) | ||
| 7861 | #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) | ||
| 7862 | /*! @} */ | ||
| 7863 | |||
| 7864 | /* The count of DMA_NBYTES_MLNO */ | ||
| 7865 | #define DMA_NBYTES_MLNO_COUNT (16U) | ||
| 7866 | |||
| 7867 | /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */ | ||
| 7868 | /*! @{ */ | ||
| 7869 | #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) | ||
| 7870 | #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) | ||
| 7871 | #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) | ||
| 7872 | #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) | ||
| 7873 | #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) | ||
| 7874 | /*! DMLOE - Destination Minor Loop Offset enable | ||
| 7875 | * 0b0..The minor loop offset is not applied to the DADDR | ||
| 7876 | * 0b1..The minor loop offset is applied to the DADDR | ||
| 7877 | */ | ||
| 7878 | #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) | ||
| 7879 | #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) | ||
| 7880 | #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) | ||
| 7881 | /*! SMLOE - Source Minor Loop Offset Enable | ||
| 7882 | * 0b0..The minor loop offset is not applied to the SADDR | ||
| 7883 | * 0b1..The minor loop offset is applied to the SADDR | ||
| 7884 | */ | ||
| 7885 | #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) | ||
| 7886 | /*! @} */ | ||
| 7887 | |||
| 7888 | /* The count of DMA_NBYTES_MLOFFNO */ | ||
| 7889 | #define DMA_NBYTES_MLOFFNO_COUNT (16U) | ||
| 7890 | |||
| 7891 | /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */ | ||
| 7892 | /*! @{ */ | ||
| 7893 | #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) | ||
| 7894 | #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) | ||
| 7895 | #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) | ||
| 7896 | #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) | ||
| 7897 | #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) | ||
| 7898 | #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) | ||
| 7899 | #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) | ||
| 7900 | #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) | ||
| 7901 | /*! DMLOE - Destination Minor Loop Offset enable | ||
| 7902 | * 0b0..The minor loop offset is not applied to the DADDR | ||
| 7903 | * 0b1..The minor loop offset is applied to the DADDR | ||
| 7904 | */ | ||
| 7905 | #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) | ||
| 7906 | #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) | ||
| 7907 | #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) | ||
| 7908 | /*! SMLOE - Source Minor Loop Offset Enable | ||
| 7909 | * 0b0..The minor loop offset is not applied to the SADDR | ||
| 7910 | * 0b1..The minor loop offset is applied to the SADDR | ||
| 7911 | */ | ||
| 7912 | #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) | ||
| 7913 | /*! @} */ | ||
| 7914 | |||
| 7915 | /* The count of DMA_NBYTES_MLOFFYES */ | ||
| 7916 | #define DMA_NBYTES_MLOFFYES_COUNT (16U) | ||
| 7917 | |||
| 7918 | /*! @name SLAST - TCD Last Source Address Adjustment */ | ||
| 7919 | /*! @{ */ | ||
| 7920 | #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) | ||
| 7921 | #define DMA_SLAST_SLAST_SHIFT (0U) | ||
| 7922 | #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) | ||
| 7923 | /*! @} */ | ||
| 7924 | |||
| 7925 | /* The count of DMA_SLAST */ | ||
| 7926 | #define DMA_SLAST_COUNT (16U) | ||
| 7927 | |||
| 7928 | /*! @name DADDR - TCD Destination Address */ | ||
| 7929 | /*! @{ */ | ||
| 7930 | #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) | ||
| 7931 | #define DMA_DADDR_DADDR_SHIFT (0U) | ||
| 7932 | #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) | ||
| 7933 | /*! @} */ | ||
| 7934 | |||
| 7935 | /* The count of DMA_DADDR */ | ||
| 7936 | #define DMA_DADDR_COUNT (16U) | ||
| 7937 | |||
| 7938 | /*! @name DOFF - TCD Signed Destination Address Offset */ | ||
| 7939 | /*! @{ */ | ||
| 7940 | #define DMA_DOFF_DOFF_MASK (0xFFFFU) | ||
| 7941 | #define DMA_DOFF_DOFF_SHIFT (0U) | ||
| 7942 | #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) | ||
| 7943 | /*! @} */ | ||
| 7944 | |||
| 7945 | /* The count of DMA_DOFF */ | ||
| 7946 | #define DMA_DOFF_COUNT (16U) | ||
| 7947 | |||
| 7948 | /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ | ||
| 7949 | /*! @{ */ | ||
| 7950 | #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) | ||
| 7951 | #define DMA_CITER_ELINKNO_CITER_SHIFT (0U) | ||
| 7952 | #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) | ||
| 7953 | #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) | ||
| 7954 | #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) | ||
| 7955 | /*! ELINK - Enable channel-to-channel linking on minor-loop complete | ||
| 7956 | * 0b0..The channel-to-channel linking is disabled | ||
| 7957 | * 0b1..The channel-to-channel linking is enabled | ||
| 7958 | */ | ||
| 7959 | #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) | ||
| 7960 | /*! @} */ | ||
| 7961 | |||
| 7962 | /* The count of DMA_CITER_ELINKNO */ | ||
| 7963 | #define DMA_CITER_ELINKNO_COUNT (16U) | ||
| 7964 | |||
| 7965 | /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ | ||
| 7966 | /*! @{ */ | ||
| 7967 | #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) | ||
| 7968 | #define DMA_CITER_ELINKYES_CITER_SHIFT (0U) | ||
| 7969 | #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) | ||
| 7970 | #define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U) | ||
| 7971 | #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) | ||
| 7972 | #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) | ||
| 7973 | #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) | ||
| 7974 | #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) | ||
| 7975 | /*! ELINK - Enable channel-to-channel linking on minor-loop complete | ||
| 7976 | * 0b0..The channel-to-channel linking is disabled | ||
| 7977 | * 0b1..The channel-to-channel linking is enabled | ||
| 7978 | */ | ||
| 7979 | #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) | ||
| 7980 | /*! @} */ | ||
| 7981 | |||
| 7982 | /* The count of DMA_CITER_ELINKYES */ | ||
| 7983 | #define DMA_CITER_ELINKYES_COUNT (16U) | ||
| 7984 | |||
| 7985 | /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ | ||
| 7986 | /*! @{ */ | ||
| 7987 | #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) | ||
| 7988 | #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) | ||
| 7989 | #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) | ||
| 7990 | /*! @} */ | ||
| 7991 | |||
| 7992 | /* The count of DMA_DLAST_SGA */ | ||
| 7993 | #define DMA_DLAST_SGA_COUNT (16U) | ||
| 7994 | |||
| 7995 | /*! @name CSR - TCD Control and Status */ | ||
| 7996 | /*! @{ */ | ||
| 7997 | #define DMA_CSR_START_MASK (0x1U) | ||
| 7998 | #define DMA_CSR_START_SHIFT (0U) | ||
| 7999 | /*! START - Channel Start | ||
| 8000 | * 0b0..The channel is not explicitly started | ||
| 8001 | * 0b1..The channel is explicitly started via a software initiated service request | ||
| 8002 | */ | ||
| 8003 | #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) | ||
| 8004 | #define DMA_CSR_INTMAJOR_MASK (0x2U) | ||
| 8005 | #define DMA_CSR_INTMAJOR_SHIFT (1U) | ||
| 8006 | /*! INTMAJOR - Enable an interrupt when major iteration count completes | ||
| 8007 | * 0b0..The end-of-major loop interrupt is disabled | ||
| 8008 | * 0b1..The end-of-major loop interrupt is enabled | ||
| 8009 | */ | ||
| 8010 | #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) | ||
| 8011 | #define DMA_CSR_INTHALF_MASK (0x4U) | ||
| 8012 | #define DMA_CSR_INTHALF_SHIFT (2U) | ||
| 8013 | /*! INTHALF - Enable an interrupt when major counter is half complete. | ||
| 8014 | * 0b0..The half-point interrupt is disabled | ||
| 8015 | * 0b1..The half-point interrupt is enabled | ||
| 8016 | */ | ||
| 8017 | #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) | ||
| 8018 | #define DMA_CSR_DREQ_MASK (0x8U) | ||
| 8019 | #define DMA_CSR_DREQ_SHIFT (3U) | ||
| 8020 | /*! DREQ - Disable Request | ||
| 8021 | * 0b0..The channel's ERQ bit is not affected | ||
| 8022 | * 0b1..The channel's ERQ bit is cleared when the major loop is complete | ||
| 8023 | */ | ||
| 8024 | #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) | ||
| 8025 | #define DMA_CSR_ESG_MASK (0x10U) | ||
| 8026 | #define DMA_CSR_ESG_SHIFT (4U) | ||
| 8027 | /*! ESG - Enable Scatter/Gather Processing | ||
| 8028 | * 0b0..The current channel's TCD is normal format. | ||
| 8029 | * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. | ||
| 8030 | */ | ||
| 8031 | #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) | ||
| 8032 | #define DMA_CSR_MAJORELINK_MASK (0x20U) | ||
| 8033 | #define DMA_CSR_MAJORELINK_SHIFT (5U) | ||
| 8034 | /*! MAJORELINK - Enable channel-to-channel linking on major loop complete | ||
| 8035 | * 0b0..The channel-to-channel linking is disabled | ||
| 8036 | * 0b1..The channel-to-channel linking is enabled | ||
| 8037 | */ | ||
| 8038 | #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) | ||
| 8039 | #define DMA_CSR_ACTIVE_MASK (0x40U) | ||
| 8040 | #define DMA_CSR_ACTIVE_SHIFT (6U) | ||
| 8041 | #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) | ||
| 8042 | #define DMA_CSR_DONE_MASK (0x80U) | ||
| 8043 | #define DMA_CSR_DONE_SHIFT (7U) | ||
| 8044 | #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) | ||
| 8045 | #define DMA_CSR_MAJORLINKCH_MASK (0xF00U) | ||
| 8046 | #define DMA_CSR_MAJORLINKCH_SHIFT (8U) | ||
| 8047 | #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) | ||
| 8048 | #define DMA_CSR_BWC_MASK (0xC000U) | ||
| 8049 | #define DMA_CSR_BWC_SHIFT (14U) | ||
| 8050 | /*! BWC - Bandwidth Control | ||
| 8051 | * 0b00..No eDMA engine stalls | ||
| 8052 | * 0b01..Reserved | ||
| 8053 | * 0b10..eDMA engine stalls for 4 cycles after each r/w | ||
| 8054 | * 0b11..eDMA engine stalls for 8 cycles after each r/w | ||
| 8055 | */ | ||
| 8056 | #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) | ||
| 8057 | /*! @} */ | ||
| 8058 | |||
| 8059 | /* The count of DMA_CSR */ | ||
| 8060 | #define DMA_CSR_COUNT (16U) | ||
| 8061 | |||
| 8062 | /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ | ||
| 8063 | /*! @{ */ | ||
| 8064 | #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) | ||
| 8065 | #define DMA_BITER_ELINKNO_BITER_SHIFT (0U) | ||
| 8066 | #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) | ||
| 8067 | #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) | ||
| 8068 | #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) | ||
| 8069 | /*! ELINK - Enables channel-to-channel linking on minor loop complete | ||
| 8070 | * 0b0..The channel-to-channel linking is disabled | ||
| 8071 | * 0b1..The channel-to-channel linking is enabled | ||
| 8072 | */ | ||
| 8073 | #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) | ||
| 8074 | /*! @} */ | ||
| 8075 | |||
| 8076 | /* The count of DMA_BITER_ELINKNO */ | ||
| 8077 | #define DMA_BITER_ELINKNO_COUNT (16U) | ||
| 8078 | |||
| 8079 | /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ | ||
| 8080 | /*! @{ */ | ||
| 8081 | #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) | ||
| 8082 | #define DMA_BITER_ELINKYES_BITER_SHIFT (0U) | ||
| 8083 | #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) | ||
| 8084 | #define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U) | ||
| 8085 | #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) | ||
| 8086 | #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) | ||
| 8087 | #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) | ||
| 8088 | #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) | ||
| 8089 | /*! ELINK - Enables channel-to-channel linking on minor loop complete | ||
| 8090 | * 0b0..The channel-to-channel linking is disabled | ||
| 8091 | * 0b1..The channel-to-channel linking is enabled | ||
| 8092 | */ | ||
| 8093 | #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) | ||
| 8094 | /*! @} */ | ||
| 8095 | |||
| 8096 | /* The count of DMA_BITER_ELINKYES */ | ||
| 8097 | #define DMA_BITER_ELINKYES_COUNT (16U) | ||
| 8098 | |||
| 8099 | |||
| 8100 | /*! | ||
| 8101 | * @} | ||
| 8102 | */ /* end of group DMA_Register_Masks */ | ||
| 8103 | |||
| 8104 | |||
| 8105 | /* DMA - Peripheral instance base addresses */ | ||
| 8106 | /** Peripheral DMA base address */ | ||
| 8107 | #define DMA_BASE (0x40008000u) | ||
| 8108 | /** Peripheral DMA base pointer */ | ||
| 8109 | #define DMA0 ((DMA_Type *)DMA_BASE) | ||
| 8110 | /** Array initializer of DMA peripheral base addresses */ | ||
| 8111 | #define DMA_BASE_ADDRS { DMA_BASE } | ||
| 8112 | /** Array initializer of DMA peripheral base pointers */ | ||
| 8113 | #define DMA_BASE_PTRS { DMA0 } | ||
| 8114 | /** Interrupt vectors for the DMA peripheral type */ | ||
| 8115 | #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } } | ||
| 8116 | #define DMA_ERROR_IRQS { DMA_Error_IRQn } | ||
| 8117 | |||
| 8118 | /*! | ||
| 8119 | * @} | ||
| 8120 | */ /* end of group DMA_Peripheral_Access_Layer */ | ||
| 8121 | |||
| 8122 | |||
| 8123 | /* ---------------------------------------------------------------------------- | ||
| 8124 | -- DMAMUX Peripheral Access Layer | ||
| 8125 | ---------------------------------------------------------------------------- */ | ||
| 8126 | |||
| 8127 | /*! | ||
| 8128 | * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer | ||
| 8129 | * @{ | ||
| 8130 | */ | ||
| 8131 | |||
| 8132 | /** DMAMUX - Register Layout Typedef */ | ||
| 8133 | typedef struct { | ||
| 8134 | __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ | ||
| 8135 | } DMAMUX_Type; | ||
| 8136 | |||
| 8137 | /* ---------------------------------------------------------------------------- | ||
| 8138 | -- DMAMUX Register Masks | ||
| 8139 | ---------------------------------------------------------------------------- */ | ||
| 8140 | |||
| 8141 | /*! | ||
| 8142 | * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks | ||
| 8143 | * @{ | ||
| 8144 | */ | ||
| 8145 | |||
| 8146 | /*! @name CHCFG - Channel Configuration register */ | ||
| 8147 | /*! @{ */ | ||
| 8148 | #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) | ||
| 8149 | #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) | ||
| 8150 | /*! SOURCE - DMA Channel Source (Slot) | ||
| 8151 | * 0b000000..Disable_Signal | ||
| 8152 | * 0b000010..UART0_Rx_Signal | ||
| 8153 | * 0b000011..UART0_Tx_Signal | ||
| 8154 | * 0b000100..UART1_Rx_Signal | ||
| 8155 | * 0b000101..UART1_Tx_Signal | ||
| 8156 | * 0b000110..UART2_Rx_Signal | ||
| 8157 | * 0b000111..UART2_Tx_Signal | ||
| 8158 | * 0b001000..UART3_Rx_Signal | ||
| 8159 | * 0b001001..UART3_Tx_Signal | ||
| 8160 | * 0b001010..UART4_Signal | ||
| 8161 | * 0b001011..UART5_Signal | ||
| 8162 | * 0b001100..I2S0_Rx_Signal | ||
| 8163 | * 0b001101..I2S0_Tx_Signal | ||
| 8164 | * 0b001110..SPI0_Rx_Signal | ||
| 8165 | * 0b001111..SPI0_Tx_Signal | ||
| 8166 | * 0b010000..SPI1_Signal | ||
| 8167 | * 0b010001..SPI2_Signal | ||
| 8168 | * 0b010010..I2C0_Signal | ||
| 8169 | * 0b010011..I2C1_I2C2_Signal | ||
| 8170 | * 0b010100..FTM0_Channel0_Signal | ||
| 8171 | * 0b010101..FTM0_Channel1_Signal | ||
| 8172 | * 0b010110..FTM0_Channel2_Signal | ||
| 8173 | * 0b010111..FTM0_Channel3_Signal | ||
| 8174 | * 0b011000..FTM0_Channel4_Signal | ||
| 8175 | * 0b011001..FTM0_Channel5_Signal | ||
| 8176 | * 0b011010..FTM0_Channel6_Signal | ||
| 8177 | * 0b011011..FTM0_Channel7_Signal | ||
| 8178 | * 0b011100..FTM1_Channel0_Signal | ||
| 8179 | * 0b011101..FTM1_Channel1_Signal | ||
| 8180 | * 0b011110..FTM2_Channel0_Signal | ||
| 8181 | * 0b011111..FTM2_Channel1_Signal | ||
| 8182 | * 0b100000..FTM3_Channel0_Signal | ||
| 8183 | * 0b100001..FTM3_Channel1_Signal | ||
| 8184 | * 0b100010..FTM3_Channel2_Signal | ||
| 8185 | * 0b100011..FTM3_Channel3_Signal | ||
| 8186 | * 0b100100..FTM3_Channel4_Signal | ||
| 8187 | * 0b100101..FTM3_Channel5_Signal | ||
| 8188 | * 0b100110..FTM3_Channel6_Signal | ||
| 8189 | * 0b100111..FTM3_Channel7_Signal | ||
| 8190 | * 0b101000..ADC0_Signal | ||
| 8191 | * 0b101001..ADC1_Signal | ||
| 8192 | * 0b101010..CMP0_Signal | ||
| 8193 | * 0b101011..CMP1_Signal | ||
| 8194 | * 0b101100..CMP2_Signal | ||
| 8195 | * 0b101101..DAC0_Signal | ||
| 8196 | * 0b101110..DAC1_Signal | ||
| 8197 | * 0b101111..CMT_Signal | ||
| 8198 | * 0b110000..PDB_Signal | ||
| 8199 | * 0b110001..PortA_Signal | ||
| 8200 | * 0b110010..PortB_Signal | ||
| 8201 | * 0b110011..PortC_Signal | ||
| 8202 | * 0b110100..PortD_Signal | ||
| 8203 | * 0b110101..PortE_Signal | ||
| 8204 | * 0b110110..IEEE1588Timer0_Signal | ||
| 8205 | * 0b110111..IEEE1588Timer1_Signal | ||
| 8206 | * 0b111000..IEEE1588Timer2_Signal | ||
| 8207 | * 0b111001..IEEE1588Timer3_Signal | ||
| 8208 | * 0b111010..AlwaysOn58_Signal | ||
| 8209 | * 0b111011..AlwaysOn59_Signal | ||
| 8210 | * 0b111100..AlwaysOn60_Signal | ||
| 8211 | * 0b111101..AlwaysOn61_Signal | ||
| 8212 | * 0b111110..AlwaysOn62_Signal | ||
| 8213 | * 0b111111..AlwaysOn63_Signal | ||
| 8214 | */ | ||
| 8215 | #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) | ||
| 8216 | #define DMAMUX_CHCFG_TRIG_MASK (0x40U) | ||
| 8217 | #define DMAMUX_CHCFG_TRIG_SHIFT (6U) | ||
| 8218 | /*! TRIG - DMA Channel Trigger Enable | ||
| 8219 | * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) | ||
| 8220 | * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. | ||
| 8221 | */ | ||
| 8222 | #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) | ||
| 8223 | #define DMAMUX_CHCFG_ENBL_MASK (0x80U) | ||
| 8224 | #define DMAMUX_CHCFG_ENBL_SHIFT (7U) | ||
| 8225 | /*! ENBL - DMA Channel Enable | ||
| 8226 | * 0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. | ||
| 8227 | * 0b1..DMA channel is enabled | ||
| 8228 | */ | ||
| 8229 | #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) | ||
| 8230 | /*! @} */ | ||
| 8231 | |||
| 8232 | /* The count of DMAMUX_CHCFG */ | ||
| 8233 | #define DMAMUX_CHCFG_COUNT (16U) | ||
| 8234 | |||
| 8235 | |||
| 8236 | /*! | ||
| 8237 | * @} | ||
| 8238 | */ /* end of group DMAMUX_Register_Masks */ | ||
| 8239 | |||
| 8240 | |||
| 8241 | /* DMAMUX - Peripheral instance base addresses */ | ||
| 8242 | /** Peripheral DMAMUX base address */ | ||
| 8243 | #define DMAMUX_BASE (0x40021000u) | ||
| 8244 | /** Peripheral DMAMUX base pointer */ | ||
| 8245 | #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) | ||
| 8246 | /** Array initializer of DMAMUX peripheral base addresses */ | ||
| 8247 | #define DMAMUX_BASE_ADDRS { DMAMUX_BASE } | ||
| 8248 | /** Array initializer of DMAMUX peripheral base pointers */ | ||
| 8249 | #define DMAMUX_BASE_PTRS { DMAMUX } | ||
| 8250 | |||
| 8251 | /*! | ||
| 8252 | * @} | ||
| 8253 | */ /* end of group DMAMUX_Peripheral_Access_Layer */ | ||
| 8254 | |||
| 8255 | |||
| 8256 | /* ---------------------------------------------------------------------------- | ||
| 8257 | -- ENET Peripheral Access Layer | ||
| 8258 | ---------------------------------------------------------------------------- */ | ||
| 8259 | |||
| 8260 | /*! | ||
| 8261 | * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer | ||
| 8262 | * @{ | ||
| 8263 | */ | ||
| 8264 | |||
| 8265 | /** ENET - Register Layout Typedef */ | ||
| 8266 | typedef struct { | ||
| 8267 | uint8_t RESERVED_0[4]; | ||
| 8268 | __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ | ||
| 8269 | __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ | ||
| 8270 | uint8_t RESERVED_1[4]; | ||
| 8271 | __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */ | ||
| 8272 | __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */ | ||
| 8273 | uint8_t RESERVED_2[12]; | ||
| 8274 | __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ | ||
| 8275 | uint8_t RESERVED_3[24]; | ||
| 8276 | __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ | ||
| 8277 | __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ | ||
| 8278 | uint8_t RESERVED_4[28]; | ||
| 8279 | __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ | ||
| 8280 | uint8_t RESERVED_5[28]; | ||
| 8281 | __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ | ||
| 8282 | uint8_t RESERVED_6[60]; | ||
| 8283 | __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ | ||
| 8284 | uint8_t RESERVED_7[28]; | ||
| 8285 | __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ | ||
| 8286 | __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ | ||
| 8287 | __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ | ||
| 8288 | uint8_t RESERVED_8[40]; | ||
| 8289 | __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ | ||
| 8290 | __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ | ||
| 8291 | __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ | ||
| 8292 | __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ | ||
| 8293 | uint8_t RESERVED_9[28]; | ||
| 8294 | __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ | ||
| 8295 | uint8_t RESERVED_10[56]; | ||
| 8296 | __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */ | ||
| 8297 | __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */ | ||
| 8298 | __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */ | ||
| 8299 | uint8_t RESERVED_11[4]; | ||
| 8300 | __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ | ||
| 8301 | __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ | ||
| 8302 | __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ | ||
| 8303 | __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ | ||
| 8304 | __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ | ||
| 8305 | __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ | ||
| 8306 | __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ | ||
| 8307 | __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ | ||
| 8308 | __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ | ||
| 8309 | uint8_t RESERVED_12[12]; | ||
| 8310 | __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ | ||
| 8311 | __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ | ||
| 8312 | uint8_t RESERVED_13[60]; | ||
| 8313 | __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ | ||
| 8314 | __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ | ||
| 8315 | __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ | ||
| 8316 | __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ | ||
| 8317 | __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ | ||
| 8318 | __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ | ||
| 8319 | __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ | ||
| 8320 | __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ | ||
| 8321 | __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ | ||
| 8322 | __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ | ||
| 8323 | __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ | ||
| 8324 | __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ | ||
| 8325 | __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ | ||
| 8326 | __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ | ||
| 8327 | __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ | ||
| 8328 | __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ | ||
| 8329 | __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ | ||
| 8330 | uint8_t RESERVED_14[4]; | ||
| 8331 | __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ | ||
| 8332 | __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ | ||
| 8333 | __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ | ||
| 8334 | __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ | ||
| 8335 | __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ | ||
| 8336 | __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ | ||
| 8337 | __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ | ||
| 8338 | __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ | ||
| 8339 | uint8_t RESERVED_15[4]; | ||
| 8340 | __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ | ||
| 8341 | __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ | ||
| 8342 | uint8_t RESERVED_16[12]; | ||
| 8343 | __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ | ||
| 8344 | __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ | ||
| 8345 | __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ | ||
| 8346 | __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ | ||
| 8347 | __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ | ||
| 8348 | __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ | ||
| 8349 | __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ | ||
| 8350 | __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ | ||
| 8351 | uint8_t RESERVED_17[4]; | ||
| 8352 | __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ | ||
| 8353 | __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ | ||
| 8354 | __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ | ||
| 8355 | __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ | ||
| 8356 | __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ | ||
| 8357 | __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ | ||
| 8358 | __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ | ||
| 8359 | __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ | ||
| 8360 | __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ | ||
| 8361 | __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ | ||
| 8362 | __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ | ||
| 8363 | __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ | ||
| 8364 | __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ | ||
| 8365 | __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ | ||
| 8366 | __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ | ||
| 8367 | uint8_t RESERVED_18[284]; | ||
| 8368 | __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ | ||
| 8369 | __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ | ||
| 8370 | __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ | ||
| 8371 | __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ | ||
| 8372 | __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ | ||
| 8373 | __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ | ||
| 8374 | __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ | ||
| 8375 | uint8_t RESERVED_19[488]; | ||
| 8376 | __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ | ||
| 8377 | struct { /* offset: 0x608, array step: 0x8 */ | ||
| 8378 | __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ | ||
| 8379 | __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ | ||
| 8380 | } CHANNEL[4]; | ||
| 8381 | } ENET_Type; | ||
| 8382 | |||
| 8383 | /* ---------------------------------------------------------------------------- | ||
| 8384 | -- ENET Register Masks | ||
| 8385 | ---------------------------------------------------------------------------- */ | ||
| 8386 | |||
| 8387 | /*! | ||
| 8388 | * @addtogroup ENET_Register_Masks ENET Register Masks | ||
| 8389 | * @{ | ||
| 8390 | */ | ||
| 8391 | |||
| 8392 | /*! @name EIR - Interrupt Event Register */ | ||
| 8393 | /*! @{ */ | ||
| 8394 | #define ENET_EIR_TS_TIMER_MASK (0x8000U) | ||
| 8395 | #define ENET_EIR_TS_TIMER_SHIFT (15U) | ||
| 8396 | #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) | ||
| 8397 | #define ENET_EIR_TS_AVAIL_MASK (0x10000U) | ||
| 8398 | #define ENET_EIR_TS_AVAIL_SHIFT (16U) | ||
| 8399 | #define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) | ||
| 8400 | #define ENET_EIR_WAKEUP_MASK (0x20000U) | ||
| 8401 | #define ENET_EIR_WAKEUP_SHIFT (17U) | ||
| 8402 | #define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) | ||
| 8403 | #define ENET_EIR_PLR_MASK (0x40000U) | ||
| 8404 | #define ENET_EIR_PLR_SHIFT (18U) | ||
| 8405 | #define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) | ||
| 8406 | #define ENET_EIR_UN_MASK (0x80000U) | ||
| 8407 | #define ENET_EIR_UN_SHIFT (19U) | ||
| 8408 | #define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) | ||
| 8409 | #define ENET_EIR_RL_MASK (0x100000U) | ||
| 8410 | #define ENET_EIR_RL_SHIFT (20U) | ||
| 8411 | #define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) | ||
| 8412 | #define ENET_EIR_LC_MASK (0x200000U) | ||
| 8413 | #define ENET_EIR_LC_SHIFT (21U) | ||
| 8414 | #define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) | ||
| 8415 | #define ENET_EIR_EBERR_MASK (0x400000U) | ||
| 8416 | #define ENET_EIR_EBERR_SHIFT (22U) | ||
| 8417 | #define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) | ||
| 8418 | #define ENET_EIR_MII_MASK (0x800000U) | ||
| 8419 | #define ENET_EIR_MII_SHIFT (23U) | ||
| 8420 | #define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) | ||
| 8421 | #define ENET_EIR_RXB_MASK (0x1000000U) | ||
| 8422 | #define ENET_EIR_RXB_SHIFT (24U) | ||
| 8423 | #define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) | ||
| 8424 | #define ENET_EIR_RXF_MASK (0x2000000U) | ||
| 8425 | #define ENET_EIR_RXF_SHIFT (25U) | ||
| 8426 | #define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) | ||
| 8427 | #define ENET_EIR_TXB_MASK (0x4000000U) | ||
| 8428 | #define ENET_EIR_TXB_SHIFT (26U) | ||
| 8429 | #define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) | ||
| 8430 | #define ENET_EIR_TXF_MASK (0x8000000U) | ||
| 8431 | #define ENET_EIR_TXF_SHIFT (27U) | ||
| 8432 | #define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) | ||
| 8433 | #define ENET_EIR_GRA_MASK (0x10000000U) | ||
| 8434 | #define ENET_EIR_GRA_SHIFT (28U) | ||
| 8435 | #define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) | ||
| 8436 | #define ENET_EIR_BABT_MASK (0x20000000U) | ||
| 8437 | #define ENET_EIR_BABT_SHIFT (29U) | ||
| 8438 | #define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) | ||
| 8439 | #define ENET_EIR_BABR_MASK (0x40000000U) | ||
| 8440 | #define ENET_EIR_BABR_SHIFT (30U) | ||
| 8441 | #define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) | ||
| 8442 | /*! @} */ | ||
| 8443 | |||
| 8444 | /*! @name EIMR - Interrupt Mask Register */ | ||
| 8445 | /*! @{ */ | ||
| 8446 | #define ENET_EIMR_TS_TIMER_MASK (0x8000U) | ||
| 8447 | #define ENET_EIMR_TS_TIMER_SHIFT (15U) | ||
| 8448 | #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) | ||
| 8449 | #define ENET_EIMR_TS_AVAIL_MASK (0x10000U) | ||
| 8450 | #define ENET_EIMR_TS_AVAIL_SHIFT (16U) | ||
| 8451 | #define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) | ||
| 8452 | #define ENET_EIMR_WAKEUP_MASK (0x20000U) | ||
| 8453 | #define ENET_EIMR_WAKEUP_SHIFT (17U) | ||
| 8454 | #define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) | ||
| 8455 | #define ENET_EIMR_PLR_MASK (0x40000U) | ||
| 8456 | #define ENET_EIMR_PLR_SHIFT (18U) | ||
| 8457 | #define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) | ||
| 8458 | #define ENET_EIMR_UN_MASK (0x80000U) | ||
| 8459 | #define ENET_EIMR_UN_SHIFT (19U) | ||
| 8460 | #define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) | ||
| 8461 | #define ENET_EIMR_RL_MASK (0x100000U) | ||
| 8462 | #define ENET_EIMR_RL_SHIFT (20U) | ||
| 8463 | #define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) | ||
| 8464 | #define ENET_EIMR_LC_MASK (0x200000U) | ||
| 8465 | #define ENET_EIMR_LC_SHIFT (21U) | ||
| 8466 | #define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) | ||
| 8467 | #define ENET_EIMR_EBERR_MASK (0x400000U) | ||
| 8468 | #define ENET_EIMR_EBERR_SHIFT (22U) | ||
| 8469 | #define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) | ||
| 8470 | #define ENET_EIMR_MII_MASK (0x800000U) | ||
| 8471 | #define ENET_EIMR_MII_SHIFT (23U) | ||
| 8472 | #define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) | ||
| 8473 | #define ENET_EIMR_RXB_MASK (0x1000000U) | ||
| 8474 | #define ENET_EIMR_RXB_SHIFT (24U) | ||
| 8475 | #define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) | ||
| 8476 | #define ENET_EIMR_RXF_MASK (0x2000000U) | ||
| 8477 | #define ENET_EIMR_RXF_SHIFT (25U) | ||
| 8478 | #define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) | ||
| 8479 | #define ENET_EIMR_TXB_MASK (0x4000000U) | ||
| 8480 | #define ENET_EIMR_TXB_SHIFT (26U) | ||
| 8481 | /*! TXB - TXB Interrupt Mask | ||
| 8482 | * 0b0..The corresponding interrupt source is masked. | ||
| 8483 | * 0b1..The corresponding interrupt source is not masked. | ||
| 8484 | */ | ||
| 8485 | #define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) | ||
| 8486 | #define ENET_EIMR_TXF_MASK (0x8000000U) | ||
| 8487 | #define ENET_EIMR_TXF_SHIFT (27U) | ||
| 8488 | /*! TXF - TXF Interrupt Mask | ||
| 8489 | * 0b0..The corresponding interrupt source is masked. | ||
| 8490 | * 0b1..The corresponding interrupt source is not masked. | ||
| 8491 | */ | ||
| 8492 | #define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) | ||
| 8493 | #define ENET_EIMR_GRA_MASK (0x10000000U) | ||
| 8494 | #define ENET_EIMR_GRA_SHIFT (28U) | ||
| 8495 | /*! GRA - GRA Interrupt Mask | ||
| 8496 | * 0b0..The corresponding interrupt source is masked. | ||
| 8497 | * 0b1..The corresponding interrupt source is not masked. | ||
| 8498 | */ | ||
| 8499 | #define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) | ||
| 8500 | #define ENET_EIMR_BABT_MASK (0x20000000U) | ||
| 8501 | #define ENET_EIMR_BABT_SHIFT (29U) | ||
| 8502 | /*! BABT - BABT Interrupt Mask | ||
| 8503 | * 0b0..The corresponding interrupt source is masked. | ||
| 8504 | * 0b1..The corresponding interrupt source is not masked. | ||
| 8505 | */ | ||
| 8506 | #define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) | ||
| 8507 | #define ENET_EIMR_BABR_MASK (0x40000000U) | ||
| 8508 | #define ENET_EIMR_BABR_SHIFT (30U) | ||
| 8509 | /*! BABR - BABR Interrupt Mask | ||
| 8510 | * 0b0..The corresponding interrupt source is masked. | ||
| 8511 | * 0b1..The corresponding interrupt source is not masked. | ||
| 8512 | */ | ||
| 8513 | #define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) | ||
| 8514 | /*! @} */ | ||
| 8515 | |||
| 8516 | /*! @name RDAR - Receive Descriptor Active Register */ | ||
| 8517 | /*! @{ */ | ||
| 8518 | #define ENET_RDAR_RDAR_MASK (0x1000000U) | ||
| 8519 | #define ENET_RDAR_RDAR_SHIFT (24U) | ||
| 8520 | #define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) | ||
| 8521 | /*! @} */ | ||
| 8522 | |||
| 8523 | /*! @name TDAR - Transmit Descriptor Active Register */ | ||
| 8524 | /*! @{ */ | ||
| 8525 | #define ENET_TDAR_TDAR_MASK (0x1000000U) | ||
| 8526 | #define ENET_TDAR_TDAR_SHIFT (24U) | ||
| 8527 | #define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) | ||
| 8528 | /*! @} */ | ||
| 8529 | |||
| 8530 | /*! @name ECR - Ethernet Control Register */ | ||
| 8531 | /*! @{ */ | ||
| 8532 | #define ENET_ECR_RESET_MASK (0x1U) | ||
| 8533 | #define ENET_ECR_RESET_SHIFT (0U) | ||
| 8534 | #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) | ||
| 8535 | #define ENET_ECR_ETHEREN_MASK (0x2U) | ||
| 8536 | #define ENET_ECR_ETHEREN_SHIFT (1U) | ||
| 8537 | /*! ETHEREN - Ethernet Enable | ||
| 8538 | * 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. | ||
| 8539 | * 0b1..MAC is enabled, and reception and transmission are possible. | ||
| 8540 | */ | ||
| 8541 | #define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) | ||
| 8542 | #define ENET_ECR_MAGICEN_MASK (0x4U) | ||
| 8543 | #define ENET_ECR_MAGICEN_SHIFT (2U) | ||
| 8544 | /*! MAGICEN - Magic Packet Detection Enable | ||
| 8545 | * 0b0..Magic detection logic disabled. | ||
| 8546 | * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. | ||
| 8547 | */ | ||
| 8548 | #define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) | ||
| 8549 | #define ENET_ECR_SLEEP_MASK (0x8U) | ||
| 8550 | #define ENET_ECR_SLEEP_SHIFT (3U) | ||
| 8551 | /*! SLEEP - Sleep Mode Enable | ||
| 8552 | * 0b0..Normal operating mode. | ||
| 8553 | * 0b1..Sleep mode. | ||
| 8554 | */ | ||
| 8555 | #define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) | ||
| 8556 | #define ENET_ECR_EN1588_MASK (0x10U) | ||
| 8557 | #define ENET_ECR_EN1588_SHIFT (4U) | ||
| 8558 | /*! EN1588 - EN1588 Enable | ||
| 8559 | * 0b0..Legacy FEC buffer descriptors and functions enabled. | ||
| 8560 | * 0b1..Enhanced frame time-stamping functions enabled. | ||
| 8561 | */ | ||
| 8562 | #define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) | ||
| 8563 | #define ENET_ECR_DBGEN_MASK (0x40U) | ||
| 8564 | #define ENET_ECR_DBGEN_SHIFT (6U) | ||
| 8565 | /*! DBGEN - Debug Enable | ||
| 8566 | * 0b0..MAC continues operation in debug mode. | ||
| 8567 | * 0b1..MAC enters hardware freeze mode when the processor is in debug mode. | ||
| 8568 | */ | ||
| 8569 | #define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) | ||
| 8570 | #define ENET_ECR_STOPEN_MASK (0x80U) | ||
| 8571 | #define ENET_ECR_STOPEN_SHIFT (7U) | ||
| 8572 | #define ENET_ECR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK) | ||
| 8573 | #define ENET_ECR_DBSWP_MASK (0x100U) | ||
| 8574 | #define ENET_ECR_DBSWP_SHIFT (8U) | ||
| 8575 | /*! DBSWP - Descriptor Byte Swapping Enable | ||
| 8576 | * 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. | ||
| 8577 | * 0b1..The buffer descriptor bytes are swapped to support little-endian devices. | ||
| 8578 | */ | ||
| 8579 | #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) | ||
| 8580 | /*! @} */ | ||
| 8581 | |||
| 8582 | /*! @name MMFR - MII Management Frame Register */ | ||
| 8583 | /*! @{ */ | ||
| 8584 | #define ENET_MMFR_DATA_MASK (0xFFFFU) | ||
| 8585 | #define ENET_MMFR_DATA_SHIFT (0U) | ||
| 8586 | #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) | ||
| 8587 | #define ENET_MMFR_TA_MASK (0x30000U) | ||
| 8588 | #define ENET_MMFR_TA_SHIFT (16U) | ||
| 8589 | #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) | ||
| 8590 | #define ENET_MMFR_RA_MASK (0x7C0000U) | ||
| 8591 | #define ENET_MMFR_RA_SHIFT (18U) | ||
| 8592 | #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) | ||
| 8593 | #define ENET_MMFR_PA_MASK (0xF800000U) | ||
| 8594 | #define ENET_MMFR_PA_SHIFT (23U) | ||
| 8595 | #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) | ||
| 8596 | #define ENET_MMFR_OP_MASK (0x30000000U) | ||
| 8597 | #define ENET_MMFR_OP_SHIFT (28U) | ||
| 8598 | /*! OP - Operation Code | ||
| 8599 | * 0b00..Write frame operation, but not MII compliant. | ||
| 8600 | * 0b01..Write frame operation for a valid MII management frame. | ||
| 8601 | * 0b10..Read frame operation for a valid MII management frame. | ||
| 8602 | * 0b11..Read frame operation, but not MII compliant. | ||
| 8603 | */ | ||
| 8604 | #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) | ||
| 8605 | #define ENET_MMFR_ST_MASK (0xC0000000U) | ||
| 8606 | #define ENET_MMFR_ST_SHIFT (30U) | ||
| 8607 | #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) | ||
| 8608 | /*! @} */ | ||
| 8609 | |||
| 8610 | /*! @name MSCR - MII Speed Control Register */ | ||
| 8611 | /*! @{ */ | ||
| 8612 | #define ENET_MSCR_MII_SPEED_MASK (0x7EU) | ||
| 8613 | #define ENET_MSCR_MII_SPEED_SHIFT (1U) | ||
| 8614 | #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) | ||
| 8615 | #define ENET_MSCR_DIS_PRE_MASK (0x80U) | ||
| 8616 | #define ENET_MSCR_DIS_PRE_SHIFT (7U) | ||
| 8617 | /*! DIS_PRE - Disable Preamble | ||
| 8618 | * 0b0..Preamble enabled. | ||
| 8619 | * 0b1..Preamble (32 ones) is not prepended to the MII management frame. | ||
| 8620 | */ | ||
| 8621 | #define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) | ||
| 8622 | #define ENET_MSCR_HOLDTIME_MASK (0x700U) | ||
| 8623 | #define ENET_MSCR_HOLDTIME_SHIFT (8U) | ||
| 8624 | /*! HOLDTIME - Hold time On MDIO Output | ||
| 8625 | * 0b000..1 internal module clock cycle | ||
| 8626 | * 0b001..2 internal module clock cycles | ||
| 8627 | * 0b010..3 internal module clock cycles | ||
| 8628 | * 0b111..8 internal module clock cycles | ||
| 8629 | */ | ||
| 8630 | #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) | ||
| 8631 | /*! @} */ | ||
| 8632 | |||
| 8633 | /*! @name MIBC - MIB Control Register */ | ||
| 8634 | /*! @{ */ | ||
| 8635 | #define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) | ||
| 8636 | #define ENET_MIBC_MIB_CLEAR_SHIFT (29U) | ||
| 8637 | #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) | ||
| 8638 | #define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) | ||
| 8639 | #define ENET_MIBC_MIB_IDLE_SHIFT (30U) | ||
| 8640 | #define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) | ||
| 8641 | #define ENET_MIBC_MIB_DIS_MASK (0x80000000U) | ||
| 8642 | #define ENET_MIBC_MIB_DIS_SHIFT (31U) | ||
| 8643 | #define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) | ||
| 8644 | /*! @} */ | ||
| 8645 | |||
| 8646 | /*! @name RCR - Receive Control Register */ | ||
| 8647 | /*! @{ */ | ||
| 8648 | #define ENET_RCR_LOOP_MASK (0x1U) | ||
| 8649 | #define ENET_RCR_LOOP_SHIFT (0U) | ||
| 8650 | /*! LOOP - Internal Loopback | ||
| 8651 | * 0b0..Loopback disabled. | ||
| 8652 | * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. | ||
| 8653 | */ | ||
| 8654 | #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) | ||
| 8655 | #define ENET_RCR_DRT_MASK (0x2U) | ||
| 8656 | #define ENET_RCR_DRT_SHIFT (1U) | ||
| 8657 | /*! DRT - Disable Receive On Transmit | ||
| 8658 | * 0b0..Receive path operates independently of transmit. Used for full-duplex or to monitor transmit activity in half-duplex mode. | ||
| 8659 | * 0b1..Disable reception of frames while transmitting. Normally used for half-duplex mode. | ||
| 8660 | */ | ||
| 8661 | #define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) | ||
| 8662 | #define ENET_RCR_MII_MODE_MASK (0x4U) | ||
| 8663 | #define ENET_RCR_MII_MODE_SHIFT (2U) | ||
| 8664 | /*! MII_MODE - Media Independent Interface Mode | ||
| 8665 | * 0b0..Reserved. | ||
| 8666 | * 0b1..MII or RMII mode, as indicated by the RMII_MODE field. | ||
| 8667 | */ | ||
| 8668 | #define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) | ||
| 8669 | #define ENET_RCR_PROM_MASK (0x8U) | ||
| 8670 | #define ENET_RCR_PROM_SHIFT (3U) | ||
| 8671 | /*! PROM - Promiscuous Mode | ||
| 8672 | * 0b0..Disabled. | ||
| 8673 | * 0b1..Enabled. | ||
| 8674 | */ | ||
| 8675 | #define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) | ||
| 8676 | #define ENET_RCR_BC_REJ_MASK (0x10U) | ||
| 8677 | #define ENET_RCR_BC_REJ_SHIFT (4U) | ||
| 8678 | #define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) | ||
| 8679 | #define ENET_RCR_FCE_MASK (0x20U) | ||
| 8680 | #define ENET_RCR_FCE_SHIFT (5U) | ||
| 8681 | #define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) | ||
| 8682 | #define ENET_RCR_RMII_MODE_MASK (0x100U) | ||
| 8683 | #define ENET_RCR_RMII_MODE_SHIFT (8U) | ||
| 8684 | /*! RMII_MODE - RMII Mode Enable | ||
| 8685 | * 0b0..MAC configured for MII mode. | ||
| 8686 | * 0b1..MAC configured for RMII operation. | ||
| 8687 | */ | ||
| 8688 | #define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) | ||
| 8689 | #define ENET_RCR_RMII_10T_MASK (0x200U) | ||
| 8690 | #define ENET_RCR_RMII_10T_SHIFT (9U) | ||
| 8691 | /*! RMII_10T | ||
| 8692 | * 0b0..100 Mbps operation. | ||
| 8693 | * 0b1..10 Mbps operation. | ||
| 8694 | */ | ||
| 8695 | #define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) | ||
| 8696 | #define ENET_RCR_PADEN_MASK (0x1000U) | ||
| 8697 | #define ENET_RCR_PADEN_SHIFT (12U) | ||
| 8698 | /*! PADEN - Enable Frame Padding Remove On Receive | ||
| 8699 | * 0b0..No padding is removed on receive by the MAC. | ||
| 8700 | * 0b1..Padding is removed from received frames. | ||
| 8701 | */ | ||
| 8702 | #define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) | ||
| 8703 | #define ENET_RCR_PAUFWD_MASK (0x2000U) | ||
| 8704 | #define ENET_RCR_PAUFWD_SHIFT (13U) | ||
| 8705 | /*! PAUFWD - Terminate/Forward Pause Frames | ||
| 8706 | * 0b0..Pause frames are terminated and discarded in the MAC. | ||
| 8707 | * 0b1..Pause frames are forwarded to the user application. | ||
| 8708 | */ | ||
| 8709 | #define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) | ||
| 8710 | #define ENET_RCR_CRCFWD_MASK (0x4000U) | ||
| 8711 | #define ENET_RCR_CRCFWD_SHIFT (14U) | ||
| 8712 | /*! CRCFWD - Terminate/Forward Received CRC | ||
| 8713 | * 0b0..The CRC field of received frames is transmitted to the user application. | ||
| 8714 | * 0b1..The CRC field is stripped from the frame. | ||
| 8715 | */ | ||
| 8716 | #define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) | ||
| 8717 | #define ENET_RCR_CFEN_MASK (0x8000U) | ||
| 8718 | #define ENET_RCR_CFEN_SHIFT (15U) | ||
| 8719 | /*! CFEN - MAC Control Frame Enable | ||
| 8720 | * 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. | ||
| 8721 | * 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. | ||
| 8722 | */ | ||
| 8723 | #define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) | ||
| 8724 | #define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) | ||
| 8725 | #define ENET_RCR_MAX_FL_SHIFT (16U) | ||
| 8726 | #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) | ||
| 8727 | #define ENET_RCR_NLC_MASK (0x40000000U) | ||
| 8728 | #define ENET_RCR_NLC_SHIFT (30U) | ||
| 8729 | /*! NLC - Payload Length Check Disable | ||
| 8730 | * 0b0..The payload length check is disabled. | ||
| 8731 | * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLC] field. | ||
| 8732 | */ | ||
| 8733 | #define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) | ||
| 8734 | #define ENET_RCR_GRS_MASK (0x80000000U) | ||
| 8735 | #define ENET_RCR_GRS_SHIFT (31U) | ||
| 8736 | #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) | ||
| 8737 | /*! @} */ | ||
| 8738 | |||
| 8739 | /*! @name TCR - Transmit Control Register */ | ||
| 8740 | /*! @{ */ | ||
| 8741 | #define ENET_TCR_GTS_MASK (0x1U) | ||
| 8742 | #define ENET_TCR_GTS_SHIFT (0U) | ||
| 8743 | #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) | ||
| 8744 | #define ENET_TCR_FDEN_MASK (0x4U) | ||
| 8745 | #define ENET_TCR_FDEN_SHIFT (2U) | ||
| 8746 | #define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) | ||
| 8747 | #define ENET_TCR_TFC_PAUSE_MASK (0x8U) | ||
| 8748 | #define ENET_TCR_TFC_PAUSE_SHIFT (3U) | ||
| 8749 | /*! TFC_PAUSE - Transmit Frame Control Pause | ||
| 8750 | * 0b0..No PAUSE frame transmitted. | ||
| 8751 | * 0b1..The MAC stops transmission of data frames after the current transmission is complete. | ||
| 8752 | */ | ||
| 8753 | #define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) | ||
| 8754 | #define ENET_TCR_RFC_PAUSE_MASK (0x10U) | ||
| 8755 | #define ENET_TCR_RFC_PAUSE_SHIFT (4U) | ||
| 8756 | #define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) | ||
| 8757 | #define ENET_TCR_ADDSEL_MASK (0xE0U) | ||
| 8758 | #define ENET_TCR_ADDSEL_SHIFT (5U) | ||
| 8759 | /*! ADDSEL - Source MAC Address Select On Transmit | ||
| 8760 | * 0b000..Node MAC address programmed on PADDR1/2 registers. | ||
| 8761 | * 0b100..Reserved. | ||
| 8762 | * 0b101..Reserved. | ||
| 8763 | * 0b110..Reserved. | ||
| 8764 | */ | ||
| 8765 | #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) | ||
| 8766 | #define ENET_TCR_ADDINS_MASK (0x100U) | ||
| 8767 | #define ENET_TCR_ADDINS_SHIFT (8U) | ||
| 8768 | /*! ADDINS - Set MAC Address On Transmit | ||
| 8769 | * 0b0..The source MAC address is not modified by the MAC. | ||
| 8770 | * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. | ||
| 8771 | */ | ||
| 8772 | #define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) | ||
| 8773 | #define ENET_TCR_CRCFWD_MASK (0x200U) | ||
| 8774 | #define ENET_TCR_CRCFWD_SHIFT (9U) | ||
| 8775 | /*! CRCFWD - Forward Frame From Application With CRC | ||
| 8776 | * 0b0..TxBD[TC] controls whether the frame has a CRC from the application. | ||
| 8777 | * 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. | ||
| 8778 | */ | ||
| 8779 | #define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) | ||
| 8780 | /*! @} */ | ||
| 8781 | |||
| 8782 | /*! @name PALR - Physical Address Lower Register */ | ||
| 8783 | /*! @{ */ | ||
| 8784 | #define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) | ||
| 8785 | #define ENET_PALR_PADDR1_SHIFT (0U) | ||
| 8786 | #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) | ||
| 8787 | /*! @} */ | ||
| 8788 | |||
| 8789 | /*! @name PAUR - Physical Address Upper Register */ | ||
| 8790 | /*! @{ */ | ||
| 8791 | #define ENET_PAUR_TYPE_MASK (0xFFFFU) | ||
| 8792 | #define ENET_PAUR_TYPE_SHIFT (0U) | ||
| 8793 | #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) | ||
| 8794 | #define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) | ||
| 8795 | #define ENET_PAUR_PADDR2_SHIFT (16U) | ||
| 8796 | #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) | ||
| 8797 | /*! @} */ | ||
| 8798 | |||
| 8799 | /*! @name OPD - Opcode/Pause Duration Register */ | ||
| 8800 | /*! @{ */ | ||
| 8801 | #define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) | ||
| 8802 | #define ENET_OPD_PAUSE_DUR_SHIFT (0U) | ||
| 8803 | #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) | ||
| 8804 | #define ENET_OPD_OPCODE_MASK (0xFFFF0000U) | ||
| 8805 | #define ENET_OPD_OPCODE_SHIFT (16U) | ||
| 8806 | #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) | ||
| 8807 | /*! @} */ | ||
| 8808 | |||
| 8809 | /*! @name IAUR - Descriptor Individual Upper Address Register */ | ||
| 8810 | /*! @{ */ | ||
| 8811 | #define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) | ||
| 8812 | #define ENET_IAUR_IADDR1_SHIFT (0U) | ||
| 8813 | #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) | ||
| 8814 | /*! @} */ | ||
| 8815 | |||
| 8816 | /*! @name IALR - Descriptor Individual Lower Address Register */ | ||
| 8817 | /*! @{ */ | ||
| 8818 | #define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) | ||
| 8819 | #define ENET_IALR_IADDR2_SHIFT (0U) | ||
| 8820 | #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) | ||
| 8821 | /*! @} */ | ||
| 8822 | |||
| 8823 | /*! @name GAUR - Descriptor Group Upper Address Register */ | ||
| 8824 | /*! @{ */ | ||
| 8825 | #define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) | ||
| 8826 | #define ENET_GAUR_GADDR1_SHIFT (0U) | ||
| 8827 | #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) | ||
| 8828 | /*! @} */ | ||
| 8829 | |||
| 8830 | /*! @name GALR - Descriptor Group Lower Address Register */ | ||
| 8831 | /*! @{ */ | ||
| 8832 | #define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) | ||
| 8833 | #define ENET_GALR_GADDR2_SHIFT (0U) | ||
| 8834 | #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) | ||
| 8835 | /*! @} */ | ||
| 8836 | |||
| 8837 | /*! @name TFWR - Transmit FIFO Watermark Register */ | ||
| 8838 | /*! @{ */ | ||
| 8839 | #define ENET_TFWR_TFWR_MASK (0x3FU) | ||
| 8840 | #define ENET_TFWR_TFWR_SHIFT (0U) | ||
| 8841 | /*! TFWR - Transmit FIFO Write | ||
| 8842 | * 0b000000..64 bytes written. | ||
| 8843 | * 0b000001..64 bytes written. | ||
| 8844 | * 0b000010..128 bytes written. | ||
| 8845 | * 0b000011..192 bytes written. | ||
| 8846 | * 0b111110..3968 bytes written. | ||
| 8847 | * 0b111111..4032 bytes written. | ||
| 8848 | */ | ||
| 8849 | #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) | ||
| 8850 | #define ENET_TFWR_STRFWD_MASK (0x100U) | ||
| 8851 | #define ENET_TFWR_STRFWD_SHIFT (8U) | ||
| 8852 | /*! STRFWD - Store And Forward Enable | ||
| 8853 | * 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. | ||
| 8854 | * 0b1..Enabled. | ||
| 8855 | */ | ||
| 8856 | #define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) | ||
| 8857 | /*! @} */ | ||
| 8858 | |||
| 8859 | /*! @name RDSR - Receive Descriptor Ring Start Register */ | ||
| 8860 | /*! @{ */ | ||
| 8861 | #define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) | ||
| 8862 | #define ENET_RDSR_R_DES_START_SHIFT (3U) | ||
| 8863 | #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) | ||
| 8864 | /*! @} */ | ||
| 8865 | |||
| 8866 | /*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */ | ||
| 8867 | /*! @{ */ | ||
| 8868 | #define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) | ||
| 8869 | #define ENET_TDSR_X_DES_START_SHIFT (3U) | ||
| 8870 | #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) | ||
| 8871 | /*! @} */ | ||
| 8872 | |||
| 8873 | /*! @name MRBR - Maximum Receive Buffer Size Register */ | ||
| 8874 | /*! @{ */ | ||
| 8875 | #define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) | ||
| 8876 | #define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) | ||
| 8877 | #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) | ||
| 8878 | /*! @} */ | ||
| 8879 | |||
| 8880 | /*! @name RSFL - Receive FIFO Section Full Threshold */ | ||
| 8881 | /*! @{ */ | ||
| 8882 | #define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU) | ||
| 8883 | #define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) | ||
| 8884 | #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) | ||
| 8885 | /*! @} */ | ||
| 8886 | |||
| 8887 | /*! @name RSEM - Receive FIFO Section Empty Threshold */ | ||
| 8888 | /*! @{ */ | ||
| 8889 | #define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU) | ||
| 8890 | #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) | ||
| 8891 | #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) | ||
| 8892 | #define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) | ||
| 8893 | #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) | ||
| 8894 | #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) | ||
| 8895 | /*! @} */ | ||
| 8896 | |||
| 8897 | /*! @name RAEM - Receive FIFO Almost Empty Threshold */ | ||
| 8898 | /*! @{ */ | ||
| 8899 | #define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU) | ||
| 8900 | #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) | ||
| 8901 | #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) | ||
| 8902 | /*! @} */ | ||
| 8903 | |||
| 8904 | /*! @name RAFL - Receive FIFO Almost Full Threshold */ | ||
| 8905 | /*! @{ */ | ||
| 8906 | #define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU) | ||
| 8907 | #define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) | ||
| 8908 | #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) | ||
| 8909 | /*! @} */ | ||
| 8910 | |||
| 8911 | /*! @name TSEM - Transmit FIFO Section Empty Threshold */ | ||
| 8912 | /*! @{ */ | ||
| 8913 | #define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU) | ||
| 8914 | #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) | ||
| 8915 | #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) | ||
| 8916 | /*! @} */ | ||
| 8917 | |||
| 8918 | /*! @name TAEM - Transmit FIFO Almost Empty Threshold */ | ||
| 8919 | /*! @{ */ | ||
| 8920 | #define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU) | ||
| 8921 | #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) | ||
| 8922 | #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) | ||
| 8923 | /*! @} */ | ||
| 8924 | |||
| 8925 | /*! @name TAFL - Transmit FIFO Almost Full Threshold */ | ||
| 8926 | /*! @{ */ | ||
| 8927 | #define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU) | ||
| 8928 | #define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) | ||
| 8929 | #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) | ||
| 8930 | /*! @} */ | ||
| 8931 | |||
| 8932 | /*! @name TIPG - Transmit Inter-Packet Gap */ | ||
| 8933 | /*! @{ */ | ||
| 8934 | #define ENET_TIPG_IPG_MASK (0x1FU) | ||
| 8935 | #define ENET_TIPG_IPG_SHIFT (0U) | ||
| 8936 | #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) | ||
| 8937 | /*! @} */ | ||
| 8938 | |||
| 8939 | /*! @name FTRL - Frame Truncation Length */ | ||
| 8940 | /*! @{ */ | ||
| 8941 | #define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) | ||
| 8942 | #define ENET_FTRL_TRUNC_FL_SHIFT (0U) | ||
| 8943 | #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) | ||
| 8944 | /*! @} */ | ||
| 8945 | |||
| 8946 | /*! @name TACC - Transmit Accelerator Function Configuration */ | ||
| 8947 | /*! @{ */ | ||
| 8948 | #define ENET_TACC_SHIFT16_MASK (0x1U) | ||
| 8949 | #define ENET_TACC_SHIFT16_SHIFT (0U) | ||
| 8950 | /*! SHIFT16 - TX FIFO Shift-16 | ||
| 8951 | * 0b0..Disabled. | ||
| 8952 | * 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header. | ||
| 8953 | */ | ||
| 8954 | #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) | ||
| 8955 | #define ENET_TACC_IPCHK_MASK (0x8U) | ||
| 8956 | #define ENET_TACC_IPCHK_SHIFT (3U) | ||
| 8957 | /*! IPCHK | ||
| 8958 | * 0b0..Checksum is not inserted. | ||
| 8959 | * 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified. | ||
| 8960 | */ | ||
| 8961 | #define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) | ||
| 8962 | #define ENET_TACC_PROCHK_MASK (0x10U) | ||
| 8963 | #define ENET_TACC_PROCHK_SHIFT (4U) | ||
| 8964 | /*! PROCHK | ||
| 8965 | * 0b0..Checksum not inserted. | ||
| 8966 | * 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified. | ||
| 8967 | */ | ||
| 8968 | #define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) | ||
| 8969 | /*! @} */ | ||
| 8970 | |||
| 8971 | /*! @name RACC - Receive Accelerator Function Configuration */ | ||
| 8972 | /*! @{ */ | ||
| 8973 | #define ENET_RACC_PADREM_MASK (0x1U) | ||
| 8974 | #define ENET_RACC_PADREM_SHIFT (0U) | ||
| 8975 | /*! PADREM - Enable Padding Removal For Short IP Frames | ||
| 8976 | * 0b0..Padding not removed. | ||
| 8977 | * 0b1..Any bytes following the IP payload section of the frame are removed from the frame. | ||
| 8978 | */ | ||
| 8979 | #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) | ||
| 8980 | #define ENET_RACC_IPDIS_MASK (0x2U) | ||
| 8981 | #define ENET_RACC_IPDIS_SHIFT (1U) | ||
| 8982 | /*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum | ||
| 8983 | * 0b0..Frames with wrong IPv4 header checksum are not discarded. | ||
| 8984 | * 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). | ||
| 8985 | */ | ||
| 8986 | #define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) | ||
| 8987 | #define ENET_RACC_PRODIS_MASK (0x4U) | ||
| 8988 | #define ENET_RACC_PRODIS_SHIFT (2U) | ||
| 8989 | /*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum | ||
| 8990 | * 0b0..Frames with wrong checksum are not discarded. | ||
| 8991 | * 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). | ||
| 8992 | */ | ||
| 8993 | #define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) | ||
| 8994 | #define ENET_RACC_LINEDIS_MASK (0x40U) | ||
| 8995 | #define ENET_RACC_LINEDIS_SHIFT (6U) | ||
| 8996 | /*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors | ||
| 8997 | * 0b0..Frames with errors are not discarded. | ||
| 8998 | * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. | ||
| 8999 | */ | ||
| 9000 | #define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) | ||
| 9001 | #define ENET_RACC_SHIFT16_MASK (0x80U) | ||
| 9002 | #define ENET_RACC_SHIFT16_SHIFT (7U) | ||
| 9003 | /*! SHIFT16 - RX FIFO Shift-16 | ||
| 9004 | * 0b0..Disabled. | ||
| 9005 | * 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. | ||
| 9006 | */ | ||
| 9007 | #define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) | ||
| 9008 | /*! @} */ | ||
| 9009 | |||
| 9010 | /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ | ||
| 9011 | /*! @{ */ | ||
| 9012 | #define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) | ||
| 9013 | #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) | ||
| 9014 | #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) | ||
| 9015 | /*! @} */ | ||
| 9016 | |||
| 9017 | /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ | ||
| 9018 | /*! @{ */ | ||
| 9019 | #define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) | ||
| 9020 | #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) | ||
| 9021 | #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) | ||
| 9022 | /*! @} */ | ||
| 9023 | |||
| 9024 | /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ | ||
| 9025 | /*! @{ */ | ||
| 9026 | #define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) | ||
| 9027 | #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) | ||
| 9028 | #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) | ||
| 9029 | /*! @} */ | ||
| 9030 | |||
| 9031 | /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ | ||
| 9032 | /*! @{ */ | ||
| 9033 | #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) | ||
| 9034 | #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) | ||
| 9035 | #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) | ||
| 9036 | /*! @} */ | ||
| 9037 | |||
| 9038 | /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ | ||
| 9039 | /*! @{ */ | ||
| 9040 | #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) | ||
| 9041 | #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) | ||
| 9042 | #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) | ||
| 9043 | /*! @} */ | ||
| 9044 | |||
| 9045 | /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ | ||
| 9046 | /*! @{ */ | ||
| 9047 | #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) | ||
| 9048 | #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) | ||
| 9049 | #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) | ||
| 9050 | /*! @} */ | ||
| 9051 | |||
| 9052 | /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ | ||
| 9053 | /*! @{ */ | ||
| 9054 | #define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) | ||
| 9055 | #define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) | ||
| 9056 | #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) | ||
| 9057 | /*! @} */ | ||
| 9058 | |||
| 9059 | /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ | ||
| 9060 | /*! @{ */ | ||
| 9061 | #define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) | ||
| 9062 | #define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) | ||
| 9063 | #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) | ||
| 9064 | /*! @} */ | ||
| 9065 | |||
| 9066 | /*! @name RMON_T_COL - Tx Collision Count Statistic Register */ | ||
| 9067 | /*! @{ */ | ||
| 9068 | #define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) | ||
| 9069 | #define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) | ||
| 9070 | #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) | ||
| 9071 | /*! @} */ | ||
| 9072 | |||
| 9073 | /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ | ||
| 9074 | /*! @{ */ | ||
| 9075 | #define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) | ||
| 9076 | #define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) | ||
| 9077 | #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) | ||
| 9078 | /*! @} */ | ||
| 9079 | |||
| 9080 | /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ | ||
| 9081 | /*! @{ */ | ||
| 9082 | #define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) | ||
| 9083 | #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) | ||
| 9084 | #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) | ||
| 9085 | /*! @} */ | ||
| 9086 | |||
| 9087 | /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ | ||
| 9088 | /*! @{ */ | ||
| 9089 | #define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) | ||
| 9090 | #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) | ||
| 9091 | #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) | ||
| 9092 | /*! @} */ | ||
| 9093 | |||
| 9094 | /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ | ||
| 9095 | /*! @{ */ | ||
| 9096 | #define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) | ||
| 9097 | #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) | ||
| 9098 | #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) | ||
| 9099 | /*! @} */ | ||
| 9100 | |||
| 9101 | /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ | ||
| 9102 | /*! @{ */ | ||
| 9103 | #define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) | ||
| 9104 | #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) | ||
| 9105 | #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) | ||
| 9106 | /*! @} */ | ||
| 9107 | |||
| 9108 | /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ | ||
| 9109 | /*! @{ */ | ||
| 9110 | #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) | ||
| 9111 | #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) | ||
| 9112 | #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) | ||
| 9113 | /*! @} */ | ||
| 9114 | |||
| 9115 | /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ | ||
| 9116 | /*! @{ */ | ||
| 9117 | #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) | ||
| 9118 | #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) | ||
| 9119 | #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) | ||
| 9120 | /*! @} */ | ||
| 9121 | |||
| 9122 | /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ | ||
| 9123 | /*! @{ */ | ||
| 9124 | #define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) | ||
| 9125 | #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) | ||
| 9126 | #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) | ||
| 9127 | /*! @} */ | ||
| 9128 | |||
| 9129 | /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ | ||
| 9130 | /*! @{ */ | ||
| 9131 | #define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) | ||
| 9132 | #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) | ||
| 9133 | #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) | ||