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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/drivers/fsl_clock.h
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1/*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2020, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_CLOCK_H_
10#define _FSL_CLOCK_H_
11
12#include "fsl_common.h"
13
14/*! @addtogroup clock */
15/*! @{ */
16
17/*! @file */
18
19/*******************************************************************************
20 * Configurations
21 ******************************************************************************/
22
23/*! @brief Configures whether to check a parameter in a function.
24 *
25 * Some MCG settings must be changed with conditions, for example:
26 * 1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when
27 * MCGIRCLK is used as a system clock source.
28 * 2. MCG_C7[OSCSEL] should not be changed when the external reference clock is used
29 * as a system clock source. For example, in FBE/BLPE/PBE modes.
30 * 3. The users should only switch between the supported clock modes.
31 *
32 * MCG functions check the parameter and MCG status before setting, if not allowed
33 * to change, the functions return error. The parameter checking increases code size,
34 * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to
35 * disable parameter checking.
36 */
37#ifndef MCG_CONFIG_CHECK_PARAM
38#define MCG_CONFIG_CHECK_PARAM 0U
39#endif
40
41/*! @brief Configure whether driver controls clock
42 *
43 * When set to 0, peripheral drivers will enable clock in initialize function
44 * and disable clock in de-initialize function. When set to 1, peripheral
45 * driver will not control the clock, application could control the clock out of
46 * the driver.
47 *
48 * @note All drivers share this feature switcher. If it is set to 1, application
49 * should handle clock enable and disable for all drivers.
50 */
51#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
52#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
53#endif
54
55/*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58
59/*! @name Driver version */
60/*@{*/
61/*! @brief CLOCK driver version 2.5.1. */
62#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
63/*@}*/
64
65/*! @brief External XTAL0 (OSC0) clock frequency.
66 *
67 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
68 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
69 * if XTAL0 is 8 MHz:
70 * @code
71 * Set up the OSC0
72 * CLOCK_InitOsc0(...);
73 * Set the XTAL0 value to the clock driver.
74 * CLOCK_SetXtal0Freq(80000000);
75 * @endcode
76 *
77 * This is important for the multicore platforms where only one core needs to set up the
78 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
79 * to get a valid clock frequency.
80 */
81extern volatile uint32_t g_xtal0Freq;
82
83/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
84 *
85 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
86 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
87 *
88 * This is important for the multicore platforms where only one core needs to set up
89 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
90 * to get a valid clock frequency.
91 */
92extern volatile uint32_t g_xtal32Freq;
93
94/*! @brief IRC48M clock frequency in Hz. */
95#define MCG_INTERNAL_IRC_48M 48000000U
96
97#if (defined(OSC) && !(defined(OSC0)))
98#define OSC0 OSC
99#endif
100
101/* Definition for delay API in clock driver, users can redefine it to the real application. */
102#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
103#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (120000000UL)
104#endif
105
106/*! @brief Clock ip name array for DMAMUX. */
107#define DMAMUX_CLOCKS \
108 { \
109 kCLOCK_Dmamux0 \
110 }
111
112/*! @brief Clock ip name array for RTC. */
113#define RTC_CLOCKS \
114 { \
115 kCLOCK_Rtc0 \
116 }
117
118/*! @brief Clock ip name array for ENET. */
119#define ENET_CLOCKS \
120 { \
121 kCLOCK_Enet0 \
122 }
123
124/*! @brief Clock ip name array for PORT. */
125#define PORT_CLOCKS \
126 { \
127 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
128 }
129
130/*! @brief Clock ip name array for SAI. */
131#define SAI_CLOCKS \
132 { \
133 kCLOCK_Sai0 \
134 }
135
136/*! @brief Clock ip name array for FLEXBUS. */
137#define FLEXBUS_CLOCKS \
138 { \
139 kCLOCK_Flexbus0 \
140 }
141
142/*! @brief Clock ip name array for TSI. */
143#define TSI_CLOCKS \
144 { \
145 kCLOCK_Tsi0 \
146 }
147
148/*! @brief Clock ip name array for LPUART. */
149#define LPUART_CLOCKS \
150 { \
151 kCLOCK_Lpuart0 \
152 }
153
154/*! @brief Clock ip name array for EWM. */
155#define EWM_CLOCKS \
156 { \
157 kCLOCK_Ewm0 \
158 }
159
160/*! @brief Clock ip name array for PIT. */
161#define PIT_CLOCKS \
162 { \
163 kCLOCK_Pit0 \
164 }
165
166/*! @brief Clock ip name array for DSPI. */
167#define DSPI_CLOCKS \
168 { \
169 kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2 \
170 }
171
172/*! @brief Clock ip name array for LPTMR. */
173#define LPTMR_CLOCKS \
174 { \
175 kCLOCK_Lptmr0 \
176 }
177
178/*! @brief Clock ip name array for SDHC. */
179#define SDHC_CLOCKS \
180 { \
181 kCLOCK_Sdhc0 \
182 }
183
184/*! @brief Clock ip name array for FTM. */
185#define FTM_CLOCKS \
186 { \
187 kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \
188 }
189
190/*! @brief Clock ip name array for EDMA. */
191#define EDMA_CLOCKS \
192 { \
193 kCLOCK_Dma0 \
194 }
195
196/*! @brief Clock ip name array for FLEXCAN. */
197#define FLEXCAN_CLOCKS \
198 { \
199 kCLOCK_Flexcan0, kCLOCK_Flexcan1 \
200 }
201
202/*! @brief Clock ip name array for DAC. */
203#define DAC_CLOCKS \
204 { \
205 kCLOCK_Dac0, kCLOCK_Dac1 \
206 }
207
208/*! @brief Clock ip name array for ADC16. */
209#define ADC16_CLOCKS \
210 { \
211 kCLOCK_Adc0, kCLOCK_Adc1 \
212 }
213
214/*! @brief Clock ip name array for SDRAM. */
215#define SDRAM_CLOCKS \
216 { \
217 kCLOCK_Sdramc0 \
218 }
219
220/*! @brief Clock ip name array for MPU. */
221#define SYSMPU_CLOCKS \
222 { \
223 kCLOCK_Sysmpu0 \
224 }
225
226/*! @brief Clock ip name array for VREF. */
227#define VREF_CLOCKS \
228 { \
229 kCLOCK_Vref0 \
230 }
231
232/*! @brief Clock ip name array for CMT. */
233#define CMT_CLOCKS \
234 { \
235 kCLOCK_Cmt0 \
236 }
237
238/*! @brief Clock ip name array for UART. */
239#define UART_CLOCKS \
240 { \
241 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4 \
242 }
243
244/*! @brief Clock ip name array for TPM. */
245#define TPM_CLOCKS \
246 { \
247 kCLOCK_IpInvalid, kCLOCK_Tpm1, kCLOCK_Tpm2 \
248 }
249
250/*! @brief Clock ip name array for RNGA. */
251#define RNGA_CLOCKS \
252 { \
253 kCLOCK_Rnga0 \
254 }
255
256/*! @brief Clock ip name array for CRC. */
257#define CRC_CLOCKS \
258 { \
259 kCLOCK_Crc0 \
260 }
261
262/*! @brief Clock ip name array for I2C. */
263#define I2C_CLOCKS \
264 { \
265 kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3 \
266 }
267
268/*! @brief Clock ip name array for FTF. */
269#define FTF_CLOCKS \
270 { \
271 kCLOCK_Ftf0 \
272 }
273
274/*! @brief Clock ip name array for PDB. */
275#define PDB_CLOCKS \
276 { \
277 kCLOCK_Pdb0 \
278 }
279
280/*! @brief Clock ip name array for CMP. */
281#define CMP_CLOCKS \
282 { \
283 kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2, kCLOCK_Cmp3 \
284 }
285
286/*!
287 * @brief LPO clock frequency.
288 */
289#define LPO_CLK_FREQ 1000U
290
291/*! @brief Peripherals clock source definition. */
292#define SYS_CLK kCLOCK_CoreSysClk
293#define BUS_CLK kCLOCK_BusClk
294
295#define I2C0_CLK_SRC BUS_CLK
296#define I2C1_CLK_SRC BUS_CLK
297#define I2C2_CLK_SRC BUS_CLK
298#define I2C3_CLK_SRC BUS_CLK
299#define DSPI0_CLK_SRC BUS_CLK
300#define DSPI1_CLK_SRC BUS_CLK
301#define DSPI2_CLK_SRC BUS_CLK
302#define UART0_CLK_SRC SYS_CLK
303#define UART1_CLK_SRC SYS_CLK
304#define UART2_CLK_SRC BUS_CLK
305#define UART3_CLK_SRC BUS_CLK
306#define UART4_CLK_SRC BUS_CLK
307
308/*! @brief Clock name used to get clock frequency. */
309typedef enum _clock_name
310{
311
312 /* ----------------------------- System layer clock -------------------------------*/
313 kCLOCK_CoreSysClk, /*!< Core/system clock */
314 kCLOCK_PlatClk, /*!< Platform clock */
315 kCLOCK_BusClk, /*!< Bus clock */
316 kCLOCK_FlexBusClk, /*!< FlexBus clock */
317 kCLOCK_FlashClk, /*!< Flash clock */
318 kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */
319 kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */
320
321 /* ---------------------------------- OSC clock -----------------------------------*/
322 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
323 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
324 kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */
325 kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */
326
327 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
328 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
329 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
330 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
331 kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */
332 kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */
333 kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */
334 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
335 kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */
336
337 /* --------------------------------- Other clock ----------------------------------*/
338 kCLOCK_LpoClk, /*!< LPO clock */
339
340} clock_name_t;
341
342/*! @brief USB clock source definition. */
343typedef enum _clock_usb_src
344{
345 kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */
346 kCLOCK_UsbSrcUsbPfd = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(2U), /*!< Use USBPFDCLK. */
347 kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M. */
348 kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U), /*!< Use USB_CLKIN. */
349 kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
350 care the clock source. */
351} clock_usb_src_t;
352
353/*! @brief Source of the USB HS PHY. */
354typedef enum _clock_usb_phy_src
355{
356 kCLOCK_UsbPhySrcExt = 0U, /*!< Use external crystal. */
357} clock_usb_phy_src_t;
358
359/*! @brief Source of the USB HS PFD clock (USB1PFDCLK) */
360typedef enum _clock_usb_pfd_src
361{
362 kCLOCK_UsbPfdSrcExt = 0U, /*!< Use external crystal. */
363 kCLOCK_UsbPfdSrcFracDivBy4 = 1U, /*!< Use PFD_FRAC output divided by 4. */
364 kCLOCK_UsbPfdSrcFracDivBy2 = 2U, /*!< Use PFD_FRAC output divided by 2. */
365 kCLOCK_UsbPfdSrcFrac = 3U, /*!< Use PFD_FRAC output. */
366} clock_usb_pfd_src_t;
367
368/*------------------------------------------------------------------------------
369
370 clock_gate_t definition:
371
372 31 16 0
373 -----------------------------------------------------------------
374 | SIM_SCGC register offset | control bit offset in SCGC |
375 -----------------------------------------------------------------
376
377 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
378 SIM_SCGC3 offset in SIM is 0x1030, then kClockGateSdhc0 is defined as
379
380 kClockGateSdhc0 = (0x1030 << 16) | 17;
381
382------------------------------------------------------------------------------*/
383
384#define CLK_GATE_REG_OFFSET_SHIFT 16U
385#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
386#define CLK_GATE_BIT_SHIFT_SHIFT 0U
387#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
388
389#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
390 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
391 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
392
393#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
394#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
395
396/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
397typedef enum _clock_ip_name
398{
399 kCLOCK_IpInvalid = 0U,
400 kCLOCK_I2c2 = CLK_GATE_DEFINE(0x1028U, 6U),
401 kCLOCK_I2c3 = CLK_GATE_DEFINE(0x1028U, 7U),
402 kCLOCK_Uart4 = CLK_GATE_DEFINE(0x1028U, 10U),
403
404 kCLOCK_Enet0 = CLK_GATE_DEFINE(0x102CU, 0U),
405 kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x102CU, 4U),
406 kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x102CU, 9U),
407 kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x102CU, 10U),
408 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x102CU, 12U),
409 kCLOCK_Dac1 = CLK_GATE_DEFINE(0x102CU, 13U),
410
411 kCLOCK_Rnga0 = CLK_GATE_DEFINE(0x1030U, 0U),
412 kCLOCK_Usbhs0 = CLK_GATE_DEFINE(0x1030U, 1U),
413 kCLOCK_UsbhsPhy0 = CLK_GATE_DEFINE(0x1030U, 2U),
414 kCLOCK_UsbhsDcd0 = CLK_GATE_DEFINE(0x1030U, 3U),
415 kCLOCK_Flexcan1 = CLK_GATE_DEFINE(0x1030U, 4U),
416 kCLOCK_Spi2 = CLK_GATE_DEFINE(0x1030U, 12U),
417 kCLOCK_Sdhc0 = CLK_GATE_DEFINE(0x1030U, 17U),
418 kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x1030U, 25U),
419 kCLOCK_Adc1 = CLK_GATE_DEFINE(0x1030U, 27U),
420
421 kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
422 kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U),
423 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
424 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
425 kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U),
426 kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U),
427 kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U),
428 kCLOCK_Uart3 = CLK_GATE_DEFINE(0x1034U, 13U),
429 kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U),
430 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
431 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
432 kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U),
433 kCLOCK_Cmp3 = CLK_GATE_DEFINE(0x1034U, 19U),
434 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
435
436 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
437 kCLOCK_Tsi0 = CLK_GATE_DEFINE(0x1038U, 5U),
438 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
439 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
440 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
441 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
442 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
443
444 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
445 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
446 kCLOCK_Flexcan0 = CLK_GATE_DEFINE(0x103CU, 4U),
447 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
448 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
449 kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U),
450 kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
451 kCLOCK_Usbdcd0 = CLK_GATE_DEFINE(0x103CU, 21U),
452 kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
453 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
454 kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U),
455 kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U),
456 kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U),
457 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
458 kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
459
460 kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U),
461 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
462 kCLOCK_Sysmpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
463 kCLOCK_Sdramc0 = CLK_GATE_DEFINE(0x1040U, 3U),
464} clock_ip_name_t;
465
466/*!@brief SIM configuration structure for clock setting. */
467typedef struct _sim_clock_config
468{
469 uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
470 uint8_t pllFllDiv; /*!< PLLFLLSEL clock divider divisor. */
471 uint8_t pllFllFrac; /*!< PLLFLLSEL clock divider fraction. */
472 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
473 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
474} sim_clock_config_t;
475
476/*! @brief OSC work mode. */
477typedef enum _osc_mode
478{
479 kOSC_ModeExt = 0U, /*!< Use an external clock. */
480#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
481 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
482#else
483 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
484#endif
485 kOSC_ModeOscHighGain = 0U
486#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
487 | MCG_C2_EREFS_MASK
488#else
489 | MCG_C2_EREFS0_MASK
490#endif
491#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
492 | MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
493#else
494 | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
495#endif
496} osc_mode_t;
497
498/*! @brief Oscillator capacitor load setting.*/
499enum _osc_cap_load
500{
501 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
502 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
503 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
504 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
505};
506
507/*! @brief OSCERCLK enable mode. */
508enum _oscer_enable_mode
509{
510 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
511 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
512};
513
514/*! @brief OSC configuration for OSCERCLK. */
515typedef struct _oscer_config
516{
517 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */
518
519 uint8_t erclkDiv; /*!< Divider for OSCERCLK.*/
520} oscer_config_t;
521
522/*!
523 * @brief OSC Initialization Configuration Structure
524 *
525 * Defines the configuration data structure to initialize the OSC.
526 * When porting to a new board, set the following members
527 * according to the board setting:
528 * 1. freq: The external frequency.
529 * 2. workMode: The OSC module mode.
530 */
531typedef struct _osc_config
532{
533 uint32_t freq; /*!< External clock frequency. */
534 uint8_t capLoad; /*!< Capacitor load setting. */
535 osc_mode_t workMode; /*!< OSC work mode setting. */
536 oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
537} osc_config_t;
538
539/*! @brief MCG FLL reference clock source select. */
540typedef enum _mcg_fll_src
541{
542 kMCG_FllSrcExternal, /*!< External reference clock is selected */
543 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
544} mcg_fll_src_t;
545
546/*! @brief MCG internal reference clock select */
547typedef enum _mcg_irc_mode
548{
549 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
550 kMCG_IrcFast /*!< Fast internal reference clock selected */
551} mcg_irc_mode_t;
552
553/*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
554typedef enum _mcg_dmx32
555{
556 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
557 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
558} mcg_dmx32_t;
559
560/*! @brief MCG DCO range select */
561typedef enum _mcg_drs
562{
563 kMCG_DrsLow, /*!< Low frequency range */
564 kMCG_DrsMid, /*!< Mid frequency range */
565 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
566 kMCG_DrsHigh /*!< High frequency range */
567} mcg_drs_t;
568
569/*! @brief MCG PLL reference clock select */
570typedef enum _mcg_pll_ref_src
571{
572 kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
573 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
574} mcg_pll_ref_src_t;
575
576/*! @brief MCGOUT clock source. */
577typedef enum _mcg_clkout_src
578{
579 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
580 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
581 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
582} mcg_clkout_src_t;
583
584/*! @brief MCG Automatic Trim Machine Select */
585typedef enum _mcg_atm_select
586{
587 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
588 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
589} mcg_atm_select_t;
590
591/*! @brief MCG OSC Clock Select */
592typedef enum _mcg_oscsel
593{
594 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
595 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
596 kMCG_OscselIrc /*!< Selects 48 MHz IRC Oscillator */
597} mcg_oscsel_t;
598
599/*! @brief MCG PLLCS select */
600typedef enum _mcg_pll_clk_select
601{
602 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
603 kMCG_PllClkSelExtPll /* The external PLL clock is selected */
604} mcg_pll_clk_select_t;
605
606/*! @brief MCG clock monitor mode. */
607typedef enum _mcg_monitor_mode
608{
609 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
610 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
611 kMCG_MonitorReset /*!< System reset when clock lost. */
612} mcg_monitor_mode_t;
613
614/*! @brief MCG status. Enumeration _mcg_status */
615enum
616{
617 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0U), /*!< Can't switch to target mode. */
618 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1U), /*!< Current mode invalid for the specific
619 function. */
620 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2U), /*!< Invalid bus clock for ATM. */
621 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3U), /*!< Invalid desired frequency for ATM. */
622 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4U), /*!< IRC is used when using ATM. */
623 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5U), /*!< Hardware fail occurs during ATM. */
624 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6U) /*!< Can't change the clock source because
625 it is in use. */
626};
627
628/*! @brief MCG status flags. Enumeration _mcg_status_flags_t */
629enum
630{
631 kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */
632 kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */
633 kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */
634 kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */
635 kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */
636 kMCG_ExtPllLostFlag = (1U << 9U), /*!< External PLL lost. */
637};
638
639/*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. Enumeration _mcg_irclk_enable_mode */
640enum
641{
642 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
643 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
644};
645
646/*! @brief MCG PLL clock enable mode definition. Enumeration _mcg_pll_enable_mode */
647enum
648{
649 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
650 MCG clock mode. Generally, the PLL
651 is disabled in FLL modes
652 (FEI/FBI/FEE/FBE). Setting the PLL clock
653 enable independent, enables the
654 PLL in the FLL modes. */
655 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
656};
657
658/*! @brief MCG mode definitions */
659typedef enum _mcg_mode
660{
661 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
662 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
663 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
664 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
665 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
666 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
667 kMCG_ModePBE, /*!< PBE - PLL Bypassed External */
668 kMCG_ModePEE, /*!< PEE - PLL Engaged External */
669 kMCG_ModeError /*!< Unknown mode */
670} mcg_mode_t;
671
672/*! @brief MCG PLL configuration. */
673typedef struct _mcg_pll_config
674{
675 uint8_t enableMode; /*!< Enable mode. OR'ed value of enumeration _mcg_pll_enable_mode. */
676 uint8_t prdiv; /*!< Reference divider PRDIV. */
677 uint8_t vdiv; /*!< VCO divider VDIV. */
678} mcg_pll_config_t;
679
680/*! @brief MCG mode change configuration structure
681 *
682 * When porting to a new board, set the following members
683 * according to the board setting:
684 * 1. frdiv: If the FLL uses the external reference clock, set this
685 * value to ensure that the external reference clock divided by frdiv is
686 * in the 31.25 kHz to 39.0625 kHz range.
687 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
688 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
689 * FSL_FEATURE_MCG_PLL_REF_MAX range.
690 */
691typedef struct _mcg_config
692{
693 mcg_mode_t mcgMode; /*!< MCG mode. */
694
695 /* ----------------------- MCGIRCCLK settings ------------------------ */
696 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
697 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
698 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
699
700 /* ------------------------ MCG FLL settings ------------------------- */
701 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
702 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
703 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
704 mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */
705
706 /* ------------------------ MCG PLL settings ------------------------- */
707 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
708
709 mcg_pll_clk_select_t pllcs; /*!< PLL select as output, PLLCS.*/
710
711} mcg_config_t;
712
713/*******************************************************************************
714 * API
715 ******************************************************************************/
716
717#if defined(__cplusplus)
718extern "C" {
719#endif /* __cplusplus */
720
721/*!
722 * @brief Enable the clock for specific IP.
723 *
724 * @param name Which clock to enable, see \ref clock_ip_name_t.
725 */
726static inline void CLOCK_EnableClock(clock_ip_name_t name)
727{
728 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
729 (*(volatile uint32_t *)regAddr) |= (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
730}
731
732/*!
733 * @brief Disable the clock for specific IP.
734 *
735 * @param name Which clock to disable, see \ref clock_ip_name_t.
736 */
737static inline void CLOCK_DisableClock(clock_ip_name_t name)
738{
739 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
740 (*(volatile uint32_t *)regAddr) &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
741}
742
743/*!
744 * @brief Set ERCLK32K source.
745 *
746 * @param src The value to set ERCLK32K clock source.
747 */
748static inline void CLOCK_SetEr32kClock(uint32_t src)
749{
750 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
751}
752
753/*!
754 * @brief Set SDHC0 clock source.
755 *
756 * @param src The value to set SDHC0 clock source.
757 */
758static inline void CLOCK_SetSdhc0Clock(uint32_t src)
759{
760 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) | SIM_SOPT2_SDHCSRC(src));
761}
762
763/*!
764 * @brief Set LPUART clock source.
765 *
766 * @param src The value to set LPUART clock source.
767 */
768static inline void CLOCK_SetLpuartClock(uint32_t src)
769{
770 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUARTSRC_MASK) | SIM_SOPT2_LPUARTSRC(src));
771}
772
773/*!
774 * @brief Set enet timestamp clock source.
775 *
776 * @param src The value to set enet timestamp clock source.
777 */
778static inline void CLOCK_SetEnetTime0Clock(uint32_t src)
779{
780 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TIMESRC_MASK) | SIM_SOPT2_TIMESRC(src));
781}
782
783/*!
784 * @brief Set RMII clock source.
785 *
786 * @param src The value to set RMII clock source.
787 */
788static inline void CLOCK_SetRmii0Clock(uint32_t src)
789{
790 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RMIISRC_MASK) | SIM_SOPT2_RMIISRC(src));
791}
792
793/*!
794 * @brief Set TPM clock source.
795 *
796 * @param src The value to set TPM clock source.
797 */
798static inline void CLOCK_SetTpmClock(uint32_t src)
799{
800 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) | SIM_SOPT2_TPMSRC(src));
801}
802
803/*!
804 * @brief Set debug trace clock source.
805 *
806 * @param src The value to set debug trace clock source.
807 * @param divValue PLLFLL clock divider divisor.
808 * @param fracValue PLLFLL clock divider fraction.
809 */
810static inline void CLOCK_SetTraceClock(uint32_t src, uint32_t divValue, uint32_t fracValue)
811{
812 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src));
813 SIM->CLKDIV4 = SIM_CLKDIV4_TRACEDIV(divValue) | SIM_CLKDIV4_TRACEFRAC(fracValue);
814}
815
816/*!
817 * @brief Set PLLFLLSEL clock source.
818 *
819 * @param src The value to set PLLFLLSEL clock source.
820 * @param divValue PLLFLL clock divider divisor.
821 * @param fracValue PLLFLL clock divider fraction.
822 */
823static inline void CLOCK_SetPllFllSelClock(uint32_t src, uint32_t divValue, uint32_t fracValue)
824{
825 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src));
826 SIM->CLKDIV3 = SIM_CLKDIV3_PLLFLLDIV(divValue) | SIM_CLKDIV3_PLLFLLFRAC(fracValue);
827}
828
829/*!
830 * @brief Set CLKOUT source.
831 *
832 * @param src The value to set CLKOUT source.
833 */
834static inline void CLOCK_SetClkOutClock(uint32_t src)
835{
836 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
837}
838
839/*!
840 * @brief Set RTC_CLKOUT source.
841 *
842 * @param src The value to set RTC_CLKOUT source.
843 */
844static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
845{
846 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src));
847}
848
849/*! @brief Enable USB HS clock.
850 *
851 * This function only enables the access to USB HS prepheral, upper layer
852 * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
853 * clock to use USB HS.
854 *
855 * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
856 * @param freq USB HS does not care about the clock source, so this parameter is ignored.
857 * @retval true The clock is set successfully.
858 * @retval false The clock source is invalid to get proper USB HS clock.
859 */
860bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
861
862/*! @brief Disable USB HS clock.
863 *
864 * Disable USB HS clock, this function should not be called after
865 * @ref CLOCK_DisableUsbhs0PhyPllClock.
866 */
867void CLOCK_DisableUsbhs0Clock(void);
868
869/*! @brief Enable USB HS PHY PLL clock.
870 *
871 * This function enables the internal 480MHz USB PHY PLL clock.
872 *
873 * @param src USB HS PHY PLL clock source.
874 * @param freq The frequency specified by src.
875 * @retval true The clock is set successfully.
876 * @retval false The clock source is invalid to get proper USB HS clock.
877 */
878bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
879
880/*! @brief Disable USB HS PHY PLL clock.
881 *
882 * This function disables USB HS PHY PLL clock.
883 */
884void CLOCK_DisableUsbhs0PhyPllClock(void);
885
886/*! @brief Enable USB HS PFD clock.
887 *
888 * This function enables USB HS PFD clock. It should be called after function
889 * @ref CLOCK_EnableUsbhs0PhyPllClock.
890 * The PFD output clock is selected by the parameter @p src. When the @p src is
891 * @ref kCLOCK_UsbPfdSrcExt, then the PFD outout is from external crystal
892 * directly, in this case, the @p frac is not used. In other cases, the PFD_FRAC
893 * output clock frequency is 480MHz*18/frac, the PFD output frequency is based
894 * on the PFD_FRAC output.
895 *
896 * @param frac The value set to PFD_FRAC, it must be in the range of 18 to 35.
897 * @param src Source of the USB HS PFD clock (USB1PFDCLK).
898 */
899void CLOCK_EnableUsbhs0PfdClock(uint8_t frac, clock_usb_pfd_src_t src);
900
901/*! @brief Disable USB HS PFD clock.
902 *
903 * This function disables USB HS PFD clock. It should be called before function
904 * @ref CLOCK_DisableUsbhs0PhyPllClock.
905 */
906void CLOCK_DisableUsbhs0PfdClock(void);
907
908/*! @brief Enable USB FS clock.
909 *
910 * @param src USB FS clock source.
911 * @param freq The frequency specified by src.
912 * @retval true The clock is set successfully.
913 * @retval false The clock source is invalid to get proper USB FS clock.
914 */
915bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
916
917/*! @brief Disable USB FS clock.
918 *
919 * Disable USB FS clock.
920 */
921static inline void CLOCK_DisableUsbfs0Clock(void)
922{
923 CLOCK_DisableClock(kCLOCK_Usbfs0);
924}
925
926/*!
927 * @brief System clock divider
928 *
929 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4].
930 *
931 * @param outdiv1 Clock 1 output divider value.
932 *
933 * @param outdiv2 Clock 2 output divider value.
934 *
935 * @param outdiv3 Clock 3 output divider value.
936 *
937 * @param outdiv4 Clock 4 output divider value.
938 */
939static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4)
940{
941 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) |
942 SIM_CLKDIV1_OUTDIV4(outdiv4);
943}
944
945/*!
946 * @brief Gets the clock frequency for a specific clock name.
947 *
948 * This function checks the current clock configurations and then calculates
949 * the clock frequency for a specific clock name defined in clock_name_t.
950 * The MCG must be properly configured before using this function.
951 *
952 * @param clockName Clock names defined in clock_name_t
953 * @return Clock frequency value in Hertz
954 */
955uint32_t CLOCK_GetFreq(clock_name_t clockName);
956
957/*!
958 * @brief Get the core clock or system clock frequency.
959 *
960 * @return Clock frequency in Hz.
961 */
962uint32_t CLOCK_GetCoreSysClkFreq(void);
963
964/*!
965 * @brief Get the platform clock frequency.
966 *
967 * @return Clock frequency in Hz.
968 */
969uint32_t CLOCK_GetPlatClkFreq(void);
970
971/*!
972 * @brief Get the bus clock frequency.
973 *
974 * @return Clock frequency in Hz.
975 */
976uint32_t CLOCK_GetBusClkFreq(void);
977
978/*!
979 * @brief Get the flexbus clock frequency.
980 *
981 * @return Clock frequency in Hz.
982 */
983uint32_t CLOCK_GetFlexBusClkFreq(void);
984
985/*!
986 * @brief Get the flash clock frequency.
987 *
988 * @return Clock frequency in Hz.
989 */
990uint32_t CLOCK_GetFlashClkFreq(void);
991
992/*!
993 * @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
994 *
995 * @return Clock frequency in Hz.
996 */
997uint32_t CLOCK_GetPllFllSelClkFreq(void);
998
999/*!
1000 * @brief Get the external reference 32K clock frequency (ERCLK32K).
1001 *
1002 * @return Clock frequency in Hz.
1003 */
1004uint32_t CLOCK_GetEr32kClkFreq(void);
1005
1006/*!
1007 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
1008 *
1009 * @return Clock frequency in Hz.
1010 */
1011uint32_t CLOCK_GetOsc0ErClkFreq(void);
1012
1013/*!
1014 * @brief Get the OSC0 external reference divided clock frequency.
1015 *
1016 * @return Clock frequency in Hz.
1017 */
1018uint32_t CLOCK_GetOsc0ErClkDivFreq(void);
1019
1020/*!
1021 * @brief Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV).
1022 *
1023 * @return Clock frequency in Hz.
1024 */
1025uint32_t CLOCK_GetOsc0ErClkUndivFreq(void);
1026
1027/*!
1028 * @brief Set the clock configure in SIM module.
1029 *
1030 * This function sets system layer clock settings in SIM module.
1031 *
1032 * @param config Pointer to the configure structure.
1033 */
1034void CLOCK_SetSimConfig(sim_clock_config_t const *config);
1035
1036/*!
1037 * @brief Set the system clock dividers in SIM to safe value.
1038 *
1039 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
1040 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
1041 * changes then the system level clocks may be out of range. This function could
1042 * be used before MCG mode change, to make sure system level clocks are in allowed
1043 * range.
1044 *
1045 */
1046static inline void CLOCK_SetSimSafeDivs(void)
1047{
1048 SIM->CLKDIV1 = 0x02260000U;
1049}
1050
1051/*! @name MCG frequency functions. */
1052/*@{*/
1053
1054/*!
1055 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
1056 *
1057 * This function gets the MCG output clock frequency in Hz based on the current MCG
1058 * register value.
1059 *
1060 * @return The frequency of MCGOUTCLK.
1061 */
1062uint32_t CLOCK_GetOutClkFreq(void);
1063
1064/*!
1065 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
1066 *
1067 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
1068 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
1069 * disabled in low power state in other modes.
1070 *
1071 * @return The frequency of MCGFLLCLK.
1072 */
1073uint32_t CLOCK_GetFllFreq(void);
1074
1075/*!
1076 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
1077 *
1078 * This function gets the MCG internal reference clock frequency in Hz based
1079 * on the current MCG register value.
1080 *
1081 * @return The frequency of MCGIRCLK.
1082 */
1083uint32_t CLOCK_GetInternalRefClkFreq(void);
1084
1085/*!
1086 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
1087 *
1088 * This function gets the MCG fixed frequency clock frequency in Hz based
1089 * on the current MCG register value.
1090 *
1091 * @return The frequency of MCGFFCLK.
1092 */
1093uint32_t CLOCK_GetFixedFreqClkFreq(void);
1094
1095/*!
1096 * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
1097 *
1098 * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
1099 * register value.
1100 *
1101 * @return The frequency of MCGPLL0CLK.
1102 */
1103uint32_t CLOCK_GetPll0Freq(void);
1104
1105/*!
1106 * @brief Gets the MCG external PLL frequency.
1107 *
1108 * This function gets the MCG external PLL frequency in Hz.
1109 *
1110 * @return The frequency of the MCG external PLL.
1111 */
1112uint32_t CLOCK_GetExtPllFreq(void);
1113
1114/*!
1115 * @brief Sets the MCG external PLL frequency.
1116 *
1117 * This function sets the MCG external PLL frequency in Hz. The MCG external PLL
1118 * frequency is passed to the MCG driver using this function. Call this
1119 * function after the external PLL frequency is changed. Otherwise, the APIs, which are used to get
1120 * the frequency, may return an incorrect value.
1121 *
1122 * @param freq The frequency of MCG external PLL.
1123 */
1124void CLOCK_SetExtPllFreq(uint32_t freq);
1125
1126/*@}*/
1127
1128/*! @name MCG clock configuration. */
1129/*@{*/
1130
1131/*!
1132 * @brief Enables or disables the MCG low power.
1133 *
1134 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
1135 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
1136 * PBI modes, enabling low power sets the MCG to BLPI mode.
1137 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
1138 *
1139 * @param enable True to enable MCG low power, false to disable MCG low power.
1140 */
1141static inline void CLOCK_SetLowPowerEnable(bool enable)
1142{
1143 if (enable)
1144 {
1145 MCG->C2 |= MCG_C2_LP_MASK;
1146 }
1147 else
1148 {
1149 MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
1150 }
1151}
1152
1153/*!
1154 * @brief Configures the Internal Reference clock (MCGIRCLK).
1155 *
1156 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
1157 * source. If the fast IRC is used, this function sets the fast IRC divider.
1158 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
1159 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
1160 * using the function in these modes it is not allowed.
1161 *
1162 * @param enableMode MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
1163 * @param ircs MCGIRCLK clock source, choose fast or slow.
1164 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
1165 * @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source,
1166 * the configuration should not be changed. Otherwise, a glitch occurs.
1167 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
1168 */
1169status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
1170
1171/*!
1172 * @brief Selects the MCG external reference clock.
1173 *
1174 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
1175 * and waits for the clock source to be stable. Because the external reference
1176 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
1177 *
1178 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
1179 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
1180 * the configuration should not be changed. Otherwise, a glitch occurs.
1181 * @retval kStatus_Success External reference clock set successfully.
1182 */
1183status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
1184
1185/*!
1186 * @brief Set the FLL external reference clock divider value.
1187 *
1188 * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
1189 *
1190 * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
1191 */
1192static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
1193{
1194 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
1195}
1196
1197/*!
1198 * @brief Enables the PLL0 in FLL mode.
1199 *
1200 * This function sets us the PLL0 in FLL mode and reconfigures
1201 * the PLL0. Ensure that the PLL reference
1202 * clock is enabled before calling this function and that the PLL0 is not used as a clock source.
1203 * The function CLOCK_CalcPllDiv gets the correct PLL
1204 * divider values.
1205 *
1206 * @param config Pointer to the configuration structure.
1207 */
1208void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1209
1210/*!
1211 * @brief Disables the PLL0 in FLL mode.
1212 *
1213 * This function disables the PLL0 in FLL mode. It should be used together with the
1214 * @ref CLOCK_EnablePll0.
1215 */
1216static inline void CLOCK_DisablePll0(void)
1217{
1218 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK));
1219}
1220
1221/*!
1222 * @brief Calculates the PLL divider setting for a desired output frequency.
1223 *
1224 * This function calculates the correct reference clock divider (\c PRDIV) and
1225 * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
1226 * closest frequency match with the corresponding \c PRDIV/VDIV
1227 * returned from parameters. If a desired frequency is not valid, this function
1228 * returns 0.
1229 *
1230 * @param refFreq PLL reference clock frequency.
1231 * @param desireFreq Desired PLL output frequency.
1232 * @param prdiv PRDIV value to generate desired PLL frequency.
1233 * @param vdiv VDIV value to generate desired PLL frequency.
1234 * @return Closest frequency match that the PLL was able generate.
1235 */
1236uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv);
1237
1238/*!
1239 * @brief Set the PLL selection.
1240 *
1241 * This function sets the PLL selection between PLL0/PLL1/EXTPLL, and waits for
1242 * change finished.
1243 *
1244 * @param pllcs The PLL to select.
1245 */
1246void CLOCK_SetPllClkSel(mcg_pll_clk_select_t pllcs);
1247
1248/*@}*/
1249
1250/*! @name MCG clock lock monitor functions. */
1251/*@{*/
1252
1253/*!
1254 * @brief Sets the OSC0 clock monitor mode.
1255 *
1256 * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1257 *
1258 * @param mode Monitor mode to set.
1259 */
1260void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
1261
1262/*!
1263 * @brief Sets the RTC OSC clock monitor mode.
1264 *
1265 * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
1266 *
1267 * @param mode Monitor mode to set.
1268 */
1269void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
1270
1271/*!
1272 * @brief Sets the PLL0 clock monitor mode.
1273 *
1274 * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1275 *
1276 * @param mode Monitor mode to set.
1277 */
1278void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
1279
1280/*!
1281 * @brief Sets the external PLL clock monitor mode.
1282 *
1283 * This function ets the external PLL clock monitor mode. See @ref mcg_monitor_mode_t
1284 * for details.
1285 *
1286 * @param mode Monitor mode to set.
1287 */
1288void CLOCK_SetExtPllMonitorMode(mcg_monitor_mode_t mode);
1289
1290/*!
1291 * @brief Gets the MCG status flags.
1292 *
1293 * This function gets the MCG clock status flags. All status flags are
1294 * returned as a logical OR of the enumeration refer to _mcg_status_flags_t. To
1295 * check a specific flag, compare the return value with the flag.
1296 *
1297 * Example:
1298 * @code
1299 * To check the clock lost lock status of OSC0 and PLL0.
1300 * uint32_t mcgFlags;
1301 *
1302 * mcgFlags = CLOCK_GetStatusFlags();
1303 *
1304 * if (mcgFlags & kMCG_Osc0LostFlag)
1305 * {
1306 * OSC0 clock lock lost. Do something.
1307 * }
1308 * if (mcgFlags & kMCG_Pll0LostFlag)
1309 * {
1310 * PLL0 clock lock lost. Do something.
1311 * }
1312 * @endcode
1313 *
1314 * @return Logical OR value of the enumeration _mcg_status_flags_t.
1315 */
1316uint32_t CLOCK_GetStatusFlags(void);
1317
1318/*!
1319 * @brief Clears the MCG status flags.
1320 *
1321 * This function clears the MCG clock lock lost status. The parameter is a logical
1322 * OR value of the flags to clear. See the enumeration _mcg_status_flags_t.
1323 *
1324 * Example:
1325 * @code
1326 * To clear the clock lost lock status flags of OSC0 and PLL0.
1327 *
1328 * CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
1329 * @endcode
1330 *
1331 * @param mask The status flags to clear. This is a logical OR of members of the
1332 * enumeration _mcg_status_flags_t.
1333 */
1334void CLOCK_ClearStatusFlags(uint32_t mask);
1335
1336/*@}*/
1337
1338/*!
1339 * @name OSC configuration
1340 * @{
1341 */
1342
1343/*!
1344 * @brief Configures the OSC external reference clock (OSCERCLK).
1345 *
1346 * This function configures the OSC external reference clock (OSCERCLK).
1347 * This is an example to enable the OSCERCLK in normal and stop modes and also set
1348 * the output divider to 1:
1349 *
1350 @code
1351 oscer_config_t config =
1352 {
1353 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
1354 .erclkDiv = 1U,
1355 };
1356
1357 OSC_SetExtRefClkConfig(OSC, &config);
1358 @endcode
1359 *
1360 * @param base OSC peripheral address.
1361 * @param config Pointer to the configuration structure.
1362 */
1363static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
1364{
1365 uint8_t reg = base->CR;
1366
1367 reg &= (uint8_t)(~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK));
1368 reg |= config->enableMode;
1369
1370 base->CR = reg;
1371
1372 base->DIV = OSC_DIV_ERPS(config->erclkDiv);
1373}
1374
1375/*!
1376 * @brief Sets the capacitor load configuration for the oscillator.
1377 *
1378 * This function sets the specified capacitors configuration for the oscillator.
1379 * This should be done in the early system level initialization function call
1380 * based on the system configuration.
1381 *
1382 * @param base OSC peripheral address.
1383 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
1384 *
1385 * Example:
1386 @code
1387 To enable only 2 pF and 8 pF capacitor load, please use like this.
1388 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
1389 @endcode
1390 */
1391static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
1392{
1393 uint8_t reg = base->CR;
1394
1395 reg &= (uint8_t)(~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK));
1396 reg |= capLoad;
1397
1398 base->CR = reg;
1399}
1400
1401/*!
1402 * @brief Initializes the OSC0.
1403 *
1404 * This function initializes the OSC0 according to the board configuration.
1405 *
1406 * @param config Pointer to the OSC0 configuration structure.
1407 */
1408void CLOCK_InitOsc0(osc_config_t const *config);
1409
1410/*!
1411 * @brief Deinitializes the OSC0.
1412 *
1413 * This function deinitializes the OSC0.
1414 */
1415void CLOCK_DeinitOsc0(void);
1416
1417/* @} */
1418
1419/*!
1420 * @name External clock frequency
1421 * @{
1422 */
1423
1424/*!
1425 * @brief Sets the XTAL0 frequency based on board settings.
1426 *
1427 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
1428 */
1429static inline void CLOCK_SetXtal0Freq(uint32_t freq)
1430{
1431 g_xtal0Freq = freq;
1432}
1433
1434/*!
1435 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
1436 *
1437 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
1438 */
1439static inline void CLOCK_SetXtal32Freq(uint32_t freq)
1440{
1441 g_xtal32Freq = freq;
1442}
1443/* @} */
1444
1445/*!
1446 * @name IRCs frequency
1447 * @{
1448 */
1449
1450/*!
1451 * @brief Set the Slow IRC frequency based on the trimmed value
1452 *
1453 * @param freq The Slow IRC frequency input clock frequency in Hz.
1454 */
1455void CLOCK_SetSlowIrcFreq(uint32_t freq);
1456
1457/*!
1458 * @brief Set the Fast IRC frequency based on the trimmed value
1459 *
1460 * @param freq The Fast IRC frequency input clock frequency in Hz.
1461 */
1462void CLOCK_SetFastIrcFreq(uint32_t freq);
1463/* @} */
1464
1465/*!
1466 * @name MCG auto-trim machine.
1467 * @{
1468 */
1469
1470/*!
1471 * @brief Auto trims the internal reference clock.
1472 *
1473 * This function trims the internal reference clock by using the external clock. If
1474 * successful, it returns the kStatus_Success and the frequency after
1475 * trimming is received in the parameter @p actualFreq. If an error occurs,
1476 * the error code is returned.
1477 *
1478 * @param extFreq External clock frequency, which should be a bus clock.
1479 * @param desireFreq Frequency to trim to.
1480 * @param actualFreq Actual frequency after trimming.
1481 * @param atms Trim fast or slow internal reference clock.
1482 * @retval kStatus_Success ATM success.
1483 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
1484 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
1485 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
1486 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
1487 */
1488status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
1489/* @} */
1490
1491/*! @name MCG mode functions. */
1492/*@{*/
1493
1494/*!
1495 * @brief Gets the current MCG mode.
1496 *
1497 * This function checks the MCG registers and determines the current MCG mode.
1498 *
1499 * @return Current MCG mode or error code; See @ref mcg_mode_t.
1500 */
1501mcg_mode_t CLOCK_GetMode(void);
1502
1503/*!
1504 * @brief Sets the MCG to FEI mode.
1505 *
1506 * This function sets the MCG to FEI mode. If setting to FEI mode fails
1507 * from the current mode, this function returns an error.
1508 *
1509 * @param dmx32 DMX32 in FEI mode.
1510 * @param drs The DCO range selection.
1511 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
1512 * NULL does not cause a delay.
1513 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1514 * @retval kStatus_Success Switched to the target mode successfully.
1515 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1516 * to a frequency above 32768 Hz.
1517 */
1518status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1519
1520/*!
1521 * @brief Sets the MCG to FEE mode.
1522 *
1523 * This function sets the MCG to FEE mode. If setting to FEE mode fails
1524 * from the current mode, this function returns an error.
1525 *
1526 * @param frdiv FLL reference clock divider setting, FRDIV.
1527 * @param dmx32 DMX32 in FEE mode.
1528 * @param drs The DCO range selection.
1529 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
1530 * NULL does not cause a delay.
1531 *
1532 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1533 * @retval kStatus_Success Switched to the target mode successfully.
1534 */
1535status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1536
1537/*!
1538 * @brief Sets the MCG to FBI mode.
1539 *
1540 * This function sets the MCG to FBI mode. If setting to FBI mode fails
1541 * from the current mode, this function returns an error.
1542 *
1543 * @param dmx32 DMX32 in FBI mode.
1544 * @param drs The DCO range selection.
1545 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1546 * is not used in FBI mode, this parameter can be NULL. Passing
1547 * NULL does not cause a delay.
1548 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1549 * @retval kStatus_Success Switched to the target mode successfully.
1550 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1551 * to frequency above 32768 Hz.
1552 */
1553status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1554
1555/*!
1556 * @brief Sets the MCG to FBE mode.
1557 *
1558 * This function sets the MCG to FBE mode. If setting to FBE mode fails
1559 * from the current mode, this function returns an error.
1560 *
1561 * @param frdiv FLL reference clock divider setting, FRDIV.
1562 * @param dmx32 DMX32 in FBE mode.
1563 * @param drs The DCO range selection.
1564 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1565 * is not used in FBE mode, this parameter can be NULL. Passing NULL
1566 * does not cause a delay.
1567 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1568 * @retval kStatus_Success Switched to the target mode successfully.
1569 */
1570status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1571
1572/*!
1573 * @brief Sets the MCG to BLPI mode.
1574 *
1575 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
1576 * from the current mode, this function returns an error.
1577 *
1578 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1579 * @retval kStatus_Success Switched to the target mode successfully.
1580 */
1581status_t CLOCK_SetBlpiMode(void);
1582
1583/*!
1584 * @brief Sets the MCG to BLPE mode.
1585 *
1586 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
1587 * from the current mode, this function returns an error.
1588 *
1589 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1590 * @retval kStatus_Success Switched to the target mode successfully.
1591 */
1592status_t CLOCK_SetBlpeMode(void);
1593
1594/*!
1595 * @brief Sets the MCG to PBE mode.
1596 *
1597 * This function sets the MCG to PBE mode. If setting to PBE mode fails
1598 * from the current mode, this function returns an error.
1599 *
1600 * @param pllcs The PLL selection, PLLCS.
1601 * @param config Pointer to the PLL configuration.
1602 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1603 * @retval kStatus_Success Switched to the target mode successfully.
1604 *
1605 * @note
1606 * 1. The parameter \c pllcs selects the PLL. For platforms with
1607 * only one PLL, the parameter pllcs is kept for interface compatibility.
1608 * 2. The parameter \c config is the PLL configuration structure. On some
1609 * platforms, it is possible to choose the external PLL directly, which renders the
1610 * configuration structure not necessary. In this case, pass in NULL.
1611 * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
1612 */
1613status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1614
1615/*!
1616 * @brief Sets the MCG to PEE mode.
1617 *
1618 * This function sets the MCG to PEE mode.
1619 *
1620 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1621 * @retval kStatus_Success Switched to the target mode successfully.
1622 *
1623 * @note This function only changes the CLKS to use the PLL/FLL output. If the
1624 * PRDIV/VDIV are different than in the PBE mode, set them up
1625 * in PBE mode and wait. When the clock is stable, switch to PEE mode.
1626 */
1627status_t CLOCK_SetPeeMode(void);
1628
1629/*!
1630 * @brief Switches the MCG to FBE mode from the external mode.
1631 *
1632 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
1633 * The external clock is used as the system clock source and PLL is disabled. However,
1634 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
1635 * during the mode switch. For example, to switch from PEE mode to FEI mode:
1636 *
1637 * @code
1638 * CLOCK_ExternalModeToFbeModeQuick();
1639 * CLOCK_SetFeiMode(...);
1640 * @endcode
1641 *
1642 * @retval kStatus_Success Switched successfully.
1643 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
1644 */
1645status_t CLOCK_ExternalModeToFbeModeQuick(void);
1646
1647/*!
1648 * @brief Switches the MCG to FBI mode from internal modes.
1649 *
1650 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
1651 * The MCGIRCLK is used as the system clock source and PLL is disabled. However,
1652 * FLL settings are not configured. This is a lite function with a small code size, which is useful
1653 * during the mode switch. For example, to switch from PEI mode to FEE mode:
1654 *
1655 * @code
1656 * CLOCK_InternalModeToFbiModeQuick();
1657 * CLOCK_SetFeeMode(...);
1658 * @endcode
1659 *
1660 * @retval kStatus_Success Switched successfully.
1661 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
1662 */
1663status_t CLOCK_InternalModeToFbiModeQuick(void);
1664
1665/*!
1666 * @brief Sets the MCG to FEI mode during system boot up.
1667 *
1668 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
1669 * set up MCG during system boot up.
1670 *
1671 * @param dmx32 DMX32 in FEI mode.
1672 * @param drs The DCO range selection.
1673 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1674 *
1675 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1676 * @retval kStatus_Success Switched to the target mode successfully.
1677 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1678 * to frequency above 32768 Hz.
1679 */
1680status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1681
1682/*!
1683 * @brief Sets the MCG to FEE mode during system bootup.
1684 *
1685 * This function sets MCG to FEE mode from the reset mode. It can also be used to
1686 * set up the MCG during system boot up.
1687 *
1688 * @param oscsel OSC clock select, OSCSEL.
1689 * @param frdiv FLL reference clock divider setting, FRDIV.
1690 * @param dmx32 DMX32 in FEE mode.
1691 * @param drs The DCO range selection.
1692 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1693 *
1694 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1695 * @retval kStatus_Success Switched to the target mode successfully.
1696 */
1697status_t CLOCK_BootToFeeMode(
1698 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1699
1700/*!
1701 * @brief Sets the MCG to BLPI mode during system boot up.
1702 *
1703 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
1704 * set up the MCG during system boot up.
1705 *
1706 * @param fcrdiv Fast IRC divider, FCRDIV.
1707 * @param ircs The internal reference clock to select, IRCS.
1708 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
1709 *
1710 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
1711 * @retval kStatus_Success Switched to the target mode successfully.
1712 */
1713status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
1714
1715/*!
1716 * @brief Sets the MCG to BLPE mode during system boot up.
1717 *
1718 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
1719 * set up the MCG during system boot up.
1720 *
1721 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1722 *
1723 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1724 * @retval kStatus_Success Switched to the target mode successfully.
1725 */
1726status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
1727
1728/*!
1729 * @brief Sets the MCG to PEE mode during system boot up.
1730 *
1731 * This function sets the MCG to PEE mode from reset mode. It can also be used to
1732 * set up the MCG during system boot up.
1733 *
1734 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1735 * @param pllcs The PLL selection, PLLCS.
1736 * @param config Pointer to the PLL configuration.
1737 *
1738 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1739 * @retval kStatus_Success Switched to the target mode successfully.
1740 */
1741status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1742
1743/*!
1744 * @brief Sets the MCG to a target mode.
1745 *
1746 * This function sets MCG to a target mode defined by the configuration
1747 * structure. If switching to the target mode fails, this function
1748 * chooses the correct path.
1749 *
1750 * @param config Pointer to the target MCG mode configuration structure.
1751 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code _mcg_status.
1752 *
1753 * @note If the external clock is used in the target mode, ensure that it is
1754 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
1755 * function.
1756 */
1757status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
1758
1759/*@}*/
1760
1761#if defined(__cplusplus)
1762}
1763#endif /* __cplusplus */
1764
1765/*! @} */
1766
1767#endif /* _FSL_CLOCK_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 20:18:00 +0100