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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/MK65F18.h30702
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/MK65F18_features.h1901
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/arm/MKD256_4KB_SECTOR.FLMbin0 -> 28436 bytes
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/arm/MK_P1M0.FLMbin0 -> 26580 bytes
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/arm/MK_P2M0.FLMbin0 -> 26580 bytes
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/drivers/driver_reset.cmake14
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/drivers/fsl_clock.c2671
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/drivers/fsl_clock.h1767
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/fsl_device_registers.h35
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/gcc/MK65FN2M0xxx18_flash.ld223
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/gcc/MK65FN2M0xxx18_ram.ld214
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/gcc/MK65FX1M0xxx18_flash.ld223
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/gcc/MK65FX1M0xxx18_ram.ld214
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/gcc/startup_MK65F18.S1060
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/mcuxpresso/startup_mk65f18.c1040
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/mcuxpresso/startup_mk65f18.cpp1040
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/project_template/board.c30
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/project_template/board.h193
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/project_template/clock_config.c180
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/project_template/clock_config.h76
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/project_template/peripherals.c51
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/project_template/peripherals.h34
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/project_template/pin_mux.c60
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/project_template/pin_mux.h52
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/system_MK65F18.c242
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/system_MK65F18.h145
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/template/RTE_Device.h209
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/utilities/fsl_notifier.c209
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/utilities/fsl_notifier.h237
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/utilities/fsl_shell.c1085
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/utilities/fsl_shell.h292
31 files changed, 44199 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/MK65F18.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/MK65F18.h
new file mode 100644
index 000000000..042036c55
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MK65F18/MK65F18.h
@@ -0,0 +1,30702 @@
1/*
2** ###################################################################
3** Processors: MK65FN2M0CAC18
4** MK65FN2M0VMI18
5** MK65FX1M0CAC18
6** MK65FX1M0VMI18
7**
8** Compilers: Keil ARM C/C++ Compiler
9** Freescale C/C++ for Embedded ARM
10** GNU C Compiler
11** IAR ANSI C/C++ Compiler for ARM
12** MCUXpresso Compiler
13**
14** Reference manual: K65P169M180SF5RMV2, Rev. 1, Mar 2015
15** Version: rev. 3.0, 2015-03-25
16** Build: b180801
17**
18** Abstract:
19** CMSIS Peripheral Access Layer for MK65F18
20**
21** Copyright 1997-2016 Freescale Semiconductor, Inc.
22** Copyright 2016-2018 NXP
23**
24** SPDX-License-Identifier: BSD-3-Clause
25**
26** http: www.nxp.com
27** mail: [email protected]
28**
29** Revisions:
30** - rev. 1.0 (2013-09-02)
31** Initial version.
32** - rev. 2.0 (2014-02-17)
33** Register accessor macros added to the memory map.
34** Symbols for Processor Expert memory map compatibility added to the memory map.
35** Startup file for gcc has been updated according to CMSIS 3.2.
36** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
37** Update according to reference manual rev. 2
38** - rev. 2.1 (2014-04-16)
39** Update of SystemInit() and SystemCoreClockUpdate() functions.
40** - rev. 2.2 (2014-10-14)
41** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
42** - rev. 2.3 (2014-11-20)
43** Update according to reverence manual K65P169M180SF5RMV2_NDA, Rev. 0 Draft A, October 2014.
44** Update of SystemInit() to use 16MHz external crystal.
45** - rev. 2.4 (2015-02-19)
46** Renamed interrupt vector LLW to LLWU.
47** - rev. 3.0 (2015-03-25)
48** Registers updated according to the reference manual revision 1, March 2015
49**
50** ###################################################################
51*/
52
53/*!
54 * @file MK65F18.h
55 * @version 3.0
56 * @date 2015-03-25
57 * @brief CMSIS Peripheral Access Layer for MK65F18
58 *
59 * CMSIS Peripheral Access Layer for MK65F18
60 */
61
62#ifndef _MK65F18_H_
63#define _MK65F18_H_ /**< Symbol preventing repeated inclusion */
64
65/** Memory map major version (memory maps with equal major version number are
66 * compatible) */
67#define MCU_MEM_MAP_VERSION 0x0300U
68/** Memory map minor version */
69#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
70
71/**
72 * @brief Macro to calculate address of an aliased word in the peripheral
73 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
74 * 0x400FFFFF).
75 * @param Reg Register to access.
76 * @param Bit Bit number to access.
77 * @return Address of the aliased word in the peripheral bitband area.
78 */
79#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
80/**
81 * @brief Macro to access a single bit of a peripheral register (bit band region
82 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
83 * be used for peripherals with 32bit access allowed.
84 * @param Reg Register to access.
85 * @param Bit Bit number to access.
86 * @return Value of the targeted bit in the bit band region.
87 */
88#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
89#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
90/**
91 * @brief Macro to access a single bit of a peripheral register (bit band region
92 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
93 * be used for peripherals with 16bit access allowed.
94 * @param Reg Register to access.
95 * @param Bit Bit number to access.
96 * @return Value of the targeted bit in the bit band region.
97 */
98#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
99/**
100 * @brief Macro to access a single bit of a peripheral register (bit band region
101 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
102 * be used for peripherals with 8bit access allowed.
103 * @param Reg Register to access.
104 * @param Bit Bit number to access.
105 * @return Value of the targeted bit in the bit band region.
106 */
107#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
108
109/* ----------------------------------------------------------------------------
110 -- Interrupt vector numbers
111 ---------------------------------------------------------------------------- */
112
113/*!
114 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
115 * @{
116 */
117
118/** Interrupt Number Definitions */
119#define NUMBER_OF_INT_VECTORS 116 /**< Number of interrupts in the Vector table */
120
121typedef enum IRQn {
122 /* Auxiliary constants */
123 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
124
125 /* Core interrupts */
126 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
127 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
128 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
129 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
130 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
131 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
132 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
133 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
134 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
135
136 /* Device specific interrupts */
137 DMA0_DMA16_IRQn = 0, /**< DMA Channel 0, 16 Transfer Complete */
138 DMA1_DMA17_IRQn = 1, /**< DMA Channel 1, 17 Transfer Complete */
139 DMA2_DMA18_IRQn = 2, /**< DMA Channel 2, 18 Transfer Complete */
140 DMA3_DMA19_IRQn = 3, /**< DMA Channel 3, 19 Transfer Complete */
141 DMA4_DMA20_IRQn = 4, /**< DMA Channel 4, 20 Transfer Complete */
142 DMA5_DMA21_IRQn = 5, /**< DMA Channel 5, 21 Transfer Complete */
143 DMA6_DMA22_IRQn = 6, /**< DMA Channel 6, 22 Transfer Complete */
144 DMA7_DMA23_IRQn = 7, /**< DMA Channel 7, 23 Transfer Complete */
145 DMA8_DMA24_IRQn = 8, /**< DMA Channel 8, 24 Transfer Complete */
146 DMA9_DMA25_IRQn = 9, /**< DMA Channel 9, 25 Transfer Complete */
147 DMA10_DMA26_IRQn = 10, /**< DMA Channel 10, 26 Transfer Complete */
148 DMA11_DMA27_IRQn = 11, /**< DMA Channel 11, 27 Transfer Complete */
149 DMA12_DMA28_IRQn = 12, /**< DMA Channel 12, 28 Transfer Complete */
150 DMA13_DMA29_IRQn = 13, /**< DMA Channel 13, 29 Transfer Complete */
151 DMA14_DMA30_IRQn = 14, /**< DMA Channel 14, 30 Transfer Complete */
152 DMA15_DMA31_IRQn = 15, /**< DMA Channel 15, 31 Transfer Complete */
153 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
154 MCM_IRQn = 17, /**< Normal Interrupt */
155 FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
156 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
157 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
158 LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */
159 WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */
160 RNG_IRQn = 23, /**< RNG Interrupt */
161 I2C0_IRQn = 24, /**< I2C0 interrupt */
162 I2C1_IRQn = 25, /**< I2C1 interrupt */
163 SPI0_IRQn = 26, /**< SPI0 Interrupt */
164 SPI1_IRQn = 27, /**< SPI1 Interrupt */
165 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
166 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
167 Reserved46_IRQn = 30, /**< Reserved interrupt 46 */
168 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
169 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
170 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
171 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
172 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
173 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
174 UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
175 UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
176 ADC0_IRQn = 39, /**< ADC0 interrupt */
177 CMP0_IRQn = 40, /**< CMP0 interrupt */
178 CMP1_IRQn = 41, /**< CMP1 interrupt */
179 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
180 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
181 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
182 CMT_IRQn = 45, /**< CMT interrupt */
183 RTC_IRQn = 46, /**< RTC interrupt */
184 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
185 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
186 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
187 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
188 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
189 PDB0_IRQn = 52, /**< PDB0 Interrupt */
190 USB0_IRQn = 53, /**< USB0 interrupt */
191 USBDCD_IRQn = 54, /**< USBDCD Interrupt */
192 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
193 DAC0_IRQn = 56, /**< DAC0 interrupt */
194 MCG_IRQn = 57, /**< MCG Interrupt */
195 LPTMR0_IRQn = 58, /**< LPTimer interrupt */
196 PORTA_IRQn = 59, /**< Port A interrupt */
197 PORTB_IRQn = 60, /**< Port B interrupt */
198 PORTC_IRQn = 61, /**< Port C interrupt */
199 PORTD_IRQn = 62, /**< Port D interrupt */
200 PORTE_IRQn = 63, /**< Port E interrupt */
201 SWI_IRQn = 64, /**< Software interrupt */
202 SPI2_IRQn = 65, /**< SPI2 Interrupt */
203 UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
204 UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
205 Reserved84_IRQn = 68, /**< Reserved interrupt 84 */
206 Reserved85_IRQn = 69, /**< Reserved interrupt 85 */
207 CMP2_IRQn = 70, /**< CMP2 interrupt */
208 FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
209 DAC1_IRQn = 72, /**< DAC1 interrupt */
210 ADC1_IRQn = 73, /**< ADC1 interrupt */
211 I2C2_IRQn = 74, /**< I2C2 interrupt */
212 CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
213 CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
214 CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
215 CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
216 CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
217 CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
218 SDHC_IRQn = 81, /**< SDHC interrupt */
219 ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
220 ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */
221 ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */
222 ENET_Error_IRQn = 85, /**< Ethernet MAC Error and miscelaneous Interrupt */
223 LPUART0_IRQn = 86, /**< LPUART0 status/error interrupt */
224 TSI0_IRQn = 87, /**< TSI0 interrupt */
225 TPM1_IRQn = 88, /**< TPM1 fault, overflow and channels interrupt */
226 TPM2_IRQn = 89, /**< TPM2 fault, overflow and channels interrupt */
227 USBHSDCD_IRQn = 90, /**< USBHSDCD, USBHS Phy Interrupt */
228 I2C3_IRQn = 91, /**< I2C3 interrupt */
229 CMP3_IRQn = 92, /**< CMP3 interrupt */
230 USBHS_IRQn = 93, /**< USB high speed OTG interrupt */
231 CAN1_ORed_Message_buffer_IRQn = 94, /**< CAN1 OR'd message buffers interrupt */
232 CAN1_Bus_Off_IRQn = 95, /**< CAN1 bus off interrupt */
233 CAN1_Error_IRQn = 96, /**< CAN1 error interrupt */
234 CAN1_Tx_Warning_IRQn = 97, /**< CAN1 Tx warning interrupt */
235 CAN1_Rx_Warning_IRQn = 98, /**< CAN1 Rx warning interrupt */
236 CAN1_Wake_Up_IRQn = 99 /**< CAN1 wake up interrupt */
237} IRQn_Type;
238
239/*!
240 * @}
241 */ /* end of group Interrupt_vector_numbers */
242
243
244/* ----------------------------------------------------------------------------
245 -- Cortex M4 Core Configuration
246 ---------------------------------------------------------------------------- */
247
248/*!
249 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
250 * @{
251 */
252
253#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
254#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
255#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
256#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
257
258#include "core_cm4.h" /* Core Peripheral Access Layer */
259#include "system_MK65F18.h" /* Device specific configuration file */
260
261/*!
262 * @}
263 */ /* end of group Cortex_Core_Configuration */
264
265
266/* ----------------------------------------------------------------------------
267 -- Mapping Information
268 ---------------------------------------------------------------------------- */
269
270/*!
271 * @addtogroup Mapping_Information Mapping Information
272 * @{
273 */
274
275/** Mapping Information */
276/*!
277 * @addtogroup edma_request
278 * @{
279 */
280
281/*******************************************************************************
282 * Definitions
283 ******************************************************************************/
284
285/*!
286 * @brief Structure for the DMA hardware request
287 *
288 * Defines the structure for the DMA hardware request collections. The user can configure the
289 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
290 * of the hardware request varies according to the to SoC.
291 */
292typedef enum _dma_request_source
293{
294 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
295 kDmaRequestMux0TSI0 = 1|0x100U, /**< TSI0. */
296 kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */
297 kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */
298 kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */
299 kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */
300 kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */
301 kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */
302 kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 Receive. */
303 kDmaRequestMux0UART3Tx = 9|0x100U, /**< UART3 Transmit. */
304 kDmaRequestMux0UART4 = 10|0x100U, /**< UART4 Transmit or Receive. */
305 kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */
306 kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */
307 kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */
308 kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
309 kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
310 kDmaRequestMux0SPI1Rx = 16|0x100U, /**< SPI1 Receive. */
311 kDmaRequestMux0SPI1Tx = 17|0x100U, /**< SPI1 Transmit. */
312 kDmaRequestMux0I2C0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */
313 kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0 and I2C3. */
314 kDmaRequestMux0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */
315 kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
316 kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */
317 kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
318 kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
319 kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
320 kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
321 kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
322 kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
323 kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
324 kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */
325 kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */
326 kDmaRequestMux0FTM1TPM1Channel0 = 28|0x100U, /**< FTM1 C0V and TPM1 C0V. */
327 kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V and TPM1 C0V. */
328 kDmaRequestMux0TPM1Channel0 = 28|0x100U, /**< FTM1 C0V and TPM1 C0V. */
329 kDmaRequestMux0FTM1TPM1Channel1 = 29|0x100U, /**< FTM1 C1V and TPM1 C1V. */
330 kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V and TPM1 C1V. */
331 kDmaRequestMux0TPM1Channel1 = 29|0x100U, /**< FTM1 C1V and TPM1 C1V. */
332 kDmaRequestMux0FTM2TPM2Channel0 = 30|0x100U, /**< FTM2 C0V and TPM2 C0V. */
333 kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V and TPM2 C0V. */
334 kDmaRequestMux0TPM2Channel0 = 30|0x100U, /**< FTM2 C0V and TPM2 C0V. */
335 kDmaRequestMux0FTM2TPM2Channel1 = 31|0x100U, /**< FTM2 C1V and TPM2 C1V. */
336 kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V and TPM2 C1V. */
337 kDmaRequestMux0TPM2Channel1 = 31|0x100U, /**< FTM2 C1V and TPM2 C1V. */
338 kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */
339 kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */
340 kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */
341 kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */
342 kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */
343 kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */
344 kDmaRequestMux0FTM3Channel6SPI2Rx = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */
345 kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */
346 kDmaRequestMux0SPI2Rx = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */
347 kDmaRequestMux0FTM3Channel7SPI2Tx = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */
348 kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */
349 kDmaRequestMux0SPI2Tx = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */
350 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
351 kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */
352 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
353 kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
354 kDmaRequestMux0CMP2CMP3 = 44|0x100U, /**< CMP2 and CMP3. */
355 kDmaRequestMux0CMP2 = 44|0x100U, /**< CMP2 and CMP3. */
356 kDmaRequestMux0CMP3 = 44|0x100U, /**< CMP2 and CMP3. */
357 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
358 kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1. */
359 kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */
360 kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
361 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
362 kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
363 kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
364 kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
365 kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
366 kDmaRequestMux0IEEE1588Timer0 = 54|0x100U, /**< ENET IEEE 1588 timer 0. */
367 kDmaRequestMux0IEEE1588Timer1TPM1Overflow = 55|0x100U, /**< ENET IEEE 1588 timer 1 and TPM1. */
368 kDmaRequestMux0IEEE1588Timer1 = 55|0x100U, /**< ENET IEEE 1588 timer 1 and TPM1. */
369 kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< ENET IEEE 1588 timer 1 and TPM1. */
370 kDmaRequestMux0IEEE1588Timer2TPM2Overflow = 56|0x100U, /**< ENET IEEE 1588 timer 2 and TPM2. */
371 kDmaRequestMux0IEEE1588Timer2 = 56|0x100U, /**< ENET IEEE 1588 timer 2 and TPM2. */
372 kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< ENET IEEE 1588 timer 2 and TPM2. */
373 kDmaRequestMux0IEEE1588Timer3 = 57|0x100U, /**< ENET IEEE 1588 timer 3. */
374 kDmaRequestMux0LPUART0Rx = 58|0x100U, /**< LPUART0 Receive. */
375 kDmaRequestMux0LPUART0Tx = 59|0x100U, /**< LPUART0 Transmit. */
376 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
377 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
378 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
379 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
380} dma_request_source_t;
381
382/* @} */
383
384
385/*!
386 * @}
387 */ /* end of group Mapping_Information */
388
389
390/* ----------------------------------------------------------------------------
391 -- Device Peripheral Access Layer
392 ---------------------------------------------------------------------------- */
393
394/*!
395 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
396 * @{
397 */
398
399
400/*
401** Start of section using anonymous unions
402*/
403
404#if defined(__ARMCC_VERSION)
405 #if (__ARMCC_VERSION >= 6010050)
406 #pragma clang diagnostic push
407 #else
408 #pragma push
409 #pragma anon_unions
410 #endif
411#elif defined(__CWCC__)
412 #pragma push
413 #pragma cpp_extensions on
414#elif defined(__GNUC__)
415 /* anonymous unions are enabled by default */
416#elif defined(__IAR_SYSTEMS_ICC__)
417 #pragma language=extended
418#else
419 #error Not supported compiler type
420#endif
421
422/* ----------------------------------------------------------------------------
423 -- ADC Peripheral Access Layer
424 ---------------------------------------------------------------------------- */
425
426/*!
427 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
428 * @{
429 */
430
431/** ADC - Register Layout Typedef */
432typedef struct {
433 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
434 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
435 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
436 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
437 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
438 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
439 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
440 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
441 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
442 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
443 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
444 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
445 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
446 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
447 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
448 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
449 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
450 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
451 uint8_t RESERVED_0[4];
452 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
453 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
454 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
455 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
456 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
457 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
458 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
459} ADC_Type;
460
461/* ----------------------------------------------------------------------------
462 -- ADC Register Masks
463 ---------------------------------------------------------------------------- */
464
465/*!
466 * @addtogroup ADC_Register_Masks ADC Register Masks
467 * @{
468 */
469
470/*! @name SC1 - ADC Status and Control Registers 1 */
471/*! @{ */
472#define ADC_SC1_ADCH_MASK (0x1FU)
473#define ADC_SC1_ADCH_SHIFT (0U)
474/*! ADCH - Input channel select
475 * 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
476 * 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
477 * 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
478 * 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
479 * 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
480 * 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
481 * 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
482 * 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
483 * 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
484 * 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
485 * 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
486 * 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
487 * 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
488 * 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
489 * 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
490 * 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
491 * 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
492 * 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
493 * 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
494 * 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
495 * 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
496 * 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
497 * 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
498 * 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
499 * 0b11000..Reserved.
500 * 0b11001..Reserved.
501 * 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
502 * 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
503 * 0b11100..Reserved.
504 * 0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
505 * 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
506 * 0b11111..Module is disabled.
507 */
508#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
509#define ADC_SC1_DIFF_MASK (0x20U)
510#define ADC_SC1_DIFF_SHIFT (5U)
511/*! DIFF - Differential Mode Enable
512 * 0b0..Single-ended conversions and input channels are selected.
513 * 0b1..Differential conversions and input channels are selected.
514 */
515#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
516#define ADC_SC1_AIEN_MASK (0x40U)
517#define ADC_SC1_AIEN_SHIFT (6U)
518/*! AIEN - Interrupt Enable
519 * 0b0..Conversion complete interrupt is disabled.
520 * 0b1..Conversion complete interrupt is enabled.
521 */
522#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
523#define ADC_SC1_COCO_MASK (0x80U)
524#define ADC_SC1_COCO_SHIFT (7U)
525/*! COCO - Conversion Complete Flag
526 * 0b0..Conversion is not completed.
527 * 0b1..Conversion is completed.
528 */
529#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
530/*! @} */
531
532/* The count of ADC_SC1 */
533#define ADC_SC1_COUNT (2U)
534
535/*! @name CFG1 - ADC Configuration Register 1 */
536/*! @{ */
537#define ADC_CFG1_ADICLK_MASK (0x3U)
538#define ADC_CFG1_ADICLK_SHIFT (0U)
539/*! ADICLK - Input Clock Select
540 * 0b00..Bus clock
541 * 0b01..Bus clock divided by 2(BUSCLK/2)
542 * 0b10..Alternate clock (ALTCLK)
543 * 0b11..Asynchronous clock (ADACK)
544 */
545#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
546#define ADC_CFG1_MODE_MASK (0xCU)
547#define ADC_CFG1_MODE_SHIFT (2U)
548/*! MODE - Conversion mode selection
549 * 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.
550 * 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output.
551 * 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output
552 * 0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output
553 */
554#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
555#define ADC_CFG1_ADLSMP_MASK (0x10U)
556#define ADC_CFG1_ADLSMP_SHIFT (4U)
557/*! ADLSMP - Sample Time Configuration
558 * 0b0..Short sample time.
559 * 0b1..Long sample time.
560 */
561#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
562#define ADC_CFG1_ADIV_MASK (0x60U)
563#define ADC_CFG1_ADIV_SHIFT (5U)
564/*! ADIV - Clock Divide Select
565 * 0b00..The divide ratio is 1 and the clock rate is input clock.
566 * 0b01..The divide ratio is 2 and the clock rate is (input clock)/2.
567 * 0b10..The divide ratio is 4 and the clock rate is (input clock)/4.
568 * 0b11..The divide ratio is 8 and the clock rate is (input clock)/8.
569 */
570#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
571#define ADC_CFG1_ADLPC_MASK (0x80U)
572#define ADC_CFG1_ADLPC_SHIFT (7U)
573/*! ADLPC - Low-Power Configuration
574 * 0b0..Normal power configuration.
575 * 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed.
576 */
577#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
578/*! @} */
579
580/*! @name CFG2 - ADC Configuration Register 2 */
581/*! @{ */
582#define ADC_CFG2_ADLSTS_MASK (0x3U)
583#define ADC_CFG2_ADLSTS_SHIFT (0U)
584/*! ADLSTS - Long Sample Time Select
585 * 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
586 * 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time.
587 * 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time.
588 * 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.
589 */
590#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
591#define ADC_CFG2_ADHSC_MASK (0x4U)
592#define ADC_CFG2_ADHSC_SHIFT (2U)
593/*! ADHSC - High-Speed Configuration
594 * 0b0..Normal conversion sequence selected.
595 * 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
596 */
597#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
598#define ADC_CFG2_ADACKEN_MASK (0x8U)
599#define ADC_CFG2_ADACKEN_SHIFT (3U)
600/*! ADACKEN - Asynchronous Clock Output Enable
601 * 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
602 * 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC.
603 */
604#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
605#define ADC_CFG2_MUXSEL_MASK (0x10U)
606#define ADC_CFG2_MUXSEL_SHIFT (4U)
607/*! MUXSEL - ADC Mux Select
608 * 0b0..ADxxa channels are selected.
609 * 0b1..ADxxb channels are selected.
610 */
611#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
612/*! @} */
613
614/*! @name R - ADC Data Result Register */
615/*! @{ */
616#define ADC_R_D_MASK (0xFFFFU)
617#define ADC_R_D_SHIFT (0U)
618#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
619/*! @} */
620
621/* The count of ADC_R */
622#define ADC_R_COUNT (2U)
623
624/*! @name CV1 - Compare Value Registers */
625/*! @{ */
626#define ADC_CV1_CV_MASK (0xFFFFU)
627#define ADC_CV1_CV_SHIFT (0U)
628#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
629/*! @} */
630
631/*! @name CV2 - Compare Value Registers */
632/*! @{ */
633#define ADC_CV2_CV_MASK (0xFFFFU)
634#define ADC_CV2_CV_SHIFT (0U)
635#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
636/*! @} */
637
638/*! @name SC2 - Status and Control Register 2 */
639/*! @{ */
640#define ADC_SC2_REFSEL_MASK (0x3U)
641#define ADC_SC2_REFSEL_SHIFT (0U)
642/*! REFSEL - Voltage Reference Selection
643 * 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL
644 * 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
645 * 0b10..Reserved
646 * 0b11..Reserved
647 */
648#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
649#define ADC_SC2_DMAEN_MASK (0x4U)
650#define ADC_SC2_DMAEN_SHIFT (2U)
651/*! DMAEN - DMA Enable
652 * 0b0..DMA is disabled.
653 * 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
654 */
655#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
656#define ADC_SC2_ACREN_MASK (0x8U)
657#define ADC_SC2_ACREN_SHIFT (3U)
658/*! ACREN - Compare Function Range Enable
659 * 0b0..Range function disabled. Only CV1 is compared.
660 * 0b1..Range function enabled. Both CV1 and CV2 are compared.
661 */
662#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
663#define ADC_SC2_ACFGT_MASK (0x10U)
664#define ADC_SC2_ACFGT_SHIFT (4U)
665/*! ACFGT - Compare Function Greater Than Enable
666 * 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
667 * 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
668 */
669#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
670#define ADC_SC2_ACFE_MASK (0x20U)
671#define ADC_SC2_ACFE_SHIFT (5U)
672/*! ACFE - Compare Function Enable
673 * 0b0..Compare function disabled.
674 * 0b1..Compare function enabled.
675 */
676#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
677#define ADC_SC2_ADTRG_MASK (0x40U)
678#define ADC_SC2_ADTRG_SHIFT (6U)
679/*! ADTRG - Conversion Trigger Select
680 * 0b0..Software trigger selected.
681 * 0b1..Hardware trigger selected.
682 */
683#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
684#define ADC_SC2_ADACT_MASK (0x80U)
685#define ADC_SC2_ADACT_SHIFT (7U)
686/*! ADACT - Conversion Active
687 * 0b0..Conversion not in progress.
688 * 0b1..Conversion in progress.
689 */
690#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
691/*! @} */
692
693/*! @name SC3 - Status and Control Register 3 */
694/*! @{ */
695#define ADC_SC3_AVGS_MASK (0x3U)
696#define ADC_SC3_AVGS_SHIFT (0U)
697/*! AVGS - Hardware Average Select
698 * 0b00..4 samples averaged.
699 * 0b01..8 samples averaged.
700 * 0b10..16 samples averaged.
701 * 0b11..32 samples averaged.
702 */
703#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
704#define ADC_SC3_AVGE_MASK (0x4U)
705#define ADC_SC3_AVGE_SHIFT (2U)
706/*! AVGE - Hardware Average Enable
707 * 0b0..Hardware average function disabled.
708 * 0b1..Hardware average function enabled.
709 */
710#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
711#define ADC_SC3_ADCO_MASK (0x8U)
712#define ADC_SC3_ADCO_SHIFT (3U)
713/*! ADCO - Continuous Conversion Enable
714 * 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
715 * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
716 */
717#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
718#define ADC_SC3_CALF_MASK (0x40U)
719#define ADC_SC3_CALF_SHIFT (6U)
720/*! CALF - Calibration Failed Flag
721 * 0b0..Calibration completed normally.
722 * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
723 */
724#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
725#define ADC_SC3_CAL_MASK (0x80U)
726#define ADC_SC3_CAL_SHIFT (7U)
727#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
728/*! @} */
729
730/*! @name OFS - ADC Offset Correction Register */
731/*! @{ */
732#define ADC_OFS_OFS_MASK (0xFFFFU)
733#define ADC_OFS_OFS_SHIFT (0U)
734#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
735/*! @} */
736
737/*! @name PG - ADC Plus-Side Gain Register */
738/*! @{ */
739#define ADC_PG_PG_MASK (0xFFFFU)
740#define ADC_PG_PG_SHIFT (0U)
741#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
742/*! @} */
743
744/*! @name MG - ADC Minus-Side Gain Register */
745/*! @{ */
746#define ADC_MG_MG_MASK (0xFFFFU)
747#define ADC_MG_MG_SHIFT (0U)
748#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
749/*! @} */
750
751/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
752/*! @{ */
753#define ADC_CLPD_CLPD_MASK (0x3FU)
754#define ADC_CLPD_CLPD_SHIFT (0U)
755#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
756/*! @} */
757
758/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
759/*! @{ */
760#define ADC_CLPS_CLPS_MASK (0x3FU)
761#define ADC_CLPS_CLPS_SHIFT (0U)
762#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
763/*! @} */
764
765/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
766/*! @{ */
767#define ADC_CLP4_CLP4_MASK (0x3FFU)
768#define ADC_CLP4_CLP4_SHIFT (0U)
769#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
770/*! @} */
771
772/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
773/*! @{ */
774#define ADC_CLP3_CLP3_MASK (0x1FFU)
775#define ADC_CLP3_CLP3_SHIFT (0U)
776#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
777/*! @} */
778
779/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
780/*! @{ */
781#define ADC_CLP2_CLP2_MASK (0xFFU)
782#define ADC_CLP2_CLP2_SHIFT (0U)
783#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
784/*! @} */
785
786/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
787/*! @{ */
788#define ADC_CLP1_CLP1_MASK (0x7FU)
789#define ADC_CLP1_CLP1_SHIFT (0U)
790#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
791/*! @} */
792
793/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
794/*! @{ */
795#define ADC_CLP0_CLP0_MASK (0x3FU)
796#define ADC_CLP0_CLP0_SHIFT (0U)
797#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
798/*! @} */
799
800/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
801/*! @{ */
802#define ADC_CLMD_CLMD_MASK (0x3FU)
803#define ADC_CLMD_CLMD_SHIFT (0U)
804#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
805/*! @} */
806
807/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
808/*! @{ */
809#define ADC_CLMS_CLMS_MASK (0x3FU)
810#define ADC_CLMS_CLMS_SHIFT (0U)
811#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
812/*! @} */
813
814/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
815/*! @{ */
816#define ADC_CLM4_CLM4_MASK (0x3FFU)
817#define ADC_CLM4_CLM4_SHIFT (0U)
818#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
819/*! @} */
820
821/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
822/*! @{ */
823#define ADC_CLM3_CLM3_MASK (0x1FFU)
824#define ADC_CLM3_CLM3_SHIFT (0U)
825#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
826/*! @} */
827
828/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
829/*! @{ */
830#define ADC_CLM2_CLM2_MASK (0xFFU)
831#define ADC_CLM2_CLM2_SHIFT (0U)
832#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
833/*! @} */
834
835/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
836/*! @{ */
837#define ADC_CLM1_CLM1_MASK (0x7FU)
838#define ADC_CLM1_CLM1_SHIFT (0U)
839#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
840/*! @} */
841
842/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
843/*! @{ */
844#define ADC_CLM0_CLM0_MASK (0x3FU)
845#define ADC_CLM0_CLM0_SHIFT (0U)
846#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
847/*! @} */
848
849
850/*!
851 * @}
852 */ /* end of group ADC_Register_Masks */
853
854
855/* ADC - Peripheral instance base addresses */
856/** Peripheral ADC0 base address */
857#define ADC0_BASE (0x4003B000u)
858/** Peripheral ADC0 base pointer */
859#define ADC0 ((ADC_Type *)ADC0_BASE)
860/** Peripheral ADC1 base address */
861#define ADC1_BASE (0x400BB000u)
862/** Peripheral ADC1 base pointer */
863#define ADC1 ((ADC_Type *)ADC1_BASE)
864/** Array initializer of ADC peripheral base addresses */
865#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
866/** Array initializer of ADC peripheral base pointers */
867#define ADC_BASE_PTRS { ADC0, ADC1 }
868/** Interrupt vectors for the ADC peripheral type */
869#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
870
871/*!
872 * @}
873 */ /* end of group ADC_Peripheral_Access_Layer */
874
875
876/* ----------------------------------------------------------------------------
877 -- AIPS Peripheral Access Layer
878 ---------------------------------------------------------------------------- */
879
880/*!
881 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
882 * @{
883 */
884
885/** AIPS - Register Layout Typedef */
886typedef struct {
887 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
888 uint8_t RESERVED_0[28];
889 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
890 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
891 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
892 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
893 uint8_t RESERVED_1[16];
894 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
895 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
896 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
897 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
898 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
899 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
900 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
901 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
902 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
903 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
904 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
905 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
906} AIPS_Type;
907
908/* ----------------------------------------------------------------------------
909 -- AIPS Register Masks
910 ---------------------------------------------------------------------------- */
911
912/*!
913 * @addtogroup AIPS_Register_Masks AIPS Register Masks
914 * @{
915 */
916
917/*! @name MPRA - Master Privilege Register A */
918/*! @{ */
919#define AIPS_MPRA_MPL6_MASK (0x10U)
920#define AIPS_MPRA_MPL6_SHIFT (4U)
921/*! MPL6 - Master 6 Privilege Level
922 * 0b0..Accesses from this master are forced to user-mode.
923 * 0b1..Accesses from this master are not forced to user-mode.
924 */
925#define AIPS_MPRA_MPL6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL6_SHIFT)) & AIPS_MPRA_MPL6_MASK)
926#define AIPS_MPRA_MTW6_MASK (0x20U)
927#define AIPS_MPRA_MTW6_SHIFT (5U)
928/*! MTW6 - Master 6 Trusted for Writes
929 * 0b0..This master is not trusted for write accesses.
930 * 0b1..This master is trusted for write accesses.
931 */
932#define AIPS_MPRA_MTW6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW6_SHIFT)) & AIPS_MPRA_MTW6_MASK)
933#define AIPS_MPRA_MTR6_MASK (0x40U)
934#define AIPS_MPRA_MTR6_SHIFT (6U)
935/*! MTR6 - Master 6 Trusted for Read
936 * 0b0..This master is not trusted for read accesses.
937 * 0b1..This master is trusted for read accesses.
938 */
939#define AIPS_MPRA_MTR6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR6_SHIFT)) & AIPS_MPRA_MTR6_MASK)
940#define AIPS_MPRA_MPL5_MASK (0x100U)
941#define AIPS_MPRA_MPL5_SHIFT (8U)
942/*! MPL5 - Master 5 Privilege Level
943 * 0b0..Accesses from this master are forced to user-mode.
944 * 0b1..Accesses from this master are not forced to user-mode.
945 */
946#define AIPS_MPRA_MPL5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
947#define AIPS_MPRA_MTW5_MASK (0x200U)
948#define AIPS_MPRA_MTW5_SHIFT (9U)
949/*! MTW5 - Master 5 Trusted For Writes
950 * 0b0..This master is not trusted for write accesses.
951 * 0b1..This master is trusted for write accesses.
952 */
953#define AIPS_MPRA_MTW5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
954#define AIPS_MPRA_MTR5_MASK (0x400U)
955#define AIPS_MPRA_MTR5_SHIFT (10U)
956/*! MTR5 - Master 5 Trusted For Read
957 * 0b0..This master is not trusted for read accesses.
958 * 0b1..This master is trusted for read accesses.
959 */
960#define AIPS_MPRA_MTR5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
961#define AIPS_MPRA_MPL4_MASK (0x1000U)
962#define AIPS_MPRA_MPL4_SHIFT (12U)
963/*! MPL4 - Master 4 Privilege Level
964 * 0b0..Accesses from this master are forced to user-mode.
965 * 0b1..Accesses from this master are not forced to user-mode.
966 */
967#define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
968#define AIPS_MPRA_MTW4_MASK (0x2000U)
969#define AIPS_MPRA_MTW4_SHIFT (13U)
970/*! MTW4 - Master 4 Trusted For Writes
971 * 0b0..This master is not trusted for write accesses.
972 * 0b1..This master is trusted for write accesses.
973 */
974#define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
975#define AIPS_MPRA_MTR4_MASK (0x4000U)
976#define AIPS_MPRA_MTR4_SHIFT (14U)
977/*! MTR4 - Master 4 Trusted For Read
978 * 0b0..This master is not trusted for read accesses.
979 * 0b1..This master is trusted for read accesses.
980 */
981#define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
982#define AIPS_MPRA_MPL3_MASK (0x10000U)
983#define AIPS_MPRA_MPL3_SHIFT (16U)
984/*! MPL3 - Master 3 Privilege Level
985 * 0b0..Accesses from this master are forced to user-mode.
986 * 0b1..Accesses from this master are not forced to user-mode.
987 */
988#define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
989#define AIPS_MPRA_MTW3_MASK (0x20000U)
990#define AIPS_MPRA_MTW3_SHIFT (17U)
991/*! MTW3 - Master 3 Trusted For Writes
992 * 0b0..This master is not trusted for write accesses.
993 * 0b1..This master is trusted for write accesses.
994 */
995#define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
996#define AIPS_MPRA_MTR3_MASK (0x40000U)
997#define AIPS_MPRA_MTR3_SHIFT (18U)
998/*! MTR3 - Master 3 Trusted For Read
999 * 0b0..This master is not trusted for read accesses.
1000 * 0b1..This master is trusted for read accesses.
1001 */
1002#define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
1003#define AIPS_MPRA_MPL2_MASK (0x100000U)
1004#define AIPS_MPRA_MPL2_SHIFT (20U)
1005/*! MPL2 - Master 2 Privilege Level
1006 * 0b0..Accesses from this master are forced to user-mode.
1007 * 0b1..Accesses from this master are not forced to user-mode.
1008 */
1009#define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
1010#define AIPS_MPRA_MTW2_MASK (0x200000U)
1011#define AIPS_MPRA_MTW2_SHIFT (21U)
1012/*! MTW2 - Master 2 Trusted For Writes
1013 * 0b0..This master is not trusted for write accesses.
1014 * 0b1..This master is trusted for write accesses.
1015 */
1016#define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
1017#define AIPS_MPRA_MTR2_MASK (0x400000U)
1018#define AIPS_MPRA_MTR2_SHIFT (22U)
1019/*! MTR2 - Master 2 Trusted For Read
1020 * 0b0..This master is not trusted for read accesses.
1021 * 0b1..This master is trusted for read accesses.
1022 */
1023#define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
1024#define AIPS_MPRA_MPL1_MASK (0x1000000U)
1025#define AIPS_MPRA_MPL1_SHIFT (24U)
1026/*! MPL1 - Master 1 Privilege Level
1027 * 0b0..Accesses from this master are forced to user-mode.
1028 * 0b1..Accesses from this master are not forced to user-mode.
1029 */
1030#define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
1031#define AIPS_MPRA_MTW1_MASK (0x2000000U)
1032#define AIPS_MPRA_MTW1_SHIFT (25U)
1033/*! MTW1 - Master 1 Trusted for Writes
1034 * 0b0..This master is not trusted for write accesses.
1035 * 0b1..This master is trusted for write accesses.
1036 */
1037#define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
1038#define AIPS_MPRA_MTR1_MASK (0x4000000U)
1039#define AIPS_MPRA_MTR1_SHIFT (26U)
1040/*! MTR1 - Master 1 Trusted for Read
1041 * 0b0..This master is not trusted for read accesses.
1042 * 0b1..This master is trusted for read accesses.
1043 */
1044#define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
1045#define AIPS_MPRA_MPL0_MASK (0x10000000U)
1046#define AIPS_MPRA_MPL0_SHIFT (28U)
1047/*! MPL0 - Master 0 Privilege Level
1048 * 0b0..Accesses from this master are forced to user-mode.
1049 * 0b1..Accesses from this master are not forced to user-mode.
1050 */
1051#define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
1052#define AIPS_MPRA_MTW0_MASK (0x20000000U)
1053#define AIPS_MPRA_MTW0_SHIFT (29U)
1054/*! MTW0 - Master 0 Trusted For Writes
1055 * 0b0..This master is not trusted for write accesses.
1056 * 0b1..This master is trusted for write accesses.
1057 */
1058#define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
1059#define AIPS_MPRA_MTR0_MASK (0x40000000U)
1060#define AIPS_MPRA_MTR0_SHIFT (30U)
1061/*! MTR0 - Master 0 Trusted For Read
1062 * 0b0..This master is not trusted for read accesses.
1063 * 0b1..This master is trusted for read accesses.
1064 */
1065#define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
1066/*! @} */
1067
1068/*! @name PACRA - Peripheral Access Control Register */
1069/*! @{ */
1070#define AIPS_PACRA_TP7_MASK (0x1U)
1071#define AIPS_PACRA_TP7_SHIFT (0U)
1072/*! TP7 - Trusted Protect
1073 * 0b0..Accesses from an untrusted master are allowed.
1074 * 0b1..Accesses from an untrusted master are not allowed.
1075 */
1076#define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
1077#define AIPS_PACRA_WP7_MASK (0x2U)
1078#define AIPS_PACRA_WP7_SHIFT (1U)
1079/*! WP7 - Write Protect
1080 * 0b0..This peripheral allows write accesses.
1081 * 0b1..This peripheral is write protected.
1082 */
1083#define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
1084#define AIPS_PACRA_SP7_MASK (0x4U)
1085#define AIPS_PACRA_SP7_SHIFT (2U)
1086/*! SP7 - Supervisor Protect
1087 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1088 * 0b1..This peripheral requires supervisor privilege level for accesses.
1089 */
1090#define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
1091#define AIPS_PACRA_TP6_MASK (0x10U)
1092#define AIPS_PACRA_TP6_SHIFT (4U)
1093/*! TP6 - Trusted Protect
1094 * 0b0..Accesses from an untrusted master are allowed.
1095 * 0b1..Accesses from an untrusted master are not allowed.
1096 */
1097#define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
1098#define AIPS_PACRA_WP6_MASK (0x20U)
1099#define AIPS_PACRA_WP6_SHIFT (5U)
1100/*! WP6 - Write Protect
1101 * 0b0..This peripheral allows write accesses.
1102 * 0b1..This peripheral is write protected.
1103 */
1104#define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
1105#define AIPS_PACRA_SP6_MASK (0x40U)
1106#define AIPS_PACRA_SP6_SHIFT (6U)
1107/*! SP6 - Supervisor Protect
1108 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1109 * 0b1..This peripheral requires supervisor privilege level for accesses.
1110 */
1111#define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
1112#define AIPS_PACRA_TP5_MASK (0x100U)
1113#define AIPS_PACRA_TP5_SHIFT (8U)
1114/*! TP5 - Trusted Protect
1115 * 0b0..Accesses from an untrusted master are allowed.
1116 * 0b1..Accesses from an untrusted master are not allowed.
1117 */
1118#define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
1119#define AIPS_PACRA_WP5_MASK (0x200U)
1120#define AIPS_PACRA_WP5_SHIFT (9U)
1121/*! WP5 - Write Protect
1122 * 0b0..This peripheral allows write accesses.
1123 * 0b1..This peripheral is write protected.
1124 */
1125#define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
1126#define AIPS_PACRA_SP5_MASK (0x400U)
1127#define AIPS_PACRA_SP5_SHIFT (10U)
1128/*! SP5 - Supervisor Protect
1129 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1130 * 0b1..This peripheral requires supervisor privilege level for accesses.
1131 */
1132#define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
1133#define AIPS_PACRA_TP4_MASK (0x1000U)
1134#define AIPS_PACRA_TP4_SHIFT (12U)
1135/*! TP4 - Trusted Protect
1136 * 0b0..Accesses from an untrusted master are allowed.
1137 * 0b1..Accesses from an untrusted master are not allowed.
1138 */
1139#define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
1140#define AIPS_PACRA_WP4_MASK (0x2000U)
1141#define AIPS_PACRA_WP4_SHIFT (13U)
1142/*! WP4 - Write Protect
1143 * 0b0..This peripheral allows write accesses.
1144 * 0b1..This peripheral is write protected.
1145 */
1146#define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
1147#define AIPS_PACRA_SP4_MASK (0x4000U)
1148#define AIPS_PACRA_SP4_SHIFT (14U)
1149/*! SP4 - Supervisor Protect
1150 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1151 * 0b1..This peripheral requires supervisor privilege level for accesses.
1152 */
1153#define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
1154#define AIPS_PACRA_TP3_MASK (0x10000U)
1155#define AIPS_PACRA_TP3_SHIFT (16U)
1156/*! TP3 - Trusted Protect
1157 * 0b0..Accesses from an untrusted master are allowed.
1158 * 0b1..Accesses from an untrusted master are not allowed.
1159 */
1160#define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
1161#define AIPS_PACRA_WP3_MASK (0x20000U)
1162#define AIPS_PACRA_WP3_SHIFT (17U)
1163/*! WP3 - Write Protect
1164 * 0b0..This peripheral allows write accesses.
1165 * 0b1..This peripheral is write protected.
1166 */
1167#define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
1168#define AIPS_PACRA_SP3_MASK (0x40000U)
1169#define AIPS_PACRA_SP3_SHIFT (18U)
1170/*! SP3 - Supervisor Protect
1171 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1172 * 0b1..This peripheral requires supervisor privilege level for accesses.
1173 */
1174#define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
1175#define AIPS_PACRA_TP2_MASK (0x100000U)
1176#define AIPS_PACRA_TP2_SHIFT (20U)
1177/*! TP2 - Trusted Protect
1178 * 0b0..Accesses from an untrusted master are allowed.
1179 * 0b1..Accesses from an untrusted master are not allowed.
1180 */
1181#define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
1182#define AIPS_PACRA_WP2_MASK (0x200000U)
1183#define AIPS_PACRA_WP2_SHIFT (21U)
1184/*! WP2 - Write Protect
1185 * 0b0..This peripheral allows write accesses.
1186 * 0b1..This peripheral is write protected.
1187 */
1188#define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
1189#define AIPS_PACRA_SP2_MASK (0x400000U)
1190#define AIPS_PACRA_SP2_SHIFT (22U)
1191/*! SP2 - Supervisor Protect
1192 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1193 * 0b1..This peripheral requires supervisor privilege level for accesses.
1194 */
1195#define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
1196#define AIPS_PACRA_TP1_MASK (0x1000000U)
1197#define AIPS_PACRA_TP1_SHIFT (24U)
1198/*! TP1 - Trusted Protect
1199 * 0b0..Accesses from an untrusted master are allowed.
1200 * 0b1..Accesses from an untrusted master are not allowed.
1201 */
1202#define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
1203#define AIPS_PACRA_WP1_MASK (0x2000000U)
1204#define AIPS_PACRA_WP1_SHIFT (25U)
1205/*! WP1 - Write Protect
1206 * 0b0..This peripheral allows write accesses.
1207 * 0b1..This peripheral is write protected.
1208 */
1209#define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
1210#define AIPS_PACRA_SP1_MASK (0x4000000U)
1211#define AIPS_PACRA_SP1_SHIFT (26U)
1212/*! SP1 - Supervisor Protect
1213 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1214 * 0b1..This peripheral requires supervisor privilege level for accesses.
1215 */
1216#define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
1217#define AIPS_PACRA_TP0_MASK (0x10000000U)
1218#define AIPS_PACRA_TP0_SHIFT (28U)
1219/*! TP0 - Trusted Protect
1220 * 0b0..Accesses from an untrusted master are allowed.
1221 * 0b1..Accesses from an untrusted master are not allowed.
1222 */
1223#define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
1224#define AIPS_PACRA_WP0_MASK (0x20000000U)
1225#define AIPS_PACRA_WP0_SHIFT (29U)
1226/*! WP0 - Write Protect
1227 * 0b0..This peripheral allows write accesses.
1228 * 0b1..This peripheral is write protected.
1229 */
1230#define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
1231#define AIPS_PACRA_SP0_MASK (0x40000000U)
1232#define AIPS_PACRA_SP0_SHIFT (30U)
1233/*! SP0 - Supervisor Protect
1234 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1235 * 0b1..This peripheral requires supervisor privilege level for accesses.
1236 */
1237#define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
1238/*! @} */
1239
1240/*! @name PACRB - Peripheral Access Control Register */
1241/*! @{ */
1242#define AIPS_PACRB_TP7_MASK (0x1U)
1243#define AIPS_PACRB_TP7_SHIFT (0U)
1244/*! TP7 - Trusted Protect
1245 * 0b0..Accesses from an untrusted master are allowed.
1246 * 0b1..Accesses from an untrusted master are not allowed.
1247 */
1248#define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
1249#define AIPS_PACRB_WP7_MASK (0x2U)
1250#define AIPS_PACRB_WP7_SHIFT (1U)
1251/*! WP7 - Write Protect
1252 * 0b0..This peripheral allows write accesses.
1253 * 0b1..This peripheral is write protected.
1254 */
1255#define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
1256#define AIPS_PACRB_SP7_MASK (0x4U)
1257#define AIPS_PACRB_SP7_SHIFT (2U)
1258/*! SP7 - Supervisor Protect
1259 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1260 * 0b1..This peripheral requires supervisor privilege level for accesses.
1261 */
1262#define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
1263#define AIPS_PACRB_TP6_MASK (0x10U)
1264#define AIPS_PACRB_TP6_SHIFT (4U)
1265/*! TP6 - Trusted Protect
1266 * 0b0..Accesses from an untrusted master are allowed.
1267 * 0b1..Accesses from an untrusted master are not allowed.
1268 */
1269#define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
1270#define AIPS_PACRB_WP6_MASK (0x20U)
1271#define AIPS_PACRB_WP6_SHIFT (5U)
1272/*! WP6 - Write Protect
1273 * 0b0..This peripheral allows write accesses.
1274 * 0b1..This peripheral is write protected.
1275 */
1276#define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
1277#define AIPS_PACRB_SP6_MASK (0x40U)
1278#define AIPS_PACRB_SP6_SHIFT (6U)
1279/*! SP6 - Supervisor Protect
1280 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1281 * 0b1..This peripheral requires supervisor privilege level for accesses.
1282 */
1283#define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
1284#define AIPS_PACRB_TP5_MASK (0x100U)
1285#define AIPS_PACRB_TP5_SHIFT (8U)
1286/*! TP5 - Trusted Protect
1287 * 0b0..Accesses from an untrusted master are allowed.
1288 * 0b1..Accesses from an untrusted master are not allowed.
1289 */
1290#define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
1291#define AIPS_PACRB_WP5_MASK (0x200U)
1292#define AIPS_PACRB_WP5_SHIFT (9U)
1293/*! WP5 - Write Protect
1294 * 0b0..This peripheral allows write accesses.
1295 * 0b1..This peripheral is write protected.
1296 */
1297#define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
1298#define AIPS_PACRB_SP5_MASK (0x400U)
1299#define AIPS_PACRB_SP5_SHIFT (10U)
1300/*! SP5 - Supervisor Protect
1301 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1302 * 0b1..This peripheral requires supervisor privilege level for accesses.
1303 */
1304#define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
1305#define AIPS_PACRB_TP4_MASK (0x1000U)
1306#define AIPS_PACRB_TP4_SHIFT (12U)
1307/*! TP4 - Trusted Protect
1308 * 0b0..Accesses from an untrusted master are allowed.
1309 * 0b1..Accesses from an untrusted master are not allowed.
1310 */
1311#define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
1312#define AIPS_PACRB_WP4_MASK (0x2000U)
1313#define AIPS_PACRB_WP4_SHIFT (13U)
1314/*! WP4 - Write Protect
1315 * 0b0..This peripheral allows write accesses.
1316 * 0b1..This peripheral is write protected.
1317 */
1318#define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
1319#define AIPS_PACRB_SP4_MASK (0x4000U)
1320#define AIPS_PACRB_SP4_SHIFT (14U)
1321/*! SP4 - Supervisor Protect
1322 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1323 * 0b1..This peripheral requires supervisor privilege level for accesses.
1324 */
1325#define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
1326#define AIPS_PACRB_TP3_MASK (0x10000U)
1327#define AIPS_PACRB_TP3_SHIFT (16U)
1328/*! TP3 - Trusted Protect
1329 * 0b0..Accesses from an untrusted master are allowed.
1330 * 0b1..Accesses from an untrusted master are not allowed.
1331 */
1332#define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
1333#define AIPS_PACRB_WP3_MASK (0x20000U)
1334#define AIPS_PACRB_WP3_SHIFT (17U)
1335/*! WP3 - Write Protect
1336 * 0b0..This peripheral allows write accesses.
1337 * 0b1..This peripheral is write protected.
1338 */
1339#define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
1340#define AIPS_PACRB_SP3_MASK (0x40000U)
1341#define AIPS_PACRB_SP3_SHIFT (18U)
1342/*! SP3 - Supervisor Protect
1343 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1344 * 0b1..This peripheral requires supervisor privilege level for accesses.
1345 */
1346#define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
1347#define AIPS_PACRB_TP2_MASK (0x100000U)
1348#define AIPS_PACRB_TP2_SHIFT (20U)
1349/*! TP2 - Trusted Protect
1350 * 0b0..Accesses from an untrusted master are allowed.
1351 * 0b1..Accesses from an untrusted master are not allowed.
1352 */
1353#define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
1354#define AIPS_PACRB_WP2_MASK (0x200000U)
1355#define AIPS_PACRB_WP2_SHIFT (21U)
1356/*! WP2 - Write Protect
1357 * 0b0..This peripheral allows write accesses.
1358 * 0b1..This peripheral is write protected.
1359 */
1360#define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
1361#define AIPS_PACRB_SP2_MASK (0x400000U)
1362#define AIPS_PACRB_SP2_SHIFT (22U)
1363/*! SP2 - Supervisor Protect
1364 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1365 * 0b1..This peripheral requires supervisor privilege level for accesses.
1366 */
1367#define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
1368#define AIPS_PACRB_TP1_MASK (0x1000000U)
1369#define AIPS_PACRB_TP1_SHIFT (24U)
1370/*! TP1 - Trusted Protect
1371 * 0b0..Accesses from an untrusted master are allowed.
1372 * 0b1..Accesses from an untrusted master are not allowed.
1373 */
1374#define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
1375#define AIPS_PACRB_WP1_MASK (0x2000000U)
1376#define AIPS_PACRB_WP1_SHIFT (25U)
1377/*! WP1 - Write Protect
1378 * 0b0..This peripheral allows write accesses.
1379 * 0b1..This peripheral is write protected.
1380 */
1381#define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
1382#define AIPS_PACRB_SP1_MASK (0x4000000U)
1383#define AIPS_PACRB_SP1_SHIFT (26U)
1384/*! SP1 - Supervisor Protect
1385 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1386 * 0b1..This peripheral requires supervisor privilege level for accesses.
1387 */
1388#define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
1389#define AIPS_PACRB_TP0_MASK (0x10000000U)
1390#define AIPS_PACRB_TP0_SHIFT (28U)
1391/*! TP0 - Trusted Protect
1392 * 0b0..Accesses from an untrusted master are allowed.
1393 * 0b1..Accesses from an untrusted master are not allowed.
1394 */
1395#define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
1396#define AIPS_PACRB_WP0_MASK (0x20000000U)
1397#define AIPS_PACRB_WP0_SHIFT (29U)
1398/*! WP0 - Write Protect
1399 * 0b0..This peripheral allows write accesses.
1400 * 0b1..This peripheral is write protected.
1401 */
1402#define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
1403#define AIPS_PACRB_SP0_MASK (0x40000000U)
1404#define AIPS_PACRB_SP0_SHIFT (30U)
1405/*! SP0 - Supervisor Protect
1406 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1407 * 0b1..This peripheral requires supervisor privilege level for accesses.
1408 */
1409#define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
1410/*! @} */
1411
1412/*! @name PACRC - Peripheral Access Control Register */
1413/*! @{ */
1414#define AIPS_PACRC_TP7_MASK (0x1U)
1415#define AIPS_PACRC_TP7_SHIFT (0U)
1416/*! TP7 - Trusted Protect
1417 * 0b0..Accesses from an untrusted master are allowed.
1418 * 0b1..Accesses from an untrusted master are not allowed.
1419 */
1420#define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
1421#define AIPS_PACRC_WP7_MASK (0x2U)
1422#define AIPS_PACRC_WP7_SHIFT (1U)
1423/*! WP7 - Write Protect
1424 * 0b0..This peripheral allows write accesses.
1425 * 0b1..This peripheral is write protected.
1426 */
1427#define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
1428#define AIPS_PACRC_SP7_MASK (0x4U)
1429#define AIPS_PACRC_SP7_SHIFT (2U)
1430/*! SP7 - Supervisor Protect
1431 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1432 * 0b1..This peripheral requires supervisor privilege level for accesses.
1433 */
1434#define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
1435#define AIPS_PACRC_TP6_MASK (0x10U)
1436#define AIPS_PACRC_TP6_SHIFT (4U)
1437/*! TP6 - Trusted Protect
1438 * 0b0..Accesses from an untrusted master are allowed.
1439 * 0b1..Accesses from an untrusted master are not allowed.
1440 */
1441#define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
1442#define AIPS_PACRC_WP6_MASK (0x20U)
1443#define AIPS_PACRC_WP6_SHIFT (5U)
1444/*! WP6 - Write Protect
1445 * 0b0..This peripheral allows write accesses.
1446 * 0b1..This peripheral is write protected.
1447 */
1448#define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
1449#define AIPS_PACRC_SP6_MASK (0x40U)
1450#define AIPS_PACRC_SP6_SHIFT (6U)
1451/*! SP6 - Supervisor Protect
1452 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1453 * 0b1..This peripheral requires supervisor privilege level for accesses.
1454 */
1455#define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
1456#define AIPS_PACRC_TP5_MASK (0x100U)
1457#define AIPS_PACRC_TP5_SHIFT (8U)
1458/*! TP5 - Trusted Protect
1459 * 0b0..Accesses from an untrusted master are allowed.
1460 * 0b1..Accesses from an untrusted master are not allowed.
1461 */
1462#define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
1463#define AIPS_PACRC_WP5_MASK (0x200U)
1464#define AIPS_PACRC_WP5_SHIFT (9U)
1465/*! WP5 - Write Protect
1466 * 0b0..This peripheral allows write accesses.
1467 * 0b1..This peripheral is write protected.
1468 */
1469#define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
1470#define AIPS_PACRC_SP5_MASK (0x400U)
1471#define AIPS_PACRC_SP5_SHIFT (10U)
1472/*! SP5 - Supervisor Protect
1473 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1474 * 0b1..This peripheral requires supervisor privilege level for accesses.
1475 */
1476#define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
1477#define AIPS_PACRC_TP4_MASK (0x1000U)
1478#define AIPS_PACRC_TP4_SHIFT (12U)
1479/*! TP4 - Trusted Protect
1480 * 0b0..Accesses from an untrusted master are allowed.
1481 * 0b1..Accesses from an untrusted master are not allowed.
1482 */
1483#define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
1484#define AIPS_PACRC_WP4_MASK (0x2000U)
1485#define AIPS_PACRC_WP4_SHIFT (13U)
1486/*! WP4 - Write Protect
1487 * 0b0..This peripheral allows write accesses.
1488 * 0b1..This peripheral is write protected.
1489 */
1490#define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
1491#define AIPS_PACRC_SP4_MASK (0x4000U)
1492#define AIPS_PACRC_SP4_SHIFT (14U)
1493/*! SP4 - Supervisor Protect
1494 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1495 * 0b1..This peripheral requires supervisor privilege level for accesses.
1496 */
1497#define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
1498#define AIPS_PACRC_TP3_MASK (0x10000U)
1499#define AIPS_PACRC_TP3_SHIFT (16U)
1500/*! TP3 - Trusted Protect
1501 * 0b0..Accesses from an untrusted master are allowed.
1502 * 0b1..Accesses from an untrusted master are not allowed.
1503 */
1504#define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
1505#define AIPS_PACRC_WP3_MASK (0x20000U)
1506#define AIPS_PACRC_WP3_SHIFT (17U)
1507/*! WP3 - Write Protect
1508 * 0b0..This peripheral allows write accesses.
1509 * 0b1..This peripheral is write protected.
1510 */
1511#define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
1512#define AIPS_PACRC_SP3_MASK (0x40000U)
1513#define AIPS_PACRC_SP3_SHIFT (18U)
1514/*! SP3 - Supervisor Protect
1515 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1516 * 0b1..This peripheral requires supervisor privilege level for accesses.
1517 */
1518#define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
1519#define AIPS_PACRC_TP2_MASK (0x100000U)
1520#define AIPS_PACRC_TP2_SHIFT (20U)
1521/*! TP2 - Trusted Protect
1522 * 0b0..Accesses from an untrusted master are allowed.
1523 * 0b1..Accesses from an untrusted master are not allowed.
1524 */
1525#define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
1526#define AIPS_PACRC_WP2_MASK (0x200000U)
1527#define AIPS_PACRC_WP2_SHIFT (21U)
1528/*! WP2 - Write Protect
1529 * 0b0..This peripheral allows write accesses.
1530 * 0b1..This peripheral is write protected.
1531 */
1532#define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
1533#define AIPS_PACRC_SP2_MASK (0x400000U)
1534#define AIPS_PACRC_SP2_SHIFT (22U)
1535/*! SP2 - Supervisor Protect
1536 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1537 * 0b1..This peripheral requires supervisor privilege level for accesses.
1538 */
1539#define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
1540#define AIPS_PACRC_TP1_MASK (0x1000000U)
1541#define AIPS_PACRC_TP1_SHIFT (24U)
1542/*! TP1 - Trusted Protect
1543 * 0b0..Accesses from an untrusted master are allowed.
1544 * 0b1..Accesses from an untrusted master are not allowed.
1545 */
1546#define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
1547#define AIPS_PACRC_WP1_MASK (0x2000000U)
1548#define AIPS_PACRC_WP1_SHIFT (25U)
1549/*! WP1 - Write Protect
1550 * 0b0..This peripheral allows write accesses.
1551 * 0b1..This peripheral is write protected.
1552 */
1553#define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
1554#define AIPS_PACRC_SP1_MASK (0x4000000U)
1555#define AIPS_PACRC_SP1_SHIFT (26U)
1556/*! SP1 - Supervisor Protect
1557 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1558 * 0b1..This peripheral requires supervisor privilege level for accesses.
1559 */
1560#define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
1561#define AIPS_PACRC_TP0_MASK (0x10000000U)
1562#define AIPS_PACRC_TP0_SHIFT (28U)
1563/*! TP0 - Trusted Protect
1564 * 0b0..Accesses from an untrusted master are allowed.
1565 * 0b1..Accesses from an untrusted master are not allowed.
1566 */
1567#define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
1568#define AIPS_PACRC_WP0_MASK (0x20000000U)
1569#define AIPS_PACRC_WP0_SHIFT (29U)
1570/*! WP0 - Write Protect
1571 * 0b0..This peripheral allows write accesses.
1572 * 0b1..This peripheral is write protected.
1573 */
1574#define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
1575#define AIPS_PACRC_SP0_MASK (0x40000000U)
1576#define AIPS_PACRC_SP0_SHIFT (30U)
1577/*! SP0 - Supervisor Protect
1578 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1579 * 0b1..This peripheral requires supervisor privilege level for accesses.
1580 */
1581#define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
1582/*! @} */
1583
1584/*! @name PACRD - Peripheral Access Control Register */
1585/*! @{ */
1586#define AIPS_PACRD_TP7_MASK (0x1U)
1587#define AIPS_PACRD_TP7_SHIFT (0U)
1588/*! TP7 - Trusted Protect
1589 * 0b0..Accesses from an untrusted master are allowed.
1590 * 0b1..Accesses from an untrusted master are not allowed.
1591 */
1592#define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
1593#define AIPS_PACRD_WP7_MASK (0x2U)
1594#define AIPS_PACRD_WP7_SHIFT (1U)
1595/*! WP7 - Write Protect
1596 * 0b0..This peripheral allows write accesses.
1597 * 0b1..This peripheral is write protected.
1598 */
1599#define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
1600#define AIPS_PACRD_SP7_MASK (0x4U)
1601#define AIPS_PACRD_SP7_SHIFT (2U)
1602/*! SP7 - Supervisor Protect
1603 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1604 * 0b1..This peripheral requires supervisor privilege level for accesses.
1605 */
1606#define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
1607#define AIPS_PACRD_TP6_MASK (0x10U)
1608#define AIPS_PACRD_TP6_SHIFT (4U)
1609/*! TP6 - Trusted Protect
1610 * 0b0..Accesses from an untrusted master are allowed.
1611 * 0b1..Accesses from an untrusted master are not allowed.
1612 */
1613#define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
1614#define AIPS_PACRD_WP6_MASK (0x20U)
1615#define AIPS_PACRD_WP6_SHIFT (5U)
1616/*! WP6 - Write Protect
1617 * 0b0..This peripheral allows write accesses.
1618 * 0b1..This peripheral is write protected.
1619 */
1620#define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
1621#define AIPS_PACRD_SP6_MASK (0x40U)
1622#define AIPS_PACRD_SP6_SHIFT (6U)
1623/*! SP6 - Supervisor Protect
1624 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1625 * 0b1..This peripheral requires supervisor privilege level for accesses.
1626 */
1627#define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
1628#define AIPS_PACRD_TP5_MASK (0x100U)
1629#define AIPS_PACRD_TP5_SHIFT (8U)
1630/*! TP5 - Trusted Protect
1631 * 0b0..Accesses from an untrusted master are allowed.
1632 * 0b1..Accesses from an untrusted master are not allowed.
1633 */
1634#define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
1635#define AIPS_PACRD_WP5_MASK (0x200U)
1636#define AIPS_PACRD_WP5_SHIFT (9U)
1637/*! WP5 - Write Protect
1638 * 0b0..This peripheral allows write accesses.
1639 * 0b1..This peripheral is write protected.
1640 */
1641#define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
1642#define AIPS_PACRD_SP5_MASK (0x400U)
1643#define AIPS_PACRD_SP5_SHIFT (10U)
1644/*! SP5 - Supervisor Protect
1645 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1646 * 0b1..This peripheral requires supervisor privilege level for accesses.
1647 */
1648#define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
1649#define AIPS_PACRD_TP4_MASK (0x1000U)
1650#define AIPS_PACRD_TP4_SHIFT (12U)
1651/*! TP4 - Trusted Protect
1652 * 0b0..Accesses from an untrusted master are allowed.
1653 * 0b1..Accesses from an untrusted master are not allowed.
1654 */
1655#define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
1656#define AIPS_PACRD_WP4_MASK (0x2000U)
1657#define AIPS_PACRD_WP4_SHIFT (13U)
1658/*! WP4 - Write Protect
1659 * 0b0..This peripheral allows write accesses.
1660 * 0b1..This peripheral is write protected.
1661 */
1662#define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
1663#define AIPS_PACRD_SP4_MASK (0x4000U)
1664#define AIPS_PACRD_SP4_SHIFT (14U)
1665/*! SP4 - Supervisor Protect
1666 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1667 * 0b1..This peripheral requires supervisor privilege level for accesses.
1668 */
1669#define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
1670#define AIPS_PACRD_TP3_MASK (0x10000U)
1671#define AIPS_PACRD_TP3_SHIFT (16U)
1672/*! TP3 - Trusted Protect
1673 * 0b0..Accesses from an untrusted master are allowed.
1674 * 0b1..Accesses from an untrusted master are not allowed.
1675 */
1676#define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
1677#define AIPS_PACRD_WP3_MASK (0x20000U)
1678#define AIPS_PACRD_WP3_SHIFT (17U)
1679/*! WP3 - Write Protect
1680 * 0b0..This peripheral allows write accesses.
1681 * 0b1..This peripheral is write protected.
1682 */
1683#define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
1684#define AIPS_PACRD_SP3_MASK (0x40000U)
1685#define AIPS_PACRD_SP3_SHIFT (18U)
1686/*! SP3 - Supervisor Protect
1687 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1688 * 0b1..This peripheral requires supervisor privilege level for accesses.
1689 */
1690#define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
1691#define AIPS_PACRD_TP2_MASK (0x100000U)
1692#define AIPS_PACRD_TP2_SHIFT (20U)
1693/*! TP2 - Trusted Protect
1694 * 0b0..Accesses from an untrusted master are allowed.
1695 * 0b1..Accesses from an untrusted master are not allowed.
1696 */
1697#define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
1698#define AIPS_PACRD_WP2_MASK (0x200000U)
1699#define AIPS_PACRD_WP2_SHIFT (21U)
1700/*! WP2 - Write Protect
1701 * 0b0..This peripheral allows write accesses.
1702 * 0b1..This peripheral is write protected.
1703 */
1704#define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
1705#define AIPS_PACRD_SP2_MASK (0x400000U)
1706#define AIPS_PACRD_SP2_SHIFT (22U)
1707/*! SP2 - Supervisor Protect
1708 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1709 * 0b1..This peripheral requires supervisor privilege level for accesses.
1710 */
1711#define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
1712#define AIPS_PACRD_TP1_MASK (0x1000000U)
1713#define AIPS_PACRD_TP1_SHIFT (24U)
1714/*! TP1 - Trusted Protect
1715 * 0b0..Accesses from an untrusted master are allowed.
1716 * 0b1..Accesses from an untrusted master are not allowed.
1717 */
1718#define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
1719#define AIPS_PACRD_WP1_MASK (0x2000000U)
1720#define AIPS_PACRD_WP1_SHIFT (25U)
1721/*! WP1 - Write Protect
1722 * 0b0..This peripheral allows write accesses.
1723 * 0b1..This peripheral is write protected.
1724 */
1725#define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
1726#define AIPS_PACRD_SP1_MASK (0x4000000U)
1727#define AIPS_PACRD_SP1_SHIFT (26U)
1728/*! SP1 - Supervisor Protect
1729 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1730 * 0b1..This peripheral requires supervisor privilege level for accesses.
1731 */
1732#define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
1733#define AIPS_PACRD_TP0_MASK (0x10000000U)
1734#define AIPS_PACRD_TP0_SHIFT (28U)
1735/*! TP0 - Trusted Protect
1736 * 0b0..Accesses from an untrusted master are allowed.
1737 * 0b1..Accesses from an untrusted master are not allowed.
1738 */
1739#define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
1740#define AIPS_PACRD_WP0_MASK (0x20000000U)
1741#define AIPS_PACRD_WP0_SHIFT (29U)
1742/*! WP0 - Write Protect
1743 * 0b0..This peripheral allows write accesses.
1744 * 0b1..This peripheral is write protected.
1745 */
1746#define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
1747#define AIPS_PACRD_SP0_MASK (0x40000000U)
1748#define AIPS_PACRD_SP0_SHIFT (30U)
1749/*! SP0 - Supervisor Protect
1750 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1751 * 0b1..This peripheral requires supervisor privilege level for accesses.
1752 */
1753#define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
1754/*! @} */
1755
1756/*! @name PACRE - Peripheral Access Control Register */
1757/*! @{ */
1758#define AIPS_PACRE_TP7_MASK (0x1U)
1759#define AIPS_PACRE_TP7_SHIFT (0U)
1760/*! TP7 - Trusted Protect
1761 * 0b0..Accesses from an untrusted master are allowed.
1762 * 0b1..Accesses from an untrusted master are not allowed.
1763 */
1764#define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
1765#define AIPS_PACRE_WP7_MASK (0x2U)
1766#define AIPS_PACRE_WP7_SHIFT (1U)
1767/*! WP7 - Write Protect
1768 * 0b0..This peripheral allows write accesses.
1769 * 0b1..This peripheral is write protected.
1770 */
1771#define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
1772#define AIPS_PACRE_SP7_MASK (0x4U)
1773#define AIPS_PACRE_SP7_SHIFT (2U)
1774/*! SP7 - Supervisor Protect
1775 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1776 * 0b1..This peripheral requires supervisor privilege level for accesses.
1777 */
1778#define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
1779#define AIPS_PACRE_TP6_MASK (0x10U)
1780#define AIPS_PACRE_TP6_SHIFT (4U)
1781/*! TP6 - Trusted Protect
1782 * 0b0..Accesses from an untrusted master are allowed.
1783 * 0b1..Accesses from an untrusted master are not allowed.
1784 */
1785#define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
1786#define AIPS_PACRE_WP6_MASK (0x20U)
1787#define AIPS_PACRE_WP6_SHIFT (5U)
1788/*! WP6 - Write Protect
1789 * 0b0..This peripheral allows write accesses.
1790 * 0b1..This peripheral is write protected.
1791 */
1792#define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
1793#define AIPS_PACRE_SP6_MASK (0x40U)
1794#define AIPS_PACRE_SP6_SHIFT (6U)
1795/*! SP6 - Supervisor Protect
1796 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1797 * 0b1..This peripheral requires supervisor privilege level for accesses.
1798 */
1799#define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
1800#define AIPS_PACRE_TP5_MASK (0x100U)
1801#define AIPS_PACRE_TP5_SHIFT (8U)
1802/*! TP5 - Trusted Protect
1803 * 0b0..Accesses from an untrusted master are allowed.
1804 * 0b1..Accesses from an untrusted master are not allowed.
1805 */
1806#define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
1807#define AIPS_PACRE_WP5_MASK (0x200U)
1808#define AIPS_PACRE_WP5_SHIFT (9U)
1809/*! WP5 - Write Protect
1810 * 0b0..This peripheral allows write accesses.
1811 * 0b1..This peripheral is write protected.
1812 */
1813#define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
1814#define AIPS_PACRE_SP5_MASK (0x400U)
1815#define AIPS_PACRE_SP5_SHIFT (10U)
1816/*! SP5 - Supervisor Protect
1817 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1818 * 0b1..This peripheral requires supervisor privilege level for accesses.
1819 */
1820#define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
1821#define AIPS_PACRE_TP4_MASK (0x1000U)
1822#define AIPS_PACRE_TP4_SHIFT (12U)
1823/*! TP4 - Trusted Protect
1824 * 0b0..Accesses from an untrusted master are allowed.
1825 * 0b1..Accesses from an untrusted master are not allowed.
1826 */
1827#define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
1828#define AIPS_PACRE_WP4_MASK (0x2000U)
1829#define AIPS_PACRE_WP4_SHIFT (13U)
1830/*! WP4 - Write Protect
1831 * 0b0..This peripheral allows write accesses.
1832 * 0b1..This peripheral is write protected.
1833 */
1834#define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
1835#define AIPS_PACRE_SP4_MASK (0x4000U)
1836#define AIPS_PACRE_SP4_SHIFT (14U)
1837/*! SP4 - Supervisor Protect
1838 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1839 * 0b1..This peripheral requires supervisor privilege level for accesses.
1840 */
1841#define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
1842#define AIPS_PACRE_TP3_MASK (0x10000U)
1843#define AIPS_PACRE_TP3_SHIFT (16U)
1844/*! TP3 - Trusted Protect
1845 * 0b0..Accesses from an untrusted master are allowed.
1846 * 0b1..Accesses from an untrusted master are not allowed.
1847 */
1848#define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
1849#define AIPS_PACRE_WP3_MASK (0x20000U)
1850#define AIPS_PACRE_WP3_SHIFT (17U)
1851/*! WP3 - Write Protect
1852 * 0b0..This peripheral allows write accesses.
1853 * 0b1..This peripheral is write protected.
1854 */
1855#define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
1856#define AIPS_PACRE_SP3_MASK (0x40000U)
1857#define AIPS_PACRE_SP3_SHIFT (18U)
1858/*! SP3 - Supervisor Protect
1859 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1860 * 0b1..This peripheral requires supervisor privilege level for accesses.
1861 */
1862#define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
1863#define AIPS_PACRE_TP2_MASK (0x100000U)
1864#define AIPS_PACRE_TP2_SHIFT (20U)
1865/*! TP2 - Trusted Protect
1866 * 0b0..Accesses from an untrusted master are allowed.
1867 * 0b1..Accesses from an untrusted master are not allowed.
1868 */
1869#define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
1870#define AIPS_PACRE_WP2_MASK (0x200000U)
1871#define AIPS_PACRE_WP2_SHIFT (21U)
1872/*! WP2 - Write Protect
1873 * 0b0..This peripheral allows write accesses.
1874 * 0b1..This peripheral is write protected.
1875 */
1876#define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
1877#define AIPS_PACRE_SP2_MASK (0x400000U)
1878#define AIPS_PACRE_SP2_SHIFT (22U)
1879/*! SP2 - Supervisor Protect
1880 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1881 * 0b1..This peripheral requires supervisor privilege level for accesses.
1882 */
1883#define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
1884#define AIPS_PACRE_TP1_MASK (0x1000000U)
1885#define AIPS_PACRE_TP1_SHIFT (24U)
1886/*! TP1 - Trusted Protect
1887 * 0b0..Accesses from an untrusted master are allowed.
1888 * 0b1..Accesses from an untrusted master are not allowed.
1889 */
1890#define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
1891#define AIPS_PACRE_WP1_MASK (0x2000000U)
1892#define AIPS_PACRE_WP1_SHIFT (25U)
1893/*! WP1 - Write Protect
1894 * 0b0..This peripheral allows write accesses.
1895 * 0b1..This peripheral is write protected.
1896 */
1897#define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
1898#define AIPS_PACRE_SP1_MASK (0x4000000U)
1899#define AIPS_PACRE_SP1_SHIFT (26U)
1900/*! SP1 - Supervisor Protect
1901 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1902 * 0b1..This peripheral requires supervisor privilege level for accesses.
1903 */
1904#define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
1905#define AIPS_PACRE_TP0_MASK (0x10000000U)
1906#define AIPS_PACRE_TP0_SHIFT (28U)
1907/*! TP0 - Trusted Protect
1908 * 0b0..Accesses from an untrusted master are allowed.
1909 * 0b1..Accesses from an untrusted master are not allowed.
1910 */
1911#define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
1912#define AIPS_PACRE_WP0_MASK (0x20000000U)
1913#define AIPS_PACRE_WP0_SHIFT (29U)
1914/*! WP0 - Write Protect
1915 * 0b0..This peripheral allows write accesses.
1916 * 0b1..This peripheral is write protected.
1917 */
1918#define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
1919#define AIPS_PACRE_SP0_MASK (0x40000000U)
1920#define AIPS_PACRE_SP0_SHIFT (30U)
1921/*! SP0 - Supervisor Protect
1922 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1923 * 0b1..This peripheral requires supervisor privilege level for accesses.
1924 */
1925#define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
1926/*! @} */
1927
1928/*! @name PACRF - Peripheral Access Control Register */
1929/*! @{ */
1930#define AIPS_PACRF_TP7_MASK (0x1U)
1931#define AIPS_PACRF_TP7_SHIFT (0U)
1932/*! TP7 - Trusted Protect
1933 * 0b0..Accesses from an untrusted master are allowed.
1934 * 0b1..Accesses from an untrusted master are not allowed.
1935 */
1936#define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
1937#define AIPS_PACRF_WP7_MASK (0x2U)
1938#define AIPS_PACRF_WP7_SHIFT (1U)
1939/*! WP7 - Write Protect
1940 * 0b0..This peripheral allows write accesses.
1941 * 0b1..This peripheral is write protected.
1942 */
1943#define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
1944#define AIPS_PACRF_SP7_MASK (0x4U)
1945#define AIPS_PACRF_SP7_SHIFT (2U)
1946/*! SP7 - Supervisor Protect
1947 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1948 * 0b1..This peripheral requires supervisor privilege level for accesses.
1949 */
1950#define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
1951#define AIPS_PACRF_TP6_MASK (0x10U)
1952#define AIPS_PACRF_TP6_SHIFT (4U)
1953/*! TP6 - Trusted Protect
1954 * 0b0..Accesses from an untrusted master are allowed.
1955 * 0b1..Accesses from an untrusted master are not allowed.
1956 */
1957#define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
1958#define AIPS_PACRF_WP6_MASK (0x20U)
1959#define AIPS_PACRF_WP6_SHIFT (5U)
1960/*! WP6 - Write Protect
1961 * 0b0..This peripheral allows write accesses.
1962 * 0b1..This peripheral is write protected.
1963 */
1964#define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
1965#define AIPS_PACRF_SP6_MASK (0x40U)
1966#define AIPS_PACRF_SP6_SHIFT (6U)
1967/*! SP6 - Supervisor Protect
1968 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1969 * 0b1..This peripheral requires supervisor privilege level for accesses.
1970 */
1971#define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
1972#define AIPS_PACRF_TP5_MASK (0x100U)
1973#define AIPS_PACRF_TP5_SHIFT (8U)
1974/*! TP5 - Trusted Protect
1975 * 0b0..Accesses from an untrusted master are allowed.
1976 * 0b1..Accesses from an untrusted master are not allowed.
1977 */
1978#define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
1979#define AIPS_PACRF_WP5_MASK (0x200U)
1980#define AIPS_PACRF_WP5_SHIFT (9U)
1981/*! WP5 - Write Protect
1982 * 0b0..This peripheral allows write accesses.
1983 * 0b1..This peripheral is write protected.
1984 */
1985#define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
1986#define AIPS_PACRF_SP5_MASK (0x400U)
1987#define AIPS_PACRF_SP5_SHIFT (10U)
1988/*! SP5 - Supervisor Protect
1989 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1990 * 0b1..This peripheral requires supervisor privilege level for accesses.
1991 */
1992#define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
1993#define AIPS_PACRF_TP4_MASK (0x1000U)
1994#define AIPS_PACRF_TP4_SHIFT (12U)
1995/*! TP4 - Trusted Protect
1996 * 0b0..Accesses from an untrusted master are allowed.
1997 * 0b1..Accesses from an untrusted master are not allowed.
1998 */
1999#define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
2000#define AIPS_PACRF_WP4_MASK (0x2000U)
2001#define AIPS_PACRF_WP4_SHIFT (13U)
2002/*! WP4 - Write Protect
2003 * 0b0..This peripheral allows write accesses.
2004 * 0b1..This peripheral is write protected.
2005 */
2006#define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
2007#define AIPS_PACRF_SP4_MASK (0x4000U)
2008#define AIPS_PACRF_SP4_SHIFT (14U)
2009/*! SP4 - Supervisor Protect
2010 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2011 * 0b1..This peripheral requires supervisor privilege level for accesses.
2012 */
2013#define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
2014#define AIPS_PACRF_TP3_MASK (0x10000U)
2015#define AIPS_PACRF_TP3_SHIFT (16U)
2016/*! TP3 - Trusted Protect
2017 * 0b0..Accesses from an untrusted master are allowed.
2018 * 0b1..Accesses from an untrusted master are not allowed.
2019 */
2020#define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
2021#define AIPS_PACRF_WP3_MASK (0x20000U)
2022#define AIPS_PACRF_WP3_SHIFT (17U)
2023/*! WP3 - Write Protect
2024 * 0b0..This peripheral allows write accesses.
2025 * 0b1..This peripheral is write protected.
2026 */
2027#define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
2028#define AIPS_PACRF_SP3_MASK (0x40000U)
2029#define AIPS_PACRF_SP3_SHIFT (18U)
2030/*! SP3 - Supervisor Protect
2031 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2032 * 0b1..This peripheral requires supervisor privilege level for accesses.
2033 */
2034#define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
2035#define AIPS_PACRF_TP2_MASK (0x100000U)
2036#define AIPS_PACRF_TP2_SHIFT (20U)
2037/*! TP2 - Trusted Protect
2038 * 0b0..Accesses from an untrusted master are allowed.
2039 * 0b1..Accesses from an untrusted master are not allowed.
2040 */
2041#define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
2042#define AIPS_PACRF_WP2_MASK (0x200000U)
2043#define AIPS_PACRF_WP2_SHIFT (21U)
2044/*! WP2 - Write Protect
2045 * 0b0..This peripheral allows write accesses.
2046 * 0b1..This peripheral is write protected.
2047 */
2048#define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
2049#define AIPS_PACRF_SP2_MASK (0x400000U)
2050#define AIPS_PACRF_SP2_SHIFT (22U)
2051/*! SP2 - Supervisor Protect
2052 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2053 * 0b1..This peripheral requires supervisor privilege level for accesses.
2054 */
2055#define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
2056#define AIPS_PACRF_TP1_MASK (0x1000000U)
2057#define AIPS_PACRF_TP1_SHIFT (24U)
2058/*! TP1 - Trusted Protect
2059 * 0b0..Accesses from an untrusted master are allowed.
2060 * 0b1..Accesses from an untrusted master are not allowed.
2061 */
2062#define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
2063#define AIPS_PACRF_WP1_MASK (0x2000000U)
2064#define AIPS_PACRF_WP1_SHIFT (25U)
2065/*! WP1 - Write Protect
2066 * 0b0..This peripheral allows write accesses.
2067 * 0b1..This peripheral is write protected.
2068 */
2069#define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
2070#define AIPS_PACRF_SP1_MASK (0x4000000U)
2071#define AIPS_PACRF_SP1_SHIFT (26U)
2072/*! SP1 - Supervisor Protect
2073 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2074 * 0b1..This peripheral requires supervisor privilege level for accesses.
2075 */
2076#define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
2077#define AIPS_PACRF_TP0_MASK (0x10000000U)
2078#define AIPS_PACRF_TP0_SHIFT (28U)
2079/*! TP0 - Trusted Protect
2080 * 0b0..Accesses from an untrusted master are allowed.
2081 * 0b1..Accesses from an untrusted master are not allowed.
2082 */
2083#define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
2084#define AIPS_PACRF_WP0_MASK (0x20000000U)
2085#define AIPS_PACRF_WP0_SHIFT (29U)
2086/*! WP0 - Write Protect
2087 * 0b0..This peripheral allows write accesses.
2088 * 0b1..This peripheral is write protected.
2089 */
2090#define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
2091#define AIPS_PACRF_SP0_MASK (0x40000000U)
2092#define AIPS_PACRF_SP0_SHIFT (30U)
2093/*! SP0 - Supervisor Protect
2094 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2095 * 0b1..This peripheral requires supervisor privilege level for accesses.
2096 */
2097#define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
2098/*! @} */
2099
2100/*! @name PACRG - Peripheral Access Control Register */
2101/*! @{ */
2102#define AIPS_PACRG_TP7_MASK (0x1U)
2103#define AIPS_PACRG_TP7_SHIFT (0U)
2104/*! TP7 - Trusted Protect
2105 * 0b0..Accesses from an untrusted master are allowed.
2106 * 0b1..Accesses from an untrusted master are not allowed.
2107 */
2108#define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
2109#define AIPS_PACRG_WP7_MASK (0x2U)
2110#define AIPS_PACRG_WP7_SHIFT (1U)
2111/*! WP7 - Write Protect
2112 * 0b0..This peripheral allows write accesses.
2113 * 0b1..This peripheral is write protected.
2114 */
2115#define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
2116#define AIPS_PACRG_SP7_MASK (0x4U)
2117#define AIPS_PACRG_SP7_SHIFT (2U)
2118/*! SP7 - Supervisor Protect
2119 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2120 * 0b1..This peripheral requires supervisor privilege level for accesses.
2121 */
2122#define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
2123#define AIPS_PACRG_TP6_MASK (0x10U)
2124#define AIPS_PACRG_TP6_SHIFT (4U)
2125/*! TP6 - Trusted Protect
2126 * 0b0..Accesses from an untrusted master are allowed.
2127 * 0b1..Accesses from an untrusted master are not allowed.
2128 */
2129#define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
2130#define AIPS_PACRG_WP6_MASK (0x20U)
2131#define AIPS_PACRG_WP6_SHIFT (5U)
2132/*! WP6 - Write Protect
2133 * 0b0..This peripheral allows write accesses.
2134 * 0b1..This peripheral is write protected.
2135 */
2136#define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
2137#define AIPS_PACRG_SP6_MASK (0x40U)
2138#define AIPS_PACRG_SP6_SHIFT (6U)
2139/*! SP6 - Supervisor Protect
2140 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2141 * 0b1..This peripheral requires supervisor privilege level for accesses.
2142 */
2143#define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
2144#define AIPS_PACRG_TP5_MASK (0x100U)
2145#define AIPS_PACRG_TP5_SHIFT (8U)
2146/*! TP5 - Trusted Protect
2147 * 0b0..Accesses from an untrusted master are allowed.
2148 * 0b1..Accesses from an untrusted master are not allowed.
2149 */
2150#define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
2151#define AIPS_PACRG_WP5_MASK (0x200U)
2152#define AIPS_PACRG_WP5_SHIFT (9U)
2153/*! WP5 - Write Protect
2154 * 0b0..This peripheral allows write accesses.
2155 * 0b1..This peripheral is write protected.
2156 */
2157#define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
2158#define AIPS_PACRG_SP5_MASK (0x400U)
2159#define AIPS_PACRG_SP5_SHIFT (10U)
2160/*! SP5 - Supervisor Protect
2161 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2162 * 0b1..This peripheral requires supervisor privilege level for accesses.
2163 */
2164#define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
2165#define AIPS_PACRG_TP4_MASK (0x1000U)
2166#define AIPS_PACRG_TP4_SHIFT (12U)
2167/*! TP4 - Trusted Protect
2168 * 0b0..Accesses from an untrusted master are allowed.
2169 * 0b1..Accesses from an untrusted master are not allowed.
2170 */
2171#define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
2172#define AIPS_PACRG_WP4_MASK (0x2000U)
2173#define AIPS_PACRG_WP4_SHIFT (13U)
2174/*! WP4 - Write Protect
2175 * 0b0..This peripheral allows write accesses.
2176 * 0b1..This peripheral is write protected.
2177 */
2178#define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
2179#define AIPS_PACRG_SP4_MASK (0x4000U)
2180#define AIPS_PACRG_SP4_SHIFT (14U)
2181/*! SP4 - Supervisor Protect
2182 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2183 * 0b1..This peripheral requires supervisor privilege level for accesses.
2184 */
2185#define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
2186#define AIPS_PACRG_TP3_MASK (0x10000U)
2187#define AIPS_PACRG_TP3_SHIFT (16U)
2188/*! TP3 - Trusted Protect
2189 * 0b0..Accesses from an untrusted master are allowed.
2190 * 0b1..Accesses from an untrusted master are not allowed.
2191 */
2192#define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
2193#define AIPS_PACRG_WP3_MASK (0x20000U)
2194#define AIPS_PACRG_WP3_SHIFT (17U)
2195/*! WP3 - Write Protect
2196 * 0b0..This peripheral allows write accesses.
2197 * 0b1..This peripheral is write protected.
2198 */
2199#define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
2200#define AIPS_PACRG_SP3_MASK (0x40000U)
2201#define AIPS_PACRG_SP3_SHIFT (18U)
2202/*! SP3 - Supervisor Protect
2203 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2204 * 0b1..This peripheral requires supervisor privilege level for accesses.
2205 */
2206#define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
2207#define AIPS_PACRG_TP2_MASK (0x100000U)
2208#define AIPS_PACRG_TP2_SHIFT (20U)
2209/*! TP2 - Trusted Protect
2210 * 0b0..Accesses from an untrusted master are allowed.
2211 * 0b1..Accesses from an untrusted master are not allowed.
2212 */
2213#define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
2214#define AIPS_PACRG_WP2_MASK (0x200000U)
2215#define AIPS_PACRG_WP2_SHIFT (21U)
2216/*! WP2 - Write Protect
2217 * 0b0..This peripheral allows write accesses.
2218 * 0b1..This peripheral is write protected.
2219 */
2220#define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
2221#define AIPS_PACRG_SP2_MASK (0x400000U)
2222#define AIPS_PACRG_SP2_SHIFT (22U)
2223/*! SP2 - Supervisor Protect
2224 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2225 * 0b1..This peripheral requires supervisor privilege level for accesses.
2226 */
2227#define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
2228#define AIPS_PACRG_TP1_MASK (0x1000000U)
2229#define AIPS_PACRG_TP1_SHIFT (24U)
2230/*! TP1 - Trusted Protect
2231 * 0b0..Accesses from an untrusted master are allowed.
2232 * 0b1..Accesses from an untrusted master are not allowed.
2233 */
2234#define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
2235#define AIPS_PACRG_WP1_MASK (0x2000000U)
2236#define AIPS_PACRG_WP1_SHIFT (25U)
2237/*! WP1 - Write Protect
2238 * 0b0..This peripheral allows write accesses.
2239 * 0b1..This peripheral is write protected.
2240 */
2241#define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
2242#define AIPS_PACRG_SP1_MASK (0x4000000U)
2243#define AIPS_PACRG_SP1_SHIFT (26U)
2244/*! SP1 - Supervisor Protect
2245 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2246 * 0b1..This peripheral requires supervisor privilege level for accesses.
2247 */
2248#define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
2249#define AIPS_PACRG_TP0_MASK (0x10000000U)
2250#define AIPS_PACRG_TP0_SHIFT (28U)
2251/*! TP0 - Trusted Protect
2252 * 0b0..Accesses from an untrusted master are allowed.
2253 * 0b1..Accesses from an untrusted master are not allowed.
2254 */
2255#define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
2256#define AIPS_PACRG_WP0_MASK (0x20000000U)
2257#define AIPS_PACRG_WP0_SHIFT (29U)
2258/*! WP0 - Write Protect
2259 * 0b0..This peripheral allows write accesses.
2260 * 0b1..This peripheral is write protected.
2261 */
2262#define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
2263#define AIPS_PACRG_SP0_MASK (0x40000000U)
2264#define AIPS_PACRG_SP0_SHIFT (30U)
2265/*! SP0 - Supervisor Protect
2266 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2267 * 0b1..This peripheral requires supervisor privilege level for accesses.
2268 */
2269#define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
2270/*! @} */
2271
2272/*! @name PACRH - Peripheral Access Control Register */
2273/*! @{ */
2274#define AIPS_PACRH_TP7_MASK (0x1U)
2275#define AIPS_PACRH_TP7_SHIFT (0U)
2276/*! TP7 - Trusted Protect
2277 * 0b0..Accesses from an untrusted master are allowed.
2278 * 0b1..Accesses from an untrusted master are not allowed.
2279 */
2280#define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
2281#define AIPS_PACRH_WP7_MASK (0x2U)
2282#define AIPS_PACRH_WP7_SHIFT (1U)
2283/*! WP7 - Write Protect
2284 * 0b0..This peripheral allows write accesses.
2285 * 0b1..This peripheral is write protected.
2286 */
2287#define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
2288#define AIPS_PACRH_SP7_MASK (0x4U)
2289#define AIPS_PACRH_SP7_SHIFT (2U)
2290/*! SP7 - Supervisor Protect
2291 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2292 * 0b1..This peripheral requires supervisor privilege level for accesses.
2293 */
2294#define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
2295#define AIPS_PACRH_TP6_MASK (0x10U)
2296#define AIPS_PACRH_TP6_SHIFT (4U)
2297/*! TP6 - Trusted Protect
2298 * 0b0..Accesses from an untrusted master are allowed.
2299 * 0b1..Accesses from an untrusted master are not allowed.
2300 */
2301#define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
2302#define AIPS_PACRH_WP6_MASK (0x20U)
2303#define AIPS_PACRH_WP6_SHIFT (5U)
2304/*! WP6 - Write Protect
2305 * 0b0..This peripheral allows write accesses.
2306 * 0b1..This peripheral is write protected.
2307 */
2308#define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
2309#define AIPS_PACRH_SP6_MASK (0x40U)
2310#define AIPS_PACRH_SP6_SHIFT (6U)
2311/*! SP6 - Supervisor Protect
2312 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2313 * 0b1..This peripheral requires supervisor privilege level for accesses.
2314 */
2315#define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
2316#define AIPS_PACRH_TP5_MASK (0x100U)
2317#define AIPS_PACRH_TP5_SHIFT (8U)
2318/*! TP5 - Trusted Protect
2319 * 0b0..Accesses from an untrusted master are allowed.
2320 * 0b1..Accesses from an untrusted master are not allowed.
2321 */
2322#define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
2323#define AIPS_PACRH_WP5_MASK (0x200U)
2324#define AIPS_PACRH_WP5_SHIFT (9U)
2325/*! WP5 - Write Protect
2326 * 0b0..This peripheral allows write accesses.
2327 * 0b1..This peripheral is write protected.
2328 */
2329#define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
2330#define AIPS_PACRH_SP5_MASK (0x400U)
2331#define AIPS_PACRH_SP5_SHIFT (10U)
2332/*! SP5 - Supervisor Protect
2333 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2334 * 0b1..This peripheral requires supervisor privilege level for accesses.
2335 */
2336#define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
2337#define AIPS_PACRH_TP4_MASK (0x1000U)
2338#define AIPS_PACRH_TP4_SHIFT (12U)
2339/*! TP4 - Trusted Protect
2340 * 0b0..Accesses from an untrusted master are allowed.
2341 * 0b1..Accesses from an untrusted master are not allowed.
2342 */
2343#define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
2344#define AIPS_PACRH_WP4_MASK (0x2000U)
2345#define AIPS_PACRH_WP4_SHIFT (13U)
2346/*! WP4 - Write Protect
2347 * 0b0..This peripheral allows write accesses.
2348 * 0b1..This peripheral is write protected.
2349 */
2350#define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
2351#define AIPS_PACRH_SP4_MASK (0x4000U)
2352#define AIPS_PACRH_SP4_SHIFT (14U)
2353/*! SP4 - Supervisor Protect
2354 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2355 * 0b1..This peripheral requires supervisor privilege level for accesses.
2356 */
2357#define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
2358#define AIPS_PACRH_TP3_MASK (0x10000U)
2359#define AIPS_PACRH_TP3_SHIFT (16U)
2360/*! TP3 - Trusted Protect
2361 * 0b0..Accesses from an untrusted master are allowed.
2362 * 0b1..Accesses from an untrusted master are not allowed.
2363 */
2364#define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
2365#define AIPS_PACRH_WP3_MASK (0x20000U)
2366#define AIPS_PACRH_WP3_SHIFT (17U)
2367/*! WP3 - Write Protect
2368 * 0b0..This peripheral allows write accesses.
2369 * 0b1..This peripheral is write protected.
2370 */
2371#define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
2372#define AIPS_PACRH_SP3_MASK (0x40000U)
2373#define AIPS_PACRH_SP3_SHIFT (18U)
2374/*! SP3 - Supervisor Protect
2375 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2376 * 0b1..This peripheral requires supervisor privilege level for accesses.
2377 */
2378#define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
2379#define AIPS_PACRH_TP2_MASK (0x100000U)
2380#define AIPS_PACRH_TP2_SHIFT (20U)
2381/*! TP2 - Trusted Protect
2382 * 0b0..Accesses from an untrusted master are allowed.
2383 * 0b1..Accesses from an untrusted master are not allowed.
2384 */
2385#define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
2386#define AIPS_PACRH_WP2_MASK (0x200000U)
2387#define AIPS_PACRH_WP2_SHIFT (21U)
2388/*! WP2 - Write Protect
2389 * 0b0..This peripheral allows write accesses.
2390 * 0b1..This peripheral is write protected.
2391 */
2392#define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
2393#define AIPS_PACRH_SP2_MASK (0x400000U)
2394#define AIPS_PACRH_SP2_SHIFT (22U)
2395/*! SP2 - Supervisor Protect
2396 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2397 * 0b1..This peripheral requires supervisor privilege level for accesses.
2398 */
2399#define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
2400#define AIPS_PACRH_TP1_MASK (0x1000000U)
2401#define AIPS_PACRH_TP1_SHIFT (24U)
2402/*! TP1 - Trusted Protect
2403 * 0b0..Accesses from an untrusted master are allowed.
2404 * 0b1..Accesses from an untrusted master are not allowed.
2405 */
2406#define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
2407#define AIPS_PACRH_WP1_MASK (0x2000000U)
2408#define AIPS_PACRH_WP1_SHIFT (25U)
2409/*! WP1 - Write Protect
2410 * 0b0..This peripheral allows write accesses.
2411 * 0b1..This peripheral is write protected.
2412 */
2413#define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
2414#define AIPS_PACRH_SP1_MASK (0x4000000U)
2415#define AIPS_PACRH_SP1_SHIFT (26U)
2416/*! SP1 - Supervisor Protect
2417 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2418 * 0b1..This peripheral requires supervisor privilege level for accesses.
2419 */
2420#define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
2421#define AIPS_PACRH_TP0_MASK (0x10000000U)
2422#define AIPS_PACRH_TP0_SHIFT (28U)
2423/*! TP0 - Trusted Protect
2424 * 0b0..Accesses from an untrusted master are allowed.
2425 * 0b1..Accesses from an untrusted master are not allowed.
2426 */
2427#define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
2428#define AIPS_PACRH_WP0_MASK (0x20000000U)
2429#define AIPS_PACRH_WP0_SHIFT (29U)
2430/*! WP0 - Write Protect
2431 * 0b0..This peripheral allows write accesses.
2432 * 0b1..This peripheral is write protected.
2433 */
2434#define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
2435#define AIPS_PACRH_SP0_MASK (0x40000000U)
2436#define AIPS_PACRH_SP0_SHIFT (30U)
2437/*! SP0 - Supervisor Protect
2438 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2439 * 0b1..This peripheral requires supervisor privilege level for accesses.
2440 */
2441#define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
2442/*! @} */
2443
2444/*! @name PACRI - Peripheral Access Control Register */
2445/*! @{ */
2446#define AIPS_PACRI_TP7_MASK (0x1U)
2447#define AIPS_PACRI_TP7_SHIFT (0U)
2448/*! TP7 - Trusted Protect
2449 * 0b0..Accesses from an untrusted master are allowed.
2450 * 0b1..Accesses from an untrusted master are not allowed.
2451 */
2452#define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
2453#define AIPS_PACRI_WP7_MASK (0x2U)
2454#define AIPS_PACRI_WP7_SHIFT (1U)
2455/*! WP7 - Write Protect
2456 * 0b0..This peripheral allows write accesses.
2457 * 0b1..This peripheral is write protected.
2458 */
2459#define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
2460#define AIPS_PACRI_SP7_MASK (0x4U)
2461#define AIPS_PACRI_SP7_SHIFT (2U)
2462/*! SP7 - Supervisor Protect
2463 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2464 * 0b1..This peripheral requires supervisor privilege level for accesses.
2465 */
2466#define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
2467#define AIPS_PACRI_TP6_MASK (0x10U)
2468#define AIPS_PACRI_TP6_SHIFT (4U)
2469/*! TP6 - Trusted Protect
2470 * 0b0..Accesses from an untrusted master are allowed.
2471 * 0b1..Accesses from an untrusted master are not allowed.
2472 */
2473#define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
2474#define AIPS_PACRI_WP6_MASK (0x20U)
2475#define AIPS_PACRI_WP6_SHIFT (5U)
2476/*! WP6 - Write Protect
2477 * 0b0..This peripheral allows write accesses.
2478 * 0b1..This peripheral is write protected.
2479 */
2480#define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
2481#define AIPS_PACRI_SP6_MASK (0x40U)
2482#define AIPS_PACRI_SP6_SHIFT (6U)
2483/*! SP6 - Supervisor Protect
2484 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2485 * 0b1..This peripheral requires supervisor privilege level for accesses.
2486 */
2487#define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
2488#define AIPS_PACRI_TP5_MASK (0x100U)
2489#define AIPS_PACRI_TP5_SHIFT (8U)
2490/*! TP5 - Trusted Protect
2491 * 0b0..Accesses from an untrusted master are allowed.
2492 * 0b1..Accesses from an untrusted master are not allowed.
2493 */
2494#define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
2495#define AIPS_PACRI_WP5_MASK (0x200U)
2496#define AIPS_PACRI_WP5_SHIFT (9U)
2497/*! WP5 - Write Protect
2498 * 0b0..This peripheral allows write accesses.
2499 * 0b1..This peripheral is write protected.
2500 */
2501#define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
2502#define AIPS_PACRI_SP5_MASK (0x400U)
2503#define AIPS_PACRI_SP5_SHIFT (10U)
2504/*! SP5 - Supervisor Protect
2505 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2506 * 0b1..This peripheral requires supervisor privilege level for accesses.
2507 */
2508#define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
2509#define AIPS_PACRI_TP4_MASK (0x1000U)
2510#define AIPS_PACRI_TP4_SHIFT (12U)
2511/*! TP4 - Trusted Protect
2512 * 0b0..Accesses from an untrusted master are allowed.
2513 * 0b1..Accesses from an untrusted master are not allowed.
2514 */
2515#define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
2516#define AIPS_PACRI_WP4_MASK (0x2000U)
2517#define AIPS_PACRI_WP4_SHIFT (13U)
2518/*! WP4 - Write Protect
2519 * 0b0..This peripheral allows write accesses.
2520 * 0b1..This peripheral is write protected.
2521 */
2522#define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
2523#define AIPS_PACRI_SP4_MASK (0x4000U)
2524#define AIPS_PACRI_SP4_SHIFT (14U)
2525/*! SP4 - Supervisor Protect
2526 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2527 * 0b1..This peripheral requires supervisor privilege level for accesses.
2528 */
2529#define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
2530#define AIPS_PACRI_TP3_MASK (0x10000U)
2531#define AIPS_PACRI_TP3_SHIFT (16U)
2532/*! TP3 - Trusted Protect
2533 * 0b0..Accesses from an untrusted master are allowed.
2534 * 0b1..Accesses from an untrusted master are not allowed.
2535 */
2536#define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
2537#define AIPS_PACRI_WP3_MASK (0x20000U)
2538#define AIPS_PACRI_WP3_SHIFT (17U)
2539/*! WP3 - Write Protect
2540 * 0b0..This peripheral allows write accesses.
2541 * 0b1..This peripheral is write protected.
2542 */
2543#define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
2544#define AIPS_PACRI_SP3_MASK (0x40000U)
2545#define AIPS_PACRI_SP3_SHIFT (18U)
2546/*! SP3 - Supervisor Protect
2547 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2548 * 0b1..This peripheral requires supervisor privilege level for accesses.
2549 */
2550#define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
2551#define AIPS_PACRI_TP2_MASK (0x100000U)
2552#define AIPS_PACRI_TP2_SHIFT (20U)
2553/*! TP2 - Trusted Protect
2554 * 0b0..Accesses from an untrusted master are allowed.
2555 * 0b1..Accesses from an untrusted master are not allowed.
2556 */
2557#define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
2558#define AIPS_PACRI_WP2_MASK (0x200000U)
2559#define AIPS_PACRI_WP2_SHIFT (21U)
2560/*! WP2 - Write Protect
2561 * 0b0..This peripheral allows write accesses.
2562 * 0b1..This peripheral is write protected.
2563 */
2564#define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
2565#define AIPS_PACRI_SP2_MASK (0x400000U)
2566#define AIPS_PACRI_SP2_SHIFT (22U)
2567/*! SP2 - Supervisor Protect
2568 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2569 * 0b1..This peripheral requires supervisor privilege level for accesses.
2570 */
2571#define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
2572#define AIPS_PACRI_TP1_MASK (0x1000000U)
2573#define AIPS_PACRI_TP1_SHIFT (24U)
2574/*! TP1 - Trusted Protect
2575 * 0b0..Accesses from an untrusted master are allowed.
2576 * 0b1..Accesses from an untrusted master are not allowed.
2577 */
2578#define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
2579#define AIPS_PACRI_WP1_MASK (0x2000000U)
2580#define AIPS_PACRI_WP1_SHIFT (25U)
2581/*! WP1 - Write Protect
2582 * 0b0..This peripheral allows write accesses.
2583 * 0b1..This peripheral is write protected.
2584 */
2585#define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
2586#define AIPS_PACRI_SP1_MASK (0x4000000U)
2587#define AIPS_PACRI_SP1_SHIFT (26U)
2588/*! SP1 - Supervisor Protect
2589 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2590 * 0b1..This peripheral requires supervisor privilege level for accesses.
2591 */
2592#define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
2593#define AIPS_PACRI_TP0_MASK (0x10000000U)
2594#define AIPS_PACRI_TP0_SHIFT (28U)
2595/*! TP0 - Trusted Protect
2596 * 0b0..Accesses from an untrusted master are allowed.
2597 * 0b1..Accesses from an untrusted master are not allowed.
2598 */
2599#define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
2600#define AIPS_PACRI_WP0_MASK (0x20000000U)
2601#define AIPS_PACRI_WP0_SHIFT (29U)
2602/*! WP0 - Write Protect
2603 * 0b0..This peripheral allows write accesses.
2604 * 0b1..This peripheral is write protected.
2605 */
2606#define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
2607#define AIPS_PACRI_SP0_MASK (0x40000000U)
2608#define AIPS_PACRI_SP0_SHIFT (30U)
2609/*! SP0 - Supervisor Protect
2610 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2611 * 0b1..This peripheral requires supervisor privilege level for accesses.
2612 */
2613#define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
2614/*! @} */
2615
2616/*! @name PACRJ - Peripheral Access Control Register */
2617/*! @{ */
2618#define AIPS_PACRJ_TP7_MASK (0x1U)
2619#define AIPS_PACRJ_TP7_SHIFT (0U)
2620/*! TP7 - Trusted Protect
2621 * 0b0..Accesses from an untrusted master are allowed.
2622 * 0b1..Accesses from an untrusted master are not allowed.
2623 */
2624#define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
2625#define AIPS_PACRJ_WP7_MASK (0x2U)
2626#define AIPS_PACRJ_WP7_SHIFT (1U)
2627/*! WP7 - Write Protect
2628 * 0b0..This peripheral allows write accesses.
2629 * 0b1..This peripheral is write protected.
2630 */
2631#define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
2632#define AIPS_PACRJ_SP7_MASK (0x4U)
2633#define AIPS_PACRJ_SP7_SHIFT (2U)
2634/*! SP7 - Supervisor Protect
2635 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2636 * 0b1..This peripheral requires supervisor privilege level for accesses.
2637 */
2638#define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
2639#define AIPS_PACRJ_TP6_MASK (0x10U)
2640#define AIPS_PACRJ_TP6_SHIFT (4U)
2641/*! TP6 - Trusted Protect
2642 * 0b0..Accesses from an untrusted master are allowed.
2643 * 0b1..Accesses from an untrusted master are not allowed.
2644 */
2645#define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
2646#define AIPS_PACRJ_WP6_MASK (0x20U)
2647#define AIPS_PACRJ_WP6_SHIFT (5U)
2648/*! WP6 - Write Protect
2649 * 0b0..This peripheral allows write accesses.
2650 * 0b1..This peripheral is write protected.
2651 */
2652#define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
2653#define AIPS_PACRJ_SP6_MASK (0x40U)
2654#define AIPS_PACRJ_SP6_SHIFT (6U)
2655/*! SP6 - Supervisor Protect
2656 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2657 * 0b1..This peripheral requires supervisor privilege level for accesses.
2658 */
2659#define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
2660#define AIPS_PACRJ_TP5_MASK (0x100U)
2661#define AIPS_PACRJ_TP5_SHIFT (8U)
2662/*! TP5 - Trusted Protect
2663 * 0b0..Accesses from an untrusted master are allowed.
2664 * 0b1..Accesses from an untrusted master are not allowed.
2665 */
2666#define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
2667#define AIPS_PACRJ_WP5_MASK (0x200U)
2668#define AIPS_PACRJ_WP5_SHIFT (9U)
2669/*! WP5 - Write Protect
2670 * 0b0..This peripheral allows write accesses.
2671 * 0b1..This peripheral is write protected.
2672 */
2673#define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
2674#define AIPS_PACRJ_SP5_MASK (0x400U)
2675#define AIPS_PACRJ_SP5_SHIFT (10U)
2676/*! SP5 - Supervisor Protect
2677 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2678 * 0b1..This peripheral requires supervisor privilege level for accesses.
2679 */
2680#define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
2681#define AIPS_PACRJ_TP4_MASK (0x1000U)
2682#define AIPS_PACRJ_TP4_SHIFT (12U)
2683/*! TP4 - Trusted Protect
2684 * 0b0..Accesses from an untrusted master are allowed.
2685 * 0b1..Accesses from an untrusted master are not allowed.
2686 */
2687#define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
2688#define AIPS_PACRJ_WP4_MASK (0x2000U)
2689#define AIPS_PACRJ_WP4_SHIFT (13U)
2690/*! WP4 - Write Protect
2691 * 0b0..This peripheral allows write accesses.
2692 * 0b1..This peripheral is write protected.
2693 */
2694#define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
2695#define AIPS_PACRJ_SP4_MASK (0x4000U)
2696#define AIPS_PACRJ_SP4_SHIFT (14U)
2697/*! SP4 - Supervisor Protect
2698 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2699 * 0b1..This peripheral requires supervisor privilege level for accesses.
2700 */
2701#define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
2702#define AIPS_PACRJ_TP3_MASK (0x10000U)
2703#define AIPS_PACRJ_TP3_SHIFT (16U)
2704/*! TP3 - Trusted Protect
2705 * 0b0..Accesses from an untrusted master are allowed.
2706 * 0b1..Accesses from an untrusted master are not allowed.
2707 */
2708#define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
2709#define AIPS_PACRJ_WP3_MASK (0x20000U)
2710#define AIPS_PACRJ_WP3_SHIFT (17U)
2711/*! WP3 - Write Protect
2712 * 0b0..This peripheral allows write accesses.
2713 * 0b1..This peripheral is write protected.
2714 */
2715#define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
2716#define AIPS_PACRJ_SP3_MASK (0x40000U)
2717#define AIPS_PACRJ_SP3_SHIFT (18U)
2718/*! SP3 - Supervisor Protect
2719 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2720 * 0b1..This peripheral requires supervisor privilege level for accesses.
2721 */
2722#define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
2723#define AIPS_PACRJ_TP2_MASK (0x100000U)
2724#define AIPS_PACRJ_TP2_SHIFT (20U)
2725/*! TP2 - Trusted Protect
2726 * 0b0..Accesses from an untrusted master are allowed.
2727 * 0b1..Accesses from an untrusted master are not allowed.
2728 */
2729#define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
2730#define AIPS_PACRJ_WP2_MASK (0x200000U)
2731#define AIPS_PACRJ_WP2_SHIFT (21U)
2732/*! WP2 - Write Protect
2733 * 0b0..This peripheral allows write accesses.
2734 * 0b1..This peripheral is write protected.
2735 */
2736#define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
2737#define AIPS_PACRJ_SP2_MASK (0x400000U)
2738#define AIPS_PACRJ_SP2_SHIFT (22U)
2739/*! SP2 - Supervisor Protect
2740 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2741 * 0b1..This peripheral requires supervisor privilege level for accesses.
2742 */
2743#define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
2744#define AIPS_PACRJ_TP1_MASK (0x1000000U)
2745#define AIPS_PACRJ_TP1_SHIFT (24U)
2746/*! TP1 - Trusted Protect
2747 * 0b0..Accesses from an untrusted master are allowed.
2748 * 0b1..Accesses from an untrusted master are not allowed.
2749 */
2750#define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
2751#define AIPS_PACRJ_WP1_MASK (0x2000000U)
2752#define AIPS_PACRJ_WP1_SHIFT (25U)
2753/*! WP1 - Write Protect
2754 * 0b0..This peripheral allows write accesses.
2755 * 0b1..This peripheral is write protected.
2756 */
2757#define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
2758#define AIPS_PACRJ_SP1_MASK (0x4000000U)
2759#define AIPS_PACRJ_SP1_SHIFT (26U)
2760/*! SP1 - Supervisor Protect
2761 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2762 * 0b1..This peripheral requires supervisor privilege level for accesses.
2763 */
2764#define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
2765#define AIPS_PACRJ_TP0_MASK (0x10000000U)
2766#define AIPS_PACRJ_TP0_SHIFT (28U)
2767/*! TP0 - Trusted Protect
2768 * 0b0..Accesses from an untrusted master are allowed.
2769 * 0b1..Accesses from an untrusted master are not allowed.
2770 */
2771#define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
2772#define AIPS_PACRJ_WP0_MASK (0x20000000U)
2773#define AIPS_PACRJ_WP0_SHIFT (29U)
2774/*! WP0 - Write Protect
2775 * 0b0..This peripheral allows write accesses.
2776 * 0b1..This peripheral is write protected.
2777 */
2778#define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
2779#define AIPS_PACRJ_SP0_MASK (0x40000000U)
2780#define AIPS_PACRJ_SP0_SHIFT (30U)
2781/*! SP0 - Supervisor Protect
2782 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2783 * 0b1..This peripheral requires supervisor privilege level for accesses.
2784 */
2785#define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
2786/*! @} */
2787
2788/*! @name PACRK - Peripheral Access Control Register */
2789/*! @{ */
2790#define AIPS_PACRK_TP7_MASK (0x1U)
2791#define AIPS_PACRK_TP7_SHIFT (0U)
2792/*! TP7 - Trusted Protect
2793 * 0b0..Accesses from an untrusted master are allowed.
2794 * 0b1..Accesses from an untrusted master are not allowed.
2795 */
2796#define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
2797#define AIPS_PACRK_WP7_MASK (0x2U)
2798#define AIPS_PACRK_WP7_SHIFT (1U)
2799/*! WP7 - Write Protect
2800 * 0b0..This peripheral allows write accesses.
2801 * 0b1..This peripheral is write protected.
2802 */
2803#define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
2804#define AIPS_PACRK_SP7_MASK (0x4U)
2805#define AIPS_PACRK_SP7_SHIFT (2U)
2806/*! SP7 - Supervisor Protect
2807 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2808 * 0b1..This peripheral requires supervisor privilege level for accesses.
2809 */
2810#define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
2811#define AIPS_PACRK_TP6_MASK (0x10U)
2812#define AIPS_PACRK_TP6_SHIFT (4U)
2813/*! TP6 - Trusted Protect
2814 * 0b0..Accesses from an untrusted master are allowed.
2815 * 0b1..Accesses from an untrusted master are not allowed.
2816 */
2817#define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
2818#define AIPS_PACRK_WP6_MASK (0x20U)
2819#define AIPS_PACRK_WP6_SHIFT (5U)
2820/*! WP6 - Write Protect
2821 * 0b0..This peripheral allows write accesses.
2822 * 0b1..This peripheral is write protected.
2823 */
2824#define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
2825#define AIPS_PACRK_SP6_MASK (0x40U)
2826#define AIPS_PACRK_SP6_SHIFT (6U)
2827/*! SP6 - Supervisor Protect
2828 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2829 * 0b1..This peripheral requires supervisor privilege level for accesses.
2830 */
2831#define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
2832#define AIPS_PACRK_TP5_MASK (0x100U)
2833#define AIPS_PACRK_TP5_SHIFT (8U)
2834/*! TP5 - Trusted Protect
2835 * 0b0..Accesses from an untrusted master are allowed.
2836 * 0b1..Accesses from an untrusted master are not allowed.
2837 */
2838#define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
2839#define AIPS_PACRK_WP5_MASK (0x200U)
2840#define AIPS_PACRK_WP5_SHIFT (9U)
2841/*! WP5 - Write Protect
2842 * 0b0..This peripheral allows write accesses.
2843 * 0b1..This peripheral is write protected.
2844 */
2845#define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
2846#define AIPS_PACRK_SP5_MASK (0x400U)
2847#define AIPS_PACRK_SP5_SHIFT (10U)
2848/*! SP5 - Supervisor Protect
2849 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2850 * 0b1..This peripheral requires supervisor privilege level for accesses.
2851 */
2852#define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
2853#define AIPS_PACRK_TP4_MASK (0x1000U)
2854#define AIPS_PACRK_TP4_SHIFT (12U)
2855/*! TP4 - Trusted Protect
2856 * 0b0..Accesses from an untrusted master are allowed.
2857 * 0b1..Accesses from an untrusted master are not allowed.
2858 */
2859#define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
2860#define AIPS_PACRK_WP4_MASK (0x2000U)
2861#define AIPS_PACRK_WP4_SHIFT (13U)
2862/*! WP4 - Write Protect
2863 * 0b0..This peripheral allows write accesses.
2864 * 0b1..This peripheral is write protected.
2865 */
2866#define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
2867#define AIPS_PACRK_SP4_MASK (0x4000U)
2868#define AIPS_PACRK_SP4_SHIFT (14U)
2869/*! SP4 - Supervisor Protect
2870 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2871 * 0b1..This peripheral requires supervisor privilege level for accesses.
2872 */
2873#define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
2874#define AIPS_PACRK_TP3_MASK (0x10000U)
2875#define AIPS_PACRK_TP3_SHIFT (16U)
2876/*! TP3 - Trusted Protect
2877 * 0b0..Accesses from an untrusted master are allowed.
2878 * 0b1..Accesses from an untrusted master are not allowed.
2879 */
2880#define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
2881#define AIPS_PACRK_WP3_MASK (0x20000U)
2882#define AIPS_PACRK_WP3_SHIFT (17U)
2883/*! WP3 - Write Protect
2884 * 0b0..This peripheral allows write accesses.
2885 * 0b1..This peripheral is write protected.
2886 */
2887#define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
2888#define AIPS_PACRK_SP3_MASK (0x40000U)
2889#define AIPS_PACRK_SP3_SHIFT (18U)
2890/*! SP3 - Supervisor Protect
2891 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2892 * 0b1..This peripheral requires supervisor privilege level for accesses.
2893 */
2894#define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
2895#define AIPS_PACRK_TP2_MASK (0x100000U)
2896#define AIPS_PACRK_TP2_SHIFT (20U)
2897/*! TP2 - Trusted Protect
2898 * 0b0..Accesses from an untrusted master are allowed.
2899 * 0b1..Accesses from an untrusted master are not allowed.
2900 */
2901#define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
2902#define AIPS_PACRK_WP2_MASK (0x200000U)
2903#define AIPS_PACRK_WP2_SHIFT (21U)
2904/*! WP2 - Write Protect
2905 * 0b0..This peripheral allows write accesses.
2906 * 0b1..This peripheral is write protected.
2907 */
2908#define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
2909#define AIPS_PACRK_SP2_MASK (0x400000U)
2910#define AIPS_PACRK_SP2_SHIFT (22U)
2911/*! SP2 - Supervisor Protect
2912 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2913 * 0b1..This peripheral requires supervisor privilege level for accesses.
2914 */
2915#define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
2916#define AIPS_PACRK_TP1_MASK (0x1000000U)
2917#define AIPS_PACRK_TP1_SHIFT (24U)
2918/*! TP1 - Trusted Protect
2919 * 0b0..Accesses from an untrusted master are allowed.
2920 * 0b1..Accesses from an untrusted master are not allowed.
2921 */
2922#define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
2923#define AIPS_PACRK_WP1_MASK (0x2000000U)
2924#define AIPS_PACRK_WP1_SHIFT (25U)
2925/*! WP1 - Write Protect
2926 * 0b0..This peripheral allows write accesses.
2927 * 0b1..This peripheral is write protected.
2928 */
2929#define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
2930#define AIPS_PACRK_SP1_MASK (0x4000000U)
2931#define AIPS_PACRK_SP1_SHIFT (26U)
2932/*! SP1 - Supervisor Protect
2933 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2934 * 0b1..This peripheral requires supervisor privilege level for accesses.
2935 */
2936#define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
2937#define AIPS_PACRK_TP0_MASK (0x10000000U)
2938#define AIPS_PACRK_TP0_SHIFT (28U)
2939/*! TP0 - Trusted Protect
2940 * 0b0..Accesses from an untrusted master are allowed.
2941 * 0b1..Accesses from an untrusted master are not allowed.
2942 */
2943#define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
2944#define AIPS_PACRK_WP0_MASK (0x20000000U)
2945#define AIPS_PACRK_WP0_SHIFT (29U)
2946/*! WP0 - Write Protect
2947 * 0b0..This peripheral allows write accesses.
2948 * 0b1..This peripheral is write protected.
2949 */
2950#define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
2951#define AIPS_PACRK_SP0_MASK (0x40000000U)
2952#define AIPS_PACRK_SP0_SHIFT (30U)
2953/*! SP0 - Supervisor Protect
2954 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2955 * 0b1..This peripheral requires supervisor privilege level for accesses.
2956 */
2957#define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
2958/*! @} */
2959
2960/*! @name PACRL - Peripheral Access Control Register */
2961/*! @{ */
2962#define AIPS_PACRL_TP7_MASK (0x1U)
2963#define AIPS_PACRL_TP7_SHIFT (0U)
2964/*! TP7 - Trusted Protect
2965 * 0b0..Accesses from an untrusted master are allowed.
2966 * 0b1..Accesses from an untrusted master are not allowed.
2967 */
2968#define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
2969#define AIPS_PACRL_WP7_MASK (0x2U)
2970#define AIPS_PACRL_WP7_SHIFT (1U)
2971/*! WP7 - Write Protect
2972 * 0b0..This peripheral allows write accesses.
2973 * 0b1..This peripheral is write protected.
2974 */
2975#define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
2976#define AIPS_PACRL_SP7_MASK (0x4U)
2977#define AIPS_PACRL_SP7_SHIFT (2U)
2978/*! SP7 - Supervisor Protect
2979 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2980 * 0b1..This peripheral requires supervisor privilege level for accesses.
2981 */
2982#define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
2983#define AIPS_PACRL_TP6_MASK (0x10U)
2984#define AIPS_PACRL_TP6_SHIFT (4U)
2985/*! TP6 - Trusted Protect
2986 * 0b0..Accesses from an untrusted master are allowed.
2987 * 0b1..Accesses from an untrusted master are not allowed.
2988 */
2989#define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
2990#define AIPS_PACRL_WP6_MASK (0x20U)
2991#define AIPS_PACRL_WP6_SHIFT (5U)
2992/*! WP6 - Write Protect
2993 * 0b0..This peripheral allows write accesses.
2994 * 0b1..This peripheral is write protected.
2995 */
2996#define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
2997#define AIPS_PACRL_SP6_MASK (0x40U)
2998#define AIPS_PACRL_SP6_SHIFT (6U)
2999/*! SP6 - Supervisor Protect
3000 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3001 * 0b1..This peripheral requires supervisor privilege level for accesses.
3002 */
3003#define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
3004#define AIPS_PACRL_TP5_MASK (0x100U)
3005#define AIPS_PACRL_TP5_SHIFT (8U)
3006/*! TP5 - Trusted Protect
3007 * 0b0..Accesses from an untrusted master are allowed.
3008 * 0b1..Accesses from an untrusted master are not allowed.
3009 */
3010#define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
3011#define AIPS_PACRL_WP5_MASK (0x200U)
3012#define AIPS_PACRL_WP5_SHIFT (9U)
3013/*! WP5 - Write Protect
3014 * 0b0..This peripheral allows write accesses.
3015 * 0b1..This peripheral is write protected.
3016 */
3017#define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
3018#define AIPS_PACRL_SP5_MASK (0x400U)
3019#define AIPS_PACRL_SP5_SHIFT (10U)
3020/*! SP5 - Supervisor Protect
3021 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3022 * 0b1..This peripheral requires supervisor privilege level for accesses.
3023 */
3024#define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
3025#define AIPS_PACRL_TP4_MASK (0x1000U)
3026#define AIPS_PACRL_TP4_SHIFT (12U)
3027/*! TP4 - Trusted Protect
3028 * 0b0..Accesses from an untrusted master are allowed.
3029 * 0b1..Accesses from an untrusted master are not allowed.
3030 */
3031#define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
3032#define AIPS_PACRL_WP4_MASK (0x2000U)
3033#define AIPS_PACRL_WP4_SHIFT (13U)
3034/*! WP4 - Write Protect
3035 * 0b0..This peripheral allows write accesses.
3036 * 0b1..This peripheral is write protected.
3037 */
3038#define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
3039#define AIPS_PACRL_SP4_MASK (0x4000U)
3040#define AIPS_PACRL_SP4_SHIFT (14U)
3041/*! SP4 - Supervisor Protect
3042 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3043 * 0b1..This peripheral requires supervisor privilege level for accesses.
3044 */
3045#define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
3046#define AIPS_PACRL_TP3_MASK (0x10000U)
3047#define AIPS_PACRL_TP3_SHIFT (16U)
3048/*! TP3 - Trusted Protect
3049 * 0b0..Accesses from an untrusted master are allowed.
3050 * 0b1..Accesses from an untrusted master are not allowed.
3051 */
3052#define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
3053#define AIPS_PACRL_WP3_MASK (0x20000U)
3054#define AIPS_PACRL_WP3_SHIFT (17U)
3055/*! WP3 - Write Protect
3056 * 0b0..This peripheral allows write accesses.
3057 * 0b1..This peripheral is write protected.
3058 */
3059#define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
3060#define AIPS_PACRL_SP3_MASK (0x40000U)
3061#define AIPS_PACRL_SP3_SHIFT (18U)
3062/*! SP3 - Supervisor Protect
3063 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3064 * 0b1..This peripheral requires supervisor privilege level for accesses.
3065 */
3066#define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
3067#define AIPS_PACRL_TP2_MASK (0x100000U)
3068#define AIPS_PACRL_TP2_SHIFT (20U)
3069/*! TP2 - Trusted Protect
3070 * 0b0..Accesses from an untrusted master are allowed.
3071 * 0b1..Accesses from an untrusted master are not allowed.
3072 */
3073#define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
3074#define AIPS_PACRL_WP2_MASK (0x200000U)
3075#define AIPS_PACRL_WP2_SHIFT (21U)
3076/*! WP2 - Write Protect
3077 * 0b0..This peripheral allows write accesses.
3078 * 0b1..This peripheral is write protected.
3079 */
3080#define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
3081#define AIPS_PACRL_SP2_MASK (0x400000U)
3082#define AIPS_PACRL_SP2_SHIFT (22U)
3083/*! SP2 - Supervisor Protect
3084 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3085 * 0b1..This peripheral requires supervisor privilege level for accesses.
3086 */
3087#define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
3088#define AIPS_PACRL_TP1_MASK (0x1000000U)
3089#define AIPS_PACRL_TP1_SHIFT (24U)
3090/*! TP1 - Trusted Protect
3091 * 0b0..Accesses from an untrusted master are allowed.
3092 * 0b1..Accesses from an untrusted master are not allowed.
3093 */
3094#define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
3095#define AIPS_PACRL_WP1_MASK (0x2000000U)
3096#define AIPS_PACRL_WP1_SHIFT (25U)
3097/*! WP1 - Write Protect
3098 * 0b0..This peripheral allows write accesses.
3099 * 0b1..This peripheral is write protected.
3100 */
3101#define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
3102#define AIPS_PACRL_SP1_MASK (0x4000000U)
3103#define AIPS_PACRL_SP1_SHIFT (26U)
3104/*! SP1 - Supervisor Protect
3105 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3106 * 0b1..This peripheral requires supervisor privilege level for accesses.
3107 */
3108#define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
3109#define AIPS_PACRL_TP0_MASK (0x10000000U)
3110#define AIPS_PACRL_TP0_SHIFT (28U)
3111/*! TP0 - Trusted Protect
3112 * 0b0..Accesses from an untrusted master are allowed.
3113 * 0b1..Accesses from an untrusted master are not allowed.
3114 */
3115#define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
3116#define AIPS_PACRL_WP0_MASK (0x20000000U)
3117#define AIPS_PACRL_WP0_SHIFT (29U)
3118/*! WP0 - Write Protect
3119 * 0b0..This peripheral allows write accesses.
3120 * 0b1..This peripheral is write protected.
3121 */
3122#define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
3123#define AIPS_PACRL_SP0_MASK (0x40000000U)
3124#define AIPS_PACRL_SP0_SHIFT (30U)
3125/*! SP0 - Supervisor Protect
3126 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3127 * 0b1..This peripheral requires supervisor privilege level for accesses.
3128 */
3129#define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
3130/*! @} */
3131
3132/*! @name PACRM - Peripheral Access Control Register */
3133/*! @{ */
3134#define AIPS_PACRM_TP7_MASK (0x1U)
3135#define AIPS_PACRM_TP7_SHIFT (0U)
3136/*! TP7 - Trusted Protect
3137 * 0b0..Accesses from an untrusted master are allowed.
3138 * 0b1..Accesses from an untrusted master are not allowed.
3139 */
3140#define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
3141#define AIPS_PACRM_WP7_MASK (0x2U)
3142#define AIPS_PACRM_WP7_SHIFT (1U)
3143/*! WP7 - Write Protect
3144 * 0b0..This peripheral allows write accesses.
3145 * 0b1..This peripheral is write protected.
3146 */
3147#define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
3148#define AIPS_PACRM_SP7_MASK (0x4U)
3149#define AIPS_PACRM_SP7_SHIFT (2U)
3150/*! SP7 - Supervisor Protect
3151 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3152 * 0b1..This peripheral requires supervisor privilege level for accesses.
3153 */
3154#define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
3155#define AIPS_PACRM_TP6_MASK (0x10U)
3156#define AIPS_PACRM_TP6_SHIFT (4U)
3157/*! TP6 - Trusted Protect
3158 * 0b0..Accesses from an untrusted master are allowed.
3159 * 0b1..Accesses from an untrusted master are not allowed.
3160 */
3161#define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
3162#define AIPS_PACRM_WP6_MASK (0x20U)
3163#define AIPS_PACRM_WP6_SHIFT (5U)
3164/*! WP6 - Write Protect
3165 * 0b0..This peripheral allows write accesses.
3166 * 0b1..This peripheral is write protected.
3167 */
3168#define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
3169#define AIPS_PACRM_SP6_MASK (0x40U)
3170#define AIPS_PACRM_SP6_SHIFT (6U)
3171/*! SP6 - Supervisor Protect
3172 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3173 * 0b1..This peripheral requires supervisor privilege level for accesses.
3174 */
3175#define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
3176#define AIPS_PACRM_TP5_MASK (0x100U)
3177#define AIPS_PACRM_TP5_SHIFT (8U)
3178/*! TP5 - Trusted Protect
3179 * 0b0..Accesses from an untrusted master are allowed.
3180 * 0b1..Accesses from an untrusted master are not allowed.
3181 */
3182#define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
3183#define AIPS_PACRM_WP5_MASK (0x200U)
3184#define AIPS_PACRM_WP5_SHIFT (9U)
3185/*! WP5 - Write Protect
3186 * 0b0..This peripheral allows write accesses.
3187 * 0b1..This peripheral is write protected.
3188 */
3189#define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
3190#define AIPS_PACRM_SP5_MASK (0x400U)
3191#define AIPS_PACRM_SP5_SHIFT (10U)
3192/*! SP5 - Supervisor Protect
3193 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3194 * 0b1..This peripheral requires supervisor privilege level for accesses.
3195 */
3196#define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
3197#define AIPS_PACRM_TP4_MASK (0x1000U)
3198#define AIPS_PACRM_TP4_SHIFT (12U)
3199/*! TP4 - Trusted Protect
3200 * 0b0..Accesses from an untrusted master are allowed.
3201 * 0b1..Accesses from an untrusted master are not allowed.
3202 */
3203#define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
3204#define AIPS_PACRM_WP4_MASK (0x2000U)
3205#define AIPS_PACRM_WP4_SHIFT (13U)
3206/*! WP4 - Write Protect
3207 * 0b0..This peripheral allows write accesses.
3208 * 0b1..This peripheral is write protected.
3209 */
3210#define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
3211#define AIPS_PACRM_SP4_MASK (0x4000U)
3212#define AIPS_PACRM_SP4_SHIFT (14U)
3213/*! SP4 - Supervisor Protect
3214 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3215 * 0b1..This peripheral requires supervisor privilege level for accesses.
3216 */
3217#define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
3218#define AIPS_PACRM_TP3_MASK (0x10000U)
3219#define AIPS_PACRM_TP3_SHIFT (16U)
3220/*! TP3 - Trusted Protect
3221 * 0b0..Accesses from an untrusted master are allowed.
3222 * 0b1..Accesses from an untrusted master are not allowed.
3223 */
3224#define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
3225#define AIPS_PACRM_WP3_MASK (0x20000U)
3226#define AIPS_PACRM_WP3_SHIFT (17U)
3227/*! WP3 - Write Protect
3228 * 0b0..This peripheral allows write accesses.
3229 * 0b1..This peripheral is write protected.
3230 */
3231#define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
3232#define AIPS_PACRM_SP3_MASK (0x40000U)
3233#define AIPS_PACRM_SP3_SHIFT (18U)
3234/*! SP3 - Supervisor Protect
3235 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3236 * 0b1..This peripheral requires supervisor privilege level for accesses.
3237 */
3238#define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
3239#define AIPS_PACRM_TP2_MASK (0x100000U)
3240#define AIPS_PACRM_TP2_SHIFT (20U)
3241/*! TP2 - Trusted Protect
3242 * 0b0..Accesses from an untrusted master are allowed.
3243 * 0b1..Accesses from an untrusted master are not allowed.
3244 */
3245#define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
3246#define AIPS_PACRM_WP2_MASK (0x200000U)
3247#define AIPS_PACRM_WP2_SHIFT (21U)
3248/*! WP2 - Write Protect
3249 * 0b0..This peripheral allows write accesses.
3250 * 0b1..This peripheral is write protected.
3251 */
3252#define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
3253#define AIPS_PACRM_SP2_MASK (0x400000U)
3254#define AIPS_PACRM_SP2_SHIFT (22U)
3255/*! SP2 - Supervisor Protect
3256 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3257 * 0b1..This peripheral requires supervisor privilege level for accesses.
3258 */
3259#define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
3260#define AIPS_PACRM_TP1_MASK (0x1000000U)
3261#define AIPS_PACRM_TP1_SHIFT (24U)
3262/*! TP1 - Trusted Protect
3263 * 0b0..Accesses from an untrusted master are allowed.
3264 * 0b1..Accesses from an untrusted master are not allowed.
3265 */
3266#define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
3267#define AIPS_PACRM_WP1_MASK (0x2000000U)
3268#define AIPS_PACRM_WP1_SHIFT (25U)
3269/*! WP1 - Write Protect
3270 * 0b0..This peripheral allows write accesses.
3271 * 0b1..This peripheral is write protected.
3272 */
3273#define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
3274#define AIPS_PACRM_SP1_MASK (0x4000000U)
3275#define AIPS_PACRM_SP1_SHIFT (26U)
3276/*! SP1 - Supervisor Protect
3277 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3278 * 0b1..This peripheral requires supervisor privilege level for accesses.
3279 */
3280#define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
3281#define AIPS_PACRM_TP0_MASK (0x10000000U)
3282#define AIPS_PACRM_TP0_SHIFT (28U)
3283/*! TP0 - Trusted Protect
3284 * 0b0..Accesses from an untrusted master are allowed.
3285 * 0b1..Accesses from an untrusted master are not allowed.
3286 */
3287#define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
3288#define AIPS_PACRM_WP0_MASK (0x20000000U)
3289#define AIPS_PACRM_WP0_SHIFT (29U)
3290/*! WP0 - Write Protect
3291 * 0b0..This peripheral allows write accesses.
3292 * 0b1..This peripheral is write protected.
3293 */
3294#define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
3295#define AIPS_PACRM_SP0_MASK (0x40000000U)
3296#define AIPS_PACRM_SP0_SHIFT (30U)
3297/*! SP0 - Supervisor Protect
3298 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3299 * 0b1..This peripheral requires supervisor privilege level for accesses.
3300 */
3301#define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
3302/*! @} */
3303
3304/*! @name PACRN - Peripheral Access Control Register */
3305/*! @{ */
3306#define AIPS_PACRN_TP7_MASK (0x1U)
3307#define AIPS_PACRN_TP7_SHIFT (0U)
3308/*! TP7 - Trusted Protect
3309 * 0b0..Accesses from an untrusted master are allowed.
3310 * 0b1..Accesses from an untrusted master are not allowed.
3311 */
3312#define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
3313#define AIPS_PACRN_WP7_MASK (0x2U)
3314#define AIPS_PACRN_WP7_SHIFT (1U)
3315/*! WP7 - Write Protect
3316 * 0b0..This peripheral allows write accesses.
3317 * 0b1..This peripheral is write protected.
3318 */
3319#define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
3320#define AIPS_PACRN_SP7_MASK (0x4U)
3321#define AIPS_PACRN_SP7_SHIFT (2U)
3322/*! SP7 - Supervisor Protect
3323 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3324 * 0b1..This peripheral requires supervisor privilege level for accesses.
3325 */
3326#define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
3327#define AIPS_PACRN_TP6_MASK (0x10U)
3328#define AIPS_PACRN_TP6_SHIFT (4U)
3329/*! TP6 - Trusted Protect
3330 * 0b0..Accesses from an untrusted master are allowed.
3331 * 0b1..Accesses from an untrusted master are not allowed.
3332 */
3333#define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
3334#define AIPS_PACRN_WP6_MASK (0x20U)
3335#define AIPS_PACRN_WP6_SHIFT (5U)
3336/*! WP6 - Write Protect
3337 * 0b0..This peripheral allows write accesses.
3338 * 0b1..This peripheral is write protected.
3339 */
3340#define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
3341#define AIPS_PACRN_SP6_MASK (0x40U)
3342#define AIPS_PACRN_SP6_SHIFT (6U)
3343/*! SP6 - Supervisor Protect
3344 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3345 * 0b1..This peripheral requires supervisor privilege level for accesses.
3346 */
3347#define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
3348#define AIPS_PACRN_TP5_MASK (0x100U)
3349#define AIPS_PACRN_TP5_SHIFT (8U)
3350/*! TP5 - Trusted Protect
3351 * 0b0..Accesses from an untrusted master are allowed.
3352 * 0b1..Accesses from an untrusted master are not allowed.
3353 */
3354#define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
3355#define AIPS_PACRN_WP5_MASK (0x200U)
3356#define AIPS_PACRN_WP5_SHIFT (9U)
3357/*! WP5 - Write Protect
3358 * 0b0..This peripheral allows write accesses.
3359 * 0b1..This peripheral is write protected.
3360 */
3361#define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
3362#define AIPS_PACRN_SP5_MASK (0x400U)
3363#define AIPS_PACRN_SP5_SHIFT (10U)
3364/*! SP5 - Supervisor Protect
3365 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3366 * 0b1..This peripheral requires supervisor privilege level for accesses.
3367 */
3368#define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
3369#define AIPS_PACRN_TP4_MASK (0x1000U)
3370#define AIPS_PACRN_TP4_SHIFT (12U)
3371/*! TP4 - Trusted Protect
3372 * 0b0..Accesses from an untrusted master are allowed.
3373 * 0b1..Accesses from an untrusted master are not allowed.
3374 */
3375#define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
3376#define AIPS_PACRN_WP4_MASK (0x2000U)
3377#define AIPS_PACRN_WP4_SHIFT (13U)
3378/*! WP4 - Write Protect
3379 * 0b0..This peripheral allows write accesses.
3380 * 0b1..This peripheral is write protected.
3381 */
3382#define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
3383#define AIPS_PACRN_SP4_MASK (0x4000U)
3384#define AIPS_PACRN_SP4_SHIFT (14U)
3385/*! SP4 - Supervisor Protect
3386 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3387 * 0b1..This peripheral requires supervisor privilege level for accesses.
3388 */
3389#define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
3390#define AIPS_PACRN_TP3_MASK (0x10000U)
3391#define AIPS_PACRN_TP3_SHIFT (16U)
3392/*! TP3 - Trusted Protect
3393 * 0b0..Accesses from an untrusted master are allowed.
3394 * 0b1..Accesses from an untrusted master are not allowed.
3395 */
3396#define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
3397#define AIPS_PACRN_WP3_MASK (0x20000U)
3398#define AIPS_PACRN_WP3_SHIFT (17U)
3399/*! WP3 - Write Protect
3400 * 0b0..This peripheral allows write accesses.
3401 * 0b1..This peripheral is write protected.
3402 */
3403#define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
3404#define AIPS_PACRN_SP3_MASK (0x40000U)
3405#define AIPS_PACRN_SP3_SHIFT (18U)
3406/*! SP3 - Supervisor Protect
3407 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3408 * 0b1..This peripheral requires supervisor privilege level for accesses.
3409 */
3410#define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
3411#define AIPS_PACRN_TP2_MASK (0x100000U)
3412#define AIPS_PACRN_TP2_SHIFT (20U)
3413/*! TP2 - Trusted Protect
3414 * 0b0..Accesses from an untrusted master are allowed.
3415 * 0b1..Accesses from an untrusted master are not allowed.
3416 */
3417#define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
3418#define AIPS_PACRN_WP2_MASK (0x200000U)
3419#define AIPS_PACRN_WP2_SHIFT (21U)
3420/*! WP2 - Write Protect
3421 * 0b0..This peripheral allows write accesses.
3422 * 0b1..This peripheral is write protected.
3423 */
3424#define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
3425#define AIPS_PACRN_SP2_MASK (0x400000U)
3426#define AIPS_PACRN_SP2_SHIFT (22U)
3427/*! SP2 - Supervisor Protect
3428 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3429 * 0b1..This peripheral requires supervisor privilege level for accesses.
3430 */
3431#define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
3432#define AIPS_PACRN_TP1_MASK (0x1000000U)
3433#define AIPS_PACRN_TP1_SHIFT (24U)
3434/*! TP1 - Trusted Protect
3435 * 0b0..Accesses from an untrusted master are allowed.
3436 * 0b1..Accesses from an untrusted master are not allowed.
3437 */
3438#define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
3439#define AIPS_PACRN_WP1_MASK (0x2000000U)
3440#define AIPS_PACRN_WP1_SHIFT (25U)
3441/*! WP1 - Write Protect
3442 * 0b0..This peripheral allows write accesses.
3443 * 0b1..This peripheral is write protected.
3444 */
3445#define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
3446#define AIPS_PACRN_SP1_MASK (0x4000000U)
3447#define AIPS_PACRN_SP1_SHIFT (26U)
3448/*! SP1 - Supervisor Protect
3449 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3450 * 0b1..This peripheral requires supervisor privilege level for accesses.
3451 */
3452#define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
3453#define AIPS_PACRN_TP0_MASK (0x10000000U)
3454#define AIPS_PACRN_TP0_SHIFT (28U)
3455/*! TP0 - Trusted Protect
3456 * 0b0..Accesses from an untrusted master are allowed.
3457 * 0b1..Accesses from an untrusted master are not allowed.
3458 */
3459#define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
3460#define AIPS_PACRN_WP0_MASK (0x20000000U)
3461#define AIPS_PACRN_WP0_SHIFT (29U)
3462/*! WP0 - Write Protect
3463 * 0b0..This peripheral allows write accesses.
3464 * 0b1..This peripheral is write protected.
3465 */
3466#define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
3467#define AIPS_PACRN_SP0_MASK (0x40000000U)
3468#define AIPS_PACRN_SP0_SHIFT (30U)
3469/*! SP0 - Supervisor Protect
3470 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3471 * 0b1..This peripheral requires supervisor privilege level for accesses.
3472 */
3473#define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
3474/*! @} */
3475
3476/*! @name PACRO - Peripheral Access Control Register */
3477/*! @{ */
3478#define AIPS_PACRO_TP7_MASK (0x1U)
3479#define AIPS_PACRO_TP7_SHIFT (0U)
3480/*! TP7 - Trusted Protect
3481 * 0b0..Accesses from an untrusted master are allowed.
3482 * 0b1..Accesses from an untrusted master are not allowed.
3483 */
3484#define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
3485#define AIPS_PACRO_WP7_MASK (0x2U)
3486#define AIPS_PACRO_WP7_SHIFT (1U)
3487/*! WP7 - Write Protect
3488 * 0b0..This peripheral allows write accesses.
3489 * 0b1..This peripheral is write protected.
3490 */
3491#define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
3492#define AIPS_PACRO_SP7_MASK (0x4U)
3493#define AIPS_PACRO_SP7_SHIFT (2U)
3494/*! SP7 - Supervisor Protect
3495 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3496 * 0b1..This peripheral requires supervisor privilege level for accesses.
3497 */
3498#define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
3499#define AIPS_PACRO_TP6_MASK (0x10U)
3500#define AIPS_PACRO_TP6_SHIFT (4U)
3501/*! TP6 - Trusted Protect
3502 * 0b0..Accesses from an untrusted master are allowed.
3503 * 0b1..Accesses from an untrusted master are not allowed.
3504 */
3505#define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
3506#define AIPS_PACRO_WP6_MASK (0x20U)
3507#define AIPS_PACRO_WP6_SHIFT (5U)
3508/*! WP6 - Write Protect
3509 * 0b0..This peripheral allows write accesses.
3510 * 0b1..This peripheral is write protected.
3511 */
3512#define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
3513#define AIPS_PACRO_SP6_MASK (0x40U)
3514#define AIPS_PACRO_SP6_SHIFT (6U)
3515/*! SP6 - Supervisor Protect
3516 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3517 * 0b1..This peripheral requires supervisor privilege level for accesses.
3518 */
3519#define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
3520#define AIPS_PACRO_TP5_MASK (0x100U)
3521#define AIPS_PACRO_TP5_SHIFT (8U)
3522/*! TP5 - Trusted Protect
3523 * 0b0..Accesses from an untrusted master are allowed.
3524 * 0b1..Accesses from an untrusted master are not allowed.
3525 */
3526#define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
3527#define AIPS_PACRO_WP5_MASK (0x200U)
3528#define AIPS_PACRO_WP5_SHIFT (9U)
3529/*! WP5 - Write Protect
3530 * 0b0..This peripheral allows write accesses.
3531 * 0b1..This peripheral is write protected.
3532 */
3533#define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
3534#define AIPS_PACRO_SP5_MASK (0x400U)
3535#define AIPS_PACRO_SP5_SHIFT (10U)
3536/*! SP5 - Supervisor Protect
3537 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3538 * 0b1..This peripheral requires supervisor privilege level for accesses.
3539 */
3540#define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
3541#define AIPS_PACRO_TP4_MASK (0x1000U)
3542#define AIPS_PACRO_TP4_SHIFT (12U)
3543/*! TP4 - Trusted Protect
3544 * 0b0..Accesses from an untrusted master are allowed.
3545 * 0b1..Accesses from an untrusted master are not allowed.
3546 */
3547#define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
3548#define AIPS_PACRO_WP4_MASK (0x2000U)
3549#define AIPS_PACRO_WP4_SHIFT (13U)
3550/*! WP4 - Write Protect
3551 * 0b0..This peripheral allows write accesses.
3552 * 0b1..This peripheral is write protected.
3553 */
3554#define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
3555#define AIPS_PACRO_SP4_MASK (0x4000U)
3556#define AIPS_PACRO_SP4_SHIFT (14U)
3557/*! SP4 - Supervisor Protect
3558 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3559 * 0b1..This peripheral requires supervisor privilege level for accesses.
3560 */
3561#define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
3562#define AIPS_PACRO_TP3_MASK (0x10000U)
3563#define AIPS_PACRO_TP3_SHIFT (16U)
3564/*! TP3 - Trusted Protect
3565 * 0b0..Accesses from an untrusted master are allowed.
3566 * 0b1..Accesses from an untrusted master are not allowed.
3567 */
3568#define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
3569#define AIPS_PACRO_WP3_MASK (0x20000U)
3570#define AIPS_PACRO_WP3_SHIFT (17U)
3571/*! WP3 - Write Protect
3572 * 0b0..This peripheral allows write accesses.
3573 * 0b1..This peripheral is write protected.
3574 */
3575#define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
3576#define AIPS_PACRO_SP3_MASK (0x40000U)
3577#define AIPS_PACRO_SP3_SHIFT (18U)
3578/*! SP3 - Supervisor Protect
3579 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3580 * 0b1..This peripheral requires supervisor privilege level for accesses.
3581 */
3582#define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
3583#define AIPS_PACRO_TP2_MASK (0x100000U)
3584#define AIPS_PACRO_TP2_SHIFT (20U)
3585/*! TP2 - Trusted Protect
3586 * 0b0..Accesses from an untrusted master are allowed.
3587 * 0b1..Accesses from an untrusted master are not allowed.
3588 */
3589#define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
3590#define AIPS_PACRO_WP2_MASK (0x200000U)
3591#define AIPS_PACRO_WP2_SHIFT (21U)
3592/*! WP2 - Write Protect
3593 * 0b0..This peripheral allows write accesses.
3594 * 0b1..This peripheral is write protected.
3595 */
3596#define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
3597#define AIPS_PACRO_SP2_MASK (0x400000U)
3598#define AIPS_PACRO_SP2_SHIFT (22U)
3599/*! SP2 - Supervisor Protect
3600 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3601 * 0b1..This peripheral requires supervisor privilege level for accesses.
3602 */
3603#define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
3604#define AIPS_PACRO_TP1_MASK (0x1000000U)
3605#define AIPS_PACRO_TP1_SHIFT (24U)
3606/*! TP1 - Trusted Protect
3607 * 0b0..Accesses from an untrusted master are allowed.
3608 * 0b1..Accesses from an untrusted master are not allowed.
3609 */
3610#define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
3611#define AIPS_PACRO_WP1_MASK (0x2000000U)
3612#define AIPS_PACRO_WP1_SHIFT (25U)
3613/*! WP1 - Write Protect
3614 * 0b0..This peripheral allows write accesses.
3615 * 0b1..This peripheral is write protected.
3616 */
3617#define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
3618#define AIPS_PACRO_SP1_MASK (0x4000000U)
3619#define AIPS_PACRO_SP1_SHIFT (26U)
3620/*! SP1 - Supervisor Protect
3621 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3622 * 0b1..This peripheral requires supervisor privilege level for accesses.
3623 */
3624#define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
3625#define AIPS_PACRO_TP0_MASK (0x10000000U)
3626#define AIPS_PACRO_TP0_SHIFT (28U)
3627/*! TP0 - Trusted Protect
3628 * 0b0..Accesses from an untrusted master are allowed.
3629 * 0b1..Accesses from an untrusted master are not allowed.
3630 */
3631#define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
3632#define AIPS_PACRO_WP0_MASK (0x20000000U)
3633#define AIPS_PACRO_WP0_SHIFT (29U)
3634/*! WP0 - Write Protect
3635 * 0b0..This peripheral allows write accesses.
3636 * 0b1..This peripheral is write protected.
3637 */
3638#define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
3639#define AIPS_PACRO_SP0_MASK (0x40000000U)
3640#define AIPS_PACRO_SP0_SHIFT (30U)
3641/*! SP0 - Supervisor Protect
3642 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3643 * 0b1..This peripheral requires supervisor privilege level for accesses.
3644 */
3645#define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
3646/*! @} */
3647
3648/*! @name PACRP - Peripheral Access Control Register */
3649/*! @{ */
3650#define AIPS_PACRP_TP7_MASK (0x1U)
3651#define AIPS_PACRP_TP7_SHIFT (0U)
3652/*! TP7 - Trusted Protect
3653 * 0b0..Accesses from an untrusted master are allowed.
3654 * 0b1..Accesses from an untrusted master are not allowed.
3655 */
3656#define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
3657#define AIPS_PACRP_WP7_MASK (0x2U)
3658#define AIPS_PACRP_WP7_SHIFT (1U)
3659/*! WP7 - Write Protect
3660 * 0b0..This peripheral allows write accesses.
3661 * 0b1..This peripheral is write protected.
3662 */
3663#define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
3664#define AIPS_PACRP_SP7_MASK (0x4U)
3665#define AIPS_PACRP_SP7_SHIFT (2U)
3666/*! SP7 - Supervisor Protect
3667 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3668 * 0b1..This peripheral requires supervisor privilege level for accesses.
3669 */
3670#define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
3671#define AIPS_PACRP_TP6_MASK (0x10U)
3672#define AIPS_PACRP_TP6_SHIFT (4U)
3673/*! TP6 - Trusted Protect
3674 * 0b0..Accesses from an untrusted master are allowed.
3675 * 0b1..Accesses from an untrusted master are not allowed.
3676 */
3677#define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
3678#define AIPS_PACRP_WP6_MASK (0x20U)
3679#define AIPS_PACRP_WP6_SHIFT (5U)
3680/*! WP6 - Write Protect
3681 * 0b0..This peripheral allows write accesses.
3682 * 0b1..This peripheral is write protected.
3683 */
3684#define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
3685#define AIPS_PACRP_SP6_MASK (0x40U)
3686#define AIPS_PACRP_SP6_SHIFT (6U)
3687/*! SP6 - Supervisor Protect
3688 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3689 * 0b1..This peripheral requires supervisor privilege level for accesses.
3690 */
3691#define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
3692#define AIPS_PACRP_TP5_MASK (0x100U)
3693#define AIPS_PACRP_TP5_SHIFT (8U)
3694/*! TP5 - Trusted Protect
3695 * 0b0..Accesses from an untrusted master are allowed.
3696 * 0b1..Accesses from an untrusted master are not allowed.
3697 */
3698#define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
3699#define AIPS_PACRP_WP5_MASK (0x200U)
3700#define AIPS_PACRP_WP5_SHIFT (9U)
3701/*! WP5 - Write Protect
3702 * 0b0..This peripheral allows write accesses.
3703 * 0b1..This peripheral is write protected.
3704 */
3705#define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
3706#define AIPS_PACRP_SP5_MASK (0x400U)
3707#define AIPS_PACRP_SP5_SHIFT (10U)
3708/*! SP5 - Supervisor Protect
3709 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3710 * 0b1..This peripheral requires supervisor privilege level for accesses.
3711 */
3712#define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
3713#define AIPS_PACRP_TP4_MASK (0x1000U)
3714#define AIPS_PACRP_TP4_SHIFT (12U)
3715/*! TP4 - Trusted Protect
3716 * 0b0..Accesses from an untrusted master are allowed.
3717 * 0b1..Accesses from an untrusted master are not allowed.
3718 */
3719#define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
3720#define AIPS_PACRP_WP4_MASK (0x2000U)
3721#define AIPS_PACRP_WP4_SHIFT (13U)
3722/*! WP4 - Write Protect
3723 * 0b0..This peripheral allows write accesses.
3724 * 0b1..This peripheral is write protected.
3725 */
3726#define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
3727#define AIPS_PACRP_SP4_MASK (0x4000U)
3728#define AIPS_PACRP_SP4_SHIFT (14U)
3729/*! SP4 - Supervisor Protect
3730 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3731 * 0b1..This peripheral requires supervisor privilege level for accesses.
3732 */
3733#define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
3734#define AIPS_PACRP_TP3_MASK (0x10000U)
3735#define AIPS_PACRP_TP3_SHIFT (16U)
3736/*! TP3 - Trusted Protect
3737 * 0b0..Accesses from an untrusted master are allowed.
3738 * 0b1..Accesses from an untrusted master are not allowed.
3739 */
3740#define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
3741#define AIPS_PACRP_WP3_MASK (0x20000U)
3742#define AIPS_PACRP_WP3_SHIFT (17U)
3743/*! WP3 - Write Protect
3744 * 0b0..This peripheral allows write accesses.
3745 * 0b1..This peripheral is write protected.
3746 */
3747#define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
3748#define AIPS_PACRP_SP3_MASK (0x40000U)
3749#define AIPS_PACRP_SP3_SHIFT (18U)
3750/*! SP3 - Supervisor Protect
3751 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3752 * 0b1..This peripheral requires supervisor privilege level for accesses.
3753 */
3754#define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
3755#define AIPS_PACRP_TP2_MASK (0x100000U)
3756#define AIPS_PACRP_TP2_SHIFT (20U)
3757/*! TP2 - Trusted Protect
3758 * 0b0..Accesses from an untrusted master are allowed.
3759 * 0b1..Accesses from an untrusted master are not allowed.
3760 */
3761#define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
3762#define AIPS_PACRP_WP2_MASK (0x200000U)
3763#define AIPS_PACRP_WP2_SHIFT (21U)
3764/*! WP2 - Write Protect
3765 * 0b0..This peripheral allows write accesses.
3766 * 0b1..This peripheral is write protected.
3767 */
3768#define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
3769#define AIPS_PACRP_SP2_MASK (0x400000U)
3770#define AIPS_PACRP_SP2_SHIFT (22U)
3771/*! SP2 - Supervisor Protect
3772 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3773 * 0b1..This peripheral requires supervisor privilege level for accesses.
3774 */
3775#define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
3776#define AIPS_PACRP_TP1_MASK (0x1000000U)
3777#define AIPS_PACRP_TP1_SHIFT (24U)
3778/*! TP1 - Trusted Protect
3779 * 0b0..Accesses from an untrusted master are allowed.
3780 * 0b1..Accesses from an untrusted master are not allowed.
3781 */
3782#define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
3783#define AIPS_PACRP_WP1_MASK (0x2000000U)
3784#define AIPS_PACRP_WP1_SHIFT (25U)
3785/*! WP1 - Write Protect
3786 * 0b0..This peripheral allows write accesses.
3787 * 0b1..This peripheral is write protected.
3788 */
3789#define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
3790#define AIPS_PACRP_SP1_MASK (0x4000000U)
3791#define AIPS_PACRP_SP1_SHIFT (26U)
3792/*! SP1 - Supervisor Protect
3793 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3794 * 0b1..This peripheral requires supervisor privilege level for accesses.
3795 */
3796#define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
3797#define AIPS_PACRP_TP0_MASK (0x10000000U)
3798#define AIPS_PACRP_TP0_SHIFT (28U)
3799/*! TP0 - Trusted Protect
3800 * 0b0..Accesses from an untrusted master are allowed.
3801 * 0b1..Accesses from an untrusted master are not allowed.
3802 */
3803#define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
3804#define AIPS_PACRP_WP0_MASK (0x20000000U)
3805#define AIPS_PACRP_WP0_SHIFT (29U)
3806/*! WP0 - Write Protect
3807 * 0b0..This peripheral allows write accesses.
3808 * 0b1..This peripheral is write protected.
3809 */
3810#define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
3811#define AIPS_PACRP_SP0_MASK (0x40000000U)
3812#define AIPS_PACRP_SP0_SHIFT (30U)
3813/*! SP0 - Supervisor Protect
3814 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3815 * 0b1..This peripheral requires supervisor privilege level for accesses.
3816 */
3817#define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
3818/*! @} */
3819
3820
3821/*!
3822 * @}
3823 */ /* end of group AIPS_Register_Masks */
3824
3825
3826/* AIPS - Peripheral instance base addresses */
3827/** Peripheral AIPS0 base address */
3828#define AIPS0_BASE (0x40000000u)
3829/** Peripheral AIPS0 base pointer */
3830#define AIPS0 ((AIPS_Type *)AIPS0_BASE)
3831/** Peripheral AIPS1 base address */
3832#define AIPS1_BASE (0x40080000u)
3833/** Peripheral AIPS1 base pointer */
3834#define AIPS1 ((AIPS_Type *)AIPS1_BASE)
3835/** Array initializer of AIPS peripheral base addresses */
3836#define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
3837/** Array initializer of AIPS peripheral base pointers */
3838#define AIPS_BASE_PTRS { AIPS0, AIPS1 }
3839
3840/*!
3841 * @}
3842 */ /* end of group AIPS_Peripheral_Access_Layer */
3843
3844
3845/* ----------------------------------------------------------------------------
3846 -- AXBS Peripheral Access Layer
3847 ---------------------------------------------------------------------------- */
3848
3849/*!
3850 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
3851 * @{
3852 */
3853
3854/** AXBS - Register Layout Typedef */
3855typedef struct {
3856 struct { /* offset: 0x0, array step: 0x100 */
3857 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
3858 uint8_t RESERVED_0[12];
3859 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
3860 uint8_t RESERVED_1[236];
3861 } SLAVE[5];
3862 uint8_t RESERVED_0[768];
3863 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
3864 uint8_t RESERVED_1[252];
3865 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
3866 uint8_t RESERVED_2[252];
3867 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
3868 uint8_t RESERVED_3[252];
3869 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
3870 uint8_t RESERVED_4[252];
3871 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
3872 uint8_t RESERVED_5[252];
3873 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
3874 uint8_t RESERVED_6[252];
3875 __IO uint32_t MGPCR6; /**< Master General Purpose Control Register, offset: 0xE00 */
3876} AXBS_Type;
3877
3878/* ----------------------------------------------------------------------------
3879 -- AXBS Register Masks
3880 ---------------------------------------------------------------------------- */
3881
3882/*!
3883 * @addtogroup AXBS_Register_Masks AXBS Register Masks
3884 * @{
3885 */
3886
3887/*! @name PRS - Priority Registers Slave */
3888/*! @{ */
3889#define AXBS_PRS_M0_MASK (0x7U)
3890#define AXBS_PRS_M0_SHIFT (0U)
3891/*! M0 - Master 0 Priority. Sets the arbitration priority for this port on the associated slave port.
3892 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3893 * 0b001..This master has level 2 priority when accessing the slave port.
3894 * 0b010..This master has level 3 priority when accessing the slave port.
3895 * 0b011..This master has level 4 priority when accessing the slave port.
3896 * 0b100..This master has level 5 priority when accessing the slave port.
3897 * 0b101..This master has level 6 priority when accessing the slave port.
3898 * 0b110..This master has level 7 priority when accessing the slave port.
3899 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3900 */
3901#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
3902#define AXBS_PRS_M1_MASK (0x70U)
3903#define AXBS_PRS_M1_SHIFT (4U)
3904/*! M1 - Master 1 Priority. Sets the arbitration priority for this port on the associated slave port.
3905 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3906 * 0b001..This master has level 2 priority when accessing the slave port.
3907 * 0b010..This master has level 3 priority when accessing the slave port.
3908 * 0b011..This master has level 4 priority when accessing the slave port.
3909 * 0b100..This master has level 5 priority when accessing the slave port.
3910 * 0b101..This master has level 6 priority when accessing the slave port.
3911 * 0b110..This master has level 7 priority when accessing the slave port.
3912 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3913 */
3914#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
3915#define AXBS_PRS_M2_MASK (0x700U)
3916#define AXBS_PRS_M2_SHIFT (8U)
3917/*! M2 - Master 2 Priority. Sets the arbitration priority for this port on the associated slave port.
3918 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3919 * 0b001..This master has level 2 priority when accessing the slave port.
3920 * 0b010..This master has level 3 priority when accessing the slave port.
3921 * 0b011..This master has level 4 priority when accessing the slave port.
3922 * 0b100..This master has level 5 priority when accessing the slave port.
3923 * 0b101..This master has level 6 priority when accessing the slave port.
3924 * 0b110..This master has level 7 priority when accessing the slave port.
3925 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3926 */
3927#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
3928#define AXBS_PRS_M3_MASK (0x7000U)
3929#define AXBS_PRS_M3_SHIFT (12U)
3930/*! M3 - Master 3 Priority. Sets the arbitration priority for this port on the associated slave port.
3931 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3932 * 0b001..This master has level 2 priority when accessing the slave port.
3933 * 0b010..This master has level 3 priority when accessing the slave port.
3934 * 0b011..This master has level 4 priority when accessing the slave port.
3935 * 0b100..This master has level 5 priority when accessing the slave port.
3936 * 0b101..This master has level 6 priority when accessing the slave port.
3937 * 0b110..This master has level 7 priority when accessing the slave port.
3938 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3939 */
3940#define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
3941#define AXBS_PRS_M4_MASK (0x70000U)
3942#define AXBS_PRS_M4_SHIFT (16U)
3943/*! M4 - Master 4 Priority. Sets the arbitration priority for this port on the associated slave port.
3944 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3945 * 0b001..This master has level 2 priority when accessing the slave port.
3946 * 0b010..This master has level 3 priority when accessing the slave port.
3947 * 0b011..This master has level 4 priority when accessing the slave port.
3948 * 0b100..This master has level 5 priority when accessing the slave port.
3949 * 0b101..This master has level 6 priority when accessing the slave port.
3950 * 0b110..This master has level 7 priority when accessing the slave port.
3951 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3952 */
3953#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
3954#define AXBS_PRS_M5_MASK (0x700000U)
3955#define AXBS_PRS_M5_SHIFT (20U)
3956/*! M5 - Master 5 Priority. Sets the arbitration priority for this port on the associated slave port.
3957 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3958 * 0b001..This master has level 2 priority when accessing the slave port.
3959 * 0b010..This master has level 3 priority when accessing the slave port.
3960 * 0b011..This master has level 4 priority when accessing the slave port.
3961 * 0b100..This master has level 5 priority when accessing the slave port.
3962 * 0b101..This master has level 6 priority when accessing the slave port.
3963 * 0b110..This master has level 7 priority when accessing the slave port.
3964 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3965 */
3966#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
3967#define AXBS_PRS_M6_MASK (0x7000000U)
3968#define AXBS_PRS_M6_SHIFT (24U)
3969/*! M6 - Master 6 Priority. Sets the arbitration priority for this port on the associated slave port.
3970 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3971 * 0b001..This master has level 2 priority when accessing the slave port.
3972 * 0b010..This master has level 3 priority when accessing the slave port.
3973 * 0b011..This master has level 4 priority when accessing the slave port.
3974 * 0b100..This master has level 5 priority when accessing the slave port.
3975 * 0b101..This master has level 6 priority when accessing the slave port.
3976 * 0b110..This master has level 7 priority when accessing the slave port.
3977 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3978 */
3979#define AXBS_PRS_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M6_SHIFT)) & AXBS_PRS_M6_MASK)
3980/*! @} */
3981
3982/* The count of AXBS_PRS */
3983#define AXBS_PRS_COUNT (5U)
3984
3985/*! @name CRS - Control Register */
3986/*! @{ */
3987#define AXBS_CRS_PARK_MASK (0x7U)
3988#define AXBS_CRS_PARK_SHIFT (0U)
3989/*! PARK - Park
3990 * 0b000..Park on master port M0
3991 * 0b001..Park on master port M1
3992 * 0b010..Park on master port M2
3993 * 0b011..Park on master port M3
3994 * 0b100..Park on master port M4
3995 * 0b101..Park on master port M5
3996 * 0b110..Park on master port M6
3997 * 0b111..Park on master port M7
3998 */
3999#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
4000#define AXBS_CRS_PCTL_MASK (0x30U)
4001#define AXBS_CRS_PCTL_SHIFT (4U)
4002/*! PCTL - Parking Control
4003 * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field
4004 * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port
4005 * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state
4006 * 0b11..Reserved
4007 */
4008#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
4009#define AXBS_CRS_ARB_MASK (0x300U)
4010#define AXBS_CRS_ARB_SHIFT (8U)
4011/*! ARB - Arbitration Mode
4012 * 0b00..Fixed priority
4013 * 0b01..Round-robin, or rotating, priority
4014 * 0b10..Reserved
4015 * 0b11..Reserved
4016 */
4017#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
4018#define AXBS_CRS_HLP_MASK (0x40000000U)
4019#define AXBS_CRS_HLP_SHIFT (30U)
4020/*! HLP - Halt Low Priority
4021 * 0b0..The low power mode request has the highest priority for arbitration on this slave port
4022 * 0b1..The low power mode request has the lowest initial priority for arbitration on this slave port
4023 */
4024#define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
4025#define AXBS_CRS_RO_MASK (0x80000000U)
4026#define AXBS_CRS_RO_SHIFT (31U)
4027/*! RO - Read Only
4028 * 0b0..The slave port's registers are writeable
4029 * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response.
4030 */
4031#define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
4032/*! @} */
4033
4034/* The count of AXBS_CRS */
4035#define AXBS_CRS_COUNT (5U)
4036
4037/*! @name MGPCR0 - Master General Purpose Control Register */
4038/*! @{ */
4039#define AXBS_MGPCR0_AULB_MASK (0x7U)
4040#define AXBS_MGPCR0_AULB_SHIFT (0U)
4041/*! AULB - Arbitrates On Undefined Length Bursts
4042 * 0b000..No arbitration is allowed during an undefined length burst
4043 * 0b001..Arbitration is allowed at any time during an undefined length burst
4044 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4045 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4046 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4047 * 0b101..Reserved
4048 * 0b110..Reserved
4049 * 0b111..Reserved
4050 */
4051#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
4052/*! @} */
4053
4054/*! @name MGPCR1 - Master General Purpose Control Register */
4055/*! @{ */
4056#define AXBS_MGPCR1_AULB_MASK (0x7U)
4057#define AXBS_MGPCR1_AULB_SHIFT (0U)
4058/*! AULB - Arbitrates On Undefined Length Bursts
4059 * 0b000..No arbitration is allowed during an undefined length burst
4060 * 0b001..Arbitration is allowed at any time during an undefined length burst
4061 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4062 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4063 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4064 * 0b101..Reserved
4065 * 0b110..Reserved
4066 * 0b111..Reserved
4067 */
4068#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
4069/*! @} */
4070
4071/*! @name MGPCR2 - Master General Purpose Control Register */
4072/*! @{ */
4073#define AXBS_MGPCR2_AULB_MASK (0x7U)
4074#define AXBS_MGPCR2_AULB_SHIFT (0U)
4075/*! AULB - Arbitrates On Undefined Length Bursts
4076 * 0b000..No arbitration is allowed during an undefined length burst
4077 * 0b001..Arbitration is allowed at any time during an undefined length burst
4078 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4079 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4080 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4081 * 0b101..Reserved
4082 * 0b110..Reserved
4083 * 0b111..Reserved
4084 */
4085#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
4086/*! @} */
4087
4088/*! @name MGPCR3 - Master General Purpose Control Register */
4089/*! @{ */
4090#define AXBS_MGPCR3_AULB_MASK (0x7U)
4091#define AXBS_MGPCR3_AULB_SHIFT (0U)
4092/*! AULB - Arbitrates On Undefined Length Bursts
4093 * 0b000..No arbitration is allowed during an undefined length burst
4094 * 0b001..Arbitration is allowed at any time during an undefined length burst
4095 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4096 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4097 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4098 * 0b101..Reserved
4099 * 0b110..Reserved
4100 * 0b111..Reserved
4101 */
4102#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
4103/*! @} */
4104
4105/*! @name MGPCR4 - Master General Purpose Control Register */
4106/*! @{ */
4107#define AXBS_MGPCR4_AULB_MASK (0x7U)
4108#define AXBS_MGPCR4_AULB_SHIFT (0U)
4109/*! AULB - Arbitrates On Undefined Length Bursts
4110 * 0b000..No arbitration is allowed during an undefined length burst
4111 * 0b001..Arbitration is allowed at any time during an undefined length burst
4112 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4113 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4114 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4115 * 0b101..Reserved
4116 * 0b110..Reserved
4117 * 0b111..Reserved
4118 */
4119#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
4120/*! @} */
4121
4122/*! @name MGPCR5 - Master General Purpose Control Register */
4123/*! @{ */
4124#define AXBS_MGPCR5_AULB_MASK (0x7U)
4125#define AXBS_MGPCR5_AULB_SHIFT (0U)
4126/*! AULB - Arbitrates On Undefined Length Bursts
4127 * 0b000..No arbitration is allowed during an undefined length burst
4128 * 0b001..Arbitration is allowed at any time during an undefined length burst
4129 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4130 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4131 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4132 * 0b101..Reserved
4133 * 0b110..Reserved
4134 * 0b111..Reserved
4135 */
4136#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
4137/*! @} */
4138
4139/*! @name MGPCR6 - Master General Purpose Control Register */
4140/*! @{ */
4141#define AXBS_MGPCR6_AULB_MASK (0x7U)
4142#define AXBS_MGPCR6_AULB_SHIFT (0U)
4143/*! AULB - Arbitrates On Undefined Length Bursts
4144 * 0b000..No arbitration is allowed during an undefined length burst
4145 * 0b001..Arbitration is allowed at any time during an undefined length burst
4146 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4147 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4148 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4149 * 0b101..Reserved
4150 * 0b110..Reserved
4151 * 0b111..Reserved
4152 */
4153#define AXBS_MGPCR6_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR6_AULB_SHIFT)) & AXBS_MGPCR6_AULB_MASK)
4154/*! @} */
4155
4156
4157/*!
4158 * @}
4159 */ /* end of group AXBS_Register_Masks */
4160
4161
4162/* AXBS - Peripheral instance base addresses */
4163/** Peripheral AXBS base address */
4164#define AXBS_BASE (0x40004000u)
4165/** Peripheral AXBS base pointer */
4166#define AXBS ((AXBS_Type *)AXBS_BASE)
4167/** Array initializer of AXBS peripheral base addresses */
4168#define AXBS_BASE_ADDRS { AXBS_BASE }
4169/** Array initializer of AXBS peripheral base pointers */
4170#define AXBS_BASE_PTRS { AXBS }
4171
4172/*!
4173 * @}
4174 */ /* end of group AXBS_Peripheral_Access_Layer */
4175
4176
4177/* ----------------------------------------------------------------------------
4178 -- CAN Peripheral Access Layer
4179 ---------------------------------------------------------------------------- */
4180
4181/*!
4182 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
4183 * @{
4184 */
4185
4186/** CAN - Register Layout Typedef */
4187typedef struct {
4188 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
4189 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
4190 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
4191 uint8_t RESERVED_0[4];
4192 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
4193 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
4194 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
4195 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
4196 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
4197 uint8_t RESERVED_1[4];
4198 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
4199 uint8_t RESERVED_2[4];
4200 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
4201 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
4202 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
4203 uint8_t RESERVED_3[8];
4204 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
4205 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
4206 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
4207 uint8_t RESERVED_4[48];
4208 struct { /* offset: 0x80, array step: 0x10 */
4209 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
4210 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
4211 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
4212 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
4213 } MB[16];
4214 uint8_t RESERVED_5[1792];
4215 __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
4216} CAN_Type;
4217
4218/* ----------------------------------------------------------------------------
4219 -- CAN Register Masks
4220 ---------------------------------------------------------------------------- */
4221
4222/*!
4223 * @addtogroup CAN_Register_Masks CAN Register Masks
4224 * @{
4225 */
4226
4227/*! @name MCR - Module Configuration Register */
4228/*! @{ */
4229#define CAN_MCR_MAXMB_MASK (0x7FU)
4230#define CAN_MCR_MAXMB_SHIFT (0U)
4231#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
4232#define CAN_MCR_IDAM_MASK (0x300U)
4233#define CAN_MCR_IDAM_SHIFT (8U)
4234/*! IDAM - ID Acceptance Mode
4235 * 0b00..Format A: One full ID (standard and extended) per ID Filter Table element.
4236 * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element.
4237 * 0b10..Format C: Four partial 8-bit Standard IDs per ID Filter Table element.
4238 * 0b11..Format D: All frames rejected.
4239 */
4240#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
4241#define CAN_MCR_AEN_MASK (0x1000U)
4242#define CAN_MCR_AEN_SHIFT (12U)
4243/*! AEN - Abort Enable
4244 * 0b0..Abort disabled.
4245 * 0b1..Abort enabled.
4246 */
4247#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
4248#define CAN_MCR_LPRIOEN_MASK (0x2000U)
4249#define CAN_MCR_LPRIOEN_SHIFT (13U)
4250/*! LPRIOEN - Local Priority Enable
4251 * 0b0..Local Priority disabled.
4252 * 0b1..Local Priority enabled.
4253 */
4254#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
4255#define CAN_MCR_IRMQ_MASK (0x10000U)
4256#define CAN_MCR_IRMQ_SHIFT (16U)
4257/*! IRMQ - Individual Rx Masking And Queue Enable
4258 * 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY.
4259 * 0b1..Individual Rx masking and queue feature are enabled.
4260 */
4261#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
4262#define CAN_MCR_SRXDIS_MASK (0x20000U)
4263#define CAN_MCR_SRXDIS_SHIFT (17U)
4264/*! SRXDIS - Self Reception Disable
4265 * 0b0..Self reception enabled.
4266 * 0b1..Self reception disabled.
4267 */
4268#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
4269#define CAN_MCR_WAKSRC_MASK (0x80000U)
4270#define CAN_MCR_WAKSRC_SHIFT (19U)
4271/*! WAKSRC - Wake Up Source
4272 * 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
4273 * 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
4274 */
4275#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
4276#define CAN_MCR_LPMACK_MASK (0x100000U)
4277#define CAN_MCR_LPMACK_SHIFT (20U)
4278/*! LPMACK - Low-Power Mode Acknowledge
4279 * 0b0..FlexCAN is not in a low-power mode.
4280 * 0b1..FlexCAN is in a low-power mode.
4281 */
4282#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
4283#define CAN_MCR_WRNEN_MASK (0x200000U)
4284#define CAN_MCR_WRNEN_SHIFT (21U)
4285/*! WRNEN - Warning Interrupt Enable
4286 * 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
4287 * 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
4288 */
4289#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
4290#define CAN_MCR_SLFWAK_MASK (0x400000U)
4291#define CAN_MCR_SLFWAK_SHIFT (22U)
4292/*! SLFWAK - Self Wake Up
4293 * 0b0..FlexCAN Self Wake Up feature is disabled.
4294 * 0b1..FlexCAN Self Wake Up feature is enabled.
4295 */
4296#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
4297#define CAN_MCR_SUPV_MASK (0x800000U)
4298#define CAN_MCR_SUPV_SHIFT (23U)
4299/*! SUPV - Supervisor Mode
4300 * 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses .
4301 * 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location .
4302 */
4303#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
4304#define CAN_MCR_FRZACK_MASK (0x1000000U)
4305#define CAN_MCR_FRZACK_SHIFT (24U)
4306/*! FRZACK - Freeze Mode Acknowledge
4307 * 0b0..FlexCAN not in Freeze mode, prescaler running.
4308 * 0b1..FlexCAN in Freeze mode, prescaler stopped.
4309 */
4310#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
4311#define CAN_MCR_SOFTRST_MASK (0x2000000U)
4312#define CAN_MCR_SOFTRST_SHIFT (25U)
4313/*! SOFTRST - Soft Reset
4314 * 0b0..No reset request.
4315 * 0b1..Resets the registers affected by soft reset.
4316 */
4317#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
4318#define CAN_MCR_WAKMSK_MASK (0x4000000U)
4319#define CAN_MCR_WAKMSK_SHIFT (26U)
4320/*! WAKMSK - Wake Up Interrupt Mask
4321 * 0b0..Wake Up Interrupt is disabled.
4322 * 0b1..Wake Up Interrupt is enabled.
4323 */
4324#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
4325#define CAN_MCR_NOTRDY_MASK (0x8000000U)
4326#define CAN_MCR_NOTRDY_SHIFT (27U)
4327/*! NOTRDY - FlexCAN Not Ready
4328 * 0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode.
4329 * 0b1..FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
4330 */
4331#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
4332#define CAN_MCR_HALT_MASK (0x10000000U)
4333#define CAN_MCR_HALT_SHIFT (28U)
4334/*! HALT - Halt FlexCAN
4335 * 0b0..No Freeze mode request.
4336 * 0b1..Enters Freeze mode if the FRZ bit is asserted.
4337 */
4338#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
4339#define CAN_MCR_RFEN_MASK (0x20000000U)
4340#define CAN_MCR_RFEN_SHIFT (29U)
4341/*! RFEN - Rx FIFO Enable
4342 * 0b0..Rx FIFO not enabled.
4343 * 0b1..Rx FIFO enabled.
4344 */
4345#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
4346#define CAN_MCR_FRZ_MASK (0x40000000U)
4347#define CAN_MCR_FRZ_SHIFT (30U)
4348/*! FRZ - Freeze Enable
4349 * 0b0..Not enabled to enter Freeze mode.
4350 * 0b1..Enabled to enter Freeze mode.
4351 */
4352#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
4353#define CAN_MCR_MDIS_MASK (0x80000000U)
4354#define CAN_MCR_MDIS_SHIFT (31U)
4355/*! MDIS - Module Disable
4356 * 0b0..Enable the FlexCAN module.
4357 * 0b1..Disable the FlexCAN module.
4358 */
4359#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
4360/*! @} */
4361
4362/*! @name CTRL1 - Control 1 register */
4363/*! @{ */
4364#define CAN_CTRL1_PROPSEG_MASK (0x7U)
4365#define CAN_CTRL1_PROPSEG_SHIFT (0U)
4366#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
4367#define CAN_CTRL1_LOM_MASK (0x8U)
4368#define CAN_CTRL1_LOM_SHIFT (3U)
4369/*! LOM - Listen-Only Mode
4370 * 0b0..Listen-Only mode is deactivated.
4371 * 0b1..FlexCAN module operates in Listen-Only mode.
4372 */
4373#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
4374#define CAN_CTRL1_LBUF_MASK (0x10U)
4375#define CAN_CTRL1_LBUF_SHIFT (4U)
4376/*! LBUF - Lowest Buffer Transmitted First
4377 * 0b0..Buffer with highest priority is transmitted first.
4378 * 0b1..Lowest number buffer is transmitted first.
4379 */
4380#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
4381#define CAN_CTRL1_TSYN_MASK (0x20U)
4382#define CAN_CTRL1_TSYN_SHIFT (5U)
4383/*! TSYN - Timer Sync
4384 * 0b0..Timer Sync feature disabled
4385 * 0b1..Timer Sync feature enabled
4386 */
4387#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
4388#define CAN_CTRL1_BOFFREC_MASK (0x40U)
4389#define CAN_CTRL1_BOFFREC_SHIFT (6U)
4390/*! BOFFREC - Bus Off Recovery
4391 * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B.
4392 * 0b1..Automatic recovering from Bus Off state disabled.
4393 */
4394#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
4395#define CAN_CTRL1_SMP_MASK (0x80U)
4396#define CAN_CTRL1_SMP_SHIFT (7U)
4397/*! SMP - CAN Bit Sampling
4398 * 0b0..Just one sample is used to determine the bit value.
4399 * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used.
4400 */
4401#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
4402#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
4403#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
4404/*! RWRNMSK - Rx Warning Interrupt Mask
4405 * 0b0..Rx Warning Interrupt disabled.
4406 * 0b1..Rx Warning Interrupt enabled.
4407 */
4408#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
4409#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
4410#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
4411/*! TWRNMSK - Tx Warning Interrupt Mask
4412 * 0b0..Tx Warning Interrupt disabled.
4413 * 0b1..Tx Warning Interrupt enabled.
4414 */
4415#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
4416#define CAN_CTRL1_LPB_MASK (0x1000U)
4417#define CAN_CTRL1_LPB_SHIFT (12U)
4418/*! LPB - Loop Back Mode
4419 * 0b0..Loop Back disabled.
4420 * 0b1..Loop Back enabled.
4421 */
4422#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
4423#define CAN_CTRL1_CLKSRC_MASK (0x2000U)
4424#define CAN_CTRL1_CLKSRC_SHIFT (13U)
4425/*! CLKSRC - CAN Engine Clock Source
4426 * 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
4427 * 0b1..The CAN engine clock source is the peripheral clock.
4428 */
4429#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
4430#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
4431#define CAN_CTRL1_ERRMSK_SHIFT (14U)
4432/*! ERRMSK - Error Mask
4433 * 0b0..Error interrupt disabled.
4434 * 0b1..Error interrupt enabled.
4435 */
4436#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
4437#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
4438#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
4439/*! BOFFMSK - Bus Off Mask
4440 * 0b0..Bus Off interrupt disabled.
4441 * 0b1..Bus Off interrupt enabled.
4442 */
4443#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
4444#define CAN_CTRL1_PSEG2_MASK (0x70000U)
4445#define CAN_CTRL1_PSEG2_SHIFT (16U)
4446#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
4447#define CAN_CTRL1_PSEG1_MASK (0x380000U)
4448#define CAN_CTRL1_PSEG1_SHIFT (19U)
4449#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
4450#define CAN_CTRL1_RJW_MASK (0xC00000U)
4451#define CAN_CTRL1_RJW_SHIFT (22U)
4452#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
4453#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
4454#define CAN_CTRL1_PRESDIV_SHIFT (24U)
4455#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
4456/*! @} */
4457
4458/*! @name TIMER - Free Running Timer */
4459/*! @{ */
4460#define CAN_TIMER_TIMER_MASK (0xFFFFU)
4461#define CAN_TIMER_TIMER_SHIFT (0U)
4462#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
4463/*! @} */
4464
4465/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
4466/*! @{ */
4467#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
4468#define CAN_RXMGMASK_MG_SHIFT (0U)
4469/*! MG - Rx Mailboxes Global Mask Bits
4470 * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care."
4471 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.
4472 */
4473#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
4474/*! @} */
4475
4476/*! @name RX14MASK - Rx 14 Mask register */
4477/*! @{ */
4478#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
4479#define CAN_RX14MASK_RX14M_SHIFT (0U)
4480/*! RX14M - Rx Buffer 14 Mask Bits
4481 * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care."
4482 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.
4483 */
4484#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
4485/*! @} */
4486
4487/*! @name RX15MASK - Rx 15 Mask register */
4488/*! @{ */
4489#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
4490#define CAN_RX15MASK_RX15M_SHIFT (0U)
4491/*! RX15M - Rx Buffer 15 Mask Bits
4492 * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care."
4493 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.
4494 */
4495#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
4496/*! @} */
4497
4498/*! @name ECR - Error Counter */
4499/*! @{ */
4500#define CAN_ECR_TXERRCNT_MASK (0xFFU)
4501#define CAN_ECR_TXERRCNT_SHIFT (0U)
4502#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
4503#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
4504#define CAN_ECR_RXERRCNT_SHIFT (8U)
4505#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
4506/*! @} */
4507
4508/*! @name ESR1 - Error and Status 1 register */
4509/*! @{ */
4510#define CAN_ESR1_WAKINT_MASK (0x1U)
4511#define CAN_ESR1_WAKINT_SHIFT (0U)
4512/*! WAKINT - Wake-Up Interrupt
4513 * 0b0..No such occurrence.
4514 * 0b1..Indicates a recessive to dominant transition was received on the CAN bus.
4515 */
4516#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
4517#define CAN_ESR1_ERRINT_MASK (0x2U)
4518#define CAN_ESR1_ERRINT_SHIFT (1U)
4519/*! ERRINT - Error Interrupt
4520 * 0b0..No such occurrence.
4521 * 0b1..Indicates setting of any Error Bit in the Error and Status Register.
4522 */
4523#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
4524#define CAN_ESR1_BOFFINT_MASK (0x4U)
4525#define CAN_ESR1_BOFFINT_SHIFT (2U)
4526/*! BOFFINT - Bus Off Interrupt
4527 * 0b0..No such occurrence.
4528 * 0b1..FlexCAN module entered Bus Off state.
4529 */
4530#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
4531#define CAN_ESR1_RX_MASK (0x8U)
4532#define CAN_ESR1_RX_SHIFT (3U)
4533/*! RX - FlexCAN In Reception
4534 * 0b0..FlexCAN is not receiving a message.
4535 * 0b1..FlexCAN is receiving a message.
4536 */
4537#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
4538#define CAN_ESR1_FLTCONF_MASK (0x30U)
4539#define CAN_ESR1_FLTCONF_SHIFT (4U)
4540/*! FLTCONF - Fault Confinement State
4541 * 0b00..Error Active
4542 * 0b01..Error Passive
4543 * 0b1x..Bus Off
4544 */
4545#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
4546#define CAN_ESR1_TX_MASK (0x40U)
4547#define CAN_ESR1_TX_SHIFT (6U)
4548/*! TX - FlexCAN In Transmission
4549 * 0b0..FlexCAN is not transmitting a message.
4550 * 0b1..FlexCAN is transmitting a message.
4551 */
4552#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
4553#define CAN_ESR1_IDLE_MASK (0x80U)
4554#define CAN_ESR1_IDLE_SHIFT (7U)
4555/*! IDLE
4556 * 0b0..No such occurrence.
4557 * 0b1..CAN bus is now IDLE.
4558 */
4559#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
4560#define CAN_ESR1_RXWRN_MASK (0x100U)
4561#define CAN_ESR1_RXWRN_SHIFT (8U)
4562/*! RXWRN - Rx Error Warning
4563 * 0b0..No such occurrence.
4564 * 0b1..RXERRCNT is greater than or equal to 96.
4565 */
4566#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
4567#define CAN_ESR1_TXWRN_MASK (0x200U)
4568#define CAN_ESR1_TXWRN_SHIFT (9U)
4569/*! TXWRN - TX Error Warning
4570 * 0b0..No such occurrence.
4571 * 0b1..TXERRCNT is greater than or equal to 96.
4572 */
4573#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
4574#define CAN_ESR1_STFERR_MASK (0x400U)
4575#define CAN_ESR1_STFERR_SHIFT (10U)
4576/*! STFERR - Stuffing Error
4577 * 0b0..No such occurrence.
4578 * 0b1..A Stuffing Error occurred since last read of this register.
4579 */
4580#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
4581#define CAN_ESR1_FRMERR_MASK (0x800U)
4582#define CAN_ESR1_FRMERR_SHIFT (11U)
4583/*! FRMERR - Form Error
4584 * 0b0..No such occurrence.
4585 * 0b1..A Form Error occurred since last read of this register.
4586 */
4587#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
4588#define CAN_ESR1_CRCERR_MASK (0x1000U)
4589#define CAN_ESR1_CRCERR_SHIFT (12U)
4590/*! CRCERR - Cyclic Redundancy Check Error
4591 * 0b0..No such occurrence.
4592 * 0b1..A CRC error occurred since last read of this register.
4593 */
4594#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
4595#define CAN_ESR1_ACKERR_MASK (0x2000U)
4596#define CAN_ESR1_ACKERR_SHIFT (13U)
4597/*! ACKERR - Acknowledge Error
4598 * 0b0..No such occurrence.
4599 * 0b1..An ACK error occurred since last read of this register.
4600 */
4601#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
4602#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
4603#define CAN_ESR1_BIT0ERR_SHIFT (14U)
4604/*! BIT0ERR - Bit0 Error
4605 * 0b0..No such occurrence.
4606 * 0b1..At least one bit sent as dominant is received as recessive.
4607 */
4608#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
4609#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
4610#define CAN_ESR1_BIT1ERR_SHIFT (15U)
4611/*! BIT1ERR - Bit1 Error
4612 * 0b0..No such occurrence.
4613 * 0b1..At least one bit sent as recessive is received as dominant.
4614 */
4615#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
4616#define CAN_ESR1_RWRNINT_MASK (0x10000U)
4617#define CAN_ESR1_RWRNINT_SHIFT (16U)
4618/*! RWRNINT - Rx Warning Interrupt Flag
4619 * 0b0..No such occurrence.
4620 * 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.
4621 */
4622#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
4623#define CAN_ESR1_TWRNINT_MASK (0x20000U)
4624#define CAN_ESR1_TWRNINT_SHIFT (17U)
4625/*! TWRNINT - Tx Warning Interrupt Flag
4626 * 0b0..No such occurrence.
4627 * 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.
4628 */
4629#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
4630#define CAN_ESR1_SYNCH_MASK (0x40000U)
4631#define CAN_ESR1_SYNCH_SHIFT (18U)
4632/*! SYNCH - CAN Synchronization Status
4633 * 0b0..FlexCAN is not synchronized to the CAN bus.
4634 * 0b1..FlexCAN is synchronized to the CAN bus.
4635 */
4636#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
4637/*! @} */
4638
4639/*! @name IMASK1 - Interrupt Masks 1 register */
4640/*! @{ */
4641#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
4642#define CAN_IMASK1_BUFLM_SHIFT (0U)
4643/*! BUFLM - Buffer MB i Mask
4644 * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled.
4645 * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled.
4646 */
4647#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
4648/*! @} */
4649
4650/*! @name IFLAG1 - Interrupt Flags 1 register */
4651/*! @{ */
4652#define CAN_IFLAG1_BUF0I_MASK (0x1U)
4653#define CAN_IFLAG1_BUF0I_SHIFT (0U)
4654/*! BUF0I - Buffer MB0 Interrupt Or "reserved"
4655 * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
4656 * 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
4657 */
4658#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
4659#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
4660#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
4661/*! BUF4TO1I - Buffer MB i Interrupt Or "reserved"
4662 * 0b0000..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
4663 * 0b0001..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
4664 */
4665#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
4666#define CAN_IFLAG1_BUF5I_MASK (0x20U)
4667#define CAN_IFLAG1_BUF5I_SHIFT (5U)
4668/*! BUF5I - Buffer MB5 Interrupt Or "Frames available in Rx FIFO"
4669 * 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
4670 * 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1
4671 */
4672#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
4673#define CAN_IFLAG1_BUF6I_MASK (0x40U)
4674#define CAN_IFLAG1_BUF6I_SHIFT (6U)
4675/*! BUF6I - Buffer MB6 Interrupt Or "Rx FIFO Warning"
4676 * 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
4677 * 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1
4678 */
4679#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
4680#define CAN_IFLAG1_BUF7I_MASK (0x80U)
4681#define CAN_IFLAG1_BUF7I_SHIFT (7U)
4682/*! BUF7I - Buffer MB7 Interrupt Or "Rx FIFO Overflow"
4683 * 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
4684 * 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1
4685 */
4686#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
4687#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
4688#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
4689/*! BUF31TO8I - Buffer MBi Interrupt
4690 * 0b000000000000000000000000..The corresponding buffer has no occurrence of successfully completed transmission or reception.
4691 * 0b000000000000000000000001..The corresponding buffer has successfully completed transmission or reception.
4692 */
4693#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
4694/*! @} */
4695
4696/*! @name CTRL2 - Control 2 register */
4697/*! @{ */
4698#define CAN_CTRL2_EACEN_MASK (0x10000U)
4699#define CAN_CTRL2_EACEN_SHIFT (16U)
4700/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
4701 * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
4702 * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply.
4703 */
4704#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
4705#define CAN_CTRL2_RRS_MASK (0x20000U)
4706#define CAN_CTRL2_RRS_SHIFT (17U)
4707/*! RRS - Remote Request Storing
4708 * 0b0..Remote Response Frame is generated.
4709 * 0b1..Remote Request Frame is stored.
4710 */
4711#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
4712#define CAN_CTRL2_MRP_MASK (0x40000U)
4713#define CAN_CTRL2_MRP_SHIFT (18U)
4714/*! MRP - Mailboxes Reception Priority
4715 * 0b0..Matching starts from Rx FIFO and continues on Mailboxes.
4716 * 0b1..Matching starts from Mailboxes and continues on Rx FIFO.
4717 */
4718#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
4719#define CAN_CTRL2_TASD_MASK (0xF80000U)
4720#define CAN_CTRL2_TASD_SHIFT (19U)
4721#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
4722#define CAN_CTRL2_RFFN_MASK (0xF000000U)
4723#define CAN_CTRL2_RFFN_SHIFT (24U)
4724#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
4725#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
4726#define CAN_CTRL2_WRMFRZ_SHIFT (28U)
4727/*! WRMFRZ - Write-Access To Memory In Freeze Mode
4728 * 0b0..Maintain the write access restrictions.
4729 * 0b1..Enable unrestricted write access to FlexCAN memory.
4730 */
4731#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
4732/*! @} */
4733
4734/*! @name ESR2 - Error and Status 2 register */
4735/*! @{ */
4736#define CAN_ESR2_IMB_MASK (0x2000U)
4737#define CAN_ESR2_IMB_SHIFT (13U)
4738/*! IMB - Inactive Mailbox
4739 * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
4740 * 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.
4741 */
4742#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
4743#define CAN_ESR2_VPS_MASK (0x4000U)
4744#define CAN_ESR2_VPS_SHIFT (14U)
4745/*! VPS - Valid Priority Status
4746 * 0b0..Contents of IMB and LPTM are invalid.
4747 * 0b1..Contents of IMB and LPTM are valid.
4748 */
4749#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
4750#define CAN_ESR2_LPTM_MASK (0x7F0000U)
4751#define CAN_ESR2_LPTM_SHIFT (16U)
4752#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
4753/*! @} */
4754
4755/*! @name CRCR - CRC Register */
4756/*! @{ */
4757#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
4758#define CAN_CRCR_TXCRC_SHIFT (0U)
4759#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
4760#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
4761#define CAN_CRCR_MBCRC_SHIFT (16U)
4762#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
4763/*! @} */
4764
4765/*! @name RXFGMASK - Rx FIFO Global Mask register */
4766/*! @{ */
4767#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
4768#define CAN_RXFGMASK_FGM_SHIFT (0U)
4769/*! FGM - Rx FIFO Global Mask Bits
4770 * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care."
4771 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.
4772 */
4773#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
4774/*! @} */
4775
4776/*! @name RXFIR - Rx FIFO Information Register */
4777/*! @{ */
4778#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
4779#define CAN_RXFIR_IDHIT_SHIFT (0U)
4780#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
4781/*! @} */
4782
4783/*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */
4784/*! @{ */
4785#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
4786#define CAN_CS_TIME_STAMP_SHIFT (0U)
4787#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
4788#define CAN_CS_DLC_MASK (0xF0000U)
4789#define CAN_CS_DLC_SHIFT (16U)
4790#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
4791#define CAN_CS_RTR_MASK (0x100000U)
4792#define CAN_CS_RTR_SHIFT (20U)
4793#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
4794#define CAN_CS_IDE_MASK (0x200000U)
4795#define CAN_CS_IDE_SHIFT (21U)
4796#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
4797#define CAN_CS_SRR_MASK (0x400000U)
4798#define CAN_CS_SRR_SHIFT (22U)
4799#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
4800#define CAN_CS_CODE_MASK (0xF000000U)
4801#define CAN_CS_CODE_SHIFT (24U)
4802#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
4803/*! @} */
4804
4805/* The count of CAN_CS */
4806#define CAN_CS_COUNT (16U)
4807
4808/*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */
4809/*! @{ */
4810#define CAN_ID_EXT_MASK (0x3FFFFU)
4811#define CAN_ID_EXT_SHIFT (0U)
4812#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
4813#define CAN_ID_STD_MASK (0x1FFC0000U)
4814#define CAN_ID_STD_SHIFT (18U)
4815#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
4816#define CAN_ID_PRIO_MASK (0xE0000000U)
4817#define CAN_ID_PRIO_SHIFT (29U)
4818#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
4819/*! @} */
4820
4821/* The count of CAN_ID */
4822#define CAN_ID_COUNT (16U)
4823
4824/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */
4825/*! @{ */
4826#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
4827#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
4828#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
4829#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
4830#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
4831#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
4832#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
4833#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
4834#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
4835#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
4836#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
4837#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
4838/*! @} */
4839
4840/* The count of CAN_WORD0 */
4841#define CAN_WORD0_COUNT (16U)
4842
4843/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */
4844/*! @{ */
4845#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
4846#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
4847#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
4848#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
4849#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
4850#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
4851#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
4852#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
4853#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
4854#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
4855#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
4856#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
4857/*! @} */
4858
4859/* The count of CAN_WORD1 */
4860#define CAN_WORD1_COUNT (16U)
4861
4862/*! @name RXIMR - Rx Individual Mask Registers */
4863/*! @{ */
4864#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
4865#define CAN_RXIMR_MI_SHIFT (0U)
4866/*! MI - Individual Mask Bits
4867 * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care."
4868 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.
4869 */
4870#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
4871/*! @} */
4872
4873/* The count of CAN_RXIMR */
4874#define CAN_RXIMR_COUNT (16U)
4875
4876
4877/*!
4878 * @}
4879 */ /* end of group CAN_Register_Masks */
4880
4881
4882/* CAN - Peripheral instance base addresses */
4883/** Peripheral CAN0 base address */
4884#define CAN0_BASE (0x40024000u)
4885/** Peripheral CAN0 base pointer */
4886#define CAN0 ((CAN_Type *)CAN0_BASE)
4887/** Peripheral CAN1 base address */
4888#define CAN1_BASE (0x400A4000u)
4889/** Peripheral CAN1 base pointer */
4890#define CAN1 ((CAN_Type *)CAN1_BASE)
4891/** Array initializer of CAN peripheral base addresses */
4892#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
4893/** Array initializer of CAN peripheral base pointers */
4894#define CAN_BASE_PTRS { CAN0, CAN1 }
4895/** Interrupt vectors for the CAN peripheral type */
4896#define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn, CAN1_Rx_Warning_IRQn }
4897#define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn, CAN1_Tx_Warning_IRQn }
4898#define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn, CAN1_Wake_Up_IRQn }
4899#define CAN_Error_IRQS { CAN0_Error_IRQn, CAN1_Error_IRQn }
4900#define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn, CAN1_Bus_Off_IRQn }
4901#define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn, CAN1_ORed_Message_buffer_IRQn }
4902
4903/*!
4904 * @}
4905 */ /* end of group CAN_Peripheral_Access_Layer */
4906
4907
4908/* ----------------------------------------------------------------------------
4909 -- CAU Peripheral Access Layer
4910 ---------------------------------------------------------------------------- */
4911
4912/*!
4913 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
4914 * @{
4915 */
4916
4917/** CAU - Register Layout Typedef */
4918typedef struct {
4919 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
4920 uint8_t RESERVED_0[2048];
4921 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
4922 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
4923 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
4924 uint8_t RESERVED_1[20];
4925 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
4926 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
4927 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
4928 uint8_t RESERVED_2[20];
4929 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
4930 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
4931 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
4932 uint8_t RESERVED_3[20];
4933 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
4934 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
4935 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
4936 uint8_t RESERVED_4[84];
4937 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
4938 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
4939 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
4940 uint8_t RESERVED_5[20];
4941 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
4942 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
4943 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
4944 uint8_t RESERVED_6[276];
4945 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
4946 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
4947 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
4948 uint8_t RESERVED_7[20];
4949 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
4950 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
4951 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
4952} CAU_Type;
4953
4954/* ----------------------------------------------------------------------------
4955 -- CAU Register Masks
4956 ---------------------------------------------------------------------------- */
4957
4958/*!
4959 * @addtogroup CAU_Register_Masks CAU Register Masks
4960 * @{
4961 */
4962
4963/*! @name DIRECT - Direct access register 0..Direct access register 15 */
4964/*! @{ */
4965#define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
4966#define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
4967#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
4968#define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
4969#define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
4970#define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
4971#define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
4972#define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
4973#define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
4974#define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
4975#define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
4976#define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
4977#define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
4978#define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
4979#define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
4980#define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
4981#define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
4982#define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
4983#define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
4984#define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
4985#define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
4986#define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
4987#define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
4988#define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
4989#define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
4990#define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
4991#define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
4992#define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
4993#define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
4994#define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
4995#define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
4996#define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
4997#define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
4998#define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
4999#define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
5000#define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
5001#define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
5002#define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
5003#define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
5004#define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
5005#define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
5006#define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
5007#define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
5008#define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
5009#define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
5010#define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
5011#define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
5012#define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
5013/*! @} */
5014
5015/* The count of CAU_DIRECT */
5016#define CAU_DIRECT_COUNT (16U)
5017
5018/*! @name LDR_CASR - Status register - Load Register command */
5019/*! @{ */
5020#define CAU_LDR_CASR_IC_MASK (0x1U)
5021#define CAU_LDR_CASR_IC_SHIFT (0U)
5022/*! IC
5023 * 0b0..No illegal commands issued
5024 * 0b1..Illegal command issued
5025 */
5026#define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
5027#define CAU_LDR_CASR_DPE_MASK (0x2U)
5028#define CAU_LDR_CASR_DPE_SHIFT (1U)
5029/*! DPE
5030 * 0b0..No error detected
5031 * 0b1..DES key parity error detected
5032 */
5033#define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
5034#define CAU_LDR_CASR_VER_MASK (0xF0000000U)
5035#define CAU_LDR_CASR_VER_SHIFT (28U)
5036/*! VER - CAU version
5037 * 0b0001..Initial CAU version
5038 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
5039 */
5040#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
5041/*! @} */
5042
5043/*! @name LDR_CAA - Accumulator register - Load Register command */
5044/*! @{ */
5045#define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
5046#define CAU_LDR_CAA_ACC_SHIFT (0U)
5047#define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
5048/*! @} */
5049
5050/*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */
5051/*! @{ */
5052#define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
5053#define CAU_LDR_CA_CA0_SHIFT (0U)
5054#define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
5055#define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
5056#define CAU_LDR_CA_CA1_SHIFT (0U)
5057#define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
5058#define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
5059#define CAU_LDR_CA_CA2_SHIFT (0U)
5060#define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
5061#define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
5062#define CAU_LDR_CA_CA3_SHIFT (0U)
5063#define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
5064#define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
5065#define CAU_LDR_CA_CA4_SHIFT (0U)
5066#define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
5067#define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
5068#define CAU_LDR_CA_CA5_SHIFT (0U)
5069#define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
5070#define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
5071#define CAU_LDR_CA_CA6_SHIFT (0U)
5072#define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
5073#define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
5074#define CAU_LDR_CA_CA7_SHIFT (0U)
5075#define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
5076#define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
5077#define CAU_LDR_CA_CA8_SHIFT (0U)
5078#define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
5079/*! @} */
5080
5081/* The count of CAU_LDR_CA */
5082#define CAU_LDR_CA_COUNT (9U)
5083
5084/*! @name STR_CASR - Status register - Store Register command */
5085/*! @{ */
5086#define CAU_STR_CASR_IC_MASK (0x1U)
5087#define CAU_STR_CASR_IC_SHIFT (0U)
5088/*! IC
5089 * 0b0..No illegal commands issued
5090 * 0b1..Illegal command issued
5091 */
5092#define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
5093#define CAU_STR_CASR_DPE_MASK (0x2U)
5094#define CAU_STR_CASR_DPE_SHIFT (1U)
5095/*! DPE
5096 * 0b0..No error detected
5097 * 0b1..DES key parity error detected
5098 */
5099#define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
5100#define CAU_STR_CASR_VER_MASK (0xF0000000U)
5101#define CAU_STR_CASR_VER_SHIFT (28U)
5102/*! VER - CAU version
5103 * 0b0001..Initial CAU version
5104 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
5105 */
5106#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
5107/*! @} */
5108
5109/*! @name STR_CAA - Accumulator register - Store Register command */
5110/*! @{ */
5111#define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
5112#define CAU_STR_CAA_ACC_SHIFT (0U)
5113#define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
5114/*! @} */
5115
5116/*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */
5117/*! @{ */
5118#define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
5119#define CAU_STR_CA_CA0_SHIFT (0U)
5120#define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
5121#define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
5122#define CAU_STR_CA_CA1_SHIFT (0U)
5123#define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
5124#define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
5125#define CAU_STR_CA_CA2_SHIFT (0U)
5126#define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
5127#define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
5128#define CAU_STR_CA_CA3_SHIFT (0U)
5129#define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
5130#define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
5131#define CAU_STR_CA_CA4_SHIFT (0U)
5132#define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
5133#define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
5134#define CAU_STR_CA_CA5_SHIFT (0U)
5135#define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
5136#define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
5137#define CAU_STR_CA_CA6_SHIFT (0U)
5138#define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
5139#define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
5140#define CAU_STR_CA_CA7_SHIFT (0U)
5141#define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
5142#define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
5143#define CAU_STR_CA_CA8_SHIFT (0U)
5144#define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
5145/*! @} */
5146
5147/* The count of CAU_STR_CA */
5148#define CAU_STR_CA_COUNT (9U)
5149
5150/*! @name ADR_CASR - Status register - Add Register command */
5151/*! @{ */
5152#define CAU_ADR_CASR_IC_MASK (0x1U)
5153#define CAU_ADR_CASR_IC_SHIFT (0U)
5154/*! IC
5155 * 0b0..No illegal commands issued
5156 * 0b1..Illegal command issued
5157 */
5158#define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
5159#define CAU_ADR_CASR_DPE_MASK (0x2U)
5160#define CAU_ADR_CASR_DPE_SHIFT (1U)
5161/*! DPE
5162 * 0b0..No error detected
5163 * 0b1..DES key parity error detected
5164 */
5165#define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
5166#define CAU_ADR_CASR_VER_MASK (0xF0000000U)
5167#define CAU_ADR_CASR_VER_SHIFT (28U)
5168/*! VER - CAU version
5169 * 0b0001..Initial CAU version
5170 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
5171 */
5172#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
5173/*! @} */
5174
5175/*! @name ADR_CAA - Accumulator register - Add to register command */
5176/*! @{ */
5177#define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
5178#define CAU_ADR_CAA_ACC_SHIFT (0U)
5179#define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
5180/*! @} */
5181
5182/*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */
5183/*! @{ */
5184#define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
5185#define CAU_ADR_CA_CA0_SHIFT (0U)
5186#define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
5187#define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
5188#define CAU_ADR_CA_CA1_SHIFT (0U)
5189#define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
5190#define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
5191#define CAU_ADR_CA_CA2_SHIFT (0U)
5192#define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
5193#define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
5194#define CAU_ADR_CA_CA3_SHIFT (0U)
5195#define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
5196#define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
5197#define CAU_ADR_CA_CA4_SHIFT (0U)
5198#define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
5199#define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
5200#define CAU_ADR_CA_CA5_SHIFT (0U)
5201#define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
5202#define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
5203#define CAU_ADR_CA_CA6_SHIFT (0U)
5204#define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
5205#define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
5206#define CAU_ADR_CA_CA7_SHIFT (0U)
5207#define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
5208#define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
5209#define CAU_ADR_CA_CA8_SHIFT (0U)
5210#define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
5211/*! @} */
5212
5213/* The count of CAU_ADR_CA */
5214#define CAU_ADR_CA_COUNT (9U)
5215
5216/*! @name RADR_CASR - Status register - Reverse and Add to Register command */
5217/*! @{ */
5218#define CAU_RADR_CASR_IC_MASK (0x1U)
5219#define CAU_RADR_CASR_IC_SHIFT (0U)
5220/*! IC
5221 * 0b0..No illegal commands issued
5222 * 0b1..Illegal command issued
5223 */
5224#define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
5225#define CAU_RADR_CASR_DPE_MASK (0x2U)
5226#define CAU_RADR_CASR_DPE_SHIFT (1U)
5227/*! DPE
5228 * 0b0..No error detected
5229 * 0b1..DES key parity error detected
5230 */
5231#define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
5232#define CAU_RADR_CASR_VER_MASK (0xF0000000U)
5233#define CAU_RADR_CASR_VER_SHIFT (28U)
5234/*! VER - CAU version
5235 * 0b0001..Initial CAU version
5236 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
5237 */
5238#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
5239/*! @} */
5240
5241/*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
5242/*! @{ */
5243#define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
5244#define CAU_RADR_CAA_ACC_SHIFT (0U)
5245#define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
5246/*! @} */
5247
5248/*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */
5249/*! @{ */
5250#define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
5251#define CAU_RADR_CA_CA0_SHIFT (0U)
5252#define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
5253#define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
5254#define CAU_RADR_CA_CA1_SHIFT (0U)
5255#define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
5256#define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
5257#define CAU_RADR_CA_CA2_SHIFT (0U)
5258#define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
5259#define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
5260#define CAU_RADR_CA_CA3_SHIFT (0U)
5261#define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
5262#define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
5263#define CAU_RADR_CA_CA4_SHIFT (0U)
5264#define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
5265#define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
5266#define CAU_RADR_CA_CA5_SHIFT (0U)
5267#define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
5268#define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
5269#define CAU_RADR_CA_CA6_SHIFT (0U)
5270#define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
5271#define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
5272#define CAU_RADR_CA_CA7_SHIFT (0U)
5273#define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
5274#define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
5275#define CAU_RADR_CA_CA8_SHIFT (0U)
5276#define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
5277/*! @} */
5278
5279/* The count of CAU_RADR_CA */
5280#define CAU_RADR_CA_COUNT (9U)
5281
5282/*! @name XOR_CASR - Status register - Exclusive Or command */
5283/*! @{ */
5284#define CAU_XOR_CASR_IC_MASK (0x1U)
5285#define CAU_XOR_CASR_IC_SHIFT (0U)
5286/*! IC
5287 * 0b0..No illegal commands issued
5288 * 0b1..Illegal command issued
5289 */
5290#define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
5291#define CAU_XOR_CASR_DPE_MASK (0x2U)
5292#define CAU_XOR_CASR_DPE_SHIFT (1U)
5293/*! DPE
5294 * 0b0..No error detected
5295 * 0b1..DES key parity error detected
5296 */
5297#define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
5298#define CAU_XOR_CASR_VER_MASK (0xF0000000U)
5299#define CAU_XOR_CASR_VER_SHIFT (28U)
5300/*! VER - CAU version
5301 * 0b0001..Initial CAU version
5302 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
5303 */
5304#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
5305/*! @} */
5306
5307/*! @name XOR_CAA - Accumulator register - Exclusive Or command */
5308/*! @{ */
5309#define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
5310#define CAU_XOR_CAA_ACC_SHIFT (0U)
5311#define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
5312/*! @} */
5313
5314/*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */
5315/*! @{ */
5316#define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
5317#define CAU_XOR_CA_CA0_SHIFT (0U)
5318#define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
5319#define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
5320#define CAU_XOR_CA_CA1_SHIFT (0U)
5321#define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
5322#define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
5323#define CAU_XOR_CA_CA2_SHIFT (0U)
5324#define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
5325#define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
5326#define CAU_XOR_CA_CA3_SHIFT (0U)
5327#define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
5328#define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
5329#define CAU_XOR_CA_CA4_SHIFT (0U)
5330#define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
5331#define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
5332#define CAU_XOR_CA_CA5_SHIFT (0U)
5333#define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
5334#define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
5335#define CAU_XOR_CA_CA6_SHIFT (0U)
5336#define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
5337#define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
5338#define CAU_XOR_CA_CA7_SHIFT (0U)
5339#define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
5340#define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
5341#define CAU_XOR_CA_CA8_SHIFT (0U)
5342#define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
5343/*! @} */
5344
5345/* The count of CAU_XOR_CA */
5346#define CAU_XOR_CA_COUNT (9U)
5347
5348/*! @name ROTL_CASR - Status register - Rotate Left command */
5349/*! @{ */
5350#define CAU_ROTL_CASR_IC_MASK (0x1U)
5351#define CAU_ROTL_CASR_IC_SHIFT (0U)
5352/*! IC
5353 * 0b0..No illegal commands issued
5354 * 0b1..Illegal command issued
5355 */
5356#define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
5357#define CAU_ROTL_CASR_DPE_MASK (0x2U)
5358#define CAU_ROTL_CASR_DPE_SHIFT (1U)
5359/*! DPE
5360 * 0b0..No error detected
5361 * 0b1..DES key parity error detected
5362 */
5363#define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
5364#define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
5365#define CAU_ROTL_CASR_VER_SHIFT (28U)
5366/*! VER - CAU version
5367 * 0b0001..Initial CAU version
5368 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
5369 */
5370#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
5371/*! @} */
5372
5373/*! @name ROTL_CAA - Accumulator register - Rotate Left command */
5374/*! @{ */
5375#define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
5376#define CAU_ROTL_CAA_ACC_SHIFT (0U)
5377#define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
5378/*! @} */
5379
5380/*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */
5381/*! @{ */
5382#define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
5383#define CAU_ROTL_CA_CA0_SHIFT (0U)
5384#define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
5385#define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
5386#define CAU_ROTL_CA_CA1_SHIFT (0U)
5387#define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
5388#define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
5389#define CAU_ROTL_CA_CA2_SHIFT (0U)
5390#define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
5391#define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
5392#define CAU_ROTL_CA_CA3_SHIFT (0U)
5393#define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
5394#define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
5395#define CAU_ROTL_CA_CA4_SHIFT (0U)
5396#define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
5397#define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
5398#define CAU_ROTL_CA_CA5_SHIFT (0U)
5399#define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
5400#define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
5401#define CAU_ROTL_CA_CA6_SHIFT (0U)
5402#define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
5403#define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
5404#define CAU_ROTL_CA_CA7_SHIFT (0U)
5405#define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
5406#define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
5407#define CAU_ROTL_CA_CA8_SHIFT (0U)
5408#define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
5409/*! @} */
5410
5411/* The count of CAU_ROTL_CA */
5412#define CAU_ROTL_CA_COUNT (9U)
5413
5414/*! @name AESC_CASR - Status register - AES Column Operation command */
5415/*! @{ */
5416#define CAU_AESC_CASR_IC_MASK (0x1U)
5417#define CAU_AESC_CASR_IC_SHIFT (0U)
5418/*! IC
5419 * 0b0..No illegal commands issued
5420 * 0b1..Illegal command issued
5421 */
5422#define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
5423#define CAU_AESC_CASR_DPE_MASK (0x2U)
5424#define CAU_AESC_CASR_DPE_SHIFT (1U)
5425/*! DPE
5426 * 0b0..No error detected
5427 * 0b1..DES key parity error detected
5428 */
5429#define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
5430#define CAU_AESC_CASR_VER_MASK (0xF0000000U)
5431#define CAU_AESC_CASR_VER_SHIFT (28U)
5432/*! VER - CAU version
5433 * 0b0001..Initial CAU version
5434 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
5435 */
5436#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
5437/*! @} */
5438
5439/*! @name AESC_CAA - Accumulator register - AES Column Operation command */
5440/*! @{ */
5441#define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
5442#define CAU_AESC_CAA_ACC_SHIFT (0U)
5443#define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
5444/*! @} */
5445
5446/*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */
5447/*! @{ */
5448#define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
5449#define CAU_AESC_CA_CA0_SHIFT (0U)
5450#define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
5451#define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
5452#define CAU_AESC_CA_CA1_SHIFT (0U)
5453#define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
5454#define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
5455#define CAU_AESC_CA_CA2_SHIFT (0U)
5456#define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
5457#define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
5458#define CAU_AESC_CA_CA3_SHIFT (0U)
5459#define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
5460#define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
5461#define CAU_AESC_CA_CA4_SHIFT (0U)
5462#define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
5463#define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
5464#define CAU_AESC_CA_CA5_SHIFT (0U)
5465#define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
5466#define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
5467#define CAU_AESC_CA_CA6_SHIFT (0U)
5468#define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
5469#define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
5470#define CAU_AESC_CA_CA7_SHIFT (0U)
5471#define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
5472#define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
5473#define CAU_AESC_CA_CA8_SHIFT (0U)
5474#define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
5475/*! @} */
5476
5477/* The count of CAU_AESC_CA */
5478#define CAU_AESC_CA_COUNT (9U)
5479
5480/*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
5481/*! @{ */
5482#define CAU_AESIC_CASR_IC_MASK (0x1U)
5483#define CAU_AESIC_CASR_IC_SHIFT (0U)
5484/*! IC
5485 * 0b0..No illegal commands issued
5486 * 0b1..Illegal command issued
5487 */
5488#define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
5489#define CAU_AESIC_CASR_DPE_MASK (0x2U)
5490#define CAU_AESIC_CASR_DPE_SHIFT (1U)
5491/*! DPE
5492 * 0b0..No error detected
5493 * 0b1..DES key parity error detected
5494 */
5495#define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
5496#define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
5497#define CAU_AESIC_CASR_VER_SHIFT (28U)
5498/*! VER - CAU version
5499 * 0b0001..Initial CAU version
5500 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
5501 */
5502#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
5503/*! @} */
5504
5505/*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */
5506/*! @{ */
5507#define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
5508#define CAU_AESIC_CAA_ACC_SHIFT (0U)
5509#define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
5510/*! @} */
5511
5512/*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */
5513/*! @{ */
5514#define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
5515#define CAU_AESIC_CA_CA0_SHIFT (0U)
5516#define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
5517#define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
5518#define CAU_AESIC_CA_CA1_SHIFT (0U)
5519#define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
5520#define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
5521#define CAU_AESIC_CA_CA2_SHIFT (0U)
5522#define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
5523#define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
5524#define CAU_AESIC_CA_CA3_SHIFT (0U)
5525#define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
5526#define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
5527#define CAU_AESIC_CA_CA4_SHIFT (0U)
5528#define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
5529#define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
5530#define CAU_AESIC_CA_CA5_SHIFT (0U)
5531#define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
5532#define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
5533#define CAU_AESIC_CA_CA6_SHIFT (0U)
5534#define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
5535#define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
5536#define CAU_AESIC_CA_CA7_SHIFT (0U)
5537#define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
5538#define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
5539#define CAU_AESIC_CA_CA8_SHIFT (0U)
5540#define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
5541/*! @} */
5542
5543/* The count of CAU_AESIC_CA */
5544#define CAU_AESIC_CA_COUNT (9U)
5545
5546
5547/*!
5548 * @}
5549 */ /* end of group CAU_Register_Masks */
5550
5551
5552/* CAU - Peripheral instance base addresses */
5553/** Peripheral CAU base address */
5554#define CAU_BASE (0xE0081000u)
5555/** Peripheral CAU base pointer */
5556#define CAU ((CAU_Type *)CAU_BASE)
5557/** Array initializer of CAU peripheral base addresses */
5558#define CAU_BASE_ADDRS { CAU_BASE }
5559/** Array initializer of CAU peripheral base pointers */
5560#define CAU_BASE_PTRS { CAU }
5561
5562/*!
5563 * @}
5564 */ /* end of group CAU_Peripheral_Access_Layer */
5565
5566
5567/* ----------------------------------------------------------------------------
5568 -- CMP Peripheral Access Layer
5569 ---------------------------------------------------------------------------- */
5570
5571/*!
5572 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
5573 * @{
5574 */
5575
5576/** CMP - Register Layout Typedef */
5577typedef struct {
5578 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
5579 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
5580 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
5581 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
5582 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
5583 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
5584} CMP_Type;
5585
5586/* ----------------------------------------------------------------------------
5587 -- CMP Register Masks
5588 ---------------------------------------------------------------------------- */
5589
5590/*!
5591 * @addtogroup CMP_Register_Masks CMP Register Masks
5592 * @{
5593 */
5594
5595/*! @name CR0 - CMP Control Register 0 */
5596/*! @{ */
5597#define CMP_CR0_HYSTCTR_MASK (0x3U)
5598#define CMP_CR0_HYSTCTR_SHIFT (0U)
5599/*! HYSTCTR - Comparator hard block hysteresis control
5600 * 0b00..Level 0
5601 * 0b01..Level 1
5602 * 0b10..Level 2
5603 * 0b11..Level 3
5604 */
5605#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
5606#define CMP_CR0_FILTER_CNT_MASK (0x70U)
5607#define CMP_CR0_FILTER_CNT_SHIFT (4U)
5608/*! FILTER_CNT - Filter Sample Count
5609 * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
5610 * 0b001..One sample must agree. The comparator output is simply sampled.
5611 * 0b010..2 consecutive samples must agree.
5612 * 0b011..3 consecutive samples must agree.
5613 * 0b100..4 consecutive samples must agree.
5614 * 0b101..5 consecutive samples must agree.
5615 * 0b110..6 consecutive samples must agree.
5616 * 0b111..7 consecutive samples must agree.
5617 */
5618#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
5619/*! @} */
5620
5621/*! @name CR1 - CMP Control Register 1 */
5622/*! @{ */
5623#define CMP_CR1_EN_MASK (0x1U)
5624#define CMP_CR1_EN_SHIFT (0U)
5625/*! EN - Comparator Module Enable
5626 * 0b0..Analog Comparator is disabled.
5627 * 0b1..Analog Comparator is enabled.
5628 */
5629#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
5630#define CMP_CR1_OPE_MASK (0x2U)
5631#define CMP_CR1_OPE_SHIFT (1U)
5632/*! OPE - Comparator Output Pin Enable
5633 * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
5634 * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.
5635 */
5636#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
5637#define CMP_CR1_COS_MASK (0x4U)
5638#define CMP_CR1_COS_SHIFT (2U)
5639/*! COS - Comparator Output Select
5640 * 0b0..Set the filtered comparator output (CMPO) to equal COUT.
5641 * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
5642 */
5643#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
5644#define CMP_CR1_INV_MASK (0x8U)
5645#define CMP_CR1_INV_SHIFT (3U)
5646/*! INV - Comparator INVERT
5647 * 0b0..Does not invert the comparator output.
5648 * 0b1..Inverts the comparator output.
5649 */
5650#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
5651#define CMP_CR1_PMODE_MASK (0x10U)
5652#define CMP_CR1_PMODE_SHIFT (4U)
5653/*! PMODE - Power Mode Select
5654 * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
5655 * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
5656 */
5657#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
5658#define CMP_CR1_TRIGM_MASK (0x20U)
5659#define CMP_CR1_TRIGM_SHIFT (5U)
5660/*! TRIGM - Trigger Mode Enable
5661 * 0b0..Trigger mode is disabled.
5662 * 0b1..Trigger mode is enabled.
5663 */
5664#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
5665#define CMP_CR1_WE_MASK (0x40U)
5666#define CMP_CR1_WE_SHIFT (6U)
5667/*! WE - Windowing Enable
5668 * 0b0..Windowing mode is not selected.
5669 * 0b1..Windowing mode is selected.
5670 */
5671#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
5672#define CMP_CR1_SE_MASK (0x80U)
5673#define CMP_CR1_SE_SHIFT (7U)
5674/*! SE - Sample Enable
5675 * 0b0..Sampling mode is not selected.
5676 * 0b1..Sampling mode is selected.
5677 */
5678#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
5679/*! @} */
5680
5681/*! @name FPR - CMP Filter Period Register */
5682/*! @{ */
5683#define CMP_FPR_FILT_PER_MASK (0xFFU)
5684#define CMP_FPR_FILT_PER_SHIFT (0U)
5685#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
5686/*! @} */
5687
5688/*! @name SCR - CMP Status and Control Register */
5689/*! @{ */
5690#define CMP_SCR_COUT_MASK (0x1U)
5691#define CMP_SCR_COUT_SHIFT (0U)
5692#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
5693#define CMP_SCR_CFF_MASK (0x2U)
5694#define CMP_SCR_CFF_SHIFT (1U)
5695/*! CFF - Analog Comparator Flag Falling
5696 * 0b0..Falling-edge on COUT has not been detected.
5697 * 0b1..Falling-edge on COUT has occurred.
5698 */
5699#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
5700#define CMP_SCR_CFR_MASK (0x4U)
5701#define CMP_SCR_CFR_SHIFT (2U)
5702/*! CFR - Analog Comparator Flag Rising
5703 * 0b0..Rising-edge on COUT has not been detected.
5704 * 0b1..Rising-edge on COUT has occurred.
5705 */
5706#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
5707#define CMP_SCR_IEF_MASK (0x8U)
5708#define CMP_SCR_IEF_SHIFT (3U)
5709/*! IEF - Comparator Interrupt Enable Falling
5710 * 0b0..Interrupt is disabled.
5711 * 0b1..Interrupt is enabled.
5712 */
5713#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
5714#define CMP_SCR_IER_MASK (0x10U)
5715#define CMP_SCR_IER_SHIFT (4U)
5716/*! IER - Comparator Interrupt Enable Rising
5717 * 0b0..Interrupt is disabled.
5718 * 0b1..Interrupt is enabled.
5719 */
5720#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
5721#define CMP_SCR_DMAEN_MASK (0x40U)
5722#define CMP_SCR_DMAEN_SHIFT (6U)
5723/*! DMAEN - DMA Enable Control
5724 * 0b0..DMA is disabled.
5725 * 0b1..DMA is enabled.
5726 */
5727#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
5728/*! @} */
5729
5730/*! @name DACCR - DAC Control Register */
5731/*! @{ */
5732#define CMP_DACCR_VOSEL_MASK (0x3FU)
5733#define CMP_DACCR_VOSEL_SHIFT (0U)
5734#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
5735#define CMP_DACCR_VRSEL_MASK (0x40U)
5736#define CMP_DACCR_VRSEL_SHIFT (6U)
5737/*! VRSEL - Supply Voltage Reference Source Select
5738 * 0b0..Vin1 is selected as resistor ladder network supply reference.
5739 * 0b1..Vin2 is selected as resistor ladder network supply reference.
5740 */
5741#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
5742#define CMP_DACCR_DACEN_MASK (0x80U)
5743#define CMP_DACCR_DACEN_SHIFT (7U)
5744/*! DACEN - DAC Enable
5745 * 0b0..DAC is disabled.
5746 * 0b1..DAC is enabled.
5747 */
5748#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
5749/*! @} */
5750
5751/*! @name MUXCR - MUX Control Register */
5752/*! @{ */
5753#define CMP_MUXCR_MSEL_MASK (0x7U)
5754#define CMP_MUXCR_MSEL_SHIFT (0U)
5755/*! MSEL - Minus Input Mux Control
5756 * 0b000..IN0
5757 * 0b001..IN1
5758 * 0b010..IN2
5759 * 0b011..IN3
5760 * 0b100..IN4
5761 * 0b101..IN5
5762 * 0b110..IN6
5763 * 0b111..IN7
5764 */
5765#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
5766#define CMP_MUXCR_PSEL_MASK (0x38U)
5767#define CMP_MUXCR_PSEL_SHIFT (3U)
5768/*! PSEL - Plus Input Mux Control
5769 * 0b000..IN0
5770 * 0b001..IN1
5771 * 0b010..IN2
5772 * 0b011..IN3
5773 * 0b100..IN4
5774 * 0b101..IN5
5775 * 0b110..IN6
5776 * 0b111..IN7
5777 */
5778#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
5779#define CMP_MUXCR_PSTM_MASK (0x80U)
5780#define CMP_MUXCR_PSTM_SHIFT (7U)
5781/*! PSTM - Pass Through Mode Enable
5782 * 0b0..Pass Through Mode is disabled.
5783 * 0b1..Pass Through Mode is enabled.
5784 */
5785#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
5786/*! @} */
5787
5788
5789/*!
5790 * @}
5791 */ /* end of group CMP_Register_Masks */
5792
5793
5794/* CMP - Peripheral instance base addresses */
5795/** Peripheral CMP0 base address */
5796#define CMP0_BASE (0x40073000u)
5797/** Peripheral CMP0 base pointer */
5798#define CMP0 ((CMP_Type *)CMP0_BASE)
5799/** Peripheral CMP1 base address */
5800#define CMP1_BASE (0x40073008u)
5801/** Peripheral CMP1 base pointer */
5802#define CMP1 ((CMP_Type *)CMP1_BASE)
5803/** Peripheral CMP2 base address */
5804#define CMP2_BASE (0x40073010u)
5805/** Peripheral CMP2 base pointer */
5806#define CMP2 ((CMP_Type *)CMP2_BASE)
5807/** Peripheral CMP3 base address */
5808#define CMP3_BASE (0x40073018u)
5809/** Peripheral CMP3 base pointer */
5810#define CMP3 ((CMP_Type *)CMP3_BASE)
5811/** Array initializer of CMP peripheral base addresses */
5812#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }
5813/** Array initializer of CMP peripheral base pointers */
5814#define CMP_BASE_PTRS { CMP0, CMP1, CMP2, CMP3 }
5815/** Interrupt vectors for the CMP peripheral type */
5816#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn, CMP3_IRQn }
5817
5818/*!
5819 * @}
5820 */ /* end of group CMP_Peripheral_Access_Layer */
5821
5822
5823/* ----------------------------------------------------------------------------
5824 -- CMT Peripheral Access Layer
5825 ---------------------------------------------------------------------------- */
5826
5827/*!
5828 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
5829 * @{
5830 */
5831
5832/** CMT - Register Layout Typedef */
5833typedef struct {
5834 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
5835 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
5836 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
5837 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
5838 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
5839 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
5840 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
5841 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
5842 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
5843 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
5844 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
5845 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
5846} CMT_Type;
5847
5848/* ----------------------------------------------------------------------------
5849 -- CMT Register Masks
5850 ---------------------------------------------------------------------------- */
5851
5852/*!
5853 * @addtogroup CMT_Register_Masks CMT Register Masks
5854 * @{
5855 */
5856
5857/*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
5858/*! @{ */
5859#define CMT_CGH1_PH_MASK (0xFFU)
5860#define CMT_CGH1_PH_SHIFT (0U)
5861#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
5862/*! @} */
5863
5864/*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
5865/*! @{ */
5866#define CMT_CGL1_PL_MASK (0xFFU)
5867#define CMT_CGL1_PL_SHIFT (0U)
5868#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
5869/*! @} */
5870
5871/*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
5872/*! @{ */
5873#define CMT_CGH2_SH_MASK (0xFFU)
5874#define CMT_CGH2_SH_SHIFT (0U)
5875#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
5876/*! @} */
5877
5878/*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
5879/*! @{ */
5880#define CMT_CGL2_SL_MASK (0xFFU)
5881#define CMT_CGL2_SL_SHIFT (0U)
5882#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
5883/*! @} */
5884
5885/*! @name OC - CMT Output Control Register */
5886/*! @{ */
5887#define CMT_OC_IROPEN_MASK (0x20U)
5888#define CMT_OC_IROPEN_SHIFT (5U)
5889/*! IROPEN - IRO Pin Enable
5890 * 0b0..The IRO signal is disabled.
5891 * 0b1..The IRO signal is enabled as output.
5892 */
5893#define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
5894#define CMT_OC_CMTPOL_MASK (0x40U)
5895#define CMT_OC_CMTPOL_SHIFT (6U)
5896/*! CMTPOL - CMT Output Polarity
5897 * 0b0..The IRO signal is active-low.
5898 * 0b1..The IRO signal is active-high.
5899 */
5900#define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
5901#define CMT_OC_IROL_MASK (0x80U)
5902#define CMT_OC_IROL_SHIFT (7U)
5903#define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
5904/*! @} */
5905
5906/*! @name MSC - CMT Modulator Status and Control Register */
5907/*! @{ */
5908#define CMT_MSC_MCGEN_MASK (0x1U)
5909#define CMT_MSC_MCGEN_SHIFT (0U)
5910/*! MCGEN - Modulator and Carrier Generator Enable
5911 * 0b0..Modulator and carrier generator disabled
5912 * 0b1..Modulator and carrier generator enabled
5913 */
5914#define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
5915#define CMT_MSC_EOCIE_MASK (0x2U)
5916#define CMT_MSC_EOCIE_SHIFT (1U)
5917/*! EOCIE - End of Cycle Interrupt Enable
5918 * 0b0..CPU interrupt is disabled.
5919 * 0b1..CPU interrupt is enabled.
5920 */
5921#define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
5922#define CMT_MSC_FSK_MASK (0x4U)
5923#define CMT_MSC_FSK_SHIFT (2U)
5924/*! FSK - FSK Mode Select
5925 * 0b0..The CMT operates in Time or Baseband mode.
5926 * 0b1..The CMT operates in FSK mode.
5927 */
5928#define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
5929#define CMT_MSC_BASE_MASK (0x8U)
5930#define CMT_MSC_BASE_SHIFT (3U)
5931/*! BASE - Baseband Enable
5932 * 0b0..Baseband mode is disabled.
5933 * 0b1..Baseband mode is enabled.
5934 */
5935#define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
5936#define CMT_MSC_EXSPC_MASK (0x10U)
5937#define CMT_MSC_EXSPC_SHIFT (4U)
5938/*! EXSPC - Extended Space Enable
5939 * 0b0..Extended space is disabled.
5940 * 0b1..Extended space is enabled.
5941 */
5942#define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
5943#define CMT_MSC_CMTDIV_MASK (0x60U)
5944#define CMT_MSC_CMTDIV_SHIFT (5U)
5945/*! CMTDIV - CMT Clock Divide Prescaler
5946 * 0b00..IF * 1
5947 * 0b01..IF * 2
5948 * 0b10..IF * 4
5949 * 0b11..IF * 8
5950 */
5951#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
5952#define CMT_MSC_EOCF_MASK (0x80U)
5953#define CMT_MSC_EOCF_SHIFT (7U)
5954/*! EOCF - End Of Cycle Status Flag
5955 * 0b0..End of modulation cycle has not occured since the flag last cleared.
5956 * 0b1..End of modulator cycle has occurred.
5957 */
5958#define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
5959/*! @} */
5960
5961/*! @name CMD1 - CMT Modulator Data Register Mark High */
5962/*! @{ */
5963#define CMT_CMD1_MB_MASK (0xFFU)
5964#define CMT_CMD1_MB_SHIFT (0U)
5965#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
5966/*! @} */
5967
5968/*! @name CMD2 - CMT Modulator Data Register Mark Low */
5969/*! @{ */
5970#define CMT_CMD2_MB_MASK (0xFFU)
5971#define CMT_CMD2_MB_SHIFT (0U)
5972#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
5973/*! @} */
5974
5975/*! @name CMD3 - CMT Modulator Data Register Space High */
5976/*! @{ */
5977#define CMT_CMD3_SB_MASK (0xFFU)
5978#define CMT_CMD3_SB_SHIFT (0U)
5979#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
5980/*! @} */
5981
5982/*! @name CMD4 - CMT Modulator Data Register Space Low */
5983/*! @{ */
5984#define CMT_CMD4_SB_MASK (0xFFU)
5985#define CMT_CMD4_SB_SHIFT (0U)
5986#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
5987/*! @} */
5988
5989/*! @name PPS - CMT Primary Prescaler Register */
5990/*! @{ */
5991#define CMT_PPS_PPSDIV_MASK (0xFU)
5992#define CMT_PPS_PPSDIV_SHIFT (0U)
5993/*! PPSDIV - Primary Prescaler Divider
5994 * 0b0000..Bus clock * 1
5995 * 0b0001..Bus clock * 2
5996 * 0b0010..Bus clock * 3
5997 * 0b0011..Bus clock * 4
5998 * 0b0100..Bus clock * 5
5999 * 0b0101..Bus clock * 6
6000 * 0b0110..Bus clock * 7
6001 * 0b0111..Bus clock * 8
6002 * 0b1000..Bus clock * 9
6003 * 0b1001..Bus clock * 10
6004 * 0b1010..Bus clock * 11
6005 * 0b1011..Bus clock * 12
6006 * 0b1100..Bus clock * 13
6007 * 0b1101..Bus clock * 14
6008 * 0b1110..Bus clock * 15
6009 * 0b1111..Bus clock * 16
6010 */
6011#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
6012/*! @} */
6013
6014/*! @name DMA - CMT Direct Memory Access Register */
6015/*! @{ */
6016#define CMT_DMA_DMA_MASK (0x1U)
6017#define CMT_DMA_DMA_SHIFT (0U)
6018/*! DMA - DMA Enable
6019 * 0b0..DMA transfer request and done are disabled.
6020 * 0b1..DMA transfer request and done are enabled.
6021 */
6022#define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
6023/*! @} */
6024
6025
6026/*!
6027 * @}
6028 */ /* end of group CMT_Register_Masks */
6029
6030
6031/* CMT - Peripheral instance base addresses */
6032/** Peripheral CMT base address */
6033#define CMT_BASE (0x40062000u)
6034/** Peripheral CMT base pointer */
6035#define CMT ((CMT_Type *)CMT_BASE)
6036/** Array initializer of CMT peripheral base addresses */
6037#define CMT_BASE_ADDRS { CMT_BASE }
6038/** Array initializer of CMT peripheral base pointers */
6039#define CMT_BASE_PTRS { CMT }
6040/** Interrupt vectors for the CMT peripheral type */
6041#define CMT_IRQS { CMT_IRQn }
6042
6043/*!
6044 * @}
6045 */ /* end of group CMT_Peripheral_Access_Layer */
6046
6047
6048/* ----------------------------------------------------------------------------
6049 -- CRC Peripheral Access Layer
6050 ---------------------------------------------------------------------------- */
6051
6052/*!
6053 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
6054 * @{
6055 */
6056
6057/** CRC - Register Layout Typedef */
6058typedef struct {
6059 union { /* offset: 0x0 */
6060 struct { /* offset: 0x0 */
6061 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
6062 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
6063 } ACCESS16BIT;
6064 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
6065 struct { /* offset: 0x0 */
6066 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
6067 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
6068 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
6069 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
6070 } ACCESS8BIT;
6071 };
6072 union { /* offset: 0x4 */
6073 struct { /* offset: 0x4 */
6074 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
6075 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
6076 } GPOLY_ACCESS16BIT;
6077 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
6078 struct { /* offset: 0x4 */
6079 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
6080 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
6081 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
6082 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
6083 } GPOLY_ACCESS8BIT;
6084 };
6085 union { /* offset: 0x8 */
6086 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
6087 struct { /* offset: 0x8 */
6088 uint8_t RESERVED_0[3];
6089 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
6090 } CTRL_ACCESS8BIT;
6091 };
6092} CRC_Type;
6093
6094/* ----------------------------------------------------------------------------
6095 -- CRC Register Masks
6096 ---------------------------------------------------------------------------- */
6097
6098/*!
6099 * @addtogroup CRC_Register_Masks CRC Register Masks
6100 * @{
6101 */
6102
6103/*! @name DATAL - CRC_DATAL register. */
6104/*! @{ */
6105#define CRC_DATAL_DATAL_MASK (0xFFFFU)
6106#define CRC_DATAL_DATAL_SHIFT (0U)
6107#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
6108/*! @} */
6109
6110/*! @name DATAH - CRC_DATAH register. */
6111/*! @{ */
6112#define CRC_DATAH_DATAH_MASK (0xFFFFU)
6113#define CRC_DATAH_DATAH_SHIFT (0U)
6114#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
6115/*! @} */
6116
6117/*! @name DATA - CRC Data register */
6118/*! @{ */
6119#define CRC_DATA_LL_MASK (0xFFU)
6120#define CRC_DATA_LL_SHIFT (0U)
6121#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
6122#define CRC_DATA_LU_MASK (0xFF00U)
6123#define CRC_DATA_LU_SHIFT (8U)
6124#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
6125#define CRC_DATA_HL_MASK (0xFF0000U)
6126#define CRC_DATA_HL_SHIFT (16U)
6127#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
6128#define CRC_DATA_HU_MASK (0xFF000000U)
6129#define CRC_DATA_HU_SHIFT (24U)
6130#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
6131/*! @} */
6132
6133/*! @name DATALL - CRC_DATALL register. */
6134/*! @{ */
6135#define CRC_DATALL_DATALL_MASK (0xFFU)
6136#define CRC_DATALL_DATALL_SHIFT (0U)
6137#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
6138/*! @} */
6139
6140/*! @name DATALU - CRC_DATALU register. */
6141/*! @{ */
6142#define CRC_DATALU_DATALU_MASK (0xFFU)
6143#define CRC_DATALU_DATALU_SHIFT (0U)
6144#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
6145/*! @} */
6146
6147/*! @name DATAHL - CRC_DATAHL register. */
6148/*! @{ */
6149#define CRC_DATAHL_DATAHL_MASK (0xFFU)
6150#define CRC_DATAHL_DATAHL_SHIFT (0U)
6151#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
6152/*! @} */
6153
6154/*! @name DATAHU - CRC_DATAHU register. */
6155/*! @{ */
6156#define CRC_DATAHU_DATAHU_MASK (0xFFU)
6157#define CRC_DATAHU_DATAHU_SHIFT (0U)
6158#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
6159/*! @} */
6160
6161/*! @name GPOLYL - CRC_GPOLYL register. */
6162/*! @{ */
6163#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
6164#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
6165#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
6166/*! @} */
6167
6168/*! @name GPOLYH - CRC_GPOLYH register. */
6169/*! @{ */
6170#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
6171#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
6172#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
6173/*! @} */
6174
6175/*! @name GPOLY - CRC Polynomial register */
6176/*! @{ */
6177#define CRC_GPOLY_LOW_MASK (0xFFFFU)
6178#define CRC_GPOLY_LOW_SHIFT (0U)
6179#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
6180#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
6181#define CRC_GPOLY_HIGH_SHIFT (16U)
6182#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
6183/*! @} */
6184
6185/*! @name GPOLYLL - CRC_GPOLYLL register. */
6186/*! @{ */
6187#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
6188#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
6189#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
6190/*! @} */
6191
6192/*! @name GPOLYLU - CRC_GPOLYLU register. */
6193/*! @{ */
6194#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
6195#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
6196#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
6197/*! @} */
6198
6199/*! @name GPOLYHL - CRC_GPOLYHL register. */
6200/*! @{ */
6201#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
6202#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
6203#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
6204/*! @} */
6205
6206/*! @name GPOLYHU - CRC_GPOLYHU register. */
6207/*! @{ */
6208#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
6209#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
6210#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
6211/*! @} */
6212
6213/*! @name CTRL - CRC Control register */
6214/*! @{ */
6215#define CRC_CTRL_TCRC_MASK (0x1000000U)
6216#define CRC_CTRL_TCRC_SHIFT (24U)
6217/*! TCRC
6218 * 0b0..16-bit CRC protocol.
6219 * 0b1..32-bit CRC protocol.
6220 */
6221#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
6222#define CRC_CTRL_WAS_MASK (0x2000000U)
6223#define CRC_CTRL_WAS_SHIFT (25U)
6224/*! WAS - Write CRC Data Register As Seed
6225 * 0b0..Writes to the CRC data register are data values.
6226 * 0b1..Writes to the CRC data register are seed values.
6227 */
6228#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
6229#define CRC_CTRL_FXOR_MASK (0x4000000U)
6230#define CRC_CTRL_FXOR_SHIFT (26U)
6231/*! FXOR - Complement Read Of CRC Data Register
6232 * 0b0..No XOR on reading.
6233 * 0b1..Invert or complement the read value of the CRC Data register.
6234 */
6235#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
6236#define CRC_CTRL_TOTR_MASK (0x30000000U)
6237#define CRC_CTRL_TOTR_SHIFT (28U)
6238/*! TOTR - Type Of Transpose For Read
6239 * 0b00..No transposition.
6240 * 0b01..Bits in bytes are transposed; bytes are not transposed.
6241 * 0b10..Both bits in bytes and bytes are transposed.
6242 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
6243 */
6244#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
6245#define CRC_CTRL_TOT_MASK (0xC0000000U)
6246#define CRC_CTRL_TOT_SHIFT (30U)
6247/*! TOT - Type Of Transpose For Writes
6248 * 0b00..No transposition.
6249 * 0b01..Bits in bytes are transposed; bytes are not transposed.
6250 * 0b10..Both bits in bytes and bytes are transposed.
6251 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
6252 */
6253#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
6254/*! @} */
6255
6256/*! @name CTRLHU - CRC_CTRLHU register. */
6257/*! @{ */
6258#define CRC_CTRLHU_TCRC_MASK (0x1U)
6259#define CRC_CTRLHU_TCRC_SHIFT (0U)
6260/*! TCRC
6261 * 0b0..16-bit CRC protocol.
6262 * 0b1..32-bit CRC protocol.
6263 */
6264#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
6265#define CRC_CTRLHU_WAS_MASK (0x2U)
6266#define CRC_CTRLHU_WAS_SHIFT (1U)
6267/*! WAS
6268 * 0b0..Writes to CRC data register are data values.
6269 * 0b1..Writes to CRC data reguster are seed values.
6270 */
6271#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
6272#define CRC_CTRLHU_FXOR_MASK (0x4U)
6273#define CRC_CTRLHU_FXOR_SHIFT (2U)
6274/*! FXOR
6275 * 0b0..No XOR on reading.
6276 * 0b1..Invert or complement the read value of CRC data register.
6277 */
6278#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
6279#define CRC_CTRLHU_TOTR_MASK (0x30U)
6280#define CRC_CTRLHU_TOTR_SHIFT (4U)
6281/*! TOTR
6282 * 0b00..No Transposition.
6283 * 0b01..Bits in bytes are transposed, bytes are not transposed.
6284 * 0b10..Both bits in bytes and bytes are transposed.
6285 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
6286 */
6287#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
6288#define CRC_CTRLHU_TOT_MASK (0xC0U)
6289#define CRC_CTRLHU_TOT_SHIFT (6U)
6290/*! TOT
6291 * 0b00..No Transposition.
6292 * 0b01..Bits in bytes are transposed, bytes are not transposed.
6293 * 0b10..Both bits in bytes and bytes are transposed.
6294 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
6295 */
6296#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
6297/*! @} */
6298
6299
6300/*!
6301 * @}
6302 */ /* end of group CRC_Register_Masks */
6303
6304
6305/* CRC - Peripheral instance base addresses */
6306/** Peripheral CRC base address */
6307#define CRC_BASE (0x40032000u)
6308/** Peripheral CRC base pointer */
6309#define CRC0 ((CRC_Type *)CRC_BASE)
6310/** Array initializer of CRC peripheral base addresses */
6311#define CRC_BASE_ADDRS { CRC_BASE }
6312/** Array initializer of CRC peripheral base pointers */
6313#define CRC_BASE_PTRS { CRC0 }
6314
6315/*!
6316 * @}
6317 */ /* end of group CRC_Peripheral_Access_Layer */
6318
6319
6320/* ----------------------------------------------------------------------------
6321 -- DAC Peripheral Access Layer
6322 ---------------------------------------------------------------------------- */
6323
6324/*!
6325 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
6326 * @{
6327 */
6328
6329/** DAC - Register Layout Typedef */
6330typedef struct {
6331 struct { /* offset: 0x0, array step: 0x2 */
6332 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
6333 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
6334 } DAT[16];
6335 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
6336 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
6337 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
6338 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
6339} DAC_Type;
6340
6341/* ----------------------------------------------------------------------------
6342 -- DAC Register Masks
6343 ---------------------------------------------------------------------------- */
6344
6345/*!
6346 * @addtogroup DAC_Register_Masks DAC Register Masks
6347 * @{
6348 */
6349
6350/*! @name DATL - DAC Data Low Register */
6351/*! @{ */
6352#define DAC_DATL_DATA0_MASK (0xFFU)
6353#define DAC_DATL_DATA0_SHIFT (0U)
6354#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
6355/*! @} */
6356
6357/* The count of DAC_DATL */
6358#define DAC_DATL_COUNT (16U)
6359
6360/*! @name DATH - DAC Data High Register */
6361/*! @{ */
6362#define DAC_DATH_DATA1_MASK (0xFU)
6363#define DAC_DATH_DATA1_SHIFT (0U)
6364#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
6365/*! @} */
6366
6367/* The count of DAC_DATH */
6368#define DAC_DATH_COUNT (16U)
6369
6370/*! @name SR - DAC Status Register */
6371/*! @{ */
6372#define DAC_SR_DACBFRPBF_MASK (0x1U)
6373#define DAC_SR_DACBFRPBF_SHIFT (0U)
6374/*! DACBFRPBF - DAC Buffer Read Pointer Bottom Position Flag
6375 * 0b0..The DAC buffer read pointer is not equal to C2[DACBFUP].
6376 * 0b1..The DAC buffer read pointer is equal to C2[DACBFUP].
6377 */
6378#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
6379#define DAC_SR_DACBFRPTF_MASK (0x2U)
6380#define DAC_SR_DACBFRPTF_SHIFT (1U)
6381/*! DACBFRPTF - DAC Buffer Read Pointer Top Position Flag
6382 * 0b0..The DAC buffer read pointer is not zero.
6383 * 0b1..The DAC buffer read pointer is zero.
6384 */
6385#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
6386#define DAC_SR_DACBFWMF_MASK (0x4U)
6387#define DAC_SR_DACBFWMF_SHIFT (2U)
6388/*! DACBFWMF - DAC Buffer Watermark Flag
6389 * 0b0..The DAC buffer read pointer has not reached the watermark level.
6390 * 0b1..The DAC buffer read pointer has reached the watermark level.
6391 */
6392#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
6393/*! @} */
6394
6395/*! @name C0 - DAC Control Register */
6396/*! @{ */
6397#define DAC_C0_DACBBIEN_MASK (0x1U)
6398#define DAC_C0_DACBBIEN_SHIFT (0U)
6399/*! DACBBIEN - DAC Buffer Read Pointer Bottom Flag Interrupt Enable
6400 * 0b0..The DAC buffer read pointer bottom flag interrupt is disabled.
6401 * 0b1..The DAC buffer read pointer bottom flag interrupt is enabled.
6402 */
6403#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
6404#define DAC_C0_DACBTIEN_MASK (0x2U)
6405#define DAC_C0_DACBTIEN_SHIFT (1U)
6406/*! DACBTIEN - DAC Buffer Read Pointer Top Flag Interrupt Enable
6407 * 0b0..The DAC buffer read pointer top flag interrupt is disabled.
6408 * 0b1..The DAC buffer read pointer top flag interrupt is enabled.
6409 */
6410#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
6411#define DAC_C0_DACBWIEN_MASK (0x4U)
6412#define DAC_C0_DACBWIEN_SHIFT (2U)
6413/*! DACBWIEN - DAC Buffer Watermark Interrupt Enable
6414 * 0b0..The DAC buffer watermark interrupt is disabled.
6415 * 0b1..The DAC buffer watermark interrupt is enabled.
6416 */
6417#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
6418#define DAC_C0_LPEN_MASK (0x8U)
6419#define DAC_C0_LPEN_SHIFT (3U)
6420/*! LPEN - DAC Low Power Control
6421 * 0b0..High-Power mode
6422 * 0b1..Low-Power mode
6423 */
6424#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
6425#define DAC_C0_DACSWTRG_MASK (0x10U)
6426#define DAC_C0_DACSWTRG_SHIFT (4U)
6427/*! DACSWTRG - DAC Software Trigger
6428 * 0b0..The DAC soft trigger is not valid.
6429 * 0b1..The DAC soft trigger is valid.
6430 */
6431#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
6432#define DAC_C0_DACTRGSEL_MASK (0x20U)
6433#define DAC_C0_DACTRGSEL_SHIFT (5U)
6434/*! DACTRGSEL - DAC Trigger Select
6435 * 0b0..The DAC hardware trigger is selected.
6436 * 0b1..The DAC software trigger is selected.
6437 */
6438#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
6439#define DAC_C0_DACRFS_MASK (0x40U)
6440#define DAC_C0_DACRFS_SHIFT (6U)
6441/*! DACRFS - DAC Reference Select
6442 * 0b0..The DAC selects DACREF_1 as the reference voltage.
6443 * 0b1..The DAC selects DACREF_2 as the reference voltage.
6444 */
6445#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
6446#define DAC_C0_DACEN_MASK (0x80U)
6447#define DAC_C0_DACEN_SHIFT (7U)
6448/*! DACEN - DAC Enable
6449 * 0b0..The DAC system is disabled.
6450 * 0b1..The DAC system is enabled.
6451 */
6452#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
6453/*! @} */
6454
6455/*! @name C1 - DAC Control Register 1 */
6456/*! @{ */
6457#define DAC_C1_DACBFEN_MASK (0x1U)
6458#define DAC_C1_DACBFEN_SHIFT (0U)
6459/*! DACBFEN - DAC Buffer Enable
6460 * 0b0..Buffer read pointer is disabled. The converted data is always the first word of the buffer.
6461 * 0b1..Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.
6462 */
6463#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
6464#define DAC_C1_DACBFMD_MASK (0x6U)
6465#define DAC_C1_DACBFMD_SHIFT (1U)
6466/*! DACBFMD - DAC Buffer Work Mode Select
6467 * 0b00..Normal mode
6468 * 0b01..Swing mode
6469 * 0b10..One-Time Scan mode
6470 * 0b11..Reserved
6471 */
6472#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
6473#define DAC_C1_DACBFWM_MASK (0x18U)
6474#define DAC_C1_DACBFWM_SHIFT (3U)
6475/*! DACBFWM - DAC Buffer Watermark Select
6476 * 0b00..1 word
6477 * 0b01..2 words
6478 * 0b10..3 words
6479 * 0b11..4 words
6480 */
6481#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
6482#define DAC_C1_DMAEN_MASK (0x80U)
6483#define DAC_C1_DMAEN_SHIFT (7U)
6484/*! DMAEN - DMA Enable Select
6485 * 0b0..DMA is disabled.
6486 * 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.
6487 */
6488#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
6489/*! @} */
6490
6491/*! @name C2 - DAC Control Register 2 */
6492/*! @{ */
6493#define DAC_C2_DACBFUP_MASK (0xFU)
6494#define DAC_C2_DACBFUP_SHIFT (0U)
6495#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
6496#define DAC_C2_DACBFRP_MASK (0xF0U)
6497#define DAC_C2_DACBFRP_SHIFT (4U)
6498#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
6499/*! @} */
6500
6501
6502/*!
6503 * @}
6504 */ /* end of group DAC_Register_Masks */
6505
6506
6507/* DAC - Peripheral instance base addresses */
6508/** Peripheral DAC0 base address */
6509#define DAC0_BASE (0x400CC000u)
6510/** Peripheral DAC0 base pointer */
6511#define DAC0 ((DAC_Type *)DAC0_BASE)
6512/** Peripheral DAC1 base address */
6513#define DAC1_BASE (0x400CD000u)
6514/** Peripheral DAC1 base pointer */
6515#define DAC1 ((DAC_Type *)DAC1_BASE)
6516/** Array initializer of DAC peripheral base addresses */
6517#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
6518/** Array initializer of DAC peripheral base pointers */
6519#define DAC_BASE_PTRS { DAC0, DAC1 }
6520/** Interrupt vectors for the DAC peripheral type */
6521#define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
6522
6523/*!
6524 * @}
6525 */ /* end of group DAC_Peripheral_Access_Layer */
6526
6527
6528/* ----------------------------------------------------------------------------
6529 -- DMA Peripheral Access Layer
6530 ---------------------------------------------------------------------------- */
6531
6532/*!
6533 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
6534 * @{
6535 */
6536
6537/** DMA - Register Layout Typedef */
6538typedef struct {
6539 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
6540 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
6541 uint8_t RESERVED_0[4];
6542 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
6543 uint8_t RESERVED_1[4];
6544 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
6545 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
6546 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
6547 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
6548 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
6549 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
6550 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
6551 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
6552 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
6553 uint8_t RESERVED_2[4];
6554 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
6555 uint8_t RESERVED_3[4];
6556 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
6557 uint8_t RESERVED_4[4];
6558 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
6559 uint8_t RESERVED_5[12];
6560 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
6561 uint8_t RESERVED_6[184];
6562 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
6563 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
6564 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
6565 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
6566 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
6567 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
6568 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
6569 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
6570 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
6571 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
6572 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
6573 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
6574 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
6575 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
6576 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
6577 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
6578 __IO uint8_t DCHPRI19; /**< Channel n Priority Register, offset: 0x110 */
6579 __IO uint8_t DCHPRI18; /**< Channel n Priority Register, offset: 0x111 */
6580 __IO uint8_t DCHPRI17; /**< Channel n Priority Register, offset: 0x112 */
6581 __IO uint8_t DCHPRI16; /**< Channel n Priority Register, offset: 0x113 */
6582 __IO uint8_t DCHPRI23; /**< Channel n Priority Register, offset: 0x114 */
6583 __IO uint8_t DCHPRI22; /**< Channel n Priority Register, offset: 0x115 */
6584 __IO uint8_t DCHPRI21; /**< Channel n Priority Register, offset: 0x116 */
6585 __IO uint8_t DCHPRI20; /**< Channel n Priority Register, offset: 0x117 */
6586 __IO uint8_t DCHPRI27; /**< Channel n Priority Register, offset: 0x118 */
6587 __IO uint8_t DCHPRI26; /**< Channel n Priority Register, offset: 0x119 */
6588 __IO uint8_t DCHPRI25; /**< Channel n Priority Register, offset: 0x11A */
6589 __IO uint8_t DCHPRI24; /**< Channel n Priority Register, offset: 0x11B */
6590 __IO uint8_t DCHPRI31; /**< Channel n Priority Register, offset: 0x11C */
6591 __IO uint8_t DCHPRI30; /**< Channel n Priority Register, offset: 0x11D */
6592 __IO uint8_t DCHPRI29; /**< Channel n Priority Register, offset: 0x11E */
6593 __IO uint8_t DCHPRI28; /**< Channel n Priority Register, offset: 0x11F */
6594 uint8_t RESERVED_7[3808];
6595 struct { /* offset: 0x1000, array step: 0x20 */
6596 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
6597 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
6598 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
6599 union { /* offset: 0x1008, array step: 0x20 */
6600 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
6601 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
6602 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
6603 };
6604 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
6605 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
6606 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
6607 union { /* offset: 0x1016, array step: 0x20 */
6608 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
6609 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
6610 };
6611 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
6612 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
6613 union { /* offset: 0x101E, array step: 0x20 */
6614 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
6615 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
6616 };
6617 } TCD[32];
6618} DMA_Type;
6619
6620/* ----------------------------------------------------------------------------
6621 -- DMA Register Masks
6622 ---------------------------------------------------------------------------- */
6623
6624/*!
6625 * @addtogroup DMA_Register_Masks DMA Register Masks
6626 * @{
6627 */
6628
6629/*! @name CR - Control Register */
6630/*! @{ */
6631#define DMA_CR_EDBG_MASK (0x2U)
6632#define DMA_CR_EDBG_SHIFT (1U)
6633/*! EDBG - Enable Debug
6634 * 0b0..When in debug mode, the DMA continues to operate.
6635 * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
6636 */
6637#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
6638#define DMA_CR_ERCA_MASK (0x4U)
6639#define DMA_CR_ERCA_SHIFT (2U)
6640/*! ERCA - Enable Round Robin Channel Arbitration
6641 * 0b0..Fixed priority arbitration is used for channel selection within each group.
6642 * 0b1..Round robin arbitration is used for channel selection within each group.
6643 */
6644#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
6645#define DMA_CR_ERGA_MASK (0x8U)
6646#define DMA_CR_ERGA_SHIFT (3U)
6647/*! ERGA - Enable Round Robin Group Arbitration
6648 * 0b0..Fixed priority arbitration is used for selection among the groups.
6649 * 0b1..Round robin arbitration is used for selection among the groups.
6650 */
6651#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
6652#define DMA_CR_HOE_MASK (0x10U)
6653#define DMA_CR_HOE_SHIFT (4U)
6654/*! HOE - Halt On Error
6655 * 0b0..Normal operation
6656 * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
6657 */
6658#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
6659#define DMA_CR_HALT_MASK (0x20U)
6660#define DMA_CR_HALT_SHIFT (5U)
6661/*! HALT - Halt DMA Operations
6662 * 0b0..Normal operation
6663 * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
6664 */
6665#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
6666#define DMA_CR_CLM_MASK (0x40U)
6667#define DMA_CR_CLM_SHIFT (6U)
6668/*! CLM - Continuous Link Mode
6669 * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again.
6670 * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.
6671 */
6672#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
6673#define DMA_CR_EMLM_MASK (0x80U)
6674#define DMA_CR_EMLM_SHIFT (7U)
6675/*! EMLM - Enable Minor Loop Mapping
6676 * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
6677 * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.
6678 */
6679#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
6680#define DMA_CR_GRP0PRI_MASK (0x100U)
6681#define DMA_CR_GRP0PRI_SHIFT (8U)
6682#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
6683#define DMA_CR_GRP1PRI_MASK (0x400U)
6684#define DMA_CR_GRP1PRI_SHIFT (10U)
6685#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
6686#define DMA_CR_ECX_MASK (0x10000U)
6687#define DMA_CR_ECX_SHIFT (16U)
6688/*! ECX - Error Cancel Transfer
6689 * 0b0..Normal operation
6690 * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.
6691 */
6692#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
6693#define DMA_CR_CX_MASK (0x20000U)
6694#define DMA_CR_CX_SHIFT (17U)
6695/*! CX - Cancel Transfer
6696 * 0b0..Normal operation
6697 * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
6698 */
6699#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
6700/*! @} */
6701
6702/*! @name ES - Error Status Register */
6703/*! @{ */
6704#define DMA_ES_DBE_MASK (0x1U)
6705#define DMA_ES_DBE_SHIFT (0U)
6706/*! DBE - Destination Bus Error
6707 * 0b0..No destination bus error
6708 * 0b1..The last recorded error was a bus error on a destination write
6709 */
6710#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
6711#define DMA_ES_SBE_MASK (0x2U)
6712#define DMA_ES_SBE_SHIFT (1U)
6713/*! SBE - Source Bus Error
6714 * 0b0..No source bus error
6715 * 0b1..The last recorded error was a bus error on a source read
6716 */
6717#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
6718#define DMA_ES_SGE_MASK (0x4U)
6719#define DMA_ES_SGE_SHIFT (2U)
6720/*! SGE - Scatter/Gather Configuration Error
6721 * 0b0..No scatter/gather configuration error
6722 * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
6723 */
6724#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
6725#define DMA_ES_NCE_MASK (0x8U)
6726#define DMA_ES_NCE_SHIFT (3U)
6727/*! NCE - NBYTES/CITER Configuration Error
6728 * 0b0..No NBYTES/CITER configuration error
6729 * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
6730 */
6731#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
6732#define DMA_ES_DOE_MASK (0x10U)
6733#define DMA_ES_DOE_SHIFT (4U)
6734/*! DOE - Destination Offset Error
6735 * 0b0..No destination offset configuration error
6736 * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
6737 */
6738#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
6739#define DMA_ES_DAE_MASK (0x20U)
6740#define DMA_ES_DAE_SHIFT (5U)
6741/*! DAE - Destination Address Error
6742 * 0b0..No destination address configuration error
6743 * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
6744 */
6745#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
6746#define DMA_ES_SOE_MASK (0x40U)
6747#define DMA_ES_SOE_SHIFT (6U)
6748/*! SOE - Source Offset Error
6749 * 0b0..No source offset configuration error
6750 * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
6751 */
6752#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
6753#define DMA_ES_SAE_MASK (0x80U)
6754#define DMA_ES_SAE_SHIFT (7U)
6755/*! SAE - Source Address Error
6756 * 0b0..No source address configuration error.
6757 * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
6758 */
6759#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
6760#define DMA_ES_ERRCHN_MASK (0x1F00U)
6761#define DMA_ES_ERRCHN_SHIFT (8U)
6762#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
6763#define DMA_ES_CPE_MASK (0x4000U)
6764#define DMA_ES_CPE_SHIFT (14U)
6765/*! CPE - Channel Priority Error
6766 * 0b0..No channel priority error
6767 * 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique.
6768 */
6769#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
6770#define DMA_ES_GPE_MASK (0x8000U)
6771#define DMA_ES_GPE_SHIFT (15U)
6772/*! GPE - Group Priority Error
6773 * 0b0..No group priority error
6774 * 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique.
6775 */
6776#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
6777#define DMA_ES_ECX_MASK (0x10000U)
6778#define DMA_ES_ECX_SHIFT (16U)
6779/*! ECX - Transfer Canceled
6780 * 0b0..No canceled transfers
6781 * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input
6782 */
6783#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
6784#define DMA_ES_VLD_MASK (0x80000000U)
6785#define DMA_ES_VLD_SHIFT (31U)
6786/*! VLD
6787 * 0b0..No ERR bits are set.
6788 * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.
6789 */
6790#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
6791/*! @} */
6792
6793/*! @name ERQ - Enable Request Register */
6794/*! @{ */
6795#define DMA_ERQ_ERQ0_MASK (0x1U)
6796#define DMA_ERQ_ERQ0_SHIFT (0U)
6797/*! ERQ0 - Enable DMA Request 0
6798 * 0b0..The DMA request signal for the corresponding channel is disabled
6799 * 0b1..The DMA request signal for the corresponding channel is enabled
6800 */
6801#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
6802#define DMA_ERQ_ERQ1_MASK (0x2U)
6803#define DMA_ERQ_ERQ1_SHIFT (1U)
6804/*! ERQ1 - Enable DMA Request 1
6805 * 0b0..The DMA request signal for the corresponding channel is disabled
6806 * 0b1..The DMA request signal for the corresponding channel is enabled
6807 */
6808#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
6809#define DMA_ERQ_ERQ2_MASK (0x4U)
6810#define DMA_ERQ_ERQ2_SHIFT (2U)
6811/*! ERQ2 - Enable DMA Request 2
6812 * 0b0..The DMA request signal for the corresponding channel is disabled
6813 * 0b1..The DMA request signal for the corresponding channel is enabled
6814 */
6815#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
6816#define DMA_ERQ_ERQ3_MASK (0x8U)
6817#define DMA_ERQ_ERQ3_SHIFT (3U)
6818/*! ERQ3 - Enable DMA Request 3
6819 * 0b0..The DMA request signal for the corresponding channel is disabled
6820 * 0b1..The DMA request signal for the corresponding channel is enabled
6821 */
6822#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
6823#define DMA_ERQ_ERQ4_MASK (0x10U)
6824#define DMA_ERQ_ERQ4_SHIFT (4U)
6825/*! ERQ4 - Enable DMA Request 4
6826 * 0b0..The DMA request signal for the corresponding channel is disabled
6827 * 0b1..The DMA request signal for the corresponding channel is enabled
6828 */
6829#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
6830#define DMA_ERQ_ERQ5_MASK (0x20U)
6831#define DMA_ERQ_ERQ5_SHIFT (5U)
6832/*! ERQ5 - Enable DMA Request 5
6833 * 0b0..The DMA request signal for the corresponding channel is disabled
6834 * 0b1..The DMA request signal for the corresponding channel is enabled
6835 */
6836#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
6837#define DMA_ERQ_ERQ6_MASK (0x40U)
6838#define DMA_ERQ_ERQ6_SHIFT (6U)
6839/*! ERQ6 - Enable DMA Request 6
6840 * 0b0..The DMA request signal for the corresponding channel is disabled
6841 * 0b1..The DMA request signal for the corresponding channel is enabled
6842 */
6843#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
6844#define DMA_ERQ_ERQ7_MASK (0x80U)
6845#define DMA_ERQ_ERQ7_SHIFT (7U)
6846/*! ERQ7 - Enable DMA Request 7
6847 * 0b0..The DMA request signal for the corresponding channel is disabled
6848 * 0b1..The DMA request signal for the corresponding channel is enabled
6849 */
6850#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
6851#define DMA_ERQ_ERQ8_MASK (0x100U)
6852#define DMA_ERQ_ERQ8_SHIFT (8U)
6853/*! ERQ8 - Enable DMA Request 8
6854 * 0b0..The DMA request signal for the corresponding channel is disabled
6855 * 0b1..The DMA request signal for the corresponding channel is enabled
6856 */
6857#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
6858#define DMA_ERQ_ERQ9_MASK (0x200U)
6859#define DMA_ERQ_ERQ9_SHIFT (9U)
6860/*! ERQ9 - Enable DMA Request 9
6861 * 0b0..The DMA request signal for the corresponding channel is disabled
6862 * 0b1..The DMA request signal for the corresponding channel is enabled
6863 */
6864#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
6865#define DMA_ERQ_ERQ10_MASK (0x400U)
6866#define DMA_ERQ_ERQ10_SHIFT (10U)
6867/*! ERQ10 - Enable DMA Request 10
6868 * 0b0..The DMA request signal for the corresponding channel is disabled
6869 * 0b1..The DMA request signal for the corresponding channel is enabled
6870 */
6871#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
6872#define DMA_ERQ_ERQ11_MASK (0x800U)
6873#define DMA_ERQ_ERQ11_SHIFT (11U)
6874/*! ERQ11 - Enable DMA Request 11
6875 * 0b0..The DMA request signal for the corresponding channel is disabled
6876 * 0b1..The DMA request signal for the corresponding channel is enabled
6877 */
6878#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
6879#define DMA_ERQ_ERQ12_MASK (0x1000U)
6880#define DMA_ERQ_ERQ12_SHIFT (12U)
6881/*! ERQ12 - Enable DMA Request 12
6882 * 0b0..The DMA request signal for the corresponding channel is disabled
6883 * 0b1..The DMA request signal for the corresponding channel is enabled
6884 */
6885#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
6886#define DMA_ERQ_ERQ13_MASK (0x2000U)
6887#define DMA_ERQ_ERQ13_SHIFT (13U)
6888/*! ERQ13 - Enable DMA Request 13
6889 * 0b0..The DMA request signal for the corresponding channel is disabled
6890 * 0b1..The DMA request signal for the corresponding channel is enabled
6891 */
6892#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
6893#define DMA_ERQ_ERQ14_MASK (0x4000U)
6894#define DMA_ERQ_ERQ14_SHIFT (14U)
6895/*! ERQ14 - Enable DMA Request 14
6896 * 0b0..The DMA request signal for the corresponding channel is disabled
6897 * 0b1..The DMA request signal for the corresponding channel is enabled
6898 */
6899#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
6900#define DMA_ERQ_ERQ15_MASK (0x8000U)
6901#define DMA_ERQ_ERQ15_SHIFT (15U)
6902/*! ERQ15 - Enable DMA Request 15
6903 * 0b0..The DMA request signal for the corresponding channel is disabled
6904 * 0b1..The DMA request signal for the corresponding channel is enabled
6905 */
6906#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
6907#define DMA_ERQ_ERQ16_MASK (0x10000U)
6908#define DMA_ERQ_ERQ16_SHIFT (16U)
6909/*! ERQ16 - Enable DMA Request 16
6910 * 0b0..The DMA request signal for the corresponding channel is disabled
6911 * 0b1..The DMA request signal for the corresponding channel is enabled
6912 */
6913#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
6914#define DMA_ERQ_ERQ17_MASK (0x20000U)
6915#define DMA_ERQ_ERQ17_SHIFT (17U)
6916/*! ERQ17 - Enable DMA Request 17
6917 * 0b0..The DMA request signal for the corresponding channel is disabled
6918 * 0b1..The DMA request signal for the corresponding channel is enabled
6919 */
6920#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
6921#define DMA_ERQ_ERQ18_MASK (0x40000U)
6922#define DMA_ERQ_ERQ18_SHIFT (18U)
6923/*! ERQ18 - Enable DMA Request 18
6924 * 0b0..The DMA request signal for the corresponding channel is disabled
6925 * 0b1..The DMA request signal for the corresponding channel is enabled
6926 */
6927#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
6928#define DMA_ERQ_ERQ19_MASK (0x80000U)
6929#define DMA_ERQ_ERQ19_SHIFT (19U)
6930/*! ERQ19 - Enable DMA Request 19
6931 * 0b0..The DMA request signal for the corresponding channel is disabled
6932 * 0b1..The DMA request signal for the corresponding channel is enabled
6933 */
6934#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
6935#define DMA_ERQ_ERQ20_MASK (0x100000U)
6936#define DMA_ERQ_ERQ20_SHIFT (20U)
6937/*! ERQ20 - Enable DMA Request 20
6938 * 0b0..The DMA request signal for the corresponding channel is disabled
6939 * 0b1..The DMA request signal for the corresponding channel is enabled
6940 */
6941#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
6942#define DMA_ERQ_ERQ21_MASK (0x200000U)
6943#define DMA_ERQ_ERQ21_SHIFT (21U)
6944/*! ERQ21 - Enable DMA Request 21
6945 * 0b0..The DMA request signal for the corresponding channel is disabled
6946 * 0b1..The DMA request signal for the corresponding channel is enabled
6947 */
6948#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
6949#define DMA_ERQ_ERQ22_MASK (0x400000U)
6950#define DMA_ERQ_ERQ22_SHIFT (22U)
6951/*! ERQ22 - Enable DMA Request 22
6952 * 0b0..The DMA request signal for the corresponding channel is disabled
6953 * 0b1..The DMA request signal for the corresponding channel is enabled
6954 */
6955#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
6956#define DMA_ERQ_ERQ23_MASK (0x800000U)
6957#define DMA_ERQ_ERQ23_SHIFT (23U)
6958/*! ERQ23 - Enable DMA Request 23
6959 * 0b0..The DMA request signal for the corresponding channel is disabled
6960 * 0b1..The DMA request signal for the corresponding channel is enabled
6961 */
6962#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
6963#define DMA_ERQ_ERQ24_MASK (0x1000000U)
6964#define DMA_ERQ_ERQ24_SHIFT (24U)
6965/*! ERQ24 - Enable DMA Request 24
6966 * 0b0..The DMA request signal for the corresponding channel is disabled
6967 * 0b1..The DMA request signal for the corresponding channel is enabled
6968 */
6969#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
6970#define DMA_ERQ_ERQ25_MASK (0x2000000U)
6971#define DMA_ERQ_ERQ25_SHIFT (25U)
6972/*! ERQ25 - Enable DMA Request 25
6973 * 0b0..The DMA request signal for the corresponding channel is disabled
6974 * 0b1..The DMA request signal for the corresponding channel is enabled
6975 */
6976#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
6977#define DMA_ERQ_ERQ26_MASK (0x4000000U)
6978#define DMA_ERQ_ERQ26_SHIFT (26U)
6979/*! ERQ26 - Enable DMA Request 26
6980 * 0b0..The DMA request signal for the corresponding channel is disabled
6981 * 0b1..The DMA request signal for the corresponding channel is enabled
6982 */
6983#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
6984#define DMA_ERQ_ERQ27_MASK (0x8000000U)
6985#define DMA_ERQ_ERQ27_SHIFT (27U)
6986/*! ERQ27 - Enable DMA Request 27
6987 * 0b0..The DMA request signal for the corresponding channel is disabled
6988 * 0b1..The DMA request signal for the corresponding channel is enabled
6989 */
6990#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
6991#define DMA_ERQ_ERQ28_MASK (0x10000000U)
6992#define DMA_ERQ_ERQ28_SHIFT (28U)
6993/*! ERQ28 - Enable DMA Request 28
6994 * 0b0..The DMA request signal for the corresponding channel is disabled
6995 * 0b1..The DMA request signal for the corresponding channel is enabled
6996 */
6997#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
6998#define DMA_ERQ_ERQ29_MASK (0x20000000U)
6999#define DMA_ERQ_ERQ29_SHIFT (29U)
7000/*! ERQ29 - Enable DMA Request 29
7001 * 0b0..The DMA request signal for the corresponding channel is disabled
7002 * 0b1..The DMA request signal for the corresponding channel is enabled
7003 */
7004#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
7005#define DMA_ERQ_ERQ30_MASK (0x40000000U)
7006#define DMA_ERQ_ERQ30_SHIFT (30U)
7007/*! ERQ30 - Enable DMA Request 30
7008 * 0b0..The DMA request signal for the corresponding channel is disabled
7009 * 0b1..The DMA request signal for the corresponding channel is enabled
7010 */
7011#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
7012#define DMA_ERQ_ERQ31_MASK (0x80000000U)
7013#define DMA_ERQ_ERQ31_SHIFT (31U)
7014/*! ERQ31 - Enable DMA Request 31
7015 * 0b0..The DMA request signal for the corresponding channel is disabled
7016 * 0b1..The DMA request signal for the corresponding channel is enabled
7017 */
7018#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
7019/*! @} */
7020
7021/*! @name EEI - Enable Error Interrupt Register */
7022/*! @{ */
7023#define DMA_EEI_EEI0_MASK (0x1U)
7024#define DMA_EEI_EEI0_SHIFT (0U)
7025/*! EEI0 - Enable Error Interrupt 0
7026 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7027 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7028 */
7029#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
7030#define DMA_EEI_EEI1_MASK (0x2U)
7031#define DMA_EEI_EEI1_SHIFT (1U)
7032/*! EEI1 - Enable Error Interrupt 1
7033 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7034 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7035 */
7036#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
7037#define DMA_EEI_EEI2_MASK (0x4U)
7038#define DMA_EEI_EEI2_SHIFT (2U)
7039/*! EEI2 - Enable Error Interrupt 2
7040 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7041 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7042 */
7043#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
7044#define DMA_EEI_EEI3_MASK (0x8U)
7045#define DMA_EEI_EEI3_SHIFT (3U)
7046/*! EEI3 - Enable Error Interrupt 3
7047 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7048 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7049 */
7050#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
7051#define DMA_EEI_EEI4_MASK (0x10U)
7052#define DMA_EEI_EEI4_SHIFT (4U)
7053/*! EEI4 - Enable Error Interrupt 4
7054 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7055 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7056 */
7057#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
7058#define DMA_EEI_EEI5_MASK (0x20U)
7059#define DMA_EEI_EEI5_SHIFT (5U)
7060/*! EEI5 - Enable Error Interrupt 5
7061 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7062 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7063 */
7064#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
7065#define DMA_EEI_EEI6_MASK (0x40U)
7066#define DMA_EEI_EEI6_SHIFT (6U)
7067/*! EEI6 - Enable Error Interrupt 6
7068 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7069 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7070 */
7071#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
7072#define DMA_EEI_EEI7_MASK (0x80U)
7073#define DMA_EEI_EEI7_SHIFT (7U)
7074/*! EEI7 - Enable Error Interrupt 7
7075 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7076 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7077 */
7078#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
7079#define DMA_EEI_EEI8_MASK (0x100U)
7080#define DMA_EEI_EEI8_SHIFT (8U)
7081/*! EEI8 - Enable Error Interrupt 8
7082 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7083 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7084 */
7085#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
7086#define DMA_EEI_EEI9_MASK (0x200U)
7087#define DMA_EEI_EEI9_SHIFT (9U)
7088/*! EEI9 - Enable Error Interrupt 9
7089 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7090 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7091 */
7092#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
7093#define DMA_EEI_EEI10_MASK (0x400U)
7094#define DMA_EEI_EEI10_SHIFT (10U)
7095/*! EEI10 - Enable Error Interrupt 10
7096 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7097 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7098 */
7099#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
7100#define DMA_EEI_EEI11_MASK (0x800U)
7101#define DMA_EEI_EEI11_SHIFT (11U)
7102/*! EEI11 - Enable Error Interrupt 11
7103 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7104 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7105 */
7106#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
7107#define DMA_EEI_EEI12_MASK (0x1000U)
7108#define DMA_EEI_EEI12_SHIFT (12U)
7109/*! EEI12 - Enable Error Interrupt 12
7110 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7111 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7112 */
7113#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
7114#define DMA_EEI_EEI13_MASK (0x2000U)
7115#define DMA_EEI_EEI13_SHIFT (13U)
7116/*! EEI13 - Enable Error Interrupt 13
7117 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7118 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7119 */
7120#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
7121#define DMA_EEI_EEI14_MASK (0x4000U)
7122#define DMA_EEI_EEI14_SHIFT (14U)
7123/*! EEI14 - Enable Error Interrupt 14
7124 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7125 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7126 */
7127#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
7128#define DMA_EEI_EEI15_MASK (0x8000U)
7129#define DMA_EEI_EEI15_SHIFT (15U)
7130/*! EEI15 - Enable Error Interrupt 15
7131 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7132 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7133 */
7134#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
7135#define DMA_EEI_EEI16_MASK (0x10000U)
7136#define DMA_EEI_EEI16_SHIFT (16U)
7137/*! EEI16 - Enable Error Interrupt 16
7138 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7139 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7140 */
7141#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
7142#define DMA_EEI_EEI17_MASK (0x20000U)
7143#define DMA_EEI_EEI17_SHIFT (17U)
7144/*! EEI17 - Enable Error Interrupt 17
7145 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7146 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7147 */
7148#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
7149#define DMA_EEI_EEI18_MASK (0x40000U)
7150#define DMA_EEI_EEI18_SHIFT (18U)
7151/*! EEI18 - Enable Error Interrupt 18
7152 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7153 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7154 */
7155#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
7156#define DMA_EEI_EEI19_MASK (0x80000U)
7157#define DMA_EEI_EEI19_SHIFT (19U)
7158/*! EEI19 - Enable Error Interrupt 19
7159 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7160 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7161 */
7162#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
7163#define DMA_EEI_EEI20_MASK (0x100000U)
7164#define DMA_EEI_EEI20_SHIFT (20U)
7165/*! EEI20 - Enable Error Interrupt 20
7166 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7167 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7168 */
7169#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
7170#define DMA_EEI_EEI21_MASK (0x200000U)
7171#define DMA_EEI_EEI21_SHIFT (21U)
7172/*! EEI21 - Enable Error Interrupt 21
7173 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7174 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7175 */
7176#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
7177#define DMA_EEI_EEI22_MASK (0x400000U)
7178#define DMA_EEI_EEI22_SHIFT (22U)
7179/*! EEI22 - Enable Error Interrupt 22
7180 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7181 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7182 */
7183#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
7184#define DMA_EEI_EEI23_MASK (0x800000U)
7185#define DMA_EEI_EEI23_SHIFT (23U)
7186/*! EEI23 - Enable Error Interrupt 23
7187 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7188 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7189 */
7190#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
7191#define DMA_EEI_EEI24_MASK (0x1000000U)
7192#define DMA_EEI_EEI24_SHIFT (24U)
7193/*! EEI24 - Enable Error Interrupt 24
7194 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7195 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7196 */
7197#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
7198#define DMA_EEI_EEI25_MASK (0x2000000U)
7199#define DMA_EEI_EEI25_SHIFT (25U)
7200/*! EEI25 - Enable Error Interrupt 25
7201 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7202 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7203 */
7204#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
7205#define DMA_EEI_EEI26_MASK (0x4000000U)
7206#define DMA_EEI_EEI26_SHIFT (26U)
7207/*! EEI26 - Enable Error Interrupt 26
7208 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7209 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7210 */
7211#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
7212#define DMA_EEI_EEI27_MASK (0x8000000U)
7213#define DMA_EEI_EEI27_SHIFT (27U)
7214/*! EEI27 - Enable Error Interrupt 27
7215 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7216 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7217 */
7218#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
7219#define DMA_EEI_EEI28_MASK (0x10000000U)
7220#define DMA_EEI_EEI28_SHIFT (28U)
7221/*! EEI28 - Enable Error Interrupt 28
7222 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7223 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7224 */
7225#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
7226#define DMA_EEI_EEI29_MASK (0x20000000U)
7227#define DMA_EEI_EEI29_SHIFT (29U)
7228/*! EEI29 - Enable Error Interrupt 29
7229 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7230 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7231 */
7232#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
7233#define DMA_EEI_EEI30_MASK (0x40000000U)
7234#define DMA_EEI_EEI30_SHIFT (30U)
7235/*! EEI30 - Enable Error Interrupt 30
7236 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7237 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7238 */
7239#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
7240#define DMA_EEI_EEI31_MASK (0x80000000U)
7241#define DMA_EEI_EEI31_SHIFT (31U)
7242/*! EEI31 - Enable Error Interrupt 31
7243 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7244 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7245 */
7246#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
7247/*! @} */
7248
7249/*! @name CEEI - Clear Enable Error Interrupt Register */
7250/*! @{ */
7251#define DMA_CEEI_CEEI_MASK (0x1FU)
7252#define DMA_CEEI_CEEI_SHIFT (0U)
7253#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
7254#define DMA_CEEI_CAEE_MASK (0x40U)
7255#define DMA_CEEI_CAEE_SHIFT (6U)
7256/*! CAEE - Clear All Enable Error Interrupts
7257 * 0b0..Clear only the EEI bit specified in the CEEI field
7258 * 0b1..Clear all bits in EEI
7259 */
7260#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
7261#define DMA_CEEI_NOP_MASK (0x80U)
7262#define DMA_CEEI_NOP_SHIFT (7U)
7263/*! NOP - No Op enable
7264 * 0b0..Normal operation
7265 * 0b1..No operation, ignore the other bits in this register
7266 */
7267#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
7268/*! @} */
7269
7270/*! @name SEEI - Set Enable Error Interrupt Register */
7271/*! @{ */
7272#define DMA_SEEI_SEEI_MASK (0x1FU)
7273#define DMA_SEEI_SEEI_SHIFT (0U)
7274#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
7275#define DMA_SEEI_SAEE_MASK (0x40U)
7276#define DMA_SEEI_SAEE_SHIFT (6U)
7277/*! SAEE - Sets All Enable Error Interrupts
7278 * 0b0..Set only the EEI bit specified in the SEEI field.
7279 * 0b1..Sets all bits in EEI
7280 */
7281#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
7282#define DMA_SEEI_NOP_MASK (0x80U)
7283#define DMA_SEEI_NOP_SHIFT (7U)
7284/*! NOP - No Op enable
7285 * 0b0..Normal operation
7286 * 0b1..No operation, ignore the other bits in this register
7287 */
7288#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
7289/*! @} */
7290
7291/*! @name CERQ - Clear Enable Request Register */
7292/*! @{ */
7293#define DMA_CERQ_CERQ_MASK (0x1FU)
7294#define DMA_CERQ_CERQ_SHIFT (0U)
7295#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
7296#define DMA_CERQ_CAER_MASK (0x40U)
7297#define DMA_CERQ_CAER_SHIFT (6U)
7298/*! CAER - Clear All Enable Requests
7299 * 0b0..Clear only the ERQ bit specified in the CERQ field
7300 * 0b1..Clear all bits in ERQ
7301 */
7302#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
7303#define DMA_CERQ_NOP_MASK (0x80U)
7304#define DMA_CERQ_NOP_SHIFT (7U)
7305/*! NOP - No Op enable
7306 * 0b0..Normal operation
7307 * 0b1..No operation, ignore the other bits in this register
7308 */
7309#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
7310/*! @} */
7311
7312/*! @name SERQ - Set Enable Request Register */
7313/*! @{ */
7314#define DMA_SERQ_SERQ_MASK (0x1FU)
7315#define DMA_SERQ_SERQ_SHIFT (0U)
7316#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
7317#define DMA_SERQ_SAER_MASK (0x40U)
7318#define DMA_SERQ_SAER_SHIFT (6U)
7319/*! SAER - Set All Enable Requests
7320 * 0b0..Set only the ERQ bit specified in the SERQ field
7321 * 0b1..Set all bits in ERQ
7322 */
7323#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
7324#define DMA_SERQ_NOP_MASK (0x80U)
7325#define DMA_SERQ_NOP_SHIFT (7U)
7326/*! NOP - No Op enable
7327 * 0b0..Normal operation
7328 * 0b1..No operation, ignore the other bits in this register
7329 */
7330#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
7331/*! @} */
7332
7333/*! @name CDNE - Clear DONE Status Bit Register */
7334/*! @{ */
7335#define DMA_CDNE_CDNE_MASK (0x1FU)
7336#define DMA_CDNE_CDNE_SHIFT (0U)
7337#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
7338#define DMA_CDNE_CADN_MASK (0x40U)
7339#define DMA_CDNE_CADN_SHIFT (6U)
7340/*! CADN - Clears All DONE Bits
7341 * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
7342 * 0b1..Clears all bits in TCDn_CSR[DONE]
7343 */
7344#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
7345#define DMA_CDNE_NOP_MASK (0x80U)
7346#define DMA_CDNE_NOP_SHIFT (7U)
7347/*! NOP - No Op enable
7348 * 0b0..Normal operation
7349 * 0b1..No operation, ignore the other bits in this register
7350 */
7351#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
7352/*! @} */
7353
7354/*! @name SSRT - Set START Bit Register */
7355/*! @{ */
7356#define DMA_SSRT_SSRT_MASK (0x1FU)
7357#define DMA_SSRT_SSRT_SHIFT (0U)
7358#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
7359#define DMA_SSRT_SAST_MASK (0x40U)
7360#define DMA_SSRT_SAST_SHIFT (6U)
7361/*! SAST - Set All START Bits (activates all channels)
7362 * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field
7363 * 0b1..Set all bits in TCDn_CSR[START]
7364 */
7365#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
7366#define DMA_SSRT_NOP_MASK (0x80U)
7367#define DMA_SSRT_NOP_SHIFT (7U)
7368/*! NOP - No Op enable
7369 * 0b0..Normal operation
7370 * 0b1..No operation, ignore the other bits in this register
7371 */
7372#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
7373/*! @} */
7374
7375/*! @name CERR - Clear Error Register */
7376/*! @{ */
7377#define DMA_CERR_CERR_MASK (0x1FU)
7378#define DMA_CERR_CERR_SHIFT (0U)
7379#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
7380#define DMA_CERR_CAEI_MASK (0x40U)
7381#define DMA_CERR_CAEI_SHIFT (6U)
7382/*! CAEI - Clear All Error Indicators
7383 * 0b0..Clear only the ERR bit specified in the CERR field
7384 * 0b1..Clear all bits in ERR
7385 */
7386#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
7387#define DMA_CERR_NOP_MASK (0x80U)
7388#define DMA_CERR_NOP_SHIFT (7U)
7389/*! NOP - No Op enable
7390 * 0b0..Normal operation
7391 * 0b1..No operation, ignore the other bits in this register
7392 */
7393#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
7394/*! @} */
7395
7396/*! @name CINT - Clear Interrupt Request Register */
7397/*! @{ */
7398#define DMA_CINT_CINT_MASK (0x1FU)
7399#define DMA_CINT_CINT_SHIFT (0U)
7400#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
7401#define DMA_CINT_CAIR_MASK (0x40U)
7402#define DMA_CINT_CAIR_SHIFT (6U)
7403/*! CAIR - Clear All Interrupt Requests
7404 * 0b0..Clear only the INT bit specified in the CINT field
7405 * 0b1..Clear all bits in INT
7406 */
7407#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
7408#define DMA_CINT_NOP_MASK (0x80U)
7409#define DMA_CINT_NOP_SHIFT (7U)
7410/*! NOP - No Op enable
7411 * 0b0..Normal operation
7412 * 0b1..No operation, ignore the other bits in this register
7413 */
7414#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
7415/*! @} */
7416
7417/*! @name INT - Interrupt Request Register */
7418/*! @{ */
7419#define DMA_INT_INT0_MASK (0x1U)
7420#define DMA_INT_INT0_SHIFT (0U)
7421/*! INT0 - Interrupt Request 0
7422 * 0b0..The interrupt request for corresponding channel is cleared
7423 * 0b1..The interrupt request for corresponding channel is active
7424 */
7425#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
7426#define DMA_INT_INT1_MASK (0x2U)
7427#define DMA_INT_INT1_SHIFT (1U)
7428/*! INT1 - Interrupt Request 1
7429 * 0b0..The interrupt request for corresponding channel is cleared
7430 * 0b1..The interrupt request for corresponding channel is active
7431 */
7432#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
7433#define DMA_INT_INT2_MASK (0x4U)
7434#define DMA_INT_INT2_SHIFT (2U)
7435/*! INT2 - Interrupt Request 2
7436 * 0b0..The interrupt request for corresponding channel is cleared
7437 * 0b1..The interrupt request for corresponding channel is active
7438 */
7439#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
7440#define DMA_INT_INT3_MASK (0x8U)
7441#define DMA_INT_INT3_SHIFT (3U)
7442/*! INT3 - Interrupt Request 3
7443 * 0b0..The interrupt request for corresponding channel is cleared
7444 * 0b1..The interrupt request for corresponding channel is active
7445 */
7446#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
7447#define DMA_INT_INT4_MASK (0x10U)
7448#define DMA_INT_INT4_SHIFT (4U)
7449/*! INT4 - Interrupt Request 4
7450 * 0b0..The interrupt request for corresponding channel is cleared
7451 * 0b1..The interrupt request for corresponding channel is active
7452 */
7453#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
7454#define DMA_INT_INT5_MASK (0x20U)
7455#define DMA_INT_INT5_SHIFT (5U)
7456/*! INT5 - Interrupt Request 5
7457 * 0b0..The interrupt request for corresponding channel is cleared
7458 * 0b1..The interrupt request for corresponding channel is active
7459 */
7460#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
7461#define DMA_INT_INT6_MASK (0x40U)
7462#define DMA_INT_INT6_SHIFT (6U)
7463/*! INT6 - Interrupt Request 6
7464 * 0b0..The interrupt request for corresponding channel is cleared
7465 * 0b1..The interrupt request for corresponding channel is active
7466 */
7467#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
7468#define DMA_INT_INT7_MASK (0x80U)
7469#define DMA_INT_INT7_SHIFT (7U)
7470/*! INT7 - Interrupt Request 7
7471 * 0b0..The interrupt request for corresponding channel is cleared
7472 * 0b1..The interrupt request for corresponding channel is active
7473 */
7474#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
7475#define DMA_INT_INT8_MASK (0x100U)
7476#define DMA_INT_INT8_SHIFT (8U)
7477/*! INT8 - Interrupt Request 8
7478 * 0b0..The interrupt request for corresponding channel is cleared
7479 * 0b1..The interrupt request for corresponding channel is active
7480 */
7481#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
7482#define DMA_INT_INT9_MASK (0x200U)
7483#define DMA_INT_INT9_SHIFT (9U)
7484/*! INT9 - Interrupt Request 9
7485 * 0b0..The interrupt request for corresponding channel is cleared
7486 * 0b1..The interrupt request for corresponding channel is active
7487 */
7488#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
7489#define DMA_INT_INT10_MASK (0x400U)
7490#define DMA_INT_INT10_SHIFT (10U)
7491/*! INT10 - Interrupt Request 10
7492 * 0b0..The interrupt request for corresponding channel is cleared
7493 * 0b1..The interrupt request for corresponding channel is active
7494 */
7495#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
7496#define DMA_INT_INT11_MASK (0x800U)
7497#define DMA_INT_INT11_SHIFT (11U)
7498/*! INT11 - Interrupt Request 11
7499 * 0b0..The interrupt request for corresponding channel is cleared
7500 * 0b1..The interrupt request for corresponding channel is active
7501 */
7502#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
7503#define DMA_INT_INT12_MASK (0x1000U)
7504#define DMA_INT_INT12_SHIFT (12U)
7505/*! INT12 - Interrupt Request 12
7506 * 0b0..The interrupt request for corresponding channel is cleared
7507 * 0b1..The interrupt request for corresponding channel is active
7508 */
7509#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
7510#define DMA_INT_INT13_MASK (0x2000U)
7511#define DMA_INT_INT13_SHIFT (13U)
7512/*! INT13 - Interrupt Request 13
7513 * 0b0..The interrupt request for corresponding channel is cleared
7514 * 0b1..The interrupt request for corresponding channel is active
7515 */
7516#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
7517#define DMA_INT_INT14_MASK (0x4000U)
7518#define DMA_INT_INT14_SHIFT (14U)
7519/*! INT14 - Interrupt Request 14
7520 * 0b0..The interrupt request for corresponding channel is cleared
7521 * 0b1..The interrupt request for corresponding channel is active
7522 */
7523#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
7524#define DMA_INT_INT15_MASK (0x8000U)
7525#define DMA_INT_INT15_SHIFT (15U)
7526/*! INT15 - Interrupt Request 15
7527 * 0b0..The interrupt request for corresponding channel is cleared
7528 * 0b1..The interrupt request for corresponding channel is active
7529 */
7530#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
7531#define DMA_INT_INT16_MASK (0x10000U)
7532#define DMA_INT_INT16_SHIFT (16U)
7533/*! INT16 - Interrupt Request 16
7534 * 0b0..The interrupt request for corresponding channel is cleared
7535 * 0b1..The interrupt request for corresponding channel is active
7536 */
7537#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
7538#define DMA_INT_INT17_MASK (0x20000U)
7539#define DMA_INT_INT17_SHIFT (17U)
7540/*! INT17 - Interrupt Request 17
7541 * 0b0..The interrupt request for corresponding channel is cleared
7542 * 0b1..The interrupt request for corresponding channel is active
7543 */
7544#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
7545#define DMA_INT_INT18_MASK (0x40000U)
7546#define DMA_INT_INT18_SHIFT (18U)
7547/*! INT18 - Interrupt Request 18
7548 * 0b0..The interrupt request for corresponding channel is cleared
7549 * 0b1..The interrupt request for corresponding channel is active
7550 */
7551#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
7552#define DMA_INT_INT19_MASK (0x80000U)
7553#define DMA_INT_INT19_SHIFT (19U)
7554/*! INT19 - Interrupt Request 19
7555 * 0b0..The interrupt request for corresponding channel is cleared
7556 * 0b1..The interrupt request for corresponding channel is active
7557 */
7558#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
7559#define DMA_INT_INT20_MASK (0x100000U)
7560#define DMA_INT_INT20_SHIFT (20U)
7561/*! INT20 - Interrupt Request 20
7562 * 0b0..The interrupt request for corresponding channel is cleared
7563 * 0b1..The interrupt request for corresponding channel is active
7564 */
7565#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
7566#define DMA_INT_INT21_MASK (0x200000U)
7567#define DMA_INT_INT21_SHIFT (21U)
7568/*! INT21 - Interrupt Request 21
7569 * 0b0..The interrupt request for corresponding channel is cleared
7570 * 0b1..The interrupt request for corresponding channel is active
7571 */
7572#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
7573#define DMA_INT_INT22_MASK (0x400000U)
7574#define DMA_INT_INT22_SHIFT (22U)
7575/*! INT22 - Interrupt Request 22
7576 * 0b0..The interrupt request for corresponding channel is cleared
7577 * 0b1..The interrupt request for corresponding channel is active
7578 */
7579#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
7580#define DMA_INT_INT23_MASK (0x800000U)
7581#define DMA_INT_INT23_SHIFT (23U)
7582/*! INT23 - Interrupt Request 23
7583 * 0b0..The interrupt request for corresponding channel is cleared
7584 * 0b1..The interrupt request for corresponding channel is active
7585 */
7586#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
7587#define DMA_INT_INT24_MASK (0x1000000U)
7588#define DMA_INT_INT24_SHIFT (24U)
7589/*! INT24 - Interrupt Request 24
7590 * 0b0..The interrupt request for corresponding channel is cleared
7591 * 0b1..The interrupt request for corresponding channel is active
7592 */
7593#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
7594#define DMA_INT_INT25_MASK (0x2000000U)
7595#define DMA_INT_INT25_SHIFT (25U)
7596/*! INT25 - Interrupt Request 25
7597 * 0b0..The interrupt request for corresponding channel is cleared
7598 * 0b1..The interrupt request for corresponding channel is active
7599 */
7600#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
7601#define DMA_INT_INT26_MASK (0x4000000U)
7602#define DMA_INT_INT26_SHIFT (26U)
7603/*! INT26 - Interrupt Request 26
7604 * 0b0..The interrupt request for corresponding channel is cleared
7605 * 0b1..The interrupt request for corresponding channel is active
7606 */
7607#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
7608#define DMA_INT_INT27_MASK (0x8000000U)
7609#define DMA_INT_INT27_SHIFT (27U)
7610/*! INT27 - Interrupt Request 27
7611 * 0b0..The interrupt request for corresponding channel is cleared
7612 * 0b1..The interrupt request for corresponding channel is active
7613 */
7614#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
7615#define DMA_INT_INT28_MASK (0x10000000U)
7616#define DMA_INT_INT28_SHIFT (28U)
7617/*! INT28 - Interrupt Request 28
7618 * 0b0..The interrupt request for corresponding channel is cleared
7619 * 0b1..The interrupt request for corresponding channel is active
7620 */
7621#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
7622#define DMA_INT_INT29_MASK (0x20000000U)
7623#define DMA_INT_INT29_SHIFT (29U)
7624/*! INT29 - Interrupt Request 29
7625 * 0b0..The interrupt request for corresponding channel is cleared
7626 * 0b1..The interrupt request for corresponding channel is active
7627 */
7628#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
7629#define DMA_INT_INT30_MASK (0x40000000U)
7630#define DMA_INT_INT30_SHIFT (30U)
7631/*! INT30 - Interrupt Request 30
7632 * 0b0..The interrupt request for corresponding channel is cleared
7633 * 0b1..The interrupt request for corresponding channel is active
7634 */
7635#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
7636#define DMA_INT_INT31_MASK (0x80000000U)
7637#define DMA_INT_INT31_SHIFT (31U)
7638/*! INT31 - Interrupt Request 31
7639 * 0b0..The interrupt request for corresponding channel is cleared
7640 * 0b1..The interrupt request for corresponding channel is active
7641 */
7642#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
7643/*! @} */
7644
7645/*! @name ERR - Error Register */
7646/*! @{ */
7647#define DMA_ERR_ERR0_MASK (0x1U)
7648#define DMA_ERR_ERR0_SHIFT (0U)
7649/*! ERR0 - Error In Channel 0
7650 * 0b0..An error in this channel has not occurred
7651 * 0b1..An error in this channel has occurred
7652 */
7653#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
7654#define DMA_ERR_ERR1_MASK (0x2U)
7655#define DMA_ERR_ERR1_SHIFT (1U)
7656/*! ERR1 - Error In Channel 1
7657 * 0b0..An error in this channel has not occurred
7658 * 0b1..An error in this channel has occurred
7659 */
7660#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
7661#define DMA_ERR_ERR2_MASK (0x4U)
7662#define DMA_ERR_ERR2_SHIFT (2U)
7663/*! ERR2 - Error In Channel 2
7664 * 0b0..An error in this channel has not occurred
7665 * 0b1..An error in this channel has occurred
7666 */
7667#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
7668#define DMA_ERR_ERR3_MASK (0x8U)
7669#define DMA_ERR_ERR3_SHIFT (3U)
7670/*! ERR3 - Error In Channel 3
7671 * 0b0..An error in this channel has not occurred
7672 * 0b1..An error in this channel has occurred
7673 */
7674#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
7675#define DMA_ERR_ERR4_MASK (0x10U)
7676#define DMA_ERR_ERR4_SHIFT (4U)
7677/*! ERR4 - Error In Channel 4
7678 * 0b0..An error in this channel has not occurred
7679 * 0b1..An error in this channel has occurred
7680 */
7681#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
7682#define DMA_ERR_ERR5_MASK (0x20U)
7683#define DMA_ERR_ERR5_SHIFT (5U)
7684/*! ERR5 - Error In Channel 5
7685 * 0b0..An error in this channel has not occurred
7686 * 0b1..An error in this channel has occurred
7687 */
7688#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
7689#define DMA_ERR_ERR6_MASK (0x40U)
7690#define DMA_ERR_ERR6_SHIFT (6U)
7691/*! ERR6 - Error In Channel 6
7692 * 0b0..An error in this channel has not occurred
7693 * 0b1..An error in this channel has occurred
7694 */
7695#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
7696#define DMA_ERR_ERR7_MASK (0x80U)
7697#define DMA_ERR_ERR7_SHIFT (7U)
7698/*! ERR7 - Error In Channel 7
7699 * 0b0..An error in this channel has not occurred
7700 * 0b1..An error in this channel has occurred
7701 */
7702#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
7703#define DMA_ERR_ERR8_MASK (0x100U)
7704#define DMA_ERR_ERR8_SHIFT (8U)
7705/*! ERR8 - Error In Channel 8
7706 * 0b0..An error in this channel has not occurred
7707 * 0b1..An error in this channel has occurred
7708 */
7709#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
7710#define DMA_ERR_ERR9_MASK (0x200U)
7711#define DMA_ERR_ERR9_SHIFT (9U)
7712/*! ERR9 - Error In Channel 9
7713 * 0b0..An error in this channel has not occurred
7714 * 0b1..An error in this channel has occurred
7715 */
7716#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
7717#define DMA_ERR_ERR10_MASK (0x400U)
7718#define DMA_ERR_ERR10_SHIFT (10U)
7719/*! ERR10 - Error In Channel 10
7720 * 0b0..An error in this channel has not occurred
7721 * 0b1..An error in this channel has occurred
7722 */
7723#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
7724#define DMA_ERR_ERR11_MASK (0x800U)
7725#define DMA_ERR_ERR11_SHIFT (11U)
7726/*! ERR11 - Error In Channel 11
7727 * 0b0..An error in this channel has not occurred
7728 * 0b1..An error in this channel has occurred
7729 */
7730#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
7731#define DMA_ERR_ERR12_MASK (0x1000U)
7732#define DMA_ERR_ERR12_SHIFT (12U)
7733/*! ERR12 - Error In Channel 12
7734 * 0b0..An error in this channel has not occurred
7735 * 0b1..An error in this channel has occurred
7736 */
7737#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
7738#define DMA_ERR_ERR13_MASK (0x2000U)
7739#define DMA_ERR_ERR13_SHIFT (13U)
7740/*! ERR13 - Error In Channel 13
7741 * 0b0..An error in this channel has not occurred
7742 * 0b1..An error in this channel has occurred
7743 */
7744#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
7745#define DMA_ERR_ERR14_MASK (0x4000U)
7746#define DMA_ERR_ERR14_SHIFT (14U)
7747/*! ERR14 - Error In Channel 14
7748 * 0b0..An error in this channel has not occurred
7749 * 0b1..An error in this channel has occurred
7750 */
7751#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
7752#define DMA_ERR_ERR15_MASK (0x8000U)
7753#define DMA_ERR_ERR15_SHIFT (15U)
7754/*! ERR15 - Error In Channel 15
7755 * 0b0..An error in this channel has not occurred
7756 * 0b1..An error in this channel has occurred
7757 */
7758#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
7759#define DMA_ERR_ERR16_MASK (0x10000U)
7760#define DMA_ERR_ERR16_SHIFT (16U)
7761/*! ERR16 - Error In Channel 16
7762 * 0b0..An error in this channel has not occurred
7763 * 0b1..An error in this channel has occurred
7764 */
7765#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
7766#define DMA_ERR_ERR17_MASK (0x20000U)
7767#define DMA_ERR_ERR17_SHIFT (17U)
7768/*! ERR17 - Error In Channel 17
7769 * 0b0..An error in this channel has not occurred
7770 * 0b1..An error in this channel has occurred
7771 */
7772#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
7773#define DMA_ERR_ERR18_MASK (0x40000U)
7774#define DMA_ERR_ERR18_SHIFT (18U)
7775/*! ERR18 - Error In Channel 18
7776 * 0b0..An error in this channel has not occurred
7777 * 0b1..An error in this channel has occurred
7778 */
7779#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
7780#define DMA_ERR_ERR19_MASK (0x80000U)
7781#define DMA_ERR_ERR19_SHIFT (19U)
7782/*! ERR19 - Error In Channel 19
7783 * 0b0..An error in this channel has not occurred
7784 * 0b1..An error in this channel has occurred
7785 */
7786#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
7787#define DMA_ERR_ERR20_MASK (0x100000U)
7788#define DMA_ERR_ERR20_SHIFT (20U)
7789/*! ERR20 - Error In Channel 20
7790 * 0b0..An error in this channel has not occurred
7791 * 0b1..An error in this channel has occurred
7792 */
7793#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
7794#define DMA_ERR_ERR21_MASK (0x200000U)
7795#define DMA_ERR_ERR21_SHIFT (21U)
7796/*! ERR21 - Error In Channel 21
7797 * 0b0..An error in this channel has not occurred
7798 * 0b1..An error in this channel has occurred
7799 */
7800#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
7801#define DMA_ERR_ERR22_MASK (0x400000U)
7802#define DMA_ERR_ERR22_SHIFT (22U)
7803/*! ERR22 - Error In Channel 22
7804 * 0b0..An error in this channel has not occurred
7805 * 0b1..An error in this channel has occurred
7806 */
7807#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
7808#define DMA_ERR_ERR23_MASK (0x800000U)
7809#define DMA_ERR_ERR23_SHIFT (23U)
7810/*! ERR23 - Error In Channel 23
7811 * 0b0..An error in this channel has not occurred
7812 * 0b1..An error in this channel has occurred
7813 */
7814#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
7815#define DMA_ERR_ERR24_MASK (0x1000000U)
7816#define DMA_ERR_ERR24_SHIFT (24U)
7817/*! ERR24 - Error In Channel 24
7818 * 0b0..An error in this channel has not occurred
7819 * 0b1..An error in this channel has occurred
7820 */
7821#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
7822#define DMA_ERR_ERR25_MASK (0x2000000U)
7823#define DMA_ERR_ERR25_SHIFT (25U)
7824/*! ERR25 - Error In Channel 25
7825 * 0b0..An error in this channel has not occurred
7826 * 0b1..An error in this channel has occurred
7827 */
7828#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
7829#define DMA_ERR_ERR26_MASK (0x4000000U)
7830#define DMA_ERR_ERR26_SHIFT (26U)
7831/*! ERR26 - Error In Channel 26
7832 * 0b0..An error in this channel has not occurred
7833 * 0b1..An error in this channel has occurred
7834 */
7835#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
7836#define DMA_ERR_ERR27_MASK (0x8000000U)
7837#define DMA_ERR_ERR27_SHIFT (27U)
7838/*! ERR27 - Error In Channel 27
7839 * 0b0..An error in this channel has not occurred
7840 * 0b1..An error in this channel has occurred
7841 */
7842#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
7843#define DMA_ERR_ERR28_MASK (0x10000000U)
7844#define DMA_ERR_ERR28_SHIFT (28U)
7845/*! ERR28 - Error In Channel 28
7846 * 0b0..An error in this channel has not occurred
7847 * 0b1..An error in this channel has occurred
7848 */
7849#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
7850#define DMA_ERR_ERR29_MASK (0x20000000U)
7851#define DMA_ERR_ERR29_SHIFT (29U)
7852/*! ERR29 - Error In Channel 29
7853 * 0b0..An error in this channel has not occurred
7854 * 0b1..An error in this channel has occurred
7855 */
7856#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
7857#define DMA_ERR_ERR30_MASK (0x40000000U)
7858#define DMA_ERR_ERR30_SHIFT (30U)
7859/*! ERR30 - Error In Channel 30
7860 * 0b0..An error in this channel has not occurred
7861 * 0b1..An error in this channel has occurred
7862 */
7863#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
7864#define DMA_ERR_ERR31_MASK (0x80000000U)
7865#define DMA_ERR_ERR31_SHIFT (31U)
7866/*! ERR31 - Error In Channel 31
7867 * 0b0..An error in this channel has not occurred
7868 * 0b1..An error in this channel has occurred
7869 */
7870#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
7871/*! @} */
7872
7873/*! @name HRS - Hardware Request Status Register */
7874/*! @{ */
7875#define DMA_HRS_HRS0_MASK (0x1U)
7876#define DMA_HRS_HRS0_SHIFT (0U)
7877/*! HRS0 - Hardware Request Status Channel 0
7878 * 0b0..A hardware service request for channel 0 is not present
7879 * 0b1..A hardware service request for channel 0 is present
7880 */
7881#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
7882#define DMA_HRS_HRS1_MASK (0x2U)
7883#define DMA_HRS_HRS1_SHIFT (1U)
7884/*! HRS1 - Hardware Request Status Channel 1
7885 * 0b0..A hardware service request for channel 1 is not present
7886 * 0b1..A hardware service request for channel 1 is present
7887 */
7888#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
7889#define DMA_HRS_HRS2_MASK (0x4U)
7890#define DMA_HRS_HRS2_SHIFT (2U)
7891/*! HRS2 - Hardware Request Status Channel 2
7892 * 0b0..A hardware service request for channel 2 is not present
7893 * 0b1..A hardware service request for channel 2 is present
7894 */
7895#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
7896#define DMA_HRS_HRS3_MASK (0x8U)
7897#define DMA_HRS_HRS3_SHIFT (3U)
7898/*! HRS3 - Hardware Request Status Channel 3
7899 * 0b0..A hardware service request for channel 3 is not present
7900 * 0b1..A hardware service request for channel 3 is present
7901 */
7902#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
7903#define DMA_HRS_HRS4_MASK (0x10U)
7904#define DMA_HRS_HRS4_SHIFT (4U)
7905/*! HRS4 - Hardware Request Status Channel 4
7906 * 0b0..A hardware service request for channel 4 is not present
7907 * 0b1..A hardware service request for channel 4 is present
7908 */
7909#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
7910#define DMA_HRS_HRS5_MASK (0x20U)
7911#define DMA_HRS_HRS5_SHIFT (5U)
7912/*! HRS5 - Hardware Request Status Channel 5
7913 * 0b0..A hardware service request for channel 5 is not present
7914 * 0b1..A hardware service request for channel 5 is present
7915 */
7916#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
7917#define DMA_HRS_HRS6_MASK (0x40U)
7918#define DMA_HRS_HRS6_SHIFT (6U)
7919/*! HRS6 - Hardware Request Status Channel 6
7920 * 0b0..A hardware service request for channel 6 is not present
7921 * 0b1..A hardware service request for channel 6 is present
7922 */
7923#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
7924#define DMA_HRS_HRS7_MASK (0x80U)
7925#define DMA_HRS_HRS7_SHIFT (7U)
7926/*! HRS7 - Hardware Request Status Channel 7
7927 * 0b0..A hardware service request for channel 7 is not present
7928 * 0b1..A hardware service request for channel 7 is present
7929 */
7930#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
7931#define DMA_HRS_HRS8_MASK (0x100U)
7932#define DMA_HRS_HRS8_SHIFT (8U)
7933/*! HRS8 - Hardware Request Status Channel 8
7934 * 0b0..A hardware service request for channel 8 is not present
7935 * 0b1..A hardware service request for channel 8 is present
7936 */
7937#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
7938#define DMA_HRS_HRS9_MASK (0x200U)
7939#define DMA_HRS_HRS9_SHIFT (9U)
7940/*! HRS9 - Hardware Request Status Channel 9
7941 * 0b0..A hardware service request for channel 9 is not present
7942 * 0b1..A hardware service request for channel 9 is present
7943 */
7944#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
7945#define DMA_HRS_HRS10_MASK (0x400U)
7946#define DMA_HRS_HRS10_SHIFT (10U)
7947/*! HRS10 - Hardware Request Status Channel 10
7948 * 0b0..A hardware service request for channel 10 is not present
7949 * 0b1..A hardware service request for channel 10 is present
7950 */
7951#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
7952#define DMA_HRS_HRS11_MASK (0x800U)
7953#define DMA_HRS_HRS11_SHIFT (11U)
7954/*! HRS11 - Hardware Request Status Channel 11
7955 * 0b0..A hardware service request for channel 11 is not present
7956 * 0b1..A hardware service request for channel 11 is present
7957 */
7958#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
7959#define DMA_HRS_HRS12_MASK (0x1000U)
7960#define DMA_HRS_HRS12_SHIFT (12U)
7961/*! HRS12 - Hardware Request Status Channel 12
7962 * 0b0..A hardware service request for channel 12 is not present
7963 * 0b1..A hardware service request for channel 12 is present
7964 */
7965#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
7966#define DMA_HRS_HRS13_MASK (0x2000U)
7967#define DMA_HRS_HRS13_SHIFT (13U)
7968/*! HRS13 - Hardware Request Status Channel 13
7969 * 0b0..A hardware service request for channel 13 is not present
7970 * 0b1..A hardware service request for channel 13 is present
7971 */
7972#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
7973#define DMA_HRS_HRS14_MASK (0x4000U)
7974#define DMA_HRS_HRS14_SHIFT (14U)
7975/*! HRS14 - Hardware Request Status Channel 14
7976 * 0b0..A hardware service request for channel 14 is not present
7977 * 0b1..A hardware service request for channel 14 is present
7978 */
7979#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
7980#define DMA_HRS_HRS15_MASK (0x8000U)
7981#define DMA_HRS_HRS15_SHIFT (15U)
7982/*! HRS15 - Hardware Request Status Channel 15
7983 * 0b0..A hardware service request for channel 15 is not present
7984 * 0b1..A hardware service request for channel 15 is present
7985 */
7986#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
7987#define DMA_HRS_HRS16_MASK (0x10000U)
7988#define DMA_HRS_HRS16_SHIFT (16U)
7989/*! HRS16 - Hardware Request Status Channel 16
7990 * 0b0..A hardware service request for channel 16 is not present
7991 * 0b1..A hardware service request for channel 16 is present
7992 */
7993#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
7994#define DMA_HRS_HRS17_MASK (0x20000U)
7995#define DMA_HRS_HRS17_SHIFT (17U)
7996/*! HRS17 - Hardware Request Status Channel 17
7997 * 0b0..A hardware service request for channel 17 is not present
7998 * 0b1..A hardware service request for channel 17 is present
7999 */
8000#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
8001#define DMA_HRS_HRS18_MASK (0x40000U)
8002#define DMA_HRS_HRS18_SHIFT (18U)
8003/*! HRS18 - Hardware Request Status Channel 18
8004 * 0b0..A hardware service request for channel 18 is not present
8005 * 0b1..A hardware service request for channel 18 is present
8006 */
8007#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
8008#define DMA_HRS_HRS19_MASK (0x80000U)
8009#define DMA_HRS_HRS19_SHIFT (19U)
8010/*! HRS19 - Hardware Request Status Channel 19
8011 * 0b0..A hardware service request for channel 19 is not present
8012 * 0b1..A hardware service request for channel 19 is present
8013 */
8014#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
8015#define DMA_HRS_HRS20_MASK (0x100000U)
8016#define DMA_HRS_HRS20_SHIFT (20U)
8017/*! HRS20 - Hardware Request Status Channel 20
8018 * 0b0..A hardware service request for channel 20 is not present
8019 * 0b1..A hardware service request for channel 20 is present
8020 */
8021#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
8022#define DMA_HRS_HRS21_MASK (0x200000U)
8023#define DMA_HRS_HRS21_SHIFT (21U)
8024/*! HRS21 - Hardware Request Status Channel 21
8025 * 0b0..A hardware service request for channel 21 is not present
8026 * 0b1..A hardware service request for channel 21 is present
8027 */
8028#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
8029#define DMA_HRS_HRS22_MASK (0x400000U)
8030#define DMA_HRS_HRS22_SHIFT (22U)
8031/*! HRS22 - Hardware Request Status Channel 22
8032 * 0b0..A hardware service request for channel 22 is not present
8033 * 0b1..A hardware service request for channel 22 is present
8034 */
8035#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
8036#define DMA_HRS_HRS23_MASK (0x800000U)
8037#define DMA_HRS_HRS23_SHIFT (23U)
8038/*! HRS23 - Hardware Request Status Channel 23
8039 * 0b0..A hardware service request for channel 23 is not present
8040 * 0b1..A hardware service request for channel 23 is present
8041 */
8042#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
8043#define DMA_HRS_HRS24_MASK (0x1000000U)
8044#define DMA_HRS_HRS24_SHIFT (24U)
8045/*! HRS24 - Hardware Request Status Channel 24
8046 * 0b0..A hardware service request for channel 24 is not present
8047 * 0b1..A hardware service request for channel 24 is present
8048 */
8049#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
8050#define DMA_HRS_HRS25_MASK (0x2000000U)
8051#define DMA_HRS_HRS25_SHIFT (25U)
8052/*! HRS25 - Hardware Request Status Channel 25
8053 * 0b0..A hardware service request for channel 25 is not present
8054 * 0b1..A hardware service request for channel 25 is present
8055 */
8056#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
8057#define DMA_HRS_HRS26_MASK (0x4000000U)
8058#define DMA_HRS_HRS26_SHIFT (26U)
8059/*! HRS26 - Hardware Request Status Channel 26
8060 * 0b0..A hardware service request for channel 26 is not present
8061 * 0b1..A hardware service request for channel 26 is present
8062 */
8063#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
8064#define DMA_HRS_HRS27_MASK (0x8000000U)
8065#define DMA_HRS_HRS27_SHIFT (27U)
8066/*! HRS27 - Hardware Request Status Channel 27
8067 * 0b0..A hardware service request for channel 27 is not present
8068 * 0b1..A hardware service request for channel 27 is present
8069 */
8070#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
8071#define DMA_HRS_HRS28_MASK (0x10000000U)
8072#define DMA_HRS_HRS28_SHIFT (28U)
8073/*! HRS28 - Hardware Request Status Channel 28
8074 * 0b0..A hardware service request for channel 28 is not present
8075 * 0b1..A hardware service request for channel 28 is present
8076 */
8077#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
8078#define DMA_HRS_HRS29_MASK (0x20000000U)
8079#define DMA_HRS_HRS29_SHIFT (29U)
8080/*! HRS29 - Hardware Request Status Channel 29
8081 * 0b0..A hardware service request for channel 29 is not preset
8082 * 0b1..A hardware service request for channel 29 is present
8083 */
8084#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
8085#define DMA_HRS_HRS30_MASK (0x40000000U)
8086#define DMA_HRS_HRS30_SHIFT (30U)
8087/*! HRS30 - Hardware Request Status Channel 30
8088 * 0b0..A hardware service request for channel 30 is not present
8089 * 0b1..A hardware service request for for channel 30 is present
8090 */
8091#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
8092#define DMA_HRS_HRS31_MASK (0x80000000U)
8093#define DMA_HRS_HRS31_SHIFT (31U)
8094/*! HRS31 - Hardware Request Status Channel 31
8095 * 0b0..A hardware service request for channel 31 is not present
8096 * 0b1..A hardware service request for channel 31 is present
8097 */
8098#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
8099/*! @} */
8100
8101/*! @name EARS - Enable Asynchronous Request in Stop Register */
8102/*! @{ */
8103#define DMA_EARS_EDREQ_0_MASK (0x1U)
8104#define DMA_EARS_EDREQ_0_SHIFT (0U)
8105/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0.
8106 * 0b0..Disable asynchronous DMA request for channel 0.
8107 * 0b1..Enable asynchronous DMA request for channel 0.
8108 */
8109#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
8110#define DMA_EARS_EDREQ_1_MASK (0x2U)
8111#define DMA_EARS_EDREQ_1_SHIFT (1U)
8112/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1.
8113 * 0b0..Disable asynchronous DMA request for channel 1
8114 * 0b1..Enable asynchronous DMA request for channel 1.
8115 */
8116#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
8117#define DMA_EARS_EDREQ_2_MASK (0x4U)
8118#define DMA_EARS_EDREQ_2_SHIFT (2U)
8119/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2.
8120 * 0b0..Disable asynchronous DMA request for channel 2.
8121 * 0b1..Enable asynchronous DMA request for channel 2.
8122 */
8123#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
8124#define DMA_EARS_EDREQ_3_MASK (0x8U)
8125#define DMA_EARS_EDREQ_3_SHIFT (3U)
8126/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3.
8127 * 0b0..Disable asynchronous DMA request for channel 3.
8128 * 0b1..Enable asynchronous DMA request for channel 3.
8129 */
8130#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
8131#define DMA_EARS_EDREQ_4_MASK (0x10U)
8132#define DMA_EARS_EDREQ_4_SHIFT (4U)
8133/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4
8134 * 0b0..Disable asynchronous DMA request for channel 4.
8135 * 0b1..Enable asynchronous DMA request for channel 4.
8136 */
8137#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
8138#define DMA_EARS_EDREQ_5_MASK (0x20U)
8139#define DMA_EARS_EDREQ_5_SHIFT (5U)
8140/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5
8141 * 0b0..Disable asynchronous DMA request for channel 5.
8142 * 0b1..Enable asynchronous DMA request for channel 5.
8143 */
8144#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
8145#define DMA_EARS_EDREQ_6_MASK (0x40U)
8146#define DMA_EARS_EDREQ_6_SHIFT (6U)
8147/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6
8148 * 0b0..Disable asynchronous DMA request for channel 6.
8149 * 0b1..Enable asynchronous DMA request for channel 6.
8150 */
8151#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
8152#define DMA_EARS_EDREQ_7_MASK (0x80U)
8153#define DMA_EARS_EDREQ_7_SHIFT (7U)
8154/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7
8155 * 0b0..Disable asynchronous DMA request for channel 7.
8156 * 0b1..Enable asynchronous DMA request for channel 7.
8157 */
8158#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
8159#define DMA_EARS_EDREQ_8_MASK (0x100U)
8160#define DMA_EARS_EDREQ_8_SHIFT (8U)
8161/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8
8162 * 0b0..Disable asynchronous DMA request for channel 8.
8163 * 0b1..Enable asynchronous DMA request for channel 8.
8164 */
8165#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
8166#define DMA_EARS_EDREQ_9_MASK (0x200U)
8167#define DMA_EARS_EDREQ_9_SHIFT (9U)
8168/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9
8169 * 0b0..Disable asynchronous DMA request for channel 9.
8170 * 0b1..Enable asynchronous DMA request for channel 9.
8171 */
8172#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
8173#define DMA_EARS_EDREQ_10_MASK (0x400U)
8174#define DMA_EARS_EDREQ_10_SHIFT (10U)
8175/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10
8176 * 0b0..Disable asynchronous DMA request for channel 10.
8177 * 0b1..Enable asynchronous DMA request for channel 10.
8178 */
8179#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
8180#define DMA_EARS_EDREQ_11_MASK (0x800U)
8181#define DMA_EARS_EDREQ_11_SHIFT (11U)
8182/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11
8183 * 0b0..Disable asynchronous DMA request for channel 11.
8184 * 0b1..Enable asynchronous DMA request for channel 11.
8185 */
8186#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
8187#define DMA_EARS_EDREQ_12_MASK (0x1000U)
8188#define DMA_EARS_EDREQ_12_SHIFT (12U)
8189/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12
8190 * 0b0..Disable asynchronous DMA request for channel 12.
8191 * 0b1..Enable asynchronous DMA request for channel 12.
8192 */
8193#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
8194#define DMA_EARS_EDREQ_13_MASK (0x2000U)
8195#define DMA_EARS_EDREQ_13_SHIFT (13U)
8196/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13
8197 * 0b0..Disable asynchronous DMA request for channel 13.
8198 * 0b1..Enable asynchronous DMA request for channel 13.
8199 */
8200#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
8201#define DMA_EARS_EDREQ_14_MASK (0x4000U)
8202#define DMA_EARS_EDREQ_14_SHIFT (14U)
8203/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14
8204 * 0b0..Disable asynchronous DMA request for channel 14.
8205 * 0b1..Enable asynchronous DMA request for channel 14.
8206 */
8207#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
8208#define DMA_EARS_EDREQ_15_MASK (0x8000U)
8209#define DMA_EARS_EDREQ_15_SHIFT (15U)
8210/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15
8211 * 0b0..Disable asynchronous DMA request for channel 15.
8212 * 0b1..Enable asynchronous DMA request for channel 15.
8213 */
8214#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
8215#define DMA_EARS_EDREQ_16_MASK (0x10000U)
8216#define DMA_EARS_EDREQ_16_SHIFT (16U)
8217/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16
8218 * 0b0..Disable asynchronous DMA request for channel 16
8219 * 0b1..Enable asynchronous DMA request for channel 16
8220 */
8221#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
8222#define DMA_EARS_EDREQ_17_MASK (0x20000U)
8223#define DMA_EARS_EDREQ_17_SHIFT (17U)
8224/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17
8225 * 0b0..Disable asynchronous DMA request for channel 17
8226 * 0b1..Enable asynchronous DMA request for channel 17
8227 */
8228#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
8229#define DMA_EARS_EDREQ_18_MASK (0x40000U)
8230#define DMA_EARS_EDREQ_18_SHIFT (18U)
8231/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18
8232 * 0b0..Disable asynchronous DMA request for channel 18
8233 * 0b1..Enable asynchronous DMA request for channel 18
8234 */
8235#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
8236#define DMA_EARS_EDREQ_19_MASK (0x80000U)
8237#define DMA_EARS_EDREQ_19_SHIFT (19U)
8238/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19
8239 * 0b0..Disable asynchronous DMA request for channel 19
8240 * 0b1..Enable asynchronous DMA request for channel 19
8241 */
8242#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
8243#define DMA_EARS_EDREQ_20_MASK (0x100000U)
8244#define DMA_EARS_EDREQ_20_SHIFT (20U)
8245/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20
8246 * 0b0..Disable asynchronous DMA request for channel 20
8247 * 0b1..Enable asynchronous DMA request for channel 20
8248 */
8249#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
8250#define DMA_EARS_EDREQ_21_MASK (0x200000U)
8251#define DMA_EARS_EDREQ_21_SHIFT (21U)
8252/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21
8253 * 0b0..Disable asynchronous DMA request for channel 21
8254 * 0b1..Enable asynchronous DMA request for channel 21
8255 */
8256#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
8257#define DMA_EARS_EDREQ_22_MASK (0x400000U)
8258#define DMA_EARS_EDREQ_22_SHIFT (22U)
8259/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22
8260 * 0b0..Disable asynchronous DMA request for channel 22
8261 * 0b1..Enable asynchronous DMA request for channel 22
8262 */
8263#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
8264#define DMA_EARS_EDREQ_23_MASK (0x800000U)
8265#define DMA_EARS_EDREQ_23_SHIFT (23U)
8266/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23
8267 * 0b0..Disable asynchronous DMA request for channel 23
8268 * 0b1..Enable asynchronous DMA request for channel 23
8269 */
8270#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
8271#define DMA_EARS_EDREQ_24_MASK (0x1000000U)
8272#define DMA_EARS_EDREQ_24_SHIFT (24U)
8273/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24
8274 * 0b0..Disable asynchronous DMA request for channel 24
8275 * 0b1..Enable asynchronous DMA request for channel 24
8276 */
8277#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
8278#define DMA_EARS_EDREQ_25_MASK (0x2000000U)
8279#define DMA_EARS_EDREQ_25_SHIFT (25U)
8280/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25
8281 * 0b0..Disable asynchronous DMA request for channel 25
8282 * 0b1..Enable asynchronous DMA request for channel 25
8283 */
8284#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
8285#define DMA_EARS_EDREQ_26_MASK (0x4000000U)
8286#define DMA_EARS_EDREQ_26_SHIFT (26U)
8287/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26
8288 * 0b0..Disable asynchronous DMA request for channel 26
8289 * 0b1..Enable asynchronous DMA request for channel 26
8290 */
8291#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
8292#define DMA_EARS_EDREQ_27_MASK (0x8000000U)
8293#define DMA_EARS_EDREQ_27_SHIFT (27U)
8294/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27
8295 * 0b0..Disable asynchronous DMA request for channel 27
8296 * 0b1..Enable asynchronous DMA request for channel 27
8297 */
8298#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
8299#define DMA_EARS_EDREQ_28_MASK (0x10000000U)
8300#define DMA_EARS_EDREQ_28_SHIFT (28U)
8301/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28
8302 * 0b0..Disable asynchronous DMA request for channel 28
8303 * 0b1..Enable asynchronous DMA request for channel 28
8304 */
8305#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
8306#define DMA_EARS_EDREQ_29_MASK (0x20000000U)
8307#define DMA_EARS_EDREQ_29_SHIFT (29U)
8308/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29
8309 * 0b0..Disable asynchronous DMA request for channel 29
8310 * 0b1..Enable asynchronous DMA request for channel 29
8311 */
8312#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
8313#define DMA_EARS_EDREQ_30_MASK (0x40000000U)
8314#define DMA_EARS_EDREQ_30_SHIFT (30U)
8315/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30
8316 * 0b0..Disable asynchronous DMA request for channel 30
8317 * 0b1..Enable asynchronous DMA request for channel 30
8318 */
8319#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
8320#define DMA_EARS_EDREQ_31_MASK (0x80000000U)
8321#define DMA_EARS_EDREQ_31_SHIFT (31U)
8322/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31
8323 * 0b0..Disable asynchronous DMA request for channel 31
8324 * 0b1..Enable asynchronous DMA request for channel 31
8325 */
8326#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
8327/*! @} */
8328
8329/*! @name DCHPRI3 - Channel n Priority Register */
8330/*! @{ */
8331#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
8332#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
8333#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
8334#define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
8335#define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
8336#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
8337#define DMA_DCHPRI3_DPA_MASK (0x40U)
8338#define DMA_DCHPRI3_DPA_SHIFT (6U)
8339/*! DPA - Disable Preempt Ability.
8340 * 0b0..Channel n can suspend a lower priority channel.
8341 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8342 */
8343#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
8344#define DMA_DCHPRI3_ECP_MASK (0x80U)
8345#define DMA_DCHPRI3_ECP_SHIFT (7U)
8346/*! ECP - Enable Channel Preemption.
8347 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8348 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8349 */
8350#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
8351/*! @} */
8352
8353/*! @name DCHPRI2 - Channel n Priority Register */
8354/*! @{ */
8355#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
8356#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
8357#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
8358#define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
8359#define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
8360#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
8361#define DMA_DCHPRI2_DPA_MASK (0x40U)
8362#define DMA_DCHPRI2_DPA_SHIFT (6U)
8363/*! DPA - Disable Preempt Ability.
8364 * 0b0..Channel n can suspend a lower priority channel.
8365 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8366 */
8367#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
8368#define DMA_DCHPRI2_ECP_MASK (0x80U)
8369#define DMA_DCHPRI2_ECP_SHIFT (7U)
8370/*! ECP - Enable Channel Preemption.
8371 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8372 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8373 */
8374#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
8375/*! @} */
8376
8377/*! @name DCHPRI1 - Channel n Priority Register */
8378/*! @{ */
8379#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
8380#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
8381#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
8382#define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
8383#define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
8384#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
8385#define DMA_DCHPRI1_DPA_MASK (0x40U)
8386#define DMA_DCHPRI1_DPA_SHIFT (6U)
8387/*! DPA - Disable Preempt Ability.
8388 * 0b0..Channel n can suspend a lower priority channel.
8389 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8390 */
8391#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
8392#define DMA_DCHPRI1_ECP_MASK (0x80U)
8393#define DMA_DCHPRI1_ECP_SHIFT (7U)
8394/*! ECP - Enable Channel Preemption.
8395 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8396 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8397 */
8398#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
8399/*! @} */
8400
8401/*! @name DCHPRI0 - Channel n Priority Register */
8402/*! @{ */
8403#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
8404#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
8405#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
8406#define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
8407#define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
8408#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
8409#define DMA_DCHPRI0_DPA_MASK (0x40U)
8410#define DMA_DCHPRI0_DPA_SHIFT (6U)
8411/*! DPA - Disable Preempt Ability.
8412 * 0b0..Channel n can suspend a lower priority channel.
8413 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8414 */
8415#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
8416#define DMA_DCHPRI0_ECP_MASK (0x80U)
8417#define DMA_DCHPRI0_ECP_SHIFT (7U)
8418/*! ECP - Enable Channel Preemption.
8419 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8420 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8421 */
8422#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
8423/*! @} */
8424
8425/*! @name DCHPRI7 - Channel n Priority Register */
8426/*! @{ */
8427#define DMA_DCHPRI7_CHPRI_MASK (0xFU)
8428#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
8429#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
8430#define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
8431#define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
8432#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
8433#define DMA_DCHPRI7_DPA_MASK (0x40U)
8434#define DMA_DCHPRI7_DPA_SHIFT (6U)
8435/*! DPA - Disable Preempt Ability.
8436 * 0b0..Channel n can suspend a lower priority channel.
8437 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8438 */
8439#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
8440#define DMA_DCHPRI7_ECP_MASK (0x80U)
8441#define DMA_DCHPRI7_ECP_SHIFT (7U)
8442/*! ECP - Enable Channel Preemption.
8443 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8444 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8445 */
8446#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
8447/*! @} */
8448
8449/*! @name DCHPRI6 - Channel n Priority Register */
8450/*! @{ */
8451#define DMA_DCHPRI6_CHPRI_MASK (0xFU)
8452#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
8453#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
8454#define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
8455#define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
8456#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
8457#define DMA_DCHPRI6_DPA_MASK (0x40U)
8458#define DMA_DCHPRI6_DPA_SHIFT (6U)
8459/*! DPA - Disable Preempt Ability.
8460 * 0b0..Channel n can suspend a lower priority channel.
8461 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8462 */
8463#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
8464#define DMA_DCHPRI6_ECP_MASK (0x80U)
8465#define DMA_DCHPRI6_ECP_SHIFT (7U)
8466/*! ECP - Enable Channel Preemption.
8467 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8468 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8469 */
8470#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
8471/*! @} */
8472
8473/*! @name DCHPRI5 - Channel n Priority Register */
8474/*! @{ */
8475#define DMA_DCHPRI5_CHPRI_MASK (0xFU)
8476#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
8477#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
8478#define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
8479#define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
8480#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
8481#define DMA_DCHPRI5_DPA_MASK (0x40U)
8482#define DMA_DCHPRI5_DPA_SHIFT (6U)
8483/*! DPA - Disable Preempt Ability.
8484 * 0b0..Channel n can suspend a lower priority channel.
8485 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8486 */
8487#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
8488#define DMA_DCHPRI5_ECP_MASK (0x80U)
8489#define DMA_DCHPRI5_ECP_SHIFT (7U)
8490/*! ECP - Enable Channel Preemption.
8491 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8492 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8493 */
8494#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
8495/*! @} */
8496
8497/*! @name DCHPRI4 - Channel n Priority Register */
8498/*! @{ */
8499#define DMA_DCHPRI4_CHPRI_MASK (0xFU)
8500#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
8501#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
8502#define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
8503#define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
8504#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
8505#define DMA_DCHPRI4_DPA_MASK (0x40U)
8506#define DMA_DCHPRI4_DPA_SHIFT (6U)
8507/*! DPA - Disable Preempt Ability.
8508 * 0b0..Channel n can suspend a lower priority channel.
8509 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8510 */
8511#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
8512#define DMA_DCHPRI4_ECP_MASK (0x80U)
8513#define DMA_DCHPRI4_ECP_SHIFT (7U)
8514/*! ECP - Enable Channel Preemption.
8515 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8516 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8517 */
8518#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
8519/*! @} */
8520
8521/*! @name DCHPRI11 - Channel n Priority Register */
8522/*! @{ */
8523#define DMA_DCHPRI11_CHPRI_MASK (0xFU)
8524#define DMA_DCHPRI11_CHPRI_SHIFT (0U)
8525#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
8526#define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
8527#define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
8528#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
8529#define DMA_DCHPRI11_DPA_MASK (0x40U)
8530#define DMA_DCHPRI11_DPA_SHIFT (6U)
8531/*! DPA - Disable Preempt Ability.
8532 * 0b0..Channel n can suspend a lower priority channel.
8533 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8534 */
8535#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
8536#define DMA_DCHPRI11_ECP_MASK (0x80U)
8537#define DMA_DCHPRI11_ECP_SHIFT (7U)
8538/*! ECP - Enable Channel Preemption.
8539 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8540 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8541 */
8542#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
8543/*! @} */
8544
8545/*! @name DCHPRI10 - Channel n Priority Register */
8546/*! @{ */
8547#define DMA_DCHPRI10_CHPRI_MASK (0xFU)
8548#define DMA_DCHPRI10_CHPRI_SHIFT (0U)
8549#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
8550#define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
8551#define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
8552#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
8553#define DMA_DCHPRI10_DPA_MASK (0x40U)
8554#define DMA_DCHPRI10_DPA_SHIFT (6U)
8555/*! DPA - Disable Preempt Ability.
8556 * 0b0..Channel n can suspend a lower priority channel.
8557 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8558 */
8559#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
8560#define DMA_DCHPRI10_ECP_MASK (0x80U)
8561#define DMA_DCHPRI10_ECP_SHIFT (7U)
8562/*! ECP - Enable Channel Preemption.
8563 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8564 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8565 */
8566#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
8567/*! @} */
8568
8569/*! @name DCHPRI9 - Channel n Priority Register */
8570/*! @{ */
8571#define DMA_DCHPRI9_CHPRI_MASK (0xFU)
8572#define DMA_DCHPRI9_CHPRI_SHIFT (0U)
8573#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
8574#define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
8575#define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
8576#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
8577#define DMA_DCHPRI9_DPA_MASK (0x40U)
8578#define DMA_DCHPRI9_DPA_SHIFT (6U)
8579/*! DPA - Disable Preempt Ability.
8580 * 0b0..Channel n can suspend a lower priority channel.
8581 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8582 */
8583#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
8584#define DMA_DCHPRI9_ECP_MASK (0x80U)
8585#define DMA_DCHPRI9_ECP_SHIFT (7U)
8586/*! ECP - Enable Channel Preemption.
8587 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8588 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8589 */
8590#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
8591/*! @} */
8592
8593/*! @name DCHPRI8 - Channel n Priority Register */
8594/*! @{ */
8595#define DMA_DCHPRI8_CHPRI_MASK (0xFU)
8596#define DMA_DCHPRI8_CHPRI_SHIFT (0U)
8597#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
8598#define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
8599#define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
8600#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
8601#define DMA_DCHPRI8_DPA_MASK (0x40U)
8602#define DMA_DCHPRI8_DPA_SHIFT (6U)
8603/*! DPA - Disable Preempt Ability.
8604 * 0b0..Channel n can suspend a lower priority channel.
8605 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8606 */
8607#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
8608#define DMA_DCHPRI8_ECP_MASK (0x80U)
8609#define DMA_DCHPRI8_ECP_SHIFT (7U)
8610/*! ECP - Enable Channel Preemption.
8611 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8612 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8613 */
8614#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
8615/*! @} */
8616
8617/*! @name DCHPRI15 - Channel n Priority Register */
8618/*! @{ */
8619#define DMA_DCHPRI15_CHPRI_MASK (0xFU)
8620#define DMA_DCHPRI15_CHPRI_SHIFT (0U)
8621#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
8622#define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
8623#define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
8624#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
8625#define DMA_DCHPRI15_DPA_MASK (0x40U)
8626#define DMA_DCHPRI15_DPA_SHIFT (6U)
8627/*! DPA - Disable Preempt Ability.
8628 * 0b0..Channel n can suspend a lower priority channel.
8629 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8630 */
8631#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
8632#define DMA_DCHPRI15_ECP_MASK (0x80U)
8633#define DMA_DCHPRI15_ECP_SHIFT (7U)
8634/*! ECP - Enable Channel Preemption.
8635 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8636 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8637 */
8638#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
8639/*! @} */
8640
8641/*! @name DCHPRI14 - Channel n Priority Register */
8642/*! @{ */
8643#define DMA_DCHPRI14_CHPRI_MASK (0xFU)
8644#define DMA_DCHPRI14_CHPRI_SHIFT (0U)
8645#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
8646#define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
8647#define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
8648#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
8649#define DMA_DCHPRI14_DPA_MASK (0x40U)
8650#define DMA_DCHPRI14_DPA_SHIFT (6U)
8651/*! DPA - Disable Preempt Ability.
8652 * 0b0..Channel n can suspend a lower priority channel.
8653 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8654 */
8655#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
8656#define DMA_DCHPRI14_ECP_MASK (0x80U)
8657#define DMA_DCHPRI14_ECP_SHIFT (7U)
8658/*! ECP - Enable Channel Preemption.
8659 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8660 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8661 */
8662#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
8663/*! @} */
8664
8665/*! @name DCHPRI13 - Channel n Priority Register */
8666/*! @{ */
8667#define DMA_DCHPRI13_CHPRI_MASK (0xFU)
8668#define DMA_DCHPRI13_CHPRI_SHIFT (0U)
8669#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
8670#define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
8671#define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
8672#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
8673#define DMA_DCHPRI13_DPA_MASK (0x40U)
8674#define DMA_DCHPRI13_DPA_SHIFT (6U)
8675/*! DPA - Disable Preempt Ability.
8676 * 0b0..Channel n can suspend a lower priority channel.
8677 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8678 */
8679#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
8680#define DMA_DCHPRI13_ECP_MASK (0x80U)
8681#define DMA_DCHPRI13_ECP_SHIFT (7U)
8682/*! ECP - Enable Channel Preemption.
8683 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8684 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8685 */
8686#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
8687/*! @} */
8688
8689/*! @name DCHPRI12 - Channel n Priority Register */
8690/*! @{ */
8691#define DMA_DCHPRI12_CHPRI_MASK (0xFU)
8692#define DMA_DCHPRI12_CHPRI_SHIFT (0U)
8693#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
8694#define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
8695#define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
8696#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
8697#define DMA_DCHPRI12_DPA_MASK (0x40U)
8698#define DMA_DCHPRI12_DPA_SHIFT (6U)
8699/*! DPA - Disable Preempt Ability.
8700 * 0b0..Channel n can suspend a lower priority channel.
8701 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8702 */
8703#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
8704#define DMA_DCHPRI12_ECP_MASK (0x80U)
8705#define DMA_DCHPRI12_ECP_SHIFT (7U)
8706/*! ECP - Enable Channel Preemption.
8707 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8708 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8709 */
8710#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
8711/*! @} */
8712
8713/*! @name DCHPRI19 - Channel n Priority Register */
8714/*! @{ */
8715#define DMA_DCHPRI19_CHPRI_MASK (0xFU)
8716#define DMA_DCHPRI19_CHPRI_SHIFT (0U)
8717#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
8718#define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
8719#define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
8720#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
8721#define DMA_DCHPRI19_DPA_MASK (0x40U)
8722#define DMA_DCHPRI19_DPA_SHIFT (6U)
8723/*! DPA - Disable Preempt Ability.
8724 * 0b0..Channel n can suspend a lower priority channel.
8725 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8726 */
8727#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
8728#define DMA_DCHPRI19_ECP_MASK (0x80U)
8729#define DMA_DCHPRI19_ECP_SHIFT (7U)
8730/*! ECP - Enable Channel Preemption.
8731 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8732 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8733 */
8734#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
8735/*! @} */
8736
8737/*! @name DCHPRI18 - Channel n Priority Register */
8738/*! @{ */
8739#define DMA_DCHPRI18_CHPRI_MASK (0xFU)
8740#define DMA_DCHPRI18_CHPRI_SHIFT (0U)
8741#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
8742#define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
8743#define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
8744#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
8745#define DMA_DCHPRI18_DPA_MASK (0x40U)
8746#define DMA_DCHPRI18_DPA_SHIFT (6U)
8747/*! DPA - Disable Preempt Ability.
8748 * 0b0..Channel n can suspend a lower priority channel.
8749 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8750 */
8751#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
8752#define DMA_DCHPRI18_ECP_MASK (0x80U)
8753#define DMA_DCHPRI18_ECP_SHIFT (7U)
8754/*! ECP - Enable Channel Preemption.
8755 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8756 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8757 */
8758#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
8759/*! @} */
8760
8761/*! @name DCHPRI17 - Channel n Priority Register */
8762/*! @{ */
8763#define DMA_DCHPRI17_CHPRI_MASK (0xFU)
8764#define DMA_DCHPRI17_CHPRI_SHIFT (0U)
8765#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
8766#define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
8767#define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
8768#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
8769#define DMA_DCHPRI17_DPA_MASK (0x40U)
8770#define DMA_DCHPRI17_DPA_SHIFT (6U)
8771/*! DPA - Disable Preempt Ability.
8772 * 0b0..Channel n can suspend a lower priority channel.
8773 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8774 */
8775#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
8776#define DMA_DCHPRI17_ECP_MASK (0x80U)
8777#define DMA_DCHPRI17_ECP_SHIFT (7U)
8778/*! ECP - Enable Channel Preemption.
8779 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8780 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8781 */
8782#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
8783/*! @} */
8784
8785/*! @name DCHPRI16 - Channel n Priority Register */
8786/*! @{ */
8787#define DMA_DCHPRI16_CHPRI_MASK (0xFU)
8788#define DMA_DCHPRI16_CHPRI_SHIFT (0U)
8789#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
8790#define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
8791#define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
8792#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
8793#define DMA_DCHPRI16_DPA_MASK (0x40U)
8794#define DMA_DCHPRI16_DPA_SHIFT (6U)
8795/*! DPA - Disable Preempt Ability.
8796 * 0b0..Channel n can suspend a lower priority channel.
8797 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8798 */
8799#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
8800#define DMA_DCHPRI16_ECP_MASK (0x80U)
8801#define DMA_DCHPRI16_ECP_SHIFT (7U)
8802/*! ECP - Enable Channel Preemption.
8803 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8804 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8805 */
8806#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
8807/*! @} */
8808
8809/*! @name DCHPRI23 - Channel n Priority Register */
8810/*! @{ */
8811#define DMA_DCHPRI23_CHPRI_MASK (0xFU)
8812#define DMA_DCHPRI23_CHPRI_SHIFT (0U)
8813#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
8814#define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
8815#define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
8816#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
8817#define DMA_DCHPRI23_DPA_MASK (0x40U)
8818#define DMA_DCHPRI23_DPA_SHIFT (6U)
8819/*! DPA - Disable Preempt Ability.
8820 * 0b0..Channel n can suspend a lower priority channel.
8821 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8822 */
8823#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
8824#define DMA_DCHPRI23_ECP_MASK (0x80U)
8825#define DMA_DCHPRI23_ECP_SHIFT (7U)
8826/*! ECP - Enable Channel Preemption.
8827 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8828 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8829 */
8830#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
8831/*! @} */
8832
8833/*! @name DCHPRI22 - Channel n Priority Register */
8834/*! @{ */
8835#define DMA_DCHPRI22_CHPRI_MASK (0xFU)
8836#define DMA_DCHPRI22_CHPRI_SHIFT (0U)
8837#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
8838#define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
8839#define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
8840#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
8841#define DMA_DCHPRI22_DPA_MASK (0x40U)
8842#define DMA_DCHPRI22_DPA_SHIFT (6U)
8843/*! DPA - Disable Preempt Ability.
8844 * 0b0..Channel n can suspend a lower priority channel.
8845 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8846 */
8847#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
8848#define DMA_DCHPRI22_ECP_MASK (0x80U)
8849#define DMA_DCHPRI22_ECP_SHIFT (7U)
8850/*! ECP - Enable Channel Preemption.
8851 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8852 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8853 */
8854#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
8855/*! @} */
8856
8857/*! @name DCHPRI21 - Channel n Priority Register */
8858/*! @{ */
8859#define DMA_DCHPRI21_CHPRI_MASK (0xFU)
8860#define DMA_DCHPRI21_CHPRI_SHIFT (0U)
8861#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
8862#define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
8863#define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
8864#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
8865#define DMA_DCHPRI21_DPA_MASK (0x40U)
8866#define DMA_DCHPRI21_DPA_SHIFT (6U)
8867/*! DPA - Disable Preempt Ability.
8868 * 0b0..Channel n can suspend a lower priority channel.
8869 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8870 */
8871#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
8872#define DMA_DCHPRI21_ECP_MASK (0x80U)
8873#define DMA_DCHPRI21_ECP_SHIFT (7U)
8874/*! ECP - Enable Channel Preemption.
8875 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8876 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8877 */
8878#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
8879/*! @} */
8880
8881/*! @name DCHPRI20 - Channel n Priority Register */
8882/*! @{ */
8883#define DMA_DCHPRI20_CHPRI_MASK (0xFU)
8884#define DMA_DCHPRI20_CHPRI_SHIFT (0U)
8885#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
8886#define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
8887#define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
8888#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
8889#define DMA_DCHPRI20_DPA_MASK (0x40U)
8890#define DMA_DCHPRI20_DPA_SHIFT (6U)
8891/*! DPA - Disable Preempt Ability.
8892 * 0b0..Channel n can suspend a lower priority channel.
8893 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8894 */
8895#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
8896#define DMA_DCHPRI20_ECP_MASK (0x80U)
8897#define DMA_DCHPRI20_ECP_SHIFT (7U)
8898/*! ECP - Enable Channel Preemption.
8899 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8900 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8901 */
8902#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
8903/*! @} */
8904
8905/*! @name DCHPRI27 - Channel n Priority Register */
8906/*! @{ */
8907#define DMA_DCHPRI27_CHPRI_MASK (0xFU)
8908#define DMA_DCHPRI27_CHPRI_SHIFT (0U)
8909#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
8910#define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
8911#define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
8912#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
8913#define DMA_DCHPRI27_DPA_MASK (0x40U)
8914#define DMA_DCHPRI27_DPA_SHIFT (6U)
8915/*! DPA - Disable Preempt Ability.
8916 * 0b0..Channel n can suspend a lower priority channel.
8917 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8918 */
8919#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
8920#define DMA_DCHPRI27_ECP_MASK (0x80U)
8921#define DMA_DCHPRI27_ECP_SHIFT (7U)
8922/*! ECP - Enable Channel Preemption.
8923 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8924 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8925 */
8926#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
8927/*! @} */
8928
8929/*! @name DCHPRI26 - Channel n Priority Register */
8930/*! @{ */
8931#define DMA_DCHPRI26_CHPRI_MASK (0xFU)
8932#define DMA_DCHPRI26_CHPRI_SHIFT (0U)
8933#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
8934#define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
8935#define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
8936#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
8937#define DMA_DCHPRI26_DPA_MASK (0x40U)
8938#define DMA_DCHPRI26_DPA_SHIFT (6U)
8939/*! DPA - Disable Preempt Ability.
8940 * 0b0..Channel n can suspend a lower priority channel.
8941 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8942 */
8943#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
8944#define DMA_DCHPRI26_ECP_MASK (0x80U)
8945#define DMA_DCHPRI26_ECP_SHIFT (7U)
8946/*! ECP - Enable Channel Preemption.
8947 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8948 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8949 */
8950#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
8951/*! @} */
8952
8953/*! @name DCHPRI25 - Channel n Priority Register */
8954/*! @{ */
8955#define DMA_DCHPRI25_CHPRI_MASK (0xFU)
8956#define DMA_DCHPRI25_CHPRI_SHIFT (0U)
8957#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
8958#define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
8959#define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
8960#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
8961#define DMA_DCHPRI25_DPA_MASK (0x40U)
8962#define DMA_DCHPRI25_DPA_SHIFT (6U)
8963/*! DPA - Disable Preempt Ability.
8964 * 0b0..Channel n can suspend a lower priority channel.
8965 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8966 */
8967#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
8968#define DMA_DCHPRI25_ECP_MASK (0x80U)
8969#define DMA_DCHPRI25_ECP_SHIFT (7U)
8970/*! ECP - Enable Channel Preemption.
8971 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8972 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8973 */
8974#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
8975/*! @} */
8976
8977/*! @name DCHPRI24 - Channel n Priority Register */
8978/*! @{ */
8979#define DMA_DCHPRI24_CHPRI_MASK (0xFU)
8980#define DMA_DCHPRI24_CHPRI_SHIFT (0U)
8981#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
8982#define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
8983#define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
8984#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
8985#define DMA_DCHPRI24_DPA_MASK (0x40U)
8986#define DMA_DCHPRI24_DPA_SHIFT (6U)
8987/*! DPA - Disable Preempt Ability.
8988 * 0b0..Channel n can suspend a lower priority channel.
8989 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8990 */
8991#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
8992#define DMA_DCHPRI24_ECP_MASK (0x80U)
8993#define DMA_DCHPRI24_ECP_SHIFT (7U)
8994/*! ECP - Enable Channel Preemption.
8995 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8996 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8997 */
8998#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
8999/*! @} */
9000
9001/*! @name DCHPRI31 - Channel n Priority Register */
9002/*! @{ */
9003#define DMA_DCHPRI31_CHPRI_MASK (0xFU)
9004#define DMA_DCHPRI31_CHPRI_SHIFT (0U)
9005#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
9006#define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
9007#define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
9008#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
9009#define DMA_DCHPRI31_DPA_MASK (0x40U)
9010#define DMA_DCHPRI31_DPA_SHIFT (6U)
9011/*! DPA - Disable Preempt Ability.
9012 * 0b0..Channel n can suspend a lower priority channel.
9013 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
9014 */
9015#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
9016#define DMA_DCHPRI31_ECP_MASK (0x80U)
9017#define DMA_DCHPRI31_ECP_SHIFT (7U)
9018/*! ECP - Enable Channel Preemption.
9019 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
9020 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
9021 */
9022#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
9023/*! @} */
9024
9025/*! @name DCHPRI30 - Channel n Priority Register */
9026/*! @{ */
9027#define DMA_DCHPRI30_CHPRI_MASK (0xFU)
9028#define DMA_DCHPRI30_CHPRI_SHIFT (0U)
9029#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
9030#define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
9031#define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
9032#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
9033#define DMA_DCHPRI30_DPA_MASK (0x40U)
9034#define DMA_DCHPRI30_DPA_SHIFT (6U)
9035/*! DPA - Disable Preempt Ability.
9036 * 0b0..Channel n can suspend a lower priority channel.
9037 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
9038 */
9039#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3