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diff --git a/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F165x/ht32f165x.h b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F165x/ht32f165x.h
new file mode 100644
index 000000000..e16d32412
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+++ b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F165x/ht32f165x.h
@@ -0,0 +1,254 @@
1/*
2 * Copyright (C) 2014-2016 Fabio Utzig, http://fabioutzig.com
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23#ifndef _HT32F165x_H_
24#define _HT32F165x_H_
25
26#if defined(HT32F1653) || defined(HT32F1654)
27 #define HT32F1653_4
28#elif defined(HT32F1655) || defined(HT32F1656)
29 #define HT32F1655_6
30#else
31 #error "Unknown HT32 device"
32#endif
33
34#if defined(HT32F1653_4) || defined(HT32F1655_6)
35 #define HT32
36 #define HT32F165x
37#endif
38
39/*
40 * ==============================================================
41 * ---------- Interrupt Number Definition -----------------------
42 * ==============================================================
43 */
44typedef enum IRQn
45{
46/****** Cortex-M3 Processor Exceptions Numbers ****************/
47 InitialSP_IRQn = -16,
48 InitialPC_IRQn = -15,
49 NonMaskableInt_IRQn = -14,
50 HardFault_IRQn = -13,
51 MemoryManagement_IRQn = -12,
52 BusFault_IRQn = -11,
53 UsageFault_IRQn = -10,
54
55 SVCall_IRQn = -5,
56 DebugMonitor_IRQn = -4,
57
58 PendSV_IRQn = -2,
59 SysTick_IRQn = -1,
60
61/****** HT32F165x Specific Interrupt Numbers ***********************/
62 CKRDY_IRQn = 0,
63 LVD_IRQn = 1,
64 BOD_IRQn = 2,
65 WDT_IRQn = 3,
66 RTC_IRQn = 4,
67 FMC_IRQn = 5,
68 EVWUP_IRQn = 6,
69 LPWUP_IRQn = 7,
70 EXTI0_IRQn = 8,
71 EXTI1_IRQn = 9,
72 EXTI2_IRQn = 10,
73 EXTI3_IRQn = 11,
74 EXTI4_IRQn = 12,
75 EXTI5_IRQn = 13,
76 EXTI6_IRQn = 14,
77 EXTI7_IRQn = 15,
78 EXTI8_IRQn = 16,
79 EXTI9_IRQn = 17,
80 EXTI10_IRQn = 18,
81 EXTI11_IRQn = 19,
82 EXTI12_IRQn = 20,
83 EXTI13_IRQn = 21,
84 EXTI14_IRQn = 22,
85 EXTI15_IRQn = 23,
86 COMP_IRQn = 24,
87 ADC_IRQn = 25,
88
89 MCTM0_BRK_IRQn = 27,
90 MCTM0_UP_IRQn = 28,
91 MCTM0_TR_UP2_IRQn = 29,
92 MCTM0_CC_IRQn = 30,
93 MCTM1_BRK_IRQn = 31,
94 MCTM1_UP_IRQn = 32,
95 MCTM1_TR_UP2_IRQn = 33,
96 MCTM1_CC_IRQn = 34,
97 GPTM0_IRQn = 35,
98 GPTM1_IRQn = 36,
99
100 BFTM0_IRQn = 41,
101 BFTM1_IRQn = 42,
102 I2C0_IRQn = 43,
103 I2C1_IRQn = 44,
104 SPI0_IRQn = 45,
105 SPI1_IRQn = 46,
106 USART0_IRQn = 47,
107 USART1_IRQn = 48,
108 UART0_IRQn = 49,
109 UART1_IRQn = 50,
110 SCI_IRQn = 51,
111 I2C_IRQn = 52,
112 USB_IRQn = 53,
113
114 PDMA_CH0_IRQn = 55,
115 PDMA_CH1_IRQn = 56,
116 PDMA_CH2_IRQn = 57,
117 PDMA_CH3_IRQn = 58,
118 PDMA_CH4_IRQn = 59,
119 PDMA_CH5_IRQn = 60,
120 PDMA_CH6_IRQn = 61,
121 PDMA_CH7_IRQn = 62,
122
123 EBI_IRQn = 68,
124} IRQn_Type;
125
126/*
127 * ==========================================================================
128 * ----------- Processor and Core Peripheral Section ------------------------
129 * ==========================================================================
130 */
131
132/**
133 * @brief HT32F165x Interrupt Number Definition, according to the selected device
134 * in @ref Library_configuration_section
135 */
136#define __FPU_PRESENT 0
137#define __MPU_PRESENT 0
138#define __NVIC_PRIO_BITS 4
139#define __Vendor_SysTickConfig 0
140#define __CM3_REV 0x0201
141
142#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
143
144/****************************************************************/
145/* Peripheral memory map */
146/****************************************************************/
147#define USART0_BASE ((uint32_t)0x40000000)
148#define UART0_BASE ((uint32_t)0x40001000)
149#define SPI0_BASE ((uint32_t)0x40004000)
150#define ADC_BASE ((uint32_t)0x40010000)
151#if defined(HT32F1655_6)
152#define OPACMP0_BASE ((uint32_t)0x40018000)
153#define OPACMP1_BASE ((uint32_t)0x40018100)
154#endif
155#define AFIO_BASE ((uint32_t)0x40022000)
156#define EXTI_BASE ((uint32_t)0x40024000)
157#define I2S_BASE ((uint32_t)0x40026000)
158#define MCTM0_BASE ((uint32_t)0x4002C000)
159#define MCTM1_BASE ((uint32_t)0x4002D000)
160
161#define USART1_BASE ((uint32_t)0x40040000)
162#define UART1_BASE ((uint32_t)0x40041000)
163#define SCI_BASE ((uint32_t)0x40043000)
164#define SPI1_BASE ((uint32_t)0x40044000)
165#define I2C0_BASE ((uint32_t)0x40048000)
166#define I2C1_BASE ((uint32_t)0x40049000)
167#if defined(HT32F1653_4)
168#define CMP0_BASE ((uint32_t)0x40058000)
169#define CMP1_BASE ((uint32_t)0x40058100)
170#endif
171#define WDT_BASE ((uint32_t)0x40068000)
172#define RTC_BASE ((uint32_t)0x4006A000)
173#define PWRCU_BASE ((uint32_t)0x4006A000)
174#define GPTM0_BASE ((uint32_t)0x4006E000)
175#define GPTM1_BASE ((uint32_t)0x4006F000)
176#define BFTM0_BASE ((uint32_t)0x40076000)
177#define BFTM1_BASE ((uint32_t)0x40077000)
178
179#define FMC_BASE ((uint32_t)0x40080000)
180#define CKCU_BASE ((uint32_t)0x40088000)
181#define RSTCU_BASE ((uint32_t)0x40088000)
182#define CRC_BASE ((uint32_t)0x4008A000)
183#define PDMA_BASE ((uint32_t)0x40090000)
184#define EBI_BASE ((uint32_t)0x40098000)
185#define USB_BASE ((uint32_t)0x400A8000)
186#define USB_SRAM_BASE ((uint32_t)0x400AA000)
187#define GPIO_A_BASE ((uint32_t)0x400B0000)
188#define GPIO_B_BASE ((uint32_t)0x400B2000)
189#define GPIO_C_BASE ((uint32_t)0x400B4000)
190#define GPIO_D_BASE ((uint32_t)0x400B6000)
191#if defined(HT32F1655_6)
192#define GPIO_E_BASE ((uint32_t)0x400B8000)
193#endif
194
195// Registers Headers
196#include "ht32f165x_reg.h"
197
198/****************************************************************/
199/* Peripheral declaration */
200/****************************************************************/
201#define USART0 ((USART_TypeDef *) USART0_BASE)
202#define UART0 ((USART_TypeDef *) UART0_BASE)
203#define SPI0 ((SPI_TypeDef *) SPI0_BASE)
204#define ADC ((ADC_TypeDef *) ADC_BASE)
205#if defined(HT32F1655_6)
206#define OPACMP0 ((OPACMP_TypeDef *) OPACMP0_BASE)
207#define OPACMP1 ((OPACMP_TypeDef *) OPACMP1_BASE)
208#endif
209#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
210#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
211#define I2S ((I2S_TypeDef *) I2S_BASE)
212#define MCTM0 ((TM_TypeDef *) MCTM0_BASE)
213#define MCTM1 ((TM_TypeDef *) MCTM1_BASE)
214
215#define USART1 ((USART_TypeDef *) USART1_BASE)
216#define UART1 ((USART_TypeDef *) UART1_BASE)
217#define SCI ((SCI_TypeDef *) SCI_BASE)
218#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
219#define I2C0 ((I2C_TypeDef *) I2C0_BASE)
220#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
221#if defined(HT32F1653_4)
222#define CMP0 ((CMP_TypeDef *) CMP0_BASE)
223#define CMP1 ((CMP_TypeDef *) CMP1_BASE)
224#endif
225#define WDT ((WDT_TypeDef *) WDT_BASE)
226#define RTC ((RTC_TypeDef *) RTC_BASE)
227#define PWRCU ((PWRCU_TypeDef *) PWRCU_BASE)
228#define GPTM0 ((TM_TypeDef *) GPTM0_BASE)
229#define GPTM1 ((TM_TypeDef *) GPTM1_BASE)
230#define BFTM0 ((BFTM_TypeDef *) BFTM0_BASE)
231#define BFTM1 ((BFTM_TypeDef *) BFTM1_BASE)
232
233#define FMC ((FMC_TypeDef *) FMC_BASE)
234#define CKCU ((CKCU_TypeDef *) CKCU_BASE)
235#define RSTCU ((RSTCU_TypeDef *) RSTCU_BASE)
236#define CRC ((CRC_TypeDef *) CRC_BASE)
237#define PDMA ((PDMA_TypeDef *) PDMA_BASE)
238#define EBI ((EBI_TypeDef *) EBI_BASE)
239#define USB ((USB_TypeDef *) USB_BASE)
240
241#define GPIOA ((GPIO_TypeDef *) GPIO_A_BASE)
242#define GPIO_A GPIOA
243#define GPIOB ((GPIO_TypeDef *) GPIO_B_BASE)
244#define GPIO_B GPIOB
245#define GPIOC ((GPIO_TypeDef *) GPIO_C_BASE)
246#define GPIO_C GPIOC
247#define GPIOD ((GPIO_TypeDef *) GPIO_D_BASE)
248#define GPIO_D GPIOD
249#if defined(HT32F1655_6)
250#define GPIOE ((GPIO_TypeDef *) GPIO_E_BASE)
251#define GPIO_E GPIOE
252#endif
253
254#endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 16:17:25 +0100