diff options
Diffstat (limited to 'lib/chibios-contrib/os')
792 files changed, 328310 insertions, 0 deletions
diff --git a/lib/chibios-contrib/os/.keep b/lib/chibios-contrib/os/.keep new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/lib/chibios-contrib/os/.keep | |||
diff --git a/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F165x/ht32f165x.h b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F165x/ht32f165x.h new file mode 100644 index 000000000..e16d32412 --- /dev/null +++ b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F165x/ht32f165x.h | |||
| @@ -0,0 +1,254 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014-2016 Fabio Utzig, http://fabioutzig.com | ||
| 3 | * | ||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining | ||
| 5 | * a copy of this software and associated documentation files (the "Software"), | ||
| 6 | * to deal in the Software without restriction, including without limitation | ||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||
| 10 | * | ||
| 11 | * The above copyright notice and this permission notice shall be included in | ||
| 12 | * all copies or substantial portions of the Software. | ||
| 13 | * | ||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | ||
| 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE | ||
| 17 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
| 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
| 19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | ||
| 20 | * SOFTWARE. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef _HT32F165x_H_ | ||
| 24 | #define _HT32F165x_H_ | ||
| 25 | |||
| 26 | #if defined(HT32F1653) || defined(HT32F1654) | ||
| 27 | #define HT32F1653_4 | ||
| 28 | #elif defined(HT32F1655) || defined(HT32F1656) | ||
| 29 | #define HT32F1655_6 | ||
| 30 | #else | ||
| 31 | #error "Unknown HT32 device" | ||
| 32 | #endif | ||
| 33 | |||
| 34 | #if defined(HT32F1653_4) || defined(HT32F1655_6) | ||
| 35 | #define HT32 | ||
| 36 | #define HT32F165x | ||
| 37 | #endif | ||
| 38 | |||
| 39 | /* | ||
| 40 | * ============================================================== | ||
| 41 | * ---------- Interrupt Number Definition ----------------------- | ||
| 42 | * ============================================================== | ||
| 43 | */ | ||
| 44 | typedef enum IRQn | ||
| 45 | { | ||
| 46 | /****** Cortex-M3 Processor Exceptions Numbers ****************/ | ||
| 47 | InitialSP_IRQn = -16, | ||
| 48 | InitialPC_IRQn = -15, | ||
| 49 | NonMaskableInt_IRQn = -14, | ||
| 50 | HardFault_IRQn = -13, | ||
| 51 | MemoryManagement_IRQn = -12, | ||
| 52 | BusFault_IRQn = -11, | ||
| 53 | UsageFault_IRQn = -10, | ||
| 54 | |||
| 55 | SVCall_IRQn = -5, | ||
| 56 | DebugMonitor_IRQn = -4, | ||
| 57 | |||
| 58 | PendSV_IRQn = -2, | ||
| 59 | SysTick_IRQn = -1, | ||
| 60 | |||
| 61 | /****** HT32F165x Specific Interrupt Numbers ***********************/ | ||
| 62 | CKRDY_IRQn = 0, | ||
| 63 | LVD_IRQn = 1, | ||
| 64 | BOD_IRQn = 2, | ||
| 65 | WDT_IRQn = 3, | ||
| 66 | RTC_IRQn = 4, | ||
| 67 | FMC_IRQn = 5, | ||
| 68 | EVWUP_IRQn = 6, | ||
| 69 | LPWUP_IRQn = 7, | ||
| 70 | EXTI0_IRQn = 8, | ||
| 71 | EXTI1_IRQn = 9, | ||
| 72 | EXTI2_IRQn = 10, | ||
| 73 | EXTI3_IRQn = 11, | ||
| 74 | EXTI4_IRQn = 12, | ||
| 75 | EXTI5_IRQn = 13, | ||
| 76 | EXTI6_IRQn = 14, | ||
| 77 | EXTI7_IRQn = 15, | ||
| 78 | EXTI8_IRQn = 16, | ||
| 79 | EXTI9_IRQn = 17, | ||
| 80 | EXTI10_IRQn = 18, | ||
| 81 | EXTI11_IRQn = 19, | ||
| 82 | EXTI12_IRQn = 20, | ||
| 83 | EXTI13_IRQn = 21, | ||
| 84 | EXTI14_IRQn = 22, | ||
| 85 | EXTI15_IRQn = 23, | ||
| 86 | COMP_IRQn = 24, | ||
| 87 | ADC_IRQn = 25, | ||
| 88 | |||
| 89 | MCTM0_BRK_IRQn = 27, | ||
| 90 | MCTM0_UP_IRQn = 28, | ||
| 91 | MCTM0_TR_UP2_IRQn = 29, | ||
| 92 | MCTM0_CC_IRQn = 30, | ||
| 93 | MCTM1_BRK_IRQn = 31, | ||
| 94 | MCTM1_UP_IRQn = 32, | ||
| 95 | MCTM1_TR_UP2_IRQn = 33, | ||
| 96 | MCTM1_CC_IRQn = 34, | ||
| 97 | GPTM0_IRQn = 35, | ||
| 98 | GPTM1_IRQn = 36, | ||
| 99 | |||
| 100 | BFTM0_IRQn = 41, | ||
| 101 | BFTM1_IRQn = 42, | ||
| 102 | I2C0_IRQn = 43, | ||
| 103 | I2C1_IRQn = 44, | ||
| 104 | SPI0_IRQn = 45, | ||
| 105 | SPI1_IRQn = 46, | ||
| 106 | USART0_IRQn = 47, | ||
| 107 | USART1_IRQn = 48, | ||
| 108 | UART0_IRQn = 49, | ||
| 109 | UART1_IRQn = 50, | ||
| 110 | SCI_IRQn = 51, | ||
| 111 | I2C_IRQn = 52, | ||
| 112 | USB_IRQn = 53, | ||
| 113 | |||
| 114 | PDMA_CH0_IRQn = 55, | ||
| 115 | PDMA_CH1_IRQn = 56, | ||
| 116 | PDMA_CH2_IRQn = 57, | ||
| 117 | PDMA_CH3_IRQn = 58, | ||
| 118 | PDMA_CH4_IRQn = 59, | ||
| 119 | PDMA_CH5_IRQn = 60, | ||
| 120 | PDMA_CH6_IRQn = 61, | ||
| 121 | PDMA_CH7_IRQn = 62, | ||
| 122 | |||
| 123 | EBI_IRQn = 68, | ||
| 124 | } IRQn_Type; | ||
| 125 | |||
| 126 | /* | ||
| 127 | * ========================================================================== | ||
| 128 | * ----------- Processor and Core Peripheral Section ------------------------ | ||
| 129 | * ========================================================================== | ||
| 130 | */ | ||
| 131 | |||
| 132 | /** | ||
| 133 | * @brief HT32F165x Interrupt Number Definition, according to the selected device | ||
| 134 | * in @ref Library_configuration_section | ||
| 135 | */ | ||
| 136 | #define __FPU_PRESENT 0 | ||
| 137 | #define __MPU_PRESENT 0 | ||
| 138 | #define __NVIC_PRIO_BITS 4 | ||
| 139 | #define __Vendor_SysTickConfig 0 | ||
| 140 | #define __CM3_REV 0x0201 | ||
| 141 | |||
| 142 | #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ | ||
| 143 | |||
| 144 | /****************************************************************/ | ||
| 145 | /* Peripheral memory map */ | ||
| 146 | /****************************************************************/ | ||
| 147 | #define USART0_BASE ((uint32_t)0x40000000) | ||
| 148 | #define UART0_BASE ((uint32_t)0x40001000) | ||
| 149 | #define SPI0_BASE ((uint32_t)0x40004000) | ||
| 150 | #define ADC_BASE ((uint32_t)0x40010000) | ||
| 151 | #if defined(HT32F1655_6) | ||
| 152 | #define OPACMP0_BASE ((uint32_t)0x40018000) | ||
| 153 | #define OPACMP1_BASE ((uint32_t)0x40018100) | ||
| 154 | #endif | ||
| 155 | #define AFIO_BASE ((uint32_t)0x40022000) | ||
| 156 | #define EXTI_BASE ((uint32_t)0x40024000) | ||
| 157 | #define I2S_BASE ((uint32_t)0x40026000) | ||
| 158 | #define MCTM0_BASE ((uint32_t)0x4002C000) | ||
| 159 | #define MCTM1_BASE ((uint32_t)0x4002D000) | ||
| 160 | |||
| 161 | #define USART1_BASE ((uint32_t)0x40040000) | ||
| 162 | #define UART1_BASE ((uint32_t)0x40041000) | ||
| 163 | #define SCI_BASE ((uint32_t)0x40043000) | ||
| 164 | #define SPI1_BASE ((uint32_t)0x40044000) | ||
| 165 | #define I2C0_BASE ((uint32_t)0x40048000) | ||
| 166 | #define I2C1_BASE ((uint32_t)0x40049000) | ||
| 167 | #if defined(HT32F1653_4) | ||
| 168 | #define CMP0_BASE ((uint32_t)0x40058000) | ||
| 169 | #define CMP1_BASE ((uint32_t)0x40058100) | ||
| 170 | #endif | ||
| 171 | #define WDT_BASE ((uint32_t)0x40068000) | ||
| 172 | #define RTC_BASE ((uint32_t)0x4006A000) | ||
| 173 | #define PWRCU_BASE ((uint32_t)0x4006A000) | ||
| 174 | #define GPTM0_BASE ((uint32_t)0x4006E000) | ||
| 175 | #define GPTM1_BASE ((uint32_t)0x4006F000) | ||
| 176 | #define BFTM0_BASE ((uint32_t)0x40076000) | ||
| 177 | #define BFTM1_BASE ((uint32_t)0x40077000) | ||
| 178 | |||
| 179 | #define FMC_BASE ((uint32_t)0x40080000) | ||
| 180 | #define CKCU_BASE ((uint32_t)0x40088000) | ||
| 181 | #define RSTCU_BASE ((uint32_t)0x40088000) | ||
| 182 | #define CRC_BASE ((uint32_t)0x4008A000) | ||
| 183 | #define PDMA_BASE ((uint32_t)0x40090000) | ||
| 184 | #define EBI_BASE ((uint32_t)0x40098000) | ||
| 185 | #define USB_BASE ((uint32_t)0x400A8000) | ||
| 186 | #define USB_SRAM_BASE ((uint32_t)0x400AA000) | ||
| 187 | #define GPIO_A_BASE ((uint32_t)0x400B0000) | ||
| 188 | #define GPIO_B_BASE ((uint32_t)0x400B2000) | ||
| 189 | #define GPIO_C_BASE ((uint32_t)0x400B4000) | ||
| 190 | #define GPIO_D_BASE ((uint32_t)0x400B6000) | ||
| 191 | #if defined(HT32F1655_6) | ||
| 192 | #define GPIO_E_BASE ((uint32_t)0x400B8000) | ||
| 193 | #endif | ||
| 194 | |||
| 195 | // Registers Headers | ||
| 196 | #include "ht32f165x_reg.h" | ||
| 197 | |||
| 198 | /****************************************************************/ | ||
| 199 | /* Peripheral declaration */ | ||
| 200 | /****************************************************************/ | ||
| 201 | #define USART0 ((USART_TypeDef *) USART0_BASE) | ||
| 202 | #define UART0 ((USART_TypeDef *) UART0_BASE) | ||
| 203 | #define SPI0 ((SPI_TypeDef *) SPI0_BASE) | ||
| 204 | #define ADC ((ADC_TypeDef *) ADC_BASE) | ||
| 205 | #if defined(HT32F1655_6) | ||
| 206 | #define OPACMP0 ((OPACMP_TypeDef *) OPACMP0_BASE) | ||
| 207 | #define OPACMP1 ((OPACMP_TypeDef *) OPACMP1_BASE) | ||
| 208 | #endif | ||
| 209 | #define AFIO ((AFIO_TypeDef *) AFIO_BASE) | ||
| 210 | #define EXTI ((EXTI_TypeDef *) EXTI_BASE) | ||
| 211 | #define I2S ((I2S_TypeDef *) I2S_BASE) | ||
| 212 | #define MCTM0 ((TM_TypeDef *) MCTM0_BASE) | ||
| 213 | #define MCTM1 ((TM_TypeDef *) MCTM1_BASE) | ||
| 214 | |||
| 215 | #define USART1 ((USART_TypeDef *) USART1_BASE) | ||
| 216 | #define UART1 ((USART_TypeDef *) UART1_BASE) | ||
| 217 | #define SCI ((SCI_TypeDef *) SCI_BASE) | ||
| 218 | #define SPI1 ((SPI_TypeDef *) SPI1_BASE) | ||
| 219 | #define I2C0 ((I2C_TypeDef *) I2C0_BASE) | ||
| 220 | #define I2C1 ((I2C_TypeDef *) I2C1_BASE) | ||
| 221 | #if defined(HT32F1653_4) | ||
| 222 | #define CMP0 ((CMP_TypeDef *) CMP0_BASE) | ||
| 223 | #define CMP1 ((CMP_TypeDef *) CMP1_BASE) | ||
| 224 | #endif | ||
| 225 | #define WDT ((WDT_TypeDef *) WDT_BASE) | ||
| 226 | #define RTC ((RTC_TypeDef *) RTC_BASE) | ||
| 227 | #define PWRCU ((PWRCU_TypeDef *) PWRCU_BASE) | ||
| 228 | #define GPTM0 ((TM_TypeDef *) GPTM0_BASE) | ||
| 229 | #define GPTM1 ((TM_TypeDef *) GPTM1_BASE) | ||
| 230 | #define BFTM0 ((BFTM_TypeDef *) BFTM0_BASE) | ||
| 231 | #define BFTM1 ((BFTM_TypeDef *) BFTM1_BASE) | ||
| 232 | |||
| 233 | #define FMC ((FMC_TypeDef *) FMC_BASE) | ||
| 234 | #define CKCU ((CKCU_TypeDef *) CKCU_BASE) | ||
| 235 | #define RSTCU ((RSTCU_TypeDef *) RSTCU_BASE) | ||
| 236 | #define CRC ((CRC_TypeDef *) CRC_BASE) | ||
| 237 | #define PDMA ((PDMA_TypeDef *) PDMA_BASE) | ||
| 238 | #define EBI ((EBI_TypeDef *) EBI_BASE) | ||
| 239 | #define USB ((USB_TypeDef *) USB_BASE) | ||
| 240 | |||
| 241 | #define GPIOA ((GPIO_TypeDef *) GPIO_A_BASE) | ||
| 242 | #define GPIO_A GPIOA | ||
| 243 | #define GPIOB ((GPIO_TypeDef *) GPIO_B_BASE) | ||
| 244 | #define GPIO_B GPIOB | ||
| 245 | #define GPIOC ((GPIO_TypeDef *) GPIO_C_BASE) | ||
| 246 | #define GPIO_C GPIOC | ||
| 247 | #define GPIOD ((GPIO_TypeDef *) GPIO_D_BASE) | ||
| 248 | #define GPIO_D GPIOD | ||
| 249 | #if defined(HT32F1655_6) | ||
| 250 | #define GPIOE ((GPIO_TypeDef *) GPIO_E_BASE) | ||
| 251 | #define GPIO_E GPIOE | ||
| 252 | #endif | ||
| 253 | |||
| 254 | #endif | ||
diff --git a/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F165x/ht32f165x_reg.h b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F165x/ht32f165x_reg.h new file mode 100644 index 000000000..b47416b56 --- /dev/null +++ b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F165x/ht32f165x_reg.h | |||
| @@ -0,0 +1,679 @@ | |||
| 1 | #ifndef HT32F165x_REG_H | ||
| 2 | #define HT32F165x_REG_H | ||
| 3 | |||
| 4 | #ifndef __IO | ||
| 5 | #define __IO volatile | ||
| 6 | #endif | ||
| 7 | |||
| 8 | // Constants | ||
| 9 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 10 | #define AFIO_DEFAULT 0 | ||
| 11 | #define AFIO_GPIO 1 | ||
| 12 | #define AFIO_ADC 2 | ||
| 13 | #define AFIO_CMP 3 | ||
| 14 | #define AFIO_TM 4 | ||
| 15 | #define AFIO_SPI 5 | ||
| 16 | #define AFIO_USART 6 | ||
| 17 | #define AFIO_I2C 7 | ||
| 18 | #define AFIO_SMC 8 | ||
| 19 | #define AFIO_EBI 9 | ||
| 20 | #define AFIO_I2S 10 | ||
| 21 | #define AFIO_OTHER 15 | ||
| 22 | |||
| 23 | // Flash Memory Controller | ||
| 24 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 25 | typedef struct { | ||
| 26 | __IO uint32_t TADR; //!< 0x000 Flash Target Address Register | ||
| 27 | __IO uint32_t WRDR; //!< 0x004 Flash Write Data Register | ||
| 28 | uint32_t RESERVED0[1]; //!< 0x008 Reserved | ||
| 29 | __IO uint32_t OCMR; //!< 0x00C Flash Operation Command Register | ||
| 30 | __IO uint32_t OPCR; //!< 0x010 Flash Operation Control Register | ||
| 31 | __IO uint32_t OIER; //!< 0x014 Flash Operation Interrupt Enable Register | ||
| 32 | __IO uint32_t OISR; //!< 0x018 Flash Operation Interrupt and Status Register | ||
| 33 | uint32_t RESERVED1[1]; //!< 0x01C Reserved | ||
| 34 | __IO uint32_t PPSR[4]; //!< 0x020 ~ 0x02C Flash Page Erase/Program Protection Status Register | ||
| 35 | __IO uint32_t CPSR; //!< 0x030 Flash Security Protection Status Register | ||
| 36 | uint32_t RESERVED2[51]; //!< 0x034 ~ 0x0FC Reserved | ||
| 37 | __IO uint32_t VMCR; //!< 0x100 Flash Vector Mapping Control Register | ||
| 38 | uint32_t RESERVED3[31]; //!< 0x104 ~ 0x17C Reserved | ||
| 39 | __IO uint32_t MDID; //!< 0x180 Manufacturer and Device ID Register | ||
| 40 | __IO uint32_t PNSR; //!< 0x184 Flash Page Number Status Register | ||
| 41 | __IO uint32_t PSSR; //!< 0x188 Flash Page Size Status Register | ||
| 42 | #if defined(HT32F165x) | ||
| 43 | uint32_t RESERVED4[29]; //!< 0x18C ~ 0x1FC Reserved | ||
| 44 | #else | ||
| 45 | __IO uint32_t DID; //!< 0x18C Device ID Register | ||
| 46 | uint32_t RESERVED4[28]; //!< 0x190 ~ 0x1FC Reserved | ||
| 47 | #endif | ||
| 48 | __IO uint32_t CFCR; //!< 0x200 Flash Cache and Pre-fetch Control Register | ||
| 49 | uint32_t RESERVED5[63]; //!< 0x204 ~ 0x2FC Reserved | ||
| 50 | __IO uint32_t SBVT[4]; //!< 0x300 ~ 0x30C SRAM Booting Vector (4x32Bit) | ||
| 51 | #if defined(HT32F165x) | ||
| 52 | #else | ||
| 53 | __IO uint32_t CID[4]; //!< 0x310 ~ 0x31C Custom ID Register | ||
| 54 | #endif | ||
| 55 | } FMC_TypeDef; | ||
| 56 | |||
| 57 | #define FMC_OCMR_CMD_MASK (0xF << 0) | ||
| 58 | #define FMC_OCMR_CMD_IDLE (0x0 << 0) | ||
| 59 | #define FMC_OCMR_CMD_WORD_PROGRAM (0x4 << 0) | ||
| 60 | #define FMC_OCMR_CMD_PAGE_ERASE (0x8 << 0) | ||
| 61 | #define FMC_OCMR_CMD_MASS_ERASE (0xA << 0) | ||
| 62 | #define FMC_OPCR_OPM_MASK (0xF << 1) | ||
| 63 | #define FMC_OPCR_OPM_IDLE (0x6 << 1) | ||
| 64 | #define FMC_OPCR_OPM_COMMIT (0xA << 1) | ||
| 65 | #define FMC_OPCR_OPM_FINISHED (0xE << 1) | ||
| 66 | #define FMC_CFCR_CE (1U << 12) | ||
| 67 | #define FMC_CFCR_WAIT_MASK (7U << 0) | ||
| 68 | #define FMC_CFCR_WAIT_0 (1U) | ||
| 69 | #define FMC_CFCR_WAIT_1 (2U) | ||
| 70 | #define FMC_CFCR_WAIT_2 (3U) | ||
| 71 | |||
| 72 | // Power Control Unit | ||
| 73 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 74 | typedef struct { | ||
| 75 | uint32_t RESERVE0[64]; | ||
| 76 | __IO uint32_t BAKSR; //!< 0x000 Status Register | ||
| 77 | __IO uint32_t BAKCR; //!< 0x004 Control Register | ||
| 78 | __IO uint32_t BAKTEST; //!< 0x008 Test Register | ||
| 79 | __IO uint32_t HSIRCR; //!< 0x00C HSI Ready Counter Control Register | ||
| 80 | __IO uint32_t LVDCSR; //!< 0x010 Low Voltage/Brown Out Detect Control and Status Register | ||
| 81 | uint32_t RESERVE1[59]; //!< 0x014 ~ 0x0FC Reserved | ||
| 82 | __IO uint32_t BAKREG[10]; //!< 0x100 ~ 0x124 Backup Register 0 ~ 9 | ||
| 83 | } PWRCU_TypeDef; | ||
| 84 | |||
| 85 | // Clock Control Unit | ||
| 86 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 87 | typedef struct { | ||
| 88 | __IO uint32_t GCFGR; //!< 0x000 Global Clock Configuration Register | ||
| 89 | __IO uint32_t GCCR; //!< 0x004 Global Clock Control Register | ||
| 90 | __IO uint32_t GCSR; //!< 0x008 Global Clock Status Register | ||
| 91 | __IO uint32_t GCIR; //!< 0x00C Global Clock Interrupt Register | ||
| 92 | uint32_t RESERVED0[2]; //!< 0x010 ~ 0x014 Reserved | ||
| 93 | __IO uint32_t PLLCFGR; //!< 0x018 PLL Configuration Register | ||
| 94 | __IO uint32_t PLLCR; //!< 0x01C PLL Control Register | ||
| 95 | __IO uint32_t AHBCFGR; //!< 0x020 AHB Configuration Register | ||
| 96 | __IO uint32_t AHBCCR; //!< 0x024 AHB Clock Control Register | ||
| 97 | __IO uint32_t APBCFGR; //!< 0x028 APB Configuration Register | ||
| 98 | __IO uint32_t APBCCR0; //!< 0x02C APB Clock Control Register 0 | ||
| 99 | __IO uint32_t APBCCR1; //!< 0x030 APB Clock Control Register 1 | ||
| 100 | __IO uint32_t CKST; //!< 0x034 Clock source status Register | ||
| 101 | #if defined(HT32F1653_4) | ||
| 102 | __IO uint32_t APBPCSR0; //!< 0x038 APB Peripheral Clock Selection Register 0 | ||
| 103 | __IO uint32_t APBPCSR1; //!< 0x03C APB Peripheral Clock Selection Register 1 | ||
| 104 | __IO uint32_t HSICR; //!< 0x040 HSI Control Register | ||
| 105 | __IO uint32_t HSIATCR; //!< 0x044 HSI Auto Trimming Counter Register | ||
| 106 | #else | ||
| 107 | uint32_t RESERVED1[4]; //!< 0x038 ~ 0x044 Reserved | ||
| 108 | #endif | ||
| 109 | uint32_t RESERVED2[174]; //!< 0x048 ~ 0x2FC Reserved | ||
| 110 | __IO uint32_t LPCR; //!< 0x300 Low Power Control Register | ||
| 111 | __IO uint32_t MCUDBGCR; //!< 0x304 MCU Debug Control Register | ||
| 112 | } CKCU_TypeDef; | ||
| 113 | |||
| 114 | #define CKCU_GCFGR_LPMOD_MASK (7U << 29) | ||
| 115 | #define CKCU_GCFGR_USBPRE_MASK (3U << 22) | ||
| 116 | #define CKCU_GCFGR_URPRE_MASK (3U << 20) | ||
| 117 | #define CKCU_GCFGR_PLLSRC (1U << 8) | ||
| 118 | #define CKCU_GCFGR_CKOUTSRC_MASK (7U << 0) | ||
| 119 | #define CKCU_GCFGR_CKOUTSRC_CK_REF (0U << 0) | ||
| 120 | #define CKCU_GCFGR_CKOUTSRC_CK_AHB (1U << 0) | ||
| 121 | #define CKCU_GCFGR_CKOUTSRC_CK_SYS (2U << 0) | ||
| 122 | #define CKCU_GCFGR_CKOUTSRC_CK_HSE (3U << 0) | ||
| 123 | #define CKCU_GCFGR_CKOUTSRC_CK_HSI (4U << 0) | ||
| 124 | #define CKCU_GCFGR_CKOUTSRC_CK_LSE (5U << 0) | ||
| 125 | #define CKCU_GCFGR_CKOUTSRC_CK_LSI (6U << 0) | ||
| 126 | #define CKCU_GCCR_PSRCEN (1U << 17) | ||
| 127 | #define CKCU_GCCR_CKMEN (1U << 16) | ||
| 128 | #define CKCU_GCCR_HSIEN (1U << 11) | ||
| 129 | #define CKCU_GCCR_HSEEN (1U << 10) | ||
| 130 | #define CKCU_GCCR_PLLEN (1U << 9) | ||
| 131 | #define CKCU_GCCR_SW_MASK (3U << 0) | ||
| 132 | #define CKCU_GCCR_SW_PLL (1U << 0) | ||
| 133 | #define CKCU_GCCR_SW_HSE (2U << 0) | ||
| 134 | #define CKCU_GCCR_SW_HSI (3U << 0) | ||
| 135 | #define CKCU_GCSR_LSIRDY (1U << 5) | ||
| 136 | #define CKCU_GCSR_LSERDY (1U << 4) | ||
| 137 | #define CKCU_GCSR_HSIRDY (1U << 3) | ||
| 138 | #define CKCU_GCSR_HSERDY (1U << 2) | ||
| 139 | #define CKCU_GCSR_PLLRDY (1U << 1) | ||
| 140 | #define CKCU_PLLCFGR_PFBD_MASK (0x3fU << 23) | ||
| 141 | #define CKCU_PLLCFGR_POTD_MASK (3U << 21) | ||
| 142 | #define CKCU_PLLCR_PLLBPS (1U << 31) | ||
| 143 | #define CKCU_AHBCFGR_AHBPRE_MASK (3U << 0) | ||
| 144 | #define CKCU_AHBCCR_PAEN (1U << 16) | ||
| 145 | #define CKCU_AHBCCR_CRCEN (1U << 13) | ||
| 146 | #define CKCU_AHBCCR_EBIEN (1U << 12) | ||
| 147 | #define CKCU_AHBCCR_CKREFEN (1U << 11) | ||
| 148 | #define CKCU_AHBCCR_USBEN (1U << 10) | ||
| 149 | #define CKCU_APBCFGR_ADCDIV_MASK (7U << 16) | ||
| 150 | #define CKCU_APBCCR0_I2SEN (1U << 25) | ||
| 151 | #define CKCU_APBCCR0_SCIEN (1U << 24) | ||
| 152 | #define CKCU_APBCCR0_EXTIEN (1U << 15) | ||
| 153 | #define CKCU_APBCCR0_AFIOEN (1U << 14) | ||
| 154 | #define CKCU_APBCCR0_UR1EN (1U << 11) | ||
| 155 | #define CKCU_APBCCR0_UR0EN (1U << 10) | ||
| 156 | #define CKCU_APBCCR0_USR1EN (1U << 9) | ||
| 157 | #define CKCU_APBCCR0_USR0EN (1U << 8) | ||
| 158 | #define CKCU_APBCCR0_SPI1EN (1U << 5) | ||
| 159 | #define CKCU_APBCCR0_SPI0EN (1U << 4) | ||
| 160 | #define CKCU_APBCCR0_I2C1EN (1U << 1) | ||
| 161 | #define CKCU_APBCCR0_I2C0EN (1U << 0) | ||
| 162 | #define CKCU_APBCCR1_ADCEN (1U << 24) | ||
| 163 | #define CKCU_APBCCR1_OPA1EN (1U << 23) | ||
| 164 | #define CKCU_APBCCR1_OPA0EN (1U << 22) | ||
| 165 | #define CKCU_APBCCR1_BFTM1EN (1U << 17) | ||
| 166 | #define CKCU_APBCCR1_BFTM0EN (1U << 16) | ||
| 167 | #define CKCU_APBCCR1_GPTM1EN (1U << 9) | ||
| 168 | #define CKCU_APBCCR1_GPTM0EN (1U << 8) | ||
| 169 | #define CKCU_APBCCR1_BKPREN (1U << 6) | ||
| 170 | #define CKCU_APBCCR1_WDTREN (1U << 4) | ||
| 171 | #define CKCU_APBCCR1_MCTM1EN (1U << 1) | ||
| 172 | #define CKCU_APBCCR1_MCTM0EN (1U << 0) | ||
| 173 | #define CKCU_CKST_CKSWST_MASK (3U << 30) | ||
| 174 | #define CKCU_CKST_HSIST_MASK (7U << 24) | ||
| 175 | #define CKCU_CKST_HSEST_MASK (3U << 16) | ||
| 176 | #define CKCU_CKST_PLLST_MASK (0xfU << 8) | ||
| 177 | #define CKCU_LPCR_USBSLEEP (1U << 8) | ||
| 178 | #define CKCU_LPCR_BKISO (1U << 0) | ||
| 179 | |||
| 180 | // Reset Control Unit | ||
| 181 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 182 | typedef struct { | ||
| 183 | __IO uint32_t GRSR; //!< 0x000 Global Reset Status Register | ||
| 184 | __IO uint32_t AHBPRSTR; //!< 0x004 AHB Peripheral Reset Register | ||
| 185 | __IO uint32_t APBPRSTR0; //!< 0x008 APB Peripheral Reset Register 0 | ||
| 186 | __IO uint32_t APBPRSTR1; //!< 0x00C APB Peripheral Reset Register 1 | ||
| 187 | } RSTCU_TypeDef; | ||
| 188 | |||
| 189 | #define RSTCU_GRSR_PORSTF (1U << 3) | ||
| 190 | #define RSTCU_GRSR_WDTRSTF (1U << 2) | ||
| 191 | #define RSTCU_GRSR_EXTRSTF (1U << 1) | ||
| 192 | #define RSTCU_GRSR_SYSRSTF (1U << 0) | ||
| 193 | #define RSTCU_AHBPRSTR_PxRST(n) ((1U << 8) << (n)) | ||
| 194 | #define RSTCU_AHBPRSTR_CRCRST (1U << 7) | ||
| 195 | #define RSTCU_AHBPRSTR_EBIRST (1U << 6) | ||
| 196 | #define RSTCU_AHBPRSTR_USBRST (1U << 5) | ||
| 197 | #define RSTCU_AHBPRSTR_DMARST (1U << 0) | ||
| 198 | #define RSTCU_APBPRSTR0_I2SRST (1U << 25) | ||
| 199 | #define RSTCU_APBPRSTR0_SCIRST (1U << 24) | ||
| 200 | #define RSTCU_APBPRSTR0_EXTIRST (1U << 15) | ||
| 201 | #define RSTCU_APBPRSTR0_AFIORST (1U << 14) | ||
| 202 | #define RSTCU_APBPRSTR0_UR1RST (1U << 11) | ||
| 203 | #define RSTCU_APBPRSTR0_UR0RST (1U << 10) | ||
| 204 | #define RSTCU_APBPRSTR0_USR1RST (1U << 9) | ||
| 205 | #define RSTCU_APBPRSTR0_USR0RST (1U << 8) | ||
| 206 | #define RSTCU_APBPRSTR0_SPI1RST (1U << 5) | ||
| 207 | #define RSTCU_APBPRSTR0_SPI0RST (1U << 4) | ||
| 208 | #define RSTCU_APBPRSTR0_I2C1RST (1U << 1) | ||
| 209 | #define RSTCU_APBPRSTR0_I2C0RST (1U << 0) | ||
| 210 | #define RSTCU_APBPRSTR1_ADCRST (1U << 24) | ||
| 211 | #define RSTCU_APBPRSTR1_OPA1RST (1U << 23) | ||
| 212 | #define RSTCU_APBPRSTR1_OPA0RST (1U << 22) | ||
| 213 | #define RSTCU_APBPRSTR1_BFTM1RST (1U << 17) | ||
| 214 | #define RSTCU_APBPRSTR1_BFTM0RST (1U << 16) | ||
| 215 | #define RSTCU_APBPRSTR1_GPTM1RST (1U << 9) | ||
| 216 | #define RSTCU_APBPRSTR1_GPTM0RST (1U << 8) | ||
| 217 | #define RSTCU_APBPRSTR1_WDTRST (1U << 4) | ||
| 218 | #define RSTCU_APBPRSTR1_MCTM1RST (1U << 1) | ||
| 219 | #define RSTCU_APBPRSTR1_MCTM0RST (1U << 0) | ||
| 220 | |||
| 221 | // General Purpose I/O | ||
| 222 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 223 | typedef struct { | ||
| 224 | __IO uint32_t DIRCR; //!< 0x000 Data Direction Control Register | ||
| 225 | __IO uint32_t INER; //!< 0x004 Input function enable register | ||
| 226 | __IO uint32_t PUR; //!< 0x008 Pull-Up Selection Register | ||
| 227 | __IO uint32_t PDR; //!< 0x00C Pull-Down Selection Register | ||
| 228 | __IO uint32_t ODR; //!< 0x010 Open Drain Selection Register | ||
| 229 | __IO uint32_t DRVR; //!< 0x014 Drive Current Selection Register | ||
| 230 | __IO uint32_t LOCKR; //!< 0x018 Lock Register | ||
| 231 | __IO uint32_t DINR; //!< 0x01c Data Input Register | ||
| 232 | __IO uint32_t DOUTR; //!< 0x020 Data Output Register | ||
| 233 | __IO uint32_t SRR; //!< 0x024 Output Set and Reset Control Register | ||
| 234 | __IO uint32_t RR; //!< 0x028 Output Reset Control Register | ||
| 235 | } GPIO_TypeDef; | ||
| 236 | |||
| 237 | // Alternate Function Input/Output | ||
| 238 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 239 | typedef struct { | ||
| 240 | __IO uint32_t ESSR[2]; //!< 0x000 ~ 0x004 EXTI Source Selection Register 0 ~ 1 | ||
| 241 | uint32_t RESERVE0[6]; //!< 0x008 ~ 0x01C Reserved | ||
| 242 | union { | ||
| 243 | struct { | ||
| 244 | __IO uint32_t GPACFGR[2]; //!< 0x020 ~ 0x024 GPIO Port A Configuration Register 0 ~ 1 | ||
| 245 | __IO uint32_t GPBCFGR[2]; //!< 0x028 ~ 0x02C GPIO Port B Configuration Register 0 ~ 1 | ||
| 246 | __IO uint32_t GPCCFGR[2]; //!< 0x030 ~ 0x034 GPIO Port C Configuration Register 0 ~ 1 | ||
| 247 | __IO uint32_t GPDCFGR[2]; //!< 0x038 ~ 0x03C GPIO Port D Configuration Register 0 ~ 1 | ||
| 248 | #if defined(HT32F1655_6) | ||
| 249 | __IO uint32_t GPECFGR[2]; //!< 0x040 ~ 0x044 GPIO Port E Configuration Register 0 ~ 1 | ||
| 250 | #endif | ||
| 251 | }; | ||
| 252 | // alternate mapping | ||
| 253 | struct { | ||
| 254 | __IO uint32_t GPxCFGR[0][2]; //!< 0x020 ~ 0x044 GPIO Port x Configuration Register 0 ~ 1 | ||
| 255 | }; | ||
| 256 | }; | ||
| 257 | } AFIO_TypeDef; | ||
| 258 | |||
| 259 | // Nested Vectored Interrupt Controller | ||
| 260 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 261 | // Implemented in Cortex-M3 Headers | ||
| 262 | |||
| 263 | // External Interrupt/Event Controller | ||
| 264 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 265 | typedef struct { | ||
| 266 | __IO uint32_t CFGR0; //!< 0x000 EXTI Interrupt 0 Configuration Register | ||
| 267 | __IO uint32_t CFGR1; //!< 0x004 EXTI Interrupt 1 Configuration Register | ||
| 268 | __IO uint32_t CFGR2; //!< 0x008 EXTI Interrupt 2 Configuration Register | ||
| 269 | __IO uint32_t CFGR3; //!< 0x00C EXTI Interrupt 3 Configuration Register | ||
| 270 | __IO uint32_t CFGR4; //!< 0x010 EXTI Interrupt 4 Configuration Register | ||
| 271 | __IO uint32_t CFGR5; //!< 0x014 EXTI Interrupt 5 Configuration Register | ||
| 272 | __IO uint32_t CFGR6; //!< 0x018 EXTI Interrupt 6 Configuration Register | ||
| 273 | __IO uint32_t CFGR7; //!< 0x01C EXTI Interrupt 7 Configuration Register | ||
| 274 | __IO uint32_t CFGR8; //!< 0x020 EXTI Interrupt 8 Configuration Register | ||
| 275 | __IO uint32_t CFGR9; //!< 0x024 EXTI Interrupt 9 Configuration Register | ||
| 276 | __IO uint32_t CFGR10; //!< 0x028 EXTI Interrupt 10 Configuration Register | ||
| 277 | __IO uint32_t CFGR11; //!< 0x02C EXTI Interrupt 11 Configuration Register | ||
| 278 | __IO uint32_t CFGR12; //!< 0x030 EXTI Interrupt 12 Configuration Register | ||
| 279 | __IO uint32_t CFGR13; //!< 0x034 EXTI Interrupt 13 Configuration Register | ||
| 280 | __IO uint32_t CFGR14; //!< 0x038 EXTI Interrupt 14 Configuration Register | ||
| 281 | __IO uint32_t CFGR15; //!< 0x03C EXTI Interrupt 15 Configuration Register | ||
| 282 | __IO uint32_t CR; //!< 0x040 EXTI Interrupt Control Register | ||
| 283 | __IO uint32_t EDGEFLGR; //!< 0x044 EXTI Interrupt Edge Flag Register | ||
| 284 | __IO uint32_t EDGESR; //!< 0x048 EXTI Interrupt Edge Status Register | ||
| 285 | __IO uint32_t SSCR; //!< 0x04C EXTI Interrupt Software Set Command Register | ||
| 286 | __IO uint32_t WAKUPCR; //!< 0x050 EXTI Interrupt Wakeup Control Register | ||
| 287 | __IO uint32_t WAKUPPOLR; //!< 0x054 EXTI Interrupt Wakeup Polarity Register | ||
| 288 | __IO uint32_t WAKUPFLG; //!< 0x058 EXTI Interrupt Wakeup Flag Register | ||
| 289 | } EXTI_TypeDef; | ||
| 290 | |||
| 291 | // Analog To Digital Converter | ||
| 292 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 293 | |||
| 294 | // Operational Amplifier / Comparator | ||
| 295 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 296 | #if defined(HT32F1653_4) | ||
| 297 | typedef struct { | ||
| 298 | __IO uint32_t CR; //!< 0x000 Comparator Control Register | ||
| 299 | __IO uint32_t VALR; //!< 0x004 Comparator Voltage Reference Register | ||
| 300 | __IO uint32_t IER; //!< 0x008 Comparator Interrupt Enable Register | ||
| 301 | __IO uint32_t TFR; //!< 0x00C Comparator Transition Flag Register | ||
| 302 | } CMP_TypeDef; | ||
| 303 | #else | ||
| 304 | typedef struct { | ||
| 305 | __IO uint32_t OPACR; //!< 0x000 Operational Amplifier Control Register | ||
| 306 | __IO uint32_t OFVCR; //!< 0x004 Comparator Input Offset Voltage Cancellation Register | ||
| 307 | __IO uint32_t CMPIER; //!< 0x008 Comparator Interrupt Enable Register | ||
| 308 | __IO uint32_t CMPRSR; //!< 0x00C Comparator Raw Status Register | ||
| 309 | __IO uint32_t CMPISR; //!< 0x010 Comparator Masked Interrupt Status Register | ||
| 310 | __IO uint32_t CMPICLR; //!< 0x014 Comparator Interrupt Clear Register | ||
| 311 | } OPACMP_TypeDef; | ||
| 312 | #endif | ||
| 313 | |||
| 314 | // Basic Function Timers | ||
| 315 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 316 | typedef struct { | ||
| 317 | __IO uint32_t CR; //!< 0x000 Control Register | ||
| 318 | __IO uint32_t SR; //!< 0x004 Status Register | ||
| 319 | __IO uint32_t CNTR; //!< 0x008 Counter Value Register | ||
| 320 | __IO uint32_t CMP; //!< 0x00C Compare Value Register | ||
| 321 | } BFTM_TypeDef; | ||
| 322 | |||
| 323 | #define BFTM_CR_CEN (1U << 2) | ||
| 324 | #define BFTM_CR_OSM (1U << 1) | ||
| 325 | #define BFTM_CR_MIEN (1U << 0) | ||
| 326 | #define BFTM_SR_MIF (1U << 0) | ||
| 327 | |||
| 328 | // General Purpose Timers | ||
| 329 | // Motor Control Timers | ||
| 330 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 331 | typedef struct { | ||
| 332 | __IO uint32_t CNTCFR; //!< 0x000 Timer Counter Configuaration Register | ||
| 333 | __IO uint32_t MDCFR; //!< 0x004 Timer Mode Configuration Register | ||
| 334 | __IO uint32_t TRCFR; //!< 0x008 Timer Trigger Configuration Register | ||
| 335 | uint32_t RESERVED0[1]; //!< 0x00C Reserved | ||
| 336 | __IO uint32_t CTR; //!< 0x010 Timer Counter Register | ||
| 337 | uint32_t RESERVED1[3]; //!< 0x014 ~ 0x01C Reserved | ||
| 338 | __IO uint32_t CHnICFR[4]; //!< 0x020 ~ 0x02C Channel n Input Configuration Register | ||
| 339 | uint32_t RESERVED2[4]; //!< 0x030 ~ 0x03C Reserved | ||
| 340 | __IO uint32_t CHnOCFR[4]; //!< 0x040 ~ 0x04C Channel n Output Configuration Register | ||
| 341 | __IO uint32_t CHCTR; //!< 0x050 Channel Control Register | ||
| 342 | __IO uint32_t CHPOLR; //!< 0x054 Channel Polarity Control Register | ||
| 343 | uint32_t RESERVED3[5]; //!< 0x058 ~ 0x068 Reserved | ||
| 344 | // note: only available as MCTM | ||
| 345 | __IO uint32_t CHBRKCFR; //!< 0x06C Channel Break Configuration Register | ||
| 346 | __IO uint32_t CHBRKCTR; //!< 0x070 Channel Break Control Register | ||
| 347 | // end note | ||
| 348 | __IO uint32_t DICTR; //!< 0x074 Timer PDMA/Interrupt Control Register | ||
| 349 | __IO uint32_t EVGR; //!< 0x078 Timer Event Generator Register | ||
| 350 | __IO uint32_t INTSR; //!< 0x07C Timer Interrupt Status Register | ||
| 351 | __IO uint32_t CNTR; //!< 0x080 Timer Counter Register | ||
| 352 | __IO uint32_t PSCR; //!< 0x084 Timer Prescaler Register | ||
| 353 | __IO uint32_t CRR; //!< 0x088 Timer Counter Reload Register | ||
| 354 | // note: only available as MCTM | ||
| 355 | __IO uint32_t REPR; //!< 0x08C Timer Repetition Register | ||
| 356 | // end note | ||
| 357 | __IO uint32_t CHnCCR[4]; //!< 0x090 ~ 0x09C Channel n Capture/Compare Register | ||
| 358 | __IO uint32_t CHnACR[4]; //!< 0x0A0 ~ 0x0AC Channel n Asymmentric Compare Register | ||
| 359 | } TM_TypeDef; | ||
| 360 | |||
| 361 | #define TM_CNTCFR_CMSEL_MASK (3U << 16) | ||
| 362 | #define TM_CNTCFR_CMSEL_MODE_3 (3U << 16) | ||
| 363 | #define TM_CNTCFR_CMSEL_MODE_2 (2U << 16) | ||
| 364 | #define TM_CNTCFR_CMSEL_MODE_1 (1U << 16) | ||
| 365 | #define TM_CNTCFR_CMSEL_MODE_0 (0U << 16) | ||
| 366 | #define TM_CTR_CHCCDS (1U << 16) | ||
| 367 | #define TM_CTR_COMUS (1U << 9) | ||
| 368 | #define TM_CTR_COMPRE (1U << 8) | ||
| 369 | #define TM_CTR_CRBE (1U << 1) | ||
| 370 | #define TM_CTR_TME (1U << 0) | ||
| 371 | #define TM_CHnOCFR_CHnPRE (1U << 4) | ||
| 372 | #define TM_CHnOCFR_REFnCE (1U << 3) | ||
| 373 | #define TM_CHnOCFR_CHnOM(n) ((((n)>>0)&7)|((((n)>>3)&1)<<8)) | ||
| 374 | #define TM_CHBRKCTR_CHMOE (1U << 4) | ||
| 375 | |||
| 376 | // Real Time Clock | ||
| 377 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 378 | |||
| 379 | // Watchdog Timer | ||
| 380 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 381 | |||
| 382 | // I2C | ||
| 383 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 384 | typedef struct { | ||
| 385 | __IO uint32_t CR; //!< 0x000 Control Register | ||
| 386 | __IO uint32_t IER; //!< 0x004 Interrupt Enable Register | ||
| 387 | __IO uint32_t ADDR; //!< 0x008 Address Register | ||
| 388 | __IO uint32_t SR; //!< 0x00C Status Register | ||
| 389 | __IO uint32_t SHPGR; //!< 0x010 SCL High Period Generation Register | ||
| 390 | __IO uint32_t SLPGR; //!< 0x014 SCL Low Period Generation Register | ||
| 391 | __IO uint32_t DR; //!< 0x018 Data Register | ||
| 392 | __IO uint32_t TAR; //!< 0x01C Target Register | ||
| 393 | __IO uint32_t ADDMR; //!< 0x020 Address Mask Register | ||
| 394 | __IO uint32_t ADDSR; //!< 0x024 Address Snoop Register | ||
| 395 | __IO uint32_t TOUT; //!< 0x028 Timeout Register | ||
| 396 | } I2C_TypeDef; | ||
| 397 | |||
| 398 | #define I2C_CR_SEQ_FILTER_MASK (3U << 14) | ||
| 399 | #define I2C_CR_SEQ_FILTER_2_PCLK (2U << 14) | ||
| 400 | #define I2C_CR_SEQ_FILTER_1_PCLK (1U << 14) | ||
| 401 | #define I2C_CR_SEQ_FILTER_DISABLE (0U << 14) | ||
| 402 | #define I2C_CR_COMB_FILTER_En (1U << 13) | ||
| 403 | #define I2C_CR_ENTOUT (1U << 12) | ||
| 404 | #define I2C_CR_DMANACK (1U << 10) | ||
| 405 | #define I2C_CR_RXDMAE (1U << 9) | ||
| 406 | #define I2C_CR_TXDMAE (1U << 8) | ||
| 407 | #define I2C_CR_ADRM (1U << 7) | ||
| 408 | #define I2C_CR_I2CEN (1U << 3) | ||
| 409 | #define I2C_CR_GCEN (1U << 2) | ||
| 410 | #define I2C_CR_STOP (1U << 1) | ||
| 411 | #define I2C_CR_AA (1U << 0) | ||
| 412 | #define I2C_IER_RXBFIE (1U << 18) | ||
| 413 | #define I2C_IER_TXDEIE (1U << 17) | ||
| 414 | #define I2C_IER_RXDNEIE (1U << 16) | ||
| 415 | #define I2C_IER_TOUTIE (1U << 11) | ||
| 416 | #define I2C_IER_BUSERRIE (1U << 10) | ||
| 417 | #define I2C_IER_RXNACKIE (1U << 9) | ||
| 418 | #define I2C_IER_ARBLOSIE (1U << 8) | ||
| 419 | #define I2C_IER_GCSIE (1U << 3) | ||
| 420 | #define I2C_IER_ADRSIE (1U << 2) | ||
| 421 | #define I2C_IER_STOIE (1U << 1) | ||
| 422 | #define I2C_IER_STAIE (1U << 0) | ||
| 423 | #define I2C_SR_TXNRX (1U << 21) | ||
| 424 | #define I2C_SR_MASTER (1U << 20) | ||
| 425 | #define I2C_SR_BUSBUSY (1U << 19) | ||
| 426 | #define I2C_SR_RXBF (1U << 18) | ||
| 427 | #define I2C_SR_TXDE (1U << 17) | ||
| 428 | #define I2C_SR_RXDNE (1U << 16) | ||
| 429 | #define I2C_SR_TOUTF (1U << 11) | ||
| 430 | #define I2C_SR_BUSERR (1U << 10) | ||
| 431 | #define I2C_SR_RXNACK (1U << 9) | ||
| 432 | #define I2C_SR_ARBLOS (1U << 8) | ||
| 433 | #define I2C_SR_GCS (1U << 3) | ||
| 434 | #define I2C_SR_ADRS (1U << 2) | ||
| 435 | #define I2C_SR_STO (1U << 1) | ||
| 436 | #define I2C_SR_STA (1U << 0) | ||
| 437 | #define I2C_TAR_RWD (1U << 10) | ||
| 438 | |||
| 439 | // SPI | ||
| 440 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 441 | typedef struct { | ||
| 442 | __IO uint32_t CR0; //!< 0x000 Control Register 0 | ||
| 443 | __IO uint32_t CR1; //!< 0x004 Control Register 1 | ||
| 444 | __IO uint32_t IER; //!< 0x008 Interrupt Enable Register | ||
| 445 | __IO uint32_t CPR; //!< 0x00C Clock Prescaler Register | ||
| 446 | __IO uint32_t DR; //!< 0x010 Data Register | ||
| 447 | __IO uint32_t SR; //!< 0x014 Status Register | ||
| 448 | __IO uint32_t FCR; //!< 0x018 FIFO Control Register | ||
| 449 | __IO uint32_t FSR; //!< 0x01C FIFO Status Register | ||
| 450 | __IO uint32_t FTOCR; //!< 0x020 FIFO Time Out Counter Register | ||
| 451 | } SPI_TypeDef; | ||
| 452 | |||
| 453 | #define SPI_CR0_GUADTEN (1U << 7) | ||
| 454 | #define SPI_CR0_DUALEN (1U << 6) | ||
| 455 | #define SPI_CR0_SSELC (1U << 4) | ||
| 456 | #define SPI_CR0_SELOEN (1U << 3) | ||
| 457 | #define SPI_CR0_SPIEN (1U << 0) | ||
| 458 | #define SPI_CR1_MODE (1U << 14) | ||
| 459 | #define SPI_CR1_SELM (1U << 13) | ||
| 460 | #define SPI_CR1_FIRSTBIT (1U << 12) | ||
| 461 | #define SPI_CR1_SELAP (1U << 11) | ||
| 462 | #define SPI_CR1_FORMAT_MASK (7U << 8) | ||
| 463 | #define SPI_CR1_FORMAT_MODE0 (0x1U << 8) | ||
| 464 | #define SPI_CR1_FORMAT_MODE1 (0x2U << 8) | ||
| 465 | #define SPI_CR1_FORMAT_MODE2 (0x6U << 8) | ||
| 466 | #define SPI_CR1_FORMAT_MODE3 (0x5U << 8) | ||
| 467 | #define SPI_IER_RXBNEIEN (1U << 2) | ||
| 468 | #define SPI_IER_TXBEIEN (1U << 0) | ||
| 469 | #define SPI_SR_RXBNE (1U << 2) | ||
| 470 | #define SPI_SR_TXE (1U << 1) | ||
| 471 | #define SPI_SR_TXBE (1U << 0) | ||
| 472 | #define SPI_FCR_FIFOEN (1U << 10) | ||
| 473 | #define SPI_FSR_TXFS_MASK (0xfU << 0) | ||
| 474 | #define SPI_FSR_RXFS_MASK (0xfU << 4) | ||
| 475 | |||
| 476 | // USART | ||
| 477 | // UART | ||
| 478 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 479 | typedef struct { | ||
| 480 | union { | ||
| 481 | __IO uint32_t RBR; //!< 0x000 Receive Buffer Register | ||
| 482 | __IO uint32_t TBR; //!< 0x000 Transmit Holding Register | ||
| 483 | __IO uint32_t DR; //!< 0x000 Data Register | ||
| 484 | }; | ||
| 485 | __IO uint32_t IER; //!< 0x004 Interrupt Enable Register | ||
| 486 | __IO uint32_t IIR; //!< 0x008 Interrupt Identification Register/FIFO Control Register | ||
| 487 | __IO uint32_t FCR; //!< 0x00C FIFO Control Register | ||
| 488 | __IO uint32_t LCR; //!< 0x010 Line Control Register | ||
| 489 | // note: only available as USART | ||
| 490 | __IO uint32_t MODCR; //!< 0x014 Modem Control Register | ||
| 491 | // end note | ||
| 492 | __IO uint32_t LSR; //!< 0x018 Line Status Register | ||
| 493 | // note: only available as USART | ||
| 494 | __IO uint32_t MODSR; //!< 0x01C Modem Status Register | ||
| 495 | // end note | ||
| 496 | __IO uint32_t TPR; //!< 0x020 Timing Parameter Register | ||
| 497 | __IO uint32_t MDR; //!< 0x024 Mode Register | ||
| 498 | // note: only available as USART | ||
| 499 | __IO uint32_t IrDACR; //!< 0x028 IrDA Control Register | ||
| 500 | __IO uint32_t RS485CR; //!< 0x02C RS485 Control Register | ||
| 501 | __IO uint32_t SYNCR; //!< 0x030 Synchronous Control Register | ||
| 502 | // end note | ||
| 503 | __IO uint32_t FSR; //!< 0x034 FIFO Status Register | ||
| 504 | __IO uint32_t DLR; //!< 0x038 Divisor Latch Register | ||
| 505 | uint32_t RESERVED0; //!< 0x03C Reserved | ||
| 506 | __IO uint32_t DEGTSTR; //!< 0x040 Debug/Test Register | ||
| 507 | } USART_TypeDef; | ||
| 508 | |||
| 509 | #define USART_FCR_FME (1 << 0) | ||
| 510 | #define USART_FCR_RFR (1 << 1) | ||
| 511 | #define USART_FCR_TFR (1 << 2) | ||
| 512 | #define USART_FCR_TFTL_MASK (0x3 << 4) | ||
| 513 | #define USART_FCR_TFTL_0BYTE (0x0 << 4) | ||
| 514 | #define USART_FCR_TFTL_2BYTE (0x1 << 4) | ||
| 515 | #define USART_FCR_TFTL_4BYTE (0x2 << 4) | ||
| 516 | #define USART_FCR_TFTL_8BYTE (0x3 << 4) | ||
| 517 | #define USART_FCR_RFTL_MASK (0x3 << 6) | ||
| 518 | #define USART_FCR_RFTL_1BYTE (0x0 << 6) | ||
| 519 | #define USART_FCR_RFTL_4BYTE (0x1 << 6) | ||
| 520 | #define USART_FCR_RFTL_8BYTE (0x2 << 6) | ||
| 521 | #define USART_FCR_RFTL_14BYTE (0x3 << 6) | ||
| 522 | #define USART_FCR_URTXEN (1 << 8) | ||
| 523 | #define USART_FCR_URRXEN (1 << 9) | ||
| 524 | #define USART_LCR_WLS_MASK (0x3 << 0) | ||
| 525 | #define USART_LCR_WLS_7BIT (0x0 << 0) | ||
| 526 | #define USART_LCR_WLS_8BIT (0x1 << 0) | ||
| 527 | #define USART_LCR_WLS_9BIT (0x2 << 0) | ||
| 528 | #define USART_LCR_NSB (1 << 2) | ||
| 529 | #define USART_LCR_PBE (1 << 3) | ||
| 530 | #define USART_LCR_EPE (1 << 4) | ||
| 531 | #define USART_LCR_SPE (1 << 5) | ||
| 532 | #define USART_LCR_BCB (1 << 6) | ||
| 533 | #define USART_LSR_RFDR (1 << 0) | ||
| 534 | #define USART_LSR_OEI (1 << 1) | ||
| 535 | #define USART_LSR_PEI (1 << 2) | ||
| 536 | #define USART_LSR_FEI (1 << 3) | ||
| 537 | #define USART_LSR_BII (1 << 4) | ||
| 538 | #define USART_LSR_TXFEMPT (1 << 5) | ||
| 539 | #define USART_LSR_TXEMPT (1 << 6) | ||
| 540 | #define USART_LSR_ERRRX (1 << 7) | ||
| 541 | #define USART_LSR_RSADDEF (1 << 8) | ||
| 542 | #define USART_MDR_MODE_MASK (0x3 << 0) | ||
| 543 | #define USART_MDR_MODE_NORMAL (0x0 << 0) | ||
| 544 | #define USART_MDR_MODE_IRDA (0x1 << 0) | ||
| 545 | #define USART_MDR_MODE_RS485 (0x2 << 0) | ||
| 546 | #define USART_MDR_MODE_SYNCHRONOUS (0x3 << 0) | ||
| 547 | #define USART_MDR_TRSM (1 << 2) | ||
| 548 | #define USART_MDR_TXDMAEN (1 << 4) | ||
| 549 | #define USART_MDR_RXDMAEN (1 << 5) | ||
| 550 | |||
| 551 | // Smart Card Interface | ||
| 552 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 553 | |||
| 554 | // USB | ||
| 555 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 556 | typedef struct { | ||
| 557 | __IO uint32_t CSR; //!< 0x000 USB Control and Status Register | ||
| 558 | __IO uint32_t IER; //!< 0x004 USB Interrupt Enable Register | ||
| 559 | __IO uint32_t ISR; //!< 0x008 USB Interrupt Status Register | ||
| 560 | __IO uint32_t FCR; //!< 0x00C USB Frame Count Register | ||
| 561 | __IO uint32_t DEVAR; //!< 0x010 USB Device Address Register | ||
| 562 | struct { | ||
| 563 | __IO uint32_t CSR; //!< 0x014 USB Endpoint n Control and Status Register | ||
| 564 | __IO uint32_t IER; //!< 0x018 USB Endpoint n Interrupt Enable Register | ||
| 565 | __IO uint32_t ISR; //!< 0x01C USB Endpoint n Interrupt Status Register | ||
| 566 | __IO uint32_t TCR; //!< 0x020 USB Endpoint n Transfer Count Register | ||
| 567 | __IO uint32_t CFGR; //!< 0x024 USB Endpoint n Configuration Register | ||
| 568 | } EP[8]; | ||
| 569 | } USB_TypeDef; | ||
| 570 | |||
| 571 | // USBCSR | ||
| 572 | #define USBCSR_FRES (0x002) // Force USB Reset Control | ||
| 573 | #define USBCSR_PDWN (0x004) // Power Down Mode Control | ||
| 574 | #define USBCSR_LPMODE (0x008) // Low-Power Mode Control | ||
| 575 | #define USBCSR_GENRSM (0x020) // Resume Request Generation Control | ||
| 576 | #define USBCSR_RXDP (0x040) // Received DP Line Status | ||
| 577 | #define USBCSR_RXDM (0x080) // Received DM Line Status | ||
| 578 | #define USBCSR_ADRSET (0x100) // Device Address Setting Control | ||
| 579 | #define USBCSR_SRAMRSTC (0x200) // USB SRAM Reset Condition | ||
| 580 | #define USBCSR_DPPUEN (0x400) // DP Pull Up Enable | ||
| 581 | #define USBCSR_DPWKEN (0x800) // DP Wake Up Enable | ||
| 582 | |||
| 583 | // USBIER | ||
| 584 | #define USBIER_UGIE (0x0001) // USB global Interrupt Enable | ||
| 585 | #define USBIER_SOFIE (0x0002) // Start Of Frame Interrupt Enable | ||
| 586 | #define USBIER_URSTIE (0x0004) // USB Reset Interrupt Enable | ||
| 587 | #define USBIER_RSMIE (0x0008) // Resume Interrupt Enable | ||
| 588 | #define USBIER_SUSPIE (0x0010) // Suspend Interrupt Enable | ||
| 589 | #define USBIER_ESOFIE (0x0020) // Expected Start Of Frame Enable | ||
| 590 | #define USBIER_EP0IE (0x0100) // Endpoint 0 Interrupt Enable | ||
| 591 | #define USBIER_EP1IE (0x0200) // Endpoint 1 Interrupt Enable | ||
| 592 | #define USBIER_EP2IE (0x0400) // Endpoint 2 Interrupt Enable | ||
| 593 | #define USBIER_EP3IE (0x0800) // Endpoint 3 Interrupt Enable | ||
| 594 | #define USBIER_EP4IE (0x1000) // Endpoint 4 Interrupt Enable | ||
| 595 | #define USBIER_EP5IE (0x2000) // Endpoint 5 Interrupt Enable | ||
| 596 | #define USBIER_EP6IE (0x4000) // Endpoint 6 Interrupt Enable | ||
| 597 | #define USBIER_EP7IE (0x8000) // Endpoint 7 Interrupt Enable | ||
| 598 | |||
| 599 | // USBISR | ||
| 600 | #define USBISR_SOFIF (0x0002) // Start Of Frame Interrupt Flag | ||
| 601 | #define USBISR_URSTIF (0x0004) // USB Reset Interrupt Flag | ||
| 602 | #define USBISR_RSMIF (0x0008) // Resume Interrupt Flag | ||
| 603 | #define USBISR_SUSPIF (0x0010) // Suspend Interrupt Flag | ||
| 604 | #define USBISR_ESOFIF (0x0020) // Expected Start Of Frame Interrupt | ||
| 605 | #define USBISR_EP0IF (1U << 8) // Endpoint 0 Interrupt Flag | ||
| 606 | #define USBISR_EP1IF (1U << 9) // Endpoint 1 Interrupt Flag | ||
| 607 | #define USBISR_EP2IF (1U << 10) // Endpoint 2 Interrupt Flag | ||
| 608 | #define USBISR_EP3IF (1U << 11) // Endpoint 3 Interrupt Flag | ||
| 609 | #define USBISR_EP4IF (1U << 12) // Endpoint 4 Interrupt Flag | ||
| 610 | #define USBISR_EP5IF (1U << 13) // Endpoint 5 Interrupt Flag | ||
| 611 | #define USBISR_EP6IF (1U << 14) // Endpoint 6 Interrupt Flag | ||
| 612 | #define USBISR_EP7IF (1U << 15) // Endpoint 7 Interrupt Flag | ||
| 613 | #define USBISR_EPnIF (0xFF00) // Endpoint Interrupt Mask | ||
| 614 | |||
| 615 | // USBFCR | ||
| 616 | #define USBFCR_FRNUM (0x7FF) // Frame Number | ||
| 617 | #define USBFCR_SOFLCK (1U << 16) // Start-of-Frame Lock Flag | ||
| 618 | #define USBFCR_LSOF (0x3U << 17) // Lost Start-of-Frame Number | ||
| 619 | |||
| 620 | // USBEPnCSR | ||
| 621 | #define USBEPnCSR_DTGTX (0x01) // Data Toggle Status, for IN transfer | ||
| 622 | #define USBEPnCSR_NAKTX (0x02) // NAK Status, for IN transfer | ||
| 623 | #define USBEPnCSR_STLTX (0x04) // STALL Status, for IN transfer | ||
| 624 | #define USBEPnCSR_DTGRX (0x08) // Data Toggle Status, for OUT transfer | ||
| 625 | #define USBEPnCSR_NAKRX (0x10) // NAK Status, for OUT transfer | ||
| 626 | #define USBEPnCSR_STLRX (0x20) // STALL Status, for OUT transfer | ||
| 627 | |||
| 628 | // USBEPnIER | ||
| 629 | #define USBEPnIER_OTRXIE (0x001) // OUT Token Received Interrupt Enable | ||
| 630 | #define USBEPnIER_ODRXIE (0x002) // OUT Data Received Interrupt Enable | ||
| 631 | #define USBEPnIER_ODOVIE (0x004) // OUT Data Buffer Overrun Interrupt Enable | ||
| 632 | #define USBEPnIER_ITRXIE (0x008) // IN Token Received Interrupt Enable | ||
| 633 | #define USBEPnIER_IDTXIE (0x010) // IN Data Transmitted Interrupt Enable | ||
| 634 | #define USBEPnIER_NAKIE (0x020) // NAK Transmitted Interrupt Enable | ||
| 635 | #define USBEPnIER_STLIE (0x040) // STALL Transmitted Interrupt Enable | ||
| 636 | #define USBEPnIER_UERIE (0x080) // USB Error Interrupt Enable | ||
| 637 | #define USBEPnIER_STRXIE (0x100) // SETUP Token Received Interrupt Enable | ||
| 638 | #define USBEPnIER_SDRXIE (0x200) // SETUP Data Received Interrupt Enable | ||
| 639 | #define USBEPnIER_SDERIE (0x400) // SETUP Data Error Interrupt Enable | ||
| 640 | #define USBEPnIER_ZLRXIE (0x800) // Zero Length Data Received Interrupt Enable | ||
| 641 | |||
| 642 | // USBEPnISR | ||
| 643 | #define USBEPnISR_OTRXIF (0x001) // OUT Token Received Interrupt Flag | ||
| 644 | #define USBEPnISR_ODRXIF (0x002) // OUT Data Received Interrupt Flag | ||
| 645 | #define USBEPnISR_ODOVIF (0x004) // OUT Data Buffer Overrun Interrupt Flag | ||
| 646 | #define USBEPnISR_ITRXIF (0x008) // IN Token Received Interrupt Flag | ||
| 647 | #define USBEPnISR_IDTXIF (0x010) // IN Data Transmitted Interrupt Flag | ||
| 648 | #define USBEPnISR_NAKIF (0x020) // NAK Transmitted Interrupt Flag | ||
| 649 | #define USBEPnISR_STLIF (0x040) // STALL Transmitted Interrupt Flag | ||
| 650 | #define USBEPnISR_UERIF (0x080) // USB Error Interrupt Flag | ||
| 651 | #define USBEPnISR_STRXIF (0x100) // SETUP Token Received Interrupt Flag | ||
| 652 | #define USBEPnISR_SDRXIF (0x200) // SETUP Data Received Interrupt Flag | ||
| 653 | #define USBEPnISR_SDERIF (0x400) // SETUP Data Error Interrupt Flag | ||
| 654 | #define USBEPnISR_ZLRXIF (0x800) // Zero Length Data Received Interrupt Flag | ||
| 655 | |||
| 656 | // USBEPnTCR | ||
| 657 | #define USBEPnTCR_TCNT (0x1FF) // Transfer Byte Count | ||
| 658 | |||
| 659 | // USBEPnCFGR | ||
| 660 | #define USBEPnCFGR_EPEN (1U << 31) // Endpoint Enable | ||
| 661 | #define USBEPnCFGR_EPTYPE (1U << 29) // Transfer Type | ||
| 662 | #define USBEPnCFGR_EPDIR (1U << 28) // Transfer Direction | ||
| 663 | #define USBEPnCFGR_EPADR (0xFU << 24) // Endpoint Address | ||
| 664 | #define USBEPnCFGR_EPLEN (0x7FU << 10) // Buffer Length | ||
| 665 | #define USBEPnCFGR_EPBUFA (0x3FF) // Endpoint Buffer Address | ||
| 666 | |||
| 667 | // Peripheral Direct Memory Access | ||
| 668 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 669 | |||
| 670 | // Extend Bus Interface | ||
| 671 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 672 | |||
| 673 | // Inter-IC Sound | ||
| 674 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 675 | |||
| 676 | // CRC | ||
| 677 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 678 | |||
| 679 | #endif // HT32F165x_REG_H | ||
diff --git a/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2.h b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2.h new file mode 100644 index 000000000..ba4871636 --- /dev/null +++ b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2.h | |||
| @@ -0,0 +1,199 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2020 Codetector <[email protected]> | ||
| 3 | * | ||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining | ||
| 5 | * a copy of this software and associated documentation files (the "Software"), | ||
| 6 | * to deal in the Software without restriction, including without limitation | ||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||
| 10 | * | ||
| 11 | * The above copyright notice and this permission notice shall be included in | ||
| 12 | * all copies or substantial portions of the Software. | ||
| 13 | * | ||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | ||
| 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE | ||
| 17 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
| 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
| 19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | ||
| 20 | * SOFTWARE. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #pragma once | ||
| 24 | |||
| 25 | #if defined(HT32F52342) || defined(HT32F52352) | ||
| 26 | #define HT32F523x2 | ||
| 27 | #else | ||
| 28 | #error "Unknown HT32 device" | ||
| 29 | #endif | ||
| 30 | |||
| 31 | #if defined(HT32F523x2) | ||
| 32 | #define HT32 | ||
| 33 | #endif | ||
| 34 | |||
| 35 | /* | ||
| 36 | * ============================================================== | ||
| 37 | * ---------- Interrupt Number Definition ----------------------- | ||
| 38 | * ============================================================== | ||
| 39 | */ | ||
| 40 | typedef enum IRQn | ||
| 41 | { | ||
| 42 | /****** Cortex-M3 Processor Exceptions Numbers ****************/ | ||
| 43 | InitialSP_IRQn = -16, | ||
| 44 | InitialPC_IRQn = -15, | ||
| 45 | NonMaskableInt_IRQn = -14, | ||
| 46 | HardFault_IRQn = -13, | ||
| 47 | SVCall_IRQn = -5, | ||
| 48 | PendSV_IRQn = -2, | ||
| 49 | SysTick_IRQn = -1, | ||
| 50 | |||
| 51 | /****** HT32F165x Specific Interrupt Numbers ***********************/ | ||
| 52 | LVD_IRQn = 0, | ||
| 53 | RTC_IRQn = 1, | ||
| 54 | FMC_IRQn = 2, | ||
| 55 | WKUP_IRQn = 3, | ||
| 56 | EXTI0_1_IRQn = 4, | ||
| 57 | EXTI2_3_IRQn = 5, | ||
| 58 | EXTI4_15_IRQn = 6, | ||
| 59 | CMP_IRQn = 7, | ||
| 60 | ADC_IRQn = 8, | ||
| 61 | |||
| 62 | MCTM_IRQn = 10, | ||
| 63 | GPTM1_IRQn = 11, | ||
| 64 | GPTM0_IRQn = 12, | ||
| 65 | SCTM0_IRQn = 13, | ||
| 66 | SCTM1_IRQn = 14, | ||
| 67 | |||
| 68 | BFTM0_IRQn = 17, | ||
| 69 | BFTM1_IRQn = 18, | ||
| 70 | I2C0_IRQn = 19, | ||
| 71 | I2C1_IRQn = 20, | ||
| 72 | SPI0_IRQn = 21, | ||
| 73 | SPI1_IRQn = 22, | ||
| 74 | USART0_IRQn = 23, | ||
| 75 | USART1_IRQn = 24, | ||
| 76 | UART0_IRQn = 25, | ||
| 77 | UART1_IRQn = 26, | ||
| 78 | SCI_IRQn = 27, | ||
| 79 | I2S_IRQn = 28, | ||
| 80 | USB_IRQn = 29, | ||
| 81 | PDMA_CH0_1_IRQn = 30, | ||
| 82 | PDMA_CH2_5_IRQn = 31 | ||
| 83 | } IRQn_Type; | ||
| 84 | |||
| 85 | /* | ||
| 86 | * ========================================================================== | ||
| 87 | * ----------- Processor and Core Peripheral Section ------------------------ | ||
| 88 | * ========================================================================== | ||
| 89 | */ | ||
| 90 | |||
| 91 | /** | ||
| 92 | * @brief HT32F165x Interrupt Number Definition, according to the selected device | ||
| 93 | * in @ref Library_configuration_section | ||
| 94 | */ | ||
| 95 | #define __FPU_PRESENT 0 | ||
| 96 | #define __MPU_PRESENT 0 | ||
| 97 | #define __NVIC_PRIO_BITS 8 | ||
| 98 | #define __Vendor_SysTickConfig 0 | ||
| 99 | |||
| 100 | #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ | ||
| 101 | |||
| 102 | /****************************************************************/ | ||
| 103 | /* Peripheral memory map */ | ||
| 104 | /****************************************************************/ | ||
| 105 | #define USART0_BASE ((uint32_t)0x40000000) | ||
| 106 | #define UART0_BASE ((uint32_t)0x40001000) | ||
| 107 | #define SPI0_BASE ((uint32_t)0x40004000) | ||
| 108 | #define ADC_BASE ((uint32_t)0x40010000) | ||
| 109 | |||
| 110 | #define AFIO_BASE ((uint32_t)0x40022000) | ||
| 111 | #define EXTI_BASE ((uint32_t)0x40024000) | ||
| 112 | #define I2S_BASE ((uint32_t)0x40026000) | ||
| 113 | #define MCTM0_BASE ((uint32_t)0x4002C000) | ||
| 114 | #define MCTM1_BASE ((uint32_t)0x4002D000) | ||
| 115 | |||
| 116 | #define USART1_BASE ((uint32_t)0x40040000) | ||
| 117 | #define UART1_BASE ((uint32_t)0x40041000) | ||
| 118 | #define SCI_BASE ((uint32_t)0x40043000) | ||
| 119 | #define SPI1_BASE ((uint32_t)0x40044000) | ||
| 120 | #define I2C0_BASE ((uint32_t)0x40048000) | ||
| 121 | #define I2C1_BASE ((uint32_t)0x40049000) | ||
| 122 | |||
| 123 | #define CMP0_BASE ((uint32_t)0x40058000) | ||
| 124 | #define CMP1_BASE ((uint32_t)0x40058100) | ||
| 125 | |||
| 126 | #define WDT_BASE ((uint32_t)0x40068000) | ||
| 127 | #define RTC_BASE ((uint32_t)0x4006A000) | ||
| 128 | #define PWRCU_BASE ((uint32_t)0x4006A000) | ||
| 129 | #define GPTM0_BASE ((uint32_t)0x4006E000) | ||
| 130 | #define GPTM1_BASE ((uint32_t)0x4006F000) | ||
| 131 | #define BFTM0_BASE ((uint32_t)0x40076000) | ||
| 132 | #define BFTM1_BASE ((uint32_t)0x40077000) | ||
| 133 | |||
| 134 | #define FMC_BASE ((uint32_t)0x40080000) | ||
| 135 | #define CKCU_BASE ((uint32_t)0x40088000) | ||
| 136 | #define RSTCU_BASE ((uint32_t)0x40088000) | ||
| 137 | #define CRC_BASE ((uint32_t)0x4008A000) | ||
| 138 | #define PDMA_BASE ((uint32_t)0x40090000) | ||
| 139 | #define EBI_BASE ((uint32_t)0x40098000) | ||
| 140 | #define USB_BASE ((uint32_t)0x400A8000) | ||
| 141 | #define USB_SRAM_BASE ((uint32_t)0x400AA000) | ||
| 142 | #define GPIO_A_BASE ((uint32_t)0x400B0000) | ||
| 143 | #define GPIO_B_BASE ((uint32_t)0x400B2000) | ||
| 144 | #define GPIO_C_BASE ((uint32_t)0x400B4000) | ||
| 145 | #define GPIO_D_BASE ((uint32_t)0x400B6000) | ||
| 146 | |||
| 147 | |||
| 148 | // Registers Headers | ||
| 149 | #include "ht32f523x2_reg.h" | ||
| 150 | |||
| 151 | /****************************************************************/ | ||
| 152 | /* Peripheral declaration */ | ||
| 153 | /****************************************************************/ | ||
| 154 | #define USART0 ((USART_TypeDef *) USART0_BASE) | ||
| 155 | #define UART0 ((USART_TypeDef *) UART0_BASE) | ||
| 156 | #define SPI0 ((SPI_TypeDef *) SPI0_BASE) | ||
| 157 | #define ADC ((ADC_TypeDef *) ADC_BASE) | ||
| 158 | |||
| 159 | #define AFIO ((AFIO_TypeDef *) AFIO_BASE) | ||
| 160 | #define EXTI ((EXTI_TypeDef *) EXTI_BASE) | ||
| 161 | #define I2S ((I2S_TypeDef *) I2S_BASE) | ||
| 162 | #define MCTM0 ((TM_TypeDef *) MCTM0_BASE) | ||
| 163 | #define MCTM1 ((TM_TypeDef *) MCTM1_BASE) | ||
| 164 | |||
| 165 | #define USART1 ((USART_TypeDef *) USART1_BASE) | ||
| 166 | #define UART1 ((USART_TypeDef *) UART1_BASE) | ||
| 167 | #define SCI ((SCI_TypeDef *) SCI_BASE) | ||
| 168 | #define SPI1 ((SPI_TypeDef *) SPI1_BASE) | ||
| 169 | #define I2C0 ((I2C_TypeDef *) I2C0_BASE) | ||
| 170 | #define I2C1 ((I2C_TypeDef *) I2C1_BASE) | ||
| 171 | |||
| 172 | #define CMP0 ((CMP_TypeDef *) CMP0_BASE) | ||
| 173 | #define CMP1 ((CMP_TypeDef *) CMP1_BASE) | ||
| 174 | |||
| 175 | #define WDT ((WDT_TypeDef *) WDT_BASE) | ||
| 176 | #define RTC ((RTC_TypeDef *) RTC_BASE) | ||
| 177 | #define PWRCU ((PWRCU_TypeDef *) PWRCU_BASE) | ||
| 178 | #define GPTM0 ((TM_TypeDef *) GPTM0_BASE) | ||
| 179 | #define GPTM1 ((TM_TypeDef *) GPTM1_BASE) | ||
| 180 | #define BFTM0 ((BFTM_TypeDef *) BFTM0_BASE) | ||
| 181 | #define BFTM1 ((BFTM_TypeDef *) BFTM1_BASE) | ||
| 182 | |||
| 183 | #define FMC ((FMC_TypeDef *) FMC_BASE) | ||
| 184 | #define CKCU ((CKCU_TypeDef *) CKCU_BASE) | ||
| 185 | #define RSTCU ((RSTCU_TypeDef *) RSTCU_BASE) | ||
| 186 | #define CRC ((CRC_TypeDef *) CRC_BASE) | ||
| 187 | #define PDMA ((PDMA_TypeDef *) PDMA_BASE) | ||
| 188 | #define EBI ((EBI_TypeDef *) EBI_BASE) | ||
| 189 | #define USB ((USB_TypeDef *) USB_BASE) | ||
| 190 | |||
| 191 | #define GPIOA ((GPIO_TypeDef *) GPIO_A_BASE) | ||
| 192 | #define GPIO_A GPIOA | ||
| 193 | #define GPIOB ((GPIO_TypeDef *) GPIO_B_BASE) | ||
| 194 | #define GPIO_B GPIOB | ||
| 195 | #define GPIOC ((GPIO_TypeDef *) GPIO_C_BASE) | ||
| 196 | #define GPIO_C GPIOC | ||
| 197 | #define GPIOD ((GPIO_TypeDef *) GPIO_D_BASE) | ||
| 198 | #define GPIO_D GPIOD | ||
| 199 | |||
diff --git a/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2_reg.h b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2_reg.h new file mode 100644 index 000000000..d8aad785d --- /dev/null +++ b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2_reg.h | |||
| @@ -0,0 +1,657 @@ | |||
| 1 | #pragma once | ||
| 2 | |||
| 3 | #ifndef __IO | ||
| 4 | #define __IO volatile | ||
| 5 | #endif | ||
| 6 | |||
| 7 | // Constants | ||
| 8 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 9 | #define AFIO_DEFAULT 0 | ||
| 10 | #define AFIO_GPIO 1 | ||
| 11 | #define AFIO_ADC 2 | ||
| 12 | #define AFIO_CMP 3 | ||
| 13 | #define AFIO_TM 4 | ||
| 14 | #define AFIO_SPI 5 | ||
| 15 | #define AFIO_USART 6 | ||
| 16 | #define AFIO_I2C 7 | ||
| 17 | #define AFIO_SMC 8 | ||
| 18 | #define AFIO_EBI 9 | ||
| 19 | #define AFIO_I2S 10 | ||
| 20 | #define AFIO_OTHER 15 | ||
| 21 | |||
| 22 | // Flash Memory Controller | ||
| 23 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 24 | typedef struct { | ||
| 25 | __IO uint32_t TADR; //!< 0x000 Flash Target Address Register | ||
| 26 | __IO uint32_t WRDR; //!< 0x004 Flash Write Data Register | ||
| 27 | uint32_t RESERVED0[1]; //!< 0x008 Reserved | ||
| 28 | __IO uint32_t OCMR; //!< 0x00C Flash Operation Command Register | ||
| 29 | __IO uint32_t OPCR; //!< 0x010 Flash Operation Control Register | ||
| 30 | __IO uint32_t OIER; //!< 0x014 Flash Operation Interrupt Enable Register | ||
| 31 | __IO uint32_t OISR; //!< 0x018 Flash Operation Interrupt and Status Register | ||
| 32 | uint32_t RESERVED1[1]; //!< 0x01C Reserved | ||
| 33 | __IO uint32_t PPSR[4]; //!< 0x020 ~ 0x02C Flash Page Erase/Program Protection Status Register | ||
| 34 | __IO uint32_t CPSR; //!< 0x030 Flash Security Protection Status Register | ||
| 35 | uint32_t RESERVED2[51]; //!< 0x034 ~ 0x0FC Reserved | ||
| 36 | __IO uint32_t VMCR; //!< 0x100 Flash Vector Mapping Control Register | ||
| 37 | uint32_t RESERVED3[31]; //!< 0x104 ~ 0x17C Reserved | ||
| 38 | __IO uint32_t MDID; //!< 0x180 Manufacturer and Device ID Register | ||
| 39 | __IO uint32_t PNSR; //!< 0x184 Flash Page Number Status Register | ||
| 40 | __IO uint32_t PSSR; //!< 0x188 Flash Page Size Status Register | ||
| 41 | #if defined(HT32F165x) | ||
| 42 | uint32_t RESERVED4[29]; //!< 0x18C ~ 0x1FC Reserved | ||
| 43 | #else | ||
| 44 | __IO uint32_t DID; //!< 0x18C Device ID Register | ||
| 45 | uint32_t RESERVED4[28]; //!< 0x190 ~ 0x1FC Reserved | ||
| 46 | #endif | ||
| 47 | __IO uint32_t CFCR; //!< 0x200 Flash Cache and Pre-fetch Control Register | ||
| 48 | uint32_t RESERVED5[63]; //!< 0x204 ~ 0x2FC Reserved | ||
| 49 | __IO uint32_t SBVT[4]; //!< 0x300 ~ 0x30C SRAM Booting Vector (4x32Bit) | ||
| 50 | #if defined(HT32F165x) | ||
| 51 | #else | ||
| 52 | __IO uint32_t CID[4]; //!< 0x310 ~ 0x31C Custom ID Register | ||
| 53 | #endif | ||
| 54 | } FMC_TypeDef; | ||
| 55 | |||
| 56 | #define FMC_OCMR_CMD_MASK (0xF << 0) | ||
| 57 | #define FMC_OCMR_CMD_IDLE (0x0 << 0) | ||
| 58 | #define FMC_OCMR_CMD_WORD_PROGRAM (0x4 << 0) | ||
| 59 | #define FMC_OCMR_CMD_PAGE_ERASE (0x8 << 0) | ||
| 60 | #define FMC_OCMR_CMD_MASS_ERASE (0xA << 0) | ||
| 61 | #define FMC_OPCR_OPM_MASK (0xF << 1) | ||
| 62 | #define FMC_OPCR_OPM_IDLE (0x6 << 1) | ||
| 63 | #define FMC_OPCR_OPM_COMMIT (0xA << 1) | ||
| 64 | #define FMC_OPCR_OPM_FINISHED (0xE << 1) | ||
| 65 | #define FMC_CFCR_CE (1U << 12) | ||
| 66 | #define FMC_CFCR_WAIT_MASK (7U << 0) | ||
| 67 | #define FMC_CFCR_WAIT_0 (1U) | ||
| 68 | #define FMC_CFCR_WAIT_1 (2U) | ||
| 69 | |||
| 70 | // Power Control Unit | ||
| 71 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 72 | typedef struct { | ||
| 73 | uint32_t RESERVE0[64]; | ||
| 74 | __IO uint32_t BAKSR; //!< 0x000 Status Register | ||
| 75 | __IO uint32_t BAKCR; //!< 0x004 Control Register | ||
| 76 | __IO uint32_t BAKTEST; //!< 0x008 Test Register | ||
| 77 | __IO uint32_t HSIRCR; //!< 0x00C HSI Ready Counter Control Register | ||
| 78 | __IO uint32_t LVDCSR; //!< 0x010 Low Voltage/Brown Out Detect Control and Status Register | ||
| 79 | uint32_t RESERVE1[59]; //!< 0x014 ~ 0x0FC Reserved | ||
| 80 | __IO uint32_t BAKREG[10]; //!< 0x100 ~ 0x124 Backup Register 0 ~ 9 | ||
| 81 | } PWRCU_TypeDef; | ||
| 82 | |||
| 83 | // Clock Control Unit | ||
| 84 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 85 | typedef struct { | ||
| 86 | __IO uint32_t GCFGR; //!< 0x000 Global Clock Configuration Register | ||
| 87 | __IO uint32_t GCCR; //!< 0x004 Global Clock Control Register | ||
| 88 | __IO uint32_t GCSR; //!< 0x008 Global Clock Status Register | ||
| 89 | __IO uint32_t GCIR; //!< 0x00C Global Clock Interrupt Register | ||
| 90 | uint32_t RESERVED0[2]; //!< 0x010 ~ 0x014 Reserved | ||
| 91 | __IO uint32_t PLLCFGR; //!< 0x018 PLL Configuration Register | ||
| 92 | __IO uint32_t PLLCR; //!< 0x01C PLL Control Register | ||
| 93 | __IO uint32_t AHBCFGR; //!< 0x020 AHB Configuration Register | ||
| 94 | __IO uint32_t AHBCCR; //!< 0x024 AHB Clock Control Register | ||
| 95 | __IO uint32_t APBCFGR; //!< 0x028 APB Configuration Register | ||
| 96 | __IO uint32_t APBCCR0; //!< 0x02C APB Clock Control Register 0 | ||
| 97 | __IO uint32_t APBCCR1; //!< 0x030 APB Clock Control Register 1 | ||
| 98 | __IO uint32_t CKST; //!< 0x034 Clock source status Register | ||
| 99 | |||
| 100 | __IO uint32_t APBPCSR0; //!< 0x038 APB Peripheral Clock Selection Register 0 | ||
| 101 | __IO uint32_t APBPCSR1; //!< 0x03C APB Peripheral Clock Selection Register 1 | ||
| 102 | __IO uint32_t HSICR; //!< 0x040 HSI Control Register | ||
| 103 | __IO uint32_t HSIATCR; //!< 0x044 HSI Auto Trimming Counter Register | ||
| 104 | |||
| 105 | uint32_t RESERVED2[174]; //!< 0x048 ~ 0x2FC Reserved | ||
| 106 | __IO uint32_t LPCR; //!< 0x300 Low Power Control Register | ||
| 107 | __IO uint32_t MCUDBGCR; //!< 0x304 MCU Debug Control Register | ||
| 108 | } CKCU_TypeDef; | ||
| 109 | |||
| 110 | #define CKCU_GCFGR_LPMOD_MASK (7U << 29) | ||
| 111 | #define CKCU_GCFGR_USBPRE_MASK (3U << 22) | ||
| 112 | #define CKCU_GCFGR_PLLSRC (1U << 8) | ||
| 113 | #define CKCU_GCFGR_CKOUTSRC_MASK (7U << 0) | ||
| 114 | #define CKCU_GCFGR_CKOUTSRC_CK_REF (0U << 0) | ||
| 115 | #define CKCU_GCFGR_CKOUTSRC_CK_AHB (1U << 0) | ||
| 116 | #define CKCU_GCFGR_CKOUTSRC_CK_SYS (2U << 0) | ||
| 117 | #define CKCU_GCFGR_CKOUTSRC_CK_HSE (3U << 0) | ||
| 118 | #define CKCU_GCFGR_CKOUTSRC_CK_HSI (4U << 0) | ||
| 119 | #define CKCU_GCFGR_CKOUTSRC_CK_LSE (5U << 0) | ||
| 120 | #define CKCU_GCFGR_CKOUTSRC_CK_LSI (6U << 0) | ||
| 121 | #define CKCU_GCCR_PSRCEN (1U << 17) | ||
| 122 | #define CKCU_GCCR_CKMEN (1U << 16) | ||
| 123 | #define CKCU_GCCR_HSIEN (1U << 11) | ||
| 124 | #define CKCU_GCCR_HSEEN (1U << 10) | ||
| 125 | #define CKCU_GCCR_PLLEN (1U << 9) | ||
| 126 | #define CKCU_GCCR_SW_MASK (3U << 0) | ||
| 127 | #define CKCU_GCCR_SW_PLL (1U << 0) | ||
| 128 | #define CKCU_GCCR_SW_HSE (2U << 0) | ||
| 129 | #define CKCU_GCCR_SW_HSI (3U << 0) | ||
| 130 | #define CKCU_GCSR_LSIRDY (1U << 5) | ||
| 131 | #define CKCU_GCSR_LSERDY (1U << 4) | ||
| 132 | #define CKCU_GCSR_HSIRDY (1U << 3) | ||
| 133 | #define CKCU_GCSR_HSERDY (1U << 2) | ||
| 134 | #define CKCU_GCSR_PLLRDY (1U << 1) | ||
| 135 | #define CKCU_PLLCFGR_PFBD_MASK (0x3fU << 23) | ||
| 136 | #define CKCU_PLLCFGR_POTD_MASK (3U << 21) | ||
| 137 | #define CKCU_PLLCR_PLLBPS (1U << 31) | ||
| 138 | #define CKCU_AHBCFGR_AHBPRE_MASK (3U << 0) | ||
| 139 | #define CKCU_AHBCCR_PAEN (1U << 16) | ||
| 140 | #define CKCU_AHBCCR_CRCEN (1U << 13) | ||
| 141 | #define CKCU_AHBCCR_EBIEN (1U << 12) | ||
| 142 | #define CKCU_AHBCCR_CKREFEN (1U << 11) | ||
| 143 | #define CKCU_AHBCCR_USBEN (1U << 10) | ||
| 144 | #define CKCU_APBCFGR_ADCDIV_MASK (7U << 16) | ||
| 145 | #define CKCU_APBCCR0_I2SEN (1U << 25) | ||
| 146 | #define CKCU_APBCCR0_SCIEN (1U << 24) | ||
| 147 | #define CKCU_APBCCR0_EXTIEN (1U << 15) | ||
| 148 | #define CKCU_APBCCR0_AFIOEN (1U << 14) | ||
| 149 | #define CKCU_APBCCR0_UR1EN (1U << 11) | ||
| 150 | #define CKCU_APBCCR0_UR0EN (1U << 10) | ||
| 151 | #define CKCU_APBCCR0_USR1EN (1U << 9) | ||
| 152 | #define CKCU_APBCCR0_USR0EN (1U << 8) | ||
| 153 | #define CKCU_APBCCR0_SPI1EN (1U << 5) | ||
| 154 | #define CKCU_APBCCR0_SPI0EN (1U << 4) | ||
| 155 | #define CKCU_APBCCR0_I2C1EN (1U << 1) | ||
| 156 | #define CKCU_APBCCR0_I2C0EN (1U << 0) | ||
| 157 | #define CKCU_APBCCR1_ADCEN (1U << 24) | ||
| 158 | #define CKCU_APBCCR1_OPA1EN (1U << 23) | ||
| 159 | #define CKCU_APBCCR1_OPA0EN (1U << 22) | ||
| 160 | #define CKCU_APBCCR1_BFTM1EN (1U << 17) | ||
| 161 | #define CKCU_APBCCR1_BFTM0EN (1U << 16) | ||
| 162 | #define CKCU_APBCCR1_GPTM1EN (1U << 9) | ||
| 163 | #define CKCU_APBCCR1_GPTM0EN (1U << 8) | ||
| 164 | #define CKCU_APBCCR1_BKPREN (1U << 6) | ||
| 165 | #define CKCU_APBCCR1_WDTREN (1U << 4) | ||
| 166 | #define CKCU_APBCCR1_MCTM1EN (1U << 1) | ||
| 167 | #define CKCU_APBCCR1_MCTM0EN (1U << 0) | ||
| 168 | #define CKCU_CKST_CKSWST_MASK (3U << 30) | ||
| 169 | #define CKCU_CKST_HSIST_MASK (7U << 24) | ||
| 170 | #define CKCU_CKST_HSEST_MASK (3U << 16) | ||
| 171 | #define CKCU_CKST_PLLST_MASK (0xfU << 8) | ||
| 172 | #define CKCU_LPCR_USBSLEEP (1U << 8) | ||
| 173 | #define CKCU_LPCR_BKISO (1U << 0) | ||
| 174 | |||
| 175 | // Reset Control Unit | ||
| 176 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 177 | typedef struct { | ||
| 178 | __IO uint32_t GRSR; //!< 0x000 Global Reset Status Register | ||
| 179 | __IO uint32_t AHBPRSTR; //!< 0x004 AHB Peripheral Reset Register | ||
| 180 | __IO uint32_t APBPRSTR0; //!< 0x008 APB Peripheral Reset Register 0 | ||
| 181 | __IO uint32_t APBPRSTR1; //!< 0x00C APB Peripheral Reset Register 1 | ||
| 182 | } RSTCU_TypeDef; | ||
| 183 | |||
| 184 | #define RSTCU_GRSR_PORSTF (1U << 3) | ||
| 185 | #define RSTCU_GRSR_WDTRSTF (1U << 2) | ||
| 186 | #define RSTCU_GRSR_EXTRSTF (1U << 1) | ||
| 187 | #define RSTCU_GRSR_SYSRSTF (1U << 0) | ||
| 188 | #define RSTCU_AHBPRSTR_PxRST(n) ((1U << 8) << (n)) | ||
| 189 | #define RSTCU_AHBPRSTR_CRCRST (1U << 7) | ||
| 190 | #define RSTCU_AHBPRSTR_EBIRST (1U << 6) | ||
| 191 | #define RSTCU_AHBPRSTR_USBRST (1U << 5) | ||
| 192 | #define RSTCU_AHBPRSTR_DMARST (1U << 0) | ||
| 193 | #define RSTCU_APBPRSTR0_I2SRST (1U << 25) | ||
| 194 | #define RSTCU_APBPRSTR0_SCIRST (1U << 24) | ||
| 195 | #define RSTCU_APBPRSTR0_EXTIRST (1U << 15) | ||
| 196 | #define RSTCU_APBPRSTR0_AFIORST (1U << 14) | ||
| 197 | #define RSTCU_APBPRSTR0_UR1RST (1U << 11) | ||
| 198 | #define RSTCU_APBPRSTR0_UR0RST (1U << 10) | ||
| 199 | #define RSTCU_APBPRSTR0_USR1RST (1U << 9) | ||
| 200 | #define RSTCU_APBPRSTR0_USR0RST (1U << 8) | ||
| 201 | #define RSTCU_APBPRSTR0_SPI1RST (1U << 5) | ||
| 202 | #define RSTCU_APBPRSTR0_SPI0RST (1U << 4) | ||
| 203 | #define RSTCU_APBPRSTR0_I2C1RST (1U << 1) | ||
| 204 | #define RSTCU_APBPRSTR0_I2C0RST (1U << 0) | ||
| 205 | #define RSTCU_APBPRSTR1_ADCRST (1U << 24) | ||
| 206 | #define RSTCU_APBPRSTR1_OPA1RST (1U << 23) | ||
| 207 | #define RSTCU_APBPRSTR1_OPA0RST (1U << 22) | ||
| 208 | #define RSTCU_APBPRSTR1_BFTM1RST (1U << 17) | ||
| 209 | #define RSTCU_APBPRSTR1_BFTM0RST (1U << 16) | ||
| 210 | #define RSTCU_APBPRSTR1_GPTM1RST (1U << 9) | ||
| 211 | #define RSTCU_APBPRSTR1_GPTM0RST (1U << 8) | ||
| 212 | #define RSTCU_APBPRSTR1_WDTRST (1U << 4) | ||
| 213 | #define RSTCU_APBPRSTR1_MCTM1RST (1U << 1) | ||
| 214 | #define RSTCU_APBPRSTR1_MCTM0RST (1U << 0) | ||
| 215 | |||
| 216 | // General Purpose I/O | ||
| 217 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 218 | typedef struct { | ||
| 219 | __IO uint32_t DIRCR; //!< 0x000 Data Direction Control Register | ||
| 220 | __IO uint32_t INER; //!< 0x004 Input function enable register | ||
| 221 | __IO uint32_t PUR; //!< 0x008 Pull-Up Selection Register | ||
| 222 | __IO uint32_t PDR; //!< 0x00C Pull-Down Selection Register | ||
| 223 | __IO uint32_t ODR; //!< 0x010 Open Drain Selection Register | ||
| 224 | __IO uint32_t DRVR; //!< 0x014 Drive Current Selection Register | ||
| 225 | __IO uint32_t LOCKR; //!< 0x018 Lock Register | ||
| 226 | __IO uint32_t DINR; //!< 0x01c Data Input Register | ||
| 227 | __IO uint32_t DOUTR; //!< 0x020 Data Output Register | ||
| 228 | __IO uint32_t SRR; //!< 0x024 Output Set and Reset Control Register | ||
| 229 | __IO uint32_t RR; //!< 0x028 Output Reset Control Register | ||
| 230 | } GPIO_TypeDef; | ||
| 231 | |||
| 232 | // Alternate Function Input/Output | ||
| 233 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 234 | typedef struct { | ||
| 235 | __IO uint32_t ESSR[2]; //!< 0x000 ~ 0x004 EXTI Source Selection Register 0 ~ 1 | ||
| 236 | uint32_t RESERVE0[6]; //!< 0x008 ~ 0x01C Reserved | ||
| 237 | union { | ||
| 238 | struct { | ||
| 239 | __IO uint32_t GPACFGR[2]; //!< 0x020 ~ 0x024 GPIO Port A Configuration Register 0 ~ 1 | ||
| 240 | __IO uint32_t GPBCFGR[2]; //!< 0x028 ~ 0x02C GPIO Port B Configuration Register 0 ~ 1 | ||
| 241 | __IO uint32_t GPCCFGR[2]; //!< 0x030 ~ 0x034 GPIO Port C Configuration Register 0 ~ 1 | ||
| 242 | __IO uint32_t GPDCFGR[2]; //!< 0x038 ~ 0x03C GPIO Port D Configuration Register 0 ~ 1 | ||
| 243 | }; | ||
| 244 | // alternate mapping | ||
| 245 | struct { | ||
| 246 | __IO uint32_t GPxCFGR[0][2]; //!< 0x020 ~ 0x03C GPIO Port x Configuration Register 0 ~ 1 | ||
| 247 | }; | ||
| 248 | }; | ||
| 249 | } AFIO_TypeDef; | ||
| 250 | |||
| 251 | // Nested Vectored Interrupt Controller | ||
| 252 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 253 | // Implemented in Cortex-M3 Headers | ||
| 254 | |||
| 255 | // External Interrupt/Event Controller | ||
| 256 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 257 | typedef struct { | ||
| 258 | __IO uint32_t CFGR0; //!< 0x000 EXTI Interrupt 0 Configuration Register | ||
| 259 | __IO uint32_t CFGR1; //!< 0x004 EXTI Interrupt 1 Configuration Register | ||
| 260 | __IO uint32_t CFGR2; //!< 0x008 EXTI Interrupt 2 Configuration Register | ||
| 261 | __IO uint32_t CFGR3; //!< 0x00C EXTI Interrupt 3 Configuration Register | ||
| 262 | __IO uint32_t CFGR4; //!< 0x010 EXTI Interrupt 4 Configuration Register | ||
| 263 | __IO uint32_t CFGR5; //!< 0x014 EXTI Interrupt 5 Configuration Register | ||
| 264 | __IO uint32_t CFGR6; //!< 0x018 EXTI Interrupt 6 Configuration Register | ||
| 265 | __IO uint32_t CFGR7; //!< 0x01C EXTI Interrupt 7 Configuration Register | ||
| 266 | __IO uint32_t CFGR8; //!< 0x020 EXTI Interrupt 8 Configuration Register | ||
| 267 | __IO uint32_t CFGR9; //!< 0x024 EXTI Interrupt 9 Configuration Register | ||
| 268 | __IO uint32_t CFGR10; //!< 0x028 EXTI Interrupt 10 Configuration Register | ||
| 269 | __IO uint32_t CFGR11; //!< 0x02C EXTI Interrupt 11 Configuration Register | ||
| 270 | __IO uint32_t CFGR12; //!< 0x030 EXTI Interrupt 12 Configuration Register | ||
| 271 | __IO uint32_t CFGR13; //!< 0x034 EXTI Interrupt 13 Configuration Register | ||
| 272 | __IO uint32_t CFGR14; //!< 0x038 EXTI Interrupt 14 Configuration Register | ||
| 273 | __IO uint32_t CFGR15; //!< 0x03C EXTI Interrupt 15 Configuration Register | ||
| 274 | __IO uint32_t CR; //!< 0x040 EXTI Interrupt Control Register | ||
| 275 | __IO uint32_t EDGEFLGR; //!< 0x044 EXTI Interrupt Edge Flag Register | ||
| 276 | __IO uint32_t EDGESR; //!< 0x048 EXTI Interrupt Edge Status Register | ||
| 277 | __IO uint32_t SSCR; //!< 0x04C EXTI Interrupt Software Set Command Register | ||
| 278 | __IO uint32_t WAKUPCR; //!< 0x050 EXTI Interrupt Wakeup Control Register | ||
| 279 | __IO uint32_t WAKUPPOLR; //!< 0x054 EXTI Interrupt Wakeup Polarity Register | ||
| 280 | __IO uint32_t WAKUPFLG; //!< 0x058 EXTI Interrupt Wakeup Flag Register | ||
| 281 | } EXTI_TypeDef; | ||
| 282 | |||
| 283 | // Analog To Digital Converter | ||
| 284 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 285 | |||
| 286 | // Operational Amplifier / Comparator | ||
| 287 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 288 | typedef struct { | ||
| 289 | __IO uint32_t CR; //!< 0x000 Comparator Control Register | ||
| 290 | __IO uint32_t VALR; //!< 0x004 Comparator Voltage Reference Register | ||
| 291 | __IO uint32_t IER; //!< 0x008 Comparator Interrupt Enable Register | ||
| 292 | __IO uint32_t TFR; //!< 0x00C Comparator Transition Flag Register | ||
| 293 | } CMP_TypeDef; | ||
| 294 | |||
| 295 | |||
| 296 | // Basic Function Timers | ||
| 297 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 298 | typedef struct { | ||
| 299 | __IO uint32_t CR; //!< 0x000 Control Register | ||
| 300 | __IO uint32_t SR; //!< 0x004 Status Register | ||
| 301 | __IO uint32_t CNTR; //!< 0x008 Counter Value Register | ||
| 302 | __IO uint32_t CMP; //!< 0x00C Compare Value Register | ||
| 303 | } BFTM_TypeDef; | ||
| 304 | |||
| 305 | #define BFTM_CR_CEN (1U << 2) | ||
| 306 | #define BFTM_CR_OSM (1U << 1) | ||
| 307 | #define BFTM_CR_MIEN (1U << 0) | ||
| 308 | #define BFTM_SR_MIF (1U << 0) | ||
| 309 | |||
| 310 | // General Purpose Timers | ||
| 311 | // Motor Control Timers | ||
| 312 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 313 | typedef struct { | ||
| 314 | __IO uint32_t CNTCFR; //!< 0x000 Timer Counter Configuaration Register | ||
| 315 | __IO uint32_t MDCFR; //!< 0x004 Timer Mode Configuration Register | ||
| 316 | __IO uint32_t TRCFR; //!< 0x008 Timer Trigger Configuration Register | ||
| 317 | uint32_t RESERVED0[1]; //!< 0x00C Reserved | ||
| 318 | __IO uint32_t CTR; //!< 0x010 Timer Counter Register | ||
| 319 | uint32_t RESERVED1[3]; //!< 0x014 ~ 0x01C Reserved | ||
| 320 | __IO uint32_t CHnICFR[4]; //!< 0x020 ~ 0x02C Channel n Input Configuration Register | ||
| 321 | uint32_t RESERVED2[4]; //!< 0x030 ~ 0x03C Reserved | ||
| 322 | __IO uint32_t CHnOCFR[4]; //!< 0x040 ~ 0x04C Channel n Output Configuration Register | ||
| 323 | __IO uint32_t CHCTR; //!< 0x050 Channel Control Register | ||
| 324 | __IO uint32_t CHPOLR; //!< 0x054 Channel Polarity Control Register | ||
| 325 | uint32_t RESERVED3[5]; //!< 0x058 ~ 0x068 Reserved | ||
| 326 | // note: only available as MCTM | ||
| 327 | __IO uint32_t CHBRKCFR; //!< 0x06C Channel Break Configuration Register | ||
| 328 | __IO uint32_t CHBRKCTR; //!< 0x070 Channel Break Control Register | ||
| 329 | // end note | ||
| 330 | __IO uint32_t DICTR; //!< 0x074 Timer PDMA/Interrupt Control Register | ||
| 331 | __IO uint32_t EVGR; //!< 0x078 Timer Event Generator Register | ||
| 332 | __IO uint32_t INTSR; //!< 0x07C Timer Interrupt Status Register | ||
| 333 | __IO uint32_t CNTR; //!< 0x080 Timer Counter Register | ||
| 334 | __IO uint32_t PSCR; //!< 0x084 Timer Prescaler Register | ||
| 335 | __IO uint32_t CRR; //!< 0x088 Timer Counter Reload Register | ||
| 336 | // note: only available as MCTM | ||
| 337 | __IO uint32_t REPR; //!< 0x08C Timer Repetition Register | ||
| 338 | // end note | ||
| 339 | __IO uint32_t CHnCCR[4]; //!< 0x090 ~ 0x09C Channel n Capture/Compare Register | ||
| 340 | __IO uint32_t CHnACR[4]; //!< 0x0A0 ~ 0x0AC Channel n Asymmentric Compare Register | ||
| 341 | } TM_TypeDef; | ||
| 342 | |||
| 343 | #define TM_CNTCFR_CMSEL_MASK (3U << 16) | ||
| 344 | #define TM_CNTCFR_CMSEL_MODE_3 (3U << 16) | ||
| 345 | #define TM_CNTCFR_CMSEL_MODE_2 (2U << 16) | ||
| 346 | #define TM_CNTCFR_CMSEL_MODE_1 (1U << 16) | ||
| 347 | #define TM_CNTCFR_CMSEL_MODE_0 (0U << 16) | ||
| 348 | #define TM_CTR_CHCCDS (1U << 16) | ||
| 349 | #define TM_CTR_COMUS (1U << 9) | ||
| 350 | #define TM_CTR_COMPRE (1U << 8) | ||
| 351 | #define TM_CTR_CRBE (1U << 1) | ||
| 352 | #define TM_CTR_TME (1U << 0) | ||
| 353 | #define TM_CHnOCFR_CHnPRE (1U << 4) | ||
| 354 | #define TM_CHnOCFR_REFnCE (1U << 3) | ||
| 355 | #define TM_CHnOCFR_CHnOM(n) ((((n)>>0)&7)|((((n)>>3)&1)<<8)) | ||
| 356 | #define TM_CHBRKCTR_CHMOE (1U << 4) | ||
| 357 | |||
| 358 | // Real Time Clock | ||
| 359 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 360 | |||
| 361 | // Watchdog Timer | ||
| 362 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 363 | |||
| 364 | // I2C | ||
| 365 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 366 | typedef struct { | ||
| 367 | __IO uint32_t CR; //!< 0x000 Control Register | ||
| 368 | __IO uint32_t IER; //!< 0x004 Interrupt Enable Register | ||
| 369 | __IO uint32_t ADDR; //!< 0x008 Address Register | ||
| 370 | __IO uint32_t SR; //!< 0x00C Status Register | ||
| 371 | __IO uint32_t SHPGR; //!< 0x010 SCL High Period Generation Register | ||
| 372 | __IO uint32_t SLPGR; //!< 0x014 SCL Low Period Generation Register | ||
| 373 | __IO uint32_t DR; //!< 0x018 Data Register | ||
| 374 | __IO uint32_t TAR; //!< 0x01C Target Register | ||
| 375 | __IO uint32_t ADDMR; //!< 0x020 Address Mask Register | ||
| 376 | __IO uint32_t ADDSR; //!< 0x024 Address Snoop Register | ||
| 377 | __IO uint32_t TOUT; //!< 0x028 Timeout Register | ||
| 378 | } I2C_TypeDef; | ||
| 379 | |||
| 380 | #define I2C_CR_SEQ_FILTER_MASK (3U << 14) | ||
| 381 | #define I2C_CR_SEQ_FILTER_2_PCLK (2U << 14) | ||
| 382 | #define I2C_CR_SEQ_FILTER_1_PCLK (1U << 14) | ||
| 383 | #define I2C_CR_SEQ_FILTER_DISABLE (0U << 14) | ||
| 384 | #define I2C_CR_COMB_FILTER_En (1U << 13) | ||
| 385 | #define I2C_CR_ENTOUT (1U << 12) | ||
| 386 | #define I2C_CR_DMANACK (1U << 10) | ||
| 387 | #define I2C_CR_RXDMAE (1U << 9) | ||
| 388 | #define I2C_CR_TXDMAE (1U << 8) | ||
| 389 | #define I2C_CR_ADRM (1U << 7) | ||
| 390 | #define I2C_CR_I2CEN (1U << 3) | ||
| 391 | #define I2C_CR_GCEN (1U << 2) | ||
| 392 | #define I2C_CR_STOP (1U << 1) | ||
| 393 | #define I2C_CR_AA (1U << 0) | ||
| 394 | #define I2C_IER_RXBFIE (1U << 18) | ||
| 395 | #define I2C_IER_TXDEIE (1U << 17) | ||
| 396 | #define I2C_IER_RXDNEIE (1U << 16) | ||
| 397 | #define I2C_IER_TOUTIE (1U << 11) | ||
| 398 | #define I2C_IER_BUSERRIE (1U << 10) | ||
| 399 | #define I2C_IER_RXNACKIE (1U << 9) | ||
| 400 | #define I2C_IER_ARBLOSIE (1U << 8) | ||
| 401 | #define I2C_IER_GCSIE (1U << 3) | ||
| 402 | #define I2C_IER_ADRSIE (1U << 2) | ||
| 403 | #define I2C_IER_STOIE (1U << 1) | ||
| 404 | #define I2C_IER_STAIE (1U << 0) | ||
| 405 | #define I2C_SR_TXNRX (1U << 21) | ||
| 406 | #define I2C_SR_MASTER (1U << 20) | ||
| 407 | #define I2C_SR_BUSBUSY (1U << 19) | ||
| 408 | #define I2C_SR_RXBF (1U << 18) | ||
| 409 | #define I2C_SR_TXDE (1U << 17) | ||
| 410 | #define I2C_SR_RXDNE (1U << 16) | ||
| 411 | #define I2C_SR_TOUTF (1U << 11) | ||
| 412 | #define I2C_SR_BUSERR (1U << 10) | ||
| 413 | #define I2C_SR_RXNACK (1U << 9) | ||
| 414 | #define I2C_SR_ARBLOS (1U << 8) | ||
| 415 | #define I2C_SR_GCS (1U << 3) | ||
| 416 | #define I2C_SR_ADRS (1U << 2) | ||
| 417 | #define I2C_SR_STO (1U << 1) | ||
| 418 | #define I2C_SR_STA (1U << 0) | ||
| 419 | #define I2C_TAR_RWD (1U << 10) | ||
| 420 | |||
| 421 | // SPI | ||
| 422 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 423 | typedef struct { | ||
| 424 | __IO uint32_t CR0; //!< 0x000 Control Register 0 | ||
| 425 | __IO uint32_t CR1; //!< 0x004 Control Register 1 | ||
| 426 | __IO uint32_t IER; //!< 0x008 Interrupt Enable Register | ||
| 427 | __IO uint32_t CPR; //!< 0x00C Clock Prescaler Register | ||
| 428 | __IO uint32_t DR; //!< 0x010 Data Register | ||
| 429 | __IO uint32_t SR; //!< 0x014 Status Register | ||
| 430 | __IO uint32_t FCR; //!< 0x018 FIFO Control Register | ||
| 431 | __IO uint32_t FSR; //!< 0x01C FIFO Status Register | ||
| 432 | __IO uint32_t FTOCR; //!< 0x020 FIFO Time Out Counter Register | ||
| 433 | } SPI_TypeDef; | ||
| 434 | |||
| 435 | #define SPI_CR0_GUADTEN (1U << 7) | ||
| 436 | #define SPI_CR0_DUALEN (1U << 6) | ||
| 437 | #define SPI_CR0_SSELC (1U << 4) | ||
| 438 | #define SPI_CR0_SELOEN (1U << 3) | ||
| 439 | #define SPI_CR0_SPIEN (1U << 0) | ||
| 440 | #define SPI_CR1_MODE (1U << 14) | ||
| 441 | #define SPI_CR1_SELM (1U << 13) | ||
| 442 | #define SPI_CR1_FIRSTBIT (1U << 12) | ||
| 443 | #define SPI_CR1_SELAP (1U << 11) | ||
| 444 | #define SPI_CR1_FORMAT_MASK (7U << 8) | ||
| 445 | #define SPI_CR1_FORMAT_MODE0 (0x1U << 8) | ||
| 446 | #define SPI_CR1_FORMAT_MODE1 (0x2U << 8) | ||
| 447 | #define SPI_CR1_FORMAT_MODE2 (0x6U << 8) | ||
| 448 | #define SPI_CR1_FORMAT_MODE3 (0x5U << 8) | ||
| 449 | #define SPI_IER_RXBNEIEN (1U << 2) | ||
| 450 | #define SPI_IER_TXBEIEN (1U << 0) | ||
| 451 | #define SPI_SR_RXBNE (1U << 2) | ||
| 452 | #define SPI_SR_TXE (1U << 1) | ||
| 453 | #define SPI_SR_TXBE (1U << 0) | ||
| 454 | #define SPI_FCR_FIFOEN (1U << 10) | ||
| 455 | #define SPI_FSR_TXFS_MASK (0xfU << 0) | ||
| 456 | #define SPI_FSR_RXFS_MASK (0xfU << 4) | ||
| 457 | |||
| 458 | // USART | ||
| 459 | // UART | ||
| 460 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 461 | typedef struct { | ||
| 462 | __IO uint32_t DR; //!< 0x000 Data Register | ||
| 463 | __IO uint32_t CR; //!< 0x004 Control Register | ||
| 464 | // Only USART | ||
| 465 | __IO uint32_t FCR; //!< 0x008 FIFO Control Register | ||
| 466 | __IO uint32_t IER; //!< 0x00C Interrupt Enable Register | ||
| 467 | __IO uint32_t SIFR; //!< 0x010 Status & Interrupt Flag Register | ||
| 468 | |||
| 469 | __IO uint32_t TPR; //!< 0x014 Timing Parameter Register | ||
| 470 | |||
| 471 | __IO uint32_t IrDACR; //!< 0x018 IrDA Control Register | ||
| 472 | __IO uint32_t RS485CR; //!< 0x01C RS485 Control Register | ||
| 473 | __IO uint32_t SYNCR; //!< 0x020 Synchronous Control Register | ||
| 474 | // end note | ||
| 475 | __IO uint32_t DLR; //!< 0x024 Divider Latch Register | ||
| 476 | __IO uint32_t TSTR; //!< 0x028 Debug/Test Register | ||
| 477 | } USART_TypeDef; | ||
| 478 | |||
| 479 | // USART CR | ||
| 480 | #define UART_CR_MODE_MASK (0b11 << 0) | ||
| 481 | #define UART_CR_MODE_NORMAL (0 << 0) | ||
| 482 | #define UART_CR_TRSM (1 << 2) | ||
| 483 | #define UART_CR_HFCEN (1 << 3) | ||
| 484 | #define UART_CR_URTXEN (1 << 4) | ||
| 485 | #define UART_CR_URRXEN (1 << 5) | ||
| 486 | #define UART_CR_TXDMAEN (1 << 6) | ||
| 487 | #define UART_CR_RXDMAEN (1 << 7) | ||
| 488 | #define UART_CR_WLS_MASK (0b11 << 8) | ||
| 489 | #define UART_CR_WLS_7B (0b00 << 8) | ||
| 490 | #define UART_CR_WLS_8B (0b01 << 8) | ||
| 491 | #define UART_CR_WLS_9B (0b10 << 8) | ||
| 492 | #define UART_CR_NSB (1 << 10) | ||
| 493 | #define UART_CR_PBE (1 << 11) | ||
| 494 | #define UART_CR_EPE (1 << 12) | ||
| 495 | #define UART_CR_SPE (1 << 13) | ||
| 496 | #define UART_CR_BCB (1 << 14) | ||
| 497 | #define UART_CR_RTS (1 << 15) | ||
| 498 | // USART FCR (FIFO CR) | ||
| 499 | #define USART_FCR_TXR (1 << 0) | ||
| 500 | #define USART_FCR_RXR (1 << 1) | ||
| 501 | #define USART_FCR_TXTL_MASK (0b11 << 4) | ||
| 502 | #define USART_FCR_RXTL_MASK (0b11 << 6) | ||
| 503 | #define USART_FCR_TXFS_MASK (0xF << 16) | ||
| 504 | #define USART_FCR_RXFS_MASK (0xF << 24) | ||
| 505 | // USART SIFR Status and Interrupt Flag Register | ||
| 506 | #define USART_SIFR_RXDNE (1 << 0) | ||
| 507 | #define USART_SIFR_OEI (1 << 1) | ||
| 508 | #define USART_SIFR_PEI (1 << 2) | ||
| 509 | #define USART_SIFR_FEI (1 << 3) | ||
| 510 | #define USART_SIFR_BII (1 << 4) | ||
| 511 | #define USART_SIFR_RXDR (1 << 5) | ||
| 512 | #define USART_SIFR_RXTOF (1 << 6) | ||
| 513 | #define USART_SIFR_TXDE (1 << 7) | ||
| 514 | #define USART_SIFR_TXC (1 << 8) | ||
| 515 | #define USART_SIFR_RSADDE (1 << 9) | ||
| 516 | #define USART_SIFR_CTSC (1 << 10) | ||
| 517 | #define USART_SIFR_CTSS (1 << 11) | ||
| 518 | // USART IER | ||
| 519 | #define USART_IER_RXDRIE (1 << 0) | ||
| 520 | #define USART_IER_TXDEIE (1 << 1) | ||
| 521 | #define USART_IER_TXCIE (1 << 2) | ||
| 522 | #define USART_IER_OEIE (1 << 3) | ||
| 523 | #define USART_IER_PEIE (1 << 4) | ||
| 524 | #define USART_IER_FEIE (1 << 5) | ||
| 525 | #define USART_IER_BIE (1 << 6) | ||
| 526 | #define USART_IER_RSADDIE (1 << 7) | ||
| 527 | #define USART_IER_RXTOIE (1 << 8) | ||
| 528 | #define USART_IER_CTSIE (1 << 9) | ||
| 529 | |||
| 530 | |||
| 531 | // Smart Card Interface | ||
| 532 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 533 | |||
| 534 | // USB | ||
| 535 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 536 | typedef struct { | ||
| 537 | __IO uint32_t CSR; //!< 0x000 USB Control and Status Register | ||
| 538 | __IO uint32_t IER; //!< 0x004 USB Interrupt Enable Register | ||
| 539 | __IO uint32_t ISR; //!< 0x008 USB Interrupt Status Register | ||
| 540 | __IO uint32_t FCR; //!< 0x00C USB Frame Count Register | ||
| 541 | __IO uint32_t DEVAR; //!< 0x010 USB Device Address Register | ||
| 542 | struct { | ||
| 543 | __IO uint32_t CSR; //!< 0x014 USB Endpoint n Control and Status Register | ||
| 544 | __IO uint32_t IER; //!< 0x018 USB Endpoint n Interrupt Enable Register | ||
| 545 | __IO uint32_t ISR; //!< 0x01C USB Endpoint n Interrupt Status Register | ||
| 546 | __IO uint32_t TCR; //!< 0x020 USB Endpoint n Transfer Count Register | ||
| 547 | __IO uint32_t CFGR; //!< 0x024 USB Endpoint n Configuration Register | ||
| 548 | } EP[8]; | ||
| 549 | } USB_TypeDef; | ||
| 550 | |||
| 551 | // USBCSR | ||
| 552 | #define USBCSR_FRES (0x002) // Force USB Reset Control | ||
| 553 | #define USBCSR_PDWN (0x004) // Power Down Mode Control | ||
| 554 | #define USBCSR_LPMODE (0x008) // Low-Power Mode Control | ||
| 555 | #define USBCSR_GENRSM (0x020) // Resume Request Generation Control | ||
| 556 | #define USBCSR_RXDP (0x040) // Received DP Line Status | ||
| 557 | #define USBCSR_RXDM (0x080) // Received DM Line Status | ||
| 558 | #define USBCSR_ADRSET (0x100) // Device Address Setting Control | ||
| 559 | #define USBCSR_SRAMRSTC (0x200) // USB SRAM Reset Condition | ||
| 560 | #define USBCSR_DPPUEN (0x400) // DP Pull Up Enable | ||
| 561 | #define USBCSR_DPWKEN (0x800) // DP Wake Up Enable | ||
| 562 | |||
| 563 | // USBIER | ||
| 564 | #define USBIER_UGIE (0x0001) // USB global Interrupt Enable | ||
| 565 | #define USBIER_SOFIE (0x0002) // Start Of Frame Interrupt Enable | ||
| 566 | #define USBIER_URSTIE (0x0004) // USB Reset Interrupt Enable | ||
| 567 | #define USBIER_RSMIE (0x0008) // Resume Interrupt Enable | ||
| 568 | #define USBIER_SUSPIE (0x0010) // Suspend Interrupt Enable | ||
| 569 | #define USBIER_ESOFIE (0x0020) // Expected Start Of Frame Enable | ||
| 570 | #define USBIER_EP0IE (0x0100) // Endpoint 0 Interrupt Enable | ||
| 571 | #define USBIER_EP1IE (0x0200) // Endpoint 1 Interrupt Enable | ||
| 572 | #define USBIER_EP2IE (0x0400) // Endpoint 2 Interrupt Enable | ||
| 573 | #define USBIER_EP3IE (0x0800) // Endpoint 3 Interrupt Enable | ||
| 574 | #define USBIER_EP4IE (0x1000) // Endpoint 4 Interrupt Enable | ||
| 575 | #define USBIER_EP5IE (0x2000) // Endpoint 5 Interrupt Enable | ||
| 576 | #define USBIER_EP6IE (0x4000) // Endpoint 6 Interrupt Enable | ||
| 577 | #define USBIER_EP7IE (0x8000) // Endpoint 7 Interrupt Enable | ||
| 578 | |||
| 579 | // USBISR | ||
| 580 | #define USBISR_SOFIF (0x0002) // Start Of Frame Interrupt Flag | ||
| 581 | #define USBISR_URSTIF (0x0004) // USB Reset Interrupt Flag | ||
| 582 | #define USBISR_RSMIF (0x0008) // Resume Interrupt Flag | ||
| 583 | #define USBISR_SUSPIF (0x0010) // Suspend Interrupt Flag | ||
| 584 | #define USBISR_ESOFIF (0x0020) // Expected Start Of Frame Interrupt | ||
| 585 | #define USBISR_EP0IF (1U << 8) // Endpoint 0 Interrupt Flag | ||
| 586 | #define USBISR_EP1IF (1U << 9) // Endpoint 1 Interrupt Flag | ||
| 587 | #define USBISR_EP2IF (1U << 10) // Endpoint 2 Interrupt Flag | ||
| 588 | #define USBISR_EP3IF (1U << 11) // Endpoint 3 Interrupt Flag | ||
| 589 | #define USBISR_EP4IF (1U << 12) // Endpoint 4 Interrupt Flag | ||
| 590 | #define USBISR_EP5IF (1U << 13) // Endpoint 5 Interrupt Flag | ||
| 591 | #define USBISR_EP6IF (1U << 14) // Endpoint 6 Interrupt Flag | ||
| 592 | #define USBISR_EP7IF (1U << 15) // Endpoint 7 Interrupt Flag | ||
| 593 | #define USBISR_EPnIF (0xFF00) // Endpoint Interrupt Mask | ||
| 594 | |||
| 595 | // USBFCR | ||
| 596 | #define USBFCR_FRNUM (0x7FF) // Frame Number | ||
| 597 | #define USBFCR_SOFLCK (1U << 16) // Start-of-Frame Lock Flag | ||
| 598 | #define USBFCR_LSOF (0x3U << 17) // Lost Start-of-Frame Number | ||
| 599 | |||
| 600 | // USBEPnCSR | ||
| 601 | #define USBEPnCSR_DTGTX (0x01) // Data Toggle Status, for IN transfer | ||
| 602 | #define USBEPnCSR_NAKTX (0x02) // NAK Status, for IN transfer | ||
| 603 | #define USBEPnCSR_STLTX (0x04) // STALL Status, for IN transfer | ||
| 604 | #define USBEPnCSR_DTGRX (0x08) // Data Toggle Status, for OUT transfer | ||
| 605 | #define USBEPnCSR_NAKRX (0x10) // NAK Status, for OUT transfer | ||
| 606 | #define USBEPnCSR_STLRX (0x20) // STALL Status, for OUT transfer | ||
| 607 | |||
| 608 | // USBEPnIER | ||
| 609 | #define USBEPnIER_OTRXIE (0x001) // OUT Token Received Interrupt Enable | ||
| 610 | #define USBEPnIER_ODRXIE (0x002) // OUT Data Received Interrupt Enable | ||
| 611 | #define USBEPnIER_ODOVIE (0x004) // OUT Data Buffer Overrun Interrupt Enable | ||
| 612 | #define USBEPnIER_ITRXIE (0x008) // IN Token Received Interrupt Enable | ||
| 613 | #define USBEPnIER_IDTXIE (0x010) // IN Data Transmitted Interrupt Enable | ||
| 614 | #define USBEPnIER_NAKIE (0x020) // NAK Transmitted Interrupt Enable | ||
| 615 | #define USBEPnIER_STLIE (0x040) // STALL Transmitted Interrupt Enable | ||
| 616 | #define USBEPnIER_UERIE (0x080) // USB Error Interrupt Enable | ||
| 617 | #define USBEPnIER_STRXIE (0x100) // SETUP Token Received Interrupt Enable | ||
| 618 | #define USBEPnIER_SDRXIE (0x200) // SETUP Data Received Interrupt Enable | ||
| 619 | #define USBEPnIER_SDERIE (0x400) // SETUP Data Error Interrupt Enable | ||
| 620 | #define USBEPnIER_ZLRXIE (0x800) // Zero Length Data Received Interrupt Enable | ||
| 621 | |||
| 622 | // USBEPnISR | ||
| 623 | #define USBEPnISR_OTRXIF (0x001) // OUT Token Received Interrupt Flag | ||
| 624 | #define USBEPnISR_ODRXIF (0x002) // OUT Data Received Interrupt Flag | ||
| 625 | #define USBEPnISR_ODOVIF (0x004) // OUT Data Buffer Overrun Interrupt Flag | ||
| 626 | #define USBEPnISR_ITRXIF (0x008) // IN Token Received Interrupt Flag | ||
| 627 | #define USBEPnISR_IDTXIF (0x010) // IN Data Transmitted Interrupt Flag | ||
| 628 | #define USBEPnISR_NAKIF (0x020) // NAK Transmitted Interrupt Flag | ||
| 629 | #define USBEPnISR_STLIF (0x040) // STALL Transmitted Interrupt Flag | ||
| 630 | #define USBEPnISR_UERIF (0x080) // USB Error Interrupt Flag | ||
| 631 | #define USBEPnISR_STRXIF (0x100) // SETUP Token Received Interrupt Flag | ||
| 632 | #define USBEPnISR_SDRXIF (0x200) // SETUP Data Received Interrupt Flag | ||
| 633 | #define USBEPnISR_SDERIF (0x400) // SETUP Data Error Interrupt Flag | ||
| 634 | #define USBEPnISR_ZLRXIF (0x800) // Zero Length Data Received Interrupt Flag | ||
| 635 | |||
| 636 | // USBEPnTCR | ||
| 637 | #define USBEPnTCR_TCNT (0x1FF) // Transfer Byte Count | ||
| 638 | |||
| 639 | // USBEPnCFGR | ||
| 640 | #define USBEPnCFGR_EPEN (1U << 31) // Endpoint Enable | ||
| 641 | #define USBEPnCFGR_EPTYPE (1U << 29) // Transfer Type | ||
| 642 | #define USBEPnCFGR_EPDIR (1U << 28) // Transfer Direction | ||
| 643 | #define USBEPnCFGR_EPADR (0xFU << 24) // Endpoint Address | ||
| 644 | #define USBEPnCFGR_EPLEN (0x7FU << 10) // Buffer Length | ||
| 645 | #define USBEPnCFGR_EPBUFA (0x3FF) // Endpoint Buffer Address | ||
| 646 | |||
| 647 | // Peripheral Direct Memory Access | ||
| 648 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 649 | |||
| 650 | // Extend Bus Interface | ||
| 651 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 652 | |||
| 653 | // Inter-IC Sound | ||
| 654 | // ///////////////////////////////////////////////////////////////////////////// | ||
| 655 | |||
| 656 | // CRC | ||
| 657 | // ///////////////////////////////////////////////////////////////////////////// | ||
diff --git a/lib/chibios-contrib/os/common/ext/CMSIS/KINETIS/MK66F18.h b/lib/chibios-contrib/os/common/ext/CMSIS/KINETIS/MK66F18.h new file mode 100644 index 000000000..237089e0c --- /dev/null +++ b/lib/chibios-contrib/os/common/ext/CMSIS/KINETIS/MK66F18.h | |||
| @@ -0,0 +1,21214 @@ | |||
| 1 | /* | ||
| 2 | ** ################################################################### | ||
| 3 | ** Processors: MK66FN2M0VLQ18 | ||
| 4 | ** MK66FN2M0VMD18 | ||
| 5 | ** MK66FX1M0VLQ18 | ||
| 6 | ** MK66FX1M0VMD18 | ||
| 7 | ** | ||
| 8 | ** Compilers: Keil ARM C/C++ Compiler | ||
| 9 | ** Freescale C/C++ for Embedded ARM | ||
| 10 | ** GNU C Compiler | ||
| 11 | ** IAR ANSI C/C++ Compiler for ARM | ||
| 12 | ** MCUXpresso Compiler | ||
| 13 | ** | ||
| 14 | ** Reference manual: K66P144M180SF5RMV2, Rev. 1, Mar 2015 | ||
| 15 | ** Version: rev. 3.0, 2015-03-25 | ||
| 16 | ** Build: b171205 | ||
| 17 | ** | ||
| 18 | ** Abstract: | ||
| 19 | ** CMSIS Peripheral Access Layer for MK66F18 | ||
| 20 | ** | ||
| 21 | ** The Clear BSD License | ||
| 22 | ** Copyright 1997-2016 Freescale Semiconductor, Inc. | ||
| 23 | ** Copyright 2016-2017 NXP | ||
| 24 | ** All rights reserved. | ||
| 25 | ** | ||
| 26 | ** Redistribution and use in source and binary forms, with or without | ||
| 27 | ** modification, are permitted (subject to the limitations in the | ||
| 28 | ** disclaimer below) provided that the following conditions are met: | ||
| 29 | ** | ||
| 30 | ** * Redistributions of source code must retain the above copyright | ||
| 31 | ** notice, this list of conditions and the following disclaimer. | ||
| 32 | ** | ||
| 33 | ** * Redistributions in binary form must reproduce the above copyright | ||
| 34 | ** notice, this list of conditions and the following disclaimer in the | ||
| 35 | ** documentation and/or other materials provided with the distribution. | ||
| 36 | ** | ||
| 37 | ** * Neither the name of the copyright holder nor the names of its | ||
| 38 | ** contributors may be used to endorse or promote products derived from | ||
| 39 | ** this software without specific prior written permission. | ||
| 40 | ** | ||
| 41 | ** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE | ||
| 42 | ** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT | ||
| 43 | ** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED | ||
| 44 | ** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 45 | ** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | ||
| 46 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE | ||
| 47 | ** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
| 48 | ** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
| 49 | ** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
| 50 | ** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
| 51 | ** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
| 52 | ** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
| 53 | ** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 54 | ** | ||
| 55 | ** http: www.nxp.com | ||
| 56 | ** mail: [email protected] | ||
| 57 | ** | ||
| 58 | ** Revisions: | ||
| 59 | ** - rev. 1.0 (2013-09-02) | ||
| 60 | ** Initial version. | ||
| 61 | ** - rev. 2.0 (2014-02-17) | ||
| 62 | ** Register accessor macros added to the memory map. | ||
| 63 | ** Symbols for Processor Expert memory map compatibility added to the memory map. | ||
| 64 | ** Startup file for gcc has been updated according to CMSIS 3.2. | ||
| 65 | ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. | ||
| 66 | ** Update according to reference manual rev. 2 | ||
| 67 | ** - rev. 2.1 (2014-04-16) | ||
| 68 | ** Update of SystemInit() and SystemCoreClockUpdate() functions. | ||
| 69 | ** - rev. 2.2 (2014-10-14) | ||
| 70 | ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. | ||
| 71 | ** - rev. 2.3 (2014-11-20) | ||
| 72 | ** Update according to reverence manual K65P169M180SF5RMV2_NDA, Rev. 0 Draft A, October 2014. | ||
| 73 | ** Update of SystemInit() to use 16MHz external crystal. | ||
| 74 | ** - rev. 2.4 (2015-02-19) | ||
| 75 | ** Renamed interrupt vector LLW to LLWU. | ||
| 76 | ** - rev. 3.0 (2015-03-25) | ||
| 77 | ** Registers updated according to the reference manual revision 1, March 2015 | ||
| 78 | ** - Revised 2018-05-04 by Michael Walker <[email protected]> to support ChibiOS LLD HAL | ||
| 79 | ** Register names and other names updated to match other Kinetis definitions for other MCUs | ||
| 80 | ** | ||
| 81 | ** ################################################################### | ||
| 82 | */ | ||
| 83 | |||
| 84 | /*! | ||
| 85 | * @file MK66F18.h | ||
| 86 | * @version 3.0 | ||
| 87 | * @date 2015-03-25 | ||
| 88 | * @brief CMSIS Peripheral Access Layer for MK66F18 | ||
| 89 | * | ||
| 90 | * CMSIS Peripheral Access Layer for MK66F18 | ||
| 91 | */ | ||
| 92 | |||
| 93 | #ifndef _MK66F18_H_ | ||
| 94 | #define _MK66F18_H_ /**< Symbol preventing repeated inclusion */ | ||
| 95 | |||
| 96 | /** Memory map major version (memory maps with equal major version number are | ||
| 97 | * compatible) */ | ||
| 98 | #define MCU_MEM_MAP_VERSION 0x0300U | ||
| 99 | /** Memory map minor version */ | ||
| 100 | #define MCU_MEM_MAP_VERSION_MINOR 0x0000U | ||
| 101 | |||
| 102 | /** | ||
| 103 | * @brief Macro to calculate address of an aliased word in the peripheral | ||
| 104 | * bitband area for a peripheral register and bit (bit band region 0x40000000 to | ||
| 105 | * 0x400FFFFF). | ||
| 106 | * @param Reg Register to access. | ||
| 107 | * @param Bit Bit number to access. | ||
| 108 | * @return Address of the aliased word in the peripheral bitband area. | ||
| 109 | */ | ||
| 110 | #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) | ||
| 111 | /** | ||
| 112 | * @brief Macro to access a single bit of a peripheral register (bit band region | ||
| 113 | * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can | ||
| 114 | * be used for peripherals with 32bit access allowed. | ||
| 115 | * @param Reg Register to access. | ||
| 116 | * @param Bit Bit number to access. | ||
| 117 | * @return Value of the targeted bit in the bit band region. | ||
| 118 | */ | ||
| 119 | #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) | ||
| 120 | #define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit))) | ||
| 121 | /** | ||
| 122 | * @brief Macro to access a single bit of a peripheral register (bit band region | ||
| 123 | * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can | ||
| 124 | * be used for peripherals with 16bit access allowed. | ||
| 125 | * @param Reg Register to access. | ||
| 126 | * @param Bit Bit number to access. | ||
| 127 | * @return Value of the targeted bit in the bit band region. | ||
| 128 | */ | ||
| 129 | #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) | ||
| 130 | /** | ||
| 131 | * @brief Macro to access a single bit of a peripheral register (bit band region | ||
| 132 | * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can | ||
| 133 | * be used for peripherals with 8bit access allowed. | ||
| 134 | * @param Reg Register to access. | ||
| 135 | * @param Bit Bit number to access. | ||
| 136 | * @return Value of the targeted bit in the bit band region. | ||
| 137 | */ | ||
| 138 | #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) | ||
| 139 | |||
| 140 | /* ---------------------------------------------------------------------------- | ||
| 141 | -- Interrupt vector numbers | ||
| 142 | ---------------------------------------------------------------------------- */ | ||
| 143 | |||
| 144 | /*! | ||
| 145 | * @addtogroup Interrupt_vector_numbers Interrupt vector numbers | ||
| 146 | * @{ | ||
| 147 | */ | ||
| 148 | |||
| 149 | /** Interrupt Number Definitions */ | ||
| 150 | #define NUMBER_OF_INT_VECTORS 116 /**< Number of interrupts in the Vector table */ | ||
| 151 | |||
| 152 | #define DMA0_IRQn DMA0_DMA16_IRQn | ||
| 153 | #define DMA1_IRQn DMA1_DMA17_IRQn | ||
| 154 | #define DMA2_IRQn DMA2_DMA18_IRQn | ||
| 155 | #define DMA3_IRQn DMA3_DMA19_IRQn | ||
| 156 | #define DMA4_IRQn DMA4_DMA20_IRQn | ||
| 157 | #define DMA5_IRQn DMA5_DMA21_IRQn | ||
| 158 | #define DMA6_IRQn DMA6_DMA22_IRQn | ||
| 159 | #define DMA7_IRQn DMA7_DMA23_IRQn | ||
| 160 | #define DMA8_IRQn DMA8_DMA24_IRQn | ||
| 161 | #define DMA9_IRQn DMA9_DMA25_IRQn | ||
| 162 | #define DMA10_IRQn DMA10_DMA26_IRQn | ||
| 163 | #define DMA11_IRQn DMA11_DMA27_IRQn | ||
| 164 | #define DMA12_IRQn DMA12_DMA28_IRQn | ||
| 165 | #define DMA13_IRQn DMA13_DMA29_IRQn | ||
| 166 | #define DMA14_IRQn DMA14_DMA30_IRQn | ||
| 167 | #define DMA15_IRQn DMA15_DMA21_IRQn | ||
| 168 | |||
| 169 | typedef enum IRQn { | ||
| 170 | /* Auxiliary constants */ | ||
| 171 | NotAvail_IRQn = -128, /**< Not available device specific interrupt */ | ||
| 172 | |||
| 173 | /* Core interrupts */ | ||
| 174 | NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ | ||
| 175 | HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ | ||
| 176 | MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ | ||
| 177 | BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ | ||
| 178 | UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ | ||
| 179 | SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ | ||
| 180 | DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ | ||
| 181 | PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ | ||
| 182 | SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ | ||
| 183 | |||
| 184 | /* Device specific interrupts */ | ||
| 185 | DMA0_DMA16_IRQn = 0, /**< DMA Channel 0, 16 Transfer Complete */ | ||
| 186 | DMA1_DMA17_IRQn = 1, /**< DMA Channel 1, 17 Transfer Complete */ | ||
| 187 | DMA2_DMA18_IRQn = 2, /**< DMA Channel 2, 18 Transfer Complete */ | ||
| 188 | DMA3_DMA19_IRQn = 3, /**< DMA Channel 3, 19 Transfer Complete */ | ||
| 189 | DMA4_DMA20_IRQn = 4, /**< DMA Channel 4, 20 Transfer Complete */ | ||
| 190 | DMA5_DMA21_IRQn = 5, /**< DMA Channel 5, 21 Transfer Complete */ | ||
| 191 | DMA6_DMA22_IRQn = 6, /**< DMA Channel 6, 22 Transfer Complete */ | ||
| 192 | DMA7_DMA23_IRQn = 7, /**< DMA Channel 7, 23 Transfer Complete */ | ||
| 193 | DMA8_DMA24_IRQn = 8, /**< DMA Channel 8, 24 Transfer Complete */ | ||
| 194 | DMA9_DMA25_IRQn = 9, /**< DMA Channel 9, 25 Transfer Complete */ | ||
| 195 | DMA10_DMA26_IRQn = 10, /**< DMA Channel 10, 26 Transfer Complete */ | ||
| 196 | DMA11_DMA27_IRQn = 11, /**< DMA Channel 11, 27 Transfer Complete */ | ||
| 197 | DMA12_DMA28_IRQn = 12, /**< DMA Channel 12, 28 Transfer Complete */ | ||
| 198 | DMA13_DMA29_IRQn = 13, /**< DMA Channel 13, 29 Transfer Complete */ | ||
| 199 | DMA14_DMA30_IRQn = 14, /**< DMA Channel 14, 30 Transfer Complete */ | ||
| 200 | DMA15_DMA31_IRQn = 15, /**< DMA Channel 15, 31 Transfer Complete */ | ||
| 201 | DMA_Error_IRQn = 16, /**< DMA Error Interrupt */ | ||
| 202 | MCM_IRQn = 17, /**< Normal Interrupt */ | ||
| 203 | FTFE_IRQn = 18, /**< FTFE Command complete interrupt */ | ||
| 204 | Read_Collision_IRQn = 19, /**< Read Collision Interrupt */ | ||
| 205 | LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ | ||
| 206 | LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */ | ||
| 207 | WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */ | ||
| 208 | RNG_IRQn = 23, /**< RNG Interrupt */ | ||
| 209 | I2C0_IRQn = 24, /**< I2C0 interrupt */ | ||
| 210 | I2C1_IRQn = 25, /**< I2C1 interrupt */ | ||
| 211 | SPI0_IRQn = 26, /**< SPI0 Interrupt */ | ||
| 212 | SPI1_IRQn = 27, /**< SPI1 Interrupt */ | ||
| 213 | I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */ | ||
| 214 | I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */ | ||
| 215 | Reserved46_IRQn = 30, /**< Reserved interrupt 46 */ | ||
| 216 | UART0Status_IRQn = 31, /**< UART0 Receive/Transmit interrupt */ | ||
| 217 | UART0Error_IRQn = 32, /**< UART0 Error interrupt */ | ||
| 218 | UART1Status_IRQn = 33, /**< UART1 Receive/Transmit interrupt */ | ||
| 219 | UART1Error_IRQn = 34, /**< UART1 Error interrupt */ | ||
| 220 | UART2Status_IRQn = 35, /**< UART2 Receive/Transmit interrupt */ | ||
| 221 | UART2Error_IRQn = 36, /**< UART2 Error interrupt */ | ||
| 222 | UART3Status_IRQn = 37, /**< UART3 Receive/Transmit interrupt */ | ||
| 223 | UART3Error_IRQn = 38, /**< UART3 Error interrupt */ | ||
| 224 | ADC0_IRQn = 39, /**< ADC0 interrupt */ | ||
| 225 | CMP0_IRQn = 40, /**< CMP0 interrupt */ | ||
| 226 | CMP1_IRQn = 41, /**< CMP1 interrupt */ | ||
| 227 | FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */ | ||
| 228 | FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */ | ||
| 229 | FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */ | ||
| 230 | CMT_IRQn = 45, /**< CMT interrupt */ | ||
| 231 | RTC_IRQn = 46, /**< RTC interrupt */ | ||
| 232 | RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */ | ||
| 233 | PITChannel0_IRQn = 48, /**< PIT timer channel 0 interrupt */ | ||
| 234 | PITChannel1_IRQn = 49, /**< PIT timer channel 1 interrupt */ | ||
| 235 | PITChannel2_IRQn = 50, /**< PIT timer channel 2 interrupt */ | ||
| 236 | PITChannel3_IRQn = 51, /**< PIT timer channel 3 interrupt */ | ||
| 237 | PDB0_IRQn = 52, /**< PDB0 Interrupt */ | ||
| 238 | USB_OTG_IRQn = 53, /**< USB0 interrupt */ | ||
| 239 | USBDCD_IRQn = 54, /**< USBDCD Interrupt */ | ||
| 240 | Reserved71_IRQn = 55, /**< Reserved interrupt 71 */ | ||
| 241 | DAC0_IRQn = 56, /**< DAC0 interrupt */ | ||
| 242 | MCG_IRQn = 57, /**< MCG Interrupt */ | ||
| 243 | LPTMR0_IRQn = 58, /**< LPTimer interrupt */ | ||
| 244 | PINA_IRQn = 59, /**< Port A interrupt */ | ||
| 245 | PINB_IRQn = 60, /**< Port B interrupt */ | ||
| 246 | PINC_IRQn = 61, /**< Port C interrupt */ | ||
| 247 | PIND_IRQn = 62, /**< Port D interrupt */ | ||
| 248 | PINE_IRQn = 63, /**< Port E interrupt */ | ||
| 249 | SWI_IRQn = 64, /**< Software interrupt */ | ||
| 250 | SPI2_IRQn = 65, /**< SPI2 Interrupt */ | ||
| 251 | UART4Status_IRQn = 66, /**< UART4 Receive/Transmit interrupt */ | ||
| 252 | UART4Error_IRQn = 67, /**< UART4 Error interrupt */ | ||
| 253 | Reserved84_IRQn = 68, /**< Reserved interrupt 84 */ | ||
| 254 | Reserved85_IRQn = 69, /**< Reserved interrupt 85 */ | ||
| 255 | CMP2_IRQn = 70, /**< CMP2 interrupt */ | ||
| 256 | FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */ | ||
| 257 | DAC1_IRQn = 72, /**< DAC1 interrupt */ | ||
| 258 | ADC1_IRQn = 73, /**< ADC1 interrupt */ | ||
| 259 | I2C2_IRQn = 74, /**< I2C2 interrupt */ | ||
| 260 | CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */ | ||
| 261 | CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */ | ||
| 262 | CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */ | ||
| 263 | CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */ | ||
| 264 | CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */ | ||
| 265 | CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */ | ||
| 266 | SDHC_IRQn = 81, /**< SDHC interrupt */ | ||
| 267 | ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */ | ||
| 268 | ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */ | ||
| 269 | ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */ | ||
| 270 | ENET_Error_IRQn = 85, /**< Ethernet MAC Error and miscelaneous Interrupt */ | ||
| 271 | LPUART0_IRQn = 86, /**< LPUART0 status/error interrupt */ | ||
| 272 | TSI0_IRQn = 87, /**< TSI0 interrupt */ | ||
| 273 | TPM1_IRQn = 88, /**< TPM1 fault, overflow and channels interrupt */ | ||
| 274 | TPM2_IRQn = 89, /**< TPM2 fault, overflow and channels interrupt */ | ||
| 275 | USBHSDCD_IRQn = 90, /**< USBHSDCD, USBHS Phy Interrupt */ | ||
| 276 | I2C3_IRQn = 91, /**< I2C3 interrupt */ | ||
| 277 | CMP3_IRQn = 92, /**< CMP3 interrupt */ | ||
| 278 | USBHS_IRQn = 93, /**< USB high speed OTG interrupt */ | ||
| 279 | CAN1_ORed_Message_buffer_IRQn = 94, /**< CAN1 OR'd message buffers interrupt */ | ||
| 280 | CAN1_Bus_Off_IRQn = 95, /**< CAN1 bus off interrupt */ | ||
| 281 | CAN1_Error_IRQn = 96, /**< CAN1 error interrupt */ | ||
| 282 | CAN1_Tx_Warning_IRQn = 97, /**< CAN1 Tx warning interrupt */ | ||
| 283 | CAN1_Rx_Warning_IRQn = 98, /**< CAN1 Rx warning interrupt */ | ||
| 284 | CAN1_Wake_Up_IRQn = 99 /**< CAN1 wake up interrupt */ | ||
| 285 | } IRQn_Type; | ||
| 286 | |||
| 287 | /*! | ||
| 288 | * @} | ||
| 289 | */ /* end of group Interrupt_vector_numbers */ | ||
| 290 | |||
| 291 | |||
| 292 | /* ---------------------------------------------------------------------------- | ||
| 293 | -- Cortex M4 Core Configuration | ||
| 294 | ---------------------------------------------------------------------------- */ | ||
| 295 | |||
| 296 | /*! | ||
| 297 | * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration | ||
| 298 | * @{ | ||
| 299 | */ | ||
| 300 | |||
| 301 | #define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ | ||
| 302 | #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ | ||
| 303 | #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ | ||
| 304 | #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ | ||
| 305 | |||
| 306 | #include "core_cm4.h" /* Core Peripheral Access Layer */ | ||
| 307 | #include "system_MK66F18.h" /* Device specific configuration file */ | ||
| 308 | |||
| 309 | /*! | ||
| 310 | * @} | ||
| 311 | */ /* end of group Cortex_Core_Configuration */ | ||
| 312 | |||
| 313 | |||
| 314 | /* ---------------------------------------------------------------------------- | ||
| 315 | -- Mapping Information | ||
| 316 | ---------------------------------------------------------------------------- */ | ||
| 317 | |||
| 318 | /*! | ||
| 319 | * @addtogroup Mapping_Information Mapping Information | ||
| 320 | * @{ | ||
| 321 | */ | ||
| 322 | |||
| 323 | /** Mapping Information */ | ||
| 324 | /*! | ||
| 325 | * @addtogroup edma_request | ||
| 326 | * @{ | ||
| 327 | */ | ||
| 328 | |||
| 329 | /******************************************************************************* | ||
| 330 | * Definitions | ||
| 331 | ******************************************************************************/ | ||
| 332 | |||
| 333 | /*! | ||
| 334 | * @brief Structure for the DMA hardware request | ||
| 335 | * | ||
| 336 | * Defines the structure for the DMA hardware request collections. The user can configure the | ||
| 337 | * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index | ||
| 338 | * of the hardware request varies according to the to SoC. | ||
| 339 | */ | ||
| 340 | typedef enum _dma_request_source | ||
| 341 | { | ||
| 342 | kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ | ||
| 343 | kDmaRequestMux0TSI0 = 1|0x100U, /**< TSI0. */ | ||
| 344 | kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */ | ||
| 345 | kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */ | ||
| 346 | kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */ | ||
| 347 | kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */ | ||
| 348 | kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */ | ||
| 349 | kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */ | ||
| 350 | kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 Receive. */ | ||
| 351 | kDmaRequestMux0UART3Tx = 9|0x100U, /**< UART3 Transmit. */ | ||
| 352 | kDmaRequestMux0UART4 = 10|0x100U, /**< UART4 Transmit or Receive. */ | ||
| 353 | kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */ | ||
| 354 | kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */ | ||
| 355 | kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */ | ||
| 356 | kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */ | ||
| 357 | kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */ | ||
| 358 | kDmaRequestMux0SPI1Rx = 16|0x100U, /**< SPI1 Receive. */ | ||
| 359 | kDmaRequestMux0SPI1Tx = 17|0x100U, /**< SPI1 Transmit. */ | ||
| 360 | kDmaRequestMux0I2C0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */ | ||
| 361 | kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0 and I2C3. */ | ||
| 362 | kDmaRequestMux0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */ | ||
| 363 | kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */ | ||
| 364 | kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */ | ||
| 365 | kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */ | ||
| 366 | kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */ | ||
| 367 | kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */ | ||
| 368 | kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */ | ||
| 369 | kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */ | ||
| 370 | kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */ | ||
| 371 | kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */ | ||
| 372 | kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */ | ||
| 373 | kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */ | ||
| 374 | kDmaRequestMux0FTM1TPM1Channel0 = 28|0x100U, /**< FTM1 C0V and TPM1 C0V. */ | ||
| 375 | kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V and TPM1 C0V. */ | ||
| 376 | kDmaRequestMux0TPM1Channel0 = 28|0x100U, /**< FTM1 C0V and TPM1 C0V. */ | ||
| 377 | kDmaRequestMux0FTM1TPM1Channel1 = 29|0x100U, /**< FTM1 C1V and TPM1 C1V. */ | ||
| 378 | kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V and TPM1 C1V. */ | ||
| 379 | kDmaRequestMux0TPM1Channel1 = 29|0x100U, /**< FTM1 C1V and TPM1 C1V. */ | ||
| 380 | kDmaRequestMux0FTM2TPM2Channel0 = 30|0x100U, /**< FTM2 C0V and TPM2 C0V. */ | ||
| 381 | kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V and TPM2 C0V. */ | ||
| 382 | kDmaRequestMux0TPM2Channel0 = 30|0x100U, /**< FTM2 C0V and TPM2 C0V. */ | ||
| 383 | kDmaRequestMux0FTM2TPM2Channel1 = 31|0x100U, /**< FTM2 C1V and TPM2 C1V. */ | ||
| 384 | kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V and TPM2 C1V. */ | ||
| 385 | kDmaRequestMux0TPM2Channel1 = 31|0x100U, /**< FTM2 C1V and TPM2 C1V. */ | ||
| 386 | kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */ | ||
| 387 | kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */ | ||
| 388 | kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */ | ||
| 389 | kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */ | ||
| 390 | kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */ | ||
| 391 | kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */ | ||
| 392 | kDmaRequestMux0FTM3Channel6SPI2Rx = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */ | ||
| 393 | kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */ | ||
| 394 | kDmaRequestMux0SPI2Rx = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */ | ||
| 395 | kDmaRequestMux0FTM3Channel7SPI2Tx = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */ | ||
| 396 | kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */ | ||
| 397 | kDmaRequestMux0SPI2Tx = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */ | ||
| 398 | kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ | ||
| 399 | kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */ | ||
| 400 | kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ | ||
| 401 | kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */ | ||
| 402 | kDmaRequestMux0CMP2CMP3 = 44|0x100U, /**< CMP2 and CMP3. */ | ||
| 403 | kDmaRequestMux0CMP2 = 44|0x100U, /**< CMP2 and CMP3. */ | ||
| 404 | kDmaRequestMux0CMP3 = 44|0x100U, /**< CMP2 and CMP3. */ | ||
| 405 | kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */ | ||
| 406 | kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1. */ | ||
| 407 | kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */ | ||
| 408 | kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */ | ||
| 409 | kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ | ||
| 410 | kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */ | ||
| 411 | kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */ | ||
| 412 | kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */ | ||
| 413 | kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */ | ||
| 414 | kDmaRequestMux0IEEE1588Timer0 = 54|0x100U, /**< ENET IEEE 1588 timer 0. */ | ||
| 415 | kDmaRequestMux0IEEE1588Timer1TPM1Overflow = 55|0x100U, /**< ENET IEEE 1588 timer 1 and TPM1. */ | ||
| 416 | kDmaRequestMux0IEEE1588Timer1 = 55|0x100U, /**< ENET IEEE 1588 timer 1 and TPM1. */ | ||
| 417 | kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< ENET IEEE 1588 timer 1 and TPM1. */ | ||
| 418 | kDmaRequestMux0IEEE1588Timer2TPM2Overflow = 56|0x100U, /**< ENET IEEE 1588 timer 2 and TPM2. */ | ||
| 419 | kDmaRequestMux0IEEE1588Timer2 = 56|0x100U, /**< ENET IEEE 1588 timer 2 and TPM2. */ | ||
| 420 | kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< ENET IEEE 1588 timer 2 and TPM2. */ | ||
| 421 | kDmaRequestMux0IEEE1588Timer3 = 57|0x100U, /**< ENET IEEE 1588 timer 3. */ | ||
| 422 | kDmaRequestMux0LPUART0Rx = 58|0x100U, /**< LPUART0 Receive. */ | ||
| 423 | kDmaRequestMux0LPUART0Tx = 59|0x100U, /**< LPUART0 Transmit. */ | ||
| 424 | kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ | ||
| 425 | kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ | ||
| 426 | kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ | ||
| 427 | kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ | ||
| 428 | } dma_request_source_t; | ||
| 429 | |||
| 430 | /* @} */ | ||
| 431 | |||
| 432 | |||
| 433 | /*! | ||
| 434 | * @} | ||
| 435 | */ /* end of group Mapping_Information */ | ||
| 436 | |||
| 437 | |||
| 438 | /* ---------------------------------------------------------------------------- | ||
| 439 | -- Device Peripheral Access Layer | ||
| 440 | ---------------------------------------------------------------------------- */ | ||
| 441 | |||
| 442 | /*! | ||
| 443 | * @addtogroup Peripheral_access_layer Device Peripheral Access Layer | ||
| 444 | * @{ | ||
| 445 | */ | ||
| 446 | |||
| 447 | |||
| 448 | /* | ||
| 449 | ** Start of section using anonymous unions | ||
| 450 | */ | ||
| 451 | |||
| 452 | #if defined(__ARMCC_VERSION) | ||
| 453 | #if (__ARMCC_VERSION >= 6010050) | ||
| 454 | #pragma clang diagnostic push | ||
| 455 | #else | ||
| 456 | #pragma push | ||
| 457 | #pragma anon_unions | ||
| 458 | #endif | ||
| 459 | #elif defined(__CWCC__) | ||
| 460 | #pragma push | ||
| 461 | #pragma cpp_extensions on | ||
| 462 | #elif defined(__GNUC__) | ||
| 463 | /* anonymous unions are enabled by default */ | ||
| 464 | #elif defined(__IAR_SYSTEMS_ICC__) | ||
| 465 | #pragma language=extended | ||
| 466 | #else | ||
| 467 | #error Not supported compiler type | ||
| 468 | #endif | ||
| 469 | |||
| 470 | /* ---------------------------------------------------------------------------- | ||
| 471 | -- ADC Peripheral Access Layer | ||
| 472 | ---------------------------------------------------------------------------- */ | ||
| 473 | |||
| 474 | /*! | ||
| 475 | * @addtogroup ADCx_Peripheral_Access_Layer ADC Peripheral Access Layer | ||
| 476 | * @{ | ||
| 477 | */ | ||
| 478 | |||
| 479 | /** ADC - Register Layout Typedef */ | ||
| 480 | typedef struct { | ||
| 481 | __IO uint32_t SC1A; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ | ||
| 482 | __IO uint32_t SC1B; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ | ||
| 483 | __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ | ||
| 484 | __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ | ||
| 485 | __I uint32_t RA; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ | ||
| 486 | __I uint32_t RB; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ | ||
| 487 | __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ | ||
| 488 | __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ | ||
| 489 | __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ | ||
| 490 | __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ | ||
| 491 | __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ | ||
| 492 | __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ | ||
| 493 | __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ | ||
| 494 | __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ | ||
| 495 | __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ | ||
| 496 | __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ | ||
| 497 | __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ | ||
| 498 | __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ | ||
| 499 | __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ | ||
| 500 | __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ | ||
| 501 | uint8_t RESERVED_0[4]; | ||
| 502 | __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ | ||
| 503 | __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ | ||
| 504 | __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ | ||
| 505 | __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ | ||
| 506 | __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ | ||
| 507 | __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ | ||
| 508 | __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ | ||
| 509 | } ADC_TypeDef; | ||
| 510 | |||
| 511 | /* ---------------------------------------------------------------------------- | ||
| 512 | -- ADC Register Masks | ||
| 513 | ---------------------------------------------------------------------------- */ | ||
| 514 | |||
| 515 | /*! | ||
| 516 | * @addtogroup ADCx_Register_Masks ADC Register Masks | ||
| 517 | * @{ | ||
| 518 | */ | ||
| 519 | |||
| 520 | /*! @name SC1 - ADC Status and Control Registers 1 */ | ||
| 521 | #define ADCx_SC1n_ADCH_MASK (0x1FU) | ||
| 522 | #define ADCx_SC1n_ADCH_SHIFT (0U) | ||
| 523 | #define ADCx_SC1n_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC1n_ADCH_SHIFT)) & ADCx_SC1n_ADCH_MASK) | ||
| 524 | #define ADCx_SC1n_DIFF_MASK (0x20U) | ||
| 525 | #define ADCx_SC1n_DIFF_SHIFT (5U) | ||
| 526 | #define ADCx_SC1n_DIFF_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC1n_DIFF_SHIFT)) & ADCx_SC1n_DIFF_MASK) | ||
| 527 | #define ADCx_SC1n_DIFF ADCx_SC1n_DIFF_MASK | ||
| 528 | #define ADCx_SC1n_AIEN_MASK (0x40U) | ||
| 529 | #define ADCx_SC1n_AIEN_SHIFT (6U) | ||
| 530 | #define ADCx_SC1n_AIEN_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC1n_AIEN_SHIFT)) & ADCx_SC1n_AIEN_MASK) | ||
| 531 | #define ADCx_SC1n_AIEN ADCx_SC1n_AIEN_MASK | ||
| 532 | #define ADCx_SC1n_COCO_MASK (0x80U) | ||
| 533 | #define ADCx_SC1n_COCO_SHIFT (7U) | ||
| 534 | #define ADCx_SC1n_COCO_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC1n_COCO_SHIFT)) & ADCx_SC1n_COCO_MASK) | ||
| 535 | #define ADCx_SC1n_COCO ADCx_SC1n_COCO_MASK | ||
| 536 | |||
| 537 | /* The count of ADCx_SC1n */ | ||
| 538 | #define ADCx_SC1n_COUNT (2U) | ||
| 539 | |||
| 540 | /*! @name CFG1 - ADC Configuration Register 1 */ | ||
| 541 | #define ADCx_CFG1_ADICLK_MASK (0x3U) | ||
| 542 | #define ADCx_CFG1_ADICLK_SHIFT (0U) | ||
| 543 | #define ADCx_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_ADICLK_SHIFT)) & ADCx_CFG1_ADICLK_MASK) | ||
| 544 | #define ADCx_CFG1_MODE_MASK (0xCU) | ||
| 545 | #define ADCx_CFG1_MODE_SHIFT (2U) | ||
| 546 | #define ADCx_CFG1_MODE_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_MODE_SHIFT)) & ADCx_CFG1_MODE_MASK) | ||
| 547 | #define ADCx_CFG1_MODE ADCx_CFG1_MODE_MASK | ||
| 548 | #define ADCx_CFG1_ADLSMP_MASK (0x10U) | ||
| 549 | #define ADCx_CFG1_ADLSMP_SHIFT (4U) | ||
| 550 | #define ADCx_CFG1_ADLSMP_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_ADLSMP_SHIFT)) & ADCx_CFG1_ADLSMP_MASK) | ||
| 551 | #define ADCx_CFG1_ADLSMP ADCx_CFG1_ADLSMP_MASK | ||
| 552 | #define ADCx_CFG1_ADIV_MASK (0x60U) | ||
| 553 | #define ADCx_CFG1_ADIV_SHIFT (5U) | ||
| 554 | #define ADCx_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_ADIV_SHIFT)) & ADCx_CFG1_ADIV_MASK) | ||
| 555 | #define ADCx_CFG1_ADLPC_MASK (0x80U) | ||
| 556 | #define ADCx_CFG1_ADLPC_SHIFT (7U) | ||
| 557 | #define ADCx_CFG1_ADLPC_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_ADLPC_SHIFT)) & ADCx_CFG1_ADLPC_MASK) | ||
| 558 | #define ADCx_CFG1_ADLPC ADCx_CFG1_ADLPC_MASK | ||
| 559 | |||
| 560 | /*! @name CFG2 - ADC Configuration Register 2 */ | ||
| 561 | #define ADCx_CFG2_ADLSTS_MASK (0x3U) | ||
| 562 | #define ADCx_CFG2_ADLSTS_SHIFT (0U) | ||
| 563 | #define ADCx_CFG2_ADLSTS_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CFG2_ADLSTS_SHIFT)) & ADCx_CFG2_ADLSTS_MASK) | ||
| 564 | #define ADCx_CFG2_ADLSTS ADCx_CFG2_ADLSTS_MASK | ||
| 565 | #define ADCx_CFG2_ADHSC_MASK (0x4U) | ||
| 566 | #define ADCx_CFG2_ADHSC_SHIFT (2U) | ||
| 567 | #define ADCx_CFG2_ADHSC_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CFG2_ADHSC_SHIFT)) & ADCx_CFG2_ADHSC_MASK) | ||
| 568 | #define ADCx_CFG2_ADHSC ADCx_CFG2_ADHSC_MASK | ||
| 569 | #define ADCx_CFG2_ADACKEN_MASK (0x8U) | ||
| 570 | #define ADCx_CFG2_ADACKEN_SHIFT (3U) | ||
| 571 | #define ADCx_CFG2_ADACKEN_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CFG2_ADACKEN_SHIFT)) & ADCx_CFG2_ADACKEN_MASK) | ||
| 572 | #define ADCx_CFG2_ADACKEN ADCx_CFG2_ADACKEN_MASK | ||
| 573 | #define ADCx_CFG2_MUXSEL_MASK (0x10U) | ||
| 574 | #define ADCx_CFG2_MUXSEL_SHIFT (4U) | ||
| 575 | #define ADCx_CFG2_MUXSEL_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CFG2_MUXSEL_SHIFT)) & ADCx_CFG2_MUXSEL_MASK) | ||
| 576 | #define ADCx_CFG2_MUXSEL ADCx_CFG2_MUXSEL_MASK | ||
| 577 | |||
| 578 | /*! @name R - ADC Data Result Register */ | ||
| 579 | #define ADCx_R_D_MASK (0xFFFFU) | ||
| 580 | #define ADCx_R_D_SHIFT (0U) | ||
| 581 | #define ADCx_R_D_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_R_D_SHIFT)) & ADCx_R_D_MASK) | ||
| 582 | #define ADCx_R_D ADCx_R_D_MASK | ||
| 583 | |||
| 584 | /* The count of ADCx_R */ | ||
| 585 | #define ADCx_R_COUNT (2U) | ||
| 586 | |||
| 587 | /*! @name CV1 - Compare Value Registers */ | ||
| 588 | #define ADCx_CV1_CV_MASK (0xFFFFU) | ||
| 589 | #define ADCx_CV1_CV_SHIFT (0U) | ||
| 590 | #define ADCx_CV1_CV_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CV1_CV_SHIFT)) & ADCx_CV1_CV_MASK) | ||
| 591 | #define ADCx_CV1_CV ADCx_CV1_CV_MASK | ||
| 592 | |||
| 593 | /*! @name CV2 - Compare Value Registers */ | ||
| 594 | #define ADCx_CV2_CV_MASK (0xFFFFU) | ||
| 595 | #define ADCx_CV2_CV_SHIFT (0U) | ||
| 596 | #define ADCx_CV2_CV_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CV2_CV_SHIFT)) & ADCx_CV2_CV_MASK) | ||
| 597 | #define ADCx_CV2_CV ADCx_CV2_CV_MASK | ||
| 598 | |||
| 599 | /*! @name SC2 - Status and Control Register 2 */ | ||
| 600 | #define ADCx_SC2_REFSEL_MASK (0x3U) | ||
| 601 | #define ADCx_SC2_REFSEL_SHIFT (0U) | ||
| 602 | #define ADCx_SC2_REFSEL_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_REFSEL_SHIFT)) & ADCx_SC2_REFSEL_MASK) | ||
| 603 | #define ADCx_SC2_REFSEL ADCx_SC2_REFSEL_MASK | ||
| 604 | #define ADCx_SC2_DMAEN_MASK (0x4U) | ||
| 605 | #define ADCx_SC2_DMAEN_SHIFT (2U) | ||
| 606 | #define ADCx_SC2_DMAEN_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_DMAEN_SHIFT)) & ADCx_SC2_DMAEN_MASK) | ||
| 607 | #define ADCx_SC2_DMAEN ADCx_SC2_DMAEN_MASK | ||
| 608 | #define ADCx_SC2_ACREN_MASK (0x8U) | ||
| 609 | #define ADCx_SC2_ACREN_SHIFT (3U) | ||
| 610 | #define ADCx_SC2_ACREN_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_ACREN_SHIFT)) & ADCx_SC2_ACREN_MASK) | ||
| 611 | #define ADCx_SC2_ACREN ADCx_SC2_ACREN_MASK | ||
| 612 | #define ADCx_SC2_ACFGT_MASK (0x10U) | ||
| 613 | #define ADCx_SC2_ACFGT_SHIFT (4U) | ||
| 614 | #define ADCx_SC2_ACFGT_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_ACFGT_SHIFT)) & ADCx_SC2_ACFGT_MASK) | ||
| 615 | #define ADCx_SC2_ACFGT ADCx_SC2_ACFGT_MASK | ||
| 616 | #define ADCx_SC2_ACFE_MASK (0x20U) | ||
| 617 | #define ADCx_SC2_ACFE_SHIFT (5U) | ||
| 618 | #define ADCx_SC2_ACFE_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_ACFE_SHIFT)) & ADCx_SC2_ACFE_MASK) | ||
| 619 | #define ADCx_SC2_ACFE ADCx_SC2_ACFE_MASK | ||
| 620 | #define ADCx_SC2_ADTRG_MASK (0x40U) | ||
| 621 | #define ADCx_SC2_ADTRG_SHIFT (6U) | ||
| 622 | #define ADCx_SC2_ADTRG_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_ADTRG_SHIFT)) & ADCx_SC2_ADTRG_MASK) | ||
| 623 | #define ADCx_SC2_ADTRG ADCx_SC2_ADTRG_MASK | ||
| 624 | #define ADCx_SC2_ADACT_MASK (0x80U) | ||
| 625 | #define ADCx_SC2_ADACT_SHIFT (7U) | ||
| 626 | #define ADCx_SC2_ADACT_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_ADACT_SHIFT)) & ADCx_SC2_ADACT_MASK) | ||
| 627 | #define ADCx_SC2_ADACT ADCx_SC2_ADACT_MASK | ||
| 628 | |||
| 629 | /*! @name SC3 - Status and Control Register 3 */ | ||
| 630 | #define ADCx_SC3_AVGS_MASK (0x3U) | ||
| 631 | #define ADCx_SC3_AVGS_SHIFT (0U) | ||
| 632 | #define ADCx_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC3_AVGS_SHIFT)) & ADCx_SC3_AVGS_MASK) | ||
| 633 | #define ADCx_SC3_AVGE_MASK (0x4U) | ||
| 634 | #define ADCx_SC3_AVGE_SHIFT (2U) | ||
| 635 | #define ADCx_SC3_AVGE_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC3_AVGE_SHIFT)) & ADCx_SC3_AVGE_MASK) | ||
| 636 | #define ADCx_SC3_AVGE ADCx_SC3_AVGE_MASK | ||
| 637 | #define ADCx_SC3_ADCO_MASK (0x8U) | ||
| 638 | #define ADCx_SC3_ADCO_SHIFT (3U) | ||
| 639 | #define ADCx_SC3_ADCO_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC3_ADCO_SHIFT)) & ADCx_SC3_ADCO_MASK) | ||
| 640 | #define ADCx_SC3_ADCO ADCx_SC3_ADCO_MASK | ||
| 641 | #define ADCx_SC3_CALF_MASK (0x40U) | ||
| 642 | #define ADCx_SC3_CALF_SHIFT (6U) | ||
| 643 | #define ADCx_SC3_CALF_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC3_CALF_SHIFT)) & ADCx_SC3_CALF_MASK) | ||
| 644 | #define ADCx_SC3_CALF ADCx_SC3_CALF_MASK | ||
| 645 | #define ADCx_SC3_CAL_MASK (0x80U) | ||
| 646 | #define ADCx_SC3_CAL_SHIFT (7U) | ||
| 647 | #define ADCx_SC3_CAL_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC3_CAL_SHIFT)) & ADCx_SC3_CAL_MASK) | ||
| 648 | #define ADCx_SC3_CAL ADCx_SC3_CAL_MASK | ||
| 649 | |||
| 650 | /*! @name OFS - ADC Offset Correction Register */ | ||
| 651 | #define ADCx_OFS_OFS_MASK (0xFFFFU) | ||
| 652 | #define ADCx_OFS_OFS_SHIFT (0U) | ||
| 653 | #define ADCx_OFS_OFS_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_OFS_OFS_SHIFT)) & ADCx_OFS_OFS_MASK) | ||
| 654 | #define ADCx_OFS_OFS ADCx_OFS_OFS_MASK | ||
| 655 | |||
| 656 | /*! @name PG - ADC Plus-Side Gain Register */ | ||
| 657 | #define ADCx_PG_PG_MASK (0xFFFFU) | ||
| 658 | #define ADCx_PG_PG_SHIFT (0U) | ||
| 659 | #define ADCx_PG_PG_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_PG_PG_SHIFT)) & ADCx_PG_PG_MASK) | ||
| 660 | #define ADCx_PG_PG ADCx_PG_PG_MASK | ||
| 661 | |||
| 662 | /*! @name MG - ADC Minus-Side Gain Register */ | ||
| 663 | #define ADCx_MG_MG_MASK (0xFFFFU) | ||
| 664 | #define ADCx_MG_MG_SHIFT (0U) | ||
| 665 | #define ADCx_MG_MG_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_MG_MG_SHIFT)) & ADCx_MG_MG_MASK) | ||
| 666 | #define ADCx_MG_MG ADCx_MG_MG_MASK | ||
| 667 | |||
| 668 | /*! @name CLPD - ADC Plus-Side General Calibration Value Register */ | ||
| 669 | #define ADCx_CLPD_CLPD_MASK (0x3FU) | ||
| 670 | #define ADCx_CLPD_CLPD_SHIFT (0U) | ||
| 671 | #define ADCx_CLPD_CLPD_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLPD_CLPD_SHIFT)) & ADCx_CLPD_CLPD_MASK) | ||
| 672 | #define ADCx_CLPD_CLPD ADCx_CLPD_CLPD_MASK | ||
| 673 | |||
| 674 | /*! @name CLPS - ADC Plus-Side General Calibration Value Register */ | ||
| 675 | #define ADCx_CLPS_CLPS_MASK (0x3FU) | ||
| 676 | #define ADCx_CLPS_CLPS_SHIFT (0U) | ||
| 677 | #define ADCx_CLPS_CLPS_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLPS_CLPS_SHIFT)) & ADCx_CLPS_CLPS_MASK) | ||
| 678 | #define ADCx_CLPS_CLPS ADCx_CLPS_CLPS_MASK | ||
| 679 | |||
| 680 | /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ | ||
| 681 | #define ADCx_CLP4_CLP4_MASK (0x3FFU) | ||
| 682 | #define ADCx_CLP4_CLP4_SHIFT (0U) | ||
| 683 | #define ADCx_CLP4_CLP4_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLP4_CLP4_SHIFT)) & ADCx_CLP4_CLP4_MASK) | ||
| 684 | #define ADCx_CLP4_CLP4 ADCx_CLP4_CLP4_MASK | ||
| 685 | |||
| 686 | /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ | ||
| 687 | #define ADCx_CLP3_CLP3_MASK (0x1FFU) | ||
| 688 | #define ADCx_CLP3_CLP3_SHIFT (0U) | ||
| 689 | #define ADCx_CLP3_CLP3_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLP3_CLP3_SHIFT)) & ADCx_CLP3_CLP3_MASK) | ||
| 690 | #define ADCx_CLP3_CLP3 ADCx_CLP3_CLP3_MASK | ||
| 691 | |||
| 692 | /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ | ||
| 693 | #define ADCx_CLP2_CLP2_MASK (0xFFU) | ||
| 694 | #define ADCx_CLP2_CLP2_SHIFT (0U) | ||
| 695 | #define ADCx_CLP2_CLP2_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLP2_CLP2_SHIFT)) & ADCx_CLP2_CLP2_MASK) | ||
| 696 | #define ADCx_CLP2_CLP2 ADCx_CLP2_CLP2_MASK | ||
| 697 | |||
| 698 | /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ | ||
| 699 | #define ADCx_CLP1_CLP1_MASK (0x7FU) | ||
| 700 | #define ADCx_CLP1_CLP1_SHIFT (0U) | ||
| 701 | #define ADCx_CLP1_CLP1_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLP1_CLP1_SHIFT)) & ADCx_CLP1_CLP1_MASK) | ||
| 702 | #define ADCx_CLP1_CLP1 ADCx_CLP1_CLP1_MASK | ||
| 703 | |||
| 704 | /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ | ||
| 705 | #define ADCx_CLP0_CLP0_MASK (0x3FU) | ||
| 706 | #define ADCx_CLP0_CLP0_SHIFT (0U) | ||
| 707 | #define ADCx_CLP0_CLP0_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLP0_CLP0_SHIFT)) & ADCx_CLP0_CLP0_MASK) | ||
| 708 | #define ADCx_CLP0_CLP0 ADCx_CLP0_CLP0_MASK | ||
| 709 | |||
| 710 | /*! @name CLMD - ADC Minus-Side General Calibration Value Register */ | ||
| 711 | #define ADCx_CLMD_CLMD_MASK (0x3FU) | ||
| 712 | #define ADCx_CLMD_CLMD_SHIFT (0U) | ||
| 713 | #define ADCx_CLMD_CLMD_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLMD_CLMD_SHIFT)) & ADCx_CLMD_CLMD_MASK) | ||
| 714 | #define ADCx_CLMD_CLMD ADCx_CLMD_CLMD_MASK | ||
| 715 | |||
| 716 | /*! @name CLMS - ADC Minus-Side General Calibration Value Register */ | ||
| 717 | #define ADCx_CLMS_CLMS_MASK (0x3FU) | ||
| 718 | #define ADCx_CLMS_CLMS_SHIFT (0U) | ||
| 719 | #define ADCx_CLMS_CLMS_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLMS_CLMS_SHIFT)) & ADCx_CLMS_CLMS_MASK) | ||
| 720 | #define ADCx_CLMS_CLMS ADCx_CLMS_CLMS_MASK | ||
| 721 | |||
| 722 | /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */ | ||
| 723 | #define ADCx_CLM4_CLM4_MASK (0x3FFU) | ||
| 724 | #define ADCx_CLM4_CLM4_SHIFT (0U) | ||
| 725 | #define ADCx_CLM4_CLM4_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLM4_CLM4_SHIFT)) & ADCx_CLM4_CLM4_MASK) | ||
| 726 | #define ADCx_CLM4_CLM4 ADCx_CLM4_CLM4_MASK | ||
| 727 | |||
| 728 | /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */ | ||
| 729 | #define ADCx_CLM3_CLM3_MASK (0x1FFU) | ||
| 730 | #define ADCx_CLM3_CLM3_SHIFT (0U) | ||
| 731 | #define ADCx_CLM3_CLM3_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLM3_CLM3_SHIFT)) & ADCx_CLM3_CLM3_MASK) | ||
| 732 | #define ADCx_CLM3_CLM3 ADCx_CLM3_CLM3_MASK | ||
| 733 | |||
| 734 | /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */ | ||
| 735 | #define ADCx_CLM2_CLM2_MASK (0xFFU) | ||
| 736 | #define ADCx_CLM2_CLM2_SHIFT (0U) | ||
| 737 | #define ADCx_CLM2_CLM2_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLM2_CLM2_SHIFT)) & ADCx_CLM2_CLM2_MASK) | ||
| 738 | #define ADCx_CLM2_CLM2 ADCx_CLM2_CLM2_MASK | ||
| 739 | |||
| 740 | /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */ | ||
| 741 | #define ADCx_CLM1_CLM1_MASK (0x7FU) | ||
| 742 | #define ADCx_CLM1_CLM1_SHIFT (0U) | ||
| 743 | #define ADCx_CLM1_CLM1_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLM1_CLM1_SHIFT)) & ADCx_CLM1_CLM1_MASK) | ||
| 744 | #define ADCx_CLM1_CLM1 ADCx_CLM1_CLM1_MASK | ||
| 745 | |||
| 746 | /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */ | ||
| 747 | #define ADCx_CLM0_CLM0_MASK (0x3FU) | ||
| 748 | #define ADCx_CLM0_CLM0_SHIFT (0U) | ||
| 749 | #define ADCx_CLM0_CLM0_SET(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLM0_CLM0_SHIFT)) & ADCx_CLM0_CLM0_MASK) | ||
| 750 | #define ADCx_CLM0_CLM0 ADCx_CLM0_CLM0_MASK | ||
| 751 | |||
| 752 | |||
| 753 | /*! | ||
| 754 | * @} | ||
| 755 | */ /* end of group ADCx_Register_Masks */ | ||
| 756 | |||
| 757 | |||
| 758 | /* ADC - Peripheral instance base addresses */ | ||
| 759 | /** Peripheral ADC0 base address */ | ||
| 760 | #define ADC0_BASE (0x4003B000u) | ||
| 761 | /** Peripheral ADC0 base pointer */ | ||
| 762 | #define ADC0 ((ADC_TypeDef *)ADC0_BASE) | ||
| 763 | /** Peripheral ADC1 base address */ | ||
| 764 | #define ADC1_BASE (0x400BB000u) | ||
| 765 | /** Peripheral ADC1 base pointer */ | ||
| 766 | #define ADC1 ((ADC_TypeDef *)ADC1_BASE) | ||
| 767 | /** Array initializer of ADC peripheral base addresses */ | ||
| 768 | #define ADCx_BASE_ADDRS { ADC0_BASE, ADC1_BASE } | ||
| 769 | /** Array initializer of ADC peripheral base pointers */ | ||
| 770 | #define ADCx_BASE_PTRS { ADC0, ADC1 } | ||
| 771 | /** Interrupt vectors for the ADC peripheral type */ | ||
| 772 | #define ADCx_IRQS { ADC0_IRQn, ADC1_IRQn } | ||
| 773 | |||
| 774 | /*! | ||
| 775 | * @} | ||
| 776 | */ /* end of group ADCx_Peripheral_Access_Layer */ | ||
| 777 | |||
| 778 | |||
| 779 | /* ---------------------------------------------------------------------------- | ||
| 780 | -- AIPS Peripheral Access Layer | ||
| 781 | ---------------------------------------------------------------------------- */ | ||
| 782 | |||
| 783 | /*! | ||
| 784 | * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer | ||
| 785 | * @{ | ||
| 786 | */ | ||
| 787 | |||
| 788 | /** AIPS - Register Layout Typedef */ | ||
| 789 | typedef struct { | ||
| 790 | __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */ | ||
| 791 | uint8_t RESERVED_0[28]; | ||
| 792 | __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */ | ||
| 793 | __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */ | ||
| 794 | __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */ | ||
| 795 | __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */ | ||
| 796 | uint8_t RESERVED_1[16]; | ||
| 797 | __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */ | ||
| 798 | __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */ | ||
| 799 | __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */ | ||
| 800 | __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */ | ||
| 801 | __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */ | ||
| 802 | __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */ | ||
| 803 | __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */ | ||
| 804 | __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */ | ||
| 805 | __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */ | ||
| 806 | __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */ | ||
| 807 | __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */ | ||
| 808 | __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */ | ||
| 809 | } AIPS_TypeDef; | ||
| 810 | |||
| 811 | /* ---------------------------------------------------------------------------- | ||
| 812 | -- AIPS Register Masks | ||
| 813 | ---------------------------------------------------------------------------- */ | ||
| 814 | |||
| 815 | /*! | ||
| 816 | * @addtogroup AIPS_Register_Masks AIPS Register Masks | ||
| 817 | * @{ | ||
| 818 | */ | ||
| 819 | |||
| 820 | /*! @name MPRA - Master Privilege Register A */ | ||
| 821 | #define AIPS_MPRA_MPL6_MASK (0x10U) | ||
| 822 | #define AIPS_MPRA_MPL6_SHIFT (4U) | ||
| 823 | #define AIPS_MPRA_MPL6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL6_SHIFT)) & AIPS_MPRA_MPL6_MASK) | ||
| 824 | #define AIPS_MPRA_MPL6 AIPS_MPRA_MPL6_MASK | ||
| 825 | #define AIPS_MPRA_MTW6_MASK (0x20U) | ||
| 826 | #define AIPS_MPRA_MTW6_SHIFT (5U) | ||
| 827 | #define AIPS_MPRA_MTW6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW6_SHIFT)) & AIPS_MPRA_MTW6_MASK) | ||
| 828 | #define AIPS_MPRA_MTW6 AIPS_MPRA_MTW6_MASK | ||
| 829 | #define AIPS_MPRA_MTR6_MASK (0x40U) | ||
| 830 | #define AIPS_MPRA_MTR6_SHIFT (6U) | ||
| 831 | #define AIPS_MPRA_MTR6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR6_SHIFT)) & AIPS_MPRA_MTR6_MASK) | ||
| 832 | #define AIPS_MPRA_MTR6 AIPS_MPRA_MTR6_MASK | ||
| 833 | #define AIPS_MPRA_MPL5_MASK (0x100U) | ||
| 834 | #define AIPS_MPRA_MPL5_SHIFT (8U) | ||
| 835 | #define AIPS_MPRA_MPL5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK) | ||
| 836 | #define AIPS_MPRA_MPL5 AIPS_MPRA_MPL5_MASK | ||
| 837 | #define AIPS_MPRA_MTW5_MASK (0x200U) | ||
| 838 | #define AIPS_MPRA_MTW5_SHIFT (9U) | ||
| 839 | #define AIPS_MPRA_MTW5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK) | ||
| 840 | #define AIPS_MPRA_MTW5 AIPS_MPRA_MTW5_MASK | ||
| 841 | #define AIPS_MPRA_MTR5_MASK (0x400U) | ||
| 842 | #define AIPS_MPRA_MTR5_SHIFT (10U) | ||
| 843 | #define AIPS_MPRA_MTR5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK) | ||
| 844 | #define AIPS_MPRA_MTR5 AIPS_MPRA_MTR5_MASK | ||
| 845 | #define AIPS_MPRA_MPL4_MASK (0x1000U) | ||
| 846 | #define AIPS_MPRA_MPL4_SHIFT (12U) | ||
| 847 | #define AIPS_MPRA_MPL4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK) | ||
| 848 | #define AIPS_MPRA_MPL4 AIPS_MPRA_MPL4_MASK | ||
| 849 | #define AIPS_MPRA_MTW4_MASK (0x2000U) | ||
| 850 | #define AIPS_MPRA_MTW4_SHIFT (13U) | ||
| 851 | #define AIPS_MPRA_MTW4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK) | ||
| 852 | #define AIPS_MPRA_MTW4 AIPS_MPRA_MTW4_MASK | ||
| 853 | #define AIPS_MPRA_MTR4_MASK (0x4000U) | ||
| 854 | #define AIPS_MPRA_MTR4_SHIFT (14U) | ||
| 855 | #define AIPS_MPRA_MTR4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK) | ||
| 856 | #define AIPS_MPRA_MTR4 AIPS_MPRA_MTR4_MASK | ||
| 857 | #define AIPS_MPRA_MPL3_MASK (0x10000U) | ||
| 858 | #define AIPS_MPRA_MPL3_SHIFT (16U) | ||
| 859 | #define AIPS_MPRA_MPL3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK) | ||
| 860 | #define AIPS_MPRA_MPL3 AIPS_MPRA_MPL3_MASK | ||
| 861 | #define AIPS_MPRA_MTW3_MASK (0x20000U) | ||
| 862 | #define AIPS_MPRA_MTW3_SHIFT (17U) | ||
| 863 | #define AIPS_MPRA_MTW3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK) | ||
| 864 | #define AIPS_MPRA_MTW3 AIPS_MPRA_MTW3_MASK | ||
| 865 | #define AIPS_MPRA_MTR3_MASK (0x40000U) | ||
| 866 | #define AIPS_MPRA_MTR3_SHIFT (18U) | ||
| 867 | #define AIPS_MPRA_MTR3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK) | ||
| 868 | #define AIPS_MPRA_MTR3 AIPS_MPRA_MTR3_MASK | ||
| 869 | #define AIPS_MPRA_MPL2_MASK (0x100000U) | ||
| 870 | #define AIPS_MPRA_MPL2_SHIFT (20U) | ||
| 871 | #define AIPS_MPRA_MPL2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK) | ||
| 872 | #define AIPS_MPRA_MPL2 AIPS_MPRA_MPL2_MASK | ||
| 873 | #define AIPS_MPRA_MTW2_MASK (0x200000U) | ||
| 874 | #define AIPS_MPRA_MTW2_SHIFT (21U) | ||
| 875 | #define AIPS_MPRA_MTW2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK) | ||
| 876 | #define AIPS_MPRA_MTW2 AIPS_MPRA_MTW2_MASK | ||
| 877 | #define AIPS_MPRA_MTR2_MASK (0x400000U) | ||
| 878 | #define AIPS_MPRA_MTR2_SHIFT (22U) | ||
| 879 | #define AIPS_MPRA_MTR2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK) | ||
| 880 | #define AIPS_MPRA_MTR2 AIPS_MPRA_MTR2_MASK | ||
| 881 | #define AIPS_MPRA_MPL1_MASK (0x1000000U) | ||
| 882 | #define AIPS_MPRA_MPL1_SHIFT (24U) | ||
| 883 | #define AIPS_MPRA_MPL1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK) | ||
| 884 | #define AIPS_MPRA_MPL1 AIPS_MPRA_MPL1_MASK | ||
| 885 | #define AIPS_MPRA_MTW1_MASK (0x2000000U) | ||
| 886 | #define AIPS_MPRA_MTW1_SHIFT (25U) | ||
| 887 | #define AIPS_MPRA_MTW1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK) | ||
| 888 | #define AIPS_MPRA_MTW1 AIPS_MPRA_MTW1_MASK | ||
| 889 | #define AIPS_MPRA_MTR1_MASK (0x4000000U) | ||
| 890 | #define AIPS_MPRA_MTR1_SHIFT (26U) | ||
| 891 | #define AIPS_MPRA_MTR1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK) | ||
| 892 | #define AIPS_MPRA_MTR1 AIPS_MPRA_MTR1_MASK | ||
| 893 | #define AIPS_MPRA_MPL0_MASK (0x10000000U) | ||
| 894 | #define AIPS_MPRA_MPL0_SHIFT (28U) | ||
| 895 | #define AIPS_MPRA_MPL0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK) | ||
| 896 | #define AIPS_MPRA_MPL0 AIPS_MPRA_MPL0_MASK | ||
| 897 | #define AIPS_MPRA_MTW0_MASK (0x20000000U) | ||
| 898 | #define AIPS_MPRA_MTW0_SHIFT (29U) | ||
| 899 | #define AIPS_MPRA_MTW0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK) | ||
| 900 | #define AIPS_MPRA_MTW0 AIPS_MPRA_MTW0_MASK | ||
| 901 | #define AIPS_MPRA_MTR0_MASK (0x40000000U) | ||
| 902 | #define AIPS_MPRA_MTR0_SHIFT (30U) | ||
| 903 | #define AIPS_MPRA_MTR0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK) | ||
| 904 | #define AIPS_MPRA_MTR0 AIPS_MPRA_MTR0_MASK | ||
| 905 | |||
| 906 | /*! @name PACRA - Peripheral Access Control Register */ | ||
| 907 | #define AIPS_PACRA_TP7_MASK (0x1U) | ||
| 908 | #define AIPS_PACRA_TP7_SHIFT (0U) | ||
| 909 | #define AIPS_PACRA_TP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK) | ||
| 910 | #define AIPS_PACRA_TP7 AIPS_PACRA_TP7_MASK | ||
| 911 | #define AIPS_PACRA_WP7_MASK (0x2U) | ||
| 912 | #define AIPS_PACRA_WP7_SHIFT (1U) | ||
| 913 | #define AIPS_PACRA_WP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK) | ||
| 914 | #define AIPS_PACRA_WP7 AIPS_PACRA_WP7_MASK | ||
| 915 | #define AIPS_PACRA_SP7_MASK (0x4U) | ||
| 916 | #define AIPS_PACRA_SP7_SHIFT (2U) | ||
| 917 | #define AIPS_PACRA_SP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK) | ||
| 918 | #define AIPS_PACRA_SP7 AIPS_PACRA_SP7_MASK | ||
| 919 | #define AIPS_PACRA_TP6_MASK (0x10U) | ||
| 920 | #define AIPS_PACRA_TP6_SHIFT (4U) | ||
| 921 | #define AIPS_PACRA_TP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK) | ||
| 922 | #define AIPS_PACRA_TP6 AIPS_PACRA_TP6_MASK | ||
| 923 | #define AIPS_PACRA_WP6_MASK (0x20U) | ||
| 924 | #define AIPS_PACRA_WP6_SHIFT (5U) | ||
| 925 | #define AIPS_PACRA_WP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK) | ||
| 926 | #define AIPS_PACRA_WP6 AIPS_PACRA_WP6_MASK | ||
| 927 | #define AIPS_PACRA_SP6_MASK (0x40U) | ||
| 928 | #define AIPS_PACRA_SP6_SHIFT (6U) | ||
| 929 | #define AIPS_PACRA_SP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK) | ||
| 930 | #define AIPS_PACRA_SP6 AIPS_PACRA_SP6_MASK | ||
| 931 | #define AIPS_PACRA_TP5_MASK (0x100U) | ||
| 932 | #define AIPS_PACRA_TP5_SHIFT (8U) | ||
| 933 | #define AIPS_PACRA_TP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK) | ||
| 934 | #define AIPS_PACRA_TP5 AIPS_PACRA_TP5_MASK | ||
| 935 | #define AIPS_PACRA_WP5_MASK (0x200U) | ||
| 936 | #define AIPS_PACRA_WP5_SHIFT (9U) | ||
| 937 | #define AIPS_PACRA_WP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK) | ||
| 938 | #define AIPS_PACRA_WP5 AIPS_PACRA_WP5_MASK | ||
| 939 | #define AIPS_PACRA_SP5_MASK (0x400U) | ||
| 940 | #define AIPS_PACRA_SP5_SHIFT (10U) | ||
| 941 | #define AIPS_PACRA_SP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK) | ||
| 942 | #define AIPS_PACRA_SP5 AIPS_PACRA_SP5_MASK | ||
| 943 | #define AIPS_PACRA_TP4_MASK (0x1000U) | ||
| 944 | #define AIPS_PACRA_TP4_SHIFT (12U) | ||
| 945 | #define AIPS_PACRA_TP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK) | ||
| 946 | #define AIPS_PACRA_TP4 AIPS_PACRA_TP4_MASK | ||
| 947 | #define AIPS_PACRA_WP4_MASK (0x2000U) | ||
| 948 | #define AIPS_PACRA_WP4_SHIFT (13U) | ||
| 949 | #define AIPS_PACRA_WP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK) | ||
| 950 | #define AIPS_PACRA_WP4 AIPS_PACRA_WP4_MASK | ||
| 951 | #define AIPS_PACRA_SP4_MASK (0x4000U) | ||
| 952 | #define AIPS_PACRA_SP4_SHIFT (14U) | ||
| 953 | #define AIPS_PACRA_SP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK) | ||
| 954 | #define AIPS_PACRA_SP4 AIPS_PACRA_SP4_MASK | ||
| 955 | #define AIPS_PACRA_TP3_MASK (0x10000U) | ||
| 956 | #define AIPS_PACRA_TP3_SHIFT (16U) | ||
| 957 | #define AIPS_PACRA_TP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK) | ||
| 958 | #define AIPS_PACRA_TP3 AIPS_PACRA_TP3_MASK | ||
| 959 | #define AIPS_PACRA_WP3_MASK (0x20000U) | ||
| 960 | #define AIPS_PACRA_WP3_SHIFT (17U) | ||
| 961 | #define AIPS_PACRA_WP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK) | ||
| 962 | #define AIPS_PACRA_WP3 AIPS_PACRA_WP3_MASK | ||
| 963 | #define AIPS_PACRA_SP3_MASK (0x40000U) | ||
| 964 | #define AIPS_PACRA_SP3_SHIFT (18U) | ||
| 965 | #define AIPS_PACRA_SP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK) | ||
| 966 | #define AIPS_PACRA_SP3 AIPS_PACRA_SP3_MASK | ||
| 967 | #define AIPS_PACRA_TP2_MASK (0x100000U) | ||
| 968 | #define AIPS_PACRA_TP2_SHIFT (20U) | ||
| 969 | #define AIPS_PACRA_TP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK) | ||
| 970 | #define AIPS_PACRA_TP2 AIPS_PACRA_TP2_MASK | ||
| 971 | #define AIPS_PACRA_WP2_MASK (0x200000U) | ||
| 972 | #define AIPS_PACRA_WP2_SHIFT (21U) | ||
| 973 | #define AIPS_PACRA_WP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK) | ||
| 974 | #define AIPS_PACRA_WP2 AIPS_PACRA_WP2_MASK | ||
| 975 | #define AIPS_PACRA_SP2_MASK (0x400000U) | ||
| 976 | #define AIPS_PACRA_SP2_SHIFT (22U) | ||
| 977 | #define AIPS_PACRA_SP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK) | ||
| 978 | #define AIPS_PACRA_SP2 AIPS_PACRA_SP2_MASK | ||
| 979 | #define AIPS_PACRA_TP1_MASK (0x1000000U) | ||
| 980 | #define AIPS_PACRA_TP1_SHIFT (24U) | ||
| 981 | #define AIPS_PACRA_TP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK) | ||
| 982 | #define AIPS_PACRA_TP1 AIPS_PACRA_TP1_MASK | ||
| 983 | #define AIPS_PACRA_WP1_MASK (0x2000000U) | ||
| 984 | #define AIPS_PACRA_WP1_SHIFT (25U) | ||
| 985 | #define AIPS_PACRA_WP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK) | ||
| 986 | #define AIPS_PACRA_WP1 AIPS_PACRA_WP1_MASK | ||
| 987 | #define AIPS_PACRA_SP1_MASK (0x4000000U) | ||
| 988 | #define AIPS_PACRA_SP1_SHIFT (26U) | ||
| 989 | #define AIPS_PACRA_SP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK) | ||
| 990 | #define AIPS_PACRA_SP1 AIPS_PACRA_SP1_MASK | ||
| 991 | #define AIPS_PACRA_TP0_MASK (0x10000000U) | ||
| 992 | #define AIPS_PACRA_TP0_SHIFT (28U) | ||
| 993 | #define AIPS_PACRA_TP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK) | ||
| 994 | #define AIPS_PACRA_TP0 AIPS_PACRA_TP0_MASK | ||
| 995 | #define AIPS_PACRA_WP0_MASK (0x20000000U) | ||
| 996 | #define AIPS_PACRA_WP0_SHIFT (29U) | ||
| 997 | #define AIPS_PACRA_WP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK) | ||
| 998 | #define AIPS_PACRA_WP0 AIPS_PACRA_WP0_MASK | ||
| 999 | #define AIPS_PACRA_SP0_MASK (0x40000000U) | ||
| 1000 | #define AIPS_PACRA_SP0_SHIFT (30U) | ||
| 1001 | #define AIPS_PACRA_SP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK) | ||
| 1002 | #define AIPS_PACRA_SP0 AIPS_PACRA_SP0_MASK | ||
| 1003 | |||
| 1004 | /*! @name PACRB - Peripheral Access Control Register */ | ||
| 1005 | #define AIPS_PACRB_TP7_MASK (0x1U) | ||
| 1006 | #define AIPS_PACRB_TP7_SHIFT (0U) | ||
| 1007 | #define AIPS_PACRB_TP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK) | ||
| 1008 | #define AIPS_PACRB_TP7 AIPS_PACRB_TP7_MASK | ||
| 1009 | #define AIPS_PACRB_WP7_MASK (0x2U) | ||
| 1010 | #define AIPS_PACRB_WP7_SHIFT (1U) | ||
| 1011 | #define AIPS_PACRB_WP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK) | ||
| 1012 | #define AIPS_PACRB_WP7 AIPS_PACRB_WP7_MASK | ||
| 1013 | #define AIPS_PACRB_SP7_MASK (0x4U) | ||
| 1014 | #define AIPS_PACRB_SP7_SHIFT (2U) | ||
| 1015 | #define AIPS_PACRB_SP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK) | ||
| 1016 | #define AIPS_PACRB_SP7 AIPS_PACRB_SP7_MASK | ||
| 1017 | #define AIPS_PACRB_TP6_MASK (0x10U) | ||
| 1018 | #define AIPS_PACRB_TP6_SHIFT (4U) | ||
| 1019 | #define AIPS_PACRB_TP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK) | ||
| 1020 | #define AIPS_PACRB_TP6 AIPS_PACRB_TP6_MASK | ||
| 1021 | #define AIPS_PACRB_WP6_MASK (0x20U) | ||
| 1022 | #define AIPS_PACRB_WP6_SHIFT (5U) | ||
| 1023 | #define AIPS_PACRB_WP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK) | ||
| 1024 | #define AIPS_PACRB_WP6 AIPS_PACRB_WP6_MASK | ||
| 1025 | #define AIPS_PACRB_SP6_MASK (0x40U) | ||
| 1026 | #define AIPS_PACRB_SP6_SHIFT (6U) | ||
| 1027 | #define AIPS_PACRB_SP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK) | ||
| 1028 | #define AIPS_PACRB_SP6 AIPS_PACRB_SP6_MASK | ||
| 1029 | #define AIPS_PACRB_TP5_MASK (0x100U) | ||
| 1030 | #define AIPS_PACRB_TP5_SHIFT (8U) | ||
| 1031 | #define AIPS_PACRB_TP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK) | ||
| 1032 | #define AIPS_PACRB_TP5 AIPS_PACRB_TP5_MASK | ||
| 1033 | #define AIPS_PACRB_WP5_MASK (0x200U) | ||
| 1034 | #define AIPS_PACRB_WP5_SHIFT (9U) | ||
| 1035 | #define AIPS_PACRB_WP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK) | ||
| 1036 | #define AIPS_PACRB_WP5 AIPS_PACRB_WP5_MASK | ||
| 1037 | #define AIPS_PACRB_SP5_MASK (0x400U) | ||
| 1038 | #define AIPS_PACRB_SP5_SHIFT (10U) | ||
| 1039 | #define AIPS_PACRB_SP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK) | ||
| 1040 | #define AIPS_PACRB_SP5 AIPS_PACRB_SP5_MASK | ||
| 1041 | #define AIPS_PACRB_TP4_MASK (0x1000U) | ||
| 1042 | #define AIPS_PACRB_TP4_SHIFT (12U) | ||
| 1043 | #define AIPS_PACRB_TP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK) | ||
| 1044 | #define AIPS_PACRB_TP4 AIPS_PACRB_TP4_MASK | ||
| 1045 | #define AIPS_PACRB_WP4_MASK (0x2000U) | ||
| 1046 | #define AIPS_PACRB_WP4_SHIFT (13U) | ||
| 1047 | #define AIPS_PACRB_WP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK) | ||
| 1048 | #define AIPS_PACRB_WP4 AIPS_PACRB_WP4_MASK | ||
| 1049 | #define AIPS_PACRB_SP4_MASK (0x4000U) | ||
| 1050 | #define AIPS_PACRB_SP4_SHIFT (14U) | ||
| 1051 | #define AIPS_PACRB_SP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK) | ||
| 1052 | #define AIPS_PACRB_SP4 AIPS_PACRB_SP4_MASK | ||
| 1053 | #define AIPS_PACRB_TP3_MASK (0x10000U) | ||
| 1054 | #define AIPS_PACRB_TP3_SHIFT (16U) | ||
| 1055 | #define AIPS_PACRB_TP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK) | ||
| 1056 | #define AIPS_PACRB_TP3 AIPS_PACRB_TP3_MASK | ||
| 1057 | #define AIPS_PACRB_WP3_MASK (0x20000U) | ||
| 1058 | #define AIPS_PACRB_WP3_SHIFT (17U) | ||
| 1059 | #define AIPS_PACRB_WP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK) | ||
| 1060 | #define AIPS_PACRB_WP3 AIPS_PACRB_WP3_MASK | ||
| 1061 | #define AIPS_PACRB_SP3_MASK (0x40000U) | ||
| 1062 | #define AIPS_PACRB_SP3_SHIFT (18U) | ||
| 1063 | #define AIPS_PACRB_SP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK) | ||
| 1064 | #define AIPS_PACRB_SP3 AIPS_PACRB_SP3_MASK | ||
| 1065 | #define AIPS_PACRB_TP2_MASK (0x100000U) | ||
| 1066 | #define AIPS_PACRB_TP2_SHIFT (20U) | ||
| 1067 | #define AIPS_PACRB_TP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK) | ||
| 1068 | #define AIPS_PACRB_TP2 AIPS_PACRB_TP2_MASK | ||
| 1069 | #define AIPS_PACRB_WP2_MASK (0x200000U) | ||
| 1070 | #define AIPS_PACRB_WP2_SHIFT (21U) | ||
| 1071 | #define AIPS_PACRB_WP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK) | ||
| 1072 | #define AIPS_PACRB_WP2 AIPS_PACRB_WP2_MASK | ||
| 1073 | #define AIPS_PACRB_SP2_MASK (0x400000U) | ||
| 1074 | #define AIPS_PACRB_SP2_SHIFT (22U) | ||
| 1075 | #define AIPS_PACRB_SP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK) | ||
| 1076 | #define AIPS_PACRB_SP2 AIPS_PACRB_SP2_MASK | ||
| 1077 | #define AIPS_PACRB_TP1_MASK (0x1000000U) | ||
| 1078 | #define AIPS_PACRB_TP1_SHIFT (24U) | ||
| 1079 | #define AIPS_PACRB_TP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK) | ||
| 1080 | #define AIPS_PACRB_TP1 AIPS_PACRB_TP1_MASK | ||
| 1081 | #define AIPS_PACRB_WP1_MASK (0x2000000U) | ||
| 1082 | #define AIPS_PACRB_WP1_SHIFT (25U) | ||
| 1083 | #define AIPS_PACRB_WP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK) | ||
| 1084 | #define AIPS_PACRB_WP1 AIPS_PACRB_WP1_MASK | ||
| 1085 | #define AIPS_PACRB_SP1_MASK (0x4000000U) | ||
| 1086 | #define AIPS_PACRB_SP1_SHIFT (26U) | ||
| 1087 | #define AIPS_PACRB_SP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK) | ||
| 1088 | #define AIPS_PACRB_SP1 AIPS_PACRB_SP1_MASK | ||
| 1089 | #define AIPS_PACRB_TP0_MASK (0x10000000U) | ||
| 1090 | #define AIPS_PACRB_TP0_SHIFT (28U) | ||
| 1091 | #define AIPS_PACRB_TP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK) | ||
| 1092 | #define AIPS_PACRB_TP0 AIPS_PACRB_TP0_MASK | ||
| 1093 | #define AIPS_PACRB_WP0_MASK (0x20000000U) | ||
| 1094 | #define AIPS_PACRB_WP0_SHIFT (29U) | ||
| 1095 | #define AIPS_PACRB_WP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK) | ||
| 1096 | #define AIPS_PACRB_WP0 AIPS_PACRB_WP0_MASK | ||
| 1097 | #define AIPS_PACRB_SP0_MASK (0x40000000U) | ||
| 1098 | #define AIPS_PACRB_SP0_SHIFT (30U) | ||
| 1099 | #define AIPS_PACRB_SP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK) | ||
| 1100 | #define AIPS_PACRB_SP0 AIPS_PACRB_SP0_MASK | ||
| 1101 | |||
| 1102 | /*! @name PACRC - Peripheral Access Control Register */ | ||
| 1103 | #define AIPS_PACRC_TP7_MASK (0x1U) | ||
| 1104 | #define AIPS_PACRC_TP7_SHIFT (0U) | ||
| 1105 | #define AIPS_PACRC_TP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK) | ||
| 1106 | #define AIPS_PACRC_TP7 AIPS_PACRC_TP7_MASK | ||
| 1107 | #define AIPS_PACRC_WP7_MASK (0x2U) | ||
| 1108 | #define AIPS_PACRC_WP7_SHIFT (1U) | ||
| 1109 | #define AIPS_PACRC_WP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK) | ||
| 1110 | #define AIPS_PACRC_WP7 AIPS_PACRC_WP7_MASK | ||
| 1111 | #define AIPS_PACRC_SP7_MASK (0x4U) | ||
| 1112 | #define AIPS_PACRC_SP7_SHIFT (2U) | ||
| 1113 | #define AIPS_PACRC_SP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK) | ||
| 1114 | #define AIPS_PACRC_SP7 AIPS_PACRC_SP7_MASK | ||
| 1115 | #define AIPS_PACRC_TP6_MASK (0x10U) | ||
| 1116 | #define AIPS_PACRC_TP6_SHIFT (4U) | ||
| 1117 | #define AIPS_PACRC_TP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK) | ||
| 1118 | #define AIPS_PACRC_TP6 AIPS_PACRC_TP6_MASK | ||
| 1119 | #define AIPS_PACRC_WP6_MASK (0x20U) | ||
| 1120 | #define AIPS_PACRC_WP6_SHIFT (5U) | ||
| 1121 | #define AIPS_PACRC_WP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK) | ||
| 1122 | #define AIPS_PACRC_WP6 AIPS_PACRC_WP6_MASK | ||
| 1123 | #define AIPS_PACRC_SP6_MASK (0x40U) | ||
| 1124 | #define AIPS_PACRC_SP6_SHIFT (6U) | ||
| 1125 | #define AIPS_PACRC_SP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK) | ||
| 1126 | #define AIPS_PACRC_SP6 AIPS_PACRC_SP6_MASK | ||
| 1127 | #define AIPS_PACRC_TP5_MASK (0x100U) | ||
| 1128 | #define AIPS_PACRC_TP5_SHIFT (8U) | ||
| 1129 | #define AIPS_PACRC_TP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK) | ||
| 1130 | #define AIPS_PACRC_TP5 AIPS_PACRC_TP5_MASK | ||
| 1131 | #define AIPS_PACRC_WP5_MASK (0x200U) | ||
| 1132 | #define AIPS_PACRC_WP5_SHIFT (9U) | ||
| 1133 | #define AIPS_PACRC_WP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK) | ||
| 1134 | #define AIPS_PACRC_WP5 AIPS_PACRC_WP5_MASK | ||
| 1135 | #define AIPS_PACRC_SP5_MASK (0x400U) | ||
| 1136 | #define AIPS_PACRC_SP5_SHIFT (10U) | ||
| 1137 | #define AIPS_PACRC_SP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK) | ||
| 1138 | #define AIPS_PACRC_SP5 AIPS_PACRC_SP5_MASK | ||
| 1139 | #define AIPS_PACRC_TP4_MASK (0x1000U) | ||
| 1140 | #define AIPS_PACRC_TP4_SHIFT (12U) | ||
| 1141 | #define AIPS_PACRC_TP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK) | ||
| 1142 | #define AIPS_PACRC_TP4 AIPS_PACRC_TP4_MASK | ||
| 1143 | #define AIPS_PACRC_WP4_MASK (0x2000U) | ||
| 1144 | #define AIPS_PACRC_WP4_SHIFT (13U) | ||
| 1145 | #define AIPS_PACRC_WP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK) | ||
| 1146 | #define AIPS_PACRC_WP4 AIPS_PACRC_WP4_MASK | ||
| 1147 | #define AIPS_PACRC_SP4_MASK (0x4000U) | ||
| 1148 | #define AIPS_PACRC_SP4_SHIFT (14U) | ||
| 1149 | #define AIPS_PACRC_SP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK) | ||
| 1150 | #define AIPS_PACRC_SP4 AIPS_PACRC_SP4_MASK | ||
| 1151 | #define AIPS_PACRC_TP3_MASK (0x10000U) | ||
| 1152 | #define AIPS_PACRC_TP3_SHIFT (16U) | ||
| 1153 | #define AIPS_PACRC_TP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK) | ||
| 1154 | #define AIPS_PACRC_TP3 AIPS_PACRC_TP3_MASK | ||
| 1155 | #define AIPS_PACRC_WP3_MASK (0x20000U) | ||
| 1156 | #define AIPS_PACRC_WP3_SHIFT (17U) | ||
| 1157 | #define AIPS_PACRC_WP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK) | ||
| 1158 | #define AIPS_PACRC_WP3 AIPS_PACRC_WP3_MASK | ||
| 1159 | #define AIPS_PACRC_SP3_MASK (0x40000U) | ||
| 1160 | #define AIPS_PACRC_SP3_SHIFT (18U) | ||
| 1161 | #define AIPS_PACRC_SP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK) | ||
| 1162 | #define AIPS_PACRC_SP3 AIPS_PACRC_SP3_MASK | ||
| 1163 | #define AIPS_PACRC_TP2_MASK (0x100000U) | ||
| 1164 | #define AIPS_PACRC_TP2_SHIFT (20U) | ||
| 1165 | #define AIPS_PACRC_TP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK) | ||
| 1166 | #define AIPS_PACRC_TP2 AIPS_PACRC_TP2_MASK | ||
| 1167 | #define AIPS_PACRC_WP2_MASK (0x200000U) | ||
| 1168 | #define AIPS_PACRC_WP2_SHIFT (21U) | ||
| 1169 | #define AIPS_PACRC_WP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK) | ||
| 1170 | #define AIPS_PACRC_WP2 AIPS_PACRC_WP2_MASK | ||
| 1171 | #define AIPS_PACRC_SP2_MASK (0x400000U) | ||
| 1172 | #define AIPS_PACRC_SP2_SHIFT (22U) | ||
| 1173 | #define AIPS_PACRC_SP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK) | ||
| 1174 | #define AIPS_PACRC_SP2 AIPS_PACRC_SP2_MASK | ||
| 1175 | #define AIPS_PACRC_TP1_MASK (0x1000000U) | ||
| 1176 | #define AIPS_PACRC_TP1_SHIFT (24U) | ||
| 1177 | #define AIPS_PACRC_TP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK) | ||
| 1178 | #define AIPS_PACRC_TP1 AIPS_PACRC_TP1_MASK | ||
| 1179 | #define AIPS_PACRC_WP1_MASK (0x2000000U) | ||
| 1180 | #define AIPS_PACRC_WP1_SHIFT (25U) | ||
| 1181 | #define AIPS_PACRC_WP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK) | ||
| 1182 | #define AIPS_PACRC_WP1 AIPS_PACRC_WP1_MASK | ||
| 1183 | #define AIPS_PACRC_SP1_MASK (0x4000000U) | ||
| 1184 | #define AIPS_PACRC_SP1_SHIFT (26U) | ||
| 1185 | #define AIPS_PACRC_SP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK) | ||
| 1186 | #define AIPS_PACRC_SP1 AIPS_PACRC_SP1_MASK | ||
| 1187 | #define AIPS_PACRC_TP0_MASK (0x10000000U) | ||
| 1188 | #define AIPS_PACRC_TP0_SHIFT (28U) | ||
| 1189 | #define AIPS_PACRC_TP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK) | ||
| 1190 | #define AIPS_PACRC_TP0 AIPS_PACRC_TP0_MASK | ||
| 1191 | #define AIPS_PACRC_WP0_MASK (0x20000000U) | ||
| 1192 | #define AIPS_PACRC_WP0_SHIFT (29U) | ||
| 1193 | #define AIPS_PACRC_WP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK) | ||
| 1194 | #define AIPS_PACRC_WP0 AIPS_PACRC_WP0_MASK | ||
| 1195 | #define AIPS_PACRC_SP0_MASK (0x40000000U) | ||
| 1196 | #define AIPS_PACRC_SP0_SHIFT (30U) | ||
| 1197 | #define AIPS_PACRC_SP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK) | ||
| 1198 | #define AIPS_PACRC_SP0 AIPS_PACRC_SP0_MASK | ||
| 1199 | |||
| 1200 | /*! @name PACRD - Peripheral Access Control Register */ | ||
| 1201 | #define AIPS_PACRD_TP7_MASK (0x1U) | ||
| 1202 | #define AIPS_PACRD_TP7_SHIFT (0U) | ||
| 1203 | #define AIPS_PACRD_TP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK) | ||
| 1204 | #define AIPS_PACRD_TP7 AIPS_PACRD_TP7_MASK | ||
| 1205 | #define AIPS_PACRD_WP7_MASK (0x2U) | ||
| 1206 | #define AIPS_PACRD_WP7_SHIFT (1U) | ||
| 1207 | #define AIPS_PACRD_WP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK) | ||
| 1208 | #define AIPS_PACRD_WP7 AIPS_PACRD_WP7_MASK | ||
| 1209 | #define AIPS_PACRD_SP7_MASK (0x4U) | ||
| 1210 | #define AIPS_PACRD_SP7_SHIFT (2U) | ||
| 1211 | #define AIPS_PACRD_SP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK) | ||
| 1212 | #define AIPS_PACRD_SP7 AIPS_PACRD_SP7_MASK | ||
| 1213 | #define AIPS_PACRD_TP6_MASK (0x10U) | ||
| 1214 | #define AIPS_PACRD_TP6_SHIFT (4U) | ||
| 1215 | #define AIPS_PACRD_TP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK) | ||
| 1216 | #define AIPS_PACRD_TP6 AIPS_PACRD_TP6_MASK | ||
| 1217 | #define AIPS_PACRD_WP6_MASK (0x20U) | ||
| 1218 | #define AIPS_PACRD_WP6_SHIFT (5U) | ||
| 1219 | #define AIPS_PACRD_WP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK) | ||
| 1220 | #define AIPS_PACRD_WP6 AIPS_PACRD_WP6_MASK | ||
| 1221 | #define AIPS_PACRD_SP6_MASK (0x40U) | ||
| 1222 | #define AIPS_PACRD_SP6_SHIFT (6U) | ||
| 1223 | #define AIPS_PACRD_SP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK) | ||
| 1224 | #define AIPS_PACRD_SP6 AIPS_PACRD_SP6_MASK | ||
| 1225 | #define AIPS_PACRD_TP5_MASK (0x100U) | ||
| 1226 | #define AIPS_PACRD_TP5_SHIFT (8U) | ||
| 1227 | #define AIPS_PACRD_TP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK) | ||
| 1228 | #define AIPS_PACRD_TP5 AIPS_PACRD_TP5_MASK | ||
| 1229 | #define AIPS_PACRD_WP5_MASK (0x200U) | ||
| 1230 | #define AIPS_PACRD_WP5_SHIFT (9U) | ||
| 1231 | #define AIPS_PACRD_WP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK) | ||
| 1232 | #define AIPS_PACRD_WP5 AIPS_PACRD_WP5_MASK | ||
| 1233 | #define AIPS_PACRD_SP5_MASK (0x400U) | ||
| 1234 | #define AIPS_PACRD_SP5_SHIFT (10U) | ||
| 1235 | #define AIPS_PACRD_SP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK) | ||
| 1236 | #define AIPS_PACRD_SP5 AIPS_PACRD_SP5_MASK | ||
| 1237 | #define AIPS_PACRD_TP4_MASK (0x1000U) | ||
| 1238 | #define AIPS_PACRD_TP4_SHIFT (12U) | ||
| 1239 | #define AIPS_PACRD_TP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK) | ||
| 1240 | #define AIPS_PACRD_TP4 AIPS_PACRD_TP4_MASK | ||
| 1241 | #define AIPS_PACRD_WP4_MASK (0x2000U) | ||
| 1242 | #define AIPS_PACRD_WP4_SHIFT (13U) | ||
| 1243 | #define AIPS_PACRD_WP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK) | ||
| 1244 | #define AIPS_PACRD_WP4 AIPS_PACRD_WP4_MASK | ||
| 1245 | #define AIPS_PACRD_SP4_MASK (0x4000U) | ||
| 1246 | #define AIPS_PACRD_SP4_SHIFT (14U) | ||
| 1247 | #define AIPS_PACRD_SP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK) | ||
| 1248 | #define AIPS_PACRD_SP4 AIPS_PACRD_SP4_MASK | ||
| 1249 | #define AIPS_PACRD_TP3_MASK (0x10000U) | ||
| 1250 | #define AIPS_PACRD_TP3_SHIFT (16U) | ||
| 1251 | #define AIPS_PACRD_TP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK) | ||
| 1252 | #define AIPS_PACRD_TP3 AIPS_PACRD_TP3_MASK | ||
| 1253 | #define AIPS_PACRD_WP3_MASK (0x20000U) | ||
| 1254 | #define AIPS_PACRD_WP3_SHIFT (17U) | ||
| 1255 | #define AIPS_PACRD_WP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK) | ||
| 1256 | #define AIPS_PACRD_WP3 AIPS_PACRD_WP3_MASK | ||
| 1257 | #define AIPS_PACRD_SP3_MASK (0x40000U) | ||
| 1258 | #define AIPS_PACRD_SP3_SHIFT (18U) | ||
| 1259 | #define AIPS_PACRD_SP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK) | ||
| 1260 | #define AIPS_PACRD_SP3 AIPS_PACRD_SP3_MASK | ||
| 1261 | #define AIPS_PACRD_TP2_MASK (0x100000U) | ||
| 1262 | #define AIPS_PACRD_TP2_SHIFT (20U) | ||
| 1263 | #define AIPS_PACRD_TP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK) | ||
| 1264 | #define AIPS_PACRD_TP2 AIPS_PACRD_TP2_MASK | ||
| 1265 | #define AIPS_PACRD_WP2_MASK (0x200000U) | ||
| 1266 | #define AIPS_PACRD_WP2_SHIFT (21U) | ||
| 1267 | #define AIPS_PACRD_WP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK) | ||
| 1268 | #define AIPS_PACRD_WP2 AIPS_PACRD_WP2_MASK | ||
| 1269 | #define AIPS_PACRD_SP2_MASK (0x400000U) | ||
| 1270 | #define AIPS_PACRD_SP2_SHIFT (22U) | ||
| 1271 | #define AIPS_PACRD_SP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK) | ||
| 1272 | #define AIPS_PACRD_SP2 AIPS_PACRD_SP2_MASK | ||
| 1273 | #define AIPS_PACRD_TP1_MASK (0x1000000U) | ||
| 1274 | #define AIPS_PACRD_TP1_SHIFT (24U) | ||
| 1275 | #define AIPS_PACRD_TP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK) | ||
| 1276 | #define AIPS_PACRD_TP1 AIPS_PACRD_TP1_MASK | ||
| 1277 | #define AIPS_PACRD_WP1_MASK (0x2000000U) | ||
| 1278 | #define AIPS_PACRD_WP1_SHIFT (25U) | ||
| 1279 | #define AIPS_PACRD_WP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK) | ||
| 1280 | #define AIPS_PACRD_WP1 AIPS_PACRD_WP1_MASK | ||
| 1281 | #define AIPS_PACRD_SP1_MASK (0x4000000U) | ||
| 1282 | #define AIPS_PACRD_SP1_SHIFT (26U) | ||
| 1283 | #define AIPS_PACRD_SP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK) | ||
| 1284 | #define AIPS_PACRD_SP1 AIPS_PACRD_SP1_MASK | ||
| 1285 | #define AIPS_PACRD_TP0_MASK (0x10000000U) | ||
| 1286 | #define AIPS_PACRD_TP0_SHIFT (28U) | ||
| 1287 | #define AIPS_PACRD_TP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK) | ||
| 1288 | #define AIPS_PACRD_TP0 AIPS_PACRD_TP0_MASK | ||
| 1289 | #define AIPS_PACRD_WP0_MASK (0x20000000U) | ||
| 1290 | #define AIPS_PACRD_WP0_SHIFT (29U) | ||
| 1291 | #define AIPS_PACRD_WP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK) | ||
| 1292 | #define AIPS_PACRD_WP0 AIPS_PACRD_WP0_MASK | ||
| 1293 | #define AIPS_PACRD_SP0_MASK (0x40000000U) | ||
| 1294 | #define AIPS_PACRD_SP0_SHIFT (30U) | ||
| 1295 | #define AIPS_PACRD_SP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK) | ||
| 1296 | #define AIPS_PACRD_SP0 AIPS_PACRD_SP0_MASK | ||
| 1297 | |||
| 1298 | /*! @name PACRE - Peripheral Access Control Register */ | ||
| 1299 | #define AIPS_PACRE_TP7_MASK (0x1U) | ||
| 1300 | #define AIPS_PACRE_TP7_SHIFT (0U) | ||
| 1301 | #define AIPS_PACRE_TP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK) | ||
| 1302 | #define AIPS_PACRE_TP7 AIPS_PACRE_TP7_MASK | ||
| 1303 | #define AIPS_PACRE_WP7_MASK (0x2U) | ||
| 1304 | #define AIPS_PACRE_WP7_SHIFT (1U) | ||
| 1305 | #define AIPS_PACRE_WP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK) | ||
| 1306 | #define AIPS_PACRE_WP7 AIPS_PACRE_WP7_MASK | ||
| 1307 | #define AIPS_PACRE_SP7_MASK (0x4U) | ||
| 1308 | #define AIPS_PACRE_SP7_SHIFT (2U) | ||
| 1309 | #define AIPS_PACRE_SP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK) | ||
| 1310 | #define AIPS_PACRE_SP7 AIPS_PACRE_SP7_MASK | ||
| 1311 | #define AIPS_PACRE_TP6_MASK (0x10U) | ||
| 1312 | #define AIPS_PACRE_TP6_SHIFT (4U) | ||
| 1313 | #define AIPS_PACRE_TP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK) | ||
| 1314 | #define AIPS_PACRE_TP6 AIPS_PACRE_TP6_MASK | ||
| 1315 | #define AIPS_PACRE_WP6_MASK (0x20U) | ||
| 1316 | #define AIPS_PACRE_WP6_SHIFT (5U) | ||
| 1317 | #define AIPS_PACRE_WP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK) | ||
| 1318 | #define AIPS_PACRE_WP6 AIPS_PACRE_WP6_MASK | ||
| 1319 | #define AIPS_PACRE_SP6_MASK (0x40U) | ||
| 1320 | #define AIPS_PACRE_SP6_SHIFT (6U) | ||
| 1321 | #define AIPS_PACRE_SP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK) | ||
| 1322 | #define AIPS_PACRE_SP6 AIPS_PACRE_SP6_MASK | ||
| 1323 | #define AIPS_PACRE_TP5_MASK (0x100U) | ||
| 1324 | #define AIPS_PACRE_TP5_SHIFT (8U) | ||
| 1325 | #define AIPS_PACRE_TP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK) | ||
| 1326 | #define AIPS_PACRE_TP5 AIPS_PACRE_TP5_MASK | ||
| 1327 | #define AIPS_PACRE_WP5_MASK (0x200U) | ||
| 1328 | #define AIPS_PACRE_WP5_SHIFT (9U) | ||
| 1329 | #define AIPS_PACRE_WP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK) | ||
| 1330 | #define AIPS_PACRE_WP5 AIPS_PACRE_WP5_MASK | ||
| 1331 | #define AIPS_PACRE_SP5_MASK (0x400U) | ||
| 1332 | #define AIPS_PACRE_SP5_SHIFT (10U) | ||
| 1333 | #define AIPS_PACRE_SP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK) | ||
| 1334 | #define AIPS_PACRE_SP5 AIPS_PACRE_SP5_MASK | ||
| 1335 | #define AIPS_PACRE_TP4_MASK (0x1000U) | ||
| 1336 | #define AIPS_PACRE_TP4_SHIFT (12U) | ||
| 1337 | #define AIPS_PACRE_TP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK) | ||
| 1338 | #define AIPS_PACRE_TP4 AIPS_PACRE_TP4_MASK | ||
| 1339 | #define AIPS_PACRE_WP4_MASK (0x2000U) | ||
| 1340 | #define AIPS_PACRE_WP4_SHIFT (13U) | ||
| 1341 | #define AIPS_PACRE_WP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK) | ||
| 1342 | #define AIPS_PACRE_WP4 AIPS_PACRE_WP4_MASK | ||
| 1343 | #define AIPS_PACRE_SP4_MASK (0x4000U) | ||
| 1344 | #define AIPS_PACRE_SP4_SHIFT (14U) | ||
| 1345 | #define AIPS_PACRE_SP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK) | ||
| 1346 | #define AIPS_PACRE_SP4 AIPS_PACRE_SP4_MASK | ||
| 1347 | #define AIPS_PACRE_TP3_MASK (0x10000U) | ||
| 1348 | #define AIPS_PACRE_TP3_SHIFT (16U) | ||
| 1349 | #define AIPS_PACRE_TP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK) | ||
| 1350 | #define AIPS_PACRE_TP3 AIPS_PACRE_TP3_MASK | ||
| 1351 | #define AIPS_PACRE_WP3_MASK (0x20000U) | ||
| 1352 | #define AIPS_PACRE_WP3_SHIFT (17U) | ||
| 1353 | #define AIPS_PACRE_WP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK) | ||
| 1354 | #define AIPS_PACRE_WP3 AIPS_PACRE_WP3_MASK | ||
| 1355 | #define AIPS_PACRE_SP3_MASK (0x40000U) | ||
| 1356 | #define AIPS_PACRE_SP3_SHIFT (18U) | ||
| 1357 | #define AIPS_PACRE_SP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK) | ||
| 1358 | #define AIPS_PACRE_SP3 AIPS_PACRE_SP3_MASK | ||
| 1359 | #define AIPS_PACRE_TP2_MASK (0x100000U) | ||
| 1360 | #define AIPS_PACRE_TP2_SHIFT (20U) | ||
| 1361 | #define AIPS_PACRE_TP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK) | ||
| 1362 | #define AIPS_PACRE_TP2 AIPS_PACRE_TP2_MASK | ||
| 1363 | #define AIPS_PACRE_WP2_MASK (0x200000U) | ||
| 1364 | #define AIPS_PACRE_WP2_SHIFT (21U) | ||
| 1365 | #define AIPS_PACRE_WP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK) | ||
| 1366 | #define AIPS_PACRE_WP2 AIPS_PACRE_WP2_MASK | ||
| 1367 | #define AIPS_PACRE_SP2_MASK (0x400000U) | ||
| 1368 | #define AIPS_PACRE_SP2_SHIFT (22U) | ||
| 1369 | #define AIPS_PACRE_SP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK) | ||
| 1370 | #define AIPS_PACRE_SP2 AIPS_PACRE_SP2_MASK | ||
| 1371 | #define AIPS_PACRE_TP1_MASK (0x1000000U) | ||
| 1372 | #define AIPS_PACRE_TP1_SHIFT (24U) | ||
| 1373 | #define AIPS_PACRE_TP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK) | ||
| 1374 | #define AIPS_PACRE_TP1 AIPS_PACRE_TP1_MASK | ||
| 1375 | #define AIPS_PACRE_WP1_MASK (0x2000000U) | ||
| 1376 | #define AIPS_PACRE_WP1_SHIFT (25U) | ||
| 1377 | #define AIPS_PACRE_WP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK) | ||
| 1378 | #define AIPS_PACRE_WP1 AIPS_PACRE_WP1_MASK | ||
| 1379 | #define AIPS_PACRE_SP1_MASK (0x4000000U) | ||
| 1380 | #define AIPS_PACRE_SP1_SHIFT (26U) | ||
| 1381 | #define AIPS_PACRE_SP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK) | ||
| 1382 | #define AIPS_PACRE_SP1 AIPS_PACRE_SP1_MASK | ||
| 1383 | #define AIPS_PACRE_TP0_MASK (0x10000000U) | ||
| 1384 | #define AIPS_PACRE_TP0_SHIFT (28U) | ||
| 1385 | #define AIPS_PACRE_TP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK) | ||
| 1386 | #define AIPS_PACRE_TP0 AIPS_PACRE_TP0_MASK | ||
| 1387 | #define AIPS_PACRE_WP0_MASK (0x20000000U) | ||
| 1388 | #define AIPS_PACRE_WP0_SHIFT (29U) | ||
| 1389 | #define AIPS_PACRE_WP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK) | ||
| 1390 | #define AIPS_PACRE_WP0 AIPS_PACRE_WP0_MASK | ||
| 1391 | #define AIPS_PACRE_SP0_MASK (0x40000000U) | ||
| 1392 | #define AIPS_PACRE_SP0_SHIFT (30U) | ||
| 1393 | #define AIPS_PACRE_SP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK) | ||
| 1394 | #define AIPS_PACRE_SP0 AIPS_PACRE_SP0_MASK | ||
| 1395 | |||
| 1396 | /*! @name PACRF - Peripheral Access Control Register */ | ||
| 1397 | #define AIPS_PACRF_TP7_MASK (0x1U) | ||
| 1398 | #define AIPS_PACRF_TP7_SHIFT (0U) | ||
| 1399 | #define AIPS_PACRF_TP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK) | ||
| 1400 | #define AIPS_PACRF_TP7 AIPS_PACRF_TP7_MASK | ||
| 1401 | #define AIPS_PACRF_WP7_MASK (0x2U) | ||
| 1402 | #define AIPS_PACRF_WP7_SHIFT (1U) | ||
| 1403 | #define AIPS_PACRF_WP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK) | ||
| 1404 | #define AIPS_PACRF_WP7 AIPS_PACRF_WP7_MASK | ||
| 1405 | #define AIPS_PACRF_SP7_MASK (0x4U) | ||
| 1406 | #define AIPS_PACRF_SP7_SHIFT (2U) | ||
| 1407 | #define AIPS_PACRF_SP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK) | ||
| 1408 | #define AIPS_PACRF_SP7 AIPS_PACRF_SP7_MASK | ||
| 1409 | #define AIPS_PACRF_TP6_MASK (0x10U) | ||
| 1410 | #define AIPS_PACRF_TP6_SHIFT (4U) | ||
| 1411 | #define AIPS_PACRF_TP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK) | ||
| 1412 | #define AIPS_PACRF_TP6 AIPS_PACRF_TP6_MASK | ||
| 1413 | #define AIPS_PACRF_WP6_MASK (0x20U) | ||
| 1414 | #define AIPS_PACRF_WP6_SHIFT (5U) | ||
| 1415 | #define AIPS_PACRF_WP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK) | ||
| 1416 | #define AIPS_PACRF_WP6 AIPS_PACRF_WP6_MASK | ||
| 1417 | #define AIPS_PACRF_SP6_MASK (0x40U) | ||
| 1418 | #define AIPS_PACRF_SP6_SHIFT (6U) | ||
| 1419 | #define AIPS_PACRF_SP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK) | ||
| 1420 | #define AIPS_PACRF_SP6 AIPS_PACRF_SP6_MASK | ||
| 1421 | #define AIPS_PACRF_TP5_MASK (0x100U) | ||
| 1422 | #define AIPS_PACRF_TP5_SHIFT (8U) | ||
| 1423 | #define AIPS_PACRF_TP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK) | ||
| 1424 | #define AIPS_PACRF_TP5 AIPS_PACRF_TP5_MASK | ||
| 1425 | #define AIPS_PACRF_WP5_MASK (0x200U) | ||
| 1426 | #define AIPS_PACRF_WP5_SHIFT (9U) | ||
| 1427 | #define AIPS_PACRF_WP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK) | ||
| 1428 | #define AIPS_PACRF_WP5 AIPS_PACRF_WP5_MASK | ||
| 1429 | #define AIPS_PACRF_SP5_MASK (0x400U) | ||
| 1430 | #define AIPS_PACRF_SP5_SHIFT (10U) | ||
| 1431 | #define AIPS_PACRF_SP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK) | ||
| 1432 | #define AIPS_PACRF_SP5 AIPS_PACRF_SP5_MASK | ||
| 1433 | #define AIPS_PACRF_TP4_MASK (0x1000U) | ||
| 1434 | #define AIPS_PACRF_TP4_SHIFT (12U) | ||
| 1435 | #define AIPS_PACRF_TP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK) | ||
| 1436 | #define AIPS_PACRF_TP4 AIPS_PACRF_TP4_MASK | ||
| 1437 | #define AIPS_PACRF_WP4_MASK (0x2000U) | ||
| 1438 | #define AIPS_PACRF_WP4_SHIFT (13U) | ||
| 1439 | #define AIPS_PACRF_WP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK) | ||
| 1440 | #define AIPS_PACRF_WP4 AIPS_PACRF_WP4_MASK | ||
| 1441 | #define AIPS_PACRF_SP4_MASK (0x4000U) | ||
| 1442 | #define AIPS_PACRF_SP4_SHIFT (14U) | ||
| 1443 | #define AIPS_PACRF_SP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK) | ||
| 1444 | #define AIPS_PACRF_SP4 AIPS_PACRF_SP4_MASK | ||
| 1445 | #define AIPS_PACRF_TP3_MASK (0x10000U) | ||
| 1446 | #define AIPS_PACRF_TP3_SHIFT (16U) | ||
| 1447 | #define AIPS_PACRF_TP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK) | ||
| 1448 | #define AIPS_PACRF_TP3 AIPS_PACRF_TP3_MASK | ||
| 1449 | #define AIPS_PACRF_WP3_MASK (0x20000U) | ||
| 1450 | #define AIPS_PACRF_WP3_SHIFT (17U) | ||
| 1451 | #define AIPS_PACRF_WP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK) | ||
| 1452 | #define AIPS_PACRF_WP3 AIPS_PACRF_WP3_MASK | ||
| 1453 | #define AIPS_PACRF_SP3_MASK (0x40000U) | ||
| 1454 | #define AIPS_PACRF_SP3_SHIFT (18U) | ||
| 1455 | #define AIPS_PACRF_SP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK) | ||
| 1456 | #define AIPS_PACRF_SP3 AIPS_PACRF_SP3_MASK | ||
| 1457 | #define AIPS_PACRF_TP2_MASK (0x100000U) | ||
| 1458 | #define AIPS_PACRF_TP2_SHIFT (20U) | ||
| 1459 | #define AIPS_PACRF_TP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK) | ||
| 1460 | #define AIPS_PACRF_TP2 AIPS_PACRF_TP2_MASK | ||
| 1461 | #define AIPS_PACRF_WP2_MASK (0x200000U) | ||
| 1462 | #define AIPS_PACRF_WP2_SHIFT (21U) | ||
| 1463 | #define AIPS_PACRF_WP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK) | ||
| 1464 | #define AIPS_PACRF_WP2 AIPS_PACRF_WP2_MASK | ||
| 1465 | #define AIPS_PACRF_SP2_MASK (0x400000U) | ||
| 1466 | #define AIPS_PACRF_SP2_SHIFT (22U) | ||
| 1467 | #define AIPS_PACRF_SP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK) | ||
| 1468 | #define AIPS_PACRF_SP2 AIPS_PACRF_SP2_MASK | ||
| 1469 | #define AIPS_PACRF_TP1_MASK (0x1000000U) | ||
| 1470 | #define AIPS_PACRF_TP1_SHIFT (24U) | ||
| 1471 | #define AIPS_PACRF_TP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK) | ||
| 1472 | #define AIPS_PACRF_TP1 AIPS_PACRF_TP1_MASK | ||
| 1473 | #define AIPS_PACRF_WP1_MASK (0x2000000U) | ||
| 1474 | #define AIPS_PACRF_WP1_SHIFT (25U) | ||
| 1475 | #define AIPS_PACRF_WP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK) | ||
| 1476 | #define AIPS_PACRF_WP1 AIPS_PACRF_WP1_MASK | ||
| 1477 | #define AIPS_PACRF_SP1_MASK (0x4000000U) | ||
| 1478 | #define AIPS_PACRF_SP1_SHIFT (26U) | ||
| 1479 | #define AIPS_PACRF_SP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK) | ||
| 1480 | #define AIPS_PACRF_SP1 AIPS_PACRF_SP1_MASK | ||
| 1481 | #define AIPS_PACRF_TP0_MASK (0x10000000U) | ||
| 1482 | #define AIPS_PACRF_TP0_SHIFT (28U) | ||
| 1483 | #define AIPS_PACRF_TP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK) | ||
| 1484 | #define AIPS_PACRF_TP0 AIPS_PACRF_TP0_MASK | ||
| 1485 | #define AIPS_PACRF_WP0_MASK (0x20000000U) | ||
| 1486 | #define AIPS_PACRF_WP0_SHIFT (29U) | ||
| 1487 | #define AIPS_PACRF_WP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK) | ||
| 1488 | #define AIPS_PACRF_WP0 AIPS_PACRF_WP0_MASK | ||
| 1489 | #define AIPS_PACRF_SP0_MASK (0x40000000U) | ||
| 1490 | #define AIPS_PACRF_SP0_SHIFT (30U) | ||
| 1491 | #define AIPS_PACRF_SP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK) | ||
| 1492 | #define AIPS_PACRF_SP0 AIPS_PACRF_SP0_MASK | ||
| 1493 | |||
| 1494 | /*! @name PACRG - Peripheral Access Control Register */ | ||
| 1495 | #define AIPS_PACRG_TP7_MASK (0x1U) | ||
| 1496 | #define AIPS_PACRG_TP7_SHIFT (0U) | ||
| 1497 | #define AIPS_PACRG_TP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK) | ||
| 1498 | #define AIPS_PACRG_TP7 AIPS_PACRG_TP7_MASK | ||
| 1499 | #define AIPS_PACRG_WP7_MASK (0x2U) | ||
| 1500 | #define AIPS_PACRG_WP7_SHIFT (1U) | ||
| 1501 | #define AIPS_PACRG_WP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK) | ||
| 1502 | #define AIPS_PACRG_WP7 AIPS_PACRG_WP7_MASK | ||
| 1503 | #define AIPS_PACRG_SP7_MASK (0x4U) | ||
| 1504 | #define AIPS_PACRG_SP7_SHIFT (2U) | ||
| 1505 | #define AIPS_PACRG_SP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK) | ||
| 1506 | #define AIPS_PACRG_SP7 AIPS_PACRG_SP7_MASK | ||
| 1507 | #define AIPS_PACRG_TP6_MASK (0x10U) | ||
| 1508 | #define AIPS_PACRG_TP6_SHIFT (4U) | ||
| 1509 | #define AIPS_PACRG_TP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK) | ||
| 1510 | #define AIPS_PACRG_TP6 AIPS_PACRG_TP6_MASK | ||
| 1511 | #define AIPS_PACRG_WP6_MASK (0x20U) | ||
| 1512 | #define AIPS_PACRG_WP6_SHIFT (5U) | ||
| 1513 | #define AIPS_PACRG_WP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK) | ||
| 1514 | #define AIPS_PACRG_WP6 AIPS_PACRG_WP6_MASK | ||
| 1515 | #define AIPS_PACRG_SP6_MASK (0x40U) | ||
| 1516 | #define AIPS_PACRG_SP6_SHIFT (6U) | ||
| 1517 | #define AIPS_PACRG_SP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK) | ||
| 1518 | #define AIPS_PACRG_SP6 AIPS_PACRG_SP6_MASK | ||
| 1519 | #define AIPS_PACRG_TP5_MASK (0x100U) | ||
| 1520 | #define AIPS_PACRG_TP5_SHIFT (8U) | ||
| 1521 | #define AIPS_PACRG_TP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK) | ||
| 1522 | #define AIPS_PACRG_TP5 AIPS_PACRG_TP5_MASK | ||
| 1523 | #define AIPS_PACRG_WP5_MASK (0x200U) | ||
| 1524 | #define AIPS_PACRG_WP5_SHIFT (9U) | ||
| 1525 | #define AIPS_PACRG_WP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK) | ||
| 1526 | #define AIPS_PACRG_WP5 AIPS_PACRG_WP5_MASK | ||
| 1527 | #define AIPS_PACRG_SP5_MASK (0x400U) | ||
| 1528 | #define AIPS_PACRG_SP5_SHIFT (10U) | ||
| 1529 | #define AIPS_PACRG_SP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK) | ||
| 1530 | #define AIPS_PACRG_SP5 AIPS_PACRG_SP5_MASK | ||
| 1531 | #define AIPS_PACRG_TP4_MASK (0x1000U) | ||
| 1532 | #define AIPS_PACRG_TP4_SHIFT (12U) | ||
| 1533 | #define AIPS_PACRG_TP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK) | ||
| 1534 | #define AIPS_PACRG_TP4 AIPS_PACRG_TP4_MASK | ||
| 1535 | #define AIPS_PACRG_WP4_MASK (0x2000U) | ||
| 1536 | #define AIPS_PACRG_WP4_SHIFT (13U) | ||
| 1537 | #define AIPS_PACRG_WP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK) | ||
| 1538 | #define AIPS_PACRG_WP4 AIPS_PACRG_WP4_MASK | ||
| 1539 | #define AIPS_PACRG_SP4_MASK (0x4000U) | ||
| 1540 | #define AIPS_PACRG_SP4_SHIFT (14U) | ||
| 1541 | #define AIPS_PACRG_SP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK) | ||
| 1542 | #define AIPS_PACRG_SP4 AIPS_PACRG_SP4_MASK | ||
| 1543 | #define AIPS_PACRG_TP3_MASK (0x10000U) | ||
| 1544 | #define AIPS_PACRG_TP3_SHIFT (16U) | ||
| 1545 | #define AIPS_PACRG_TP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK) | ||
| 1546 | #define AIPS_PACRG_TP3 AIPS_PACRG_TP3_MASK | ||
| 1547 | #define AIPS_PACRG_WP3_MASK (0x20000U) | ||
| 1548 | #define AIPS_PACRG_WP3_SHIFT (17U) | ||
| 1549 | #define AIPS_PACRG_WP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK) | ||
| 1550 | #define AIPS_PACRG_WP3 AIPS_PACRG_WP3_MASK | ||
| 1551 | #define AIPS_PACRG_SP3_MASK (0x40000U) | ||
| 1552 | #define AIPS_PACRG_SP3_SHIFT (18U) | ||
| 1553 | #define AIPS_PACRG_SP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK) | ||
| 1554 | #define AIPS_PACRG_SP3 AIPS_PACRG_SP3_MASK | ||
| 1555 | #define AIPS_PACRG_TP2_MASK (0x100000U) | ||
| 1556 | #define AIPS_PACRG_TP2_SHIFT (20U) | ||
| 1557 | #define AIPS_PACRG_TP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK) | ||
| 1558 | #define AIPS_PACRG_TP2 AIPS_PACRG_TP2_MASK | ||
| 1559 | #define AIPS_PACRG_WP2_MASK (0x200000U) | ||
| 1560 | #define AIPS_PACRG_WP2_SHIFT (21U) | ||
| 1561 | #define AIPS_PACRG_WP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK) | ||
| 1562 | #define AIPS_PACRG_WP2 AIPS_PACRG_WP2_MASK | ||
| 1563 | #define AIPS_PACRG_SP2_MASK (0x400000U) | ||
| 1564 | #define AIPS_PACRG_SP2_SHIFT (22U) | ||
| 1565 | #define AIPS_PACRG_SP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK) | ||
| 1566 | #define AIPS_PACRG_SP2 AIPS_PACRG_SP2_MASK | ||
| 1567 | #define AIPS_PACRG_TP1_MASK (0x1000000U) | ||
| 1568 | #define AIPS_PACRG_TP1_SHIFT (24U) | ||
| 1569 | #define AIPS_PACRG_TP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK) | ||
| 1570 | #define AIPS_PACRG_TP1 AIPS_PACRG_TP1_MASK | ||
| 1571 | #define AIPS_PACRG_WP1_MASK (0x2000000U) | ||
| 1572 | #define AIPS_PACRG_WP1_SHIFT (25U) | ||
| 1573 | #define AIPS_PACRG_WP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK) | ||
| 1574 | #define AIPS_PACRG_WP1 AIPS_PACRG_WP1_MASK | ||
| 1575 | #define AIPS_PACRG_SP1_MASK (0x4000000U) | ||
| 1576 | #define AIPS_PACRG_SP1_SHIFT (26U) | ||
| 1577 | #define AIPS_PACRG_SP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK) | ||
| 1578 | #define AIPS_PACRG_SP1 AIPS_PACRG_SP1_MASK | ||
| 1579 | #define AIPS_PACRG_TP0_MASK (0x10000000U) | ||
| 1580 | #define AIPS_PACRG_TP0_SHIFT (28U) | ||
| 1581 | #define AIPS_PACRG_TP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK) | ||
| 1582 | #define AIPS_PACRG_TP0 AIPS_PACRG_TP0_MASK | ||
| 1583 | #define AIPS_PACRG_WP0_MASK (0x20000000U) | ||
| 1584 | #define AIPS_PACRG_WP0_SHIFT (29U) | ||
| 1585 | #define AIPS_PACRG_WP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK) | ||
| 1586 | #define AIPS_PACRG_WP0 AIPS_PACRG_WP0_MASK | ||
| 1587 | #define AIPS_PACRG_SP0_MASK (0x40000000U) | ||
| 1588 | #define AIPS_PACRG_SP0_SHIFT (30U) | ||
| 1589 | #define AIPS_PACRG_SP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK) | ||
| 1590 | #define AIPS_PACRG_SP0 AIPS_PACRG_SP0_MASK | ||
| 1591 | |||
| 1592 | /*! @name PACRH - Peripheral Access Control Register */ | ||
| 1593 | #define AIPS_PACRH_TP7_MASK (0x1U) | ||
| 1594 | #define AIPS_PACRH_TP7_SHIFT (0U) | ||
| 1595 | #define AIPS_PACRH_TP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK) | ||
| 1596 | #define AIPS_PACRH_TP7 AIPS_PACRH_TP7_MASK | ||
| 1597 | #define AIPS_PACRH_WP7_MASK (0x2U) | ||
| 1598 | #define AIPS_PACRH_WP7_SHIFT (1U) | ||
| 1599 | #define AIPS_PACRH_WP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK) | ||
| 1600 | #define AIPS_PACRH_WP7 AIPS_PACRH_WP7_MASK | ||
| 1601 | #define AIPS_PACRH_SP7_MASK (0x4U) | ||
| 1602 | #define AIPS_PACRH_SP7_SHIFT (2U) | ||
| 1603 | #define AIPS_PACRH_SP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK) | ||
| 1604 | #define AIPS_PACRH_SP7 AIPS_PACRH_SP7_MASK | ||
| 1605 | #define AIPS_PACRH_TP6_MASK (0x10U) | ||
| 1606 | #define AIPS_PACRH_TP6_SHIFT (4U) | ||
| 1607 | #define AIPS_PACRH_TP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK) | ||
| 1608 | #define AIPS_PACRH_TP6 AIPS_PACRH_TP6_MASK | ||
| 1609 | #define AIPS_PACRH_WP6_MASK (0x20U) | ||
| 1610 | #define AIPS_PACRH_WP6_SHIFT (5U) | ||
| 1611 | #define AIPS_PACRH_WP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK) | ||
| 1612 | #define AIPS_PACRH_WP6 AIPS_PACRH_WP6_MASK | ||
| 1613 | #define AIPS_PACRH_SP6_MASK (0x40U) | ||
| 1614 | #define AIPS_PACRH_SP6_SHIFT (6U) | ||
| 1615 | #define AIPS_PACRH_SP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK) | ||
| 1616 | #define AIPS_PACRH_SP6 AIPS_PACRH_SP6_MASK | ||
| 1617 | #define AIPS_PACRH_TP5_MASK (0x100U) | ||
| 1618 | #define AIPS_PACRH_TP5_SHIFT (8U) | ||
| 1619 | #define AIPS_PACRH_TP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK) | ||
| 1620 | #define AIPS_PACRH_TP5 AIPS_PACRH_TP5_MASK | ||
| 1621 | #define AIPS_PACRH_WP5_MASK (0x200U) | ||
| 1622 | #define AIPS_PACRH_WP5_SHIFT (9U) | ||
| 1623 | #define AIPS_PACRH_WP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK) | ||
| 1624 | #define AIPS_PACRH_WP5 AIPS_PACRH_WP5_MASK | ||
| 1625 | #define AIPS_PACRH_SP5_MASK (0x400U) | ||
| 1626 | #define AIPS_PACRH_SP5_SHIFT (10U) | ||
| 1627 | #define AIPS_PACRH_SP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK) | ||
| 1628 | #define AIPS_PACRH_SP5 AIPS_PACRH_SP5_MASK | ||
| 1629 | #define AIPS_PACRH_TP4_MASK (0x1000U) | ||
| 1630 | #define AIPS_PACRH_TP4_SHIFT (12U) | ||
| 1631 | #define AIPS_PACRH_TP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK) | ||
| 1632 | #define AIPS_PACRH_TP4 AIPS_PACRH_TP4_MASK | ||
| 1633 | #define AIPS_PACRH_WP4_MASK (0x2000U) | ||
| 1634 | #define AIPS_PACRH_WP4_SHIFT (13U) | ||
| 1635 | #define AIPS_PACRH_WP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK) | ||
| 1636 | #define AIPS_PACRH_WP4 AIPS_PACRH_WP4_MASK | ||
| 1637 | #define AIPS_PACRH_SP4_MASK (0x4000U) | ||
| 1638 | #define AIPS_PACRH_SP4_SHIFT (14U) | ||
| 1639 | #define AIPS_PACRH_SP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK) | ||
| 1640 | #define AIPS_PACRH_SP4 AIPS_PACRH_SP4_MASK | ||
| 1641 | #define AIPS_PACRH_TP3_MASK (0x10000U) | ||
| 1642 | #define AIPS_PACRH_TP3_SHIFT (16U) | ||
| 1643 | #define AIPS_PACRH_TP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK) | ||
| 1644 | #define AIPS_PACRH_TP3 AIPS_PACRH_TP3_MASK | ||
| 1645 | #define AIPS_PACRH_WP3_MASK (0x20000U) | ||
| 1646 | #define AIPS_PACRH_WP3_SHIFT (17U) | ||
| 1647 | #define AIPS_PACRH_WP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK) | ||
| 1648 | #define AIPS_PACRH_WP3 AIPS_PACRH_WP3_MASK | ||
| 1649 | #define AIPS_PACRH_SP3_MASK (0x40000U) | ||
| 1650 | #define AIPS_PACRH_SP3_SHIFT (18U) | ||
| 1651 | #define AIPS_PACRH_SP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK) | ||
| 1652 | #define AIPS_PACRH_SP3 AIPS_PACRH_SP3_MASK | ||
| 1653 | #define AIPS_PACRH_TP2_MASK (0x100000U) | ||
| 1654 | #define AIPS_PACRH_TP2_SHIFT (20U) | ||
| 1655 | #define AIPS_PACRH_TP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK) | ||
| 1656 | #define AIPS_PACRH_TP2 AIPS_PACRH_TP2_MASK | ||
| 1657 | #define AIPS_PACRH_WP2_MASK (0x200000U) | ||
| 1658 | #define AIPS_PACRH_WP2_SHIFT (21U) | ||
| 1659 | #define AIPS_PACRH_WP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK) | ||
| 1660 | #define AIPS_PACRH_WP2 AIPS_PACRH_WP2_MASK | ||
| 1661 | #define AIPS_PACRH_SP2_MASK (0x400000U) | ||
| 1662 | #define AIPS_PACRH_SP2_SHIFT (22U) | ||
| 1663 | #define AIPS_PACRH_SP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK) | ||
| 1664 | #define AIPS_PACRH_SP2 AIPS_PACRH_SP2_MASK | ||
| 1665 | #define AIPS_PACRH_TP1_MASK (0x1000000U) | ||
| 1666 | #define AIPS_PACRH_TP1_SHIFT (24U) | ||
| 1667 | #define AIPS_PACRH_TP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK) | ||
| 1668 | #define AIPS_PACRH_TP1 AIPS_PACRH_TP1_MASK | ||
| 1669 | #define AIPS_PACRH_WP1_MASK (0x2000000U) | ||
| 1670 | #define AIPS_PACRH_WP1_SHIFT (25U) | ||
| 1671 | #define AIPS_PACRH_WP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK) | ||
| 1672 | #define AIPS_PACRH_WP1 AIPS_PACRH_WP1_MASK | ||
| 1673 | #define AIPS_PACRH_SP1_MASK (0x4000000U) | ||
| 1674 | #define AIPS_PACRH_SP1_SHIFT (26U) | ||
| 1675 | #define AIPS_PACRH_SP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK) | ||
| 1676 | #define AIPS_PACRH_SP1 AIPS_PACRH_SP1_MASK | ||
| 1677 | #define AIPS_PACRH_TP0_MASK (0x10000000U) | ||
| 1678 | #define AIPS_PACRH_TP0_SHIFT (28U) | ||
| 1679 | #define AIPS_PACRH_TP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK) | ||
| 1680 | #define AIPS_PACRH_TP0 AIPS_PACRH_TP0_MASK | ||
| 1681 | #define AIPS_PACRH_WP0_MASK (0x20000000U) | ||
| 1682 | #define AIPS_PACRH_WP0_SHIFT (29U) | ||
| 1683 | #define AIPS_PACRH_WP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK) | ||
| 1684 | #define AIPS_PACRH_WP0 AIPS_PACRH_WP0_MASK | ||
| 1685 | #define AIPS_PACRH_SP0_MASK (0x40000000U) | ||
| 1686 | #define AIPS_PACRH_SP0_SHIFT (30U) | ||
| 1687 | #define AIPS_PACRH_SP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK) | ||
| 1688 | #define AIPS_PACRH_SP0 AIPS_PACRH_SP0_MASK | ||
| 1689 | |||
| 1690 | /*! @name PACRI - Peripheral Access Control Register */ | ||
| 1691 | #define AIPS_PACRI_TP7_MASK (0x1U) | ||
| 1692 | #define AIPS_PACRI_TP7_SHIFT (0U) | ||
| 1693 | #define AIPS_PACRI_TP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK) | ||
| 1694 | #define AIPS_PACRI_TP7 AIPS_PACRI_TP7_MASK | ||
| 1695 | #define AIPS_PACRI_WP7_MASK (0x2U) | ||
| 1696 | #define AIPS_PACRI_WP7_SHIFT (1U) | ||
| 1697 | #define AIPS_PACRI_WP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK) | ||
| 1698 | #define AIPS_PACRI_WP7 AIPS_PACRI_WP7_MASK | ||
| 1699 | #define AIPS_PACRI_SP7_MASK (0x4U) | ||
| 1700 | #define AIPS_PACRI_SP7_SHIFT (2U) | ||
| 1701 | #define AIPS_PACRI_SP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK) | ||
| 1702 | #define AIPS_PACRI_SP7 AIPS_PACRI_SP7_MASK | ||
| 1703 | #define AIPS_PACRI_TP6_MASK (0x10U) | ||
| 1704 | #define AIPS_PACRI_TP6_SHIFT (4U) | ||
| 1705 | #define AIPS_PACRI_TP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK) | ||
| 1706 | #define AIPS_PACRI_TP6 AIPS_PACRI_TP6_MASK | ||
| 1707 | #define AIPS_PACRI_WP6_MASK (0x20U) | ||
| 1708 | #define AIPS_PACRI_WP6_SHIFT (5U) | ||
| 1709 | #define AIPS_PACRI_WP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK) | ||
| 1710 | #define AIPS_PACRI_WP6 AIPS_PACRI_WP6_MASK | ||
| 1711 | #define AIPS_PACRI_SP6_MASK (0x40U) | ||
| 1712 | #define AIPS_PACRI_SP6_SHIFT (6U) | ||
| 1713 | #define AIPS_PACRI_SP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK) | ||
| 1714 | #define AIPS_PACRI_SP6 AIPS_PACRI_SP6_MASK | ||
| 1715 | #define AIPS_PACRI_TP5_MASK (0x100U) | ||
| 1716 | #define AIPS_PACRI_TP5_SHIFT (8U) | ||
| 1717 | #define AIPS_PACRI_TP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK) | ||
| 1718 | #define AIPS_PACRI_TP5 AIPS_PACRI_TP5_MASK | ||
| 1719 | #define AIPS_PACRI_WP5_MASK (0x200U) | ||
| 1720 | #define AIPS_PACRI_WP5_SHIFT (9U) | ||
| 1721 | #define AIPS_PACRI_WP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK) | ||
| 1722 | #define AIPS_PACRI_WP5 AIPS_PACRI_WP5_MASK | ||
| 1723 | #define AIPS_PACRI_SP5_MASK (0x400U) | ||
| 1724 | #define AIPS_PACRI_SP5_SHIFT (10U) | ||
| 1725 | #define AIPS_PACRI_SP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK) | ||
| 1726 | #define AIPS_PACRI_SP5 AIPS_PACRI_SP5_MASK | ||
| 1727 | #define AIPS_PACRI_TP4_MASK (0x1000U) | ||
| 1728 | #define AIPS_PACRI_TP4_SHIFT (12U) | ||
| 1729 | #define AIPS_PACRI_TP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK) | ||
| 1730 | #define AIPS_PACRI_TP4 AIPS_PACRI_TP4_MASK | ||
| 1731 | #define AIPS_PACRI_WP4_MASK (0x2000U) | ||
| 1732 | #define AIPS_PACRI_WP4_SHIFT (13U) | ||
| 1733 | #define AIPS_PACRI_WP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK) | ||
| 1734 | #define AIPS_PACRI_WP4 AIPS_PACRI_WP4_MASK | ||
| 1735 | #define AIPS_PACRI_SP4_MASK (0x4000U) | ||
| 1736 | #define AIPS_PACRI_SP4_SHIFT (14U) | ||
| 1737 | #define AIPS_PACRI_SP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK) | ||
| 1738 | #define AIPS_PACRI_SP4 AIPS_PACRI_SP4_MASK | ||
| 1739 | #define AIPS_PACRI_TP3_MASK (0x10000U) | ||
| 1740 | #define AIPS_PACRI_TP3_SHIFT (16U) | ||
| 1741 | #define AIPS_PACRI_TP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK) | ||
| 1742 | #define AIPS_PACRI_TP3 AIPS_PACRI_TP3_MASK | ||
| 1743 | #define AIPS_PACRI_WP3_MASK (0x20000U) | ||
| 1744 | #define AIPS_PACRI_WP3_SHIFT (17U) | ||
| 1745 | #define AIPS_PACRI_WP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK) | ||
| 1746 | #define AIPS_PACRI_WP3 AIPS_PACRI_WP3_MASK | ||
| 1747 | #define AIPS_PACRI_SP3_MASK (0x40000U) | ||
| 1748 | #define AIPS_PACRI_SP3_SHIFT (18U) | ||
| 1749 | #define AIPS_PACRI_SP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK) | ||
| 1750 | #define AIPS_PACRI_SP3 AIPS_PACRI_SP3_MASK | ||
| 1751 | #define AIPS_PACRI_TP2_MASK (0x100000U) | ||
| 1752 | #define AIPS_PACRI_TP2_SHIFT (20U) | ||
| 1753 | #define AIPS_PACRI_TP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK) | ||
| 1754 | #define AIPS_PACRI_TP2 AIPS_PACRI_TP2_MASK | ||
| 1755 | #define AIPS_PACRI_WP2_MASK (0x200000U) | ||
| 1756 | #define AIPS_PACRI_WP2_SHIFT (21U) | ||
| 1757 | #define AIPS_PACRI_WP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK) | ||
| 1758 | #define AIPS_PACRI_WP2 AIPS_PACRI_WP2_MASK | ||
| 1759 | #define AIPS_PACRI_SP2_MASK (0x400000U) | ||
| 1760 | #define AIPS_PACRI_SP2_SHIFT (22U) | ||
| 1761 | #define AIPS_PACRI_SP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK) | ||
| 1762 | #define AIPS_PACRI_SP2 AIPS_PACRI_SP2_MASK | ||
| 1763 | #define AIPS_PACRI_TP1_MASK (0x1000000U) | ||
| 1764 | #define AIPS_PACRI_TP1_SHIFT (24U) | ||
| 1765 | #define AIPS_PACRI_TP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK) | ||
| 1766 | #define AIPS_PACRI_TP1 AIPS_PACRI_TP1_MASK | ||
| 1767 | #define AIPS_PACRI_WP1_MASK (0x2000000U) | ||
| 1768 | #define AIPS_PACRI_WP1_SHIFT (25U) | ||
| 1769 | #define AIPS_PACRI_WP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK) | ||
| 1770 | #define AIPS_PACRI_WP1 AIPS_PACRI_WP1_MASK | ||
| 1771 | #define AIPS_PACRI_SP1_MASK (0x4000000U) | ||
| 1772 | #define AIPS_PACRI_SP1_SHIFT (26U) | ||
| 1773 | #define AIPS_PACRI_SP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK) | ||
| 1774 | #define AIPS_PACRI_SP1 AIPS_PACRI_SP1_MASK | ||
| 1775 | #define AIPS_PACRI_TP0_MASK (0x10000000U) | ||
| 1776 | #define AIPS_PACRI_TP0_SHIFT (28U) | ||
| 1777 | #define AIPS_PACRI_TP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK) | ||
| 1778 | #define AIPS_PACRI_TP0 AIPS_PACRI_TP0_MASK | ||
| 1779 | #define AIPS_PACRI_WP0_MASK (0x20000000U) | ||
| 1780 | #define AIPS_PACRI_WP0_SHIFT (29U) | ||
| 1781 | #define AIPS_PACRI_WP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK) | ||
| 1782 | #define AIPS_PACRI_WP0 AIPS_PACRI_WP0_MASK | ||
| 1783 | #define AIPS_PACRI_SP0_MASK (0x40000000U) | ||
| 1784 | #define AIPS_PACRI_SP0_SHIFT (30U) | ||
| 1785 | #define AIPS_PACRI_SP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK) | ||
| 1786 | #define AIPS_PACRI_SP0 AIPS_PACRI_SP0_MASK | ||
| 1787 | |||
| 1788 | /*! @name PACRJ - Peripheral Access Control Register */ | ||
| 1789 | #define AIPS_PACRJ_TP7_MASK (0x1U) | ||
| 1790 | #define AIPS_PACRJ_TP7_SHIFT (0U) | ||
| 1791 | #define AIPS_PACRJ_TP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK) | ||
| 1792 | #define AIPS_PACRJ_TP7 AIPS_PACRJ_TP7_MASK | ||
| 1793 | #define AIPS_PACRJ_WP7_MASK (0x2U) | ||
| 1794 | #define AIPS_PACRJ_WP7_SHIFT (1U) | ||
| 1795 | #define AIPS_PACRJ_WP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK) | ||
| 1796 | #define AIPS_PACRJ_WP7 AIPS_PACRJ_WP7_MASK | ||
| 1797 | #define AIPS_PACRJ_SP7_MASK (0x4U) | ||
| 1798 | #define AIPS_PACRJ_SP7_SHIFT (2U) | ||
| 1799 | #define AIPS_PACRJ_SP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK) | ||
| 1800 | #define AIPS_PACRJ_SP7 AIPS_PACRJ_SP7_MASK | ||
| 1801 | #define AIPS_PACRJ_TP6_MASK (0x10U) | ||
| 1802 | #define AIPS_PACRJ_TP6_SHIFT (4U) | ||
| 1803 | #define AIPS_PACRJ_TP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK) | ||
| 1804 | #define AIPS_PACRJ_TP6 AIPS_PACRJ_TP6_MASK | ||
| 1805 | #define AIPS_PACRJ_WP6_MASK (0x20U) | ||
| 1806 | #define AIPS_PACRJ_WP6_SHIFT (5U) | ||
| 1807 | #define AIPS_PACRJ_WP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK) | ||
| 1808 | #define AIPS_PACRJ_WP6 AIPS_PACRJ_WP6_MASK | ||
| 1809 | #define AIPS_PACRJ_SP6_MASK (0x40U) | ||
| 1810 | #define AIPS_PACRJ_SP6_SHIFT (6U) | ||
| 1811 | #define AIPS_PACRJ_SP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK) | ||
| 1812 | #define AIPS_PACRJ_SP6 AIPS_PACRJ_SP6_MASK | ||
| 1813 | #define AIPS_PACRJ_TP5_MASK (0x100U) | ||
| 1814 | #define AIPS_PACRJ_TP5_SHIFT (8U) | ||
| 1815 | #define AIPS_PACRJ_TP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK) | ||
| 1816 | #define AIPS_PACRJ_TP5 AIPS_PACRJ_TP5_MASK | ||
| 1817 | #define AIPS_PACRJ_WP5_MASK (0x200U) | ||
| 1818 | #define AIPS_PACRJ_WP5_SHIFT (9U) | ||
| 1819 | #define AIPS_PACRJ_WP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK) | ||
| 1820 | #define AIPS_PACRJ_WP5 AIPS_PACRJ_WP5_MASK | ||
| 1821 | #define AIPS_PACRJ_SP5_MASK (0x400U) | ||
| 1822 | #define AIPS_PACRJ_SP5_SHIFT (10U) | ||
| 1823 | #define AIPS_PACRJ_SP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK) | ||
| 1824 | #define AIPS_PACRJ_SP5 AIPS_PACRJ_SP5_MASK | ||
| 1825 | #define AIPS_PACRJ_TP4_MASK (0x1000U) | ||
| 1826 | #define AIPS_PACRJ_TP4_SHIFT (12U) | ||
| 1827 | #define AIPS_PACRJ_TP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK) | ||
| 1828 | #define AIPS_PACRJ_TP4 AIPS_PACRJ_TP4_MASK | ||
| 1829 | #define AIPS_PACRJ_WP4_MASK (0x2000U) | ||
| 1830 | #define AIPS_PACRJ_WP4_SHIFT (13U) | ||
| 1831 | #define AIPS_PACRJ_WP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK) | ||
| 1832 | #define AIPS_PACRJ_WP4 AIPS_PACRJ_WP4_MASK | ||
| 1833 | #define AIPS_PACRJ_SP4_MASK (0x4000U) | ||
| 1834 | #define AIPS_PACRJ_SP4_SHIFT (14U) | ||
| 1835 | #define AIPS_PACRJ_SP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK) | ||
| 1836 | #define AIPS_PACRJ_SP4 AIPS_PACRJ_SP4_MASK | ||
| 1837 | #define AIPS_PACRJ_TP3_MASK (0x10000U) | ||
| 1838 | #define AIPS_PACRJ_TP3_SHIFT (16U) | ||
| 1839 | #define AIPS_PACRJ_TP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK) | ||
| 1840 | #define AIPS_PACRJ_TP3 AIPS_PACRJ_TP3_MASK | ||
| 1841 | #define AIPS_PACRJ_WP3_MASK (0x20000U) | ||
| 1842 | #define AIPS_PACRJ_WP3_SHIFT (17U) | ||
| 1843 | #define AIPS_PACRJ_WP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK) | ||
| 1844 | #define AIPS_PACRJ_WP3 AIPS_PACRJ_WP3_MASK | ||
| 1845 | #define AIPS_PACRJ_SP3_MASK (0x40000U) | ||
| 1846 | #define AIPS_PACRJ_SP3_SHIFT (18U) | ||
| 1847 | #define AIPS_PACRJ_SP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK) | ||
| 1848 | #define AIPS_PACRJ_SP3 AIPS_PACRJ_SP3_MASK | ||
| 1849 | #define AIPS_PACRJ_TP2_MASK (0x100000U) | ||
| 1850 | #define AIPS_PACRJ_TP2_SHIFT (20U) | ||
| 1851 | #define AIPS_PACRJ_TP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK) | ||
| 1852 | #define AIPS_PACRJ_TP2 AIPS_PACRJ_TP2_MASK | ||
| 1853 | #define AIPS_PACRJ_WP2_MASK (0x200000U) | ||
| 1854 | #define AIPS_PACRJ_WP2_SHIFT (21U) | ||
| 1855 | #define AIPS_PACRJ_WP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK) | ||
| 1856 | #define AIPS_PACRJ_WP2 AIPS_PACRJ_WP2_MASK | ||
| 1857 | #define AIPS_PACRJ_SP2_MASK (0x400000U) | ||
| 1858 | #define AIPS_PACRJ_SP2_SHIFT (22U) | ||
| 1859 | #define AIPS_PACRJ_SP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK) | ||
| 1860 | #define AIPS_PACRJ_SP2 AIPS_PACRJ_SP2_MASK | ||
| 1861 | #define AIPS_PACRJ_TP1_MASK (0x1000000U) | ||
| 1862 | #define AIPS_PACRJ_TP1_SHIFT (24U) | ||
| 1863 | #define AIPS_PACRJ_TP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK) | ||
| 1864 | #define AIPS_PACRJ_TP1 AIPS_PACRJ_TP1_MASK | ||
| 1865 | #define AIPS_PACRJ_WP1_MASK (0x2000000U) | ||
| 1866 | #define AIPS_PACRJ_WP1_SHIFT (25U) | ||
| 1867 | #define AIPS_PACRJ_WP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK) | ||
| 1868 | #define AIPS_PACRJ_WP1 AIPS_PACRJ_WP1_MASK | ||
| 1869 | #define AIPS_PACRJ_SP1_MASK (0x4000000U) | ||
| 1870 | #define AIPS_PACRJ_SP1_SHIFT (26U) | ||
| 1871 | #define AIPS_PACRJ_SP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK) | ||
| 1872 | #define AIPS_PACRJ_SP1 AIPS_PACRJ_SP1_MASK | ||
| 1873 | #define AIPS_PACRJ_TP0_MASK (0x10000000U) | ||
| 1874 | #define AIPS_PACRJ_TP0_SHIFT (28U) | ||
| 1875 | #define AIPS_PACRJ_TP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK) | ||
| 1876 | #define AIPS_PACRJ_TP0 AIPS_PACRJ_TP0_MASK | ||
| 1877 | #define AIPS_PACRJ_WP0_MASK (0x20000000U) | ||
| 1878 | #define AIPS_PACRJ_WP0_SHIFT (29U) | ||
| 1879 | #define AIPS_PACRJ_WP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK) | ||
| 1880 | #define AIPS_PACRJ_WP0 AIPS_PACRJ_WP0_MASK | ||
| 1881 | #define AIPS_PACRJ_SP0_MASK (0x40000000U) | ||
| 1882 | #define AIPS_PACRJ_SP0_SHIFT (30U) | ||
| 1883 | #define AIPS_PACRJ_SP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK) | ||
| 1884 | #define AIPS_PACRJ_SP0 AIPS_PACRJ_SP0_MASK | ||
| 1885 | |||
| 1886 | /*! @name PACRK - Peripheral Access Control Register */ | ||
| 1887 | #define AIPS_PACRK_TP7_MASK (0x1U) | ||
| 1888 | #define AIPS_PACRK_TP7_SHIFT (0U) | ||
| 1889 | #define AIPS_PACRK_TP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK) | ||
| 1890 | #define AIPS_PACRK_TP7 AIPS_PACRK_TP7_MASK | ||
| 1891 | #define AIPS_PACRK_WP7_MASK (0x2U) | ||
| 1892 | #define AIPS_PACRK_WP7_SHIFT (1U) | ||
| 1893 | #define AIPS_PACRK_WP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK) | ||
| 1894 | #define AIPS_PACRK_WP7 AIPS_PACRK_WP7_MASK | ||
| 1895 | #define AIPS_PACRK_SP7_MASK (0x4U) | ||
| 1896 | #define AIPS_PACRK_SP7_SHIFT (2U) | ||
| 1897 | #define AIPS_PACRK_SP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK) | ||
| 1898 | #define AIPS_PACRK_SP7 AIPS_PACRK_SP7_MASK | ||
| 1899 | #define AIPS_PACRK_TP6_MASK (0x10U) | ||
| 1900 | #define AIPS_PACRK_TP6_SHIFT (4U) | ||
| 1901 | #define AIPS_PACRK_TP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK) | ||
| 1902 | #define AIPS_PACRK_TP6 AIPS_PACRK_TP6_MASK | ||
| 1903 | #define AIPS_PACRK_WP6_MASK (0x20U) | ||
| 1904 | #define AIPS_PACRK_WP6_SHIFT (5U) | ||
| 1905 | #define AIPS_PACRK_WP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK) | ||
| 1906 | #define AIPS_PACRK_WP6 AIPS_PACRK_WP6_MASK | ||
| 1907 | #define AIPS_PACRK_SP6_MASK (0x40U) | ||
| 1908 | #define AIPS_PACRK_SP6_SHIFT (6U) | ||
| 1909 | #define AIPS_PACRK_SP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK) | ||
| 1910 | #define AIPS_PACRK_SP6 AIPS_PACRK_SP6_MASK | ||
| 1911 | #define AIPS_PACRK_TP5_MASK (0x100U) | ||
| 1912 | #define AIPS_PACRK_TP5_SHIFT (8U) | ||
| 1913 | #define AIPS_PACRK_TP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK) | ||
| 1914 | #define AIPS_PACRK_TP5 AIPS_PACRK_TP5_MASK | ||
| 1915 | #define AIPS_PACRK_WP5_MASK (0x200U) | ||
| 1916 | #define AIPS_PACRK_WP5_SHIFT (9U) | ||
| 1917 | #define AIPS_PACRK_WP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK) | ||
| 1918 | #define AIPS_PACRK_WP5 AIPS_PACRK_WP5_MASK | ||
| 1919 | #define AIPS_PACRK_SP5_MASK (0x400U) | ||
| 1920 | #define AIPS_PACRK_SP5_SHIFT (10U) | ||
| 1921 | #define AIPS_PACRK_SP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK) | ||
| 1922 | #define AIPS_PACRK_SP5 AIPS_PACRK_SP5_MASK | ||
| 1923 | #define AIPS_PACRK_TP4_MASK (0x1000U) | ||
| 1924 | #define AIPS_PACRK_TP4_SHIFT (12U) | ||
| 1925 | #define AIPS_PACRK_TP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK) | ||
| 1926 | #define AIPS_PACRK_TP4 AIPS_PACRK_TP4_MASK | ||
| 1927 | #define AIPS_PACRK_WP4_MASK (0x2000U) | ||
| 1928 | #define AIPS_PACRK_WP4_SHIFT (13U) | ||
| 1929 | #define AIPS_PACRK_WP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK) | ||
| 1930 | #define AIPS_PACRK_WP4 AIPS_PACRK_WP4_MASK | ||
| 1931 | #define AIPS_PACRK_SP4_MASK (0x4000U) | ||
| 1932 | #define AIPS_PACRK_SP4_SHIFT (14U) | ||
| 1933 | #define AIPS_PACRK_SP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK) | ||
| 1934 | #define AIPS_PACRK_SP4 AIPS_PACRK_SP4_MASK | ||
| 1935 | #define AIPS_PACRK_TP3_MASK (0x10000U) | ||
| 1936 | #define AIPS_PACRK_TP3_SHIFT (16U) | ||
| 1937 | #define AIPS_PACRK_TP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK) | ||
| 1938 | #define AIPS_PACRK_TP3 AIPS_PACRK_TP3_MASK | ||
| 1939 | #define AIPS_PACRK_WP3_MASK (0x20000U) | ||
| 1940 | #define AIPS_PACRK_WP3_SHIFT (17U) | ||
| 1941 | #define AIPS_PACRK_WP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK) | ||
| 1942 | #define AIPS_PACRK_WP3 AIPS_PACRK_WP3_MASK | ||
| 1943 | #define AIPS_PACRK_SP3_MASK (0x40000U) | ||
| 1944 | #define AIPS_PACRK_SP3_SHIFT (18U) | ||
| 1945 | #define AIPS_PACRK_SP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK) | ||
| 1946 | #define AIPS_PACRK_SP3 AIPS_PACRK_SP3_MASK | ||
| 1947 | #define AIPS_PACRK_TP2_MASK (0x100000U) | ||
| 1948 | #define AIPS_PACRK_TP2_SHIFT (20U) | ||
| 1949 | #define AIPS_PACRK_TP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK) | ||
| 1950 | #define AIPS_PACRK_TP2 AIPS_PACRK_TP2_MASK | ||
| 1951 | #define AIPS_PACRK_WP2_MASK (0x200000U) | ||
| 1952 | #define AIPS_PACRK_WP2_SHIFT (21U) | ||
| 1953 | #define AIPS_PACRK_WP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK) | ||
| 1954 | #define AIPS_PACRK_WP2 AIPS_PACRK_WP2_MASK | ||
| 1955 | #define AIPS_PACRK_SP2_MASK (0x400000U) | ||
| 1956 | #define AIPS_PACRK_SP2_SHIFT (22U) | ||
| 1957 | #define AIPS_PACRK_SP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK) | ||
| 1958 | #define AIPS_PACRK_SP2 AIPS_PACRK_SP2_MASK | ||
| 1959 | #define AIPS_PACRK_TP1_MASK (0x1000000U) | ||
| 1960 | #define AIPS_PACRK_TP1_SHIFT (24U) | ||
| 1961 | #define AIPS_PACRK_TP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK) | ||
| 1962 | #define AIPS_PACRK_TP1 AIPS_PACRK_TP1_MASK | ||
| 1963 | #define AIPS_PACRK_WP1_MASK (0x2000000U) | ||
| 1964 | #define AIPS_PACRK_WP1_SHIFT (25U) | ||
| 1965 | #define AIPS_PACRK_WP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK) | ||
| 1966 | #define AIPS_PACRK_WP1 AIPS_PACRK_WP1_MASK | ||
| 1967 | #define AIPS_PACRK_SP1_MASK (0x4000000U) | ||
| 1968 | #define AIPS_PACRK_SP1_SHIFT (26U) | ||
| 1969 | #define AIPS_PACRK_SP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK) | ||
| 1970 | #define AIPS_PACRK_SP1 AIPS_PACRK_SP1_MASK | ||
| 1971 | #define AIPS_PACRK_TP0_MASK (0x10000000U) | ||
| 1972 | #define AIPS_PACRK_TP0_SHIFT (28U) | ||
| 1973 | #define AIPS_PACRK_TP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK) | ||
| 1974 | #define AIPS_PACRK_TP0 AIPS_PACRK_TP0_MASK | ||
| 1975 | #define AIPS_PACRK_WP0_MASK (0x20000000U) | ||
| 1976 | #define AIPS_PACRK_WP0_SHIFT (29U) | ||
| 1977 | #define AIPS_PACRK_WP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK) | ||
| 1978 | #define AIPS_PACRK_WP0 AIPS_PACRK_WP0_MASK | ||
| 1979 | #define AIPS_PACRK_SP0_MASK (0x40000000U) | ||
| 1980 | #define AIPS_PACRK_SP0_SHIFT (30U) | ||
| 1981 | #define AIPS_PACRK_SP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK) | ||
| 1982 | #define AIPS_PACRK_SP0 AIPS_PACRK_SP0_MASK | ||
| 1983 | |||
| 1984 | /*! @name PACRL - Peripheral Access Control Register */ | ||
| 1985 | #define AIPS_PACRL_TP7_MASK (0x1U) | ||
| 1986 | #define AIPS_PACRL_TP7_SHIFT (0U) | ||
| 1987 | #define AIPS_PACRL_TP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK) | ||
| 1988 | #define AIPS_PACRL_TP7 AIPS_PACRL_TP7_MASK | ||
| 1989 | #define AIPS_PACRL_WP7_MASK (0x2U) | ||
| 1990 | #define AIPS_PACRL_WP7_SHIFT (1U) | ||
| 1991 | #define AIPS_PACRL_WP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK) | ||
| 1992 | #define AIPS_PACRL_WP7 AIPS_PACRL_WP7_MASK | ||
| 1993 | #define AIPS_PACRL_SP7_MASK (0x4U) | ||
| 1994 | #define AIPS_PACRL_SP7_SHIFT (2U) | ||
| 1995 | #define AIPS_PACRL_SP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK) | ||
| 1996 | #define AIPS_PACRL_SP7 AIPS_PACRL_SP7_MASK | ||
| 1997 | #define AIPS_PACRL_TP6_MASK (0x10U) | ||
| 1998 | #define AIPS_PACRL_TP6_SHIFT (4U) | ||
| 1999 | #define AIPS_PACRL_TP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK) | ||
| 2000 | #define AIPS_PACRL_TP6 AIPS_PACRL_TP6_MASK | ||
| 2001 | #define AIPS_PACRL_WP6_MASK (0x20U) | ||
| 2002 | #define AIPS_PACRL_WP6_SHIFT (5U) | ||
| 2003 | #define AIPS_PACRL_WP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK) | ||
| 2004 | #define AIPS_PACRL_WP6 AIPS_PACRL_WP6_MASK | ||
| 2005 | #define AIPS_PACRL_SP6_MASK (0x40U) | ||
| 2006 | #define AIPS_PACRL_SP6_SHIFT (6U) | ||
| 2007 | #define AIPS_PACRL_SP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK) | ||
| 2008 | #define AIPS_PACRL_SP6 AIPS_PACRL_SP6_MASK | ||
| 2009 | #define AIPS_PACRL_TP5_MASK (0x100U) | ||
| 2010 | #define AIPS_PACRL_TP5_SHIFT (8U) | ||
| 2011 | #define AIPS_PACRL_TP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK) | ||
| 2012 | #define AIPS_PACRL_TP5 AIPS_PACRL_TP5_MASK | ||
| 2013 | #define AIPS_PACRL_WP5_MASK (0x200U) | ||
| 2014 | #define AIPS_PACRL_WP5_SHIFT (9U) | ||
| 2015 | #define AIPS_PACRL_WP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK) | ||
| 2016 | #define AIPS_PACRL_WP5 AIPS_PACRL_WP5_MASK | ||
| 2017 | #define AIPS_PACRL_SP5_MASK (0x400U) | ||
| 2018 | #define AIPS_PACRL_SP5_SHIFT (10U) | ||
| 2019 | #define AIPS_PACRL_SP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK) | ||
| 2020 | #define AIPS_PACRL_SP5 AIPS_PACRL_SP5_MASK | ||
| 2021 | #define AIPS_PACRL_TP4_MASK (0x1000U) | ||
| 2022 | #define AIPS_PACRL_TP4_SHIFT (12U) | ||
| 2023 | #define AIPS_PACRL_TP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK) | ||
| 2024 | #define AIPS_PACRL_TP4 AIPS_PACRL_TP4_MASK | ||
| 2025 | #define AIPS_PACRL_WP4_MASK (0x2000U) | ||
| 2026 | #define AIPS_PACRL_WP4_SHIFT (13U) | ||
| 2027 | #define AIPS_PACRL_WP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK) | ||
| 2028 | #define AIPS_PACRL_WP4 AIPS_PACRL_WP4_MASK | ||
| 2029 | #define AIPS_PACRL_SP4_MASK (0x4000U) | ||
| 2030 | #define AIPS_PACRL_SP4_SHIFT (14U) | ||
| 2031 | #define AIPS_PACRL_SP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK) | ||
| 2032 | #define AIPS_PACRL_SP4 AIPS_PACRL_SP4_MASK | ||
| 2033 | #define AIPS_PACRL_TP3_MASK (0x10000U) | ||
| 2034 | #define AIPS_PACRL_TP3_SHIFT (16U) | ||
| 2035 | #define AIPS_PACRL_TP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK) | ||
| 2036 | #define AIPS_PACRL_TP3 AIPS_PACRL_TP3_MASK | ||
| 2037 | #define AIPS_PACRL_WP3_MASK (0x20000U) | ||
| 2038 | #define AIPS_PACRL_WP3_SHIFT (17U) | ||
| 2039 | #define AIPS_PACRL_WP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK) | ||
| 2040 | #define AIPS_PACRL_WP3 AIPS_PACRL_WP3_MASK | ||
| 2041 | #define AIPS_PACRL_SP3_MASK (0x40000U) | ||
| 2042 | #define AIPS_PACRL_SP3_SHIFT (18U) | ||
| 2043 | #define AIPS_PACRL_SP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK) | ||
| 2044 | #define AIPS_PACRL_SP3 AIPS_PACRL_SP3_MASK | ||
| 2045 | #define AIPS_PACRL_TP2_MASK (0x100000U) | ||
| 2046 | #define AIPS_PACRL_TP2_SHIFT (20U) | ||
| 2047 | #define AIPS_PACRL_TP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK) | ||
| 2048 | #define AIPS_PACRL_TP2 AIPS_PACRL_TP2_MASK | ||
| 2049 | #define AIPS_PACRL_WP2_MASK (0x200000U) | ||
| 2050 | #define AIPS_PACRL_WP2_SHIFT (21U) | ||
| 2051 | #define AIPS_PACRL_WP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK) | ||
| 2052 | #define AIPS_PACRL_WP2 AIPS_PACRL_WP2_MASK | ||
| 2053 | #define AIPS_PACRL_SP2_MASK (0x400000U) | ||
| 2054 | #define AIPS_PACRL_SP2_SHIFT (22U) | ||
| 2055 | #define AIPS_PACRL_SP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK) | ||
| 2056 | #define AIPS_PACRL_SP2 AIPS_PACRL_SP2_MASK | ||
| 2057 | #define AIPS_PACRL_TP1_MASK (0x1000000U) | ||
| 2058 | #define AIPS_PACRL_TP1_SHIFT (24U) | ||
| 2059 | #define AIPS_PACRL_TP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK) | ||
| 2060 | #define AIPS_PACRL_TP1 AIPS_PACRL_TP1_MASK | ||
| 2061 | #define AIPS_PACRL_WP1_MASK (0x2000000U) | ||
| 2062 | #define AIPS_PACRL_WP1_SHIFT (25U) | ||
| 2063 | #define AIPS_PACRL_WP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK) | ||
| 2064 | #define AIPS_PACRL_WP1 AIPS_PACRL_WP1_MASK | ||
| 2065 | #define AIPS_PACRL_SP1_MASK (0x4000000U) | ||
| 2066 | #define AIPS_PACRL_SP1_SHIFT (26U) | ||
| 2067 | #define AIPS_PACRL_SP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK) | ||
| 2068 | #define AIPS_PACRL_SP1 AIPS_PACRL_SP1_MASK | ||
| 2069 | #define AIPS_PACRL_TP0_MASK (0x10000000U) | ||
| 2070 | #define AIPS_PACRL_TP0_SHIFT (28U) | ||
| 2071 | #define AIPS_PACRL_TP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK) | ||
| 2072 | #define AIPS_PACRL_TP0 AIPS_PACRL_TP0_MASK | ||
| 2073 | #define AIPS_PACRL_WP0_MASK (0x20000000U) | ||
| 2074 | #define AIPS_PACRL_WP0_SHIFT (29U) | ||
| 2075 | #define AIPS_PACRL_WP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK) | ||
| 2076 | #define AIPS_PACRL_WP0 AIPS_PACRL_WP0_MASK | ||
| 2077 | #define AIPS_PACRL_SP0_MASK (0x40000000U) | ||
| 2078 | #define AIPS_PACRL_SP0_SHIFT (30U) | ||
| 2079 | #define AIPS_PACRL_SP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK) | ||
| 2080 | #define AIPS_PACRL_SP0 AIPS_PACRL_SP0_MASK | ||
| 2081 | |||
| 2082 | /*! @name PACRM - Peripheral Access Control Register */ | ||
| 2083 | #define AIPS_PACRM_TP7_MASK (0x1U) | ||
| 2084 | #define AIPS_PACRM_TP7_SHIFT (0U) | ||
| 2085 | #define AIPS_PACRM_TP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK) | ||
| 2086 | #define AIPS_PACRM_TP7 AIPS_PACRM_TP7_MASK | ||
| 2087 | #define AIPS_PACRM_WP7_MASK (0x2U) | ||
| 2088 | #define AIPS_PACRM_WP7_SHIFT (1U) | ||
| 2089 | #define AIPS_PACRM_WP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK) | ||
| 2090 | #define AIPS_PACRM_WP7 AIPS_PACRM_WP7_MASK | ||
| 2091 | #define AIPS_PACRM_SP7_MASK (0x4U) | ||
| 2092 | #define AIPS_PACRM_SP7_SHIFT (2U) | ||
| 2093 | #define AIPS_PACRM_SP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK) | ||
| 2094 | #define AIPS_PACRM_SP7 AIPS_PACRM_SP7_MASK | ||
| 2095 | #define AIPS_PACRM_TP6_MASK (0x10U) | ||
| 2096 | #define AIPS_PACRM_TP6_SHIFT (4U) | ||
| 2097 | #define AIPS_PACRM_TP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK) | ||
| 2098 | #define AIPS_PACRM_TP6 AIPS_PACRM_TP6_MASK | ||
| 2099 | #define AIPS_PACRM_WP6_MASK (0x20U) | ||
| 2100 | #define AIPS_PACRM_WP6_SHIFT (5U) | ||
| 2101 | #define AIPS_PACRM_WP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK) | ||
| 2102 | #define AIPS_PACRM_WP6 AIPS_PACRM_WP6_MASK | ||
| 2103 | #define AIPS_PACRM_SP6_MASK (0x40U) | ||
| 2104 | #define AIPS_PACRM_SP6_SHIFT (6U) | ||
| 2105 | #define AIPS_PACRM_SP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK) | ||
| 2106 | #define AIPS_PACRM_SP6 AIPS_PACRM_SP6_MASK | ||
| 2107 | #define AIPS_PACRM_TP5_MASK (0x100U) | ||
| 2108 | #define AIPS_PACRM_TP5_SHIFT (8U) | ||
| 2109 | #define AIPS_PACRM_TP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK) | ||
| 2110 | #define AIPS_PACRM_TP5 AIPS_PACRM_TP5_MASK | ||
| 2111 | #define AIPS_PACRM_WP5_MASK (0x200U) | ||
| 2112 | #define AIPS_PACRM_WP5_SHIFT (9U) | ||
| 2113 | #define AIPS_PACRM_WP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK) | ||
| 2114 | #define AIPS_PACRM_WP5 AIPS_PACRM_WP5_MASK | ||
| 2115 | #define AIPS_PACRM_SP5_MASK (0x400U) | ||
| 2116 | #define AIPS_PACRM_SP5_SHIFT (10U) | ||
| 2117 | #define AIPS_PACRM_SP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK) | ||
| 2118 | #define AIPS_PACRM_SP5 AIPS_PACRM_SP5_MASK | ||
| 2119 | #define AIPS_PACRM_TP4_MASK (0x1000U) | ||
| 2120 | #define AIPS_PACRM_TP4_SHIFT (12U) | ||
| 2121 | #define AIPS_PACRM_TP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK) | ||
| 2122 | #define AIPS_PACRM_TP4 AIPS_PACRM_TP4_MASK | ||
| 2123 | #define AIPS_PACRM_WP4_MASK (0x2000U) | ||
| 2124 | #define AIPS_PACRM_WP4_SHIFT (13U) | ||
| 2125 | #define AIPS_PACRM_WP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK) | ||
| 2126 | #define AIPS_PACRM_WP4 AIPS_PACRM_WP4_MASK | ||
| 2127 | #define AIPS_PACRM_SP4_MASK (0x4000U) | ||
| 2128 | #define AIPS_PACRM_SP4_SHIFT (14U) | ||
| 2129 | #define AIPS_PACRM_SP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK) | ||
| 2130 | #define AIPS_PACRM_SP4 AIPS_PACRM_SP4_MASK | ||
| 2131 | #define AIPS_PACRM_TP3_MASK (0x10000U) | ||
| 2132 | #define AIPS_PACRM_TP3_SHIFT (16U) | ||
| 2133 | #define AIPS_PACRM_TP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK) | ||
| 2134 | #define AIPS_PACRM_TP3 AIPS_PACRM_TP3_MASK | ||
| 2135 | #define AIPS_PACRM_WP3_MASK (0x20000U) | ||
| 2136 | #define AIPS_PACRM_WP3_SHIFT (17U) | ||
| 2137 | #define AIPS_PACRM_WP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK) | ||
| 2138 | #define AIPS_PACRM_WP3 AIPS_PACRM_WP3_MASK | ||
| 2139 | #define AIPS_PACRM_SP3_MASK (0x40000U) | ||
| 2140 | #define AIPS_PACRM_SP3_SHIFT (18U) | ||
| 2141 | #define AIPS_PACRM_SP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK) | ||
| 2142 | #define AIPS_PACRM_SP3 AIPS_PACRM_SP3_MASK | ||
| 2143 | #define AIPS_PACRM_TP2_MASK (0x100000U) | ||
| 2144 | #define AIPS_PACRM_TP2_SHIFT (20U) | ||
| 2145 | #define AIPS_PACRM_TP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK) | ||
| 2146 | #define AIPS_PACRM_TP2 AIPS_PACRM_TP2_MASK | ||
| 2147 | #define AIPS_PACRM_WP2_MASK (0x200000U) | ||
| 2148 | #define AIPS_PACRM_WP2_SHIFT (21U) | ||
| 2149 | #define AIPS_PACRM_WP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK) | ||
| 2150 | #define AIPS_PACRM_WP2 AIPS_PACRM_WP2_MASK | ||
| 2151 | #define AIPS_PACRM_SP2_MASK (0x400000U) | ||
| 2152 | #define AIPS_PACRM_SP2_SHIFT (22U) | ||
| 2153 | #define AIPS_PACRM_SP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK) | ||
| 2154 | #define AIPS_PACRM_SP2 AIPS_PACRM_SP2_MASK | ||
| 2155 | #define AIPS_PACRM_TP1_MASK (0x1000000U) | ||
| 2156 | #define AIPS_PACRM_TP1_SHIFT (24U) | ||
| 2157 | #define AIPS_PACRM_TP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK) | ||
| 2158 | #define AIPS_PACRM_TP1 AIPS_PACRM_TP1_MASK | ||
| 2159 | #define AIPS_PACRM_WP1_MASK (0x2000000U) | ||
| 2160 | #define AIPS_PACRM_WP1_SHIFT (25U) | ||
| 2161 | #define AIPS_PACRM_WP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK) | ||
| 2162 | #define AIPS_PACRM_WP1 AIPS_PACRM_WP1_MASK | ||
| 2163 | #define AIPS_PACRM_SP1_MASK (0x4000000U) | ||
| 2164 | #define AIPS_PACRM_SP1_SHIFT (26U) | ||
| 2165 | #define AIPS_PACRM_SP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK) | ||
| 2166 | #define AIPS_PACRM_SP1 AIPS_PACRM_SP1_MASK | ||
| 2167 | #define AIPS_PACRM_TP0_MASK (0x10000000U) | ||
| 2168 | #define AIPS_PACRM_TP0_SHIFT (28U) | ||
| 2169 | #define AIPS_PACRM_TP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK) | ||
| 2170 | #define AIPS_PACRM_TP0 AIPS_PACRM_TP0_MASK | ||
| 2171 | #define AIPS_PACRM_WP0_MASK (0x20000000U) | ||
| 2172 | #define AIPS_PACRM_WP0_SHIFT (29U) | ||
| 2173 | #define AIPS_PACRM_WP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK) | ||
| 2174 | #define AIPS_PACRM_WP0 AIPS_PACRM_WP0_MASK | ||
| 2175 | #define AIPS_PACRM_SP0_MASK (0x40000000U) | ||
| 2176 | #define AIPS_PACRM_SP0_SHIFT (30U) | ||
| 2177 | #define AIPS_PACRM_SP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK) | ||
| 2178 | #define AIPS_PACRM_SP0 AIPS_PACRM_SP0_MASK | ||
| 2179 | |||
| 2180 | /*! @name PACRN - Peripheral Access Control Register */ | ||
| 2181 | #define AIPS_PACRN_TP7_MASK (0x1U) | ||
| 2182 | #define AIPS_PACRN_TP7_SHIFT (0U) | ||
| 2183 | #define AIPS_PACRN_TP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK) | ||
| 2184 | #define AIPS_PACRN_TP7 AIPS_PACRN_TP7_MASK | ||
| 2185 | #define AIPS_PACRN_WP7_MASK (0x2U) | ||
| 2186 | #define AIPS_PACRN_WP7_SHIFT (1U) | ||
| 2187 | #define AIPS_PACRN_WP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK) | ||
| 2188 | #define AIPS_PACRN_WP7 AIPS_PACRN_WP7_MASK | ||
| 2189 | #define AIPS_PACRN_SP7_MASK (0x4U) | ||
| 2190 | #define AIPS_PACRN_SP7_SHIFT (2U) | ||
| 2191 | #define AIPS_PACRN_SP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK) | ||
| 2192 | #define AIPS_PACRN_SP7 AIPS_PACRN_SP7_MASK | ||
| 2193 | #define AIPS_PACRN_TP6_MASK (0x10U) | ||
| 2194 | #define AIPS_PACRN_TP6_SHIFT (4U) | ||
| 2195 | #define AIPS_PACRN_TP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK) | ||
| 2196 | #define AIPS_PACRN_TP6 AIPS_PACRN_TP6_MASK | ||
| 2197 | #define AIPS_PACRN_WP6_MASK (0x20U) | ||
| 2198 | #define AIPS_PACRN_WP6_SHIFT (5U) | ||
| 2199 | #define AIPS_PACRN_WP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK) | ||
| 2200 | #define AIPS_PACRN_WP6 AIPS_PACRN_WP6_MASK | ||
| 2201 | #define AIPS_PACRN_SP6_MASK (0x40U) | ||
| 2202 | #define AIPS_PACRN_SP6_SHIFT (6U) | ||
| 2203 | #define AIPS_PACRN_SP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK) | ||
| 2204 | #define AIPS_PACRN_SP6 AIPS_PACRN_SP6_MASK | ||
| 2205 | #define AIPS_PACRN_TP5_MASK (0x100U) | ||
| 2206 | #define AIPS_PACRN_TP5_SHIFT (8U) | ||
| 2207 | #define AIPS_PACRN_TP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK) | ||
| 2208 | #define AIPS_PACRN_TP5 AIPS_PACRN_TP5_MASK | ||
| 2209 | #define AIPS_PACRN_WP5_MASK (0x200U) | ||
| 2210 | #define AIPS_PACRN_WP5_SHIFT (9U) | ||
| 2211 | #define AIPS_PACRN_WP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK) | ||
| 2212 | #define AIPS_PACRN_WP5 AIPS_PACRN_WP5_MASK | ||
| 2213 | #define AIPS_PACRN_SP5_MASK (0x400U) | ||
| 2214 | #define AIPS_PACRN_SP5_SHIFT (10U) | ||
| 2215 | #define AIPS_PACRN_SP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK) | ||
| 2216 | #define AIPS_PACRN_SP5 AIPS_PACRN_SP5_MASK | ||
| 2217 | #define AIPS_PACRN_TP4_MASK (0x1000U) | ||
| 2218 | #define AIPS_PACRN_TP4_SHIFT (12U) | ||
| 2219 | #define AIPS_PACRN_TP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK) | ||
| 2220 | #define AIPS_PACRN_TP4 AIPS_PACRN_TP4_MASK | ||
| 2221 | #define AIPS_PACRN_WP4_MASK (0x2000U) | ||
| 2222 | #define AIPS_PACRN_WP4_SHIFT (13U) | ||
| 2223 | #define AIPS_PACRN_WP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK) | ||
| 2224 | #define AIPS_PACRN_WP4 AIPS_PACRN_WP4_MASK | ||
| 2225 | #define AIPS_PACRN_SP4_MASK (0x4000U) | ||
| 2226 | #define AIPS_PACRN_SP4_SHIFT (14U) | ||
| 2227 | #define AIPS_PACRN_SP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK) | ||
| 2228 | #define AIPS_PACRN_SP4 AIPS_PACRN_SP4_MASK | ||
| 2229 | #define AIPS_PACRN_TP3_MASK (0x10000U) | ||
| 2230 | #define AIPS_PACRN_TP3_SHIFT (16U) | ||
| 2231 | #define AIPS_PACRN_TP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK) | ||
| 2232 | #define AIPS_PACRN_TP3 AIPS_PACRN_TP3_MASK | ||
| 2233 | #define AIPS_PACRN_WP3_MASK (0x20000U) | ||
| 2234 | #define AIPS_PACRN_WP3_SHIFT (17U) | ||
| 2235 | #define AIPS_PACRN_WP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK) | ||
| 2236 | #define AIPS_PACRN_WP3 AIPS_PACRN_WP3_MASK | ||
| 2237 | #define AIPS_PACRN_SP3_MASK (0x40000U) | ||
| 2238 | #define AIPS_PACRN_SP3_SHIFT (18U) | ||
| 2239 | #define AIPS_PACRN_SP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK) | ||
| 2240 | #define AIPS_PACRN_SP3 AIPS_PACRN_SP3_MASK | ||
| 2241 | #define AIPS_PACRN_TP2_MASK (0x100000U) | ||
| 2242 | #define AIPS_PACRN_TP2_SHIFT (20U) | ||
| 2243 | #define AIPS_PACRN_TP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK) | ||
| 2244 | #define AIPS_PACRN_TP2 AIPS_PACRN_TP2_MASK | ||
| 2245 | #define AIPS_PACRN_WP2_MASK (0x200000U) | ||
| 2246 | #define AIPS_PACRN_WP2_SHIFT (21U) | ||
| 2247 | #define AIPS_PACRN_WP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK) | ||
| 2248 | #define AIPS_PACRN_WP2 AIPS_PACRN_WP2_MASK | ||
| 2249 | #define AIPS_PACRN_SP2_MASK (0x400000U) | ||
| 2250 | #define AIPS_PACRN_SP2_SHIFT (22U) | ||
| 2251 | #define AIPS_PACRN_SP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK) | ||
| 2252 | #define AIPS_PACRN_SP2 AIPS_PACRN_SP2_MASK | ||
| 2253 | #define AIPS_PACRN_TP1_MASK (0x1000000U) | ||
| 2254 | #define AIPS_PACRN_TP1_SHIFT (24U) | ||
| 2255 | #define AIPS_PACRN_TP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK) | ||
| 2256 | #define AIPS_PACRN_TP1 AIPS_PACRN_TP1_MASK | ||
| 2257 | #define AIPS_PACRN_WP1_MASK (0x2000000U) | ||
| 2258 | #define AIPS_PACRN_WP1_SHIFT (25U) | ||
| 2259 | #define AIPS_PACRN_WP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK) | ||
| 2260 | #define AIPS_PACRN_WP1 AIPS_PACRN_WP1_MASK | ||
| 2261 | #define AIPS_PACRN_SP1_MASK (0x4000000U) | ||
| 2262 | #define AIPS_PACRN_SP1_SHIFT (26U) | ||
| 2263 | #define AIPS_PACRN_SP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK) | ||
| 2264 | #define AIPS_PACRN_SP1 AIPS_PACRN_SP1_MASK | ||
| 2265 | #define AIPS_PACRN_TP0_MASK (0x10000000U) | ||
| 2266 | #define AIPS_PACRN_TP0_SHIFT (28U) | ||
| 2267 | #define AIPS_PACRN_TP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK) | ||
| 2268 | #define AIPS_PACRN_TP0 AIPS_PACRN_TP0_MASK | ||
| 2269 | #define AIPS_PACRN_WP0_MASK (0x20000000U) | ||
| 2270 | #define AIPS_PACRN_WP0_SHIFT (29U) | ||
| 2271 | #define AIPS_PACRN_WP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK) | ||
| 2272 | #define AIPS_PACRN_WP0 AIPS_PACRN_WP0_MASK | ||
| 2273 | #define AIPS_PACRN_SP0_MASK (0x40000000U) | ||
| 2274 | #define AIPS_PACRN_SP0_SHIFT (30U) | ||
| 2275 | #define AIPS_PACRN_SP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK) | ||
| 2276 | #define AIPS_PACRN_SP0 AIPS_PACRN_SP0_MASK | ||
| 2277 | |||
| 2278 | /*! @name PACRO - Peripheral Access Control Register */ | ||
| 2279 | #define AIPS_PACRO_TP7_MASK (0x1U) | ||
| 2280 | #define AIPS_PACRO_TP7_SHIFT (0U) | ||
| 2281 | #define AIPS_PACRO_TP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK) | ||
| 2282 | #define AIPS_PACRO_TP7 AIPS_PACRO_TP7_MASK | ||
| 2283 | #define AIPS_PACRO_WP7_MASK (0x2U) | ||
| 2284 | #define AIPS_PACRO_WP7_SHIFT (1U) | ||
| 2285 | #define AIPS_PACRO_WP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK) | ||
| 2286 | #define AIPS_PACRO_WP7 AIPS_PACRO_WP7_MASK | ||
| 2287 | #define AIPS_PACRO_SP7_MASK (0x4U) | ||
| 2288 | #define AIPS_PACRO_SP7_SHIFT (2U) | ||
| 2289 | #define AIPS_PACRO_SP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK) | ||
| 2290 | #define AIPS_PACRO_SP7 AIPS_PACRO_SP7_MASK | ||
| 2291 | #define AIPS_PACRO_TP6_MASK (0x10U) | ||
| 2292 | #define AIPS_PACRO_TP6_SHIFT (4U) | ||
| 2293 | #define AIPS_PACRO_TP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK) | ||
| 2294 | #define AIPS_PACRO_TP6 AIPS_PACRO_TP6_MASK | ||
| 2295 | #define AIPS_PACRO_WP6_MASK (0x20U) | ||
| 2296 | #define AIPS_PACRO_WP6_SHIFT (5U) | ||
| 2297 | #define AIPS_PACRO_WP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK) | ||
| 2298 | #define AIPS_PACRO_WP6 AIPS_PACRO_WP6_MASK | ||
| 2299 | #define AIPS_PACRO_SP6_MASK (0x40U) | ||
| 2300 | #define AIPS_PACRO_SP6_SHIFT (6U) | ||
| 2301 | #define AIPS_PACRO_SP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK) | ||
| 2302 | #define AIPS_PACRO_SP6 AIPS_PACRO_SP6_MASK | ||
| 2303 | #define AIPS_PACRO_TP5_MASK (0x100U) | ||
| 2304 | #define AIPS_PACRO_TP5_SHIFT (8U) | ||
| 2305 | #define AIPS_PACRO_TP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK) | ||
| 2306 | #define AIPS_PACRO_TP5 AIPS_PACRO_TP5_MASK | ||
| 2307 | #define AIPS_PACRO_WP5_MASK (0x200U) | ||
| 2308 | #define AIPS_PACRO_WP5_SHIFT (9U) | ||
| 2309 | #define AIPS_PACRO_WP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK) | ||
| 2310 | #define AIPS_PACRO_WP5 AIPS_PACRO_WP5_MASK | ||
| 2311 | #define AIPS_PACRO_SP5_MASK (0x400U) | ||
| 2312 | #define AIPS_PACRO_SP5_SHIFT (10U) | ||
| 2313 | #define AIPS_PACRO_SP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK) | ||
| 2314 | #define AIPS_PACRO_SP5 AIPS_PACRO_SP5_MASK | ||
| 2315 | #define AIPS_PACRO_TP4_MASK (0x1000U) | ||
| 2316 | #define AIPS_PACRO_TP4_SHIFT (12U) | ||
| 2317 | #define AIPS_PACRO_TP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK) | ||
| 2318 | #define AIPS_PACRO_TP4 AIPS_PACRO_TP4_MASK | ||
| 2319 | #define AIPS_PACRO_WP4_MASK (0x2000U) | ||
| 2320 | #define AIPS_PACRO_WP4_SHIFT (13U) | ||
| 2321 | #define AIPS_PACRO_WP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK) | ||
| 2322 | #define AIPS_PACRO_WP4 AIPS_PACRO_WP4_MASK | ||
| 2323 | #define AIPS_PACRO_SP4_MASK (0x4000U) | ||
| 2324 | #define AIPS_PACRO_SP4_SHIFT (14U) | ||
| 2325 | #define AIPS_PACRO_SP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK) | ||
| 2326 | #define AIPS_PACRO_SP4 AIPS_PACRO_SP4_MASK | ||
| 2327 | #define AIPS_PACRO_TP3_MASK (0x10000U) | ||
| 2328 | #define AIPS_PACRO_TP3_SHIFT (16U) | ||
| 2329 | #define AIPS_PACRO_TP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK) | ||
| 2330 | #define AIPS_PACRO_TP3 AIPS_PACRO_TP3_MASK | ||
| 2331 | #define AIPS_PACRO_WP3_MASK (0x20000U) | ||
| 2332 | #define AIPS_PACRO_WP3_SHIFT (17U) | ||
| 2333 | #define AIPS_PACRO_WP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK) | ||
| 2334 | #define AIPS_PACRO_WP3 AIPS_PACRO_WP3_MASK | ||
| 2335 | #define AIPS_PACRO_SP3_MASK (0x40000U) | ||
| 2336 | #define AIPS_PACRO_SP3_SHIFT (18U) | ||
| 2337 | #define AIPS_PACRO_SP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK) | ||
| 2338 | #define AIPS_PACRO_SP3 AIPS_PACRO_SP3_MASK | ||
| 2339 | #define AIPS_PACRO_TP2_MASK (0x100000U) | ||
| 2340 | #define AIPS_PACRO_TP2_SHIFT (20U) | ||
| 2341 | #define AIPS_PACRO_TP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK) | ||
| 2342 | #define AIPS_PACRO_TP2 AIPS_PACRO_TP2_MASK | ||
| 2343 | #define AIPS_PACRO_WP2_MASK (0x200000U) | ||
| 2344 | #define AIPS_PACRO_WP2_SHIFT (21U) | ||
| 2345 | #define AIPS_PACRO_WP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK) | ||
| 2346 | #define AIPS_PACRO_WP2 AIPS_PACRO_WP2_MASK | ||
| 2347 | #define AIPS_PACRO_SP2_MASK (0x400000U) | ||
| 2348 | #define AIPS_PACRO_SP2_SHIFT (22U) | ||
| 2349 | #define AIPS_PACRO_SP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK) | ||
| 2350 | #define AIPS_PACRO_SP2 AIPS_PACRO_SP2_MASK | ||
| 2351 | #define AIPS_PACRO_TP1_MASK (0x1000000U) | ||
| 2352 | #define AIPS_PACRO_TP1_SHIFT (24U) | ||
| 2353 | #define AIPS_PACRO_TP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK) | ||
| 2354 | #define AIPS_PACRO_TP1 AIPS_PACRO_TP1_MASK | ||
| 2355 | #define AIPS_PACRO_WP1_MASK (0x2000000U) | ||
| 2356 | #define AIPS_PACRO_WP1_SHIFT (25U) | ||
| 2357 | #define AIPS_PACRO_WP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK) | ||
| 2358 | #define AIPS_PACRO_WP1 AIPS_PACRO_WP1_MASK | ||
| 2359 | #define AIPS_PACRO_SP1_MASK (0x4000000U) | ||
| 2360 | #define AIPS_PACRO_SP1_SHIFT (26U) | ||
| 2361 | #define AIPS_PACRO_SP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK) | ||
| 2362 | #define AIPS_PACRO_SP1 AIPS_PACRO_SP1_MASK | ||
| 2363 | #define AIPS_PACRO_TP0_MASK (0x10000000U) | ||
| 2364 | #define AIPS_PACRO_TP0_SHIFT (28U) | ||
| 2365 | #define AIPS_PACRO_TP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK) | ||
| 2366 | #define AIPS_PACRO_TP0 AIPS_PACRO_TP0_MASK | ||
| 2367 | #define AIPS_PACRO_WP0_MASK (0x20000000U) | ||
| 2368 | #define AIPS_PACRO_WP0_SHIFT (29U) | ||
| 2369 | #define AIPS_PACRO_WP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK) | ||
| 2370 | #define AIPS_PACRO_WP0 AIPS_PACRO_WP0_MASK | ||
| 2371 | #define AIPS_PACRO_SP0_MASK (0x40000000U) | ||
| 2372 | #define AIPS_PACRO_SP0_SHIFT (30U) | ||
| 2373 | #define AIPS_PACRO_SP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK) | ||
| 2374 | #define AIPS_PACRO_SP0 AIPS_PACRO_SP0_MASK | ||
| 2375 | |||
| 2376 | /*! @name PACRP - Peripheral Access Control Register */ | ||
| 2377 | #define AIPS_PACRP_TP7_MASK (0x1U) | ||
| 2378 | #define AIPS_PACRP_TP7_SHIFT (0U) | ||
| 2379 | #define AIPS_PACRP_TP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK) | ||
| 2380 | #define AIPS_PACRP_TP7 AIPS_PACRP_TP7_MASK | ||
| 2381 | #define AIPS_PACRP_WP7_MASK (0x2U) | ||
| 2382 | #define AIPS_PACRP_WP7_SHIFT (1U) | ||
| 2383 | #define AIPS_PACRP_WP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK) | ||
| 2384 | #define AIPS_PACRP_WP7 AIPS_PACRP_WP7_MASK | ||
| 2385 | #define AIPS_PACRP_SP7_MASK (0x4U) | ||
| 2386 | #define AIPS_PACRP_SP7_SHIFT (2U) | ||
| 2387 | #define AIPS_PACRP_SP7_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK) | ||
| 2388 | #define AIPS_PACRP_SP7 AIPS_PACRP_SP7_MASK | ||
| 2389 | #define AIPS_PACRP_TP6_MASK (0x10U) | ||
| 2390 | #define AIPS_PACRP_TP6_SHIFT (4U) | ||
| 2391 | #define AIPS_PACRP_TP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK) | ||
| 2392 | #define AIPS_PACRP_TP6 AIPS_PACRP_TP6_MASK | ||
| 2393 | #define AIPS_PACRP_WP6_MASK (0x20U) | ||
| 2394 | #define AIPS_PACRP_WP6_SHIFT (5U) | ||
| 2395 | #define AIPS_PACRP_WP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK) | ||
| 2396 | #define AIPS_PACRP_WP6 AIPS_PACRP_WP6_MASK | ||
| 2397 | #define AIPS_PACRP_SP6_MASK (0x40U) | ||
| 2398 | #define AIPS_PACRP_SP6_SHIFT (6U) | ||
| 2399 | #define AIPS_PACRP_SP6_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK) | ||
| 2400 | #define AIPS_PACRP_SP6 AIPS_PACRP_SP6_MASK | ||
| 2401 | #define AIPS_PACRP_TP5_MASK (0x100U) | ||
| 2402 | #define AIPS_PACRP_TP5_SHIFT (8U) | ||
| 2403 | #define AIPS_PACRP_TP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK) | ||
| 2404 | #define AIPS_PACRP_TP5 AIPS_PACRP_TP5_MASK | ||
| 2405 | #define AIPS_PACRP_WP5_MASK (0x200U) | ||
| 2406 | #define AIPS_PACRP_WP5_SHIFT (9U) | ||
| 2407 | #define AIPS_PACRP_WP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK) | ||
| 2408 | #define AIPS_PACRP_WP5 AIPS_PACRP_WP5_MASK | ||
| 2409 | #define AIPS_PACRP_SP5_MASK (0x400U) | ||
| 2410 | #define AIPS_PACRP_SP5_SHIFT (10U) | ||
| 2411 | #define AIPS_PACRP_SP5_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK) | ||
| 2412 | #define AIPS_PACRP_SP5 AIPS_PACRP_SP5_MASK | ||
| 2413 | #define AIPS_PACRP_TP4_MASK (0x1000U) | ||
| 2414 | #define AIPS_PACRP_TP4_SHIFT (12U) | ||
| 2415 | #define AIPS_PACRP_TP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK) | ||
| 2416 | #define AIPS_PACRP_TP4 AIPS_PACRP_TP4_MASK | ||
| 2417 | #define AIPS_PACRP_WP4_MASK (0x2000U) | ||
| 2418 | #define AIPS_PACRP_WP4_SHIFT (13U) | ||
| 2419 | #define AIPS_PACRP_WP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK) | ||
| 2420 | #define AIPS_PACRP_WP4 AIPS_PACRP_WP4_MASK | ||
| 2421 | #define AIPS_PACRP_SP4_MASK (0x4000U) | ||
| 2422 | #define AIPS_PACRP_SP4_SHIFT (14U) | ||
| 2423 | #define AIPS_PACRP_SP4_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK) | ||
| 2424 | #define AIPS_PACRP_SP4 AIPS_PACRP_SP4_MASK | ||
| 2425 | #define AIPS_PACRP_TP3_MASK (0x10000U) | ||
| 2426 | #define AIPS_PACRP_TP3_SHIFT (16U) | ||
| 2427 | #define AIPS_PACRP_TP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK) | ||
| 2428 | #define AIPS_PACRP_TP3 AIPS_PACRP_TP3_MASK | ||
| 2429 | #define AIPS_PACRP_WP3_MASK (0x20000U) | ||
| 2430 | #define AIPS_PACRP_WP3_SHIFT (17U) | ||
| 2431 | #define AIPS_PACRP_WP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK) | ||
| 2432 | #define AIPS_PACRP_WP3 AIPS_PACRP_WP3_MASK | ||
| 2433 | #define AIPS_PACRP_SP3_MASK (0x40000U) | ||
| 2434 | #define AIPS_PACRP_SP3_SHIFT (18U) | ||
| 2435 | #define AIPS_PACRP_SP3_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK) | ||
| 2436 | #define AIPS_PACRP_SP3 AIPS_PACRP_SP3_MASK | ||
| 2437 | #define AIPS_PACRP_TP2_MASK (0x100000U) | ||
| 2438 | #define AIPS_PACRP_TP2_SHIFT (20U) | ||
| 2439 | #define AIPS_PACRP_TP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK) | ||
| 2440 | #define AIPS_PACRP_TP2 AIPS_PACRP_TP2_MASK | ||
| 2441 | #define AIPS_PACRP_WP2_MASK (0x200000U) | ||
| 2442 | #define AIPS_PACRP_WP2_SHIFT (21U) | ||
| 2443 | #define AIPS_PACRP_WP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK) | ||
| 2444 | #define AIPS_PACRP_WP2 AIPS_PACRP_WP2_MASK | ||
| 2445 | #define AIPS_PACRP_SP2_MASK (0x400000U) | ||
| 2446 | #define AIPS_PACRP_SP2_SHIFT (22U) | ||
| 2447 | #define AIPS_PACRP_SP2_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK) | ||
| 2448 | #define AIPS_PACRP_SP2 AIPS_PACRP_SP2_MASK | ||
| 2449 | #define AIPS_PACRP_TP1_MASK (0x1000000U) | ||
| 2450 | #define AIPS_PACRP_TP1_SHIFT (24U) | ||
| 2451 | #define AIPS_PACRP_TP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK) | ||
| 2452 | #define AIPS_PACRP_TP1 AIPS_PACRP_TP1_MASK | ||
| 2453 | #define AIPS_PACRP_WP1_MASK (0x2000000U) | ||
| 2454 | #define AIPS_PACRP_WP1_SHIFT (25U) | ||
| 2455 | #define AIPS_PACRP_WP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK) | ||
| 2456 | #define AIPS_PACRP_WP1 AIPS_PACRP_WP1_MASK | ||
| 2457 | #define AIPS_PACRP_SP1_MASK (0x4000000U) | ||
| 2458 | #define AIPS_PACRP_SP1_SHIFT (26U) | ||
| 2459 | #define AIPS_PACRP_SP1_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK) | ||
| 2460 | #define AIPS_PACRP_SP1 AIPS_PACRP_SP1_MASK | ||
| 2461 | #define AIPS_PACRP_TP0_MASK (0x10000000U) | ||
| 2462 | #define AIPS_PACRP_TP0_SHIFT (28U) | ||
| 2463 | #define AIPS_PACRP_TP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK) | ||
| 2464 | #define AIPS_PACRP_TP0 AIPS_PACRP_TP0_MASK | ||
| 2465 | #define AIPS_PACRP_WP0_MASK (0x20000000U) | ||
| 2466 | #define AIPS_PACRP_WP0_SHIFT (29U) | ||
| 2467 | #define AIPS_PACRP_WP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK) | ||
| 2468 | #define AIPS_PACRP_WP0 AIPS_PACRP_WP0_MASK | ||
| 2469 | #define AIPS_PACRP_SP0_MASK (0x40000000U) | ||
| 2470 | #define AIPS_PACRP_SP0_SHIFT (30U) | ||
| 2471 | #define AIPS_PACRP_SP0_SET(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK) | ||
| 2472 | #define AIPS_PACRP_SP0 AIPS_PACRP_SP0_MASK | ||
| 2473 | |||
| 2474 | |||
| 2475 | /*! | ||
| 2476 | * @} | ||
| 2477 | */ /* end of group AIPS_Register_Masks */ | ||
| 2478 | |||
| 2479 | |||
| 2480 | /* AIPS - Peripheral instance base addresses */ | ||
| 2481 | /** Peripheral AIPS0 base address */ | ||
| 2482 | #define AIPS0_BASE (0x40000000u) | ||
| 2483 | /** Peripheral AIPS0 base pointer */ | ||
| 2484 | #define AIPS0 ((AIPS_TypeDef *)AIPS0_BASE) | ||
| 2485 | /** Peripheral AIPS1 base address */ | ||
| 2486 | #define AIPS1_BASE (0x40080000u) | ||
| 2487 | /** Peripheral AIPS1 base pointer */ | ||
| 2488 | #define AIPS1 ((AIPS_TypeDef *)AIPS1_BASE) | ||
| 2489 | /** Array initializer of AIPS peripheral base addresses */ | ||
| 2490 | #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE } | ||
| 2491 | /** Array initializer of AIPS peripheral base pointers */ | ||
| 2492 | #define AIPS_BASE_PTRS { AIPS0, AIPS1 } | ||
| 2493 | |||
| 2494 | /*! | ||
| 2495 | * @} | ||
| 2496 | */ /* end of group AIPS_Peripheral_Access_Layer */ | ||
| 2497 | |||
| 2498 | |||
| 2499 | /* ---------------------------------------------------------------------------- | ||
| 2500 | -- AXBS Peripheral Access Layer | ||
| 2501 | ---------------------------------------------------------------------------- */ | ||
| 2502 | |||
| 2503 | /*! | ||
| 2504 | * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer | ||
| 2505 | * @{ | ||
| 2506 | */ | ||
| 2507 | |||
| 2508 | /** AXBS - Register Layout Typedef */ | ||
| 2509 | typedef struct { | ||
| 2510 | struct { /* offset: 0x0, array step: 0x100 */ | ||
| 2511 | __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */ | ||
| 2512 | uint8_t RESERVED_0[12]; | ||
| 2513 | __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */ | ||
| 2514 | uint8_t RESERVED_1[236]; | ||
| 2515 | } SLAVE[5]; | ||
| 2516 | uint8_t RESERVED_0[768]; | ||
| 2517 | __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ | ||
| 2518 | uint8_t RESERVED_1[252]; | ||
| 2519 | __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ | ||
| 2520 | uint8_t RESERVED_2[252]; | ||
| 2521 | __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ | ||
| 2522 | uint8_t RESERVED_3[252]; | ||
| 2523 | __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */ | ||
| 2524 | uint8_t RESERVED_4[252]; | ||
| 2525 | __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ | ||
| 2526 | uint8_t RESERVED_5[252]; | ||
| 2527 | __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ | ||
| 2528 | uint8_t RESERVED_6[252]; | ||
| 2529 | __IO uint32_t MGPCR6; /**< Master General Purpose Control Register, offset: 0xE00 */ | ||
| 2530 | } AXBS_TypeDef; | ||
| 2531 | |||
| 2532 | /* ---------------------------------------------------------------------------- | ||
| 2533 | -- AXBS Register Masks | ||
| 2534 | ---------------------------------------------------------------------------- */ | ||
| 2535 | |||
| 2536 | /*! | ||
| 2537 | * @addtogroup AXBS_Register_Masks AXBS Register Masks | ||
| 2538 | * @{ | ||
| 2539 | */ | ||
| 2540 | |||
| 2541 | /*! @name PRS - Priority Registers Slave */ | ||
| 2542 | #define AXBS_PRS_M0_MASK (0x7U) | ||
| 2543 | #define AXBS_PRS_M0_SHIFT (0U) | ||
| 2544 | #define AXBS_PRS_M0_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK) | ||
| 2545 | #define AXBS_PRS_M0 AXBS_PRS_M0_MASK | ||
| 2546 | #define AXBS_PRS_M1_MASK (0x70U) | ||
| 2547 | #define AXBS_PRS_M1_SHIFT (4U) | ||
| 2548 | #define AXBS_PRS_M1_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK) | ||
| 2549 | #define AXBS_PRS_M1 AXBS_PRS_M1_MASK | ||
| 2550 | #define AXBS_PRS_M2_MASK (0x700U) | ||
| 2551 | #define AXBS_PRS_M2_SHIFT (8U) | ||
| 2552 | #define AXBS_PRS_M2_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK) | ||
| 2553 | #define AXBS_PRS_M2 AXBS_PRS_M2_MASK | ||
| 2554 | #define AXBS_PRS_M3_MASK (0x7000U) | ||
| 2555 | #define AXBS_PRS_M3_SHIFT (12U) | ||
| 2556 | #define AXBS_PRS_M3_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK) | ||
| 2557 | #define AXBS_PRS_M3 AXBS_PRS_M3_MASK | ||
| 2558 | #define AXBS_PRS_M4_MASK (0x70000U) | ||
| 2559 | #define AXBS_PRS_M4_SHIFT (16U) | ||
| 2560 | #define AXBS_PRS_M4_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK) | ||
| 2561 | #define AXBS_PRS_M4 AXBS_PRS_M4_MASK | ||
| 2562 | #define AXBS_PRS_M5_MASK (0x700000U) | ||
| 2563 | #define AXBS_PRS_M5_SHIFT (20U) | ||
| 2564 | #define AXBS_PRS_M5_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK) | ||
| 2565 | #define AXBS_PRS_M5 AXBS_PRS_M5_MASK | ||
| 2566 | #define AXBS_PRS_M6_MASK (0x7000000U) | ||
| 2567 | #define AXBS_PRS_M6_SHIFT (24U) | ||
| 2568 | #define AXBS_PRS_M6_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M6_SHIFT)) & AXBS_PRS_M6_MASK) | ||
| 2569 | #define AXBS_PRS_M6 AXBS_PRS_M6_MASK | ||
| 2570 | |||
| 2571 | /* The count of AXBS_PRS */ | ||
| 2572 | #define AXBS_PRS_COUNT (5U) | ||
| 2573 | |||
| 2574 | /*! @name CRS - Control Register */ | ||
| 2575 | #define AXBS_CRS_PARK_MASK (0x7U) | ||
| 2576 | #define AXBS_CRS_PARK_SHIFT (0U) | ||
| 2577 | #define AXBS_CRS_PARK_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK) | ||
| 2578 | #define AXBS_CRS_PARK AXBS_CRS_PARK_MASK | ||
| 2579 | #define AXBS_CRS_PCTL_MASK (0x30U) | ||
| 2580 | #define AXBS_CRS_PCTL_SHIFT (4U) | ||
| 2581 | #define AXBS_CRS_PCTL_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK) | ||
| 2582 | #define AXBS_CRS_PCTL AXBS_CRS_PCTL_MASK | ||
| 2583 | #define AXBS_CRS_ARB_MASK (0x300U) | ||
| 2584 | #define AXBS_CRS_ARB_SHIFT (8U) | ||
| 2585 | #define AXBS_CRS_ARB_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK) | ||
| 2586 | #define AXBS_CRS_ARB AXBS_CRS_ARB_MASK | ||
| 2587 | #define AXBS_CRS_HLP_MASK (0x40000000U) | ||
| 2588 | #define AXBS_CRS_HLP_SHIFT (30U) | ||
| 2589 | #define AXBS_CRS_HLP_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK) | ||
| 2590 | #define AXBS_CRS_HLP AXBS_CRS_HLP_MASK | ||
| 2591 | #define AXBS_CRS_RO_MASK (0x80000000U) | ||
| 2592 | #define AXBS_CRS_RO_SHIFT (31U) | ||
| 2593 | #define AXBS_CRS_RO_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK) | ||
| 2594 | #define AXBS_CRS_RO AXBS_CRS_RO_MASK | ||
| 2595 | |||
| 2596 | /* The count of AXBS_CRS */ | ||
| 2597 | #define AXBS_CRS_COUNT (5U) | ||
| 2598 | |||
| 2599 | /*! @name MGPCR0 - Master General Purpose Control Register */ | ||
| 2600 | #define AXBS_MGPCR0_AULB_MASK (0x7U) | ||
| 2601 | #define AXBS_MGPCR0_AULB_SHIFT (0U) | ||
| 2602 | #define AXBS_MGPCR0_AULB_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK) | ||
| 2603 | #define AXBS_MGPCR0_AULB AXBS_MGPCR0_AULB_MASK | ||
| 2604 | |||
| 2605 | /*! @name MGPCR1 - Master General Purpose Control Register */ | ||
| 2606 | #define AXBS_MGPCR1_AULB_MASK (0x7U) | ||
| 2607 | #define AXBS_MGPCR1_AULB_SHIFT (0U) | ||
| 2608 | #define AXBS_MGPCR1_AULB_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK) | ||
| 2609 | #define AXBS_MGPCR1_AULB AXBS_MGPCR1_AULB_MASK | ||
| 2610 | |||
| 2611 | /*! @name MGPCR2 - Master General Purpose Control Register */ | ||
| 2612 | #define AXBS_MGPCR2_AULB_MASK (0x7U) | ||
| 2613 | #define AXBS_MGPCR2_AULB_SHIFT (0U) | ||
| 2614 | #define AXBS_MGPCR2_AULB_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK) | ||
| 2615 | #define AXBS_MGPCR2_AULB AXBS_MGPCR2_AULB_MASK | ||
| 2616 | |||
| 2617 | /*! @name MGPCR3 - Master General Purpose Control Register */ | ||
| 2618 | #define AXBS_MGPCR3_AULB_MASK (0x7U) | ||
| 2619 | #define AXBS_MGPCR3_AULB_SHIFT (0U) | ||
| 2620 | #define AXBS_MGPCR3_AULB_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK) | ||
| 2621 | #define AXBS_MGPCR3_AULB AXBS_MGPCR3_AULB_MASK | ||
| 2622 | |||
| 2623 | /*! @name MGPCR4 - Master General Purpose Control Register */ | ||
| 2624 | #define AXBS_MGPCR4_AULB_MASK (0x7U) | ||
| 2625 | #define AXBS_MGPCR4_AULB_SHIFT (0U) | ||
| 2626 | #define AXBS_MGPCR4_AULB_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK) | ||
| 2627 | #define AXBS_MGPCR4_AULB AXBS_MGPCR4_AULB_MASK | ||
| 2628 | |||
| 2629 | /*! @name MGPCR5 - Master General Purpose Control Register */ | ||
| 2630 | #define AXBS_MGPCR5_AULB_MASK (0x7U) | ||
| 2631 | #define AXBS_MGPCR5_AULB_SHIFT (0U) | ||
| 2632 | #define AXBS_MGPCR5_AULB_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK) | ||
| 2633 | #define AXBS_MGPCR5_AULB AXBS_MGPCR5_AULB_MASK | ||
| 2634 | |||
| 2635 | /*! @name MGPCR6 - Master General Purpose Control Register */ | ||
| 2636 | #define AXBS_MGPCR6_AULB_MASK (0x7U) | ||
| 2637 | #define AXBS_MGPCR6_AULB_SHIFT (0U) | ||
| 2638 | #define AXBS_MGPCR6_AULB_SET(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR6_AULB_SHIFT)) & AXBS_MGPCR6_AULB_MASK) | ||
| 2639 | #define AXBS_MGPCR6_AULB AXBS_MGPCR6_AULB_MASK | ||
| 2640 | |||
| 2641 | |||
| 2642 | /*! | ||
| 2643 | * @} | ||
| 2644 | */ /* end of group AXBS_Register_Masks */ | ||
| 2645 | |||
| 2646 | |||
| 2647 | /* AXBS - Peripheral instance base addresses */ | ||
| 2648 | /** Peripheral AXBS base address */ | ||
| 2649 | #define AXBS_BASE (0x40004000u) | ||
| 2650 | /** Peripheral AXBS base pointer */ | ||
| 2651 | #define AXBS ((AXBS_TypeDef *)AXBS_BASE) | ||
| 2652 | /** Array initializer of AXBS peripheral base addresses */ | ||
| 2653 | #define AXBS_BASE_ADDRS { AXBS_BASE } | ||
| 2654 | /** Array initializer of AXBS peripheral base pointers */ | ||
| 2655 | #define AXBS_BASE_PTRS { AXBS } | ||
| 2656 | |||
| 2657 | /*! | ||
| 2658 | * @} | ||
| 2659 | */ /* end of group AXBS_Peripheral_Access_Layer */ | ||
| 2660 | |||
| 2661 | |||
| 2662 | /* ---------------------------------------------------------------------------- | ||
| 2663 | -- CAN Peripheral Access Layer | ||
| 2664 | ---------------------------------------------------------------------------- */ | ||
| 2665 | |||
| 2666 | /*! | ||
| 2667 | * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer | ||
| 2668 | * @{ | ||
| 2669 | */ | ||
| 2670 | |||
| 2671 | /** CAN - Register Layout Typedef */ | ||
| 2672 | typedef struct { | ||
| 2673 | __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ | ||
| 2674 | __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */ | ||
| 2675 | __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */ | ||
| 2676 | uint8_t RESERVED_0[4]; | ||
| 2677 | __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ | ||
| 2678 | __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */ | ||
| 2679 | __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */ | ||
| 2680 | __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ | ||
| 2681 | __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */ | ||
| 2682 | uint8_t RESERVED_1[4]; | ||
| 2683 | __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */ | ||
| 2684 | uint8_t RESERVED_2[4]; | ||
| 2685 | __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */ | ||
| 2686 | __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */ | ||
| 2687 | __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */ | ||
| 2688 | uint8_t RESERVED_3[8]; | ||
| 2689 | __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ | ||
| 2690 | __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */ | ||
| 2691 | __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ | ||
| 2692 | uint8_t RESERVED_4[48]; | ||
| 2693 | struct { /* offset: 0x80, array step: 0x10 */ | ||
| 2694 | __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */ | ||
| 2695 | __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */ | ||
| 2696 | __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */ | ||
| 2697 | __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */ | ||
| 2698 | } MB[16]; | ||
| 2699 | uint8_t RESERVED_5[1792]; | ||
| 2700 | __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ | ||
| 2701 | } CAN_TypeDef; | ||
| 2702 | |||
| 2703 | /* ---------------------------------------------------------------------------- | ||
| 2704 | -- CAN Register Masks | ||
| 2705 | ---------------------------------------------------------------------------- */ | ||
| 2706 | |||
| 2707 | /*! | ||
| 2708 | * @addtogroup CAN_Register_Masks CAN Register Masks | ||
| 2709 | * @{ | ||
| 2710 | */ | ||
| 2711 | |||
| 2712 | /*! @name MCR - Module Configuration Register */ | ||
| 2713 | #define CAN_MCR_MAXMB_MASK (0x7FU) | ||
| 2714 | #define CAN_MCR_MAXMB_SHIFT (0U) | ||
| 2715 | #define CAN_MCR_MAXMB_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) | ||
| 2716 | #define CAN_MCR_MAXMB CAN_MCR_MAXMB_MASK | ||
| 2717 | #define CAN_MCR_IDAM_MASK (0x300U) | ||
| 2718 | #define CAN_MCR_IDAM_SHIFT (8U) | ||
| 2719 | #define CAN_MCR_IDAM_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) | ||
| 2720 | #define CAN_MCR_IDAM CAN_MCR_IDAM_MASK | ||
| 2721 | #define CAN_MCR_AEN_MASK (0x1000U) | ||
| 2722 | #define CAN_MCR_AEN_SHIFT (12U) | ||
| 2723 | #define CAN_MCR_AEN_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) | ||
| 2724 | #define CAN_MCR_AEN CAN_MCR_AEN_MASK | ||
| 2725 | #define CAN_MCR_LPRIOEN_MASK (0x2000U) | ||
| 2726 | #define CAN_MCR_LPRIOEN_SHIFT (13U) | ||
| 2727 | #define CAN_MCR_LPRIOEN_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) | ||
| 2728 | #define CAN_MCR_LPRIOEN CAN_MCR_LPRIOEN_MASK | ||
| 2729 | #define CAN_MCR_IRMQ_MASK (0x10000U) | ||
| 2730 | #define CAN_MCR_IRMQ_SHIFT (16U) | ||
| 2731 | #define CAN_MCR_IRMQ_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) | ||
| 2732 | #define CAN_MCR_IRMQ CAN_MCR_IRMQ_MASK | ||
| 2733 | #define CAN_MCR_SRXDIS_MASK (0x20000U) | ||
| 2734 | #define CAN_MCR_SRXDIS_SHIFT (17U) | ||
| 2735 | #define CAN_MCR_SRXDIS_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) | ||
| 2736 | #define CAN_MCR_SRXDIS CAN_MCR_SRXDIS_MASK | ||
| 2737 | #define CAN_MCR_WAKSRC_MASK (0x80000U) | ||
| 2738 | #define CAN_MCR_WAKSRC_SHIFT (19U) | ||
| 2739 | #define CAN_MCR_WAKSRC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) | ||
| 2740 | #define CAN_MCR_WAKSRC CAN_MCR_WAKSRC_MASK | ||
| 2741 | #define CAN_MCR_LPMACK_MASK (0x100000U) | ||
| 2742 | #define CAN_MCR_LPMACK_SHIFT (20U) | ||
| 2743 | #define CAN_MCR_LPMACK_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) | ||
| 2744 | #define CAN_MCR_LPMACK CAN_MCR_LPMACK_MASK | ||
| 2745 | #define CAN_MCR_WRNEN_MASK (0x200000U) | ||
| 2746 | #define CAN_MCR_WRNEN_SHIFT (21U) | ||
| 2747 | #define CAN_MCR_WRNEN_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) | ||
| 2748 | #define CAN_MCR_WRNEN CAN_MCR_WRNEN_MASK | ||
| 2749 | #define CAN_MCR_SLFWAK_MASK (0x400000U) | ||
| 2750 | #define CAN_MCR_SLFWAK_SHIFT (22U) | ||
| 2751 | #define CAN_MCR_SLFWAK_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) | ||
| 2752 | #define CAN_MCR_SLFWAK CAN_MCR_SLFWAK_MASK | ||
| 2753 | #define CAN_MCR_SUPV_MASK (0x800000U) | ||
| 2754 | #define CAN_MCR_SUPV_SHIFT (23U) | ||
| 2755 | #define CAN_MCR_SUPV_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) | ||
| 2756 | #define CAN_MCR_SUPV CAN_MCR_SUPV_MASK | ||
| 2757 | #define CAN_MCR_FRZACK_MASK (0x1000000U) | ||
| 2758 | #define CAN_MCR_FRZACK_SHIFT (24U) | ||
| 2759 | #define CAN_MCR_FRZACK_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) | ||
| 2760 | #define CAN_MCR_FRZACK CAN_MCR_FRZACK_MASK | ||
| 2761 | #define CAN_MCR_SOFTRST_MASK (0x2000000U) | ||
| 2762 | #define CAN_MCR_SOFTRST_SHIFT (25U) | ||
| 2763 | #define CAN_MCR_SOFTRST_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) | ||
| 2764 | #define CAN_MCR_SOFTRST CAN_MCR_SOFTRST_MASK | ||
| 2765 | #define CAN_MCR_WAKMSK_MASK (0x4000000U) | ||
| 2766 | #define CAN_MCR_WAKMSK_SHIFT (26U) | ||
| 2767 | #define CAN_MCR_WAKMSK_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) | ||
| 2768 | #define CAN_MCR_WAKMSK CAN_MCR_WAKMSK_MASK | ||
| 2769 | #define CAN_MCR_NOTRDY_MASK (0x8000000U) | ||
| 2770 | #define CAN_MCR_NOTRDY_SHIFT (27U) | ||
| 2771 | #define CAN_MCR_NOTRDY_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) | ||
| 2772 | #define CAN_MCR_NOTRDY CAN_MCR_NOTRDY_MASK | ||
| 2773 | #define CAN_MCR_HALT_MASK (0x10000000U) | ||
| 2774 | #define CAN_MCR_HALT_SHIFT (28U) | ||
| 2775 | #define CAN_MCR_HALT_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) | ||
| 2776 | #define CAN_MCR_HALT CAN_MCR_HALT_MASK | ||
| 2777 | #define CAN_MCR_RFEN_MASK (0x20000000U) | ||
| 2778 | #define CAN_MCR_RFEN_SHIFT (29U) | ||
| 2779 | #define CAN_MCR_RFEN_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) | ||
| 2780 | #define CAN_MCR_RFEN CAN_MCR_RFEN_MASK | ||
| 2781 | #define CAN_MCR_FRZ_MASK (0x40000000U) | ||
| 2782 | #define CAN_MCR_FRZ_SHIFT (30U) | ||
| 2783 | #define CAN_MCR_FRZ_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) | ||
| 2784 | #define CAN_MCR_FRZ CAN_MCR_FRZ_MASK | ||
| 2785 | #define CAN_MCR_MDIS_MASK (0x80000000U) | ||
| 2786 | #define CAN_MCR_MDIS_SHIFT (31U) | ||
| 2787 | #define CAN_MCR_MDIS_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) | ||
| 2788 | #define CAN_MCR_MDIS CAN_MCR_MDIS_MASK | ||
| 2789 | |||
| 2790 | /*! @name CTRL1 - Control 1 register */ | ||
| 2791 | #define CAN_CTRL1_PROPSEG_MASK (0x7U) | ||
| 2792 | #define CAN_CTRL1_PROPSEG_SHIFT (0U) | ||
| 2793 | #define CAN_CTRL1_PROPSEG_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) | ||
| 2794 | #define CAN_CTRL1_PROPSEG CAN_CTRL1_PROPSEG_MASK | ||
| 2795 | #define CAN_CTRL1_LOM_MASK (0x8U) | ||
| 2796 | #define CAN_CTRL1_LOM_SHIFT (3U) | ||
| 2797 | #define CAN_CTRL1_LOM_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) | ||
| 2798 | #define CAN_CTRL1_LOM CAN_CTRL1_LOM_MASK | ||
| 2799 | #define CAN_CTRL1_LBUF_MASK (0x10U) | ||
| 2800 | #define CAN_CTRL1_LBUF_SHIFT (4U) | ||
| 2801 | #define CAN_CTRL1_LBUF_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) | ||
| 2802 | #define CAN_CTRL1_LBUF CAN_CTRL1_LBUF_MASK | ||
| 2803 | #define CAN_CTRL1_TSYN_MASK (0x20U) | ||
| 2804 | #define CAN_CTRL1_TSYN_SHIFT (5U) | ||
| 2805 | #define CAN_CTRL1_TSYN_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) | ||
| 2806 | #define CAN_CTRL1_TSYN CAN_CTRL1_TSYN_MASK | ||
| 2807 | #define CAN_CTRL1_BOFFREC_MASK (0x40U) | ||
| 2808 | #define CAN_CTRL1_BOFFREC_SHIFT (6U) | ||
| 2809 | #define CAN_CTRL1_BOFFREC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) | ||
| 2810 | #define CAN_CTRL1_BOFFREC CAN_CTRL1_BOFFREC_MASK | ||
| 2811 | #define CAN_CTRL1_SMP_MASK (0x80U) | ||
| 2812 | #define CAN_CTRL1_SMP_SHIFT (7U) | ||
| 2813 | #define CAN_CTRL1_SMP_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) | ||
| 2814 | #define CAN_CTRL1_SMP CAN_CTRL1_SMP_MASK | ||
| 2815 | #define CAN_CTRL1_RWRNMSK_MASK (0x400U) | ||
| 2816 | #define CAN_CTRL1_RWRNMSK_SHIFT (10U) | ||
| 2817 | #define CAN_CTRL1_RWRNMSK_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) | ||
| 2818 | #define CAN_CTRL1_RWRNMSK CAN_CTRL1_RWRNMSK_MASK | ||
| 2819 | #define CAN_CTRL1_TWRNMSK_MASK (0x800U) | ||
| 2820 | #define CAN_CTRL1_TWRNMSK_SHIFT (11U) | ||
| 2821 | #define CAN_CTRL1_TWRNMSK_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) | ||
| 2822 | #define CAN_CTRL1_TWRNMSK CAN_CTRL1_TWRNMSK_MASK | ||
| 2823 | #define CAN_CTRL1_LPB_MASK (0x1000U) | ||
| 2824 | #define CAN_CTRL1_LPB_SHIFT (12U) | ||
| 2825 | #define CAN_CTRL1_LPB_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) | ||
| 2826 | #define CAN_CTRL1_LPB CAN_CTRL1_LPB_MASK | ||
| 2827 | #define CAN_CTRL1_CLKSRC_MASK (0x2000U) | ||
| 2828 | #define CAN_CTRL1_CLKSRC_SHIFT (13U) | ||
| 2829 | #define CAN_CTRL1_CLKSRC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK) | ||
| 2830 | #define CAN_CTRL1_CLKSRC CAN_CTRL1_CLKSRC_MASK | ||
| 2831 | #define CAN_CTRL1_ERRMSK_MASK (0x4000U) | ||
| 2832 | #define CAN_CTRL1_ERRMSK_SHIFT (14U) | ||
| 2833 | #define CAN_CTRL1_ERRMSK_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) | ||
| 2834 | #define CAN_CTRL1_ERRMSK CAN_CTRL1_ERRMSK_MASK | ||
| 2835 | #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) | ||
| 2836 | #define CAN_CTRL1_BOFFMSK_SHIFT (15U) | ||
| 2837 | #define CAN_CTRL1_BOFFMSK_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) | ||
| 2838 | #define CAN_CTRL1_BOFFMSK CAN_CTRL1_BOFFMSK_MASK | ||
| 2839 | #define CAN_CTRL1_PSEG2_MASK (0x70000U) | ||
| 2840 | #define CAN_CTRL1_PSEG2_SHIFT (16U) | ||
| 2841 | #define CAN_CTRL1_PSEG2_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) | ||
| 2842 | #define CAN_CTRL1_PSEG2 CAN_CTRL1_PSEG2_MASK | ||
| 2843 | #define CAN_CTRL1_PSEG1_MASK (0x380000U) | ||
| 2844 | #define CAN_CTRL1_PSEG1_SHIFT (19U) | ||
| 2845 | #define CAN_CTRL1_PSEG1_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) | ||
| 2846 | #define CAN_CTRL1_PSEG1 CAN_CTRL1_PSEG1_MASK | ||
| 2847 | #define CAN_CTRL1_RJW_MASK (0xC00000U) | ||
| 2848 | #define CAN_CTRL1_RJW_SHIFT (22U) | ||
| 2849 | #define CAN_CTRL1_RJW_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) | ||
| 2850 | #define CAN_CTRL1_RJW CAN_CTRL1_RJW_MASK | ||
| 2851 | #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) | ||
| 2852 | #define CAN_CTRL1_PRESDIV_SHIFT (24U) | ||
| 2853 | #define CAN_CTRL1_PRESDIV_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) | ||
| 2854 | #define CAN_CTRL1_PRESDIV CAN_CTRL1_PRESDIV_MASK | ||
| 2855 | |||
| 2856 | /*! @name TIMER - Free Running Timer */ | ||
| 2857 | #define CAN_TIMER_TIMER_MASK (0xFFFFU) | ||
| 2858 | #define CAN_TIMER_TIMER_SHIFT (0U) | ||
| 2859 | #define CAN_TIMER_TIMER_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) | ||
| 2860 | #define CAN_TIMER_TIMER CAN_TIMER_TIMER_MASK | ||
| 2861 | |||
| 2862 | /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ | ||
| 2863 | #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) | ||
| 2864 | #define CAN_RXMGMASK_MG_SHIFT (0U) | ||
| 2865 | #define CAN_RXMGMASK_MG_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) | ||
| 2866 | #define CAN_RXMGMASK_MG CAN_RXMGMASK_MG_MASK | ||
| 2867 | |||
| 2868 | /*! @name RX14MASK - Rx 14 Mask register */ | ||
| 2869 | #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) | ||
| 2870 | #define CAN_RX14MASK_RX14M_SHIFT (0U) | ||
| 2871 | #define CAN_RX14MASK_RX14M_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) | ||
| 2872 | #define CAN_RX14MASK_RX14M CAN_RX14MASK_RX14M_MASK | ||
| 2873 | |||
| 2874 | /*! @name RX15MASK - Rx 15 Mask register */ | ||
| 2875 | #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) | ||
| 2876 | #define CAN_RX15MASK_RX15M_SHIFT (0U) | ||
| 2877 | #define CAN_RX15MASK_RX15M_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) | ||
| 2878 | #define CAN_RX15MASK_RX15M CAN_RX15MASK_RX15M_MASK | ||
| 2879 | |||
| 2880 | /*! @name ECR - Error Counter */ | ||
| 2881 | #define CAN_ECR_TXERRCNT_MASK (0xFFU) | ||
| 2882 | #define CAN_ECR_TXERRCNT_SHIFT (0U) | ||
| 2883 | #define CAN_ECR_TXERRCNT_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) | ||
| 2884 | #define CAN_ECR_TXERRCNT CAN_ECR_TXERRCNT_MASK | ||
| 2885 | #define CAN_ECR_RXERRCNT_MASK (0xFF00U) | ||
| 2886 | #define CAN_ECR_RXERRCNT_SHIFT (8U) | ||
| 2887 | #define CAN_ECR_RXERRCNT_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) | ||
| 2888 | #define CAN_ECR_RXERRCNT CAN_ECR_RXERRCNT_MASK | ||
| 2889 | |||
| 2890 | /*! @name ESR1 - Error and Status 1 register */ | ||
| 2891 | #define CAN_ESR1_WAKINT_MASK (0x1U) | ||
| 2892 | #define CAN_ESR1_WAKINT_SHIFT (0U) | ||
| 2893 | #define CAN_ESR1_WAKINT_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) | ||
| 2894 | #define CAN_ESR1_WAKINT CAN_ESR1_WAKINT_MASK | ||
| 2895 | #define CAN_ESR1_ERRINT_MASK (0x2U) | ||
| 2896 | #define CAN_ESR1_ERRINT_SHIFT (1U) | ||
| 2897 | #define CAN_ESR1_ERRINT_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) | ||
| 2898 | #define CAN_ESR1_ERRINT CAN_ESR1_ERRINT_MASK | ||
| 2899 | #define CAN_ESR1_BOFFINT_MASK (0x4U) | ||
| 2900 | #define CAN_ESR1_BOFFINT_SHIFT (2U) | ||
| 2901 | #define CAN_ESR1_BOFFINT_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) | ||
| 2902 | #define CAN_ESR1_BOFFINT CAN_ESR1_BOFFINT_MASK | ||
| 2903 | #define CAN_ESR1_RX_MASK (0x8U) | ||
| 2904 | #define CAN_ESR1_RX_SHIFT (3U) | ||
| 2905 | #define CAN_ESR1_RX_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) | ||
| 2906 | #define CAN_ESR1_RX CAN_ESR1_RX_MASK | ||
| 2907 | #define CAN_ESR1_FLTCONF_MASK (0x30U) | ||
| 2908 | #define CAN_ESR1_FLTCONF_SHIFT (4U) | ||
| 2909 | #define CAN_ESR1_FLTCONF_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) | ||
| 2910 | #define CAN_ESR1_FLTCONF CAN_ESR1_FLTCONF_MASK | ||
| 2911 | #define CAN_ESR1_TX_MASK (0x40U) | ||
| 2912 | #define CAN_ESR1_TX_SHIFT (6U) | ||
| 2913 | #define CAN_ESR1_TX_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) | ||
| 2914 | #define CAN_ESR1_TX CAN_ESR1_TX_MASK | ||
| 2915 | #define CAN_ESR1_IDLE_MASK (0x80U) | ||
| 2916 | #define CAN_ESR1_IDLE_SHIFT (7U) | ||
| 2917 | #define CAN_ESR1_IDLE_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) | ||
| 2918 | #define CAN_ESR1_IDLE CAN_ESR1_IDLE_MASK | ||
| 2919 | #define CAN_ESR1_RXWRN_MASK (0x100U) | ||
| 2920 | #define CAN_ESR1_RXWRN_SHIFT (8U) | ||
| 2921 | #define CAN_ESR1_RXWRN_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) | ||
| 2922 | #define CAN_ESR1_RXWRN CAN_ESR1_RXWRN_MASK | ||
| 2923 | #define CAN_ESR1_TXWRN_MASK (0x200U) | ||
| 2924 | #define CAN_ESR1_TXWRN_SHIFT (9U) | ||
| 2925 | #define CAN_ESR1_TXWRN_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) | ||
| 2926 | #define CAN_ESR1_TXWRN CAN_ESR1_TXWRN_MASK | ||
| 2927 | #define CAN_ESR1_STFERR_MASK (0x400U) | ||
| 2928 | #define CAN_ESR1_STFERR_SHIFT (10U) | ||
| 2929 | #define CAN_ESR1_STFERR_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) | ||
| 2930 | #define CAN_ESR1_STFERR CAN_ESR1_STFERR_MASK | ||
| 2931 | #define CAN_ESR1_FRMERR_MASK (0x800U) | ||
| 2932 | #define CAN_ESR1_FRMERR_SHIFT (11U) | ||
| 2933 | #define CAN_ESR1_FRMERR_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) | ||
| 2934 | #define CAN_ESR1_FRMERR CAN_ESR1_FRMERR_MASK | ||
| 2935 | #define CAN_ESR1_CRCERR_MASK (0x1000U) | ||
| 2936 | #define CAN_ESR1_CRCERR_SHIFT (12U) | ||
| 2937 | #define CAN_ESR1_CRCERR_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) | ||
| 2938 | #define CAN_ESR1_CRCERR CAN_ESR1_CRCERR_MASK | ||
| 2939 | #define CAN_ESR1_ACKERR_MASK (0x2000U) | ||
| 2940 | #define CAN_ESR1_ACKERR_SHIFT (13U) | ||
| 2941 | #define CAN_ESR1_ACKERR_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) | ||
| 2942 | #define CAN_ESR1_ACKERR CAN_ESR1_ACKERR_MASK | ||
| 2943 | #define CAN_ESR1_BIT0ERR_MASK (0x4000U) | ||
| 2944 | #define CAN_ESR1_BIT0ERR_SHIFT (14U) | ||
| 2945 | #define CAN_ESR1_BIT0ERR_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) | ||
| 2946 | #define CAN_ESR1_BIT0ERR CAN_ESR1_BIT0ERR_MASK | ||
| 2947 | #define CAN_ESR1_BIT1ERR_MASK (0x8000U) | ||
| 2948 | #define CAN_ESR1_BIT1ERR_SHIFT (15U) | ||
| 2949 | #define CAN_ESR1_BIT1ERR_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) | ||
| 2950 | #define CAN_ESR1_BIT1ERR CAN_ESR1_BIT1ERR_MASK | ||
| 2951 | #define CAN_ESR1_RWRNINT_MASK (0x10000U) | ||
| 2952 | #define CAN_ESR1_RWRNINT_SHIFT (16U) | ||
| 2953 | #define CAN_ESR1_RWRNINT_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) | ||
| 2954 | #define CAN_ESR1_RWRNINT CAN_ESR1_RWRNINT_MASK | ||
| 2955 | #define CAN_ESR1_TWRNINT_MASK (0x20000U) | ||
| 2956 | #define CAN_ESR1_TWRNINT_SHIFT (17U) | ||
| 2957 | #define CAN_ESR1_TWRNINT_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) | ||
| 2958 | #define CAN_ESR1_TWRNINT CAN_ESR1_TWRNINT_MASK | ||
| 2959 | #define CAN_ESR1_SYNCH_MASK (0x40000U) | ||
| 2960 | #define CAN_ESR1_SYNCH_SHIFT (18U) | ||
| 2961 | #define CAN_ESR1_SYNCH_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) | ||
| 2962 | #define CAN_ESR1_SYNCH CAN_ESR1_SYNCH_MASK | ||
| 2963 | |||
| 2964 | /*! @name IMASK1 - Interrupt Masks 1 register */ | ||
| 2965 | #define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) | ||
| 2966 | #define CAN_IMASK1_BUFLM_SHIFT (0U) | ||
| 2967 | #define CAN_IMASK1_BUFLM_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) | ||
| 2968 | #define CAN_IMASK1_BUFLM CAN_IMASK1_BUFLM_MASK | ||
| 2969 | |||
| 2970 | /*! @name IFLAG1 - Interrupt Flags 1 register */ | ||
| 2971 | #define CAN_IFLAG1_BUF0I_MASK (0x1U) | ||
| 2972 | #define CAN_IFLAG1_BUF0I_SHIFT (0U) | ||
| 2973 | #define CAN_IFLAG1_BUF0I_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) | ||
| 2974 | #define CAN_IFLAG1_BUF0I CAN_IFLAG1_BUF0I_MASK | ||
| 2975 | #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) | ||
| 2976 | #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) | ||
| 2977 | #define CAN_IFLAG1_BUF4TO1I_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) | ||
| 2978 | #define CAN_IFLAG1_BUF4TO1I CAN_IFLAG1_BUF4TO1I_MASK | ||
| 2979 | #define CAN_IFLAG1_BUF5I_MASK (0x20U) | ||
| 2980 | #define CAN_IFLAG1_BUF5I_SHIFT (5U) | ||
| 2981 | #define CAN_IFLAG1_BUF5I_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) | ||
| 2982 | #define CAN_IFLAG1_BUF5I CAN_IFLAG1_BUF5I_MASK | ||
| 2983 | #define CAN_IFLAG1_BUF6I_MASK (0x40U) | ||
| 2984 | #define CAN_IFLAG1_BUF6I_SHIFT (6U) | ||
| 2985 | #define CAN_IFLAG1_BUF6I_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) | ||
| 2986 | #define CAN_IFLAG1_BUF6I CAN_IFLAG1_BUF6I_MASK | ||
| 2987 | #define CAN_IFLAG1_BUF7I_MASK (0x80U) | ||
| 2988 | #define CAN_IFLAG1_BUF7I_SHIFT (7U) | ||
| 2989 | #define CAN_IFLAG1_BUF7I_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) | ||
| 2990 | #define CAN_IFLAG1_BUF7I CAN_IFLAG1_BUF7I_MASK | ||
| 2991 | #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) | ||
| 2992 | #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) | ||
| 2993 | #define CAN_IFLAG1_BUF31TO8I_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) | ||
| 2994 | #define CAN_IFLAG1_BUF31TO8I CAN_IFLAG1_BUF31TO8I_MASK | ||
| 2995 | |||
| 2996 | /*! @name CTRL2 - Control 2 register */ | ||
| 2997 | #define CAN_CTRL2_EACEN_MASK (0x10000U) | ||
| 2998 | #define CAN_CTRL2_EACEN_SHIFT (16U) | ||
| 2999 | #define CAN_CTRL2_EACEN_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) | ||
| 3000 | #define CAN_CTRL2_EACEN CAN_CTRL2_EACEN_MASK | ||
| 3001 | #define CAN_CTRL2_RRS_MASK (0x20000U) | ||
| 3002 | #define CAN_CTRL2_RRS_SHIFT (17U) | ||
| 3003 | #define CAN_CTRL2_RRS_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) | ||
| 3004 | #define CAN_CTRL2_RRS CAN_CTRL2_RRS_MASK | ||
| 3005 | #define CAN_CTRL2_MRP_MASK (0x40000U) | ||
| 3006 | #define CAN_CTRL2_MRP_SHIFT (18U) | ||
| 3007 | #define CAN_CTRL2_MRP_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) | ||
| 3008 | #define CAN_CTRL2_MRP CAN_CTRL2_MRP_MASK | ||
| 3009 | #define CAN_CTRL2_TASD_MASK (0xF80000U) | ||
| 3010 | #define CAN_CTRL2_TASD_SHIFT (19U) | ||
| 3011 | #define CAN_CTRL2_TASD_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) | ||
| 3012 | #define CAN_CTRL2_TASD CAN_CTRL2_TASD_MASK | ||
| 3013 | #define CAN_CTRL2_RFFN_MASK (0xF000000U) | ||
| 3014 | #define CAN_CTRL2_RFFN_SHIFT (24U) | ||
| 3015 | #define CAN_CTRL2_RFFN_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) | ||
| 3016 | #define CAN_CTRL2_RFFN CAN_CTRL2_RFFN_MASK | ||
| 3017 | #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) | ||
| 3018 | #define CAN_CTRL2_WRMFRZ_SHIFT (28U) | ||
| 3019 | #define CAN_CTRL2_WRMFRZ_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) | ||
| 3020 | #define CAN_CTRL2_WRMFRZ CAN_CTRL2_WRMFRZ_MASK | ||
| 3021 | |||
| 3022 | /*! @name ESR2 - Error and Status 2 register */ | ||
| 3023 | #define CAN_ESR2_IMB_MASK (0x2000U) | ||
| 3024 | #define CAN_ESR2_IMB_SHIFT (13U) | ||
| 3025 | #define CAN_ESR2_IMB_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) | ||
| 3026 | #define CAN_ESR2_IMB CAN_ESR2_IMB_MASK | ||
| 3027 | #define CAN_ESR2_VPS_MASK (0x4000U) | ||
| 3028 | #define CAN_ESR2_VPS_SHIFT (14U) | ||
| 3029 | #define CAN_ESR2_VPS_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) | ||
| 3030 | #define CAN_ESR2_VPS CAN_ESR2_VPS_MASK | ||
| 3031 | #define CAN_ESR2_LPTM_MASK (0x7F0000U) | ||
| 3032 | #define CAN_ESR2_LPTM_SHIFT (16U) | ||
| 3033 | #define CAN_ESR2_LPTM_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) | ||
| 3034 | #define CAN_ESR2_LPTM CAN_ESR2_LPTM_MASK | ||
| 3035 | |||
| 3036 | /*! @name CRCR - CRC Register */ | ||
| 3037 | #define CAN_CRCR_TXCRC_MASK (0x7FFFU) | ||
| 3038 | #define CAN_CRCR_TXCRC_SHIFT (0U) | ||
| 3039 | #define CAN_CRCR_TXCRC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) | ||
| 3040 | #define CAN_CRCR_TXCRC CAN_CRCR_TXCRC_MASK | ||
| 3041 | #define CAN_CRCR_MBCRC_MASK (0x7F0000U) | ||
| 3042 | #define CAN_CRCR_MBCRC_SHIFT (16U) | ||
| 3043 | #define CAN_CRCR_MBCRC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) | ||
| 3044 | #define CAN_CRCR_MBCRC CAN_CRCR_MBCRC_MASK | ||
| 3045 | |||
| 3046 | /*! @name RXFGMASK - Rx FIFO Global Mask register */ | ||
| 3047 | #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) | ||
| 3048 | #define CAN_RXFGMASK_FGM_SHIFT (0U) | ||
| 3049 | #define CAN_RXFGMASK_FGM_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) | ||
| 3050 | #define CAN_RXFGMASK_FGM CAN_RXFGMASK_FGM_MASK | ||
| 3051 | |||
| 3052 | /*! @name RXFIR - Rx FIFO Information Register */ | ||
| 3053 | #define CAN_RXFIR_IDHIT_MASK (0x1FFU) | ||
| 3054 | #define CAN_RXFIR_IDHIT_SHIFT (0U) | ||
| 3055 | #define CAN_RXFIR_IDHIT_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) | ||
| 3056 | #define CAN_RXFIR_IDHIT CAN_RXFIR_IDHIT_MASK | ||
| 3057 | |||
| 3058 | /*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */ | ||
| 3059 | #define CAN_CS_TIME_STAMP_MASK (0xFFFFU) | ||
| 3060 | #define CAN_CS_TIME_STAMP_SHIFT (0U) | ||
| 3061 | #define CAN_CS_TIME_STAMP_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) | ||
| 3062 | #define CAN_CS_TIME_STAMP CAN_CS_TIME_STAMP_MASK | ||
| 3063 | #define CAN_CS_DLC_MASK (0xF0000U) | ||
| 3064 | #define CAN_CS_DLC_SHIFT (16U) | ||
| 3065 | #define CAN_CS_DLC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) | ||
| 3066 | #define CAN_CS_DLC CAN_CS_DLC_MASK | ||
| 3067 | #define CAN_CS_RTR_MASK (0x100000U) | ||
| 3068 | #define CAN_CS_RTR_SHIFT (20U) | ||
| 3069 | #define CAN_CS_RTR_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) | ||
| 3070 | #define CAN_CS_RTR CAN_CS_RTR_MASK | ||
| 3071 | #define CAN_CS_IDE_MASK (0x200000U) | ||
| 3072 | #define CAN_CS_IDE_SHIFT (21U) | ||
| 3073 | #define CAN_CS_IDE_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) | ||
| 3074 | #define CAN_CS_IDE CAN_CS_IDE_MASK | ||
| 3075 | #define CAN_CS_SRR_MASK (0x400000U) | ||
| 3076 | #define CAN_CS_SRR_SHIFT (22U) | ||
| 3077 | #define CAN_CS_SRR_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) | ||
| 3078 | #define CAN_CS_SRR CAN_CS_SRR_MASK | ||
| 3079 | #define CAN_CS_CODE_MASK (0xF000000U) | ||
| 3080 | #define CAN_CS_CODE_SHIFT (24U) | ||
| 3081 | #define CAN_CS_CODE_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) | ||
| 3082 | #define CAN_CS_CODE CAN_CS_CODE_MASK | ||
| 3083 | |||
| 3084 | /* The count of CAN_CS */ | ||
| 3085 | #define CAN_CS_COUNT (16U) | ||
| 3086 | |||
| 3087 | /*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */ | ||
| 3088 | #define CAN_ID_EXT_MASK (0x3FFFFU) | ||
| 3089 | #define CAN_ID_EXT_SHIFT (0U) | ||
| 3090 | #define CAN_ID_EXT_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) | ||
| 3091 | #define CAN_ID_EXT CAN_ID_EXT_MASK | ||
| 3092 | #define CAN_ID_STD_MASK (0x1FFC0000U) | ||
| 3093 | #define CAN_ID_STD_SHIFT (18U) | ||
| 3094 | #define CAN_ID_STD_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) | ||
| 3095 | #define CAN_ID_STD CAN_ID_STD_MASK | ||
| 3096 | #define CAN_ID_PRIO_MASK (0xE0000000U) | ||
| 3097 | #define CAN_ID_PRIO_SHIFT (29U) | ||
| 3098 | #define CAN_ID_PRIO_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) | ||
| 3099 | #define CAN_ID_PRIO CAN_ID_PRIO_MASK | ||
| 3100 | |||
| 3101 | /* The count of CAN_ID */ | ||
| 3102 | #define CAN_ID_COUNT (16U) | ||
| 3103 | |||
| 3104 | /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */ | ||
| 3105 | #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) | ||
| 3106 | #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) | ||
| 3107 | #define CAN_WORD0_DATA_BYTE_3_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) | ||
| 3108 | #define CAN_WORD0_DATA_BYTE_3 CAN_WORD0_DATA_BYTE_3_MASK | ||
| 3109 | #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) | ||
| 3110 | #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) | ||
| 3111 | #define CAN_WORD0_DATA_BYTE_2_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) | ||
| 3112 | #define CAN_WORD0_DATA_BYTE_2 CAN_WORD0_DATA_BYTE_2_MASK | ||
| 3113 | #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) | ||
| 3114 | #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) | ||
| 3115 | #define CAN_WORD0_DATA_BYTE_1_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) | ||
| 3116 | #define CAN_WORD0_DATA_BYTE_1 CAN_WORD0_DATA_BYTE_1_MASK | ||
| 3117 | #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) | ||
| 3118 | #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) | ||
| 3119 | #define CAN_WORD0_DATA_BYTE_0_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) | ||
| 3120 | #define CAN_WORD0_DATA_BYTE_0 CAN_WORD0_DATA_BYTE_0_MASK | ||
| 3121 | |||
| 3122 | /* The count of CAN_WORD0 */ | ||
| 3123 | #define CAN_WORD0_COUNT (16U) | ||
| 3124 | |||
| 3125 | /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */ | ||
| 3126 | #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) | ||
| 3127 | #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) | ||
| 3128 | #define CAN_WORD1_DATA_BYTE_7_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) | ||
| 3129 | #define CAN_WORD1_DATA_BYTE_7 CAN_WORD1_DATA_BYTE_7_MASK | ||
| 3130 | #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) | ||
| 3131 | #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) | ||
| 3132 | #define CAN_WORD1_DATA_BYTE_6_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) | ||
| 3133 | #define CAN_WORD1_DATA_BYTE_6 CAN_WORD1_DATA_BYTE_6_MASK | ||
| 3134 | #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) | ||
| 3135 | #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) | ||
| 3136 | #define CAN_WORD1_DATA_BYTE_5_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) | ||
| 3137 | #define CAN_WORD1_DATA_BYTE_5 CAN_WORD1_DATA_BYTE_5_MASK | ||
| 3138 | #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) | ||
| 3139 | #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) | ||
| 3140 | #define CAN_WORD1_DATA_BYTE_4_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) | ||
| 3141 | #define CAN_WORD1_DATA_BYTE_4 CAN_WORD1_DATA_BYTE_4_MASK | ||
| 3142 | |||
| 3143 | /* The count of CAN_WORD1 */ | ||
| 3144 | #define CAN_WORD1_COUNT (16U) | ||
| 3145 | |||
| 3146 | /*! @name RXIMR - Rx Individual Mask Registers */ | ||
| 3147 | #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) | ||
| 3148 | #define CAN_RXIMR_MI_SHIFT (0U) | ||
| 3149 | #define CAN_RXIMR_MI_SET(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) | ||
| 3150 | #define CAN_RXIMR_MI CAN_RXIMR_MI_MASK | ||
| 3151 | |||
| 3152 | /* The count of CAN_RXIMR */ | ||
| 3153 | #define CAN_RXIMR_COUNT (16U) | ||
| 3154 | |||
| 3155 | |||
| 3156 | /*! | ||
| 3157 | * @} | ||
| 3158 | */ /* end of group CAN_Register_Masks */ | ||
| 3159 | |||
| 3160 | |||
| 3161 | /* CAN - Peripheral instance base addresses */ | ||
| 3162 | /** Peripheral CAN0 base address */ | ||
| 3163 | #define CAN0_BASE (0x40024000u) | ||
| 3164 | /** Peripheral CAN0 base pointer */ | ||
| 3165 | #define CAN0 ((CAN_TypeDef *)CAN0_BASE) | ||
| 3166 | /** Peripheral CAN1 base address */ | ||
| 3167 | #define CAN1_BASE (0x400A4000u) | ||
| 3168 | /** Peripheral CAN1 base pointer */ | ||
| 3169 | #define CAN1 ((CAN_TypeDef *)CAN1_BASE) | ||
| 3170 | /** Array initializer of CAN peripheral base addresses */ | ||
| 3171 | #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE } | ||
| 3172 | /** Array initializer of CAN peripheral base pointers */ | ||
| 3173 | #define CAN_BASE_PTRS { CAN0, CAN1 } | ||
| 3174 | /** Interrupt vectors for the CAN peripheral type */ | ||
| 3175 | #define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn, CAN1_Rx_Warning_IRQn } | ||
| 3176 | #define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn, CAN1_Tx_Warning_IRQn } | ||
| 3177 | #define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn, CAN1_Wake_Up_IRQn } | ||
| 3178 | #define CAN_Error_IRQS { CAN0_Error_IRQn, CAN1_Error_IRQn } | ||
| 3179 | #define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn, CAN1_Bus_Off_IRQn } | ||
| 3180 | #define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn, CAN1_ORed_Message_buffer_IRQn } | ||
| 3181 | |||
| 3182 | /*! | ||
| 3183 | * @} | ||
| 3184 | */ /* end of group CAN_Peripheral_Access_Layer */ | ||
| 3185 | |||
| 3186 | |||
| 3187 | /* ---------------------------------------------------------------------------- | ||
| 3188 | -- CAU Peripheral Access Layer | ||
| 3189 | ---------------------------------------------------------------------------- */ | ||
| 3190 | |||
| 3191 | /*! | ||
| 3192 | * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer | ||
| 3193 | * @{ | ||
| 3194 | */ | ||
| 3195 | |||
| 3196 | /** CAU - Register Layout Typedef */ | ||
| 3197 | typedef struct { | ||
| 3198 | __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */ | ||
| 3199 | uint8_t RESERVED_0[2048]; | ||
| 3200 | __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */ | ||
| 3201 | __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */ | ||
| 3202 | __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */ | ||
| 3203 | uint8_t RESERVED_1[20]; | ||
| 3204 | __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */ | ||
| 3205 | __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */ | ||
| 3206 | __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */ | ||
| 3207 | uint8_t RESERVED_2[20]; | ||
| 3208 | __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */ | ||
| 3209 | __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */ | ||
| 3210 | __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */ | ||
| 3211 | uint8_t RESERVED_3[20]; | ||
| 3212 | __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */ | ||
| 3213 | __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */ | ||
| 3214 | __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */ | ||
| 3215 | uint8_t RESERVED_4[84]; | ||
| 3216 | __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */ | ||
| 3217 | __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */ | ||
| 3218 | __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */ | ||
| 3219 | uint8_t RESERVED_5[20]; | ||
| 3220 | __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */ | ||
| 3221 | __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */ | ||
| 3222 | __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */ | ||
| 3223 | uint8_t RESERVED_6[276]; | ||
| 3224 | __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */ | ||
| 3225 | __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */ | ||
| 3226 | __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */ | ||
| 3227 | uint8_t RESERVED_7[20]; | ||
| 3228 | __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */ | ||
| 3229 | __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */ | ||
| 3230 | __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */ | ||
| 3231 | } CAU_TypeDef; | ||
| 3232 | |||
| 3233 | /* ---------------------------------------------------------------------------- | ||
| 3234 | -- CAU Register Masks | ||
| 3235 | ---------------------------------------------------------------------------- */ | ||
| 3236 | |||
| 3237 | /*! | ||
| 3238 | * @addtogroup CAU_Register_Masks CAU Register Masks | ||
| 3239 | * @{ | ||
| 3240 | */ | ||
| 3241 | |||
| 3242 | /*! @name DIRECT - Direct access register 0..Direct access register 15 */ | ||
| 3243 | #define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU) | ||
| 3244 | #define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U) | ||
| 3245 | #define CAU_DIRECT_CAU_DIRECT0_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK) | ||
| 3246 | #define CAU_DIRECT_CAU_DIRECT0 CAU_DIRECT_CAU_DIRECT0_MASK | ||
| 3247 | #define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU) | ||
| 3248 | #define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U) | ||
| 3249 | #define CAU_DIRECT_CAU_DIRECT1_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK) | ||
| 3250 | #define CAU_DIRECT_CAU_DIRECT1 CAU_DIRECT_CAU_DIRECT1_MASK | ||
| 3251 | #define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU) | ||
| 3252 | #define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U) | ||
| 3253 | #define CAU_DIRECT_CAU_DIRECT2_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK) | ||
| 3254 | #define CAU_DIRECT_CAU_DIRECT2 CAU_DIRECT_CAU_DIRECT2_MASK | ||
| 3255 | #define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU) | ||
| 3256 | #define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U) | ||
| 3257 | #define CAU_DIRECT_CAU_DIRECT3_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK) | ||
| 3258 | #define CAU_DIRECT_CAU_DIRECT3 CAU_DIRECT_CAU_DIRECT3_MASK | ||
| 3259 | #define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU) | ||
| 3260 | #define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U) | ||
| 3261 | #define CAU_DIRECT_CAU_DIRECT4_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK) | ||
| 3262 | #define CAU_DIRECT_CAU_DIRECT4 CAU_DIRECT_CAU_DIRECT4_MASK | ||
| 3263 | #define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU) | ||
| 3264 | #define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U) | ||
| 3265 | #define CAU_DIRECT_CAU_DIRECT5_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK) | ||
| 3266 | #define CAU_DIRECT_CAU_DIRECT5 CAU_DIRECT_CAU_DIRECT5_MASK | ||
| 3267 | #define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU) | ||
| 3268 | #define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U) | ||
| 3269 | #define CAU_DIRECT_CAU_DIRECT6_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK) | ||
| 3270 | #define CAU_DIRECT_CAU_DIRECT6 CAU_DIRECT_CAU_DIRECT6_MASK | ||
| 3271 | #define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU) | ||
| 3272 | #define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U) | ||
| 3273 | #define CAU_DIRECT_CAU_DIRECT7_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK) | ||
| 3274 | #define CAU_DIRECT_CAU_DIRECT7 CAU_DIRECT_CAU_DIRECT7_MASK | ||
| 3275 | #define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU) | ||
| 3276 | #define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U) | ||
| 3277 | #define CAU_DIRECT_CAU_DIRECT8_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK) | ||
| 3278 | #define CAU_DIRECT_CAU_DIRECT8 CAU_DIRECT_CAU_DIRECT8_MASK | ||
| 3279 | #define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU) | ||
| 3280 | #define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U) | ||
| 3281 | #define CAU_DIRECT_CAU_DIRECT9_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK) | ||
| 3282 | #define CAU_DIRECT_CAU_DIRECT9 CAU_DIRECT_CAU_DIRECT9_MASK | ||
| 3283 | #define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU) | ||
| 3284 | #define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U) | ||
| 3285 | #define CAU_DIRECT_CAU_DIRECT10_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK) | ||
| 3286 | #define CAU_DIRECT_CAU_DIRECT10 CAU_DIRECT_CAU_DIRECT10_MASK | ||
| 3287 | #define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU) | ||
| 3288 | #define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U) | ||
| 3289 | #define CAU_DIRECT_CAU_DIRECT11_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK) | ||
| 3290 | #define CAU_DIRECT_CAU_DIRECT11 CAU_DIRECT_CAU_DIRECT11_MASK | ||
| 3291 | #define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU) | ||
| 3292 | #define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U) | ||
| 3293 | #define CAU_DIRECT_CAU_DIRECT12_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK) | ||
| 3294 | #define CAU_DIRECT_CAU_DIRECT12 CAU_DIRECT_CAU_DIRECT12_MASK | ||
| 3295 | #define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU) | ||
| 3296 | #define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U) | ||
| 3297 | #define CAU_DIRECT_CAU_DIRECT13_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK) | ||
| 3298 | #define CAU_DIRECT_CAU_DIRECT13 CAU_DIRECT_CAU_DIRECT13_MASK | ||
| 3299 | #define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU) | ||
| 3300 | #define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U) | ||
| 3301 | #define CAU_DIRECT_CAU_DIRECT14_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK) | ||
| 3302 | #define CAU_DIRECT_CAU_DIRECT14 CAU_DIRECT_CAU_DIRECT14_MASK | ||
| 3303 | #define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU) | ||
| 3304 | #define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U) | ||
| 3305 | #define CAU_DIRECT_CAU_DIRECT15_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK) | ||
| 3306 | #define CAU_DIRECT_CAU_DIRECT15 CAU_DIRECT_CAU_DIRECT15_MASK | ||
| 3307 | |||
| 3308 | /* The count of CAU_DIRECT */ | ||
| 3309 | #define CAU_DIRECT_COUNT (16U) | ||
| 3310 | |||
| 3311 | /*! @name LDR_CASR - Status register - Load Register command */ | ||
| 3312 | #define CAU_LDR_CASR_IC_MASK (0x1U) | ||
| 3313 | #define CAU_LDR_CASR_IC_SHIFT (0U) | ||
| 3314 | #define CAU_LDR_CASR_IC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK) | ||
| 3315 | #define CAU_LDR_CASR_IC CAU_LDR_CASR_IC_MASK | ||
| 3316 | #define CAU_LDR_CASR_DPE_MASK (0x2U) | ||
| 3317 | #define CAU_LDR_CASR_DPE_SHIFT (1U) | ||
| 3318 | #define CAU_LDR_CASR_DPE_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK) | ||
| 3319 | #define CAU_LDR_CASR_DPE CAU_LDR_CASR_DPE_MASK | ||
| 3320 | #define CAU_LDR_CASR_VER_MASK (0xF0000000U) | ||
| 3321 | #define CAU_LDR_CASR_VER_SHIFT (28U) | ||
| 3322 | #define CAU_LDR_CASR_VER_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK) | ||
| 3323 | #define CAU_LDR_CASR_VER CAU_LDR_CASR_VER_MASK | ||
| 3324 | |||
| 3325 | /*! @name LDR_CAA - Accumulator register - Load Register command */ | ||
| 3326 | #define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU) | ||
| 3327 | #define CAU_LDR_CAA_ACC_SHIFT (0U) | ||
| 3328 | #define CAU_LDR_CAA_ACC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK) | ||
| 3329 | #define CAU_LDR_CAA_ACC CAU_LDR_CAA_ACC_MASK | ||
| 3330 | |||
| 3331 | /*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */ | ||
| 3332 | #define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU) | ||
| 3333 | #define CAU_LDR_CA_CA0_SHIFT (0U) | ||
| 3334 | #define CAU_LDR_CA_CA0_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK) | ||
| 3335 | #define CAU_LDR_CA_CA0 CAU_LDR_CA_CA0_MASK | ||
| 3336 | #define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU) | ||
| 3337 | #define CAU_LDR_CA_CA1_SHIFT (0U) | ||
| 3338 | #define CAU_LDR_CA_CA1_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK) | ||
| 3339 | #define CAU_LDR_CA_CA1 CAU_LDR_CA_CA1_MASK | ||
| 3340 | #define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU) | ||
| 3341 | #define CAU_LDR_CA_CA2_SHIFT (0U) | ||
| 3342 | #define CAU_LDR_CA_CA2_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK) | ||
| 3343 | #define CAU_LDR_CA_CA2 CAU_LDR_CA_CA2_MASK | ||
| 3344 | #define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU) | ||
| 3345 | #define CAU_LDR_CA_CA3_SHIFT (0U) | ||
| 3346 | #define CAU_LDR_CA_CA3_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK) | ||
| 3347 | #define CAU_LDR_CA_CA3 CAU_LDR_CA_CA3_MASK | ||
| 3348 | #define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU) | ||
| 3349 | #define CAU_LDR_CA_CA4_SHIFT (0U) | ||
| 3350 | #define CAU_LDR_CA_CA4_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK) | ||
| 3351 | #define CAU_LDR_CA_CA4 CAU_LDR_CA_CA4_MASK | ||
| 3352 | #define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU) | ||
| 3353 | #define CAU_LDR_CA_CA5_SHIFT (0U) | ||
| 3354 | #define CAU_LDR_CA_CA5_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK) | ||
| 3355 | #define CAU_LDR_CA_CA5 CAU_LDR_CA_CA5_MASK | ||
| 3356 | #define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU) | ||
| 3357 | #define CAU_LDR_CA_CA6_SHIFT (0U) | ||
| 3358 | #define CAU_LDR_CA_CA6_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK) | ||
| 3359 | #define CAU_LDR_CA_CA6 CAU_LDR_CA_CA6_MASK | ||
| 3360 | #define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU) | ||
| 3361 | #define CAU_LDR_CA_CA7_SHIFT (0U) | ||
| 3362 | #define CAU_LDR_CA_CA7_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK) | ||
| 3363 | #define CAU_LDR_CA_CA7 CAU_LDR_CA_CA7_MASK | ||
| 3364 | #define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU) | ||
| 3365 | #define CAU_LDR_CA_CA8_SHIFT (0U) | ||
| 3366 | #define CAU_LDR_CA_CA8_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK) | ||
| 3367 | #define CAU_LDR_CA_CA8 CAU_LDR_CA_CA8_MASK | ||
| 3368 | |||
| 3369 | /* The count of CAU_LDR_CA */ | ||
| 3370 | #define CAU_LDR_CA_COUNT (9U) | ||
| 3371 | |||
| 3372 | /*! @name STR_CASR - Status register - Store Register command */ | ||
| 3373 | #define CAU_STR_CASR_IC_MASK (0x1U) | ||
| 3374 | #define CAU_STR_CASR_IC_SHIFT (0U) | ||
| 3375 | #define CAU_STR_CASR_IC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK) | ||
| 3376 | #define CAU_STR_CASR_IC CAU_STR_CASR_IC_MASK | ||
| 3377 | #define CAU_STR_CASR_DPE_MASK (0x2U) | ||
| 3378 | #define CAU_STR_CASR_DPE_SHIFT (1U) | ||
| 3379 | #define CAU_STR_CASR_DPE_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK) | ||
| 3380 | #define CAU_STR_CASR_DPE CAU_STR_CASR_DPE_MASK | ||
| 3381 | #define CAU_STR_CASR_VER_MASK (0xF0000000U) | ||
| 3382 | #define CAU_STR_CASR_VER_SHIFT (28U) | ||
| 3383 | #define CAU_STR_CASR_VER_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK) | ||
| 3384 | #define CAU_STR_CASR_VER CAU_STR_CASR_VER_MASK | ||
| 3385 | |||
| 3386 | /*! @name STR_CAA - Accumulator register - Store Register command */ | ||
| 3387 | #define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU) | ||
| 3388 | #define CAU_STR_CAA_ACC_SHIFT (0U) | ||
| 3389 | #define CAU_STR_CAA_ACC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK) | ||
| 3390 | #define CAU_STR_CAA_ACC CAU_STR_CAA_ACC_MASK | ||
| 3391 | |||
| 3392 | /*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */ | ||
| 3393 | #define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU) | ||
| 3394 | #define CAU_STR_CA_CA0_SHIFT (0U) | ||
| 3395 | #define CAU_STR_CA_CA0_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK) | ||
| 3396 | #define CAU_STR_CA_CA0 CAU_STR_CA_CA0_MASK | ||
| 3397 | #define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU) | ||
| 3398 | #define CAU_STR_CA_CA1_SHIFT (0U) | ||
| 3399 | #define CAU_STR_CA_CA1_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK) | ||
| 3400 | #define CAU_STR_CA_CA1 CAU_STR_CA_CA1_MASK | ||
| 3401 | #define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU) | ||
| 3402 | #define CAU_STR_CA_CA2_SHIFT (0U) | ||
| 3403 | #define CAU_STR_CA_CA2_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK) | ||
| 3404 | #define CAU_STR_CA_CA2 CAU_STR_CA_CA2_MASK | ||
| 3405 | #define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU) | ||
| 3406 | #define CAU_STR_CA_CA3_SHIFT (0U) | ||
| 3407 | #define CAU_STR_CA_CA3_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK) | ||
| 3408 | #define CAU_STR_CA_CA3 CAU_STR_CA_CA3_MASK | ||
| 3409 | #define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU) | ||
| 3410 | #define CAU_STR_CA_CA4_SHIFT (0U) | ||
| 3411 | #define CAU_STR_CA_CA4_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK) | ||
| 3412 | #define CAU_STR_CA_CA4 CAU_STR_CA_CA4_MASK | ||
| 3413 | #define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU) | ||
| 3414 | #define CAU_STR_CA_CA5_SHIFT (0U) | ||
| 3415 | #define CAU_STR_CA_CA5_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK) | ||
| 3416 | #define CAU_STR_CA_CA5 CAU_STR_CA_CA5_MASK | ||
| 3417 | #define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU) | ||
| 3418 | #define CAU_STR_CA_CA6_SHIFT (0U) | ||
| 3419 | #define CAU_STR_CA_CA6_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK) | ||
| 3420 | #define CAU_STR_CA_CA6 CAU_STR_CA_CA6_MASK | ||
| 3421 | #define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU) | ||
| 3422 | #define CAU_STR_CA_CA7_SHIFT (0U) | ||
| 3423 | #define CAU_STR_CA_CA7_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK) | ||
| 3424 | #define CAU_STR_CA_CA7 CAU_STR_CA_CA7_MASK | ||
| 3425 | #define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU) | ||
| 3426 | #define CAU_STR_CA_CA8_SHIFT (0U) | ||
| 3427 | #define CAU_STR_CA_CA8_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK) | ||
| 3428 | #define CAU_STR_CA_CA8 CAU_STR_CA_CA8_MASK | ||
| 3429 | |||
| 3430 | /* The count of CAU_STR_CA */ | ||
| 3431 | #define CAU_STR_CA_COUNT (9U) | ||
| 3432 | |||
| 3433 | /*! @name ADR_CASR - Status register - Add Register command */ | ||
| 3434 | #define CAU_ADR_CASR_IC_MASK (0x1U) | ||
| 3435 | #define CAU_ADR_CASR_IC_SHIFT (0U) | ||
| 3436 | #define CAU_ADR_CASR_IC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK) | ||
| 3437 | #define CAU_ADR_CASR_IC CAU_ADR_CASR_IC_MASK | ||
| 3438 | #define CAU_ADR_CASR_DPE_MASK (0x2U) | ||
| 3439 | #define CAU_ADR_CASR_DPE_SHIFT (1U) | ||
| 3440 | #define CAU_ADR_CASR_DPE_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK) | ||
| 3441 | #define CAU_ADR_CASR_DPE CAU_ADR_CASR_DPE_MASK | ||
| 3442 | #define CAU_ADR_CASR_VER_MASK (0xF0000000U) | ||
| 3443 | #define CAU_ADR_CASR_VER_SHIFT (28U) | ||
| 3444 | #define CAU_ADR_CASR_VER_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK) | ||
| 3445 | #define CAU_ADR_CASR_VER CAU_ADR_CASR_VER_MASK | ||
| 3446 | |||
| 3447 | /*! @name ADR_CAA - Accumulator register - Add to register command */ | ||
| 3448 | #define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU) | ||
| 3449 | #define CAU_ADR_CAA_ACC_SHIFT (0U) | ||
| 3450 | #define CAU_ADR_CAA_ACC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK) | ||
| 3451 | #define CAU_ADR_CAA_ACC CAU_ADR_CAA_ACC_MASK | ||
| 3452 | |||
| 3453 | /*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */ | ||
| 3454 | #define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU) | ||
| 3455 | #define CAU_ADR_CA_CA0_SHIFT (0U) | ||
| 3456 | #define CAU_ADR_CA_CA0_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK) | ||
| 3457 | #define CAU_ADR_CA_CA0 CAU_ADR_CA_CA0_MASK | ||
| 3458 | #define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU) | ||
| 3459 | #define CAU_ADR_CA_CA1_SHIFT (0U) | ||
| 3460 | #define CAU_ADR_CA_CA1_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK) | ||
| 3461 | #define CAU_ADR_CA_CA1 CAU_ADR_CA_CA1_MASK | ||
| 3462 | #define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU) | ||
| 3463 | #define CAU_ADR_CA_CA2_SHIFT (0U) | ||
| 3464 | #define CAU_ADR_CA_CA2_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK) | ||
| 3465 | #define CAU_ADR_CA_CA2 CAU_ADR_CA_CA2_MASK | ||
| 3466 | #define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU) | ||
| 3467 | #define CAU_ADR_CA_CA3_SHIFT (0U) | ||
| 3468 | #define CAU_ADR_CA_CA3_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK) | ||
| 3469 | #define CAU_ADR_CA_CA3 CAU_ADR_CA_CA3_MASK | ||
| 3470 | #define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU) | ||
| 3471 | #define CAU_ADR_CA_CA4_SHIFT (0U) | ||
| 3472 | #define CAU_ADR_CA_CA4_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK) | ||
| 3473 | #define CAU_ADR_CA_CA4 CAU_ADR_CA_CA4_MASK | ||
| 3474 | #define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU) | ||
| 3475 | #define CAU_ADR_CA_CA5_SHIFT (0U) | ||
| 3476 | #define CAU_ADR_CA_CA5_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK) | ||
| 3477 | #define CAU_ADR_CA_CA5 CAU_ADR_CA_CA5_MASK | ||
| 3478 | #define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU) | ||
| 3479 | #define CAU_ADR_CA_CA6_SHIFT (0U) | ||
| 3480 | #define CAU_ADR_CA_CA6_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK) | ||
| 3481 | #define CAU_ADR_CA_CA6 CAU_ADR_CA_CA6_MASK | ||
| 3482 | #define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU) | ||
| 3483 | #define CAU_ADR_CA_CA7_SHIFT (0U) | ||
| 3484 | #define CAU_ADR_CA_CA7_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK) | ||
| 3485 | #define CAU_ADR_CA_CA7 CAU_ADR_CA_CA7_MASK | ||
| 3486 | #define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU) | ||
| 3487 | #define CAU_ADR_CA_CA8_SHIFT (0U) | ||
| 3488 | #define CAU_ADR_CA_CA8_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK) | ||
| 3489 | #define CAU_ADR_CA_CA8 CAU_ADR_CA_CA8_MASK | ||
| 3490 | |||
| 3491 | /* The count of CAU_ADR_CA */ | ||
| 3492 | #define CAU_ADR_CA_COUNT (9U) | ||
| 3493 | |||
| 3494 | /*! @name RADR_CASR - Status register - Reverse and Add to Register command */ | ||
| 3495 | #define CAU_RADR_CASR_IC_MASK (0x1U) | ||
| 3496 | #define CAU_RADR_CASR_IC_SHIFT (0U) | ||
| 3497 | #define CAU_RADR_CASR_IC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK) | ||
| 3498 | #define CAU_RADR_CASR_IC CAU_RADR_CASR_IC_MASK | ||
| 3499 | #define CAU_RADR_CASR_DPE_MASK (0x2U) | ||
| 3500 | #define CAU_RADR_CASR_DPE_SHIFT (1U) | ||
| 3501 | #define CAU_RADR_CASR_DPE_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK) | ||
| 3502 | #define CAU_RADR_CASR_DPE CAU_RADR_CASR_DPE_MASK | ||
| 3503 | #define CAU_RADR_CASR_VER_MASK (0xF0000000U) | ||
| 3504 | #define CAU_RADR_CASR_VER_SHIFT (28U) | ||
| 3505 | #define CAU_RADR_CASR_VER_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK) | ||
| 3506 | #define CAU_RADR_CASR_VER CAU_RADR_CASR_VER_MASK | ||
| 3507 | |||
| 3508 | /*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */ | ||
| 3509 | #define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU) | ||
| 3510 | #define CAU_RADR_CAA_ACC_SHIFT (0U) | ||
| 3511 | #define CAU_RADR_CAA_ACC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK) | ||
| 3512 | #define CAU_RADR_CAA_ACC CAU_RADR_CAA_ACC_MASK | ||
| 3513 | |||
| 3514 | /*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */ | ||
| 3515 | #define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU) | ||
| 3516 | #define CAU_RADR_CA_CA0_SHIFT (0U) | ||
| 3517 | #define CAU_RADR_CA_CA0_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK) | ||
| 3518 | #define CAU_RADR_CA_CA0 CAU_RADR_CA_CA0_MASK | ||
| 3519 | #define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU) | ||
| 3520 | #define CAU_RADR_CA_CA1_SHIFT (0U) | ||
| 3521 | #define CAU_RADR_CA_CA1_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK) | ||
| 3522 | #define CAU_RADR_CA_CA1 CAU_RADR_CA_CA1_MASK | ||
| 3523 | #define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU) | ||
| 3524 | #define CAU_RADR_CA_CA2_SHIFT (0U) | ||
| 3525 | #define CAU_RADR_CA_CA2_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK) | ||
| 3526 | #define CAU_RADR_CA_CA2 CAU_RADR_CA_CA2_MASK | ||
| 3527 | #define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU) | ||
| 3528 | #define CAU_RADR_CA_CA3_SHIFT (0U) | ||
| 3529 | #define CAU_RADR_CA_CA3_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK) | ||
| 3530 | #define CAU_RADR_CA_CA3 CAU_RADR_CA_CA3_MASK | ||
| 3531 | #define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU) | ||
| 3532 | #define CAU_RADR_CA_CA4_SHIFT (0U) | ||
| 3533 | #define CAU_RADR_CA_CA4_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK) | ||
| 3534 | #define CAU_RADR_CA_CA4 CAU_RADR_CA_CA4_MASK | ||
| 3535 | #define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU) | ||
| 3536 | #define CAU_RADR_CA_CA5_SHIFT (0U) | ||
| 3537 | #define CAU_RADR_CA_CA5_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK) | ||
| 3538 | #define CAU_RADR_CA_CA5 CAU_RADR_CA_CA5_MASK | ||
| 3539 | #define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU) | ||
| 3540 | #define CAU_RADR_CA_CA6_SHIFT (0U) | ||
| 3541 | #define CAU_RADR_CA_CA6_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK) | ||
| 3542 | #define CAU_RADR_CA_CA6 CAU_RADR_CA_CA6_MASK | ||
| 3543 | #define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU) | ||
| 3544 | #define CAU_RADR_CA_CA7_SHIFT (0U) | ||
| 3545 | #define CAU_RADR_CA_CA7_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK) | ||
| 3546 | #define CAU_RADR_CA_CA7 CAU_RADR_CA_CA7_MASK | ||
| 3547 | #define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU) | ||
| 3548 | #define CAU_RADR_CA_CA8_SHIFT (0U) | ||
| 3549 | #define CAU_RADR_CA_CA8_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK) | ||
| 3550 | #define CAU_RADR_CA_CA8 CAU_RADR_CA_CA8_MASK | ||
| 3551 | |||
| 3552 | /* The count of CAU_RADR_CA */ | ||
| 3553 | #define CAU_RADR_CA_COUNT (9U) | ||
| 3554 | |||
| 3555 | /*! @name XOR_CASR - Status register - Exclusive Or command */ | ||
| 3556 | #define CAU_XOR_CASR_IC_MASK (0x1U) | ||
| 3557 | #define CAU_XOR_CASR_IC_SHIFT (0U) | ||
| 3558 | #define CAU_XOR_CASR_IC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK) | ||
| 3559 | #define CAU_XOR_CASR_IC CAU_XOR_CASR_IC_MASK | ||
| 3560 | #define CAU_XOR_CASR_DPE_MASK (0x2U) | ||
| 3561 | #define CAU_XOR_CASR_DPE_SHIFT (1U) | ||
| 3562 | #define CAU_XOR_CASR_DPE_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK) | ||
| 3563 | #define CAU_XOR_CASR_DPE CAU_XOR_CASR_DPE_MASK | ||
| 3564 | #define CAU_XOR_CASR_VER_MASK (0xF0000000U) | ||
| 3565 | #define CAU_XOR_CASR_VER_SHIFT (28U) | ||
| 3566 | #define CAU_XOR_CASR_VER_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK) | ||
| 3567 | #define CAU_XOR_CASR_VER CAU_XOR_CASR_VER_MASK | ||
| 3568 | |||
| 3569 | /*! @name XOR_CAA - Accumulator register - Exclusive Or command */ | ||
| 3570 | #define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU) | ||
| 3571 | #define CAU_XOR_CAA_ACC_SHIFT (0U) | ||
| 3572 | #define CAU_XOR_CAA_ACC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK) | ||
| 3573 | #define CAU_XOR_CAA_ACC CAU_XOR_CAA_ACC_MASK | ||
| 3574 | |||
| 3575 | /*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */ | ||
| 3576 | #define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU) | ||
| 3577 | #define CAU_XOR_CA_CA0_SHIFT (0U) | ||
| 3578 | #define CAU_XOR_CA_CA0_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK) | ||
| 3579 | #define CAU_XOR_CA_CA0 CAU_XOR_CA_CA0_MASK | ||
| 3580 | #define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU) | ||
| 3581 | #define CAU_XOR_CA_CA1_SHIFT (0U) | ||
| 3582 | #define CAU_XOR_CA_CA1_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK) | ||
| 3583 | #define CAU_XOR_CA_CA1 CAU_XOR_CA_CA1_MASK | ||
| 3584 | #define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU) | ||
| 3585 | #define CAU_XOR_CA_CA2_SHIFT (0U) | ||
| 3586 | #define CAU_XOR_CA_CA2_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK) | ||
| 3587 | #define CAU_XOR_CA_CA2 CAU_XOR_CA_CA2_MASK | ||
| 3588 | #define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU) | ||
| 3589 | #define CAU_XOR_CA_CA3_SHIFT (0U) | ||
| 3590 | #define CAU_XOR_CA_CA3_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK) | ||
| 3591 | #define CAU_XOR_CA_CA3 CAU_XOR_CA_CA3_MASK | ||
| 3592 | #define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU) | ||
| 3593 | #define CAU_XOR_CA_CA4_SHIFT (0U) | ||
| 3594 | #define CAU_XOR_CA_CA4_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK) | ||
| 3595 | #define CAU_XOR_CA_CA4 CAU_XOR_CA_CA4_MASK | ||
| 3596 | #define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU) | ||
| 3597 | #define CAU_XOR_CA_CA5_SHIFT (0U) | ||
| 3598 | #define CAU_XOR_CA_CA5_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK) | ||
| 3599 | #define CAU_XOR_CA_CA5 CAU_XOR_CA_CA5_MASK | ||
| 3600 | #define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU) | ||
| 3601 | #define CAU_XOR_CA_CA6_SHIFT (0U) | ||
| 3602 | #define CAU_XOR_CA_CA6_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK) | ||
| 3603 | #define CAU_XOR_CA_CA6 CAU_XOR_CA_CA6_MASK | ||
| 3604 | #define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU) | ||
| 3605 | #define CAU_XOR_CA_CA7_SHIFT (0U) | ||
| 3606 | #define CAU_XOR_CA_CA7_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK) | ||
| 3607 | #define CAU_XOR_CA_CA7 CAU_XOR_CA_CA7_MASK | ||
| 3608 | #define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU) | ||
| 3609 | #define CAU_XOR_CA_CA8_SHIFT (0U) | ||
| 3610 | #define CAU_XOR_CA_CA8_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK) | ||
| 3611 | #define CAU_XOR_CA_CA8 CAU_XOR_CA_CA8_MASK | ||
| 3612 | |||
| 3613 | /* The count of CAU_XOR_CA */ | ||
| 3614 | #define CAU_XOR_CA_COUNT (9U) | ||
| 3615 | |||
| 3616 | /*! @name ROTL_CASR - Status register - Rotate Left command */ | ||
| 3617 | #define CAU_ROTL_CASR_IC_MASK (0x1U) | ||
| 3618 | #define CAU_ROTL_CASR_IC_SHIFT (0U) | ||
| 3619 | #define CAU_ROTL_CASR_IC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK) | ||
| 3620 | #define CAU_ROTL_CASR_IC CAU_ROTL_CASR_IC_MASK | ||
| 3621 | #define CAU_ROTL_CASR_DPE_MASK (0x2U) | ||
| 3622 | #define CAU_ROTL_CASR_DPE_SHIFT (1U) | ||
| 3623 | #define CAU_ROTL_CASR_DPE_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK) | ||
| 3624 | #define CAU_ROTL_CASR_DPE CAU_ROTL_CASR_DPE_MASK | ||
| 3625 | #define CAU_ROTL_CASR_VER_MASK (0xF0000000U) | ||
| 3626 | #define CAU_ROTL_CASR_VER_SHIFT (28U) | ||
| 3627 | #define CAU_ROTL_CASR_VER_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK) | ||
| 3628 | #define CAU_ROTL_CASR_VER CAU_ROTL_CASR_VER_MASK | ||
| 3629 | |||
| 3630 | /*! @name ROTL_CAA - Accumulator register - Rotate Left command */ | ||
| 3631 | #define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU) | ||
| 3632 | #define CAU_ROTL_CAA_ACC_SHIFT (0U) | ||
| 3633 | #define CAU_ROTL_CAA_ACC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK) | ||
| 3634 | #define CAU_ROTL_CAA_ACC CAU_ROTL_CAA_ACC_MASK | ||
| 3635 | |||
| 3636 | /*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */ | ||
| 3637 | #define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU) | ||
| 3638 | #define CAU_ROTL_CA_CA0_SHIFT (0U) | ||
| 3639 | #define CAU_ROTL_CA_CA0_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK) | ||
| 3640 | #define CAU_ROTL_CA_CA0 CAU_ROTL_CA_CA0_MASK | ||
| 3641 | #define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU) | ||
| 3642 | #define CAU_ROTL_CA_CA1_SHIFT (0U) | ||
| 3643 | #define CAU_ROTL_CA_CA1_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK) | ||
| 3644 | #define CAU_ROTL_CA_CA1 CAU_ROTL_CA_CA1_MASK | ||
| 3645 | #define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU) | ||
| 3646 | #define CAU_ROTL_CA_CA2_SHIFT (0U) | ||
| 3647 | #define CAU_ROTL_CA_CA2_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK) | ||
| 3648 | #define CAU_ROTL_CA_CA2 CAU_ROTL_CA_CA2_MASK | ||
| 3649 | #define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU) | ||
| 3650 | #define CAU_ROTL_CA_CA3_SHIFT (0U) | ||
| 3651 | #define CAU_ROTL_CA_CA3_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK) | ||
| 3652 | #define CAU_ROTL_CA_CA3 CAU_ROTL_CA_CA3_MASK | ||
| 3653 | #define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU) | ||
| 3654 | #define CAU_ROTL_CA_CA4_SHIFT (0U) | ||
| 3655 | #define CAU_ROTL_CA_CA4_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK) | ||
| 3656 | #define CAU_ROTL_CA_CA4 CAU_ROTL_CA_CA4_MASK | ||
| 3657 | #define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU) | ||
| 3658 | #define CAU_ROTL_CA_CA5_SHIFT (0U) | ||
| 3659 | #define CAU_ROTL_CA_CA5_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK) | ||
| 3660 | #define CAU_ROTL_CA_CA5 CAU_ROTL_CA_CA5_MASK | ||
| 3661 | #define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU) | ||
| 3662 | #define CAU_ROTL_CA_CA6_SHIFT (0U) | ||
| 3663 | #define CAU_ROTL_CA_CA6_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK) | ||
| 3664 | #define CAU_ROTL_CA_CA6 CAU_ROTL_CA_CA6_MASK | ||
| 3665 | #define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU) | ||
| 3666 | #define CAU_ROTL_CA_CA7_SHIFT (0U) | ||
| 3667 | #define CAU_ROTL_CA_CA7_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK) | ||
| 3668 | #define CAU_ROTL_CA_CA7 CAU_ROTL_CA_CA7_MASK | ||
| 3669 | #define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU) | ||
| 3670 | #define CAU_ROTL_CA_CA8_SHIFT (0U) | ||
| 3671 | #define CAU_ROTL_CA_CA8_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK) | ||
| 3672 | #define CAU_ROTL_CA_CA8 CAU_ROTL_CA_CA8_MASK | ||
| 3673 | |||
| 3674 | /* The count of CAU_ROTL_CA */ | ||
| 3675 | #define CAU_ROTL_CA_COUNT (9U) | ||
| 3676 | |||
| 3677 | /*! @name AESC_CASR - Status register - AES Column Operation command */ | ||
| 3678 | #define CAU_AESC_CASR_IC_MASK (0x1U) | ||
| 3679 | #define CAU_AESC_CASR_IC_SHIFT (0U) | ||
| 3680 | #define CAU_AESC_CASR_IC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK) | ||
| 3681 | #define CAU_AESC_CASR_IC CAU_AESC_CASR_IC_MASK | ||
| 3682 | #define CAU_AESC_CASR_DPE_MASK (0x2U) | ||
| 3683 | #define CAU_AESC_CASR_DPE_SHIFT (1U) | ||
| 3684 | #define CAU_AESC_CASR_DPE_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK) | ||
| 3685 | #define CAU_AESC_CASR_DPE CAU_AESC_CASR_DPE_MASK | ||
| 3686 | #define CAU_AESC_CASR_VER_MASK (0xF0000000U) | ||
| 3687 | #define CAU_AESC_CASR_VER_SHIFT (28U) | ||
| 3688 | #define CAU_AESC_CASR_VER_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK) | ||
| 3689 | #define CAU_AESC_CASR_VER CAU_AESC_CASR_VER_MASK | ||
| 3690 | |||
| 3691 | /*! @name AESC_CAA - Accumulator register - AES Column Operation command */ | ||
| 3692 | #define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU) | ||
| 3693 | #define CAU_AESC_CAA_ACC_SHIFT (0U) | ||
| 3694 | #define CAU_AESC_CAA_ACC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK) | ||
| 3695 | #define CAU_AESC_CAA_ACC CAU_AESC_CAA_ACC_MASK | ||
| 3696 | |||
| 3697 | /*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */ | ||
| 3698 | #define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU) | ||
| 3699 | #define CAU_AESC_CA_CA0_SHIFT (0U) | ||
| 3700 | #define CAU_AESC_CA_CA0_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK) | ||
| 3701 | #define CAU_AESC_CA_CA0 CAU_AESC_CA_CA0_MASK | ||
| 3702 | #define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU) | ||
| 3703 | #define CAU_AESC_CA_CA1_SHIFT (0U) | ||
| 3704 | #define CAU_AESC_CA_CA1_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK) | ||
| 3705 | #define CAU_AESC_CA_CA1 CAU_AESC_CA_CA1_MASK | ||
| 3706 | #define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU) | ||
| 3707 | #define CAU_AESC_CA_CA2_SHIFT (0U) | ||
| 3708 | #define CAU_AESC_CA_CA2_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK) | ||
| 3709 | #define CAU_AESC_CA_CA2 CAU_AESC_CA_CA2_MASK | ||
| 3710 | #define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU) | ||
| 3711 | #define CAU_AESC_CA_CA3_SHIFT (0U) | ||
| 3712 | #define CAU_AESC_CA_CA3_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK) | ||
| 3713 | #define CAU_AESC_CA_CA3 CAU_AESC_CA_CA3_MASK | ||
| 3714 | #define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU) | ||
| 3715 | #define CAU_AESC_CA_CA4_SHIFT (0U) | ||
| 3716 | #define CAU_AESC_CA_CA4_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK) | ||
| 3717 | #define CAU_AESC_CA_CA4 CAU_AESC_CA_CA4_MASK | ||
| 3718 | #define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU) | ||
| 3719 | #define CAU_AESC_CA_CA5_SHIFT (0U) | ||
| 3720 | #define CAU_AESC_CA_CA5_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK) | ||
| 3721 | #define CAU_AESC_CA_CA5 CAU_AESC_CA_CA5_MASK | ||
| 3722 | #define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU) | ||
| 3723 | #define CAU_AESC_CA_CA6_SHIFT (0U) | ||
| 3724 | #define CAU_AESC_CA_CA6_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK) | ||
| 3725 | #define CAU_AESC_CA_CA6 CAU_AESC_CA_CA6_MASK | ||
| 3726 | #define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU) | ||
| 3727 | #define CAU_AESC_CA_CA7_SHIFT (0U) | ||
| 3728 | #define CAU_AESC_CA_CA7_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK) | ||
| 3729 | #define CAU_AESC_CA_CA7 CAU_AESC_CA_CA7_MASK | ||
| 3730 | #define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU) | ||
| 3731 | #define CAU_AESC_CA_CA8_SHIFT (0U) | ||
| 3732 | #define CAU_AESC_CA_CA8_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK) | ||
| 3733 | #define CAU_AESC_CA_CA8 CAU_AESC_CA_CA8_MASK | ||
| 3734 | |||
| 3735 | /* The count of CAU_AESC_CA */ | ||
| 3736 | #define CAU_AESC_CA_COUNT (9U) | ||
| 3737 | |||
| 3738 | /*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */ | ||
| 3739 | #define CAU_AESIC_CASR_IC_MASK (0x1U) | ||
| 3740 | #define CAU_AESIC_CASR_IC_SHIFT (0U) | ||
| 3741 | #define CAU_AESIC_CASR_IC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK) | ||
| 3742 | #define CAU_AESIC_CASR_IC CAU_AESIC_CASR_IC_MASK | ||
| 3743 | #define CAU_AESIC_CASR_DPE_MASK (0x2U) | ||
| 3744 | #define CAU_AESIC_CASR_DPE_SHIFT (1U) | ||
| 3745 | #define CAU_AESIC_CASR_DPE_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK) | ||
| 3746 | #define CAU_AESIC_CASR_DPE CAU_AESIC_CASR_DPE_MASK | ||
| 3747 | #define CAU_AESIC_CASR_VER_MASK (0xF0000000U) | ||
| 3748 | #define CAU_AESIC_CASR_VER_SHIFT (28U) | ||
| 3749 | #define CAU_AESIC_CASR_VER_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK) | ||
| 3750 | #define CAU_AESIC_CASR_VER CAU_AESIC_CASR_VER_MASK | ||
| 3751 | |||
| 3752 | /*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */ | ||
| 3753 | #define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU) | ||
| 3754 | #define CAU_AESIC_CAA_ACC_SHIFT (0U) | ||
| 3755 | #define CAU_AESIC_CAA_ACC_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK) | ||
| 3756 | #define CAU_AESIC_CAA_ACC CAU_AESIC_CAA_ACC_MASK | ||
| 3757 | |||
| 3758 | /*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */ | ||
| 3759 | #define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU) | ||
| 3760 | #define CAU_AESIC_CA_CA0_SHIFT (0U) | ||
| 3761 | #define CAU_AESIC_CA_CA0_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK) | ||
| 3762 | #define CAU_AESIC_CA_CA0 CAU_AESIC_CA_CA0_MASK | ||
| 3763 | #define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU) | ||
| 3764 | #define CAU_AESIC_CA_CA1_SHIFT (0U) | ||
| 3765 | #define CAU_AESIC_CA_CA1_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK) | ||
| 3766 | #define CAU_AESIC_CA_CA1 CAU_AESIC_CA_CA1_MASK | ||
| 3767 | #define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU) | ||
| 3768 | #define CAU_AESIC_CA_CA2_SHIFT (0U) | ||
| 3769 | #define CAU_AESIC_CA_CA2_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK) | ||
| 3770 | #define CAU_AESIC_CA_CA2 CAU_AESIC_CA_CA2_MASK | ||
| 3771 | #define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU) | ||
| 3772 | #define CAU_AESIC_CA_CA3_SHIFT (0U) | ||
| 3773 | #define CAU_AESIC_CA_CA3_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK) | ||
| 3774 | #define CAU_AESIC_CA_CA3 CAU_AESIC_CA_CA3_MASK | ||
| 3775 | #define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU) | ||
| 3776 | #define CAU_AESIC_CA_CA4_SHIFT (0U) | ||
| 3777 | #define CAU_AESIC_CA_CA4_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK) | ||
| 3778 | #define CAU_AESIC_CA_CA4 CAU_AESIC_CA_CA4_MASK | ||
| 3779 | #define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU) | ||
| 3780 | #define CAU_AESIC_CA_CA5_SHIFT (0U) | ||
| 3781 | #define CAU_AESIC_CA_CA5_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK) | ||
| 3782 | #define CAU_AESIC_CA_CA5 CAU_AESIC_CA_CA5_MASK | ||
| 3783 | #define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU) | ||
| 3784 | #define CAU_AESIC_CA_CA6_SHIFT (0U) | ||
| 3785 | #define CAU_AESIC_CA_CA6_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK) | ||
| 3786 | #define CAU_AESIC_CA_CA6 CAU_AESIC_CA_CA6_MASK | ||
| 3787 | #define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU) | ||
| 3788 | #define CAU_AESIC_CA_CA7_SHIFT (0U) | ||
| 3789 | #define CAU_AESIC_CA_CA7_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK) | ||
| 3790 | #define CAU_AESIC_CA_CA7 CAU_AESIC_CA_CA7_MASK | ||
| 3791 | #define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU) | ||
| 3792 | #define CAU_AESIC_CA_CA8_SHIFT (0U) | ||
| 3793 | #define CAU_AESIC_CA_CA8_SET(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK) | ||
| 3794 | #define CAU_AESIC_CA_CA8 CAU_AESIC_CA_CA8_MASK | ||
| 3795 | |||
| 3796 | /* The count of CAU_AESIC_CA */ | ||
| 3797 | #define CAU_AESIC_CA_COUNT (9U) | ||
| 3798 | |||
| 3799 | |||
| 3800 | /*! | ||
| 3801 | * @} | ||
| 3802 | */ /* end of group CAU_Register_Masks */ | ||
| 3803 | |||
| 3804 | |||
| 3805 | /* CAU - Peripheral instance base addresses */ | ||
| 3806 | /** Peripheral CAU base address */ | ||
| 3807 | #define CAU_BASE (0xE0081000u) | ||
| 3808 | /** Peripheral CAU base pointer */ | ||
| 3809 | #define CAU ((CAU_TypeDef *)CAU_BASE) | ||
| 3810 | /** Array initializer of CAU peripheral base addresses */ | ||
| 3811 | #define CAU_BASE_ADDRS { CAU_BASE } | ||
| 3812 | /** Array initializer of CAU peripheral base pointers */ | ||
| 3813 | #define CAU_BASE_PTRS { CAU } | ||
| 3814 | |||
| 3815 | /*! | ||
| 3816 | * @} | ||
| 3817 | */ /* end of group CAU_Peripheral_Access_Layer */ | ||
| 3818 | |||
| 3819 | |||
| 3820 | /* ---------------------------------------------------------------------------- | ||
| 3821 | -- CMP Peripheral Access Layer | ||
| 3822 | ---------------------------------------------------------------------------- */ | ||
| 3823 | |||
| 3824 | /*! | ||
| 3825 | * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer | ||
| 3826 | * @{ | ||
| 3827 | */ | ||
| 3828 | |||
| 3829 | /** CMP - Register Layout Typedef */ | ||
| 3830 | typedef struct { | ||
| 3831 | __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ | ||
| 3832 | __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ | ||
| 3833 | __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ | ||
| 3834 | __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ | ||
| 3835 | __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ | ||
| 3836 | __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ | ||
| 3837 | } CMP_TypeDef; | ||
| 3838 | |||
| 3839 | /* ---------------------------------------------------------------------------- | ||
| 3840 | -- CMP Register Masks | ||
| 3841 | ---------------------------------------------------------------------------- */ | ||
| 3842 | |||
| 3843 | /*! | ||
| 3844 | * @addtogroup CMP_Register_Masks CMP Register Masks | ||
| 3845 | * @{ | ||
| 3846 | */ | ||
| 3847 | |||
| 3848 | /*! @name CR0 - CMP Control Register 0 */ | ||
| 3849 | #define CMP_CR0_HYSTCTR_MASK (0x3U) | ||
| 3850 | #define CMP_CR0_HYSTCTR_SHIFT (0U) | ||
| 3851 | #define CMP_CR0_HYSTCTR_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) | ||
| 3852 | #define CMP_CR0_HYSTCTR CMP_CR0_HYSTCTR_MASK | ||
| 3853 | #define CMP_CR0_FILTER_CNT_MASK (0x70U) | ||
| 3854 | #define CMP_CR0_FILTER_CNT_SHIFT (4U) | ||
| 3855 | #define CMP_CR0_FILTER_CNT_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) | ||
| 3856 | #define CMP_CR0_FILTER_CNT CMP_CR0_FILTER_CNT_MASK | ||
| 3857 | |||
| 3858 | /*! @name CR1 - CMP Control Register 1 */ | ||
| 3859 | #define CMP_CR1_EN_MASK (0x1U) | ||
| 3860 | #define CMP_CR1_EN_SHIFT (0U) | ||
| 3861 | #define CMP_CR1_EN_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) | ||
| 3862 | #define CMP_CR1_EN CMP_CR1_EN_MASK | ||
| 3863 | #define CMP_CR1_OPE_MASK (0x2U) | ||
| 3864 | #define CMP_CR1_OPE_SHIFT (1U) | ||
| 3865 | #define CMP_CR1_OPE_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) | ||
| 3866 | #define CMP_CR1_OPE CMP_CR1_OPE_MASK | ||
| 3867 | #define CMP_CR1_COS_MASK (0x4U) | ||
| 3868 | #define CMP_CR1_COS_SHIFT (2U) | ||
| 3869 | #define CMP_CR1_COS_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) | ||
| 3870 | #define CMP_CR1_COS CMP_CR1_COS_MASK | ||
| 3871 | #define CMP_CR1_INV_MASK (0x8U) | ||
| 3872 | #define CMP_CR1_INV_SHIFT (3U) | ||
| 3873 | #define CMP_CR1_INV_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) | ||
| 3874 | #define CMP_CR1_INV CMP_CR1_INV_MASK | ||
| 3875 | #define CMP_CR1_PMODE_MASK (0x10U) | ||
| 3876 | #define CMP_CR1_PMODE_SHIFT (4U) | ||
| 3877 | #define CMP_CR1_PMODE_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) | ||
| 3878 | #define CMP_CR1_PMODE CMP_CR1_PMODE_MASK | ||
| 3879 | #define CMP_CR1_TRIGM_MASK (0x20U) | ||
| 3880 | #define CMP_CR1_TRIGM_SHIFT (5U) | ||
| 3881 | #define CMP_CR1_TRIGM_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK) | ||
| 3882 | #define CMP_CR1_TRIGM CMP_CR1_TRIGM_MASK | ||
| 3883 | #define CMP_CR1_WE_MASK (0x40U) | ||
| 3884 | #define CMP_CR1_WE_SHIFT (6U) | ||
| 3885 | #define CMP_CR1_WE_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) | ||
| 3886 | #define CMP_CR1_WE CMP_CR1_WE_MASK | ||
| 3887 | #define CMP_CR1_SE_MASK (0x80U) | ||
| 3888 | #define CMP_CR1_SE_SHIFT (7U) | ||
| 3889 | #define CMP_CR1_SE_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) | ||
| 3890 | #define CMP_CR1_SE CMP_CR1_SE_MASK | ||
| 3891 | |||
| 3892 | /*! @name FPR - CMP Filter Period Register */ | ||
| 3893 | #define CMP_FPR_FILT_PER_MASK (0xFFU) | ||
| 3894 | #define CMP_FPR_FILT_PER_SHIFT (0U) | ||
| 3895 | #define CMP_FPR_FILT_PER_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) | ||
| 3896 | #define CMP_FPR_FILT_PER CMP_FPR_FILT_PER_MASK | ||
| 3897 | |||
| 3898 | /*! @name SCR - CMP Status and Control Register */ | ||
| 3899 | #define CMP_SCR_COUT_MASK (0x1U) | ||
| 3900 | #define CMP_SCR_COUT_SHIFT (0U) | ||
| 3901 | #define CMP_SCR_COUT_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) | ||
| 3902 | #define CMP_SCR_COUT CMP_SCR_COUT_MASK | ||
| 3903 | #define CMP_SCR_CFF_MASK (0x2U) | ||
| 3904 | #define CMP_SCR_CFF_SHIFT (1U) | ||
| 3905 | #define CMP_SCR_CFF_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) | ||
| 3906 | #define CMP_SCR_CFF CMP_SCR_CFF_MASK | ||
| 3907 | #define CMP_SCR_CFR_MASK (0x4U) | ||
| 3908 | #define CMP_SCR_CFR_SHIFT (2U) | ||
| 3909 | #define CMP_SCR_CFR_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) | ||
| 3910 | #define CMP_SCR_CFR CMP_SCR_CFR_MASK | ||
| 3911 | #define CMP_SCR_IEF_MASK (0x8U) | ||
| 3912 | #define CMP_SCR_IEF_SHIFT (3U) | ||
| 3913 | #define CMP_SCR_IEF_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) | ||
| 3914 | #define CMP_SCR_IEF CMP_SCR_IEF_MASK | ||
| 3915 | #define CMP_SCR_IER_MASK (0x10U) | ||
| 3916 | #define CMP_SCR_IER_SHIFT (4U) | ||
| 3917 | #define CMP_SCR_IER_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) | ||
| 3918 | #define CMP_SCR_IER CMP_SCR_IER_MASK | ||
| 3919 | #define CMP_SCR_DMAEN_MASK (0x40U) | ||
| 3920 | #define CMP_SCR_DMAEN_SHIFT (6U) | ||
| 3921 | #define CMP_SCR_DMAEN_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) | ||
| 3922 | #define CMP_SCR_DMAEN CMP_SCR_DMAEN_MASK | ||
| 3923 | |||
| 3924 | /*! @name DACCR - DAC Control Register */ | ||
| 3925 | #define CMP_DACCR_VOSEL_MASK (0x3FU) | ||
| 3926 | #define CMP_DACCR_VOSEL_SHIFT (0U) | ||
| 3927 | #define CMP_DACCR_VOSEL_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) | ||
| 3928 | #define CMP_DACCR_VOSEL CMP_DACCR_VOSEL_MASK | ||
| 3929 | #define CMP_DACCR_VRSEL_MASK (0x40U) | ||
| 3930 | #define CMP_DACCR_VRSEL_SHIFT (6U) | ||
| 3931 | #define CMP_DACCR_VRSEL_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) | ||
| 3932 | #define CMP_DACCR_VRSEL CMP_DACCR_VRSEL_MASK | ||
| 3933 | #define CMP_DACCR_DACEN_MASK (0x80U) | ||
| 3934 | #define CMP_DACCR_DACEN_SHIFT (7U) | ||
| 3935 | #define CMP_DACCR_DACEN_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) | ||
| 3936 | #define CMP_DACCR_DACEN CMP_DACCR_DACEN_MASK | ||
| 3937 | |||
| 3938 | /*! @name MUXCR - MUX Control Register */ | ||
| 3939 | #define CMP_MUXCR_MSEL_MASK (0x7U) | ||
| 3940 | #define CMP_MUXCR_MSEL_SHIFT (0U) | ||
| 3941 | #define CMP_MUXCR_MSEL_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) | ||
| 3942 | #define CMP_MUXCR_MSEL CMP_MUXCR_MSEL_MASK | ||
| 3943 | #define CMP_MUXCR_PSEL_MASK (0x38U) | ||
| 3944 | #define CMP_MUXCR_PSEL_SHIFT (3U) | ||
| 3945 | #define CMP_MUXCR_PSEL_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) | ||
| 3946 | #define CMP_MUXCR_PSEL CMP_MUXCR_PSEL_MASK | ||
| 3947 | #define CMP_MUXCR_PSTM_MASK (0x80U) | ||
| 3948 | #define CMP_MUXCR_PSTM_SHIFT (7U) | ||
| 3949 | #define CMP_MUXCR_PSTM_SET(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK) | ||
| 3950 | #define CMP_MUXCR_PSTM CMP_MUXCR_PSTM_MASK | ||
| 3951 | |||
| 3952 | |||
| 3953 | /*! | ||
| 3954 | * @} | ||
| 3955 | */ /* end of group CMP_Register_Masks */ | ||
| 3956 | |||
| 3957 | |||
| 3958 | /* CMP - Peripheral instance base addresses */ | ||
| 3959 | /** Peripheral CMP0 base address */ | ||
| 3960 | #define CMP0_BASE (0x40073000u) | ||
| 3961 | /** Peripheral CMP0 base pointer */ | ||
| 3962 | #define CMP0 ((CMP_TypeDef *)CMP0_BASE) | ||
| 3963 | /** Peripheral CMP1 base address */ | ||
| 3964 | #define CMP1_BASE (0x40073008u) | ||
| 3965 | /** Peripheral CMP1 base pointer */ | ||
| 3966 | #define CMP1 ((CMP_TypeDef *)CMP1_BASE) | ||
| 3967 | /** Peripheral CMP2 base address */ | ||
| 3968 | #define CMP2_BASE (0x40073010u) | ||
| 3969 | /** Peripheral CMP2 base pointer */ | ||
| 3970 | #define CMP2 ((CMP_TypeDef *)CMP2_BASE) | ||
| 3971 | /** Peripheral CMP3 base address */ | ||
| 3972 | #define CMP3_BASE (0x40073018u) | ||
| 3973 | /** Peripheral CMP3 base pointer */ | ||
| 3974 | #define CMP3 ((CMP_TypeDef *)CMP3_BASE) | ||
| 3975 | /** Array initializer of CMP peripheral base addresses */ | ||
| 3976 | #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE } | ||
| 3977 | /** Array initializer of CMP peripheral base pointers */ | ||
| 3978 | #define CMP_BASE_PTRS { CMP0, CMP1, CMP2, CMP3 } | ||
| 3979 | /** Interrupt vectors for the CMP peripheral type */ | ||
| 3980 | #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn, CMP3_IRQn } | ||
| 3981 | |||
| 3982 | /*! | ||
| 3983 | * @} | ||
| 3984 | */ /* end of group CMP_Peripheral_Access_Layer */ | ||
| 3985 | |||
| 3986 | |||
| 3987 | /* ---------------------------------------------------------------------------- | ||
| 3988 | -- CMT Peripheral Access Layer | ||
| 3989 | ---------------------------------------------------------------------------- */ | ||
| 3990 | |||
| 3991 | /*! | ||
| 3992 | * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer | ||
| 3993 | * @{ | ||
| 3994 | */ | ||
| 3995 | |||
| 3996 | /** CMT - Register Layout Typedef */ | ||
| 3997 | typedef struct { | ||
| 3998 | __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */ | ||
| 3999 | __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */ | ||
| 4000 | __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */ | ||
| 4001 | __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */ | ||
| 4002 | __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */ | ||
| 4003 | __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */ | ||
| 4004 | __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */ | ||
| 4005 | __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */ | ||
| 4006 | __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */ | ||
| 4007 | __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */ | ||
| 4008 | __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */ | ||
| 4009 | __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */ | ||
| 4010 | } CMT_TypeDef; | ||
| 4011 | |||
| 4012 | /* ---------------------------------------------------------------------------- | ||
| 4013 | -- CMT Register Masks | ||
| 4014 | ---------------------------------------------------------------------------- */ | ||
| 4015 | |||
| 4016 | /*! | ||
| 4017 | * @addtogroup CMT_Register_Masks CMT Register Masks | ||
| 4018 | * @{ | ||
| 4019 | */ | ||
| 4020 | |||
| 4021 | /*! @name CGH1 - CMT Carrier Generator High Data Register 1 */ | ||
| 4022 | #define CMT_CGH1_PH_MASK (0xFFU) | ||
| 4023 | #define CMT_CGH1_PH_SHIFT (0U) | ||
| 4024 | #define CMT_CGH1_PH_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK) | ||
| 4025 | #define CMT_CGH1_PH CMT_CGH1_PH_MASK | ||
| 4026 | |||
| 4027 | /*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */ | ||
| 4028 | #define CMT_CGL1_PL_MASK (0xFFU) | ||
| 4029 | #define CMT_CGL1_PL_SHIFT (0U) | ||
| 4030 | #define CMT_CGL1_PL_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK) | ||
| 4031 | #define CMT_CGL1_PL CMT_CGL1_PL_MASK | ||
| 4032 | |||
| 4033 | /*! @name CGH2 - CMT Carrier Generator High Data Register 2 */ | ||
| 4034 | #define CMT_CGH2_SH_MASK (0xFFU) | ||
| 4035 | #define CMT_CGH2_SH_SHIFT (0U) | ||
| 4036 | #define CMT_CGH2_SH_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK) | ||
| 4037 | #define CMT_CGH2_SH CMT_CGH2_SH_MASK | ||
| 4038 | |||
| 4039 | /*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */ | ||
| 4040 | #define CMT_CGL2_SL_MASK (0xFFU) | ||
| 4041 | #define CMT_CGL2_SL_SHIFT (0U) | ||
| 4042 | #define CMT_CGL2_SL_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK) | ||
| 4043 | #define CMT_CGL2_SL CMT_CGL2_SL_MASK | ||
| 4044 | |||
| 4045 | /*! @name OC - CMT Output Control Register */ | ||
| 4046 | #define CMT_OC_IROPEN_MASK (0x20U) | ||
| 4047 | #define CMT_OC_IROPEN_SHIFT (5U) | ||
| 4048 | #define CMT_OC_IROPEN_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK) | ||
| 4049 | #define CMT_OC_IROPEN CMT_OC_IROPEN_MASK | ||
| 4050 | #define CMT_OC_CMTPOL_MASK (0x40U) | ||
| 4051 | #define CMT_OC_CMTPOL_SHIFT (6U) | ||
| 4052 | #define CMT_OC_CMTPOL_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK) | ||
| 4053 | #define CMT_OC_CMTPOL CMT_OC_CMTPOL_MASK | ||
| 4054 | #define CMT_OC_IROL_MASK (0x80U) | ||
| 4055 | #define CMT_OC_IROL_SHIFT (7U) | ||
| 4056 | #define CMT_OC_IROL_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK) | ||
| 4057 | #define CMT_OC_IROL CMT_OC_IROL_MASK | ||
| 4058 | |||
| 4059 | /*! @name MSC - CMT Modulator Status and Control Register */ | ||
| 4060 | #define CMT_MSC_MCGEN_MASK (0x1U) | ||
| 4061 | #define CMT_MSC_MCGEN_SHIFT (0U) | ||
| 4062 | #define CMT_MSC_MCGEN_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK) | ||
| 4063 | #define CMT_MSC_MCGEN CMT_MSC_MCGEN_MASK | ||
| 4064 | #define CMT_MSC_EOCIE_MASK (0x2U) | ||
| 4065 | #define CMT_MSC_EOCIE_SHIFT (1U) | ||
| 4066 | #define CMT_MSC_EOCIE_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK) | ||
| 4067 | #define CMT_MSC_EOCIE CMT_MSC_EOCIE_MASK | ||
| 4068 | #define CMT_MSC_FSK_MASK (0x4U) | ||
| 4069 | #define CMT_MSC_FSK_SHIFT (2U) | ||
| 4070 | #define CMT_MSC_FSK_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK) | ||
| 4071 | #define CMT_MSC_FSK CMT_MSC_FSK_MASK | ||
| 4072 | #define CMT_MSC_BASE_MASK (0x8U) | ||
| 4073 | #define CMT_MSC_BASE_SHIFT (3U) | ||
| 4074 | #define CMT_MSC_BASE_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK) | ||
| 4075 | #define CMT_MSC_BASE CMT_MSC_BASE_MASK | ||
| 4076 | #define CMT_MSC_EXSPC_MASK (0x10U) | ||
| 4077 | #define CMT_MSC_EXSPC_SHIFT (4U) | ||
| 4078 | #define CMT_MSC_EXSPC_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK) | ||
| 4079 | #define CMT_MSC_EXSPC CMT_MSC_EXSPC_MASK | ||
| 4080 | #define CMT_MSC_CMTDIV_MASK (0x60U) | ||
| 4081 | #define CMT_MSC_CMTDIV_SHIFT (5U) | ||
| 4082 | #define CMT_MSC_CMTDIV_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK) | ||
| 4083 | #define CMT_MSC_CMTDIV CMT_MSC_CMTDIV_MASK | ||
| 4084 | #define CMT_MSC_EOCF_MASK (0x80U) | ||
| 4085 | #define CMT_MSC_EOCF_SHIFT (7U) | ||
| 4086 | #define CMT_MSC_EOCF_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK) | ||
| 4087 | #define CMT_MSC_EOCF CMT_MSC_EOCF_MASK | ||
| 4088 | |||
| 4089 | /*! @name CMD1 - CMT Modulator Data Register Mark High */ | ||
| 4090 | #define CMT_CMD1_MB_MASK (0xFFU) | ||
| 4091 | #define CMT_CMD1_MB_SHIFT (0U) | ||
| 4092 | #define CMT_CMD1_MB_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK) | ||
| 4093 | #define CMT_CMD1_MB CMT_CMD1_MB_MASK | ||
| 4094 | |||
| 4095 | /*! @name CMD2 - CMT Modulator Data Register Mark Low */ | ||
| 4096 | #define CMT_CMD2_MB_MASK (0xFFU) | ||
| 4097 | #define CMT_CMD2_MB_SHIFT (0U) | ||
| 4098 | #define CMT_CMD2_MB_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK) | ||
| 4099 | #define CMT_CMD2_MB CMT_CMD2_MB_MASK | ||
| 4100 | |||
| 4101 | /*! @name CMD3 - CMT Modulator Data Register Space High */ | ||
| 4102 | #define CMT_CMD3_SB_MASK (0xFFU) | ||
| 4103 | #define CMT_CMD3_SB_SHIFT (0U) | ||
| 4104 | #define CMT_CMD3_SB_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK) | ||
| 4105 | #define CMT_CMD3_SB CMT_CMD3_SB_MASK | ||
| 4106 | |||
| 4107 | /*! @name CMD4 - CMT Modulator Data Register Space Low */ | ||
| 4108 | #define CMT_CMD4_SB_MASK (0xFFU) | ||
| 4109 | #define CMT_CMD4_SB_SHIFT (0U) | ||
| 4110 | #define CMT_CMD4_SB_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK) | ||
| 4111 | #define CMT_CMD4_SB CMT_CMD4_SB_MASK | ||
| 4112 | |||
| 4113 | /*! @name PPS - CMT Primary Prescaler Register */ | ||
| 4114 | #define CMT_PPS_PPSDIV_MASK (0xFU) | ||
| 4115 | #define CMT_PPS_PPSDIV_SHIFT (0U) | ||
| 4116 | #define CMT_PPS_PPSDIV_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK) | ||
| 4117 | #define CMT_PPS_PPSDIV CMT_PPS_PPSDIV_MASK | ||
| 4118 | |||
| 4119 | /*! @name DMA - CMT Direct Memory Access Register */ | ||
| 4120 | #define CMT_DMA_DMA_MASK (0x1U) | ||
| 4121 | #define CMT_DMA_DMA_SHIFT (0U) | ||
| 4122 | #define CMT_DMA_DMA_SET(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK) | ||
| 4123 | #define CMT_DMA_DMA CMT_DMA_DMA_MASK | ||
| 4124 | |||
| 4125 | |||
| 4126 | /*! | ||
| 4127 | * @} | ||
| 4128 | */ /* end of group CMT_Register_Masks */ | ||
| 4129 | |||
| 4130 | |||
| 4131 | /* CMT - Peripheral instance base addresses */ | ||
| 4132 | /** Peripheral CMT base address */ | ||
| 4133 | #define CMT_BASE (0x40062000u) | ||
| 4134 | /** Peripheral CMT base pointer */ | ||
| 4135 | #define CMT ((CMT_TypeDef *)CMT_BASE) | ||
| 4136 | /** Array initializer of CMT peripheral base addresses */ | ||
| 4137 | #define CMT_BASE_ADDRS { CMT_BASE } | ||
| 4138 | /** Array initializer of CMT peripheral base pointers */ | ||
| 4139 | #define CMT_BASE_PTRS { CMT } | ||
| 4140 | /** Interrupt vectors for the CMT peripheral type */ | ||
| 4141 | #define CMT_IRQS { CMT_IRQn } | ||
| 4142 | |||
| 4143 | /*! | ||
| 4144 | * @} | ||
| 4145 | */ /* end of group CMT_Peripheral_Access_Layer */ | ||
| 4146 | |||
| 4147 | |||
| 4148 | /* ---------------------------------------------------------------------------- | ||
| 4149 | -- CRC Peripheral Access Layer | ||
| 4150 | ---------------------------------------------------------------------------- */ | ||
| 4151 | |||
| 4152 | /*! | ||
| 4153 | * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer | ||
| 4154 | * @{ | ||
| 4155 | */ | ||
| 4156 | |||
| 4157 | /** CRC - Register Layout Typedef */ | ||
| 4158 | typedef struct { | ||
| 4159 | union { /* offset: 0x0 */ | ||
| 4160 | struct { /* offset: 0x0 */ | ||
| 4161 | __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */ | ||
| 4162 | __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */ | ||
| 4163 | } ACCESS16BIT; | ||
| 4164 | __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ | ||
| 4165 | struct { /* offset: 0x0 */ | ||
| 4166 | __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */ | ||
| 4167 | __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */ | ||
| 4168 | __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */ | ||
| 4169 | __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */ | ||
| 4170 | } ACCESS8BIT; | ||
| 4171 | }; | ||
| 4172 | union { /* offset: 0x4 */ | ||
| 4173 | struct { /* offset: 0x4 */ | ||
| 4174 | __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ | ||
| 4175 | __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ | ||
| 4176 | } GPOLY_ACCESS16BIT; | ||
| 4177 | __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ | ||
| 4178 | struct { /* offset: 0x4 */ | ||
| 4179 | __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ | ||
| 4180 | __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ | ||
| 4181 | __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ | ||
| 4182 | __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ | ||
| 4183 | } GPOLY_ACCESS8BIT; | ||
| 4184 | }; | ||
| 4185 | union { /* offset: 0x8 */ | ||
| 4186 | __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ | ||
| 4187 | struct { /* offset: 0x8 */ | ||
| 4188 | uint8_t RESERVED_0[3]; | ||
| 4189 | __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ | ||
| 4190 | } CTRL_ACCESS8BIT; | ||
| 4191 | }; | ||
| 4192 | } CRC_TypeDef; | ||
| 4193 | |||
| 4194 | /* ---------------------------------------------------------------------------- | ||
| 4195 | -- CRC Register Masks | ||
| 4196 | ---------------------------------------------------------------------------- */ | ||
| 4197 | |||
| 4198 | /*! | ||
| 4199 | * @addtogroup CRC_Register_Masks CRC Register Masks | ||
| 4200 | * @{ | ||
| 4201 | */ | ||
| 4202 | |||
| 4203 | /*! @name DATAL - CRC_DATAL register. */ | ||
| 4204 | #define CRC_DATAL_DATAL_MASK (0xFFFFU) | ||
| 4205 | #define CRC_DATAL_DATAL_SHIFT (0U) | ||
| 4206 | #define CRC_DATAL_DATAL_SET(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) | ||
| 4207 | #define CRC_DATAL_DATAL CRC_DATAL_DATAL_MASK | ||
| 4208 | |||
| 4209 | /*! @name DATAH - CRC_DATAH register. */ | ||
| 4210 | #define CRC_DATAH_DATAH_MASK (0xFFFFU) | ||
| 4211 | #define CRC_DATAH_DATAH_SHIFT (0U) | ||
| 4212 | #define CRC_DATAH_DATAH_SET(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) | ||
| 4213 | #define CRC_DATAH_DATAH CRC_DATAH_DATAH_MASK | ||
| 4214 | |||
| 4215 | /*! @name DATA - CRC Data register */ | ||
| 4216 | #define CRC_DATA_LL_MASK (0xFFU) | ||
| 4217 | #define CRC_DATA_LL_SHIFT (0U) | ||
| 4218 | #define CRC_DATA_LL_SET(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) | ||
| 4219 | #define CRC_DATA_LL CRC_DATA_LL_MASK | ||
| 4220 | #define CRC_DATA_LU_MASK (0xFF00U) | ||
| 4221 | #define CRC_DATA_LU_SHIFT (8U) | ||
| 4222 | #define CRC_DATA_LU_SET(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) | ||
| 4223 | #define CRC_DATA_LU CRC_DATA_LU_MASK | ||
| 4224 | #define CRC_DATA_HL_MASK (0xFF0000U) | ||
| 4225 | #define CRC_DATA_HL_SHIFT (16U) | ||
| 4226 | #define CRC_DATA_HL_SET(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) | ||
| 4227 | #define CRC_DATA_HL CRC_DATA_HL_MASK | ||
| 4228 | #define CRC_DATA_HU_MASK (0xFF000000U) | ||
| 4229 | #define CRC_DATA_HU_SHIFT (24U) | ||
| 4230 | #define CRC_DATA_HU_SET(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) | ||
| 4231 | #define CRC_DATA_HU CRC_DATA_HU_MASK | ||
| 4232 | |||
| 4233 | /*! @name DATALL - CRC_DATALL register. */ | ||
| 4234 | #define CRC_DATALL_DATALL_MASK (0xFFU) | ||
| 4235 | #define CRC_DATALL_DATALL_SHIFT (0U) | ||
| 4236 | #define CRC_DATALL_DATALL_SET(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) | ||
| 4237 | #define CRC_DATALL_DATALL CRC_DATALL_DATALL_MASK | ||
| 4238 | |||
| 4239 | /*! @name DATALU - CRC_DATALU register. */ | ||
| 4240 | #define CRC_DATALU_DATALU_MASK (0xFFU) | ||
| 4241 | #define CRC_DATALU_DATALU_SHIFT (0U) | ||
| 4242 | #define CRC_DATALU_DATALU_SET(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) | ||
| 4243 | #define CRC_DATALU_DATALU CRC_DATALU_DATALU_MASK | ||
| 4244 | |||
| 4245 | /*! @name DATAHL - CRC_DATAHL register. */ | ||
| 4246 | #define CRC_DATAHL_DATAHL_MASK (0xFFU) | ||
| 4247 | #define CRC_DATAHL_DATAHL_SHIFT (0U) | ||
| 4248 | #define CRC_DATAHL_DATAHL_SET(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) | ||
| 4249 | #define CRC_DATAHL_DATAHL CRC_DATAHL_DATAHL_MASK | ||
| 4250 | |||
| 4251 | /*! @name DATAHU - CRC_DATAHU register. */ | ||
| 4252 | #define CRC_DATAHU_DATAHU_MASK (0xFFU) | ||
| 4253 | #define CRC_DATAHU_DATAHU_SHIFT (0U) | ||
| 4254 | #define CRC_DATAHU_DATAHU_SET(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) | ||
| 4255 | #define CRC_DATAHU_DATAHU CRC_DATAHU_DATAHU_MASK | ||
| 4256 | |||
| 4257 | /*! @name GPOLYL - CRC_GPOLYL register. */ | ||
| 4258 | #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) | ||
| 4259 | #define CRC_GPOLYL_GPOLYL_SHIFT (0U) | ||
| 4260 | #define CRC_GPOLYL_GPOLYL_SET(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) | ||
| 4261 | #define CRC_GPOLYL_GPOLYL CRC_GPOLYL_GPOLYL_MASK | ||
| 4262 | |||
| 4263 | /*! @name GPOLYH - CRC_GPOLYH register. */ | ||
| 4264 | #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) | ||
| 4265 | #define CRC_GPOLYH_GPOLYH_SHIFT (0U) | ||
| 4266 | #define CRC_GPOLYH_GPOLYH_SET(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) | ||
| 4267 | #define CRC_GPOLYH_GPOLYH CRC_GPOLYH_GPOLYH_MASK | ||
| 4268 | |||
| 4269 | /*! @name GPOLY - CRC Polynomial register */ | ||
| 4270 | #define CRC_GPOLY_LOW_MASK (0xFFFFU) | ||
| 4271 | #define CRC_GPOLY_LOW_SHIFT (0U) | ||
| 4272 | #define CRC_GPOLY_LOW_SET(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) | ||
| 4273 | #define CRC_GPOLY_LOW CRC_GPOLY_LOW_MASK | ||
| 4274 | #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) | ||
| 4275 | #define CRC_GPOLY_HIGH_SHIFT (16U) | ||
| 4276 | #define CRC_GPOLY_HIGH_SET(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) | ||
| 4277 | #define CRC_GPOLY_HIGH CRC_GPOLY_HIGH_MASK | ||
| 4278 | |||
| 4279 | /*! @name GPOLYLL - CRC_GPOLYLL register. */ | ||
| 4280 | #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) | ||
| 4281 | #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) | ||
| 4282 | #define CRC_GPOLYLL_GPOLYLL_SET(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) | ||
| 4283 | #define CRC_GPOLYLL_GPOLYLL CRC_GPOLYLL_GPOLYLL_MASK | ||
| 4284 | |||
| 4285 | /*! @name GPOLYLU - CRC_GPOLYLU register. */ | ||
| 4286 | #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) | ||
| 4287 | #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) | ||
| 4288 | #define CRC_GPOLYLU_GPOLYLU_SET(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) | ||
| 4289 | #define CRC_GPOLYLU_GPOLYLU CRC_GPOLYLU_GPOLYLU_MASK | ||
| 4290 | |||
| 4291 | /*! @name GPOLYHL - CRC_GPOLYHL register. */ | ||
| 4292 | #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) | ||
| 4293 | #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) | ||
| 4294 | #define CRC_GPOLYHL_GPOLYHL_SET(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) | ||
| 4295 | #define CRC_GPOLYHL_GPOLYHL CRC_GPOLYHL_GPOLYHL_MASK | ||
| 4296 | |||
| 4297 | /*! @name GPOLYHU - CRC_GPOLYHU register. */ | ||
| 4298 | #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) | ||
| 4299 | #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) | ||
| 4300 | #define CRC_GPOLYHU_GPOLYHU_SET(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) | ||
| 4301 | #define CRC_GPOLYHU_GPOLYHU CRC_GPOLYHU_GPOLYHU_MASK | ||
| 4302 | |||
| 4303 | /*! @name CTRL - CRC Control register */ | ||
| 4304 | #define CRC_CTRL_TCRC_MASK (0x1000000U) | ||
| 4305 | #define CRC_CTRL_TCRC_SHIFT (24U) | ||
| 4306 | #define CRC_CTRL_TCRC_SET(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) | ||
| 4307 | #define CRC_CTRL_TCRC CRC_CTRL_TCRC_MASK | ||
| 4308 | #define CRC_CTRL_WAS_MASK (0x2000000U) | ||
| 4309 | #define CRC_CTRL_WAS_SHIFT (25U) | ||
| 4310 | #define CRC_CTRL_WAS_SET(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) | ||
| 4311 | #define CRC_CTRL_WAS CRC_CTRL_WAS_MASK | ||
| 4312 | #define CRC_CTRL_FXOR_MASK (0x4000000U) | ||
| 4313 | #define CRC_CTRL_FXOR_SHIFT (26U) | ||
| 4314 | #define CRC_CTRL_FXOR_SET(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) | ||
| 4315 | #define CRC_CTRL_FXOR CRC_CTRL_FXOR_MASK | ||
| 4316 | #define CRC_CTRL_TOTR_MASK (0x30000000U) | ||
| 4317 | #define CRC_CTRL_TOTR_SHIFT (28U) | ||
| 4318 | #define CRC_CTRL_TOTR_SET(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) | ||
| 4319 | #define CRC_CTRL_TOTR CRC_CTRL_TOTR_MASK | ||
| 4320 | #define CRC_CTRL_TOT_MASK (0xC0000000U) | ||
| 4321 | #define CRC_CTRL_TOT_SHIFT (30U) | ||
| 4322 | #define CRC_CTRL_TOT_SET(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) | ||
| 4323 | #define CRC_CTRL_TOT CRC_CTRL_TOT_MASK | ||
| 4324 | |||
| 4325 | /*! @name CTRLHU - CRC_CTRLHU register. */ | ||
| 4326 | #define CRC_CTRLHU_TCRC_MASK (0x1U) | ||
| 4327 | #define CRC_CTRLHU_TCRC_SHIFT (0U) | ||
| 4328 | #define CRC_CTRLHU_TCRC_SET(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) | ||
| 4329 | #define CRC_CTRLHU_TCRC CRC_CTRLHU_TCRC_MASK | ||
| 4330 | #define CRC_CTRLHU_WAS_MASK (0x2U) | ||
| 4331 | #define CRC_CTRLHU_WAS_SHIFT (1U) | ||
| 4332 | #define CRC_CTRLHU_WAS_SET(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) | ||
| 4333 | #define CRC_CTRLHU_WAS CRC_CTRLHU_WAS_MASK | ||
| 4334 | #define CRC_CTRLHU_FXOR_MASK (0x4U) | ||
| 4335 | #define CRC_CTRLHU_FXOR_SHIFT (2U) | ||
| 4336 | #define CRC_CTRLHU_FXOR_SET(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) | ||
| 4337 | #define CRC_CTRLHU_FXOR CRC_CTRLHU_FXOR_MASK | ||
| 4338 | #define CRC_CTRLHU_TOTR_MASK (0x30U) | ||
| 4339 | #define CRC_CTRLHU_TOTR_SHIFT (4U) | ||
| 4340 | #define CRC_CTRLHU_TOTR_SET(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) | ||
| 4341 | #define CRC_CTRLHU_TOTR CRC_CTRLHU_TOTR_MASK | ||
| 4342 | #define CRC_CTRLHU_TOT_MASK (0xC0U) | ||
| 4343 | #define CRC_CTRLHU_TOT_SHIFT (6U) | ||
| 4344 | #define CRC_CTRLHU_TOT_SET(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) | ||
| 4345 | #define CRC_CTRLHU_TOT CRC_CTRLHU_TOT_MASK | ||
| 4346 | |||
| 4347 | |||
| 4348 | /*! | ||
| 4349 | * @} | ||
| 4350 | */ /* end of group CRC_Register_Masks */ | ||
| 4351 | |||
| 4352 | |||
| 4353 | /* CRC - Peripheral instance base addresses */ | ||
| 4354 | /** Peripheral CRC base address */ | ||
| 4355 | #define CRC_BASE (0x40032000u) | ||
| 4356 | /** Peripheral CRC base pointer */ | ||
| 4357 | #define CRC0 ((CRC_TypeDef *)CRC_BASE) | ||
| 4358 | /** Array initializer of CRC peripheral base addresses */ | ||
| 4359 | #define CRC_BASE_ADDRS { CRC_BASE } | ||
| 4360 | /** Array initializer of CRC peripheral base pointers */ | ||
| 4361 | #define CRC_BASE_PTRS { CRC0 } | ||
| 4362 | |||
| 4363 | /*! | ||
| 4364 | * @} | ||
| 4365 | */ /* end of group CRC_Peripheral_Access_Layer */ | ||
| 4366 | |||
| 4367 | |||
| 4368 | /* ---------------------------------------------------------------------------- | ||
| 4369 | -- DAC Peripheral Access Layer | ||
| 4370 | ---------------------------------------------------------------------------- */ | ||
| 4371 | |||
| 4372 | /*! | ||
| 4373 | * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer | ||
| 4374 | * @{ | ||
| 4375 | */ | ||
| 4376 | |||
| 4377 | /** DAC - Register Layout Typedef */ | ||
| 4378 | typedef struct { | ||
| 4379 | struct { /* offset: 0x0, array step: 0x2 */ | ||
| 4380 | __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ | ||
| 4381 | __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ | ||
| 4382 | } DAT[16]; | ||
| 4383 | __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ | ||
| 4384 | __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ | ||
| 4385 | __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ | ||
| 4386 | __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ | ||
| 4387 | } DAC_TypeDef; | ||
| 4388 | |||
| 4389 | /* ---------------------------------------------------------------------------- | ||
| 4390 | -- DAC Register Masks | ||
| 4391 | ---------------------------------------------------------------------------- */ | ||
| 4392 | |||
| 4393 | /*! | ||
| 4394 | * @addtogroup DAC_Register_Masks DAC Register Masks | ||
| 4395 | * @{ | ||
| 4396 | */ | ||
| 4397 | |||
| 4398 | /*! @name DATL - DAC Data Low Register */ | ||
| 4399 | #define DAC_DATL_DATA0_MASK (0xFFU) | ||
| 4400 | #define DAC_DATL_DATA0_SHIFT (0U) | ||
| 4401 | #define DAC_DATL_DATA0_SET(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK) | ||
| 4402 | #define DAC_DATL_DATA0 DAC_DATL_DATA0_MASK | ||
| 4403 | |||
| 4404 | /* The count of DAC_DATL */ | ||
| 4405 | #define DAC_DATL_COUNT (16U) | ||
| 4406 | |||
| 4407 | /*! @name DATH - DAC Data High Register */ | ||
| 4408 | #define DAC_DATH_DATA1_MASK (0xFU) | ||
| 4409 | #define DAC_DATH_DATA1_SHIFT (0U) | ||
| 4410 | #define DAC_DATH_DATA1_SET(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK) | ||
| 4411 | #define DAC_DATH_DATA1 DAC_DATH_DATA1_MASK | ||
| 4412 | |||
| 4413 | /* The count of DAC_DATH */ | ||
| 4414 | #define DAC_DATH_COUNT (16U) | ||
| 4415 | |||
| 4416 | /*! @name SR - DAC Status Register */ | ||
| 4417 | #define DAC_SR_DACBFRPBF_MASK (0x1U) | ||
| 4418 | #define DAC_SR_DACBFRPBF_SHIFT (0U) | ||
| 4419 | #define DAC_SR_DACBFRPBF_SET(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK) | ||
| 4420 | #define DAC_SR_DACBFRPBF DAC_SR_DACBFRPBF_MASK | ||
| 4421 | #define DAC_SR_DACBFRPTF_MASK (0x2U) | ||
| 4422 | #define DAC_SR_DACBFRPTF_SHIFT (1U) | ||
| 4423 | #define DAC_SR_DACBFRPTF_SET(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK) | ||
| 4424 | #define DAC_SR_DACBFRPTF DAC_SR_DACBFRPTF_MASK | ||
| 4425 | #define DAC_SR_DACBFWMF_MASK (0x4U) | ||
| 4426 | #define DAC_SR_DACBFWMF_SHIFT (2U) | ||
| 4427 | #define DAC_SR_DACBFWMF_SET(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK) | ||
| 4428 | #define DAC_SR_DACBFWMF DAC_SR_DACBFWMF_MASK | ||
| 4429 | |||
| 4430 | /*! @name C0 - DAC Control Register */ | ||
| 4431 | #define DAC_C0_DACBBIEN_MASK (0x1U) | ||
| 4432 | #define DAC_C0_DACBBIEN_SHIFT (0U) | ||
| 4433 | #define DAC_C0_DACBBIEN_SET(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK) | ||
| 4434 | #define DAC_C0_DACBBIEN DAC_C0_DACBBIEN_MASK | ||
| 4435 | #define DAC_C0_DACBTIEN_MASK (0x2U) | ||
| 4436 | #define DAC_C0_DACBTIEN_SHIFT (1U) | ||
| 4437 | #define DAC_C0_DACBTIEN_SET(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK) | ||
| 4438 | #define DAC_C0_DACBTIEN DAC_C0_DACBTIEN_MASK | ||
| 4439 | #define DAC_C0_DACBWIEN_MASK (0x4U) | ||
| 4440 | #define DAC_C0_DACBWIEN_SHIFT (2U) | ||
| 4441 | #define DAC_C0_DACBWIEN_SET(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK) | ||
| 4442 | #define DAC_C0_DACBWIEN DAC_C0_DACBWIEN_MASK | ||
| 4443 | #define DAC_C0_LPEN_MASK (0x8U) | ||
| 4444 | #define DAC_C0_LPEN_SHIFT (3U) | ||
| 4445 | #define DAC_C0_LPEN_SET(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK) | ||
| 4446 | #define DAC_C0_LPEN DAC_C0_LPEN_MASK | ||
| 4447 | #define DAC_C0_DACSWTRG_MASK (0x10U) | ||
| 4448 | #define DAC_C0_DACSWTRG_SHIFT (4U) | ||
| 4449 | #define DAC_C0_DACSWTRG_SET(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK) | ||
| 4450 | #define DAC_C0_DACSWTRG DAC_C0_DACSWTRG_MASK | ||
| 4451 | #define DAC_C0_DACTRGSEL_MASK (0x20U) | ||
| 4452 | #define DAC_C0_DACTRGSEL_SHIFT (5U) | ||
| 4453 | #define DAC_C0_DACTRGSEL_SET(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK) | ||
| 4454 | #define DAC_C0_DACTRGSEL DAC_C0_DACTRGSEL_MASK | ||
| 4455 | #define DAC_C0_DACRFS_MASK (0x40U) | ||
| 4456 | #define DAC_C0_DACRFS_SHIFT (6U) | ||
| 4457 | #define DAC_C0_DACRFS_SET(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK) | ||
| 4458 | #define DAC_C0_DACRFS DAC_C0_DACRFS_MASK | ||
| 4459 | #define DAC_C0_DACEN_MASK (0x80U) | ||
| 4460 | #define DAC_C0_DACEN_SHIFT (7U) | ||
| 4461 | #define DAC_C0_DACEN_SET(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK) | ||
| 4462 | #define DAC_C0_DACEN DAC_C0_DACEN_MASK | ||
| 4463 | |||
| 4464 | /*! @name C1 - DAC Control Register 1 */ | ||
| 4465 | #define DAC_C1_DACBFEN_MASK (0x1U) | ||
| 4466 | #define DAC_C1_DACBFEN_SHIFT (0U) | ||
| 4467 | #define DAC_C1_DACBFEN_SET(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK) | ||
| 4468 | #define DAC_C1_DACBFEN DAC_C1_DACBFEN_MASK | ||
| 4469 | #define DAC_C1_DACBFMD_MASK (0x6U) | ||
| 4470 | #define DAC_C1_DACBFMD_SHIFT (1U) | ||
| 4471 | #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK) | ||
| 4472 | #define DAC_C1_DACBFWM_MASK (0x18U) | ||
| 4473 | #define DAC_C1_DACBFWM_SHIFT (3U) | ||
| 4474 | #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK) | ||
| 4475 | #define DAC_C1_DMAEN_MASK (0x80U) | ||
| 4476 | #define DAC_C1_DMAEN_SHIFT (7U) | ||
| 4477 | #define DAC_C1_DMAEN_SET(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK) | ||
| 4478 | #define DAC_C1_DMAEN DAC_C1_DMAEN_MASK | ||
| 4479 | |||
| 4480 | /*! @name C2 - DAC Control Register 2 */ | ||
| 4481 | #define DAC_C2_DACBFUP_MASK (0xFU) | ||
| 4482 | #define DAC_C2_DACBFUP_SHIFT (0U) | ||
| 4483 | #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK) | ||
| 4484 | #define DAC_C2_DACBFRP_MASK (0xF0U) | ||
| 4485 | #define DAC_C2_DACBFRP_SHIFT (4U) | ||
| 4486 | #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK) | ||
| 4487 | |||
| 4488 | |||
| 4489 | /*! | ||
| 4490 | * @} | ||
| 4491 | */ /* end of group DAC_Register_Masks */ | ||
| 4492 | |||
| 4493 | |||
| 4494 | /* DAC - Peripheral instance base addresses */ | ||
| 4495 | /** Peripheral DAC0 base address */ | ||
| 4496 | #define DAC0_BASE (0x400CC000u) | ||
| 4497 | /** Peripheral DAC0 base pointer */ | ||
| 4498 | #define DAC0 ((DAC_TypeDef *)DAC0_BASE) | ||
| 4499 | /** Peripheral DAC1 base address */ | ||
| 4500 | #define DAC1_BASE (0x400CD000u) | ||
| 4501 | /** Peripheral DAC1 base pointer */ | ||
| 4502 | #define DAC1 ((DAC_TypeDef *)DAC1_BASE) | ||
| 4503 | /** Array initializer of DAC peripheral base addresses */ | ||
| 4504 | #define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } | ||
| 4505 | /** Array initializer of DAC peripheral base pointers */ | ||
| 4506 | #define DAC_BASE_PTRS { DAC0, DAC1 } | ||
| 4507 | /** Interrupt vectors for the DAC peripheral type */ | ||
| 4508 | #define DAC_IRQS { DAC0_IRQn, DAC1_IRQn } | ||
| 4509 | |||
| 4510 | /*! | ||
| 4511 | * @} | ||
| 4512 | */ /* end of group DAC_Peripheral_Access_Layer */ | ||
| 4513 | |||
| 4514 | |||
| 4515 | /* ---------------------------------------------------------------------------- | ||
| 4516 | -- DMA Peripheral Access Layer | ||
| 4517 | ---------------------------------------------------------------------------- */ | ||
| 4518 | |||
| 4519 | /*! | ||
| 4520 | * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer | ||
| 4521 | * @{ | ||
| 4522 | */ | ||
| 4523 | |||
| 4524 | /** DMA - Register Layout Typedef */ | ||
| 4525 | typedef struct { | ||
| 4526 | __IO uint32_t CR; /**< Control Register, offset: 0x0 */ | ||
| 4527 | __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ | ||
| 4528 | uint8_t RESERVED_0[4]; | ||
| 4529 | __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ | ||
| 4530 | uint8_t RESERVED_1[4]; | ||
| 4531 | __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ | ||
| 4532 | __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ | ||
| 4533 | __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ | ||
| 4534 | __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ | ||
| 4535 | __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ | ||
| 4536 | __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ | ||
| 4537 | __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ | ||
| 4538 | __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ | ||
| 4539 | __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ | ||
| 4540 | uint8_t RESERVED_2[4]; | ||
| 4541 | __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ | ||
| 4542 | uint8_t RESERVED_3[4]; | ||
| 4543 | __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ | ||
| 4544 | uint8_t RESERVED_4[4]; | ||
| 4545 | __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ | ||
| 4546 | uint8_t RESERVED_5[12]; | ||
| 4547 | __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */ | ||
| 4548 | uint8_t RESERVED_6[184]; | ||
| 4549 | __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ | ||
| 4550 | __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ | ||
| 4551 | __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ | ||
| 4552 | __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ | ||
| 4553 | __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ | ||
| 4554 | __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ | ||
| 4555 | __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ | ||
| 4556 | __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ | ||
| 4557 | __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */ | ||
| 4558 | __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */ | ||
| 4559 | __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */ | ||
| 4560 | __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */ | ||
| 4561 | __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */ | ||
| 4562 | __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */ | ||
| 4563 | __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */ | ||
| 4564 | __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */ | ||
| 4565 | __IO uint8_t DCHPRI19; /**< Channel n Priority Register, offset: 0x110 */ | ||
| 4566 | __IO uint8_t DCHPRI18; /**< Channel n Priority Register, offset: 0x111 */ | ||
| 4567 | __IO uint8_t DCHPRI17; /**< Channel n Priority Register, offset: 0x112 */ | ||
| 4568 | __IO uint8_t DCHPRI16; /**< Channel n Priority Register, offset: 0x113 */ | ||
| 4569 | __IO uint8_t DCHPRI23; /**< Channel n Priority Register, offset: 0x114 */ | ||
| 4570 | __IO uint8_t DCHPRI22; /**< Channel n Priority Register, offset: 0x115 */ | ||
| 4571 | __IO uint8_t DCHPRI21; /**< Channel n Priority Register, offset: 0x116 */ | ||
| 4572 | __IO uint8_t DCHPRI20; /**< Channel n Priority Register, offset: 0x117 */ | ||
| 4573 | __IO uint8_t DCHPRI27; /**< Channel n Priority Register, offset: 0x118 */ | ||
| 4574 | __IO uint8_t DCHPRI26; /**< Channel n Priority Register, offset: 0x119 */ | ||
| 4575 | __IO uint8_t DCHPRI25; /**< Channel n Priority Register, offset: 0x11A */ | ||
| 4576 | __IO uint8_t DCHPRI24; /**< Channel n Priority Register, offset: 0x11B */ | ||
| 4577 | __IO uint8_t DCHPRI31; /**< Channel n Priority Register, offset: 0x11C */ | ||
| 4578 | __IO uint8_t DCHPRI30; /**< Channel n Priority Register, offset: 0x11D */ | ||
| 4579 | __IO uint8_t DCHPRI29; /**< Channel n Priority Register, offset: 0x11E */ | ||
| 4580 | __IO uint8_t DCHPRI28; /**< Channel n Priority Register, offset: 0x11F */ | ||
| 4581 | uint8_t RESERVED_7[3808]; | ||
| 4582 | struct { /* offset: 0x1000, array step: 0x20 */ | ||
| 4583 | __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ | ||
| 4584 | __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ | ||
| 4585 | __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ | ||
| 4586 | union { /* offset: 0x1008, array step: 0x20 */ | ||
| 4587 | __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ | ||
| 4588 | __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ | ||
| 4589 | __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ | ||
| 4590 | }; | ||
| 4591 | __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ | ||
| 4592 | __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ | ||
| 4593 | __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ | ||
| 4594 | union { /* offset: 0x1016, array step: 0x20 */ | ||
| 4595 | __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ | ||
| 4596 | __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ | ||
| 4597 | }; | ||
| 4598 | __IO uint32_t DLASTSGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ | ||
| 4599 | __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ | ||
| 4600 | union { /* offset: 0x101E, array step: 0x20 */ | ||
| 4601 | __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ | ||
| 4602 | __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ | ||
| 4603 | }; | ||
| 4604 | } TCD[32]; | ||
| 4605 | } DMA_TypeDef; | ||
| 4606 | |||
| 4607 | /* ---------------------------------------------------------------------------- | ||
| 4608 | -- DMA Register Masks | ||
| 4609 | ---------------------------------------------------------------------------- */ | ||
| 4610 | |||
| 4611 | /*! | ||
| 4612 | * @addtogroup DMA_Register_Masks DMA Register Masks | ||
| 4613 | * @{ | ||
| 4614 | */ | ||
| 4615 | |||
| 4616 | /*! @name CR - Control Register */ | ||
| 4617 | #define DMA_CR_EDBG_MASK (0x2U) | ||
| 4618 | #define DMA_CR_EDBG_SHIFT (1U) | ||
| 4619 | #define DMA_CR_EDBG_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) | ||
| 4620 | #define DMA_CR_EDBG DMA_CR_EDBG_MASK | ||
| 4621 | #define DMA_CR_ERCA_MASK (0x4U) | ||
| 4622 | #define DMA_CR_ERCA_SHIFT (2U) | ||
| 4623 | #define DMA_CR_ERCA_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) | ||
| 4624 | #define DMA_CR_ERCA DMA_CR_ERCA_MASK | ||
| 4625 | #define DMA_CR_ERGA_MASK (0x8U) | ||
| 4626 | #define DMA_CR_ERGA_SHIFT (3U) | ||
| 4627 | #define DMA_CR_ERGA_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK) | ||
| 4628 | #define DMA_CR_ERGA DMA_CR_ERGA_MASK | ||
| 4629 | #define DMA_CR_HOE_MASK (0x10U) | ||
| 4630 | #define DMA_CR_HOE_SHIFT (4U) | ||
| 4631 | #define DMA_CR_HOE_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) | ||
| 4632 | #define DMA_CR_HOE DMA_CR_HOE_MASK | ||
| 4633 | #define DMA_CR_HALT_MASK (0x20U) | ||
| 4634 | #define DMA_CR_HALT_SHIFT (5U) | ||
| 4635 | #define DMA_CR_HALT_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) | ||
| 4636 | #define DMA_CR_HALT DMA_CR_HALT_MASK | ||
| 4637 | #define DMA_CR_CLM_MASK (0x40U) | ||
| 4638 | #define DMA_CR_CLM_SHIFT (6U) | ||
| 4639 | #define DMA_CR_CLM_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) | ||
| 4640 | #define DMA_CR_CLM DMA_CR_CLM_MASK | ||
| 4641 | #define DMA_CR_EMLM_MASK (0x80U) | ||
| 4642 | #define DMA_CR_EMLM_SHIFT (7U) | ||
| 4643 | #define DMA_CR_EMLM_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) | ||
| 4644 | #define DMA_CR_EMLM DMA_CR_EMLM_MASK | ||
| 4645 | #define DMA_CR_GRP0PRI_MASK (0x100U) | ||
| 4646 | #define DMA_CR_GRP0PRI_SHIFT (8U) | ||
| 4647 | #define DMA_CR_GRP0PRI_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK) | ||
| 4648 | #define DMA_CR_GRP0PRI DMA_CR_GRP0PRI_MASK | ||
| 4649 | #define DMA_CR_GRP1PRI_MASK (0x400U) | ||
| 4650 | #define DMA_CR_GRP1PRI_SHIFT (10U) | ||
| 4651 | #define DMA_CR_GRP1PRI_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK) | ||
| 4652 | #define DMA_CR_GRP1PRI DMA_CR_GRP1PRI_MASK | ||
| 4653 | #define DMA_CR_ECX_MASK (0x10000U) | ||
| 4654 | #define DMA_CR_ECX_SHIFT (16U) | ||
| 4655 | #define DMA_CR_ECX_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) | ||
| 4656 | #define DMA_CR_ECX DMA_CR_ECX_MASK | ||
| 4657 | #define DMA_CR_CX_MASK (0x20000U) | ||
| 4658 | #define DMA_CR_CX_SHIFT (17U) | ||
| 4659 | #define DMA_CR_CX_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) | ||
| 4660 | #define DMA_CR_CX DMA_CR_CX_MASK | ||
| 4661 | |||
| 4662 | /*! @name ES - Error Status Register */ | ||
| 4663 | #define DMA_ES_DBE_MASK (0x1U) | ||
| 4664 | #define DMA_ES_DBE_SHIFT (0U) | ||
| 4665 | #define DMA_ES_DBE_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) | ||
| 4666 | #define DMA_ES_DBE DMA_ES_DBE_MASK | ||
| 4667 | #define DMA_ES_SBE_MASK (0x2U) | ||
| 4668 | #define DMA_ES_SBE_SHIFT (1U) | ||
| 4669 | #define DMA_ES_SBE_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) | ||
| 4670 | #define DMA_ES_SBE DMA_ES_SBE_MASK | ||
| 4671 | #define DMA_ES_SGE_MASK (0x4U) | ||
| 4672 | #define DMA_ES_SGE_SHIFT (2U) | ||
| 4673 | #define DMA_ES_SGE_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) | ||
| 4674 | #define DMA_ES_SGE DMA_ES_SGE_MASK | ||
| 4675 | #define DMA_ES_NCE_MASK (0x8U) | ||
| 4676 | #define DMA_ES_NCE_SHIFT (3U) | ||
| 4677 | #define DMA_ES_NCE_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) | ||
| 4678 | #define DMA_ES_NCE DMA_ES_NCE_MASK | ||
| 4679 | #define DMA_ES_DOE_MASK (0x10U) | ||
| 4680 | #define DMA_ES_DOE_SHIFT (4U) | ||
| 4681 | #define DMA_ES_DOE_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) | ||
| 4682 | #define DMA_ES_DOE DMA_ES_DOE_MASK | ||
| 4683 | #define DMA_ES_DAE_MASK (0x20U) | ||
| 4684 | #define DMA_ES_DAE_SHIFT (5U) | ||
| 4685 | #define DMA_ES_DAE_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) | ||
| 4686 | #define DMA_ES_DAE DMA_ES_DAE_MASK | ||
| 4687 | #define DMA_ES_SOE_MASK (0x40U) | ||
| 4688 | #define DMA_ES_SOE_SHIFT (6U) | ||
| 4689 | #define DMA_ES_SOE_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) | ||
| 4690 | #define DMA_ES_SOE DMA_ES_SOE_MASK | ||
| 4691 | #define DMA_ES_SAE_MASK (0x80U) | ||
| 4692 | #define DMA_ES_SAE_SHIFT (7U) | ||
| 4693 | #define DMA_ES_SAE_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) | ||
| 4694 | #define DMA_ES_SAE DMA_ES_SAE_MASK | ||
| 4695 | #define DMA_ES_ERRCHN_MASK (0x1F00U) | ||
| 4696 | #define DMA_ES_ERRCHN_SHIFT (8U) | ||
| 4697 | #define DMA_ES_ERRCHN_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) | ||
| 4698 | #define DMA_ES_ERRCHN DMA_ES_ERRCHN_MASK | ||
| 4699 | #define DMA_ES_CPE_MASK (0x4000U) | ||
| 4700 | #define DMA_ES_CPE_SHIFT (14U) | ||
| 4701 | #define DMA_ES_CPE_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) | ||
| 4702 | #define DMA_ES_CPE DMA_ES_CPE_MASK | ||
| 4703 | #define DMA_ES_GPE_MASK (0x8000U) | ||
| 4704 | #define DMA_ES_GPE_SHIFT (15U) | ||
| 4705 | #define DMA_ES_GPE_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK) | ||
| 4706 | #define DMA_ES_GPE DMA_ES_GPE_MASK | ||
| 4707 | #define DMA_ES_ECX_MASK (0x10000U) | ||
| 4708 | #define DMA_ES_ECX_SHIFT (16U) | ||
| 4709 | #define DMA_ES_ECX_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) | ||
| 4710 | #define DMA_ES_ECX DMA_ES_ECX_MASK | ||
| 4711 | #define DMA_ES_VLD_MASK (0x80000000U) | ||
| 4712 | #define DMA_ES_VLD_SHIFT (31U) | ||
| 4713 | #define DMA_ES_VLD_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) | ||
| 4714 | #define DMA_ES_VLD DMA_ES_VLD_MASK | ||
| 4715 | |||
| 4716 | /*! @name ERQ - Enable Request Register */ | ||
| 4717 | #define DMA_ERQ_ERQ0_MASK (0x1U) | ||
| 4718 | #define DMA_ERQ_ERQ0_SHIFT (0U) | ||
| 4719 | #define DMA_ERQ_ERQ0_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) | ||
| 4720 | #define DMA_ERQ_ERQ0 DMA_ERQ_ERQ0_MASK | ||
| 4721 | #define DMA_ERQ_ERQ1_MASK (0x2U) | ||
| 4722 | #define DMA_ERQ_ERQ1_SHIFT (1U) | ||
| 4723 | #define DMA_ERQ_ERQ1_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) | ||
| 4724 | #define DMA_ERQ_ERQ1 DMA_ERQ_ERQ1_MASK | ||
| 4725 | #define DMA_ERQ_ERQ2_MASK (0x4U) | ||
| 4726 | #define DMA_ERQ_ERQ2_SHIFT (2U) | ||
| 4727 | #define DMA_ERQ_ERQ2_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) | ||
| 4728 | #define DMA_ERQ_ERQ2 DMA_ERQ_ERQ2_MASK | ||
| 4729 | #define DMA_ERQ_ERQ3_MASK (0x8U) | ||
| 4730 | #define DMA_ERQ_ERQ3_SHIFT (3U) | ||
| 4731 | #define DMA_ERQ_ERQ3_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) | ||
| 4732 | #define DMA_ERQ_ERQ3 DMA_ERQ_ERQ3_MASK | ||
| 4733 | #define DMA_ERQ_ERQ4_MASK (0x10U) | ||
| 4734 | #define DMA_ERQ_ERQ4_SHIFT (4U) | ||
| 4735 | #define DMA_ERQ_ERQ4_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) | ||
| 4736 | #define DMA_ERQ_ERQ4 DMA_ERQ_ERQ4_MASK | ||
| 4737 | #define DMA_ERQ_ERQ5_MASK (0x20U) | ||
| 4738 | #define DMA_ERQ_ERQ5_SHIFT (5U) | ||
| 4739 | #define DMA_ERQ_ERQ5_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) | ||
| 4740 | #define DMA_ERQ_ERQ5 DMA_ERQ_ERQ5_MASK | ||
| 4741 | #define DMA_ERQ_ERQ6_MASK (0x40U) | ||
| 4742 | #define DMA_ERQ_ERQ6_SHIFT (6U) | ||
| 4743 | #define DMA_ERQ_ERQ6_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) | ||
| 4744 | #define DMA_ERQ_ERQ6 DMA_ERQ_ERQ6_MASK | ||
| 4745 | #define DMA_ERQ_ERQ7_MASK (0x80U) | ||
| 4746 | #define DMA_ERQ_ERQ7_SHIFT (7U) | ||
| 4747 | #define DMA_ERQ_ERQ7_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) | ||
| 4748 | #define DMA_ERQ_ERQ7 DMA_ERQ_ERQ7_MASK | ||
| 4749 | #define DMA_ERQ_ERQ8_MASK (0x100U) | ||
| 4750 | #define DMA_ERQ_ERQ8_SHIFT (8U) | ||
| 4751 | #define DMA_ERQ_ERQ8_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) | ||
| 4752 | #define DMA_ERQ_ERQ8 DMA_ERQ_ERQ8_MASK | ||
| 4753 | #define DMA_ERQ_ERQ9_MASK (0x200U) | ||
| 4754 | #define DMA_ERQ_ERQ9_SHIFT (9U) | ||
| 4755 | #define DMA_ERQ_ERQ9_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) | ||
| 4756 | #define DMA_ERQ_ERQ9 DMA_ERQ_ERQ9_MASK | ||
| 4757 | #define DMA_ERQ_ERQ10_MASK (0x400U) | ||
| 4758 | #define DMA_ERQ_ERQ10_SHIFT (10U) | ||
| 4759 | #define DMA_ERQ_ERQ10_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) | ||
| 4760 | #define DMA_ERQ_ERQ10 DMA_ERQ_ERQ10_MASK | ||
| 4761 | #define DMA_ERQ_ERQ11_MASK (0x800U) | ||
| 4762 | #define DMA_ERQ_ERQ11_SHIFT (11U) | ||
| 4763 | #define DMA_ERQ_ERQ11_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) | ||
| 4764 | #define DMA_ERQ_ERQ11 DMA_ERQ_ERQ11_MASK | ||
| 4765 | #define DMA_ERQ_ERQ12_MASK (0x1000U) | ||
| 4766 | #define DMA_ERQ_ERQ12_SHIFT (12U) | ||
| 4767 | #define DMA_ERQ_ERQ12_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) | ||
| 4768 | #define DMA_ERQ_ERQ12 DMA_ERQ_ERQ12_MASK | ||
| 4769 | #define DMA_ERQ_ERQ13_MASK (0x2000U) | ||
| 4770 | #define DMA_ERQ_ERQ13_SHIFT (13U) | ||
| 4771 | #define DMA_ERQ_ERQ13_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) | ||
| 4772 | #define DMA_ERQ_ERQ13 DMA_ERQ_ERQ13_MASK | ||
| 4773 | #define DMA_ERQ_ERQ14_MASK (0x4000U) | ||
| 4774 | #define DMA_ERQ_ERQ14_SHIFT (14U) | ||
| 4775 | #define DMA_ERQ_ERQ14_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) | ||
| 4776 | #define DMA_ERQ_ERQ14 DMA_ERQ_ERQ14_MASK | ||
| 4777 | #define DMA_ERQ_ERQ15_MASK (0x8000U) | ||
| 4778 | #define DMA_ERQ_ERQ15_SHIFT (15U) | ||
| 4779 | #define DMA_ERQ_ERQ15_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) | ||
| 4780 | #define DMA_ERQ_ERQ15 DMA_ERQ_ERQ15_MASK | ||
| 4781 | #define DMA_ERQ_ERQ16_MASK (0x10000U) | ||
| 4782 | #define DMA_ERQ_ERQ16_SHIFT (16U) | ||
| 4783 | #define DMA_ERQ_ERQ16_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK) | ||
| 4784 | #define DMA_ERQ_ERQ16 DMA_ERQ_ERQ16_MASK | ||
| 4785 | #define DMA_ERQ_ERQ17_MASK (0x20000U) | ||
| 4786 | #define DMA_ERQ_ERQ17_SHIFT (17U) | ||
| 4787 | #define DMA_ERQ_ERQ17_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK) | ||
| 4788 | #define DMA_ERQ_ERQ17 DMA_ERQ_ERQ17_MASK | ||
| 4789 | #define DMA_ERQ_ERQ18_MASK (0x40000U) | ||
| 4790 | #define DMA_ERQ_ERQ18_SHIFT (18U) | ||
| 4791 | #define DMA_ERQ_ERQ18_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK) | ||
| 4792 | #define DMA_ERQ_ERQ18 DMA_ERQ_ERQ18_MASK | ||
| 4793 | #define DMA_ERQ_ERQ19_MASK (0x80000U) | ||
| 4794 | #define DMA_ERQ_ERQ19_SHIFT (19U) | ||
| 4795 | #define DMA_ERQ_ERQ19_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK) | ||
| 4796 | #define DMA_ERQ_ERQ19 DMA_ERQ_ERQ19_MASK | ||
| 4797 | #define DMA_ERQ_ERQ20_MASK (0x100000U) | ||
| 4798 | #define DMA_ERQ_ERQ20_SHIFT (20U) | ||
| 4799 | #define DMA_ERQ_ERQ20_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK) | ||
| 4800 | #define DMA_ERQ_ERQ20 DMA_ERQ_ERQ20_MASK | ||
| 4801 | #define DMA_ERQ_ERQ21_MASK (0x200000U) | ||
| 4802 | #define DMA_ERQ_ERQ21_SHIFT (21U) | ||
| 4803 | #define DMA_ERQ_ERQ21_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK) | ||
| 4804 | #define DMA_ERQ_ERQ21 DMA_ERQ_ERQ21_MASK | ||
| 4805 | #define DMA_ERQ_ERQ22_MASK (0x400000U) | ||
| 4806 | #define DMA_ERQ_ERQ22_SHIFT (22U) | ||
| 4807 | #define DMA_ERQ_ERQ22_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK) | ||
| 4808 | #define DMA_ERQ_ERQ22 DMA_ERQ_ERQ22_MASK | ||
| 4809 | #define DMA_ERQ_ERQ23_MASK (0x800000U) | ||
| 4810 | #define DMA_ERQ_ERQ23_SHIFT (23U) | ||
| 4811 | #define DMA_ERQ_ERQ23_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK) | ||
| 4812 | #define DMA_ERQ_ERQ23 DMA_ERQ_ERQ23_MASK | ||
| 4813 | #define DMA_ERQ_ERQ24_MASK (0x1000000U) | ||
| 4814 | #define DMA_ERQ_ERQ24_SHIFT (24U) | ||
| 4815 | #define DMA_ERQ_ERQ24_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK) | ||
| 4816 | #define DMA_ERQ_ERQ24 DMA_ERQ_ERQ24_MASK | ||
| 4817 | #define DMA_ERQ_ERQ25_MASK (0x2000000U) | ||
| 4818 | #define DMA_ERQ_ERQ25_SHIFT (25U) | ||
| 4819 | #define DMA_ERQ_ERQ25_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK) | ||
| 4820 | #define DMA_ERQ_ERQ25 DMA_ERQ_ERQ25_MASK | ||
| 4821 | #define DMA_ERQ_ERQ26_MASK (0x4000000U) | ||
| 4822 | #define DMA_ERQ_ERQ26_SHIFT (26U) | ||
| 4823 | #define DMA_ERQ_ERQ26_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK) | ||
| 4824 | #define DMA_ERQ_ERQ26 DMA_ERQ_ERQ26_MASK | ||
| 4825 | #define DMA_ERQ_ERQ27_MASK (0x8000000U) | ||
| 4826 | #define DMA_ERQ_ERQ27_SHIFT (27U) | ||
| 4827 | #define DMA_ERQ_ERQ27_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK) | ||
| 4828 | #define DMA_ERQ_ERQ27 DMA_ERQ_ERQ27_MASK | ||
| 4829 | #define DMA_ERQ_ERQ28_MASK (0x10000000U) | ||
| 4830 | #define DMA_ERQ_ERQ28_SHIFT (28U) | ||
| 4831 | #define DMA_ERQ_ERQ28_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK) | ||
| 4832 | #define DMA_ERQ_ERQ28 DMA_ERQ_ERQ28_MASK | ||
| 4833 | #define DMA_ERQ_ERQ29_MASK (0x20000000U) | ||
| 4834 | #define DMA_ERQ_ERQ29_SHIFT (29U) | ||
| 4835 | #define DMA_ERQ_ERQ29_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK) | ||
| 4836 | #define DMA_ERQ_ERQ29 DMA_ERQ_ERQ29_MASK | ||
| 4837 | #define DMA_ERQ_ERQ30_MASK (0x40000000U) | ||
| 4838 | #define DMA_ERQ_ERQ30_SHIFT (30U) | ||
| 4839 | #define DMA_ERQ_ERQ30_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK) | ||
| 4840 | #define DMA_ERQ_ERQ30 DMA_ERQ_ERQ30_MASK | ||
| 4841 | #define DMA_ERQ_ERQ31_MASK (0x80000000U) | ||
| 4842 | #define DMA_ERQ_ERQ31_SHIFT (31U) | ||
| 4843 | #define DMA_ERQ_ERQ31_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK) | ||
| 4844 | #define DMA_ERQ_ERQ31 DMA_ERQ_ERQ31_MASK | ||
| 4845 | |||
| 4846 | /*! @name EEI - Enable Error Interrupt Register */ | ||
| 4847 | #define DMA_EEI_EEI0_MASK (0x1U) | ||
| 4848 | #define DMA_EEI_EEI0_SHIFT (0U) | ||
| 4849 | #define DMA_EEI_EEI0_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) | ||
| 4850 | #define DMA_EEI_EEI0 DMA_EEI_EEI0_MASK | ||
| 4851 | #define DMA_EEI_EEI1_MASK (0x2U) | ||
| 4852 | #define DMA_EEI_EEI1_SHIFT (1U) | ||
| 4853 | #define DMA_EEI_EEI1_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) | ||
| 4854 | #define DMA_EEI_EEI1 DMA_EEI_EEI1_MASK | ||
| 4855 | #define DMA_EEI_EEI2_MASK (0x4U) | ||
| 4856 | #define DMA_EEI_EEI2_SHIFT (2U) | ||
| 4857 | #define DMA_EEI_EEI2_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) | ||
| 4858 | #define DMA_EEI_EEI2 DMA_EEI_EEI2_MASK | ||
| 4859 | #define DMA_EEI_EEI3_MASK (0x8U) | ||
| 4860 | #define DMA_EEI_EEI3_SHIFT (3U) | ||
| 4861 | #define DMA_EEI_EEI3_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) | ||
| 4862 | #define DMA_EEI_EEI3 DMA_EEI_EEI3_MASK | ||
| 4863 | #define DMA_EEI_EEI4_MASK (0x10U) | ||
| 4864 | #define DMA_EEI_EEI4_SHIFT (4U) | ||
| 4865 | #define DMA_EEI_EEI4_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) | ||
| 4866 | #define DMA_EEI_EEI4 DMA_EEI_EEI4_MASK | ||
| 4867 | #define DMA_EEI_EEI5_MASK (0x20U) | ||
| 4868 | #define DMA_EEI_EEI5_SHIFT (5U) | ||
| 4869 | #define DMA_EEI_EEI5_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) | ||
| 4870 | #define DMA_EEI_EEI5 DMA_EEI_EEI5_MASK | ||
| 4871 | #define DMA_EEI_EEI6_MASK (0x40U) | ||
| 4872 | #define DMA_EEI_EEI6_SHIFT (6U) | ||
| 4873 | #define DMA_EEI_EEI6_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) | ||
| 4874 | #define DMA_EEI_EEI6 DMA_EEI_EEI6_MASK | ||
| 4875 | #define DMA_EEI_EEI7_MASK (0x80U) | ||
| 4876 | #define DMA_EEI_EEI7_SHIFT (7U) | ||
| 4877 | #define DMA_EEI_EEI7_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) | ||
| 4878 | #define DMA_EEI_EEI7 DMA_EEI_EEI7_MASK | ||
| 4879 | #define DMA_EEI_EEI8_MASK (0x100U) | ||
| 4880 | #define DMA_EEI_EEI8_SHIFT (8U) | ||
| 4881 | #define DMA_EEI_EEI8_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) | ||
| 4882 | #define DMA_EEI_EEI8 DMA_EEI_EEI8_MASK | ||
| 4883 | #define DMA_EEI_EEI9_MASK (0x200U) | ||
| 4884 | #define DMA_EEI_EEI9_SHIFT (9U) | ||
| 4885 | #define DMA_EEI_EEI9_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) | ||
| 4886 | #define DMA_EEI_EEI9 DMA_EEI_EEI9_MASK | ||
| 4887 | #define DMA_EEI_EEI10_MASK (0x400U) | ||
| 4888 | #define DMA_EEI_EEI10_SHIFT (10U) | ||
| 4889 | #define DMA_EEI_EEI10_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) | ||
| 4890 | #define DMA_EEI_EEI10 DMA_EEI_EEI10_MASK | ||
| 4891 | #define DMA_EEI_EEI11_MASK (0x800U) | ||
| 4892 | #define DMA_EEI_EEI11_SHIFT (11U) | ||
| 4893 | #define DMA_EEI_EEI11_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) | ||
| 4894 | #define DMA_EEI_EEI11 DMA_EEI_EEI11_MASK | ||
| 4895 | #define DMA_EEI_EEI12_MASK (0x1000U) | ||
| 4896 | #define DMA_EEI_EEI12_SHIFT (12U) | ||
| 4897 | #define DMA_EEI_EEI12_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) | ||
| 4898 | #define DMA_EEI_EEI12 DMA_EEI_EEI12_MASK | ||
| 4899 | #define DMA_EEI_EEI13_MASK (0x2000U) | ||
| 4900 | #define DMA_EEI_EEI13_SHIFT (13U) | ||
| 4901 | #define DMA_EEI_EEI13_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) | ||
| 4902 | #define DMA_EEI_EEI13 DMA_EEI_EEI13_MASK | ||
| 4903 | #define DMA_EEI_EEI14_MASK (0x4000U) | ||
| 4904 | #define DMA_EEI_EEI14_SHIFT (14U) | ||
| 4905 | #define DMA_EEI_EEI14_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) | ||
| 4906 | #define DMA_EEI_EEI14 DMA_EEI_EEI14_MASK | ||
| 4907 | #define DMA_EEI_EEI15_MASK (0x8000U) | ||
| 4908 | #define DMA_EEI_EEI15_SHIFT (15U) | ||
| 4909 | #define DMA_EEI_EEI15_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) | ||
| 4910 | #define DMA_EEI_EEI15 DMA_EEI_EEI15_MASK | ||
| 4911 | #define DMA_EEI_EEI16_MASK (0x10000U) | ||
| 4912 | #define DMA_EEI_EEI16_SHIFT (16U) | ||
| 4913 | #define DMA_EEI_EEI16_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK) | ||
| 4914 | #define DMA_EEI_EEI16 DMA_EEI_EEI16_MASK | ||
| 4915 | #define DMA_EEI_EEI17_MASK (0x20000U) | ||
| 4916 | #define DMA_EEI_EEI17_SHIFT (17U) | ||
| 4917 | #define DMA_EEI_EEI17_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK) | ||
| 4918 | #define DMA_EEI_EEI17 DMA_EEI_EEI17_MASK | ||
| 4919 | #define DMA_EEI_EEI18_MASK (0x40000U) | ||
| 4920 | #define DMA_EEI_EEI18_SHIFT (18U) | ||
| 4921 | #define DMA_EEI_EEI18_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK) | ||
| 4922 | #define DMA_EEI_EEI18 DMA_EEI_EEI18_MASK | ||
| 4923 | #define DMA_EEI_EEI19_MASK (0x80000U) | ||
| 4924 | #define DMA_EEI_EEI19_SHIFT (19U) | ||
| 4925 | #define DMA_EEI_EEI19_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK) | ||
| 4926 | #define DMA_EEI_EEI19 DMA_EEI_EEI19_MASK | ||
| 4927 | #define DMA_EEI_EEI20_MASK (0x100000U) | ||
| 4928 | #define DMA_EEI_EEI20_SHIFT (20U) | ||
| 4929 | #define DMA_EEI_EEI20_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK) | ||
| 4930 | #define DMA_EEI_EEI20 DMA_EEI_EEI20_MASK | ||
| 4931 | #define DMA_EEI_EEI21_MASK (0x200000U) | ||
| 4932 | #define DMA_EEI_EEI21_SHIFT (21U) | ||
| 4933 | #define DMA_EEI_EEI21_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK) | ||
| 4934 | #define DMA_EEI_EEI21 DMA_EEI_EEI21_MASK | ||
| 4935 | #define DMA_EEI_EEI22_MASK (0x400000U) | ||
| 4936 | #define DMA_EEI_EEI22_SHIFT (22U) | ||
| 4937 | #define DMA_EEI_EEI22_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK) | ||
| 4938 | #define DMA_EEI_EEI22 DMA_EEI_EEI22_MASK | ||
| 4939 | #define DMA_EEI_EEI23_MASK (0x800000U) | ||
| 4940 | #define DMA_EEI_EEI23_SHIFT (23U) | ||
| 4941 | #define DMA_EEI_EEI23_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK) | ||
| 4942 | #define DMA_EEI_EEI23 DMA_EEI_EEI23_MASK | ||
| 4943 | #define DMA_EEI_EEI24_MASK (0x1000000U) | ||
| 4944 | #define DMA_EEI_EEI24_SHIFT (24U) | ||
| 4945 | #define DMA_EEI_EEI24_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK) | ||
| 4946 | #define DMA_EEI_EEI24 DMA_EEI_EEI24_MASK | ||
| 4947 | #define DMA_EEI_EEI25_MASK (0x2000000U) | ||
| 4948 | #define DMA_EEI_EEI25_SHIFT (25U) | ||
| 4949 | #define DMA_EEI_EEI25_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK) | ||
| 4950 | #define DMA_EEI_EEI25 DMA_EEI_EEI25_MASK | ||
| 4951 | #define DMA_EEI_EEI26_MASK (0x4000000U) | ||
| 4952 | #define DMA_EEI_EEI26_SHIFT (26U) | ||
| 4953 | #define DMA_EEI_EEI26_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK) | ||
| 4954 | #define DMA_EEI_EEI26 DMA_EEI_EEI26_MASK | ||
| 4955 | #define DMA_EEI_EEI27_MASK (0x8000000U) | ||
| 4956 | #define DMA_EEI_EEI27_SHIFT (27U) | ||
| 4957 | #define DMA_EEI_EEI27_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK) | ||
| 4958 | #define DMA_EEI_EEI27 DMA_EEI_EEI27_MASK | ||
| 4959 | #define DMA_EEI_EEI28_MASK (0x10000000U) | ||
| 4960 | #define DMA_EEI_EEI28_SHIFT (28U) | ||
| 4961 | #define DMA_EEI_EEI28_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK) | ||
| 4962 | #define DMA_EEI_EEI28 DMA_EEI_EEI28_MASK | ||
| 4963 | #define DMA_EEI_EEI29_MASK (0x20000000U) | ||
| 4964 | #define DMA_EEI_EEI29_SHIFT (29U) | ||
| 4965 | #define DMA_EEI_EEI29_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK) | ||
| 4966 | #define DMA_EEI_EEI29 DMA_EEI_EEI29_MASK | ||
| 4967 | #define DMA_EEI_EEI30_MASK (0x40000000U) | ||
| 4968 | #define DMA_EEI_EEI30_SHIFT (30U) | ||
| 4969 | #define DMA_EEI_EEI30_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK) | ||
| 4970 | #define DMA_EEI_EEI30 DMA_EEI_EEI30_MASK | ||
| 4971 | #define DMA_EEI_EEI31_MASK (0x80000000U) | ||
| 4972 | #define DMA_EEI_EEI31_SHIFT (31U) | ||
| 4973 | #define DMA_EEI_EEI31_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK) | ||
| 4974 | #define DMA_EEI_EEI31 DMA_EEI_EEI31_MASK | ||
| 4975 | |||
| 4976 | /*! @name CEEI - Clear Enable Error Interrupt Register */ | ||
| 4977 | #define DMA_CEEI_CEEI_MASK (0x1FU) | ||
| 4978 | #define DMA_CEEI_CEEI_SHIFT (0U) | ||
| 4979 | #define DMA_CEEI_CEEI_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) | ||
| 4980 | #define DMA_CEEI_CEEI DMA_CEEI_CEEI_MASK | ||
| 4981 | #define DMA_CEEI_CAEE_MASK (0x40U) | ||
| 4982 | #define DMA_CEEI_CAEE_SHIFT (6U) | ||
| 4983 | #define DMA_CEEI_CAEE_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) | ||
| 4984 | #define DMA_CEEI_CAEE DMA_CEEI_CAEE_MASK | ||
| 4985 | #define DMA_CEEI_NOP_MASK (0x80U) | ||
| 4986 | #define DMA_CEEI_NOP_SHIFT (7U) | ||
| 4987 | #define DMA_CEEI_NOP_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) | ||
| 4988 | #define DMA_CEEI_NOP DMA_CEEI_NOP_MASK | ||
| 4989 | |||
| 4990 | /*! @name SEEI - Set Enable Error Interrupt Register */ | ||
| 4991 | #define DMA_SEEI_SEEI_MASK (0x1FU) | ||
| 4992 | #define DMA_SEEI_SEEI_SHIFT (0U) | ||
| 4993 | #define DMA_SEEI_SEEI_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) | ||
| 4994 | #define DMA_SEEI_SEEI DMA_SEEI_SEEI_MASK | ||
| 4995 | #define DMA_SEEI_SAEE_MASK (0x40U) | ||
| 4996 | #define DMA_SEEI_SAEE_SHIFT (6U) | ||
| 4997 | #define DMA_SEEI_SAEE_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) | ||
| 4998 | #define DMA_SEEI_SAEE DMA_SEEI_SAEE_MASK | ||
| 4999 | #define DMA_SEEI_NOP_MASK (0x80U) | ||
| 5000 | #define DMA_SEEI_NOP_SHIFT (7U) | ||
| 5001 | #define DMA_SEEI_NOP_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) | ||
| 5002 | #define DMA_SEEI_NOP DMA_SEEI_NOP_MASK | ||
| 5003 | |||
| 5004 | /*! @name CERQ - Clear Enable Request Register */ | ||
| 5005 | #define DMA_CERQ_CERQ_MASK (0x1FU) | ||
| 5006 | #define DMA_CERQ_CERQ_SHIFT (0U) | ||
| 5007 | #define DMA_CERQ_CERQ_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) | ||
| 5008 | #define DMA_CERQ_CERQ DMA_CERQ_CERQ_MASK | ||
| 5009 | #define DMA_CERQ_CAER_MASK (0x40U) | ||
| 5010 | #define DMA_CERQ_CAER_SHIFT (6U) | ||
| 5011 | #define DMA_CERQ_CAER_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) | ||
| 5012 | #define DMA_CERQ_CAER DMA_CERQ_CAER_MASK | ||
| 5013 | #define DMA_CERQ_NOP_MASK (0x80U) | ||
| 5014 | #define DMA_CERQ_NOP_SHIFT (7U) | ||
| 5015 | #define DMA_CERQ_NOP_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) | ||
| 5016 | #define DMA_CERQ_NOP DMA_CERQ_NOP_MASK | ||
| 5017 | |||
| 5018 | /*! @name SERQ - Set Enable Request Register */ | ||
| 5019 | #define DMA_SERQ_SERQ_MASK (0x1FU) | ||
| 5020 | #define DMA_SERQ_SERQ_SHIFT (0U) | ||
| 5021 | #define DMA_SERQ_SERQ_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) | ||
| 5022 | #define DMA_SERQ_SERQ DMA_SERQ_SERQ_MASK | ||
| 5023 | #define DMA_SERQ_SAER_MASK (0x40U) | ||
| 5024 | #define DMA_SERQ_SAER_SHIFT (6U) | ||
| 5025 | #define DMA_SERQ_SAER_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) | ||
| 5026 | #define DMA_SERQ_SAER DMA_SERQ_SAER_MASK | ||
| 5027 | #define DMA_SERQ_NOP_MASK (0x80U) | ||
| 5028 | #define DMA_SERQ_NOP_SHIFT (7U) | ||
| 5029 | #define DMA_SERQ_NOP_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) | ||
| 5030 | #define DMA_SERQ_NOP DMA_SERQ_NOP_MASK | ||
| 5031 | |||
| 5032 | /*! @name CDNE - Clear DONE Status Bit Register */ | ||
| 5033 | #define DMA_CDNE_CDNE_MASK (0x1FU) | ||
| 5034 | #define DMA_CDNE_CDNE_SHIFT (0U) | ||
| 5035 | #define DMA_CDNE_CDNE_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) | ||
| 5036 | #define DMA_CDNE_CDNE DMA_CDNE_CDNE_MASK | ||
| 5037 | #define DMA_CDNE_CADN_MASK (0x40U) | ||
| 5038 | #define DMA_CDNE_CADN_SHIFT (6U) | ||
| 5039 | #define DMA_CDNE_CADN_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) | ||
| 5040 | #define DMA_CDNE_CADN DMA_CDNE_CADN_MASK | ||
| 5041 | #define DMA_CDNE_NOP_MASK (0x80U) | ||
| 5042 | #define DMA_CDNE_NOP_SHIFT (7U) | ||
| 5043 | #define DMA_CDNE_NOP_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) | ||
| 5044 | #define DMA_CDNE_NOP DMA_CDNE_NOP_MASK | ||
| 5045 | |||
| 5046 | /*! @name SSRT - Set START Bit Register */ | ||
| 5047 | #define DMA_SSRT_SSRT_MASK (0x1FU) | ||
| 5048 | #define DMA_SSRT_SSRT_SHIFT (0U) | ||
| 5049 | #define DMA_SSRT_SSRT_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) | ||
| 5050 | #define DMA_SSRT_SSRT DMA_SSRT_SSRT_MASK | ||
| 5051 | #define DMA_SSRT_SAST_MASK (0x40U) | ||
| 5052 | #define DMA_SSRT_SAST_SHIFT (6U) | ||
| 5053 | #define DMA_SSRT_SAST_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) | ||
| 5054 | #define DMA_SSRT_SAST DMA_SSRT_SAST_MASK | ||
| 5055 | #define DMA_SSRT_NOP_MASK (0x80U) | ||
| 5056 | #define DMA_SSRT_NOP_SHIFT (7U) | ||
| 5057 | #define DMA_SSRT_NOP_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) | ||
| 5058 | #define DMA_SSRT_NOP DMA_SSRT_NOP_MASK | ||
| 5059 | |||
| 5060 | /*! @name CERR - Clear Error Register */ | ||
| 5061 | #define DMA_CERR_CERR_MASK (0x1FU) | ||
| 5062 | #define DMA_CERR_CERR_SHIFT (0U) | ||
| 5063 | #define DMA_CERR_CERR_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) | ||
| 5064 | #define DMA_CERR_CERR DMA_CERR_CERR_MASK | ||
| 5065 | #define DMA_CERR_CAEI_MASK (0x40U) | ||
| 5066 | #define DMA_CERR_CAEI_SHIFT (6U) | ||
| 5067 | #define DMA_CERR_CAEI_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) | ||
| 5068 | #define DMA_CERR_CAEI DMA_CERR_CAEI_MASK | ||
| 5069 | #define DMA_CERR_NOP_MASK (0x80U) | ||
| 5070 | #define DMA_CERR_NOP_SHIFT (7U) | ||
| 5071 | #define DMA_CERR_NOP_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) | ||
| 5072 | #define DMA_CERR_NOP DMA_CERR_NOP_MASK | ||
| 5073 | |||
| 5074 | /*! @name CINT - Clear Interrupt Request Register */ | ||
| 5075 | #define DMA_CINT_CINT_MASK (0x1FU) | ||
| 5076 | #define DMA_CINT_CINT_SHIFT (0U) | ||
| 5077 | #define DMA_CINT_CINT_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) | ||
| 5078 | #define DMA_CINT_CINT DMA_CINT_CINT_MASK | ||
| 5079 | #define DMA_CINT_CAIR_MASK (0x40U) | ||
| 5080 | #define DMA_CINT_CAIR_SHIFT (6U) | ||
| 5081 | #define DMA_CINT_CAIR_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) | ||
| 5082 | #define DMA_CINT_CAIR DMA_CINT_CAIR_MASK | ||
| 5083 | #define DMA_CINT_NOP_MASK (0x80U) | ||
| 5084 | #define DMA_CINT_NOP_SHIFT (7U) | ||
| 5085 | #define DMA_CINT_NOP_SET(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) | ||
| 5086 | #define DMA_CINT_NOP DMA_CINT_NOP_MASK | ||
| 5087 | |||
| 5088 | /*! @name INT - Interrupt Request Register */ | ||
| 5089 | #define DMA_INT_INT0_MASK (0x1U) | ||
| 5090 | #define DMA_INT_INT0_SHIFT (0U) | ||
| 5091 | #define DMA_INT_INT0_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) | ||
| 5092 | #define DMA_INT_INT0 DMA_INT_INT0_MASK | ||
| 5093 | #define DMA_INT_INT1_MASK (0x2U) | ||
| 5094 | #define DMA_INT_INT1_SHIFT (1U) | ||
| 5095 | #define DMA_INT_INT1_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) | ||
| 5096 | #define DMA_INT_INT1 DMA_INT_INT1_MASK | ||
| 5097 | #define DMA_INT_INT2_MASK (0x4U) | ||
| 5098 | #define DMA_INT_INT2_SHIFT (2U) | ||
| 5099 | #define DMA_INT_INT2_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) | ||
| 5100 | #define DMA_INT_INT2 DMA_INT_INT2_MASK | ||
| 5101 | #define DMA_INT_INT3_MASK (0x8U) | ||
| 5102 | #define DMA_INT_INT3_SHIFT (3U) | ||
| 5103 | #define DMA_INT_INT3_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) | ||
| 5104 | #define DMA_INT_INT3 DMA_INT_INT3_MASK | ||
| 5105 | #define DMA_INT_INT4_MASK (0x10U) | ||
| 5106 | #define DMA_INT_INT4_SHIFT (4U) | ||
| 5107 | #define DMA_INT_INT4_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) | ||
| 5108 | #define DMA_INT_INT4 DMA_INT_INT4_MASK | ||
| 5109 | #define DMA_INT_INT5_MASK (0x20U) | ||
| 5110 | #define DMA_INT_INT5_SHIFT (5U) | ||
| 5111 | #define DMA_INT_INT5_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) | ||
| 5112 | #define DMA_INT_INT5 DMA_INT_INT5_MASK | ||
| 5113 | #define DMA_INT_INT6_MASK (0x40U) | ||
| 5114 | #define DMA_INT_INT6_SHIFT (6U) | ||
| 5115 | #define DMA_INT_INT6_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) | ||
| 5116 | #define DMA_INT_INT6 DMA_INT_INT6_MASK | ||
| 5117 | #define DMA_INT_INT7_MASK (0x80U) | ||
| 5118 | #define DMA_INT_INT7_SHIFT (7U) | ||
| 5119 | #define DMA_INT_INT7_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) | ||
| 5120 | #define DMA_INT_INT7 DMA_INT_INT7_MASK | ||
| 5121 | #define DMA_INT_INT8_MASK (0x100U) | ||
| 5122 | #define DMA_INT_INT8_SHIFT (8U) | ||
| 5123 | #define DMA_INT_INT8_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) | ||
| 5124 | #define DMA_INT_INT8 DMA_INT_INT8_MASK | ||
| 5125 | #define DMA_INT_INT9_MASK (0x200U) | ||
| 5126 | #define DMA_INT_INT9_SHIFT (9U) | ||
| 5127 | #define DMA_INT_INT9_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) | ||
| 5128 | #define DMA_INT_INT9 DMA_INT_INT9_MASK | ||
| 5129 | #define DMA_INT_INT10_MASK (0x400U) | ||
| 5130 | #define DMA_INT_INT10_SHIFT (10U) | ||
| 5131 | #define DMA_INT_INT10_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) | ||
| 5132 | #define DMA_INT_INT10 DMA_INT_INT10_MASK | ||
| 5133 | #define DMA_INT_INT11_MASK (0x800U) | ||
| 5134 | #define DMA_INT_INT11_SHIFT (11U) | ||
| 5135 | #define DMA_INT_INT11_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) | ||
| 5136 | #define DMA_INT_INT11 DMA_INT_INT11_MASK | ||
| 5137 | #define DMA_INT_INT12_MASK (0x1000U) | ||
| 5138 | #define DMA_INT_INT12_SHIFT (12U) | ||
| 5139 | #define DMA_INT_INT12_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) | ||
| 5140 | #define DMA_INT_INT12 DMA_INT_INT12_MASK | ||
| 5141 | #define DMA_INT_INT13_MASK (0x2000U) | ||
| 5142 | #define DMA_INT_INT13_SHIFT (13U) | ||
| 5143 | #define DMA_INT_INT13_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) | ||
| 5144 | #define DMA_INT_INT13 DMA_INT_INT13_MASK | ||
| 5145 | #define DMA_INT_INT14_MASK (0x4000U) | ||
| 5146 | #define DMA_INT_INT14_SHIFT (14U) | ||
| 5147 | #define DMA_INT_INT14_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) | ||
| 5148 | #define DMA_INT_INT14 DMA_INT_INT14_MASK | ||
| 5149 | #define DMA_INT_INT15_MASK (0x8000U) | ||
| 5150 | #define DMA_INT_INT15_SHIFT (15U) | ||
| 5151 | #define DMA_INT_INT15_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) | ||
| 5152 | #define DMA_INT_INT15 DMA_INT_INT15_MASK | ||
| 5153 | #define DMA_INT_INT16_MASK (0x10000U) | ||
| 5154 | #define DMA_INT_INT16_SHIFT (16U) | ||
| 5155 | #define DMA_INT_INT16_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK) | ||
| 5156 | #define DMA_INT_INT16 DMA_INT_INT16_MASK | ||
| 5157 | #define DMA_INT_INT17_MASK (0x20000U) | ||
| 5158 | #define DMA_INT_INT17_SHIFT (17U) | ||
| 5159 | #define DMA_INT_INT17_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK) | ||
| 5160 | #define DMA_INT_INT17 DMA_INT_INT17_MASK | ||
| 5161 | #define DMA_INT_INT18_MASK (0x40000U) | ||
| 5162 | #define DMA_INT_INT18_SHIFT (18U) | ||
| 5163 | #define DMA_INT_INT18_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK) | ||
| 5164 | #define DMA_INT_INT18 DMA_INT_INT18_MASK | ||
| 5165 | #define DMA_INT_INT19_MASK (0x80000U) | ||
| 5166 | #define DMA_INT_INT19_SHIFT (19U) | ||
| 5167 | #define DMA_INT_INT19_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK) | ||
| 5168 | #define DMA_INT_INT19 DMA_INT_INT19_MASK | ||
| 5169 | #define DMA_INT_INT20_MASK (0x100000U) | ||
| 5170 | #define DMA_INT_INT20_SHIFT (20U) | ||
| 5171 | #define DMA_INT_INT20_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK) | ||
| 5172 | #define DMA_INT_INT20 DMA_INT_INT20_MASK | ||
| 5173 | #define DMA_INT_INT21_MASK (0x200000U) | ||
| 5174 | #define DMA_INT_INT21_SHIFT (21U) | ||
| 5175 | #define DMA_INT_INT21_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK) | ||
| 5176 | #define DMA_INT_INT21 DMA_INT_INT21_MASK | ||
| 5177 | #define DMA_INT_INT22_MASK (0x400000U) | ||
| 5178 | #define DMA_INT_INT22_SHIFT (22U) | ||
| 5179 | #define DMA_INT_INT22_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK) | ||
| 5180 | #define DMA_INT_INT22 DMA_INT_INT22_MASK | ||
| 5181 | #define DMA_INT_INT23_MASK (0x800000U) | ||
| 5182 | #define DMA_INT_INT23_SHIFT (23U) | ||
| 5183 | #define DMA_INT_INT23_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK) | ||
| 5184 | #define DMA_INT_INT23 DMA_INT_INT23_MASK | ||
| 5185 | #define DMA_INT_INT24_MASK (0x1000000U) | ||
| 5186 | #define DMA_INT_INT24_SHIFT (24U) | ||
| 5187 | #define DMA_INT_INT24_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK) | ||
| 5188 | #define DMA_INT_INT24 DMA_INT_INT24_MASK | ||
| 5189 | #define DMA_INT_INT25_MASK (0x2000000U) | ||
| 5190 | #define DMA_INT_INT25_SHIFT (25U) | ||
| 5191 | #define DMA_INT_INT25_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK) | ||
| 5192 | #define DMA_INT_INT25 DMA_INT_INT25_MASK | ||
| 5193 | #define DMA_INT_INT26_MASK (0x4000000U) | ||
| 5194 | #define DMA_INT_INT26_SHIFT (26U) | ||
| 5195 | #define DMA_INT_INT26_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK) | ||
| 5196 | #define DMA_INT_INT26 DMA_INT_INT26_MASK | ||
| 5197 | #define DMA_INT_INT27_MASK (0x8000000U) | ||
| 5198 | #define DMA_INT_INT27_SHIFT (27U) | ||
| 5199 | #define DMA_INT_INT27_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK) | ||
| 5200 | #define DMA_INT_INT27 DMA_INT_INT27_MASK | ||
| 5201 | #define DMA_INT_INT28_MASK (0x10000000U) | ||
| 5202 | #define DMA_INT_INT28_SHIFT (28U) | ||
| 5203 | #define DMA_INT_INT28_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK) | ||
| 5204 | #define DMA_INT_INT28 DMA_INT_INT28_MASK | ||
| 5205 | #define DMA_INT_INT29_MASK (0x20000000U) | ||
| 5206 | #define DMA_INT_INT29_SHIFT (29U) | ||
| 5207 | #define DMA_INT_INT29_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK) | ||
| 5208 | #define DMA_INT_INT29 DMA_INT_INT29_MASK | ||
| 5209 | #define DMA_INT_INT30_MASK (0x40000000U) | ||
| 5210 | #define DMA_INT_INT30_SHIFT (30U) | ||
| 5211 | #define DMA_INT_INT30_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK) | ||
| 5212 | #define DMA_INT_INT30 DMA_INT_INT30_MASK | ||
| 5213 | #define DMA_INT_INT31_MASK (0x80000000U) | ||
| 5214 | #define DMA_INT_INT31_SHIFT (31U) | ||
| 5215 | #define DMA_INT_INT31_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK) | ||
| 5216 | #define DMA_INT_INT31 DMA_INT_INT31_MASK | ||
| 5217 | |||
| 5218 | /*! @name ERR - Error Register */ | ||
| 5219 | #define DMA_ERR_ERR0_MASK (0x1U) | ||
| 5220 | #define DMA_ERR_ERR0_SHIFT (0U) | ||
| 5221 | #define DMA_ERR_ERR0_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) | ||
| 5222 | #define DMA_ERR_ERR0 DMA_ERR_ERR0_MASK | ||
| 5223 | #define DMA_ERR_ERR1_MASK (0x2U) | ||
| 5224 | #define DMA_ERR_ERR1_SHIFT (1U) | ||
| 5225 | #define DMA_ERR_ERR1_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) | ||
| 5226 | #define DMA_ERR_ERR1 DMA_ERR_ERR1_MASK | ||
| 5227 | #define DMA_ERR_ERR2_MASK (0x4U) | ||
| 5228 | #define DMA_ERR_ERR2_SHIFT (2U) | ||
| 5229 | #define DMA_ERR_ERR2_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) | ||
| 5230 | #define DMA_ERR_ERR2 DMA_ERR_ERR2_MASK | ||
| 5231 | #define DMA_ERR_ERR3_MASK (0x8U) | ||
| 5232 | #define DMA_ERR_ERR3_SHIFT (3U) | ||
| 5233 | #define DMA_ERR_ERR3_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) | ||
| 5234 | #define DMA_ERR_ERR3 DMA_ERR_ERR3_MASK | ||
| 5235 | #define DMA_ERR_ERR4_MASK (0x10U) | ||
| 5236 | #define DMA_ERR_ERR4_SHIFT (4U) | ||
| 5237 | #define DMA_ERR_ERR4_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) | ||
| 5238 | #define DMA_ERR_ERR4 DMA_ERR_ERR4_MASK | ||
| 5239 | #define DMA_ERR_ERR5_MASK (0x20U) | ||
| 5240 | #define DMA_ERR_ERR5_SHIFT (5U) | ||
| 5241 | #define DMA_ERR_ERR5_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) | ||
| 5242 | #define DMA_ERR_ERR5 DMA_ERR_ERR5_MASK | ||
| 5243 | #define DMA_ERR_ERR6_MASK (0x40U) | ||
| 5244 | #define DMA_ERR_ERR6_SHIFT (6U) | ||
| 5245 | #define DMA_ERR_ERR6_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) | ||
| 5246 | #define DMA_ERR_ERR6 DMA_ERR_ERR6_MASK | ||
| 5247 | #define DMA_ERR_ERR7_MASK (0x80U) | ||
| 5248 | #define DMA_ERR_ERR7_SHIFT (7U) | ||
| 5249 | #define DMA_ERR_ERR7_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) | ||
| 5250 | #define DMA_ERR_ERR7 DMA_ERR_ERR7_MASK | ||
| 5251 | #define DMA_ERR_ERR8_MASK (0x100U) | ||
| 5252 | #define DMA_ERR_ERR8_SHIFT (8U) | ||
| 5253 | #define DMA_ERR_ERR8_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) | ||
| 5254 | #define DMA_ERR_ERR8 DMA_ERR_ERR8_MASK | ||
| 5255 | #define DMA_ERR_ERR9_MASK (0x200U) | ||
| 5256 | #define DMA_ERR_ERR9_SHIFT (9U) | ||
| 5257 | #define DMA_ERR_ERR9_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) | ||
| 5258 | #define DMA_ERR_ERR9 DMA_ERR_ERR9_MASK | ||
| 5259 | #define DMA_ERR_ERR10_MASK (0x400U) | ||
| 5260 | #define DMA_ERR_ERR10_SHIFT (10U) | ||
| 5261 | #define DMA_ERR_ERR10_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) | ||
| 5262 | #define DMA_ERR_ERR10 DMA_ERR_ERR10_MASK | ||
| 5263 | #define DMA_ERR_ERR11_MASK (0x800U) | ||
| 5264 | #define DMA_ERR_ERR11_SHIFT (11U) | ||
| 5265 | #define DMA_ERR_ERR11_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) | ||
| 5266 | #define DMA_ERR_ERR11 DMA_ERR_ERR11_MASK | ||
| 5267 | #define DMA_ERR_ERR12_MASK (0x1000U) | ||
| 5268 | #define DMA_ERR_ERR12_SHIFT (12U) | ||
| 5269 | #define DMA_ERR_ERR12_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) | ||
| 5270 | #define DMA_ERR_ERR12 DMA_ERR_ERR12_MASK | ||
| 5271 | #define DMA_ERR_ERR13_MASK (0x2000U) | ||
| 5272 | #define DMA_ERR_ERR13_SHIFT (13U) | ||
| 5273 | #define DMA_ERR_ERR13_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) | ||
| 5274 | #define DMA_ERR_ERR13 DMA_ERR_ERR13_MASK | ||
| 5275 | #define DMA_ERR_ERR14_MASK (0x4000U) | ||
| 5276 | #define DMA_ERR_ERR14_SHIFT (14U) | ||
| 5277 | #define DMA_ERR_ERR14_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) | ||
| 5278 | #define DMA_ERR_ERR14 DMA_ERR_ERR14_MASK | ||
| 5279 | #define DMA_ERR_ERR15_MASK (0x8000U) | ||
| 5280 | #define DMA_ERR_ERR15_SHIFT (15U) | ||
| 5281 | #define DMA_ERR_ERR15_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) | ||
| 5282 | #define DMA_ERR_ERR15 DMA_ERR_ERR15_MASK | ||
| 5283 | #define DMA_ERR_ERR16_MASK (0x10000U) | ||
| 5284 | #define DMA_ERR_ERR16_SHIFT (16U) | ||
| 5285 | #define DMA_ERR_ERR16_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK) | ||
| 5286 | #define DMA_ERR_ERR16 DMA_ERR_ERR16_MASK | ||
| 5287 | #define DMA_ERR_ERR17_MASK (0x20000U) | ||
| 5288 | #define DMA_ERR_ERR17_SHIFT (17U) | ||
| 5289 | #define DMA_ERR_ERR17_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK) | ||
| 5290 | #define DMA_ERR_ERR17 DMA_ERR_ERR17_MASK | ||
| 5291 | #define DMA_ERR_ERR18_MASK (0x40000U) | ||
| 5292 | #define DMA_ERR_ERR18_SHIFT (18U) | ||
| 5293 | #define DMA_ERR_ERR18_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK) | ||
| 5294 | #define DMA_ERR_ERR18 DMA_ERR_ERR18_MASK | ||
| 5295 | #define DMA_ERR_ERR19_MASK (0x80000U) | ||
| 5296 | #define DMA_ERR_ERR19_SHIFT (19U) | ||
| 5297 | #define DMA_ERR_ERR19_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK) | ||
| 5298 | #define DMA_ERR_ERR19 DMA_ERR_ERR19_MASK | ||
| 5299 | #define DMA_ERR_ERR20_MASK (0x100000U) | ||
| 5300 | #define DMA_ERR_ERR20_SHIFT (20U) | ||
| 5301 | #define DMA_ERR_ERR20_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK) | ||
| 5302 | #define DMA_ERR_ERR20 DMA_ERR_ERR20_MASK | ||
| 5303 | #define DMA_ERR_ERR21_MASK (0x200000U) | ||
| 5304 | #define DMA_ERR_ERR21_SHIFT (21U) | ||
| 5305 | #define DMA_ERR_ERR21_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK) | ||
| 5306 | #define DMA_ERR_ERR21 DMA_ERR_ERR21_MASK | ||
| 5307 | #define DMA_ERR_ERR22_MASK (0x400000U) | ||
| 5308 | #define DMA_ERR_ERR22_SHIFT (22U) | ||
| 5309 | #define DMA_ERR_ERR22_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK) | ||
| 5310 | #define DMA_ERR_ERR22 DMA_ERR_ERR22_MASK | ||
| 5311 | #define DMA_ERR_ERR23_MASK (0x800000U) | ||
| 5312 | #define DMA_ERR_ERR23_SHIFT (23U) | ||
| 5313 | #define DMA_ERR_ERR23_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK) | ||
| 5314 | #define DMA_ERR_ERR23 DMA_ERR_ERR23_MASK | ||
| 5315 | #define DMA_ERR_ERR24_MASK (0x1000000U) | ||
| 5316 | #define DMA_ERR_ERR24_SHIFT (24U) | ||
| 5317 | #define DMA_ERR_ERR24_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK) | ||
| 5318 | #define DMA_ERR_ERR24 DMA_ERR_ERR24_MASK | ||
| 5319 | #define DMA_ERR_ERR25_MASK (0x2000000U) | ||
| 5320 | #define DMA_ERR_ERR25_SHIFT (25U) | ||
| 5321 | #define DMA_ERR_ERR25_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK) | ||
| 5322 | #define DMA_ERR_ERR25 DMA_ERR_ERR25_MASK | ||
| 5323 | #define DMA_ERR_ERR26_MASK (0x4000000U) | ||
| 5324 | #define DMA_ERR_ERR26_SHIFT (26U) | ||
| 5325 | #define DMA_ERR_ERR26_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK) | ||
| 5326 | #define DMA_ERR_ERR26 DMA_ERR_ERR26_MASK | ||
| 5327 | #define DMA_ERR_ERR27_MASK (0x8000000U) | ||
| 5328 | #define DMA_ERR_ERR27_SHIFT (27U) | ||
| 5329 | #define DMA_ERR_ERR27_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK) | ||
| 5330 | #define DMA_ERR_ERR27 DMA_ERR_ERR27_MASK | ||
| 5331 | #define DMA_ERR_ERR28_MASK (0x10000000U) | ||
| 5332 | #define DMA_ERR_ERR28_SHIFT (28U) | ||
| 5333 | #define DMA_ERR_ERR28_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK) | ||
| 5334 | #define DMA_ERR_ERR28 DMA_ERR_ERR28_MASK | ||
| 5335 | #define DMA_ERR_ERR29_MASK (0x20000000U) | ||
| 5336 | #define DMA_ERR_ERR29_SHIFT (29U) | ||
| 5337 | #define DMA_ERR_ERR29_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK) | ||
| 5338 | #define DMA_ERR_ERR29 DMA_ERR_ERR29_MASK | ||
| 5339 | #define DMA_ERR_ERR30_MASK (0x40000000U) | ||
| 5340 | #define DMA_ERR_ERR30_SHIFT (30U) | ||
| 5341 | #define DMA_ERR_ERR30_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK) | ||
| 5342 | #define DMA_ERR_ERR30 DMA_ERR_ERR30_MASK | ||
| 5343 | #define DMA_ERR_ERR31_MASK (0x80000000U) | ||
| 5344 | #define DMA_ERR_ERR31_SHIFT (31U) | ||
| 5345 | #define DMA_ERR_ERR31_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK) | ||
| 5346 | #define DMA_ERR_ERR31 DMA_ERR_ERR31_MASK | ||
| 5347 | |||
| 5348 | /*! @name HRS - Hardware Request Status Register */ | ||
| 5349 | #define DMA_HRS_HRS0_MASK (0x1U) | ||
| 5350 | #define DMA_HRS_HRS0_SHIFT (0U) | ||
| 5351 | #define DMA_HRS_HRS0_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) | ||
| 5352 | #define DMA_HRS_HRS0 DMA_HRS_HRS0_MASK | ||
| 5353 | #define DMA_HRS_HRS1_MASK (0x2U) | ||
| 5354 | #define DMA_HRS_HRS1_SHIFT (1U) | ||
| 5355 | #define DMA_HRS_HRS1_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) | ||
| 5356 | #define DMA_HRS_HRS1 DMA_HRS_HRS1_MASK | ||
| 5357 | #define DMA_HRS_HRS2_MASK (0x4U) | ||
| 5358 | #define DMA_HRS_HRS2_SHIFT (2U) | ||
| 5359 | #define DMA_HRS_HRS2_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) | ||
| 5360 | #define DMA_HRS_HRS2 DMA_HRS_HRS2_MASK | ||
| 5361 | #define DMA_HRS_HRS3_MASK (0x8U) | ||
| 5362 | #define DMA_HRS_HRS3_SHIFT (3U) | ||
| 5363 | #define DMA_HRS_HRS3_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) | ||
| 5364 | #define DMA_HRS_HRS3 DMA_HRS_HRS3_MASK | ||
| 5365 | #define DMA_HRS_HRS4_MASK (0x10U) | ||
| 5366 | #define DMA_HRS_HRS4_SHIFT (4U) | ||
| 5367 | #define DMA_HRS_HRS4_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) | ||
| 5368 | #define DMA_HRS_HRS4 DMA_HRS_HRS4_MASK | ||
| 5369 | #define DMA_HRS_HRS5_MASK (0x20U) | ||
| 5370 | #define DMA_HRS_HRS5_SHIFT (5U) | ||
| 5371 | #define DMA_HRS_HRS5_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) | ||
| 5372 | #define DMA_HRS_HRS5 DMA_HRS_HRS5_MASK | ||
| 5373 | #define DMA_HRS_HRS6_MASK (0x40U) | ||
| 5374 | #define DMA_HRS_HRS6_SHIFT (6U) | ||
| 5375 | #define DMA_HRS_HRS6_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) | ||
| 5376 | #define DMA_HRS_HRS6 DMA_HRS_HRS6_MASK | ||
| 5377 | #define DMA_HRS_HRS7_MASK (0x80U) | ||
| 5378 | #define DMA_HRS_HRS7_SHIFT (7U) | ||
| 5379 | #define DMA_HRS_HRS7_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) | ||
| 5380 | #define DMA_HRS_HRS7 DMA_HRS_HRS7_MASK | ||
| 5381 | #define DMA_HRS_HRS8_MASK (0x100U) | ||
| 5382 | #define DMA_HRS_HRS8_SHIFT (8U) | ||
| 5383 | #define DMA_HRS_HRS8_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) | ||
| 5384 | #define DMA_HRS_HRS8 DMA_HRS_HRS8_MASK | ||
| 5385 | #define DMA_HRS_HRS9_MASK (0x200U) | ||
| 5386 | #define DMA_HRS_HRS9_SHIFT (9U) | ||
| 5387 | #define DMA_HRS_HRS9_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) | ||
| 5388 | #define DMA_HRS_HRS9 DMA_HRS_HRS9_MASK | ||
| 5389 | #define DMA_HRS_HRS10_MASK (0x400U) | ||
| 5390 | #define DMA_HRS_HRS10_SHIFT (10U) | ||
| 5391 | #define DMA_HRS_HRS10_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) | ||
| 5392 | #define DMA_HRS_HRS10 DMA_HRS_HRS10_MASK | ||
| 5393 | #define DMA_HRS_HRS11_MASK (0x800U) | ||
| 5394 | #define DMA_HRS_HRS11_SHIFT (11U) | ||
| 5395 | #define DMA_HRS_HRS11_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) | ||
| 5396 | #define DMA_HRS_HRS11 DMA_HRS_HRS11_MASK | ||
| 5397 | #define DMA_HRS_HRS12_MASK (0x1000U) | ||
| 5398 | #define DMA_HRS_HRS12_SHIFT (12U) | ||
| 5399 | #define DMA_HRS_HRS12_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) | ||
| 5400 | #define DMA_HRS_HRS12 DMA_HRS_HRS12_MASK | ||
| 5401 | #define DMA_HRS_HRS13_MASK (0x2000U) | ||
| 5402 | #define DMA_HRS_HRS13_SHIFT (13U) | ||
| 5403 | #define DMA_HRS_HRS13_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) | ||
| 5404 | #define DMA_HRS_HRS13 DMA_HRS_HRS13_MASK | ||
| 5405 | #define DMA_HRS_HRS14_MASK (0x4000U) | ||
| 5406 | #define DMA_HRS_HRS14_SHIFT (14U) | ||
| 5407 | #define DMA_HRS_HRS14_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) | ||
| 5408 | #define DMA_HRS_HRS14 DMA_HRS_HRS14_MASK | ||
| 5409 | #define DMA_HRS_HRS15_MASK (0x8000U) | ||
| 5410 | #define DMA_HRS_HRS15_SHIFT (15U) | ||
| 5411 | #define DMA_HRS_HRS15_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) | ||
| 5412 | #define DMA_HRS_HRS15 DMA_HRS_HRS15_MASK | ||
| 5413 | #define DMA_HRS_HRS16_MASK (0x10000U) | ||
| 5414 | #define DMA_HRS_HRS16_SHIFT (16U) | ||
| 5415 | #define DMA_HRS_HRS16_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK) | ||
| 5416 | #define DMA_HRS_HRS16 DMA_HRS_HRS16_MASK | ||
| 5417 | #define DMA_HRS_HRS17_MASK (0x20000U) | ||
| 5418 | #define DMA_HRS_HRS17_SHIFT (17U) | ||
| 5419 | #define DMA_HRS_HRS17_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK) | ||
| 5420 | #define DMA_HRS_HRS17 DMA_HRS_HRS17_MASK | ||
| 5421 | #define DMA_HRS_HRS18_MASK (0x40000U) | ||
| 5422 | #define DMA_HRS_HRS18_SHIFT (18U) | ||
| 5423 | #define DMA_HRS_HRS18_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK) | ||
| 5424 | #define DMA_HRS_HRS18 DMA_HRS_HRS18_MASK | ||
| 5425 | #define DMA_HRS_HRS19_MASK (0x80000U) | ||
| 5426 | #define DMA_HRS_HRS19_SHIFT (19U) | ||
| 5427 | #define DMA_HRS_HRS19_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK) | ||
| 5428 | #define DMA_HRS_HRS19 DMA_HRS_HRS19_MASK | ||
| 5429 | #define DMA_HRS_HRS20_MASK (0x100000U) | ||
| 5430 | #define DMA_HRS_HRS20_SHIFT (20U) | ||
| 5431 | #define DMA_HRS_HRS20_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK) | ||
| 5432 | #define DMA_HRS_HRS20 DMA_HRS_HRS20_MASK | ||
| 5433 | #define DMA_HRS_HRS21_MASK (0x200000U) | ||
| 5434 | #define DMA_HRS_HRS21_SHIFT (21U) | ||
| 5435 | #define DMA_HRS_HRS21_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK) | ||
| 5436 | #define DMA_HRS_HRS21 DMA_HRS_HRS21_MASK | ||
| 5437 | #define DMA_HRS_HRS22_MASK (0x400000U) | ||
| 5438 | #define DMA_HRS_HRS22_SHIFT (22U) | ||
| 5439 | #define DMA_HRS_HRS22_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK) | ||
| 5440 | #define DMA_HRS_HRS22 DMA_HRS_HRS22_MASK | ||
| 5441 | #define DMA_HRS_HRS23_MASK (0x800000U) | ||
| 5442 | #define DMA_HRS_HRS23_SHIFT (23U) | ||
| 5443 | #define DMA_HRS_HRS23_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK) | ||
| 5444 | #define DMA_HRS_HRS23 DMA_HRS_HRS23_MASK | ||
| 5445 | #define DMA_HRS_HRS24_MASK (0x1000000U) | ||
| 5446 | #define DMA_HRS_HRS24_SHIFT (24U) | ||
| 5447 | #define DMA_HRS_HRS24_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK) | ||
| 5448 | #define DMA_HRS_HRS24 DMA_HRS_HRS24_MASK | ||
| 5449 | #define DMA_HRS_HRS25_MASK (0x2000000U) | ||
| 5450 | #define DMA_HRS_HRS25_SHIFT (25U) | ||
| 5451 | #define DMA_HRS_HRS25_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK) | ||
| 5452 | #define DMA_HRS_HRS25 DMA_HRS_HRS25_MASK | ||
| 5453 | #define DMA_HRS_HRS26_MASK (0x4000000U) | ||
| 5454 | #define DMA_HRS_HRS26_SHIFT (26U) | ||
| 5455 | #define DMA_HRS_HRS26_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK) | ||
| 5456 | #define DMA_HRS_HRS26 DMA_HRS_HRS26_MASK | ||
| 5457 | #define DMA_HRS_HRS27_MASK (0x8000000U) | ||
| 5458 | #define DMA_HRS_HRS27_SHIFT (27U) | ||
| 5459 | #define DMA_HRS_HRS27_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK) | ||
| 5460 | #define DMA_HRS_HRS27 DMA_HRS_HRS27_MASK | ||
| 5461 | #define DMA_HRS_HRS28_MASK (0x10000000U) | ||
| 5462 | #define DMA_HRS_HRS28_SHIFT (28U) | ||
| 5463 | #define DMA_HRS_HRS28_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK) | ||
| 5464 | #define DMA_HRS_HRS28 DMA_HRS_HRS28_MASK | ||
| 5465 | #define DMA_HRS_HRS29_MASK (0x20000000U) | ||
| 5466 | #define DMA_HRS_HRS29_SHIFT (29U) | ||
| 5467 | #define DMA_HRS_HRS29_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK) | ||
| 5468 | #define DMA_HRS_HRS29 DMA_HRS_HRS29_MASK | ||
| 5469 | #define DMA_HRS_HRS30_MASK (0x40000000U) | ||
| 5470 | #define DMA_HRS_HRS30_SHIFT (30U) | ||
| 5471 | #define DMA_HRS_HRS30_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK) | ||
| 5472 | #define DMA_HRS_HRS30 DMA_HRS_HRS30_MASK | ||
| 5473 | #define DMA_HRS_HRS31_MASK (0x80000000U) | ||
| 5474 | #define DMA_HRS_HRS31_SHIFT (31U) | ||
| 5475 | #define DMA_HRS_HRS31_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK) | ||
| 5476 | #define DMA_HRS_HRS31 DMA_HRS_HRS31_MASK | ||
| 5477 | |||
| 5478 | /*! @name EARS - Enable Asynchronous Request in Stop Register */ | ||
| 5479 | #define DMA_EARS_EDREQ_0_MASK (0x1U) | ||
| 5480 | #define DMA_EARS_EDREQ_0_SHIFT (0U) | ||
| 5481 | #define DMA_EARS_EDREQ_0_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) | ||
| 5482 | #define DMA_EARS_EDREQ_0 DMA_EARS_EDREQ_0_MASK | ||
| 5483 | #define DMA_EARS_EDREQ_1_MASK (0x2U) | ||
| 5484 | #define DMA_EARS_EDREQ_1_SHIFT (1U) | ||
| 5485 | #define DMA_EARS_EDREQ_1_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) | ||
| 5486 | #define DMA_EARS_EDREQ_1 DMA_EARS_EDREQ_1_MASK | ||
| 5487 | #define DMA_EARS_EDREQ_2_MASK (0x4U) | ||
| 5488 | #define DMA_EARS_EDREQ_2_SHIFT (2U) | ||
| 5489 | #define DMA_EARS_EDREQ_2_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) | ||
| 5490 | #define DMA_EARS_EDREQ_2 DMA_EARS_EDREQ_2_MASK | ||
| 5491 | #define DMA_EARS_EDREQ_3_MASK (0x8U) | ||
| 5492 | #define DMA_EARS_EDREQ_3_SHIFT (3U) | ||
| 5493 | #define DMA_EARS_EDREQ_3_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) | ||
| 5494 | #define DMA_EARS_EDREQ_3 DMA_EARS_EDREQ_3_MASK | ||
| 5495 | #define DMA_EARS_EDREQ_4_MASK (0x10U) | ||
| 5496 | #define DMA_EARS_EDREQ_4_SHIFT (4U) | ||
| 5497 | #define DMA_EARS_EDREQ_4_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) | ||
| 5498 | #define DMA_EARS_EDREQ_4 DMA_EARS_EDREQ_4_MASK | ||
| 5499 | #define DMA_EARS_EDREQ_5_MASK (0x20U) | ||
| 5500 | #define DMA_EARS_EDREQ_5_SHIFT (5U) | ||
| 5501 | #define DMA_EARS_EDREQ_5_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) | ||
| 5502 | #define DMA_EARS_EDREQ_5 DMA_EARS_EDREQ_5_MASK | ||
| 5503 | #define DMA_EARS_EDREQ_6_MASK (0x40U) | ||
| 5504 | #define DMA_EARS_EDREQ_6_SHIFT (6U) | ||
| 5505 | #define DMA_EARS_EDREQ_6_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) | ||
| 5506 | #define DMA_EARS_EDREQ_6 DMA_EARS_EDREQ_6_MASK | ||
| 5507 | #define DMA_EARS_EDREQ_7_MASK (0x80U) | ||
| 5508 | #define DMA_EARS_EDREQ_7_SHIFT (7U) | ||
| 5509 | #define DMA_EARS_EDREQ_7_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) | ||
| 5510 | #define DMA_EARS_EDREQ_7 DMA_EARS_EDREQ_7_MASK | ||
| 5511 | #define DMA_EARS_EDREQ_8_MASK (0x100U) | ||
| 5512 | #define DMA_EARS_EDREQ_8_SHIFT (8U) | ||
| 5513 | #define DMA_EARS_EDREQ_8_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) | ||
| 5514 | #define DMA_EARS_EDREQ_8 DMA_EARS_EDREQ_8_MASK | ||
| 5515 | #define DMA_EARS_EDREQ_9_MASK (0x200U) | ||
| 5516 | #define DMA_EARS_EDREQ_9_SHIFT (9U) | ||
| 5517 | #define DMA_EARS_EDREQ_9_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) | ||
| 5518 | #define DMA_EARS_EDREQ_9 DMA_EARS_EDREQ_9_MASK | ||
| 5519 | #define DMA_EARS_EDREQ_10_MASK (0x400U) | ||
| 5520 | #define DMA_EARS_EDREQ_10_SHIFT (10U) | ||
| 5521 | #define DMA_EARS_EDREQ_10_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) | ||
| 5522 | #define DMA_EARS_EDREQ_10 DMA_EARS_EDREQ_10_MASK | ||
| 5523 | #define DMA_EARS_EDREQ_11_MASK (0x800U) | ||
| 5524 | #define DMA_EARS_EDREQ_11_SHIFT (11U) | ||
| 5525 | #define DMA_EARS_EDREQ_11_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) | ||
| 5526 | #define DMA_EARS_EDREQ_11 DMA_EARS_EDREQ_11_MASK | ||
| 5527 | #define DMA_EARS_EDREQ_12_MASK (0x1000U) | ||
| 5528 | #define DMA_EARS_EDREQ_12_SHIFT (12U) | ||
| 5529 | #define DMA_EARS_EDREQ_12_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) | ||
| 5530 | #define DMA_EARS_EDREQ_12 DMA_EARS_EDREQ_12_MASK | ||
| 5531 | #define DMA_EARS_EDREQ_13_MASK (0x2000U) | ||
| 5532 | #define DMA_EARS_EDREQ_13_SHIFT (13U) | ||
| 5533 | #define DMA_EARS_EDREQ_13_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) | ||
| 5534 | #define DMA_EARS_EDREQ_13 DMA_EARS_EDREQ_13_MASK | ||
| 5535 | #define DMA_EARS_EDREQ_14_MASK (0x4000U) | ||
| 5536 | #define DMA_EARS_EDREQ_14_SHIFT (14U) | ||
| 5537 | #define DMA_EARS_EDREQ_14_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) | ||
| 5538 | #define DMA_EARS_EDREQ_14 DMA_EARS_EDREQ_14_MASK | ||
| 5539 | #define DMA_EARS_EDREQ_15_MASK (0x8000U) | ||
| 5540 | #define DMA_EARS_EDREQ_15_SHIFT (15U) | ||
| 5541 | #define DMA_EARS_EDREQ_15_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) | ||
| 5542 | #define DMA_EARS_EDREQ_15 DMA_EARS_EDREQ_15_MASK | ||
| 5543 | #define DMA_EARS_EDREQ_16_MASK (0x10000U) | ||
| 5544 | #define DMA_EARS_EDREQ_16_SHIFT (16U) | ||
| 5545 | #define DMA_EARS_EDREQ_16_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK) | ||
| 5546 | #define DMA_EARS_EDREQ_16 DMA_EARS_EDREQ_16_MASK | ||
| 5547 | #define DMA_EARS_EDREQ_17_MASK (0x20000U) | ||
| 5548 | #define DMA_EARS_EDREQ_17_SHIFT (17U) | ||
| 5549 | #define DMA_EARS_EDREQ_17_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK) | ||
| 5550 | #define DMA_EARS_EDREQ_17 DMA_EARS_EDREQ_17_MASK | ||
| 5551 | #define DMA_EARS_EDREQ_18_MASK (0x40000U) | ||
| 5552 | #define DMA_EARS_EDREQ_18_SHIFT (18U) | ||
| 5553 | #define DMA_EARS_EDREQ_18_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK) | ||
| 5554 | #define DMA_EARS_EDREQ_18 DMA_EARS_EDREQ_18_MASK | ||
| 5555 | #define DMA_EARS_EDREQ_19_MASK (0x80000U) | ||
| 5556 | #define DMA_EARS_EDREQ_19_SHIFT (19U) | ||
| 5557 | #define DMA_EARS_EDREQ_19_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK) | ||
| 5558 | #define DMA_EARS_EDREQ_19 DMA_EARS_EDREQ_19_MASK | ||
| 5559 | #define DMA_EARS_EDREQ_20_MASK (0x100000U) | ||
| 5560 | #define DMA_EARS_EDREQ_20_SHIFT (20U) | ||
| 5561 | #define DMA_EARS_EDREQ_20_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK) | ||
| 5562 | #define DMA_EARS_EDREQ_20 DMA_EARS_EDREQ_20_MASK | ||
| 5563 | #define DMA_EARS_EDREQ_21_MASK (0x200000U) | ||
| 5564 | #define DMA_EARS_EDREQ_21_SHIFT (21U) | ||
| 5565 | #define DMA_EARS_EDREQ_21_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK) | ||
| 5566 | #define DMA_EARS_EDREQ_21 DMA_EARS_EDREQ_21_MASK | ||
| 5567 | #define DMA_EARS_EDREQ_22_MASK (0x400000U) | ||
| 5568 | #define DMA_EARS_EDREQ_22_SHIFT (22U) | ||
| 5569 | #define DMA_EARS_EDREQ_22_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK) | ||
| 5570 | #define DMA_EARS_EDREQ_22 DMA_EARS_EDREQ_22_MASK | ||
| 5571 | #define DMA_EARS_EDREQ_23_MASK (0x800000U) | ||
| 5572 | #define DMA_EARS_EDREQ_23_SHIFT (23U) | ||
| 5573 | #define DMA_EARS_EDREQ_23_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK) | ||
| 5574 | #define DMA_EARS_EDREQ_23 DMA_EARS_EDREQ_23_MASK | ||
| 5575 | #define DMA_EARS_EDREQ_24_MASK (0x1000000U) | ||
| 5576 | #define DMA_EARS_EDREQ_24_SHIFT (24U) | ||
| 5577 | #define DMA_EARS_EDREQ_24_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK) | ||
| 5578 | #define DMA_EARS_EDREQ_24 DMA_EARS_EDREQ_24_MASK | ||
| 5579 | #define DMA_EARS_EDREQ_25_MASK (0x2000000U) | ||
| 5580 | #define DMA_EARS_EDREQ_25_SHIFT (25U) | ||
| 5581 | #define DMA_EARS_EDREQ_25_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK) | ||
| 5582 | #define DMA_EARS_EDREQ_25 DMA_EARS_EDREQ_25_MASK | ||
| 5583 | #define DMA_EARS_EDREQ_26_MASK (0x4000000U) | ||
| 5584 | #define DMA_EARS_EDREQ_26_SHIFT (26U) | ||
| 5585 | #define DMA_EARS_EDREQ_26_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK) | ||
| 5586 | #define DMA_EARS_EDREQ_26 DMA_EARS_EDREQ_26_MASK | ||
| 5587 | #define DMA_EARS_EDREQ_27_MASK (0x8000000U) | ||
| 5588 | #define DMA_EARS_EDREQ_27_SHIFT (27U) | ||
| 5589 | #define DMA_EARS_EDREQ_27_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK) | ||
| 5590 | #define DMA_EARS_EDREQ_27 DMA_EARS_EDREQ_27_MASK | ||
| 5591 | #define DMA_EARS_EDREQ_28_MASK (0x10000000U) | ||
| 5592 | #define DMA_EARS_EDREQ_28_SHIFT (28U) | ||
| 5593 | #define DMA_EARS_EDREQ_28_SET(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK) | ||
| 5594 | #define DMA_EARS_EDREQ_28 DMA_EARS_EDREQ_28_MASK | ||
| 5595 | #define DMA_EARS_EDREQ_29_MASK (0x20000000U) | ||
| 5596 | #define DMA_EARS_EDREQ_29_SHIFT (2 | ||