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1/*
2** ###################################################################
3** Processors: MK64FN1M0CAJ12
4** MK64FN1M0VDC12
5** MK64FN1M0VLL12
6** MK64FN1M0VLQ12
7** MK64FN1M0VMD12
8** MK64FX512VDC12
9** MK64FX512VLL12
10** MK64FX512VLQ12
11** MK64FX512VMD12
12**
13** Compilers: Keil ARM C/C++ Compiler
14** Freescale C/C++ for Embedded ARM
15** GNU C Compiler
16** IAR ANSI C/C++ Compiler for ARM
17**
18** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
19** Version: rev. 2.9, 2016-03-21
20** Build: b160321
21**
22** Abstract:
23** CMSIS Peripheral Access Layer for MK64F12
24**
25** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
26** All rights reserved.
27**
28** Redistribution and use in source and binary forms, with or without modification,
29** are permitted provided that the following conditions are met:
30**
31** o Redistributions of source code must retain the above copyright notice, this list
32** of conditions and the following disclaimer.
33**
34** o Redistributions in binary form must reproduce the above copyright notice, this
35** list of conditions and the following disclaimer in the documentation and/or
36** other materials provided with the distribution.
37**
38** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
39** contributors may be used to endorse or promote products derived from this
40** software without specific prior written permission.
41**
42** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
43** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
44** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
45** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
46** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
47** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
48** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
49** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
50** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
51** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
52**
53** http: www.freescale.com
54** mail: [email protected]
55**
56** Revisions:
57** - rev. 1.0 (2013-08-12)
58** Initial version.
59** - rev. 2.0 (2013-10-29)
60** Register accessor macros added to the memory map.
61** Symbols for Processor Expert memory map compatibility added to the memory map.
62** Startup file for gcc has been updated according to CMSIS 3.2.
63** System initialization updated.
64** MCG - registers updated.
65** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
66** - rev. 2.1 (2013-10-30)
67** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
68** - rev. 2.2 (2013-12-09)
69** DMA - EARS register removed.
70** AIPS0, AIPS1 - MPRA register updated.
71** - rev. 2.3 (2014-01-24)
72** Update according to reference manual rev. 2
73** ENET, MCG, MCM, SIM, USB - registers updated
74** - rev. 2.4 (2014-02-10)
75** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
76** Update of SystemInit() and SystemCoreClockUpdate() functions.
77** - rev. 2.5 (2014-02-10)
78** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
79** Update of SystemInit() and SystemCoreClockUpdate() functions.
80** Module access macro module_BASES replaced by module_BASE_PTRS.
81** - rev. 2.6 (2014-08-28)
82** Update of system files - default clock configuration changed.
83** Update of startup files - possibility to override DefaultISR added.
84** - rev. 2.7 (2014-10-14)
85** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
86** - rev. 2.8 (2015-02-19)
87** Renamed interrupt vector LLW to LLWU.
88** - rev. 2.9 (2016-03-21)
89** Added MK64FN1M0CAJ12 part.
90** GPIO - renamed port instances: PTx -> GPIOx.
91**
92** ###################################################################
93*/
94
95/*!
96 * @file MK64F12.h
97 * @version 2.9
98 * @date 2016-03-21
99 * @brief CMSIS Peripheral Access Layer for MK64F12
100 *
101 * CMSIS Peripheral Access Layer for MK64F12
102 */
103
104#ifndef _MK64F12_H_
105#define _MK64F12_H_ /**< Symbol preventing repeated inclusion */
106
107/** Memory map major version (memory maps with equal major version number are
108 * compatible) */
109#define MCU_MEM_MAP_VERSION 0x0200U
110/** Memory map minor version */
111#define MCU_MEM_MAP_VERSION_MINOR 0x0009U
112
113/**
114 * @brief Macro to calculate address of an aliased word in the peripheral
115 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
116 * 0x400FFFFF).
117 * @param Reg Register to access.
118 * @param Bit Bit number to access.
119 * @return Address of the aliased word in the peripheral bitband area.
120 */
121#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
122/**
123 * @brief Macro to access a single bit of a peripheral register (bit band region
124 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
125 * be used for peripherals with 32bit access allowed.
126 * @param Reg Register to access.
127 * @param Bit Bit number to access.
128 * @return Value of the targeted bit in the bit band region.
129 */
130#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
131#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
132/**
133 * @brief Macro to access a single bit of a peripheral register (bit band region
134 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
135 * be used for peripherals with 16bit access allowed.
136 * @param Reg Register to access.
137 * @param Bit Bit number to access.
138 * @return Value of the targeted bit in the bit band region.
139 */
140#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
141/**
142 * @brief Macro to access a single bit of a peripheral register (bit band region
143 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
144 * be used for peripherals with 8bit access allowed.
145 * @param Reg Register to access.
146 * @param Bit Bit number to access.
147 * @return Value of the targeted bit in the bit band region.
148 */
149#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
150
151/* ----------------------------------------------------------------------------
152 -- Interrupt vector numbers
153 ---------------------------------------------------------------------------- */
154
155/*!
156 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
157 * @{
158 */
159
160/** Interrupt Number Definitions */
161#define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */
162
163typedef enum IRQn {
164 /* Auxiliary constants */
165 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
166
167 /* Core interrupts */
168 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
169 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
170 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
171 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
172 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
173 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
174 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
175 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
176 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
177
178 /* Device specific interrupts */
179 DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
180 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
181 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
182 DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
183 DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
184 DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
185 DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
186 DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
187 DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
188 DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
189 DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
190 DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
191 DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
192 DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
193 DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
194 DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
195 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
196 MCM_IRQn = 17, /**< Normal Interrupt */
197 FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
198 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
199 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
200 LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */
201 WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */
202 RNG_IRQn = 23, /**< RNG Interrupt */
203 I2C0_IRQn = 24, /**< I2C0 interrupt */
204 I2C1_IRQn = 25, /**< I2C1 interrupt */
205 SPI0_IRQn = 26, /**< SPI0 Interrupt */
206 SPI1_IRQn = 27, /**< SPI1 Interrupt */
207 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
208 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
209 UART0_LON_IRQn = 30, /**< UART0 LON interrupt */
210 UART0Status_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
211 UART0Error_IRQn = 32, /**< UART0 Error interrupt */
212 UART1Status_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
213 UART1Error_IRQn = 34, /**< UART1 Error interrupt */
214 UART2Status_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
215 UART2Error_IRQn = 36, /**< UART2 Error interrupt */
216 UART3Status_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
217 UART3Error_IRQn = 38, /**< UART3 Error interrupt */
218 ADC0_IRQn = 39, /**< ADC0 interrupt */
219 CMP0_IRQn = 40, /**< CMP0 interrupt */
220 CMP1_IRQn = 41, /**< CMP1 interrupt */
221 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
222 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
223 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
224 CMT_IRQn = 45, /**< CMT interrupt */
225 RTC_IRQn = 46, /**< RTC interrupt */
226 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
227 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
228 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
229 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
230 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
231 PDB0_IRQn = 52, /**< PDB0 Interrupt */
232 USB0_IRQn = 53, /**< USB0 interrupt */
233 USBDCD_IRQn = 54, /**< USBDCD Interrupt */
234 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
235 DAC0_IRQn = 56, /**< DAC0 interrupt */
236 MCG_IRQn = 57, /**< MCG Interrupt */
237 LPTMR0_IRQn = 58, /**< LPTimer interrupt */
238 PORTA_IRQn = 59, /**< Port A interrupt */
239 PORTB_IRQn = 60, /**< Port B interrupt */
240 PORTC_IRQn = 61, /**< Port C interrupt */
241 PORTD_IRQn = 62, /**< Port D interrupt */
242 PORTE_IRQn = 63, /**< Port E interrupt */
243 SWI_IRQn = 64, /**< Software interrupt */
244 SPI2_IRQn = 65, /**< SPI2 Interrupt */
245 UART4Status_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
246 UART4Error_IRQn = 67, /**< UART4 Error interrupt */
247 UART5Status_IRQn = 68, /**< UART5 Receive/Transmit interrupt */
248 UART5Error_IRQn = 69, /**< UART5 Error interrupt */
249 CMP2_IRQn = 70, /**< CMP2 interrupt */
250 FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
251 DAC1_IRQn = 72, /**< DAC1 interrupt */
252 ADC1_IRQn = 73, /**< ADC1 interrupt */
253 I2C2_IRQn = 74, /**< I2C2 interrupt */
254 CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
255 CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
256 CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
257 CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
258 CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
259 CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
260 SDHC_IRQn = 81, /**< SDHC interrupt */
261 ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
262 ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */
263 ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */
264 ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */
265} IRQn_Type;
266
267/*!
268 * @}
269 */ /* end of group Interrupt_vector_numbers */
270
271
272/* ----------------------------------------------------------------------------
273 -- Cortex M4 Core Configuration
274 ---------------------------------------------------------------------------- */
275
276/*!
277 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
278 * @{
279 */
280
281#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
282#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
283#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
284#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
285
286#include "core_cm4.h" /* Core Peripheral Access Layer */
287/* #include "system_MK64F12.h" /+ Device specific configuration file */
288
289/*!
290 * @}
291 */ /* end of group Cortex_Core_Configuration */
292
293
294/* ----------------------------------------------------------------------------
295 -- Mapping Information
296 ---------------------------------------------------------------------------- */
297
298/*!
299 * @addtogroup Mapping_Information Mapping Information
300 * @{
301 */
302
303/** Mapping Information */
304/*!
305 * @addtogroup edma_request
306 * @{
307 */
308
309/*******************************************************************************
310 * Definitions
311 ******************************************************************************/
312
313/*!
314 * @brief Structure for the DMA hardware request
315 *
316 * Defines the structure for the DMA hardware request collections. The user can configure the
317 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
318 * of the hardware request varies according to the to SoC.
319 */
320typedef enum _dma_request_source
321{
322 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
323 kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
324 kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */
325 kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */
326 kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */
327 kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */
328 kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */
329 kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */
330 kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 Receive. */
331 kDmaRequestMux0UART3Tx = 9|0x100U, /**< UART3 Transmit. */
332 kDmaRequestMux0UART4 = 10|0x100U, /**< UART4 Transmit or Receive. */
333 kDmaRequestMux0UART5 = 11|0x100U, /**< UART5 Transmit or Receive. */
334 kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */
335 kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */
336 kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
337 kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
338 kDmaRequestMux0SPI1 = 16|0x100U, /**< SPI1 Transmit or Receive. */
339 kDmaRequestMux0SPI2 = 17|0x100U, /**< SPI2 Transmit or Receive. */
340 kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0. */
341 kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
342 kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */
343 kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
344 kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
345 kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
346 kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
347 kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
348 kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
349 kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
350 kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */
351 kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */
352 kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */
353 kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */
354 kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */
355 kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */
356 kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */
357 kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */
358 kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */
359 kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */
360 kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */
361 kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */
362 kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V. */
363 kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V. */
364 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
365 kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */
366 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
367 kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
368 kDmaRequestMux0CMP2 = 44|0x100U, /**< CMP2. */
369 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
370 kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1. */
371 kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */
372 kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
373 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
374 kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
375 kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
376 kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
377 kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
378 kDmaRequestMux0IEEE1588Timer0 = 54|0x100U, /**< ENET IEEE 1588 timer 0. */
379 kDmaRequestMux0IEEE1588Timer1 = 55|0x100U, /**< ENET IEEE 1588 timer 1. */
380 kDmaRequestMux0IEEE1588Timer2 = 56|0x100U, /**< ENET IEEE 1588 timer 2. */
381 kDmaRequestMux0IEEE1588Timer3 = 57|0x100U, /**< ENET IEEE 1588 timer 3. */
382 kDmaRequestMux0AlwaysOn58 = 58|0x100U, /**< DMAMUX Always Enabled slot. */
383 kDmaRequestMux0AlwaysOn59 = 59|0x100U, /**< DMAMUX Always Enabled slot. */
384 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
385 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
386 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
387 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
388} dma_request_source_t;
389
390/* @} */
391
392
393/*!
394 * @}
395 */ /* end of group Mapping_Information */
396
397
398/* ----------------------------------------------------------------------------
399 -- Device Peripheral Access Layer
400 ---------------------------------------------------------------------------- */
401
402/*!
403 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
404 * @{
405 */
406
407
408/*
409** Start of section using anonymous unions
410*/
411
412#if defined(__ARMCC_VERSION)
413 #pragma push
414 #pragma anon_unions
415#elif defined(__CWCC__)
416 #pragma push
417 #pragma cpp_extensions on
418#elif defined(__GNUC__)
419 /* anonymous unions are enabled by default */
420#elif defined(__IAR_SYSTEMS_ICC__)
421 #pragma language=extended
422#else
423 #error Not supported compiler type
424#endif
425
426/* ----------------------------------------------------------------------------
427 -- ADC Peripheral Access Layer
428 ---------------------------------------------------------------------------- */
429
430/*!
431 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
432 * @{
433 */
434
435/** ADC - Register Layout Typedef */
436typedef struct {
437 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
438 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
439 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
440 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
441 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
442 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
443 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
444 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
445 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
446 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
447 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
448 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
449 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
450 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
451 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
452 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
453 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
454 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
455 uint8_t RESERVED_0[4];
456 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
457 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
458 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
459 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
460 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
461 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
462 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
463} ADC_TypeDef;
464
465/* ----------------------------------------------------------------------------
466 -- ADC Register Masks
467 ---------------------------------------------------------------------------- */
468
469/*!
470 * @addtogroup ADC_Register_Masks ADC Register Masks
471 * @{
472 */
473
474/*! @name SC1 - ADC Status and Control Registers 1 */
475#define ADCx_SC1n_ADCH_MASK (0x1FU)
476#define ADCx_SC1n_ADCH_SHIFT (0U)
477#define ADCx_SC1n_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC1n_ADCH_SHIFT)) & ADCx_SC1n_ADCH_MASK)
478#define ADCx_SC1n_DIFF (0x20U)
479#define ADCx_SC1n_AIEN (0x40U)
480#define ADCx_SC1n_COCO (0x80U)
481
482/* The count of ADC_SC1 */
483#define ADCx_SC1_COUNT (2U)
484
485/*! @name CFG1 - ADC Configuration Register 1 */
486#define ADCx_CFG1_ADICLK_MASK (0x3U)
487#define ADCx_CFG1_ADICLK_SHIFT (0U)
488#define ADCx_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_ADICLK_SHIFT)) & ADCx_CFG1_ADICLK_MASK)
489#define ADCx_CFG1_MODE_MASK (0xCU)
490#define ADCx_CFG1_MODE_SHIFT (2U)
491#define ADCx_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_MODE_SHIFT)) & ADCx_CFG1_MODE_MASK)
492#define ADCx_CFG1_ADLSMP (0x10U)
493#define ADCx_CFG1_ADIV_MASK (0x60U)
494#define ADCx_CFG1_ADIV_SHIFT (5U)
495#define ADCx_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_ADIV_SHIFT)) & ADCx_CFG1_ADIV_MASK)
496#define ADCx_CFG1_ADLPC (0x80U)
497
498/*! @name CFG2 - ADC Configuration Register 2 */
499#define ADCx_CFG2_ADLSTS_MASK (0x3U)
500#define ADCx_CFG2_ADLSTS_SHIFT (0U)
501#define ADCx_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CFG2_ADLSTS_SHIFT)) & ADCx_CFG2_ADLSTS_MASK)
502#define ADCx_CFG2_ADHSC (0x4U)
503#define ADCx_CFG2_ADACKEN (0x8U)
504#define ADCx_CFG2_MUXSEL (0x10U)
505
506/*! @name R - ADC Data Result Register */
507#define ADCx_Rn_D_MASK (0xFFFFU)
508#define ADCx_Rn_D_SHIFT (0U)
509#define ADCx_Rn_D(x) (((uint32_t)(((uint32_t)(x)) << ADCx_R_D_SHIFT)) & ADCx_R_D_MASK)
510
511/* The count of ADC_R */
512#define ADCx_R_COUNT (2U)
513
514/*! @name CV1 - Compare Value Registers */
515#define ADCx_CV1_CV_MASK (0xFFFFU)
516#define ADCx_CV1_CV_SHIFT (0U)
517#define ADCx_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CV1_CV_SHIFT)) & ADCx_CV1_CV_MASK)
518
519/*! @name CV2 - Compare Value Registers */
520#define ADCx_CV2_CV_MASK (0xFFFFU)
521#define ADCx_CV2_CV_SHIFT (0U)
522#define ADCx_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CV2_CV_SHIFT)) & ADCx_CV2_CV_MASK)
523
524/*! @name SC2 - Status and Control Register 2 */
525#define ADCx_SC2_REFSEL_MASK (0x3U)
526#define ADCx_SC2_REFSEL_SHIFT (0U)
527#define ADCx_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_REFSEL_SHIFT)) & ADCx_SC2_REFSEL_MASK)
528#define ADCx_SC2_DMAEN (0x4U)
529#define ADCx_SC2_ACREN (0x8U)
530#define ADCx_SC2_ACFGT (0x10U)
531#define ADCx_SC2_ACFE (0x20U)
532#define ADCx_SC2_ADTRG (0x40U)
533#define ADCx_SC2_ADACT (0x80U)
534
535/*! @name SC3 - Status and Control Register 3 */
536#define ADCx_SC3_AVGS_MASK (0x3U)
537#define ADCx_SC3_AVGS_SHIFT (0U)
538#define ADCx_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADCx_SC3_AVGS_SHIFT)) & ADCx_SC3_AVGS_MASK)
539#define ADCx_SC3_AVGE (0x4U)
540#define ADCx_SC3_ADCO (0x8U)
541#define ADCx_SC3_CALF (0x40U)
542#define ADCx_SC3_CAL (0x80U)
543
544/*! @name OFS - ADC Offset Correction Register */
545#define ADCx_OFS_OFS_MASK (0xFFFFU)
546#define ADCx_OFS_OFS_SHIFT (0U)
547#define ADCx_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADCx_OFS_OFS_SHIFT)) & ADCx_OFS_OFS_MASK)
548
549/*! @name PG - ADC Plus-Side Gain Register */
550#define ADCx_PG_PG_MASK (0xFFFFU)
551#define ADCx_PG_PG_SHIFT (0U)
552#define ADCx_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADCx_PG_PG_SHIFT)) & ADCx_PG_PG_MASK)
553
554/*! @name MG - ADC Minus-Side Gain Register */
555#define ADCx_MG_MG_MASK (0xFFFFU)
556#define ADCx_MG_MG_SHIFT (0U)
557#define ADCx_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADCx_MG_MG_SHIFT)) & ADCx_MG_MG_MASK)
558
559/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
560#define ADCx_CLPD_CLPD_MASK (0x3FU)
561#define ADCx_CLPD_CLPD_SHIFT (0U)
562#define ADCx_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLPD_CLPD_SHIFT)) & ADCx_CLPD_CLPD_MASK)
563
564/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
565#define ADCx_CLPS_CLPS_MASK (0x3FU)
566#define ADCx_CLPS_CLPS_SHIFT (0U)
567#define ADCx_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLPS_CLPS_SHIFT)) & ADCx_CLPS_CLPS_MASK)
568
569/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
570#define ADCx_CLP4_CLP4_MASK (0x3FFU)
571#define ADCx_CLP4_CLP4_SHIFT (0U)
572#define ADCx_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLP4_CLP4_SHIFT)) & ADCx_CLP4_CLP4_MASK)
573
574/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
575#define ADCx_CLP3_CLP3_MASK (0x1FFU)
576#define ADCx_CLP3_CLP3_SHIFT (0U)
577#define ADCx_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLP3_CLP3_SHIFT)) & ADCx_CLP3_CLP3_MASK)
578
579/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
580#define ADCx_CLP2_CLP2_MASK (0xFFU)
581#define ADCx_CLP2_CLP2_SHIFT (0U)
582#define ADCx_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLP2_CLP2_SHIFT)) & ADCx_CLP2_CLP2_MASK)
583
584/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
585#define ADCx_CLP1_CLP1_MASK (0x7FU)
586#define ADCx_CLP1_CLP1_SHIFT (0U)
587#define ADCx_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLP1_CLP1_SHIFT)) & ADCx_CLP1_CLP1_MASK)
588
589/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
590#define ADCx_CLP0_CLP0_MASK (0x3FU)
591#define ADCx_CLP0_CLP0_SHIFT (0U)
592#define ADCx_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLP0_CLP0_SHIFT)) & ADCx_CLP0_CLP0_MASK)
593
594/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
595#define ADCx_CLMD_CLMD_MASK (0x3FU)
596#define ADCx_CLMD_CLMD_SHIFT (0U)
597#define ADCx_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLMD_CLMD_SHIFT)) & ADCx_CLMD_CLMD_MASK)
598
599/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
600#define ADCx_CLMS_CLMS_MASK (0x3FU)
601#define ADCx_CLMS_CLMS_SHIFT (0U)
602#define ADCx_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLMS_CLMS_SHIFT)) & ADCx_CLMS_CLMS_MASK)
603
604/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
605#define ADCx_CLM4_CLM4_MASK (0x3FFU)
606#define ADCx_CLM4_CLM4_SHIFT (0U)
607#define ADCx_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLM4_CLM4_SHIFT)) & ADCx_CLM4_CLM4_MASK)
608
609/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
610#define ADCx_CLM3_CLM3_MASK (0x1FFU)
611#define ADCx_CLM3_CLM3_SHIFT (0U)
612#define ADCx_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLM3_CLM3_SHIFT)) & ADCx_CLM3_CLM3_MASK)
613
614/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
615#define ADCx_CLM2_CLM2_MASK (0xFFU)
616#define ADCx_CLM2_CLM2_SHIFT (0U)
617#define ADCx_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLM2_CLM2_SHIFT)) & ADCx_CLM2_CLM2_MASK)
618
619/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
620#define ADCx_CLM1_CLM1_MASK (0x7FU)
621#define ADCx_CLM1_CLM1_SHIFT (0U)
622#define ADCx_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLM1_CLM1_SHIFT)) & ADCx_CLM1_CLM1_MASK)
623
624/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
625#define ADCx_CLM0_CLM0_MASK (0x3FU)
626#define ADCx_CLM0_CLM0_SHIFT (0U)
627#define ADCx_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADCx_CLM0_CLM0_SHIFT)) & ADCx_CLM0_CLM0_MASK)
628
629
630/*!
631 * @}
632 */ /* end of group ADC_Register_Masks */
633
634
635/* ADC - Peripheral instance base addresses */
636/** Peripheral ADC0 base address */
637#define ADC0_BASE (0x4003B000u)
638/** Peripheral ADC0 base pointer */
639#define ADC0 ((ADC_TypeDef *)ADC0_BASE)
640/** Peripheral ADC1 base address */
641#define ADC1_BASE (0x400BB000u)
642/** Peripheral ADC1 base pointer */
643#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
644/** Array initializer of ADC peripheral base addresses */
645#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
646/** Array initializer of ADC peripheral base pointers */
647#define ADC_BASE_PTRS { ADC0, ADC1 }
648/** Interrupt vectors for the ADC peripheral type */
649#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
650
651/*!
652 * @}
653 */ /* end of group ADC_Peripheral_Access_Layer */
654
655
656/* ----------------------------------------------------------------------------
657 -- AIPS Peripheral Access Layer
658 ---------------------------------------------------------------------------- */
659
660/*!
661 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
662 * @{
663 */
664
665/** AIPS - Register Layout Typedef */
666typedef struct {
667 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
668 uint8_t RESERVED_0[28];
669 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
670 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
671 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
672 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
673 uint8_t RESERVED_1[16];
674 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
675 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
676 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
677 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
678 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
679 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
680 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
681 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
682 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
683 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
684 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
685 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
686 uint8_t RESERVED_2[16];
687 __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */
688} AIPS_TypeDef;
689
690/* ----------------------------------------------------------------------------
691 -- AIPS Register Masks
692 ---------------------------------------------------------------------------- */
693
694/*!
695 * @addtogroup AIPS_Register_Masks AIPS Register Masks
696 * @{
697 */
698
699/*! @name MPRA - Master Privilege Register A */
700#define AIPS_MPRA_MPL5 (0x100U)
701#define AIPS_MPRA_MTW5 (0x200U)
702#define AIPS_MPRA_MTR5 (0x400U)
703#define AIPS_MPRA_MPL4 (0x1000U)
704#define AIPS_MPRA_MTW4 (0x2000U)
705#define AIPS_MPRA_MTR4 (0x4000U)
706#define AIPS_MPRA_MPL3 (0x10000U)
707#define AIPS_MPRA_MTW3 (0x20000U)
708#define AIPS_MPRA_MTR3 (0x40000U)
709#define AIPS_MPRA_MPL2 (0x100000U)
710#define AIPS_MPRA_MTW2 (0x200000U)
711#define AIPS_MPRA_MTR2 (0x400000U)
712#define AIPS_MPRA_MPL1 (0x1000000U)
713#define AIPS_MPRA_MTW1 (0x2000000U)
714#define AIPS_MPRA_MTR1 (0x4000000U)
715#define AIPS_MPRA_MPL0 (0x10000000U)
716#define AIPS_MPRA_MTW0 (0x20000000U)
717#define AIPS_MPRA_MTR0 (0x40000000U)
718
719/*! @name PACRA - Peripheral Access Control Register */
720#define AIPS_PACRA_TP7 (0x1U)
721#define AIPS_PACRA_WP7 (0x2U)
722#define AIPS_PACRA_SP7 (0x4U)
723#define AIPS_PACRA_TP6 (0x10U)
724#define AIPS_PACRA_WP6 (0x20U)
725#define AIPS_PACRA_SP6 (0x40U)
726#define AIPS_PACRA_TP5 (0x100U)
727#define AIPS_PACRA_WP5 (0x200U)
728#define AIPS_PACRA_SP5 (0x400U)
729#define AIPS_PACRA_TP4 (0x1000U)
730#define AIPS_PACRA_WP4 (0x2000U)
731#define AIPS_PACRA_SP4 (0x4000U)
732#define AIPS_PACRA_TP3 (0x10000U)
733#define AIPS_PACRA_WP3 (0x20000U)
734#define AIPS_PACRA_SP3 (0x40000U)
735#define AIPS_PACRA_TP2 (0x100000U)
736#define AIPS_PACRA_WP2 (0x200000U)
737#define AIPS_PACRA_SP2 (0x400000U)
738#define AIPS_PACRA_TP1 (0x1000000U)
739#define AIPS_PACRA_WP1 (0x2000000U)
740#define AIPS_PACRA_SP1 (0x4000000U)
741#define AIPS_PACRA_TP0 (0x10000000U)
742#define AIPS_PACRA_WP0 (0x20000000U)
743#define AIPS_PACRA_SP0 (0x40000000U)
744
745/*! @name PACRB - Peripheral Access Control Register */
746#define AIPS_PACRB_TP7 (0x1U)
747#define AIPS_PACRB_WP7 (0x2U)
748#define AIPS_PACRB_SP7 (0x4U)
749#define AIPS_PACRB_TP6 (0x10U)
750#define AIPS_PACRB_WP6 (0x20U)
751#define AIPS_PACRB_SP6 (0x40U)
752#define AIPS_PACRB_TP5 (0x100U)
753#define AIPS_PACRB_WP5 (0x200U)
754#define AIPS_PACRB_SP5 (0x400U)
755#define AIPS_PACRB_TP4 (0x1000U)
756#define AIPS_PACRB_WP4 (0x2000U)
757#define AIPS_PACRB_SP4 (0x4000U)
758#define AIPS_PACRB_TP3 (0x10000U)
759#define AIPS_PACRB_WP3 (0x20000U)
760#define AIPS_PACRB_SP3 (0x40000U)
761#define AIPS_PACRB_TP2 (0x100000U)
762#define AIPS_PACRB_WP2 (0x200000U)
763#define AIPS_PACRB_SP2 (0x400000U)
764#define AIPS_PACRB_TP1 (0x1000000U)
765#define AIPS_PACRB_WP1 (0x2000000U)
766#define AIPS_PACRB_SP1 (0x4000000U)
767#define AIPS_PACRB_TP0 (0x10000000U)
768#define AIPS_PACRB_WP0 (0x20000000U)
769#define AIPS_PACRB_SP0 (0x40000000U)
770
771/*! @name PACRC - Peripheral Access Control Register */
772#define AIPS_PACRC_TP7 (0x1U)
773#define AIPS_PACRC_WP7 (0x2U)
774#define AIPS_PACRC_SP7 (0x4U)
775#define AIPS_PACRC_TP6 (0x10U)
776#define AIPS_PACRC_WP6 (0x20U)
777#define AIPS_PACRC_SP6 (0x40U)
778#define AIPS_PACRC_TP5 (0x100U)
779#define AIPS_PACRC_WP5 (0x200U)
780#define AIPS_PACRC_SP5 (0x400U)
781#define AIPS_PACRC_TP4 (0x1000U)
782#define AIPS_PACRC_WP4 (0x2000U)
783#define AIPS_PACRC_SP4 (0x4000U)
784#define AIPS_PACRC_TP3 (0x10000U)
785#define AIPS_PACRC_WP3 (0x20000U)
786#define AIPS_PACRC_SP3 (0x40000U)
787#define AIPS_PACRC_TP2 (0x100000U)
788#define AIPS_PACRC_WP2 (0x200000U)
789#define AIPS_PACRC_SP2 (0x400000U)
790#define AIPS_PACRC_TP1 (0x1000000U)
791#define AIPS_PACRC_WP1 (0x2000000U)
792#define AIPS_PACRC_SP1 (0x4000000U)
793#define AIPS_PACRC_TP0 (0x10000000U)
794#define AIPS_PACRC_WP0 (0x20000000U)
795#define AIPS_PACRC_SP0 (0x40000000U)
796
797/*! @name PACRD - Peripheral Access Control Register */
798#define AIPS_PACRD_TP7 (0x1U)
799#define AIPS_PACRD_WP7 (0x2U)
800#define AIPS_PACRD_SP7 (0x4U)
801#define AIPS_PACRD_TP6 (0x10U)
802#define AIPS_PACRD_WP6 (0x20U)
803#define AIPS_PACRD_SP6 (0x40U)
804#define AIPS_PACRD_TP5 (0x100U)
805#define AIPS_PACRD_WP5 (0x200U)
806#define AIPS_PACRD_SP5 (0x400U)
807#define AIPS_PACRD_TP4 (0x1000U)
808#define AIPS_PACRD_WP4 (0x2000U)
809#define AIPS_PACRD_SP4 (0x4000U)
810#define AIPS_PACRD_TP3 (0x10000U)
811#define AIPS_PACRD_WP3 (0x20000U)
812#define AIPS_PACRD_SP3 (0x40000U)
813#define AIPS_PACRD_TP2 (0x100000U)
814#define AIPS_PACRD_WP2 (0x200000U)
815#define AIPS_PACRD_SP2 (0x400000U)
816#define AIPS_PACRD_TP1 (0x1000000U)
817#define AIPS_PACRD_WP1 (0x2000000U)
818#define AIPS_PACRD_SP1 (0x4000000U)
819#define AIPS_PACRD_TP0 (0x10000000U)
820#define AIPS_PACRD_WP0 (0x20000000U)
821#define AIPS_PACRD_SP0 (0x40000000U)
822
823/*! @name PACRE - Peripheral Access Control Register */
824#define AIPS_PACRE_TP7 (0x1U)
825#define AIPS_PACRE_WP7 (0x2U)
826#define AIPS_PACRE_SP7 (0x4U)
827#define AIPS_PACRE_TP6 (0x10U)
828#define AIPS_PACRE_WP6 (0x20U)
829#define AIPS_PACRE_SP6 (0x40U)
830#define AIPS_PACRE_TP5 (0x100U)
831#define AIPS_PACRE_WP5 (0x200U)
832#define AIPS_PACRE_SP5 (0x400U)
833#define AIPS_PACRE_TP4 (0x1000U)
834#define AIPS_PACRE_WP4 (0x2000U)
835#define AIPS_PACRE_SP4 (0x4000U)
836#define AIPS_PACRE_TP3 (0x10000U)
837#define AIPS_PACRE_WP3 (0x20000U)
838#define AIPS_PACRE_SP3 (0x40000U)
839#define AIPS_PACRE_TP2 (0x100000U)
840#define AIPS_PACRE_WP2 (0x200000U)
841#define AIPS_PACRE_SP2 (0x400000U)
842#define AIPS_PACRE_TP1 (0x1000000U)
843#define AIPS_PACRE_WP1 (0x2000000U)
844#define AIPS_PACRE_SP1 (0x4000000U)
845#define AIPS_PACRE_TP0 (0x10000000U)
846#define AIPS_PACRE_WP0 (0x20000000U)
847#define AIPS_PACRE_SP0 (0x40000000U)
848
849/*! @name PACRF - Peripheral Access Control Register */
850#define AIPS_PACRF_TP7 (0x1U)
851#define AIPS_PACRF_WP7 (0x2U)
852#define AIPS_PACRF_SP7 (0x4U)
853#define AIPS_PACRF_TP6 (0x10U)
854#define AIPS_PACRF_WP6 (0x20U)
855#define AIPS_PACRF_SP6 (0x40U)
856#define AIPS_PACRF_TP5 (0x100U)
857#define AIPS_PACRF_WP5 (0x200U)
858#define AIPS_PACRF_SP5 (0x400U)
859#define AIPS_PACRF_TP4 (0x1000U)
860#define AIPS_PACRF_WP4 (0x2000U)
861#define AIPS_PACRF_SP4 (0x4000U)
862#define AIPS_PACRF_TP3 (0x10000U)
863#define AIPS_PACRF_WP3 (0x20000U)
864#define AIPS_PACRF_SP3 (0x40000U)
865#define AIPS_PACRF_TP2 (0x100000U)
866#define AIPS_PACRF_WP2 (0x200000U)
867#define AIPS_PACRF_SP2 (0x400000U)
868#define AIPS_PACRF_TP1 (0x1000000U)
869#define AIPS_PACRF_WP1 (0x2000000U)
870#define AIPS_PACRF_SP1 (0x4000000U)
871#define AIPS_PACRF_TP0 (0x10000000U)
872#define AIPS_PACRF_WP0 (0x20000000U)
873#define AIPS_PACRF_SP0 (0x40000000U)
874
875/*! @name PACRG - Peripheral Access Control Register */
876#define AIPS_PACRG_TP7 (0x1U)
877#define AIPS_PACRG_WP7 (0x2U)
878#define AIPS_PACRG_SP7 (0x4U)
879#define AIPS_PACRG_TP6 (0x10U)
880#define AIPS_PACRG_WP6 (0x20U)
881#define AIPS_PACRG_SP6 (0x40U)
882#define AIPS_PACRG_TP5 (0x100U)
883#define AIPS_PACRG_WP5 (0x200U)
884#define AIPS_PACRG_SP5 (0x400U)
885#define AIPS_PACRG_TP4 (0x1000U)
886#define AIPS_PACRG_WP4 (0x2000U)
887#define AIPS_PACRG_SP4 (0x4000U)
888#define AIPS_PACRG_TP3 (0x10000U)
889#define AIPS_PACRG_WP3 (0x20000U)
890#define AIPS_PACRG_SP3 (0x40000U)
891#define AIPS_PACRG_TP2 (0x100000U)
892#define AIPS_PACRG_WP2 (0x200000U)
893#define AIPS_PACRG_SP2 (0x400000U)
894#define AIPS_PACRG_TP1 (0x1000000U)
895#define AIPS_PACRG_WP1 (0x2000000U)
896#define AIPS_PACRG_SP1 (0x4000000U)
897#define AIPS_PACRG_TP0 (0x10000000U)
898#define AIPS_PACRG_WP0 (0x20000000U)
899#define AIPS_PACRG_SP0 (0x40000000U)
900
901/*! @name PACRH - Peripheral Access Control Register */
902#define AIPS_PACRH_TP7 (0x1U)
903#define AIPS_PACRH_WP7 (0x2U)
904#define AIPS_PACRH_SP7 (0x4U)
905#define AIPS_PACRH_TP6 (0x10U)
906#define AIPS_PACRH_WP6 (0x20U)
907#define AIPS_PACRH_SP6 (0x40U)
908#define AIPS_PACRH_TP5 (0x100U)
909#define AIPS_PACRH_WP5 (0x200U)
910#define AIPS_PACRH_SP5 (0x400U)
911#define AIPS_PACRH_TP4 (0x1000U)
912#define AIPS_PACRH_WP4 (0x2000U)
913#define AIPS_PACRH_SP4 (0x4000U)
914#define AIPS_PACRH_TP3 (0x10000U)
915#define AIPS_PACRH_WP3 (0x20000U)
916#define AIPS_PACRH_SP3 (0x40000U)
917#define AIPS_PACRH_TP2 (0x100000U)
918#define AIPS_PACRH_WP2 (0x200000U)
919#define AIPS_PACRH_SP2 (0x400000U)
920#define AIPS_PACRH_TP1 (0x1000000U)
921#define AIPS_PACRH_WP1 (0x2000000U)
922#define AIPS_PACRH_SP1 (0x4000000U)
923#define AIPS_PACRH_TP0 (0x10000000U)
924#define AIPS_PACRH_WP0 (0x20000000U)
925#define AIPS_PACRH_SP0 (0x40000000U)
926
927/*! @name PACRI - Peripheral Access Control Register */
928#define AIPS_PACRI_TP7 (0x1U)
929#define AIPS_PACRI_WP7 (0x2U)
930#define AIPS_PACRI_SP7 (0x4U)
931#define AIPS_PACRI_TP6 (0x10U)
932#define AIPS_PACRI_WP6 (0x20U)
933#define AIPS_PACRI_SP6 (0x40U)
934#define AIPS_PACRI_TP5 (0x100U)
935#define AIPS_PACRI_WP5 (0x200U)
936#define AIPS_PACRI_SP5 (0x400U)
937#define AIPS_PACRI_TP4 (0x1000U)
938#define AIPS_PACRI_WP4 (0x2000U)
939#define AIPS_PACRI_SP4 (0x4000U)
940#define AIPS_PACRI_TP3 (0x10000U)
941#define AIPS_PACRI_WP3 (0x20000U)
942#define AIPS_PACRI_SP3 (0x40000U)
943#define AIPS_PACRI_TP2 (0x100000U)
944#define AIPS_PACRI_WP2 (0x200000U)
945#define AIPS_PACRI_SP2 (0x400000U)
946#define AIPS_PACRI_TP1 (0x1000000U)
947#define AIPS_PACRI_WP1 (0x2000000U)
948#define AIPS_PACRI_SP1 (0x4000000U)
949#define AIPS_PACRI_TP0 (0x10000000U)
950#define AIPS_PACRI_WP0 (0x20000000U)
951#define AIPS_PACRI_SP0 (0x40000000U)
952
953/*! @name PACRJ - Peripheral Access Control Register */
954#define AIPS_PACRJ_TP7 (0x1U)
955#define AIPS_PACRJ_WP7 (0x2U)
956#define AIPS_PACRJ_SP7 (0x4U)
957#define AIPS_PACRJ_TP6 (0x10U)
958#define AIPS_PACRJ_WP6 (0x20U)
959#define AIPS_PACRJ_SP6 (0x40U)
960#define AIPS_PACRJ_TP5 (0x100U)
961#define AIPS_PACRJ_WP5 (0x200U)
962#define AIPS_PACRJ_SP5 (0x400U)
963#define AIPS_PACRJ_TP4 (0x1000U)
964#define AIPS_PACRJ_WP4 (0x2000U)
965#define AIPS_PACRJ_SP4 (0x4000U)
966#define AIPS_PACRJ_TP3 (0x10000U)
967#define AIPS_PACRJ_WP3 (0x20000U)
968#define AIPS_PACRJ_SP3 (0x40000U)
969#define AIPS_PACRJ_TP2 (0x100000U)
970#define AIPS_PACRJ_WP2 (0x200000U)
971#define AIPS_PACRJ_SP2 (0x400000U)
972#define AIPS_PACRJ_TP1 (0x1000000U)
973#define AIPS_PACRJ_WP1 (0x2000000U)
974#define AIPS_PACRJ_SP1 (0x4000000U)
975#define AIPS_PACRJ_TP0 (0x10000000U)
976#define AIPS_PACRJ_WP0 (0x20000000U)
977#define AIPS_PACRJ_SP0 (0x40000000U)
978
979/*! @name PACRK - Peripheral Access Control Register */
980#define AIPS_PACRK_TP7 (0x1U)
981#define AIPS_PACRK_WP7 (0x2U)
982#define AIPS_PACRK_SP7 (0x4U)
983#define AIPS_PACRK_TP6 (0x10U)
984#define AIPS_PACRK_WP6 (0x20U)
985#define AIPS_PACRK_SP6 (0x40U)
986#define AIPS_PACRK_TP5 (0x100U)
987#define AIPS_PACRK_WP5 (0x200U)
988#define AIPS_PACRK_SP5 (0x400U)
989#define AIPS_PACRK_TP4 (0x1000U)
990#define AIPS_PACRK_WP4 (0x2000U)
991#define AIPS_PACRK_SP4 (0x4000U)
992#define AIPS_PACRK_TP3 (0x10000U)
993#define AIPS_PACRK_WP3 (0x20000U)
994#define AIPS_PACRK_SP3 (0x40000U)
995#define AIPS_PACRK_TP2 (0x100000U)
996#define AIPS_PACRK_WP2 (0x200000U)
997#define AIPS_PACRK_SP2 (0x400000U)
998#define AIPS_PACRK_TP1 (0x1000000U)
999#define AIPS_PACRK_WP1 (0x2000000U)
1000#define AIPS_PACRK_SP1 (0x4000000U)
1001#define AIPS_PACRK_TP0 (0x10000000U)
1002#define AIPS_PACRK_WP0 (0x20000000U)
1003#define AIPS_PACRK_SP0 (0x40000000U)
1004
1005/*! @name PACRL - Peripheral Access Control Register */
1006#define AIPS_PACRL_TP7 (0x1U)
1007#define AIPS_PACRL_WP7 (0x2U)
1008#define AIPS_PACRL_SP7 (0x4U)
1009#define AIPS_PACRL_TP6 (0x10U)
1010#define AIPS_PACRL_WP6 (0x20U)
1011#define AIPS_PACRL_SP6 (0x40U)
1012#define AIPS_PACRL_TP5 (0x100U)
1013#define AIPS_PACRL_WP5 (0x200U)
1014#define AIPS_PACRL_SP5 (0x400U)
1015#define AIPS_PACRL_TP4 (0x1000U)
1016#define AIPS_PACRL_WP4 (0x2000U)
1017#define AIPS_PACRL_SP4 (0x4000U)
1018#define AIPS_PACRL_TP3 (0x10000U)
1019#define AIPS_PACRL_WP3 (0x20000U)
1020#define AIPS_PACRL_SP3 (0x40000U)
1021#define AIPS_PACRL_TP2 (0x100000U)
1022#define AIPS_PACRL_WP2 (0x200000U)
1023#define AIPS_PACRL_SP2 (0x400000U)
1024#define AIPS_PACRL_TP1 (0x1000000U)
1025#define AIPS_PACRL_WP1 (0x2000000U)
1026#define AIPS_PACRL_SP1 (0x4000000U)
1027#define AIPS_PACRL_TP0 (0x10000000U)
1028#define AIPS_PACRL_WP0 (0x20000000U)
1029#define AIPS_PACRL_SP0 (0x40000000U)
1030
1031/*! @name PACRM - Peripheral Access Control Register */
1032#define AIPS_PACRM_TP7 (0x1U)
1033#define AIPS_PACRM_WP7 (0x2U)
1034#define AIPS_PACRM_SP7 (0x4U)
1035#define AIPS_PACRM_TP6 (0x10U)
1036#define AIPS_PACRM_WP6 (0x20U)
1037#define AIPS_PACRM_SP6 (0x40U)
1038#define AIPS_PACRM_TP5 (0x100U)
1039#define AIPS_PACRM_WP5 (0x200U)
1040#define AIPS_PACRM_SP5 (0x400U)
1041#define AIPS_PACRM_TP4 (0x1000U)
1042#define AIPS_PACRM_WP4 (0x2000U)
1043#define AIPS_PACRM_SP4 (0x4000U)
1044#define AIPS_PACRM_TP3 (0x10000U)
1045#define AIPS_PACRM_WP3 (0x20000U)
1046#define AIPS_PACRM_SP3 (0x40000U)
1047#define AIPS_PACRM_TP2 (0x100000U)
1048#define AIPS_PACRM_WP2 (0x200000U)
1049#define AIPS_PACRM_SP2 (0x400000U)
1050#define AIPS_PACRM_TP1 (0x1000000U)
1051#define AIPS_PACRM_WP1 (0x2000000U)
1052#define AIPS_PACRM_SP1 (0x4000000U)
1053#define AIPS_PACRM_TP0 (0x10000000U)
1054#define AIPS_PACRM_WP0 (0x20000000U)
1055#define AIPS_PACRM_SP0 (0x40000000U)
1056
1057/*! @name PACRN - Peripheral Access Control Register */
1058#define AIPS_PACRN_TP7 (0x1U)
1059#define AIPS_PACRN_WP7 (0x2U)
1060#define AIPS_PACRN_SP7 (0x4U)
1061#define AIPS_PACRN_TP6 (0x10U)
1062#define AIPS_PACRN_WP6 (0x20U)
1063#define AIPS_PACRN_SP6 (0x40U)
1064#define AIPS_PACRN_TP5 (0x100U)
1065#define AIPS_PACRN_WP5 (0x200U)
1066#define AIPS_PACRN_SP5 (0x400U)
1067#define AIPS_PACRN_TP4 (0x1000U)
1068#define AIPS_PACRN_WP4 (0x2000U)
1069#define AIPS_PACRN_SP4 (0x4000U)
1070#define AIPS_PACRN_TP3 (0x10000U)
1071#define AIPS_PACRN_WP3 (0x20000U)
1072#define AIPS_PACRN_SP3 (0x40000U)
1073#define AIPS_PACRN_TP2 (0x100000U)
1074#define AIPS_PACRN_WP2 (0x200000U)
1075#define AIPS_PACRN_SP2 (0x400000U)
1076#define AIPS_PACRN_TP1 (0x1000000U)
1077#define AIPS_PACRN_WP1 (0x2000000U)
1078#define AIPS_PACRN_SP1 (0x4000000U)
1079#define AIPS_PACRN_TP0 (0x10000000U)
1080#define AIPS_PACRN_WP0 (0x20000000U)
1081#define AIPS_PACRN_SP0 (0x40000000U)
1082
1083/*! @name PACRO - Peripheral Access Control Register */
1084#define AIPS_PACRO_TP7 (0x1U)
1085#define AIPS_PACRO_WP7 (0x2U)
1086#define AIPS_PACRO_SP7 (0x4U)
1087#define AIPS_PACRO_TP6 (0x10U)
1088#define AIPS_PACRO_WP6 (0x20U)
1089#define AIPS_PACRO_SP6 (0x40U)
1090#define AIPS_PACRO_TP5 (0x100U)
1091#define AIPS_PACRO_WP5 (0x200U)
1092#define AIPS_PACRO_SP5 (0x400U)
1093#define AIPS_PACRO_TP4 (0x1000U)
1094#define AIPS_PACRO_WP4 (0x2000U)
1095#define AIPS_PACRO_SP4 (0x4000U)
1096#define AIPS_PACRO_TP3 (0x10000U)
1097#define AIPS_PACRO_WP3 (0x20000U)
1098#define AIPS_PACRO_SP3 (0x40000U)
1099#define AIPS_PACRO_TP2 (0x100000U)
1100#define AIPS_PACRO_WP2 (0x200000U)
1101#define AIPS_PACRO_SP2 (0x400000U)
1102#define AIPS_PACRO_TP1 (0x1000000U)
1103#define AIPS_PACRO_WP1 (0x2000000U)
1104#define AIPS_PACRO_SP1 (0x4000000U)
1105#define AIPS_PACRO_TP0 (0x10000000U)
1106#define AIPS_PACRO_WP0 (0x20000000U)
1107#define AIPS_PACRO_SP0 (0x40000000U)
1108
1109/*! @name PACRP - Peripheral Access Control Register */
1110#define AIPS_PACRP_TP7 (0x1U)
1111#define AIPS_PACRP_WP7 (0x2U)
1112#define AIPS_PACRP_SP7 (0x4U)
1113#define AIPS_PACRP_TP6 (0x10U)
1114#define AIPS_PACRP_WP6 (0x20U)
1115#define AIPS_PACRP_SP6 (0x40U)
1116#define AIPS_PACRP_TP5 (0x100U)
1117#define AIPS_PACRP_WP5 (0x200U)
1118#define AIPS_PACRP_SP5 (0x400U)
1119#define AIPS_PACRP_TP4 (0x1000U)
1120#define AIPS_PACRP_WP4 (0x2000U)
1121#define AIPS_PACRP_SP4 (0x4000U)
1122#define AIPS_PACRP_TP3 (0x10000U)
1123#define AIPS_PACRP_WP3 (0x20000U)
1124#define AIPS_PACRP_SP3 (0x40000U)
1125#define AIPS_PACRP_TP2 (0x100000U)
1126#define AIPS_PACRP_WP2 (0x200000U)
1127#define AIPS_PACRP_SP2 (0x400000U)
1128#define AIPS_PACRP_TP1 (0x1000000U)
1129#define AIPS_PACRP_WP1 (0x2000000U)
1130#define AIPS_PACRP_SP1 (0x4000000U)
1131#define AIPS_PACRP_TP0 (0x10000000U)
1132#define AIPS_PACRP_WP0 (0x20000000U)
1133#define AIPS_PACRP_SP0 (0x40000000U)
1134
1135/*! @name PACRU - Peripheral Access Control Register */
1136#define AIPS_PACRU_TP1 (0x1000000U)
1137#define AIPS_PACRU_WP1 (0x2000000U)
1138#define AIPS_PACRU_SP1 (0x4000000U)
1139#define AIPS_PACRU_TP0 (0x10000000U)
1140#define AIPS_PACRU_WP0 (0x20000000U)
1141#define AIPS_PACRU_SP0 (0x40000000U)
1142
1143
1144/*!
1145 * @}
1146 */ /* end of group AIPS_Register_Masks */
1147
1148
1149/* AIPS - Peripheral instance base addresses */
1150/** Peripheral AIPS0 base address */
1151#define AIPS0_BASE (0x40000000u)
1152/** Peripheral AIPS0 base pointer */
1153#define AIPS0 ((AIPS_TypeDef *)AIPS0_BASE)
1154/** Peripheral AIPS1 base address */
1155#define AIPS1_BASE (0x40080000u)
1156/** Peripheral AIPS1 base pointer */
1157#define AIPS1 ((AIPS_TypeDef *)AIPS1_BASE)
1158/** Array initializer of AIPS peripheral base addresses */
1159#define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
1160/** Array initializer of AIPS peripheral base pointers */
1161#define AIPS_BASE_PTRS { AIPS0, AIPS1 }
1162
1163/*!
1164 * @}
1165 */ /* end of group AIPS_Peripheral_Access_Layer */
1166
1167
1168/* ----------------------------------------------------------------------------
1169 -- AXBS Peripheral Access Layer
1170 ---------------------------------------------------------------------------- */
1171
1172/*!
1173 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
1174 * @{
1175 */
1176
1177/** AXBS - Register Layout Typedef */
1178typedef struct {
1179 struct { /* offset: 0x0, array step: 0x100 */
1180 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
1181 uint8_t RESERVED_0[12];
1182 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
1183 uint8_t RESERVED_1[236];
1184 } SLAVE[5];
1185 uint8_t RESERVED_0[768];
1186 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
1187 uint8_t RESERVED_1[252];
1188 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
1189 uint8_t RESERVED_2[252];
1190 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
1191 uint8_t RESERVED_3[252];
1192 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
1193 uint8_t RESERVED_4[252];
1194 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
1195 uint8_t RESERVED_5[252];
1196 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
1197} AXBS_TypeDef;
1198
1199/* ----------------------------------------------------------------------------
1200 -- AXBS Register Masks
1201 ---------------------------------------------------------------------------- */
1202
1203/*!
1204 * @addtogroup AXBS_Register_Masks AXBS Register Masks
1205 * @{
1206 */
1207
1208/*! @name PRS - Priority Registers Slave */
1209#define AXBS_PRS_M0_MASK (0x7U)
1210#define AXBS_PRS_M0_SHIFT (0U)
1211#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
1212#define AXBS_PRS_M1_MASK (0x70U)
1213#define AXBS_PRS_M1_SHIFT (4U)
1214#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
1215#define AXBS_PRS_M2_MASK (0x700U)
1216#define AXBS_PRS_M2_SHIFT (8U)
1217#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
1218#define AXBS_PRS_M3_MASK (0x7000U)
1219#define AXBS_PRS_M3_SHIFT (12U)
1220#define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
1221#define AXBS_PRS_M4_MASK (0x70000U)
1222#define AXBS_PRS_M4_SHIFT (16U)
1223#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
1224#define AXBS_PRS_M5_MASK (0x700000U)
1225#define AXBS_PRS_M5_SHIFT (20U)
1226#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
1227
1228/* The count of AXBS_PRS */
1229#define AXBS_PRS_COUNT (5U)
1230
1231/*! @name CRS - Control Register */
1232#define AXBS_CRS_PARK_MASK (0x7U)
1233#define AXBS_CRS_PARK_SHIFT (0U)
1234#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
1235#define AXBS_CRS_PCTL_MASK (0x30U)
1236#define AXBS_CRS_PCTL_SHIFT (4U)
1237#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
1238#define AXBS_CRS_ARB_MASK (0x300U)
1239#define AXBS_CRS_ARB_SHIFT (8U)
1240#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
1241#define AXBS_CRS_HLP (0x40000000U)
1242#define AXBS_CRS_RO (0x80000000U)
1243
1244/* The count of AXBS_CRS */
1245#define AXBS_CRS_COUNT (5U)
1246
1247/*! @name MGPCR0 - Master General Purpose Control Register */
1248#define AXBS_MGPCR0_AULB_MASK (0x7U)
1249#define AXBS_MGPCR0_AULB_SHIFT (0U)
1250#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
1251
1252/*! @name MGPCR1 - Master General Purpose Control Register */
1253#define AXBS_MGPCR1_AULB_MASK (0x7U)
1254#define AXBS_MGPCR1_AULB_SHIFT (0U)
1255#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
1256
1257/*! @name MGPCR2 - Master General Purpose Control Register */
1258#define AXBS_MGPCR2_AULB_MASK (0x7U)
1259#define AXBS_MGPCR2_AULB_SHIFT (0U)
1260#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
1261
1262/*! @name MGPCR3 - Master General Purpose Control Register */
1263#define AXBS_MGPCR3_AULB_MASK (0x7U)
1264#define AXBS_MGPCR3_AULB_SHIFT (0U)
1265#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
1266
1267/*! @name MGPCR4 - Master General Purpose Control Register */
1268#define AXBS_MGPCR4_AULB_MASK (0x7U)
1269#define AXBS_MGPCR4_AULB_SHIFT (0U)
1270#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
1271
1272/*! @name MGPCR5 - Master General Purpose Control Register */
1273#define AXBS_MGPCR5_AULB_MASK (0x7U)
1274#define AXBS_MGPCR5_AULB_SHIFT (0U)
1275#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
1276
1277
1278/*!
1279 * @}
1280 */ /* end of group AXBS_Register_Masks */
1281
1282
1283/* AXBS - Peripheral instance base addresses */
1284/** Peripheral AXBS base address */
1285#define AXBS_BASE (0x40004000u)
1286/** Peripheral AXBS base pointer */
1287#define AXBS ((AXBS_TypeDef *)AXBS_BASE)
1288/** Array initializer of AXBS peripheral base addresses */
1289#define AXBS_BASE_ADDRS { AXBS_BASE }
1290/** Array initializer of AXBS peripheral base pointers */
1291#define AXBS_BASE_PTRS { AXBS }
1292
1293/*!
1294 * @}
1295 */ /* end of group AXBS_Peripheral_Access_Layer */
1296
1297
1298/* ----------------------------------------------------------------------------
1299 -- CAN Peripheral Access Layer
1300 ---------------------------------------------------------------------------- */
1301
1302/*!
1303 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
1304 * @{
1305 */
1306
1307/** CAN - Register Layout Typedef */
1308typedef struct {
1309 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
1310 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
1311 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
1312 uint8_t RESERVED_0[4];
1313 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
1314 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
1315 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
1316 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
1317 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
1318 uint8_t RESERVED_1[4];
1319 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
1320 uint8_t RESERVED_2[4];
1321 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
1322 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
1323 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
1324 uint8_t RESERVED_3[8];
1325 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
1326 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
1327 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
1328 uint8_t RESERVED_4[48];
1329 struct { /* offset: 0x80, array step: 0x10 */
1330 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
1331 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
1332 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
1333 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
1334 } MB[16];
1335 uint8_t RESERVED_5[1792];
1336 __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
1337} CAN_TypeDef;
1338
1339/* ----------------------------------------------------------------------------
1340 -- CAN Register Masks
1341 ---------------------------------------------------------------------------- */
1342
1343/*!
1344 * @addtogroup CAN_Register_Masks CAN Register Masks
1345 * @{
1346 */
1347
1348/*! @name MCR - Module Configuration Register */
1349#define CAN_MCR_MAXMB_MASK (0x7FU)
1350#define CAN_MCR_MAXMB_SHIFT (0U)
1351#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
1352#define CAN_MCR_IDAM_MASK (0x300U)
1353#define CAN_MCR_IDAM_SHIFT (8U)
1354#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
1355#define CAN_MCR_AEN (0x1000U)
1356#define CAN_MCR_LPRIOEN (0x2000U)
1357#define CAN_MCR_IRMQ (0x10000U)
1358#define CAN_MCR_SRXDIS (0x20000U)
1359#define CAN_MCR_WAKSRC (0x80000U)
1360#define CAN_MCR_LPMACK (0x100000U)
1361#define CAN_MCR_WRNEN (0x200000U)
1362#define CAN_MCR_SLFWAK (0x400000U)
1363#define CAN_MCR_SUPV (0x800000U)
1364#define CAN_MCR_FRZACK (0x1000000U)
1365#define CAN_MCR_SOFTRST (0x2000000U)
1366#define CAN_MCR_WAKMSK (0x4000000U)
1367#define CAN_MCR_NOTRDY (0x8000000U)
1368#define CAN_MCR_HALT (0x10000000U)
1369#define CAN_MCR_RFEN (0x20000000U)
1370#define CAN_MCR_FRZ (0x40000000U)
1371#define CAN_MCR_MDIS (0x80000000U)
1372
1373/*! @name CTRL1 - Control 1 register */
1374#define CAN_CTRL1_PROPSEG_MASK (0x7U)
1375#define CAN_CTRL1_PROPSEG_SHIFT (0U)
1376#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
1377#define CAN_CTRL1_LOM (0x8U)
1378#define CAN_CTRL1_LBUF (0x10U)
1379#define CAN_CTRL1_TSYN (0x20U)
1380#define CAN_CTRL1_BOFFREC (0x40U)
1381#define CAN_CTRL1_SMP (0x80U)
1382#define CAN_CTRL1_RWRNMSK (0x400U)
1383#define CAN_CTRL1_TWRNMSK (0x800U)
1384#define CAN_CTRL1_LPB (0x1000U)
1385#define CAN_CTRL1_CLKSRC (0x2000U)
1386#define CAN_CTRL1_ERRMSK (0x4000U)
1387#define CAN_CTRL1_BOFFMSK (0x8000U)
1388#define CAN_CTRL1_PSEG2_MASK (0x70000U)
1389#define CAN_CTRL1_PSEG2_SHIFT (16U)
1390#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
1391#define CAN_CTRL1_PSEG1_MASK (0x380000U)
1392#define CAN_CTRL1_PSEG1_SHIFT (19U)
1393#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
1394#define CAN_CTRL1_RJW_MASK (0xC00000U)
1395#define CAN_CTRL1_RJW_SHIFT (22U)
1396#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
1397#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
1398#define CAN_CTRL1_PRESDIV_SHIFT (24U)
1399#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
1400
1401/*! @name TIMER - Free Running Timer */
1402#define CAN_TIMER_TIMER_MASK (0xFFFFU)
1403#define CAN_TIMER_TIMER_SHIFT (0U)
1404#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
1405
1406/*! @name ECR - Error Counter */
1407#define CAN_ECR_TXERRCNT_MASK (0xFFU)
1408#define CAN_ECR_TXERRCNT_SHIFT (0U)
1409#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
1410#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
1411#define CAN_ECR_RXERRCNT_SHIFT (8U)
1412#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
1413
1414/*! @name ESR1 - Error and Status 1 register */
1415#define CAN_ESR1_WAKINT (0x1U)
1416#define CAN_ESR1_ERRINT (0x2U)
1417#define CAN_ESR1_BOFFINT (0x4U)
1418#define CAN_ESR1_RX (0x8U)
1419#define CAN_ESR1_FLTCONF_MASK (0x30U)
1420#define CAN_ESR1_FLTCONF_SHIFT (4U)
1421#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
1422#define CAN_ESR1_TX (0x40U)
1423#define CAN_ESR1_IDLE (0x80U)
1424#define CAN_ESR1_RXWRN (0x100U)
1425#define CAN_ESR1_TXWRN (0x200U)
1426#define CAN_ESR1_STFERR (0x400U)
1427#define CAN_ESR1_FRMERR (0x800U)
1428#define CAN_ESR1_CRCERR (0x1000U)
1429#define CAN_ESR1_ACKERR (0x2000U)
1430#define CAN_ESR1_BIT0ERR (0x4000U)
1431#define CAN_ESR1_BIT1ERR (0x8000U)
1432#define CAN_ESR1_RWRNINT (0x10000U)
1433#define CAN_ESR1_TWRNINT (0x20000U)
1434#define CAN_ESR1_SYNCH (0x40000U)
1435
1436/*! @name IFLAG1 - Interrupt Flags 1 register */
1437#define CAN_IFLAG1_BUF0I (0x1U)
1438#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
1439#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
1440#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
1441#define CAN_IFLAG1_BUF5I (0x20U)
1442#define CAN_IFLAG1_BUF6I (0x40U)
1443#define CAN_IFLAG1_BUF7I (0x80U)
1444#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
1445#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
1446#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
1447
1448/*! @name CTRL2 - Control 2 register */
1449#define CAN_CTRL2_EACEN (0x10000U)
1450#define CAN_CTRL2_RRS (0x20000U)
1451#define CAN_CTRL2_MRP (0x40000U)
1452#define CAN_CTRL2_TASD_MASK (0xF80000U)
1453#define CAN_CTRL2_TASD_SHIFT (19U)
1454#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
1455#define CAN_CTRL2_RFFN_MASK (0xF000000U)
1456#define CAN_CTRL2_RFFN_SHIFT (24U)
1457#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
1458#define CAN_CTRL2_WRMFRZ (0x10000000U)
1459
1460/*! @name ESR2 - Error and Status 2 register */
1461#define CAN_ESR2_IMB (0x2000U)
1462#define CAN_ESR2_VPS (0x4000U)
1463#define CAN_ESR2_LPTM_MASK (0x7F0000U)
1464#define CAN_ESR2_LPTM_SHIFT (16U)
1465#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
1466
1467/*! @name CRCR - CRC Register */
1468#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
1469#define CAN_CRCR_TXCRC_SHIFT (0U)
1470#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
1471#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
1472#define CAN_CRCR_MBCRC_SHIFT (16U)
1473#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
1474
1475/*! @name RXFIR - Rx FIFO Information Register */
1476#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
1477#define CAN_RXFIR_IDHIT_SHIFT (0U)
1478#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
1479
1480/*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */
1481#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
1482#define CAN_CS_TIME_STAMP_SHIFT (0U)
1483#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
1484#define CAN_CS_DLC_MASK (0xF0000U)
1485#define CAN_CS_DLC_SHIFT (16U)
1486#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
1487#define CAN_CS_RTR (0x100000U)
1488#define CAN_CS_IDE (0x200000U)
1489#define CAN_CS_SRR (0x400000U)
1490#define CAN_CS_CODE_MASK (0xF000000U)
1491#define CAN_CS_CODE_SHIFT (24U)
1492#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
1493
1494/* The count of CAN_CS */
1495#define CAN_CS_COUNT (16U)
1496
1497/*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */
1498#define CAN_ID_EXT_MASK (0x3FFFFU)
1499#define CAN_ID_EXT_SHIFT (0U)
1500#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
1501#define CAN_ID_STD_MASK (0x1FFC0000U)
1502#define CAN_ID_STD_SHIFT (18U)
1503#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
1504#define CAN_ID_PRIO_MASK (0xE0000000U)
1505#define CAN_ID_PRIO_SHIFT (29U)
1506#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
1507
1508/* The count of CAN_ID */
1509#define CAN_ID_COUNT (16U)
1510
1511/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */
1512#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
1513#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
1514#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
1515#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
1516#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
1517#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
1518#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
1519#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
1520#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
1521#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
1522#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
1523#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
1524
1525/* The count of CAN_WORD0 */
1526#define CAN_WORD0_COUNT (16U)
1527
1528/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */
1529#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
1530#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
1531#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
1532#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
1533#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
1534#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
1535#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
1536#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
1537#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
1538#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
1539#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
1540#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
1541
1542/* The count of CAN_WORD1 */
1543#define CAN_WORD1_COUNT (16U)
1544
1545/* The count of CAN_RXIMR */
1546#define CAN_RXIMR_COUNT (16U)
1547
1548/*!
1549 * @}
1550 */ /* end of group CAN_Register_Masks */
1551
1552
1553/* CAN - Peripheral instance base addresses */
1554/** Peripheral CAN0 base address */
1555#define CAN0_BASE (0x40024000u)
1556/** Peripheral CAN0 base pointer */
1557#define CAN0 ((CAN_TypeDef *)CAN0_BASE)
1558/** Array initializer of CAN peripheral base addresses */
1559#define CAN_BASE_ADDRS { CAN0_BASE }
1560/** Array initializer of CAN peripheral base pointers */
1561#define CAN_BASE_PTRS { CAN0 }
1562/** Interrupt vectors for the CAN peripheral type */
1563#define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn }
1564#define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn }
1565#define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn }
1566#define CAN_Error_IRQS { CAN0_Error_IRQn }
1567#define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn }
1568#define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn }
1569
1570/*!
1571 * @}
1572 */ /* end of group CAN_Peripheral_Access_Layer */
1573
1574
1575/* ----------------------------------------------------------------------------
1576 -- CAU Peripheral Access Layer
1577 ---------------------------------------------------------------------------- */
1578
1579/*!
1580 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
1581 * @{
1582 */
1583
1584/** CAU - Register Layout Typedef */
1585typedef struct {
1586 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
1587 uint8_t RESERVED_0[2048];
1588 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
1589 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
1590 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
1591 uint8_t RESERVED_1[20];
1592 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
1593 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
1594 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
1595 uint8_t RESERVED_2[20];
1596 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
1597 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
1598 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
1599 uint8_t RESERVED_3[20];
1600 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
1601 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
1602 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
1603 uint8_t RESERVED_4[84];
1604 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
1605 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
1606 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
1607 uint8_t RESERVED_5[20];
1608 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
1609 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
1610 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
1611 uint8_t RESERVED_6[276];
1612 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
1613 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
1614 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
1615 uint8_t RESERVED_7[20];
1616 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
1617 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
1618 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
1619} CAU_TypeDef;
1620
1621/* ----------------------------------------------------------------------------
1622 -- CAU Register Masks
1623 ---------------------------------------------------------------------------- */
1624
1625/*!
1626 * @addtogroup CAU_Register_Masks CAU Register Masks
1627 * @{
1628 */
1629
1630/* The count of CAU_DIRECT */
1631#define CAU_DIRECT_COUNT (16U)
1632
1633/*! @name LDR_CASR - Status register - Load Register command */
1634#define CAU_LDR_CASR_IC (0x1U)
1635#define CAU_LDR_CASR_DPE (0x2U)
1636#define CAU_LDR_CASR_VER_MASK (0xF0000000U)
1637#define CAU_LDR_CASR_VER_SHIFT (28U)
1638#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
1639
1640/* The count of CAU_LDR_CA */
1641#define CAU_LDR_CA_COUNT (9U)
1642
1643/*! @name STR_CASR - Status register - Store Register command */
1644#define CAU_STR_CASR_IC (0x1U)
1645#define CAU_STR_CASR_DPE (0x2U)
1646#define CAU_STR_CASR_VER_MASK (0xF0000000U)
1647#define CAU_STR_CASR_VER_SHIFT (28U)
1648#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
1649
1650/* The count of CAU_STR_CA */
1651#define CAU_STR_CA_COUNT (9U)
1652
1653/*! @name ADR_CASR - Status register - Add Register command */
1654#define CAU_ADR_CASR_IC (0x1U)
1655#define CAU_ADR_CASR_DPE (0x2U)
1656#define CAU_ADR_CASR_VER_MASK (0xF0000000U)
1657#define CAU_ADR_CASR_VER_SHIFT (28U)
1658#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
1659
1660/* The count of CAU_ADR_CA */
1661#define CAU_ADR_CA_COUNT (9U)
1662
1663/*! @name RADR_CASR - Status register - Reverse and Add to Register command */
1664#define CAU_RADR_CASR_IC (0x1U)
1665#define CAU_RADR_CASR_DPE (0x2U)
1666#define CAU_RADR_CASR_VER_MASK (0xF0000000U)
1667#define CAU_RADR_CASR_VER_SHIFT (28U)
1668#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
1669
1670/* The count of CAU_RADR_CA */
1671#define CAU_RADR_CA_COUNT (9U)
1672
1673/*! @name XOR_CASR - Status register - Exclusive Or command */
1674#define CAU_XOR_CASR_IC (0x1U)
1675#define CAU_XOR_CASR_DPE (0x2U)
1676#define CAU_XOR_CASR_VER_MASK (0xF0000000U)
1677#define CAU_XOR_CASR_VER_SHIFT (28U)
1678#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
1679
1680/* The count of CAU_XOR_CA */
1681#define CAU_XOR_CA_COUNT (9U)
1682
1683/*! @name ROTL_CASR - Status register - Rotate Left command */
1684#define CAU_ROTL_CASR_IC (0x1U)
1685#define CAU_ROTL_CASR_DPE (0x2U)
1686#define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
1687#define CAU_ROTL_CASR_VER_SHIFT (28U)
1688#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
1689
1690/* The count of CAU_ROTL_CA */
1691#define CAU_ROTL_CA_COUNT (9U)
1692
1693/*! @name AESC_CASR - Status register - AES Column Operation command */
1694#define CAU_AESC_CASR_IC (0x1U)
1695#define CAU_AESC_CASR_DPE (0x2U)
1696#define CAU_AESC_CASR_VER_MASK (0xF0000000U)
1697#define CAU_AESC_CASR_VER_SHIFT (28U)
1698#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
1699
1700/* The count of CAU_AESC_CA */
1701#define CAU_AESC_CA_COUNT (9U)
1702
1703/*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
1704#define CAU_AESIC_CASR_IC (0x1U)
1705#define CAU_AESIC_CASR_DPE (0x2U)
1706#define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
1707#define CAU_AESIC_CASR_VER_SHIFT (28U)
1708#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
1709
1710/* The count of CAU_AESIC_CA */
1711#define CAU_AESIC_CA_COUNT (9U)
1712
1713
1714/*!
1715 * @}
1716 */ /* end of group CAU_Register_Masks */
1717
1718
1719/* CAU - Peripheral instance base addresses */
1720/** Peripheral CAU base address */
1721#define CAU_BASE (0xE0081000u)
1722/** Peripheral CAU base pointer */
1723#define CAU ((CAU_TypeDef *)CAU_BASE)
1724/** Array initializer of CAU peripheral base addresses */
1725#define CAU_BASE_ADDRS { CAU_BASE }
1726/** Array initializer of CAU peripheral base pointers */
1727#define CAU_BASE_PTRS { CAU }
1728
1729/*!
1730 * @}
1731 */ /* end of group CAU_Peripheral_Access_Layer */
1732
1733
1734/* ----------------------------------------------------------------------------
1735 -- CMP Peripheral Access Layer
1736 ---------------------------------------------------------------------------- */
1737
1738/*!
1739 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
1740 * @{
1741 */
1742
1743/** CMP - Register Layout Typedef */
1744typedef struct {
1745 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
1746 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
1747 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
1748 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
1749 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
1750 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
1751} CMP_TypeDef;
1752
1753/* ----------------------------------------------------------------------------
1754 -- CMP Register Masks
1755 ---------------------------------------------------------------------------- */
1756
1757/*!
1758 * @addtogroup CMP_Register_Masks CMP Register Masks
1759 * @{
1760 */
1761
1762/*! @name CR0 - CMP Control Register 0 */
1763#define CMP_CR0_HYSTCTR_MASK (0x3U)
1764#define CMP_CR0_HYSTCTR_SHIFT (0U)
1765#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
1766#define CMP_CR0_FILTER_CNT_MASK (0x70U)
1767#define CMP_CR0_FILTER_CNT_SHIFT (4U)
1768#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
1769
1770/*! @name CR1 - CMP Control Register 1 */
1771#define CMP_CR1_EN (0x1U)
1772#define CMP_CR1_OPE (0x2U)
1773#define CMP_CR1_COS (0x4U)
1774#define CMP_CR1_INV (0x8U)
1775#define CMP_CR1_PMODE (0x10U)
1776#define CMP_CR1_WE (0x40U)
1777#define CMP_CR1_SE (0x80U)
1778
1779/*! @name FPR - CMP Filter Period Register */
1780#define CMP_FPR_FILT_PER_MASK (0xFFU)
1781#define CMP_FPR_FILT_PER_SHIFT (0U)
1782#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
1783
1784/*! @name SCR - CMP Status and Control Register */
1785#define CMP_SCR_COUT (0x1U)
1786#define CMP_SCR_CFF (0x2U)
1787#define CMP_SCR_CFR (0x4U)
1788#define CMP_SCR_IEF (0x8U)
1789#define CMP_SCR_IER (0x10U)
1790#define CMP_SCR_DMAEN (0x40U)
1791
1792/*! @name DACCR - DAC Control Register */
1793#define CMP_DACCR_VOSEL_MASK (0x3FU)
1794#define CMP_DACCR_VOSEL_SHIFT (0U)
1795#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
1796#define CMP_DACCR_VRSEL (0x40U)
1797#define CMP_DACCR_DACEN (0x80U)
1798
1799/*! @name MUXCR - MUX Control Register */
1800#define CMP_MUXCR_MSEL_MASK (0x7U)
1801#define CMP_MUXCR_MSEL_SHIFT (0U)
1802#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
1803#define CMP_MUXCR_PSEL_MASK (0x38U)
1804#define CMP_MUXCR_PSEL_SHIFT (3U)
1805#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
1806#define CMP_MUXCR_PSTM (0x80U)
1807
1808
1809/*!
1810 * @}
1811 */ /* end of group CMP_Register_Masks */
1812
1813
1814/* CMP - Peripheral instance base addresses */
1815/** Peripheral CMP0 base address */
1816#define CMP0_BASE (0x40073000u)
1817/** Peripheral CMP0 base pointer */
1818#define CMP0 ((CMP_TypeDef *)CMP0_BASE)
1819/** Peripheral CMP1 base address */
1820#define CMP1_BASE (0x40073008u)
1821/** Peripheral CMP1 base pointer */
1822#define CMP1 ((CMP_TypeDef *)CMP1_BASE)
1823/** Peripheral CMP2 base address */
1824#define CMP2_BASE (0x40073010u)
1825/** Peripheral CMP2 base pointer */
1826#define CMP2 ((CMP_TypeDef *)CMP2_BASE)
1827/** Array initializer of CMP peripheral base addresses */
1828#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
1829/** Array initializer of CMP peripheral base pointers */
1830#define CMP_BASE_PTRS { CMP0, CMP1, CMP2 }
1831/** Interrupt vectors for the CMP peripheral type */
1832#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
1833
1834/*!
1835 * @}
1836 */ /* end of group CMP_Peripheral_Access_Layer */
1837
1838
1839/* ----------------------------------------------------------------------------
1840 -- CMT Peripheral Access Layer
1841 ---------------------------------------------------------------------------- */
1842
1843/*!
1844 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
1845 * @{
1846 */
1847
1848/** CMT - Register Layout Typedef */
1849typedef struct {
1850 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
1851 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
1852 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
1853 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
1854 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
1855 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
1856 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
1857 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
1858 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
1859 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
1860 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
1861 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
1862} CMT_TypeDef;
1863
1864/* ----------------------------------------------------------------------------
1865 -- CMT Register Masks
1866 ---------------------------------------------------------------------------- */
1867
1868/*!
1869 * @addtogroup CMT_Register_Masks CMT Register Masks
1870 * @{
1871 */
1872
1873/*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
1874#define CMT_CGH1_PH_MASK (0xFFU)
1875#define CMT_CGH1_PH_SHIFT (0U)
1876#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
1877
1878/*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
1879#define CMT_CGL1_PL_MASK (0xFFU)
1880#define CMT_CGL1_PL_SHIFT (0U)
1881#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
1882
1883/*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
1884#define CMT_CGH2_SH_MASK (0xFFU)
1885#define CMT_CGH2_SH_SHIFT (0U)
1886#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
1887
1888/*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
1889#define CMT_CGL2_SL_MASK (0xFFU)
1890#define CMT_CGL2_SL_SHIFT (0U)
1891#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
1892
1893/*! @name OC - CMT Output Control Register */
1894#define CMT_OC_IROPEN (0x20U)
1895#define CMT_OC_CMTPOL (0x40U)
1896#define CMT_OC_IROL (0x80U)
1897
1898/*! @name MSC - CMT Modulator Status and Control Register */
1899#define CMT_MSC_MCGEN (0x1U)
1900#define CMT_MSC_EOCIE (0x2U)
1901#define CMT_MSC_FSK (0x4U)
1902#define CMT_MSC_BASE (0x8U)
1903#define CMT_MSC_EXSPC (0x10U)
1904#define CMT_MSC_CMTDIV_MASK (0x60U)
1905#define CMT_MSC_CMTDIV_SHIFT (5U)
1906#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
1907#define CMT_MSC_EOCF (0x80U)
1908
1909/*! @name CMD1 - CMT Modulator Data Register Mark High */
1910#define CMT_CMD1_MB_MASK (0xFFU)
1911#define CMT_CMD1_MB_SHIFT (0U)
1912#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
1913
1914/*! @name CMD2 - CMT Modulator Data Register Mark Low */
1915#define CMT_CMD2_MB_MASK (0xFFU)
1916#define CMT_CMD2_MB_SHIFT (0U)
1917#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
1918
1919/*! @name CMD3 - CMT Modulator Data Register Space High */
1920#define CMT_CMD3_SB_MASK (0xFFU)
1921#define CMT_CMD3_SB_SHIFT (0U)
1922#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
1923
1924/*! @name CMD4 - CMT Modulator Data Register Space Low */
1925#define CMT_CMD4_SB_MASK (0xFFU)
1926#define CMT_CMD4_SB_SHIFT (0U)
1927#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
1928
1929/*! @name PPS - CMT Primary Prescaler Register */
1930#define CMT_PPS_PPSDIV_MASK (0xFU)
1931#define CMT_PPS_PPSDIV_SHIFT (0U)
1932#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
1933
1934/*! @name DMA - CMT Direct Memory Access Register */
1935#define CMT_DMA_DMA (0x1U)
1936
1937
1938/*!
1939 * @}
1940 */ /* end of group CMT_Register_Masks */
1941
1942
1943/* CMT - Peripheral instance base addresses */
1944/** Peripheral CMT base address */
1945#define CMT_BASE (0x40062000u)
1946/** Peripheral CMT base pointer */
1947#define CMT ((CMT_TypeDef *)CMT_BASE)
1948/** Array initializer of CMT peripheral base addresses */
1949#define CMT_BASE_ADDRS { CMT_BASE }
1950/** Array initializer of CMT peripheral base pointers */
1951#define CMT_BASE_PTRS { CMT }
1952/** Interrupt vectors for the CMT peripheral type */
1953#define CMT_IRQS { CMT_IRQn }
1954
1955/*!
1956 * @}
1957 */ /* end of group CMT_Peripheral_Access_Layer */
1958
1959
1960/* ----------------------------------------------------------------------------
1961 -- CRC Peripheral Access Layer
1962 ---------------------------------------------------------------------------- */
1963
1964/*!
1965 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
1966 * @{
1967 */
1968
1969/** CRC - Register Layout Typedef */
1970typedef struct {
1971 union { /* offset: 0x0 */
1972 struct { /* offset: 0x0 */
1973 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
1974 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
1975 } ACCESS16BIT;
1976 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
1977 struct { /* offset: 0x0 */
1978 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
1979 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
1980 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
1981 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
1982 } ACCESS8BIT;
1983 };
1984 union { /* offset: 0x4 */
1985 struct { /* offset: 0x4 */
1986 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
1987 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
1988 } GPOLY_ACCESS16BIT;
1989 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
1990 struct { /* offset: 0x4 */
1991 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
1992 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
1993 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
1994 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
1995 } GPOLY_ACCESS8BIT;
1996 };
1997 union { /* offset: 0x8 */
1998 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
1999 struct { /* offset: 0x8 */
2000 uint8_t RESERVED_0[3];
2001 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
2002 } CTRL_ACCESS8BIT;
2003 };
2004} CRC_TypeDef;
2005
2006/* ----------------------------------------------------------------------------
2007 -- CRC Register Masks
2008 ---------------------------------------------------------------------------- */
2009
2010/*!
2011 * @addtogroup CRC_Register_Masks CRC Register Masks
2012 * @{
2013 */
2014
2015/*! @name DATAL - CRC_DATAL register. */
2016#define CRC_DATAL_DATAL_MASK (0xFFFFU)
2017#define CRC_DATAL_DATAL_SHIFT (0U)
2018#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
2019
2020/*! @name DATAH - CRC_DATAH register. */
2021#define CRC_DATAH_DATAH_MASK (0xFFFFU)
2022#define CRC_DATAH_DATAH_SHIFT (0U)
2023#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
2024
2025/*! @name DATA - CRC Data register */
2026#define CRC_DATA_LL_MASK (0xFFU)
2027#define CRC_DATA_LL_SHIFT (0U)
2028#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
2029#define CRC_DATA_LU_MASK (0xFF00U)
2030#define CRC_DATA_LU_SHIFT (8U)
2031#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
2032#define CRC_DATA_HL_MASK (0xFF0000U)
2033#define CRC_DATA_HL_SHIFT (16U)
2034#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
2035#define CRC_DATA_HU_MASK (0xFF000000U)
2036#define CRC_DATA_HU_SHIFT (24U)
2037#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
2038
2039/*! @name DATALL - CRC_DATALL register. */
2040#define CRC_DATALL_DATALL_MASK (0xFFU)
2041#define CRC_DATALL_DATALL_SHIFT (0U)
2042#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
2043
2044/*! @name DATALU - CRC_DATALU register. */
2045#define CRC_DATALU_DATALU_MASK (0xFFU)
2046#define CRC_DATALU_DATALU_SHIFT (0U)
2047#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
2048
2049/*! @name DATAHL - CRC_DATAHL register. */
2050#define CRC_DATAHL_DATAHL_MASK (0xFFU)
2051#define CRC_DATAHL_DATAHL_SHIFT (0U)
2052#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
2053
2054/*! @name DATAHU - CRC_DATAHU register. */
2055#define CRC_DATAHU_DATAHU_MASK (0xFFU)
2056#define CRC_DATAHU_DATAHU_SHIFT (0U)
2057#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
2058
2059/*! @name GPOLYL - CRC_GPOLYL register. */
2060#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
2061#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
2062#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
2063
2064/*! @name GPOLYH - CRC_GPOLYH register. */
2065#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
2066#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
2067#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
2068
2069/*! @name GPOLY - CRC Polynomial register */
2070#define CRC_GPOLY_LOW_MASK (0xFFFFU)
2071#define CRC_GPOLY_LOW_SHIFT (0U)
2072#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
2073#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
2074#define CRC_GPOLY_HIGH_SHIFT (16U)
2075#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
2076
2077/*! @name GPOLYLL - CRC_GPOLYLL register. */
2078#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
2079#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
2080#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
2081
2082/*! @name GPOLYLU - CRC_GPOLYLU register. */
2083#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
2084#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
2085#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
2086
2087/*! @name GPOLYHL - CRC_GPOLYHL register. */
2088#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
2089#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
2090#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
2091
2092/*! @name GPOLYHU - CRC_GPOLYHU register. */
2093#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
2094#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
2095#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
2096
2097/*! @name CTRL - CRC Control register */
2098#define CRC_CTRL_TCRC (0x1000000U)
2099#define CRC_CTRL_WAS (0x2000000U)
2100#define CRC_CTRL_FXOR (0x4000000U)
2101#define CRC_CTRL_TOTR_MASK (0x30000000U)
2102#define CRC_CTRL_TOTR_SHIFT (28U)
2103#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
2104#define CRC_CTRL_TOT_MASK (0xC0000000U)
2105#define CRC_CTRL_TOT_SHIFT (30U)
2106#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
2107
2108/*! @name CTRLHU - CRC_CTRLHU register. */
2109#define CRC_CTRLHU_TCRC (0x1U)
2110#define CRC_CTRLHU_WAS (0x2U)
2111#define CRC_CTRLHU_FXOR (0x4U)
2112#define CRC_CTRLHU_TOTR_MASK (0x30U)
2113#define CRC_CTRLHU_TOTR_SHIFT (4U)
2114#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
2115#define CRC_CTRLHU_TOT_MASK (0xC0U)
2116#define CRC_CTRLHU_TOT_SHIFT (6U)
2117#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
2118
2119
2120/*!
2121 * @}
2122 */ /* end of group CRC_Register_Masks */
2123
2124
2125/* CRC - Peripheral instance base addresses */
2126/** Peripheral CRC base address */
2127#define CRC_BASE (0x40032000u)
2128/** Peripheral CRC base pointer */
2129#define CRC0 ((CRC_TypeDef *)CRC_BASE)
2130/** Array initializer of CRC peripheral base addresses */
2131#define CRC_BASE_ADDRS { CRC_BASE }
2132/** Array initializer of CRC peripheral base pointers */
2133#define CRC_BASE_PTRS { CRC0 }
2134
2135/*!
2136 * @}
2137 */ /* end of group CRC_Peripheral_Access_Layer */
2138
2139
2140/* ----------------------------------------------------------------------------
2141 -- DAC Peripheral Access Layer
2142 ---------------------------------------------------------------------------- */
2143
2144/*!
2145 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
2146 * @{
2147 */
2148
2149/** DAC - Register Layout Typedef */
2150typedef struct {
2151 struct { /* offset: 0x0, array step: 0x2 */
2152 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
2153 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
2154 } DAT[16];
2155 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
2156 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
2157 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
2158 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
2159} DAC_TypeDef;
2160
2161/* ----------------------------------------------------------------------------
2162 -- DAC Register Masks
2163 ---------------------------------------------------------------------------- */
2164
2165/*!
2166 * @addtogroup DAC_Register_Masks DAC Register Masks
2167 * @{
2168 */
2169
2170/*! @name DATL - DAC Data Low Register */
2171#define DAC_DATL_DATA0_MASK (0xFFU)
2172#define DAC_DATL_DATA0_SHIFT (0U)
2173#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
2174
2175/* The count of DAC_DATL */
2176#define DAC_DATL_COUNT (16U)
2177
2178/*! @name DATH - DAC Data High Register */
2179#define DAC_DATH_DATA1_MASK (0xFU)
2180#define DAC_DATH_DATA1_SHIFT (0U)
2181#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
2182
2183/* The count of DAC_DATH */
2184#define DAC_DATH_COUNT (16U)
2185
2186/*! @name SR - DAC Status Register */
2187#define DAC_SR_DACBFRPBF (0x1U)
2188#define DAC_SR_DACBFRPTF (0x2U)
2189#define DAC_SR_DACBFWMF (0x4U)
2190
2191/*! @name C0 - DAC Control Register */
2192#define DAC_C0_DACBBIEN (0x1U)
2193#define DAC_C0_DACBTIEN (0x2U)
2194#define DAC_C0_DACBWIEN (0x4U)
2195#define DAC_C0_LPEN (0x8U)
2196#define DAC_C0_DACSWTRG (0x10U)
2197#define DAC_C0_DACTRGSEL (0x20U)
2198#define DAC_C0_DACRFS (0x40U)
2199#define DAC_C0_DACEN (0x80U)
2200
2201/*! @name C1 - DAC Control Register 1 */
2202#define DAC_C1_DACBFEN (0x1U)
2203#define DAC_C1_DACBFMD_MASK (0x6U)
2204#define DAC_C1_DACBFMD_SHIFT (1U)
2205#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
2206#define DAC_C1_DACBFWM_MASK (0x18U)
2207#define DAC_C1_DACBFWM_SHIFT (3U)
2208#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
2209#define DAC_C1_DMAEN (0x80U)
2210
2211/*! @name C2 - DAC Control Register 2 */
2212#define DAC_C2_DACBFUP_MASK (0xFU)
2213#define DAC_C2_DACBFUP_SHIFT (0U)
2214#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
2215#define DAC_C2_DACBFRP_MASK (0xF0U)
2216#define DAC_C2_DACBFRP_SHIFT (4U)
2217#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
2218
2219
2220/*!
2221 * @}
2222 */ /* end of group DAC_Register_Masks */
2223
2224
2225/* DAC - Peripheral instance base addresses */
2226/** Peripheral DAC0 base address */
2227#define DAC0_BASE (0x400CC000u)
2228/** Peripheral DAC0 base pointer */
2229#define DAC0 ((DAC_TypeDef *)DAC0_BASE)
2230/** Peripheral DAC1 base address */
2231#define DAC1_BASE (0x400CD000u)
2232/** Peripheral DAC1 base pointer */
2233#define DAC1 ((DAC_TypeDef *)DAC1_BASE)
2234/** Array initializer of DAC peripheral base addresses */
2235#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
2236/** Array initializer of DAC peripheral base pointers */
2237#define DAC_BASE_PTRS { DAC0, DAC1 }
2238/** Interrupt vectors for the DAC peripheral type */
2239#define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
2240
2241/*!
2242 * @}
2243 */ /* end of group DAC_Peripheral_Access_Layer */
2244
2245
2246/* ----------------------------------------------------------------------------
2247 -- DMA Peripheral Access Layer
2248 ---------------------------------------------------------------------------- */
2249
2250/*!
2251 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
2252 * @{
2253 */
2254
2255/** DMA - Register Layout Typedef */
2256typedef struct {
2257 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
2258 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
2259 uint8_t RESERVED_0[4];
2260 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
2261 uint8_t RESERVED_1[4];
2262 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
2263 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
2264 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
2265 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
2266 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
2267 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
2268 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
2269 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
2270 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
2271 uint8_t RESERVED_2[4];
2272 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
2273 uint8_t RESERVED_3[4];
2274 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
2275 uint8_t RESERVED_4[4];
2276 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
2277 uint8_t RESERVED_5[200];
2278 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
2279 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
2280 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
2281 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
2282 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
2283 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
2284 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
2285 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
2286 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
2287 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
2288 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
2289 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
2290 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
2291 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
2292 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
2293 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
2294 uint8_t RESERVED_6[3824];
2295 struct { /* offset: 0x1000, array step: 0x20 */
2296 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
2297 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
2298 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
2299 union { /* offset: 0x1008, array step: 0x20 */
2300 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
2301 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
2302 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
2303 };
2304 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
2305 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
2306 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
2307 union { /* offset: 0x1016, array step: 0x20 */
2308 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
2309 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
2310 };
2311 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
2312 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
2313 union { /* offset: 0x101E, array step: 0x20 */
2314 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
2315 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
2316 };
2317 } TCD[16];
2318} DMA_TypeDef;
2319
2320/* ----------------------------------------------------------------------------
2321 -- DMA Register Masks
2322 ---------------------------------------------------------------------------- */
2323
2324/*!
2325 * @addtogroup DMA_Register_Masks DMA Register Masks
2326 * @{
2327 */
2328
2329/*! @name CR - Control Register */
2330#define DMA_CR_EDBG (0x2U)
2331#define DMA_CR_ERCA (0x4U)
2332#define DMA_CR_HOE (0x10U)
2333#define DMA_CR_HALT (0x20U)
2334#define DMA_CR_CLM (0x40U)
2335#define DMA_CR_EMLM (0x80U)
2336#define DMA_CR_ECX (0x10000U)
2337#define DMA_CR_CX (0x20000U)
2338
2339/*! @name ES - Error Status Register */
2340#define DMA_ES_DBE (0x1U)
2341#define DMA_ES_SBE (0x2U)
2342#define DMA_ES_SGE (0x4U)
2343#define DMA_ES_NCE (0x8U)
2344#define DMA_ES_DOE (0x10U)
2345#define DMA_ES_DAE (0x20U)
2346#define DMA_ES_SOE (0x40U)
2347#define DMA_ES_SAE (0x80U)
2348#define DMA_ES_ERRCHN_MASK (0xF00U)
2349#define DMA_ES_ERRCHN_SHIFT (8U)
2350#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
2351#define DMA_ES_CPE (0x4000U)
2352#define DMA_ES_ECX (0x10000U)
2353#define DMA_ES_VLD (0x80000000U)
2354
2355/*! @name CEEI - Clear Enable Error Interrupt Register */
2356#define DMA_CEEI_CEEI_MASK (0xFU)
2357#define DMA_CEEI_CEEI_SHIFT (0U)
2358#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
2359#define DMA_CEEI_CAEE (0x40U)
2360#define DMA_CEEI_NOP (0x80U)
2361
2362/*! @name SEEI - Set Enable Error Interrupt Register */
2363#define DMA_SEEI_SEEI_MASK (0xFU)
2364#define DMA_SEEI_SEEI_SHIFT (0U)
2365#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
2366#define DMA_SEEI_SAEE (0x40U)
2367#define DMA_SEEI_NOP (0x80U)
2368
2369/*! @name CERQ - Clear Enable Request Register */
2370#define DMA_CERQ_CERQ_MASK (0xFU)
2371#define DMA_CERQ_CERQ_SHIFT (0U)
2372#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
2373#define DMA_CERQ_CAER (0x40U)
2374#define DMA_CERQ_NOP (0x80U)
2375
2376/*! @name SERQ - Set Enable Request Register */
2377#define DMA_SERQ_SERQ_MASK (0xFU)
2378#define DMA_SERQ_SERQ_SHIFT (0U)
2379#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
2380#define DMA_SERQ_SAER (0x40U)
2381#define DMA_SERQ_NOP (0x80U)
2382
2383/*! @name CDNE - Clear DONE Status Bit Register */
2384#define DMA_CDNE_CDNE_MASK (0xFU)
2385#define DMA_CDNE_CDNE_SHIFT (0U)
2386#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
2387#define DMA_CDNE_CADN (0x40U)
2388#define DMA_CDNE_NOP (0x80U)
2389
2390/*! @name SSRT - Set START Bit Register */
2391#define DMA_SSRT_SSRT_MASK (0xFU)
2392#define DMA_SSRT_SSRT_SHIFT (0U)
2393#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
2394#define DMA_SSRT_SAST (0x40U)
2395#define DMA_SSRT_NOP (0x80U)
2396
2397/*! @name CERR - Clear Error Register */
2398#define DMA_CERR_CERR_MASK (0xFU)
2399#define DMA_CERR_CERR_SHIFT (0U)
2400#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
2401#define DMA_CERR_CAEI (0x40U)
2402#define DMA_CERR_NOP (0x80U)
2403
2404/*! @name CINT - Clear Interrupt Request Register */
2405#define DMA_CINT_CINT_MASK (0xFU)
2406#define DMA_CINT_CINT_SHIFT (0U)
2407#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
2408#define DMA_CINT_CAIR (0x40U)
2409#define DMA_CINT_NOP (0x80U)
2410
2411/*! @name DCHPRIn - Channel n Priority Register */
2412#define DMA_DCHPRIn_CHPRI_MASK (0xFU)
2413#define DMA_DCHPRIn_CHPRI_SHIFT (0U)
2414#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
2415#define DMA_DCHPRIn_DPA (0x40U)
2416#define DMA_DCHPRIn_ECP (0x80U)
2417
2418/*! @name SOFF - TCD Signed Source Address Offset */
2419#define DMA_SOFF_SOFF_MASK (0xFFFFU)
2420#define DMA_SOFF_SOFF_SHIFT (0U)
2421#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
2422
2423/*! @name ATTR - TCD Transfer Attributes */
2424#define DMA_ATTR_DSIZE_MASK (0x7U)
2425#define DMA_ATTR_DSIZE_SHIFT (0U)
2426#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
2427#define DMA_ATTR_DMOD_MASK (0xF8U)
2428#define DMA_ATTR_DMOD_SHIFT (3U)
2429#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
2430#define DMA_ATTR_SSIZE_MASK (0x700U)
2431#define DMA_ATTR_SSIZE_SHIFT (8U)
2432#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
2433#define DMA_ATTR_SMOD_MASK (0xF800U)
2434#define DMA_ATTR_SMOD_SHIFT (11U)
2435#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
2436
2437/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
2438#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
2439#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
2440#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
2441#define DMA_NBYTES_MLOFFNO_DMLOE (0x40000000U)
2442#define DMA_NBYTES_MLOFFNO_SMLOE (0x80000000U)
2443
2444/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
2445#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
2446#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
2447#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
2448#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
2449#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
2450#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
2451#define DMA_NBYTES_MLOFFYES_DMLOE (0x40000000U)
2452#define DMA_NBYTES_MLOFFYES_SMLOE (0x80000000U)
2453
2454/*! @name DOFF - TCD Signed Destination Address Offset */
2455#define DMA_DOFF_DOFF_MASK (0xFFFFU)
2456#define DMA_DOFF_DOFF_SHIFT (0U)
2457#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
2458
2459/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
2460#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
2461#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
2462#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
2463#define DMA_CITER_ELINKNO_ELINK (0x8000U)
2464
2465/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
2466#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
2467#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
2468#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
2469#define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U)
2470#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
2471#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
2472#define DMA_CITER_ELINKYES_ELINK (0x8000U)
2473
2474/*! @name CSR - TCD Control and Status */
2475#define DMA_CSR_START (0x1U)
2476#define DMA_CSR_INTMAJOR (0x2U)
2477#define DMA_CSR_INTHALF (0x4U)
2478#define DMA_CSR_DREQ (0x8U)
2479#define DMA_CSR_ESG (0x10U)
2480#define DMA_CSR_MAJORELINK (0x20U)
2481#define DMA_CSR_ACTIVE (0x40U)
2482#define DMA_CSR_DONE (0x80U)
2483#define DMA_CSR_MAJORLINKCH_MASK (0xF00U)
2484#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
2485#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
2486#define DMA_CSR_BWC_MASK (0xC000U)
2487#define DMA_CSR_BWC_SHIFT (14U)
2488#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
2489
2490/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
2491#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
2492#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
2493#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
2494#define DMA_BITER_ELINKNO_ELINK (0x8000U)
2495
2496/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
2497#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
2498#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
2499#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
2500#define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U)
2501#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
2502#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
2503#define DMA_BITER_ELINKYES_ELINK (0x8000U)
2504
2505/* The count of DMA_TCD */
2506#define DMA_TCD_COUNT (16U)
2507
2508/*!
2509 * @}
2510 */ /* end of group DMA_Register_Masks */
2511
2512
2513/* DMA - Peripheral instance base addresses */
2514/** Peripheral DMA base address */
2515#define DMA_BASE (0x40008000u)
2516/** Peripheral DMA base pointer */
2517#define DMA0 ((DMA_TypeDef *)DMA_BASE)
2518/** Array initializer of DMA peripheral base addresses */
2519#define DMA_BASE_ADDRS { DMA_BASE }
2520/** Array initializer of DMA peripheral base pointers */
2521#define DMA_BASE_PTRS { DMA0 }
2522/** Interrupt vectors for the DMA peripheral type */
2523#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
2524#define DMA_ERROR_IRQS { DMA_Error_IRQn }
2525
2526/*!
2527 * @}
2528 */ /* end of group DMA_Peripheral_Access_Layer */
2529
2530
2531/* ----------------------------------------------------------------------------
2532 -- DMAMUX Peripheral Access Layer
2533 ---------------------------------------------------------------------------- */
2534
2535/*!
2536 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
2537 * @{
2538 */
2539
2540/** DMAMUX - Register Layout Typedef */
2541typedef struct {
2542 __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
2543} DMAMUX_TypeDef;
2544
2545/* ----------------------------------------------------------------------------
2546 -- DMAMUX Register Masks
2547 ---------------------------------------------------------------------------- */
2548
2549/*!
2550 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
2551 * @{
2552 */
2553
2554/*! @name CHCFG - Channel Configuration register */
2555#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
2556#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
2557#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
2558#define DMAMUX_CHCFG_TRIG (0x40U)
2559#define DMAMUX_CHCFG_ENBL (0x80U)
2560
2561/* The count of DMAMUX_CHCFG */
2562#define DMAMUX_CHCFG_COUNT (16U)
2563
2564
2565/*!
2566 * @}
2567 */ /* end of group DMAMUX_Register_Masks */
2568
2569
2570/* DMAMUX - Peripheral instance base addresses */
2571/** Peripheral DMAMUX base address */
2572#define DMAMUX_BASE (0x40021000u)
2573/** Peripheral DMAMUX base pointer */
2574#define DMAMUX ((DMAMUX_TypeDef *)DMAMUX_BASE)
2575/** Array initializer of DMAMUX peripheral base addresses */
2576#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
2577/** Array initializer of DMAMUX peripheral base pointers */
2578#define DMAMUX_BASE_PTRS { DMAMUX }
2579
2580/*!
2581 * @}
2582 */ /* end of group DMAMUX_Peripheral_Access_Layer */
2583
2584
2585/* ----------------------------------------------------------------------------
2586 -- ENET Peripheral Access Layer
2587 ---------------------------------------------------------------------------- */
2588
2589/*!
2590 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
2591 * @{
2592 */
2593
2594/** ENET - Register Layout Typedef */
2595typedef struct {
2596 uint8_t RESERVED_0[4];
2597 __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
2598 __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
2599 uint8_t RESERVED_1[4];
2600 __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
2601 __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
2602 uint8_t RESERVED_2[12];
2603 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
2604 uint8_t RESERVED_3[24];
2605 __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
2606 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
2607 uint8_t RESERVED_4[28];
2608 __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
2609 uint8_t RESERVED_5[28];
2610 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
2611 uint8_t RESERVED_6[60];
2612 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
2613 uint8_t RESERVED_7[28];
2614 __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
2615 __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
2616 __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
2617 uint8_t RESERVED_8[40];
2618 __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
2619 __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
2620 __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
2621 __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
2622 uint8_t RESERVED_9[28];
2623 __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
2624 uint8_t RESERVED_10[56];
2625 __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
2626 __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
2627 __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
2628 uint8_t RESERVED_11[4];
2629 __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
2630 __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
2631 __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
2632 __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
2633 __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
2634 __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
2635 __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
2636 __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
2637 __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
2638 uint8_t RESERVED_12[12];
2639 __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
2640 __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
2641 uint8_t RESERVED_13[60];
2642 __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
2643 __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
2644 __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
2645 __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
2646 __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
2647 __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
2648 __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
2649 __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
2650 __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
2651 __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
2652 __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
2653 __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
2654 __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
2655 __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
2656 __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
2657 __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
2658 __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
2659 uint8_t RESERVED_14[4];
2660 __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
2661 __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
2662 __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
2663 __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
2664 __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
2665 __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
2666 __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
2667 __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
2668 uint8_t RESERVED_15[4];
2669 __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
2670 __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
2671 uint8_t RESERVED_16[12];
2672 __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
2673 __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
2674 __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
2675 __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
2676 __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
2677 __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
2678 __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
2679 __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
2680 uint8_t RESERVED_17[4];
2681 __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
2682 __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
2683 __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
2684 __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
2685 __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
2686 __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
2687 __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
2688 __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
2689 __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
2690 __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
2691 __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
2692 __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
2693 __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
2694 __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
2695 __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
2696 uint8_t RESERVED_18[284];
2697 __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
2698 __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
2699 __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
2700 __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
2701 __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
2702 __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
2703 __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
2704 uint8_t RESERVED_19[488];
2705 __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
2706 struct { /* offset: 0x608, array step: 0x8 */
2707 __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
2708 __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
2709 } CHANNEL[4];
2710} ENET_TypeDef;
2711
2712/* ----------------------------------------------------------------------------
2713 -- ENET Register Masks
2714 ---------------------------------------------------------------------------- */
2715
2716/*!
2717 * @addtogroup ENET_Register_Masks ENET Register Masks
2718 * @{
2719 */
2720
2721/*! @name EIR - Interrupt Event Register */
2722#define ENET_EIR_TS_TIMER (0x8000U)
2723#define ENET_EIR_TS_AVAIL (0x10000U)
2724#define ENET_EIR_WAKEUP (0x20000U)
2725#define ENET_EIR_PLR (0x40000U)
2726#define ENET_EIR_UN (0x80000U)
2727#define ENET_EIR_RL (0x100000U)
2728#define ENET_EIR_LC (0x200000U)
2729#define ENET_EIR_EBERR (0x400000U)
2730#define ENET_EIR_MII (0x800000U)
2731#define ENET_EIR_RXB (0x1000000U)
2732#define ENET_EIR_RXF (0x2000000U)
2733#define ENET_EIR_TXB (0x4000000U)
2734#define ENET_EIR_TXF (0x8000000U)
2735#define ENET_EIR_GRA (0x10000000U)
2736#define ENET_EIR_BABT (0x20000000U)
2737#define ENET_EIR_BABR (0x40000000U)
2738
2739/*! @name EIMR - Interrupt Mask Register */
2740#define ENET_EIMR_TS_TIMER (0x8000U)
2741#define ENET_EIMR_TS_AVAIL (0x10000U)
2742#define ENET_EIMR_WAKEUP (0x20000U)
2743#define ENET_EIMR_PLR (0x40000U)
2744#define ENET_EIMR_UN (0x80000U)
2745#define ENET_EIMR_RL (0x100000U)
2746#define ENET_EIMR_LC (0x200000U)
2747#define ENET_EIMR_EBERR (0x400000U)
2748#define ENET_EIMR_MII (0x800000U)
2749#define ENET_EIMR_RXB (0x1000000U)
2750#define ENET_EIMR_RXF (0x2000000U)
2751#define ENET_EIMR_TXB (0x4000000U)
2752#define ENET_EIMR_TXF (0x8000000U)
2753#define ENET_EIMR_GRA (0x10000000U)
2754#define ENET_EIMR_BABT (0x20000000U)
2755#define ENET_EIMR_BABR (0x40000000U)
2756
2757/*! @name RDAR - Receive Descriptor Active Register */
2758#define ENET_RDAR_RDAR (0x1000000U)
2759
2760/*! @name TDAR - Transmit Descriptor Active Register */
2761#define ENET_TDAR_TDAR (0x1000000U)
2762
2763/*! @name ECR - Ethernet Control Register */
2764#define ENET_ECR_RESET (0x1U)
2765#define ENET_ECR_ETHEREN (0x2U)
2766#define ENET_ECR_MAGICEN (0x4U)
2767#define ENET_ECR_SLEEP (0x8U)
2768#define ENET_ECR_EN1588 (0x10U)
2769#define ENET_ECR_DBGEN (0x40U)
2770#define ENET_ECR_STOPEN (0x80U)
2771#define ENET_ECR_DBSWP (0x100U)
2772
2773/*! @name MMFR - MII Management Frame Register */
2774#define ENET_MMFR_DATA_MASK (0xFFFFU)
2775#define ENET_MMFR_DATA_SHIFT (0U)
2776#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
2777#define ENET_MMFR_TA_MASK (0x30000U)
2778#define ENET_MMFR_TA_SHIFT (16U)
2779#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
2780#define ENET_MMFR_RA_MASK (0x7C0000U)
2781#define ENET_MMFR_RA_SHIFT (18U)
2782#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
2783#define ENET_MMFR_PA_MASK (0xF800000U)
2784#define ENET_MMFR_PA_SHIFT (23U)
2785#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
2786#define ENET_MMFR_OP_MASK (0x30000000U)
2787#define ENET_MMFR_OP_SHIFT (28U)
2788#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
2789#define ENET_MMFR_ST_MASK (0xC0000000U)
2790#define ENET_MMFR_ST_SHIFT (30U)
2791#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
2792
2793/*! @name MSCR - MII Speed Control Register */
2794#define ENET_MSCR_MII_SPEED_MASK (0x7EU)
2795#define ENET_MSCR_MII_SPEED_SHIFT (1U)
2796#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
2797#define ENET_MSCR_DIS_PRE (0x80U)
2798#define ENET_MSCR_HOLDTIME_MASK (0x700U)
2799#define ENET_MSCR_HOLDTIME_SHIFT (8U)
2800#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
2801
2802/*! @name MIBC - MIB Control Register */
2803#define ENET_MIBC_MIB_CLEAR (0x20000000U)
2804#define ENET_MIBC_MIB_IDLE (0x40000000U)
2805#define ENET_MIBC_MIB_DIS (0x80000000U)
2806
2807/*! @name RCR - Receive Control Register */
2808#define ENET_RCR_LOOP (0x1U)
2809#define ENET_RCR_DRT (0x2U)
2810#define ENET_RCR_MII_MODE (0x4U)
2811#define ENET_RCR_PROM (0x8U)
2812#define ENET_RCR_BC_REJ (0x10U)
2813#define ENET_RCR_FCE (0x20U)
2814#define ENET_RCR_RMII_MODE (0x100U)
2815#define ENET_RCR_RMII_10T (0x200U)
2816#define ENET_RCR_PADEN (0x1000U)
2817#define ENET_RCR_PAUFWD (0x2000U)
2818#define ENET_RCR_CRCFWD (0x4000U)
2819#define ENET_RCR_CFEN (0x8000U)
2820#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
2821#define ENET_RCR_MAX_FL_SHIFT (16U)
2822#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
2823#define ENET_RCR_NLC (0x40000000U)
2824#define ENET_RCR_GRS (0x80000000U)
2825
2826/*! @name TCR - Transmit Control Register */
2827#define ENET_TCR_GTS (0x1U)
2828#define ENET_TCR_FDEN (0x4U)
2829#define ENET_TCR_TFC_PAUSE (0x8U)
2830#define ENET_TCR_RFC_PAUSE (0x10U)
2831#define ENET_TCR_ADDSEL_MASK (0xE0U)
2832#define ENET_TCR_ADDSEL_SHIFT (5U)
2833#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
2834#define ENET_TCR_ADDINS (0x100U)
2835#define ENET_TCR_CRCFWD (0x200U)
2836
2837/*! @name PAUR - Physical Address Upper Register */
2838#define ENET_PAUR_TYPE_MASK (0xFFFFU)
2839#define ENET_PAUR_TYPE_SHIFT (0U)
2840#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
2841#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
2842#define ENET_PAUR_PADDR2_SHIFT (16U)
2843#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
2844
2845/*! @name OPD - Opcode/Pause Duration Register */
2846#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
2847#define ENET_OPD_PAUSE_DUR_SHIFT (0U)
2848#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
2849#define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
2850#define ENET_OPD_OPCODE_SHIFT (16U)
2851#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
2852
2853/*! @name TFWR - Transmit FIFO Watermark Register */
2854#define ENET_TFWR_TFWR_MASK (0x3FU)
2855#define ENET_TFWR_TFWR_SHIFT (0U)
2856#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
2857#define ENET_TFWR_STRFWD (0x100U)
2858
2859/*! @name RDSR - Receive Descriptor Ring Start Register */
2860#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
2861#define ENET_RDSR_R_DES_START_SHIFT (3U)
2862#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
2863
2864/*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */
2865#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
2866#define ENET_TDSR_X_DES_START_SHIFT (3U)
2867#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
2868
2869/*! @name MRBR - Maximum Receive Buffer Size Register */
2870#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)
2871#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
2872#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
2873
2874/*! @name RSFL - Receive FIFO Section Full Threshold */
2875#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)
2876#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
2877#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
2878
2879/*! @name RSEM - Receive FIFO Section Empty Threshold */
2880#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)
2881#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
2882#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
2883#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
2884#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
2885#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
2886
2887/*! @name RAEM - Receive FIFO Almost Empty Threshold */
2888#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)
2889#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
2890#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
2891
2892/*! @name RAFL - Receive FIFO Almost Full Threshold */
2893#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)
2894#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
2895#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
2896
2897/*! @name TSEM - Transmit FIFO Section Empty Threshold */
2898#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)
2899#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
2900#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
2901
2902/*! @name TAEM - Transmit FIFO Almost Empty Threshold */
2903#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)
2904#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
2905#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
2906
2907/*! @name TAFL - Transmit FIFO Almost Full Threshold */
2908#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)
2909#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
2910#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
2911
2912/*! @name TIPG - Transmit Inter-Packet Gap */
2913#define ENET_TIPG_IPG_MASK (0x1FU)
2914#define ENET_TIPG_IPG_SHIFT (0U)
2915#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
2916
2917/*! @name FTRL - Frame Truncation Length */
2918#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
2919#define ENET_FTRL_TRUNC_FL_SHIFT (0U)
2920#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
2921
2922/*! @name TACC - Transmit Accelerator Function Configuration */
2923#define ENET_TACC_SHIFT16 (0x1U)
2924#define ENET_TACC_IPCHK (0x8U)
2925#define ENET_TACC_PROCHK (0x10U)
2926
2927/*! @name RACC - Receive Accelerator Function Configuration */
2928#define ENET_RACC_PADREM (0x1U)
2929#define ENET_RACC_IPDIS (0x2U)
2930#define ENET_RACC_PRODIS (0x4U)
2931#define ENET_RACC_LINEDIS (0x40U)
2932#define ENET_RACC_SHIFT16 (0x80U)
2933
2934/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
2935#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
2936#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
2937#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
2938
2939/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
2940#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
2941#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
2942#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
2943
2944/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
2945#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
2946#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
2947#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
2948
2949/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
2950#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
2951#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
2952#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
2953
2954/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
2955#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
2956#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
2957#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
2958
2959/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
2960#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
2961#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
2962#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
2963
2964/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
2965#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
2966#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
2967#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
2968
2969/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
2970#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
2971#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
2972#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
2973
2974/*! @name RMON_T_COL - Tx Collision Count Statistic Register */
2975#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
2976#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
2977#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
2978
2979/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
2980#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
2981#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
2982#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
2983
2984/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
2985#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
2986#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
2987#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
2988
2989/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
2990#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
2991#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
2992#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
2993
2994/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
2995#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
2996#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
2997#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
2998
2999/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
3000#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
3001#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
3002#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
3003
3004/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
3005#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
3006#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
3007#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
3008
3009/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
3010#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
3011#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
3012#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
3013
3014/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
3015#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
3016#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
3017#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
3018
3019/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
3020#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
3021#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
3022#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
3023
3024/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
3025#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
3026#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
3027#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
3028
3029/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
3030#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
3031#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
3032#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
3033
3034/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
3035#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
3036#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
3037#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
3038
3039/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
3040#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
3041#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
3042#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
3043
3044/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
3045#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
3046#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
3047#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
3048
3049/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
3050#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
3051#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
3052#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
3053
3054/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
3055#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
3056#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
3057#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
3058
3059/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
3060#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
3061#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
3062#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
3063
3064/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
3065#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
3066#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
3067#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
3068
3069/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
3070#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
3071#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
3072#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
3073
3074/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
3075#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
3076#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
3077#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
3078
3079/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
3080#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
3081#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
3082#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
3083
3084/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
3085#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
3086#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
3087#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
3088
3089/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
3090#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
3091#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
3092#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
3093
3094/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
3095#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
3096#define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
3097#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
3098
3099/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
3100#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
3101#define ENET_RMON_R_P64_COUNT_SHIFT (0U)
3102#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
3103
3104/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
3105#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
3106#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
3107#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
3108
3109/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
3110#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
3111#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
3112#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
3113
3114/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
3115#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
3116#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
3117#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
3118
3119/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
3120#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
3121#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
3122#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
3123
3124/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
3125#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
3126#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
3127#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
3128
3129/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
3130#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
3131#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
3132#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
3133
3134/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
3135#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
3136#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
3137#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
3138
3139/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
3140#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
3141#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
3142#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
3143
3144/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
3145#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
3146#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
3147#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
3148
3149/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
3150#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
3151#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
3152#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
3153
3154/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
3155#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
3156#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
3157#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
3158
3159/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
3160#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
3161#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
3162#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
3163
3164/*! @name ATCR - Adjustable Timer Control Register */
3165#define ENET_ATCR_EN (0x1U)
3166#define ENET_ATCR_OFFEN (0x4U)
3167#define ENET_ATCR_OFFRST (0x8U)
3168#define ENET_ATCR_PEREN (0x10U)
3169#define ENET_ATCR_PINPER (0x80U)
3170#define ENET_ATCR_RESTART (0x200U)
3171#define ENET_ATCR_CAPTURE (0x800U)
3172#define ENET_ATCR_SLAVE (0x2000U)
3173
3174/*! @name ATCOR - Timer Correction Register */
3175#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
3176#define ENET_ATCOR_COR_SHIFT (0U)
3177#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
3178
3179/*! @name ATINC - Time-Stamping Clock Period Register */
3180#define ENET_ATINC_INC_MASK (0x7FU)
3181#define ENET_ATINC_INC_SHIFT (0U)
3182#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
3183#define ENET_ATINC_INC_CORR_MASK (0x7F00U)
3184#define ENET_ATINC_INC_CORR_SHIFT (8U)
3185#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
3186
3187/*! @name TGSR - Timer Global Status Register */
3188#define ENET_TGSR_TF0 (0x1U)
3189#define ENET_TGSR_TF1 (0x2U)
3190#define ENET_TGSR_TF2 (0x4U)
3191#define ENET_TGSR_TF3 (0x8U)
3192
3193/*! @name TCSR - Timer Control Status Register */
3194#define ENET_TCSR_TDRE (0x1U)
3195#define ENET_TCSR_TMODE_MASK (0x3CU)
3196#define ENET_TCSR_TMODE_SHIFT (2U)
3197#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
3198#define ENET_TCSR_TIE (0x40U)
3199#define ENET_TCSR_TF (0x80U)
3200
3201/* The count of ENET_TCSR */
3202#define ENET_TCSR_COUNT (4U)
3203
3204/* The count of ENET_TCCR */
3205#define ENET_TCCR_COUNT (4U)
3206
3207
3208/*!
3209 * @}
3210 */ /* end of group ENET_Register_Masks */
3211
3212
3213/* ENET - Peripheral instance base addresses */
3214/** Peripheral ENET base address */
3215#define ENET_BASE (0x400C0000u)
3216/** Peripheral ENET base pointer */
3217#define ENET ((ENET_TypeDef *)ENET_BASE)
3218/** Array initializer of ENET peripheral base addresses */
3219#define ENET_BASE_ADDRS { ENET_BASE }
3220/** Array initializer of ENET peripheral base pointers */
3221#define ENET_BASE_PTRS { ENET }
3222/** Interrupt vectors for the ENET peripheral type */
3223#define ENET_Transmit_IRQS { ENET_Transmit_IRQn }
3224#define ENET_Receive_IRQS { ENET_Receive_IRQn }
3225#define ENET_Error_IRQS { ENET_Error_IRQn }
3226#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
3227
3228/*!
3229 * @}
3230 */ /* end of group ENET_Peripheral_Access_Layer */
3231
3232
3233/* ----------------------------------------------------------------------------
3234 -- EWM Peripheral Access Layer
3235 ---------------------------------------------------------------------------- */
3236
3237/*!
3238 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
3239 * @{
3240 */
3241
3242/** EWM - Register Layout Typedef */
3243typedef struct {
3244 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
3245 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
3246 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
3247 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
3248} EWM_TypeDef;
3249
3250/* ----------------------------------------------------------------------------
3251 -- EWM Register Masks
3252 ---------------------------------------------------------------------------- */
3253
3254/*!
3255 * @addtogroup EWM_Register_Masks EWM Register Masks
3256 * @{
3257 */
3258
3259/*! @name CTRL - Control Register */
3260#define EWM_CTRL_EWMEN (0x1U)
3261#define EWM_CTRL_ASSIN (0x2U)
3262#define EWM_CTRL_INEN (0x4U)
3263#define EWM_CTRL_INTEN (0x8U)
3264
3265/*! @name SERV - Service Register */
3266#define EWM_SERV_SERVICE_MASK (0xFFU)
3267#define EWM_SERV_SERVICE_SHIFT (0U)
3268#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
3269
3270/*! @name CMPL - Compare Low Register */
3271#define EWM_CMPL_COMPAREL_MASK (0xFFU)
3272#define EWM_CMPL_COMPAREL_SHIFT (0U)
3273#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
3274
3275/*! @name CMPH - Compare High Register */
3276#define EWM_CMPH_COMPAREH_MASK (0xFFU)
3277#define EWM_CMPH_COMPAREH_SHIFT (0U)
3278#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
3279
3280
3281/*!
3282 * @}
3283 */ /* end of group EWM_Register_Masks */
3284
3285
3286/* EWM - Peripheral instance base addresses */
3287/** Peripheral EWM base address */
3288#define EWM_BASE (0x40061000u)
3289/** Peripheral EWM base pointer */
3290#define EWM ((EWM_TypeDef *)EWM_BASE)
3291/** Array initializer of EWM peripheral base addresses */
3292#define EWM_BASE_ADDRS { EWM_BASE }
3293/** Array initializer of EWM peripheral base pointers */
3294#define EWM_BASE_PTRS { EWM }
3295/** Interrupt vectors for the EWM peripheral type */
3296#define EWM_IRQS { WDOG_EWM_IRQn }
3297
3298/*!
3299 * @}
3300 */ /* end of group EWM_Peripheral_Access_Layer */
3301
3302
3303/* ----------------------------------------------------------------------------
3304 -- FB Peripheral Access Layer
3305 ---------------------------------------------------------------------------- */
3306
3307/*!
3308 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
3309 * @{
3310 */
3311
3312/** FB - Register Layout Typedef */
3313typedef struct {
3314 struct { /* offset: 0x0, array step: 0xC */
3315 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
3316 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
3317 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
3318 } CS[6];
3319 uint8_t RESERVED_0[24];
3320 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
3321} FB_TypeDef;
3322
3323/* ----------------------------------------------------------------------------
3324 -- FB Register Masks
3325 ---------------------------------------------------------------------------- */
3326
3327/*!
3328 * @addtogroup FB_Register_Masks FB Register Masks
3329 * @{
3330 */
3331
3332/*! @name CSAR - Chip Select Address Register */
3333#define FB_CSAR_BA_MASK (0xFFFF0000U)
3334#define FB_CSAR_BA_SHIFT (16U)
3335#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
3336
3337/* The count of FB_CSAR */
3338#define FB_CSAR_COUNT (6U)
3339
3340/*! @name CSMR - Chip Select Mask Register */
3341#define FB_CSMR_V (0x1U)
3342#define FB_CSMR_WP (0x100U)
3343#define FB_CSMR_BAM_MASK (0xFFFF0000U)
3344#define FB_CSMR_BAM_SHIFT (16U)
3345#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
3346
3347/* The count of FB_CSMR */
3348#define FB_CSMR_COUNT (6U)
3349
3350/*! @name CSCR - Chip Select Control Register */
3351#define FB_CSCR_BSTW (0x8U)
3352#define FB_CSCR_BSTR (0x10U)
3353#define FB_CSCR_BEM (0x20U)
3354#define FB_CSCR_PS_MASK (0xC0U)
3355#define FB_CSCR_PS_SHIFT (6U)
3356#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
3357#define FB_CSCR_AA (0x100U)
3358#define FB_CSCR_BLS (0x200U)
3359#define FB_CSCR_WS_MASK (0xFC00U)
3360#define FB_CSCR_WS_SHIFT (10U)
3361#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
3362#define FB_CSCR_WRAH_MASK (0x30000U)
3363#define FB_CSCR_WRAH_SHIFT (16U)
3364#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
3365#define FB_CSCR_RDAH_MASK (0xC0000U)
3366#define FB_CSCR_RDAH_SHIFT (18U)
3367#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
3368#define FB_CSCR_ASET_MASK (0x300000U)
3369#define FB_CSCR_ASET_SHIFT (20U)
3370#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
3371#define FB_CSCR_EXTS (0x400000U)
3372#define FB_CSCR_SWSEN (0x800000U)
3373#define FB_CSCR_SWS_MASK (0xFC000000U)
3374#define FB_CSCR_SWS_SHIFT (26U)
3375#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
3376
3377/* The count of FB_CSCR */
3378#define FB_CSCR_COUNT (6U)
3379
3380/*! @name CSPMCR - Chip Select port Multiplexing Control Register */
3381#define FB_CSPMCR_GROUP5_MASK (0xF000U)
3382#define FB_CSPMCR_GROUP5_SHIFT (12U)
3383#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
3384#define FB_CSPMCR_GROUP4_MASK (0xF0000U)
3385#define FB_CSPMCR_GROUP4_SHIFT (16U)
3386#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
3387#define FB_CSPMCR_GROUP3_MASK (0xF00000U)
3388#define FB_CSPMCR_GROUP3_SHIFT (20U)
3389#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
3390#define FB_CSPMCR_GROUP2_MASK (0xF000000U)
3391#define FB_CSPMCR_GROUP2_SHIFT (24U)
3392#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
3393#define FB_CSPMCR_GROUP1_MASK (0xF0000000U)
3394#define FB_CSPMCR_GROUP1_SHIFT (28U)
3395#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
3396
3397
3398/*!
3399 * @}
3400 */ /* end of group FB_Register_Masks */
3401
3402
3403/* FB - Peripheral instance base addresses */
3404/** Peripheral FB base address */
3405#define FB_BASE (0x4000C000u)
3406/** Peripheral FB base pointer */
3407#define FB ((FB_TypeDef *)FB_BASE)
3408/** Array initializer of FB peripheral base addresses */
3409#define FB_BASE_ADDRS { FB_BASE }
3410/** Array initializer of FB peripheral base pointers */
3411#define FB_BASE_PTRS { FB }
3412
3413/*!
3414 * @}
3415 */ /* end of group FB_Peripheral_Access_Layer */
3416
3417
3418/* ----------------------------------------------------------------------------
3419 -- FMC Peripheral Access Layer
3420 ---------------------------------------------------------------------------- */
3421
3422/*!
3423 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
3424 * @{
3425 */
3426
3427/** FMC - Register Layout Typedef */
3428typedef struct {
3429 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
3430 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
3431 __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
3432 uint8_t RESERVED_0[244];
3433 __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
3434 __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
3435 __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
3436 __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
3437 uint8_t RESERVED_1[192];
3438 struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */
3439 __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
3440 __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
3441 } SET[4][4];
3442} FMC_TypeDef;
3443
3444/* ----------------------------------------------------------------------------
3445 -- FMC Register Masks
3446 ---------------------------------------------------------------------------- */
3447
3448/*!
3449 * @addtogroup FMC_Register_Masks FMC Register Masks
3450 * @{
3451 */
3452
3453/*! @name PFAPR - Flash Access Protection Register */
3454#define FMC_PFAPR_M0AP_MASK (0x3U)
3455#define FMC_PFAPR_M0AP_SHIFT (0U)
3456#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
3457#define FMC_PFAPR_M1AP_MASK (0xCU)
3458#define FMC_PFAPR_M1AP_SHIFT (2U)
3459#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
3460#define FMC_PFAPR_M2AP_MASK (0x30U)
3461#define FMC_PFAPR_M2AP_SHIFT (4U)
3462#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
3463#define FMC_PFAPR_M3AP_MASK (0xC0U)
3464#define FMC_PFAPR_M3AP_SHIFT (6U)
3465#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
3466#define FMC_PFAPR_M4AP_MASK (0x300U)
3467#define FMC_PFAPR_M4AP_SHIFT (8U)
3468#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
3469#define FMC_PFAPR_M5AP_MASK (0xC00U)
3470#define FMC_PFAPR_M5AP_SHIFT (10U)
3471#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
3472#define FMC_PFAPR_M6AP_MASK (0x3000U)
3473#define FMC_PFAPR_M6AP_SHIFT (12U)
3474#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
3475#define FMC_PFAPR_M7AP_MASK (0xC000U)
3476#define FMC_PFAPR_M7AP_SHIFT (14U)
3477#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
3478#define FMC_PFAPR_M0PFD (0x10000U)
3479#define FMC_PFAPR_M1PFD (0x20000U)
3480#define FMC_PFAPR_M2PFD (0x40000U)
3481#define FMC_PFAPR_M3PFD (0x80000U)
3482#define FMC_PFAPR_M4PFD (0x100000U)
3483#define FMC_PFAPR_M5PFD (0x200000U)
3484#define FMC_PFAPR_M6PFD (0x400000U)
3485#define FMC_PFAPR_M7PFD (0x800000U)
3486
3487/*! @name PFB0CR - Flash Bank 0 Control Register */
3488#define FMC_PFB0CR_B0SEBE (0x1U)
3489#define FMC_PFB0CR_B0IPE (0x2U)
3490#define FMC_PFB0CR_B0DPE (0x4U)
3491#define FMC_PFB0CR_B0ICE (0x8U)
3492#define FMC_PFB0CR_B0DCE (0x10U)
3493#define FMC_PFB0CR_CRC_MASK (0xE0U)
3494#define FMC_PFB0CR_CRC_SHIFT (5U)
3495#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
3496#define FMC_PFB0CR_B0MW_MASK (0x60000U)
3497#define FMC_PFB0CR_B0MW_SHIFT (17U)
3498#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
3499#define FMC_PFB0CR_S_B_INV (0x80000U)
3500#define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U)
3501#define FMC_PFB0CR_CINV_WAY_SHIFT (20U)
3502#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
3503#define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U)
3504#define FMC_PFB0CR_CLCK_WAY_SHIFT (24U)
3505#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
3506#define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U)
3507#define FMC_PFB0CR_B0RWSC_SHIFT (28U)
3508#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
3509
3510/*! @name PFB1CR - Flash Bank 1 Control Register */
3511#define FMC_PFB1CR_B1SEBE (0x1U)
3512#define FMC_PFB1CR_B1IPE (0x2U)
3513#define FMC_PFB1CR_B1DPE (0x4U)
3514#define FMC_PFB1CR_B1ICE (0x8U)
3515#define FMC_PFB1CR_B1DCE (0x10U)
3516#define FMC_PFB1CR_B1MW_MASK (0x60000U)
3517#define FMC_PFB1CR_B1MW_SHIFT (17U)
3518#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)
3519#define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U)
3520#define FMC_PFB1CR_B1RWSC_SHIFT (28U)
3521#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK)
3522
3523/*! @name TAGVDW0S - Cache Tag Storage */
3524#define FMC_TAGVDW0S_valid (0x1U)
3525#define FMC_TAGVDW0S_tag_MASK (0x7FFE0U)
3526#define FMC_TAGVDW0S_tag_SHIFT (5U)
3527#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
3528
3529/* The count of FMC_TAGVDW0S */
3530#define FMC_TAGVDW0S_COUNT (4U)
3531
3532/*! @name TAGVDW1S - Cache Tag Storage */
3533#define FMC_TAGVDW1S_valid (0x1U)
3534#define FMC_TAGVDW1S_tag_MASK (0x7FFE0U)
3535#define FMC_TAGVDW1S_tag_SHIFT (5U)
3536#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
3537
3538/* The count of FMC_TAGVDW1S */
3539#define FMC_TAGVDW1S_COUNT (4U)
3540
3541/*! @name TAGVDW2S - Cache Tag Storage */
3542#define FMC_TAGVDW2S_valid (0x1U)
3543#define FMC_TAGVDW2S_tag_MASK (0x7FFE0U)
3544#define FMC_TAGVDW2S_tag_SHIFT (5U)
3545#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
3546
3547/* The count of FMC_TAGVDW2S */
3548#define FMC_TAGVDW2S_COUNT (4U)
3549
3550/*! @name TAGVDW3S - Cache Tag Storage */
3551#define FMC_TAGVDW3S_valid (0x1U)
3552#define FMC_TAGVDW3S_tag_MASK (0x7FFE0U)
3553#define FMC_TAGVDW3S_tag_SHIFT (5U)
3554#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
3555
3556/* The count of FMC_TAGVDW3S */
3557#define FMC_TAGVDW3S_COUNT (4U)
3558
3559/* The count of FMC_DATA_U */
3560#define FMC_DATA_U_COUNT (4U)
3561
3562/* The count of FMC_DATA_U */
3563#define FMC_DATA_U_COUNT2 (4U)
3564
3565/* The count of FMC_DATA_L */
3566#define FMC_DATA_L_COUNT (4U)
3567
3568/* The count of FMC_DATA_L */
3569#define FMC_DATA_L_COUNT2 (4U)
3570
3571
3572/*!
3573 * @}
3574 */ /* end of group FMC_Register_Masks */
3575
3576
3577/* FMC - Peripheral instance base addresses */
3578/** Peripheral FMC base address */
3579#define FMC_BASE (0x4001F000u)
3580/** Peripheral FMC base pointer */
3581#define FMC ((FMC_TypeDef *)FMC_BASE)
3582/** Array initializer of FMC peripheral base addresses */
3583#define FMC_BASE_ADDRS { FMC_BASE }
3584/** Array initializer of FMC peripheral base pointers */
3585#define FMC_BASE_PTRS { FMC }
3586
3587/*!
3588 * @}
3589 */ /* end of group FMC_Peripheral_Access_Layer */
3590
3591
3592/* ----------------------------------------------------------------------------
3593 -- FTFE Peripheral Access Layer
3594 ---------------------------------------------------------------------------- */
3595
3596/*!
3597 * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
3598 * @{
3599 */
3600
3601/** FTFE - Register Layout Typedef */
3602typedef struct {
3603 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
3604 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
3605 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
3606 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
3607 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
3608 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
3609 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
3610 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
3611 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
3612 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
3613 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
3614 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
3615 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
3616 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
3617 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
3618 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
3619 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
3620 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
3621 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
3622 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
3623 uint8_t RESERVED_0[2];
3624 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
3625 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
3626} FTFE_TypeDef;
3627
3628/* ----------------------------------------------------------------------------
3629 -- FTFE Register Masks
3630 ---------------------------------------------------------------------------- */
3631
3632/*!
3633 * @addtogroup FTFE_Register_Masks FTFE Register Masks
3634 * @{
3635 */
3636
3637/*! @name FSTAT - Flash Status Register */
3638#define FTFE_FSTAT_MGSTAT0 (0x1U)
3639#define FTFE_FSTAT_FPVIOL (0x10U)
3640#define FTFE_FSTAT_ACCERR (0x20U)
3641#define FTFE_FSTAT_RDCOLERR (0x40U)
3642#define FTFE_FSTAT_CCIF (0x80U)
3643
3644/*! @name FCNFG - Flash Configuration Register */
3645#define FTFE_FCNFG_EEERDY (0x1U)
3646#define FTFE_FCNFG_RAMRDY (0x2U)
3647#define FTFE_FCNFG_PFLSH (0x4U)
3648#define FTFE_FCNFG_SWAP (0x8U)
3649#define FTFE_FCNFG_ERSSUSP (0x10U)
3650#define FTFE_FCNFG_ERSAREQ (0x20U)
3651#define FTFE_FCNFG_RDCOLLIE (0x40U)
3652#define FTFE_FCNFG_CCIE (0x80U)
3653
3654/*! @name FSEC - Flash Security Register */
3655#define FTFE_FSEC_SEC_MASK (0x3U)
3656#define FTFE_FSEC_SEC_SHIFT (0U)
3657#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
3658#define FTFE_FSEC_FSLACC_MASK (0xCU)
3659#define FTFE_FSEC_FSLACC_SHIFT (2U)
3660#define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
3661#define FTFE_FSEC_MEEN_MASK (0x30U)
3662#define FTFE_FSEC_MEEN_SHIFT (4U)
3663#define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
3664#define FTFE_FSEC_KEYEN_MASK (0xC0U)
3665#define FTFE_FSEC_KEYEN_SHIFT (6U)
3666#define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
3667
3668/*! @name FOPT - Flash Option Register */
3669#define FTFE_FOPT_OPT_MASK (0xFFU)
3670#define FTFE_FOPT_OPT_SHIFT (0U)
3671#define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)
3672
3673/*! @name FCCOB3 - Flash Common Command Object Registers */
3674#define FTFE_FCCOB3_CCOBn_MASK (0xFFU)
3675#define FTFE_FCCOB3_CCOBn_SHIFT (0U)
3676#define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
3677
3678/*! @name FCCOB2 - Flash Common Command Object Registers */
3679#define FTFE_FCCOB2_CCOBn_MASK (0xFFU)
3680#define FTFE_FCCOB2_CCOBn_SHIFT (0U)
3681#define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
3682
3683/*! @name FCCOB1 - Flash Common Command Object Registers */
3684#define FTFE_FCCOB1_CCOBn_MASK (0xFFU)
3685#define FTFE_FCCOB1_CCOBn_SHIFT (0U)
3686#define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
3687
3688/*! @name FCCOB0 - Flash Common Command Object Registers */
3689#define FTFE_FCCOB0_CCOBn_MASK (0xFFU)
3690#define FTFE_FCCOB0_CCOBn_SHIFT (0U)
3691#define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
3692
3693/*! @name FCCOB7 - Flash Common Command Object Registers */
3694#define FTFE_FCCOB7_CCOBn_MASK (0xFFU)
3695#define FTFE_FCCOB7_CCOBn_SHIFT (0U)
3696#define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
3697
3698/*! @name FCCOB6 - Flash Common Command Object Registers */
3699#define FTFE_FCCOB6_CCOBn_MASK (0xFFU)
3700#define FTFE_FCCOB6_CCOBn_SHIFT (0U)
3701#define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
3702
3703/*! @name FCCOB5 - Flash Common Command Object Registers */
3704#define FTFE_FCCOB5_CCOBn_MASK (0xFFU)
3705#define FTFE_FCCOB5_CCOBn_SHIFT (0U)
3706#define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
3707
3708/*! @name FCCOB4 - Flash Common Command Object Registers */
3709#define FTFE_FCCOB4_CCOBn_MASK (0xFFU)
3710#define FTFE_FCCOB4_CCOBn_SHIFT (0U)
3711#define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
3712
3713/*! @name FCCOBB - Flash Common Command Object Registers */
3714#define FTFE_FCCOBB_CCOBn_MASK (0xFFU)
3715#define FTFE_FCCOBB_CCOBn_SHIFT (0U)
3716#define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
3717
3718/*! @name FCCOBA - Flash Common Command Object Registers */
3719#define FTFE_FCCOBA_CCOBn_MASK (0xFFU)
3720#define FTFE_FCCOBA_CCOBn_SHIFT (0U)
3721#define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
3722
3723/*! @name FCCOB9 - Flash Common Command Object Registers */
3724#define FTFE_FCCOB9_CCOBn_MASK (0xFFU)
3725#define FTFE_FCCOB9_CCOBn_SHIFT (0U)
3726#define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
3727
3728/*! @name FCCOB8 - Flash Common Command Object Registers */
3729#define FTFE_FCCOB8_CCOBn_MASK (0xFFU)
3730#define FTFE_FCCOB8_CCOBn_SHIFT (0U)
3731#define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
3732
3733/*! @name FPROT3 - Program Flash Protection Registers */
3734#define FTFE_FPROT3_PROT_MASK (0xFFU)
3735#define FTFE_FPROT3_PROT_SHIFT (0U)
3736#define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)
3737
3738/*! @name FPROT2 - Program Flash Protection Registers */
3739#define FTFE_FPROT2_PROT_MASK (0xFFU)
3740#define FTFE_FPROT2_PROT_SHIFT (0U)
3741#define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)
3742
3743/*! @name FPROT1 - Program Flash Protection Registers */
3744#define FTFE_FPROT1_PROT_MASK (0xFFU)
3745#define FTFE_FPROT1_PROT_SHIFT (0U)
3746#define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)
3747
3748/*! @name FPROT0 - Program Flash Protection Registers */
3749#define FTFE_FPROT0_PROT_MASK (0xFFU)
3750#define FTFE_FPROT0_PROT_SHIFT (0U)
3751#define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)
3752
3753/*! @name FEPROT - EEPROM Protection Register */
3754#define FTFE_FEPROT_EPROT_MASK (0xFFU)
3755#define FTFE_FEPROT_EPROT_SHIFT (0U)
3756#define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)
3757
3758/*! @name FDPROT - Data Flash Protection Register */
3759#define FTFE_FDPROT_DPROT_MASK (0xFFU)
3760#define FTFE_FDPROT_DPROT_SHIFT (0U)
3761#define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)
3762
3763
3764/*!
3765 * @}
3766 */ /* end of group FTFE_Register_Masks */
3767
3768
3769/* FTFE - Peripheral instance base addresses */
3770/** Peripheral FTFE base address */
3771#define FTFE_BASE (0x40020000u)
3772/** Peripheral FTFE base pointer */
3773#define FTFE ((FTFE_TypeDef *)FTFE_BASE)
3774/** Array initializer of FTFE peripheral base addresses */
3775#define FTFE_BASE_ADDRS { FTFE_BASE }
3776/** Array initializer of FTFE peripheral base pointers */
3777#define FTFE_BASE_PTRS { FTFE }
3778/** Interrupt vectors for the FTFE peripheral type */
3779#define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn }
3780#define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn }
3781
3782/*!
3783 * @}
3784 */ /* end of group FTFE_Peripheral_Access_Layer */
3785
3786
3787/* ----------------------------------------------------------------------------
3788 -- FTM Peripheral Access Layer
3789 ---------------------------------------------------------------------------- */
3790
3791/*!
3792 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
3793 * @{
3794 */
3795
3796/** FTM - Register Layout Typedef */
3797typedef struct {
3798 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
3799 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
3800 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
3801 struct { /* offset: 0xC, array step: 0x8 */
3802 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
3803 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
3804 } CONTROLS[8];
3805 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
3806 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
3807 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
3808 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
3809 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
3810 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
3811 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
3812 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
3813 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
3814 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
3815 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
3816 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
3817 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
3818 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
3819 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
3820 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
3821 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
3822 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
3823 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
3824 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
3825} FTM_TypeDef;
3826
3827/* ----------------------------------------------------------------------------
3828 -- FTM Register Masks
3829 ---------------------------------------------------------------------------- */
3830
3831/*!
3832 * @addtogroup FTM_Register_Masks FTM Register Masks
3833 * @{
3834 */
3835
3836/*! @name SC - Status And Control */
3837#define FTM_SC_PS_MASK (0x7U)
3838#define FTM_SC_PS_SHIFT (0U)
3839#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
3840#define FTM_SC_CLKS_MASK (0x18U)
3841#define FTM_SC_CLKS_SHIFT (3U)
3842#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
3843#define FTM_SC_CPWMS (0x20U)
3844#define FTM_SC_TOIE (0x40U)
3845#define FTM_SC_TOF (0x80U)
3846
3847/*! @name CNT - Counter */
3848#define FTM_CNT_COUNT_MASK (0xFFFFU)
3849#define FTM_CNT_COUNT_SHIFT (0U)
3850#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
3851
3852/*! @name MOD - Modulo */
3853#define FTM_MOD_MOD_MASK (0xFFFFU)
3854#define FTM_MOD_MOD_SHIFT (0U)
3855#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
3856
3857/*! @name CnSC - Channel (n) Status And Control */
3858#define FTM_CnSC_DMA (0x1U)
3859#define FTM_CnSC_ELSA (0x4U)
3860#define FTM_CnSC_ELSB (0x8U)
3861#define FTM_CnSC_MSA (0x10U)
3862#define FTM_CnSC_MSB (0x20U)
3863#define FTM_CnSC_CHIE (0x40U)
3864#define FTM_CnSC_CHF (0x80U)
3865
3866/* The count of FTM_CnSC */
3867#define FTM_CnSC_COUNT (8U)
3868
3869/*! @name CnV - Channel (n) Value */
3870#define FTM_CnV_VAL_MASK (0xFFFFU)
3871#define FTM_CnV_VAL_SHIFT (0U)
3872#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
3873
3874/* The count of FTM_CnV */
3875#define FTM_CnV_COUNT (8U)
3876
3877/*! @name CNTIN - Counter Initial Value */
3878#define FTM_CNTIN_INIT_MASK (0xFFFFU)
3879#define FTM_CNTIN_INIT_SHIFT (0U)
3880#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
3881
3882/*! @name STATUS - Capture And Compare Status */
3883#define FTM_STATUS_CH0F (0x1U)
3884#define FTM_STATUS_CH1F (0x2U)
3885#define FTM_STATUS_CH2F (0x4U)
3886#define FTM_STATUS_CH3F (0x8U)
3887#define FTM_STATUS_CH4F (0x10U)
3888#define FTM_STATUS_CH5F (0x20U)
3889#define FTM_STATUS_CH6F (0x40U)
3890#define FTM_STATUS_CH7F (0x80U)
3891
3892/*! @name MODE - Features Mode Selection */
3893#define FTM_MODE_FTMEN (0x1U)
3894#define FTM_MODE_INIT (0x2U)
3895#define FTM_MODE_WPDIS (0x4U)
3896#define FTM_MODE_PWMSYNC (0x8U)
3897#define FTM_MODE_CAPTEST (0x10U)
3898#define FTM_MODE_FAULTM_MASK (0x60U)
3899#define FTM_MODE_FAULTM_SHIFT (5U)
3900#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
3901#define FTM_MODE_FAULTIE (0x80U)
3902
3903/*! @name SYNC - Synchronization */
3904#define FTM_SYNC_CNTMIN (0x1U)
3905#define FTM_SYNC_CNTMAX (0x2U)
3906#define FTM_SYNC_REINIT (0x4U)
3907#define FTM_SYNC_SYNCHOM (0x8U)
3908#define FTM_SYNC_TRIG0 (0x10U)
3909#define FTM_SYNC_TRIG1 (0x20U)
3910#define FTM_SYNC_TRIG2 (0x40U)
3911#define FTM_SYNC_SWSYNC (0x80U)
3912
3913/*! @name OUTINIT - Initial State For Channels Output */
3914#define FTM_OUTINIT_CH0OI (0x1U)
3915#define FTM_OUTINIT_CH1OI (0x2U)
3916#define FTM_OUTINIT_CH2OI (0x4U)
3917#define FTM_OUTINIT_CH3OI (0x8U)
3918#define FTM_OUTINIT_CH4OI (0x10U)
3919#define FTM_OUTINIT_CH5OI (0x20U)
3920#define FTM_OUTINIT_CH6OI (0x40U)
3921#define FTM_OUTINIT_CH7OI (0x80U)
3922
3923/*! @name OUTMASK - Output Mask */
3924#define FTM_OUTMASK_CH0OM (0x1U)
3925#define FTM_OUTMASK_CH1OM (0x2U)
3926#define FTM_OUTMASK_CH2OM (0x4U)
3927#define FTM_OUTMASK_CH3OM (0x8U)
3928#define FTM_OUTMASK_CH4OM (0x10U)
3929#define FTM_OUTMASK_CH5OM (0x20U)
3930#define FTM_OUTMASK_CH6OM (0x40U)
3931#define FTM_OUTMASK_CH7OM (0x80U)
3932
3933/*! @name COMBINE - Function For Linked Channels */
3934#define FTM_COMBINE_COMBINE0 (0x1U)
3935#define FTM_COMBINE_COMP0 (0x2U)
3936#define FTM_COMBINE_DECAPEN0 (0x4U)
3937#define FTM_COMBINE_DECAP0 (0x8U)
3938#define FTM_COMBINE_DTEN0 (0x10U)
3939#define FTM_COMBINE_SYNCEN0 (0x20U)
3940#define FTM_COMBINE_FAULTEN0 (0x40U)
3941#define FTM_COMBINE_COMBINE1 (0x100U)
3942#define FTM_COMBINE_COMP1 (0x200U)
3943#define FTM_COMBINE_DECAPEN1 (0x400U)
3944#define FTM_COMBINE_DECAP1 (0x800U)
3945#define FTM_COMBINE_DTEN1 (0x1000U)
3946#define FTM_COMBINE_SYNCEN1 (0x2000U)
3947#define FTM_COMBINE_FAULTEN1 (0x4000U)
3948#define FTM_COMBINE_COMBINE2 (0x10000U)
3949#define FTM_COMBINE_COMP2 (0x20000U)
3950#define FTM_COMBINE_DECAPEN2 (0x40000U)
3951#define FTM_COMBINE_DECAP2 (0x80000U)
3952#define FTM_COMBINE_DTEN2 (0x100000U)
3953#define FTM_COMBINE_SYNCEN2 (0x200000U)
3954#define FTM_COMBINE_FAULTEN2 (0x400000U)
3955#define FTM_COMBINE_COMBINE3 (0x1000000U)
3956#define FTM_COMBINE_COMP3 (0x2000000U)
3957#define FTM_COMBINE_DECAPEN3 (0x4000000U)
3958#define FTM_COMBINE_DECAP3 (0x8000000U)
3959#define FTM_COMBINE_DTEN3 (0x10000000U)
3960#define FTM_COMBINE_SYNCEN3 (0x20000000U)
3961#define FTM_COMBINE_FAULTEN3 (0x40000000U)
3962
3963/*! @name DEADTIME - Deadtime Insertion Control */
3964#define FTM_DEADTIME_DTVAL_MASK (0x3FU)
3965#define FTM_DEADTIME_DTVAL_SHIFT (0U)
3966#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
3967#define FTM_DEADTIME_DTPS_MASK (0xC0U)
3968#define FTM_DEADTIME_DTPS_SHIFT (6U)
3969#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
3970
3971/*! @name EXTTRIG - FTM External Trigger */
3972#define FTM_EXTTRIG_CH2TRIG (0x1U)
3973#define FTM_EXTTRIG_CH3TRIG (0x2U)
3974#define FTM_EXTTRIG_CH4TRIG (0x4U)
3975#define FTM_EXTTRIG_CH5TRIG (0x8U)
3976#define FTM_EXTTRIG_CH0TRIG (0x10U)
3977#define FTM_EXTTRIG_CH1TRIG (0x20U)
3978#define FTM_EXTTRIG_INITTRIGEN (0x40U)
3979#define FTM_EXTTRIG_TRIGF (0x80U)
3980
3981/*! @name POL - Channels Polarity */
3982#define FTM_POL_POL0 (0x1U)
3983#define FTM_POL_POL1 (0x2U)
3984#define FTM_POL_POL2 (0x4U)
3985#define FTM_POL_POL3 (0x8U)
3986#define FTM_POL_POL4 (0x10U)
3987#define FTM_POL_POL5 (0x20U)
3988#define FTM_POL_POL6 (0x40U)
3989#define FTM_POL_POL7 (0x80U)
3990
3991/*! @name FMS - Fault Mode Status */
3992#define FTM_FMS_FAULTF0 (0x1U)
3993#define FTM_FMS_FAULTF1 (0x2U)
3994#define FTM_FMS_FAULTF2 (0x4U)
3995#define FTM_FMS_FAULTF3 (0x8U)
3996#define FTM_FMS_FAULTIN (0x20U)
3997#define FTM_FMS_WPEN (0x40U)
3998#define FTM_FMS_FAULTF (0x80U)
3999
4000/*! @name FILTER - Input Capture Filter Control */
4001#define FTM_FILTER_CH0FVAL_MASK (0xFU)
4002#define FTM_FILTER_CH0FVAL_SHIFT (0U)
4003#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
4004#define FTM_FILTER_CH1FVAL_MASK (0xF0U)
4005#define FTM_FILTER_CH1FVAL_SHIFT (4U)
4006#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
4007#define FTM_FILTER_CH2FVAL_MASK (0xF00U)
4008#define FTM_FILTER_CH2FVAL_SHIFT (8U)
4009#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
4010#define FTM_FILTER_CH3FVAL_MASK (0xF000U)
4011#define FTM_FILTER_CH3FVAL_SHIFT (12U)
4012#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
4013
4014/*! @name FLTCTRL - Fault Control */
4015#define FTM_FLTCTRL_FAULT0EN (0x1U)
4016#define FTM_FLTCTRL_FAULT1EN (0x2U)
4017#define FTM_FLTCTRL_FAULT2EN (0x4U)
4018#define FTM_FLTCTRL_FAULT3EN (0x8U)
4019#define FTM_FLTCTRL_FFLTR0EN (0x10U)
4020#define FTM_FLTCTRL_FFLTR1EN (0x20U)
4021#define FTM_FLTCTRL_FFLTR2EN (0x40U)
4022#define FTM_FLTCTRL_FFLTR3EN (0x80U)
4023#define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
4024#define FTM_FLTCTRL_FFVAL_SHIFT (8U)
4025#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
4026
4027/*! @name QDCTRL - Quadrature Decoder Control And Status */
4028#define FTM_QDCTRL_QUADEN (0x1U)
4029#define FTM_QDCTRL_TOFDIR (0x2U)
4030#define FTM_QDCTRL_QUADIR (0x4U)
4031#define FTM_QDCTRL_QUADMODE (0x8U)
4032#define FTM_QDCTRL_PHBPOL (0x10U)
4033#define FTM_QDCTRL_PHAPOL (0x20U)
4034#define FTM_QDCTRL_PHBFLTREN (0x40U)
4035#define FTM_QDCTRL_PHAFLTREN (0x80U)
4036
4037/*! @name CONF - Configuration */
4038#define FTM_CONF_NUMTOF_MASK (0x1FU)
4039#define FTM_CONF_NUMTOF_SHIFT (0U)
4040#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
4041#define FTM_CONF_BDMMODE_MASK (0xC0U)
4042#define FTM_CONF_BDMMODE_SHIFT (6U)
4043#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
4044#define FTM_CONF_GTBEEN (0x200U)
4045#define FTM_CONF_GTBEOUT (0x400U)
4046
4047/*! @name FLTPOL - FTM Fault Input Polarity */
4048#define FTM_FLTPOL_FLT0POL (0x1U)
4049#define FTM_FLTPOL_FLT1POL (0x2U)
4050#define FTM_FLTPOL_FLT2POL (0x4U)
4051#define FTM_FLTPOL_FLT3POL (0x8U)
4052
4053/*! @name SYNCONF - Synchronization Configuration */
4054#define FTM_SYNCONF_HWTRIGMODE (0x1U)
4055#define FTM_SYNCONF_CNTINC (0x4U)
4056#define FTM_SYNCONF_INVC (0x10U)
4057#define FTM_SYNCONF_SWOC (0x20U)
4058#define FTM_SYNCONF_SYNCMODE (0x80U)
4059#define FTM_SYNCONF_SWRSTCNT (0x100U)
4060#define FTM_SYNCONF_SWWRBUF (0x200U)
4061#define FTM_SYNCONF_SWOM (0x400U)
4062#define FTM_SYNCONF_SWINVC (0x800U)
4063#define FTM_SYNCONF_SWSOC (0x1000U)
4064#define FTM_SYNCONF_HWRSTCNT (0x10000U)
4065#define FTM_SYNCONF_HWWRBUF (0x20000U)
4066#define FTM_SYNCONF_HWOM (0x40000U)
4067#define FTM_SYNCONF_HWINVC (0x80000U)
4068#define FTM_SYNCONF_HWSOC (0x100000U)
4069
4070/*! @name INVCTRL - FTM Inverting Control */
4071#define FTM_INVCTRL_INV0EN (0x1U)
4072#define FTM_INVCTRL_INV1EN (0x2U)
4073#define FTM_INVCTRL_INV2EN (0x4U)
4074#define FTM_INVCTRL_INV3EN (0x8U)
4075
4076/*! @name SWOCTRL - FTM Software Output Control */
4077#define FTM_SWOCTRL_CH0OC (0x1U)
4078#define FTM_SWOCTRL_CH1OC (0x2U)
4079#define FTM_SWOCTRL_CH2OC (0x4U)
4080#define FTM_SWOCTRL_CH3OC (0x8U)
4081#define FTM_SWOCTRL_CH4OC (0x10U)
4082#define FTM_SWOCTRL_CH5OC (0x20U)
4083#define FTM_SWOCTRL_CH6OC (0x40U)
4084#define FTM_SWOCTRL_CH7OC (0x80U)
4085#define FTM_SWOCTRL_CH0OCV (0x100U)
4086#define FTM_SWOCTRL_CH1OCV (0x200U)
4087#define FTM_SWOCTRL_CH2OCV (0x400U)
4088#define FTM_SWOCTRL_CH3OCV (0x800U)
4089#define FTM_SWOCTRL_CH4OCV (0x1000U)
4090#define FTM_SWOCTRL_CH5OCV (0x2000U)
4091#define FTM_SWOCTRL_CH6OCV (0x4000U)
4092#define FTM_SWOCTRL_CH7OCV (0x8000U)
4093
4094/*! @name PWMLOAD - FTM PWM Load */
4095#define FTM_PWMLOAD_CH0SEL (0x1U)
4096#define FTM_PWMLOAD_CH1SEL (0x2U)
4097#define FTM_PWMLOAD_CH2SEL (0x4U)
4098#define FTM_PWMLOAD_CH3SEL (0x8U)
4099#define FTM_PWMLOAD_CH4SEL (0x10U)
4100#define FTM_PWMLOAD_CH5SEL (0x20U)
4101#define FTM_PWMLOAD_CH6SEL (0x40U)
4102#define FTM_PWMLOAD_CH7SEL (0x80U)
4103#define FTM_PWMLOAD_LDOK (0x200U)
4104
4105
4106/*!
4107 * @}
4108 */ /* end of group FTM_Register_Masks */
4109
4110
4111/* FTM - Peripheral instance base addresses */
4112/** Peripheral FTM0 base address */
4113#define FTM0_BASE (0x40038000u)
4114/** Peripheral FTM0 base pointer */
4115#define FTM0 ((FTM_TypeDef *)FTM0_BASE)
4116/** Peripheral FTM1 base address */
4117#define FTM1_BASE (0x40039000u)
4118/** Peripheral FTM1 base pointer */
4119#define FTM1 ((FTM_TypeDef *)FTM1_BASE)
4120/** Peripheral FTM2 base address */
4121#define FTM2_BASE (0x4003A000u)
4122/** Peripheral FTM2 base pointer */
4123#define FTM2 ((FTM_TypeDef *)FTM2_BASE)
4124/** Peripheral FTM3 base address */
4125#define FTM3_BASE (0x400B9000u)
4126/** Peripheral FTM3 base pointer */
4127#define FTM3 ((FTM_TypeDef *)FTM3_BASE)
4128/** Array initializer of FTM peripheral base addresses */
4129#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
4130/** Array initializer of FTM peripheral base pointers */
4131#define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
4132/** Interrupt vectors for the FTM peripheral type */
4133#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
4134
4135/*!
4136 * @}
4137 */ /* end of group FTM_Peripheral_Access_Layer */
4138
4139
4140/* ----------------------------------------------------------------------------
4141 -- GPIO Peripheral Access Layer
4142 ---------------------------------------------------------------------------- */
4143
4144/*!
4145 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
4146 * @{
4147 */
4148
4149/** GPIO - Register Layout Typedef */
4150typedef struct {
4151 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
4152 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
4153 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
4154 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
4155 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
4156 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
4157} GPIO_TypeDef;
4158
4159/* GPIO - Peripheral instance base addresses */
4160/** Peripheral GPIOA base address */
4161#define GPIOA_BASE (0x400FF000u)
4162/** Peripheral GPIOA base pointer */
4163#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
4164/** Peripheral GPIOB base address */
4165#define GPIOB_BASE (0x400FF040u)
4166/** Peripheral GPIOB base pointer */
4167#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
4168/** Peripheral GPIOC base address */
4169#define GPIOC_BASE (0x400FF080u)
4170/** Peripheral GPIOC base pointer */
4171#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
4172/** Peripheral GPIOD base address */
4173#define GPIOD_BASE (0x400FF0C0u)
4174/** Peripheral GPIOD base pointer */
4175#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
4176/** Peripheral GPIOE base address */
4177#define GPIOE_BASE (0x400FF100u)
4178/** Peripheral GPIOE base pointer */
4179#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
4180/** Array initializer of GPIO peripheral base addresses */
4181#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
4182/** Array initializer of GPIO peripheral base pointers */
4183#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
4184
4185/*!
4186 * @}
4187 */ /* end of group GPIO_Peripheral_Access_Layer */
4188
4189
4190/* ----------------------------------------------------------------------------
4191 -- I2C Peripheral Access Layer
4192 ---------------------------------------------------------------------------- */
4193
4194/*!
4195 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
4196 * @{
4197 */
4198
4199/** I2C - Register Layout Typedef */
4200typedef struct {
4201 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
4202 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
4203 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
4204 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
4205 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
4206 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
4207 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
4208 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
4209 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
4210 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
4211 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
4212 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
4213} I2C_TypeDef;
4214
4215/* ----------------------------------------------------------------------------
4216 -- I2C Register Masks
4217 ---------------------------------------------------------------------------- */
4218
4219/*!
4220 * @addtogroup I2C_Register_Masks I2C Register Masks
4221 * @{
4222 */
4223
4224/*! @name A1 - I2C Address Register 1 */
4225#define I2C_A1_AD_MASK (0xFEU)
4226#define I2C_A1_AD_SHIFT (1U)
4227#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
4228
4229/*! @name F - I2C Frequency Divider register */
4230#define I2C_F_ICR_MASK (0x3FU)
4231#define I2C_F_ICR_SHIFT (0U)
4232#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
4233#define I2C_F_MULT_MASK (0xC0U)
4234#define I2C_F_MULT_SHIFT (6U)
4235#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
4236
4237/*! @name C1 - I2C Control Register 1 */
4238#define I2C_C1_DMAEN (0x1U)
4239#define I2C_C1_WUEN (0x2U)
4240#define I2C_C1_RSTA (0x4U)
4241#define I2C_C1_TXAK (0x8U)
4242#define I2C_C1_TX (0x10U)
4243#define I2C_C1_MST (0x20U)
4244#define I2C_C1_IICIE (0x40U)
4245#define I2C_C1_IICEN (0x80U)
4246
4247/*! @name S - I2C Status register */
4248#define I2C_S_RXAK (0x1U)
4249#define I2C_S_IICIF (0x2U)
4250#define I2C_S_SRW (0x4U)
4251#define I2C_S_RAM (0x8U)
4252#define I2C_S_ARBL (0x10U)
4253#define I2C_S_BUSY (0x20U)
4254#define I2C_S_IAAS (0x40U)
4255#define I2C_S_TCF (0x80U)
4256
4257/*! @name C2 - I2C Control Register 2 */
4258#define I2C_C2_AD_MASK (0x7U)
4259#define I2C_C2_AD_SHIFT (0U)
4260#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
4261#define I2C_C2_RMEN (0x8U)
4262#define I2C_C2_SBRC (0x10U)
4263#define I2C_C2_HDRS (0x20U)
4264#define I2C_C2_ADEXT (0x40U)
4265#define I2C_C2_GCAEN (0x80U)
4266
4267/*! @name FLT - I2C Programmable Input Glitch Filter register */
4268#define I2C_FLT_FLT_MASK (0xFU)
4269#define I2C_FLT_FLT_SHIFT (0U)
4270#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
4271#define I2C_FLT_STARTF (0x10U)
4272#define I2C_FLT_SSIE (0x20U)
4273#define I2C_FLT_STOPF (0x40U)
4274#define I2C_FLT_SHEN (0x80U)
4275
4276/*! @name RA - I2C Range Address register */
4277#define I2C_RA_RAD_MASK (0xFEU)
4278#define I2C_RA_RAD_SHIFT (1U)
4279#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
4280
4281/*! @name SMB - I2C SMBus Control and Status register */
4282#define I2C_SMB_SHTF2IE (0x1U)
4283#define I2C_SMB_SHTF2 (0x2U)
4284#define I2C_SMB_SHTF1 (0x4U)
4285#define I2C_SMB_SLTF (0x8U)
4286#define I2C_SMB_TCKSEL (0x10U)
4287#define I2C_SMB_SIICAEN (0x20U)
4288#define I2C_SMB_ALERTEN (0x40U)
4289#define I2C_SMB_FACK (0x80U)
4290
4291/*! @name A2 - I2C Address Register 2 */
4292#define I2C_A2_SAD_MASK (0xFEU)
4293#define I2C_A2_SAD_SHIFT (1U)
4294#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
4295
4296/*!
4297 * @}
4298 */ /* end of group I2C_Register_Masks */
4299
4300
4301/* I2C - Peripheral instance base addresses */
4302/** Peripheral I2C0 base address */
4303#define I2C0_BASE (0x40066000u)
4304/** Peripheral I2C0 base pointer */
4305#define I2C0 ((I2C_TypeDef *)I2C0_BASE)
4306/** Peripheral I2C1 base address */
4307#define I2C1_BASE (0x40067000u)
4308/** Peripheral I2C1 base pointer */
4309#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
4310/** Peripheral I2C2 base address */
4311#define I2C2_BASE (0x400E6000u)
4312/** Peripheral I2C2 base pointer */
4313#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
4314/** Array initializer of I2C peripheral base addresses */
4315#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE }
4316/** Array initializer of I2C peripheral base pointers */
4317#define I2C_BASE_PTRS { I2C0, I2C1, I2C2 }
4318/** Interrupt vectors for the I2C peripheral type */
4319#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
4320
4321/*!
4322 * @}
4323 */ /* end of group I2C_Peripheral_Access_Layer */
4324
4325
4326/* ----------------------------------------------------------------------------
4327 -- I2S Peripheral Access Layer
4328 ---------------------------------------------------------------------------- */
4329
4330/*!
4331 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
4332 * @{
4333 */
4334
4335/** I2S - Register Layout Typedef */
4336typedef struct {
4337 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
4338 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
4339 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
4340 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
4341 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
4342 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
4343 uint8_t RESERVED_0[8];
4344 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
4345 uint8_t RESERVED_1[24];
4346 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
4347 uint8_t RESERVED_2[24];
4348 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
4349 uint8_t RESERVED_3[28];
4350 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
4351 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
4352 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
4353 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
4354 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
4355 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
4356 uint8_t RESERVED_4[8];
4357 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
4358 uint8_t RESERVED_5[24];
4359 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
4360 uint8_t RESERVED_6[24];
4361 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
4362 uint8_t RESERVED_7[28];
4363 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
4364 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
4365} I2S_TypeDef;
4366
4367/* ----------------------------------------------------------------------------
4368 -- I2S Register Masks
4369 ---------------------------------------------------------------------------- */
4370
4371/*!
4372 * @addtogroup I2S_Register_Masks I2S Register Masks
4373 * @{
4374 */
4375
4376/*! @name TCSR - SAI Transmit Control Register */
4377#define I2S_TCSR_FRDE (0x1U)
4378#define I2S_TCSR_FWDE (0x2U)
4379#define I2S_TCSR_FRIE (0x100U)
4380#define I2S_TCSR_FWIE (0x200U)
4381#define I2S_TCSR_FEIE (0x400U)
4382#define I2S_TCSR_SEIE (0x800U)
4383#define I2S_TCSR_WSIE (0x1000U)
4384#define I2S_TCSR_FRF (0x10000U)
4385#define I2S_TCSR_FWF (0x20000U)
4386#define I2S_TCSR_FEF (0x40000U)
4387#define I2S_TCSR_SEF (0x80000U)
4388#define I2S_TCSR_WSF (0x100000U)
4389#define I2S_TCSR_SR (0x1000000U)
4390#define I2S_TCSR_FR (0x2000000U)
4391#define I2S_TCSR_BCE (0x10000000U)
4392#define I2S_TCSR_DBGE (0x20000000U)
4393#define I2S_TCSR_STOPE (0x40000000U)
4394#define I2S_TCSR_TE (0x80000000U)
4395
4396/*! @name TCR1 - SAI Transmit Configuration 1 Register */
4397#define I2S_TCR1_TFW_MASK (0x7U)
4398#define I2S_TCR1_TFW_SHIFT (0U)
4399#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
4400
4401/*! @name TCR2 - SAI Transmit Configuration 2 Register */
4402#define I2S_TCR2_DIV_MASK (0xFFU)
4403#define I2S_TCR2_DIV_SHIFT (0U)
4404#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
4405#define I2S_TCR2_BCD (0x1000000U)
4406#define I2S_TCR2_BCP (0x2000000U)
4407#define I2S_TCR2_MSEL_MASK (0xC000000U)
4408#define I2S_TCR2_MSEL_SHIFT (26U)
4409#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
4410#define I2S_TCR2_BCI (0x10000000U)
4411#define I2S_TCR2_BCS (0x20000000U)
4412#define I2S_TCR2_SYNC_MASK (0xC0000000U)
4413#define I2S_TCR2_SYNC_SHIFT (30U)
4414#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
4415
4416/*! @name TCR3 - SAI Transmit Configuration 3 Register */
4417#define I2S_TCR3_WDFL_MASK (0x1FU)
4418#define I2S_TCR3_WDFL_SHIFT (0U)
4419#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
4420#define I2S_TCR3_TCE_MASK (0x30000U)
4421#define I2S_TCR3_TCE_SHIFT (16U)
4422#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
4423
4424/*! @name TCR4 - SAI Transmit Configuration 4 Register */
4425#define I2S_TCR4_FSD (0x1U)
4426#define I2S_TCR4_FSP (0x2U)
4427#define I2S_TCR4_FSE (0x8U)
4428#define I2S_TCR4_MF (0x10U)
4429#define I2S_TCR4_SYWD_MASK (0x1F00U)
4430#define I2S_TCR4_SYWD_SHIFT (8U)
4431#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
4432#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
4433#define I2S_TCR4_FRSZ_SHIFT (16U)
4434#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
4435
4436/*! @name TCR5 - SAI Transmit Configuration 5 Register */
4437#define I2S_TCR5_FBT_MASK (0x1F00U)
4438#define I2S_TCR5_FBT_SHIFT (8U)
4439#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
4440#define I2S_TCR5_W0W_MASK (0x1F0000U)
4441#define I2S_TCR5_W0W_SHIFT (16U)
4442#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
4443#define I2S_TCR5_WNW_MASK (0x1F000000U)
4444#define I2S_TCR5_WNW_SHIFT (24U)
4445#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
4446
4447/* The count of I2S_TDR */
4448#define I2S_TDR_COUNT (2U)
4449
4450/*! @name TFR - SAI Transmit FIFO Register */
4451#define I2S_TFR_RFP_MASK (0xFU)
4452#define I2S_TFR_RFP_SHIFT (0U)
4453#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
4454#define I2S_TFR_WFP_MASK (0xF0000U)
4455#define I2S_TFR_WFP_SHIFT (16U)
4456#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
4457
4458/* The count of I2S_TFR */
4459#define I2S_TFR_COUNT (2U)
4460
4461/*! @name RCSR - SAI Receive Control Register */
4462#define I2S_RCSR_FRDE (0x1U)
4463#define I2S_RCSR_FWDE (0x2U)
4464#define I2S_RCSR_FRIE (0x100U)
4465#define I2S_RCSR_FWIE (0x200U)
4466#define I2S_RCSR_FEIE (0x400U)
4467#define I2S_RCSR_SEIE (0x800U)
4468#define I2S_RCSR_WSIE (0x1000U)
4469#define I2S_RCSR_FRF (0x10000U)
4470#define I2S_RCSR_FWF (0x20000U)
4471#define I2S_RCSR_FEF (0x40000U)
4472#define I2S_RCSR_SEF (0x80000U)
4473#define I2S_RCSR_WSF (0x100000U)
4474#define I2S_RCSR_SR (0x1000000U)
4475#define I2S_RCSR_FR (0x2000000U)
4476#define I2S_RCSR_BCE (0x10000000U)
4477#define I2S_RCSR_DBGE (0x20000000U)
4478#define I2S_RCSR_STOPE (0x40000000U)
4479#define I2S_RCSR_RE (0x80000000U)
4480
4481/*! @name RCR1 - SAI Receive Configuration 1 Register */
4482#define I2S_RCR1_RFW_MASK (0x7U)
4483#define I2S_RCR1_RFW_SHIFT (0U)
4484#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
4485
4486/*! @name RCR2 - SAI Receive Configuration 2 Register */
4487#define I2S_RCR2_DIV_MASK (0xFFU)
4488#define I2S_RCR2_DIV_SHIFT (0U)
4489#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
4490#define I2S_RCR2_BCD (0x1000000U)
4491#define I2S_RCR2_BCP (0x2000000U)
4492#define I2S_RCR2_MSEL_MASK (0xC000000U)
4493#define I2S_RCR2_MSEL_SHIFT (26U)
4494#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
4495#define I2S_RCR2_BCI (0x10000000U)
4496#define I2S_RCR2_BCS (0x20000000U)
4497#define I2S_RCR2_SYNC_MASK (0xC0000000U)
4498#define I2S_RCR2_SYNC_SHIFT (30U)
4499#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
4500
4501/*! @name RCR3 - SAI Receive Configuration 3 Register */
4502#define I2S_RCR3_WDFL_MASK (0x1FU)
4503#define I2S_RCR3_WDFL_SHIFT (0U)
4504#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
4505#define I2S_RCR3_RCE_MASK (0x30000U)
4506#define I2S_RCR3_RCE_SHIFT (16U)
4507#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
4508
4509/*! @name RCR4 - SAI Receive Configuration 4 Register */
4510#define I2S_RCR4_FSD (0x1U)
4511#define I2S_RCR4_FSP (0x2U)
4512#define I2S_RCR4_FSE (0x8U)
4513#define I2S_RCR4_MF (0x10U)
4514#define I2S_RCR4_SYWD_MASK (0x1F00U)
4515#define I2S_RCR4_SYWD_SHIFT (8U)
4516#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
4517#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
4518#define I2S_RCR4_FRSZ_SHIFT (16U)
4519#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
4520
4521/*! @name RCR5 - SAI Receive Configuration 5 Register */
4522#define I2S_RCR5_FBT_MASK (0x1F00U)
4523#define I2S_RCR5_FBT_SHIFT (8U)
4524#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
4525#define I2S_RCR5_W0W_MASK (0x1F0000U)
4526#define I2S_RCR5_W0W_SHIFT (16U)
4527#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
4528#define I2S_RCR5_WNW_MASK (0x1F000000U)
4529#define I2S_RCR5_WNW_SHIFT (24U)
4530#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
4531
4532/* The count of I2S_RDR */
4533#define I2S_RDR_COUNT (2U)
4534
4535/*! @name RFR - SAI Receive FIFO Register */
4536#define I2S_RFR_RFP_MASK (0xFU)
4537#define I2S_RFR_RFP_SHIFT (0U)
4538#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
4539#define I2S_RFR_WFP_MASK (0xF0000U)
4540#define I2S_RFR_WFP_SHIFT (16U)
4541#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
4542
4543/* The count of I2S_RFR */
4544#define I2S_RFR_COUNT (2U)
4545
4546/*! @name MCR - SAI MCLK Control Register */
4547#define I2S_MCR_MICS_MASK (0x3000000U)
4548#define I2S_MCR_MICS_SHIFT (24U)
4549#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
4550#define I2S_MCR_MOE (0x40000000U)
4551#define I2S_MCR_DUF (0x80000000U)
4552
4553/*! @name MDR - SAI MCLK Divide Register */
4554#define I2S_MDR_DIVIDE_MASK (0xFFFU)
4555#define I2S_MDR_DIVIDE_SHIFT (0U)
4556#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
4557#define I2S_MDR_FRACT_MASK (0xFF000U)
4558#define I2S_MDR_FRACT_SHIFT (12U)
4559#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
4560
4561
4562/*!
4563 * @}
4564 */ /* end of group I2S_Register_Masks */
4565
4566
4567/* I2S - Peripheral instance base addresses */
4568/** Peripheral I2S0 base address */
4569#define I2S0_BASE (0x4002F000u)
4570/** Peripheral I2S0 base pointer */
4571#define I2S0 ((I2S_TypeDef *)I2S0_BASE)
4572/** Array initializer of I2S peripheral base addresses */
4573#define I2S_BASE_ADDRS { I2S0_BASE }
4574/** Array initializer of I2S peripheral base pointers */
4575#define I2S_BASE_PTRS { I2S0 }
4576/** Interrupt vectors for the I2S peripheral type */
4577#define I2S_RX_IRQS { I2S0_Rx_IRQn }
4578#define I2S_TX_IRQS { I2S0_Tx_IRQn }
4579
4580/*!
4581 * @}
4582 */ /* end of group I2S_Peripheral_Access_Layer */
4583
4584
4585/* ----------------------------------------------------------------------------
4586 -- LLWU Peripheral Access Layer
4587 ---------------------------------------------------------------------------- */
4588
4589/*!
4590 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
4591 * @{
4592 */
4593
4594/** LLWU - Register Layout Typedef */
4595typedef struct {
4596 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
4597 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
4598 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
4599 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
4600 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
4601 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
4602 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
4603 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
4604 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
4605 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
4606 __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */
4607} LLWU_TypeDef;
4608
4609/* ----------------------------------------------------------------------------
4610 -- LLWU Register Masks
4611 ---------------------------------------------------------------------------- */
4612
4613/*!
4614 * @addtogroup LLWU_Register_Masks LLWU Register Masks
4615 * @{
4616 */
4617
4618/*! @name PE1 - LLWU Pin Enable 1 register */
4619#define LLWU_PE1_WUPE0_MASK (0x3U)
4620#define LLWU_PE1_WUPE0_SHIFT (0U)
4621#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
4622#define LLWU_PE1_WUPE1_MASK (0xCU)
4623#define LLWU_PE1_WUPE1_SHIFT (2U)
4624#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
4625#define LLWU_PE1_WUPE2_MASK (0x30U)
4626#define LLWU_PE1_WUPE2_SHIFT (4U)
4627#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
4628#define LLWU_PE1_WUPE3_MASK (0xC0U)
4629#define LLWU_PE1_WUPE3_SHIFT (6U)
4630#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
4631
4632/*! @name PE2 - LLWU Pin Enable 2 register */
4633#define LLWU_PE2_WUPE4_MASK (0x3U)
4634#define LLWU_PE2_WUPE4_SHIFT (0U)
4635#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
4636#define LLWU_PE2_WUPE5_MASK (0xCU)
4637#define LLWU_PE2_WUPE5_SHIFT (2U)
4638#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
4639#define LLWU_PE2_WUPE6_MASK (0x30U)
4640#define LLWU_PE2_WUPE6_SHIFT (4U)
4641#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
4642#define LLWU_PE2_WUPE7_MASK (0xC0U)
4643#define LLWU_PE2_WUPE7_SHIFT (6U)
4644#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
4645
4646/*! @name PE3 - LLWU Pin Enable 3 register */
4647#define LLWU_PE3_WUPE8_MASK (0x3U)
4648#define LLWU_PE3_WUPE8_SHIFT (0U)
4649#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
4650#define LLWU_PE3_WUPE9_MASK (0xCU)
4651#define LLWU_PE3_WUPE9_SHIFT (2U)
4652#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
4653#define LLWU_PE3_WUPE10_MASK (0x30U)
4654#define LLWU_PE3_WUPE10_SHIFT (4U)
4655#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
4656#define LLWU_PE3_WUPE11_MASK (0xC0U)
4657#define LLWU_PE3_WUPE11_SHIFT (6U)
4658#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
4659
4660/*! @name PE4 - LLWU Pin Enable 4 register */
4661#define LLWU_PE4_WUPE12_MASK (0x3U)
4662#define LLWU_PE4_WUPE12_SHIFT (0U)
4663#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
4664#define LLWU_PE4_WUPE13_MASK (0xCU)
4665#define LLWU_PE4_WUPE13_SHIFT (2U)
4666#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
4667#define LLWU_PE4_WUPE14_MASK (0x30U)
4668#define LLWU_PE4_WUPE14_SHIFT (4U)
4669#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
4670#define LLWU_PE4_WUPE15_MASK (0xC0U)
4671#define LLWU_PE4_WUPE15_SHIFT (6U)
4672#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
4673
4674/*! @name ME - LLWU Module Enable register */
4675#define LLWU_ME_WUME0 (0x1U)
4676#define LLWU_ME_WUME1 (0x2U)
4677#define LLWU_ME_WUME2 (0x4U)
4678#define LLWU_ME_WUME3 (0x8U)
4679#define LLWU_ME_WUME4 (0x10U)
4680#define LLWU_ME_WUME5 (0x20U)
4681#define LLWU_ME_WUME6 (0x40U)
4682#define LLWU_ME_WUME7 (0x80U)
4683
4684/*! @name F1 - LLWU Flag 1 register */
4685#define LLWU_F1_WUF0 (0x1U)
4686#define LLWU_F1_WUF1 (0x2U)
4687#define LLWU_F1_WUF2 (0x4U)
4688#define LLWU_F1_WUF3 (0x8U)
4689#define LLWU_F1_WUF4 (0x10U)
4690#define LLWU_F1_WUF5 (0x20U)
4691#define LLWU_F1_WUF6 (0x40U)
4692#define LLWU_F1_WUF7 (0x80U)
4693
4694/*! @name F2 - LLWU Flag 2 register */
4695#define LLWU_F2_WUF8 (0x1U)
4696#define LLWU_F2_WUF9 (0x2U)
4697#define LLWU_F2_WUF10 (0x4U)
4698#define LLWU_F2_WUF11 (0x8U)
4699#define LLWU_F2_WUF12 (0x10U)
4700#define LLWU_F2_WUF13 (0x20U)
4701#define LLWU_F2_WUF14 (0x40U)
4702#define LLWU_F2_WUF15 (0x80U)
4703
4704/*! @name F3 - LLWU Flag 3 register */
4705#define LLWU_F3_MWUF0 (0x1U)
4706#define LLWU_F3_MWUF1 (0x2U)
4707#define LLWU_F3_MWUF2 (0x4U)
4708#define LLWU_F3_MWUF3 (0x8U)
4709#define LLWU_F3_MWUF4 (0x10U)
4710#define LLWU_F3_MWUF5 (0x20U)
4711#define LLWU_F3_MWUF6 (0x40U)
4712#define LLWU_F3_MWUF7 (0x80U)
4713
4714/*! @name FILT1 - LLWU Pin Filter 1 register */
4715#define LLWU_FILT1_FILTSEL_MASK (0xFU)
4716#define LLWU_FILT1_FILTSEL_SHIFT (0U)
4717#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
4718#define LLWU_FILT1_FILTE_MASK (0x60U)
4719#define LLWU_FILT1_FILTE_SHIFT (5U)
4720#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
4721#define LLWU_FILT1_FILTF (0x80U)
4722
4723/*! @name FILT2 - LLWU Pin Filter 2 register */
4724#define LLWU_FILT2_FILTSEL_MASK (0xFU)
4725#define LLWU_FILT2_FILTSEL_SHIFT (0U)
4726#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
4727#define LLWU_FILT2_FILTE_MASK (0x60U)
4728#define LLWU_FILT2_FILTE_SHIFT (5U)
4729#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
4730#define LLWU_FILT2_FILTF (0x80U)
4731
4732/*! @name RST - LLWU Reset Enable register */
4733#define LLWU_RST_RSTFILT (0x1U)
4734#define LLWU_RST_LLRSTE (0x2U)
4735
4736
4737/*!
4738 * @}
4739 */ /* end of group LLWU_Register_Masks */
4740
4741
4742/* LLWU - Peripheral instance base addresses */
4743/** Peripheral LLWU base address */
4744#define LLWU_BASE (0x4007C000u)
4745/** Peripheral LLWU base pointer */
4746#define LLWU ((LLWU_TypeDef *)LLWU_BASE)
4747/** Array initializer of LLWU peripheral base addresses */
4748#define LLWU_BASE_ADDRS { LLWU_BASE }
4749/** Array initializer of LLWU peripheral base pointers */
4750#define LLWU_BASE_PTRS { LLWU }
4751/** Interrupt vectors for the LLWU peripheral type */
4752#define LLWU_IRQS { LLWU_IRQn }
4753
4754/*!
4755 * @}
4756 */ /* end of group LLWU_Peripheral_Access_Layer */
4757
4758
4759/* ----------------------------------------------------------------------------
4760 -- LPTMR Peripheral Access Layer
4761 ---------------------------------------------------------------------------- */
4762
4763/*!
4764 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
4765 * @{
4766 */
4767
4768/** LPTMR - Register Layout Typedef */
4769typedef struct {
4770 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
4771 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
4772 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
4773 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
4774} LPTMR_TypeDef;
4775
4776/* ----------------------------------------------------------------------------
4777 -- LPTMR Register Masks
4778 ---------------------------------------------------------------------------- */
4779
4780/*!
4781 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
4782 * @{
4783 */
4784
4785/*! @name CSR - Low Power Timer Control Status Register */
4786#define LPTMR_CSR_TEN (0x1U)
4787#define LPTMR_CSR_TMS (0x2U)
4788#define LPTMR_CSR_TFC (0x4U)
4789#define LPTMR_CSR_TPP (0x8U)
4790#define LPTMR_CSR_TPS_MASK (0x30U)
4791#define LPTMR_CSR_TPS_SHIFT (4U)
4792#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
4793#define LPTMR_CSR_TIE (0x40U)
4794#define LPTMR_CSR_TCF (0x80U)
4795
4796/*! @name PSR - Low Power Timer Prescale Register */
4797#define LPTMR_PSR_PCS_MASK (0x3U)
4798#define LPTMR_PSR_PCS_SHIFT (0U)
4799#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
4800#define LPTMR_PSR_PBYP (0x4U)
4801#define LPTMR_PSR_PRESCALE_MASK (0x78U)
4802#define LPTMR_PSR_PRESCALE_SHIFT (3U)
4803#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
4804
4805/*! @name CMR - Low Power Timer Compare Register */
4806#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
4807#define LPTMR_CMR_COMPARE_SHIFT (0U)
4808#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
4809
4810/*! @name CNR - Low Power Timer Counter Register */
4811#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
4812#define LPTMR_CNR_COUNTER_SHIFT (0U)
4813#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
4814
4815
4816/*!
4817 * @}
4818 */ /* end of group LPTMR_Register_Masks */
4819
4820
4821/* LPTMR - Peripheral instance base addresses */
4822/** Peripheral LPTMR0 base address */
4823#define LPTMR0_BASE (0x40040000u)
4824/** Peripheral LPTMR0 base pointer */
4825#define LPTMR0 ((LPTMR_TypeDef *)LPTMR0_BASE)
4826/** Array initializer of LPTMR peripheral base addresses */
4827#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
4828/** Array initializer of LPTMR peripheral base pointers */
4829#define LPTMR_BASE_PTRS { LPTMR0 }
4830/** Interrupt vectors for the LPTMR peripheral type */
4831#define LPTMR_IRQS { LPTMR0_IRQn }
4832
4833/*!
4834 * @}
4835 */ /* end of group LPTMR_Peripheral_Access_Layer */
4836
4837
4838/* ----------------------------------------------------------------------------
4839 -- MCG Peripheral Access Layer
4840 ---------------------------------------------------------------------------- */
4841
4842/*!
4843 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
4844 * @{
4845 */
4846
4847/** MCG - Register Layout Typedef */
4848typedef struct {
4849 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
4850 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
4851 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
4852 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
4853 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
4854 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
4855 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
4856 uint8_t RESERVED_0[1];
4857 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
4858 uint8_t RESERVED_1[1];
4859 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
4860 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
4861 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
4862 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
4863} MCG_TypeDef;
4864
4865/* ----------------------------------------------------------------------------
4866 -- MCG Register Masks
4867 ---------------------------------------------------------------------------- */
4868
4869/*!
4870 * @addtogroup MCG_Register_Masks MCG Register Masks
4871 * @{
4872 */
4873
4874/*! @name C1 - MCG Control 1 Register */
4875#define MCG_C1_IREFSTEN (0x1U)
4876#define MCG_C1_IRCLKEN (0x2U)
4877#define MCG_C1_IREFS (0x4U)
4878#define MCG_C1_FRDIV_MASK (0x38U)
4879#define MCG_C1_FRDIV_SHIFT (3U)
4880#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
4881#define MCG_C1_CLKS_MASK (0xC0U)
4882#define MCG_C1_CLKS_SHIFT (6U)
4883#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
4884
4885/*! @name C2 - MCG Control 2 Register */
4886#define MCG_C2_IRCS (0x1U)
4887#define MCG_C2_LP (0x2U)
4888#define MCG_C2_EREFS (0x4U)
4889#define MCG_C2_EREFS0 MCG_C2_EREFS
4890#define MCG_C2_HGO (0x8U)
4891#define MCG_C2_RANGE_MASK (0x30U)
4892#define MCG_C2_RANGE_SHIFT (4U)
4893#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
4894#define MCG_C2_FCFTRIM (0x40U)
4895#define MCG_C2_LOCRE0 (0x80U)
4896
4897/*! @name C3 - MCG Control 3 Register */
4898#define MCG_C3_SCTRIM_MASK (0xFFU)
4899#define MCG_C3_SCTRIM_SHIFT (0U)
4900#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
4901
4902/*! @name C4 - MCG Control 4 Register */
4903#define MCG_C4_SCFTRIM (0x1U)
4904#define MCG_C4_FCTRIM_MASK (0x1EU)
4905#define MCG_C4_FCTRIM_SHIFT (1U)
4906#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
4907#define MCG_C4_DRST_DRS_MASK (0x60U)
4908#define MCG_C4_DRST_DRS_SHIFT (5U)
4909#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
4910#define MCG_C4_DMX32 (0x80U)
4911
4912/*! @name C5 - MCG Control 5 Register */
4913#define MCG_C5_PRDIV0_MASK (0x1FU)
4914#define MCG_C5_PRDIV0_SHIFT (0U)
4915#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
4916#define MCG_C5_PLLSTEN0 (0x20U)
4917#define MCG_C5_PLLCLKEN0 (0x40U)
4918
4919/*! @name C6 - MCG Control 6 Register */
4920#define MCG_C6_VDIV0_MASK (0x1FU)
4921#define MCG_C6_VDIV0_SHIFT (0U)
4922#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
4923#define MCG_C6_CME0 (0x20U)
4924#define MCG_C6_PLLS (0x40U)
4925#define MCG_C6_LOLIE0 (0x80U)
4926
4927/*! @name S - MCG Status Register */
4928#define MCG_S_IRCST (0x1U)
4929#define MCG_S_OSCINIT0 (0x2U)
4930#define MCG_S_CLKST_MASK (0xCU)
4931#define MCG_S_CLKST_SHIFT (2U)
4932#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
4933#define MCG_S_CLKST_FLL MCG_S_CLKST(0)
4934#define MCG_S_CLKST_INT MCG_S_CLKST(1)
4935#define MCG_S_CLKST_EXT MCG_S_CLKST(2)
4936#define MCG_S_CLKST_PLL MCG_S_CLKST(3)
4937#define MCG_S_IREFST (0x10U)
4938#define MCG_S_PLLST (0x20U)
4939#define MCG_S_LOCK0 (0x40U)
4940#define MCG_S_LOLS0 (0x80U)
4941
4942/*! @name SC - MCG Status and Control Register */
4943#define MCG_SC_LOCS0 (0x1U)
4944#define MCG_SC_FCRDIV_MASK (0xEU)
4945#define MCG_SC_FCRDIV_SHIFT (1U)
4946#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
4947#define MCG_SC_FLTPRSRV (0x10U)
4948#define MCG_SC_ATMF (0x20U)
4949#define MCG_SC_ATMS (0x40U)
4950#define MCG_SC_ATME (0x80U)
4951
4952/*! @name ATCVH - MCG Auto Trim Compare Value High Register */
4953#define MCG_ATCVH_ATCVH_MASK (0xFFU)
4954#define MCG_ATCVH_ATCVH_SHIFT (0U)
4955#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
4956
4957/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
4958#define MCG_ATCVL_ATCVL_MASK (0xFFU)
4959#define MCG_ATCVL_ATCVL_SHIFT (0U)
4960#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
4961
4962/*! @name C7 - MCG Control 7 Register */
4963#define MCG_C7_OSCSEL_MASK (0x3U)
4964#define MCG_C7_OSCSEL_SHIFT (0U)
4965#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
4966
4967/*! @name C8 - MCG Control 8 Register */
4968#define MCG_C8_LOCS1 (0x1U)
4969#define MCG_C8_CME1 (0x20U)
4970#define MCG_C8_LOLRE (0x40U)
4971#define MCG_C8_LOCRE1 (0x80U)
4972
4973
4974/*!
4975 * @}
4976 */ /* end of group MCG_Register_Masks */
4977
4978
4979/* MCG - Peripheral instance base addresses */
4980/** Peripheral MCG base address */
4981#define MCG_BASE (0x40064000u)
4982/** Peripheral MCG base pointer */
4983#define MCG ((MCG_TypeDef *)MCG_BASE)
4984/** Array initializer of MCG peripheral base addresses */
4985#define MCG_BASE_ADDRS { MCG_BASE }
4986/** Array initializer of MCG peripheral base pointers */
4987#define MCG_BASE_PTRS { MCG }
4988
4989/*!
4990 * @}
4991 */ /* end of group MCG_Peripheral_Access_Layer */
4992
4993
4994/* ----------------------------------------------------------------------------
4995 -- MCM Peripheral Access Layer
4996 ---------------------------------------------------------------------------- */
4997
4998/*!
4999 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
5000 * @{
5001 */
5002
5003/** MCM - Register Layout Typedef */
5004typedef struct {
5005 uint8_t RESERVED_0[8];
5006 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
5007 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
5008 __IO uint32_t CR; /**< Control Register, offset: 0xC */
5009 __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */
5010 __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
5011 __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
5012 __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
5013 uint8_t RESERVED_1[16];
5014 __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
5015} MCM_TypeDef;
5016
5017/* ----------------------------------------------------------------------------
5018 -- MCM Register Masks
5019 ---------------------------------------------------------------------------- */
5020
5021/*!
5022 * @addtogroup MCM_Register_Masks MCM Register Masks
5023 * @{
5024 */
5025
5026/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
5027#define MCM_PLASC_ASC_MASK (0xFFU)
5028#define MCM_PLASC_ASC_SHIFT (0U)
5029#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
5030
5031/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
5032#define MCM_PLAMC_AMC_MASK (0xFFU)
5033#define MCM_PLAMC_AMC_SHIFT (0U)
5034#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
5035
5036/*! @name CR - Control Register */
5037#define MCM_CR_SRAMUAP_MASK (0x3000000U)
5038#define MCM_CR_SRAMUAP_SHIFT (24U)
5039#define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
5040#define MCM_CR_SRAMUWP (0x4000000U)
5041#define MCM_CR_SRAMLAP_MASK (0x30000000U)
5042#define MCM_CR_SRAMLAP_SHIFT (28U)
5043#define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
5044#define MCM_CR_SRAMLWP (0x40000000U)
5045
5046/*! @name ISCR - Interrupt Status Register */
5047#define MCM_ISCR_IRQ (0x2U)
5048#define MCM_ISCR_NMI (0x4U)
5049#define MCM_ISCR_DHREQ (0x8U)
5050#define MCM_ISCR_FIOC (0x100U)
5051#define MCM_ISCR_FDZC (0x200U)
5052#define MCM_ISCR_FOFC (0x400U)
5053#define MCM_ISCR_FUFC (0x800U)
5054#define MCM_ISCR_FIXC (0x1000U)
5055#define MCM_ISCR_FIDC (0x8000U)
5056#define MCM_ISCR_FIOCE (0x1000000U)
5057#define MCM_ISCR_FDZCE (0x2000000U)
5058#define MCM_ISCR_FOFCE (0x4000000U)
5059#define MCM_ISCR_FUFCE (0x8000000U)
5060#define MCM_ISCR_FIXCE (0x10000000U)
5061#define MCM_ISCR_FIDCE (0x80000000U)
5062
5063/*! @name ETBCC - ETB Counter Control register */
5064#define MCM_ETBCC_CNTEN (0x1U)
5065#define MCM_ETBCC_RSPT_MASK (0x6U)
5066#define MCM_ETBCC_RSPT_SHIFT (1U)
5067#define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
5068#define MCM_ETBCC_RLRQ (0x8U)
5069#define MCM_ETBCC_ETDIS (0x10U)
5070#define MCM_ETBCC_ITDIS (0x20U)
5071
5072/*! @name ETBRL - ETB Reload register */
5073#define MCM_ETBRL_RELOAD_MASK (0x7FFU)
5074#define MCM_ETBRL_RELOAD_SHIFT (0U)
5075#define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
5076
5077/*! @name ETBCNT - ETB Counter Value register */
5078#define MCM_ETBCNT_COUNTER_MASK (0x7FFU)
5079#define MCM_ETBCNT_COUNTER_SHIFT (0U)
5080#define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
5081
5082/*! @name PID - Process ID register */
5083#define MCM_PID_PID_MASK (0xFFU)
5084#define MCM_PID_PID_SHIFT (0U)
5085#define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
5086
5087
5088/*!
5089 * @}
5090 */ /* end of group MCM_Register_Masks */
5091
5092
5093/* MCM - Peripheral instance base addresses */
5094/** Peripheral MCM base address */
5095#define MCM_BASE (0xE0080000u)
5096/** Peripheral MCM base pointer */
5097#define MCM ((MCM_TypeDef *)MCM_BASE)
5098/** Array initializer of MCM peripheral base addresses */
5099#define MCM_BASE_ADDRS { MCM_BASE }
5100/** Array initializer of MCM peripheral base pointers */
5101#define MCM_BASE_PTRS { MCM }
5102/** Interrupt vectors for the MCM peripheral type */
5103#define MCM_IRQS { MCM_IRQn }
5104
5105/*!
5106 * @}
5107 */ /* end of group MCM_Peripheral_Access_Layer */
5108
5109
5110/* ----------------------------------------------------------------------------
5111 -- MPU Peripheral Access Layer
5112 ---------------------------------------------------------------------------- */
5113
5114/*!
5115 * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
5116 * @{
5117 */
5118
5119/** MPU - Register Layout Typedef */
5120typedef struct {
5121 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
5122 uint8_t RESERVED_0[12];
5123 struct { /* offset: 0x10, array step: 0x8 */
5124 __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
5125 __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
5126 } SP[5];
5127 uint8_t RESERVED_1[968];
5128 __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
5129 uint8_t RESERVED_2[832];
5130 __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
5131} MPU_TypeDef;
5132
5133/* ----------------------------------------------------------------------------
5134 -- MPU Register Masks
5135 ---------------------------------------------------------------------------- */
5136
5137/*!
5138 * @addtogroup MPU_Register_Masks MPU Register Masks
5139 * @{
5140 */
5141
5142/*! @name CESR - Control/Error Status Register */
5143#define MPU_CESR_VLD (0x1U)
5144#define MPU_CESR_NRGD_MASK (0xF00U)
5145#define MPU_CESR_NRGD_SHIFT (8U)
5146#define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NRGD_SHIFT)) & MPU_CESR_NRGD_MASK)
5147#define MPU_CESR_NSP_MASK (0xF000U)
5148#define MPU_CESR_NSP_SHIFT (12U)
5149#define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NSP_SHIFT)) & MPU_CESR_NSP_MASK)
5150#define MPU_CESR_HRL_MASK (0xF0000U)
5151#define MPU_CESR_HRL_SHIFT (16U)
5152#define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_HRL_SHIFT)) & MPU_CESR_HRL_MASK)
5153#define MPU_CESR_SPERR_MASK (0xF8000000U)
5154#define MPU_CESR_SPERR_SHIFT (27U)
5155#define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR_SHIFT)) & MPU_CESR_SPERR_MASK)
5156
5157/* The count of MPU_EAR */
5158#define MPU_EAR_COUNT (5U)
5159
5160/*! @name EDR - Error Detail Register, slave port n */
5161#define MPU_EDR_ERW (0x1U)
5162#define MPU_EDR_EATTR_MASK (0xEU)
5163#define MPU_EDR_EATTR_SHIFT (1U)
5164#define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EATTR_SHIFT)) & MPU_EDR_EATTR_MASK)
5165#define MPU_EDR_EMN_MASK (0xF0U)
5166#define MPU_EDR_EMN_SHIFT (4U)
5167#define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EMN_SHIFT)) & MPU_EDR_EMN_MASK)
5168#define MPU_EDR_EPID_MASK (0xFF00U)
5169#define MPU_EDR_EPID_SHIFT (8U)
5170#define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EPID_SHIFT)) & MPU_EDR_EPID_MASK)
5171#define MPU_EDR_EACD_MASK (0xFFFF0000U)
5172#define MPU_EDR_EACD_SHIFT (16U)
5173#define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EACD_SHIFT)) & MPU_EDR_EACD_MASK)
5174
5175/* The count of MPU_EDR */
5176#define MPU_EDR_COUNT (5U)
5177
5178/*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
5179#define MPU_WORD_VLD (0x1U)
5180#define MPU_WORD_M0UM_MASK (0x7U)
5181#define MPU_WORD_M0UM_SHIFT (0U)
5182#define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0UM_SHIFT)) & MPU_WORD_M0UM_MASK)
5183#define MPU_WORD_M0SM_MASK (0x18U)
5184#define MPU_WORD_M0SM_SHIFT (3U)
5185#define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0SM_SHIFT)) & MPU_WORD_M0SM_MASK)
5186#define MPU_WORD_M0PE (0x20U)
5187#define MPU_WORD_ENDADDR_MASK (0xFFFFFFE0U)
5188#define MPU_WORD_ENDADDR_SHIFT (5U)
5189#define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_ENDADDR_SHIFT)) & MPU_WORD_ENDADDR_MASK)
5190#define MPU_WORD_SRTADDR_MASK (0xFFFFFFE0U)
5191#define MPU_WORD_SRTADDR_SHIFT (5U)
5192#define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_SRTADDR_SHIFT)) & MPU_WORD_SRTADDR_MASK)
5193#define MPU_WORD_M1UM_MASK (0x1C0U)
5194#define MPU_WORD_M1UM_SHIFT (6U)
5195#define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1UM_SHIFT)) & MPU_WORD_M1UM_MASK)
5196#define MPU_WORD_M1SM_MASK (0x600U)
5197#define MPU_WORD_M1SM_SHIFT (9U)
5198#define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1SM_SHIFT)) & MPU_WORD_M1SM_MASK)
5199#define MPU_WORD_M1PE (0x800U)
5200#define MPU_WORD_M2UM_MASK (0x7000U)
5201#define MPU_WORD_M2UM_SHIFT (12U)
5202#define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2UM_SHIFT)) & MPU_WORD_M2UM_MASK)
5203#define MPU_WORD_M2SM_MASK (0x18000U)
5204#define MPU_WORD_M2SM_SHIFT (15U)
5205#define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2SM_SHIFT)) & MPU_WORD_M2SM_MASK)
5206#define MPU_WORD_PIDMASK_MASK (0xFF0000U)
5207#define MPU_WORD_PIDMASK_SHIFT (16U)
5208#define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PIDMASK_SHIFT)) & MPU_WORD_PIDMASK_MASK)
5209#define MPU_WORD_M2PE (0x20000U)
5210#define MPU_WORD_M3UM_MASK (0x1C0000U)
5211#define MPU_WORD_M3UM_SHIFT (18U)
5212#define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3UM_SHIFT)) & MPU_WORD_M3UM_MASK)
5213#define MPU_WORD_M3SM_MASK (0x600000U)
5214#define MPU_WORD_M3SM_SHIFT (21U)
5215#define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3SM_SHIFT)) & MPU_WORD_M3SM_MASK)
5216#define MPU_WORD_M3PE (0x800000U)
5217#define MPU_WORD_PID_MASK (0xFF000000U)
5218#define MPU_WORD_PID_SHIFT (24U)
5219#define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PID_SHIFT)) & MPU_WORD_PID_MASK)
5220#define MPU_WORD_M4WE (0x1000000U)
5221#define MPU_WORD_M4RE (0x2000000U)
5222#define MPU_WORD_M5WE (0x4000000U)
5223#define MPU_WORD_M5RE (0x8000000U)
5224#define MPU_WORD_M6WE (0x10000000U)
5225#define MPU_WORD_M6RE (0x20000000U)
5226#define MPU_WORD_M7WE (0x40000000U)
5227#define MPU_WORD_M7RE (0x80000000U)
5228
5229/* The count of MPU_WORD */
5230#define MPU_WORD_COUNT (12U)
5231
5232/* The count of MPU_WORD */
5233#define MPU_WORD_COUNT2 (4U)
5234
5235/*! @name RGDAAC - Region Descriptor Alternate Access Control n */
5236#define MPU_RGDAAC_M0UM_MASK (0x7U)
5237#define MPU_RGDAAC_M0UM_SHIFT (0U)
5238#define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0UM_SHIFT)) & MPU_RGDAAC_M0UM_MASK)
5239#define MPU_RGDAAC_M0SM_MASK (0x18U)
5240#define MPU_RGDAAC_M0SM_SHIFT (3U)
5241#define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0SM_SHIFT)) & MPU_RGDAAC_M0SM_MASK)
5242#define MPU_RGDAAC_M0PE (0x20U)
5243#define MPU_RGDAAC_M1UM_MASK (0x1C0U)
5244#define MPU_RGDAAC_M1UM_SHIFT (6U)
5245#define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1UM_SHIFT)) & MPU_RGDAAC_M1UM_MASK)
5246#define MPU_RGDAAC_M1SM_MASK (0x600U)
5247#define MPU_RGDAAC_M1SM_SHIFT (9U)
5248#define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1SM_SHIFT)) & MPU_RGDAAC_M1SM_MASK)
5249#define MPU_RGDAAC_M1PE (0x800U)
5250#define MPU_RGDAAC_M2UM_MASK (0x7000U)
5251#define MPU_RGDAAC_M2UM_SHIFT (12U)
5252#define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2UM_SHIFT)) & MPU_RGDAAC_M2UM_MASK)
5253#define MPU_RGDAAC_M2SM_MASK (0x18000U)
5254#define MPU_RGDAAC_M2SM_SHIFT (15U)
5255#define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2SM_SHIFT)) & MPU_RGDAAC_M2SM_MASK)
5256#define MPU_RGDAAC_M2PE (0x20000U)
5257#define MPU_RGDAAC_M3UM_MASK (0x1C0000U)
5258#define MPU_RGDAAC_M3UM_SHIFT (18U)
5259#define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3UM_SHIFT)) & MPU_RGDAAC_M3UM_MASK)
5260#define MPU_RGDAAC_M3SM_MASK (0x600000U)
5261#define MPU_RGDAAC_M3SM_SHIFT (21U)
5262#define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3SM_SHIFT)) & MPU_RGDAAC_M3SM_MASK)
5263#define MPU_RGDAAC_M3PE (0x800000U)
5264#define MPU_RGDAAC_M4WE (0x1000000U)
5265#define MPU_RGDAAC_M4RE (0x2000000U)
5266#define MPU_RGDAAC_M5WE (0x4000000U)
5267#define MPU_RGDAAC_M5RE (0x8000000U)
5268#define MPU_RGDAAC_M6WE (0x10000000U)
5269#define MPU_RGDAAC_M6RE (0x20000000U)
5270#define MPU_RGDAAC_M7WE (0x40000000U)
5271#define MPU_RGDAAC_M7RE (0x80000000U)
5272
5273/* The count of MPU_RGDAAC */
5274#define MPU_RGDAAC_COUNT (12U)
5275
5276
5277/*!
5278 * @}
5279 */ /* end of group MPU_Register_Masks */
5280
5281
5282/* MPU - Peripheral instance base addresses */
5283/** Peripheral MPU base address */
5284#define MPU_BASE (0x4000D000u)
5285/** Peripheral MPU base pointer */
5286#define MPU ((MPU_TypeDef *)MPU_BASE)
5287/** Array initializer of MPU peripheral base addresses */
5288#define MPU_BASE_ADDRS { MPU_BASE }
5289/** Array initializer of MPU peripheral base pointers */
5290#define MPU_BASE_PTRS { MPU }
5291
5292/*!
5293 * @}
5294 */ /* end of group MPU_Peripheral_Access_Layer */
5295
5296
5297/* ----------------------------------------------------------------------------
5298 -- NV Peripheral Access Layer
5299 ---------------------------------------------------------------------------- */
5300
5301/*!
5302 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
5303 * @{
5304 */
5305
5306/** NV - Register Layout Typedef */
5307typedef struct {
5308 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
5309 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
5310 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
5311 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
5312 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
5313 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
5314 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
5315 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
5316 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
5317 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
5318 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
5319 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
5320 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
5321 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
5322 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
5323 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
5324} NV_TypeDef;
5325
5326/* ----------------------------------------------------------------------------
5327 -- NV Register Masks
5328 ---------------------------------------------------------------------------- */
5329
5330/*!
5331 * @addtogroup NV_Register_Masks NV Register Masks
5332 * @{
5333 */
5334
5335/*! @name FSEC - Non-volatile Flash Security Register */
5336#define NV_FSEC_SEC_MASK (0x3U)
5337#define NV_FSEC_SEC_SHIFT (0U)
5338#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
5339#define NV_FSEC_FSLACC_MASK (0xCU)
5340#define NV_FSEC_FSLACC_SHIFT (2U)
5341#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
5342#define NV_FSEC_MEEN_MASK (0x30U)
5343#define NV_FSEC_MEEN_SHIFT (4U)
5344#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
5345#define NV_FSEC_KEYEN_MASK (0xC0U)
5346#define NV_FSEC_KEYEN_SHIFT (6U)
5347#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
5348
5349/*! @name FOPT - Non-volatile Flash Option Register */
5350#define NV_FOPT_LPBOOT (0x1U)
5351#define NV_FOPT_EZPORT_DIS (0x2U)
5352
5353/*!
5354 * @}
5355 */ /* end of group NV_Register_Masks */
5356
5357
5358/* NV - Peripheral instance base addresses */
5359/** Peripheral FTFE_FlashConfig base address */
5360#define FTFE_FlashConfig_BASE (0x400u)
5361/** Peripheral FTFE_FlashConfig base pointer */
5362#define FTFE_FlashConfig ((NV_TypeDef *)FTFE_FlashConfig_BASE)
5363/** Array initializer of NV peripheral base addresses */
5364#define NV_BASE_ADDRS { FTFE_FlashConfig_BASE }
5365/** Array initializer of NV peripheral base pointers */
5366#define NV_BASE_PTRS { FTFE_FlashConfig }
5367
5368/*!
5369 * @}
5370 */ /* end of group NV_Peripheral_Access_Layer */
5371
5372
5373/* ----------------------------------------------------------------------------
5374 -- OSC Peripheral Access Layer
5375 ---------------------------------------------------------------------------- */
5376
5377/*!
5378 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
5379 * @{
5380 */
5381
5382/** OSC - Register Layout Typedef */
5383typedef struct {
5384 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
5385} OSC_TypeDef;
5386
5387/* ----------------------------------------------------------------------------
5388 -- OSC Register Masks
5389 ---------------------------------------------------------------------------- */
5390
5391/*!
5392 * @addtogroup OSC_Register_Masks OSC Register Masks
5393 * @{
5394 */
5395
5396/*! @name CR - OSC Control Register */
5397#define OSC_CR_SC16P (0x1U)
5398#define OSC_CR_SC8P (0x2U)
5399#define OSC_CR_SC4P (0x4U)
5400#define OSC_CR_SC2P (0x8U)
5401#define OSC_CR_EREFSTEN (0x20U)
5402#define OSC_CR_ERCLKEN (0x80U)
5403
5404
5405/*!
5406 * @}
5407 */ /* end of group OSC_Register_Masks */
5408
5409
5410/* OSC - Peripheral instance base addresses */
5411/** Peripheral OSC base address */
5412#define OSC_BASE (0x40065000u)
5413#define OSC0_BASE OSC_BASE
5414/** Peripheral OSC base pointer */
5415#define OSC ((OSC_TypeDef *)OSC_BASE)
5416#define OSC0 OSC
5417/** Array initializer of OSC peripheral base addresses */
5418#define OSC_BASE_ADDRS { OSC_BASE }
5419/** Array initializer of OSC peripheral base pointers */
5420#define OSC_BASE_PTRS { OSC }
5421
5422/*!
5423 * @}
5424 */ /* end of group OSC_Peripheral_Access_Layer */
5425
5426
5427/* ----------------------------------------------------------------------------
5428 -- PDB Peripheral Access Layer
5429 ---------------------------------------------------------------------------- */
5430
5431/*!
5432 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
5433 * @{
5434 */
5435
5436/** PDB - Register Layout Typedef */
5437typedef struct {
5438 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
5439 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
5440 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
5441 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
5442 struct { /* offset: 0x10, array step: 0x28 */
5443 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
5444 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
5445 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
5446 uint8_t RESERVED_0[24];
5447 } CH[2];
5448 uint8_t RESERVED_0[240];
5449 struct { /* offset: 0x150, array step: 0x8 */
5450 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
5451 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
5452 } DAC[2];
5453 uint8_t RESERVED_1[48];
5454 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
5455 __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
5456} PDB_TypeDef;
5457
5458/* ----------------------------------------------------------------------------
5459 -- PDB Register Masks
5460 ---------------------------------------------------------------------------- */
5461
5462/*!
5463 * @addtogroup PDB_Register_Masks PDB Register Masks
5464 * @{
5465 */
5466
5467/*! @name SC - Status and Control register */
5468#define PDB_SC_LDOK (0x1U)
5469#define PDB_SC_CONT (0x2U)
5470#define PDB_SC_MULT_MASK (0xCU)
5471#define PDB_SC_MULT_SHIFT (2U)
5472#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
5473#define PDB_SC_PDBIE (0x20U)
5474#define PDB_SC_PDBIF (0x40U)
5475#define PDB_SC_PDBEN (0x80U)
5476#define PDB_SC_TRGSEL_MASK (0xF00U)
5477#define PDB_SC_TRGSEL_SHIFT (8U)
5478#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
5479#define PDB_SC_PRESCALER_MASK (0x7000U)
5480#define PDB_SC_PRESCALER_SHIFT (12U)
5481#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
5482#define PDB_SC_DMAEN (0x8000U)
5483#define PDB_SC_SWTRIG (0x10000U)
5484#define PDB_SC_PDBEIE (0x20000U)
5485#define PDB_SC_LDMOD_MASK (0xC0000U)
5486#define PDB_SC_LDMOD_SHIFT (18U)
5487#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
5488
5489/*! @name MOD - Modulus register */
5490#define PDB_MOD_MOD_MASK (0xFFFFU)
5491#define PDB_MOD_MOD_SHIFT (0U)
5492#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
5493
5494/*! @name CNT - Counter register */
5495#define PDB_CNT_CNT_MASK (0xFFFFU)
5496#define PDB_CNT_CNT_SHIFT (0U)
5497#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
5498
5499/*! @name IDLY - Interrupt Delay register */
5500#define PDB_IDLY_IDLY_MASK (0xFFFFU)
5501#define PDB_IDLY_IDLY_SHIFT (0U)
5502#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
5503
5504/*! @name C1 - Channel n Control register 1 */
5505#define PDB_C1_EN_MASK (0xFFU)
5506#define PDB_C1_EN_SHIFT (0U)
5507#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
5508#define PDB_C1_TOS_MASK (0xFF00U)
5509#define PDB_C1_TOS_SHIFT (8U)
5510#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
5511#define PDB_C1_BB_MASK (0xFF0000U)
5512#define PDB_C1_BB_SHIFT (16U)
5513#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
5514
5515/* The count of PDB_C1 */
5516#define PDB_C1_COUNT (2U)
5517
5518/*! @name S - Channel n Status register */
5519#define PDB_S_ERR_MASK (0xFFU)
5520#define PDB_S_ERR_SHIFT (0U)
5521#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
5522#define PDB_S_CF_MASK (0xFF0000U)
5523#define PDB_S_CF_SHIFT (16U)
5524#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
5525
5526/* The count of PDB_S */
5527#define PDB_S_COUNT (2U)
5528
5529/*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
5530#define PDB_DLY_DLY_MASK (0xFFFFU)
5531#define PDB_DLY_DLY_SHIFT (0U)
5532#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
5533
5534/* The count of PDB_DLY */
5535#define PDB_DLY_COUNT (2U)
5536
5537/* The count of PDB_DLY */
5538#define PDB_DLY_COUNT2 (2U)
5539
5540/*! @name INTC - DAC Interval Trigger n Control register */
5541#define PDB_INTC_TOE (0x1U)
5542#define PDB_INTC_EXT (0x2U)
5543
5544/* The count of PDB_INTC */
5545#define PDB_INTC_COUNT (2U)
5546
5547/*! @name INT - DAC Interval n register */
5548#define PDB_INT_INT_MASK (0xFFFFU)
5549#define PDB_INT_INT_SHIFT (0U)
5550#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
5551
5552/* The count of PDB_INT */
5553#define PDB_INT_COUNT (2U)
5554
5555/*! @name POEN - Pulse-Out n Enable register */
5556#define PDB_POEN_POEN_MASK (0xFFU)
5557#define PDB_POEN_POEN_SHIFT (0U)
5558#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
5559
5560/*! @name PODLY - Pulse-Out n Delay register */
5561#define PDB_PODLY_DLY2_MASK (0xFFFFU)
5562#define PDB_PODLY_DLY2_SHIFT (0U)
5563#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
5564#define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
5565#define PDB_PODLY_DLY1_SHIFT (16U)
5566#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
5567
5568/* The count of PDB_PODLY */
5569#define PDB_PODLY_COUNT (3U)
5570
5571
5572/*!
5573 * @}
5574 */ /* end of group PDB_Register_Masks */
5575
5576
5577/* PDB - Peripheral instance base addresses */
5578/** Peripheral PDB0 base address */
5579#define PDB0_BASE (0x40036000u)
5580/** Peripheral PDB0 base pointer */
5581#define PDB0 ((PDB_TypeDef *)PDB0_BASE)
5582/** Array initializer of PDB peripheral base addresses */
5583#define PDB_BASE_ADDRS { PDB0_BASE }
5584/** Array initializer of PDB peripheral base pointers */
5585#define PDB_BASE_PTRS { PDB0 }
5586/** Interrupt vectors for the PDB peripheral type */
5587#define PDB_IRQS { PDB0_IRQn }
5588
5589/*!
5590 * @}
5591 */ /* end of group PDB_Peripheral_Access_Layer */
5592
5593
5594/* ----------------------------------------------------------------------------
5595 -- PIT Peripheral Access Layer
5596 ---------------------------------------------------------------------------- */
5597
5598/*!
5599 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
5600 * @{
5601 */
5602
5603/** PIT - Register Layout Typedef */
5604typedef struct {
5605 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
5606 uint8_t RESERVED_0[252];
5607 struct { /* offset: 0x100, array step: 0x10 */
5608 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
5609 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
5610 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
5611 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
5612 } CHANNEL[4];
5613} PIT_TypeDef;
5614
5615/* ----------------------------------------------------------------------------
5616 -- PIT Register Masks
5617 ---------------------------------------------------------------------------- */
5618
5619/*!
5620 * @addtogroup PIT_Register_Masks PIT Register Masks
5621 * @{
5622 */
5623
5624/*! @name MCR - PIT Module Control Register */
5625#define PIT_MCR_FRZ (0x1U)
5626#define PIT_MCR_MDIS (0x2U)
5627
5628/* The count of PIT_LDVAL */
5629#define PIT_LDVAL_COUNT (4U)
5630
5631/* The count of PIT_CVAL */
5632#define PIT_CVAL_COUNT (4U)
5633
5634/*! @name TCTRL - Timer Control Register */
5635#define PIT_TCTRL_TEN (0x1U)
5636#define PIT_TCTRL_TIE (0x2U)
5637#define PIT_TCTRL_CHN (0x4U)
5638
5639/* The count of PIT_TCTRL */
5640#define PIT_TCTRL_COUNT (4U)
5641
5642/*! @name TFLG - Timer Flag Register */
5643#define PIT_TFLG_TIF (0x1U)
5644
5645/* The count of PIT_TFLG */
5646#define PIT_TFLG_COUNT (4U)
5647
5648
5649/*!
5650 * @}
5651 */ /* end of group PIT_Register_Masks */
5652
5653
5654/* PIT - Peripheral instance base addresses */
5655/** Peripheral PIT base address */
5656#define PIT_BASE (0x40037000u)
5657/** Peripheral PIT base pointer */
5658#define PIT ((PIT_TypeDef *)PIT_BASE)
5659/** Array initializer of PIT peripheral base addresses */
5660#define PIT_BASE_ADDRS { PIT_BASE }
5661/** Array initializer of PIT peripheral base pointers */
5662#define PIT_BASE_PTRS { PIT }
5663/** Interrupt vectors for the PIT peripheral type */
5664#define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
5665
5666/*!
5667 * @}
5668 */ /* end of group PIT_Peripheral_Access_Layer */
5669
5670
5671/* ----------------------------------------------------------------------------
5672 -- PMC Peripheral Access Layer
5673 ---------------------------------------------------------------------------- */
5674
5675/*!
5676 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
5677 * @{
5678 */
5679
5680/** PMC - Register Layout Typedef */
5681typedef struct {
5682 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
5683 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
5684 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
5685} PMC_TypeDef;
5686
5687/* ----------------------------------------------------------------------------
5688 -- PMC Register Masks
5689 ---------------------------------------------------------------------------- */
5690
5691/*!
5692 * @addtogroup PMC_Register_Masks PMC Register Masks
5693 * @{
5694 */
5695
5696/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
5697#define PMC_LVDSC1_LVDV_MASK (0x3U)
5698#define PMC_LVDSC1_LVDV_SHIFT (0U)
5699#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
5700#define PMC_LVDSC1_LVDRE (0x10U)
5701#define PMC_LVDSC1_LVDIE (0x20U)
5702#define PMC_LVDSC1_LVDACK (0x40U)
5703#define PMC_LVDSC1_LVDF (0x80U)
5704
5705/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
5706#define PMC_LVDSC2_LVWV_MASK (0x3U)
5707#define PMC_LVDSC2_LVWV_SHIFT (0U)
5708#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
5709#define PMC_LVDSC2_LVWIE (0x20U)
5710#define PMC_LVDSC2_LVWACK (0x40U)
5711#define PMC_LVDSC2_LVWF (0x80U)
5712
5713/*! @name REGSC - Regulator Status And Control register */
5714#define PMC_REGSC_BGBE (0x1U)
5715#define PMC_REGSC_REGONS (0x4U)
5716#define PMC_REGSC_ACKISO (0x8U)
5717#define PMC_REGSC_BGEN (0x10U)
5718
5719
5720/*!
5721 * @}
5722 */ /* end of group PMC_Register_Masks */
5723
5724
5725/* PMC - Peripheral instance base addresses */
5726/** Peripheral PMC base address */
5727#define PMC_BASE (0x4007D000u)
5728/** Peripheral PMC base pointer */
5729#define PMC ((PMC_TypeDef *)PMC_BASE)
5730/** Array initializer of PMC peripheral base addresses */
5731#define PMC_BASE_ADDRS { PMC_BASE }
5732/** Array initializer of PMC peripheral base pointers */
5733#define PMC_BASE_PTRS { PMC }
5734/** Interrupt vectors for the PMC peripheral type */
5735#define PMC_IRQS { LVD_LVW_IRQn }
5736
5737/*!
5738 * @}
5739 */ /* end of group PMC_Peripheral_Access_Layer */
5740
5741
5742/* ----------------------------------------------------------------------------
5743 -- PORT Peripheral Access Layer
5744 ---------------------------------------------------------------------------- */
5745
5746/*!
5747 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
5748 * @{
5749 */
5750
5751/** PORT - Register Layout Typedef */
5752typedef struct {
5753 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
5754 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
5755 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
5756 uint8_t RESERVED_0[24];
5757 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
5758 uint8_t RESERVED_1[28];
5759 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
5760 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
5761 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
5762} PORT_TypeDef;
5763
5764/* ----------------------------------------------------------------------------
5765 -- PORT Register Masks
5766 ---------------------------------------------------------------------------- */
5767
5768/*!
5769 * @addtogroup PORT_Register_Masks PORT Register Masks
5770 * @{
5771 */
5772
5773/*! @name PCR - Pin Control Register n */
5774#define PORTx_PCRn_PS (0x1U)
5775#define PORTx_PCRn_PE (0x2U)
5776#define PORTx_PCRn_SRE (0x4U)
5777#define PORTx_PCRn_PFE (0x10U)
5778#define PORTx_PCRn_ODE (0x20U)
5779#define PORTx_PCRn_DSE (0x40U)
5780#define PORTx_PCRn_MUX_MASK (0x700U)
5781#define PORTx_PCRn_MUX_SHIFT (8U)
5782#define PORTx_PCRn_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_MUX_SHIFT)) & PORTx_PCRn_MUX_MASK)
5783#define PORTx_PCRn_LK (0x8000U)
5784#define PORTx_PCRn_IRQC_MASK (0xF0000U)
5785#define PORTx_PCRn_IRQC_SHIFT (16U)
5786#define PORTx_PCRn_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_IRQC_SHIFT)) & PORTx_PCRn_IRQC_MASK)
5787#define PORTx_PCRn_ISF (0x1000000U)
5788
5789/* The count of PORT_PCR */
5790#define PORT_PCR_COUNT (32U)
5791
5792/*! @name GPCLR - Global Pin Control Low Register */
5793#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
5794#define PORT_GPCLR_GPWD_SHIFT (0U)
5795#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
5796#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
5797#define PORT_GPCLR_GPWE_SHIFT (16U)
5798#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
5799
5800/*! @name GPCHR - Global Pin Control High Register */
5801#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
5802#define PORT_GPCHR_GPWD_SHIFT (0U)
5803#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
5804#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
5805#define PORT_GPCHR_GPWE_SHIFT (16U)
5806#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
5807
5808/*! @name DFCR - Digital Filter Clock Register */
5809#define PORT_DFCR_CS (0x1U)
5810
5811/*! @name DFWR - Digital Filter Width Register */
5812#define PORT_DFWR_FILT_MASK (0x1FU)
5813#define PORT_DFWR_FILT_SHIFT (0U)
5814#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
5815
5816
5817/*!
5818 * @}
5819 */ /* end of group PORT_Register_Masks */
5820
5821
5822/* PORT - Peripheral instance base addresses */
5823/** Peripheral PORTA base address */
5824#define PORTA_BASE (0x40049000u)
5825/** Peripheral PORTA base pointer */
5826#define PORTA ((PORT_TypeDef *)PORTA_BASE)
5827/** Peripheral PORTB base address */
5828#define PORTB_BASE (0x4004A000u)
5829/** Peripheral PORTB base pointer */
5830#define PORTB ((PORT_TypeDef *)PORTB_BASE)
5831/** Peripheral PORTC base address */
5832#define PORTC_BASE (0x4004B000u)
5833/** Peripheral PORTC base pointer */
5834#define PORTC ((PORT_TypeDef *)PORTC_BASE)
5835/** Peripheral PORTD base address */
5836#define PORTD_BASE (0x4004C000u)
5837/** Peripheral PORTD base pointer */
5838#define PORTD ((PORT_TypeDef *)PORTD_BASE)
5839/** Peripheral PORTE base address */
5840#define PORTE_BASE (0x4004D000u)
5841/** Peripheral PORTE base pointer */
5842#define PORTE ((PORT_TypeDef *)PORTE_BASE)
5843/** Array initializer of PORT peripheral base addresses */
5844#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
5845/** Array initializer of PORT peripheral base pointers */
5846#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
5847/** Interrupt vectors for the PORT peripheral type */
5848#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
5849
5850/*!
5851 * @}
5852 */ /* end of group PORT_Peripheral_Access_Layer */
5853
5854
5855/* ----------------------------------------------------------------------------
5856 -- RCM Peripheral Access Layer
5857 ---------------------------------------------------------------------------- */
5858
5859/*!
5860 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
5861 * @{
5862 */
5863
5864/** RCM - Register Layout Typedef */
5865typedef struct {
5866 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
5867 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
5868 uint8_t RESERVED_0[2];
5869 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
5870 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
5871 uint8_t RESERVED_1[1];
5872 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
5873} RCM_TypeDef;
5874
5875/* ----------------------------------------------------------------------------
5876 -- RCM Register Masks
5877 ---------------------------------------------------------------------------- */
5878
5879/*!
5880 * @addtogroup RCM_Register_Masks RCM Register Masks
5881 * @{
5882 */
5883
5884/*! @name SRS0 - System Reset Status Register 0 */
5885#define RCM_SRS0_WAKEUP (0x1U)
5886#define RCM_SRS0_LVD (0x2U)
5887#define RCM_SRS0_LOC (0x4U)
5888#define RCM_SRS0_LOL (0x8U)
5889#define RCM_SRS0_WDOG (0x20U)
5890#define RCM_SRS0_PIN (0x40U)
5891#define RCM_SRS0_POR (0x80U)
5892
5893/*! @name SRS1 - System Reset Status Register 1 */
5894#define RCM_SRS1_JTAG (0x1U)
5895#define RCM_SRS1_LOCKUP (0x2U)
5896#define RCM_SRS1_SW (0x4U)
5897#define RCM_SRS1_MDM_AP (0x8U)
5898#define RCM_SRS1_EZPT (0x10U)
5899#define RCM_SRS1_SACKERR (0x20U)
5900
5901/*! @name RPFC - Reset Pin Filter Control register */
5902#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
5903#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
5904#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
5905#define RCM_RPFC_RSTFLTSS (0x4U)
5906
5907/*! @name RPFW - Reset Pin Filter Width register */
5908#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
5909#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
5910#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
5911
5912/*! @name MR - Mode Register */
5913#define RCM_MR_EZP_MS (0x2U)
5914
5915
5916/*!
5917 * @}
5918 */ /* end of group RCM_Register_Masks */
5919
5920
5921/* RCM - Peripheral instance base addresses */
5922/** Peripheral RCM base address */
5923#define RCM_BASE (0x4007F000u)
5924/** Peripheral RCM base pointer */
5925#define RCM ((RCM_TypeDef *)RCM_BASE)
5926/** Array initializer of RCM peripheral base addresses */
5927#define RCM_BASE_ADDRS { RCM_BASE }
5928/** Array initializer of RCM peripheral base pointers */
5929#define RCM_BASE_PTRS { RCM }
5930
5931/*!
5932 * @}
5933 */ /* end of group RCM_Peripheral_Access_Layer */
5934
5935
5936/* ----------------------------------------------------------------------------
5937 -- RFSYS Peripheral Access Layer
5938 ---------------------------------------------------------------------------- */
5939
5940/*!
5941 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
5942 * @{
5943 */
5944
5945/** RFSYS - Register Layout Typedef */
5946typedef struct {
5947 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
5948} RFSYS_TypeDef;
5949
5950/* ----------------------------------------------------------------------------
5951 -- RFSYS Register Masks
5952 ---------------------------------------------------------------------------- */
5953
5954/*!
5955 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
5956 * @{
5957 */
5958
5959/*! @name REG - Register file register */
5960#define RFSYS_REG_LL_MASK (0xFFU)
5961#define RFSYS_REG_LL_SHIFT (0U)
5962#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
5963#define RFSYS_REG_LH_MASK (0xFF00U)
5964#define RFSYS_REG_LH_SHIFT (8U)
5965#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
5966#define RFSYS_REG_HL_MASK (0xFF0000U)
5967#define RFSYS_REG_HL_SHIFT (16U)
5968#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
5969#define RFSYS_REG_HH_MASK (0xFF000000U)
5970#define RFSYS_REG_HH_SHIFT (24U)
5971#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
5972
5973/* The count of RFSYS_REG */
5974#define RFSYS_REG_COUNT (8U)
5975
5976
5977/*!
5978 * @}
5979 */ /* end of group RFSYS_Register_Masks */
5980
5981
5982/* RFSYS - Peripheral instance base addresses */
5983/** Peripheral RFSYS base address */
5984#define RFSYS_BASE (0x40041000u)
5985/** Peripheral RFSYS base pointer */
5986#define RFSYS ((RFSYS_TypeDef *)RFSYS_BASE)
5987/** Array initializer of RFSYS peripheral base addresses */
5988#define RFSYS_BASE_ADDRS { RFSYS_BASE }
5989/** Array initializer of RFSYS peripheral base pointers */
5990#define RFSYS_BASE_PTRS { RFSYS }
5991
5992/*!
5993 * @}
5994 */ /* end of group RFSYS_Peripheral_Access_Layer */
5995
5996
5997/* ----------------------------------------------------------------------------
5998 -- RFVBAT Peripheral Access Layer
5999 ---------------------------------------------------------------------------- */
6000
6001/*!
6002 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
6003 * @{
6004 */
6005
6006/** RFVBAT - Register Layout Typedef */
6007typedef struct {
6008 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
6009} RFVBAT_TypeDef;
6010
6011/* ----------------------------------------------------------------------------
6012 -- RFVBAT Register Masks
6013 ---------------------------------------------------------------------------- */
6014
6015/*!
6016 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
6017 * @{
6018 */
6019
6020/*! @name REG - VBAT register file register */
6021#define RFVBAT_REG_LL_MASK (0xFFU)
6022#define RFVBAT_REG_LL_SHIFT (0U)
6023#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
6024#define RFVBAT_REG_LH_MASK (0xFF00U)
6025#define RFVBAT_REG_LH_SHIFT (8U)
6026#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
6027#define RFVBAT_REG_HL_MASK (0xFF0000U)
6028#define RFVBAT_REG_HL_SHIFT (16U)
6029#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
6030#define RFVBAT_REG_HH_MASK (0xFF000000U)
6031#define RFVBAT_REG_HH_SHIFT (24U)
6032#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
6033
6034/* The count of RFVBAT_REG */
6035#define RFVBAT_REG_COUNT (8U)
6036
6037
6038/*!
6039 * @}
6040 */ /* end of group RFVBAT_Register_Masks */
6041
6042
6043/* RFVBAT - Peripheral instance base addresses */
6044/** Peripheral RFVBAT base address */
6045#define RFVBAT_BASE (0x4003E000u)
6046/** Peripheral RFVBAT base pointer */
6047#define RFVBAT ((RFVBAT_TypeDef *)RFVBAT_BASE)
6048/** Array initializer of RFVBAT peripheral base addresses */
6049#define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
6050/** Array initializer of RFVBAT peripheral base pointers */
6051#define RFVBAT_BASE_PTRS { RFVBAT }
6052
6053/*!
6054 * @}
6055 */ /* end of group RFVBAT_Peripheral_Access_Layer */
6056
6057
6058/* ----------------------------------------------------------------------------
6059 -- RNG Peripheral Access Layer
6060 ---------------------------------------------------------------------------- */
6061
6062/*!
6063 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
6064 * @{
6065 */
6066
6067/** RNG - Register Layout Typedef */
6068typedef struct {
6069 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
6070 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
6071 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
6072 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
6073} RNG_TypeDef;
6074
6075/* ----------------------------------------------------------------------------
6076 -- RNG Register Masks
6077 ---------------------------------------------------------------------------- */
6078
6079/*!
6080 * @addtogroup RNG_Register_Masks RNG Register Masks
6081 * @{
6082 */
6083
6084/*! @name CR - RNGA Control Register */
6085#define RNG_CR_GO (0x1U)
6086#define RNG_CR_HA (0x2U)
6087#define RNG_CR_INTM (0x4U)
6088#define RNG_CR_CLRI (0x8U)
6089#define RNG_CR_SLP (0x10U)
6090
6091/*! @name SR - RNGA Status Register */
6092#define RNG_SR_SECV (0x1U)
6093#define RNG_SR_LRS (0x2U)
6094#define RNG_SR_ORU (0x4U)
6095#define RNG_SR_ERRI (0x8U)
6096#define RNG_SR_SLP (0x10U)
6097#define RNG_SR_OREG_LVL_MASK (0xFF00U)
6098#define RNG_SR_OREG_LVL_SHIFT (8U)
6099#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
6100#define RNG_SR_OREG_SIZE_MASK (0xFF0000U)
6101#define RNG_SR_OREG_SIZE_SHIFT (16U)
6102#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
6103
6104/*!
6105 * @}
6106 */ /* end of group RNG_Register_Masks */
6107
6108
6109/* RNG - Peripheral instance base addresses */
6110/** Peripheral RNG base address */
6111#define RNG_BASE (0x40029000u)
6112/** Peripheral RNG base pointer */
6113#define RNG ((RNG_TypeDef *)RNG_BASE)
6114/** Array initializer of RNG peripheral base addresses */
6115#define RNG_BASE_ADDRS { RNG_BASE }
6116/** Array initializer of RNG peripheral base pointers */
6117#define RNG_BASE_PTRS { RNG }
6118/** Interrupt vectors for the RNG peripheral type */
6119#define RNG_IRQS { RNG_IRQn }
6120
6121/*!
6122 * @}
6123 */ /* end of group RNG_Peripheral_Access_Layer */
6124
6125
6126/* ----------------------------------------------------------------------------
6127 -- RTC Peripheral Access Layer
6128 ---------------------------------------------------------------------------- */
6129
6130/*!
6131 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
6132 * @{
6133 */
6134
6135/** RTC - Register Layout Typedef */
6136typedef struct {
6137 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
6138 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
6139 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
6140 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
6141 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
6142 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
6143 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
6144 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
6145 uint8_t RESERVED_0[2016];
6146 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
6147 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
6148} RTC_TypeDef;
6149
6150/* ----------------------------------------------------------------------------
6151 -- RTC Register Masks
6152 ---------------------------------------------------------------------------- */
6153
6154/*!
6155 * @addtogroup RTC_Register_Masks RTC Register Masks
6156 * @{
6157 */
6158
6159/*! @name TPR - RTC Time Prescaler Register */
6160#define RTC_TPR_TPR_MASK (0xFFFFU)
6161#define RTC_TPR_TPR_SHIFT (0U)
6162#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
6163
6164/*! @name TCR - RTC Time Compensation Register */
6165#define RTC_TCR_TCR_MASK (0xFFU)
6166#define RTC_TCR_TCR_SHIFT (0U)
6167#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
6168#define RTC_TCR_CIR_MASK (0xFF00U)
6169#define RTC_TCR_CIR_SHIFT (8U)
6170#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
6171#define RTC_TCR_TCV_MASK (0xFF0000U)
6172#define RTC_TCR_TCV_SHIFT (16U)
6173#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
6174#define RTC_TCR_CIC_MASK (0xFF000000U)
6175#define RTC_TCR_CIC_SHIFT (24U)
6176#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
6177
6178/*! @name CR - RTC Control Register */
6179#define RTC_CR_SWR (0x1U)
6180#define RTC_CR_WPE (0x2U)
6181#define RTC_CR_SUP (0x4U)
6182#define RTC_CR_UM (0x8U)
6183#define RTC_CR_WPS (0x10U)
6184#define RTC_CR_OSCE (0x100U)
6185#define RTC_CR_CLKO (0x200U)
6186#define RTC_CR_SC16P (0x400U)
6187#define RTC_CR_SC8P (0x800U)
6188#define RTC_CR_SC4P (0x1000U)
6189#define RTC_CR_SC2P (0x2000U)
6190
6191/*! @name SR - RTC Status Register */
6192#define RTC_SR_TIF (0x1U)
6193#define RTC_SR_TOF (0x2U)
6194#define RTC_SR_TAF (0x4U)
6195#define RTC_SR_TCE (0x10U)
6196
6197/*! @name LR - RTC Lock Register */
6198#define RTC_LR_TCL (0x8U)
6199#define RTC_LR_CRL (0x10U)
6200#define RTC_LR_SRL (0x20U)
6201#define RTC_LR_LRL (0x40U)
6202
6203/*! @name IER - RTC Interrupt Enable Register */
6204#define RTC_IER_TIIE (0x1U)
6205#define RTC_IER_TOIE (0x2U)
6206#define RTC_IER_TAIE (0x4U)
6207#define RTC_IER_TSIE (0x10U)
6208#define RTC_IER_WPON (0x80U)
6209
6210/*! @name WAR - RTC Write Access Register */
6211#define RTC_WAR_TSRW (0x1U)
6212#define RTC_WAR_TPRW (0x2U)
6213#define RTC_WAR_TARW (0x4U)
6214#define RTC_WAR_TCRW (0x8U)
6215#define RTC_WAR_CRW (0x10U)
6216#define RTC_WAR_SRW (0x20U)
6217#define RTC_WAR_LRW (0x40U)
6218#define RTC_WAR_IERW (0x80U)
6219
6220/*! @name RAR - RTC Read Access Register */
6221#define RTC_RAR_TSRR (0x1U)
6222#define RTC_RAR_TPRR (0x2U)
6223#define RTC_RAR_TARR (0x4U)
6224#define RTC_RAR_TCRR (0x8U)
6225#define RTC_RAR_CRR (0x10U)
6226#define RTC_RAR_SRR (0x20U)
6227#define RTC_RAR_LRR (0x40U)
6228#define RTC_RAR_IERR (0x80U)
6229
6230
6231/*!
6232 * @}
6233 */ /* end of group RTC_Register_Masks */
6234
6235
6236/* RTC - Peripheral instance base addresses */
6237/** Peripheral RTC base address */
6238#define RTC_BASE (0x4003D000u)
6239/** Peripheral RTC base pointer */
6240#define RTC ((RTC_TypeDef *)RTC_BASE)
6241/** Array initializer of RTC peripheral base addresses */
6242#define RTC_BASE_ADDRS { RTC_BASE }
6243/** Array initializer of RTC peripheral base pointers */
6244#define RTC_BASE_PTRS { RTC }
6245/** Interrupt vectors for the RTC peripheral type */
6246#define RTC_IRQS { RTC_IRQn }
6247#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
6248
6249/*!
6250 * @}
6251 */ /* end of group RTC_Peripheral_Access_Layer */
6252
6253
6254/* ----------------------------------------------------------------------------
6255 -- SDHC Peripheral Access Layer
6256 ---------------------------------------------------------------------------- */
6257
6258/*!
6259 * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
6260 * @{
6261 */
6262
6263/** SDHC - Register Layout Typedef */
6264typedef struct {
6265 __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
6266 __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
6267 __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
6268 __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
6269 __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
6270 __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
6271 __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
6272 __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
6273 __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
6274 __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
6275 __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
6276 __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
6277 __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
6278 __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
6279 __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
6280 uint8_t RESERVED_0[8];
6281 __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
6282 __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
6283 __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
6284 uint8_t RESERVED_1[100];
6285 __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
6286 __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
6287 uint8_t RESERVED_2[52];
6288 __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
6289} SDHC_TypeDef;
6290
6291/* ----------------------------------------------------------------------------
6292 -- SDHC Register Masks
6293 ---------------------------------------------------------------------------- */
6294
6295/*!
6296 * @addtogroup SDHC_Register_Masks SDHC Register Masks
6297 * @{
6298 */
6299
6300/*! @name BLKATTR - Block Attributes register */
6301#define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU)
6302#define SDHC_BLKATTR_BLKSIZE_SHIFT (0U)
6303#define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
6304#define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U)
6305#define SDHC_BLKATTR_BLKCNT_SHIFT (16U)
6306#define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
6307
6308/*! @name XFERTYP - Transfer Type register */
6309#define SDHC_XFERTYP_DMAEN (0x1U)
6310#define SDHC_XFERTYP_BCEN (0x2U)
6311#define SDHC_XFERTYP_AC12EN (0x4U)
6312#define SDHC_XFERTYP_DTDSEL (0x10U)
6313#define SDHC_XFERTYP_MSBSEL (0x20U)
6314#define SDHC_XFERTYP_RSPTYP_MASK (0x30000U)
6315#define SDHC_XFERTYP_RSPTYP_SHIFT (16U)
6316#define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
6317#define SDHC_XFERTYP_CCCEN (0x80000U)
6318#define SDHC_XFERTYP_CICEN (0x100000U)
6319#define SDHC_XFERTYP_DPSEL (0x200000U)
6320#define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U)
6321#define SDHC_XFERTYP_CMDTYP_SHIFT (22U)
6322#define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
6323#define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U)
6324#define SDHC_XFERTYP_CMDINX_SHIFT (24U)
6325#define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
6326
6327/* The count of SDHC_CMDRSP */
6328#define SDHC_CMDRSP_COUNT (4U)
6329
6330/*! @name PRSSTAT - Present State register */
6331#define SDHC_PRSSTAT_CIHB (0x1U)
6332#define SDHC_PRSSTAT_CDIHB (0x2U)
6333#define SDHC_PRSSTAT_DLA (0x4U)
6334#define SDHC_PRSSTAT_SDSTB (0x8U)
6335#define SDHC_PRSSTAT_IPGOFF (0x10U)
6336#define SDHC_PRSSTAT_HCKOFF (0x20U)
6337#define SDHC_PRSSTAT_PEROFF (0x40U)
6338#define SDHC_PRSSTAT_SDOFF (0x80U)
6339#define SDHC_PRSSTAT_WTA (0x100U)
6340#define SDHC_PRSSTAT_RTA (0x200U)
6341#define SDHC_PRSSTAT_BWEN (0x400U)
6342#define SDHC_PRSSTAT_BREN (0x800U)
6343#define SDHC_PRSSTAT_CINS (0x10000U)
6344#define SDHC_PRSSTAT_CLSL (0x800000U)
6345#define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U)
6346#define SDHC_PRSSTAT_DLSL_SHIFT (24U)
6347#define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
6348
6349/*! @name PROCTL - Protocol Control register */
6350#define SDHC_PROCTL_LCTL (0x1U)
6351#define SDHC_PROCTL_DTW_MASK (0x6U)
6352#define SDHC_PROCTL_DTW_SHIFT (1U)
6353#define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
6354#define SDHC_PROCTL_D3CD (0x8U)
6355#define SDHC_PROCTL_EMODE_MASK (0x30U)
6356#define SDHC_PROCTL_EMODE_SHIFT (4U)
6357#define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
6358#define SDHC_PROCTL_CDTL (0x40U)
6359#define SDHC_PROCTL_CDSS (0x80U)
6360#define SDHC_PROCTL_DMAS_MASK (0x300U)
6361#define SDHC_PROCTL_DMAS_SHIFT (8U)
6362#define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
6363#define SDHC_PROCTL_SABGREQ (0x10000U)
6364#define SDHC_PROCTL_CREQ (0x20000U)
6365#define SDHC_PROCTL_RWCTL (0x40000U)
6366#define SDHC_PROCTL_IABG (0x80000U)
6367#define SDHC_PROCTL_WECINT (0x1000000U)
6368#define SDHC_PROCTL_WECINS (0x2000000U)
6369#define SDHC_PROCTL_WECRM (0x4000000U)
6370
6371/*! @name SYSCTL - System Control register */
6372#define SDHC_SYSCTL_IPGEN (0x1U)
6373#define SDHC_SYSCTL_HCKEN (0x2U)
6374#define SDHC_SYSCTL_PEREN (0x4U)
6375#define SDHC_SYSCTL_SDCLKEN (0x8U)
6376#define SDHC_SYSCTL_DVS_MASK (0xF0U)
6377#define SDHC_SYSCTL_DVS_SHIFT (4U)
6378#define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
6379#define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U)
6380#define SDHC_SYSCTL_SDCLKFS_SHIFT (8U)
6381#define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
6382#define SDHC_SYSCTL_DTOCV_MASK (0xF0000U)
6383#define SDHC_SYSCTL_DTOCV_SHIFT (16U)
6384#define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
6385#define SDHC_SYSCTL_RSTA (0x1000000U)
6386#define SDHC_SYSCTL_RSTC (0x2000000U)
6387#define SDHC_SYSCTL_RSTD (0x4000000U)
6388#define SDHC_SYSCTL_INITA (0x8000000U)
6389
6390/*! @name IRQSTAT - Interrupt Status register */
6391#define SDHC_IRQSTAT_CC (0x1U)
6392#define SDHC_IRQSTAT_TC (0x2U)
6393#define SDHC_IRQSTAT_BGE (0x4U)
6394#define SDHC_IRQSTAT_DINT (0x8U)
6395#define SDHC_IRQSTAT_BWR (0x10U)
6396#define SDHC_IRQSTAT_BRR (0x20U)
6397#define SDHC_IRQSTAT_CINS (0x40U)
6398#define SDHC_IRQSTAT_CRM (0x80U)
6399#define SDHC_IRQSTAT_CINT (0x100U)
6400#define SDHC_IRQSTAT_CTOE (0x10000U)
6401#define SDHC_IRQSTAT_CCE (0x20000U)
6402#define SDHC_IRQSTAT_CEBE (0x40000U)
6403#define SDHC_IRQSTAT_CIE (0x80000U)
6404#define SDHC_IRQSTAT_DTOE (0x100000U)
6405#define SDHC_IRQSTAT_DCE (0x200000U)
6406#define SDHC_IRQSTAT_DEBE (0x400000U)
6407#define SDHC_IRQSTAT_AC12E (0x1000000U)
6408#define SDHC_IRQSTAT_DMAE (0x10000000U)
6409
6410/*! @name IRQSTATEN - Interrupt Status Enable register */
6411#define SDHC_IRQSTATEN_CCSEN (0x1U)
6412#define SDHC_IRQSTATEN_TCSEN (0x2U)
6413#define SDHC_IRQSTATEN_BGESEN (0x4U)
6414#define SDHC_IRQSTATEN_DINTSEN (0x8U)
6415#define SDHC_IRQSTATEN_BWRSEN (0x10U)
6416#define SDHC_IRQSTATEN_BRRSEN (0x20U)
6417#define SDHC_IRQSTATEN_CINSEN (0x40U)
6418#define SDHC_IRQSTATEN_CRMSEN (0x80U)
6419#define SDHC_IRQSTATEN_CINTSEN (0x100U)
6420#define SDHC_IRQSTATEN_CTOESEN (0x10000U)
6421#define SDHC_IRQSTATEN_CCESEN (0x20000U)
6422#define SDHC_IRQSTATEN_CEBESEN (0x40000U)
6423#define SDHC_IRQSTATEN_CIESEN (0x80000U)
6424#define SDHC_IRQSTATEN_DTOESEN (0x100000U)
6425#define SDHC_IRQSTATEN_DCESEN (0x200000U)
6426#define SDHC_IRQSTATEN_DEBESEN (0x400000U)
6427#define SDHC_IRQSTATEN_AC12ESEN (0x1000000U)
6428#define SDHC_IRQSTATEN_DMAESEN (0x10000000U)
6429
6430/*! @name IRQSIGEN - Interrupt Signal Enable register */
6431#define SDHC_IRQSIGEN_CCIEN (0x1U)
6432#define SDHC_IRQSIGEN_TCIEN (0x2U)
6433#define SDHC_IRQSIGEN_BGEIEN (0x4U)
6434#define SDHC_IRQSIGEN_DINTIEN (0x8U)
6435#define SDHC_IRQSIGEN_BWRIEN (0x10U)
6436#define SDHC_IRQSIGEN_BRRIEN (0x20U)
6437#define SDHC_IRQSIGEN_CINSIEN (0x40U)
6438#define SDHC_IRQSIGEN_CRMIEN (0x80U)
6439#define SDHC_IRQSIGEN_CINTIEN (0x100U)
6440#define SDHC_IRQSIGEN_CTOEIEN (0x10000U)
6441#define SDHC_IRQSIGEN_CCEIEN (0x20000U)
6442#define SDHC_IRQSIGEN_CEBEIEN (0x40000U)
6443#define SDHC_IRQSIGEN_CIEIEN (0x80000U)
6444#define SDHC_IRQSIGEN_DTOEIEN (0x100000U)
6445#define SDHC_IRQSIGEN_DCEIEN (0x200000U)
6446#define SDHC_IRQSIGEN_DEBEIEN (0x400000U)
6447#define SDHC_IRQSIGEN_AC12EIEN (0x1000000U)
6448#define SDHC_IRQSIGEN_DMAEIEN (0x10000000U)
6449
6450/*! @name AC12ERR - Auto CMD12 Error Status Register */
6451#define SDHC_AC12ERR_AC12NE (0x1U)
6452#define SDHC_AC12ERR_AC12TOE (0x2U)
6453#define SDHC_AC12ERR_AC12EBE (0x4U)
6454#define SDHC_AC12ERR_AC12CE (0x8U)
6455#define SDHC_AC12ERR_AC12IE (0x10U)
6456#define SDHC_AC12ERR_CNIBAC12E (0x80U)
6457
6458/*! @name HTCAPBLT - Host Controller Capabilities */
6459#define SDHC_HTCAPBLT_MBL_MASK (0x70000U)
6460#define SDHC_HTCAPBLT_MBL_SHIFT (16U)
6461#define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
6462#define SDHC_HTCAPBLT_ADMAS (0x100000U)
6463#define SDHC_HTCAPBLT_HSS (0x200000U)
6464#define SDHC_HTCAPBLT_DMAS (0x400000U)
6465#define SDHC_HTCAPBLT_SRS (0x800000U)
6466#define SDHC_HTCAPBLT_VS33 (0x1000000U)
6467
6468/*! @name WML - Watermark Level Register */
6469#define SDHC_WML_RDWML_MASK (0xFFU)
6470#define SDHC_WML_RDWML_SHIFT (0U)
6471#define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
6472#define SDHC_WML_WRWML_MASK (0xFF0000U)
6473#define SDHC_WML_WRWML_SHIFT (16U)
6474#define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
6475
6476/*! @name FEVT - Force Event register */
6477#define SDHC_FEVT_AC12NE (0x1U)
6478#define SDHC_FEVT_AC12TOE (0x2U)
6479#define SDHC_FEVT_AC12CE (0x4U)
6480#define SDHC_FEVT_AC12EBE (0x8U)
6481#define SDHC_FEVT_AC12IE (0x10U)
6482#define SDHC_FEVT_CNIBAC12E (0x80U)
6483#define SDHC_FEVT_CTOE (0x10000U)
6484#define SDHC_FEVT_CCE (0x20000U)
6485#define SDHC_FEVT_CEBE (0x40000U)
6486#define SDHC_FEVT_CIE (0x80000U)
6487#define SDHC_FEVT_DTOE (0x100000U)
6488#define SDHC_FEVT_DCE (0x200000U)
6489#define SDHC_FEVT_DEBE (0x400000U)
6490#define SDHC_FEVT_AC12E (0x1000000U)
6491#define SDHC_FEVT_DMAE (0x10000000U)
6492#define SDHC_FEVT_CINT (0x80000000U)
6493
6494/*! @name ADMAES - ADMA Error Status register */
6495#define SDHC_ADMAES_ADMAES_MASK (0x3U)
6496#define SDHC_ADMAES_ADMAES_SHIFT (0U)
6497#define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
6498#define SDHC_ADMAES_ADMALME (0x4U)
6499#define SDHC_ADMAES_ADMADCE (0x8U)
6500
6501/*! @name VENDOR - Vendor Specific register */
6502#define SDHC_VENDOR_EXTDMAEN (0x1U)
6503#define SDHC_VENDOR_EXBLKNU (0x2U)
6504#define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U)
6505#define SDHC_VENDOR_INTSTVAL_SHIFT (16U)
6506#define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
6507
6508/*! @name MMCBOOT - MMC Boot register */
6509#define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU)
6510#define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U)
6511#define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
6512#define SDHC_MMCBOOT_BOOTACK (0x10U)
6513#define SDHC_MMCBOOT_BOOTMODE (0x20U)
6514#define SDHC_MMCBOOT_BOOTEN (0x40U)
6515#define SDHC_MMCBOOT_AUTOSABGEN (0x80U)
6516#define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U)
6517#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U)
6518#define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
6519
6520/*! @name HOSTVER - Host Controller Version */
6521#define SDHC_HOSTVER_SVN_MASK (0xFFU)
6522#define SDHC_HOSTVER_SVN_SHIFT (0U)
6523#define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
6524#define SDHC_HOSTVER_VVN_MASK (0xFF00U)
6525#define SDHC_HOSTVER_VVN_SHIFT (8U)
6526#define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
6527
6528
6529/*!
6530 * @}
6531 */ /* end of group SDHC_Register_Masks */
6532
6533
6534/* SDHC - Peripheral instance base addresses */
6535/** Peripheral SDHC base address */
6536#define SDHC_BASE (0x400B1000u)
6537/** Peripheral SDHC base pointer */
6538#define SDHC ((SDHC_TypeDef *)SDHC_BASE)
6539/** Array initializer of SDHC peripheral base addresses */
6540#define SDHC_BASE_ADDRS { SDHC_BASE }
6541/** Array initializer of SDHC peripheral base pointers */
6542#define SDHC_BASE_PTRS { SDHC }
6543/** Interrupt vectors for the SDHC peripheral type */
6544#define SDHC_IRQS { SDHC_IRQn }
6545
6546/*!
6547 * @}
6548 */ /* end of group SDHC_Peripheral_Access_Layer */
6549
6550
6551/* ----------------------------------------------------------------------------
6552 -- SIM Peripheral Access Layer
6553 ---------------------------------------------------------------------------- */
6554
6555/*!
6556 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
6557 * @{
6558 */
6559
6560/** SIM - Register Layout Typedef */
6561typedef struct {
6562 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
6563 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
6564 uint8_t RESERVED_0[4092];
6565 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
6566 uint8_t RESERVED_1[4];
6567 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
6568 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
6569 uint8_t RESERVED_2[4];
6570 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
6571 uint8_t RESERVED_3[8];
6572 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
6573 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
6574 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
6575 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
6576 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
6577 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
6578 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
6579 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
6580 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
6581 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
6582 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
6583 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
6584 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
6585 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
6586 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
6587 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
6588} SIM_TypeDef;
6589
6590/* ----------------------------------------------------------------------------
6591 -- SIM Register Masks
6592 ---------------------------------------------------------------------------- */
6593
6594/*!
6595 * @addtogroup SIM_Register_Masks SIM Register Masks
6596 * @{
6597 */
6598
6599/*! @name SOPT1 - System Options Register 1 */
6600#define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
6601#define SIM_SOPT1_RAMSIZE_SHIFT (12U)
6602#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
6603#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
6604#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
6605#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
6606#define SIM_SOPT1_USBVSTBY (0x20000000U)
6607#define SIM_SOPT1_USBSSTBY (0x40000000U)
6608#define SIM_SOPT1_USBREGEN (0x80000000U)
6609
6610/*! @name SOPT1CFG - SOPT1 Configuration Register */
6611#define SIM_SOPT1CFG_URWE (0x1000000U)
6612#define SIM_SOPT1CFG_UVSWE (0x2000000U)
6613#define SIM_SOPT1CFG_USSWE (0x4000000U)
6614
6615/*! @name SOPT2 - System Options Register 2 */
6616#define SIM_SOPT2_RTCCLKOUTSEL (0x10U)
6617#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
6618#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
6619#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
6620#define SIM_SOPT2_FBSL_MASK (0x300U)
6621#define SIM_SOPT2_FBSL_SHIFT (8U)
6622#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
6623#define SIM_SOPT2_PTD7PAD (0x800U)
6624#define SIM_SOPT2_TRACECLKSEL (0x1000U)
6625#define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U)
6626#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
6627#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
6628#define SIM_SOPT2_PLLFLLSEL_MCGFLL SIM_SOPT2_PLLFLLSEL(0)
6629#define SIM_SOPT2_PLLFLLSEL_MCGPLL SIM_SOPT2_PLLFLLSEL(1)
6630#define SIM_SOPT2_PLLFLLSEL_IRC48M SIM_SOPT2_PLLFLLSEL(3)
6631#define SIM_SOPT2_USBSRC (0x40000U)
6632#define SIM_SOPT2_RMIISRC (0x80000U)
6633#define SIM_SOPT2_TIMESRC_MASK (0x300000U)
6634#define SIM_SOPT2_TIMESRC_SHIFT (20U)
6635#define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
6636#define SIM_SOPT2_SDHCSRC_MASK (0x30000000U)
6637#define SIM_SOPT2_SDHCSRC_SHIFT (28U)
6638#define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
6639
6640/*! @name SOPT4 - System Options Register 4 */
6641#define SIM_SOPT4_FTM0FLT0 (0x1U)
6642#define SIM_SOPT4_FTM0FLT1 (0x2U)
6643#define SIM_SOPT4_FTM0FLT2 (0x4U)
6644#define SIM_SOPT4_FTM1FLT0 (0x10U)
6645#define SIM_SOPT4_FTM2FLT0 (0x100U)
6646#define SIM_SOPT4_FTM3FLT0 (0x1000U)
6647#define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
6648#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
6649#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
6650#define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
6651#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
6652#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
6653#define SIM_SOPT4_FTM0CLKSEL (0x1000000U)
6654#define SIM_SOPT4_FTM1CLKSEL (0x2000000U)
6655#define SIM_SOPT4_FTM2CLKSEL (0x4000000U)
6656#define SIM_SOPT4_FTM3CLKSEL (0x8000000U)
6657#define SIM_SOPT4_FTM0TRG0SRC (0x10000000U)
6658#define SIM_SOPT4_FTM0TRG1SRC (0x20000000U)
6659#define SIM_SOPT4_FTM3TRG0SRC (0x40000000U)
6660#define SIM_SOPT4_FTM3TRG1SRC (0x80000000U)
6661
6662/*! @name SOPT5 - System Options Register 5 */
6663#define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
6664#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
6665#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
6666#define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
6667#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
6668#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
6669#define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
6670#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
6671#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
6672#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
6673#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
6674#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
6675
6676/*! @name SOPT7 - System Options Register 7 */
6677#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
6678#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
6679#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
6680#define SIM_SOPT7_ADC0PRETRGSEL (0x10U)
6681#define SIM_SOPT7_ADC0ALTTRGEN (0x80U)
6682#define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U)
6683#define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U)
6684#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
6685#define SIM_SOPT7_ADC1PRETRGSEL (0x1000U)
6686#define SIM_SOPT7_ADC1ALTTRGEN (0x8000U)
6687
6688/*! @name SDID - System Device Identification Register */
6689#define SIM_SDID_PINID_MASK (0xFU)
6690#define SIM_SDID_PINID_SHIFT (0U)
6691#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
6692#define SIM_SDID_FAMID_MASK (0x70U)
6693#define SIM_SDID_FAMID_SHIFT (4U)
6694#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
6695#define SIM_SDID_DIEID_MASK (0xF80U)
6696#define SIM_SDID_DIEID_SHIFT (7U)
6697#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
6698#define SIM_SDID_REVID_MASK (0xF000U)
6699#define SIM_SDID_REVID_SHIFT (12U)
6700#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
6701#define SIM_SDID_SERIESID_MASK (0xF00000U)
6702#define SIM_SDID_SERIESID_SHIFT (20U)
6703#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
6704#define SIM_SDID_SUBFAMID_MASK (0xF000000U)
6705#define SIM_SDID_SUBFAMID_SHIFT (24U)
6706#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
6707#define SIM_SDID_FAMILYID_MASK (0xF0000000U)
6708#define SIM_SDID_FAMILYID_SHIFT (28U)
6709#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
6710
6711/*! @name SCGC1 - System Clock Gating Control Register 1 */
6712#define SIM_SCGC1_I2C2 (0x40U)
6713#define SIM_SCGC1_UART4 (0x400U)
6714#define SIM_SCGC1_UART5 (0x800U)
6715
6716/*! @name SCGC2 - System Clock Gating Control Register 2 */
6717#define SIM_SCGC2_ENET (0x1U)
6718#define SIM_SCGC2_DAC0 (0x1000U)
6719#define SIM_SCGC2_DAC1 (0x2000U)
6720
6721/*! @name SCGC3 - System Clock Gating Control Register 3 */
6722#define SIM_SCGC3_RNGA (0x1U)
6723#define SIM_SCGC3_SPI2 (0x1000U)
6724#define SIM_SCGC3_SDHC (0x20000U)
6725#define SIM_SCGC3_FTM2 (0x1000000U)
6726#define SIM_SCGC3_FTM3 (0x2000000U)
6727#define SIM_SCGC3_ADC1 (0x8000000U)
6728
6729/*! @name SCGC4 - System Clock Gating Control Register 4 */
6730#define SIM_SCGC4_EWM (0x2U)
6731#define SIM_SCGC4_CMT (0x4U)
6732#define SIM_SCGC4_I2C0 (0x40U)
6733#define SIM_SCGC4_I2C1 (0x80U)
6734#define SIM_SCGC4_UART0 (0x400U)
6735#define SIM_SCGC4_UART1 (0x800U)
6736#define SIM_SCGC4_UART2 (0x1000U)
6737#define SIM_SCGC4_UART3 (0x2000U)
6738#define SIM_SCGC4_USBOTG (0x40000U)
6739#define SIM_SCGC4_CMP (0x80000U)
6740#define SIM_SCGC4_VREF (0x100000U)
6741
6742/*! @name SCGC5 - System Clock Gating Control Register 5 */
6743#define SIM_SCGC5_LPTMR (0x1U)
6744#define SIM_SCGC5_PORTA (0x200U)
6745#define SIM_SCGC5_PORTB (0x400U)
6746#define SIM_SCGC5_PORTC (0x800U)
6747#define SIM_SCGC5_PORTD (0x1000U)
6748#define SIM_SCGC5_PORTE (0x2000U)
6749
6750/*! @name SCGC6 - System Clock Gating Control Register 6 */
6751#define SIM_SCGC6_FTF (0x1U)
6752#define SIM_SCGC6_DMAMUX (0x2U)
6753#define SIM_SCGC6_FLEXCAN0 (0x10U)
6754#define SIM_SCGC6_RNGA (0x200U)
6755#define SIM_SCGC6_SPI0 (0x1000U)
6756#define SIM_SCGC6_SPI1 (0x2000U)
6757#define SIM_SCGC6_I2S (0x8000U)
6758#define SIM_SCGC6_CRC (0x40000U)
6759#define SIM_SCGC6_USBDCD (0x200000U)
6760#define SIM_SCGC6_PDB (0x400000U)
6761#define SIM_SCGC6_PIT (0x800000U)
6762#define SIM_SCGC6_FTM0 (0x1000000U)
6763#define SIM_SCGC6_FTM1 (0x2000000U)
6764#define SIM_SCGC6_FTM2 (0x4000000U)
6765#define SIM_SCGC6_ADC0 (0x8000000U)
6766#define SIM_SCGC6_RTC (0x20000000U)
6767#define SIM_SCGC6_DAC0 (0x80000000U)
6768
6769/*! @name SCGC7 - System Clock Gating Control Register 7 */
6770#define SIM_SCGC7_FLEXBUS (0x1U)
6771#define SIM_SCGC7_DMA (0x2U)
6772#define SIM_SCGC7_MPU (0x4U)
6773
6774/*! @name CLKDIV1 - System Clock Divider Register 1 */
6775#define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
6776#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
6777#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
6778#define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U)
6779#define SIM_CLKDIV1_OUTDIV3_SHIFT (20U)
6780#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
6781#define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
6782#define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
6783#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
6784#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
6785#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
6786#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
6787
6788/*! @name CLKDIV2 - System Clock Divider Register 2 */
6789#define SIM_CLKDIV2_USBFRAC (0x1U)
6790#define SIM_CLKDIV2_USBDIV_MASK (0xEU)
6791#define SIM_CLKDIV2_USBDIV_SHIFT (1U)
6792#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
6793
6794/*! @name FCFG1 - Flash Configuration Register 1 */
6795#define SIM_FCFG1_FLASHDIS (0x1U)
6796#define SIM_FCFG1_FLASHDOZE (0x2U)
6797#define SIM_FCFG1_DEPART_MASK (0xF00U)
6798#define SIM_FCFG1_DEPART_SHIFT (8U)
6799#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
6800#define SIM_FCFG1_EESIZE_MASK (0xF0000U)
6801#define SIM_FCFG1_EESIZE_SHIFT (16U)
6802#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
6803#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
6804#define SIM_FCFG1_PFSIZE_SHIFT (24U)
6805#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
6806#define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U)
6807#define SIM_FCFG1_NVMSIZE_SHIFT (28U)
6808#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
6809
6810/*! @name FCFG2 - Flash Configuration Register 2 */
6811#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
6812#define SIM_FCFG2_MAXADDR1_SHIFT (16U)
6813#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
6814#define SIM_FCFG2_PFLSH (0x800000U)
6815#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
6816#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
6817#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
6818
6819
6820/*!
6821 * @}
6822 */ /* end of group SIM_Register_Masks */
6823
6824
6825/* SIM - Peripheral instance base addresses */
6826/** Peripheral SIM base address */
6827#define SIM_BASE (0x40047000u)
6828/** Peripheral SIM base pointer */
6829#define SIM ((SIM_TypeDef *)SIM_BASE)
6830/** Array initializer of SIM peripheral base addresses */
6831#define SIM_BASE_ADDRS { SIM_BASE }
6832/** Array initializer of SIM peripheral base pointers */
6833#define SIM_BASE_PTRS { SIM }
6834
6835/*!
6836 * @}
6837 */ /* end of group SIM_Peripheral_Access_Layer */
6838
6839
6840/* ----------------------------------------------------------------------------
6841 -- SMC Peripheral Access Layer
6842 ---------------------------------------------------------------------------- */
6843
6844/*!
6845 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
6846 * @{
6847 */
6848
6849/** SMC - Register Layout Typedef */
6850typedef struct {
6851 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
6852 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
6853 __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */
6854 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
6855} SMC_TypeDef;
6856
6857/* ----------------------------------------------------------------------------
6858 -- SMC Register Masks
6859 ---------------------------------------------------------------------------- */
6860
6861/*!
6862 * @addtogroup SMC_Register_Masks SMC Register Masks
6863 * @{
6864 */
6865
6866/*! @name PMPROT - Power Mode Protection register */
6867#define SMC_PMPROT_AVLLS (0x2U)
6868#define SMC_PMPROT_ALLS (0x8U)
6869#define SMC_PMPROT_AVLP (0x20U)
6870
6871/*! @name PMCTRL - Power Mode Control register */
6872#define SMC_PMCTRL_STOPM_MASK (0x7U)
6873#define SMC_PMCTRL_STOPM_SHIFT (0U)
6874#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
6875#define SMC_PMCTRL_STOPA (0x8U)
6876#define SMC_PMCTRL_RUNM_MASK (0x60U)
6877#define SMC_PMCTRL_RUNM_SHIFT (5U)
6878#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
6879#define SMC_PMCTRL_LPWUI (0x80U)
6880
6881/*! @name VLLSCTRL - VLLS Control register */
6882#define SMC_VLLSCTRL_VLLSM_MASK (0x7U)
6883#define SMC_VLLSCTRL_VLLSM_SHIFT (0U)
6884#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_VLLSM_SHIFT)) & SMC_VLLSCTRL_VLLSM_MASK)
6885#define SMC_VLLSCTRL_PORPO (0x20U)
6886
6887/*! @name PMSTAT - Power Mode Status register */
6888#define SMC_PMSTAT_PMSTAT_MASK (0x7FU)
6889#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
6890#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
6891
6892
6893/*!
6894 * @}
6895 */ /* end of group SMC_Register_Masks */
6896
6897
6898/* SMC - Peripheral instance base addresses */
6899/** Peripheral SMC base address */
6900#define SMC_BASE (0x4007E000u)
6901/** Peripheral SMC base pointer */
6902#define SMC ((SMC_TypeDef *)SMC_BASE)
6903/** Array initializer of SMC peripheral base addresses */
6904#define SMC_BASE_ADDRS { SMC_BASE }
6905/** Array initializer of SMC peripheral base pointers */
6906#define SMC_BASE_PTRS { SMC }
6907
6908/*!
6909 * @}
6910 */ /* end of group SMC_Peripheral_Access_Layer */
6911
6912
6913/* ----------------------------------------------------------------------------
6914 -- SPI Peripheral Access Layer
6915 ---------------------------------------------------------------------------- */
6916
6917/*!
6918 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
6919 * @{
6920 */
6921
6922/** SPI - Register Layout Typedef */
6923typedef struct {
6924 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
6925 uint8_t RESERVED_0[4];
6926 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
6927 union { /* offset: 0xC */
6928 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
6929 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
6930 };
6931 uint8_t RESERVED_1[24];
6932 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
6933 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
6934 union { /* offset: 0x34 */
6935 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
6936 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
6937 };
6938 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
6939 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
6940 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
6941 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
6942 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
6943 uint8_t RESERVED_2[48];
6944 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
6945 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
6946 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
6947 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
6948} SPI_TypeDef;
6949
6950/* ----------------------------------------------------------------------------
6951 -- SPI Register Masks
6952 ---------------------------------------------------------------------------- */
6953
6954/*!
6955 * @addtogroup SPI_Register_Masks SPI Register Masks
6956 * @{
6957 */
6958
6959/*! @name MCR - Module Configuration Register */
6960#define SPI_MCR_HALT (0x1U)
6961#define SPI_MCR_SMPL_PT_MASK (0x300U)
6962#define SPI_MCR_SMPL_PT_SHIFT (8U)
6963#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
6964#define SPI_MCR_CLR_RXF (0x400U)
6965#define SPI_MCR_CLR_TXF (0x800U)
6966#define SPI_MCR_DIS_RXF (0x1000U)
6967#define SPI_MCR_DIS_TXF (0x2000U)
6968#define SPI_MCR_MDIS (0x4000U)
6969#define SPI_MCR_DOZE (0x8000U)
6970#define SPI_MCR_PCSIS_MASK (0x3F0000U)
6971#define SPI_MCR_PCSIS_SHIFT (16U)
6972#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
6973#define SPI_MCR_ROOE (0x1000000U)
6974#define SPI_MCR_PCSSE (0x2000000U)
6975#define SPI_MCR_MTFE (0x4000000U)
6976#define SPI_MCR_FRZ (0x8000000U)
6977#define SPI_MCR_DCONF_MASK (0x30000000U)
6978#define SPI_MCR_DCONF_SHIFT (28U)
6979#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
6980#define SPI_MCR_CONT_SCKE (0x40000000U)
6981#define SPI_MCR_MSTR (0x80000000U)
6982
6983/*! @name TCR - Transfer Count Register */
6984#define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
6985#define SPI_TCR_SPI_TCNT_SHIFT (16U)
6986#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
6987
6988/*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
6989#define SPI_CTAR_BR_MASK (0xFU)
6990#define SPI_CTAR_BR_SHIFT (0U)
6991#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
6992#define SPI_CTAR_DT_MASK (0xF0U)
6993#define SPI_CTAR_DT_SHIFT (4U)
6994#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
6995#define SPI_CTAR_ASC_MASK (0xF00U)
6996#define SPI_CTAR_ASC_SHIFT (8U)
6997#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
6998#define SPI_CTAR_CSSCK_MASK (0xF000U)
6999#define SPI_CTAR_CSSCK_SHIFT (12U)
7000#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
7001#define SPI_CTAR_PBR_MASK (0x30000U)
7002#define SPI_CTAR_PBR_SHIFT (16U)
7003#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
7004#define SPI_CTAR_PDT_MASK (0xC0000U)
7005#define SPI_CTAR_PDT_SHIFT (18U)
7006#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
7007#define SPI_CTAR_PASC_MASK (0x300000U)
7008#define SPI_CTAR_PASC_SHIFT (20U)
7009#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
7010#define SPI_CTAR_PCSSCK_MASK (0xC00000U)
7011#define SPI_CTAR_PCSSCK_SHIFT (22U)
7012#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
7013#define SPI_CTAR_LSBFE (0x1000000U)
7014#define SPI_CTAR_CPHA (0x2000000U)
7015#define SPI_CTAR_CPOL (0x4000000U)
7016#define SPI_CTAR_FMSZ_MASK (0x78000000U)
7017#define SPI_CTAR_FMSZ_SHIFT (27U)
7018#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
7019#define SPI_CTAR_DBR (0x80000000U)
7020
7021/* The count of SPI_CTAR */
7022#define SPI_CTAR_COUNT (2U)
7023
7024/*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
7025#define SPI_CTAR_SLAVE_CPHA (0x2000000U)
7026#define SPI_CTAR_SLAVE_CPOL (0x4000000U)
7027#define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U)
7028#define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
7029#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
7030
7031/* The count of SPI_CTAR_SLAVE */
7032#define SPI_CTAR_SLAVE_COUNT (1U)
7033
7034/*! @name SR - Status Register */
7035#define SPI_SR_POPNXTPTR_MASK (0xFU)
7036#define SPI_SR_POPNXTPTR_SHIFT (0U)
7037#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
7038#define SPI_SR_RXCTR_MASK (0xF0U)
7039#define SPI_SR_RXCTR_SHIFT (4U)
7040#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
7041#define SPI_SR_TXNXTPTR_MASK (0xF00U)
7042#define SPI_SR_TXNXTPTR_SHIFT (8U)
7043#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
7044#define SPI_SR_TXCTR_MASK (0xF000U)
7045#define SPI_SR_TXCTR_SHIFT (12U)
7046#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
7047#define SPI_SR_RFDF (0x20000U)
7048#define SPI_SR_RFOF (0x80000U)
7049#define SPI_SR_TFFF (0x2000000U)
7050#define SPI_SR_TFUF (0x8000000U)
7051#define SPI_SR_EOQF (0x10000000U)
7052#define SPI_SR_TXRXS (0x40000000U)
7053#define SPI_SR_TCF (0x80000000U)
7054
7055/*! @name RSER - DMA/Interrupt Request Select and Enable Register */
7056#define SPI_RSER_RFDF_DIRS (0x10000U)
7057#define SPI_RSER_RFDF_RE (0x20000U)
7058#define SPI_RSER_RFOF_RE (0x80000U)
7059#define SPI_RSER_TFFF_DIRS (0x1000000U)
7060#define SPI_RSER_TFFF_RE (0x2000000U)
7061#define SPI_RSER_TFUF_RE (0x8000000U)
7062#define SPI_RSER_EOQF_RE (0x10000000U)
7063#define SPI_RSER_TCF_RE (0x80000000U)
7064
7065/*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
7066#define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
7067#define SPI_PUSHR_TXDATA_SHIFT (0U)
7068#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
7069#define SPI_PUSHR_PCS_MASK (0x3F0000U)
7070#define SPI_PUSHR_PCS_SHIFT (16U)
7071#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
7072#define SPI_PUSHR_CTCNT (0x4000000U)
7073#define SPI_PUSHR_EOQ (0x8000000U)
7074#define SPI_PUSHR_CTAS_MASK (0x70000000U)
7075#define SPI_PUSHR_CTAS_SHIFT (28U)
7076#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
7077#define SPI_PUSHR_CONT (0x80000000U)
7078
7079/*! @name TXFR0 - Transmit FIFO Registers */
7080#define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
7081#define SPI_TXFR0_TXDATA_SHIFT (0U)
7082#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
7083#define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
7084#define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
7085#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
7086
7087/*! @name TXFR1 - Transmit FIFO Registers */
7088#define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
7089#define SPI_TXFR1_TXDATA_SHIFT (0U)
7090#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
7091#define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
7092#define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
7093#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
7094
7095/*! @name TXFR2 - Transmit FIFO Registers */
7096#define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
7097#define SPI_TXFR2_TXDATA_SHIFT (0U)
7098#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
7099#define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
7100#define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
7101#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
7102
7103/*! @name TXFR3 - Transmit FIFO Registers */
7104#define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
7105#define SPI_TXFR3_TXDATA_SHIFT (0U)
7106#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
7107#define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
7108#define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
7109#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
7110
7111/*!
7112 * @}
7113 */ /* end of group SPI_Register_Masks */
7114
7115
7116/* SPI - Peripheral instance base addresses */
7117/** Peripheral SPI0 base address */
7118#define SPI0_BASE (0x4002C000u)
7119/** Peripheral SPI0 base pointer */
7120#define SPI0 ((SPI_TypeDef *)SPI0_BASE)
7121/** Peripheral SPI1 base address */
7122#define SPI1_BASE (0x4002D000u)
7123/** Peripheral SPI1 base pointer */
7124#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
7125/** Peripheral SPI2 base address */
7126#define SPI2_BASE (0x400AC000u)
7127/** Peripheral SPI2 base pointer */
7128#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
7129/** Array initializer of SPI peripheral base addresses */
7130#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
7131/** Array initializer of SPI peripheral base pointers */
7132#define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
7133/** Interrupt vectors for the SPI peripheral type */
7134#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
7135
7136/*!
7137 * @}
7138 */ /* end of group SPI_Peripheral_Access_Layer */
7139
7140
7141/* ----------------------------------------------------------------------------
7142 -- UART Peripheral Access Layer
7143 ---------------------------------------------------------------------------- */
7144
7145/*!
7146 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
7147 * @{
7148 */
7149
7150/** UART - Register Layout Typedef */
7151typedef struct {
7152 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
7153 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
7154 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
7155 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
7156 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
7157 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
7158 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
7159 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
7160 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
7161 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
7162 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
7163 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
7164 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
7165 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
7166 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
7167 uint8_t RESERVED_0[1];
7168 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
7169 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
7170 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
7171 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
7172 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
7173 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
7174 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
7175 uint8_t RESERVED_1[1];
7176 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
7177 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
7178 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
7179 union { /* offset: 0x1B */
7180 __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
7181 __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
7182 };
7183 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
7184 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
7185 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
7186 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
7187} UART_TypeDef;
7188
7189/* ----------------------------------------------------------------------------
7190 -- UART Register Masks
7191 ---------------------------------------------------------------------------- */
7192
7193/*!
7194 * @addtogroup UART_Register_Masks UART Register Masks
7195 * @{
7196 */
7197
7198/*! @name BDH - UART Baud Rate Registers: High */
7199#define UARTx_BDH_SBR_MASK (0x1FU)
7200#define UARTx_BDH_SBR_SHIFT (0U)
7201#define UARTx_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UARTx_BDH_SBR_SHIFT)) & UARTx_BDH_SBR_MASK)
7202#define UARTx_BDH_SBNS (0x20U)
7203#define UARTx_BDH_RXEDGIE (0x40U)
7204#define UARTx_BDH_LBKDIE (0x80U)
7205
7206/*! @name BDL - UART Baud Rate Registers: Low */
7207#define UARTx_BDL_SBR_MASK (0xFFU)
7208#define UARTx_BDL_SBR_SHIFT (0U)
7209#define UARTx_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UARTx_BDL_SBR_SHIFT)) & UARTx_BDL_SBR_MASK)
7210
7211/*! @name C1 - UART Control Register 1 */
7212#define UARTx_C1_PT (0x1U)
7213#define UARTx_C1_PE (0x2U)
7214#define UARTx_C1_ILT (0x4U)
7215#define UARTx_C1_WAKE (0x8U)
7216#define UARTx_C1_M (0x10U)
7217#define UARTx_C1_RSRC (0x20U)
7218#define UARTx_C1_UARTSWAI (0x40U)
7219#define UARTx_C1_LOOPS (0x80U)
7220
7221/*! @name C2 - UART Control Register 2 */
7222#define UARTx_C2_SBK (0x1U)
7223#define UARTx_C2_RWU (0x2U)
7224#define UARTx_C2_RE (0x4U)
7225#define UARTx_C2_TE (0x8U)
7226#define UARTx_C2_ILIE (0x10U)
7227#define UARTx_C2_RIE (0x20U)
7228#define UARTx_C2_TCIE (0x40U)
7229#define UARTx_C2_TIE (0x80U)
7230
7231/*! @name S1 - UART Status Register 1 */
7232#define UARTx_S1_PF (0x1U)
7233#define UARTx_S1_FE (0x2U)
7234#define UARTx_S1_NF (0x4U)
7235#define UARTx_S1_OR (0x8U)
7236#define UARTx_S1_IDLE (0x10U)
7237#define UARTx_S1_RDRF (0x20U)
7238#define UARTx_S1_TC (0x40U)
7239#define UARTx_S1_TDRE (0x80U)
7240
7241/*! @name S2 - UART Status Register 2 */
7242#define UARTx_S2_RAF (0x1U)
7243#define UARTx_S2_LBKDE (0x2U)
7244#define UARTx_S2_BRK13 (0x4U)
7245#define UARTx_S2_RWUID (0x8U)
7246#define UARTx_S2_RXINV (0x10U)
7247#define UARTx_S2_MSBF (0x20U)
7248#define UARTx_S2_RXEDGIF (0x40U)
7249#define UARTx_S2_LBKDIF (0x80U)
7250
7251/*! @name C3 - UART Control Register 3 */
7252#define UARTx_C3_PEIE (0x1U)
7253#define UARTx_C3_FEIE (0x2U)
7254#define UARTx_C3_NEIE (0x4U)
7255#define UARTx_C3_ORIE (0x8U)
7256#define UARTx_C3_TXINV (0x10U)
7257#define UARTx_C3_TXDIR (0x20U)
7258#define UARTx_C3_T8 (0x40U)
7259#define UARTx_C3_R8 (0x80U)
7260
7261/*! @name C4 - UART Control Register 4 */
7262#define UARTx_C4_BRFA_MASK (0x1FU)
7263#define UARTx_C4_BRFA_SHIFT (0U)
7264#define UARTx_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UARTx_C4_BRFA_SHIFT)) & UARTx_C4_BRFA_MASK)
7265#define UARTx_C4_M10 (0x20U)
7266#define UARTx_C4_MAEN2 (0x40U)
7267#define UARTx_C4_MAEN1 (0x80U)
7268
7269/*! @name C5 - UART Control Register 5 */
7270#define UARTx_C5_LBKDDMAS (0x8U)
7271#define UARTx_C5_ILDMAS (0x10U)
7272#define UARTx_C5_RDMAS (0x20U)
7273#define UARTx_C5_TCDMAS (0x40U)
7274#define UARTx_C5_TDMAS (0x80U)
7275
7276/*! @name ED - UART Extended Data Register */
7277#define UARTx_ED_PARITYE (0x40U)
7278#define UARTx_ED_NOISY (0x80U)
7279
7280/*! @name MODEM - UART Modem Register */
7281#define UARTx_MODEM_TXCTSE (0x1U)
7282#define UARTx_MODEM_TXRTSE (0x2U)
7283#define UARTx_MODEM_TXRTSPOL (0x4U)
7284#define UARTx_MODEM_RXRTSE (0x8U)
7285
7286/*! @name IR - UART Infrared Register */
7287#define UART_IR_TNP_MASK (0x3U)
7288#define UART_IR_TNP_SHIFT (0U)
7289#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
7290#define UART_IR_IREN (0x4U)
7291
7292/*! @name PFIFO - UART FIFO Parameters */
7293#define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
7294#define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
7295#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
7296#define UART_PFIFO_RXFE (0x8U)
7297#define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
7298#define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
7299#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
7300#define UART_PFIFO_TXFE (0x80U)
7301
7302/*! @name CFIFO - UART FIFO Control Register */
7303#define UART_CFIFO_RXUFE (0x1U)
7304#define UART_CFIFO_TXOFE (0x2U)
7305#define UART_CFIFO_RXOFE (0x4U)
7306#define UART_CFIFO_RXFLUSH (0x40U)
7307#define UART_CFIFO_TXFLUSH (0x80U)
7308
7309/*! @name SFIFO - UART FIFO Status Register */
7310#define UART_SFIFO_RXUF (0x1U)
7311#define UART_SFIFO_TXOF (0x2U)
7312#define UART_SFIFO_RXOF (0x4U)
7313#define UART_SFIFO_RXEMPT (0x40U)
7314#define UART_SFIFO_TXEMPT (0x80U)
7315
7316/*! @name TWFIFO - UART FIFO Transmit Watermark */
7317#define UART_TWFIFO_TXWATER_MASK (0xFFU)
7318#define UART_TWFIFO_TXWATER_SHIFT (0U)
7319#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
7320
7321/*! @name TCFIFO - UART FIFO Transmit Count */
7322#define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
7323#define UART_TCFIFO_TXCOUNT_SHIFT (0U)
7324#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
7325
7326/*! @name RWFIFO - UART FIFO Receive Watermark */
7327#define UART_RWFIFO_RXWATER_MASK (0xFFU)
7328#define UART_RWFIFO_RXWATER_SHIFT (0U)
7329#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
7330
7331/*! @name RCFIFO - UART FIFO Receive Count */
7332#define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
7333#define UART_RCFIFO_RXCOUNT_SHIFT (0U)
7334#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
7335
7336/*! @name C7816 - UART 7816 Control Register */
7337#define UART_C7816_ISO_7816E (0x1U)
7338#define UART_C7816_TTYPE (0x2U)
7339#define UART_C7816_INIT (0x4U)
7340#define UART_C7816_ANACK (0x8U)
7341#define UART_C7816_ONACK (0x10U)
7342
7343/*! @name IE7816 - UART 7816 Interrupt Enable Register */
7344#define UART_IE7816_RXTE (0x1U)
7345#define UART_IE7816_TXTE (0x2U)
7346#define UART_IE7816_GTVE (0x4U)
7347#define UART_IE7816_INITDE (0x10U)
7348#define UART_IE7816_BWTE (0x20U)
7349#define UART_IE7816_CWTE (0x40U)
7350#define UART_IE7816_WTE (0x80U)
7351
7352/*! @name IS7816 - UART 7816 Interrupt Status Register */
7353#define UART_IS7816_RXT (0x1U)
7354#define UART_IS7816_TXT (0x2U)
7355#define UART_IS7816_GTV (0x4U)
7356#define UART_IS7816_INITD (0x10U)
7357#define UART_IS7816_BWT (0x20U)
7358#define UART_IS7816_CWT (0x40U)
7359#define UART_IS7816_WT (0x80U)
7360
7361/*! @name WP7816T0 - UART 7816 Wait Parameter Register */
7362#define UART_WP7816T0_WI_MASK (0xFFU)
7363#define UART_WP7816T0_WI_SHIFT (0U)
7364#define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T0_WI_SHIFT)) & UART_WP7816T0_WI_MASK)
7365
7366/*! @name WP7816T1 - UART 7816 Wait Parameter Register */
7367#define UART_WP7816T1_BWI_MASK (0xFU)
7368#define UART_WP7816T1_BWI_SHIFT (0U)
7369#define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_BWI_SHIFT)) & UART_WP7816T1_BWI_MASK)
7370#define UART_WP7816T1_CWI_MASK (0xF0U)
7371#define UART_WP7816T1_CWI_SHIFT (4U)
7372#define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_CWI_SHIFT)) & UART_WP7816T1_CWI_MASK)
7373
7374/*! @name WN7816 - UART 7816 Wait N Register */
7375#define UART_WN7816_GTN_MASK (0xFFU)
7376#define UART_WN7816_GTN_SHIFT (0U)
7377#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
7378
7379/*! @name WF7816 - UART 7816 Wait FD Register */
7380#define UART_WF7816_GTFD_MASK (0xFFU)
7381#define UART_WF7816_GTFD_SHIFT (0U)
7382#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
7383
7384/*! @name ET7816 - UART 7816 Error Threshold Register */
7385#define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
7386#define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
7387#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
7388#define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
7389#define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
7390#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
7391
7392/*! @name TL7816 - UART 7816 Transmit Length Register */
7393#define UART_TL7816_TLEN_MASK (0xFFU)
7394#define UART_TL7816_TLEN_SHIFT (0U)
7395#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
7396
7397
7398/*!
7399 * @}
7400 */ /* end of group UART_Register_Masks */
7401
7402
7403/* UART - Peripheral instance base addresses */
7404/** Peripheral UART0 base address */
7405#define UART0_BASE (0x4006A000u)
7406/** Peripheral UART0 base pointer */
7407#define UART0 ((UART_TypeDef *)UART0_BASE)
7408/** Peripheral UART1 base address */
7409#define UART1_BASE (0x4006B000u)
7410/** Peripheral UART1 base pointer */
7411#define UART1 ((UART_TypeDef *)UART1_BASE)
7412/** Peripheral UART2 base address */
7413#define UART2_BASE (0x4006C000u)
7414/** Peripheral UART2 base pointer */
7415#define UART2 ((UART_TypeDef *)UART2_BASE)
7416/** Peripheral UART3 base address */
7417#define UART3_BASE (0x4006D000u)
7418/** Peripheral UART3 base pointer */
7419#define UART3 ((UART_TypeDef *)UART3_BASE)
7420/** Peripheral UART4 base address */
7421#define UART4_BASE (0x400EA000u)
7422/** Peripheral UART4 base pointer */
7423#define UART4 ((UART_TypeDef *)UART4_BASE)
7424/** Peripheral UART5 base address */
7425#define UART5_BASE (0x400EB000u)
7426/** Peripheral UART5 base pointer */
7427#define UART5 ((UART_TypeDef *)UART5_BASE)
7428/** Array initializer of UART peripheral base addresses */
7429#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
7430/** Array initializer of UART peripheral base pointers */
7431#define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4, UART5 }
7432/** Interrupt vectors for the UART peripheral type */
7433#define UARTStatus_IRQS { UART0Status_IRQn, UART1Status_IRQn, UART2Status_IRQn, UART3Status_IRQn, UART4Status_IRQn, UART5Status_IRQn }
7434#define UARTError_IRQS { UART0Error_IRQn, UART1Error_IRQn, UART2Error_IRQn, UART3Error_IRQn, UART4Error_IRQn, UART5Error_IRQn }
7435#define UART_LON_IRQS { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
7436
7437/*!
7438 * @}
7439 */ /* end of group UART_Peripheral_Access_Layer */
7440
7441
7442/* ----------------------------------------------------------------------------
7443 -- USB Peripheral Access Layer
7444 ---------------------------------------------------------------------------- */
7445
7446/*!
7447 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
7448 * @{
7449 */
7450
7451/** USB - Register Layout Typedef */
7452typedef struct {
7453 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
7454 uint8_t RESERVED_0[3];
7455 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
7456 uint8_t RESERVED_1[3];
7457 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
7458 uint8_t RESERVED_2[3];
7459 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
7460 uint8_t RESERVED_3[3];
7461 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
7462 uint8_t RESERVED_4[3];
7463 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
7464 uint8_t RESERVED_5[3];
7465 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
7466 uint8_t RESERVED_6[3];
7467 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
7468 uint8_t RESERVED_7[99];
7469 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
7470 uint8_t RESERVED_8[3];
7471 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
7472 uint8_t RESERVED_9[3];
7473 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
7474 uint8_t RESERVED_10[3];
7475 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
7476 uint8_t RESERVED_11[3];
7477 __I uint8_t STAT; /**< Status register, offset: 0x90 */
7478 uint8_t RESERVED_12[3];
7479 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
7480 uint8_t RESERVED_13[3];
7481 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
7482 uint8_t RESERVED_14[3];
7483 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
7484 uint8_t RESERVED_15[3];
7485 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
7486 uint8_t RESERVED_16[3];
7487 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
7488 uint8_t RESERVED_17[3];
7489 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
7490 uint8_t RESERVED_18[3];
7491 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
7492 uint8_t RESERVED_19[3];
7493 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
7494 uint8_t RESERVED_20[3];
7495 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
7496 uint8_t RESERVED_21[11];
7497 struct { /* offset: 0xC0, array step: 0x4 */
7498 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
7499 uint8_t RESERVED_0[3];
7500 } ENDPOINT[16];
7501 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
7502 uint8_t RESERVED_22[3];
7503 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
7504 uint8_t RESERVED_23[3];
7505 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
7506 uint8_t RESERVED_24[3];
7507 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
7508 uint8_t RESERVED_25[7];
7509 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
7510 uint8_t RESERVED_26[43];
7511 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
7512 uint8_t RESERVED_27[3];
7513 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
7514 uint8_t RESERVED_28[23];
7515 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
7516} USB_TypeDef;
7517
7518/* ----------------------------------------------------------------------------
7519 -- USB Register Masks
7520 ---------------------------------------------------------------------------- */
7521
7522/*!
7523 * @addtogroup USB_Register_Masks USB Register Masks
7524 * @{
7525 */
7526
7527/*! @name PERID - Peripheral ID register */
7528#define USB_PERID_ID_MASK (0x3FU)
7529#define USB_PERID_ID_SHIFT (0U)
7530#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
7531
7532/*! @name IDCOMP - Peripheral ID Complement register */
7533#define USB_IDCOMP_NID_MASK (0x3FU)
7534#define USB_IDCOMP_NID_SHIFT (0U)
7535#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
7536
7537/*! @name REV - Peripheral Revision register */
7538#define USB_REV_REV_MASK (0xFFU)
7539#define USB_REV_REV_SHIFT (0U)
7540#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
7541
7542/*! @name ADDINFO - Peripheral Additional Info register */
7543#define USB_ADDINFO_IEHOST (0x1U)
7544#define USB_ADDINFO_IRQNUM_MASK (0xF8U)
7545#define USB_ADDINFO_IRQNUM_SHIFT (3U)
7546#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK)
7547
7548/*! @name OTGISTAT - OTG Interrupt Status register */
7549#define USB_OTGISTAT_AVBUSCHG (0x1U)
7550#define USB_OTGISTAT_B_SESS_CHG (0x4U)
7551#define USB_OTGISTAT_SESSVLDCHG (0x8U)
7552#define USB_OTGISTAT_LINE_STATE_CHG (0x20U)
7553#define USB_OTGISTAT_ONEMSEC (0x40U)
7554#define USB_OTGISTAT_IDCHG (0x80U)
7555
7556/*! @name OTGICR - OTG Interrupt Control register */
7557#define USB_OTGICR_AVBUSEN (0x1U)
7558#define USB_OTGICR_BSESSEN (0x4U)
7559#define USB_OTGICR_SESSVLDEN (0x8U)
7560#define USB_OTGICR_LINESTATEEN (0x20U)
7561#define USB_OTGICR_ONEMSECEN (0x40U)
7562#define USB_OTGICR_IDEN (0x80U)
7563
7564/*! @name OTGSTAT - OTG Status register */
7565#define USB_OTGSTAT_AVBUSVLD (0x1U)
7566#define USB_OTGSTAT_BSESSEND (0x4U)
7567#define USB_OTGSTAT_SESS_VLD (0x8U)
7568#define USB_OTGSTAT_LINESTATESTABLE (0x20U)
7569#define USB_OTGSTAT_ONEMSECEN (0x40U)
7570#define USB_OTGSTAT_ID (0x80U)
7571
7572/*! @name OTGCTL - OTG Control register */
7573#define USB_OTGCTL_OTGEN (0x4U)
7574#define USB_OTGCTL_DMLOW (0x10U)
7575#define USB_OTGCTL_DPLOW (0x20U)
7576#define USB_OTGCTL_DPHIGH (0x80U)
7577
7578/*! @name ISTAT - Interrupt Status register */
7579#define USB_ISTAT_USBRST (0x1U)
7580#define USB_ISTAT_ERROR (0x2U)
7581#define USB_ISTAT_SOFTOK (0x4U)
7582#define USB_ISTAT_TOKDNE (0x8U)
7583#define USB_ISTAT_SLEEP (0x10U)
7584#define USB_ISTAT_RESUME (0x20U)
7585#define USB_ISTAT_ATTACH (0x40U)
7586#define USB_ISTAT_STALL (0x80U)
7587
7588/*! @name INTEN - Interrupt Enable register */
7589#define USB_INTEN_USBRSTEN (0x1U)
7590#define USB_INTEN_ERROREN (0x2U)
7591#define USB_INTEN_SOFTOKEN (0x4U)
7592#define USB_INTEN_TOKDNEEN (0x8U)
7593#define USB_INTEN_SLEEPEN (0x10U)
7594#define USB_INTEN_RESUMEEN (0x20U)
7595#define USB_INTEN_ATTACHEN (0x40U)
7596#define USB_INTEN_STALLEN (0x80U)
7597
7598/*! @name ERRSTAT - Error Interrupt Status register */
7599#define USB_ERRSTAT_PIDERR (0x1U)
7600#define USB_ERRSTAT_CRC5EOF (0x2U)
7601#define USB_ERRSTAT_CRC16 (0x4U)
7602#define USB_ERRSTAT_DFN8 (0x8U)
7603#define USB_ERRSTAT_BTOERR (0x10U)
7604#define USB_ERRSTAT_DMAERR (0x20U)
7605#define USB_ERRSTAT_BTSERR (0x80U)
7606
7607/*! @name ERREN - Error Interrupt Enable register */
7608#define USB_ERREN_PIDERREN (0x1U)
7609#define USB_ERREN_CRC5EOFEN (0x2U)
7610#define USB_ERREN_CRC16EN (0x4U)
7611#define USB_ERREN_DFN8EN (0x8U)
7612#define USB_ERREN_BTOERREN (0x10U)
7613#define USB_ERREN_DMAERREN (0x20U)
7614#define USB_ERREN_BTSERREN (0x80U)
7615
7616/*! @name STAT - Status register */
7617#define USB_STAT_ODD (0x4U)
7618#define USB_STAT_TX (0x8U)
7619#define USB_STAT_ENDP_MASK (0xF0U)
7620#define USB_STAT_ENDP_SHIFT (4U)
7621#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
7622
7623/*! @name CTL - Control register */
7624#define USB_CTL_USBENSOFEN (0x1U)
7625#define USB_CTL_ODDRST (0x2U)
7626#define USB_CTL_RESUME (0x4U)
7627#define USB_CTL_HOSTMODEEN (0x8U)
7628#define USB_CTL_RESET (0x10U)
7629#define USB_CTL_TXSUSPENDTOKENBUSY (0x20U)
7630#define USB_CTL_SE0 (0x40U)
7631#define USB_CTL_JSTATE (0x80U)
7632
7633/*! @name ADDR - Address register */
7634#define USB_ADDR_ADDR_MASK (0x7FU)
7635#define USB_ADDR_ADDR_SHIFT (0U)
7636#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
7637#define USB_ADDR_LSEN (0x80U)
7638
7639/*! @name BDTPAGE1 - BDT Page register 1 */
7640#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
7641#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
7642#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
7643
7644/*! @name FRMNUML - Frame Number register Low */
7645#define USB_FRMNUML_FRM_MASK (0xFFU)
7646#define USB_FRMNUML_FRM_SHIFT (0U)
7647#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
7648
7649/*! @name FRMNUMH - Frame Number register High */
7650#define USB_FRMNUMH_FRM_MASK (0x7U)
7651#define USB_FRMNUMH_FRM_SHIFT (0U)
7652#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
7653
7654/*! @name TOKEN - Token register */
7655#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
7656#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
7657#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
7658#define USB_TOKEN_TOKENPID_MASK (0xF0U)
7659#define USB_TOKEN_TOKENPID_SHIFT (4U)
7660#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
7661
7662/*! @name SOFTHLD - SOF Threshold register */
7663#define USB_SOFTHLD_CNT_MASK (0xFFU)
7664#define USB_SOFTHLD_CNT_SHIFT (0U)
7665#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
7666
7667/*! @name BDTPAGE2 - BDT Page Register 2 */
7668#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
7669#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
7670#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
7671
7672/*! @name BDTPAGE3 - BDT Page Register 3 */
7673#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
7674#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
7675#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
7676
7677/*! @name ENDPT - Endpoint Control register */
7678#define USB_ENDPT_EPHSHK (0x1U)
7679#define USB_ENDPT_EPSTALL (0x2U)
7680#define USB_ENDPT_EPTXEN (0x4U)
7681#define USB_ENDPT_EPRXEN (0x8U)
7682#define USB_ENDPT_EPCTLDIS (0x10U)
7683#define USB_ENDPT_RETRYDIS (0x40U)
7684#define USB_ENDPT_HOSTWOHUB (0x80U)
7685
7686/* The count of USB_ENDPT */
7687#define USB_ENDPT_COUNT (16U)
7688
7689/*! @name USBCTRL - USB Control register */
7690#define USB_USBCTRL_PDE (0x40U)
7691#define USB_USBCTRL_SUSP (0x80U)
7692
7693/*! @name OBSERVE - USB OTG Observe register */
7694#define USB_OBSERVE_DMPD (0x10U)
7695#define USB_OBSERVE_DPPD (0x40U)
7696#define USB_OBSERVE_DPPU (0x80U)
7697
7698/*! @name CONTROL - USB OTG Control register */
7699#define USB_CONTROL_DPPULLUPNONOTG (0x10U)
7700
7701/*! @name USBTRC0 - USB Transceiver Control register 0 */
7702#define USB_USBTRC0_USB_RESUME_INT (0x1U)
7703#define USB_USBTRC0_SYNC_DET (0x2U)
7704#define USB_USBTRC0_USB_CLK_RECOVERY_INT (0x4U)
7705#define USB_USBTRC0_USBRESMEN (0x20U)
7706#define USB_USBTRC0_USBRESET (0x80U)
7707
7708/*! @name USBFRMADJUST - Frame Adjust Register */
7709#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
7710#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
7711#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
7712
7713/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
7714#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (0x20U)
7715#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (0x40U)
7716#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (0x80U)
7717
7718/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
7719#define USB_CLK_RECOVER_IRC_EN_REG_EN (0x1U)
7720#define USB_CLK_RECOVER_IRC_EN_IRC_EN (0x2U)
7721
7722/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
7723#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (0x10U)
7724
7725
7726/*!
7727 * @}
7728 */ /* end of group USB_Register_Masks */
7729
7730
7731/* USB - Peripheral instance base addresses */
7732/** Peripheral USB0 base address */
7733#define USB0_BASE (0x40072000u)
7734/** Peripheral USB0 base pointer */
7735#define USB0 ((USB_TypeDef *)USB0_BASE)
7736/** Array initializer of USB peripheral base addresses */
7737#define USB_BASE_ADDRS { USB0_BASE }
7738/** Array initializer of USB peripheral base pointers */
7739#define USB_BASE_PTRS { USB0 }
7740/** Interrupt vectors for the USB peripheral type */
7741#define USB_IRQS { USB0_IRQn }
7742
7743/*!
7744 * @}
7745 */ /* end of group USB_Peripheral_Access_Layer */
7746
7747
7748/* ----------------------------------------------------------------------------
7749 -- USBDCD Peripheral Access Layer
7750 ---------------------------------------------------------------------------- */
7751
7752/*!
7753 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
7754 * @{
7755 */
7756
7757/** USBDCD - Register Layout Typedef */
7758typedef struct {
7759 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
7760 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
7761 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
7762 uint8_t RESERVED_0[4];
7763 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
7764 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
7765 union { /* offset: 0x18 */
7766 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
7767 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
7768 };
7769} USBDCD_TypeDef;
7770
7771/* ----------------------------------------------------------------------------
7772 -- USBDCD Register Masks
7773 ---------------------------------------------------------------------------- */
7774
7775/*!
7776 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
7777 * @{
7778 */
7779
7780/*! @name CONTROL - Control register */
7781#define USBDCD_CONTROL_IACK (0x1U)
7782#define USBDCD_CONTROL_IF (0x100U)
7783#define USBDCD_CONTROL_IE (0x10000U)
7784#define USBDCD_CONTROL_BC12 (0x20000U)
7785#define USBDCD_CONTROL_START (0x1000000U)
7786#define USBDCD_CONTROL_SR (0x2000000U)
7787
7788/*! @name CLOCK - Clock register */
7789#define USBDCD_CLOCK_CLOCK_UNIT (0x1U)
7790#define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
7791#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
7792#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
7793
7794/*! @name STATUS - Status register */
7795#define USBDCD_STATUS_SEQ_RES_MASK (0x30000U)
7796#define USBDCD_STATUS_SEQ_RES_SHIFT (16U)
7797#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
7798#define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
7799#define USBDCD_STATUS_SEQ_STAT_SHIFT (18U)
7800#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
7801#define USBDCD_STATUS_ERR (0x100000U)
7802#define USBDCD_STATUS_TO (0x200000U)
7803#define USBDCD_STATUS_ACTIVE (0x400000U)
7804
7805/*! @name TIMER0 - TIMER0 register */
7806#define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU)
7807#define USBDCD_TIMER0_TUNITCON_SHIFT (0U)
7808#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
7809#define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
7810#define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
7811#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
7812
7813/*! @name TIMER1 - TIMER1 register */
7814#define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
7815#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
7816#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
7817#define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
7818#define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
7819#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
7820
7821/*! @name TIMER2_BC11 - TIMER2_BC11 register */
7822#define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
7823#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
7824#define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
7825#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
7826#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
7827#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
7828
7829/*! @name TIMER2_BC12 - TIMER2_BC12 register */
7830#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
7831#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
7832#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
7833#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
7834#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
7835#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
7836
7837
7838/*!
7839 * @}
7840 */ /* end of group USBDCD_Register_Masks */
7841
7842
7843/* USBDCD - Peripheral instance base addresses */
7844/** Peripheral USBDCD base address */
7845#define USBDCD_BASE (0x40035000u)
7846/** Peripheral USBDCD base pointer */
7847#define USBDCD ((USBDCD_TypeDef *)USBDCD_BASE)
7848/** Array initializer of USBDCD peripheral base addresses */
7849#define USBDCD_BASE_ADDRS { USBDCD_BASE }
7850/** Array initializer of USBDCD peripheral base pointers */
7851#define USBDCD_BASE_PTRS { USBDCD }
7852/** Interrupt vectors for the USBDCD peripheral type */
7853#define USBDCD_IRQS { USBDCD_IRQn }
7854
7855/*!
7856 * @}
7857 */ /* end of group USBDCD_Peripheral_Access_Layer */
7858
7859
7860/* ----------------------------------------------------------------------------
7861 -- VREF Peripheral Access Layer
7862 ---------------------------------------------------------------------------- */
7863
7864/*!
7865 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
7866 * @{
7867 */
7868
7869/** VREF - Register Layout Typedef */
7870typedef struct {
7871 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
7872 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
7873} VREF_TypeDef;
7874
7875/* ----------------------------------------------------------------------------
7876 -- VREF Register Masks
7877 ---------------------------------------------------------------------------- */
7878
7879/*!
7880 * @addtogroup VREF_Register_Masks VREF Register Masks
7881 * @{
7882 */
7883
7884/*! @name TRM - VREF Trim Register */
7885#define VREF_TRM_TRIM_MASK (0x3FU)
7886#define VREF_TRM_TRIM_SHIFT (0U)
7887#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
7888#define VREF_TRM_CHOPEN (0x40U)
7889
7890/*! @name SC - VREF Status and Control Register */
7891#define VREF_SC_MODE_LV_MASK (0x3U)
7892#define VREF_SC_MODE_LV_SHIFT (0U)
7893#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
7894#define VREF_SC_VREFST (0x4U)
7895#define VREF_SC_ICOMPEN (0x20U)
7896#define VREF_SC_REGEN (0x40U)
7897#define VREF_SC_VREFEN (0x80U)
7898
7899
7900/*!
7901 * @}
7902 */ /* end of group VREF_Register_Masks */
7903
7904
7905/* VREF - Peripheral instance base addresses */
7906/** Peripheral VREF base address */
7907#define VREF_BASE (0x40074000u)
7908/** Peripheral VREF base pointer */
7909#define VREF ((VREF_TypeDef *)VREF_BASE)
7910/** Array initializer of VREF peripheral base addresses */
7911#define VREF_BASE_ADDRS { VREF_BASE }
7912/** Array initializer of VREF peripheral base pointers */
7913#define VREF_BASE_PTRS { VREF }
7914
7915/*!
7916 * @}
7917 */ /* end of group VREF_Peripheral_Access_Layer */
7918
7919
7920/* ----------------------------------------------------------------------------
7921 -- WDOG Peripheral Access Layer
7922 ---------------------------------------------------------------------------- */
7923
7924/*!
7925 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
7926 * @{
7927 */
7928
7929/** WDOG - Register Layout Typedef */
7930typedef struct {
7931 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
7932 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
7933 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
7934 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
7935 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
7936 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
7937 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
7938 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
7939 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
7940 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
7941 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
7942 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
7943} WDOG_TypeDef;
7944
7945/* ----------------------------------------------------------------------------
7946 -- WDOG Register Masks
7947 ---------------------------------------------------------------------------- */
7948
7949/*!
7950 * @addtogroup WDOG_Register_Masks WDOG Register Masks
7951 * @{
7952 */
7953
7954/*! @name STCTRLH - Watchdog Status and Control Register High */
7955#define WDOG_STCTRLH_WDOGEN (0x1U)
7956#define WDOG_STCTRLH_CLKSRC (0x2U)
7957#define WDOG_STCTRLH_IRQRSTEN (0x4U)
7958#define WDOG_STCTRLH_WINEN (0x8U)
7959#define WDOG_STCTRLH_ALLOWUPDATE (0x10U)
7960#define WDOG_STCTRLH_DBGEN (0x20U)
7961#define WDOG_STCTRLH_STOPEN (0x40U)
7962#define WDOG_STCTRLH_WAITEN (0x80U)
7963#define WDOG_STCTRLH_TESTWDOG (0x400U)
7964#define WDOG_STCTRLH_TESTSEL (0x800U)
7965#define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
7966#define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
7967#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
7968#define WDOG_STCTRLH_DISTESTWDOG (0x4000U)
7969
7970/*! @name STCTRLL - Watchdog Status and Control Register Low */
7971#define WDOG_STCTRLL_INTFLG (0x8000U)
7972
7973/*! @name PRESC - Watchdog Prescaler register */
7974#define WDOG_PRESC_PRESCVAL_MASK (0x700U)
7975#define WDOG_PRESC_PRESCVAL_SHIFT (8U)
7976#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
7977
7978
7979/*!
7980 * @}
7981 */ /* end of group WDOG_Register_Masks */
7982
7983
7984/* WDOG - Peripheral instance base addresses */
7985/** Peripheral WDOG base address */
7986#define WDOG_BASE (0x40052000u)
7987/** Peripheral WDOG base pointer */
7988#define WDOG ((WDOG_TypeDef *)WDOG_BASE)
7989/** Array initializer of WDOG peripheral base addresses */
7990#define WDOG_BASE_ADDRS { WDOG_BASE }
7991/** Array initializer of WDOG peripheral base pointers */
7992#define WDOG_BASE_PTRS { WDOG }
7993/** Interrupt vectors for the WDOG peripheral type */
7994#define WDOG_IRQS { WDOG_EWM_IRQn }
7995
7996/*!
7997 * @}
7998 */ /* end of group WDOG_Peripheral_Access_Layer */
7999
8000
8001/*
8002** End of section using anonymous unions
8003*/
8004
8005#if defined(__ARMCC_VERSION)
8006 #pragma pop
8007#elif defined(__CWCC__)
8008 #pragma pop
8009#elif defined(__GNUC__)
8010 /* leave anonymous unions enabled */
8011#elif defined(__IAR_SYSTEMS_ICC__)
8012 #pragma language=default
8013#else
8014 #error Not supported compiler type
8015#endif
8016
8017/*!
8018 * @}
8019 */ /* end of group Peripheral_access_layer */
8020
8021
8022/* ----------------------------------------------------------------------------
8023 -- SDK Compatibility
8024 ---------------------------------------------------------------------------- */
8025
8026/*!
8027 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
8028 * @{
8029 */
8030
8031#define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
8032#define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
8033#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
8034#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
8035#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
8036#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
8037#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
8038#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
8039#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
8040#define MCM_ISR_REG(base) MCM_ISCR_REG(base)
8041#define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
8042#define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
8043#define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
8044#define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
8045#define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
8046#define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
8047#define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
8048#define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
8049#define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
8050#define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
8051#define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
8052#define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
8053#define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
8054#define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
8055#define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
8056#define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
8057#define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
8058#define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
8059#define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
8060#define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
8061#define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
8062#define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
8063#define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
8064#define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
8065#define DSPI0 SPI0
8066#define DSPI1 SPI1
8067#define DSPI2 SPI2
8068#define FLEXCAN0 CAN0
8069#define PTA_BASE GPIOA_BASE
8070#define PTA GPIOA
8071#define PTB_BASE GPIOB_BASE
8072#define PTB GPIOB
8073#define PTC_BASE GPIOC_BASE
8074#define PTC GPIOC
8075#define PTD_BASE GPIOD_BASE
8076#define PTD GPIOD
8077#define PTE_BASE GPIOE_BASE
8078#define PTE GPIOE
8079#define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
8080#define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
8081#define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
8082#define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
8083#define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x)
8084#define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
8085#define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
8086#define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x)
8087#define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
8088#define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
8089#define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x)
8090#define Watchdog_IRQn WDOG_EWM_IRQn
8091#define Watchdog_IRQHandler WDOG_EWM_IRQHandler
8092#define LPTimer_IRQn LPTMR0_IRQn
8093#define LPTimer_IRQHandler LPTMR0_IRQHandler
8094#define LLW_IRQn LLWU_IRQn
8095#define LLW_IRQHandler LLWU_IRQHandler
8096#define DMAMUX0 DMAMUX
8097#define WDOG0 WDOG
8098#define MCM0 MCM
8099#define RTC0 RTC
8100
8101/*!
8102 * @}
8103 */ /* end of group SDK_Compatibility_Symbols */
8104
8105
8106#endif /* _MK64F12_H_ */
8107
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 18:02:43 +0100